diff --git "a/shard_new_new_cleaned_v_text_4.csv" "b/shard_new_new_cleaned_v_text_4.csv"
new file mode 100644--- /dev/null
+++ "b/shard_new_new_cleaned_v_text_4.csv"
@@ -0,0 +1,296167 @@
+text
+"// @Harness: v2-parse
+// @Result: ParseError @ 4:7
+
+component try {
+}
+"
+"// @Harness: v2-exec
+// @Test: compound assignment operators
+// @Result: 0=11, 1=5, 2=22, 3=3, 4=15, 5=8, 11=11
+
+component cmpassn27 {
+
+    method main(arg: int): 8 {
+\tlocal foo: 8 = 0xb;
+\tif ( arg == 1 ) foo >>= 1;
+\tif ( arg == 2 ) foo <<= 1;
+\tif ( arg == 3 ) foo &= 0x3;
+\tif ( arg == 4 ) foo |= 0x5;
+\tif ( arg == 5 ) foo ^= 0x3;
+\treturn foo;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array05 {
+    field a_02: bool[][] =  { {true, false}, {true} };
+}
+
+/* 
+heap {
+    record #0:1:array05 {
+        field a_02: bool[][] = #1:bool[][2];
+    }
+    record #1:2:bool[][2] {
+        field 0:bool[] = #2:bool[2];
+        field 1:bool[] = #3:bool[1];
+    }
+    record #2:2:bool[2] {
+        field 0:bool = bool:true;
+        field 1:bool = bool:false;
+    }
+    record #3:1:bool[1] {
+        field 0:bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=0, 5=0, 6=0, 7=0, 8=0, 9=1, 10=0
+
+class delegate16_a {
+    method val(): int { return 1; }
+}
+
+class delegate16_b extends delegate16_a {
+    method val(): int { return 2; }
+}
+
+component delegate16 {
+    field oa1: delegate16_a = new delegate16_a();
+    field ob1: delegate16_a = new delegate16_b();
+    field oa2: delegate16_a = new delegate16_a();
+    field ob2: delegate16_a = new delegate16_b();
+
+    method main(arg: int): bool {
+
+\tlocal af = oa1.val;
+\tlocal bf = ob1.val;
+\tlocal cf = bar;
+
+\tif ( arg == 1 ) return compare(af, f1());
+\tif ( arg == 2 ) return compare(bf, f2());
+\tif ( arg == 3 ) return compare(cf, f3());
+\tif ( arg == 4 ) return compare(af, f4());
+\tif ( arg == 5 ) return compare(bf, f5());
+\tif ( arg == 6 ) return compare(cf, f6());
+\tif ( arg == 7 ) return compare(af, f7());
+\tif ( arg == 8 ) return compare(bf, f8());
+\tif ( arg == 9 ) return compare(cf, f9());
+
+\treturn false;
+    }
+
+    method f1(): function(): int { return oa1.val; }
+    method f2(): function(): int { return ob1.val; }
+    method f3(): function(): int { return bar; }
+    method f4(): function(): int { return ob1.val; }
+    method f5(): function(): int { return oa1.val; }
+    method f6(): function(): int { return null; }
+    method f7(): function(): int { return oa2.val; }
+    method f8(): function(): int { return ob2.val; }
+    method f9(): function(): int { return bar; }
+
+    method compare(f: function(): int, g: function(): int): bool {
+\treturn f == g;
+    }
+
+    method bar(): int {
+\treturn 3;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: PASS
+
+class while_short_init04 {
+    
+    method testm(p: bool) {
+        local foo: bool;
+        while ( p and (foo = p) ) testm(foo);
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class new5 {
+  field foo: type = new (foo)[0];
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5 : 5
+
+component comp6 {
+    ;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: InvalidLiteral @ 6:20
+
+class int_lit07 {
+    field a: int = -3000000000;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking of array initializers
+// @Result: TypeMismatch @ 6:31
+
+class type58 {
+    
+    method testm() {
+        local a: int[] = { 0, 1, 2, 3, 4, false };
+    }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of assigning to array elements""
+// @Result: PASS
+
+class array03 {
+    
+    method testm(a: int[]) {
+        a[0] = 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 5:15
+
+class type_res03 {
+    
+    method testm(a: foo);
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Visitor<E> {
+    method visitA(n: A, e: E);
+    method visitB(n: B, e: E);
+}
+
+class S {
+    method accept<E>(v: Visitor<E>, e: E);
+}
+
+class A extends S {
+    method accept<E>(v: Visitor<E>, e: E);
+}
+
+class B extends S {
+    method accept<E>(v: Visitor<E>, e: E);
+}
+"
+"// @Harness: v2-exec
+// @Test: order of evaluation
+// @Result: 0=0, 1=1, 2=2, 3=3, 4=0
+
+component order08 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    method first(): function(int): int {
+        order[pos] = 1;
+        pos++;
+        return add;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method add(a: int): int { return a + 2; }
+
+    method main(arg: int): int {
+        local result = first()(second(1));
+\tif ( arg == 1 ) return order[0];
+\tif ( arg == 2 ) return order[1];
+\tif ( arg == 3 ) return result;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > xor operator
+// @Result: PASS
+
+class raw_xor03 {
+    field a: 16;
+    field b: 16;
+    field c: 16 = a ^ b;
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: PASS
+
+class for_short_init02 {
+    
+    method testm(p: bool) {
+        local foo: bool;
+        for ( ; p and (foo = p); ) {
+            testm(foo);
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 6:15
+
+class lvalue11 {
+    
+    method testm() {
+        for ( ; ; testm() = 0 ) ;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class for3 {
+  method m() {
+     for ( ; ; ) for ( ; ; ) ;
+  }
+  method n() {
+     for( a = 0; func(a); a = func(a) ) {
+       for( b = 0; func(b); b = func(b) ) {
+       }
+     }
+
+     for( a = 0; func(a); a = func(a)) {
+       for( b = 0; func(b); b = func(b) ) {
+         for( c = 0; func(c); c = func(c) ) {
+         }
+       }
+     }
+  }
+}
+"
+"/*
+ * This program implements a simple (unbalanced) binary tree,
+ * representing each node as an object. The initializer builds
+ * a tree for a set of randomly generated integers; tree search
+ * is used as a benchmark for execution performance at runtime.
+ *
+ * @author Akop Palyan
+ * @author Ben L. Titzer
+ */
+program PolyTree {
+\tentrypoint main = PolyTree.start;
+}
+
+class Value {
+\tfield value: int;
+
+\tconstructor(v: int) {
+\t\tvalue = v;
+\t}
+}
+
+class Node<T> {
+\tfield left: Node<T>;
+\tfield right: Node<T>;
+\tfield key: int;
+\tfield value: T;
+
+\tconstructor(k: int) {
+\t\tkey = k;
+\t\tleft = null;
+\t\tright = null;
+\t }
+}
+
+class Tree<T> {
+\tfield root: Node<T> = null;
+\tfield def: T;
+
+\tconstructor(d: T) {
+\t\tdef = d;
+\t}
+
+\tmethod insert(k: int, v: T) {
+\t\tlocal n = (root == null) ? root = new Node<T>(k) : insertAt(root, k);
+\t\tn.value = v;
+\t}
+
+\tmethod insertAt(n: Node<T>, k: int): Node<T> {
+\t\tif (k <= n.key) {
+\t\t\tif (n.left == null) {
+\t\t\t\tn.left = new Node<T>(k);
+\t\t\t\treturn n.left;
+\t\t\t} else {
+\t\t\t\treturn insertAt(n.left, k);
+\t\t\t}
+\t\t} else {
+\t\t\tif (n.right == null) {
+\t\t\t\tn.right = new Node<T>(k);
+\t\t\t\treturn n.right;
+\t\t\t} else {
+\t\t\t\treturn insertAt(n.right, k);
+\t\t\t}
+\t\t}
+\t}
+
+\tmethod search(k: int): T {
+\t\treturn searchAt(root, k);
+\t}
+
+\tmethod searchAt(n: Node<T>, k: int): T {
+\t\tif (n == null) {
+\t\t\treturn def;
+\t\t} else if (k < n.key) {
+\t\t\treturn searchAt(n.left, k);
+\t\t} else if (k > n.key) {
+\t\t\treturn searchAt(n.right, k);
+\t\t} else {
+\t\t\treturn n.value;
+\t\t}
+\t}
+}
+
+component PolyTree {
+\tfield seed: int = 1;
+\tfield tree_val: Tree<Value> = new Tree<Value>(null);
+\tfield tree_int: Tree<int> = new Tree<int>(0);
+\tfield v: Value = null;
+
+\tconstructor() {
+\t\tlocal i: int;
+
+\t\tfor (i = 0; i < 50; i++) {
+\t\t\tlocal k = rand() % 200;
+\t\t\t//tree_val.insert(k, new Value(k));
+\t\t\ttree_int.insert(k, k);
+\t\t}
+\t}
+
+\tmethod start() {
+\t\tlocal i: int, j: int;
+\t\tlocal cumul1 = 0;
+\t\tlocal cumul2 = 0;
+\t\tfor (i = 0; i < 100; i++) {
+\t\t\tfor (j = 0; j < 200; j++) {
+\t\t\t\tcumul2 += tree_int.search(j);
+\t\t\t}
+\t\t}
+\t}
+
+\tmethod rand(): int {
+\t\tseed = 1664525 * seed + 1013904223;
+\t\treturn seed;
+\t}
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=17, 3=42
+
+component field01a {
+    field a: int = 13;
+    field b: int = 17;
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a;
+\tif ( arg == 2 ) return b;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: UnresolvedType @ 4:38
+
+class scope10_a<Y> extends scope10_b<X> {
+}
+
+class scope10_b<X> {
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: PASS
+
+class inh08_a {
+    
+    method testm() {
+    }
+}
+class inh08_b extends inh08_a {
+    
+    method testm() {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+}
+
+class PairFactory {
+  method makePair<X, Y>(x: X, y: Y): Pair<X, Y>;
+}
+
+class NewPairFactory {
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int operations
+// @Result: PASS
+
+class raw_op01 {
+    method check(a: 8, b: 8, c: int): 8 {
+\tlocal x: 8;
+
+\t// basic operators
+\tx = a;
+\tx = a & b;
+\tx = a | b;
+\tx = a ^ b;
+\tx = a << c;
+\tx = a >> c;
+\tx = ~a;
+
+\t// indexing operators
+\tlocal y: 1;
+\ty = a[c];
+\ta[c] = b[c];\t
+
+\t// concat operator
+\tlocal z: 16;
+\tz = a # b;
+
+\treturn x;
+    }
+}
+"
+"program rma01 {
+    entrypoint main = Main.entry;
+}
+
+component Main {
+    field f: A = new A();
+    field g: B = new B();
+
+    method entry() {
+\twhile ( true ) f = f.m();
+    }
+}
+
+class A {
+    method m(): A { return this; }
+}
+
+class B extends A {
+    method m(): A { return Main.g; }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 21
+
+class virtual01b_1 {
+    method val(): int { return 11; }
+}
+
+class virtual01b_2 extends virtual01b_1 {
+    method val(): int { return 21; }
+}
+
+class virtual01b_3 extends virtual01b_1 {
+    method val(): int { return 31; }
+}
+
+component virtual01b {
+    field a: virtual01b_1 = new virtual01b_1();
+    field b: virtual01b_1 = new virtual01b_2();
+    field c: virtual01b_1 = new virtual01b_3();
+
+    method main(arg: int): int {
+\treturn b.val();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: promotion integer to 32 bit raw type
+// @Result: PASS
+
+component raw_int01 {
+    field a: 32 = 0       ;
+    field b: 32 = 1       ;
+    field c: 32 = 7       ;
+    field d: 32 = 10      ;
+    field e: 32 = 15      ;
+    field f: 32 = 16      ;
+    field g: 32 = 58      ;
+    field h: 32 = 255     ;
+    field i: 32 = 32767   ;
+    field j: 32 = 65536   ;
+    field k: 32 = 1048576 ;
+    field l: 32 = -1      ;
+    field m: 32 = -65535  ;
+    field n: 32 = -11     ;
+}
+
+/* 
+heap {
+    record #0:14:raw_int01 {
+        field a: 32 = raw.32:0x0;
+        field b: 32 = raw.32:0x1;
+        field c: 32 = raw.32:0x7;
+        field d: 32 = raw.32:0xa;
+        field e: 32 = raw.32:0xf;
+        field f: 32 = raw.32:0x10;
+        field g: 32 = raw.32:0x3a;
+        field h: 32 = raw.32:0xff;
+        field i: 32 = raw.32:0x7fff;
+        field j: 32 = raw.32:0x10000;
+        field k: 32 = raw.32:0x100000;
+        field l: 32 = raw.32:0xffffffff;
+        field m: 32 = raw.32:0xffff0001;
+        field n: 32 = raw.32:0xfffffff5;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component switch02 {
+    field foo: int = ds(1);
+
+    method ds(v: int): int {
+\tswitch ( v ) {
+\t    case ( 0 ) return 10;
+\t    case ( 1 ) return 11;
+\t    case ( 2 ) return 12;
+\t    case ( 3 ) return 13;
+\t    case ( 4, 5 ) return 15;
+\t    case ( 7, 8, 9 ) return 20;
+\t    default return -1;
+        }
+    }
+}
+
+/* 
+heap {
+    record #0:1:switch02 {
+        field foo: int = int:11;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=NullCheckException, 3=NullCheckException, 4=42
+
+class rtex_null08_obj {
+    field baz: int;
+}
+
+component rtex_null08 {
+    field foo: rtex_null08_obj = null;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) foo.baz = 13;
+\tif ( arg == 2 ) foo.baz = 15;
+\tif ( arg == 3 ) foo.baz = 17;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=42, 1=17, 2=18, 3=19, 4=20, 5=42
+
+component comp15 {
+
+    field a: int = 13;
+    field b: int = 14;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) a = 17;
+\tif ( arg == 2 ) b = 18;
+\tif ( arg == 3 ) comp15_b.a = 19;
+\tif ( arg == 4 ) comp15_b.b = 20;
+
+\tif ( arg == 1 ) return a;
+\tif ( arg == 2 ) return b;
+\tif ( arg == 3 ) return comp15_b.a;
+\tif ( arg == 4 ) return comp15_b.b;
+\treturn 42;
+    }
+}
+
+component comp15_b {
+    field a: int = 15;
+    field b: int = 16;
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class cmpassn13_obj {
+    field foo: int = 1;
+    field bar: int = inc();
+    method inc(): int {
+\tlocal i = foo;
+        foo = i += 3;
+        return i;
+    }
+}
+
+component cmpassn13 {
+    field foo: cmpassn13_obj = new cmpassn13_obj();
+}
+
+/* 
+heap {
+    record #0:1:cmpassn13 {
+        field foo: cmpassn13_obj = #1:cmpassn13_obj;
+    }
+    record #1:2:cmpassn13_obj {
+        field foo: int = int:4;
+        field bar: int = int:4;
+    }
+}*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class cast05b {
+   method m() {
+      local y = x :: (Type<X, Y>);
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component switch09 {
+    field foo: int = ds(9);
+
+    method ds(v: int): int {
+\tswitch ( v ) {
+\t    case ( 0 ) return 10;
+\t    case ( 1 ) return 11;
+\t    case ( 2 ) return 12;
+\t    case ( 3 ) return 13;
+\t    case ( 4, 5 ) return 15;
+\t    case ( 7, 8, 9 ) return 20;
+\t    default return -1;
+        }
+    }
+}
+
+/* 
+heap {
+    record #0:1:switch09 {
+        field foo: int = int:20;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_method02b_a<X> extends inh_method02b_b<int> {
+  field g: int = this.f();
+}
+
+class inh_method02b_b<X> {
+  method f(): X;
+}
+"
+"// @Harness: v2-seman
+// @Test: function () -> int[]
+// @Result: PASS
+
+class type_func03 {
+    field a: function(): int[];
+    method testm(b: function(): int[]) { a = b; }
+}
+"
+"// @Harness: v2-seman
+// @Result: BuiltinRedefined @ 4:21
+
+component void {
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; invocation of method on non-object
+// @Result: PASS
+
+class nmspc03 {
+    
+    method testm() {
+        local foo: int = 1;
+        local int: bool = true;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: duplicated method names
+// @Result: MemberRedefined @ 6:8
+
+component method3 {
+    
+    method testm();
+    
+    field testm: char;
+}
+"
+"// @Harness: v2-exec
+// @Test: getbit operator
+// @Result: 0=0, 1=0, 2=1, 3=1, 4=1, 5=0, 6=0, 7=1, 8=0, 9=0, 10=0
+
+component raw_index01 {
+    field foo: 32 = 0x3ff0eeee;
+
+    method main(arg: int): 1 {
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[1];
+\tif ( arg == 3 ) return foo[5];
+\tif ( arg == 4 ) return foo[11];
+\tif ( arg == 5 ) return foo[16];
+\tif ( arg == 6 ) return foo[17];
+\tif ( arg == 7 ) return foo[20];
+\tif ( arg == 8 ) return foo[30];
+\tif ( arg == 9 ) return foo[31];
+\treturn 0b0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=37, 5=42
+
+class W<T> {
+    field val: T;
+    constructor(v: T) {
+        val = v;
+    }
+}
+
+component ptex_wrap06 {
+
+    field a: W<int> = new W<int>(11);
+    field b: W<int> = new W<int>(21);
+    field c: W<W<int> > = new W<W<int> >(new W<int>(31));
+    field d: W<W<int> > = new W<W<int> >(new W<int>(37));
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val;
+\tif ( arg == 2 ) return b.val;
+\tif ( arg == 3 ) return c.val.val;
+\tif ( arg == 4 ) return d.val.val;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization interpreter > raw types > and operator
+// @Result: 0=0, 1=0, 2=0, 3=0, 4=1, 5=1, 6=1, 7=1
+
+component raw_index02 {
+    field foo: 8 = 0xf0;
+
+    method main(arg: int): 1 {
+\treturn foo[arg];
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component prepost15 {
+    field foo: int[] = { 1 };
+    field bar: int = foo[0]++;
+}
+
+/* 
+heap {
+    record #0:2:prepost15 {
+        field foo: int[] = #1:int[1];
+        field bar: int = int:1;
+    }
+    record #1:1:int[1] {
+\tfield 0: int = int:2;
+    }
+}*/
+"
+"program P {
+   entrypoint main = Foo.main;
+}
+
+component Foo {
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component prepost03 {
+    field foo: int = 1;
+    field bar: int = ++foo;
+}
+
+/* 
+heap {
+    record #0:2:prepost03 {
+        field foo: int = int:2;
+        field bar: int = int:2;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Result: TypeParameterRedefined @ 4:18
+
+class scope06<X, X> {
+  method first(x: X): X {
+    return x;
+  }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class decl2 {
+  method m() {
+    local a: type;
+    local b = 0;
+    local c: int = 0;
+    local d = 0 + 0;
+    local e = func(0,0);
+    local f: int[] = {1,2,3};
+    local g: int[] = { func(0), func(1), func(2) };
+
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator with truncation
+// @Result: PASS
+
+component eval_and02 {
+    field f1: 4  = 0x10  & 0xf;
+    field f2: 8  = 0x1f0 & 0x0f;
+    field f3: 16 = 0x1f3f3  & 0x1111;
+    field f4: 7  = 0b11110101  & 0b1111111;
+    field f5: 5  = 0b110101  & 0b10000;
+    field f6: 3  = 0b1101  & 0b100;
+    field f7: 32 = 0x1FFFF0000  & 0xF000F000;
+    field f8: 48 = 0x1FF00FFFF0000  & 0xF000F000F000;
+    field f9: 64 = 0xFFFF0000FFFF0000  & 0xF000F000F000F000;
+}
+
+/*
+heap {
+    record #0:1:eval_and02 {
+\tfield f1: 4  = raw.4:0x0; 
+\tfield f2: 8  = raw.8:0x00; 
+\tfield f3: 16 = raw.16:0x1111; 
+\tfield f4: 7  = raw.7:0x75; 
+\tfield f5: 5  = raw.5:0x10; 
+\tfield f6: 3  = raw.3:0x4; 
+\tfield f7: 32 = raw.32:0xf0000000; 
+\tfield f8: 48 = raw.48:0xf000f0000000; 
+\tfield f9: 64 = raw.64:0xf0000000f0000000; 
+    }
+}
+*/
+"
+"// @Harness: v2-seman
+// @Test: TypeCast operation
+// @Result: PASS
+
+class cast05_a {
+    field foo: cast05_a;
+    field bar: cast05_a = foo :: cast05_a;
+}
+
+class cast05_b extends cast05_a {
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedBinOp @ 7:25
+
+class int_add03 {
+    
+    method testm() {
+        local a = false + 0;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class constr07 {
+    constructor(): super(0) { }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: InvalidLiteral @ 6:20
+
+class int_lit08 {
+    field a: int = -10000000000;
+}
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+component logical01 {
+    field res_01: bool = op(true, true);
+    field res_02: bool = op(false, false);
+    field res_03: bool = op(true, false);
+    field res_04: bool = op(false, true);
+
+    method op(a: bool, b: bool): bool {
+\treturn a and b;
+    }
+}
+
+/* 
+heap {
+    record #0:4:logical01 {
+        field res_01: bool = bool:true;
+        field res_02: bool = bool:false;
+        field res_03: bool = bool:false;
+        field res_04: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types, << operator
+// @Result: PASS
+
+class raw_shl01 {
+    field a: 1;
+    field b: int;
+    field c: 2 = a << b;
+}
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=0, 6=0, 7=1, 8=1, 9=1, 10=1
+
+component comp06 {
+
+    method op(a: int, b: int): bool {
+\treturn a != b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(1, 2);
+\tif ( arg == 2 ) return op(2, 1);
+\tif ( arg == 3 ) return op(-1, 1);
+\tif ( arg == 4 ) return op(-1, 0);
+\tif ( arg == 5 ) return op(-200, -200);
+\tif ( arg == 6 ) return op(65535, 65535);
+\tif ( arg == 7 ) return op(14, 13);
+\tif ( arg == 8 ) return op(13, 14);
+\tif ( arg == 9 ) return op(-1255, -255);
+\tif ( arg == 10 ) return op(1000000, 48576);
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedOperator @ 7:23
+
+class inc01 {
+    method testm(a: bool) {
+        local foo = --a;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=0
+
+component raw_shr06 {
+    field res_01: 5 = op(0b01111,  1);
+    field res_02: 5 = op(0b01101,  2);
+    field res_03: 5 = op(0b00001,  3);
+    field res_04: 5 = op(0b10001,  4);
+    field res_05: 5 = op(0b00111,  5);
+    field res_06: 5 = op(0b11111,  6);
+    field res_07: 5 = op(0b10111,  0);
+    field res_08: 5 = op(0b10000,  1);
+    field res_09: 5 = op(0b01010,  3);
+
+    method op(a: 5, b: int): 5 {
+\treturn a >> b;
+    }
+
+    method main(arg: int): bool {
+        if ( arg == 1 ) return op(0b01111,  1) == res_01;
+        if ( arg == 2 ) return op(0b01101,  2) == res_02;
+        if ( arg == 3 ) return op(0b00001,  3) == res_03;
+        if ( arg == 4 ) return op(0b10001,  4) == res_04;
+        if ( arg == 5 ) return op(0b00111,  5) == res_05;
+        if ( arg == 6 ) return op(0b11111,  6) == res_06;
+        if ( arg == 7 ) return op(0b10111,  0) == res_07;
+        if ( arg == 8 ) return op(0b10000,  1) == res_08;
+        if ( arg == 9 ) return op(0b01010,  3) == res_09;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 8:37
+
+class for_init05 {
+    
+    method testm(a: int) {
+        local foo: int;
+        local uninit: int;
+        for ( foo = 0; foo < 100; foo = uninit ) {
+            if ( foo == 12 ) continue;
+            uninit = 12;
+        }
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class pv04_a {
+    method getf(): function(): int { return this.val; }
+    private method val(): int { return 1; }
+}
+
+class pv04_b extends pv04_a {
+    private method val(): int { return 2; }
+}
+
+class pv04_c extends pv04_a {
+    private method val(): int { return 3; }
+}
+
+component pv04 {
+    field a: function():int = new pv04_a().getf();
+    field b: function():int = new pv04_b().getf();
+    field c: function():int = new pv04_c().getf();
+    field av: int = a();
+    field bv: int = b();
+    field cv: int = c();
+}
+
+/* 
+heap {
+    record #0:6:pv04 {
+        field a: function():int = [#1:pv04_a,pv04_a:val()];
+        field b: function():int = [#2:pv04_b,pv04_a:val()];
+        field c: function():int = [#3:pv04_c,pv04_a:val()];
+        field av: int = int:1;
+        field bv: int = int:1;
+        field cv: int = int:1;
+    }
+    record #1:0:pv04_a {
+    }
+    record #2:0:pv04_b {
+    }
+    record #3:0:pv04_c {
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @Result: PASS
+
+class E {
+}
+
+class Pool<T> {
+    field array: T[];
+    field none: T;
+    field head: int;
+    field used: int;
+
+    constructor(size: int, nf: function(): T, n: T) {
+\tarray = new T[size];
+\tlocal i: int;
+\tfor ( i = 0; i < size; i++ ) array[i] = nf();
+\thead = 0;
+\tused = 0;
+\tnone = n;
+    }
+
+    method acquire(): T {
+\tif ( used == array.length ) return none;
+\tlocal x = array[head];
+\thead = (head + 1) % array.length;
+\tused++;
+\treturn x;
+    }
+
+    method release(x: T) {
+\tif ( used == 0 ) return;
+\tlocal pos = (head - used) % array.length;
+\tarray[pos] = x;
+\tused--;
+    }
+}
+
+component pool_init02 {
+    field a: Pool<E> = new Pool<E>(3, newE, null);
+    field b: E = a.acquire();
+
+    method newE(): E {
+\treturn new E();
+    }
+}
+
+/* 
+heap {
+    record #0:2:pool_init02 {
+        field a: Pool<E> = #1:Pool<E>;
+\tfield b: E = #3:E;
+    }
+    record #1:3:Pool<E> {
+\tfield array: E[] = #2:E[3];
+\tfield none: E = #null;
+\tfield head: int = int:1
+\tfield used: int = int:1;
+    }
+    record #2:3:E[3] {
+\tfield 0: E = #3:E;
+\tfield 1: E = #4:E;
+\tfield 2: E = #5:E;
+    }
+    record #3:0:E {
+    }
+    record #4:0:E {
+    }
+    record #5:0:E {
+    }
+} 
+*/
+"
+"// @Harness: v2-init
+// @Test: return statement
+// @Result: PASS
+
+component return05 {
+    
+    field x: int;
+
+    constructor() {
+\tx = m();
+\tif ( true ) return;
+    }
+
+    method m(): int {
+\treturn 11;
+    }
+}
+
+/* 
+heap {
+    record #0:1:return05 {
+        field x: int = int:11;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > and operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_and02 {
+    field a: 6;
+    field b: 7;
+    field c: 6 = a & b;
+    field d: 5 = a & b;
+}
+"
+"// @Harness: v2-exec
+// @Test: order of evaluation
+// @Result: 0=0, 1=1, 2=2, 3=21, 4=0
+
+component order09 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    method op(a: int, b: int): bool {
+\treturn first(a) == second(b);
+    }
+
+    method first(a: int): int {
+        order[pos] = 1;
+        pos++;
+        return a;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method main(arg: int): int {
+        local result = op(1, 2);
+\tif ( arg == 1 ) return order[0];
+\tif ( arg == 2 ) return order[1];
+\tif ( arg == 3 ) return result ? 11 : 21;
+\treturn 0;
+    }
+
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_char_int02 {
+    
+    method testm() {
+        local a = { '0', 1 };
+\tlocal b: int[] = a;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; invocation of method on non-object
+// @Result: PASS
+
+class nmspc04 {
+    
+    method testm() {
+        local foo: int = 1;
+        local int: int = 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: array rtex_index exceptions
+// @Result: 0=42, 1=13, 2=13, 3=13, 4=BoundsCheckException, 5=BoundsCheckException, 6=BoundsCheckException, 7=42
+
+component rtex_index09 {
+    field foo: int[] = new int[36];
+
+    constructor() {
+\tlocal i = 0;
+\tfor ( i = 0; i < foo.length; i++ ) foo[i] = 13;
+    }
+
+    method getf(i: int): int {
+\treturn foo[i];
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return getf(0);
+\tif ( arg == 2 ) return getf(1);
+\tif ( arg == 3 ) return getf(35);
+\tif ( arg == 4 ) return getf(36);
+\tif ( arg == 5 ) return getf(65535);
+\tif ( arg == 6 ) return getf(65536);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: null exceptions
+// @Result: NullCheckException @ 7:25
+
+class null09_obj {
+    method baz();
+}
+
+component null09 {
+    field foo: null09_obj;
+    field bar: function() = foo.baz;
+    method baz();
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: TypeMismatch @ 6:16
+
+class type31 {
+    
+    method testm() {
+        local a: int = 2 % null;
+    }
+}
+"
+"/*
+ * This program simply tests the functionality of the Radio driver.
+ * @author Xiaoli Gong
+ */
+program TestRadio {
+\tentrypoint main = TestRadio.entry;
+\tentrypoint adc = ADC.convHandler;
+\tentrypoint spi_stc = SPI.interruptHandler;
+\tentrypoint timer0_comp = Timer0.compareHandler;
+\tentrypoint usart0_rx = USART0.rec_handler;
+\tentrypoint usart0_tx = USART0.tran_handler;
+}
+
+component TestRadio {
+
+\tfield flag: boolean;
+\tfield msg: TOS_Msg;
+\tfield msg_sent: char[] = ""One Packet Sent :\
+"";
+\tfield msg_addr: char[] = ""Packet Addr:\
+"";
+\tfield msg_data: char[] = ""Packet Data:\
+"";
+\tfield counter: int = 0;
+\tfield busy: boolean = false;
+
+\tconstructor() {
+\t\tmsg = new TOS_Msg();
+\t\tmsg.addr = 0xffff;
+\t\tmsg.type = 0x04;
+\t\tmsg.group = 0x7d;
+\t\tmsg.length = 0x04;
+\t\tmsg.data[0] = 0x5d;
+\t\tmsg.data[1] = 0x01;
+\t\tmsg.data[2] = 0x01;
+\t\tmsg.data[3] = 0x00;
+\t}
+
+\tmethod sendDone(data: TOS_Msg, result: boolean) {
+\t\tlocal i: int = 0;
+\t\tflag = true;
+\t\tcounter++;
+
+\t\tif (counter % 50 == 0) {
+\t\t\tUSART0.printString(msg_sent, msg_sent.length);
+\t\t\tUSART0.printString(msg_addr, msg_addr.length);
+\t\t\tUSART0.printHex16(msg.addr);
+\t\t\tUSART0.printString(msg_data, msg_data.length);
+\t\t\tfor (i = 0; i < msg.length::int; i++)
+\t\t\t\tUSART0.printHex8(msg.data[i]);
+\t\t}
+
+\t\tmsg.data[0] = (msg.data[0]::int + 1)::8;
+\t\tmsg.data[1] = (msg.data[1]::int + 1)::8;
+\t\tbusy = false;
+\t}
+
+\tmethod receivedata(data: TOS_Msg) {
+\t\tMica2.red.toggle();
+\t\tMica2.yellow.toggle();
+\t\tMica2.green.toggle();
+\t}
+
+\tmethod entry() {
+\t\tMica2.startLEDs();
+\t\tMica2.startTerminal();
+\t\t// Mica2.red.toggle();
+\t\tCC1000Radio.init();
+\t\tCC1000Radio.start();
+\t\tCC1000Radio.SetsendDoneCallback(sendDone);
+\t\tif (counter < 10){
+\t\t\tbusy = true;
+\t\t\tCC1000Radio.send(msg);
+\t\t\t// MCU.sleepForever();
+\t\t\t//while(busy);
+\t\t}
+\t\tCC1000Radio.stop();
+\t}
+
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of array elements""
+// @Result: TypeMismatch @ 6:12
+
+class array05 {
+    
+    method testm(a: int[]) {
+        a[0] = false;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class meth05 {
+    method m(a: int, b: int) { }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type02 {
+    field f: function(type[]);
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 4:15
+
+component comp5 extends comp5a {
+  field f: type;
+  method m();
+  method n(): type;
+  method o(a: type): type;
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:29
+
+class instof06 {
+   method m() {
+      if ( x <: Type<Type<X>, Y> ) ;
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: logical operators
+// @Result: 0=0, 1=1, 2=0, 3=1, 4=1, 5=0
+
+component logical02 {
+
+    method op(a: bool, b: bool): bool {
+\treturn a or b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(true, true);
+\tif ( arg == 2 ) return op(false, false);
+\tif ( arg == 3 ) return op(true, false);
+\tif ( arg == 4 ) return op(false, true);
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component for06 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        for ( ; ; ) {
+\t    cumul += i++;
+\t    if ( i > max ) return cumul;
+\t}
+    }
+}
+
+/* 
+heap {
+    record #0:6:for06 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_id13 {
+    method test() {
+\tlocal x = new int[id('0')];
+    }
+    method id<X>(x: X): X {
+\treturn x;\t
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class cmpassn21_obj {
+    field foo: int = 6;
+}
+
+component cmpassn21 {
+    field foo: cmpassn21_obj;
+    field bar: int = obj().foo += 4;
+    
+    // this method should only be called once
+    method obj(): cmpassn21_obj {
+\treturn foo = new cmpassn21_obj();
+    }
+}
+
+/* 
+heap {
+    record #0:2:cmpassn21 {
+        field foo: cmpassn21_obj = #1:cmpassn21_obj;
+        field bar: int = int:10;
+    }
+    record #1:1:cmpassn21_obj {
+\tfield foo: int = int:10;
+    }
+}*/
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=14, 3=15, 4=42
+
+class array27_obj {
+    field foo: int;
+    constructor(i: int) { foo = i; }
+}
+
+component array27 {
+    field i: array27_obj = new array27_obj(13);
+    field j: array27_obj = new array27_obj(14);
+    field k: array27_obj = new array27_obj(15);
+
+    field a: array27_obj[] =  { i, j, k };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a[0].foo;
+\tif ( arg == 2 ) return a[1].foo;
+\tif ( arg == 3 ) return a[2].foo;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_field01b_a<X> extends inh_field01b_b<X> {
+  field g: X = this.f;
+}
+
+class inh_field01b_b<X> {
+  field f: X;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > hexadecimal constants
+// @Result: PASS
+
+class raw_hex01 {
+    field a: 4  = 0x0;
+    field b: 4  = 0xf;
+    field c: 8  = 0xe0;
+    field d: 8  = 0xef;
+    field e: 12 = 0x0e1;
+    field f: 12 = 0xfa5;
+    field g: 16 = 0x0444;
+    field h: 16 = 0xf331;
+    field i: 20 = 0x0137a;
+    field j: 20 = 0xf25bc;
+    field k: 24 = 0x0ccdef;
+    field l: 24 = 0xfc0123;
+    field m: 28 = 0x0ff7700;
+    field n: 28 = 0xf000000;
+    field o: 32 = 0x0a010145;
+    field p: 32 = 0xffffffff;
+    field q: 36 = 0x0ff823711;
+    field r: 36 = 0xf083123bb;
+    field s: 48 = 0x0123456789ab;
+    field t: 48 = 0xfedcba987654;
+    field u: 52 = 0x0123456789abc;
+    field v: 52 = 0xf00882938aabb;
+    field w: 60 = 0x088739289884999;
+    field x: 60 = 0xfaaaaaaaaaaaaaa;
+    field y: 64 = 0x01111110000fffff;
+    field z: 64 = 0xffff00001111aaaa;
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=0, 2=1, 3=0
+
+class A<X> { } 
+
+component ptex_instof03 {
+
+   field a: A<int> = new A<int>();
+
+   method m<T>(x: A<T>): bool {
+      return x <: (A<int>);
+   }
+
+   method main(arg: int): bool {
+       local meth: function(A<int>): bool = m;
+       if ( arg == 1 ) return meth(null);
+       if ( arg == 2 ) return meth(a);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component fold01 {
+    field a: int;
+    field b: int;
+
+    constructor() {
+        local array = new int[1000];
+\ta = fold(add, array, array.length - 1);
+        b = fold2(mult, array, array.length - 1);
+    }
+
+    method add(a: int, b: int): int {
+\treturn a + b;
+    }
+
+    method mult(a: int, b: int): int {
+        return a * b;
+    }
+
+    // iterative version of fold
+    method fold(f: function(int, int): int, a: int[], m: int): int {
+\treturn m == 0 ? a[0] : f(fold(f, a, m-1), a[m]);        
+    }
+
+    method fold2<T>(f: function(T, T): T, a: T[], m: int): T {
+\treturn m == 0 ? a[0] : f(fold2(f, a, m-1), a[m]);        
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component cast3 {
+\tfield f: T = 0 + a :: T;
+\tfield g: T = 1 - a :: T;
+\tfield h: T = 2 * a :: T;
+\tfield i: T = 3 / a :: T;
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42
+
+class this04_a {
+    field th: this04_a = this;
+    method val(a: int): int { return th == this ? a : 55; }
+}
+
+class this04_b extends this04_a {
+    method val(a: int): int { return th == this ? a + 10: 55; }
+}
+
+class this04_c extends this04_a {
+    method val(a: int): int { return th == this ? a + 20: 55; }
+}
+
+component this04 {
+    field a: this04_a = new this04_a();
+    field b: this04_b = new this04_b();
+    field c: this04_c = new this04_c();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val(11);
+\tif ( arg == 2 ) return b.val(11);
+\tif ( arg == 3 ) return c.val(11);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component cmpassn18 {
+    field foo: int[];
+    field bar: int = na()[0] -= 18;
+    
+    // this method should only be called once
+    method na(): int[] {
+        local arr = { 1 };
+\treturn foo = arr;
+    }
+}
+
+/* 
+heap {
+    record #0:2:cmpassn18 {
+        field foo: int[] = #1:int[1];
+        field bar: int = int:-17;
+    }
+    record #1:1:int[1] {
+\tfield 0: int = int:-17;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: continue must be inside of loop
+// @Result: StatementMustBeInLoop @ 6:5
+
+class continue1 {
+    
+    method testm() {
+        continue;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: Virgil constructors
+// @Result: ArgumentCountMismatchInNew @ 13:34
+
+class constructor04 {
+
+    field f: int;
+
+    constructor() {
+        f = 1;
+    }
+
+    method testm(): constructor04 {
+        return new constructor04(0);
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=2, 2=3, 3=0, 4=12, 5=12, 6=0
+
+component order15 {
+    field order: int[] = { 0, 0, 0 };
+    field pos: int = 0;
+
+    field data: int[] = { 7 };
+
+    method first(): int[] {
+        order[pos] = 1;
+        pos++;
+        return data;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method third(a: int): int {
+        order[pos] = 3;
+        pos++;
+        return a;
+    }
+
+    method main(arg: int): int {
+        local result = data[second(0)] = third(12);
+\tif ( arg == 1 ) return order[0];
+\tif ( arg == 2 ) return order[1];
+\tif ( arg == 3 ) return order[2];
+\tif ( arg == 4 ) return result;
+\tif ( arg == 5 ) return data[0];
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: PASS
+
+component field_res15 {
+    private field testf: int;
+    
+    method testm() {
+        testf = 0;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class for5 {
+  method m() {
+     for ( a = 0, b = 0; ; ) ;
+  }
+  method n() {
+     for ( a = 0, b = 0; b < 2; ) ;
+     for ( a = 0, b = 0; b < 2; a = b, b = a ) ;
+     for ( a = 0, b = 0, c = 0; b < 2; a = b, b = a, c = a ) ;
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment options
+// @Result: PASS
+
+component cmpassn02 {
+    field foo: int = 1;
+    field bar: int = foo -= 2;
+}
+
+/* 
+heap {
+    record #0:2:cmpassn02 {
+        field foo: int = int:-1;
+        field bar: int = int:-1;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 6:5
+
+class lvalue1 {
+    
+    method testm() {
+        testm() = 1;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+class default03b_obj {
+    field foo: int[];
+    field bar: bool = foo == null;
+}
+
+component default03b {
+    field baz: default03b_obj = new default03b_obj();
+}
+
+/* 
+heap {
+    record #0:1:default03b {
+        field baz: default03b_obj = #1:default03b_obj;
+    }
+    record #1:2:default03b_obj {
+        field foo: int[] = #null;
+        field bar: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component while05 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( true ) {
+\t    cumul += i++;
+\t    if ( i > max ) return cumul;
+\t}
+\treturn cumul;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=0, 1=1, 2=0, 3=0, 4=1, 5=0
+
+component alloc_array02 {
+    field a: bool[] = array(true, false);
+    field b: bool[] = array(false, true);
+
+    method array(c: bool, d: bool): bool[] {
+       local arr = {c, d};
+       return arr;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return a[0];
+\tif ( arg == 2 ) return a[1];
+\tif ( arg == 3 ) return b[0];
+\tif ( arg == 4 ) return b[1];
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=13, 3=42
+
+class default03b_obj {
+    field foo: int[];
+    field bar: bool = foo == null;
+}
+
+component default03b {
+    field baz: default03b_obj = new default03b_obj();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return baz.foo == null ? 13 : 10;
+\tif ( arg == 2 ) return baz.bar ? 13 : 10;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class Node<X> {
+    field value: X;
+    field link: Node<X>;
+}
+
+class List<X> {
+    field head: Node<X>;
+
+    method add(x: X) {
+\tlocal nn = new Node<X>();
+\tnn.value = x;
+\tnn.link = head;
+\thead = nn;\t
+    }
+
+    method apply(f: function(X)) {
+\tlocal pos = head;
+\twhile ( head != null ) {
+\t    f(head.value);
+\t    head = head.link;
+\t}
+    }
+}
+
+component list_init03 {
+    field y: int;
+
+    constructor() {
+\tlocal v = { 0, 12, 13, -9, 5 };
+\ttoList(v).apply(add);
+    }
+
+    method toList<T>(a: T[]): List<T> {
+\tlocal list = new List<T>();
+\tlocal i: int;
+\tfor ( i = 0; i < a.length; i++) list.add(a[i]);
+\treturn list;
+    }
+
+    method add(v: int) { y += v; }
+}
+
+/*
+heap {
+    record #0:1:list_init03 {
+        field y: int = int:21;
+    }
+}
+*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr6 {
+  field foo: type = new foo();
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42
+
+class virtual08a_1 {
+    method val(): int { return 11; }
+}
+
+class virtual08a_2 extends virtual08a_1 {
+    method val(): int { return 21; }
+}
+
+class virtual08a_3 extends virtual08a_1 {
+    method val(): int { return 31; }
+}
+
+component virtual08a {
+    field a: virtual08a_1 = new virtual08a_1();
+    field b: virtual08a_1 = new virtual08a_2();
+    field c: virtual08a_1 = new virtual08a_3();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return invoke(a);
+\tif ( arg == 2 ) return invoke(b);
+\tif ( arg == 3 ) return invoke(c);
+\treturn 42;
+    }
+
+    method invoke(o: virtual08a_1): int {
+\treturn o.val();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; invocation of method on non-object
+// @Result: PASS
+
+class pts_nmspc01<X> {
+    
+    field f: X;
+
+    method testm() {
+        local foo: int = 1;
+        local int: int = new pts_nmspc01<int>().f;
+    }
+}
+"
+"program rma_func01 {
+    entrypoint main = Main.entry;
+}
+
+component Main {
+    field f: function() = m1;
+    field g: function() = m2;
+
+    method entry() {
+\twhile ( true ) { 
+\t    f();
+        }
+    }
+
+    method m1() { }
+    method m2() { }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component order11 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    field data: int[] = { 7 };
+    field res_01: int = first()[second(0)];
+
+    method first(): int[] {
+        order[pos] = 1;
+        pos++;
+        return data;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+}
+
+/* 
+heap {
+    record #0:10:order11 {
+        field order: int[] = #1:int[2];
+        field pos: int = int:2;
+        field data: int[] = #2:int[1];
+        field res_01: int = int:7;
+    }
+    record #1:2:int[2] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+    }
+    record #2:1:int[1] {
+\tfield 0:int = int:7;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component arith13 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(-8, 3);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(0, -1);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -5);
+    field res_07: int = op(13455, -17);
+    field res_08: int = op(64, 8);
+    field res_09: int = op(255, 19);
+    field res_10: int = op(-48576, 1000);
+
+    method op(a: int, b: int): int {
+\treturn (a / b) * b + (a % b);
+    }
+}
+
+/* 
+heap {
+    record #0:10:arith13 {
+        field res_01: int = int:1;
+        field res_02: int = int:-8;
+        field res_03: int = int:-1;
+        field res_04: int = int:0;
+        field res_05: int = int:-200;
+        field res_06: int = int:65535;
+        field res_07: int = int:13455;
+        field res_08: int = int:64;
+        field res_09: int = int:255;
+        field res_10: int = int:-48576;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @Result: PASS
+
+component static01_a {
+    method val(): int { return 1; }
+}
+
+component static01_b {
+    method val(): int { return 2; }
+}
+
+component static01_c {
+    method val(): int { return 3; }
+}
+
+component static01 {
+    field av: int = static01_a.val();
+    field bv: int = static01_b.val();
+    field cv: int = static01_c.val();
+}
+
+/* 
+heap {
+    record #0:0:static01_a {
+    }
+    record #1:0:static01_b {
+    }
+    record #2:0:static01_c {
+    }
+    record #3:3:static01 {
+        field av: int = int:1;
+        field bv: int = int:2;
+        field cv: int = int:3;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class pv01_a {
+    method getf(): function(): int { return val; }
+    private method val(): int { return 1; }
+}
+
+class pv01_b extends pv01_a {
+    private method val(): int { return 2; }
+}
+
+class pv01_c extends pv01_a {
+    private method val(): int { return 3; }
+}
+
+component pv01 {
+    field a: function():int = new pv01_a().getf();
+    field b: function():int = new pv01_b().getf();
+    field c: function():int = new pv01_c().getf();
+    field av: int = a();
+    field bv: int = b();
+    field cv: int = c();
+}
+
+/* 
+heap {
+    record #0:6:pv01 {
+        field a: function():int = [#1:pv01_a,pv01_a:val()];
+        field b: function():int = [#2:pv01_b,pv01_a:val()];
+        field c: function():int = [#3:pv01_c,pv01_a:val()];
+        field av: int = int:1;
+        field bv: int = int:1;
+        field cv: int = int:1;
+    }
+    record #1:0:pv01_a {
+    }
+    record #2:0:pv01_b {
+    }
+    record #3:0:pv01_c {
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class assign05<X> {
+   field f: X;
+   method m(x: X) {
+      f = x;
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array18 {
+    field matrix: int[][] =  new int[2][3];
+    constructor() {
+\tlocal i: int, j: int, cnt = 0;
+\tfor ( i = 0; i < 2; i++ ) {
+\t    for ( j = 0; j < 3; j++ ) 
+            \tmatrix[i][j] = cnt++;
+        }
+    }
+}
+
+/* 
+heap {
+    record #0:1:array18 {
+        field matrix: int[][] = #1:int[][2];
+    }
+    record #1:2:int[][2] {
+        field 0:int[] = #2:int[3];
+        field 1:int[] = #3:int[3];
+    }
+    record #2:3:int[3] {
+        field 0:int = int:0;
+        field 1:int = int:1;
+        field 2:int = int:2;
+    }
+    record #3:3:int[3] {
+        field 0:int = int:3;
+        field 1:int = int:4;
+        field 2:int = int:5;
+    }
+} */
+"
+"program rma03 {
+    entrypoint main = Main.entry;
+}
+
+component Main {
+    field a: A = new A();
+    field b: A = new B();
+    field f: function(): A = m1;
+    field g: function(): A = m2;
+
+    method entry() {
+\twhile ( true ) { 
+\t    a = f();
+        }
+    }
+
+    method m1(): A { return a; }
+    method m2(): A { return b; }
+}
+
+class A {
+    method m(): A { return this; }
+}
+
+class B extends A {
+    method m(): A { return Main.b; }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: TypeMismatch @ 6:16
+
+class type41 {
+    
+    method testm() {
+        local a: int = 2 >= null;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: ExpectedObjectType @ 4:21
+
+class inh22 extends bool {
+}
+"
+"// @Harness: v2-seman
+// @Test: cannot declare duplicate fields
+// @Result: ExpectedVarType @ 6:17
+
+class field6 {
+    field testf: void;
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 31
+
+class virtual07c_1 {
+    method val(): int { return 11; }
+}
+
+class virtual07c_2 extends virtual07c_1 {
+    method val(): int { return 21; }
+}
+
+class virtual07c_3 extends virtual07c_1 {
+    method val(): int { return 31; }
+}
+
+class virtual07c_4 {
+    method val(): int { return 51; }
+}
+
+class virtual07c_5 extends virtual07c_4 {
+    method val(): int { return 61; }
+}
+
+component virtual07c {
+    field a: virtual07c_1 = new virtual07c_1();
+    field b: virtual07c_1 = new virtual07c_2();
+    field c: virtual07c_1 = new virtual07c_3();
+    field d: virtual07c_4 = new virtual07c_4();
+    field e: virtual07c_4 = new virtual07c_5();
+
+    method main(arg: int): int {
+\treturn c.val();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component default01a {
+    field foo: int;
+    field bar: int = foo + 1;
+}
+
+/* 
+heap {
+    record #0:2:default01a {
+        field foo: int = int:0;
+        field bar: int = int:1;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:29
+
+class cast01 {
+   method m() {
+      local y = x :: Type<X>;
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=0
+
+component raw_shr04 {
+    field res_01: 29 = op(0x0f,     1);
+    field res_02: 29 = op(0x02,     2);
+    field res_03: 29 = op(0x01,    31);
+    field res_04: 29 = op(0x30,     8);
+    field res_05: 29 = op(0xf0,    16);
+    field res_06: 29 = op(0xfffff, 12);
+    field res_07: 29 = op(0x10000, 16);
+    field res_08: 29 = op(0xff,     5);
+    field res_09: 29 = op(0xaa,     0);
+
+    method op(a: 29, b: int): 29 {
+\treturn a >> b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(0x0f,     1) == res_01;
+\tif ( arg == 2 ) return op(0x02,     2) == res_02;
+\tif ( arg == 3 ) return op(0x01,    31) == res_03;
+\tif ( arg == 4 ) return op(0x30,     8) == res_04;
+\tif ( arg == 5 ) return op(0xf0,    16) == res_05;
+\tif ( arg == 6 ) return op(0xfffff, 12) == res_06;
+\tif ( arg == 7 ) return op(0x10000, 16) == res_07;
+\tif ( arg == 8 ) return op(0xff,     5) == res_08;
+\tif ( arg == 9 ) return op(0xaa,     0) == res_09;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=14, 3=42
+
+class field03b_obj {
+    field a: int = 13;
+    field b: int = 14;
+    method geta(): int { return a; }
+    method getb(): int { return b; }
+}
+
+component field03b {
+    field foo: field03b_obj = new field03b_obj();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo.geta();
+\tif ( arg == 2 ) return foo.getb();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=42
+
+class virtual03a_1 {
+    method val(a: int): int { return a+1; }
+}
+
+class virtual03a_2 extends virtual03a_1 {
+    method val(a: int): int { return a+2; }
+}
+
+class virtual03a_3 extends virtual03a_1 {
+    method val(a: int): int { return a+3; }
+}
+
+component virtual03a {
+    field a: virtual03a_1 = new virtual03a_1();
+    field b: virtual03a_1 = new virtual03a_2();
+    field c: virtual03a_1 = new virtual03a_3();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val(10);
+\tif ( arg == 2 ) return b.val(10);
+\tif ( arg == 3 ) return c.val(10);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=2, 2=13, 3=2, 4=13, 5=2, 6=13, 7=42
+
+component array21 {
+    field a: char[] =  {\'1\', \'2\'};
+    field b: char[] =  ""earth\\tmoon\
+11"";
+    field len1: int = length(a);
+    field len2: int = length(b);
+
+    method length(a: char[]): int {
+\treturn a.length;
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return len1;
+\tif ( arg == 2 ) return len2;
+\tif ( arg == 3 ) return a.length;
+\tif ( arg == 4 ) return b.length;
+\tif ( arg == 5 ) return length(a);
+\tif ( arg == 6 ) return length(b);
+\treturn 42;
+    }
+
+}
+"
+"// @Harness: v2-init
+// @Test: initialization of arrays of raws
+// @Result: PASS
+
+component array_raw04 {
+    field a: 64[] = { 0xf0000000fe710000, 0b100, 'c', -1 };
+    field av: 64  = a[0];
+}
+
+/* 
+heap {
+    record #0:4:array_raw04 {
+\tfield a: raw.64[] = #1:raw.64[4];
+\tfield av: raw.64 = raw.64:0xf0000000fe710000;
+    }
+    record #1:3:16[4] {
+\tfield 0: raw.64 = raw.64:0xf0000000fe710000;
+\tfield 1: raw.64 = raw.64:0x00000004;
+\tfield 2: raw.64 = raw.64:0x00000063;
+\tfield 3: raw.64 = raw.64:0xffffffffffffffff;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: switch statements should have compile-time computable values
+// @Result: DuplicateCase @ 8:18
+
+class switch08 {
+    method testm(a: int): int {
+        switch(a) {
+            case(2-1) ;
+            case(1) ;
+        }
+        return 0;
+    }
+}    
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > binary constants
+// @Result: PASS
+
+class raw_bin01 {
+    field a: 1  = 0b0;
+    field b: 2  = 0b01;
+    field c: 3  = 0b101;
+    field d: 4  = 0b0101;
+    field e: 5  = 0b10101;
+    field f: 6  = 0b010101;
+    field g: 7  = 0b1010101;
+    field h: 8  = 0b01010101;
+    field i: 9  = 0b101010101;
+    field j: 10 = 0b0101011010;
+    field k: 12 = 0b011111000011;
+    field l: 13 = 0b0110010101011;
+    field m: 15 = 0b011010010101011;
+    field n: 16 = 0b0111010101000011;
+    field o: 17 = 0b01111000001010101;
+    field p: 23 = 0b01110100101010100000111;
+    field q: 24 = 0b011010101001001110101010;
+    field r: 25 = 0b0100101010010010010001010;
+    field s: 31 = 0b0110101000100010101001001110011;
+    field t: 32 = 0b01101001000101010010011110101001;
+    field u: 33 = 0b010010100010011111110010101010101;
+    field v: 63 = 0b010101010101001010100010101010010101010101001010100001010101010;
+    field w: 64 = 0b0101001010010101010100101001010100101000000001010111110101010100;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types, >> operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_shr04 {
+    field a: 7;
+    field b: 7;
+    field c: 2 = a >> b;
+}
+"
+"// @Harness: v2-seman
+// @Test: statements
+// @Result: NotAStatement @ 6:5
+
+class stmt05 {
+    
+    method testm(a: stmt05) {
+        a;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component arith12 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(-8, 3);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(0, -1);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -5);
+    field res_07: int = op(13455, -17);
+    field res_08: int = op(64, 8);
+    field res_09: int = op(255, 19);
+    field res_10: int = op(-48576, 1000);
+
+    method op(a: int, b: int): int {
+\treturn a % b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:arith12 {
+        field res_01: int = int:1;
+        field res_02: int = int:-2;
+        field res_03: int = int:0;
+        field res_04: int = int:0;
+        field res_05: int = int:-5;
+        field res_06: int = int:0;
+        field res_07: int = int:8;
+        field res_08: int = int:0;
+        field res_09: int = int:8;
+        field res_10: int = int:-576;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 8:32
+
+component for6 {
+    
+    method count(max: int): int {
+\tlocal i: int;
+        for ( i = 1; i <= max; continue ) ;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_int_char01 {
+    
+    method testm() {
+        local a: int = false ? 0 : '1';
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 6:5
+
+class type_res08 {
+    
+    method testm() {
+        new foo();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking of operators
+// @Result: TypeMismatch @ 6:25
+
+class type_func10 {
+  field f: function() = g;
+  method g(a: int) { }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array24 {
+    field a_01: function(): int[] = f;
+
+    method f(): int[] {
+        return null;
+    }
+}
+
+/* 
+heap {
+    record #0:1:array24 {
+        field a_01: function():int[] = [#0:array24,array24:f()];
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class dowhile2 {
+  method m(a: int, foo: bool) {
+
+     do {
+       local x = a;
+     } while ( true ) ;
+
+     do {
+       local x = a;
+       x = x + 1;
+     } while ( foo ) ;
+  }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > binary constants
+// @Result: TypeMismatch @ 6:18
+
+class raw_bin08 {
+    field a: 11 = 0b010010100000;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class array_raw05 {
+    field a: 9[] = { 0xf, 0b00 };
+    field b: 17[] = { 0xefef, 0b1100101 };
+    field c: 33[] = { 07755642, 0b000000000 };
+
+    field av: 9  = a[0];
+    field bv: 17 = b[2];
+    field cv: 33 = b[11];
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of multidimensional arrays""
+// @Result: PASS
+
+class array11 {
+    
+    method testm(a: int[][]): int[][] {
+        return testm(a);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 6:13
+
+class lvalue15 {
+    field foo: int = testm() = 0;
+    
+    method testm(): int {
+        return 0;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array07 {
+    field a_01: int[] =  new int[1];
+    field a_02: int[] =  new int[2];
+}
+
+/* 
+heap {
+    record #0:2:array07 {
+        field a_01: int[] = #1:int[1];
+        field a_02: int[] = #2:int[2];
+    }
+    record #1:1:int[1] {
+        field 0:int = int:0;
+    }
+    record #2:2:int[2] {
+        field 0:int = int:0;
+        field 1:int = int:0;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 8:7 
+
+class unreach8 {
+    
+    method testm() {
+        while ( true ) {
+            {
+                break;
+            }
+            local foo: int = 0;
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_int_raw01 {
+    
+    method testm() {
+        local a: 32 = false ? 0 : 0x0f;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=2, 3=3, 4=12, 5=12, 6=0
+
+component order12 {
+    field order: int[] = { 0, 0, 0 };
+    field pos: int = 0;
+
+    field data: int[] = { 7 };
+
+    method first(): int[] {
+        order[pos] = 1;
+        pos++;
+        return data;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method third(a: int): int {
+        order[pos] = 3;
+        pos++;
+        return a;
+    }
+
+    method main(arg: int): int {
+        local result = first()[second(0)] = third(12);
+\tif ( arg == 1 ) return order[0];
+\tif ( arg == 2 ) return order[1];
+\tif ( arg == 3 ) return order[2];
+\tif ( arg == 4 ) return result;
+\tif ( arg == 5 ) return data[0];
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class A<X> { } 
+
+class cast10 {
+   method m<T>(x: A<T>) {
+      local f = x :: (A<int>);
+   }
+}
+"
+"program rma_down01 {
+    entrypoint main = Main.entry;
+}
+
+component Main {
+    field f: A = new A();
+    field g: B = new B();
+
+    method entry() {
+\twhile ( true ) {
+\t    f = g; 
+\t    g = move(g);
+        }
+    }
+    method move(b: B): B {
+\tb.other = b;
+\treturn b;
+    }
+}
+
+class A {
+    field other: A;
+}
+
+class B extends A {
+}
+"
+"// @Harness: v2-exec
+// @Test: logical operators
+// @Result: 0=0, 1=1, 2=1, 3=0, 4=0, 5=0
+
+component logical05 {
+
+    method op(a: bool, b: bool): bool {
+\treturn a == b; // equivalent to xor operation
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(true, true);
+\tif ( arg == 2 ) return op(false, false);
+\tif ( arg == 3 ) return op(true, false);
+\tif ( arg == 4 ) return op(false, true);
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: compound assignment operators
+// @Result: 0=0, 1=8, 2=8, 3=0
+
+component cmpassn01 {
+    field foo: int = 6;
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = (foo += 2);
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test variable initialization in compound assignment""
+// @Result: PASS
+
+class compound04 {
+
+    method testm() {
+        local cntr = 0;
+        cntr = cntr += 2;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component dowhile05 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        do {
+\t    cumul += i++;
+\t    if ( i > max ) return cumul;
+\t} while ( true );
+\treturn cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:dowhile05 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; subtyping relations between objects
+// @Result: TypeMismatch @ 9:16
+
+class type26_a {
+}
+class type26_b extends type26_a {
+    
+    method testm(y: type26_a) {
+        local x: type26_b = y;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization interpreter > raw types > and operator
+// @Result: 0=3, 1=3, 2=7, 3=11, 4=19, 5=35, 6=67, 7=131
+
+class raw_index09_a {
+    field foo: 8 = 0x03;
+}
+
+component raw_index09 {
+    field f: raw_index09_a = new raw_index09_a();
+
+    method main(arg: int): 8 {
+\tf.foo[arg] = 0b1;
+\treturn f.foo;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=16, 2=16, 3=0
+
+component cmpassn03 {
+    field foo: int = 8;
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = (foo *= 2);
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_char02 {
+    field a: int = '0' :: int;
+    field b: int = '\
+' :: int;
+    field c: int = '\\367' :: int;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class meth05 {
+    method m() { }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 10:12
+
+class switch_init01 {
+    
+    method testm(a: int) {
+        local uninit: int;
+        switch ( 0 ) {
+            case ( 1 ) uninit = 2;
+        }
+        testm(uninit);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_shl01 {
+    field res_01: 32 = op(0x0f, 1);
+    field res_02: 32 = op(2, 2);
+    field res_03: 32 = op(1, 31);
+    field res_04: 32 = op(0, 8);
+    field res_05: 32 = op(0xf0, 16);
+    field res_06: 32 = op(65535, 2);
+    field res_07: 32 = op(0x10000, 16);
+    field res_08: 32 = op(64, 32);
+    field res_09: 32 = op(255, 5);
+    field res_10: 32 = op(0xaa, 0);
+
+    method op(a: 32, b: int): 32 {
+\treturn a << b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:raw_shl01 {
+        field res_01: raw.32 = raw.32:0x1e;
+        field res_02: raw.32 = raw.32:0x8;
+        field res_03: raw.32 = raw.32:0x80000000;
+        field res_04: raw.32 = raw.32:0x0;
+        field res_05: raw.32 = raw.32:0xf00000;
+        field res_06: raw.32 = raw.32:0x3fffc;
+        field res_07: raw.32 = raw.32:0x0;
+        field res_08: raw.32 = raw.32:0x0;
+        field res_09: raw.32 = raw.32:0x1fe0;
+        field res_10: raw.32 = raw.32:0xaa;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: dynamically allocated memory exceptions
+// @Result: 0=42, 1=AllocationException, 2=AllocationException, 3=AllocationException, 4=42
+
+component rtex_alloc01 {
+
+    method foo(): int[] {
+\tlocal x = { 11, 12, 13, 14 };
+\treturn x;
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1) return foo()[0];
+\tif ( arg == 2) return foo()[1];
+\tif ( arg == 3) return foo()[2];
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeCast operation
+// @Result: PASS
+
+class cast02_01 {
+    field bar: cast02_02;
+    field foo: cast02_01 = bar :: cast02_01;
+}
+
+class cast02_02 extends cast02_01 {
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=0, 5=0
+
+component overflow04 {
+
+    field f: int = 2147483647;
+    field g: int = -2147483648;
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return (f - 1) > 0;
+\tif ( arg == 2 ) return (f - 1) < f;
+\tif ( arg == 3 ) return (g - 1) > 0;
+\tif ( arg == 4 ) return (g - 1) == 0;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: constructors
+// @Result: SuperClauseMustBeInClass @ 5:20
+
+component constructor18 {
+    constructor(): super() {
+    }
+
+}
+"
+"// @Harness: v2-init
+// @Test: integers comparison operators
+// @Result: PASS
+
+component comp04 {
+    field res_01: bool = op(1, 2);
+    field res_02: bool = op(2, 1);
+    field res_03: bool = op(-1, 1);
+    field res_04: bool = op(-1, 0);
+    field res_05: bool = op(-200, -200);
+    field res_06: bool = op(65535, 65535);
+    field res_07: bool = op(14, 13);
+    field res_08: bool = op(13, 14);
+    field res_09: bool = op(-1255, -255);
+    field res_10: bool = op(1000000, 48576);
+
+    method op(a: int, b: int): bool {
+\treturn a >= b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:comp04 {
+        field res_01: bool = bool:false;
+        field res_02: bool = bool:true;
+        field res_03: bool = bool:false;
+        field res_04: bool = bool:false;
+        field res_05: bool = bool:true;
+        field res_06: bool = bool:true;
+        field res_07: bool = bool:true;
+        field res_08: bool = bool:false;
+        field res_09: bool = bool:false;
+        field res_10: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=11, 3=31, 4=42
+
+class virtual05a_1 {
+    method val(): int { return 11; }
+}
+
+class virtual05a_2 extends virtual05a_1 {
+}
+
+class virtual05a_3 extends virtual05a_2 {
+    method val(): int { return 31; }
+}
+
+component virtual05a {
+    field a: virtual05a_1 = new virtual05a_1();
+    field b: virtual05a_1 = new virtual05a_2();
+    field c: virtual05a_1 = new virtual05a_3();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val();
+\tif ( arg == 2 ) return b.val();
+\tif ( arg == 3 ) return c.val();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 8:8
+
+class unreach3 {
+    
+    method testm(): int {
+        while ( true ) {
+            continue;
+            break;
+        }
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 8:15
+
+component for7 {
+    
+    method count(max: int): int {
+\tlocal i = 0;
+        for ( continue; i <= max; i++ ) ;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class compare02<X> {
+    field f: X;
+    field b: bool = f != f;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class A<X> { } 
+class B<X> extends A<int> { }
+
+class cast14 {
+   method m<T>(x: A<T>) {
+      local f = x :: (B<char>);
+   }
+}
+"
+"program P {
+   entrypoint main = Foo.main;
+   entrypoint foo = Foo.entry;
+}
+
+component Foo {
+   method main() { 
+   }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test variable initialization in compound assignment""
+// @Result: PASS
+
+class compound03 {
+
+    method testm() {
+        local cntr = 0;
+        cntr += 2;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=14, 5=42
+
+class A {
+    method m(c: C): int { return 11; }
+}
+
+class B extends A {
+    method m(c: C): int { return 12; }
+}
+
+class C {
+    method n(a: A): int { return 13; }
+}
+
+class D extends C {
+    method n(a: A): int { return 14; }
+}
+
+component virtual09 {
+    field a: A = new A();
+    field b: A = new B();
+    field c: C = new C();
+    field d: C = new D();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.m(c);
+\tif ( arg == 2 ) return b.m(d);
+\tif ( arg == 3 ) return c.n(a);
+\tif ( arg == 4 ) return d.n(b);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: Virgil constructors
+// @Result: PASS
+
+class constructor05 {
+
+    field f: int;
+
+    constructor(a: int) {
+        f = a;
+    }
+
+    method testm(): constructor05 {
+        return new constructor05(0);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component prepost16 {
+    field foo: int[] = { 1 };
+    field bar: int = ++foo[0];
+}
+
+/* 
+heap {
+    record #0:2:prepost16 {
+        field foo: int[] = #1:int[1];
+        field bar: int = int:2;
+    }
+    record #1:1:int[1] {
+\tfield 0: int = int:2;
+    }
+}*/
+"
+"// @Harness: v2-init
+// @Test: conversion between raw types of various sizes
+// @Result: PASS
+
+component raw_raw01 {
+    field a: 4  = 0xf;
+    field b: 8  = a :: 8;
+    field c: 16 = a :: 16;
+    field d: 32 = a :: 32;
+}
+
+/* 
+heap {
+    record #0:14:raw_raw01 {
+        field a: 4  = raw.4:0xf;
+        field b: 8  = raw.8:0xf;
+        field c: 16 = raw.16:0xf;
+        field d: 32 = raw.32:0xf;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: return statement
+// @Result: PASS
+
+component return02 {
+    
+    field x: int;
+
+    constructor() {
+\tm();
+    }
+
+    method m() {
+\tx = 11;
+\tif ( true ) return;
+    }
+}
+
+/* 
+heap {
+    record #0:1:return02 {
+        field x: int = int:11;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: operation of instanceof construct
+// @Result: PASS
+
+class instof06_a {
+}
+
+class instof06_b extends instof06_a {
+}
+
+class instof06_c extends instof06_b {
+}
+
+component instof06 {
+    field foo: instof06_a = new instof06_c();
+    field bar: bool = foo instanceof instof06_b;
+}
+
+/* 
+heap {
+    record #0:2:instof06 {
+        field foo: instof06_a = #1:instof06_c;
+        field bar: bool = bool:true;
+    }
+    record #1:0:instof06_c {
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 6:5
+
+class lvalue5 {
+    
+    method testm() {
+        this = null;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh01<X> {
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 7:23
+
+class init06 {
+    
+    method testm() {
+        local foo: int;
+        foo = foo = foo = foo;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: TypeMismatch @ 7:19
+
+class raw_int04 {
+    field a: int;
+    field b: 31 = a;
+    field c: 32 = a;
+    field d: 48 = a;
+    field e: 64 = a;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class ovr_method04_a<X> extends ovr_method04_b<X, int> {
+  method f(x: X, y: int): X;
+}
+
+class ovr_method04_b<X, Y> {
+  method f(x: X, y: Y): X;
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: UnresolvedIdentifier @ 6:11
+
+class local_res06 {
+    
+    method testm() {
+        for ( foo = 0; ; ) ;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type06 {
+    field f: function();
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class method09 {
+    method m1<X, Y>(a: function(X): Y, b: X): Y {
+        return a(b);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of evaluation)
+// @Result: PASS
+
+class init33 {
+    
+    method testm(): bool {
+        local b: bool;
+        while ( b = false ) ;
+        return b;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class assign09<X> {
+   field f: X;
+   field g: X = m(g);
+
+   method m(x: X): X {
+      return x;
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=14, 3=15, 4=42
+
+class array23_obj {
+    field foo: int;
+    constructor(i: int) { foo = i; }
+}
+
+component array23 {
+    field i: array23_obj = new array23_obj(13);
+    field j: array23_obj = new array23_obj(14);
+    field k: array23_obj = new array23_obj(15);
+    field m: array23_obj = new array23_obj(42);
+
+    field a: array23_obj[][] =  { {i}, {j}, {k} };
+    field ma: array23_obj[] = { m };
+
+    method main(arg: int): int {
+        local r = ma;
+\tif ( arg == 1 ) r = a[0];
+\tif ( arg == 2 ) r = a[1];
+\tif ( arg == 3 ) r = a[2];
+\treturn r[0].foo;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: CannotOverrideReturnType @ 5:15
+
+class ovr_method05_a<X> extends ovr_method05_b<X> {
+  method f(): int;
+}
+
+class ovr_method05_b<X> {
+  method f(): X;
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: UnresolvedIdentifier @ 6:5
+
+class local_res14 {
+    
+    method testm() {
+        foo = 0;
+        testm();
+        local foo: int;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; subtyping relations between objects
+// @Result: PASS
+
+class type25_a {
+}
+class type25_b extends type25_a {
+    
+    method testm() {
+        local x: type25_a = new type25_b();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_align01 {
+    field res_01: bool = aligned(0xfa, 0);
+    field res_02: bool = aligned(0xf4, 1);
+    field res_03: bool = aligned(0xf1, 2);
+    field res_04: bool = aligned(0xf0, 3);
+    field res_05: bool = aligned(0xff, 4);
+    field res_06: bool = aligned(0xf7, 5);
+    field res_07: bool = aligned(0xfa, 6);
+
+    method aligned(a: 32, k: int): bool {
+\tlocal mask = (0x00000001 << k) :: int;
+\treturn (a & (mask - 1)) == 0x00000000;
+    }
+}
+
+/* 
+heap {
+    record #0:6:raw_align01 {
+        field res_01: bool = bool:true;
+        field res_02: bool = bool:true;
+        field res_03: bool = bool:false;
+        field res_04: bool = bool:true;
+        field res_05: bool = bool:false;
+        field res_06: bool = bool:false;
+        field res_07: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 12:12
+
+class for_init03 {
+    
+    method testm(a: int) {
+        local foo: int;
+        local uninit: int;
+
+        for ( foo = 1; foo < a; foo ) uninit = 2;
+
+        testm(foo);
+        testm(uninit);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class A<X> { } 
+class B<X> extends A<X> { }
+
+class instof11 {
+   method m(x: A<int>) {
+      local f = x <: (B<int>);
+   }
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeMismatch @ 6:25
+
+class assign13<X> {
+   field f: assign13<int>;
+   field g: assign13<X> = f;
+}
+"
+"// @Harness: v2-seman
+// @Test: constructors
+// @Result: ArgumentCountMismatch @ 11:32
+
+class constructor21_a {
+    constructor(a: int) {
+    }
+}
+
+class constructor21_b extends constructor21_a {
+    constructor(a: int) : super(0, 3) {
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator
+// @Result: PASS
+
+component raw_index08 {
+
+    field f: 8[] = { 0xf0, 0xf0, 0xf0, 0xf0 };
+
+    constructor() {
+\tf[0][-1] = 0b1;
+\tf[1][3]  = 0b1;
+\tf[2][7]  = 0b0;
+\tf[3][9]  = 0b1;
+    }
+}
+
+/*
+heap {
+    record #0:1:raw_index08 {
+\tfield f: 8[] = #1:8[4];
+    }
+    record #1:4:8[4] {
+\tfield 0: 8 = raw.8:0xf0;
+\tfield 1: 8 = raw.8:0xf8;
+\tfield 2: 8 = raw.8:0x70;
+\tfield 3: 8 = raw.8:0x0f0;
+    }
+}
+*/
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of evaluation)
+// @Result: PASS
+
+class order_init06 {
+    
+    method testm(a: bool) {
+        local foo: bool;
+        if ( foo = true ) testm(foo);
+    }
+}
+"
+"program HelloWorld {
+    entrypoint main = HelloWorld.main;
+}
+
+component HelloWorld {
+    method main(a: int): int {
+    \tlocal c = 5 * a;
+    \tlocal b = 0;
+    \tlocal i: int;
+    \tlocal j: int;
+    \tif(c < 100)
+    \t{
+\t\t\t\tfor (i = 0; i < 10; i++) {
+\t\t\t\t\tfor (j = 0; j < 20; j++) {
+\t\t\t\t\t\ta=a*a;
+\t\t\t\tif ( c==a ) 
+\t\t\t\t\treturn -5;
+\t\t\t}
+\t\t}
+
+\t\t}
+\t\treturn b;
+\t}
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component switch08 {
+    field foo: int = ds(8);
+
+    method ds(v: int): int {
+\tswitch ( v ) {
+\t    case ( 0 ) return 10;
+\t    case ( 1 ) return 11;
+\t    case ( 2 ) return 12;
+\t    case ( 3 ) return 13;
+\t    case ( 4, 5 ) return 15;
+\t    case ( 7, 8, 9 ) return 20;
+\t    default return -1;
+        }
+    }
+}
+
+/* 
+heap {
+    record #0:1:switch08 {
+        field foo: int = int:20;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type09 {
+    field f: type[];
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component arith12 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(-8, 3);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(0, -1);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -5);
+    field res_07: int = op(13455, -17);
+    field res_08: int = op(64, 8);
+    field res_09: int = op(255, 19);
+    field res_10: int = op(-48576, 1000);
+
+    method op(a: int, b: int): int {
+\treturn a % b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(1, -2) == res_01;
+\tif ( arg == 2 )  return op(-8, 3) == res_02;
+\tif ( arg == 3 )  return op(-1, -1) == res_03;
+\tif ( arg == 4 )  return op(0, -1) == res_04;
+\tif ( arg == 5 )  return op(-200, 13) == res_05;
+\tif ( arg == 6 )  return op(65535, -5) == res_06;
+\tif ( arg == 7 )  return op(13455, -17) == res_07;
+\tif ( arg == 8 )  return op(64, 8) == res_08;
+\tif ( arg == 9 )  return op(255, 19) == res_09;
+\tif ( arg == 10 ) return op(-48576, 1000) == res_10;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type12 {
+    field f: function(): function(): type;
+}
+"
+"// @Harness: v2-init
+// @Test: initialization of arrays of raws
+// @Result: PASS
+
+component array_raw01 {
+    field a: 8[] = { 0xf, 0b00, 'c' };
+    field av: 8  = a[0];
+}
+
+/* 
+heap {
+    record #0:4:array_raw01 {
+\tfield a: raw.8[] = #1:raw.8[3];
+\tfield av: raw.8 = raw.8:0x0f;
+    }
+    record #1:3:8[3] {
+\tfield 0: raw.8 = raw.8:0x0f;
+\tfield 1: raw.8 = raw.8:0x00;
+\tfield 2: raw.8 = raw.8:0x63;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Transform<R, E> {
+    method visitA(n: A, e: E): R;
+    method visitB(n: B, e: E): R;
+}
+
+class A {
+}
+
+class B {
+}
+"
+"// @Harness: v2-seman
+// @Test: constructors and inheritance
+// @Result: PASS
+
+class constructor15_a {
+    constructor(a: int) {
+    }
+}
+
+class constructor15_b extends constructor15_a {
+    constructor(a: int): super(a) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > auto extension
+// @Result: TypeMismatch @ 7:19
+
+class raw_assn03 {
+    field a: 3;
+    field b: 2 = a;
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=6, 2=7, 3=0
+
+class prepost14_obj {
+    field foo: int = 6;
+    field bar: int;
+    method inc(): int {
+\tlocal i = foo;
+\treturn ++i;
+    }
+}
+
+component prepost14 {
+    field foo: prepost14_obj = new prepost14_obj();
+
+    method main(arg: int): int {
+\tfoo.bar = foo.inc();
+\tif ( arg == 1 ) return foo.foo;
+\tif ( arg == 2 ) return foo.bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component dowhile05 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        do {
+\t    cumul += i++;
+\t    if ( i > max ) return cumul;
+\t} while ( true );
+\treturn cumul;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:12
+
+class field02 {
+    field g: type<X, Y>;
+    field f;
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=1, 2=2, 3=3, 4=4
+
+component prepost23 {
+    method main(arg: int): int {
+\treturn arg++;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class method07 {
+    method m1<X, Y>(a: type<X, Y>, b: type<Y>): type<X> {
+        return b;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 10:17
+
+component type_res12a {
+    field g: int = type_res12b.m();
+}
+
+component type_res12b {
+    method m(): unknown[];
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: CannotOverrideParamType @ 9:29
+
+class inh27_a {
+    method testm(x: int, y: int): int;
+}
+class inh27_b extends inh27_a {
+    method testm(x: int, y: bool): int;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_array05 {
+    method test() {
+\tset0(new int[3], 0);
+    }
+    method set0<X>(a: X[], b: X) {
+\ta[0] = b;\t
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class13<X, Y> extends class13a<X, function(Y): int> {
+}
+"
+"// @Harness: v2-seman
+// @Test: constructors and inheritance
+// @Result: PASS
+
+class constructor12_a {
+}
+
+class constructor12_b extends constructor12_a {
+    constructor() {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeQuery (instanceof) operation
+// @Result: PASS
+
+class instof02b_01 {
+    field bar: instof02b_02;
+    field foo: bool = bar <: instof02b_01;
+}
+
+class instof02b_02 extends instof02b_01 {
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeQuery (instanceof) operation
+// @Result: ExpectedObjectType @ 7:30
+
+class instof05a_01 {
+    field bar: instof05a_01;
+    field foo: bool = bar instanceof int;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Visitor<E> {
+    method visitA(n: A, e: E);
+    method visitB(n: B, e: E);
+}
+
+class A {
+}
+
+class B {
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 7:40
+
+class type_res19 {
+    method foo(): type_res16 {
+\treturn new unknown();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking success
+// @Result: PASS
+
+class int_add01 {
+    
+    method testm(a: int, x: int): int {
+        return 4 + x + a + 2;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=UnimplementedException, 2=21, 3=31, 4=42
+
+class A<T> {
+    method val(): T;
+}
+
+class B extends A<int> {
+    method val(): int { return 21; }
+}
+
+class C extends A<int> {
+    method val(): int { return 31; }
+}
+
+component ptex_virt02 {
+    field a: A<int> = new A<int>();
+    field b: A<int> = new B();
+    field c: A<int> = new C();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val();
+\tif ( arg == 2 ) return b.val();
+\tif ( arg == 3 ) return c.val();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=6, 2=5, 3=0
+
+component prepost05 {
+    method main(arg: int): int {
+\tlocal foo = 5;
+\tlocal bar = foo++;
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: type check exceptions (i.e. dynamic casts)
+// @Result: 0=41, 1=10, 2=11, 3=12, 4=10, 5=11, 6=12, 7=41
+
+class rtex_type05_a {
+    field foo: int;
+
+    constructor(f: int) { 
+\tfoo = f; 
+    }
+}
+
+class rtex_type05_b extends rtex_type05_a {
+    constructor(): super(11) { }
+}
+
+class rtex_type05_c extends rtex_type05_a {
+    constructor(): super(12) { }
+}
+
+component rtex_type05 {
+    field a: rtex_type05_a = new rtex_type05_a(10);
+    field b: rtex_type05_b = new rtex_type05_b();
+    field c: rtex_type05_c = new rtex_type05_c();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return (a::rtex_type05_a).foo;
+\tif ( arg == 2 ) return (b::rtex_type05_a).foo;
+\tif ( arg == 3 ) return (c::rtex_type05_a).foo;
+\tif ( arg == 4 ) return (a::rtex_type05_a).foo;
+\tif ( arg == 5 ) return (b::rtex_type05_b).foo;
+\tif ( arg == 6 ) return (c::rtex_type05_c).foo;
+
+\treturn 41;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization of arrays of raws
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=0
+
+component array_raw04 {
+    field a: 64[] = { 0xf0000000fe710000, 0b100, 'c', -1 };
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return a[0] == 0xf0000000fe710000;
+\tif ( arg == 2 ) return a[1] == 0x0000000000000004;
+\tif ( arg == 3 ) return a[2] == 0x0000000000000063;
+\tif ( arg == 4 ) return a[3] == 0xffffffffffffffff;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: ExpectedVarType @ 8:19
+
+component local4 {
+    
+    method testm() {
+        local foo = bar();
+    }
+
+    method bar() {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: statements
+// @Result: NotAStatement @ 6:5
+
+class stmt06 {
+    
+    method testm(a: int[]) {
+        a[0];
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: statements
+// @Result: NotAStatement @ 6:5
+
+class stmt09 {
+    
+    method testm() {
+        !true;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeMismatch @ 6:15
+
+class assign12<X, Y> {
+   field f: X;
+   field g: Y = f;
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Result: 0=0, 1=11, 2=21, 3=31, 4=0
+
+component static02_a {
+    field foo: int = 11;
+    method val(): int { return foo; }
+}
+
+component static02_b {
+    field baz: int = 21;
+    method val(): int { return baz; }
+}
+
+component static02_c {
+    field bof: int = 31;
+    method val(): int { return bof; }
+}
+
+component static02 {
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return static02_a.val();
+\tif ( arg == 2 ) return static02_b.val();
+\tif ( arg == 3 ) return static02_c.val();
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: order of operators in evaluating bit updates
+// @Result: PASS
+
+component raw_order02 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    field data: 32 = 0x6;
+    field res_01: 1 = data[first(0)] = second(0b1);
+
+    method first(a: int): int {
+        order[pos] = 1;
+        pos++;
+        return a;
+    }
+
+    method second(a: 1): 1 {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+}
+
+/* 
+heap {
+    record #0:4:raw_order02 {
+        field order: int[] = #1:int[2];
+        field pos: int = int:2;
+        field data: raw.32 = raw.32:0x7;
+        field res_01: raw.1 = raw.1:0b1;
+    }
+    record #1:3:int[2] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+class this03_obj {
+    field bar: int = this.baz();
+    method baz(): int { return 5; }
+}
+
+component this03 {
+    field foo: this03_obj = new this03_obj();
+}
+
+/* 
+heap {
+    record #0:1:this03 {
+        field foo: this03_obj = #1:this03_obj;
+    }
+    record #1:1:this03_obj {
+        field bar: int = int:5;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_field02_a<X> extends inh_field02_b<int> {
+  field g: int = f;
+}
+
+class inh_field02_b<X> {
+  field f: X;
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=104, 2=101, 3=42
+
+class field06b_obj {
+    field a: char = 'h';
+    field b: char = 'e';
+}
+
+component field06b {
+    field foo: field06b_obj = new field06b_obj();
+
+    method main(arg: int): char {
+\tif ( arg == 1 ) return foo.a;
+\tif ( arg == 2 ) return foo.b;
+\treturn '*';
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: method resolution
+// @Result: PASS
+
+component method_res10 {
+    
+    method foo() {
+    }
+    
+    method testm() {
+        foo();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_field04_a extends inh_field04_b<int> {
+  field g: int = f;
+}
+
+class inh_field04_b<X> {
+  field f: X;
+}
+"
+"component Conversions {
+
+\tmethod int_char(v: int): char { return v :: char; }
+\tmethod char_int(v: char): int { return v :: int; }
+
+\tmethod int_raw32(v: int): 32 { return v :: 32; }
+\tmethod raw32_int(v: 32): int { return v :: int; }
+
+\tmethod int_raw16(v: int): 16 { return v :: 16; }
+\tmethod raw16_int(v: 16): int { return v :: int; }
+
+\tmethod char_raw8(v: char): 8 { return v :: 8; }
+\tmethod raw8_char(v: 8): char { return v :: char; }
+
+\tmethod bool_raw1(v: boolean): 1 { return v ? 0b1 : 0b0; }
+\tmethod raw1_bool(v: 1): boolean { return v == 0b1; }
+}"
+"// @Harness: v2-seman
+// @Test: variable initialization (pre-increment operator)
+// @Result: VariableNotInitialized @ 8:16
+
+class init08 {
+    
+    method testm(): int {
+        local a: int;
+        return a;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=0, 2=0, 3=0, 4=0, 5=42
+
+component alloc_array04 {
+    field a: int[] =  a_int();
+    field b: bool[] =  a_bool();
+    field c: char[] = a_char();
+    field d: char[] = a_str();
+
+    method a_int(): int[] {
+\tlocal a: int[] = {};
+        return a;
+    }
+
+    method a_bool(): bool[] {
+\tlocal a: bool[] = {};
+        return a;
+    }
+
+    method a_char(): char[] {
+\tlocal a: char[] = {};
+        return a;
+    }
+
+    method a_str(): char[] {
+        return """";
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.length;
+\tif ( arg == 2 ) return b.length;
+\tif ( arg == 3 ) return c.length;
+\tif ( arg == 4 ) return d.length;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Visitor<E> {
+    method visitA(n: A, e: E);
+    method visitB(n: B, e: E);
+}
+
+class S {
+    method accept<E>(v: Visitor<E>, e: E);
+}
+
+class A extends S {
+    method accept<E>(v: Visitor<E>, e: E) { v.visitA(this, e); }
+}
+
+class B extends S {
+    method accept<E>(v: Visitor<E>, e: E) { v.visitB(this, e); }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component field03 {
+    field foo: int = bar();
+    method bar(): int { return 1; }
+}
+
+/* 
+heap {
+    record #0:1:field03 {
+        field foo: int = int:1;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: VariableNotInitialized @ 8:12
+
+class short_init05 {
+    
+    method testm(p: bool) {
+        local uninit: bool;
+        if ( p and (uninit = p) ) ;
+        else testm(uninit);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shorcutting of conditionals)
+// @Result: VariableNotInitialized @ 8:39
+
+class for_short_init05 {
+    
+    method testm(p: bool) {
+        local uninit: bool;
+        for ( ; p or (uninit = p); testm(uninit) ) ;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_field07_a extends inh_field07_b {
+  field h: int = f;
+  field j: bool = g;
+}
+
+class inh_field07_b extends inh_field07_c<int, bool> {
+}
+
+class inh_field07_c<Y, Z> {
+  field f: Y;
+  field g: Z;
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component order10 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    field res_01: int[][] = new int[first(1)][second(2)];
+
+    method first(a: int): int {
+        order[pos] = 1;
+        pos++;
+        return a;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+}
+
+/* 
+heap {
+    record #0:10:order10 {
+        field order: int[] = #1:int[2];
+        field pos: int = int:2;
+        field res_01: int = #2:int[][1];
+    }
+    record #1:2:int[2] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+    }
+    record #2:1:int[][1] {
+\tfield 0: int[] = #3:int[2];
+    }
+    record #3:2:int[2] {
+\tfield 0: int = int:0;
+\tfield 1: int = int:0;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=7, 2=4, 3=0
+
+class cmpassn11_obj {
+    field foo: 4 = foo = 0x4;
+    field bar: 4;
+}
+
+component cmpassn11 {
+    field foo: cmpassn11_obj = new cmpassn11_obj();
+
+    method main(arg: int): int {
+\tfoo.foo ^= 0x3;
+\tif ( arg == 1 ) return foo.foo :: int;
+\tif ( arg == 2 ) return (foo.foo ^= 0x3) :: int;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class List<X> {
+    method add(x: X) {
+    }
+}
+
+component mp_list01 {
+    method makeList<X>(a: X): List<X> {
+\treturn new List<X>();\t
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component arith09 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(2, -1);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(0, -1);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -1);
+    field res_07: int = op(13455, -17);
+    field res_08: int = op(64, 8);
+    field res_09: int = op(255, 5);
+    field res_10: int = op(-48576, 1000);
+
+    method op(a: int, b: int): int {
+\treturn a / b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return (1 / -2) == res_01;
+\tif ( arg == 2 ) return (2 / -1) == res_02;
+\tif ( arg == 3 ) return (-1 / -1) == res_03;
+\tif ( arg == 4 ) return (0 / -1) == res_04;
+\tif ( arg == 5 ) return (-200 / -13) == res_05;
+\tif ( arg == 6 ) return (65535 / -1) == res_06;
+\tif ( arg == 7 ) return (13455 / -17) == res_07;
+\tif ( arg == 8 ) return (64 / 8) == res_08;
+\tif ( arg == 9 ) return (255 / 5) == res_09;
+\tif ( arg == 10 ) return (-48576 / 1000) == res_10;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component dowhile03 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        do {
+\t    cumul += i;
+\t    if ( i == max ) break;
+\t    i++;
+\t} while ( true );
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 7:6 
+
+class unreach19 {
+    
+    method testm() {
+        return;
+        testm();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: using the char[] type for strings
+// @Result: PASS
+
+class string01 {
+    field testf: char[] = ""foo"";
+}
+"
+"// @Harness: v2-init
+// @Test: array index exceptions
+// @Result: BoundsCheckException @ 7:25
+
+component index05 {
+    field foo: int[] = new int[65536];
+    field bar: int = foo[65536];
+}
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=0, 1=1, 2=0, 3=1, 4=1, 5=1, 6=1, 7=0
+
+component comp11 {
+
+    method op(a: char, b: char): bool {
+\treturn a != b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op('1', '2');
+\tif ( arg == 2 ) return op('1', '1');
+\tif ( arg == 3 ) return op('-', '1');
+\tif ( arg == 4 ) return op('\
+', '\\r');
+\tif ( arg == 5 ) return op(' ', 'a');
+\tif ( arg == 6 ) return op('A', 'B');
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @Result: PASS
+
+component static02_a {
+    field foo: int = 1;
+    method val(): int { return foo; }
+}
+
+component static02_b {
+    field baz: int = 2;
+    method val(): int { return baz; }
+}
+
+component static02_c {
+    field bof: int = 3;
+    method val(): int { return bof; }
+}
+
+component static02 {
+    field av: int = static02_a.val();
+    field bv: int = static02_b.val();
+    field cv: int = static02_c.val();
+}
+
+/* 
+heap {
+    record #0:1:static02_a {
+\tfield foo: int = int:1;
+    }
+    record #1:1:static02_b {
+\tfield baz: int = int:2;
+    }
+    record #2:1:static02_c {
+\tfield bof: int = int:3;
+    }
+    record #3:3:static02 {
+        field av: int = int:1;
+        field bv: int = int:2;
+        field cv: int = int:3;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component while01 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( i <= max ) {
+\t    cumul += i;
+\t    i++;
+\t}
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class C<X> {
+  field g: X;
+}
+
+component init03 {
+  field f: C<int> = new C<int>();
+  constructor() {
+    f.g = -11;
+  }
+}
+
+/*
+heap {
+  record #0:1:init03 {
+    field f: C<int> = #1:C<int>;
+  }
+  record #1:0:C<int> {
+    field g: int = int:-11;
+  }
+}
+*/
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=42, 1=0, 2=0, 3=NullCheckException, 4=0, 5=42
+
+class W<T> {
+    field val: T;
+}
+
+component ptex_wrap08 {
+
+    field a: W<int> = new W<int>();
+    field b: W<int> = new W<int>();
+    field c: W<int[]> = new W<int[]>();
+    field d: W<char> = new W<char>();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val;
+\tif ( arg == 2 ) return b.val;
+\tif ( arg == 3 ) return c.val[0];
+\tif ( arg == 4 ) return d.val;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: compile-time constants for primitive types
+// @Result: PASS
+
+component const_bool01 {
+    field a: bool = true;
+    field b: bool = false;
+}
+
+/* 
+heap {
+    record #0:2:const_bool01 {
+        field a: bool = bool:true;
+        field b: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=5, 2=6, 3=0
+
+class prepost08_obj {
+    field foo: int = 6;
+    field bar: int;
+}
+
+component prepost08 {
+    field foo: prepost08_obj = new prepost08_obj();
+
+    method main(arg: int): int {
+\tfoo.bar = foo.foo--;
+\tif ( arg == 1 ) return foo.foo;
+\tif ( arg == 2 ) return foo.bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive assignments
+// @Result: TypeMismatch @ 6:12
+
+class type07 {
+    
+    method testm(a: int) {
+        testm(false);
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: compound assignment operators
+// @Result: 0=11, 1=5, 2=22, 3=3, 4=15, 5=8, 6=11
+
+component cmpassn29 {
+
+    field foo: 8[] = { 0xb, 0x2a };
+
+    method main(arg: int): 8 {
+\tlocal ind = 0;
+\tif ( arg == 1 ) foo[ind++] >>= 1;
+\tif ( arg == 2 ) foo[ind++] <<= 1;
+\tif ( arg == 3 ) foo[ind++] &= 0x3;
+\tif ( arg == 4 ) foo[ind++] |= 0x5;
+\tif ( arg == 5 ) foo[ind++] ^= 0x3;
+\treturn foo[0];
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: ExpectedVarType @ 8:19
+
+class local1 {
+    
+    method testm() {
+        local foo: void;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: UnresolvedMember @ 10:17
+
+component field_res06_a {
+    field testf: int;
+}
+component field_res06_b {
+    
+    method testm() {
+        field_res06_a.unres = 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Main: map02.main
+// @Result: 0=2, 1=5, 2=9, 3=14, 4=20, 5=27, 6=35, 7=44, 8=54, 9=65
+
+component map02 {
+    field a: int[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
+    field b: int[] = new int[10]; 
+
+    method main(arg: int): int {
+\tmap(a, inc, b, arg);
+\treturn sum(b);
+    }
+
+    method inc(a: int): int {
+\treturn a + 1;
+    }
+
+    // recursive version of map
+    method map(a: int[], f: function(int): int, res: int[], m: int) {
+        if ( m > 0 ) map(a, f, res, m-1);
+        res[m] = f(a[m]);
+    }
+
+    method sum(array: int[]): int {
+\tlocal i = 0, cumul = 0;
+        for ( ; i < array.length; i++ ) cumul += array[i];
+\treturn cumul;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component arith01 {
+    field res_01: int = op(1, 2);
+    field res_02: int = op(2, 1);
+    field res_03: int = op(-1, 1);
+    field res_04: int = op(-1, 0);
+    field res_05: int = op(-200, 13);
+    field res_06: int = op(65535, 1);
+    field res_07: int = op(13, 17);
+    field res_08: int = op(255, 12);
+    field res_09: int = op(255, -255);
+    field res_10: int = op(1000000, 48576);
+
+    method op(a: int, b: int): int {
+\treturn a + b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:arith01 {
+        field res_01: int = int:3;
+        field res_02: int = int:3;
+        field res_03: int = int:0;
+        field res_04: int = int:-1;
+        field res_05: int = int:-187;
+        field res_06: int = int:65536;
+        field res_07: int = int:30;
+        field res_08: int = int:267;
+        field res_09: int = int:0;
+        field res_10: int = int:1048576;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component for01 {
+    
+    method main(max: int): int {
+\tlocal i: int, cumul = 0;
+        for ( i = 1; i <= max; i++ ) cumul += i;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > and operator
+// @Result: PASS
+
+class type_comp01 {
+    field b: 2;
+    field c: 2 = ~b;
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > or operator with expansion
+// @Result: PASS
+
+component eval_or02 {
+    field f1: 8  = 0x10  | 0xf;
+    field f2: 12  = 0x1f0 | 0x0f;
+    field f3: 20 = 0x1f3f3  | 0x1111;
+    field f4: 8  = 0b11110101  | 0b1111111;
+    field f5: 6  = 0b110101  | 0b10000;
+    field f6: 4  = 0b1101  | 0b100;
+    field f7: 36 = 0x1FFFF0000  | 0xF000F000;
+    field f8: 52 = 0x1FF00FFFF0000  | 0xF000F000F000;
+    field f9: 64 = 0xFFFF0000FFFF0000  | 0xF000F000F000F000;
+}
+
+/*
+heap {
+    record #0:1:eval_or02 {
+\tfield f1: 8  = raw.8:0x1f; 
+\tfield f2: 12 = raw.12:0x1ff; 
+\tfield f3: 20 = raw.20:0x1f3f3; 
+\tfield f4: 8  = raw.8:0xff;
+\tfield f5: 6  = raw.6:0x35; 
+\tfield f6: 4  = raw.4:0xd; 
+\tfield f7: 36 = raw.36:0x1fffff000; 
+\tfield f8: 52 = raw.52:0x1ff00fffff000; 
+\tfield f9: 64 = raw.64:0xfffff000fffff000; 
+    }
+}
+*/
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class char_raw01 {
+    field a: char;
+    field b: 8 = a;
+    field c: 16 = a;
+    field d: 32 = a;
+    field e: 64 = a;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_array08 {
+    method test() {
+\tlocal x: int[] = makeArray();
+    }
+    method makeArray<X>(): X[] {
+\treturn new X[0];\t
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; incorrect number of arguments in call
+// @Result: ArgumentCountMismatch @ 6:12
+
+class type05 {
+    
+    method testm(a: int) {
+        testm();
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=4, 2=4, 3=0
+
+component cmpassn06 {
+    field foo: int = 8;
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = (foo /= 2);
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr15 {
+  field foo: type = foo(a,b);
+}
+"
+"// @Harness: v2-seman
+// @Test: cannot declare duplicate fields
+// @Result: ExpectedVarType @ 6:17
+
+component field5 {
+    field testf: void;
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=0
+
+component raw_shl03 {
+    field res_01: 8 = op(0x0f,  1);
+    field res_02: 8 = op(0x02,  2);
+    field res_03: 8 = op(0x01,  7);
+    field res_04: 8 = op(0x70,  5);
+    field res_05: 8 = op(0xf0,  6);
+    field res_06: 8 = op(0xff,  2);
+    field res_07: 8 = op(0x80, 11);
+    field res_08: 8 = op(0xff,  5);
+    field res_09: 8 = op(0xaa,  0);
+
+    method op(a: 8, b: int): 8 {
+\treturn a << b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(0x0f,  1) == res_01;
+\tif ( arg == 2 )  return op(0x02,  2) == res_02;
+\tif ( arg == 3 )  return op(0x01,  7) == res_03;
+\tif ( arg == 4 )  return op(0x70,  5) == res_04;
+\tif ( arg == 5 )  return op(0xf0,  6) == res_05;
+\tif ( arg == 6 )  return op(0xff,  2) == res_06;
+\tif ( arg == 7 )  return op(0x80, 11) == res_07;
+\tif ( arg == 8 )  return op(0xff,  5) == res_08;
+\tif ( arg == 9 )  return op(0xaa,  0) == res_09;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > hexadecimal constants
+// @Result: InvalidLiteral @ 6:19
+
+class raw_hex02 {
+    field a: 64  = 0x0ffffffffffffffff; 
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class cast03b {
+   method m() {
+      local y = x :: (Type<int>);
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component dowhile01 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        do {
+\t    cumul += i;
+\t    i++;
+\t} while ( i <= max );
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:dowhile01 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_int02 {
+    
+    method testm() {
+        local a = { 0, 1 };
+\tlocal b: int[] = a;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=5, 2=5, 3=0
+
+component prepost04 {
+    field foo: int = 6;
+    field bar: int;
+    method main(arg: int): int {
+\tbar = --foo;
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: CannotUnifyBranchTypes @ 8:49
+
+class unify_class06 {
+    
+    method testm(x: int) {
+        local a: unify_class06 = false ? this : x;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+component logical09 {
+    field res_01: bool;
+    field res_02: bool;
+    field res_03: bool;
+    field res_04: bool;
+
+    constructor() {
+\tres_01 = true or false;
+\tres_02 = true or true;
+\tres_03 = false or true;
+\tres_04 = false or false;
+    }
+
+}
+
+/* 
+heap {
+    record #0:4:logical09 {
+\tfield res_01: bool = bool:true;
+\tfield res_02: bool = bool:true;
+\tfield res_03: bool = bool:true;
+\tfield res_04: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:15
+
+class meth03 {
+    method m(a);
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > hexadecimal constants
+// @Result: PASS
+
+class raw_oct01 {
+    field a: 3  = 01;
+    field b: 3  = 07;
+    field c: 6  = 074;
+    field d: 6  = 012;
+    field e: 9  = 0123;
+    field f: 9  = 0654;
+    field g: 15 = 012345;
+    field h: 15 = 077110;
+    field i: 30 = 07111237457;
+    field j: 30 = 01234567123;
+    field k: 42 = 012345670123456;
+    field l: 42 = 077777777777777;
+    field m: 63 = 0777111111111111111111;
+    field n: 63 = 0111111111111111111111;
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component default02a {
+    field foo: bool;
+    field bar: bool = !foo;
+}
+
+/* 
+heap {
+    record #0:2:default02a {
+        field foo: bool = bool:false;
+        field bar: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class mp_ovr01_a {
+    method makeArray<X>(a: X): X[] {
+\treturn new X[0];\t
+    }
+}
+
+class mp_ovr01_b extends mp_ovr01_a {
+    method makeArray<Y>(a: Y): Y[] {
+\treturn new Y[200];\t
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=104, 2=101, 3=108, 4=108, 5=111, 6=42
+
+class field05b_obj {
+    field a: char[] = ""hello"";
+}
+
+component field05b {
+    field foo: field05b_obj = new field05b_obj();
+
+    method main(arg: int): char {
+\tif ( arg == 1 ) return foo.a[0];
+\tif ( arg == 2 ) return foo.a[1];
+\tif ( arg == 3 ) return foo.a[2];
+\tif ( arg == 4 ) return foo.a[3];
+\tif ( arg == 5 ) return foo.a[4];
+\treturn \'*\';
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: divide by zero exception during initialization
+// @Result: DivideByZeroException @ 10:18
+
+component divzero03 {
+    field foo: int = 0;
+    field bar: int = div(1, foo);
+
+    method div(a: int, b: int): int {
+        return a / b;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component cast4 {
+\tfield f: T = a.f :: T;
+\tfield g: T = a.m() :: T;
+\tfield h: T = g() :: T;
+\tfield i: T = a :: T :: V;
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: VariableNotInitialized @ 8:14
+
+class short_init01 {
+    
+    method testm(p: bool) {
+        local uninit: bool;
+        if ( p or (uninit = p) ) {
+            testm(uninit);
+        }
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component cmpassn16 {
+    field foo: int[] = { 1 };
+    field bar: int = foo[0] -= 9;
+}
+
+/* 
+heap {
+    record #0:2:cmpassn16 {
+        field foo: int[] = #1:int[1];
+        field bar: int = int:-8;
+    }
+    record #1:1:int[1] {
+\tfield 0: int = int:-8;
+    }
+}*/
+"
+"// @Harness: v2-init
+// @Test: parsing precedence of arithmetic operators
+// @Result: PASS
+
+component prec01 {
+    field r01: int = 1 + 2 * 3;
+    field r02: int = 1 + 3 * 2;
+    field r03: int = 6 * 1 / 2;
+    field r04: int = 2 / 1 * 8;
+    field r05: int = 4 / 1 / 2;
+    field r06: int = 3 - 2 * 3;
+    field r07: int = 6 - 4 / 2;
+    field r08: int = 6 - 4 * 2 + 7;
+    field r09: int = 6 * 4 - 7 / 2;
+}
+
+/* 
+heap {
+    record #0:10:prec01 {
+        field r01: int = int:7;
+        field r02: int = int:7;
+\tfield r03: int = int:3;
+\tfield r04: int = int:16;
+\tfield r05: int = int:2;
+\tfield r06: int = int:-3;
+\tfield r07: int = int:4;
+\tfield r08: int = int:5;
+\tfield r09: int = int:21;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class virtual05_a {
+    method val(): int { return 1; }
+}
+
+class virtual05_b extends virtual05_a {
+}
+
+class virtual05_c extends virtual05_b {
+    method val(): int { return 3; }
+}
+
+component virtual05 {
+    field a: virtual05_a = new virtual05_a();
+    field b: virtual05_a = new virtual05_b();
+    field c: virtual05_a = new virtual05_c();
+    field av: int = a.val();
+    field bv: int = b.val();
+    field cv: int = c.val();
+}
+
+/* 
+heap {
+    record #0:6:virtual05 {
+        field a: virtual05_a = #1:virtual05_a;
+        field b: virtual05_a = #2:virtual05_b;
+        field c: virtual05_a = #3:virtual05_c;
+        field av: int = int:1;
+        field bv: int = int:1;
+        field cv: int = int:3;
+    }
+    record #1:0:virtual05_a {
+    }
+    record #2:0:virtual05_b {
+    }
+    record #3:0:virtual05_c {
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component for10 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i: int, cumul = 0, loop: int;
+        for ( loop = 1; loop < 2; loop++ ) {
+            for ( i = 1; ; cumul += i, i++ ) {
+\t        if ( i > max ) break;
+\t        else continue;
+\t    }
+\t}
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:for10 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component raw_shr02 {
+    field res_01: 16 = op(0x0f,    1);
+    field res_02: 16 = op(0x02,    2);
+    field res_03: 16 = op(0x8000, 15);
+    field res_04: 16 = op(0xefe,   8);
+    field res_05: 16 = op(0xf0,   16);
+    field res_06: 16 = op(0xaaaa,  4);
+    field res_07: 16 = op(0x7000,  2);
+    field res_08: 16 = op(0x700,   4);
+    field res_09: 16 = op(0xfe09,  5);
+    field res_10: 16 = op(0xaa01,  0);
+
+    method op(a: 16, b: int): 16 {
+\treturn a >> b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(0x0f,    1) == res_01;
+\tif ( arg == 2 )  return op(0x02,    2) == res_02;
+\tif ( arg == 3 )  return op(0x8000, 15) == res_03;
+\tif ( arg == 4 )  return op(0xefe,   8) == res_04;
+\tif ( arg == 5 )  return op(0xf0,   16) == res_05;
+\tif ( arg == 6 )  return op(0xaaaa,  4) == res_06;
+\tif ( arg == 7 )  return op(0x7000,  2) == res_07;
+\tif ( arg == 8 )  return op(0x700,   4) == res_08;
+\tif ( arg == 9 )  return op(0xfe09,  5) == res_09;
+\tif ( arg == 10 ) return op(0xaa01,  0) == res_10;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization of arrays of raws
+// @Result: PASS
+
+component array_raw08 {
+    field a: 51[] = { 0x1000fe710000, 0b100, 'c', -1 };
+    field av: 51  = a[0];
+}
+
+/* 
+heap {
+    record #0:2:array_raw08 {
+\tfield a: raw.51[] = #1:raw.51[4];
+\tfield av: raw.51 = raw.51:0x1000fe710000;
+    }
+    record #1:4:51[4] {
+\tfield 0: raw.51 = raw.51:0x1000fe710000;
+\tfield 1: raw.51 = raw.51:0x00000004;
+\tfield 2: raw.51 = raw.51:0x00000063;
+\tfield 3: raw.51 = raw.51:0x7ffffffffffff;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+
+  method first(): X {
+    return a;
+  }
+
+  method second(): Y {
+    return b;
+  }
+}
+
+component Client {
+  method test() {
+    local p = new Pair<int, bool>();
+    local b: function(): int = p.first;
+    local c: function(): bool = p.second;
+  }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=11, 3=11, 4=42
+
+class private04_a {
+    method getf(): function(): int { return this.val; }
+    private method val(): int { return 11; }
+}
+
+class private04_b extends private04_a {
+    private method val(): int { return 21; }
+}
+
+class private04_c extends private04_a {
+    private method val(): int { return 31; }
+}
+
+component private04 {
+    field a: function():int = new private04_a().getf();
+    field b: function():int = new private04_b().getf();
+    field c: function():int = new private04_c().getf();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a();
+\tif ( arg == 2 ) return b();
+\tif ( arg == 3 ) return c();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=5, 2=5, 3=0
+
+class prepost10_obj {
+    field foo: int = 6;
+    field bar: int;
+}
+
+component prepost10 {
+    field foo: prepost10_obj = new prepost10_obj();
+
+    method main(arg: int): int {
+\tfoo.bar = --foo.foo;
+\tif ( arg == 1 ) return foo.foo;
+\tif ( arg == 2 ) return foo.bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking of array initialization
+// @Result: TypeMismatch @ 6:15
+
+class type59 {
+    
+    method testm() {
+        local a: int[] = 0;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component if01 {
+    
+    field res_01: int = choose(true,  -1, 1);
+    field res_02: int = choose(false, -1, 1);
+    field res_03: int = choose(true,  241, 100);
+    field res_04: int = choose(false, 241, 100);
+    field res_05: int = choose(true,  -100, 6);
+    field res_06: int = choose(false, -100, 6);
+
+    method choose(c: bool, a: int, b: int): int {
+\treturn c ? a : b;
+    }
+}
+
+/* 
+heap {
+    record #0:6:if01 {
+        field res_01: int = int:-1;
+        field res_02: int = int:1;
+        field res_03: int = int:241;
+        field res_04: int = int:100;
+        field res_05: int = int:-100;
+        field res_06: int = int:6;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=NullCheckException, 3=NullCheckException, 4=42
+
+class rtex_null07_obj {
+    field baz: int;
+}
+
+component rtex_null07 {
+    field foo: rtex_null07_obj;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) foo.baz = 13;
+\tif ( arg == 2 ) foo.baz = 15;
+\tif ( arg == 3 ) foo.baz = 17;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: cannot declare duplicate fields
+// @Result: ExpectedVarType @ 6:17
+
+class field8 {
+    field testf: field8c;
+}
+
+component field8c {
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class local01 {
+  method m() {
+     local f2: type<X>;
+  }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=55, 5=42
+
+class this02_1 {
+    field foo: int;
+    field th: this02_1 = this;
+
+    constructor(i: int) {
+\tfoo = i;
+    }
+    method getf(): int {
+\tif ( th == this ) return this.foo;
+\telse return 55;
+    }
+}
+
+component this02 {
+    field a: this02_1 = new this02_1(11);
+    field b: this02_1 = new this02_1(21);
+    field c: this02_1 = new this02_1(31);
+    field d: this02_1;
+
+    constructor() {
+\td = new this02_1(57);
+\td.th = null;
+    }\t
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.getf();
+\tif ( arg == 2 ) return b.getf();
+\tif ( arg == 3 ) return c.getf();
+\tif ( arg == 4 ) return d.getf();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking of operators
+// @Result: TypeMismatch @ 6:32
+
+class type_func11 {
+  field f: function(bool) = g;
+  method g(a: int) { }
+}
+"
+"program HelloWorld {
+    entrypoint main = HelloWorld.main;
+}
+
+component HelloWorld {
+    method main(a: int, b: int, e: int): int {
+    \tlocal c = a * 34;
+\t\tlocal d: int;
+\t\tswitch(c + b) {
+\t\t\tcase (20)
+\t\t\t\treturn 1;
+\t\t\tcase (-100)
+\t\t\t\treturn 3;
+\t\t}
+\t\t
+\t\tfor(d = 0; d < 100; d++) {
+\t\t\tif(b + d == fun(e))
+\t\t\t\treturn d + 4;
+\t\t}
+\t\t
+\t\tif(e > 10000 and b < 10000) {
+\t\t\treturn 10000;
+\t\t} else {
+\t\t\tif(e + b < 999)
+\t\t\t\treturn 9999;
+\t\t\telse
+\t\t\t\treturn 9998;
+\t\t}
+\t}
+\t
+\tmethod fun(a: int): int {
+\t\tlocal b = a - 1000;
+\t\treturn b - 3;  
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shorcutting of conditionals)
+// @Result: PASS
+
+class for_short_init03 {
+    
+    method testm(p: bool) {
+        local foo: bool;
+        for ( ; p or (foo = p); ) ;
+        testm(foo);
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 241
+
+component if02a {
+    
+    // choose(true,  241, 100) => 241
+    // choose(false, 241, 100) => 100
+    method main(arg: int): int {
+\treturn choose(true, 241, 100);
+    }
+
+    method choose(c: bool, a: int, b: int): int {
+\tif ( c ) return a;
+        return b;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: separate test cases have separate name spaces
+// @Result: PASS
+
+component same01 {
+}
+"
+"// @Harness: v2-init
+// @Test: divide by zero exception during initialization
+// @Result: DivideByZeroException @ 7:24
+
+component divzero02 {
+    field foo: int = 0;
+    field bar: int = 1 / foo;
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=0, 2=0, 3=42
+
+component default06a {
+    field foo: char;
+    field bar: char = foo;
+
+    method main(arg: int): char {
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn '*';
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: array index exceptions
+// @Result: BoundsCheckException @ 12:17
+
+component index07 {
+    field foo: int[] = new int[42];
+    field bar: int = baz();
+
+    method baz(): int {
+        local cntr: int;
+        for ( cntr = 41; cntr >= -1; cntr-- )
+\t    foo[cntr] = cntr;
+        return -4;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: UnresolvedType @ 5:15
+
+class scope13_a extends scope13_b<int> {
+  method m(x: X) { }
+}
+
+class scope13_b<X> {
+}
+"
+"// @Harness: v2-seman
+// @Test: switch statements should have non-overlapping values
+// @Result: DuplicateCase @ 7:24
+
+class switch06 {
+    
+    method testm(a: int) {
+        switch ( a ) {
+            case ( 0, 1, 2, 3, 0 ) ;
+        }
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: compile-time constants for primitive types
+// @Result: PASS
+
+component const_char01 {
+    field a: char = \'a\';
+    field b: char = \'b\';
+    field c: char = \'\
+\';
+    field d: char = \'\\t\';
+    field e: char = \'\\b\';
+    field f: char = \'\\r\';
+    field g: char = \'\\\'\';
+    field h: char = \'""\';
+    field i: char = \'\\377\';
+    field j: char = \'\\\\\';
+    field k: char = \' \';
+    field l: char = \' \';
+    field m: char = \' \';
+    field n: char = \' \';
+}
+
+/* 
+heap {
+    record #0:14:const_char01 {
+        field a: char = char:97;
+        field b: char = char:98;
+        field c: char = char:10;
+        field d: char = char:9;
+        field e: char = char:8;
+        field f: char = char:13;
+        field g: char = char:39;
+        field h: char = char:34;
+        field i: char = char:255;
+        field j: char = char:92;
+        field k: char = char:32;
+        field l: char = char:32;
+        field m: char = char:32;
+        field n: char = char:32;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: TypeCast operation
+// @Result: PASS
+
+class cast04_01 {
+    field foo: cast04_01 = null :: cast04_01;
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component for10 {
+    
+    method main(max: int): int {
+\tlocal i: int, cumul = 0, loop: int;
+        for ( loop = 1; loop < 2; loop++ ) {
+            for ( i = 1; ; cumul += i, i++ ) {
+\t        if ( i > max ) break;
+\t        else continue;
+\t    }
+\t}
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component switch10 {
+    field foo: int = ds(10);
+
+    method ds(v: int): int {
+\tswitch ( v ) {
+\t    case ( 0 ) return 10;
+\t    case ( 1 ) return 11;
+\t    case ( 2 ) return 12;
+\t    case ( 3 ) return 13;
+\t    case ( 4, 5 ) return 15;
+\t    case ( 7, 8, 9 ) return 20;
+\t    default return -1;
+        }
+    }
+}
+
+/* 
+heap {
+    record #0:1:switch10 {
+        field foo: int = int:-1;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh05_a<X> extends inh05_b<X> {
+}
+
+class inh05_b<Y> {
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of indexing multidimensional arrays""
+// @Result: PASS
+
+class array12 {
+    
+    method testm(a: int[][]): int {
+        return a[0][0];
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: uses of ""this""
+// @Result: PASS
+
+class this06b_obj {
+    field foo: bool = equals(this);
+    method equals(o: this06b_obj): bool { return o == this; }
+}
+
+component this06b {
+    field foo: this06b_obj = new this06b_obj();
+}
+
+/* 
+heap {
+    record #0:1:this06b {
+        field foo: this06b_obj = #1:this06b_obj;
+    }
+    record #1:1:this06b_obj {
+        field foo: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=51, 5=61, 6=42
+
+class virtual07a_1 {
+    method val(): int { return 11; }
+}
+
+class virtual07a_2 extends virtual07a_1 {
+    method val(): int { return 21; }
+}
+
+class virtual07a_3 extends virtual07a_1 {
+    method val(): int { return 31; }
+}
+
+class virtual07a_4 {
+    method val(): int { return 51; }
+}
+
+class virtual07a_5 extends virtual07a_4 {
+    method val(): int { return 61; }
+}
+
+component virtual07a {
+    field a: virtual07a_1 = new virtual07a_1();
+    field b: virtual07a_1 = new virtual07a_2();
+    field c: virtual07a_1 = new virtual07a_3();
+    field d: virtual07a_4 = new virtual07a_4();
+    field e: virtual07a_4 = new virtual07a_5();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val();
+\tif ( arg == 2 ) return b.val();
+\tif ( arg == 3 ) return c.val();
+\tif ( arg == 4 ) return d.val();
+\tif ( arg == 5 ) return e.val();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_id01 {
+    method test() {
+\tlocal x = id(0);
+    }
+    method id<X>(x: X): X {
+\treturn x;\t
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 7:40
+
+class type_res16 {
+    field bar: type_res16;
+    field foo: type_res16 = new unknown();
+}
+"
+"/**
+ * Queue implementation. Implements a buffer of fixed size for storing values of a 
+ * particular type. Attempts to enqueue more than N values return false, and 
+ * attempts to dequeue when the queue is empty return the null value.
+ *
+ * @author Ryan Hall, Ben L. Titzer
+ */
+class Queue<T> {
+\tfield none: T;
+\tfield data: T[];
+\tfield head: int;
+\tfield used: int;
+
+\tconstructor(size: int) {
+\t\tdata = new T[size];
+\t\thead = 0;
+\t\tused = 0;
+\t}
+
+\tmethod enqueue(c: T): boolean {
+\t\tif ( full() ) return false;
+\t\tdata[wrap(head + used)] = c;
+\t\tused++;
+\t\treturn true;
+\t}
+
+\tmethod dequeue(): T {
+\t\tif ( empty() ) return none;
+\t\tlocal c = data[head];
+\t\thead = wrap(head + 1);
+\t\tused--;
+\t\treturn c;
+\t}
+
+\tmethod enqueueArray(buf: T[], i: int, len: int): int {
+\t\tlocal pos = wrap(head + used);
+\t\tlocal cnt = data.length - used;
+\t\tif ( len < cnt ) cnt = len;
+\t\tused = used + cnt;
+\t\tif ( pos < head ) {
+\t\t\tArrayUtil.copy(buf, data, i, pos, cnt);
+\t\t\treturn cnt;
+\t\t} else if ( pos > head ) {
+\t\t\tlocal p = ArrayUtil.copyPartial(buf, data, i, pos, cnt);
+\t\t\tArrayUtil.copy(buf, data, i + p, 0, cnt - p);
+\t\t\treturn cnt;
+\t\t}
+\t\treturn 0;
+\t}
+
+\tmethod dequeueArray(buf: T[], i: int, len: int): int {
+\t\tlocal max = wrap(head + used);
+\t\tlocal cnt = used;
+\t\tif ( len < cnt ) cnt = len;
+\t\tused -= cnt;
+\t\tif ( head < max ) {
+\t\t\tArrayUtil.copy(data, buf, head, i, cnt);
+\t\t\thead += cnt;
+\t\t\treturn cnt;
+\t\t} else if ( head > max ) {
+\t\t\tlocal p = ArrayUtil.copyPartial(data, buf, head, i, cnt);
+\t\t\tArrayUtil.copy(data, buf, 0, i + p, cnt - p);
+\t\t\thead = cnt - p;
+\t\t\treturn cnt;
+\t\t}
+\t\treturn 0;
+\t}
+
+\tmethod size(): int {
+\t\treturn used;
+\t}
+
+\tmethod full(): boolean {
+\t\treturn used == data.length;
+\t}
+
+\tmethod empty(): boolean {
+\t\treturn used == 0;
+\t}
+
+\tprivate method wrap(i: int): int {
+\t\tif ( i >= data.length ) return i - data.length;
+\t\treturn i;
+\t}
+}
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=42, 1=11, 2=21, 3=48, 4=66, 5=42
+
+class W<T> {
+    field val: T;
+    constructor(v: T) {
+        val = v;
+    }
+}
+
+component ptex_wrap04 {
+
+    field a: W<int> = new W<int>(11);
+    field b: W<int> = new W<int>(21);
+    field c: W<8> = new W<8>(0x30);
+    field d: W<8> = new W<8>(0x42);
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val;
+\tif ( arg == 2 ) return b.val;
+\tif ( arg == 3 ) return c.val :: int;
+\tif ( arg == 4 ) return d.val :: int;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_raw01 {
+    field x: int;
+    field a: 32 = x;
+    field b: 48 = -109;
+    field c: 64 = 10909109;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class assign11<X> {
+   field f: X;
+
+   method m(x: X[]) {
+      x[0] = f;
+      f = x[0];
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component for02 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        for ( ; i <= max; i++ ) cumul += i;
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:for02 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: initialization interpreter > raw types > and operator
+// @Result: 0=1, 1=2, 3=8, 4=16, 7=128, 8=0
+
+component raw_index11 {
+
+    method main(arg: int): 8 {
+\tlocal x: 8 = 0x00;
+\tx[arg] = 0b1;
+\treturn x;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_raw04 {
+    
+    method testm() {
+        local a = { 0xafa, 0x0f };
+        local b: 12[] = a;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: compile-time constants for primitive types
+// @Result: PASS
+
+component char_int02 {
+    field a: bool = \'a\' == 97;
+    field b: bool = \'b\' == 98;
+    field c: bool = \'\
+\' == 10;
+    field d: bool = \'\\t\' == 9;
+    field e: bool = \'\\b\' == 8;
+    field f: bool = \'\\r\' == 13;
+    field g: bool = \'\\\'\' == 39;
+    field h: bool = \'""\' == 34;
+    field i: bool = \'\\377\' == 255;
+    field j: bool = \'\\\\\' == 92;
+    field k: bool = \' \' == 32;
+}
+
+/* 
+heap {
+    record #0:11:char_int02 {
+        field a: bool = bool:true;
+        field b: bool = bool:true;
+        field c: bool = bool:true;
+        field d: bool = bool:true;
+        field e: bool = bool:true;
+        field f: bool = bool:true;
+        field g: bool = bool:true;
+        field h: bool = bool:true;
+        field i: bool = bool:true;
+        field j: bool = bool:true;
+        field k: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: concat and bit operators
+// @Result: 0=15, 1=7, 2=4, 3=8, 4=1, 5=15, 6=14, 7=5, 8=15
+
+component raw_flip04 {
+
+    method flip(a: 4): 4 {
+\treturn a[0] # a[1] # a[2] # a[3];
+    }
+
+    method main(arg: int): 4 {
+\tif ( arg == 1 ) return flip(0xe);
+\tif ( arg == 2 ) return flip(0x2);
+\tif ( arg == 3 ) return flip(0x1);
+\tif ( arg == 4 ) return flip(0x8);
+\tif ( arg == 5 ) return flip(0xf);
+\tif ( arg == 6 ) return flip(0x7);
+\tif ( arg == 7 ) return flip(0xa);
+\treturn 0xF;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component for09 {
+    
+    method main(max: int): int {
+\tlocal i: int, cumul: int;
+        for ( i = 1, cumul = 0; ; cumul += i, i++ ) {
+\t    if ( i > max ) break;
+\t    else continue;
+\t}
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+class ander {
+    field a: bool; // true if A() evaluated
+    field b: bool; // true if B() evaluated
+    field R: bool;
+
+    method AND(v1: bool, v2: bool) {
+\tR = A(v1) and B(v2);
+    }
+
+    method A(v: bool): bool {
+\ta = true;
+\treturn v;
+    }
+
+    method B(v: bool): bool {
+\tb = true;
+\treturn v;
+    }
+}
+
+component logical06 {
+    field res_01: ander = new ander();
+    field res_02: ander = new ander();
+    field res_03: ander = new ander();
+    field res_04: ander = new ander();
+
+    constructor() {
+\tres_01.AND(true, false);
+\tres_02.AND(true, true);
+\tres_03.AND(false, true);
+\tres_04.AND(false, false);
+    }
+
+}
+
+/* 
+heap {
+    record #0:4:logical06 {
+\tfield res_01: ander = #1:ander;
+\tfield res_02: ander = #2:ander;
+\tfield res_03: ander = #3:ander;
+\tfield res_04: ander = #4:ander;
+    }
+    record #1:3: ander {
+\tfield a: bool = bool:true;
+\tfield b: bool = bool:true;
+\tfield R: bool = bool:false;
+    }
+    record #2:3: ander {
+\tfield a: bool = bool:true;
+\tfield b: bool = bool:true;
+\tfield R: bool = bool:true;
+    }
+    record #3:3: ander {
+\tfield a: bool = bool:true;
+\tfield b: bool = bool:false;
+\tfield R: bool = bool:false;
+    }
+    record #4:3: ander {
+\tfield a: bool = bool:true;
+\tfield b: bool = bool:false;
+\tfield R: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component for05 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i: int, cumul = 0;
+        for ( i = 1; ; ) {
+\t    cumul += i++;
+\t    if ( i > max ) return cumul;
+\t}
+    }
+}
+
+/* 
+heap {
+    record #0:6:for05 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: Virgil constructors
+// @Result: TypeMismatch @ 13:34
+
+class constructor08 {
+
+    field f: int;
+
+    constructor(a: int) {
+        f = a;
+    }
+
+    method testm(): constructor08 {
+        return new constructor08(false);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: method resolution
+// @Result: UnresolvedIdentifier @ 11:9
+
+class method_res02_a {
+    
+    method foo() {
+    }
+}
+class method_res02_b extends method_res02_a {
+    
+    method testm() {
+        unres();
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:18
+
+class meth10 {
+   method m() { };
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:23
+
+class meth04 {
+    method m(a: int, b);
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class array4 {
+  method m1() {
+    {
+      local a: type[];
+      local b: type[][];
+      local c: type[][][];
+    }
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component prepost18 {
+    field foo: int[];
+    field bar: int = ++na()[0];
+    
+    // this method should only be called once
+    method na(): int[] {
+        local arr = { 1 };
+\treturn foo = arr;
+    }
+}
+
+/* 
+heap {
+    record #0:2:prepost18 {
+        field foo: int[] = #1:int[1];
+        field bar: int = int:2;
+    }
+    record #1:1:int[1] {
+\tfield 0: int = int:2;
+    }
+}*/
+"
+"/**
+ * ADC (analog to digital) conversion driver.
+ * @author Ryan Hall, Akop Palyan
+ * @ modified Xiaoli Gong Feb 20 ,2009
+ * 1. disable the ADC after convert is over
+ * 2. check if there is a convert in processing
+ */
+component ADC {
+\tfield ADEN: 8 = 0x80;
+\tfield ADSC: 8 = 0x40;
+\tfield ADFR: 8 = 0x20;
+\tfield ADIF: 8 = 0x10;
+\tfield ADIE: 8 = 0x08;
+\tfield ADPS2: 8 = 0x04;
+\tfield ADPS1: 8 = 0x02;
+\tfield ADPS0: 8 = 0x01;
+
+\tfield convFunc: function(10) = none;
+\tfield busy:boolean = false;
+\tmethod enable() {
+\t\t// enable ADC by setting ADEN bit
+\t\tdevice.ADCSRA = device.ADCSRA | ADEN;
+\t\t//device.ADCSRA = device.ADCSRA | ADFR;
+\t\tdevice.ADCSRA = device.ADCSRA | ADIE;
+\t\tdevice.ADMUX = 0x0;
+\t}
+
+\tmethod disable() {
+\t\twhile(busy);
+\t\tbusy = false;
+\t\t// disable ADC by clearing ADEN bit
+\t\tdevice.ADCSRA = device.ADCSRA & ~ADEN;
+\t}
+
+\tmethod startConv(channel: int, freeRunning: boolean) {
+
+\t\tif(busy) return;
+\t\t// start ADC conversion
+\t\tenable();
+\t\tdevice.ADMUX = channel :: 8;
+\t\tdevice.ADCSRA = device.ADCSRA | ADSC;
+\t\tbusy=true;
+\t}
+
+\tmethod setConvFunc(f: function(10)) {
+\t\tconvFunc = f;
+\t}
+
+\tmethod setPrescaler(val: 3) {
+\t\tdevice.ADCSRA = device.ADCSRA & 0xf8 | val;
+\t}
+
+\tmethod convHandler() {
+\t\tlocal low: 8 = device.ADCL;
+\t\tlocal high: 8 = device.ADCH;
+\t\tlocal value: 10 = (high # low) :: 10;
+\t\tbusy=false;
+\t\tdisable();////clean the convert in processing
+\t\tconvFunc(value);
+\t}
+
+\tmethod none(value: 10) { }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42, 5=11, 6=21, 7=31, 8=42
+
+class delegate05_a {
+    method foo(): int { return 11; }
+    method bar(): int { return 21; }
+    method baz(): int { return 31; }
+}
+
+component delegate05 {
+    field am: function():int = new delegate05_a().foo;
+    field bm: function():int = new delegate05_a().bar;
+    field cm: function():int = new delegate05_a().baz;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return am();
+\tif ( arg == 2 ) return bm();
+\tif ( arg == 3 ) return cm();
+
+\tlocal m = m42;
+\tif ( arg == 5 ) m = am;
+\tif ( arg == 6 ) m = bm;
+\tif ( arg == 7 ) m = cm;
+\treturn m();
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive assignments
+// @Result: TypeMismatch @ 7:11
+
+class type09 {
+    
+    method testm() {
+        local foo: int;
+        foo = false;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component field05 {
+    field foo: char[] = ""hello"";
+}
+
+/* 
+heap {
+    record #0:1:field05 {
+        field foo: char[] = #1:char[5];
+    }
+    record #1:5:char[5] {
+        field 0: char = char:104;
+        field 1: char = char:101;
+        field 2: char = char:108;
+        field 3: char = char:108;
+        field 4: char = char:111;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > bit access operations
+// @Result: PASS
+
+class raw_index05 {
+    method m(a: 8, i: int, j: int) {
+\ta[i] = a[j];
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization of arrays of raws
+// @Result: 0=31, 1=15, 2=2, 3=28, 4=31
+
+component array_raw05 {
+    field a: 5[] = { 0xf, 0b10, 0b11100 };
+    field av: 5  = a[0];
+
+    method main(arg: int): 5 {
+\tif ( arg == 1 ) return a[0];
+\tif ( arg == 2 ) return a[1];
+\tif ( arg == 3 ) return a[2];
+\treturn 0b11111;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component for04 {
+    
+    method main(max: int): int {
+\tlocal i: int, cumul = 0;
+        for ( i = 1; ; i++ ) {
+\t    cumul += i;
+\t    if ( i >= max ) return cumul;
+\t}
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: statements
+// @Result: NotAStatement @ 6:5
+
+class stmt04 {
+    
+    method testm() {
+        0 + 1;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=0
+
+component raw_flip01 {
+
+    method flip(a: 16): 16 {
+\treturn (a :: 8) # ((a >> 8) :: 8);
+    }
+
+    method flip2(x: 16): bool {
+\treturn flip(flip(x)) == x;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return flip2(0x0ffe);
+\tif ( arg == 2 ) return flip2(0x0002);
+\tif ( arg == 3 ) return flip2(0x0001);
+\tif ( arg == 4 ) return flip2(0x8000);
+\tif ( arg == 5 ) return flip2(0xf007);
+\tif ( arg == 6 ) return flip2(0x8877);
+\tif ( arg == 7 ) return flip2(0xaa01);
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 11
+
+class virtual06b_1 {
+    method val() { virtual06b.R = 11; }
+}
+
+class virtual06b_2 extends virtual06b_1 {
+}
+
+class virtual06b_3 extends virtual06b_2 {
+    method val() { virtual06b.R = 31; }
+}
+
+component virtual06b {
+    field a: virtual06b_1 = new virtual06b_1();
+    field b: virtual06b_1 = new virtual06b_2();
+    field c: virtual06b_1 = new virtual06b_3();
+
+    field R: int;
+
+    method main(arg: int): int {
+\tb.val();
+\treturn R;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: array rtex_index exceptions
+// @Result: 0=42, 1=0, 2=1, 3=15, 4=40, 5=41, 6=BoundsCheckException, 7=42
+
+component rtex_index06 {
+    field foo: int[] = new int[42];
+
+    method scan(m: int): int {
+        local cntr: int;
+        for ( cntr = 0; cntr <= m; cntr++ ) foo[cntr] = cntr;
+        return m;
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return scan(0);
+\tif ( arg == 2 ) return scan(1);
+\tif ( arg == 3 ) return scan(15);
+\tif ( arg == 4 ) return scan(40);
+\tif ( arg == 5 ) return scan(41);
+\tif ( arg == 6 ) return scan(42);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: PASS
+
+class field_res14 {
+    private field testf: int;
+    
+    method testm() {
+        testf = 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: type check exceptions (i.e. dynamic casts)
+// @Result: 0=41, 1=41, 2=41, 3=41, 4=41
+
+class rtex_type06_a {
+    field foo: int;
+
+    constructor(f: int) { 
+\tfoo = f; 
+    }
+}
+
+class rtex_type06_b extends rtex_type06_a {
+    constructor(): super(11) { }
+}
+
+class rtex_type06_c extends rtex_type06_a {
+    constructor(): super(12) { }
+}
+
+component rtex_type06 {
+
+    method main(arg: int): int {
+\tlocal x: rtex_type06_a = null;
+\tlocal r: int = 41;
+
+\tif ( arg == 1 ) x = x :: rtex_type06_a;
+\tif ( arg == 2 ) x = x :: rtex_type06_b;
+\tif ( arg == 3 ) x = x :: rtex_type06_c;
+
+\tif ( x != null ) return x.foo;
+\telse return r;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: compound assignment operators
+// @Result: 0=11, 1=13, 2=9, 3=22, 4=5, 5=3, 6=11
+
+component cmpassn20 {
+
+    field foo: int[] = { 11, 42 };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) foo[0] += 2;
+\tif ( arg == 2 ) foo[0] -= 2;
+\tif ( arg == 3 ) foo[0] *= 2;
+\tif ( arg == 4 ) foo[0] /= 2;
+\tif ( arg == 5 ) foo[0] %= 4;
+\treturn foo[0];
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: BuiltinRedefined @ 5:7
+
+class int {
+    field foo : int;
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=14, 3=15, 4=42
+
+class array29_obj {
+    field foo: int;
+    constructor(i: int) { foo = i; }
+}
+
+component array29 {
+    field i: array29_obj = new array29_obj(13);
+    field j: array29_obj = new array29_obj(14);
+    field k: array29_obj = new array29_obj(15);
+    field m: array29_obj = new array29_obj(42);
+
+    field a: array29_obj[] =  { i, j, k };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return getf(a[0]);
+\tif ( arg == 2 ) return getf(a[1]);
+\tif ( arg == 3 ) return getf(a[2]);
+\treturn 42;
+    }
+
+    method getf(o: array29_obj): int {
+\treturn o.foo;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=6, 0=0
+
+class prepost11_obj {
+    field foo: int = 6;
+}
+
+component prepost11 {
+    field foo: prepost11_obj = new prepost11_obj();
+
+    method main(arg: int): int {
+\tfoo.foo = foo.foo++;
+\tif ( arg == 1 ) return foo.foo;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class char_int05 {
+    field a: int;
+    field b: char = m(a :: char);
+    method m<T>(x: T): T { return x; }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_char04 {
+    method test(c: char) {
+\tlocal x: int = c;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class cast01b {
+   method m() {
+      local y = x :: (Type<X>);
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: type check exceptions (i.e. dynamic casts)
+// @Result: 0=11, 1=41, 2=41, 3=41, 4=11
+
+class rtex_type07_a {
+    field foo: int;
+
+    constructor(f: int) { 
+\tfoo = f; 
+    }
+}
+
+class rtex_type07_b extends rtex_type07_a {
+    constructor(): super(11) { }
+}
+
+class rtex_type07_c extends rtex_type07_a {
+    constructor(): super(12) { }
+}
+
+component rtex_type07 {
+
+    field a: rtex_type07_a = new rtex_type07_a(11);
+
+    method main(arg: int): int {
+\tlocal x: rtex_type07_a = a;
+\tlocal y: rtex_type07_a = null;
+\tlocal r: int = 41;
+
+\tif ( arg == 1 ) x = y :: rtex_type07_a;
+\tif ( arg == 2 ) x = y :: rtex_type07_b;
+\tif ( arg == 3 ) x = y :: rtex_type07_c;
+
+\tif ( x != null ) return x.foo;
+\telse return r;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > binary constants
+// @Result: TypeMismatch @ 6:18
+
+class raw_bin10 {
+    field a: 16 = 0b01010010010101010;
+}
+"
+"// @Harness: v2-seman
+// @Test: Virgil constructors
+// @Result: PASS
+
+class constructor03 {
+
+    field f: int;
+
+    constructor() {
+        f = 1;
+    }
+
+    method testm(): constructor03 {
+        return new constructor03();
+    }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of elements of multidimensional arrays""
+// @Result: TypeMismatch @ 6:12
+
+class array15 {
+    
+    method testm(a: int[][]) {
+        a[0][0] = false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 12:5
+
+class unreach21 {
+    
+    method testm() {
+        switch ( 0 ) {
+            case ( 0 ) {
+                return;
+            }
+            case ( 1 ) {
+                return;
+            }
+            case ( 2 ) {
+                return;
+            }
+            default {
+                return;
+            }
+        }
+        testm();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component while07 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( true ) {
+\t    cumul += i++;
+\t    if ( i <= max ) continue;
+\t    break;
+\t}
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:while07 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"/*
+ * SPI (Serial peripheral interface) driver.
+ * @author Akop Palyan
+ * @ modified by Xiaoli Gong
+ * @ a hook function is needed to catch the interrupt of the SPI
+ * @ Dec 31,2008
+ * @ add a work mode selection and keep the old machinism work 
+ * @ Feb 23, 2009
+ */
+
+component SPI {
+\t// SPI Control Register
+\tfield SPIE: 3 = 07;
+\tfield SPE:  3 = 06;
+\tfield DORD: 3 = 05;
+\tfield MSTR: 3 = 04;
+\tfield CPOL: 3 = 03;
+\tfield CPHA: 3 = 02;
+\tfield SPR:  3 = 01;
+
+\t// SPI Status Register
+\tfield SPIF:  3 = 07;
+\tfield WCOL:  3 = 06;
+\tfield SPI2X: 3 = 00;
+
+\tfield t_queue: Queue<char> = new Queue<char>(10);
+\tfield r_queue: Queue<char> = new Queue<char>(10);
+
+\tfield transmitting: boolean;
+\tfield master: boolean = false;
+\tfield OutgoingByte:8 = 0x00;
+
+\tfield callback: function(8) = none;
+
+\tfield sendperByte:boolean = true;
+\tfield sendbyQueue:boolean = false;
+\tfield workMode: boolean= sendbyQueue;
+
+\tmethod setWorkMode(mode: boolean) {
+\t\tworkMode = mode;
+\t\tif (mode == sendbyQueue) {
+\t\t\tclrCallback();
+\t\t}
+\t}
+
+\tmethod startMaster() {
+\t\ttransmitting = false;
+\t\tmaster = true;
+
+\t\tdevice.SPCR[SPE::int] = 0b1;
+\t\tdevice.SPCR[MSTR::int] = 0b1;
+\t\tdevice.SPCR[SPR::int] = 0b1;
+\t\tdevice.SPCR[SPIE::int] = 0b1;
+\t\tMica2.portB.setDirection(0x6);
+\t }
+
+\tmethod startSlave() {
+\t\ttransmitting = false;
+\t\tmaster = false;
+
+\t\tdevice.DDRB[1] = 0b0; /////spi sck input
+\t\tdevice.DDRB[2] = 0b0; /////mosi input
+\t\tdevice.DDRB[3] = 0B0; /////miso input
+
+\t\tdevice.SPCR[CPOL::int] = 0b0;
+\t\tdevice.SPCR[CPHA::int] = 0b0;
+\t\tdevice.SPCR[SPIE::int] = 0b1;
+\t\tdevice.SPCR[SPE::int] = 0b1;\t
+\t\t// Mica2.portB.setDirection(0x8);
+\t}
+
+\tmethod transmitByte(data:8) {
+\t\tOutgoingByte = data;
+\t}
+\tmethod transmit() {
+\t\tif (!transmitting) {
+\t\t\tdevice.SPDR = t_queue.dequeue();
+\t\t\ttransmitting = true;
+\t\t}
+\t}
+
+\tmethod interruptHandler() {
+\t\tlocal temp:8;
+\t\ttemp = device.SPDR::8;
+\t\tif (workMode == sendbyQueue) {
+\t\t\tr_queue.enqueue(temp::char);
+\t\t\tif (!t_queue.empty()) {
+\t\t\t\tdevice.SPDR = t_queue.dequeue();
+\t\t\t} else if (master) {
+\t\t\t\ttransmitting = false;
+\t\t\t}
+\t\t}
+\t\tif (workMode == sendperByte) {
+\t\t\tdevice.SPDR = OutgoingByte;
+\t\t\tif (master) {
+\t\t\t\ttransmitting = false;
+\t\t\t}
+\t\t\tcallback(temp);
+\t\t}
+\t}
+\tmethod enableIntr() {
+\t\tdevice.SPCR = 0xC0;
+\t\tdevice.DDRB[0] = 0b0;
+\t\tPower.adjustPower();
+\t}
+
+\tmethod disableIntr() {
+\t\tdevice.SPCR[7] = 0b0;
+\t\tdevice.DDRB[0] = 0b1;
+\t\tdevice.PORTB[0] = 0b0;
+\t\tPower.adjustPower();
+\t}
+
+\tmethod rxMode() {
+\t\tdevice.DDRB[2] = 0b0; /////mosi input
+\t\tdevice.DDRB[3] = 0B0; /////miso input
+\t}
+\tmethod txMode() {
+\t\tdevice.DDRB[3] = 0B1; /////miso output
+\t\tdevice.DDRB[2] = 0b1; /////mosi output
+\t}
+
+
+\tmethod writeByte(buffer: 8): boolean {
+\t\tlocal nenqueued: int = 0;
+\t\tlocal result = false;
+\t\tlocal mask = MCU.disable();
+\t\tif (workMode != sendperByte) return result;
+\t\tresult = true;
+\t\ttransmitByte(buffer);
+\t\tMCU.restore(mask);
+\t\treturn result;
+\t}
+\tmethod write(buffer: char[], index: int, nbytes: int): int {
+\t\tlocal nenqueued: int = 0;
+\t\tlocal mask = MCU.disable();
+\t\twhile (nbytes > 0 and t_queue.enqueue(buffer[index + nenqueued])) {
+\t\t\tnbytes = nbytes - 1;
+\t\t\tnenqueued = nenqueued + 1;
+\t\t}
+\t\tif (master and !t_queue.empty()) transmit();
+\t\tMCU.restore(mask);
+\t\treturn nenqueued;
+\t}
+
+\tmethod read(buffer: char[], index: int, nbytes: int): int {
+\t\tlocal ndequeued: int = 0;
+\t\tlocal mask = MCU.disable();
+\t\twhile (nbytes > 0 and !r_queue.empty()) {
+\t\t\tbuffer[index + ndequeued] = r_queue.dequeue();
+\t\t\tnbytes = nbytes - 1;
+\t\t\tndequeued = ndequeued + 1;
+\t\t}
+\t\tMCU.restore(mask);
+\t\treturn ndequeued;
+\t}
+
+\tmethod none(inputvalue: 8) {
+\t}
+
+\tmethod setCallback(f: function(8)) {
+\t\tcallback = f;
+\t}
+
+\tmethod clrCallback(){
+\t\tcallback=none;
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class List<X> {
+    method add(x: X) {
+    }
+}
+
+component mp_list05 {
+    method test() {
+\tlocal x = makeList(0);
+    }
+    method makeList<T>(a: T): List<T> {
+\treturn new List<T>();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_id02 {
+    method test() {
+\tlocal x: int = id(0);
+    }
+    method id<X>(x: X): X {
+\treturn x;\t
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: method resolution
+// @Result: PASS
+
+class method_res09 {
+    
+    method foo() {
+    }
+    
+    method testm() {
+        foo();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int versus bool
+// @Result: TypeMismatch @ 6:17
+
+class type11 {
+    
+    method testm(a: int) {
+        local f: bool = a;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_array06 {
+    method test() {
+\tset0(null, 0);
+    }
+    method set0<X>(a: X[], b: X) {
+\ta[0] = b;\t
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=6, 2=6, 3=0
+
+class cmpassn08_obj {
+    field foo: int = 8;
+    field bar: int;
+}
+
+component cmpassn08 {
+    field foo: cmpassn08_obj = new cmpassn08_obj();
+
+    method main(arg: int): int {
+\tfoo.bar = (foo.foo -= 2);
+\tif ( arg == 1 ) return foo.foo;
+\tif ( arg == 2 ) return foo.bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component cmpassn06 {
+    field foo: 16 = 0x4;
+    field bar: 16 = foo >>= 1;
+}
+
+/* 
+heap {
+    record #0:2:cmpassn06 {
+        field foo: int = raw.16:0x2;
+        field bar: int = raw.16:0x2;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class assign07<X> {
+   field f: assign07<X>;
+   method m(x: assign07<X>) {
+      f = x;
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: switch statements should have compile-time computable values
+// @Result: NotComputable @ 7:15
+
+class switch03 {
+    
+    method testm(a: int) {
+        switch ( a ) {
+            case ( a ) ;
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+
+  method first(): X {
+    return a;
+  }
+
+  method second(): Y {
+    return b;
+  }
+}
+
+component Client {
+  method test() {
+    local p = makePair(0, false);
+  }
+
+  method makePair<T, U>(x: T, y: U): Pair<T, U> {
+    local v = new Pair<T, U>();
+    v.a = x;
+    v.b = y;
+    return v;
+  }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of operations)
+// @Result: VariableNotInitialized @ 7:11
+
+class order_init12 {
+    
+    method testm(a: order_init12): int {
+        local uninit: order_init12;
+        return uninit.testm(uninit = a);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: operation of instanceof construct
+// @Result: PASS
+
+class cast01_obj {
+}
+
+component cast01 {
+    field foo: cast01_obj;
+    field bar: cast01_obj = foo :: cast01_obj;
+}
+
+/* 
+heap {
+    record #0:2:cast01 {
+        field foo: cast01_obj = #null;
+        field bar: cast01_obj = #null;
+    }
+}*/
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component switch12 {
+    field foo: int;
+
+    constructor() {
+\tds(1);
+    }
+
+    method ds(v: int) {
+\tswitch ( v ) {
+\t    case ( 0 ) foo = 10;
+\t    case ( 2 ) foo = 13;
+\t    case ( 5, 8, 7 ) foo = 20;
+\t    case ( 1 ) foo = 11;
+\t    case ( 3, 4 ) foo = 15;
+\t    default foo = -1;
+        }
+    }
+}
+
+/* 
+heap {
+    record #0:1:switch12 {
+        field foo: int = int:11;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking of operators
+// @Result: PASS
+
+class type_null02 {
+  method testm(b: bool) {
+    b = testm == null;
+    b = null == testm;
+    b = testm != null;
+    b = null != testm;
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment options
+// @Result: PASS
+
+component prepost04 {
+    field foo: int = 6;
+    field bar: int = --foo;
+}
+
+/* 
+heap {
+    record #0:2:prepost04 {
+        field foo: int = int:5;
+        field bar: int = int:5;
+    }
+}*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr5 {
+  field foo: type = foo().bar;
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 5:3
+
+class type_res06 {
+    
+    method testm(): foo {
+        return 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=10, 2=13, 3=42
+
+class default02b_1 {
+    field foo: bool;
+    field bar: bool = !foo;
+}
+
+component default02b {
+    field baz: default02b_1 = new default02b_1();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return baz.foo ? 13 : 10;
+\tif ( arg == 2 ) return baz.bar ? 13 : 10;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg12_a {
+    method val(): int { return 1; }
+}
+
+class dg12_b extends dg12_a {
+    method val(): int { return 2; }
+}
+
+component dg12 {
+    field a: function():int = new dg12_a().val;
+    field b: function():int = new dg12_b().val;
+    field c: function():int = bar;
+    field av: int;
+    field bv: int;
+    field cv: int;
+    field dv: int;
+
+    constructor() {
+\tlocal f: function(): int;
+\tf = a; av = val(f);
+\tf = b; bv = val(f);
+\tf = c; cv = val(f);
+\tf = null; dv = val(f);
+    }
+
+    method val(f: function(): int): int {
+\tif ( f == a ) return 11;
+\tif ( f == b ) return 21;
+\tif ( f == c ) return 31;
+\tif ( f == null ) return 42;
+\treturn 77;
+    }
+    method bar(): int {
+\treturn 3;
+    }
+
+}
+
+/* 
+heap {
+    record #0:7:dg12 {
+        field a: function():int = [#1:dg12_a,dg12_a:val()];
+        field b: function():int = [#2:dg12_b,dg12_b:val()];
+        field c: function():int = [#0:dg12,dg12:bar()];
+        field av: int = int:11;
+        field bv: int = int:21;
+        field cv: int = int:31;
+        field dv: int = int:42;
+    }
+    record #1:0:dg12_a {
+    }
+    record #2:0:dg12_b {
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:13
+
+component try04 {
+   method m() {
+      local try: int;
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: TypeQuery operator
+// @Result: PASS
+
+class instof04b_a {
+}
+
+class instof04b_b extends instof04b_a {
+}
+
+component instof04b {
+    field foo: instof04b_a = new instof04b_b();
+    field bar: bool = foo <: instof04b_b;
+}
+
+/* 
+heap {
+    record #0:2:instof04b {
+        field foo: instof04b_a = #1:instof04b_b;
+        field bar: bool = bool:true;
+    }
+    record #1:0:instof04b_b {
+    }
+}*/
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=0, 1=1, 2=0, 3=1, 4=1, 5=0, 6=0, 7=0, 8=1, 9=1, 10=0
+
+component comp01 {
+
+    method op(a: int, b: int): bool {
+\treturn a < b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(1, 2);
+\tif ( arg == 2 ) return op(2, 1);
+\tif ( arg == 3 ) return op(-1, 1);
+\tif ( arg == 4 ) return op(-1, 0);
+\tif ( arg == 5 ) return op(-200, -200);
+\tif ( arg == 6 ) return op(65535, 65535);
+\tif ( arg == 7 ) return op(14, 13);
+\tif ( arg == 8 ) return op(13, 14);
+\tif ( arg == 9 ) return op(-1255, -255);
+\tif ( arg == 10 ) return op(1000000, 48576);
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42
+
+class private08_a {
+    private method val(): int { return 11; }
+}
+
+class private08_b extends private08_a {
+    method val(a: int): int { return 21; }
+}
+
+class private08_c extends private08_a {
+    method val(a: int): int { return 31; }
+}
+
+component private08 {
+    field b: function(int):int = new private08_b().val;
+    field c: function(int):int = new private08_c().val;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return 11;
+\tif ( arg == 2 ) return b(0);
+\tif ( arg == 3 ) return c(0);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_infer02 {
+    method first<X, Y>(a: X, b: Y): X {
+        return a;
+    }
+    method second<X, Y>(a: X, b: Y): Y {
+        return b;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+component logical04 {
+    field res_01: bool = op(true, true);
+    field res_02: bool = op(false, false);
+    field res_03: bool = op(true, false);
+    field res_04: bool = op(false, true);
+
+    method op(a: bool, b: bool): bool {
+\treturn a != b; // exclusive-or operation
+    }
+}
+
+/* 
+heap {
+    record #0:4:logical04 {
+        field res_01: bool = bool:false;
+        field res_02: bool = bool:false;
+        field res_03: bool = bool:true;
+        field res_04: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of array allocation expressions""
+// @Result: TypeMismatch @ 6:11
+
+class array07 {
+    
+    method testm(): int[] {
+        return new bool[2];
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: divide by zero exception during initialization
+// @Result: 0=71, 1=61, 2=43, 3=DivideByZeroException, 4=221
+
+component rtex_divzero04 {
+    field foo: int[] = { 4, 5, 9, 0 };
+
+    method main(arg: int): int {
+\tlocal r = 200;
+\tif ( (arg >= 0) and (arg < foo.length) ) r /= foo[arg];
+\treturn 21 + r;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: integers comparison operators
+// @Result: PASS
+
+component comp06 {
+    field res_01: bool = op(1, 2);
+    field res_02: bool = op(2, 1);
+    field res_03: bool = op(-1, 1);
+    field res_04: bool = op(-1, 0);
+    field res_05: bool = op(-200, -200);
+    field res_06: bool = op(65535, 65535);
+    field res_07: bool = op(14, 13);
+    field res_08: bool = op(13, 14);
+    field res_09: bool = op(-1255, -255);
+    field res_10: bool = op(1000000, 48576);
+
+    method op(a: int, b: int): bool {
+\treturn a != b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:comp06 {
+        field res_01: bool = bool:true;
+        field res_02: bool = bool:true;
+        field res_03: bool = bool:true;
+        field res_04: bool = bool:true;
+        field res_05: bool = bool:false;
+        field res_06: bool = bool:false;
+        field res_07: bool = bool:true;
+        field res_08: bool = bool:true;
+        field res_09: bool = bool:true;
+        field res_10: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42, 5=11, 6=21, 7=31, 8=42
+
+class delegate08_a {
+    method getf(): function(): int { return val; }
+    method val(): int { return 11; }
+}
+
+class delegate08_b extends delegate08_a {
+    method val(): int { return 21; }
+}
+
+class delegate08_c extends delegate08_a {
+    method val(): int { return 31; }
+}
+
+component delegate08 {
+    field am: function(): function(): int = new delegate08_a().getf;
+    field bm: function(): function(): int = new delegate08_b().getf;
+    field cm: function(): function(): int = new delegate08_c().getf;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return am()();
+\tif ( arg == 2 ) return bm()();
+\tif ( arg == 3 ) return cm()();
+
+        local m = gm42();
+\tif ( arg == 5 ) m = am();
+\tif ( arg == 6 ) m = bm();
+\tif ( arg == 7 ) m = cm();
+
+\treturn m();
+    }
+
+    method gm42(): function(): int {
+\treturn m42;
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class new2 {
+  field foo: type = new (function(): foo)[0];
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component while07 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( true ) {
+\t    cumul += i++;
+\t    if ( i <= max ) continue;
+\t    break;
+\t}
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=6, 2=6, 3=1, 4=0
+
+class cmpassn14_obj {
+    field foo: int = 8;
+}
+
+component cmpassn14 {
+
+    field cnt: int;
+    field foo: cmpassn14_obj = new cmpassn14_obj();
+
+    method getfoo(): cmpassn14_obj {
+\tcnt++;
+        return foo;
+    }
+
+    method main(arg: int): int {
+\tlocal bar = getfoo().foo -= 2;
+\tif ( arg == 1 ) return foo.foo;
+\tif ( arg == 2 ) return bar;
+\tif ( arg == 3 ) return cnt;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array09 {
+    field a_01: char[] =  new char[1];
+    field a_02: char[] =  new char[2];
+    field a_03: char[] =  new char[3];
+}
+
+/* 
+heap {
+    record #0:3:array09 {
+        field a_01: char[] = #1:char[1];
+        field a_02: char[] = #2:char[2];
+        field a_03: char[] = #3:char[3];
+    }
+    record #1:1:char[1] {
+        field 0:char = char:0;
+    }
+    record #2:2:char[2] {
+        field 0:char = char:0;
+        field 1:char = char:0;
+    }
+    record #3:3:char[3] {
+        field 0:char = char:0;
+        field 1:char = char:0;
+        field 2:char = char:0;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_field03_a<Y> extends inh_field03_b<Y> {
+  field g: Y = f;
+}
+
+class inh_field03_b<X> {
+  field f: X;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: InvalidLiteral @ 6:20
+
+class int_lit04 {
+    field a: int = 2147483648;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class10<X, Y> extends class10a<X, Y> {
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > << operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_shl04 {
+    field a: 7;
+    field b: 7;
+    field c: 2 = a << b;
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeParamArityMismatch @ 9:14
+
+class num_params03_a {
+}
+
+component num_params03_b {
+  method m(o: num_params03_a<int>) {
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+component logical11 {
+    field res_01: int;
+    field res_02: int;
+    field res_03: int;
+    field res_04: int;
+
+    constructor() {
+\tres_01 = true or false? 11 : 12;
+\tres_02 = true or true? 11 : 12;
+\tres_03 = false or true? 11 : 12;
+\tres_04 = false or false? 11 : 12;
+    }
+
+}
+
+/* 
+heap {
+    record #0:4:logical11 {
+\tfield res_01: int = int:11;
+\tfield res_02: int = int:11;
+\tfield res_03: int = int:11;
+\tfield res_04: int = int:12;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking of parameters, method calls, and returns
+// @Result: PASS
+
+class type54 {
+    
+    method testm(a: int): int {
+        return testm(a);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component for08 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i: int, cumul: int;
+        for ( i = 1, cumul = 0; i <= max; cumul += i, i++ ) ;
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:for08 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=14, 5=42
+
+component ptex_meth02 {
+
+    method main(arg: int): int {
+    \tif ( arg == 1 ) return m(11);
+    \tif ( arg == 2 ) return m(12);
+    \tif ( arg == 3 ) return m(n(13));
+    \tif ( arg == 4 ) return m(n(14));
+        return 42;
+    }
+
+    method m<T>(x: T): T { return x; }
+    method n<T>(x: T): T { return x; }
+}
+"
+"// @Harness: v2-seman
+// @Result: InvalidTypeCast @ 8:19
+
+class A<X> { } 
+
+class cast09 {
+   method m(x: A<int>) {
+      local f = x :: (A<char>);
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 13:12
+
+class switch_init02 {
+    
+    method testm(a: int) {
+        local uninit: int;
+        switch ( 0 ) {
+            case ( 1 ) ;
+            default {
+                uninit = 2;
+            }
+        }
+        testm(uninit);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: constructors
+// @Result: TypeMismatch @ 11:32
+
+class constructor20_a {
+    constructor(a: int) {
+    }
+}
+
+class constructor20_b extends constructor20_a {
+    constructor(a: int) : super(null) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: TypeMismatch @ 6:16
+
+class type29 {
+    
+    method testm() {
+        local a: int = 2 * null;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component while03 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( true ) {
+\t    cumul += i;
+\t    if ( i == max ) break;
+\t    i++;
+\t}
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42, 5=11, 6=21, 7=31, 8=42
+
+class delegate04_a {
+    method val(): int { return 11; }
+}
+
+class delegate04_b extends delegate04_a {
+    method val(): int { return 21; }
+}
+
+component delegate04 {
+    field am: function():int = new delegate04_a().val;
+    field bm: function():int = new delegate04_b().val;
+    field cm: function():int = val;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return am();
+\tif ( arg == 2 ) return bm();
+\tif ( arg == 3 ) return cm();
+
+        local m = m42;
+\tif ( arg == 5 ) m = am;
+\tif ( arg == 6 ) m = bm;
+\tif ( arg == 7 ) m = cm;
+
+\treturn m();
+    }
+
+    method val(): int {
+\treturn 31;
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array17 {
+    field a_01: int[][] =  new int[][4];
+    field a_02: bool[][] =  new bool[][3];
+    field a_03: char[][] = new char[][6];
+}
+
+/* 
+heap {
+    record #0:3:array17 {
+        field a_01: int[][] = #1:int[][4];
+        field a_02: bool[][] = #2:bool[][3];
+        field a_03: char[][] = #3:char[][6];
+    }
+    record #1:4:int[][4] {
+\tfield 0:int[] = #null;
+\tfield 1:int[] = #null;
+\tfield 2:int[] = #null;
+\tfield 3:int[] = #null;
+    }
+    record #2:3:bool[][3] {
+\tfield 0:bool[] = #null;
+\tfield 1:bool[] = #null;
+\tfield 2:bool[] = #null;
+    }
+    record #3:6:char[][6] {
+\tfield 0:char[] = #null;
+\tfield 1:char[] = #null;
+\tfield 2:char[] = #null;
+\tfield 3:char[] = #null;
+\tfield 4:char[] = #null;
+\tfield 5:char[] = #null;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: PASS
+
+class while_short_init02 {
+    
+    method testm(p: bool) {
+        local foo: bool;
+        while ( p or (foo = p) ) foo = p;
+        testm(foo);
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=42
+
+class NX {
+   method id<X>(x: X): X;
+}
+
+class MX extends NX {
+   method id<X>(x: X): X {
+      return x;
+   }
+}
+
+component ptex_vp03 {
+   field m1: NX = new MX();
+   field m2: int = m1.id(11);
+   field m3: int = m1.id(13);
+   
+   method main(arg: int): int {
+      if ( arg == 1 ) return m2;
+      if ( arg == 2 ) return m1.id(12);
+      if ( arg == 3 ) return m1.id(m3);
+      return 42;
+   }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+
+  method first(): X {
+    return a;
+  }
+
+  method second(): Y {
+    return b;
+  }
+}
+
+component Client {
+  method test() {
+    local p = new Pair<int, bool>();
+    local b: int = p.first();
+    local c: bool = p.second();
+  }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_method01b_a<X> extends inh_method01b_b<X> {
+  field g: X = this.f();
+}
+
+class inh_method01b_b<X> {
+  method f(): X;
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=7, 2=42, 3=7, 4=1, 5=0
+
+component prepost20 {
+    field ind: int = 0;
+    field foo: int[] = { 6, 42 };
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = ++foo[ind++];
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[1];
+\tif ( arg == 3 ) return bar;
+\tif ( arg == 4 ) return ind;
+\treturn 0;
+    }
+}
+"
+"component Mica2 {
+
+\tfield portA: PortA = new PortA();
+\tfield portB: PortB = new PortB();
+\tfield portC: PortC = new PortC();
+\tfield portD: PortD = new PortD();
+\tfield portE: PortE = new PortE();
+
+\tfield green: LED  = new LED(new Pin(portA, 1), ""Green"");
+\tfield yellow: LED = new LED(new Pin(portA, 0), ""Yellow"");
+\tfield red: LED\t= new LED(new Pin(portA, 2), ""Red"");
+
+\tfield LIGHT_CHANNEL: int = 1;\t\t// ADC channel for light sensor
+\tfield MAIN_CLOCK_HZ: int = 7372800;\t// main clock rate
+\tfield EXT_CLOCK_HZ:  int = 32768;\t// external clock rate
+
+\tmethod startTimer() {
+\t\tdevice.ASSR = 0b1000;\t\t\t// set Timer0 to asynch operation
+\t\tTimer0.setMode(Timer0.MODE_CTC);\t// use clear timer on compare mode
+\t\tTimer0.setCompareMatch(16);\t\t// compare matches every (16 * 1024) cycles
+\t\tTimer0.setCompareMatch(32);\t\t// compare matches every (16 * 1024) cycles
+\t\tTimer0.setCount(0);\t\t\t// reset the count
+\t\tdevice.TIMSK = 0b10;\t\t\t// enable the Timer0 compare interrupt
+\t\tTimer0.setDivider(Timer0.DIV_1024);\t// set divider to 1024
+\t\tPower.adjustPower();
+\t}
+
+\tmethod startSPI(master: boolean) {
+\t\tif ( master ) {
+\t\t\tportB.setDirection(0x6);
+\t\t\tSPI.startMaster();
+\t\t} else {
+\t\t\tportB.setDirection(0x8);
+\t\t\tSPI.startSlave();
+\t\t}
+\t}
+
+\tmethod startLightSensor() {
+\t\tportC.setOutput();
+\t\tportE.setOutput();
+\t\tportE.out(0b00100000);
+\t}
+
+\tmethod startTerminal() {
+\t//\tUSART0.enable(calculateBaud(4800, 2), true, false);
+\t\tUSART0.enable(calculateBaud(57600, 2), false, true);
+\t\tMCU.enable();
+\t}
+
+\tmethod startLEDs() {
+\t\tportA.setOutput();
+\t\tportA.out(0xff);
+\t}
+
+\tmethod setTimerCompare(cf: function()) {
+\t\tTimer0.setCompare(cf);
+\t}
+
+\tmethod displayOnLEDs(value: 3) {
+\t\tdisplayLED(red, value[0]);
+\t\tdisplayLED(yellow, value[1]);
+\t\tdisplayLED(green, value[2]);
+\t}
+
+\tmethod displayLED(led: LED, b: 1) {
+\t\tif ( b == 0b1 ) led.on();
+\t\telse led.off();
+\t}
+
+\tmethod calculateBaud(rate: int, mode: int): int {
+\t\treturn USART.calculateBaud(MAIN_CLOCK_HZ, rate, mode);
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Test: duplicate parameter names
+// @Result: ExpectedVarType @ 7:28
+
+component param4 {
+    
+    method testm(a: void) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class L<T> {
+}
+
+component C {
+\tmethod m<T>(x: T) {
+\t\tm(null :: (L<T>));
+\t}
+}"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: UnresolvedIdentifier @ 7:7
+
+class local_res04 {
+    
+    method testm() {
+        for ( ; ; ) {
+            foo = 0;
+        }
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=13, 3=NullCheckException, 4=42
+
+class rtex_null09_obj {
+    method baz(): int { return 13; }
+}
+
+component rtex_null09 {
+    field a: rtex_null09_obj;
+    field b: rtex_null09_obj = new rtex_null09_obj();
+    field c: rtex_null09_obj;
+
+    method main(arg: int): int {
+\tlocal m = m42;
+\tif ( arg == 1 ) m = a.baz;
+\tif ( arg == 2 ) m = b.baz;
+\tif ( arg == 3 ) m = c.baz;
+\treturn m();
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > and operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_and04 {
+    field a: 7;
+    field b: 7;
+    field c: 2 = a & b;
+}
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 7:10
+
+class lvalue3 {
+    
+    method testm() {
+        local foo: bool = true;
+        foo ? 3:2 = 1;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: PASS
+
+component field_res07_a {
+    field testf: int;
+}
+component field_res07_b {
+    
+    method testm() {
+        field_res07_a.testf = 0;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component prepost01 {
+    field foo: int = 1;
+    field bar: int = foo++;
+}
+
+/* 
+heap {
+    record #0:2:prepost01 {
+        field foo: int = int:2;
+        field bar: int = int:1;
+    }
+}*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class method02 {
+    method m1(a: type<X>): type<X>;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_infer10 {
+    method apply<T>(a: T, f: function(T): T): T {
+        return f(a);
+    }
+    method test() {
+        local x: int = apply(0, id);
+    }
+    method id<T>(x: T): T { return x; }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > concatenation operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_concat02 {
+    field a: 7;
+    field b: 3;
+    field c: 9 = a # b;
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:31
+
+class cast03 {
+   method m() {
+      local y = x :: Type<int>;
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: divide by zero exception during initialization
+// @Result: 0=15, 1=22, 3=DivideByZeroException, 4=215, 5=236
+
+component rtex_divzero03 {
+    field foo: int = 0;
+
+    method div(a: int, b: int): int {
+        return a / b;
+    }
+
+    method main(arg: int): int {
+\treturn 1 + div(42, 3 - arg);
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class1 {
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component if03 {
+    
+    field res_01: int = choose(true,  -1, 1);
+    field res_02: int = choose(false, -1, 1);
+    field res_03: int = choose(true,  241, 100);
+    field res_04: int = choose(false, 241, 100);
+    field res_05: int = choose(true,  -100, 6);
+    field res_06: int = choose(false, -100, 6);
+
+    method choose(c: bool, a: int, b: int): int {
+\tif ( c ) return a;
+        else return b;
+    }
+}
+
+/* 
+heap {
+    record #0:6:if03 {
+        field res_01: int = int:-1;
+        field res_02: int = int:1;
+        field res_03: int = int:241;
+        field res_04: int = int:100;
+        field res_05: int = int:-100;
+        field res_06: int = int:6;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_char01 {
+    
+    method testm() {
+        local a: char = false ? '0' : '1';
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+class field02b_obj {
+    field bar: int;
+    constructor() {
+        bar = 1;
+    }
+}
+
+component field02b {
+    field foo: field02b_obj = new field02b_obj();
+}
+
+/* 
+heap {
+    record #0:1:field02b {
+        field foo: field02b_obj = #1:field02b_obj;
+    }
+    record #1:1:field02b_obj {
+        field bar: int = int:1;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 6:13
+
+class lvalue6 {
+    
+    method testm() {
+        local i: int = testm() = 2;
+    }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test variable initialization in compound assignment""
+// @Result: VariableNotInitialized @ 7:14
+
+class compound_init02 {
+
+    method testm() {
+        local array: int[];
+        array[0] += 2;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: TypeQuery operator
+// @Result: PASS
+
+class instof01b_obj {
+}
+
+component instof01b {
+    field foo: instof01b_obj;
+    field bar: bool = foo <: instof01b_obj;
+}
+
+/* 
+heap {
+    record #0:2:instof01b {
+        field foo: instof01b_obj = #null;
+        field bar: bool = bool:false;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Visitor<E> {
+    method visitA(n: A, e: E);
+    method visitB(n: B, e: E);
+}
+
+class S {
+    method accept<E>(v: Visitor<E>, e: E);
+}
+
+class A extends S {
+    method accept<E>(v: Visitor<E>, e: E) { v.visitA(this, e); }
+}
+
+class B extends S {
+    method accept<E>(v: Visitor<E>, e: E) { v.visitB(this, e); }
+}
+
+class PriceList {
+}
+
+class Thief extends Visitor<PriceList> {
+    method visitA(n: A, e: PriceList) {
+    }
+    method visitB(n: B, e: PriceList) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; return value from method
+// @Result: TypeMismatch @ 9:30
+
+class type16 {
+    
+    method testm(): int {
+        return false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeMismatch @ 8:14
+
+class assign21<X, Y> {
+   field f: X[];
+
+   method m(x: Y) {
+      f[0] = x;
+      x = f[0];
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator
+// @Result: PASS
+
+component raw_index04 {
+    field f1: 8 = 0xf0;
+    field f2: 8 = 0xf0;
+    field f3: 8 = 0xf0;
+    field f4: 8 = 0xf0;
+    field f5: 16 = 0x3ff0;
+    field f6: 16 = 0x3ff0;
+    field f7: 32 = 0x3ff0eeee;
+    field f8: 32 = 0x3ff0eeee;
+    field f9: 32 = 0x3ff0eeee;
+
+    constructor() {
+\tlocal x1 = f1, 
+\t      x2 = f2, 
+\t      x3 = f3, 
+              x4 = f4, 
+              x5 = f5, 
+              x6 = f6, 
+              x7 = f7, 
+              x8 = f8, 
+              x9 = f9;
+
+\tx1[-1] |= 0b1;
+\tx2[3]  |= 0b1;
+\tx3[7]  |= 0b1;
+\tx4[9]  |= 0b1;
+\tx5[15] |= 0b1;
+\tx6[17] |= 0b1;
+\tx7[0]  |= 0b1;
+\tx8[31] |= 0b1;
+\tx9[32] |= 0b1;
+
+\tf1 = x1;
+\tf2 = x2;
+\tf3 = x3;
+\tf4 = x4;
+\tf5 = x5;
+\tf6 = x6;
+\tf7 = x7;
+\tf8 = x8;
+\tf9 = x9;
+    }
+}
+
+/*
+heap {
+    record #0:1:raw_index04 {
+\tfield f1: 8 = raw.8:0xf0;
+\tfield f2: 8 = raw.8:0xf8;
+\tfield f3: 8 = raw.8:0xf0;
+\tfield f4: 8 = raw.8:0x0f0;
+\tfield f5: 16 = raw.16:0xbff0;
+\tfield f6: 16 = raw.16:0x3ff0;
+\tfield f7: 32 = raw.32:0x3ff0eeef;
+\tfield f8: 32 = raw.32:0xbff0eeee;
+\tfield f9: 32 = raw.32:0x3ff0eeee;
+    }
+}
+*/
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component for02 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        for ( ; i <= max; i++ ) cumul += i;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > auto extension
+// @Result: TypeMismatch @ 7:19
+
+class raw_assn07 {
+    field a: 16;
+    field b: 15 = a;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class field1 {
+          field f1: type;
+
+  private field f2: type;
+
+}
+"
+"// @Harness: v2-init
+// @Test: divide by zero exception during initialization
+// @Result: DivideByZeroException @ 6:24
+
+component divzero01 {
+    field foo: int = 1 / 0;
+}
+"
+"// @Harness: v2-seman
+// @Test: duplicate parameter names
+// @Result: ExpectedVarType @ 7:28
+
+component param6 {
+    
+    method testm(a: param6) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > bit access operations
+// @Result: PASS
+
+class raw_index06 {
+    method m(a: 8, i: int, j: int) {
+\tlocal x: 1 = a[i] = a[j];
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: TypeMismatch @ 6:13
+
+class ternary_type02 {
+    
+    method testm() {
+        local a: int = 0 ? 1:0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_op02 {
+    method check(a: int, b: int): boolean {
+\tlocal x: boolean;
+\tx = a < b;
+\tx = a > b;
+\tx = a <= b;
+\tx = a >= b;
+\tx = a == b;
+\tx = a != b;
+\treturn x;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_id05 {
+    method test() {
+\tlocal x: int = id('a');
+    }
+    method id<X>(x: X): X {
+\treturn x;\t
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+
+  method first(): X {
+    return a;
+  }
+
+  method second(): Y {
+    return b;
+  }
+}
+"
+"// @Harness: v2-seman
+// @Test: duplicate parameter names
+// @Result: ExpectedVarType @ 7:28
+
+class param3 {
+    
+    method testm(a: void) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test variable initialization in compound assignment""
+// @Result: NotAnLvalue @ 8:28
+
+class compound02 {
+
+    method testm() {
+        local cntr: int = foo() += 2;
+    }
+
+    method foo(): int {
+        return 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int operations
+// @Result: PASS
+
+class raw_op03 {
+    method check(a: 32, b: 32, c: int): 32 {
+\tlocal x: 32;
+\tx = a;
+\tx = a & b;
+\tx = a | b;
+\tx = a ^ b;
+\tx = a << c;
+\tx = a >> c;
+\tx = ~a;
+\treturn x;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Main: fold01.main
+// @Result: 0=2, 1=8, 2=17, 3=29, 4=44, 5=62, 6=83, 7=107, 8=134, 9=164
+
+component fold01 {
+    field array: int[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
+
+    method main(arg: int): int {
+\tlocal a = fold(add, array, arg);
+        local b = fold(add2, array, arg);
+\treturn a + b;
+    }
+
+    method add(a: int, b: int): int {
+\treturn a + b;
+    }
+
+    method add2(a: int, b: int): int {
+        return a + 2 * b;
+    }
+
+    // iterative version of fold
+    method fold(f: function(int, int): int, a: int[], m: int): int {
+        local cumul = a[0];
+        local cntr = 1;
+        for ( ; cntr <= m; cntr++ ) cumul = f(cumul, a[cntr]);
+\treturn cumul; 
+    }
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class C<X> {
+}
+
+component init01 {
+  field f: C<int> = new C<int>();
+}
+
+/*
+heap {
+  record #0:1:init01 {
+    field f: C<int> = #1:C<int>;
+  }
+  record #1:0:C<int> {
+  }
+}
+*/
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Result: 1 = 11, 2 = 21, 3 = 31, 4 = 0
+
+component static01_a {
+    method val(): int { return 11; }
+}
+
+component static01_b {
+    method val(): int { return 21; }
+}
+
+component static01_c {
+    method val(): int { return 31; }
+}
+
+component static01 {
+    field val: int;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) val = static01_a.val();
+\tif ( arg == 2 ) val = static01_b.val();
+\tif ( arg == 3 ) val = static01_c.val();
+\treturn val;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: UnresolvedType @ 5:12
+
+class scope11_a extends scope11_b<int> {
+  field x: X;
+}
+
+class scope11_b<X> {
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=0
+
+component raw_shl04 {
+    field res_01: 29 = op(0x0f,     1);
+    field res_02: 29 = op(0x02,     2);
+    field res_03: 29 = op(0x01,    31);
+    field res_04: 29 = op(0x30,     8);
+    field res_05: 29 = op(0xf0,    16);
+    field res_06: 29 = op(0xfffff, 12);
+    field res_07: 29 = op(0x10000, 16);
+    field res_08: 29 = op(0xff,     5);
+    field res_09: 29 = op(0xaa,     0);
+
+    method op(a: 29, b: int): 29 {
+\treturn a << b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(0x0f,     1) == res_01;
+\tif ( arg == 2 ) return op(0x02,     2) == res_02;
+\tif ( arg == 3 ) return op(0x01,    31) == res_03;
+\tif ( arg == 4 ) return op(0x30,     8) == res_04;
+\tif ( arg == 5 ) return op(0xf0,    16) == res_05;
+\tif ( arg == 6 ) return op(0xfffff, 12) == res_06;
+\tif ( arg == 7 ) return op(0x10000, 16) == res_07;
+\tif ( arg == 8 ) return op(0xff,     5) == res_08;
+\tif ( arg == 9 ) return op(0xaa,     0) == res_09;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: VariableNotInitialized @ 8:14
+
+class while_short_init01 {
+    
+    method testm(p: bool) {
+        local uninit: bool;
+        while ( p or (uninit = p) ) {
+            testm(uninit);
+        }
+    }
+}
+"
+"program P {
+   entrypoint main = Foo.main;
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=0
+
+component raw_shrx01 {
+
+    field res_01: 32 = op(0xaa, 32);
+
+    method op(a: 32, b: int): 32 {
+\treturn a >> b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(0xaa, 32) == res_01;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_method02_a extends inh_method02_b {
+  field h: int = f();
+  field j: bool = g();
+}
+
+class inh_method02_b extends inh_method02_c {
+}
+
+class inh_method02_c {
+  method f(): int { return 0; }
+  method g(): bool { return false; }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_flip05 {
+    field res_01: 16 = flip2(0x0ffe);
+    field res_02: 16 = flip2(0x0002);
+    field res_03: 16 = flip2(0x0001);
+    field res_04: 16 = flip2(0x8000);
+    field res_05: 16 = flip2(0xf007);
+    field res_06: 16 = flip2(0x8877);
+    field res_07: 16 = flip2(0xaa01);
+
+    method flip(a: 16): 16 {
+\treturn (a :: 8) # ((a >> 8) :: 8);
+    }
+
+    method flip2(a: 16): 16 {
+\treturn flip(flip(a));
+    }
+}
+
+/* 
+heap {
+    record #0:6:raw_flip05 {
+        field res_01: raw.16 = raw.16:0x0ffe;
+        field res_02: raw.16 = raw.16:0x0002;
+        field res_03: raw.16 = raw.16:0x0001;
+        field res_04: raw.16 = raw.16:0x8000;
+        field res_05: raw.16 = raw.16:0xf007;
+        field res_06: raw.16 = raw.16:0x8877;
+        field res_07: raw.16 = raw.16:0xaa01;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class method05 {
+    method m1(a: type<X, Y>, b: type<Y>): type<X> {
+        return b;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=0, 2=1, 3=0
+
+class A<X> { } 
+
+component ptex_instof01 {
+
+   field a: A<int> = new A<int>();
+
+   method m(x: A<int>): bool {
+      return x <: (A<int>);
+   }
+
+   method main(arg: int): bool {
+       if ( arg == 1 ) return m(null);
+       if ( arg == 2 ) return m(a);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=7, 2=7, 3=0
+
+class prepost09_obj {
+    field foo: int = 6;
+    field bar: int;
+}
+
+component prepost09 {
+    field foo: prepost09_obj = new prepost09_obj();
+
+    method main(arg: int): int {
+\tfoo.bar = ++foo.foo;
+\tif ( arg == 1 ) return foo.foo;
+\tif ( arg == 2 ) return foo.bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 5:3
+
+class type_res02 {
+    
+    method testm(): foo;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_infer08 {
+    method apply<T>(a: T, f: function(T): T): T {
+        return f(a);
+    }
+    method test() {
+        local x: int = apply(0, null);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types, << operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_shl02 {
+    field a: 6;
+    field b: 7;
+    field c: 6 = a << b;
+}
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=13, 3=17, 4=NullCheckException, 5=42
+
+component rtex_null11 {
+    field a: function(): int;
+    field b: function(): int = m13;
+    field c: function(): int = m17;
+    field d: function(): int;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a();
+\tif ( arg == 2 ) return b();
+\tif ( arg == 3 ) return c();
+\tif ( arg == 4 ) return d();
+\treturn 42;
+    }
+
+    method m13(): int { return 13; }
+    method m17(): int { return 17; }
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization interpreter > raw types > and operator
+// @Result: 0=3, 1=3, 2=7, 3=11, 4=19, 5=35, 6=67, 7=131
+
+component raw_index05 {
+    field f: 8[] = { 0x03 };
+
+    method main(arg: int): 8 {
+\tf[0][arg] |= 0b1;
+\treturn f[0];
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class scope08_a<X> {
+}
+
+class scope08_b<X> {
+}
+"
+"// @Harness: v2-init
+// @Test: compile-time constants for octal integers
+// @Result: PASS
+
+component raw_bin01 {
+    field a: 1  =                               0b0;
+    field b: 1  =                               0b1;
+    field c: 2  =                              0b10;
+    field d: 3  =                             0b111;
+    field e: 4  =                            0b1000;
+    field f: 4  =                            0b1001;
+    field g: 4  =                            0b1111;
+    field h: 8  =                        0b11111111;
+    field i: 15 =                 0b111111111111111;
+    field j: 16 =                0b1111111111111111;
+    field k: 21 =           0b100000000000000000000;
+    field l: 32 = 0b1000000000000000000000000000000;
+}
+
+/* 
+heap {
+    record #0:12:raw_bin01 {
+        field a: raw.1  = raw.1:0x0;
+        field b: raw.1  = raw.1:0x1;
+        field c: raw.2  = raw.2:0x2;
+        field d: raw.3  = raw.3:0x7;
+        field e: raw.4  = raw.4:0x8;
+        field f: raw.4  = raw.4:0x9;
+        field g: raw.4  = raw.4:0xf;
+        field h: raw.8  = raw.8:0xff;
+        field i: raw.15 = raw.15:0x7fff;
+        field j: raw.16 = raw.16:0xffff;
+        field k: raw.20 = raw.21:0x100000;
+        field l: raw.32 = raw.32:0x40000000;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=1, 2=1, 3=0
+
+class A<X> { } 
+
+component ptex_cast01 {
+
+   field a: A<int> = new A<int>();
+
+   method m(x: A<int>): bool {
+      local f = x :: (A<int>);
+      return true;
+   }
+
+   method main(arg: int): bool {
+       if ( arg == 1 ) return m(null);
+       if ( arg == 2 ) return m(a);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 7:40
+
+class type_res20 {
+    method foo(): type_res20 {
+\treturn new unknown[0];
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component dowhile02 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        do cumul += i++; while ( i <= max );
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_comp02 {
+    field res_01: 32 = op(-2);
+    field res_02: 32 = op(-1);
+    field res_03: 32 = op(1100);
+    field res_04: 32 = op(0);
+    field res_05: 32 = op(-13);
+    field res_06: 32 = op(1);
+    field res_07: 32 = op(-17);
+    field res_08: 32 = op(-65536);
+    field res_09: 32 = op(255);
+    field res_10: 32 = op(1000000);
+
+    method op(a: 32): 32 {
+\treturn (~a) >> 4;
+    }
+}
+
+/* 
+heap {
+    record #0:10:raw_comp02 {
+        field res_01: raw.32 = raw.32:0x0000000;
+        field res_02: raw.32 = raw.32:0x0000000;
+        field res_03: raw.32 = raw.32:0xfffffbb;
+        field res_04: raw.32 = raw.32:0xfffffff;
+        field res_05: raw.32 = raw.32:0x0000000;
+        field res_06: raw.32 = raw.32:0xfffffff;
+        field res_07: raw.32 = raw.32:0x0000001;
+        field res_08: raw.32 = raw.32:0x0000fff;
+        field res_09: raw.32 = raw.32:0xffffff0;
+        field res_10: raw.32 = raw.32:0xfff0bdb;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+component logical05 {
+    field res_01: bool = op(true, true);
+    field res_02: bool = op(false, false);
+    field res_03: bool = op(true, false);
+    field res_04: bool = op(false, true);
+
+    method op(a: bool, b: bool): bool {
+\treturn a == b; // exclusive-or operation
+    }
+}
+
+/* 
+heap {
+    record #0:4:logical05 {
+        field res_01: bool = bool:true;
+        field res_02: bool = bool:true;
+        field res_03: bool = bool:false;
+        field res_04: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_int_char02 {
+    
+    method testm() {
+        local a = { 0, '1' };
+        local b: int[] = a;
+    }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""break statement must be inside of loop""
+// @Result: StatementMustBeInLoop @ 6:17
+
+class break2 {
+
+    method testm() {
+        if ( true ) break;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: CannotCompareValues @ 7:22
+
+class type42 {
+    
+    method testm() {
+        local a = (2 == null);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component if07 {
+    
+    field res_01: int = main(0);
+    field res_02: int = main(1);
+    field res_03: int = main(2);
+    field res_04: int = main(3);
+    field res_05: int = main(4);
+    field res_06: int = main(5);
+
+    method main(arg: int): int {
+\tif ( arg > 1 ) if ( arg == 2 ) return 3; else return 4;
+\treturn 5;
+    }
+}
+
+/*
+heap {
+    record #0:6:if07 {
+        field res_01: int = int:5;
+        field res_02: int = int:5;
+        field res_03: int = int:3;
+        field res_04: int = int:4;
+        field res_05: int = int:4;
+        field res_06: int = int:4;
+    }
+}
+*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type18 {
+    field f: ((type));
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class test3 { method foo(): int { return foo.foo(); } }
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @Result: PASS
+
+component sort_init01 {
+    field a: int[] = { 5, 2, 1, 3, 4 };
+
+    constructor() {
+\tsort(a, lessThan);
+    }
+
+    method lessThan(a: int, b: int): bool {
+\treturn a < b;
+    }
+
+    method sort<T>(a: T[], lt: function(T, T): bool) {
+\tlocal i: int, j: int, len = a.length;
+\tfor ( i = 0; i < len; i++ ) {
+\t    for ( j = i+1; j < len; j++ ) {
+\t\tlocal x = a[i], y = a[j];
+\t\tif ( lt(y, x) ) {
+\t\t    a[j] = x;
+\t\t    a[i] = y;
+\t\t}
+\t    }
+\t}
+    }
+ }
+
+/* 
+heap {
+    record #0:2:sort_init01 {
+        field a: int[] = #1:int[5];
+    }
+    record #1:5:int[5] {
+\tfield 0: int = int:1;
+\tfield 1: int = int:2;
+\tfield 2: int = int:3;
+\tfield 3: int = int:4;
+\tfield 4: int = int:5;
+    }
+} 
+*/
+"
+"// @Harness: v2-init
+// @Test: pre/post increment options
+// @Result: PASS
+
+class prepost10_obj {
+    field foo: int = 6;
+    field bar: int = --foo;
+}
+
+component prepost10 {
+    field foo: prepost10_obj = new prepost10_obj();
+
+}
+
+/* 
+heap {
+    record #0:1:prepost10 {
+        field foo: prepost10_obj = #1:prepost10_obj;
+    }
+    record #1:2:prepost10_obj {
+        field foo: int = int:5;
+        field bar: int = int:5;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > auto extension
+// @Result: TypeMismatch @ 7:19
+
+class raw_assn08 {
+    field a: 24;
+    field b: 16 = a;
+}
+"
+"// @Harness: v2-init
+// @Test: compile-time constants for primitive types
+// @Result: PASS
+
+component char_raw02 {
+    field a: bool = \'a\'    == 0x61;
+    field b: bool = \'b\'    == 0x62;
+    field c: bool = \'\
+\'   == 0x0a;
+    field d: bool = \'\\t\'   == 0x09;
+    field e: bool = \'\\b\'   == 0x08;
+    field f: bool = \'\\r\'   == 0x0d;
+    field g: bool = \'\\\'\'   == 0x27;
+    field h: bool = \'""\'    == 0x22;
+    field i: bool = \'\\377\' == 0xff;
+    field j: bool = \'\\\\\'   == 0x5c;
+    field k: bool = \' \'    == 0x20;
+}
+
+/* 
+heap {
+    record #0:14:char_raw02 {
+        field a: bool = bool:true;
+        field b: bool = bool:true;
+        field c: bool = bool:true;
+        field d: bool = bool:true;
+        field e: bool = bool:true;
+        field f: bool = bool:true;
+        field g: bool = bool:true;
+        field h: bool = bool:true;
+        field i: bool = bool:true;
+        field j: bool = bool:true;
+        field k: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: TypeMismatch @ 6:13
+
+class assign14<X> {
+   field f: assign14<int> = null;
+   field g: assign14<X> = f;
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Result: 0=42, 1=2, 2=1, 3=4, 4=255, 5=0, 6=1, 7=255, 8=42
+
+component ptex_find06 {
+
+    field farr: (function(): int)[] = { f1, f2, f3, f4, f5 };
+    field carr: (function(): char)[] = { fA, fB, fC };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return find(farr, 3);
+\tif ( arg == 2 ) return find(farr, 2);
+\tif ( arg == 3 ) return find(farr, 5);
+\tif ( arg == 4 ) return find(farr, 7);
+\tif ( arg == 5 ) return find(carr, 'A');
+\tif ( arg == 6 ) return find(carr, 'B');
+\tif ( arg == 7 ) return find(carr, 'D');
+        return 42;
+    }
+
+    method find<T>(arr: (function(): T)[], val: T): int {
+        local i = 0;
+\tfor ( ; i < arr.length; i++ ) {
+            if ( arr[i]() == val ) return i;
+        }
+        return -1;
+    }
+
+    method f1(): int { return 1; }
+    method f2(): int { return 2; }
+    method f3(): int { return 3; }
+    method f4(): int { return 4; }
+    method f5(): int { return 5; }
+
+    method fA(): char { return 'A'; }
+    method fB(): char { return 'B'; }
+    method fC(): char { return 'C'; }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class new11<X> {
+   method m() {
+      local f = new new11<X>[1];
+   }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class2 {
+  field f1: type;
+  field f2: type, f3: int;
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: PASS
+
+class short_init06 {
+    
+    method testm(p: bool) {
+        local foo: bool;
+        if ( p and (foo = p) ) testm(foo);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: method resolution
+// @Result: PASS
+
+class method_res04_a {
+    
+    method foo() {
+    }
+}
+class method_res04_b {
+    
+    method testm(arg: method_res04_a) {
+        arg.foo();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @Result: PASS
+
+component static04 {
+    field av: int = val1();
+    field bv: int = val2();
+    field cv: int = val3();
+
+    method val1(): int { return apply(val2, 2); }
+    method val2(): int { return 2; }
+    method val3(): int { return apply(val1, 4); }    
+
+    method apply(f: function(): int, a: int): int { return f() + a; }
+}
+
+/* 
+heap {
+    record #0:3:static04 {
+        field av: int = int:4;
+        field bv: int = int:2;
+        field cv: int = int:8;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: initialization of arrays of raws
+// @Result: PASS
+
+component array_raw05 {
+    field a: 5[] = { 0xf, 0b10, 0b11100 };
+    field av: 5  = a[0];
+}
+
+/* 
+heap {
+    record #0:4:array_raw05 {
+\tfield a: raw.5[] = #1:raw.5[3];
+\tfield av: raw.5 = raw.5:0xf;
+    }
+    record #1:3:5[3] {
+\tfield 0: raw.5 = raw.5:0x0f;
+\tfield 1: raw.5 = raw.5:0x02;
+\tfield 2: raw.5 = raw.5:0x1c;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array06 {
+    field a_02: char[][] =  { ""hi"", {\'c\'} };
+}
+
+/* 
+heap {
+    record #0:1:array06 {
+        field a_02: char[][] = #1:char[][2];
+    }
+    record #1:2:char[][2] {
+        field 0:char[] = #2:char[2];
+        field 1:char[] = #3:char[1];
+    }
+    record #2:2:char[2] {
+        field 0:char = char:104;
+        field 1:char = char:105;
+    }
+    record #3:1:char[1] {
+        field 0:char = char:99;
+    }
+} */
+"
+"/**
+ * @author Xiaoli Gong
+ * by hacking the CC1000RadioIntM from NesC source code
+ */
+ 
+class TOS_Msg {
+\tfield addr: 16;
+\tfield type: 8;
+\tfield group: 8;
+\tfield length: 8;
+\tfield data: 8[];
+\tfield crc: 16;
+\tfield strength: 16;
+\tfield ack: 8;
+\tfield time: 16;
+\tfield sendSecurityMode: 8;
+\tfield receiveSecurityMode: 8;
+
+\tconstructor() {
+\t\tdata = new 8[29];
+\t}
+
+\tmethod setByte(counter: int, value: 8) {
+\t\tlocal temp: 16;
+\t\tswitch (counter) {
+\t\t\tcase (0) {
+\t\t\t\ttemp = this.addr | 0xff00;
+\t\t\t\ttemp = temp & ((value :: 16) << 8);
+\t\t\t\taddr = temp;
+\t\t\t}
+\t\t\tcase (1) {
+\t\t\t\ttemp = addr &0xff00;
+\t\t\t\ttemp = temp | (value :: 16);
+\t\t\t\taddr = temp;
+\t\t\t}
+\t\t\tcase (2) {
+\t\t\t\ttype = value;
+\t\t\t}
+\t\t\tcase (3) {
+\t\t\t\tgroup= value;
+\t\t\t}
+\t\t\tcase (4) {
+\t\t\t\tlength = value;
+\t\t\t}
+\t\t\tcase (34) {
+\t\t\t\ttemp = crc|0xff00;
+\t\t\t\ttemp = temp &((value :: 16) << 8);
+\t\t\t\tcrc = temp;
+\t\t\t}
+\t\t\tcase (35) {
+\t\t\t\ttemp = crc & 0xff00;
+\t\t\t\ttemp = temp | (value :: 16);
+\t\t\t\tcrc = temp;
+\t\t\t}
+\t\t\tcase (36) {
+\t\t\t\ttemp = strength|0xff00;
+\t\t\t\ttemp = temp &((value :: 16) << 8);
+\t\t\t\tstrength = temp; 
+\t\t\t}
+\t\t\tcase (37) {
+\t\t\t\ttemp = strength & 0xff00;
+\t\t\t\ttemp = temp | (value :: 16);
+\t\t\t\tstrength = temp;
+\t\t\t}
+\t\t\tcase (38) {
+\t\t\t\tack= value;
+\t\t\t}
+\t\t\tcase (39) {
+\t\t\t\ttemp = time | 0xff00;
+\t\t\t\ttemp = temp & ((value :: 16) << 8);
+\t\t\t\ttime= temp; 
+\t\t\t}
+\t\t\tcase (40) {
+\t\t\t\ttemp = time& 0xff00;
+\t\t\t\ttemp = temp | (value :: 16);
+\t\t\t\ttime = temp;
+\t\t\t}
+\t\t\tcase (41) {
+\t\t\t\tsendSecurityMode = value;
+\t\t\t}
+\t\t\tcase (42) {
+\t\t\t\treceiveSecurityMode = value;
+\t\t\t}
+\t\t\tdefault {
+\t\t\t\tdata[counter - 5] = value;
+\t\t\t}
+\t\t}
+\t}
+ 
+\tmethod getByte(counter: int): 8 {
+\t\tlocal temp: 8 = 0x00;
+\t\tswitch (counter) {
+\t\t\tcase (0) {
+\t\t\t\ttemp = (addr >> 8) :: 8;
+\t\t\t}
+\t\t\tcase (1) {
+\t\t\t\ttemp = (addr & 0xff) :: 8;
+\t\t\t}
+\t\t\tcase (2) {
+\t\t\t\ttemp = type;
+\t\t\t}
+\t\t\tcase (3) {
+\t\t\t\ttemp = group;
+\t\t\t}
+\t\t\tcase (4) {
+\t\t\t\ttemp = length;
+\t\t\t}
+\t\t\tcase (34) {
+\t\t\t\ttemp = (crc >> 8) :: 8;
+\t\t\t}
+\t\t\tcase (35) {
+\t\t\t\ttemp = (crc & 0xff) :: 8;
+\t\t\t}
+\t\t\tcase (36) {
+\t\t\t\ttemp = (strength >> 8) :: 8;
+\t\t\t}
+\t\t\tcase (37) {
+\t\t\t\ttemp = (strength & 0xff) :: 8;
+\t\t\t}
+\t\t\tcase (38) {
+\t\t\t\ttemp = ack;
+\t\t\t}
+\t\t\tcase (39) {
+\t\t\t\ttemp = (time >> 8) :: 8;
+\t\t\t}
+\t\t\tcase (40) {
+\t\t\t\ttemp = (time & 0xff) :: 8;
+\t\t\t}
+\t\t\tcase (41) {
+\t\t\t\ttemp = sendSecurityMode;
+\t\t\t}
+\t\t\tcase (42) {
+\t\t\t\ttemp = receiveSecurityMode;
+\t\t\t}
+\t\t\tdefault {
+\t\t\t\ttemp = data[counter - 5];
+\t\t\t}
+\t\t}
+
+\t\treturn temp;
+\t} 
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+
+  method first(): X {
+    return a;
+  }
+
+  method second(): Y {
+    return b;
+  }
+}
+
+component Client {
+  method test() {
+    local p = new Pair<int, bool>();
+    local b = p.first();
+    local c = p.second();
+  }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=7, 2=6, 3=1, 4=0
+
+class prepost21_obj {
+    field foo: int = 6;
+}
+
+component prepost21 {
+    field cnt: int;
+    field foo: prepost21_obj = new prepost21_obj();
+    field bar: int;
+    
+    method obj(): prepost21_obj {
+\tcnt++; // should only be called once
+\treturn foo;
+    }
+
+    method main(arg: int): int {
+\tbar = obj().foo++;
+\tif ( arg == 1 ) return foo.foo;
+\tif ( arg == 2 ) return bar;
+\tif ( arg == 3 ) return cnt;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeCast operation
+// @Result: PASS
+
+class cast06_a {
+    field foo: cast06_a;
+    field bar: cast06_b = foo :: cast06_b;
+}
+
+class cast06_b extends cast06_a {
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > or operator
+// @Result: PASS
+
+class raw_or03 {
+    field a: 16;
+    field b: 16;
+    field c: 16 = a | b;
+    field d: 16 = b | a;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: CannotUnifyElemTypes @ 6:24
+
+class unify_int_str02 {
+    
+    method testm() {
+        local a = { 0, """" };
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @Result: PASS
+
+component static05 {
+    field m: function(): int = val1;
+    field av: int = m();
+    field bv: int = val2();
+    field cv: int = val3();
+
+    method val1(): int { return apply(val2, 2); }
+    method val2(): int { return 2; }
+    method val3(): int { return apply(val1, 4); }    
+
+    method apply(f: function(): int, a: int): int { return f() + a; }
+}
+
+/* 
+heap {
+    record #0:4:static05 {
+        field m: function():int = [#0:static05,static05:val1()];
+        field av: int = int:4;
+        field bv: int = int:2;
+        field cv: int = int:8;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=0, 2=0, 3=0, 4=0, 5=0, 6=42
+
+component default05a {
+    field foo: char[] = new char[4];
+    field bar: char = foo[0];
+
+    method main(arg: int): char {
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[0];
+\tif ( arg == 3 ) return foo[0];
+\tif ( arg == 4 ) return foo[0];
+\tif ( arg == 5 ) return bar;
+\treturn '*';
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+component logical02 {
+    field res_01: bool = op(true, true);
+    field res_02: bool = op(false, false);
+    field res_03: bool = op(true, false);
+    field res_04: bool = op(false, true);
+
+    method op(a: bool, b: bool): bool {
+\treturn a or b;
+    }
+}
+
+/* 
+heap {
+    record #0:4:logical02 {
+        field res_01: bool = bool:true;
+        field res_02: bool = bool:false;
+        field res_03: bool = bool:true;
+        field res_04: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 5:21
+
+class type_res04 {
+    
+    method testm(a: int, b: foo): int;
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeParamArityMismatch @ 9:14
+
+class num_params05_a<X> {
+}
+
+component num_params05_b {
+  method m(o: num_params05_a<int, bool>) {
+  }
+}
+"
+"/**
+ * Simple LED driver. Accepts a Pin instance and a color name.
+ * Assumes active-low (i.e. low = on).
+ * @author Ben L. Titzer
+ */
+class LED {
+\tfield pin: Pin;
+\tconstructor(p: Pin, color: char[]) {
+\t\tpin = p;
+\t}
+\tmethod toggle() {
+\t\tpin.out(!pin.in());
+\t}
+\tmethod on() {
+\t\tpin.out(false);
+\t}
+\tmethod off() {
+\t\tpin.out(true);
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of evaluation)
+// @Result: PASS
+
+class order_init03 {
+    
+    method testm(a: int, b: int): int {
+        local foo: int;
+        return testm(foo = 0, foo);
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 1
+
+class instof02_obj {
+}
+
+component instof02 {
+    field foo: instof02_obj = new instof02_obj();
+    method main(arg: int): int {
+\treturn foo instanceof instof02_obj ? 1 : 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Result: 0=42, 1=2, 2=255, 3=0, 4=2, 5=42
+
+component ptex_find01 {
+
+    field iarr: int[] = { 1, 2, 3, 4, 5 };
+    field rarr: 5[] = { 0b00001, 0b10000, 0b01000, 0b00010, 0b00100 };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return find(iarr, 3);
+\tif ( arg == 2 ) return find(iarr, 6);
+        if ( arg == 3 ) return find(rarr, 0b00001);
+        if ( arg == 4 ) return find(rarr, 0b01000);
+        return 42;
+    }
+
+    method find<T>(arr: T[], val: T): int {
+        local i = 0;
+\tfor ( ; i < arr.length; i++ ) {
+            if ( arr[i] == val ) return i;
+        }
+        return -1;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=6, 2=42, 3=6, 4=1, 5=1, 6=0
+
+component cmpassn18 {
+    field foocnt: int;
+    field indcnt: int;
+
+    field foo: int[] = { 8, 42 };
+    field bar: int;
+    
+    method getfoo(): int[] {
+\tfoocnt++;
+\treturn foo;
+    }
+    
+    method getind(): int {
+\tindcnt++;
+\treturn 0;
+    }
+
+    method main(arg: int): int {
+\tbar = getfoo()[getind()] -= 2;
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[1];
+\tif ( arg == 3 ) return bar;
+\tif ( arg == 4 ) return foocnt;
+\tif ( arg == 5 ) return indcnt;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=14, 3=15, 4=16, 5=42
+
+class field02b_obj {
+    field a: int;
+    field b: int;
+    field th: field02b_obj = this;
+
+    constructor() {
+        a = 15;
+\tb = 16;
+    }
+}
+
+component field02b {
+    field foo: field02b_obj = new field02b_obj();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo != null ? 13 : 77;
+\tif ( arg == 2 ) return foo.th == foo ? 14 : 77;
+\tif ( arg == 3 ) return foo.a;
+\tif ( arg == 4 ) return foo.b;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: array index exceptions
+// @Result: BoundsCheckException @ 12:17
+
+component index06 {
+    field foo: int[] = new int[42];
+    field bar: int = baz();
+
+    method baz(): int {
+        local cntr: int;
+        for ( cntr = 0; cntr <= 42; cntr++ )
+\t    foo[cntr] = cntr;
+        return -4;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+class default06b_obj {
+    field foo: char;
+    field bar: char = foo;
+}
+
+component default06b {
+    field baz: default06b_obj = new default06b_obj();
+}
+
+/* 
+heap {
+    record #0:1:default06b {
+        field baz: default06b_obj = #1:default06b_obj;
+    }
+    record #1:2:default06b_obj {
+        field foo: char = char:0;
+        field bar: char = char:0;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class array3 {
+  method m1() {
+    local a: type[];
+    local b: type[][];
+    local c: type[][][];
+  }
+}
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=37, 5=41, 6=42
+
+class W<T> {
+    field val: T;
+    constructor(v: T) {
+        val = v;
+    }
+}
+
+component ptex_wrap07 {
+
+    field a: W<int> = new W<int>(11);
+    field b: W<int> = new W<int>(21);
+    field c: W<W<int> > = new W<W<int> >(new W<int>(31));
+    field d: W<W<int> > = new W<W<int> >(new W<int>(37));
+    field e: W<W<function(): int> > = new W<W<function(): int> >(new W<function(): int>(m41));
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val;
+\tif ( arg == 2 ) return b.val;
+\tif ( arg == 3 ) return c.val.val;
+\tif ( arg == 4 ) return d.val.val;
+\tif ( arg == 5 ) return e.val.val();
+\treturn 42;
+    }
+
+    method m41(): int {
+        return 41;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 4:7
+
+class try {
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 8:9
+
+class unreach2 {
+    
+    method testm(): int {
+        while ( true ) {
+            break;
+            local foo: int = 0;
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: inheritance of fields
+// @Result: MemberDefinedInSuper @ 9:8
+
+class inh15_a {
+    field testf: int;
+}
+
+class inh15_b extends inh15_a {
+    method testf(): char;
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 7:5
+
+class unreach1 {
+    
+    method testm(): int {
+        return 1;
+        local foo: int = 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=42
+
+class MX {
+   method id<X>(x: X): X {
+      return x;
+   }
+}
+
+component ptex_vp01 {
+   field m1: MX = new MX();
+   field m2: int = m1.id(11);
+   field m3: int = m1.id(13);
+   
+   method main(arg: int): int {
+      if ( arg == 1 ) return m2;
+      if ( arg == 2 ) return m1.id(12);
+      if ( arg == 3 ) return m1.id(m3);
+      return 42;
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=1, 1=0, 2=0, 3=0, 4=0, 5=1
+
+component array08 {
+    field a: bool[] = new bool[1];
+    field b: bool[] = new bool[3];
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return a[0];
+\tif ( arg == 2 ) return b[0];
+\tif ( arg == 3 ) return b[1];
+\tif ( arg == 4 ) return b[2];
+\treturn true;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+class orer {
+    field a: bool; // true if A() evaluated
+    field b: bool; // true if B() evaluated
+    field R: bool;
+
+    method OR(v1: bool, v2: bool) {
+\tR = A(v1) or B(v2);
+    }
+
+    method A(v: bool): bool {
+\ta = true;
+\treturn v;
+    }
+
+    method B(v: bool): bool {
+\tb = true;
+\treturn v;
+    }
+}
+
+component logical07 {
+    field res_01: orer = new orer();
+    field res_02: orer = new orer();
+    field res_03: orer = new orer();
+    field res_04: orer = new orer();
+
+    constructor() {
+\tres_01.OR(true, false);
+\tres_02.OR(true, true);
+\tres_03.OR(false, true);
+\tres_04.OR(false, false);
+    }
+
+}
+
+/* 
+heap {
+    record #0:4:logical07 {
+\tfield res_01: orer = #1:orer;
+\tfield res_02: orer = #2:orer;
+\tfield res_03: orer = #3:orer;
+\tfield res_04: orer = #4:orer;
+    }
+    record #1:3: orer {
+\tfield a: bool = bool:true;
+\tfield b: bool = bool:false;
+\tfield R: bool = bool:true;
+    }
+    record #2:3: orer {
+\tfield a: bool = bool:true;
+\tfield b: bool = bool:false;
+\tfield R: bool = bool:true;
+    }
+    record #3:3: orer {
+\tfield a: bool = bool:true;
+\tfield b: bool = bool:true;
+\tfield R: bool = bool:true;
+    }
+    record #4:3: orer {
+\tfield a: bool = bool:true;
+\tfield b: bool = bool:true;
+\tfield R: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_class02 {
+    
+    method testm() {
+        local a: unify_class02 = false ? null : this;
+        local b: unify_class02 = false ? this : null;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component method10 {
+    method m1<X>(a: type<X, Y>, b: type<Y>): type<X> {
+        return b;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=0, 2=1, 3=3, 4=3, 5=4, 6=6, 7=6, 8=BoundsCheckException
+
+class A { 
+    field f: int;
+    field t: A = this;
+    constructor(i: int) { f = i; }
+}
+
+component sum01 {
+
+    field arr: A[] = build(7);
+
+    method build(len: int): A[] {
+        local a = new A[len];
+\tlocal cntr = 0;
+\tfor ( ; cntr < len; cntr++ ) {
+\t    a[cntr] = new A(cntr % 3);
+\t}
+\treturn a;
+    }
+    
+    method main(max: int): int {
+\tlocal i: int, cumul = 0;
+        for ( i = 0; i < max; i++ ) cumul += arr[i].t.f;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=1, 2=TypeCheckException, 3=TypeCheckException, 4=1, 5=TypeCheckException, 6=TypeCheckException, 7=0
+
+class A<X> { } 
+class B<X> extends A<int> { }
+
+component ptex_cast06 {
+
+   field a: A<int> = new A<int>();
+   field b: A<int> = new B<int>();
+   field c: A<int> = new B<char>();
+   field d: A<int> = new B<bool>();
+   field e: A<int> = new B<function()>();
+
+   method m(x: A<int>): bool {
+      local f = x :: (B<char>);
+      return true;
+   }
+
+   method main(arg: int): bool {
+       if ( arg == 1 ) return m(null);
+       if ( arg == 2 ) return m(a);
+       if ( arg == 3 ) return m(b);
+       if ( arg == 4 ) return m(c);
+       if ( arg == 5 ) return m(d);
+       if ( arg == 6 ) return m(e);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component dowhile04 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        do {
+\t    cumul += i;
+\t    if ( i == max ) return cumul;
+\t    i++;
+\t} while ( true );
+\treturn cumul;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=15, 3=42
+
+class field10_obj {
+    method bar(i: int) { field10.f = i; }
+}
+
+component field10 {
+    field f: int = 42;
+    field foo: function(int) = new field10_obj().bar;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) foo(13);
+\tif ( arg == 2 ) foo(15);
+\treturn f;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class instof01b {
+   method m() {
+      local f = x <: (Type<X>);
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator
+// @Result: PASS
+
+component raw_index01 {
+    field f1: 1 = 0xf0[-1];
+    field f2: 1 = 0xf0[0];
+    field f3: 1 = 0xf0[4];
+    field f4: 1 = 0xf0[9];
+    field f5: 1 = 0x3ff0[11];
+    field f6: 1 = 0x3ff0[17];
+    field f7: 1 = 0x3ff0eeee[1];
+    field f8: 1 = 0x3ff0eeee[24];
+    field f9: 1 = 0x3ff0eeee[32];
+}
+
+/*
+heap {
+    record #0:1:raw_index01 {
+\tfield f1: 1 = raw.1:0x0;
+\tfield f2: 1 = raw.1:0x0;
+\tfield f3: 1 = raw.1:0x1;
+\tfield f4: 1 = raw.1:0x0;
+\tfield f5: 1 = raw.1:0x1;
+\tfield f6: 1 = raw.1:0x0;
+\tfield f7: 1 = raw.1:0x1;
+\tfield f8: 1 = raw.1:0x1;
+\tfield f9: 1 = raw.1:0x0;
+    }
+}
+*/
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component cmpassn15 {
+    field foo: int[] = { 1 };
+    field bar: int = foo[0] += 4;
+}
+
+/* 
+heap {
+    record #0:2:cmpassn15 {
+        field foo: int[] = #1:int[1];
+        field bar: int = int:5;
+    }
+    record #1:1:int[1] {
+\tfield 0: int = int:5;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of operations)
+// @Result: PASS
+
+class order_init09 {
+    
+    method testm(a: int[]): int {
+        local foo: int;
+        return a[foo] = foo = 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=0, 2=1, 3=0
+
+class A<X> { } 
+
+component ptex_instof02 {
+
+   field a: A<int> = new A<int>();
+   field b: A<char> = new A<char>();
+
+   method m(x: A<int>): bool {
+      return x <: (A<int>);
+   }
+
+   method main(arg: int): bool {
+       if ( arg == 1 ) return m(null);
+       if ( arg == 2 ) return m(a);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization of arrays of raws
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=0
+
+component array_raw12 {
+    field a: 64[] = { 0x111f };
+
+    method main(arg: int): bool {
+\tlocal x: 64 = 0x2a;
+\tif ( arg == 1 ) a[0] = x = 0xf0000000fe710000;
+\tif ( arg == 2 ) a[0] = x = 0x0000000000000004;
+\tif ( arg == 3 ) a[0] = x = 'c';
+\tif ( arg == 4 ) a[0] = x = -1;
+\treturn a[0] == x;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: divide by zero exception during initialization
+// @Result: DivideByZeroException @ 6:24
+
+component divzero05 {
+    field foo: int = 1 % 0;
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+component mp_init03 {
+  field f: int[] = makeArray();
+  field g: char[] = makeArray();
+
+  method makeArray<T>(): T[] {
+    return new T[0];
+  }
+}
+
+/*
+heap {
+  record #0:1:mp_init03 {
+    field f: int[] = #1:int[0];
+    field f: char[] = #2:char[0];
+  }
+  record #1:0:int[0] {
+  }
+  record #2:0:char[0] {
+  }
+}
+*/
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 7:11
+
+class init05 {
+    
+    method testm() {
+        local foo: int;
+        foo = foo;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking of operators
+// @Result: TypeMismatch @ 7:13
+
+class type_null06 {
+  method testm(a: int) {
+    a = 0 + null;
+  }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class if5 {
+  method m() {
+    local a: int;
+    
+    if ( true ) { if ( false ) ; }
+    else if ( true ) { if ( false ) ; else ; }
+    else if ( false ) a = 0;
+    else a = 1;
+  }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=1, 2=TypeCheckException, 3=TypeCheckException, 4=1, 5=TypeCheckException, 6=0
+
+class A<X> { } 
+class B<X> extends A<int> { }
+
+component ptex_cast05 {
+
+   field a: A<int> = new A<int>();
+   field b: A<int> = new B<int>();
+   field c: A<int> = new B<char>();
+   field d: A<int> = new B<bool>();
+
+   method m(x: A<int>): bool {
+      local f = x :: (B<char>);
+      return true;
+   }
+
+   method main(arg: int): bool {
+       if ( arg == 1 ) return m(null);
+       if ( arg == 2 ) return m(a);
+       if ( arg == 3 ) return m(b);
+       if ( arg == 4 ) return m(c);
+       if ( arg == 5 ) return m(d);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: parsing precedence of arithmetic operators
+// @Result: PASS
+
+component prec02 {
+    field r01: int = (1 + 2) * 3;
+    field r02: int = (1 + 3) * 2;
+    field r03: int = 6 * (1 / 2);
+    field r04: int = 2 / (1 * 8);
+    field r05: int = 4 / (4 / 2);
+}
+
+/* 
+heap {
+    record #0:10:prec02 {
+        field r01: int = int:9;
+        field r02: int = int:8;
+\tfield r03: int = int:0;
+\tfield r04: int = int:0;
+\tfield r05: int = int:2;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types, >> operator
+// @Result: PASS
+
+class raw_shr01 {
+    field a: 1;
+    field b: int;
+    field c: 2 = a >> b;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedOperator @ 7:23
+
+component inc07 {
+    method testm(a: int[]) {
+        local foo = --a;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:12
+
+class field6 {
+    field f = 0;
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: UnresolvedIdentifier @ 7:8
+
+class local_res02 {
+    
+    method testm() {
+        {
+            foo = 1;
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 7:15
+
+class init01 {
+    
+    method testm() {
+        local foo: int;
+        local bar: int = foo;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class ovr_method01_a<X> extends ovr_method01_b<X> {
+  method f(): X;
+}
+
+class ovr_method01_b<X> {
+  method f(): X;
+}
+"
+"// @Harness: v2-seman
+// @Test: virtual method invocations
+// @Result: PASS
+
+class inh17_a {
+    method getf(): function(): int { return val; }
+    private method val(): int { return 1; }
+}
+
+class inh17_b extends inh17_a {
+    private method val(): int { return 2; }
+}
+
+component inh17 {
+    field a: function():int = new inh17_a().getf();
+    field b: function():int = new inh17_b().getf();
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type15<X, Y> {
+    field f: type14<function(X), Y>;
+}
+"
+"// @Harness: v2-init
+// @Test: operation of instanceof construct
+// @Result: PASS
+
+class instof02_obj {
+}
+
+component instof02 {
+    field foo: instof02_obj = new instof02_obj();
+    field bar: bool = foo instanceof instof02_obj;
+}
+
+/* 
+heap {
+    record #0:2:instof02 {
+        field foo: instof02_obj = #1:instof02_obj;
+        field bar: bool = bool:true;
+    }
+    record #1:0:instof02_obj {
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of indexing multidimensional arrays""
+// @Result: TypeMismatch @ 6:9
+
+class array14 {
+    
+    method testm(a: int[][]) {
+        a[0][false] = 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shorcutting of conditionals)
+// @Result: VariableNotInitialized @ 9:12
+
+class for_short_init04 {
+    
+    method testm(p: bool) {
+        local uninit: bool;
+        for ( ; p and (uninit = p); ) ;
+        testm(uninit);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg08_a {
+    method val(): int { return 1; }
+}
+
+class dg08_b extends dg08_a {
+    method val(): int { return 2; }
+}
+
+component dg08 {
+    field a: function():int = new dg08_a().val;
+    field b: function():int = new dg08_b().val;
+    field c: function():int = bar;
+    field d: function():int;
+    field av: int = val(a);
+    field bv: int = val(b);
+    field cv: int = val(c);
+    method val(f: function(): int): int {
+\treturn 3 + f();
+    }
+    method bar(): int {
+\treturn 3;
+    }
+
+}
+
+/* 
+heap {
+    record #0:7:dg08 {
+        field a: function():int = [#1:dg08_a,dg08_a:val()];
+        field b: function():int = [#2:dg08_b,dg08_b:val()];
+        field c: function():int = [#0:dg08,dg08:bar()];
+        field d: function():int = #null;
+        field av: int = int:4;
+        field bv: int = int:5;
+        field cv: int = int:6;
+    }
+    record #1:0:dg08_a {
+    }
+    record #2:0:dg08_b {
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > bit access operations
+// @Result: PASS
+
+class raw_index03 {
+    method m(a: 8, b: 1) {
+\ta[0] = b;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 13
+
+class virtual04c_1 {
+    field th: virtual04c_1;
+    method val(a: int): int { th = this; return a+1; }
+}
+
+class virtual04c_2 extends virtual04c_1 {
+    method val(a: int): int { th = this; return a+2; }
+}
+
+class virtual04c_3 extends virtual04c_1 {
+    method val(a: int): int { th = this; return a+3; }
+}
+
+component virtual04c {
+    field a: virtual04c_1 = new virtual04c_1();
+    field b: virtual04c_1 = new virtual04c_2();
+    field c: virtual04c_1 = new virtual04c_3();
+
+    method main(arg: int): int {
+\treturn c.val(10);
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class while1 {
+  method m() {
+     local a: int = -1;
+     local foo: bool = true;
+
+     while ( true ) ;
+     while ( foo ) ;
+     while ( func(a) ) ;
+
+     while ( true ) { }
+     while ( foo ) { }
+     while ( func(a) ) { }
+
+  }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class field08 {
+    method m() {
+       local f: type<X, Y>;
+       local g: type<X>;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_method09_a extends inh_method09_b<int, bool> {
+  field h: int = g();
+  field j: bool = f();
+
+  field k: int = x();
+  field l: bool = y();
+}
+
+class inh_method09_b<T, U> extends inh_method09_c<U, T> { // note permutation
+  method x(): T;
+  method y(): U;
+}
+
+class inh_method09_c<Y, Z> {
+  method f(): Y;
+  method g(): Z;
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 9:5
+
+class unreach26 {
+    
+    method testm(): int {
+        for ( ; ; ) {
+            local foo: int = 1;
+        }
+        return 0;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 4:17
+
+component comp01<X> {
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component while05 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( true ) {
+\t    cumul += i++;
+\t    if ( i > max ) return cumul;
+\t}
+\treturn cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:while05 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: PASS
+
+class for_init07 {
+    
+    method testm(a: int) {
+        local foo: int;
+        local bar: int;
+        for ( foo = 0; foo < 100; foo = bar ) {
+            if ( foo == a ) {
+                bar = 2;
+                continue;
+            }
+            if ( foo == a - 1 ) {
+                break;
+            }
+            bar = 3;
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of operations)
+// @Result: PASS
+
+class order_init07 {
+    
+    method testm(a: order_init07): int {
+        local foo: order_init07;
+        
+        return (foo = a).testm(foo);
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=13, 3=NullCheckException, 4=42
+
+class rtex_null03_obj {
+    field baz: int = 13;
+}
+
+component rtex_null03 {
+    field a: rtex_null03_obj;
+    field b: rtex_null03_obj = new rtex_null03_obj();
+    field c: rtex_null03_obj = null;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.baz;
+\tif ( arg == 2 ) return b.baz;
+\tif ( arg == 3 ) return c.baz;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: switch cases should have compile-time computable values
+// @Result: PASS
+
+class switch02 {
+    
+    method testm(a: int) {
+        switch ( a ) {
+            case ( 0 + 1 ) ;
+        }
+    }
+}
+"
+"/*
+ * This program tests the operation of the USART serial driver.
+ * @author Xiaoli Gong
+ */
+program TestUSART {
+\tentrypoint main = TestUSART.entry;
+\tentrypoint usart0_rx = USART0.rec_handler;
+\tentrypoint timer0_comp = Timer0.compareHandler;
+\tentrypoint usart0_tx = USART0.tran_handler;
+}
+
+component TestUSART {
+\tfield t_buf: char[] = ""ABCcccccDEFGHIJK\
+"";
+\tfield i: int = 0;
+
+\tmethod print(){
+\t\tUSART0.transmit(t_buf, 0, t_buf.length);
+\t}
+
+\tmethod entry() {
+\t\tMica2.setTimerCompare(print); // set the function to call on overflow
+\t\tMica2.startLEDs();
+\t\tMica2.startTerminal();
+ \t    
+\t\t// Mica2.red.toggle();
+\t\tMica2.startTimer();           // start up the basic timer
+\t\tMCU.sleep();
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of evaluation)
+// @Result: PASS
+
+class order_init05 {
+    
+    method testm(a: bool) {
+        local foo: bool;
+        if ( foo = true ) ;
+        testm(foo);
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component raw_comp04 {
+    field res_01: 32 = op(-2);
+    field res_02: 32 = op(-1);
+    field res_03: 32 = op(1100);
+    field res_04: 32 = op(0);
+    field res_05: 32 = op(-13);
+    field res_06: 32 = op(1);
+    field res_07: 32 = op(-17);
+    field res_08: 32 = op(-65536);
+    field res_09: 32 = op(255);
+    field res_10: 32 = op(1000000);
+
+    method op(a: 32): 32 {
+\treturn (~(a & 0x0fffffff)) >> 4;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(-2)      == res_01;
+\tif ( arg == 2 )  return op(-1)      == res_02;
+\tif ( arg == 3 )  return op(1100)    == res_03;
+\tif ( arg == 4 )  return op(0)       == res_04;
+\tif ( arg == 5 )  return op(-13)     == res_05;
+\tif ( arg == 6 )  return op(1)       == res_06;
+\tif ( arg == 7 )  return op(-17)     == res_07;
+\tif ( arg == 8 )  return op(-65536)  == res_08;
+\tif ( arg == 9 )  return op(255)     == res_09;
+\tif ( arg == 10 ) return op(1000000) == res_10;
+\treturn false;
+    }
+
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type03 {
+    field f: function(type, type): type[];
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr20 {
+  field foo: type = foo(foo);
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class assign10<X> {
+   field f: X[];
+
+   method m(x: X) {
+      f[0] = x;
+      x = f[0];
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; switch statements
+// @Result: TypeMismatch @ 7:13
+
+class type21 {
+    
+    method testm() {
+        switch ( 0 ) {
+            case ( false ) ;
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_int01 {
+    
+    method testm() {
+        local a: int = false ? 0 : 1;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class array_raw03 {
+    method test() {
+        local a = { 0xf, 0b00 };
+        local b = { 0xefef, 0b1100101 };
+        local c = { 07755642, 0b000000000 };
+
+        local av: 8  = a[0];
+        local bv: 16 = b[2];
+        local cv: 32 = b[11];
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component cast1 {
+\tfield f: T = a :: T;
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=4, 2=4, 3=0
+
+component cmpassn04 {
+    field foo: 8 = 0x8;
+    field bar: 8;
+
+    method main(arg: int): int {
+\tbar = (foo >>= 1);
+\tif ( arg == 1 ) return foo :: int;
+\tif ( arg == 2 ) return bar :: int;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class meth05 {
+    method m(a: int) { }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component arith07 {
+    field res_01: 32 = op(0x0f, 0xfe);
+    field res_02: 32 = op(2, -1);
+    field res_03: 32 = op(4, 2);
+    field res_04: 32 = op(0, -1);
+    field res_05: 32 = op(0xf0, 0xaa);
+    field res_06: 32 = op(65535, 345);
+    field res_07: 32 = op(0x10000, 65537);
+    field res_08: 32 = op(64, 8);
+    field res_09: 32 = op(255, 5);
+    field res_10: 32 = op(0xaa, 0x1a);
+
+    method op(a: 32, b: 32): 32 {
+\treturn a ^ b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(0x0f, 0xfe) == res_01;
+\tif ( arg == 2 )  return op(2, -1) == res_02;
+\tif ( arg == 3 )  return op(4, 2) == res_03;
+\tif ( arg == 4 )  return op(0, -1) == res_04;
+\tif ( arg == 5 )  return op(0xf0, 0xaa) == res_05;
+\tif ( arg == 6 )  return op(65535, 345) == res_06;
+\tif ( arg == 7 )  return op(0x10000, 65537) == res_07;
+\tif ( arg == 8 )  return op(64, 8) == res_08;
+\tif ( arg == 9 )  return op(255, 5) == res_09;
+\tif ( arg == 10 ) return op(0xaa, 0x1a) == res_10;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive assignments
+// @Result: TypeMismatch @ 6:15
+
+class type08 {
+    
+    method testm() {
+        local foo: int = false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class List<X> {
+    method add(x: X) {
+    }
+}
+
+component mp_list07 {
+    method test() {
+\tlocal x: List<int> = makeList(0);
+    }
+    method makeList<T>(a: T): List<T> {
+\treturn new List<T>();
+    }
+}
+"
+"
+component Sum {
+    method main(a:int, b:int): int {
+\tlocal sum = 0;
+\tlocal cntr = 0;
+\tsum = a+ b;
+\treturn sum;
+    }
+
+    method toInt(a: char[]): int {
+        local accum = 0;
+        local cntr = 0;
+        local zero = '0'::int;
+
+        for ( ; cntr < a.length; cntr++ ) {
+           local dig = a[cntr]::int;
+           accum = accum * 10 + dig - zero; 
+        }
+
+        return accum;
+     }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component order14 {
+    field order: int[] = { 0, 0, 0, 0 };
+    field pos: int = 0;
+
+    field res_01: int = op(1, 2, 3, 4);
+
+    method op(a: int, b: int, c: int, d: int): int {
+\treturn eval(a, 1) * eval(b, 2) + eval(c, 3) * eval(d, 4);
+    }
+
+    method eval(a: int, n: int): int {
+        order[pos] = n;
+        pos++;
+        return a;
+    }
+}
+
+/* 
+heap {
+    record #0:10:order14 {
+        field order: int[] = #1:int[4];
+        field pos: int = int:4;
+        field res_01: int = int:14;
+    }
+    record #1:4:int[4] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+\tfield 2:int = int:3;
+\tfield 3:int = int:4
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component arith03 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(2, -1);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(-1, 0);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -1);
+    field res_07: int = op(0, -17);
+    field res_08: int = op(255, -12);
+    field res_09: int = op(255, 255);
+    field res_10: int = op(1000, -48576);
+
+    method op(a: int, b: int): int {
+\treturn a * b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:arith03 {
+        field res_01: int = int:-2;
+        field res_02: int = int:-2;
+        field res_03: int = int:1;
+        field res_04: int = int:0;
+        field res_05: int = int:2600;
+        field res_06: int = int:-65535;
+        field res_07: int = int:0;
+        field res_08: int = int:-3060;
+        field res_09: int = int:65025;
+        field res_10: int = int:-48576000;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Result: 0=0; 1=1
+
+component pt_recurse02 {
+\tmethod main(arg: int): int {
+\t\treturn C.m(0, false);
+\t}
+}
+
+class L<T> {
+}
+
+component C {
+\tmethod m<T>(x: T, y: bool): T {
+\t\tif (y) m(null :: (L<T>), y);
+\t\treturn x;
+\t}
+}"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component field08 {
+    field foo: function() = bar;
+    method bar();
+}
+
+/* 
+heap {
+    record #0:1:field08 {
+        field foo: function() = [#0:field08,field08:bar()];
+    }
+} */
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of elements of multidimensional arrays""
+// @Result: TypeMismatch @ 6:11
+
+class array18 {
+    
+    method testm(): int[][] {
+        return new int[2];
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: TypeQuery operator
+// @Result: PASS
+
+class instof02b_obj {
+}
+
+component instof02b {
+    field foo: instof02b_obj = new instof02b_obj();
+    field bar: bool = foo <: instof02b_obj;
+}
+
+/* 
+heap {
+    record #0:2:instof02b {
+        field foo: instof02b_obj = #1:instof02b_obj;
+        field bar: bool = bool:true;
+    }
+    record #1:0:instof02b_obj {
+    }
+}*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class04<X> {
+  field f: X;
+  method m();
+  method n(): X;
+  method o(a: X): X;
+}
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 7:12
+
+class lvalue9 {
+    
+    method testm(): int {
+        switch ( 0 ) {
+            case ( testm() = 2 ) {
+            }
+        }
+        return 0;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class prepost14_obj {
+    field foo: int = 1;
+    field bar: int = inc();
+    method inc(): int {
+\tlocal i = foo;
+\treturn ++i;
+    }
+}
+
+component prepost14 {
+    field foo: prepost14_obj = new prepost14_obj();
+}
+
+/* 
+heap {
+    record #0:1:prepost14 {
+        field foo: prepost14_obj = #1:prepost14_obj;
+    }
+    record #1:2:prepost14_obj {
+        field foo: int = int:1;
+\tfield bar: int = int:2;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_raw02 {
+    
+    method testm() {
+        local a: 12 = false ? 0xafa : 0x0f;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component for06 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        for ( ; ; ) {
+\t    cumul += i++;
+\t    if ( i > max ) return cumul;
+\t}
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:34
+
+class cast06 {
+   method m() {
+      local y = x :: Type<Type<X>, Y>;
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class array_raw02 {
+    field a: 8[] = { 'c', 0b00, 0x4e };
+    field b: 16[] = { 0xefef, 0b1100101, '7', '\
+' };
+    field c: 32[] = { 07755642, 0b000000000, -1, 2009 };
+
+    field av: 8  = a[0];
+    field bv: 16 = b[2];
+    field cv: 32 = b[11];
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 10:17
+
+component type_res13a {
+    field g: int = type_res13b.f;
+}
+
+component type_res13b {
+    field f: unknown[];
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > or operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_or02 {
+    field a: 6;
+    field b: 7;
+    field c: 7 = a | b;
+    field d: 6 = a | b;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class constr08 {
+    constructor(a: int): super(a) { }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class if3 {
+  method m() {
+    local a: int = 0;
+    
+    if ( true ) if ( false ) ;
+
+    if ( true ) if ( false ) ; else ;
+
+    if ( true ) if ( false ) ; else ; else ;
+
+    if ( func(a) ) if ( func(a) ) ;
+
+    if ( func(a) ) if ( func(a) ) ; else ;
+
+    if ( func(a) ) if ( func(a) ) ; else ; else ;
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class virtual03_a {
+    method val(a: int): int { return a+1; }
+}
+
+class virtual03_b extends virtual03_a {
+    method val(a: int): int { return a+2; }
+}
+
+class virtual03_c extends virtual03_a {
+    method val(a: int): int { return a+3; }
+}
+
+component virtual03 {
+    field a: virtual03_a = new virtual03_a();
+    field b: virtual03_a = new virtual03_b();
+    field c: virtual03_a = new virtual03_c();
+    field av: int = a.val(10);
+    field bv: int = b.val(10);
+    field cv: int = c.val(10);
+}
+
+/* 
+heap {
+    record #0:6:virtual03 {
+        field a: virtual03_a = #1:virtual03_a;
+        field b: virtual03_a = #2:virtual03_b;
+        field c: virtual03_a = #3:virtual03_c;
+        field av: int = int:11;
+        field bv: int = int:12;
+        field cv: int = int:13;
+    }
+    record #1:0:virtual03_a {
+    }
+    record #2:0:virtual03_b {
+    }
+    record #3:0:virtual03_c {
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_array03 {
+    method test() {
+\tlocal x = makeArray(0);
+    }
+    method makeArray<X>(a: X): X[] {
+\treturn new X[0];\t
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: return from non-void method must have value
+// @Result: ExpectedReturnType @ 6:6
+
+component return6 {
+    
+    method testm(): return6 {
+        return null;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: character comparison operators
+// @Result: PASS
+
+component comp11 {
+    field res_01: bool = op('a', 'b');
+    field res_02: bool = op('b', 'a');
+    field res_03: bool = op('\
+', '1');
+    field res_04: bool = op('\\377', '0');
+    field res_05: bool = op('\
+', '\
+');
+    field res_06: bool = op('\\377', '\\377');
+    field res_07: bool = op('a', 'A');
+    field res_08: bool = op('A', 'Z');
+    field res_09: bool = op('$', 'z');
+    field res_10: bool = op('z', '~');
+
+    method op(a: char, b: char): bool {
+\treturn a == b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:comp11 {
+        field res_01: bool = bool:false;
+        field res_02: bool = bool:false;
+        field res_03: bool = bool:false;
+        field res_04: bool = bool:false;
+        field res_05: bool = bool:true;
+        field res_06: bool = bool:true;
+        field res_07: bool = bool:false;
+        field res_08: bool = bool:false;
+        field res_09: bool = bool:false;
+        field res_10: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=13, 3=42
+
+component default03a {
+    field foo: int[];
+    field bar: bool = foo == null;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo == null ? 13 : 10;
+\tif ( arg == 2 ) return bar ? 13 : 10;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Self<T> {
+    method foo(): T;
+}
+
+class A extends Self<A> {
+    method foo(): A { return this; }
+}
+
+class B extends Self<B> {
+    method foo(): B { return this; }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=14, 3=15, 4=42
+
+class array13_obj {
+    field foo: int;
+    constructor(i: int) { foo = i; }
+}
+
+component array13 {
+    field i: array13_obj = new array13_obj(13);
+    field j: array13_obj = new array13_obj(14);
+    field k: array13_obj = new array13_obj(15);
+    field m: array13_obj = new array13_obj(42);
+
+    field a: array13_obj[][] =  { {i}, {j, k} };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a[0][0].foo;
+\tif ( arg == 2 ) return a[1][0].foo;
+\tif ( arg == 3 ) return a[1][1].foo;
+\treturn 42;
+    }
+
+    method getf(i: int): array13_obj[] {
+\treturn a[i];
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component default06a {
+    field foo: char;
+    field bar: char = foo;
+}
+
+/* 
+heap {
+    record #0:2:default06a {
+        field foo: char = char:0;
+        field bar: char = char:0;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+component cmpassn03 {
+    field foo: int = 2;
+    field bar: int = foo *= 2;
+}
+
+/* 
+heap {
+    record #0:2:cmpassn03 {
+        field foo: int = int:4;
+        field bar: int = int:4;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: typechecking of if conditionals
+// @Result: PASS
+
+class type55 {
+    
+    method testm(a: int) {
+        if ( a == 0 ) ;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component for03 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i: int, cumul = 0;
+        for ( i = 1; ; i++ ) {
+\t    cumul += i;
+\t    if ( i == max ) break;
+\t}
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:for03 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component switch16 {
+    field foo: int;
+
+    constructor() {
+\tds(3);
+    }
+
+    method ds(v: int) {
+\tswitch ( v ) {
+\t    case ( 0 ) foo = 10;
+\t    case ( 2 ) foo = 13;
+\t    case ( 5, 8, 7 ) foo = 20;
+\t    case ( 1 ) foo = 11;
+\t    case ( 3, 4 ) foo = 15;
+\t    default foo = -1;
+        }
+    }
+}
+
+/* 
+heap {
+    record #0:1:switch16 {
+        field foo: int = int:15;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=0, 1=1, 2=0, 3=1, 4=0, 5=1, 6=0, 7=0
+
+component array15 {
+    field a: bool[][] =  { {true, false}, {true}, {false, true, false} };
+
+    method getf(b: bool[], i: int): bool {
+\treturn b[i];
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return getf(a[0], 0);
+\tif ( arg == 2 ) return getf(a[0], 1);
+\tif ( arg == 3 ) return getf(a[1], 0);
+\tif ( arg == 4 ) return getf(a[2], 0);
+\tif ( arg == 5 ) return getf(a[2], 1);
+\tif ( arg == 6 ) return getf(a[2], 2);
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: TypeMismatch @ 7:39
+
+class int_raw02 {
+    field x: int;
+    field a: 31 = x;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class new10<X> {
+   method m() {
+      local f = new X[1];
+   }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component constr03 {
+    constructor(a: int) { }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component switch03 {
+    field foo: int = ds(2);
+
+    method ds(v: int): int {
+\tswitch ( v ) {
+\t    case ( 0 ) return 10;
+\t    case ( 1 ) return 11;
+\t    case ( 2 ) return 12;
+\t    case ( 3 ) return 13;
+\t    case ( 4, 5 ) return 15;
+\t    case ( 7, 8, 9 ) return 20;
+\t    default return -1;
+        }
+    }
+}
+
+/* 
+heap {
+    record #0:1:switch03 {
+        field foo: int = int:12;
+    }
+} */
+"
+"program TestMe {
+   entrypoint main = TestMe.main;
+   entrypoint timer0_comp = TestMe.intr1;
+}
+component TestMe {
+       method main(): void {
+               while (true) {
+                       computeValue();
+                       transmitValue();
+               }
+       }
+       method computeValue(a:int, b:int, c:int): void {
+               // do something for a long time
+       }
+       method transmitValue(): void {
+           local buffer:int;
+           if (atomic_swap(sending, true)) 
+    \t\t\treturn;
+           buffer = checks(a,b,c);
+           sending = false;
+\t\t\treturn buffer;
+       }
+       field sending : false;
+       method intr1(): void {
+               transmitValue();
+       }
+       Method checks(x:int, y:int, z:int):int {
+\t\t\tif(x<100 && y == 0){
+            \tif(x>0 && z= pow(x,3)+31){
+\t       \t\t\tif(x<-5){
+                      \treturn double(-x);
+              \t\t}
+              \t\treturn 5;
+          \t\t}
+          \t\treturn return double(x)
+       \t\t}
+       \t}  
+      Method double(x: int):int{
+         Return 2*x;
+      }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component arith04 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(2, -1);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(0, -1);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -1);
+    field res_07: int = op(13455, -17);
+    field res_08: int = op(64, 8);
+    field res_09: int = op(255, 5);
+    field res_10: int = op(-48576, 1000);
+
+    method op(a: int, b: int): int {
+\treturn a / b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(1, -2) == res_01;
+\tif ( arg == 2 ) return op(2, -1) == res_02;
+\tif ( arg == 3 ) return op(-1, -1) == res_03;
+\tif ( arg == 4 ) return op(0, -1) == res_04;
+\tif ( arg == 5 ) return op(-200, -13) == res_05;
+\tif ( arg == 6 ) return op(65535, -1) == res_06;
+\tif ( arg == 7 ) return op(13455, -17) == res_07;
+\tif ( arg == 8 ) return op(64, 8) == res_08;
+\tif ( arg == 9 ) return op(255, 5) == res_09;
+\tif ( arg == 10 ) return op(-48576, 1000) == res_10;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class array_char01 {
+    field a: char[] = { \'\
+\', \'0\', \'\\\'\', \' \', \'\
+\' };
+    field b: char[] = ""fooo$&^*!@#"";
+    field c: char[] = ""\\"""";
+
+    field av: char = a[0];
+    field bv: char = ""longstring""[2];
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; new operator
+// @Result: ExpectedObjectType @ 6:9
+
+component type14 {
+    
+    method testm() {
+        new type14();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: operation of instanceof construct
+// @Result: PASS
+
+class instof03_a {
+}
+
+class instof03_b extends instof03_a {
+}
+
+component instof03 {
+    field foo: instof03_a = new instof03_a();
+    field bar: bool = foo instanceof instof03_b;
+}
+
+/* 
+heap {
+    record #0:2:instof03 {
+        field foo: instof03_a = #1:instof03_a;
+        field bar: bool = bool:false;
+    }
+    record #1:0:instof03_a {
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: method resolution
+// @Result: UnresolvedIdentifier @ 11:5
+
+class method_res06_a {
+    
+    private method priv() {
+    }
+}
+class method_res06_b extends method_res06_a {
+    
+    method testm() {
+        priv();
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: compile-time constants for primitive types
+// @Result: 0=0, 1=1, 2=0, 3=1, 4=1, 5=0, 6=0, 7=0
+
+component const03 {
+    field a: bool = true;
+    field b: bool = false;
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return a;
+\tif ( arg == 2 ) return b;
+\tif ( arg == 3 ) return a == true;
+\tif ( arg == 4 ) return b == false;
+\tif ( arg == 5 ) return a == false;
+\tif ( arg == 6 ) return b == true;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: CannotInferTypeParam @ 9:18
+
+component mp_delegate01 {
+    method makeArray<X>(a: X): X[] {
+\treturn new X[0];\t
+    }
+    method test() {
+\tlocal x = makeArray;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: ExpectedVarType @ 8:19
+
+class local3 {
+    
+    method testm() {
+        local foo = bar();
+    }
+
+    method bar() {
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:26
+
+class instof03 {
+   method m() {
+      if ( x <: Type<int> ) ;
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: BuiltinRedefined @ 5:7
+
+class bool {
+    field foo : int;
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0; 1=1
+
+component pt_recurse04 {
+\tmethod main(arg: int): int {
+\t\treturn C.m(0, false);
+\t}
+}
+
+class L<T> {
+}
+
+component C {
+\tmethod m<T>(x: T, y: bool): T {
+\t\tif (y) m(new L<T>(), y);
+\t\treturn x;
+\t}
+}"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class A<X> { } 
+class B<X> extends A<int> { }
+
+class instof14 {
+   method m<T>(x: A<T>) {
+      local f = x <: (B<char>);
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=0
+
+component raw_flip03 {
+    field res_01: 16 = flip(0x0ffe);
+    field res_02: 16 = flip(0x0002);
+    field res_03: 16 = flip(0x0001);
+    field res_04: 16 = flip(0x8000);
+    field res_05: 16 = flip(0xf007);
+    field res_06: 16 = flip(0x8877);
+    field res_07: 16 = flip(0xaa01);
+
+    method flip(a: 16): 16 {
+\treturn (a :: 8) # ((a >> 8) :: 8);
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return flip(0x0ffe) == res_01;
+\tif ( arg == 2 ) return flip(0x0002) == res_02;
+\tif ( arg == 3 ) return flip(0x0001) == res_03;
+\tif ( arg == 4 ) return flip(0x8000) == res_04;
+\tif ( arg == 5 ) return flip(0xf007) == res_05;
+\tif ( arg == 6 ) return flip(0x8877) == res_06;
+\tif ( arg == 7 ) return flip(0xaa01) == res_07;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class ovr_method02_a extends ovr_method02_b<int> {
+  method f(): int;
+}
+
+class ovr_method02_b<X> {
+  method f(): X;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > auto extension
+// @Result: TypeMismatch @ 7:19
+
+class raw_assn11 {
+    field a: 64;
+    field b: 63 = a;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class assign01<X> {
+   field f: X;
+   field g: X = f;
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=49, 2=50, 3=104, 4=101, 5=104, 6=42
+
+component alloc_array03 {
+    field a: char[] = array1();
+    field b: char[] = array2();
+
+    method array1(): char[] {
+\tlocal arr = {\'1\',\'2\'};
+        return arr;
+    }
+    method array2(): char[] {
+        return ""heh"";
+    }
+
+
+    method main(arg: int): char {
+\tif ( arg == 1 ) return a[0];
+\tif ( arg == 2 ) return a[1];
+\tif ( arg == 3 ) return b[0];
+\tif ( arg == 4 ) return b[1];
+\tif ( arg == 5 ) return b[2];
+\treturn \'*\';
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: TypeCast operator
+// @Result: TypeCheckException @ 16:31
+
+class cast05_a {
+}
+
+class cast05_b extends cast05_a {
+}
+
+class cast05_c extends cast05_a {
+}
+
+component cast05 {
+    field foo: cast05_a = new cast05_c();
+    field bar: cast05_b = foo :: cast05_b;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Transform<R, E> {
+    method visitA(n: A, e: E): R;
+    method visitB(n: B, e: E): R;
+}
+
+class A {
+    method accept<R, E>(v: Transform<R, E>, e: E): R { return v.visitA(this, e); }
+}
+
+class B {
+    method accept<R, E>(v: Transform<R, E>, e: E): R { return v.visitB(this, e); }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_method05_a<X> extends inh_method05_b<X, int> {
+  field h: X = f();
+}
+
+class inh_method05_b<Y, Z> {
+  method f(): Y;
+  method g(): Z;
+}
+"
+"/*
+ * This program implements a simple doubly-linked list. This
+ * program performs some simple operations on linked lists
+ * and is used to measure the performance overhead of compiler
+ * optimizations.
+ *
+ * @author Ben L. Titzer
+ */
+program LinkedList {
+\tentrypoint main = LinkedList.start;
+}
+
+component LinkedList {
+
+\tfield list: List;
+\tfield finder: Finder;
+
+\tconstructor() {
+\t\tfinder = new Finder();
+\t\tlist = new List();
+\t\tlist.add(new Data(0));
+\t\tlist.add(new Data(1));
+\t\tlist.add(new Data(2));
+\t\tlist.add(new Data(3));
+\t\tlist.add(new Data(4));
+\t\tlist.add(new Data(5));
+\t\tlist.add(new Data(6));
+\t\tlist.add(new Data(7));
+\t\tlist.add(new Data(8));
+\t\tlist.add(new Data(9));
+\t\tlist.add(new Data(10));
+\t\tlist.add(new Data(11));
+\t\tlist.add(new Data(12));
+\t}
+
+\tmethod start() {
+\t\tlocal i: int;
+\t\tfor (i = 0; i < 1000; i++ ) {
+\t\t\tfinder.reset(7);
+\t\tlist.apply(print);
+\t\t\tlist.apply(finder.compare);
+\t\t\tlist.apply(print);
+\t\t}
+\t}
+
+\tmethod print(d: Data) {
+\t// do nothing
+\t}
+}
+
+class List {
+\tfield head: Link;
+\tfield tail: Link;
+
+\tmethod add(d: Data) {
+\t\tif ( head == null ) {
+\t\t\thead = tail = new Link(d);
+\t\t} else {
+\t\t\tlocal next = new Link(d);
+\t\t\ttail.next = next;
+\t\t\tnext.prev = tail;
+\t\ttail = tail.next;
+\t\t}
+\t}
+
+\tmethod apply(f: function(Data)) {
+\t\tlocal pos = head;
+\t\twhile ( pos != null ) {
+\t\t\tf(pos.data);
+\t\t\tpos = pos.next;
+\t\t}
+\t}
+
+\tmethod applyRev(f: function(Data)) {
+\t\tlocal pos = tail;
+\t\twhile ( pos != null ) {
+\t\t\tf(pos.data);
+\t\t\tpos = pos.prev;
+\t\t}
+\t}
+}
+
+class Link {
+\tfield data: Data;
+\tfield next: Link;
+\tfield prev: Link;
+
+\tconstructor(d: Data) {
+\t\tdata = d;
+\t}
+
+\tmethod insert(d: Data) {
+\t\tlocal next = new Link(d);
+\t\tnext.next = this.next;
+\t\tthis.next.prev = next;
+\t\tthis.next = next;
+\t}
+}
+
+class Data {
+\tfield val: int;
+\tconstructor(i: int) {
+\t\tval = i;
+\t}
+}
+
+class Finder {
+\tfield found: boolean;
+\tfield val: int;
+\tfield index: int;
+
+\tmethod compare(d: Data) {
+\t\tif ( !found ) {
+\t\t\tindex++;
+\t\t\tif ( val == d.val ) found = true;
+\t\t}
+\t}
+
+\tmethod reset(v: int) {
+\t\tval = v;
+\t\tfound = false;
+\t\tindex = 0;
+\t}
+}"
+"// @Harness: v2-init
+// @Test: operation of instanceof construct
+// @Result: PASS
+
+class instof05_a {
+}
+
+class instof05_b extends instof05_a {
+}
+
+class instof05_c extends instof05_a {
+}
+
+component instof05 {
+    field foo: instof05_a = new instof05_c();
+    field bar: bool = foo instanceof instof05_b;
+}
+
+/* 
+heap {
+    record #0:2:instof05 {
+        field foo: instof05_a = #1:instof05_c;
+        field bar: bool = bool:false;
+    }
+    record #1:0:instof05_c {
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component sort02 {
+
+    method test() {
+\tlocal a = { 0, 21, 2, 34, 5, 6, 68, -11, -90 };
+\tsort(a, int_gt);
+    }
+
+    method int_gt(i: int, j: int): bool {
+\treturn i > j;
+    }
+
+    method sort<T>(a: T[], gt: function(T, T): bool) {
+        local i: int, j: int, len = a.length;
+        for ( i = 0; i < len; i++ ) {
+            for ( j = i+1; j < len; j++ ) {
+                if ( gt(a[i], a[j]) ) {
+                   local t = a[i];
+                   a[i] = a[j];
+                   a[j] = t;
+                }
+            }
+        }
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component dowhile08 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0, loop = 1;
+        do {
+            for ( i = 1; ; cumul += i, i++ ) {
+\t        if ( i > max ) break;
+\t        else continue;
+\t    }
+\t} while (++loop < 2);
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:dowhile08 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=32, 5=97, 6=42
+
+class Pair<X, Y> {
+    field a: X;
+    field b: Y;
+
+    constructor(x: X, y: Y) {
+        a = x;
+        b = y;
+    }
+}
+
+class I {
+    field val: int;
+    constructor(v: int) {
+        val = v;
+    }
+}
+
+component ptex_pair02 {
+    field a: Pair<int, Pair<bool, bool> > = new Pair<int, Pair<bool, bool> >(11, new Pair<bool, bool>(true, false));
+    field b: Pair<int, I> = new Pair<int, I>(21, new I(31));
+    field c: Pair<function(): int, char> = new Pair<function(): int, char>(f32, 'a');
+
+    method main(arg: int): int {
+        if ( arg == 1 ) return a.a;
+        if ( arg == 2 ) return b.a;
+        if ( arg == 3 ) return b.b.val;
+        if ( arg == 4 ) return c.a();
+        if ( arg == 5 ) return c.b;
+\treturn 42;
+    }
+
+    method f32(): int { return 32; }
+}
+"
+"// @Harness: v2-init
+// @Test: compile-time constants for primitive types
+// @Result: PASS
+
+component const_str01 {
+    field str_1: char[] = """";
+    field str_2: char[] = ""\
+\\t\\b\\r\\""\\377"";
+}
+
+/* 
+heap {
+    record #0:2:const_str01 {
+        field str_1: char[] = #1:char[0];
+        field str_2: char[] = #2:char[6];
+    }
+    record #1:0:char[0] {
+    }
+    record #2:6:char[6] {
+        field 0:char = char:10;
+        field 1:char = char:9;
+        field 2:char = char:8;
+        field 3:char = char:13;
+        field 4:char = char:34;
+        field 5:char = char:255;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=42, 1=13, 2=14, 3=15, 4=16, 5=42
+
+component comp12 {
+
+    field a: int = 13;
+    field b: int = 14;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a;
+\tif ( arg == 2 ) return b;
+\tif ( arg == 3 ) return comp12_b.c;
+\tif ( arg == 4 ) return comp12_b.d;
+\treturn 42;
+    }
+}
+
+component comp12_b {
+    field c: int = 15;
+    field d: int = 16;
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=1, 12=0
+
+component arith06 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(2, -1);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(-1, 0);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -1);
+    field res_07: int = op(13, -17);
+    field res_08: int = op(255, -12);
+    field res_09: int = op(255, 255);
+    field res_10: int = op(1000000, -48576);
+    field res_11: int = op(2147483647, 1);
+
+    method op(a: int, b: int): int {
+\treturn a - b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return (1 - -2)           == res_01;
+\tif ( arg == 2 )  return (2 - -1)           == res_02;
+\tif ( arg == 3 )  return (-1 - -1)          == res_03;
+\tif ( arg == 4 )  return (-1 - 0)           == res_04;
+\tif ( arg == 5 )  return (-200 - -13)       == res_05;
+\tif ( arg == 6 )  return (65535 - -1)       == res_06;
+\tif ( arg == 7 )  return (13 - -17)         == res_07;
+\tif ( arg == 8 )  return (255 - -12)        == res_08;
+\tif ( arg == 9 )  return (255 - 255)        == res_09;
+\tif ( arg == 10 ) return (1000000 - -48576) == res_10;
+\tif ( arg == 11 ) return (2147483647 - 1)   == res_11;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 0=0, 1=1, 2=3, 3=5, 4=0
+
+class A { }
+class B extends A { }
+class C extends A { }
+class D { }
+class E extends D { }
+
+component instof10 {
+
+    field a: A = new A();
+    field b: B = new B();
+    field c: C = new C();
+
+    method main(arg: int): int {
+\tlocal x: A = getObj(arg);
+\tlocal r = 0;
+\tif ( x <: A ) r += 1;
+\tif ( x <: B ) r += 2;
+\tif ( x <: C ) r += 4;
+\treturn r;
+    }
+
+    method getObj(arg: int): A {
+\tif ( arg == 1 ) return a;
+\tif ( arg == 2 ) return b;
+\tif ( arg == 3 ) return c;
+\treturn null;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Visitor<E> {
+    method visitA(n: A, e: E);
+    method visitB(n: B, e: E);
+}
+
+class S {
+    method accept<E>(v: Visitor<E>, e: E);
+}
+
+class A extends S {
+    method accept<E>(v: Visitor<E>, e: E) { v.visitA(this, e); }
+}
+
+class B extends S {
+    method accept<E>(v: Visitor<E>, e: E) { v.visitB(this, e); }
+}
+
+class Thief<E> extends Visitor<E> {
+    method visitA(n: A, e: E) {
+    }
+    method visitB(n: B, e: E) {
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: return statement
+// @Result: PASS
+
+component return01 {
+    
+    field x: int;
+
+    constructor() {
+\tm();
+    }
+
+    method m() {
+\tx = 11;
+\treturn;
+    }
+}
+
+/* 
+heap {
+    record #0:1:return01 {
+        field x: int = int:11;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class constr06 {
+    constructor(): super() { }
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: ExpectedVarType @ 8:19
+
+class local5 {
+    
+    method testm() {
+        local foo: local5c;
+    }
+}
+
+component local5c {
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component dowhile02 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        do cumul += i++; while ( i <= max );
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:dowhile02 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class instof07b {
+   method m() {
+      if ( x <: (Type<function(), Y>) ) ;
+   }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class01<X> {
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_char02 {
+    
+    method testm() {
+        local a = { '0', '1' };
+\tlocal b: char[] = a;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator
+// @Result: PASS
+
+component eval_or01 {
+    field f1: 4  = 0x0 | 0xf;
+    field f2: 8  = 0xf0 | 0x0f;
+    field f3: 16 = 0xf3f3 | 0x1111;
+    field f4: 7  = 0b1110101 | 0b1111111;
+    field f5: 5  = 0b10101 | 0b10000;
+    field f6: 3  = 0b101 | 0b100;
+    field f7: 32 = 0xFFFF0000 | 0xF000F000;
+    field f8: 48 = 0xFF00FFFF0000 | 0xF000F000F000;
+    field f9: 64 = 0xFFFF0000FFFF0000 | 0xF000F000F000F000;
+}
+
+/*
+heap {
+    record #0:1:eval_or01 {
+\tfield f1: 4  = raw.4:0xf; 
+\tfield f2: 8  = raw.8:0xff; 
+\tfield f3: 16 = raw.16:0xf3f3; 
+\tfield f4: 7  = raw.7:0x7f;
+\tfield f5: 5  = raw.5:0x15; 
+\tfield f6: 3  = raw.3:0x5; 
+\tfield f7: 32 = raw.32:0xfffff000; 
+\tfield f8: 48 = raw.48:0xff00fffff000; 
+\tfield f9: 64 = raw.64:0xfffff000fffff000; 
+    }
+}
+*/
+"
+"// @Harness: v2-seman
+// @Result: CannotOverrideReturnType @ 14:38
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+}
+
+class PairFactory {
+  method makePair<X, Y>(x: X, y: Y): Pair<X, Y>;
+}
+
+class NewPairFactory extends PairFactory {
+  method makePair<X, Y>(x: X, y: Y): Pair<Y, X>;
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=14, 5=42
+
+component ptex_meth08 {
+
+    method main(arg: int): int {
+        local f: function(int): int = id;
+    \tif ( arg == 1 ) return apply(11, f);
+    \tif ( arg == 2 ) return apply(12, f);
+    \tif ( arg == 3 ) return apply(id(13), id(f));
+    \tif ( arg == 4 ) return apply(id3(14), id3(f));
+        return 42;
+    }
+
+    method apply<T>(x: T, f: function(T): T): T { 
+\treturn f(x);
+    }
+
+    method id<T>(x: T): T { return x; }
+    method id3<T>(x: T): T { return id(id(id(x))); }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > and operator
+// @Result: PASS
+
+class raw_and01 {
+    field a: 1;
+    field b: 2;
+    field c: 2 = a & b;
+    field d: 2 = b & a;
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42, 5=11, 6=21, 7=31, 8=42
+
+class delegate01_a {
+    method val(): int { return 11; }
+}
+
+class delegate01_b extends delegate01_a {
+    method val(): int { return 21; }
+}
+
+class delegate01_c extends delegate01_a {
+    method val(): int { return 31; }
+}
+
+component delegate01 {
+    field a: delegate01_a = new delegate01_a();
+    field b: delegate01_a = new delegate01_b();
+    field c: delegate01_a = new delegate01_c();
+    field am: function():int = a.val;
+    field bm: function():int = b.val;
+    field cm: function():int = c.val;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return am();
+\tif ( arg == 2 ) return bm();
+\tif ( arg == 3 ) return cm();
+
+        local m = m42;
+\tif ( arg == 5 ) m = a.val;
+\tif ( arg == 6 ) m = b.val;
+\tif ( arg == 7 ) m = c.val;
+
+\treturn m();
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: conversion between raw types of various sizes
+// @Result: PASS
+
+component raw_raw02 {
+    field a: 32 = 0xffffffff;
+    field b: 24 = a :: 24;
+    field c: 16 = a :: 16;
+    field d: 12 = a :: 12;
+    field e: 8  = a :: 8;
+    field f: 4  = a :: 4;
+    field g: 3  = a :: 3;
+    field h: 1  = a :: 1;
+}
+
+/* 
+heap {
+    record #0:14:raw_raw02 {
+        field a: 32 = raw.32:0xffffffff;
+        field b: 24 = raw.24:0xffffff;
+        field c: 16 = raw.16:0xffff;
+        field d: 12 = raw.12:0xfff;
+        field e: 8  = raw.8:0xff;
+        field f: 4  = raw.4:0xf;
+        field g: 3  = raw.3:0x7;
+        field h: 1  = raw.1:0x1;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: VariableNotInitialized @ 10:12
+
+class dowhile_init02 {
+    
+    method testm(p: bool) {
+        local foo: bool;
+        do {
+            if ( p ) break;
+        }
+        while ( p or (foo = p) );
+        testm(foo);
+    }
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class C<X> {
+  field h: X;
+}
+
+component mp_init05 {
+  field f: C<int> = makeC();
+  field g: C<char> = makeC();
+
+  method makeC<T>(): C<T> {
+    return new C<T>();
+  }
+}
+
+/*
+heap {
+  record #0:2:mp_init05 {
+    field f: C<int> = #1:C<int>;
+    field g: C<char> = #2:C<char>;
+  }
+  record #1:0:C<int> {
+    field h: int = int:0;
+  }
+  record #2:0:C<char> {
+    field h: char = char:0;
+  }
+}
+*/
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 0=1, 1=1, 2=1, 3=3, 4=3, 5=5, 6=5, 7=7
+
+class A { }
+class B extends A { }
+class C extends A { }
+class D { }
+class E extends D { }
+
+component cast04 {
+
+    field arr: A[] = { new A(), new A(), new A(), new B(), new B(), new C(), new C() };
+    field d: D = new D();
+    field e: D = new E();
+
+    method main(arg: int): int {
+\tlocal x: A = getObj(arg);
+\tlocal r = 0;
+\tif ( x <: A or x == null ) { local y = x :: A; r += 1; }
+\tif ( x <: B or x == null ) { local y = x :: B; r += 2; }
+\tif ( x <: C or x == null ) { local y = x :: C; r += 4; }
+\treturn r;
+    }
+
+    method getObj(arg: int): A {
+\tif ( arg < arr.length ) return arr[arg];
+\treturn null;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class cmpassn23_obj {
+    field x: 16 = 0x1984;
+    field y: 16 = 0x2001;
+    constructor() {
+\tx ^= y ^= x ^= y;
+    }
+}
+
+component cmpassn23 {
+    field foo: cmpassn23_obj = new cmpassn23_obj();
+}
+
+/* 
+heap {
+    record #0:1:cmpassn23 {
+        field foo: cmpassn23_obj = #1:cmpassn23_obj;
+    }
+    record #1:2:cmpassn23_obj {
+        field x: int = raw.16:0x0000;
+        field y: int = raw.16:0x1984;
+    }
+}*/
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class pv02_a {
+    method getf(): int { return val(); }
+    private method val(): int { return 1; }
+}
+
+class pv02_b extends pv02_a {
+    private method val(): int { return 2; }
+}
+
+class pv02_c extends pv02_a {
+    private method val(): int { return 3; }
+}
+
+component pv02 {
+    field av: int = new pv02_a().getf();
+    field bv: int = new pv02_b().getf();
+    field cv: int = new pv02_c().getf();
+}
+
+/* 
+heap {
+    record #0:3:pv02 {
+        field av: int = int:1;
+        field bv: int = int:1;
+        field cv: int = int:1;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: ExpectedObjectType @ 4:24
+
+class inh03<X> extends X {
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_id13 {
+    method test() {
+\tlocal x = new int[8];
+\tx[id('0')] = 0;
+    }
+    method id<X>(x: X): X {
+\treturn x;\t
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking of operators
+// @Result: PASS
+
+class unify_null01 {
+  method testm(a: unify_null01, b: boolean) {
+    a = b ? this : null;
+    a = b ? null : this;
+    a = b ? null : null;
+    a = null;
+    a = this;
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg13_a {
+    method val(): int { return 1; }
+}
+
+class dg13_b extends dg13_a {
+    method val(): int { return 2; }
+}
+
+component dg13 {
+    field a: function():int = new dg13_a().val;
+    field b: function():int = new dg13_b().val;
+    field c: function():int = bar;
+    field av: int;
+    field bv: int;
+    field cv: int;
+    field dv: int;
+
+    constructor() {
+\tlocal f: function(): int;
+\tf = a; av = val(f);
+\tf = b; bv = val(f);
+\tf = c; cv = val(f);
+\tdv = val(null);
+    }
+
+    method val(f: function(): int): int {
+\tif ( f == a ) return 11;
+\tif ( f == b ) return 21;
+\tif ( f == c ) return 31;
+\tif ( f == null ) return 42;
+\treturn 77;
+    }
+    method bar(): int {
+\treturn 3;
+    }
+
+}
+
+/* 
+heap {
+    record #0:7:dg13 {
+        field a: function():int = [#1:dg13_a,dg13_a:val()];
+        field b: function():int = [#2:dg13_b,dg13_b:val()];
+        field c: function():int = [#0:dg13,dg13:bar()];
+        field av: int = int:11;
+        field bv: int = int:21;
+        field cv: int = int:31;
+        field dv: int = int:42;
+    }
+    record #1:0:dg13_a {
+    }
+    record #2:0:dg13_b {
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking of array initializers
+// @Result: TypeMismatch @ 6:15 
+
+class type57 {
+    
+    method testm() {
+        local a: int[] = { false };
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class while4 {
+  method m() {
+     local a: int = 9;
+     local foo: bool = false;
+
+     while ( true ) {
+       local x = a;
+
+       while ( true ) {
+         local y = a;
+       }
+
+       while ( foo ) {
+         local y = a;
+         x = x + 1;
+       }
+
+     }
+  }
+}
+"
+"// @Harness: v2-seman
+// @Test: function (() -> int)[]
+// @Result: PASS
+
+class type_func04 {
+    field a: (function(): int)[];
+    method testm(b: (function(): int)[]) { a = b; }
+}
+"
+"// @Harness: v2-seman
+// @Test: lvalue correctness (pre-increment operator)
+// @Result: NotAnLvalue @ 7:10
+
+class lvalue18 {
+    
+    method testm(): int {
+        2 = testm();
+        return 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; new operator
+// @Result: TypeMismatch @ 14:15
+
+class type62_obj {
+    method foo(): int {
+\treturn 0;
+    }
+}
+
+component type62 {
+    
+    method testm(): bool {
+        return new type62_obj().foo();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 8:12
+
+class init04 {
+    
+    method testm(): int {
+        local foo: int;
+        if ( true ) foo = 0;
+        return foo;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 0
+
+class ch05b {
+    field A: int;
+    field B: int;
+    field R: int;
+
+    method choose(c: bool, a: int, b: int) {
+\tif ( c ) R = A = a;
+\telse R = B = b;
+    }
+}
+
+component if05b {
+    
+    field res_01: ch05b = new ch05b();
+    field res_02: ch05b = new ch05b();
+
+    // res_01.A = 160;
+    // res_01.B = 0;
+    // res_01.R = 160;
+    // res_02.A = 0;
+    // res_02.B = 24;
+    // res_02.R = 24;
+
+    method main(arg: int): int {
+\tres_01.choose(true, 160, 42);
+        res_02.choose(false, 100, 24);
+\treturn res_01.B;
+    }
+
+}
+
+"
+"// @Harness: v2-seman
+// @Test: typechecking success
+// @Result: PASS
+
+class int_add04 {
+    
+    method testm(a: int): int {
+        return a + 2;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: shift left operator, boundary cases
+// @Result: 0=0, 1=1, 0=0
+
+component raw_shlx01 {
+    field res_01: 32 = op(64, 32);
+
+    method op(a: 32, b: int): 32 {
+\treturn a << b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(64, 32) == res_01;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class virtual01_a {
+    method val(): int { return 1; }
+}
+
+class virtual01_b extends virtual01_a {
+    method val(): int { return 2; }
+}
+
+class virtual01_c extends virtual01_a {
+    method val(): int { return 3; }
+}
+
+component virtual01 {
+    field a: virtual01_a = new virtual01_a();
+    field b: virtual01_a = new virtual01_b();
+    field c: virtual01_a = new virtual01_c();
+    field av: int = a.val();
+    field bv: int = b.val();
+    field cv: int = c.val();
+}
+
+/* 
+heap {
+    record #0:6:virtual01 {
+        field a: virtual01_a = #1:virtual01_a;
+        field b: virtual01_a = #2:virtual01_b;
+        field c: virtual01_a = #3:virtual01_c;
+        field av: int = int:1;
+        field bv: int = int:2;
+        field cv: int = int:3;
+    }
+    record #1:0:virtual01_a {
+    }
+    record #2:0:virtual01_b {
+    }
+    record #3:0:virtual01_c {
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+
+  method first(): X {
+    return a;
+  }
+
+  method second(): Y {
+    return b;
+  }
+}
+
+component Client {
+  method test() {
+    local p = new Pair<int, bool>();
+    local b = p.a;
+    local c = p.b;
+  }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=32, 2=32, 3=0
+
+component cmpassn05 {
+    field foo: 8 = 0x8;
+    field bar: 8;
+
+    method main(arg: int): int {
+\tbar = (foo <<= 2);
+\tif ( arg == 1 ) return foo :: int;
+\tif ( arg == 2 ) return bar :: int;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > binary constants
+// @Result: TypeMismatch @ 6:18
+
+class raw_bin05 {
+    field a: 4 = 0b11101;
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component while02 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( i <= max ) cumul += i++;
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:while02 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Self<T> {
+}
+
+class Myself extends Self<Myself> {
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_raw03 {
+    
+    method testm() {
+        local a = { 0xfa, 0x0f };
+        local b: 8[] = a;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: UnresolvedType @ 4:20
+
+class inh2 extends unknown {
+    field testf: int;
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 7:5
+
+class unreach12 {
+    
+    method testm(): int {
+        return 1;
+        return 2;
+        local foo: int = 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class char_raw05 {
+    field a: char;
+    field b: 8 = m(a);
+    field c: 16 = m(a);
+    field d: 32 = m(a);
+    field e: 64 = m(a);
+    method m(x: char): char { return x; }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 0
+
+class ch04d {
+    field A: int;
+    field B: int;
+    field R: int;
+
+    method choose(c: bool, a: int, b: int) {
+\tR = c ? (A = a) : (B = b);
+    }
+}
+
+component if04d {
+    
+    field res_01: ch04d = new ch04d();
+    field res_02: ch04d = new ch04d();
+
+    // res_01.A = 160;
+    // res_01.B = 0;
+    // res_01.R = 160;
+    // res_02.A = 0;
+    // res_02.B = 24;
+    // res_02.R = 24;
+
+    method main(arg: int): int {
+\tres_01.choose(true, 160, 42);
+        res_02.choose(false, 100, 24);
+\treturn res_02.A;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > auto extension
+// @Result: TypeMismatch @ 7:19
+
+class raw_assn10 {
+    field a: 40;
+    field b: 32 = a;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type01 {
+    field f: type;
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 160
+
+class ch04c {
+    field A: int;
+    field B: int;
+    field R: int;
+
+    method choose(c: bool, a: int, b: int) {
+\tR = c ? (A = a) : (B = b);
+    }
+}
+
+component if04c {
+    
+    field res_01: ch04c = new ch04c();
+    field res_02: ch04c = new ch04c();
+
+    // res_01.A = 160;
+    // res_01.B = 0;
+    // res_01.R = 160;
+    // res_02.A = 0;
+    // res_02.B = 24;
+    // res_02.R = 24;
+
+    method main(arg: int): int {
+\tres_01.choose(true, 160, 42);
+        res_02.choose(false, 100, 24);
+\treturn res_01.R;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 31
+
+class virtual02c_1 {
+    method val() { virtual02c.R = 11; }
+}
+
+class virtual02c_2 extends virtual02c_1 {
+    method val() { virtual02c.R = 21; }
+}
+
+class virtual02c_3 extends virtual02c_2 {
+    method val() { virtual02c.R = 31; }
+}
+
+component virtual02c {
+    field a: virtual02c_1 = new virtual02c_1();
+    field b: virtual02c_1 = new virtual02c_2();
+    field c: virtual02c_1 = new virtual02c_3();
+    field R: int;
+
+    method main(arg: int): int {
+\tc.val();
+\treturn R;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type10<X, Y> {
+    field f: type10<X, Y>[][];
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeQuery (instanceof) operation
+// @Result: PASS
+
+class instof01a {
+    field bar: instof01a;
+    field foo: bool = bar instanceof instof01a;
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class C<X> {
+  field g: X;
+}
+
+component init02 {
+  field f: C<int> = new C<int>();
+}
+
+/*
+heap {
+  record #0:1:init02 {
+    field f: C<int> = #1:C<int>;
+  }
+  record #1:0:C<int> {
+    field g: int = int:0;
+  }
+}
+*/
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class new16<X> {
+   constructor(x: X) {
+   }
+}
+
+component new16_a {
+   field x: new16<int> = new new16<int>(0);
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 10:5
+
+class unreach18 {
+    
+    method testm() {
+        switch ( 0 ) {
+            case ( 0 ) {
+                return;
+            }
+            default {
+                return;
+            }
+        }
+        testm();
+    }
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class C<X> {
+  field g: X[] = new X[1];
+}
+
+component init07 {
+  field f: C<int> = new C<int>();
+}
+
+/*
+heap {
+  record #0:1:init07 {
+    field f: C<int> = #1:C<int>;
+  }
+  record #1:1:C<int> {
+    field g: int[] = #2:int[1];
+  }
+  record #2:1:int[1] {
+    field 0: int = int:0;
+  }
+}
+*/
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=7, 2=42, 3=6, 4=0
+
+component prepost15 {
+    field foo: int[] = { 6, 42 };
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = foo[0]++;
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[1];
+\tif ( arg == 3 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization of arrays of raws
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=0
+
+component array_raw06 {
+    field a: 13[] = { 0xfe7, 0b100, 'c' };
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return a[0] == 0xfe7;
+\tif ( arg == 2 ) return a[1] == 0x004;
+\tif ( arg == 3 ) return a[2] == 0x063;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 21
+
+class virtual07b_1 {
+    method val(): int { return 11; }
+}
+
+class virtual07b_2 extends virtual07b_1 {
+    method val(): int { return 21; }
+}
+
+class virtual07b_3 extends virtual07b_1 {
+    method val(): int { return 31; }
+}
+
+class virtual07b_4 {
+    method val(): int { return 51; }
+}
+
+class virtual07b_5 extends virtual07b_4 {
+    method val(): int { return 61; }
+}
+
+component virtual07b {
+    field a: virtual07b_1 = new virtual07b_1();
+    field b: virtual07b_1 = new virtual07b_2();
+    field c: virtual07b_1 = new virtual07b_3();
+    field d: virtual07b_4 = new virtual07b_4();
+    field e: virtual07b_4 = new virtual07b_5();
+
+    method main(arg: int): int {
+\treturn b.val();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component while08 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0, loop = 1;
+        while ( loop++ < 2 ) {
+            for ( i = 1; ; cumul += i, i++ ) {
+\t        if ( i > max ) break;
+\t        else continue;
+\t    }
+\t}
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:while08 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=15, 3=17, 4=42
+
+component array25 {
+    field a: (function(): int)[] = { m13, m15, m17 };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a[0]();
+\tif ( arg == 2 ) return a[1]();
+\tif ( arg == 3 ) return a[2]();
+\treturn 42;
+    }
+
+    method m13(): int { return 13; }
+    method m15(): int { return 15; }
+    method m17(): int { return 17; }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=14, 5=42
+
+component ptex_meth03 {
+
+    method main(arg: int): int {
+    \tif ( arg == 1 ) return m(11);
+    \tif ( arg == 2 ) return m(12);
+    \tif ( arg == 3 ) return m(n(13));
+    \tif ( arg == 4 ) return m(n(14));
+        return 42;
+    }
+
+    method m<T>(x: T): T { return n(x); }
+    method n<T>(x: T): T { return x; }
+}
+"
+"// @Harness: v2-seman
+// @Test: using the char[] type for strings
+// @Result: PASS
+
+class string04 {
+    field testf: char[];
+    method foo(): char[] {
+        testf = foo();
+        return ""this is a string constant"";
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of evaluation)
+// @Result: VariableNotInitialized @ 7:23
+
+class order_init08 {
+    
+    method testm(a: int[]): int {
+        local uninit: int;
+        return a[uninit = 0] = uninit;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42
+
+class Self<T> {
+}
+
+class Myself extends Self<Myself> {
+    field val: int;
+    constructor(v: int) {
+        val = v;
+    }
+}
+
+component ptex_self01 {
+    field f: Myself = new Myself(11);
+    field g: Myself = new Myself(21);
+    field h: Myself = new Myself(31);
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return f.val;
+\tif ( arg == 2 ) return g.val;
+\tif ( arg == 3 ) return h.val;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: constructors and inheritance
+// @Result: PASS
+
+class constructor16_a {
+    constructor(a: int) {
+    }
+}
+
+class constructor16_b extends constructor16_a {
+    constructor(a: int, b: int): super(a) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; invocation of method on non-object
+// @Result: PASS
+
+class nmspc01 {
+    
+    field int: bool;
+
+    method testm() {
+        local foo: int = 1;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 1
+
+class instof08_a {
+}
+
+class instof08_k {
+}
+
+class instof08_b extends instof08_a {
+}
+
+class instof08_l extends instof08_k {
+}
+
+class instof08_c extends instof08_b {
+}
+
+component instof08 {
+    field foo: instof08_k = new instof08_l();
+
+    method main(arg: int): int {
+\treturn foo instanceof instof08_k ? 1 : 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component raw_shr01 {
+    field res_01: 32 = op(0x0f, 1);
+    field res_02: 32 = op(0x02, 2);
+    field res_03: 32 = op(0x80000000, 31);
+    field res_04: 32 = op(0xefe, 8);
+    field res_05: 32 = op(0xf0, 16);
+    field res_06: 32 = op(0xaaaa, 4);
+    field res_07: 32 = op(0x10000, 16);
+    field res_08: 32 = op(0x700, 8);
+    field res_09: 32 = op(-65, 5);
+    field res_10: 32 = op(0xaa, 0);
+
+    method op(a: 32, b: int): 32 {
+\treturn a >> b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(0xf, 1)         == res_01;
+\tif ( arg == 2 )  return op(0x2, 2)         == res_02;
+\tif ( arg == 3 )  return op(0x80000000, 31) == res_03;
+\tif ( arg == 4 )  return op(0xefe, 8)       == res_04;
+\tif ( arg == 5 )  return op(0xf0, 16)       == res_05;
+\tif ( arg == 6 )  return op(0xaaaa, 4)      == res_06;
+\tif ( arg == 7 )  return op(0x10000, 16)    == res_07;
+\tif ( arg == 8 )  return op(0x700, 8)       == res_08;
+\tif ( arg == 9 )  return op(-65, 5)         == res_09;
+\tif ( arg == 10 ) return op(0xaa, 0)        == res_10;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 0=0
+
+class instof05_a {
+}
+
+class instof05_b extends instof05_a {
+}
+
+class instof05_c extends instof05_a {
+}
+
+component instof05 {
+    field foo: instof05_a = new instof05_c();
+
+    method main(arg: int): int {
+\treturn foo instanceof instof05_b ? 1 : 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking of operators
+// @Result: PASS
+
+class type_func08 {
+  field f: function() = g;
+  method g() {}
+}
+"
+"component Terminal {
+
+\tprivate field buffer: char[] = new char[12];
+
+\tmethod printInt(i: int) {
+\t\tlocal neg: boolean = false;
+\t\tlocal ind: int = 10;
+
+\t\tif (i == 0) {
+\t\t\tprintChar('0');
+\t\t\treturn;
+\t\t}
+
+\t\tif (i < 0) {
+\t\t\ti = -i;
+\t\t\tneg = true;
+\t\t}
+
+\t\twhile (i > 0) {
+\t\t\tbuffer[ind--] = ((i % 10) + '0') :: char;
+\t\t\ti = i / 10;
+\t\t}
+
+\t\tif (neg) buffer[ind--] = '-';
+
+\t\tprintBuffer(buffer, ind + 1, buffer.length - ind - 1);
+\t   }
+
+\tmethod printHex(raw: 8) {
+\t\tbuffer[1] = toHexChar((raw & 0xF) :: int);
+\t\tbuffer[0] = toHexChar((raw >> 4) :: int);
+\t\tprintString(buffer, 2);
+\t}
+
+\tmethod toHexChar(digit: int): char {
+\t\tif ( digit < 10 ) return (digit + '0') :: char;
+\t\telse return (digit + 'A') :: char;
+\t}
+
+\tmethod printChar(c: char) {
+\t\tbuffer[0] = c;
+\t\tprintString(buffer, 1);
+\t}
+
+\tmethod printString(string: char[], len: int) {
+\t\tprintBuffer(string, 0, len);
+\t}
+
+\tmethod printBuffer(string: char[], ind: int, len: int) {
+\t\tMCU.sleepTransfer(string, ind, len, USART0.transmit);
+//\t\tlocal max = ind + len;
+//\t\twhile (ind < max) {
+//\t\t\tind = ind + USART0.transmit(string, ind, max - ind);
+//\t\t}
+\t}
+
+\tmethod nextLine() {
+\t\tbuffer[0] = '\
+';
+\t\tprintString(buffer, 1);
+\t}
+}
+
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class cmpassn12_obj {
+    field foo: int = 13;
+    field bar: int = foo %= 7;
+}
+
+component cmpassn12 {
+    field foo: cmpassn12_obj = new cmpassn12_obj();
+}
+
+/* 
+heap {
+    record #0:1:cmpassn12 {
+        field foo: cmpassn12_obj = #1:cmpassn12_obj;
+    }
+    record #1:2:cmpassn12_obj {
+        field foo: int = int:6;
+        field bar: int = int:6;
+    }
+}*/
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=0
+
+component overflow01 {
+
+    field f: int = 127;
+    field g: int = 255;
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return (f + 1) > 0;
+\tif ( arg == 2 ) return (f + 1) > f;
+\tif ( arg == 3 ) return (g + 1) > 0;
+\tif ( arg == 4 ) return (g + 1) > g;
+\tif ( arg == 5 ) return (f + f) > 0;
+\tif ( arg == 6 ) return (f + f) > f;
+\tif ( arg == 7 ) return (g + g) > 0;
+\tif ( arg == 8 ) return (g + g) > g;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class for2 {
+  method m() {
+     local a: int;
+
+     for( a = 0; func(a); a = func(a))
+       a = func(a,a);
+
+     for( a = 0; func(a); a = func(a)) {
+       a = func(a,a);
+     }
+
+     for( a = 0; func(a); a = func(a)) {
+       local c = func(a,a);
+     }
+
+     for( a = 0; func(a); a = func(a)) {
+       local c = func(a,a);
+       c = func(c,c) + 0;
+     }
+
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component cmpassn25 {
+    
+    field a: int;
+    field b: int;
+
+    constructor() {
+        b += a++;
+        b += a++;
+    }
+}
+
+/* 
+heap {
+    record #0:6:cmpassn25 {
+        field a: int = int:2;
+        field b: int = int:1;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive assignments
+// @Result: TypeMismatch @ 5:11
+
+class type10 {
+    field foo: int = false;
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Result: 0=42, 1=15, 2=120, 3=31, 4=31, 5=42
+
+component ptex_fold01 {
+
+    field iarr: int[] = { 1, 2, 3, 4, 5 };
+    field rarr: 5[] = { 0b00001, 0b10000, 0b01000, 0b00010, 0b00100 };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return fold(add, iarr, iarr.length - 1);
+\tif ( arg == 2 ) return fold(mult, iarr, iarr.length - 1);
+        if ( arg == 3 ) return fold(ror, rarr, rarr.length - 1) :: int;
+        if ( arg == 4 ) return fold(rxor, rarr, rarr.length - 1) :: int;
+        return 42;
+    }
+
+    method add(a: int, b: int): int {
+\treturn a + b;
+    }
+
+    method mult(a: int, b: int): int {
+        return a * b;
+    }
+
+    method ror(a: 5, b: 5): 5 {
+        return a | b;
+    }
+
+    method rxor(a: 5, b: 5): 5 {
+        return a ^ b;
+    }
+
+    method fold<T>(f: function(T, T): T, a: T[], m: int): T {
+\treturn m == 0 ? a[0] : f(fold(f, a, m-1), a[m]);        
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Transform<R, E> {
+    method visitA(n: A, e: E): R;
+    method visitB(n: B, e: E): R;
+}
+
+class S {
+    method accept<R, E>(v: Transform<R, E>, e: E): R;
+}
+
+class A extends S {
+    method accept<R, E>(v: Transform<R, E>, e: E): R { return v.visitA(this, e); }
+}
+
+class B extends S {
+    method accept<R, E>(v: Transform<R, E>, e: E): R { return v.visitB(this, e); }
+}
+
+class PriceList {
+}
+
+class Jewels {
+}
+
+class Thief extends Transform<Jewels, PriceList> {
+    method visitA(n: A, e: PriceList): Jewels {
+\treturn null;
+    }
+    method visitB(n: B, e: PriceList): Jewels {
+\treturn null;
+    }
+}
+
+component Client {
+    field a: S = new A();
+    field b: S = new B();
+    field thief: Thief = new Thief();
+
+    method test() {
+\tlocal j1: Jewels = a.accept(thief, new PriceList());
+\tlocal j2: Jewels = b.accept(thief, new PriceList());
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedUnaryOp @ 6:7
+
+class type50 {
+    
+    method testm() {
+        local a = -false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=0
+
+component raw_shl02 {
+    field res_01: 16 = init(1);
+    field res_02: 16 = init(2);
+    field res_03: 16 = init(3);
+    field res_04: 16 = init(4);
+    field res_05: 16 = init(5);
+    field res_06: 16 = init(6);
+    field res_07: 16 = init(7);
+    field res_08: 16 = init(8);
+    field res_09: 16 = init(9);
+
+    method op(a: 16, b: int): 16 {
+\treturn a << b;
+    }
+
+    method init(arg: int): 16 {
+\tif ( arg == 1 )  return op(0xf,     1);
+\tif ( arg == 2 )  return op(0x2,     2);
+\tif ( arg == 3 )  return op(0x1,    15);
+\tif ( arg == 4 )  return op(0x0,     8);
+\tif ( arg == 5 )  return op(0xf0,   16);
+\tif ( arg == 6 )  return op(0xffff,  2);
+\tif ( arg == 7 )  return op(0x8000, 16);
+\tif ( arg == 8 )  return op(0xff,    5);
+\tif ( arg == 9 )  return op(0xaa,    0);
+\treturn 0x0000;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return init(1) == res_01;
+\tif ( arg == 2 )  return init(2) == res_02;
+\tif ( arg == 3 )  return init(3) == res_03;
+\tif ( arg == 4 )  return init(4) == res_04;
+\tif ( arg == 5 )  return init(5) == res_05;
+\tif ( arg == 6 )  return init(6) == res_06;
+\tif ( arg == 7 )  return init(7) == res_07;
+\tif ( arg == 8 )  return init(8) == res_08;
+\tif ( arg == 9 )  return init(9) == res_09;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+class order05_a {
+    field foo: function(int): int = order05.add;
+}
+
+component order05 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    field res_01: int = first().foo(second(1));
+
+    method first(): order05_a {
+        order[pos] = 1;
+        pos++;
+        return new order05_a();
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method add(a: int): int { return a + 2; }
+}
+
+/* 
+heap {
+    record #0:10:order05 {
+        field order: int[] = #1:int[2];
+        field pos: int = int:2;
+        field res_01: int = int:3;
+    }
+    record #1:2:int[2] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=0
+
+component scope01 {
+    method main(arg: int): bool {
+\t{ local a = 1; if ( arg == a ) return true; }
+\t{ local a = 2; if ( arg == a ) return true; }
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Self<T> {
+    field me: T;
+    constructor(t: T) {
+        me = t;
+    }
+}
+
+class A extends Self<A> {
+    constructor() : super(this) { }
+    method foo(): A { return me; }
+}
+
+class B extends Self<B> {
+    constructor() : super(this) { }
+    method foo(): B { return me; }
+}
+"
+"// @Harness: v2-exec
+// @Test: reading of arrays of raws
+// @Result: 0=42, 1=15, 2=0, 3=99, 4=42
+
+component array_raw01 {
+    field a: 8[] = { 0xf, 0b00, 'c' };
+
+    method main(arg: int): 8 {
+\tif ( arg == 1 ) return a[0];
+\tif ( arg == 2 ) return a[1];
+\tif ( arg == 3 ) return a[2];
+\treturn 0x2a;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: TypeMismatch @ 8:21
+
+class char_int04 {
+    field a: int;
+    field b: char = m(a);
+    method m(x: char): char { return x; }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 11
+
+class virtual05b_1 {
+    method val(): int { return 11; }
+}
+
+class virtual05b_2 extends virtual05b_1 {
+}
+
+class virtual05b_3 extends virtual05b_2 {
+    method val(): int { return 31; }
+}
+
+component virtual05b {
+    field a: virtual05b_1 = new virtual05b_1();
+    field b: virtual05b_1 = new virtual05b_2();
+    field c: virtual05b_1 = new virtual05b_3();
+
+    method main(arg: int): int {
+\treturn b.val();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: CannotUnifyBranchTypes @ 6:24
+
+class unify_int_str01 {
+    
+    method testm() {
+        local a: int = false ? 0 : """";
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type06<X> {
+    field f: type06<X[]>;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: TypeMismatch @ 6:16
+
+class int_add02 {
+    
+    method testm() {
+        local a: int = 2 + null;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg11_a {
+    method val(): int { return 1; }
+}
+
+class dg11_b extends dg11_a {
+    method val(): int { return 2; }
+}
+
+component dg11 {
+    field a: function():int = new dg11_a().val;
+    field b: function():int = new dg11_b().val;
+    field c: function():int = bar;
+    field d: function():int = null;
+    field av: int = val(a);
+    field bv: int = val(b);
+    field cv: int = val(c);
+    field dv: int = val(d);
+
+    method val(f: function(): int): int {
+\tif ( f == a ) return 11;
+\tif ( f == b ) return 21;
+\tif ( f == c ) return 31;
+\tif ( f == null ) return 42;
+\treturn 77;
+    }
+    method bar(): int {
+\treturn 3;
+    }
+
+}
+
+/* 
+heap {
+    record #0:8:dg11 {
+        field a: function():int = [#1:dg11_a,dg11_a:val()];
+        field b: function():int = [#2:dg11_b,dg11_b:val()];
+        field c: function():int = [#0:dg11,dg11:bar()];
+        field d: function():int = #null;
+        field av: int = int:11;
+        field bv: int = int:21;
+        field cv: int = int:31;
+        field dv: int = int:42;
+    }
+    record #1:0:dg11_a {
+    }
+    record #2:0:dg11_b {
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=6, 2=6, 3=0
+
+component cmpassn02 {
+    field foo: int = 8;
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = (foo -= 2);
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=NullCheckException, 3=NullCheckException, 4=42
+
+component rtex_null02 {
+    field foo: int[] = null;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[1];
+\tif ( arg == 3 ) return foo[2];
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment options
+// @Result: PASS
+
+class cmpassn10_obj {
+    field foo: 16 = 0x6;
+    field bar: 16 = foo |= 0x1;
+}
+
+component cmpassn10 {
+    field foo: cmpassn10_obj = new cmpassn10_obj();
+
+}
+
+/* 
+heap {
+    record #0:1:cmpassn10 {
+        field foo: cmpassn10_obj = #1:cmpassn10_obj;
+    }
+    record #1:2:cmpassn10_obj {
+        field foo: int = raw.16:0x7;
+        field bar: int = raw.16:0x7;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test the typechecking of arrays""
+// @Result: PASS
+
+class array01 {
+    
+    method testm(a: int[]): int[] {
+        return testm(a);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_unify08 {
+    method test1(): int[] { return id(null, null); }
+    method test2(): char[] { return id(null, null); }
+    method test3(): 32[] { return id(null, null); }
+    method test4(): 8[] { return id(null, null); }
+
+    method id<X>(x: X, y: X): X {
+\treturn x;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: order of evaluation
+// @Result: 0=0, 1=1, 2=2, 3=3, 4=0
+
+component order02 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    method f(a: int, b: int): int {
+\treturn a + b;
+    }
+
+    method first(a: int): int {
+        order[pos] = 1;
+        pos++;
+        return a;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method main(arg: int): int {
+        local result = f(first(1), second(2));
+\tif ( arg == 1 ) return order[0];
+\tif ( arg == 2 ) return order[1];
+\tif ( arg == 3 ) return result;
+\treturn 0;
+    }
+
+}
+"
+"program rma_array01 {
+    entrypoint main = Main.entry;
+}
+
+component Main {
+    field f: A[] = { new A(m1) };
+    field g: A[] = { new A(m2) };
+
+    method entry() {
+\twhile ( true ) { 
+\t    f[0] = f[0].m();
+\t    f[0].func();
+        }
+    }
+
+    method m1() { }
+    method m2() { }
+}
+
+class A {
+    field func: function();
+    constructor(f: function()) { func = f; }
+    method m(): A { return this; }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 4:17
+
+component comp02<X, Y> {
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class11<X, Y> extends class11a<Pair<X, Y> > {
+}
+"
+"/**
+ * Utility functions for dealing with arrays.
+ *
+ */
+
+component ArrayUtil {
+
+\tmethod copy<T>(s: T[], d: T[], sp: int, dp: int, len: int) {
+\t\twhile (len-- > 0) d[dp++] = s[sp++];
+\t}
+
+\tmethod copyPartial<T>(s: T[], d: T[], sp: int, dp: int, len: int): int {
+\t\tlocal cnt = 0;
+\t\twhile (len - cnt > 0) {
+\t\t\tif (dp + cnt >= d.length) break;
+\t\t\td[dp + cnt] = s[sp + cnt];
+\t\t\tcnt++;
+\t\t}
+\t\treturn cnt;
+\t}
+
+\tmethod dup<T>(a: T[]): T[] {
+\t\tlocal r = new T[a.length];
+\t\tcopy(a, r, 0, 0, a.length);
+\t\treturn r;
+\t}
+
+\tmethod search<T>(a: T[], f: function(T): boolean): int {
+\t\tlocal i = 0;
+\t\twhile (i < a.length) {
+\t\t\tif (f(a[i++])) return i - 1;
+\t\t}
+\t\treturn -1;
+\t}
+}
+"
+"program HelloWorld {
+    entrypoint main = HelloWorld.main;
+    
+}
+
+component HelloWorld {
+    constructor() {
+        Mica2.setTimerCompare(Mica2.red.toggle);
+    }
+    method main(a: int, b: int, e: int): int {
+    
+        local c = a * 34;
+
+
+        if(fun(a) > c)
+\t\treturn 2;
+\telse
+      
+\treturn 1;        
+
+    }
+    
+
+    method fun(a: int): int {
+        local b = a - 1000;
+\tif(a < 100)
+        return fun2(a);
+\telse
+\treturn 0 ;
+    }
+
+    method fun2(a: int): int {
+        local b = a + 1000;
+\tif(a < 10)
+        return fun3(a);
+\telse
+\treturn 0 ;
+
+    }
+
+    method fun3(a: int): int {
+        local b = a *500;
+\tif(a < 1)
+        return b;
+\telse
+\treturn 0 ;
+
+    }
+
+}"
+"// @Harness: v2-seman
+// @Test: typechecking of operators
+// @Result: PASS
+
+class unify_null02 {
+  method testm(a: unify_null02, b: boolean) {
+    local x = b ? this : null;
+    a = x;
+    local y = b ? null : this;
+    a = y;
+  }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Self<T> {
+}
+
+class Myself extends Self<Self<Myself> > {
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr4 {
+  field foo: type = foo.bar();
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Result: 0=0, 1=12, 2=12, 3=10, 4=16, 5=0
+
+component static05 {
+    field m: function(): int = val1;
+    field av: int = m();
+    field bv: int = val2();
+    field cv: int = val3();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return m();
+\tif ( arg == 2 ) return val1();
+\tif ( arg == 3 ) return val2();
+\tif ( arg == 4 ) return val3();
+\treturn 0;
+    }
+
+    method val1(): int { return apply(val2, 2); }
+    method val2(): int { return 10; }
+    method val3(): int { return apply(val1, 4); }    
+
+    method apply(f: function(): int, a: int): int { 
+\treturn f() + a; 
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=42, 2=21, 3=31, 4=42
+
+class abstract01_1 {
+    method val(): int;
+}
+
+class abstract01_2 extends abstract01_1 {
+    method val(): int { return 21; }
+}
+
+class abstract01_3 extends abstract01_1 {
+    method val(): int { return 31; }
+}
+
+component abstract01 {
+    field b: abstract01_1 = new abstract01_2();
+    field c: abstract01_1 = new abstract01_3();
+
+    method main(arg: int): int {
+\tif ( arg == 2 ) return b.val();
+\tif ( arg == 3 ) return c.val();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: parsing precedence of bitwise operators vs bit index
+// @Result: PASS
+
+component prec04 {
+    field r01: 4 = 0b0100 | 0b0010[0];
+    field r02: 4 = 0b0100 | 0b0010[1];
+    field r03: 4 = 0b1000 ^ 0b0010[0];
+    field r04: 4 = 0b1000 ^ 0b0010[1];
+    field r05: 4 = 0b1001 & 0b1000[0];
+    field r06: 4 = 0b1001 & 0b1010[1];
+}
+
+/*
+heap {
+    record #0:10:prec04 {
+        field r01: raw.4 = raw.4:0b0100;
+        field r02: raw.4 = raw.4:0b0101;
+\tfield r03: raw.4 = raw.4:0b1000;
+\tfield r04: raw.4 = raw.4:0b1001;
+\tfield r05: raw.4 = raw.4:0b0000;
+\tfield r06: raw.4 = raw.4:0b0001;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 4:7
+
+component set {
+}
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=13, 3=14, 4=NullCheckException, 5=42
+
+class rtex_null13_obj {
+    field a: int[];
+    constructor(i: int[]) { a = i; }
+    method getf(i: int): int {
+        return a[i];
+    }
+}
+
+component rtex_null13 {
+    field i: int[] = { 13, 14 };
+    field a: rtex_null13_obj = new rtex_null13_obj(null);
+    field b: rtex_null13_obj = new rtex_null13_obj(i);
+    field c: rtex_null13_obj = new rtex_null13_obj(null);
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.getf(0);
+\tif ( arg == 2 ) return b.getf(0);
+\tif ( arg == 3 ) return b.getf(1);
+\tif ( arg == 4 ) return c.getf(0);
+\treturn 42;
+    }
+}
+"
+"program rma04 {
+    entrypoint main = Main.entry;
+}
+
+component Main {
+    field a: A = new A(new A(new A(null)));
+
+    method entry() {
+\twhile ( true ) { 
+\t    a = a.m();
+        }
+    }
+}
+
+class A {
+    field other: A;
+    constructor(o: A) { other = o; }
+    method m(): A { return this; }
+}
+
+"
+"// @Harness: v2-exec
+// @Test: array rtex_index exceptions
+// @Result: 0=42, 1=13, 2=13, 4=BoundsCheckException, 5=42
+
+component rtex_index04 {
+    field foo: int[] = new int[16];
+
+    constructor() {
+\tlocal i = 0;
+\tfor ( i = 0; i < foo.length; i++ ) foo[i] = 13;
+    }
+
+    method getf(i: int): int {
+\treturn foo[i];
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return getf(0);
+\tif ( arg == 2 ) return getf(1);
+\tif ( arg == 3 ) return getf(15);
+\tif ( arg == 4 ) return getf(16);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_unify06 {
+    method test() {
+\tlocal x: int[] = id(new int[5], null);
+\tlocal y: char[] = id(new char[5], null);
+\tlocal z: 32[] = id(new 32[5], null);
+\tlocal w: 8[] = id(new 8[5], null);
+    }
+    method id<X>(x: X, y: X): X {
+\treturn x;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: reading of arrays of raws
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=0
+
+component array_raw08 {
+    field a: 51[] = { 0x1000fe710000, 0b100, 'c', -1 };
+    field av: 51  = a[0];
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return a[0] == 0x01000fe710000;
+\tif ( arg == 2 ) return a[1] == 0x0000000000004;
+\tif ( arg == 3 ) return a[2] == 0x0000000000063;
+\tif ( arg == 4 ) return a[3] == 0x7ffffffffffff;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42
+
+class private10_a {
+    method getf(): int { return val; }
+    private field val: int = 11;
+}
+
+class private10_b extends private10_a {
+    field val: int = 21;
+}
+
+class private10_c extends private10_a {
+    field val: int = 31;
+}
+
+component private10 {
+    field a: private10_a = new private10_a();
+    field b: private10_b = new private10_b();
+    field c: private10_c = new private10_c();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.getf();
+\tif ( arg == 2 ) return b.val;
+\tif ( arg == 3 ) return c.val;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr10 {
+  field foo: type = (foo);
+}
+"
+"program Oscilloscope {
+\tentrypoint main = Oscilloscope.main;
+\tentrypoint timer0_comp = Timer0.compareHandler;
+\tentrypoint adc = ADC.convHandler;
+
+\tentrypoint usart0_rx = USART0.rec_handler; // We don\'t use RX, but without this line I get a stack overflow.
+//\tentrypoint usart0_udre = USART0.tran_handler;
+        entrypoint usart0_tx = USART0.tran_handler;
+}
+
+component Oscilloscope {
+\t// half-open range
+\tfield AdcIndexBegin: int = 2;
+\tfield AdcIndexEnd: int = 7;
+\tfield AdcCount: int = AdcIndexEnd - AdcIndexBegin;
+
+\tfield readings: 10[] = new 10[AdcCount];
+\tfield t_buf: char[] = ""Hello World\
+"";
+
+\tfield working : boolean = false;
+\tfield adcIndex: int = 0;
+\tfield outBuf : char[] = new char[10];
+
+\tconstructor() {
+\t\tADC.setConvFunc(readADC);
+\t\tMica2.setTimerCompare(startReadADC);
+\t}
+
+\tmethod main() {
+\t\tMica2.startTerminal();
+\t\tADC.enable();
+\t\tMica2.startTimer();
+\t\tTimer0.setCompareMatch(128);
+
+\t\tMCU.sleepForever();
+\t}
+
+\t// This function is called periodically (timer interrupt).
+\tmethod startReadADC() {
+\t\t// Set a flag to avoid nested timer interrupts.
+\t\tif (working) return;
+\t\tworking = true;
+
+\t\tMica2.red.toggle();
+
+\t\tadcIndex = 0;
+\t\tADC.startConv(AdcIndexBegin+adcIndex, true);
+\t}
+
+\tmethod readADC(value: 10) {
+\t\treadings[adcIndex] = value;
+
+\t\tadcIndex++;
+\t\tif (adcIndex < AdcCount) {
+\t\t\tADC.startConv(AdcIndexBegin+adcIndex, true);
+\t\t} else {
+\t\t\tadcIndex = 0;
+\t\t\tsendReadings();
+\t\t\t
+\t\t}
+\t}
+
+\tmethod sendReadings() {
+\t\tlocal bufI = 0;
+\t\tlocal adcI = 0;
+\t\twhile (adcI < AdcCount) {
+\t\t\tlocal v = readings[adcI];
+\t\t\tbufI = writeInt(outBuf, bufI, v :: int);
+//\t\t\toutBuf[bufI++] = (v >> 8) :: 8 :: char;
+//\t\t\toutBuf[bufI++] = (v & 0xf) :: 8 :: char;
+\t\t\tadcI++;
+\t\t}
+\t\toutBuf[bufI++] = \'\
+\';
+
+\t\tMCU.sleepTransfer(outBuf, 0, bufI, USART0.transmit);
+\t//\tUSART0.transmit(outBuf,0,bufI);
+\t\tworking = false;
+\t}
+
+\tmethod writeInt(buf: char[], bufI: int, value: int): int {
+\t\tbuf[bufI++] = \' \';
+\t\twhile(value <0)value +=256;
+\t\tif(true){
+\t\t\tlocal digit = (\'0\' :: int) + (value % 10);
+\t\t\tbuf[bufI++] = digit :: char;
+\t\t\tvalue = value / 10;
+\t\t\tif (value == 0)
+\t\t\t    {}
+\t\t}
+\t\treturn bufI;
+\t}
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator
+// @Result: PASS
+
+component raw_index06 {
+    field f1: 8 = 0xf0;
+    field f2: 8 = 0xf0;
+    field f3: 8 = 0xf0;
+    field f4: 8 = 0xf0;
+    field f5: 16 = 0x3ff0;
+    field f6: 16 = 0x3ff0;
+    field f7: 32 = 0x3ff0eeee;
+    field f8: 32 = 0x3ff0eeee;
+    field f9: 32 = 0x3ff0eeee;
+
+    constructor() {
+\traw_index06.f1[-1] |= 0b1;
+\traw_index06.f2[3]  |= 0b1;
+\traw_index06.f3[7]  |= 0b1;
+\traw_index06.f4[9]  |= 0b1;
+\traw_index06.f5[15] |= 0b1;
+\traw_index06.f6[17] |= 0b1;
+\traw_index06.f7[0]  |= 0b1;
+\traw_index06.f8[31] |= 0b1;
+\traw_index06.f9[32] |= 0b1;
+    }
+}
+
+/*
+heap {
+    record #0:9:raw_index06 {
+\tfield f1: 8 = raw.8:0xf0;
+\tfield f2: 8 = raw.8:0xf8;
+\tfield f3: 8 = raw.8:0xf0;
+\tfield f4: 8 = raw.8:0x0f0;
+\tfield f5: 16 = raw.16:0xbff0;
+\tfield f6: 16 = raw.16:0x3ff0;
+\tfield f7: 32 = raw.32:0x3ff0eeef;
+\tfield f8: 32 = raw.32:0xbff0eeee;
+\tfield f9: 32 = raw.32:0x3ff0eeee;
+    }
+}
+*/
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=7, 2=7, 3=1, 4=0
+
+class prepost22_obj {
+    field foo: int = 6;
+}
+
+component prepost22 {
+    field cnt: int;
+    field foo: prepost22_obj = new prepost22_obj();
+    field bar: int;
+    
+    method obj(): prepost22_obj {
+\tcnt++; // should only be called once
+\treturn foo;
+    }
+
+    method main(arg: int): int {
+\tbar = ++obj().foo;
+\tif ( arg == 1 ) return foo.foo;
+\tif ( arg == 2 ) return bar;
+\tif ( arg == 3 ) return cnt;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=11, 3=11, 4=42
+
+class private03_a {
+    method getf(): int { return val; }
+    private field val: int = 11;
+}
+
+class private03_b extends private03_a {
+    private field val: int = 21;
+}
+
+class private03_c extends private03_a {
+    private field val: int = 31;
+}
+
+component private03 {
+    field a: private03_a = new private03_a();
+    field b: private03_a = new private03_b();
+    field c: private03_a = new private03_c();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.getf();
+\tif ( arg == 2 ) return b.getf();
+\tif ( arg == 3 ) return c.getf();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int operations
+// @Result: PASS
+
+class raw_op04 {
+    method check(a: 64, b: 64, c: int): 64 {
+\tlocal x: 64;
+\tx = a;
+\tx = a & b;
+\tx = a | b;
+\tx = a ^ b;
+\tx = a << c;
+\tx = a >> c;
+\tx = ~a;
+\treturn x;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: array rtex_index exceptions
+// @Result: 0=42, 1=255, 2=0, 3=14, 4=39, 5=40, 6=BoundsCheckException, 7=BoundsCheckException
+
+component rtex_index07 {
+    field foo: int[] = new int[42];
+
+    method scan(max: int, min: int): int {
+        local cntr: int;
+        for ( cntr = max; cntr >= min; cntr-- )
+\t    foo[cntr] = cntr;
+        return cntr;
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return scan(5, 0);
+\tif ( arg == 2 ) return scan(7, 1);
+\tif ( arg == 3 ) return scan(40, 15);
+\tif ( arg == 4 ) return scan(41, 40);
+\tif ( arg == 5 ) return scan(41, 41);
+\tif ( arg == 6 ) return scan(42, 0);
+\tif ( arg == 7 ) return scan(40, -1);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > auto extension
+// @Result: TypeMismatch @ 7:19
+
+class raw_assn06 {
+    field a: 11;
+    field b: 8 = a;
+}
+"
+"// @Harness: tir-to-avr
+// @Test: type check exceptions in AVR code
+// @Result: TypeCheckException
+
+program rtex_cast01 {
+    entrypoint main = rtex_cast01.main;
+}
+
+class rtex_a {
+}
+
+class rtex_b extends rtex_a {
+}
+
+component rtex_cast01 {
+    field foo: rtex_a = new rtex_a();
+
+    method main(): int {
+\tlocal x = foo :: rtex_b;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+
+  method first(): X {
+    return a;
+  }
+
+  method second(): Y {
+    return b;
+  }
+}
+
+component Client {
+  method test() {
+    local p = new Pair<int, bool>();
+    local b = p.first;
+    local c = p.second;
+  }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class3 {
+  method m();
+  method n(a: type);
+
+  method o() {
+  }
+
+  method p(a: type) {
+  }
+}
+"
+"// @Harness: v2-init
+// @Test: parsing precedence of arithmetic operators
+// @Result: PASS
+
+component prec03 {
+    field r01: 4 = 0b0101 | 0b0010 & 0b0011; // & higher than |
+    field r02: 4 = 0b0100 | 0b0011 & 0b0010; // & higher than |
+    field r03: 4 = 0b1000 | 0b0010 ^ 0b1000; // ^ higher than |
+    field r04: 4 = 0b1000 | 0b0001 ^ 0b1000; // ^ higher than |
+    field r05: 4 = 0b1000 ^ 0b1000 & 0b0010; // & higher than ^
+    field r06: 4 = 0b1000 ^ 0b1010 & 0b0011; // & higher than ^
+}
+
+/*
+heap {
+    record #0:10:prec03 {
+        field r01: raw.4 = raw.4:0b0111;
+        field r02: raw.4 = raw.4:0b0110;
+\tfield r03: raw.4 = raw.4:0b1010;
+\tfield r04: raw.4 = raw.4:0b1001;
+\tfield r05: raw.4 = raw.4:0b1000;
+\tfield r06: raw.4 = raw.4:0b1010;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class prepost22_obj {
+    field foo: int = 6;
+}
+
+component prepost22 {
+    field foo: prepost22_obj;
+    field bar: int = ++obj().foo;
+    
+    // this method should only be called once
+    method obj(): prepost22_obj {
+\treturn foo = new prepost22_obj();
+    }
+}
+
+/* 
+heap {
+    record #0:2:prepost22 {
+        field foo: prepost22_obj = #1:prepost22_obj;
+        field bar: int = int:7;
+    }
+    record #1:1:prepost22_obj {
+\tfield foo: int = int:7;
+    }
+}*/
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=21, 3=48, 4=97, 5=42
+
+class Self<T> {
+    field self: T;
+    constructor(s: T) { self = s; }
+}
+
+class W<T> extends Self<W<T> > {
+    field val: T;
+    constructor(v: T) : super(this) {
+        val = v;
+    }
+}
+
+component ptex_self06 {
+    field f: W<int> = new W<int>(11);
+    field g: W<int> = new W<int>(21);
+    field h: W<char> = new W<char>('0');
+    field j: W<char> = new W<char>('a');
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return f.self.val;
+\tif ( arg == 2 ) return g.val;
+\tif ( arg == 3 ) return h.self.val;
+\tif ( arg == 4 ) return j.val;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: switch statements should have compile-time computable values
+// @Result: NotComputable @ 8:15
+
+class switch05 {
+    method testm(a: int): int {
+        switch(a) {
+            case(testm(a)) ;
+        }
+        return 0;
+    }
+}    
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_raw07 {
+    field x: int;
+    field a: 32 = m(x);
+    field b: 48 = m(-109);
+    field c: 64 = m(10909109);
+    method m<T>(x: T): T { return x; }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component field07 {
+    field foo: int[] = { 0, 1 };
+}
+
+/* 
+heap {
+    record #0:1:field07 {
+        field foo: int[] = #1:int[2];
+    }
+    record #1:2:int[2] {
+        field 0: int = int:0;
+        field 1: int = int:1;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array22 {
+    field a_01: char[] =  fill(new char[4]);
+    field a_02: char[] =  fill(new char[6]);
+
+    method fill(a: char[]): char[] {
+\tlocal i = 0;
+        for ( ; i < a.length; i++ ) a[i] = 'a';
+\treturn a;
+    }
+}
+
+/* 
+heap {
+    record #0:2:array22 {
+        field a_01: char[] = #1:char[4];
+        field a_02: char[] = #2:char[6];
+    }
+    record #1:4:char[4] {
+        field 0:char = char:97;
+        field 1:char = char:97;
+        field 2:char = char:97;
+        field 3:char = char:97;
+    }
+    record #2:6:char[6] {
+        field 0:char = char:97;
+        field 1:char = char:97;
+        field 2:char = char:97;
+        field 3:char = char:97;
+        field 4:char = char:97;
+        field 5:char = char:97;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 0=5, 1=5, 2=3, 3=4, 4=4, 5=4
+
+component if07 {
+    
+    method main(arg: int): int {
+\tif ( arg > 1 ) if ( arg == 2 ) return 3; else return 4;
+\treturn 5;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component order02 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    field res_01: int = op(1, 2);
+
+    method op(a: int, b: int): int {
+\treturn f(first(a), second(b));
+    }
+
+    method f(a: int, b: int): int {
+\treturn a + b;
+    }
+
+    method first(a: int): int {
+        order[pos] = 1;
+        pos++;
+        return a;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+}
+
+/* 
+heap {
+    record #0:10:order02 {
+        field order: int[] = #1:int[2];
+        field pos: int = int:2;
+        field res_01: int = int:3;
+    }
+    record #1:2:int[2] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator
+// @Result: PASS
+
+component raw_index12 {
+    field f: 8[] = { 0xf0, 0xf0, 0xf0, 0xf0 };
+
+    constructor() {
+\tlocal x = 0;
+\tf[x++][-1] |= 0b1;
+\tf[x++][3]  |= 0b1;
+\tf[x++][7]  |= 0b1;
+\tf[x++][9]  |= 0b1;
+    }
+}
+
+/*
+heap {
+    record #0:1:raw_index12 {
+\tfield f: 8[] = #1:8[4];
+    }
+    record #1:4:8[4] {
+\tfield 0: 8 = raw.8:0xf0;
+\tfield 1: 8 = raw.8:0xf8;
+\tfield 2: 8 = raw.8:0xf0;
+\tfield 3: 8 = raw.8:0xf0;
+    }
+}
+*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type14<X, Y> {
+    field f: type14<function(), Y>;
+}
+"
+"// @Harness: v2-init
+// @Test: compile-time constants for primitive types
+// @Result: PASS
+
+component const_int02 {
+    field a: int = -0;
+    field b: int = -1;
+    field c: int = -9;
+    field d: int = -15;
+    field e: int = -255;
+    field f: int = -256;
+    field g: int = -32768;
+    field h: int = -65535;
+    field i: int = -65536;
+    field j: int = -1048576;
+    field k: int = 2147483647;
+    field l: int = -2147483648;
+}
+
+/* 
+heap {
+    record #0:12:const_int02 {
+        field a: int = int:0;
+        field b: int = int:-1;
+        field c: int = int:-9;
+        field d: int = int:-15;
+        field e: int = int:-255;
+        field f: int = int:-256;
+        field g: int = int:-32768;
+        field h: int = int:-65535;
+        field i: int = int:-65536;
+        field j: int = int:-1048576;
+        field k: int = int:0x7fffffff;
+        field l: int = int:0x80000000;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type14 {
+    field f: ((type)[][])[];
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class method04 {
+    method m1(a: type<X, Y>, b: type<Y>): type<X>;
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=0, 1=13, 2=7, 3=17, 4=0
+
+component array30 {
+    field a_01: int[] =  {13};
+    field a_02: char[] =  {7::char, 17::char};
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a_01[0];
+\tif ( arg == 2 ) return a_02[0]::int;
+\tif ( arg == 3 ) return a_02[1]::int;
+\treturn 0;
+    }
+}
+"
+"component Timer0 {
+
+\t// binary values for the mode field
+\tfield MODE_NORMAL: 2   = 0b00;
+\tfield MODE_CTC: 2\t  = 0b10;
+\tfield MODE_FAST_PWM: 2 = 0b11;
+\tfield MODE_PC_PWM: 2   = 0b01;
+
+\t// octal values for the divider field
+\tfield DIV_1: 3\t= 01;
+\tfield DIV_8: 3\t= 02;
+\tfield DIV_32: 3   = 03;
+\tfield DIV_64: 3   = 04;
+\tfield DIV_128: 3  = 05;
+\tfield DIV_256: 3  = 06;
+\tfield DIV_1024: 3 = 07;
+
+\tfield overflowFunc: function() = none;
+\tfield compareFunc: function() = none;
+\tfield divider: 3;
+
+\tmethod enable() { 
+\t\t// set lower three bits
+\t\tdevice.TCCR0 = device.TCCR0 | divider; 
+\t}
+
+\tmethod disable() { 
+\t\t// clear lower 3 bits
+\t\tdevice.TCCR0 = device.TCCR0 & 0b11111000; 
+\t} 
+
+\tmethod setMode(m: 2) {
+\t\tlocal tccr: 8 = device.TCCR0;
+\t\ttccr[6] = m[0];
+\t\ttccr[3] = m[1];
+\t\tdevice.TCCR0 = tccr;
+\t}
+
+\tmethod setDivider(div: 3) { 
+\t\tdivider = div;
+\t\tdevice.TCCR0 = (device.TCCR0 & 0b11111000) | div;
+\t}
+
+\tmethod setCompareMatch(matchVal: int) { 
+\t\tdevice.OCR0 = matchVal :: 8; 
+\t}
+
+\tmethod setCount(count: int) { 
+\t\tdevice.TCNT0 = count :: 8; 
+\t}
+
+\tmethod getCount(): int { 
+\t\treturn device.TCNT0 :: int; 
+\t}
+
+\tmethod setOverflow(of: function()) { 
+\t\toverflowFunc = of; 
+\t}
+
+\tmethod setCompare(cf: function()) { 
+\t\tcompareFunc = cf; 
+\t}
+
+\tmethod overflowHandler() { 
+\t\toverflowFunc(); 
+\t}
+
+\tmethod compareHandler() { 
+\t\tcompareFunc(); 
+\t\tPower.adjustPower();
+\t}
+
+\tmethod none() { 
+\t\t// do nothing.
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_infer12 {
+    method apply<T>(a: T, f: function(T): T): T {
+        return f(a);
+    }
+    method test() {
+        local x = apply(0, id);
+    }
+    method id<U>(x: U): U { return x; }
+}
+"
+"// @Harness: v2-exec
+// @Test: compound assignment operators
+// @Result: 0=11, 1=13, 2=9, 3=22, 4=5, 5=3, 6=11
+
+component cmpassn21 {
+
+    field foo: int[] = { 11, 42 };
+
+    method main(arg: int): int {
+\tlocal ind = 0;
+\tif ( arg == 1 ) foo[ind++] += 2;
+\tif ( arg == 2 ) foo[ind++] -= 2;
+\tif ( arg == 3 ) foo[ind++] *= 2;
+\tif ( arg == 4 ) foo[ind++] /= 2;
+\tif ( arg == 5 ) foo[ind++] %= 4;
+\treturn foo[0];
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 7:40
+
+class type_res17 {
+    field bar: type_res17;
+    field foo: type_res17 = new unknown[0];
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:12
+
+class field04 {
+    field f type<X>;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class5 extends class5a {
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component comp3 {
+  method m();
+  method n(a: type);
+
+  method o() {
+  }
+
+  method p(a: type) {
+  }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=7, 2=42, 3=6, 4=1, 5=0
+
+component prepost17 {
+    field cnt: int;
+    field foo: int[] = { 6, 42 };
+    field bar: int;
+    
+    method getfoo(): int[] {
+\tcnt++; // should only be executed once
+\treturn foo;
+    }
+
+    method main(arg: int): int {
+\tbar = getfoo()[0]++;
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[1];
+\tif ( arg == 3 ) return bar;
+\tif ( arg == 4 ) return cnt;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > binary constants
+// @Result: TypeMismatch @ 6:18
+
+class raw_bin02 {
+    field a: 1 = 0b01;
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=14, 5=42
+
+component ptex_meth01 {
+
+    method main(arg: int): int {
+    \tif ( arg == 1 ) return m(11);
+    \tif ( arg == 2 ) return m(12);
+    \tif ( arg == 3 ) return m(13);
+    \tif ( arg == 4 ) return m(14);
+        return 42;
+    }
+
+    method m<T>(x: T): T { return x; }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=17, 3=42
+
+component field02a {
+    field a: int;
+    field b: int;
+
+    constructor() {
+        a = 13;
+\tb = 17;
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a;
+\tif ( arg == 2 ) return b;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+class field03b_obj {
+    field bar: int = baz();
+    method baz(): int { return 1; }
+}
+
+component field03b {
+    field foo: field03b_obj = new field03b_obj();
+}
+
+/* 
+heap {
+    record #0:1:field03b {
+        field foo: field03b_obj = #1:field03b_obj;
+    }
+    record #1:1:field03b_obj {
+        field bar: int = int:1;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type08 {
+    field f: type[][];
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: TypeMismatch @ 6:16
+
+class type36 {
+    
+    method testm() {
+        local a: int = 2 >> null;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class class02<X> {
+  field f1: X;
+  field f2: X, f3: int;
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: UnresolvedMember @ 11:10
+
+class field_res12_a {
+    private field priv: int;
+}
+class field_res12_b extends field_res12_a {
+    
+    method testm() {
+        this.priv = 0;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type09<X, Y> {
+    field f: type09<X[], Y>[][];
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array21 {
+    field a_01: char[] =  {\'1\', \'2\'};
+    field a_02: char[] =  ""hihihi"";
+    field len1: int = length(a_01);
+    field len2: int = length(a_02);
+
+    method length(a: char[]): int {
+\treturn a.length;
+    }
+}
+
+/* 
+heap {
+    record #0:4:array21 {
+        field a_01: char[] = #1:char[2];
+        field a_02: char[] = #2:char[6];
+\tfield len1: int = int:2;
+\tfield len2: int = int:6;
+    }
+    record #1:2:char[2] {
+        field 0:char = char:49;
+        field 1:char = char:50;
+    }
+    record #2:6:char[6] {
+        field 0:char = char:104;
+        field 1:char = char:105;
+        field 2:char = char:104;
+        field 3:char = char:105;
+        field 4:char = char:104;
+        field 5:char = char:105;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class C<X> {
+}
+
+component mp_init01 {
+  field f: C<int> = makeC();
+
+  method makeC<T>(): C<T> {
+    return new C<T>();
+  }
+}
+
+/*
+heap {
+  record #0:1:mp_init01 {
+    field f: C<int> = #1:C<int>;
+  }
+  record #1:0:C<int> {
+  }
+}
+*/
+"
+"// @Harness: v2-seman
+// @Test: return correctness
+// @Result: PASS
+
+class return3 {
+    
+    method testm(): int {
+        if ( true ) return 1;
+        else return 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: constructors and inheritance
+// @Result: NoDefaultConstructor @ 13:33
+
+class constructor10_a {
+
+    constructor(a: int) {
+    }
+}
+
+class constructor10_b extends constructor10_a {
+
+    constructor(a: int, b: int) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test binding of variables within correct scope""
+// @Result: VariableRedefined @ 8:13
+
+class bound1 {
+
+    method testm() {
+        {
+            local foo: int = 1;
+            local foo: char = 2;
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: PASS
+
+class field_res10_a {
+    field testf: int;
+}
+class field_res10_b extends field_res10_a {
+    
+    method testm() {
+        testf = 0;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > xor operator
+// @Result: PASS
+
+component raw_xor01 {
+    field f1: 4  = 0x0 ^ 0xf;
+    field f2: 8  = 0xf0 ^ 0x0f;
+    field f3: 16 = 0xf3f3 ^ 0x1111;
+    field f4: 7  = 0b1110101 ^ 0b1111111;
+    field f5: 5  = 0b10101 ^ 0b10000;
+    field f6: 3  = 0b101 ^ 0b100;
+    field f7: 32 = 0xFFFF0000 ^ 0xF000F000;
+    field f8: 48 = 0xFF00FFFF0000 ^ 0xF000F000F000;
+    field f9: 64 = 0xFFFF0000FFFF0000 ^ 0xF000F000F000F000;
+}
+
+/*
+heap {
+    record #0:1:raw_xor01 {
+\tfield f1: 4  = raw.4:0xf; 
+\tfield f2: 8  = raw.8:0xff; 
+\tfield f3: 16 = raw.16:0xe2e2; 
+\tfield f4: 7  = raw.7:0x0a;
+\tfield f5: 5  = raw.5:0x05; 
+\tfield f6: 3  = raw.3:0x1; 
+\tfield f7: 32 = raw.32:0x0ffff000; 
+\tfield f8: 48 = raw.48:0x0f000ffff000; 
+\tfield f9: 64 = raw.64:0x0ffff0000ffff000; 
+    }
+}
+*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type23 {
+    field f: function(1);
+    field g: function(2): 2;
+    field h: function(3): 3;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component method11 {
+    method m1<X, Y>(a: type<X, Y>, b: type<Y>): type<X> {
+        return b;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42
+
+class virtual01a_1 {
+    method val(): int { return 11; }
+}
+
+class virtual01a_2 extends virtual01a_1 {
+    method val(): int { return 21; }
+}
+
+class virtual01a_3 extends virtual01a_1 {
+    method val(): int { return 31; }
+}
+
+component virtual01a {
+    field a: virtual01a_1 = new virtual01a_1();
+    field b: virtual01a_1 = new virtual01a_2();
+    field c: virtual01a_1 = new virtual01a_3();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val();
+\tif ( arg == 2 ) return b.val();
+\tif ( arg == 3 ) return c.val();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component constr01 {
+    constructor() { }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr7 {
+  field foo: type = new foo(foo);
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_raw04 {
+    field x: int;
+    field a: 32 = x :: 32;
+    field b: 48 = -109 :: 48;
+    field c: 64 = 10909109 :: 64;
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component depend02a {
+    field foo: int = depend02b.bar;
+}
+
+component depend02b {
+    field bar: int;
+    constructor() {
+\tbar = 42;
+    }
+}
+
+/* 
+heap {
+    record #0:1:depend02a {
+        field foo: int = int:42;
+    }
+    record #1:1:depend02b {
+\tfield bar: int = int:42;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedBinOp @ 6:16
+
+class type33 {
+    
+    method testm() {
+        local a: int = 2 ^ null;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: tir2c > raw types > concat operator
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=0
+
+component raw_concat01 {
+    field f1: 8  = 0x0  # 0xf;
+    field f2: 16 = 0xf0 # 0x0f;
+    field f3: 32 = 0xf3f3  # 0x1111;
+    field f4: 14 = 0b1110101  # 0b1111111;
+    field f5: 10 = 0b10101  # 0b10000;
+    field f6: 6  = 0b101  # 0b100;
+    field f7: 32 = 0xFFFF  # 0xF000;
+
+    method main(arg: int): bool {
+        if ( arg == 1 ) return (0x0  # 0xf) == f1;
+        if ( arg == 2 ) return (0xf0 # 0x0f) == f2;
+        if ( arg == 3 ) return (0xf3f3  # 0x1111) == f3;
+        if ( arg == 4 ) return (0b1110101  # 0b1111111) == f4;
+        if ( arg == 5 ) return (0b10101  # 0b10000) == f5;
+        if ( arg == 6 ) return (0b101  # 0b100) == f6;
+        if ( arg == 7 ) return (0xFFFF  # 0xF000) == f7;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=1, 1=2, 2=3, 3=4, 4=5
+
+component prepost24 {
+    method main(arg: int): int {
+\treturn ++arg;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > and operator
+// @Result: PASS
+
+class raw_and05 {
+    field a: 2;
+    field c: 1 = a & 0b1;
+    field d: 1 = 0b1 & a;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class A<X> { } 
+class B<X> extends A<int> { }
+
+class cast13 {
+   method m(x: A<int>) {
+      local f = x :: (B<char>);
+   }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class array1 {
+  field a: type[];
+  field b: type[][];
+  field c: type[][][];
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class A<X> { } 
+
+class instof08 {
+   method m(x: A<int>) {
+      local f = x <: (A<int>);
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; while statement
+// @Result: TypeMismatch @ 6:13
+
+class type18 {
+    
+    method testm() {
+        while ( 0 ) ;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=32, 5=97, 6=42
+
+class Pair<X, Y> {
+    field a: X;
+    field b: Y;
+
+    constructor(x: X, y: Y) {
+        a = x;
+        b = y;
+    }
+}
+
+class I {
+    field val: int;
+    constructor(v: int) {
+        val = v;
+    }
+}
+
+component ptex_pair03 {
+    field a: Pair<int, Pair<bool, bool> > = new Pair<int, Pair<bool, bool> >(11, new Pair<bool, bool>(true, false));
+    field b: Pair<int, I> = new Pair<int, I>(21, new I(31));
+    field c: Pair<function(): int, char> = new Pair<function(): int, char>(f32, 'a');
+
+    method main(arg: int): int {
+        if ( arg == 1 ) return getA(a);
+        if ( arg == 2 ) return getA(b);
+        if ( arg == 3 ) return getB(b).val;
+        if ( arg == 4 ) return getA(c)();
+        if ( arg == 5 ) return getB(c) :: int;
+\treturn 42;
+    }
+
+    method f32(): int { return 32; }
+
+    method getA<X, Y>(p: Pair<X, Y>): X { return p.a; }
+    method getB<X, Y>(p: Pair<X, Y>): Y { return p.b; }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component raw_and01 {
+    field res_01: 32 = op(0x0f, 0xfe);
+    field res_02: 32 = op(2, -1);
+    field res_03: 32 = op(-1, -1);
+    field res_04: 32 = op(0, -1);
+    field res_05: 32 = op(0xf0, 0xaa);
+    field res_06: 32 = op(65535, 345);
+    field res_07: 32 = op(0xffff0000, 65537);
+    field res_08: 32 = op(64, 8);
+    field res_09: 32 = op(255, 5);
+    field res_10: 32 = op(0xaa, 0x0a);
+
+    method op(a: 32, b: 32): 32 {
+\treturn a & b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(0x0f, 0xfe)        == res_01;
+\tif ( arg == 2 ) return op(2, -1)             == res_02;
+\tif ( arg == 3 ) return op(-1, -1)            == res_03;
+\tif ( arg == 4 ) return op(0, -1)             == res_04;
+\tif ( arg == 5 ) return op(0xf0, 0xaa)        == res_05;
+\tif ( arg == 6 ) return op(65535, 345)        == res_06;
+\tif ( arg == 7 ) return op(0xffff0000, 65537) == res_07;
+\tif ( arg == 8 ) return op(64, 8)             == res_08;
+ \tif ( arg == 9 ) return op(255, 5)            == res_09;
+\tif ( arg == 10 ) return op(0xaa, 0x0a)       == res_10;
+\treturn false;
+    }
+
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_infer03 {
+    method first<X, Y>(a: X, b: Y): X {
+        return a;
+    }
+    method second<X, Y>(a: X, b: Y): Y {
+        return b;
+    }
+    method test() {
+\tlocal x: int = first(0, 0);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: InvalidTypeQuery @ 8:19
+
+class A<X> { } 
+
+class instof09 {
+   method m(x: A<int>) {
+      local f = x <: (A<char>);
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component dowhile07 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        do {
+\t    cumul += i++;
+\t    if ( i <= max ) continue;
+\t    break;
+\t} while ( true );
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:dowhile07 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: statements
+// @Result: NotAStatement @ 6:5
+
+class stmt08 {
+    
+    method testm() {
+        null;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: TypeCast operator
+// @Result: PASS
+
+class cast06_a {
+}
+
+class cast06_b extends cast06_a {
+}
+
+class cast06_c extends cast06_b {
+}
+
+component cast06 {
+    field foo: cast06_a = new cast06_c();
+    field bar: cast06_b = foo :: cast06_b;
+}
+
+/* 
+heap {
+    record #0:2:cast06 {
+        field foo: cast06_a = #1:cast06_c;
+        field bar: cast06_b = #1:cast06_c;
+    }
+    record #1:0:cast06_c {
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of evaluation)
+// @Result: PASS
+
+class init34 {
+    
+    method testm(): bool {
+        local b: bool;
+        while ( b = true ) return b;
+        return false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of operations)
+// @Result: PASS
+
+class order_init14 {
+    
+    method testm(): int[][] {
+        local foo: int;
+        return new int[foo = 0][foo];
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Pair<X, Y> {
+  field a: X;
+  field b: Y;
+
+  method first(): X {
+    return a;
+  }
+
+  method second(): Y {
+    return b;
+  }
+}
+
+component Client {
+  method test() {
+    local p = new Pair<int, bool>();
+    local b: int = p.a;
+    local c: bool = p.b;
+  }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (ternary expressions)
+// @Result: VariableNotInitialized @ 8:14
+
+class ternay_short_init03 {
+    
+    method testm(p: bool) {
+        local uninit: bool;
+        local result: bool = p or (uninit = p) ? p:p;
+        result = uninit;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: ExpectedVarType @ 8:19
+
+component local6 {
+    
+    method testm() {
+        local foo: local6;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class scope04 {
+  method first<X>(x: X): X {
+    return x;
+  }
+
+  method second<X, Y>(x: X, y: Y): Y {
+    return y;
+  }
+
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class switch1 {
+  method m() {
+     local a: int = -1, b: int, c: int;
+
+     switch ( a ) {
+     }
+
+     switch ( a ) {
+       default ;
+     }
+
+     switch ( a ) {
+       case(0) ;
+     }
+
+     switch ( a ) {
+       case(0) ;
+       case(1) ;
+     }
+
+     switch ( a ) {
+       case(0, 1) ;
+     }
+
+     switch ( a ) {
+       case(0) ;
+       case(1) ;
+       default ;
+     }
+
+     switch ( a ) {
+       case(0+0) ;
+     }
+  }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedBinOp @ 6:16
+
+class type34 {
+    
+    method testm() {
+        local a: int = 2 & null;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component arith01 {
+    field res_01: int = op(1, 2);
+    field res_02: int = op(2, 1);
+    field res_03: int = op(-1, 1);
+    field res_04: int = op(-1, 0);
+    field res_05: int = op(-200, 13);
+    field res_06: int = op(65535, 1);
+    field res_07: int = op(13, 17);
+    field res_08: int = op(255, 12);
+    field res_09: int = op(255, -255);
+    field res_10: int = op(1000000, 48576);
+
+    method op(a: int, b: int): int {
+\treturn a + b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(1, 2)            == res_01;
+\tif ( arg == 2 )  return op(2, 1)            == res_02;
+\tif ( arg == 3 )  return op(-1, 1)           == res_03;
+\tif ( arg == 4 )  return op(-1, 0)           == res_04;
+\tif ( arg == 5 )  return op(-200, 13)        == res_05;
+\tif ( arg == 6 )  return op(65535, 1)        == res_06;
+\tif ( arg == 7 )  return op(13, 17)          == res_07;
+\tif ( arg == 8 )  return op(255, 12)         == res_08;
+\tif ( arg == 9 )  return op(255, -255)       == res_09;
+\tif ( arg == 10 ) return op(1000000, 48576)  == res_10;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class meth01 {
+
+          method m1();
+  private method m3();
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=11, 3=11, 4=42
+
+class private05_a {
+    method getf(): int { return val; }
+    private field val: int = 11;
+}
+
+class private05_b extends private05_a {
+    private field val: bool = true;
+}
+
+class private05_c extends private05_a {
+    private field val: char = '3';
+}
+
+component private05 {
+    field a: private05_a = new private05_a();
+    field b: private05_a = new private05_b();
+    field c: private05_a = new private05_c();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.getf();
+\tif ( arg == 2 ) return b.getf();
+\tif ( arg == 3 ) return c.getf();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class raw_raw02 {
+    field a: boolean = (0x0 == 0x00);
+    field b: boolean = (0x00 == 0x0000);
+    field c: boolean = (0x00000 == 0x000000);
+    field d: boolean = (0x0000000 == 0x00000000);
+    field e: boolean = (0x0000 == 0x0000000000);
+    field f: boolean = (0x0000 == 0x000000000000);
+    field g: boolean = (0x0 == 0x0000000000000000);
+}
+"
+"// @Harness: v2-exec
+// @Test: while statements
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component while08 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0, loop = 1;
+        while ( loop++ < 2 ) {
+            for ( i = 1; ; cumul += i, i++ ) {
+\t        if ( i > max ) break;
+\t        else continue;
+\t    }
+\t}
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_char01 {
+    field a: int = '0';
+    field b: int = '\
+';
+    field c: int = '\\367';
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_char03 {
+    field a: int = m('0');
+    field b: int = m('\
+');
+    field c: int = m('\\367');
+    method m(x: int): int {
+\treturn x;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component arith04 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(2, -1);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(0, -1);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -1);
+    field res_07: int = op(13455, -17);
+    field res_08: int = op(64, 8);
+    field res_09: int = op(255, 5);
+    field res_10: int = op(-48576, 1000);
+
+    method op(a: int, b: int): int {
+\treturn a / b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:arith04 {
+        field res_01: int = int:0;
+        field res_02: int = int:-2;
+        field res_03: int = int:1;
+        field res_04: int = int:0;
+        field res_05: int = int:15;
+        field res_06: int = int:-65535;
+        field res_07: int = int:-791;
+        field res_08: int = int:8;
+        field res_09: int = int:51;
+        field res_10: int = int:-48;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_comp05 {
+    field res_01: 32 = op(-2);
+    field res_02: 32 = op(-1);
+    field res_03: 32 = op(1100);
+    field res_04: 32 = op(0);
+    field res_05: 32 = op(-13);
+    field res_06: 32 = op(1);
+    field res_07: 32 = op(-17);
+    field res_08: 32 = op(-65536);
+    field res_09: 32 = op(255);
+    field res_10: 32 = op(1000000);
+
+    method op(a: 32): 32 {
+\treturn (~(a & 0xfffffff)) >> 4;
+    }
+}
+
+/* 
+heap {
+    record #0:10:raw_comp05 {
+        field res_01: raw.32 = raw.32:0x000000;
+        field res_02: raw.32 = raw.32:0x000000;
+        field res_03: raw.32 = raw.32:0xffffbb;
+        field res_04: raw.32 = raw.32:0xffffff;
+        field res_05: raw.32 = raw.32:0x000000;
+        field res_06: raw.32 = raw.32:0xffffff;
+        field res_07: raw.32 = raw.32:0x000001;
+        field res_08: raw.32 = raw.32:0x000fff;
+        field res_09: raw.32 = raw.32:0xfffff0;
+        field res_10: raw.32 = raw.32:0xff0bdb;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=10, 2=10, 3=42, 4=0
+
+component cmpassn16 {
+    field foo: int[] = { 14, 42 };
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = foo[0] -= 4;
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return bar;
+\tif ( arg == 3 ) return foo[1];
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > binary constants
+// @Result: TypeMismatch @ 6:18
+
+class raw_bin09 {
+    field a: 15 = 0b0100001010100010;
+}
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @HeapGC: false
+// @Result: PASS
+
+component fold01 {
+    field a: int;
+    field b: int;
+
+    constructor() {
+        local array = { 1, 2, 3, 4, 5 };
+\ta = fold(add, array, 5);
+        b = fold(mult, array, 5);
+    }
+
+    method add(a: int, b: int): int {
+\treturn a + b;
+    }
+
+    method mult(a: int, b: int): int {
+        return a * b;
+    }
+
+    // iterative version of fold
+    method fold(f: function(int, int): int, a: int[], m: int): int {
+        local cumul = a[0];
+        local cntr = 1;
+        for ( ; cntr < m; cntr++ ) cumul = f(cumul, a[cntr]);
+\treturn cumul; 
+    }
+}
+
+/* 
+heap {
+    record #0:2:fold01 {
+        field a: int = int:15;
+        field b: int = int:120;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; for statements
+// @Result: TypeMismatch @ 7:13
+
+class type24 {
+    
+    method testm() {
+        local i: int;
+        for ( i = false; ; ) ;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class method06 {
+    method m1<X>(a: type<X, Y>, b: type<Y>): type<X> {
+        return b;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_flip04 {
+    field res_01: 4 = flip(0xe);
+    field res_02: 4 = flip(0x2);
+    field res_03: 4 = flip(0x1);
+    field res_04: 4 = flip(0x8);
+    field res_05: 4 = flip(0xf);
+    field res_06: 4 = flip(0x7);
+    field res_07: 4 = flip(0xa);
+
+    method flip(a: 4): 4 {
+\treturn a[0] # a[1] # a[2] # a[3];
+    }
+}
+
+/* 
+heap {
+    record #0:6:raw_flip04 {
+        field res_01: raw.4 = raw.4:0x7;
+        field res_02: raw.4 = raw.4:0x4;
+        field res_03: raw.4 = raw.4:0x8;
+        field res_04: raw.4 = raw.4:0x1;
+        field res_05: raw.4 = raw.4:0xf;
+        field res_06: raw.4 = raw.4:0xe;
+        field res_07: raw.4 = raw.4:0x5;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_infer07 {
+    method first<X, Y>(a: X, b: Y): X {
+        return a;
+    }
+    method second<X, Y>(a: X, b: Y): Y {
+        return b;
+    }
+    method test() {
+\tlocal x = first(0, false);
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:12
+
+class field06 {
+    field g: type<X>;
+    field f = 0;
+}
+"
+"// @Harness: v2-seman
+// @Test: cannot declare duplicate fields
+// @Result: MemberRedefined @ 6:12
+
+component field2 {
+    field testf: int;
+    field testf: char;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedOperator @ 7:21
+
+class inc02 {
+    method testm(a: bool) {
+        local foo = a++;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=6, 3=7, 4=42
+
+component field07a {
+    field a: int[] = { 6, 7 };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a != null ? 13 : 77;
+\tif ( arg == 2 ) return a[0];
+\tif ( arg == 3 ) return a[1];
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeQuery (instanceof) operation
+// @Result: PASS
+
+class instof02a_01 {
+    field bar: instof02a_02;
+    field foo: bool = bar instanceof instof02a_01;
+}
+
+class instof02a_02 extends instof02a_01 {
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class instof04b {
+   method m() {
+      if ( x <: (Type<int[]>) ) ;
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array04 {
+    field a_02: int[][] =  { {1, 2}, {-2} };
+}
+
+/* 
+heap {
+    record #0:1:array04 {
+        field a_02: int[][] = #1:int[][2];
+    }
+    record #1:2:int[][2] {
+        field 0:int[] = #2:int[2];
+        field 1:int[] = #3:int[1];
+    }
+    record #2:2:int[2] {
+        field 0:int = int:1;
+        field 1:int = int:2;
+    }
+    record #3:1:int[1] {
+        field 0:int = int:-2;
+    }
+} */
+"
+"/*
+ * This program simply tests the functionality of the Radio (wireless signal )
+ *  driver.
+ * @author Xiaoli Gong
+ */
+program TestRadio {
+\tentrypoint main = TestRadio.entry;
+\tentrypoint adc = ADC.convHandler;
+\tentrypoint spi_stc = SPI.interruptHandler;
+\tentrypoint timer0_comp = Timer0.compareHandler;
+\tentrypoint usart0_rx = USART0.rec_handler;
+\tentrypoint usart0_tx = USART0.tran_handler;
+}
+
+component TestRadio {
+\tfield flag: boolean;
+\tfield msg: TOS_Msg;
+\tfield msg_sent: char[] = ""One Packet received:\
+"";
+\tfield msg_addr: char[] = ""Packet Addr:\
+"";
+\tfield msg_data: char[] = ""Packet Data:\
+"";
+\tfield counter: int = 0;
+
+\tconstructor() {
+\t\tmsg = new TOS_Msg();
+\t\tmsg.length = 0x05;
+\t\tmsg.data[0] = 0x33;
+\t\tmsg.data[1] = 0xcc;
+\t\tmsg.data[2] = 0x03;
+\t\tmsg.data[3] = 0x04;
+\t\tmsg.data[4] = 0x05;
+\t\t// CC1000Radio.SetsendDoneCallback(sendbusy);
+\t}
+
+\tmethod sendbusy(data: TOS_Msg, result: boolean) {
+\t\t//CC1000Radio.WakeupTimerfired();
+\t}
+
+\tmethod receivedata(data:TOS_Msg): TOS_Msg {
+\t\tlocal i: int = 0;
+\t\tcounter++;
+\t\tMica2.displayOnLEDs(counter::3);
+\t\tif (counter % 50 == 0){
+\t\t\tUSART0.printString(msg_sent, msg_sent.length);
+\t\t\tUSART0.printString(msg_addr, msg_addr.length);
+\t\t\tUSART0.printHex16(msg.addr);
+\t\t\tUSART0.printString(msg_data, msg_data.length);
+\t\t\tfor (i = 0; i < msg.length::int; i++)
+\t\t\t\tUSART0.printHex8(msg.data[i]);
+\t\t}
+\t\treturn data;
+\t}
+
+\tmethod entry() {
+\t\tlocal i: int = 0;
+\t\tMica2.startLEDs();
+\t\tMica2.startTerminal();
+\t\tCC1000Radio.init();
+\t\tCC1000Radio.SetsendDoneCallback(sendbusy);
+\t\tCC1000Radio.SetReceiveCallback(receivedata);
+\t\tCC1000Radio.start();
+\t\tif (i < 1) {
+\t\t\ti++;
+\t\t\tMCU.enable();
+\t\t\tdevice.sleep();
+\t\t}
+\t}
+
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=42, 4=42, 5=11, 6=21, 7=31, 8=42
+
+class delegate09_a {
+    method val(): int { return 11; }
+}
+
+class delegate09_b extends delegate09_a {
+    method val(): int { return 21; }
+}
+
+class delegate09_c extends delegate09_a {
+    method val(): int { return 31; }
+}
+
+component delegate09 {
+    field a: delegate09_a = new delegate09_a();
+    field b: delegate09_a = new delegate09_b();
+    field c: delegate09_a = new delegate09_c();
+    field am: function():int = a.val;
+    field bm: function():int = b.val;
+    field cm: function():int;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return am();
+\tif ( arg == 2 ) return bm();
+\t//if ( arg == 3 ) return cm();
+
+        local m = m42;
+\tif ( arg == 5 ) m = a.val;
+\tif ( arg == 6 ) m = b.val;
+\tif ( arg == 7 ) m = c.val;
+
+\treturn m();
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=13, 3=NullCheckException, 4=42
+
+class rtex_null10_obj {
+    method baz(): int { return 13; }
+}
+
+component rtex_null10 {
+    field a: rtex_null10_obj;
+    field b: rtex_null10_obj = new rtex_null10_obj();
+    field c: rtex_null10_obj;
+
+    method main(arg: int): int {
+\tlocal m = m42;
+\tif ( arg == 1 ) m = getf(a);
+\tif ( arg == 2 ) m = getf(b);
+\tif ( arg == 3 ) m = getf(c);
+\treturn m();
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+
+    method getf(o: rtex_null10_obj): function(): int {
+\treturn o.baz;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: virtual method invocations
+// @Result: PASS
+
+class inh20_a {
+    method getf(): function(): int { return this.val; }
+    private method val(): int { return 1; }
+}
+
+class inh20_b extends inh20_a {
+    private method val(): int { return 2; }
+}
+
+component inh20 {
+    field a: function():int = new inh20_a().getf();
+    field b: function():int = new inh20_b().getf();
+    field av: int = a();
+    field bv: int = b();
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class char_int02 {
+    field a: int;
+    field b: char = a :: char;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type16<X, Y> {
+    field f: type14<function(X): Y, Y>;
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (ternary expressions)
+// @Result: VariableNotInitialized @ 8:12
+
+class ternay_init03 {
+    
+    method testm(b: bool): int {
+        local uninit: int;
+        local r: int = b ? 1:(uninit = 0);
+        return uninit;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class compare01<X> {
+    field f: X;
+    field b: bool = f == f;
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeQuery (instanceof) operation
+// @Result: ExpectedObjectType @ 7:30
+
+class instof04a_01 {
+    field bar: instof04a_01;
+    field foo: bool = bar instanceof instof04a_02;
+}
+
+component instof04a_02 {
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=0, 2=0, 3=0, 4=1, 5=0, 6=0
+
+class A<X> { } 
+class B<X> extends A<int> { }
+
+component ptex_instof05 {
+
+   field a: A<int> = new A<int>();
+   field b: A<int> = new B<int>();
+   field c: A<int> = new B<char>();
+   field d: A<int> = new B<bool>();
+
+   method m(x: A<int>): bool {
+      return x <: (B<char>);
+   }
+
+   method main(arg: int): bool {
+       if ( arg == 1 ) return m(null);
+       if ( arg == 2 ) return m(a);
+       if ( arg == 3 ) return m(b);
+       if ( arg == 4 ) return m(c);
+       if ( arg == 5 ) return m(d);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Transform<R, E> {
+    method visitA(n: A, e: E): R;
+    method visitB(n: B, e: E): R;
+}
+
+class A {
+    method accept<R, E>(v: Transform<R, E>, e: E): R;
+}
+
+class B {
+    method accept<R, E>(v: Transform<R, E>, e: E): R;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component fold03 {
+    field a: int;
+    field b: int;
+
+    constructor() {
+        local array = new int[1000];
+\ta = fold(add, array, array.length - 1);
+        b = fold2(mult, array, array.length - 1);
+    }
+
+    method add(a: int, b: int): int {
+\treturn a + b;
+    }
+
+    method mult(a: int, b: int): int {
+        return a * b;
+    }
+
+    // iterative version of fold
+    method fold(f: function(int, int): int, a: int[], m: int): int {
+\treturn m == 0 ? a[0] : f(fold(f, a, m-1), a[m]);        
+    }
+
+    method fold2<T>(f: function(T, T): T, a: T[], m: int): T {
+\tif ( m == 0 ) return a[0];
+\tlocal p: T = fold2(f, a, m-1);
+\tlocal r: T = f(p, a[m]);
+\treturn r;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_id12 {
+    method test(): function(int): int {
+\tlocal x: function(int): int = id;
+\treturn x;
+    }
+    method id<X>(x: X): X {
+\treturn x;\t
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=0
+
+component overflow02 {
+
+    field f: int = 32767;
+    field g: int = 66535;
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return (f + 1) > 0;
+\tif ( arg == 2 ) return (f + 1) > f;
+\tif ( arg == 3 ) return (g + 1) > 0;
+\tif ( arg == 4 ) return (g + 1) > g;
+\tif ( arg == 5 ) return (f + f) > 0;
+\tif ( arg == 6 ) return (f + f) > f;
+\tif ( arg == 7 ) return (g + g) > 0;
+\tif ( arg == 8 ) return (g + g) > g;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: order of evaluation
+// @Result: 0=0, 1=1, 2=2, 3=3, 4=0
+
+component order01 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    method op(a: int, b: int): int {
+\treturn first(a) + second(b);
+    }
+
+    method first(a: int): int {
+        order[pos] = 1;
+        pos++;
+        return a;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method main(arg: int): int {
+        local result = op(1, 2);
+\tif ( arg == 1 ) return order[0];
+\tif ( arg == 2 ) return order[1];
+\tif ( arg == 3 ) return result;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization of arrays of raws
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=0
+
+component array_raw07 {
+    field a: 29[] = { 0xfe71000, 0b100, 'c', 0xffedd };
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return a[0] == 0xfe71000;
+\tif ( arg == 2 ) return a[1] == 0x0000004;
+\tif ( arg == 3 ) return a[2] == 0x0000063;
+\tif ( arg == 4 ) return a[3] == 0x00ffedd;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_delegate03 {
+    method makeArray<X>(a: X): X[] {
+\treturn new X[0];\t
+    }
+    method test(): int[] {
+\tlocal x: function(int): int[] = makeArray;
+\treturn x(0);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+class super05_a {
+    field foo: int = 1;
+    field joe: int;
+    constructor(j: int) {
+        joe = j;
+    }
+}
+
+class super05_b extends super05_a {
+    field bar: int = foo + joe;
+    field john: int;
+    constructor() : super(2) {
+        john = bar + 1;
+    }
+}
+
+component super05 {
+    field baz: super05_a = new super05_b();
+}
+
+/* 
+heap {
+    record #0:1:super05 {
+        field baz: super05_a = #1:super05_b;
+    }
+    record #1:4:super05_b {
+        field foo: int = int:1;
+        field joe: int = int:2;
+        field bar: int = int:3;
+        field john: int = int:4;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=42, 3=31, 4=42, 5=11, 6=21, 7=31, 8=42
+
+class delegate10_a {
+    method val(): int { return 11; }
+}
+
+class delegate10_b extends delegate10_a {
+    method val(): int { return 21; }
+}
+
+class delegate10_c extends delegate10_a {
+    method val(): int { return 31; }
+}
+
+component delegate10 {
+    field a: delegate10_a = new delegate10_a();
+    field b: delegate10_a = new delegate10_b();
+    field c: delegate10_a = new delegate10_c();
+    field am: function():int = a.val;
+    field bm: function():int;
+    field cm: function():int = c.val;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return am();
+\t//if ( arg == 2 ) return bm();
+\tif ( arg == 3 ) return cm();
+
+        local m = m42;
+\tif ( arg == 5 ) m = a.val;
+\tif ( arg == 6 ) m = b.val;
+\tif ( arg == 7 ) m = c.val;
+
+\treturn m();
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeParameterRedefined @ 4:21
+
+class scope07<X, Y, X> {
+  method first(x: X): X {
+    return x;
+  }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class assign02<X> {
+   field f: assign02<X>;
+   field g: assign02<X> = f;
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Node<X> {
+    field value: X;
+    field link: Node<X>;
+}
+
+class List<X> {
+    field head: Node<X>;
+
+    method add(x: X) {
+\tlocal nn = new Node<X>();
+\tnn.value = x;
+\tnn.link = head;
+\thead = nn;\t
+    }
+
+    method apply(f: function(X)) {
+\tlocal pos = head;
+\twhile ( pos != null ) {
+\t    f(pos.value);
+\t    pos = pos.link;
+\t}
+    }
+}
+
+component cl_list02 {
+    method test() {
+\tlocal x: List<int> = makeList(0, 0);
+\tx.apply(print);
+    }
+    method makeList<T>(a: T, b: T): List<T> {
+\tlocal list = new List<T>();
+\tlist.add(a);
+\tlist.add(b);
+\treturn list;
+    }
+    method print(i: int) {
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: method resolution
+// @Result: UnresolvedMember @ 11:10
+
+class method_res07_a {
+    
+    private method priv() {
+    }
+}
+class method_res07_b extends method_res07_a {
+    
+    method testm() {
+        this.priv();
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=10
+
+component switch04 {
+\tfield foo: int;
+\tmethod main(args: int): int {
+\t\tswitch (foo) {
+\t\t\tcase (0) return 10;
+\t\t\tcase (1) return 11;
+\t\t\tdefault return -1;
+\t\t}
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 7:12
+
+class init03 {
+    
+    method testm(): int {
+        local foo: int;
+        return foo;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_id09 {
+    method test() {
+\tlocal x = new int[8];
+\tx[id(0)] = 0;
+    }
+    method id<X>(x: X): X {
+\treturn x;\t
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: compile-time constants for octal integers
+// @Result: PASS
+
+component raw_oct01 {
+    field a: 3 = 00;
+    field b: 3 = 01;
+    field c: 3 = 02;
+    field d: 3 = 07;
+    field e: 6 = 010;
+    field f: 6 = 011;
+    field g: 6 = 017;
+    field h: 9 = 0377;
+    field i: 15 = 077777;
+    field j: 18 = 0177777;
+    field k: 21 = 04000000;
+    field l: 30 = 04000000000;
+}
+
+/* 
+heap {
+    record #0:12:raw_oct01 {
+        field a: raw.3  = raw.3:0x0;
+        field b: raw.3  = raw.3:0x1;
+        field c: raw.3  = raw.3:0x2;
+        field d: raw.3  = raw.3:0x7;
+        field e: raw.6  = raw.6:0x8;
+        field f: raw.6  = raw.6:0x9;
+        field g: raw.6  = raw.6:0xf;
+        field h: raw.9  = raw.9:0xff;
+        field i: raw.15 = raw.15:0x7fff;
+        field j: raw.18 = raw.18:0xffff;
+        field k: raw.21 = raw.21:0x100000;
+        field l: raw.30 = raw.30:0x20000000;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component default04a {
+    field foo: int[] = new int[1];
+    field bar: int = foo[0];
+}
+
+/* 
+heap {
+    record #0:2:default04a {
+        field foo: int[] = #1:int[1];
+        field bar: int = int:0;
+    }
+    record #1:1:int[1] {
+        field 0: int = int:0;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=8, 2=42, 3=1, 4=1, 5=0
+
+component cmpassn17 {
+    field foocnt: int;
+    field indcnt: int;
+
+    field foo: int[] = { 6, 42 };
+    field bar: int;
+
+    method getfoo(): int[] {
+\tfoocnt++;
+\treturn foo;
+    }
+    
+    method getind(): int {
+\tindcnt++;
+\treturn 0;
+    }
+
+    method main(arg: int): int {
+\tgetfoo()[getind()] += 2;
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[1];
+\tif ( arg == 3 ) return foocnt;
+\tif ( arg == 4 ) return indcnt;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42
+
+class Self<T> {
+}
+
+class Myself extends Self<Self<Myself> > {
+    field val: int;
+    constructor(v: int) {
+        val = v;
+    }
+}
+
+component ptex_self02 {
+    field f: Myself = new Myself(11);
+    field g: Myself = new Myself(21);
+    field h: Myself = new Myself(31);
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return f.val;
+\tif ( arg == 2 ) return g.val;
+\tif ( arg == 3 ) return h.val;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: integer comparison operators
+// @Result: 0=0, 1=0, 2=1, 3=0, 4=0, 5=0, 6=0, 7=1, 8=0, 9=0, 10=1
+
+component comp02 {
+
+    method op(a: int, b: int): bool {
+\treturn a > b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(1, 2);
+\tif ( arg == 2 ) return op(2, 1);
+\tif ( arg == 3 ) return op(-1, 1);
+\tif ( arg == 4 ) return op(-1, 0);
+\tif ( arg == 5 ) return op(-200, -200);
+\tif ( arg == 6 ) return op(65535, 65535);
+\tif ( arg == 7 ) return op(14, 13);
+\tif ( arg == 8 ) return op(13, 14);
+\tif ( arg == 9 ) return op(-1255, -255);
+\tif ( arg == 10 ) return op(1000000, 48576);
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 11:16
+
+class init21 {
+    
+    method testm() {
+        local foo: int;
+        do {
+            if ( true ) continue;
+            foo = 0;
+        }
+        while ( foo < 2 );
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Visitor<E> {
+    method visitA(n: A, e: E);
+    method visitB(n: B, e: E);
+}
+
+class S {
+    method accept<E>(v: Visitor<E>, e: E);
+}
+
+class A extends S {
+    method accept<E>(v: Visitor<E>, e: E) { v.visitA(this, e); }
+}
+
+class B extends S {
+    method accept<E>(v: Visitor<E>, e: E) { v.visitB(this, e); }
+}
+
+class PriceList {
+}
+
+class Precious extends PriceList {
+}
+
+class Thief extends Visitor<PriceList> {
+    method visitA(n: A, e: PriceList) {
+    }
+    method visitB(n: B, e: PriceList) {
+    }
+}
+
+component Client {
+    field a: S = new A();
+    field b: S = new B();
+    field thief: Thief = new Thief();
+
+    method test() {
+\ta.accept(thief, new Precious());
+\tb.accept(thief, new Precious());
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: null exceptions
+// @Result: NullCheckException @ 7:25
+
+class null10_obj {
+    method baz();
+}
+
+component null10 {
+    field foo: null10_obj = null;
+    field bar: function() = foo.baz;
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class C<X> {
+}
+
+component mp_init04 {
+  field f: C<int> = makeC();
+  field g: C<char> = makeC();
+
+  method makeC<T>(): C<T> {
+    return new C<T>();
+  }
+}
+
+/*
+heap {
+  record #0:2:mp_init04 {
+    field f: C<int> = #1:C<int>;
+    field g: C<char> = #2:C<char>;
+  }
+  record #1:0:C<int> {
+  }
+  record #2:0:C<char> {
+  }
+}
+*/
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component default05a {
+    field foo: char[] = new char[1];
+    field bar: char = foo[0];
+}
+
+/* 
+heap {
+    record #0:2:default05a {
+        field foo: char[] = #1:char[1];
+        field bar: char = char:0;
+    }
+    record #1:1:int[1] {
+        field 0: char = char:0;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=21, 3=12, 4=22, 5=42
+
+class Visitor<E, R> {
+    method visitA(n: A, e: E): R;
+    method visitB(n: B, e: E): R;
+}
+
+class Item {
+    method accept<E, R>(v: Visitor<E, R>, e: E): R;
+}
+
+class A extends Item {
+    method accept<E, R>(v: Visitor<E, R>, e: E): R { return v.visitA(this, e); }
+}
+
+class B extends Item {
+    method accept<E, R>(v: Visitor<E, R>, e: E): R { return v.visitB(this, e); }
+}
+
+class Env {
+    field base: int;
+    constructor(b: int) {
+         base = b;
+    }
+}
+
+class Printer extends Visitor<Env, int> {
+    method visitA(n: A, e: Env): int {
+        return 1 + e.base;
+    }
+    method visitB(n: B, e: Env): int {
+        return 2 + e.base;
+    }
+}
+
+component ptex_visitor03 {
+    field af: function(Visitor<Env, int>, Env): int = new A().accept;
+    field bf: function(Visitor<Env, int>, Env): int = new B().accept;
+
+    field v: Printer = new Printer();
+
+    field e1: Env = new Env(10);
+    field e2: Env = new Env(20);
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return af(v, e1);
+\tif ( arg == 2 ) return af(v, e2);
+\tif ( arg == 3 ) return bf(v, e1);
+\tif ( arg == 4 ) return bf(v, e2);
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=21, 3=48, 4=97, 5=42
+
+class Self<T> {
+    field self: T;
+}
+
+class W<T> extends Self<W<T> > {
+    field val: T;
+    constructor(v: T) {
+        self = this;
+        val = v;
+    }
+}
+
+component ptex_self04 {
+    field f: W<int> = new W<int>(11);
+    field g: W<int> = new W<int>(21);
+    field h: W<char> = new W<char>('0');
+    field j: W<char> = new W<char>('a');
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return f.self.val;
+\tif ( arg == 2 ) return g.val;
+\tif ( arg == 3 ) return h.self.val;
+\tif ( arg == 4 ) return j.val;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > and operator
+// @Result: PASS
+
+class raw_and03 {
+    field a: 16;
+    field b: 16;
+    field c: 16 = a & b;
+    field d: 16 = b & a;
+}
+"
+"// @Harness: v2-exec
+// @Test: dynamically allocated memory exceptions
+// @Result: 0=42, 1=AllocationException, 2=AllocationException, 3=AllocationException, 4=42
+
+class rtex_alloc03_obj {
+    field foo: int;
+    constructor(i: int) { 
+\tfoo = i; 
+    }
+}
+
+component rtex_alloc03 {
+
+    method foo(): rtex_alloc03_obj {
+\treturn new rtex_alloc03_obj(11);
+    }
+
+    method main(arg: int): int {
+\tif ( arg == 1) return foo().foo;
+\tif ( arg == 2) return foo().foo;
+\tif ( arg == 3) return foo().foo;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class prepost12_obj {
+    field foo: int = ++foo;
+}
+
+component prepost12 {
+    field foo: prepost12_obj = new prepost12_obj();
+}
+
+/* 
+heap {
+    record #0:1:prepost12 {
+        field foo: prepost12_obj = #1:prepost12_obj;
+    }
+    record #1:1:prepost12_obj {
+        field foo: int = int:1;
+    }
+}*/
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:11
+
+component try03 {
+   method try() {
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: null exceptions
+// @Result: NullCheckException @ 7:25
+
+component null06 {
+    field foo: int[] = null;
+    field bar: int = (foo[0] = 0);
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_comp03 {
+    field res_01: 32 = op(-2);
+    field res_02: 32 = op(-1);
+    field res_03: 32 = op(1100);
+    field res_04: 32 = op(0);
+    field res_05: 32 = op(-13);
+    field res_06: 32 = op(1);
+    field res_07: 32 = op(-17);
+    field res_08: 32 = op(-65536);
+    field res_09: 32 = op(255);
+    field res_10: 32 = op(1000000);
+
+    method op(a: 32): 32 {
+\treturn (~(a :: 28)) >> 4;
+    }
+}
+
+/* 
+heap {
+    record #0:10:raw_comp03 {
+        field res_01: raw.32 = raw.32:0x000000;
+        field res_02: raw.32 = raw.32:0x000000;
+        field res_03: raw.32 = raw.32:0xffffbb;
+        field res_04: raw.32 = raw.32:0xffffff;
+        field res_05: raw.32 = raw.32:0x000000;
+        field res_06: raw.32 = raw.32:0xffffff;
+        field res_07: raw.32 = raw.32:0x000001;
+        field res_08: raw.32 = raw.32:0x000fff;
+        field res_09: raw.32 = raw.32:0xfffff0;
+        field res_10: raw.32 = raw.32:0xff0bdb;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > or operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_or04 {
+    field a: 7;
+    field b: 7;
+    field c: 2 = a | b;
+}
+"
+"// @Harness: v2-init
+// @Test: uses of ""this""
+// @Result: PASS
+
+class this01b_obj {
+    field foo: int = 1;
+    field bar: int = this.foo + 3;
+}
+
+component this01b {
+    field foo: this01b_obj = new this01b_obj();
+}
+
+/* 
+heap {
+    record #0:1:this01b {
+        field foo: this01b_obj = #1:this01b_obj;
+    }
+    record #1:2:this01b_obj {
+        field foo: int = int:1;
+        field bar: int = int:4;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: TypeCast operator
+// @Result: PASS
+
+class cast04_a {
+}
+
+class cast04_b extends cast04_a {
+}
+
+component cast04 {
+    field foo: cast04_a = new cast04_b();
+    field bar: cast04_b = foo :: cast04_b;
+}
+
+/* 
+heap {
+    record #0:2:cast04 {
+        field foo: cast04_a = #1:cast04_b;
+        field bar: cast04_b = #1:cast04_b;
+    }
+    record #1:0:cast04_b {
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: variable initialization
+// @Result: VariableNotInitialized @ 7:12
+
+class init07 {
+    
+    method testm(a: int) {
+        local foo: int;
+        testm(foo);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @HeapGC: false
+// @Result: PASS
+
+component map01 {
+    field a: int[] = { 1, 2, 3, 4, 5 };
+    field b: int[] = map(a, hash, 5);
+
+    method hash(a: int): int {
+\treturn a * 11;
+    }
+
+    // iterative version of fold
+    method map(a: int[], f: function(int): int, m: int): int[] {
+        local res = new int[m];
+        local cntr = 0;
+        for ( ; cntr < m; cntr++ ) res[cntr] = f(a[cntr]);
+\treturn res; 
+    }
+}
+
+/* 
+heap {
+    record #0:2:map01 {
+        field a: int[] = #1:int[5];
+        field b: int[] = #2:int[5];
+    }
+    record #1:5:int[5] {
+        field 0: int = int:1;
+        field 1: int = int:2;
+        field 2: int = int:3;
+        field 3: int = int:4;
+        field 4: int = int:5;
+    }
+    record #2:5:int[5] {
+        field 0: int = int:11;
+        field 1: int = int:22;
+        field 2: int = int:33;
+        field 3: int = int:44;
+        field 4: int = int:55;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=14, 5=15, 6=42
+
+component ptex_meth06 {
+
+    method main(arg: int): int {
+    \tif ( arg == 1 ) return m(11, 'c', 'd');
+    \tif ( arg == 2 ) return m(12, false, 'e');
+    \tif ( arg == 3 ) return m(n3(13), 0, false);
+    \tif ( arg == 4 ) return m(n3(14), 0xff, o);
+    \tif ( arg == 5 ) return m(n3(15), n3(o), p);
+        return 42;
+    }
+
+    method m<T, U, V>(x: T, y: U, z: V): T { 
+\tlocal t = n(y);
+\tlocal u = n(z);
+\treturn n(x); 
+    }
+
+    method n<T>(x: T): T { return x; }
+    method n3<T>(x: T): T { return n(n(n(x))); }
+    method o() { }
+    method p(x: int) { }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42, 5=11, 6=21, 7=31, 8=42
+
+class delegate07_a {
+    method getf(): function(): int { return val; }
+    method val(): int { return 11; }
+}
+
+class delegate07_b extends delegate07_a {
+    method val(): int { return 21; }
+}
+
+class delegate07_c extends delegate07_a {
+    method val(): int { return 31; }
+}
+
+component delegate07 {
+    field am: function(): function(): int = new delegate07_a().getf;
+    field bm: function(): function(): int = new delegate07_b().getf;
+    field cm: function(): function(): int = new delegate07_c().getf;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return am()();
+\tif ( arg == 2 ) return bm()();
+\tif ( arg == 3 ) return cm()();
+
+        local m = gm42;
+\tif ( arg == 5 ) m = am;
+\tif ( arg == 6 ) m = bm;
+\tif ( arg == 7 ) m = cm;
+
+\treturn m()();
+    }
+
+    method gm42(): function(): int {
+\treturn m42;
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > auto extension
+// @Result: TypeMismatch @ 7:19
+
+class raw_assn05 {
+    field a: 7;
+    field b: 6 = a;
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 7:40
+
+class type_res18 {
+    field bar: type_res18;
+    method foo(): bool {
+\treturn bar instanceof unknown;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedUnaryOp @ 6:7
+
+class type49 {
+    
+    method testm() {
+        local a = ~false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_lit02 {
+    field a: int = 0;
+    field b: int = -1002;
+    field f: int = 872811;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > xor operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_xor02 {
+    field a: 6;
+    field b: 7;
+    field c: 6 = a^ b;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class fib {
+
+  field MAX: int = 200;
+  field title: string = ""Fibonacci program - VIRGIL\
+"";
+
+  method main() {
+    local x1 = 1, x2 = 2, cntr: int;
+
+    print(title);
+
+    for ( cntr = 0; cntr < MAX; cntr++ ) {
+       local next = x1 + x2;
+       print(""The next Fibonacci number is: ""+next+""\
+"");
+       x1 = x2;
+       x2 = next;
+
+       if ( cntr == MAX-1 ) break;
+       else continue;
+    }
+  }
+}
+"
+"// @Harness: v2-init
+// @Result: PASS
+
+class C<X> {
+  field g: X[];
+}
+
+component init08 {
+  field f: C<int> = new C<int>();
+  constructor() {
+    f.g = new int[1];
+  }
+}
+
+/*
+heap {
+  record #0:1:init08 {
+    field f: C<int> = #1:C<int>;
+  }
+  record #1:1:C<int> {
+    field g: int[] = #2:int[1];
+  }
+  record #2:1:int[1] {
+    field 0: int = int:0;
+  }
+}
+*/
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_infer04 {
+    method first<X, Y>(a: X, b: Y): X {
+        return a;
+    }
+    method second<X, Y>(a: X, b: Y): Y {
+        return b;
+    }
+    method test() {
+\tlocal x: int = first(0, false);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_delegate05 {
+    method makeArray<X>(a: X): X[] {
+\treturn new X[0];\t
+    }
+    method test(): int[] {
+\tlocal x: function(int): int[] = makeArray;
+\treturn take(x, 0);
+    }
+    method take<T>(f: function(T): T[], x: T): T[] {
+\treturn f(x);
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: return from non-void method must have value
+// @Result: VoidReturn @ 21:13
+
+class fib {
+    field MAX: int = 200;
+    field title: string = ""Fibonacci program - VIRGIL\
+"";
+    
+    method main(): int {
+        local x1: int = 1,
+              x2: int = 2;
+        local cntr: int;
+
+        print(title);
+
+        for ( cntr = 0; cntr < MAX; cntr ) {
+            local next: int = x1 + x2;
+
+            print(""The next Fibonacci number is: "" + next + ""\
+"");
+
+            x1 = x2;
+            x2 = next;
+
+            if ( cntr == MAX - 1 ) break;
+            else return;
+        }
+        return 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeCast operation
+// @Result: PASS
+
+class cast03_01 {
+    field bar: cast03_01;
+    field foo: cast03_02 = bar :: cast03_02;
+}
+
+class cast03_02 extends cast03_01 {
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:23
+
+class instof05 {
+   method m() {
+      if ( x <: Type<X, Y> ) ;
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator
+// @Result: PASS
+
+component raw_index11 {
+
+    field b1: 8;
+    field b2: 8;
+    field b3: 8;
+    field b4: 8;
+
+    constructor() {
+    \tlocal f1: 8 = 0xf0;
+    \tlocal f2: 8 = 0xf0;
+    \tlocal f3: 8 = 0xf0;
+    \tlocal f4: 8 = 0xf0;
+
+\tb1 = f1[-1] = 0b1;
+\tb2 = f2[3]  = 0b1;
+\tb3 = f3[7]  = 0b0;
+\tb4 = f4[9]  = 0b1;
+    }
+}
+
+/*
+heap {
+    record #0:4:raw_index11 {
+\tfield b1: 1 = raw.1:0x1;
+\tfield b2: 1 = raw.1:0x1;
+\tfield b3: 1 = raw.1:0x0;
+\tfield b4: 1 = raw.1:0x1;
+    }
+}
+*/
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg09_a {
+    method val(): int { return 1; }
+}
+
+class dg09_b extends dg09_a {
+    method val(): int { return 2; }
+}
+
+component dg09 {
+    field a: function():int = new dg09_a().val;
+    field b: function():int = new dg09_b().val;
+    field c: function():int = bar;
+    field d: function():int;
+    field av: int = val(a);
+    field bv: int = val(b);
+    field cv: int = val(c);
+    field dv: int = val(d);
+
+    method val(f: function(): int): int {
+\tif ( f == a ) return 11;
+\tif ( f == b ) return 21;
+\tif ( f == c ) return 31;
+\tif ( f == d ) return 42;
+\treturn 77;
+    }
+    method bar(): int {
+\treturn 3;
+    }
+
+}
+
+/* 
+heap {
+    record #0:8:dg09 {
+        field a: function():int = [#1:dg09_a,dg09_a:val()];
+        field b: function():int = [#2:dg09_b,dg09_b:val()];
+        field c: function():int = [#0:dg09,dg09:bar()];
+        field d: function():int = #null;
+        field av: int = int:11;
+        field bv: int = int:21;
+        field cv: int = int:31;
+        field dv: int = int:42;
+    }
+    record #1:0:dg09_a {
+    }
+    record #2:0:dg09_b {
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type12<X, Y> {
+    field f: function(type12<X, Y>): Y;
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=7, 2=42, 3=6, 4=1, 5=0
+
+component prepost19 {
+    field ind: int = 0;
+    field foo: int[] = { 6, 42 };
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = foo[ind++]++;
+\tif ( arg == 1 ) return foo[0];
+\tif ( arg == 2 ) return foo[1];
+\tif ( arg == 3 ) return bar;
+\tif ( arg == 4 ) return ind;
+\treturn 0;
+    }
+}
+"
+"// @Harness: tir-to-avr
+// @Test: allocation exceptions in AVR code
+// @Result: AllocationException
+
+program rtex_alloc02 {
+    entrypoint main = rtex_alloc02.main;
+}
+
+component rtex_alloc02 {
+    method main(): int {
+\tlocal x = { 1 };
+\treturn x[0];
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 241
+
+component if01a {
+    
+    // choose(true,  241, 100) => 241
+    // choose(false, 241, 100) => 100
+
+    method main(arg: int): int {
+\treturn choose(true, 241, 100);
+    }
+
+    method choose(c: bool, a: int, b: int): int {
+\treturn c ? a : b;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component for07 {
+    
+    method main(max: int): int {
+\tlocal i: int, cumul = 0;
+        for ( i = 1; i <= max; cumul += i, i++ ) ;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class char_int03 {
+    field a: boolean = (0 == 'a');
+    field b: boolean = ('a' == 0);
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:13
+
+component get04 {
+   method m() {
+      local get: int;
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: CannotUnifyElemTypes @ 6:24
+
+class unify_int_bool02 {
+    
+    method testm() {
+        local a = { 0, false };
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: reading of arrays of raws
+// @Result: 0=42, 1=15, 2=0, 3=99, 4=42
+
+component array_raw09 {
+    field a: 8[] = { 0x2a };
+
+    method main(arg: int): 8 {
+\tif ( arg == 1 ) a[0] = 0xf;
+\tif ( arg == 2 ) a[0] = 0b00;
+\tif ( arg == 3 ) a[0] = 'c';
+\treturn a[0];
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 0
+
+class ch05d {
+    field A: int;
+    field B: int;
+    field R: int;
+
+    method choose(c: bool, a: int, b: int) {
+\tif ( c ) R = A = a;
+\telse R = B = b;
+    }
+}
+
+component if05d {
+    
+    field res_01: ch05d = new ch05d();
+    field res_02: ch05d = new ch05d();
+
+    // res_01.A = 160;
+    // res_01.B = 0;
+    // res_01.R = 160;
+    // res_02.A = 0;
+    // res_02.B = 24;
+    // res_02.R = 24;
+
+    method main(arg: int): int {
+\tres_01.choose(true, 160, 42);
+        res_02.choose(false, 100, 24);
+\treturn res_02.A;
+    }
+
+}
+
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component if06 {
+    
+    field res_01: int = choose(0, -1, 1, 6);
+    field res_02: int = choose(1, -1, 1, 6);
+    field res_03: int = choose(2, -1, 1, 6);
+    field res_04: int = choose(0, 241, 100, 13);
+    field res_05: int = choose(1, 241, 100, 13);
+    field res_06: int = choose(2, 241, 100, 13);
+
+    method choose(cond: int, a: int, b: int, c: int): int {
+\tif ( cond == 0 ) return a;
+        else if ( cond == 1 ) return b;
+        else return c;
+    }
+}
+
+/* 
+heap {
+    record #0:6:if06 {
+        field res_01: int = int:-1;
+        field res_02: int = int:1;
+        field res_03: int = int:6;
+        field res_04: int = int:241;
+        field res_05: int = int:100;
+        field res_06: int = int:13;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedBinOp @ 7:25
+
+class type44 {
+    
+    method testm() {
+        local a = false << 3;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > and operator
+// @Result: PASS
+
+component raw_index05 {
+    field f: 8[] = { 0xf0, 0xf0, 0xf0, 0xf0 };
+
+    constructor() {
+\tf[0][-1] |= 0b1;
+\tf[1][3]  |= 0b1;
+\tf[2][7]  |= 0b1;
+\tf[3][9]  |= 0b1;
+    }
+}
+
+/*
+heap {
+    record #0:1:raw_index05 {
+\tfield f: 8[] = #1:8[4];
+    }
+    record #1:4:8[4] {
+\tfield 0: 8 = raw.8:0xf0;
+\tfield 1: 8 = raw.8:0xf8;
+\tfield 2: 8 = raw.8:0xf0;
+\tfield 3: 8 = raw.8:0xf0;
+    }
+}
+*/
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=7, 2=13, 3=16, 4=4, 5=5, 6=6, 7=42
+
+component array04 {
+    field a: int[][] =  { {7, 13}, {16}, {4, 5, 6} };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a[0][0];
+\tif ( arg == 2 ) return a[0][1];
+\tif ( arg == 3 ) return a[1][0];
+\tif ( arg == 4 ) return a[2][0];
+\tif ( arg == 5 ) return a[2][1];
+\tif ( arg == 6 ) return a[2][2];
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 61
+
+class virtual07e_1 {
+    method val(): int { return 11; }
+}
+
+class virtual07e_2 extends virtual07e_1 {
+    method val(): int { return 21; }
+}
+
+class virtual07e_3 extends virtual07e_1 {
+    method val(): int { return 31; }
+}
+
+class virtual07e_4 {
+    method val(): int { return 51; }
+}
+
+class virtual07e_5 extends virtual07e_4 {
+    method val(): int { return 61; }
+}
+
+component virtual07e {
+    field a: virtual07e_1 = new virtual07e_1();
+    field b: virtual07e_1 = new virtual07e_2();
+    field c: virtual07e_1 = new virtual07e_3();
+    field d: virtual07e_4 = new virtual07e_4();
+    field e: virtual07e_4 = new virtual07e_5();
+
+    method main(arg: int): int {
+\treturn e.val();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class type19<X, Y> {
+    field f: type19<char, bool>;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking of operators
+// @Result: PASS
+
+class type_func12 {
+  method m() {
+     local a = { m, null };
+     local b = { null, m };
+  }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; ternary expressions
+// @Result: PASS
+
+class unify_class03_a {
+}
+
+class unify_class03_b extends unify_class03_a {
+    
+    method testm(a: unify_class03_a, b: unify_class03_b) {
+        local x: unify_class03_a = false ? a : b;
+        local y: unify_class03_a = false ? b : a;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: TypeMismatch @ 6:16
+
+class int_sub01 {
+    
+    method testm() {
+        local a: int = 2 - null;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: logical operators
+// @Result: 0=0, 1=1, 2=0, 3=0, 4=0, 5=0
+
+component logical01 {
+
+    method op(a: bool, b: bool): bool {
+\treturn a and b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return op(true, true);
+\tif ( arg == 2 ) return op(false, false);
+\tif ( arg == 3 ) return op(true, false);
+\tif ( arg == 4 ) return op(false, true);
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg07_a {
+    method getf(): function(): int { return val; }
+    method val(): int { return 1; }
+}
+
+class dg07_b extends dg07_a {
+    method val(): int { return 2; }
+}
+
+class dg07_c extends dg07_a {
+    method val(): int { return 3; }
+}
+
+component dg07 {
+    field a: function():int = new dg07_a().getf();
+    field b: function():int = new dg07_b().getf();
+    field c: function():int = new dg07_c().getf();
+    field av: int = a();
+    field bv: int = b();
+    field cv: int = c();
+}
+
+/* 
+heap {
+    record #0:6:dg07 {
+        field a: function():int = [#1:dg07_a,dg07_a:val()];
+        field b: function():int = [#2:dg07_b,dg07_b:val()];
+        field c: function():int = [#3:dg07_c,dg07_c:val()];
+        field av: int = int:1;
+        field bv: int = int:2;
+        field cv: int = int:3;
+    }
+    record #1:0:dg07_a {
+    }
+    record #2:0:dg07_b {
+    }
+    record #3:0:dg07_c {
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: UnresolvedIdentifier @ 6:15
+
+class local_res08 {
+    
+    method testm() {
+        for ( ; ; foo ) ;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 13
+
+component if06c {
+    
+//    choose(0, 241, 100, 13) = 241 
+//    choose(1, 241, 100, 13) = 100
+//    choose(2, 241, 100, 13) = 13
+
+    method main(arg: int): int {
+\treturn choose(2, 241, 100, 13);
+    }
+
+
+    method choose(cond: int, a: int, b: int, c: int): int {
+\tif ( cond == 0 ) return a;
+        else if ( cond == 1 ) return b;
+        else return c;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_array01 {
+    method makeArray<X>(a: X): X[] {
+\treturn new X[0];\t
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type13 {
+    field f: function(type): function(type);
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=17, 3=42
+
+component field08 {
+    field foo: function(int): int = bar;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo(13);
+\tif ( arg == 2 ) return foo(17);
+\treturn 42;
+    }
+
+    method bar(i: int): int { return i; }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class cmpassn14_obj {
+    field foo: int = 1;
+    field bar: int = inc();
+    method inc(): int {
+\tlocal i = foo;
+\treturn i -= 8;
+    }
+}
+
+component cmpassn14 {
+    field foo: cmpassn14_obj = new cmpassn14_obj();
+}
+
+/* 
+heap {
+    record #0:1:cmpassn14 {
+        field foo: cmpassn14_obj = #1:cmpassn14_obj;
+    }
+    record #1:2:cmpassn14_obj {
+        field foo: int = int:1;
+\tfield bar: int = int:-7;
+    }
+}*/
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component while04 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( true ) {
+\t    cumul += i;
+\t    if ( i == max ) return cumul;
+\t    i++;
+\t}
+\treturn cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:while04 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (shortcutting of conditionals)
+// @Result: VariableNotInitialized @ 9:12
+
+class dowhile_init03 {
+    
+    method testm(p: bool) {
+        local foo: bool;
+        do {
+        }
+        while ( p and (foo = p) );
+        testm(foo);
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg15_a {
+    method val(): int { return 1; }
+}
+
+class dg15_b extends dg15_a {
+    method val(): int { return 2; }
+}
+
+component dg15 {
+    field b: bool[];
+
+    constructor() {
+        b = new bool[9];
+        local ao = new dg15_a();
+        local bo = new dg15_b();
+
+\tlocal af = ao.val;
+\tlocal bf = bo.val;
+\tlocal cf = bar;
+
+\tlocal f = { ao.val, bo.val, bar, bo.val, ao.val, null, 
+\t            new dg15_a().val, new dg15_b().val, bar };
+
+\tb[0] = compare(af, f[0]);
+\tb[1] = compare(bf, f[1]);
+\tb[2] = compare(cf, f[2]);
+\tb[3] = compare(af, f[3]);
+\tb[4] = compare(bf, f[4]);
+\tb[5] = compare(cf, f[5]);
+\tb[6] = compare(af, f[6]);
+\tb[7] = compare(bf, f[7]);
+\tb[8] = compare(cf, f[8]);
+    }
+
+    method compare(f: function(): int, g: function(): int): bool {
+\treturn f == g;
+    }
+
+    method bar(): int {
+\treturn 3;
+    }
+}
+
+/* 
+heap {
+    record #0:1:dg15 {
+\tfield b: bool[] = #1:bool[9];
+    }
+    record #1:9:bool[9] {
+\tfield 0: bool = bool:true;
+\tfield 1: bool = bool:true;
+\tfield 2: bool = bool:true;
+\tfield 3: bool = bool:false;
+\tfield 4: bool = bool:false;
+\tfield 5: bool = bool:false;
+\tfield 6: bool = bool:false;
+\tfield 7: bool = bool:false;
+\tfield 8: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42
+
+class Pair<X, Y> {
+    field a: X;
+    field b: Y;
+
+    constructor(x: X, y: Y) {
+        a = x;
+        b = y;
+    }
+}
+
+component ptex_pair07 {
+    field a: int[] = { 21, 31 };
+    field b: Pair<int, int[]> = new Pair<int, int[]>(11, a);
+
+    method main(arg: int): int {
+        if ( arg == 1 ) return b.a;
+        if ( arg == 2 ) return b.b[0];
+        if ( arg == 3 ) return b.b[1];
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class new14<X> {
+   method m(): new14<X> {
+      return new new14<X>();
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_comp04 {
+    field res_01: 32 = op(-2);
+    field res_02: 32 = op(-1);
+    field res_03: 32 = op(1100);
+    field res_04: 32 = op(0);
+    field res_05: 32 = op(-13);
+    field res_06: 32 = op(1);
+    field res_07: 32 = op(-17);
+    field res_08: 32 = op(-65536);
+    field res_09: 32 = op(255);
+    field res_10: 32 = op(1000000);
+
+    method op(a: 32): 32 {
+\treturn (~(a & 0x0fffffff)) >> 4;
+    }
+}
+
+/* 
+heap {
+    record #0:10:raw_comp04 {
+        field res_01: raw.32 = raw.32:0xf000000;
+        field res_02: raw.32 = raw.32:0xf000000;
+        field res_03: raw.32 = raw.32:0xfffffbb;
+        field res_04: raw.32 = raw.32:0xfffffff;
+        field res_05: raw.32 = raw.32:0xf000000;
+        field res_06: raw.32 = raw.32:0xfffffff;
+        field res_07: raw.32 = raw.32:0xf000001;
+        field res_08: raw.32 = raw.32:0xf000fff;
+        field res_09: raw.32 = raw.32:0xffffff0;
+        field res_10: raw.32 = raw.32:0xfff0bdb;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: array rtex_index exceptions
+// @Result: 0=42, 1=BoundsCheckException, 2=BoundsCheckException, 3=BoundsCheckException, 4=BoundsCheckException, 5=42
+
+component rtex_index01 {
+    field foo: int[] = new int[0];
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo[-1];
+\tif ( arg == 2 ) return foo[0];
+\tif ( arg == 3 ) return foo[1];
+\tif ( arg == 4 ) return foo[2];
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr2 {
+  field foo: type = foo.bar;
+}
+"
+"// @Harness: v2-exec
+// @Test: initialization interpreter > raw types > and operator
+// @Result: 0=2, 1=1, 2=7, 3=11, 4=19, 5=35, 6=67, 7=131
+
+component raw_index06 {
+    field f: 8[] = { 0x03 };
+
+    method main(arg: int): 8 {
+\tf[0][arg] ^= 0b1;
+\treturn f[0];
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 6:5
+
+class lvalue4 {
+    
+    method testm() {
+        2 = 1;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 8:5
+
+class lvalue19 {
+    
+    method testm(): 32 {
+        testm()[0] = 0b1;
+\treturn 0x00;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class subtype03_a<X> extends subtype03_b {
+  field f: subtype03_b = new subtype03_a<X>();
+}
+class subtype03_b {
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 7:20
+
+component type_res22 {
+    field f: int;
+    constructor(u: unknown) {
+\tf = u;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg03_a {
+    method getf(): dg03_a { return this; }
+}
+
+class dg03_b extends dg03_a {
+}
+
+class dg03_c extends dg03_a {
+}
+
+component dg03 {
+    field a: function():dg03_a = new dg03_a().getf;
+    field b: function():dg03_a = new dg03_b().getf;
+    field c: function():dg03_a = new dg03_c().getf;
+    field av: dg03_a = a();
+    field bv: dg03_a = b();
+    field cv: dg03_a = c();
+}
+
+/* 
+heap {
+    record #0:6:dg03 {
+        field a: function():dg03_a = [#1:dg03_a,dg03_a:getf()];
+        field b: function():dg03_a = [#2:dg03_b,dg03_a:getf()];
+        field c: function():dg03_a = [#3:dg03_c,dg03_a:getf()];
+        field av: dg03_a = #1:dg03_a;
+        field bv: dg03_a = #2:dg03_b;
+        field cv: dg03_a = #3:dg03_c;
+    }
+    record #1:0:dg03_a {
+    }
+    record #2:0:dg03_b {
+    }
+    record #3:0:dg03_c {
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: TypeMismatch @ 7:9
+
+class assign19<X, Y> {
+   field f: assign19<X, Y>;
+   method m(x: assign19<Y, X>) {
+      f = x;
+   }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component raw_flip01 {
+    field res_01: 16 = flip(0x0ffe);
+    field res_02: 16 = flip(0x0002);
+    field res_03: 16 = flip(0x0001);
+    field res_04: 16 = flip(0x8000);
+    field res_05: 16 = flip(0xf007);
+    field res_06: 16 = flip(0x8877);
+    field res_07: 16 = flip(0xaa01);
+
+    method flip(a: 16): 16 {
+\treturn (a << 8) | ((a >> 8) & 0xff);
+    }
+}
+
+/* 
+heap {
+    record #0:6:raw_flip01 {
+        field res_01: raw.16 = raw.16:0xfe0f;
+        field res_02: raw.16 = raw.16:0x0200;
+        field res_03: raw.16 = raw.16:0x0100;
+        field res_04: raw.16 = raw.16:0x0080;
+        field res_05: raw.16 = raw.16:0x07f0;
+        field res_06: raw.16 = raw.16:0x7788;
+        field res_07: raw.16 = raw.16:0x01aa;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: null exceptions
+// @Result: NullCheckException @ 11:24
+
+class null07_obj {
+    field baz: int;
+}
+
+component null07 {
+    field foo: null07_obj;
+    field bar: int = (foo.baz = 0);
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 31
+
+class virtual08c_1 {
+    method val(): int { return 11; }
+}
+
+class virtual08c_2 extends virtual08c_1 {
+    method val(): int { return 21; }
+}
+
+class virtual08c_3 extends virtual08c_1 {
+    method val(): int { return 31; }
+}
+
+component virtual08c {
+    field a: virtual08c_1 = new virtual08c_1();
+    field b: virtual08c_1 = new virtual08c_2();
+    field c: virtual08c_1 = new virtual08c_3();
+
+    method main(arg: int): int {
+\tinvoke(a);
+\tinvoke(b);
+\tinvoke(c);
+\treturn invoke(c);
+    }
+
+    method invoke(o: virtual08c_1): int {
+\treturn o.val();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeMismatch @ 5:31
+
+class subtype01_a<X> extends subtype01_b<X> {
+  field f: subtype01_a<int> = new subtype01_b<int>();
+}
+class subtype01_b<X> {
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array19 {
+    field a_01: int[] =  {1, 2, 3};
+    field len: int =  a_01.length;
+}
+
+/* 
+heap {
+    record #0:2:array19 {
+        field a_01: int[] = #1:int[3];
+        field len: int = int:3;
+    }
+    record #1:3:int[3] {
+        field 0:int = int:1;
+        field 1:int = int:2;
+        field 2:int = int:3;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=11, 3=11, 4=42
+
+class private06_a {
+    method getf(): function(): int { return val; }
+    private method val(): int { return 11; }
+}
+
+class private06_b extends private06_a {
+    private method val(): bool { return true; }
+}
+
+class private06_c extends private06_a {
+    private method val(): char { return '3'; }
+}
+
+component private06 {
+    field a: function():int = new private06_a().getf();
+    field b: function():int = new private06_b().getf();
+    field c: function():int = new private06_c().getf();
+    field av: int = a();
+    field bv: int = b();
+    field cv: int = c();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a();
+\tif ( arg == 2 ) return b();
+\tif ( arg == 3 ) return c();
+\treturn 42;
+    }
+}
+"
+"program rma_down01 {
+    entrypoint main = Main.entry;
+}
+
+component Main {
+    field f: A = new A();
+    field g: B = new B();
+
+    method entry() {
+\twhile ( true ) g = move(g);
+    }
+    method move(b: B): B {
+\tb.other = b;
+\treturn b;
+    }
+}
+
+class A {
+    field other: A;
+}
+
+class B extends A {
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class expr8 {
+  field foo: type = foo()();
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 8:32
+
+component for8 {
+    
+    method count(max: int): int {
+\tlocal i: int;
+        for ( i = 1; i <= max; break ) ;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=42
+
+class MX {
+   method id<X, Y>(x: X, y: Y): X {
+      return x;
+   }
+}
+
+component ptex_vp02 {
+   field m1: MX = new MX();
+   field m2: int = m1.id(11, 8);
+   field m3: int = m1.id(13, 9);
+   
+   method main(arg: int): int {
+      if ( arg == 1 ) return m2;
+      if ( arg == 2 ) return m1.id(12, 8);
+      if ( arg == 3 ) return m1.id(m3, 9);
+      return 42;
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: Virgil constructors
+// @Result: ArgumentCountMismatchInNew @ 13:34
+
+class constructor06 {
+
+    field f: int;
+
+    constructor(a: int) {
+        f = a;
+    }
+
+    method testm(): constructor06 {
+        return new constructor06();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: array index exceptions
+// @Result: BoundsCheckException @ 7:25
+
+component index03 {
+    field foo: int[] = new int[0];
+    field bar: int = foo[-1];
+}
+"
+"// @Harness: v2-seman
+// @Test: return from non-void method must have value
+// @Result: VoidReturn @ 6:6
+
+class return1 {
+    
+    method testm(): int {
+        return;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class raw_raw01 {
+    field a: boolean = (0x00 == 0x0);
+    field b: boolean = (0x0000 == 0x00);
+    field c: boolean = (0x000000 == 0x00000);
+    field d: boolean = (0x00000000 == 0x0000000);
+    field e: boolean = (0x0000000000 == 0x0000000);
+    field f: boolean = (0x000000000000 == 0x0000000);
+    field g: boolean = (0x0000000000000000 == 0x0000000);
+}
+"
+"// @Harness: v2-seman
+// @Test: array initializers test
+// @Result: PASS 
+
+class type66 {
+    
+    field a: int[] = {};
+
+    method testm() {
+        local a: int[] = { };
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+component comp2 {
+  field f: type;
+  field f2: type, f3: type;
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component order01 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    field res_01: int = op(1, 2);
+
+    method op(a: int, b: int): int {
+\treturn first(a) + second(b);
+    }
+
+    method first(a: int): int {
+        order[pos] = 1;
+        pos++;
+        return a;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+}
+
+/* 
+heap {
+    record #0:10:order01 {
+        field order: int[] = #1:int[2];
+        field pos: int = int:2;
+        field res_01: int = int:3;
+    }
+    record #1:2:int[2] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 8:8 
+
+class unreach9 {
+    
+    method testm() {
+        while ( true ) {
+            break;
+            {
+                local foo: int = 0;
+            }
+        }
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=1, 11=0
+
+component arith08 {
+    field res_01: int = op(1, -2);
+    field res_02: int = op(2, -1);
+    field res_03: int = op(-1, -1);
+    field res_04: int = op(-1, 0);
+    field res_05: int = op(-200, -13);
+    field res_06: int = op(65535, -1);
+    field res_07: int = op(0, -17);
+    field res_08: int = op(255, -12);
+    field res_09: int = op(255, 255);
+    field res_10: int = op(1000, -48576);
+
+    method op(a: int, b: int): int {
+\treturn a * b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return (1 * -2) == res_01;
+\tif ( arg == 2 )  return (2 * -1)         == res_02;
+\tif ( arg == 3 )  return (-1 * -1)        == res_03;
+\tif ( arg == 4 )  return (-1 * 0)         == res_04;
+\tif ( arg == 5 )  return (-200 * -13)     == res_05;
+\tif ( arg == 6 )  return (65535 * -1)     == res_06;
+\tif ( arg == 7 )  return (0 * -17)        == res_07;
+\tif ( arg == 8 )  return (255 * -12)      == res_08;
+\tif ( arg == 9 )  return (255 * 255)      == res_09;
+\tif ( arg == 10 ) return (1000 * -48576)  == res_10;
+\treturn false;
+    }
+
+}
+"
+"// @Harness: v2-init
+// @Test: promotions of char->int
+// @Result: PASS
+
+component int_char01 {
+    field a: int = '0';
+    field b: int = '\
+';
+    field c: int = '\\367';
+}
+
+/* 
+heap {
+    record #0:3:int_char01 {
+        field a: int = int:48;
+        field b: int = int:10;
+        field c: int = int:247;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; invocation of method on non-object
+// @Result: UnresolvedMember @ 10:10
+
+class type04 {
+    
+    method foo(): int {
+        return 0;
+    }
+    
+    method testm() {
+        foo().bar();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: UnresolvedMember @ 10:22
+
+class field_res02_a {
+    field testf: int;
+}
+class field_res02_b {
+    
+    method testm(arg: field_res02_a) {
+        local result: int = arg.unres;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_array02 {
+    method makeArray<X>(a: X, b: X): X[] {
+\treturn new X[0];\t
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: logical operators
+// @Result: 0=0, 1=5, 2=5, 3=7, 4=6, 5=0
+
+class orer {
+    field a: bool; // true if A() evaluated
+    field b: bool; // true if B() evaluated
+    field R: bool;
+
+    method OR(v1: bool, v2: bool) {
+\tR = A(v1) or B(v2);
+    }
+
+    method A(v: bool): bool {
+\ta = true;
+\treturn v;
+    }
+
+    method B(v: bool): bool {
+\tb = true;
+\treturn v;
+    }
+}
+
+component logical07 {
+    field a: orer = new orer();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) a.OR(true, false);
+\tif ( arg == 2 ) a.OR(true, true);
+\tif ( arg == 3 ) a.OR(false, true);
+\tif ( arg == 4 ) a.OR(false, false);
+\treturn add();
+    }
+
+    method add(): int {
+\tlocal res = 0;
+\tif ( a.a ) res += 4;
+\tif ( a.b ) res += 2;
+\tif ( a.R ) res += 1;
+\treturn res;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; int type
+// @Result: PASS
+
+class int_int01 {
+    field a: int = 0 :: int;
+    field b: int = 294 :: int;
+    field c: int = -7278 :: int;
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 4:7
+
+component get {
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: UnresolvedOperator @ 7:23
+
+class inc05 {
+    method testm(a: inc05) {
+        local foo = --a;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 0=7, 1=1, 2=3, 3=5, 4=7
+
+class A { }
+class B extends A { }
+class C extends A { }
+class D { }
+class E extends D { }
+
+component cast02 {
+
+    field a: A = new A();
+    field b: B = new B();
+    field c: C = new C();
+
+    method main(arg: int): int {
+\tlocal x: A = getObj(arg);
+\tlocal r = 0;
+\tif ( x <: A or x == null ) { local y = x :: A; r += 1; }
+\tif ( x <: B or x == null ) { local y = x :: B; r += 2; }
+\tif ( x <: C or x == null ) { local y = x :: C; r += 4; }
+\treturn r;
+    }
+
+    method getObj(arg: int): A {
+\tif ( arg == 1 ) return a;
+\tif ( arg == 2 ) return b;
+\tif ( arg == 3 ) return c;
+\treturn null;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=0, 2=0, 3=1, 4=1, 5=0
+
+class A<X> { } 
+class B<X> extends A<X> { }
+
+component ptex_instof04 {
+
+   field a: A<int> = new A<int>();
+   field b: A<int> = new B<int>();
+   field c: A<int> = new B<int>();
+
+   method m(x: A<int>): bool {
+      return x <: (B<int>);
+   }
+
+   method main(arg: int): bool {
+       if ( arg == 1 ) return m(null);
+       if ( arg == 2 ) return m(a);
+       if ( arg == 3 ) return m(b);
+       if ( arg == 4 ) return m(c);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type05<X> {
+    field f: type05<X>;
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 8:15
+
+component for9 {
+    
+    method count(max: int): int {
+\tlocal i = 0;
+        for ( break; i <= max; i++ ) ;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=0
+
+component raw_shr03 {
+    field res_01: 8 = op(0x0f,  1);
+    field res_02: 8 = op(0x02,  2);
+    field res_03: 8 = op(0x01,  7);
+    field res_04: 8 = op(0x70,  5);
+    field res_05: 8 = op(0xf0,  6);
+    field res_06: 8 = op(0xff,  2);
+    field res_07: 8 = op(0x80, 11);
+    field res_08: 8 = op(0xff,  5);
+    field res_09: 8 = op(0xaa,  0);
+
+    method op(a: 8, b: int): 8 {
+\treturn a >> b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(0x0f,  1) == res_01;
+\tif ( arg == 2 )  return op(0x02,  2) == res_02;
+\tif ( arg == 3 )  return op(0x01,  7) == res_03;
+\tif ( arg == 4 )  return op(0x70,  5) == res_04;
+\tif ( arg == 5 )  return op(0xf0,  6) == res_05;
+\tif ( arg == 6 )  return op(0xff,  2) == res_06;
+\tif ( arg == 7 )  return op(0x80, 11) == res_07;
+\tif ( arg == 8 )  return op(0xff,  5) == res_08;
+\tif ( arg == 9 )  return op(0xaa,  0) == res_09;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class scope09_a<X> extends scope09_b<X> {
+}
+
+class scope09_b<X> {
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg05_a {
+    method foo(): int { return 1; }
+    method bar(): int { return 2; }
+}
+
+component dg05 {
+    field a: function():int = new dg05_a().foo;
+    field b: function():int = new dg05_a().bar;
+    field av: int = a();
+    field bv: int = b();
+}
+
+/* 
+heap {
+    record #0:4:dg05 {
+        field a: function():int = [#1:dg05_a,dg05_a:foo()];
+        field b: function():int = [#2:dg05_a,dg05_a:bar()];
+        field av: int = int:1;
+        field bv: int = int:2;
+    }
+    record #1:0:dg05_a {
+    }
+    record #2:0:dg05_a {
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: initialization interpreter > raw types > and operator
+// @Result: 0=3, 1=3, 2=7, 3=11, 4=19, 5=35, 6=67, 7=131
+
+class raw_index07_a {
+    field foo: 8 = 0x03;
+}
+
+component raw_index07 {
+    field f: raw_index07_a = new raw_index07_a();
+
+    method main(arg: int): 8 {
+\tf.foo[arg] |= 0b1;
+\treturn f.foo;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 31
+
+class virtual06c_1 {
+    method val() { virtual06c.R = 11; }
+}
+
+class virtual06c_2 extends virtual06c_1 {
+}
+
+class virtual06c_3 extends virtual06c_2 {
+    method val() { virtual06c.R = 31; }
+}
+
+component virtual06c {
+    field a: virtual06c_1 = new virtual06c_1();
+    field b: virtual06c_1 = new virtual06c_2();
+    field c: virtual06c_1 = new virtual06c_3();
+
+    field R: int;
+
+    method main(arg: int): int {
+\tc.val();
+\treturn R;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > or operator
+// @Result: PASS
+
+class raw_or01 {
+    field a: 1;
+    field b: 2;
+    field c: 2 = a | b;
+    field d: 2 = b | a;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type17 {
+    field f: function((type));
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=42, 1=11, 2=12, 3=13, 4=14, 5=42
+
+component ptex_meth07 {
+
+    method main(arg: int): int {
+        local f: function(int): int = id;
+    \tif ( arg == 1 ) return apply(11, f);
+    \tif ( arg == 2 ) return apply(12, f);
+    \tif ( arg == 3 ) return apply(13, f);
+    \tif ( arg == 4 ) return apply(14, f);
+        return 42;
+    }
+
+    method apply<T>(x: T, f: function(T): T): T { 
+\treturn f(x);
+    }
+
+    method id<T>(x: T): T { return x; }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_delegate04 {
+    method makeArray<X>(a: X): X[] {
+\treturn new X[0];\t
+    }
+    method test(): int[] {
+\tlocal x: function(int): int[] = makeArray;
+\treturn x(0);
+    }
+    method take<T>(f: function(T): T[], x: T): T[] {
+\treturn f(x);
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class switch2 {
+  method m() {
+     local a: int = 0, b: int, c: int;
+
+     switch ( a ) {
+       default b = 1;
+     }
+
+     switch ( a ) {
+       case(0) b = 1;
+     }
+
+     switch ( a ) {
+       case(0) b = 1;
+       case(1) c = 1;
+     }
+
+     switch ( a ) {
+       case(0, 1) b = 1;
+     }
+
+     switch ( a ) {
+       case(0) b = 1;
+       case(1) c = 1;
+       default c = 0;
+     }
+
+     switch ( a ) {
+       case(0+0) b = 1;
+     }
+  }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > auto extension
+// @Result: TypeMismatch @ 7:19
+
+class raw_assn09 {
+    field a: 21;
+    field b: 20 = a;
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=13, 1=0, 2=11, 3=13
+
+component default01a {
+    field foo: int;
+    field bar: int = foo + 11;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 13;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: promotion integer to 32 bit raw type
+// @Result: PASS
+
+component raw_int02 {
+    field a: 32 = 0       | 0;
+    field b: 32 = 1       | 0;
+    field c: 32 = 7       | 0;
+    field d: 32 = 10      | 0;
+    field e: 32 = 15      | 0;
+    field f: 32 = 16      | 0;
+    field g: 32 = 58      | 0;
+    field h: 32 = 255     | 0;
+    field i: 32 = 32767   | 0;
+    field j: 32 = 65536   | 0;
+    field k: 32 = 1048576 | 0;
+    field l: 32 = -1      | 0;
+    field m: 32 = -65535  | 0;
+    field n: 32 = -11     | 0;
+}
+
+/* 
+heap {
+    record #0:14:raw_int02 {
+        field a: 32 = raw.32:0x0;
+        field b: 32 = raw.32:0x1;
+        field c: 32 = raw.32:0x7;
+        field d: 32 = raw.32:0xa;
+        field e: 32 = raw.32:0xf;
+        field f: 32 = raw.32:0x10;
+        field g: 32 = raw.32:0x3a;
+        field h: 32 = raw.32:0xff;
+        field i: 32 = raw.32:0x7fff;
+        field j: 32 = raw.32:0x10000;
+        field k: 32 = raw.32:0x100000;
+        field l: 32 = raw.32:0xffffffff;
+        field m: 32 = raw.32:0xffff0001;
+        field n: 32 = raw.32:0xfffffff5;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=0, 2=0, 3=42
+
+class default06b_obj {
+    field foo: char;
+    field bar: char = foo;
+}
+
+component default06b {
+    field baz: default06b_obj = new default06b_obj();
+
+    method main(arg: int): char {
+\tif ( arg == 1 ) return baz.foo;
+\tif ( arg == 2 ) return baz.bar;
+\treturn '*';
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 9:9
+
+class unreach15 {
+    
+    method testm() {
+        switch ( 0 ) {
+            case ( 0 ) {
+                return;
+                testm();
+            }
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: Virgil constructors
+// @Result: PASS
+
+class constructor02 {
+    field f: int;
+
+    constructor(a: int) {
+        f = a;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=6, 2=6, 3=0
+
+component prepost06 {
+    method main(arg: int): int {
+\tlocal foo = 5;
+\tlocal bar = ++foo;
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component while02 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( i <= max ) cumul += i++;
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class method01 {
+          method m1(): type<X>;
+
+  private method m2(): type<X>;
+
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class new3 {
+  field foo: type = new foo[][0];
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: PASS
+
+class char_char01 {
+    field a: char;
+    field b: char = a :: char;
+    field c: char = 'a' :: char;
+}
+"
+"// @Harness: v2-init
+// @Test: character comparison operators
+// @Result: PASS
+
+component comp10 {
+    field res_01: bool = op('a', 'b');
+    field res_02: bool = op('b', 'a');
+    field res_03: bool = op('\
+', '1');
+    field res_04: bool = op('\\377', '0');
+    field res_05: bool = op('\
+', '\
+');
+    field res_06: bool = op('\\377', '\\377');
+    field res_07: bool = op('a', 'A');
+    field res_08: bool = op('A', 'Z');
+    field res_09: bool = op('$', 'z');
+    field res_10: bool = op('z', '~');
+
+    method op(a: char, b: char): bool {
+\treturn a <= b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:comp10 {
+        field res_01: bool = bool:true;
+        field res_02: bool = bool:false;
+        field res_03: bool = bool:true;
+        field res_04: bool = bool:false;
+        field res_05: bool = bool:true;
+        field res_06: bool = bool:true;
+        field res_07: bool = bool:false;
+        field res_08: bool = bool:true;
+        field res_09: bool = bool:true;
+        field res_10: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 0=42, 1=21, 2=32, 3=42
+
+class instof01_obj {
+}
+
+component instof01 {
+    field foo: instof01_obj;
+    
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo instanceof instof01_obj ? 11 : 21;
+\tif ( arg == 2 ) return foo instanceof instof01_obj ? 31 : 32;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 100
+
+component if06b {
+    
+//    choose(0, 241, 100, 13) = 241 
+//    choose(1, 241, 100, 13) = 100
+//    choose(2, 241, 100, 13) = 13
+
+    method main(arg: int): int {
+\treturn choose(1, 241, 100, 13);
+    }
+
+
+    method choose(cond: int, a: int, b: int, c: int): int {
+\tif ( cond == 0 ) return a;
+        else if ( cond == 1 ) return b;
+        else return c;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: function () -> int
+// @Result: PASS
+
+class type_func06 {
+    method testm(b: function(int): int): int { 
+\treturn b(0); 
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (ternary expressions)
+// @Result: PASS
+
+class ternay_init02 {
+    
+    method testm(b: bool): int {
+        local foo: int;
+        local r: int = b ? (foo = 0):(foo = 1);
+        return foo;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 7:8 
+
+class unreach6 {
+    
+    method testm() {
+        return;
+        {
+            local foo: int = 0;
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: switch statements should have non-overlapping values
+// @Result: DuplicateCase @ 7:15
+
+class switch07 {
+    
+    method testm(a: int) {
+        switch ( a ) {
+            case ( 2, 1 + 1 ) ;
+            case ( 0 ) ;
+        }
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 1=1, 2=3, 3=6, 10=55, 13=91
+
+component dowhile08 {
+    
+    method main(max: int): int {
+\tlocal i = 1, cumul = 0, loop = 1;
+        do {
+            for ( i = 1; ; cumul += i, i++ ) {
+\t        if ( i > max ) break;
+\t        else continue;
+\t    }
+\t} while (++loop < 2);
+        return cumul;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 6:11
+
+class lvalue7 {
+    
+    method testm() {
+        for ( testm() = 2; ; ) ;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global identifier resolution
+// @Result: UnresolvedIdentifier @ 6:13
+
+class local_res07 {
+    
+    method testm() {
+        for ( ; foo < 0; ) ;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: ExpectedObjectType @ 4:20
+
+class inh01 extends int {
+    field foo : int;
+}
+"
+"// @Harness: v2-exec
+// @Test: order of evaluation
+// @Result: 0=0, 1=1, 2=2, 3=7, 4=7, 5=0
+
+component order11 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    field data: int[] = { 7 };
+
+    method first(): int[] {
+        order[pos] = 1;
+        pos++;
+        return data;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method main(arg: int): int {
+        local result = first()[second(0)];
+\tif ( arg == 1 ) return order[0];
+\tif ( arg == 2 ) return order[1];
+\tif ( arg == 3 ) return result;
+\tif ( arg == 4 ) return data[0];
+\treturn 0;
+    }
+
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type07<X> {
+    field f: type07<X>[];
+}
+"
+"// @Harness: v2-seman
+// @Test: Lvalue correctness
+// @Result: NotAnLvalue @ 6:17
+
+class lvalue16 {
+    field bar: int = 0;
+    field foo: int = bar + bar = 2;
+}
+"
+"// @Harness: v2-init
+// @Test: integers comparison operators
+// @Result: PASS
+
+component comp05 {
+    field res_01: bool = op(1, 2);
+    field res_02: bool = op(2, 1);
+    field res_03: bool = op(-1, 1);
+    field res_04: bool = op(-1, 0);
+    field res_05: bool = op(-200, -200);
+    field res_06: bool = op(65535, 65535);
+    field res_07: bool = op(14, 13);
+    field res_08: bool = op(13, 14);
+    field res_09: bool = op(-1255, -255);
+    field res_10: bool = op(1000000, 48576);
+
+    method op(a: int, b: int): bool {
+\treturn a == b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:comp05 {
+        field res_01: bool = bool:false;
+        field res_02: bool = bool:false;
+        field res_03: bool = bool:false;
+        field res_04: bool = bool:false;
+        field res_05: bool = bool:true;
+        field res_06: bool = bool:true;
+        field res_07: bool = bool:false;
+        field res_08: bool = bool:false;
+        field res_09: bool = bool:false;
+        field res_10: bool = bool:false;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: compile-time constants for primitive types
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=0
+
+component const05 {
+    field a: int = 1;
+    field b: int = -1;
+    field c: int = 0b0101 :: int;
+    field d: int = 0xff :: int;
+    field e: int = 0777 :: int;
+    field f: int = 65536;
+    field g: int = -200000;
+    field h: int = -2147483648;
+
+    method main(arg: int): bool {
+\tif ( arg == 1 ) return a == 1;
+\tif ( arg == 2 ) return b == -1;
+\tif ( arg == 3 ) return c == 5;
+\tif ( arg == 4 ) return d == 255;
+\tif ( arg == 5 ) return e == 511;
+\tif ( arg == 6 ) return f == 65536;
+\tif ( arg == 7 ) return g == -200000;
+\tif ( arg == 8 ) return h == -2147483648;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: array initializers test
+// @Result: PASS 
+
+class type56 {
+    
+    method testm() {
+        local a: int[] = { 0, 1, 2 };
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types > exact bit sizes > hexadecimal constants
+// @Result: InvalidLiteral @ 6:19
+
+class raw_oct02 {
+    field n: 64 = 01111111111111111111111;
+}
+"
+"// @Harness: tir-to-avr
+// @Test: allocation exceptions in AVR code
+// @Result: AllocationException
+
+program rtex_alloc01 {
+    entrypoint main = rtex_alloc01.main;
+}
+
+component rtex_alloc01 {
+    method main(): int {
+\treturn (new int[0])[0];
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class this04_a {
+    field th: this04_a;
+    method val(a: int): int { th = this; return a+1; }
+}
+
+class this04_b extends this04_a {
+    method foo(a: int): int { th = this; return this.val(a)+2; }
+}
+
+class this04_c extends this04_a {
+    method foo(a: int): int { th = this; return this.val(a)+3; }
+}
+
+component this04 {
+    field a: this04_a = new this04_a();
+    field b: this04_b = new this04_b();
+    field c: this04_c = new this04_c();
+    field av: int = a.val(10);
+    field bv: int = b.foo(10);
+    field cv: int = c.foo(10);
+}
+
+/* 
+heap {
+    record #0:6:this04 {
+        field a: this04_a = #1:this04_a;
+        field b: this04_b = #2:this04_b;
+        field c: this04_c = #3:this04_c;
+        field av: int = int:11;
+        field bv: int = int:13;
+        field cv: int = int:14;
+    }
+    record #1:1:this04_a {
+\tfield th: this04_a = #1:this04_a;
+    }
+    record #2:1:this04_b {
+\tfield th: this04_a = #2:this04_b;
+    }
+    record #3:1:this04_c {
+\tfield th: this04_a = #3:this04_c;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 6:30
+
+class cast04 {
+   method m() {
+      local y = x :: Type<int[]>;
+   }
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeMismatch @ 5:31
+
+class subtype04_a<X> extends subtype04_b {
+  field f: subtype04_a<int> = new subtype04_b();
+}
+class subtype04_b {
+}
+"
+"// @Harness: v2-init
+// @Test: logical operators
+// @Result: PASS
+
+component logical03 {
+    field res_01: bool = op(true);
+    field res_02: bool = op(false);
+
+    method op(a: bool): bool {
+\treturn !a;
+    }
+}
+
+/* 
+heap {
+    record #0:2:logical03 {
+        field res_01: bool = bool:false;
+        field res_02: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type19 {
+    field f: (type);
+}
+"
+"// @Harness: v2-exec
+// @Test: if statements and ternary expressions
+// @Result: 0
+
+class ch04b {
+    field A: int;
+    field B: int;
+    field R: int;
+
+    method choose(c: bool, a: int, b: int) {
+\tR = c ? (A = a) : (B = b);
+    }
+}
+
+component if04b {
+    
+    field res_01: ch04b = new ch04b();
+    field res_02: ch04b = new ch04b();
+
+    // res_01.A = 160;
+    // res_01.B = 0;
+    // res_01.R = 160;
+    // res_02.A = 0;
+    // res_02.B = 24;
+    // res_02.R = 24;
+
+    method main(arg: int): int {
+\tres_01.choose(true, 160, 42);
+        res_02.choose(false, 100, 24);
+\treturn res_01.B;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_unify02 {
+    method test() {
+\tlocal x: int, y: int;
+\tx = id(0, 'x');
+\ty = id('x', 0);
+    }
+    method id<X>(x: X, y: X): X {
+\treturn x;
+    }
+}
+"
+"/**
+ * USART driver.
+ * @author Ryan Hall
+ * @ modified by Xiaoli Gong Feb 20, 2009
+ * @ change the initial configuration of the port
+ */
+component USART {
+
+\t// bit names for UCSRnA register
+\tfield RXCn:  8 = 0x80;  // USART receive complete
+\tfield TXCn:  8 = 0x40;  // USART transmit complete
+\tfield UDREn: 8 = 0x20;  // USART data registe empty
+\tfield FEn:   8 = 0x10;  // Frame error : set to 1 when writing to UCSRnA
+\tfield DORn:  8 = 0x08;  // Data over run : set to 0 when writing to UCSRnA
+\tfield UPEn:  8 = 0x04;  // Parity error : set to 0 when writing to UCSRnA
+\tfield U2Xn:  8 = 0x02;  // Double USART transmission speed : set to 0 in sync mode
+\tfield MPCMn: 8 = 0x01;  // Multi-processor communication mode
+
+\t// bit names for UCSRnB register
+\tfield RXCIEn: 8 = 0x80;  // enable receive complete interrupt
+\tfield TXCIEn: 8 = 0x40;  // enable transmission complete interrupt
+\tfield UDRIEn: 8 = 0x20;  // enable data register empty interrupt
+\tfield RXENn:  8 = 0x10;  // enable receiver
+\tfield TXENn:  8 = 0x08;  // enable transmitter
+\tfield UCSZn2: 8 = 0x04;  // high end bit of 3 for frame size
+\tfield RXB8n:  8 = 0x02;  // 9th bit of received character
+\tfield TXB8n:  8 = 0x01;  // 9th bit of transmitted character
+
+\t// bit names for UCSRnC register
+\tfield UMSELn: 8 = 0x40;  // 0 for async, 1 for sync mode
+\tfield UPMn1:  8 = 0x20;  // Parity mode
+\tfield UPMn0:  8 = 0x10;  // Parity mode
+\tfield USBSn:  8 = 0x08;  // Number of stop bits inserted by transmitter
+\tfield UCSZn1: 8 = 0x04;  // Character size low 2 bits
+\tfield UCSZn0: 8 = 0x02;  // Character size low 2 bits
+\tfield UCPOLn: 8 = 0x01;  // Clock polarity in sync mode
+
+\t// Baud Rate Registers
+\t// UBRRnL : lower 8 bits of baud rate
+\t// UBRRnH : higher 4 bits of baud rate
+
+\t// Data Register
+\t// UDRn
+
+\tmethod calculateBaud(fosc: int, rate: int, mode: int): int {
+\tif ( mode == 0 ) return fosc / (16 * rate) - 1;
+\tif ( mode == 1 ) return fosc / (8 * rate) - 1;
+\tif ( mode == 2 ) return fosc / (2 * rate) - 1;
+\treturn 0;
+\t}
+}
+
+component USART0 {
+
+\t//bit names for UCSR0A register
+\tfield RXC0: 8 = 0x80;   // USART receive complete
+\tfield TXC0: 8 = 0x40;   // USART transmit complete
+\tfield UDRE0: 8 = 0x20;  // USART data registe empty
+\tfield FE0: 8 = 0x10;    // Frame error : set to 1 when writing to UCSR0A
+\tfield DOR0: 8 = 0x08;   // Data over run : set to 0 when writing to UCSR0A
+\tfield UPE0: 8 = 0x04;   // Parity error : set to 0 when writing to UCSR0A
+\tfield U2X0: 8 = 0x02;   // Double USART transmission speed : set to 0 in sync mode
+\tfield MPCM0: 8 = 0x01;  // Multi-processor communication mode
+
+\t//bit names for UCSR0B register
+\tfield RXCIE0: 8 = 0x80; // enable receive complete interrupt
+\tfield TXCIE0: 8 = 0x40; // enable transmission complete interrupt
+\tfield UDRIE0: 8 = 0x20; // enable data register empty interrupt
+\tfield RXEN0: 8 = 0x10;  // enable receiver
+\tfield TXEN0: 8 = 0x08;  // enable transmitter
+\tfield UCSZ02: 8 = 0x04; // high end bit of 3 for frame size
+\tfield RXB80: 8 = 0x02;  // 9th bit of received character
+\tfield TXB80: 8 = 0x01;  // 9th bit of transmitted character
+
+\t//bit names for UCSR0C register
+\tfield UMSEL0: 8 = 0x40;  // 0 for async, 1 for sync mode
+\tfield UPM01: 8 = 0x20;   // Parity mode
+\tfield UPM00: 8 = 0x10;   // Parity mode
+\tfield USBS0: 8 = 0x08;   // Number of stop bits inserted by transmitter
+\tfield UCSZ01: 8 = 0x04;  // Charcter size low 2 bits
+\tfield UCSZ00: 8 = 0x02;  // Charcter size low 2 bits
+\tfield UCPOL0: 8 = 0x01;  // Clock polarity in sync mode
+
+\tfield r_queue : Queue<char>;  // receive queue
+\tfield t_queue : Queue<char>;  // transmit queue
+ 
+\tfield checksum: CRC;
+\tfield printBuf: char[];
+\tfield packetbuf:char[];
+\tfield runningCRC:16 = 0x0000;
+\tfield usingCRC:boolean = false;
+
+\tconstructor() {
+\t\tr_queue = new Queue<char>(50);
+\t\tt_queue = new Queue<char>(127);
+\t\tchecksum = new CRC();
+
+\t\tprintBuf = new char [10];
+\t\tpacketbuf = new char [40];
+\t}
+
+\tmethod enable(baud_rate: int, sync_mode : boolean, double_async : boolean) {
+\t\t// set character size to 8
+\t\tdevice.UCSR0C = UCSZ01 | UCSZ00;
+\t\tif (sync_mode) {
+\t\t\tdevice.UCSR0C = device.UCSR0C | UMSEL0;
+\t\t} else if (double_async) {
+\t\t\tdevice.UCSR0A = U2X0;
+\t\t}
+\t\t// set baud rate
+\t\tdevice.UBRR0H = (baud_rate >> 8) :: 8;
+\t\tdevice.UBRR0L = (baud_rate & 0xFF) :: 8;
+\t\t///////////for test just set baud rate as 56.7K
+\t\tdevice.UBRR0H = 0x00;
+\t\tdevice.UBRR0L = 15::8; 
+
+\t\t// enable interrupts, receiver and transmitter
+\t\tdevice.UCSR0B = RXEN0 | TXEN0 | RXCIE0;
+\t\tPower.adjustPower();
+\t}
+
+\tmethod disable() {
+\t\t// disable transmitter and receiver
+\t\tdevice.UCSR0B = 0x0;
+\t\tPower.adjustPower();
+\t}
+
+\tmethod transmit(buf : char[], i : int, l : int) : int {
+\t\tlocal index : int = 0;
+\t\tlocal mask = MCU.disable();
+
+\t\tif (t_queue.size() + l + 5 >127) {
+\t\t\tMCU.restore(mask);
+\t\t\treturn 0;
+\t\t}
+\t\tif (usingCRC == true) {
+\t\t\tt_queue.enqueue(0x7e::char);//////start
+\t\t\trunningCRC = checksum.crcByte(runningCRC, 66::8);
+\t\t\tt_queue.enqueue(66::char);
+\t\t}
+\t\tfor (index = 0 ; index < l ; index++) {
+
+\t\tif (buf[i + index] == 0x7e::char or 
+\t\t\tbuf[i + index] == 0x7d::char) {
+\t\t\tt_queue.enqueue(0x7d::char);
+\t\t\tt_queue.enqueue(((buf[i + index])^(0x20))::char);
+\t\t} else {
+\t\t\tt_queue.enqueue(buf[i + index]);
+\t\t}
+\t\tif (usingCRC)
+\t\t\trunningCRC = checksum.crcByte(runningCRC,buf[i + index]);
+\t\t}
+\t\tif (usingCRC) {
+\t\t\tt_queue.enqueue((runningCRC&0xff)::char);
+\t\t\tt_queue.enqueue((((runningCRC)>>8)::8)::char);
+\t\t\tt_queue.enqueue(0x7e::char);
+\t\t\trunningCRC = 0x0000;
+\t\t}
+\t\tMCU.restore(mask);
+\t\tif (t_queue.size() > 0) {
+\t\t\t// turn on data ready interrupts
+\t\t\tdevice.UCSR0B |= RXEN0 | TXEN0 | TXCIE0| RXCIE0;
+\t\t\ttran_handler();
+\t\t}
+\t\treturn index;\t
+\t}
+
+\tmethod setCRCMode(mode:boolean) {
+\t\tusingCRC = mode;
+\t}
+
+\tmethod tran_handler() {
+\t\tlocal mask=MCU.disable();
+\t\tlocal cc:char ='\\0';
+\t\tif (t_queue.size() > 0) {
+\t\t\tcc = t_queue.dequeue();
+\t\t} else {
+\t\t\tMCU.restore(mask);
+\t\t\treturn;
+\t\t}
+
+\t\tdevice.UDR0 = cc;
+\t\tdevice.UCSR0A[6] = 0b1;
+\t\tMCU.restore(mask);
+\t\t// device.UCSR0B |= RXEN0 | TXEN0 | TXCIE0| RXCIE0;
+\t}
+
+\tmethod sendPackage(packet:TOS_Msg) {
+\t\tlocal data= 36; /* MSG_DATA_SIZE */
+\t\tlocal i=0;
+\t\tfor (i = 0; i < 36; i++)
+\t\t\tpacketbuf[i] = packet.getByte(i)::char;
+\t\twhile (data > 0) {
+\t\t\tdata -=transmit(packetbuf,36-data, data);
+\t\t}
+\t}
+
+\tmethod receive(buf : char[], i : int, l : int) : int {
+\t\tlocal count : int = 0;
+\t\tlocal mask = MCU.disable();
+\t\twhile (count < l and r_queue.size() > 0) {
+\t\t\tbuf[i + count] = r_queue.dequeue();\t\t
+\t\t\tcount++;
+\t\t}
+\t\tMCU.restore(mask);
+\t\treturn count;
+\t}
+
+\tmethod rec_handler() {
+\t\tdevice.UCSR0B = RXEN0 | TXEN0 | TXCIE0| RXCIE0;
+\t}
+
+\tmethod printString(buf: char[], length:int) {
+\t\ttransmit(buf,0,length);
+\t}
+\tmethod printHex16(data_in :16) {
+\t\t// TODO: convert this to use simpler raw operators
+\t\tlocal tem:int;
+
+\t\tif ((data_in & 0x000f)::int < 0xa::int) printBuf[3] = ('0'::int + (data_in & 0x000f)::int)::char;
+\t\telse printBuf[3] = ('A'::int + (data_in & 0x000f)::int - 0xA::int)::char;
+
+\t\ttem = ((data_in >> 4) & 0x000f)::int;
+\t\tif (tem::char < 0xa::char) printBuf[2] = ('0'::int + (tem))::char;
+
+\t\telse printBuf[2] = ('A'::int + (tem)-0xa::int)::char;
+
+\t\ttem = ((data_in >>8) & 0x000f)::int;
+
+\t\tif (tem::char < 0xa::char) printBuf[1] = ('0'::int + (tem))::char;
+\t\telse printBuf[1] = ('A'::int + (tem)-0xa::int)::char;
+
+\t\ttem = ((data_in >>12) & 0x000f)::int;
+
+\t\tif (tem::char < 0xa::char) printBuf[0] = ('0'::int + (tem))::char;
+\t\telse printBuf[0] = ('A'::int + (tem)-0xa::int)::char;
+
+\t\tprintBuf[4]='\
+';
+\t\tUSART0.transmit(printBuf, 0, 5);
+\t}
+
+\tmethod printHex8(data_in :8) {
+\t\t// TODO: convert this to use simpler raw operators
+\t\tlocal tem: int;
+\t\tif ((data_in & 0x0f)::char < 0xa::char) printBuf[1] = ('0'::int + (data_in & 0x0f)::int)::char;
+\t\telse printBuf[1] = ('A'::int + (data_in & 0x0f)::int-0xA::int)::char;
+
+\t\ttem = (data_in >> 4)::int;
+\t\tif (tem::char < 0xa::char) printBuf[0] = ('0'::int + (tem))::char;
+\t\telse printBuf[0] = ('A'::int + (tem) - 0xa::int)::char;
+
+\t\tprintBuf[2]='\
+';
+\t\tUSART0.transmit(printBuf, 0, 3);
+\t}
+}
+
+component USART1 {
+
+\t//bit names for UCSR0A register
+\tfield RXC1: 8 = 0x80;   // USART receive complete
+\tfield TXC1: 8 = 0x40;   // USART transmit complete
+\tfield UDRE1: 8 = 0x20;  // USART data registe empty
+\tfield FE1: 8 = 0x10;    // Frame error : set to 1 when writing to UCSR0A
+\tfield DOR1: 8 = 0x08;   // Data over run : set to 0 when writing to UCSR0A
+\tfield UPE1: 8 = 0x04;   // Parity error : set to 0 when writing to UCSR0A
+\tfield U2X1: 8 = 0x02;   // Double USART transmission speed : set to 0 in sync mode
+\tfield MPCM1: 8 = 0x01;  // Multi-processor communication mode
+
+\t//bit names for UCSR0B register
+\tfield RXCIE1: 8 = 0x80;  // enable receive complete interrupt
+\tfield TXCIE1: 8 = 0x40;  // enable transmission complete interrupt
+\tfield UDRIE1: 8 = 0x20;  // enable data register empty interrupt
+\tfield RXEN1: 8 = 0x10;   // enable receiver
+\tfield TXEN1: 8 = 0x08;   // enable transmitter
+\tfield UCSZ12: 8 = 0x04;  // high end bit of 3 for frame size
+\tfield RXB81: 8 = 0x02;   // 9th bit of received character
+\tfield TXB81: 8 = 0x01;   // 9th bit of transmitted character
+
+\t//bit names for UCSR0C register
+\tfield UMSEL1: 8 = 0x40;  // 0 for async, 1 for sync mode
+\tfield UPM11: 8 = 0x20;   // Parity mode
+\tfield UPM10: 8 = 0x10;   // Parity mode
+\tfield USBS1: 8 = 0x08;   // Number of stop bits inserted by transmitter
+\tfield UCSZ11: 8 = 0x04;  // Character size low 2 bits
+\tfield UCSZ10: 8 = 0x02;  // Character size low 2 bits
+\tfield UCPOL1: 8 = 0x01;  // Clock polarity in sync mode
+
+\tfield r_queue : Queue<char>;  //receive queue
+\tfield t_queue : Queue<char>;  //transmit queue
+\t
+\tconstructor() {
+\t\tr_queue = new Queue<char>(10);
+\t\tt_queue = new Queue<char>(10);
+\t}
+
+\tmethod enable(baud_rate: int, sync_mode : boolean, double_async : boolean) {
+
+\t\t// set character size to 8
+\t\tdevice.UCSR1C = UCSZ11 | UCSZ10;
+\t
+\t\tif (sync_mode) {
+\t\t\tdevice.UCSR1C = device.UCSR1C | UMSEL1;
+\t\t} else if (double_async) {
+\t\t\tdevice.UCSR1A = U2X1;
+\t\t}
+\t
+\t\t// set baud rate
+\t\tdevice.UBRR1H = (baud_rate >> 8) :: 8;
+\t\tdevice.UBRR1L = (baud_rate & 0xFF) :: 8;
+ 
+\t\t// enable interrupts, receiver and transmitter
+\t\tdevice.UCSR1B = RXEN1 | TXEN1 | RXCIE1;
+\t}
+
+\tmethod disable() {
+\t\t// disable receiver, transmitter and reciever
+\t\tdevice.UCSR1B = 0x0;
+\t}
+\tmethod transmit(buf : char[], i : int, l : int) : int {
+\t\tlocal index : int = 0;
+\t\tlocal mask = MCU.disable();
+\t\tfor (index = 0 ; index < l ; index++) {
+\t\t\t// if (t_queue.enqueue(buf[i + index])) { 
+\t\t\tif (t_queue.size() > 0) {
+\t\t\t\t// turn on data ready interrupts
+\t\t\t\tdevice.UCSR1B = device.UCSR1B | UDRIE1; 
+\t\t\t}
+\t\t\t// } else {
+\t\t\t// MCU.restore(mask);
+\t\t\t// return index;
+\t\t\t// }
+\t\t}
+\t\tMCU.restore(mask);
+\t\treturn index;\t
+\t}
+
+\tmethod tran_handler() {
+\t\tlocal c = t_queue.dequeue();
+\t\tif (t_queue.size() == 0) {
+\t\t\t//turn off data ready interrupts
+\t\t\tdevice.UCSR1B = device.UCSR1B & ~UDRIE1;
+\t\t}
+\t\tdevice.UDR1 = c;
+\t}
+
+\tmethod receive(buf : char[], i : int, l : int) : int {
+\t\tlocal count : int = 0;
+\t\tlocal mask = MCU.disable();
+\t\twhile(count < l and r_queue.size() > 0) {
+\t\t\tbuf[i + count] = r_queue.dequeue();\t\t
+\t\t\tcount++;
+\t\t}
+\t\tMCU.restore(mask);
+\t\treturn count;
+\t}
+
+\tmethod rec_handler() {
+\t\tlocal c : char = (device.UDR1) :: char;
+\t\tr_queue.enqueue(c);
+\t}
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=UnimplementedException, 2=21, 3=31, 4=42
+
+class abstract02_1 {
+    method val(): int;
+}
+
+class abstract02_2 extends abstract02_1 {
+    method val(): int { return 21; }
+}
+
+class abstract02_3 extends abstract02_1 {
+    method val(): int { return 31; }
+}
+
+component abstract02 {
+    field a: abstract02_1 = new abstract02_1();
+    field b: abstract02_1 = new abstract02_2();
+    field c: abstract02_1 = new abstract02_3();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.val();
+\tif ( arg == 2 ) return b.val();
+\tif ( arg == 3 ) return c.val();
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; invocation of method on non-object
+// @Result: UnresolvedMember @ 6:6
+
+class type02 {
+    
+    method testm(a: int) {
+        a.foo();
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component field06 {
+    field foo: char = 'h';
+}
+
+/* 
+heap {
+    record #0:1:field06 {
+        field foo: char = char:104;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=13, 3=14, 4=NullCheckException, 5=42
+
+class rtex_null12_obj {
+    field foo: int[];
+    constructor(i: int[]) { foo = i; }
+}
+
+component rtex_null12 {
+    field i: int[] = { 13, 14 };
+    field a: rtex_null12_obj = new rtex_null12_obj(null);
+    field b: rtex_null12_obj = new rtex_null12_obj(i);
+    field c: rtex_null12_obj = new rtex_null12_obj(null);
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.foo[0];
+\tif ( arg == 2 ) return b.foo[0];
+\tif ( arg == 3 ) return b.foo[1];
+\tif ( arg == 4 ) return c.foo[0];
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type20 {
+    field f: 1;
+    field g: 2;
+    field h: 3;
+    field i: 4;
+    field j: 16;
+    field k: 32;
+    field l: 64;
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeParamArityMismatch @ 5:20
+
+class num_params01_a<X> {
+  method getThis(): num_params01_a { return this; }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_field03_a extends inh_field03_b {
+  field h: int;
+  field j: bool;
+}
+
+class inh_field03_b extends inh_field03_c {
+  field f: int;
+  field g: bool;
+}
+
+class inh_field03_c {
+}
+
+component inh_field03_d {
+  method m(o: inh_field03_a) {
+    local x1 = o.f;
+    local x2 = o.g;
+    local x3 = o.h;
+    local x4 = o.j;
+  }
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Result: 0=0, 1=10, 2=11, 3=12, 4=0
+
+component static03 {
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return val1();
+\tif ( arg == 2 ) return val2();
+\tif ( arg == 3 ) return val3();
+\treturn 0;
+    }
+
+    method val1(): int { return 10; }
+    method val2(): int { return val1()+1; }
+    method val3(): int { return val2()+1; }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class this05_a {
+    method getf(): function(): int { return this.val; }
+    method val(): int { return 1; }
+}
+
+class this05_b extends this05_a {
+    method val(): int { return 2; }
+}
+
+class this05_c extends this05_a {
+    method val(): int { return 3; }
+}
+
+component this05 {
+    field a: function():int = new this05_a().getf();
+    field b: function():int = new this05_b().getf();
+    field c: function():int = new this05_c().getf();
+    field av: int = a();
+    field bv: int = b();
+    field cv: int = c();
+}
+
+/* 
+heap {
+    record #0:6:this05 {
+        field a: function():int = [#1:this05_a,this05_a:val()];
+        field b: function():int = [#2:this05_b,this05_b:val()];
+        field c: function():int = [#3:this05_c,this05_c:val()];
+        field av: int = int:1;
+        field bv: int = int:2;
+        field cv: int = int:3;
+    }
+    record #1:0:this05_a {
+    }
+    record #2:0:this05_b {
+    }
+    record #3:0:this05_c {
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=2, 2=30, 3=2, 4=30, 5=42
+
+component array20 {
+    field a: char[] =  {\'1\', \'2\'};
+    field b: char[] =  ""helloyoudirtyrat--it\'s go time"";
+    field len1: int = a.length;
+    field len2: int = b.length;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return len1;
+\tif ( arg == 2 ) return len2;
+\tif ( arg == 3 ) return a.length;
+\tif ( arg == 4 ) return b.length;
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component order13 {
+    field order: int[] = { 0, 0, 0 };
+    field pos: int = 0;
+
+    field res_01: int = op(1, 2, 3);
+
+    method op(a: int, b: int, c: int): int {
+\treturn eval(a, 1) + eval(b, 2) * eval(c, 3);
+    }
+
+    method eval(a: int, n: int): int {
+        order[pos] = n;
+        pos++;
+        return a;
+    }
+}
+
+/* 
+heap {
+    record #0:10:order13 {
+        field order: int[] = #1:int[3];
+        field pos: int = int:3;
+        field res_01: int = int:7;
+    }
+    record #1:3:int[3] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+\tfield 2:int = int:3;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: TypeMismatch @ 6:16
+
+class type40 {
+    
+    method testm() {
+        local a: int = 2 <= null;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment options
+// @Result: PASS
+
+component prepost02 {
+    field foo: int = 1;
+    field bar: int = foo--;
+}
+
+/* 
+heap {
+    record #0:2:prepost02 {
+        field foo: int = int:0;
+        field bar: int = int:1;
+    }
+}*/
+"
+"// @Harness: v2-seman
+// @Test: typechecking; primitive operations
+// @Result: CannotCompareValues @ 6:16
+
+class type43 {
+    
+    method testm() {
+        local a = (2 != null);
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=13, 2=14, 3=15, 4=16, 5=17, 6=18, 7=19, 8=20, 9=21, 10=22, 11=23, 12=24, 13=25, 14=4, 15=3, 16=6, 17=42 
+
+component array17 {
+    field a: int[][] =  new int[][4];
+    field b: bool[][] =  new bool[][3];
+    field c: char[][] = new char[][6];
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a[0] == null ? 13 : 77;
+\tif ( arg == 2 ) return a[1] == null ? 14 : 77;
+\tif ( arg == 3 ) return a[2] == null ? 15 : 77;
+\tif ( arg == 4 ) return a[3] == null ? 16 : 77;
+
+\tif ( arg == 5 ) return b[0] == null ? 17 : 77;
+\tif ( arg == 6 ) return b[1] == null ? 18 : 77;
+\tif ( arg == 7 ) return b[2] == null ? 19 : 77;
+
+\tif ( arg == 8 )  return c[0] == null ? 20 : 77;
+\tif ( arg == 9 )  return c[1] == null ? 21 : 77;
+\tif ( arg == 10 ) return c[2] == null ? 22 : 77;
+\tif ( arg == 11 ) return c[3] == null ? 23 : 77;
+\tif ( arg == 12 ) return c[4] == null ? 24 : 77;
+\tif ( arg == 13 ) return c[5] == null ? 25 : 77;
+
+\tif ( arg == 14 ) return a.length;
+\tif ( arg == 15 ) return b.length;
+\tif ( arg == 16 ) return c.length;
+
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class cast02b {
+   method m() {
+      local y = x :: (Type<X>);
+   }
+}
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test typechecking of elements in multidimensional arrays""
+// @Result: PASS
+
+class array13 {
+    
+    method testm(a: int[][]) {
+        a[0][0] = 0;
+    }
+}
+"
+" /*  
+  * This module provides the layer2 functionality for the mica2 radio.
+  * While the internal architecture of this module is not CC1000 specific,
+  * It does make some CC1000 specific calls via CC1000Control.
+  * @author Xiaoli Gong
+  */
+component CC1000Radio {
+
+\tfield CC1K_SquelchInit: int\t\t= 312;
+\tfield CC1K_SquelchTableSize: int\t= 9;     
+\tfield CC1K_MaxRSSISamples: int\t\t= 5;
+\tfield CC1K_Settling: int\t\t= 1;
+\tfield CC1K_ValidPrecursor: int\t\t= 2;
+\tfield CC1K_SquelchIntervalFast: int\t= 128;
+\tfield CC1K_SquelchIntervalSlow: int\t= 2560;
+\tfield CC1K_SquelchCount: int\t\t= 30;
+\tfield CC1K_SquelchBuffer: int\t\t= 0;
+
+\tfield CC1K_LPL_STATES: int\t\t= 7;
+
+\tfield CC1K_LPL_PACKET_TIME: int\t\t= 16;
+\tfield TX_STATE: int\t\t\t= 0;
+\tfield DISABLED_STATE: int\t\t= 1;
+\tfield IDLE_STATE: int\t\t\t= 2;
+\tfield PRETX_STATE: int\t\t\t= 3;
+\tfield SYNC_STATE: int\t\t\t= 4;
+\tfield RX_STATE: int\t\t\t= 5;
+\tfield SENDING_ACK: int\t\t\t= 6;
+\tfield  POWER_DOWN_STATE: int\t\t= 7;
+\tfield NULL_STATE: int\t\t\t= 8;
+
+\tfield TXSTATE_WAIT: int\t\t\t= 0;
+\tfield TXSTATE_START: int\t\t= 1;
+\tfield TXSTATE_PREAMBLE: int\t\t= 2;
+\tfield TXSTATE_SYNC: int\t\t\t= 3;
+\tfield TXSTATE_DATA: int\t\t\t= 4;
+\tfield TXSTATE_CRC: int\t\t\t= 5;
+\tfield TXSTATE_FLUSH: int\t\t= 6;
+\tfield TXSTATE_WAIT_FOR_ACK: int\t\t= 7;
+\tfield TXSTATE_READ_ACK: int\t\t= 8;
+\tfield TXSTATE_DONE: int\t\t\t= 9;
+
+\tfield SYNC_WORD: 16\t\t\t= 0x33cc;
+\tfield NSYNC_WORD: 16\t\t\t= 0xcc33;
+\tfield SYNC_BYTE: 8\t\t\t= 0x33;
+\tfield NSYNC_BYTE: 8\t\t\t= 0xcc;
+\tfield ACK_LENGTH: int\t\t\t= 16;
+\tfield MAX_ACK_WAIT: int\t\t\t= 18;
+
+\tfield TOS_LOCAL_ADDRESS: 16\t\t= 0x0001;  
+\tfield TOS_BCAST_ADDR: 16\t\t= 0xffff;
+
+\tfield CC1K_LPL_PreambleLength: 8[];
+\tfield CC1K_LPL_SleepTime: 8[];
+\tfield CC1K_LPL_SleepPreamble: 8[];
+
+\tfield ack_code: 8[] = new 8[3]; 
+\tfield RadioState: int;
+\tfield RadioTxState: int;
+\tfield RSSIInitState: int;
+
+\tfield iRSSIcount: int;
+\tfield iSquelchCount: int;
+\tfield txlength: 16;
+\tfield rxlength: int;
+
+\tfield txbufptr: TOS_Msg;  // pointer to transmit buffer
+\tfield rxbufptr: TOS_Msg;  // pointer to receive buffer
+
+\tfield NextTxByte: 8;
+
+\tfield lplpower: int;\t\t// low power listening mode
+\tfield lplpowertx: int;\t\t// low power listening transmit mode
+
+\tfield preamblelen: int;\t\t// current length of the preamble
+
+\tfield PreambleCount: int;\t// found a valid preamble
+\tfield SOFCount: int;
+
+\tfield search_word: 16;
+
+\tfield RxShiftBuf: 16;
+\tfield RxBitOffset: int;\t\t// bit offset for spibus
+\tfield RxByteCnt: int;\t\t// received byte counter
+\tfield TxByteCnt: int;
+\tfield RSSISampleFreq: int;\t// in Bytes rcvd per sample
+\tfield bInvertRxData: boolean;\t// data inverted
+\tfield bTxPending: boolean;
+\tfield bTxBusy: boolean;
+\tfield bAckEnable: boolean;
+\tfield usRunningCRC: 16;\t\t// Running CRC variable
+\tfield usRSSIVal: int;\t\t// suppress nesc warnings
+\tfield usSquelchVal: int;
+\tfield usTempSquelch: int;
+\tfield usSquelchIndex: int;
+
+\tfield usSquelchTable: int[] = new int[CC1K_SquelchTableSize];
+
+\tfield sMacDelay: int;    // MAC delay for the next transmission
+\tfield LocalAddr: 16;
+
+\tfield receivecallback: function(TOS_Msg): TOS_Msg;
+\tfield sendDonecallback: function(TOS_Msg, boolean);
+\tfield checksum: CRC;
+\tfield tempArray: int [];
+\tfield firedTickValue: int;
+
+\tconstructor() {
+\t\tchecksum = new CRC();
+
+\t\ttempArray = new int[CC1K_SquelchTableSize];
+
+\t\tack_code[0] = 0xab;
+\t\tack_code[1] = 0xba;
+\t\tack_code[2] = 0x83;
+\t\trxbufptr = new TOS_Msg();
+
+\t\tCC1K_LPL_PreambleLength = new 8[CC1K_LPL_STATES * 2];
+\t\tCC1K_LPL_PreambleLength[0] = 0x00;
+\t\tCC1K_LPL_PreambleLength[1] = 0x08;
+\t\tCC1K_LPL_PreambleLength[2] = 0x00;
+\t\tCC1K_LPL_PreambleLength[3] = 94::8;
+\t\tCC1K_LPL_PreambleLength[4] = 0x00;
+\t\tCC1K_LPL_PreambleLength[5] = 250::8;
+\t\tCC1K_LPL_PreambleLength[6] = 0x01;
+\t\tCC1K_LPL_PreambleLength[7] = 0x73;
+\t\tCC1K_LPL_PreambleLength[8] = 0x01;
+\t\tCC1K_LPL_PreambleLength[9] = 0xea;
+\t\tCC1K_LPL_PreambleLength[10] = 0x04;
+\t\tCC1K_LPL_PreambleLength[11] = 0xbc;
+\t\tCC1K_LPL_PreambleLength[12] = 0x0a;
+\t\tCC1K_LPL_PreambleLength[13] = 0x5e;
+
+\t\tCC1K_LPL_SleepTime = new 8[CC1K_LPL_STATES * 2];
+\t\tCC1K_LPL_SleepTime[0] = 0x00;
+\t\tCC1K_LPL_SleepTime[1] = 0x00;
+\t\tCC1K_LPL_SleepTime[2] = 0x00;
+\t\tCC1K_LPL_SleepTime[3] = 20::8;
+\t\tCC1K_LPL_SleepTime[4] = 0x00;
+\t\tCC1K_LPL_SleepTime[5] = 85::8;
+\t\tCC1K_LPL_SleepTime[6] = 0x00;
+\t\tCC1K_LPL_SleepTime[7] = 135::8;
+\t\tCC1K_LPL_SleepTime[8] = 0x00;
+\t\tCC1K_LPL_SleepTime[9] = 185::8;
+\t\tCC1K_LPL_SleepTime[10] = 0x01;
+\t\tCC1K_LPL_SleepTime[11] = 0xe5;
+\t\tCC1K_LPL_SleepTime[12] = 0x04;
+\t\tCC1K_LPL_SleepTime[13] = 0x3d;\t
+
+\t\tCC1K_LPL_SleepPreamble = new 8[CC1K_LPL_STATES];
+\t\tCC1K_LPL_SleepPreamble[0] = 0x00;
+\t\tCC1K_LPL_SleepPreamble[1] = 0x08;
+\t\tCC1K_LPL_SleepPreamble[2] = 0x08;
+\t\tCC1K_LPL_SleepPreamble[3] = 0x08;
+\t\tCC1K_LPL_SleepPreamble[4] = 0x08;
+\t\tCC1K_LPL_SleepPreamble[5] = 0x08;
+\t\tCC1K_LPL_SleepPreamble[6] = 0x08;
+
+\t\treceivecallback = dummyReceiveCallback;
+\t\tsendDonecallback = dummysendDoneCallback;
+\t}
+
+\tmethod PRG_RDB(value: 8): int{
+\t\treturn (value::int);
+\t}
+
+\tmethod dummyReceiveCallback(data: TOS_Msg):TOS_Msg {
+\t\treturn data;
+\t}
+
+\tmethod dummysendDoneCallback(data: TOS_Msg, result: boolean) {
+\t}
+
+\tmethod SetReceiveCallback(callback: function(TOS_Msg): TOS_Msg) {
+\t\treceivecallback = callback;
+\t}
+
+\tmethod SetsendDoneCallback(callback: function(TOS_Msg, boolean)) {
+\t\tsendDonecallback = callback;
+\t}
+
+\tmethod SquelchTimerstart(interval : int) {
+\t\tlocal ticks: int;
+\t\tdevice.ASSR = 0b1000;               // set Timer0 to asynch operation
+\t\t// Timer0.setMode(Timer0.MODE_CTC);    // use clear timer on compare mode
+\t\tTimer0.setMode(Timer0.MODE_NORMAL);    // all the timer used in this system is ONE_SHOT timer
+
+\t\tticks = Timer0.getCount() + interval;
+\t\tif ((ticks < firedTickValue) or (firedTickValue <0) ) {
+\t\t\tTimer0.setCompareMatch(ticks);         // compare matches every (16 * 1024) cycles
+\t\t\tfiredTickValue = ticks;
+\t\t}
+\t\tdevice.TIMSK = 0b10;                // restore the Timer0 compare interrupt
+
+\t\t// Timer0.setDivider(Timer0.DIV_1024); // set divider to 1024
+\t\tTimer0.setDivider(Timer0.DIV_1); // set divider to 1
+
+\t\tMica2.setTimerCompare(SquelchTimerfired);
+\t\t// Timer0.enable();
+\t\t// Mica2.startTimer();
+\t}
+
+\tmethod SquelchTimerstop() {
+\t\tTimer0.disable();
+\t}
+
+\tmethod WakeupTimerstart(interval: int) {
+\t\t// TODO
+\t}
+
+\tmethod WakeupTimerstop() {
+\t\t// TODO: Timer0.disable();
+\t}
+
+\tmethod adjustSquelch() {
+\t\tlocal i: int, j: int, min: int;
+\t\tlocal min_value: int = 0;
+\t\tlocal tempsquelch: 32;
+
+\t\tlocal mask: 8;
+
+\t\tmask = MCU.disable();
+\t\tusSquelchTable[usSquelchIndex] = usTempSquelch;
+\t\tusSquelchIndex++;
+\t\tif (usSquelchIndex >= CC1K_SquelchTableSize) usSquelchIndex = 0;
+\t\tif (iSquelchCount <= CC1K_SquelchCount) iSquelchCount++;  
+\t\tMCU.restore(mask);
+
+\t\tfor (i = 0; i < CC1K_SquelchTableSize; i++) {
+\t\t\ttempArray[i] = usSquelchTable[i];
+\t\t}
+
+\t\tmin = 0;
+\t\tfor (j = 0; j < 3; j++) {
+\t\t\tfor (i = 1; i < CC1K_SquelchTableSize; i++) {
+\t\t\t\tif ((tempArray[i] != 65535) and 
+\t\t\t\t\t(((tempArray[i]) > (tempArray[min])) or
+\t\t\t\t\t\t(tempArray[min] == 65535))) {
+\t\t\t\t\tmin = i;
+\t\t\t\t}
+\t\t\t}
+\t\t\tmin_value = tempArray[min];
+\t\t\ttempArray[min] = 0xFFFF::int;
+\t\t}
+
+\t\ttempsquelch = ((usSquelchVal *32) + (min_value *2))::32;
+\t\t// atomic usSquelchVal = (16)((tempsquelch / 34) & 0x0FFFF);
+\t\tmask = MCU.disable();
+\t\tusSquelchVal = ((tempsquelch::int / 34) & 0xFFFF::int)::int;
+\t\tMCU.restore(mask);
+\t}
+
+\tmethod PacketRcvd(): boolean {
+\t\tlocal pBuf: TOS_Msg;
+\t\tlocal mask: 8;
+
+\t\tmask = MCU.disable();
+\t\trxbufptr.time = 0::16;
+\t\tpBuf = rxbufptr;
+\t\tMCU.restore(mask);
+\t\tpBuf = receivecallback(pBuf);
+\t\tmask = MCU.disable();
+\t\trxbufptr = pBuf;
+\t\trxbufptr.length = 0x00;
+\t\tMCU.restore(mask);
+\t\tSPI.enableIntr();
+\t\treturn true;
+\t}
+
+\tmethod PacketSent() {
+\t\tlocal pBuf:TOS_Msg; // store buf on stack 
+\t\tlocal mask: 8;
+\t\tmask = MCU.disable();
+\t\ttxbufptr.time = 0::16;
+\t\tpBuf = txbufptr;
+\t\tbTxBusy = false;
+\t\tSPI.writeByte(0xaa); // reset the buffer in device driver
+\t\tMCU.restore(mask);
+\t\tsendDonecallback(pBuf,true);
+\t}
+
+\tmethod init(): boolean {
+\t\tlocal i: int;
+\t\tlocal mask: 8;
+\t\tmask = MCU.disable();
+\t\tRadioState = DISABLED_STATE;
+\t\tRadioTxState = 2 /*TXSTATE_PREAMBLE*/;
+\t\tRSSIInitState = NULL_STATE;
+\t\trxbufptr.length = 0x00;
+\t\t// MSG_DATA_SIZE is 36 by default
+\t\trxlength = (36 - 2);
+\t\tRxBitOffset = 0;
+\t\tiSquelchCount = 0;
+
+\t\tPreambleCount = 0;
+\t\tRSSISampleFreq = 0;
+\t\t// RxShiftBuf.W = 0;
+\t\tRxShiftBuf = 0::16;
+\t\tiRSSIcount = 0;
+\t\tbTxPending = false;
+\t\tbTxBusy = false;
+\t\tbAckEnable = false;
+\t\tsMacDelay = -1;
+\t\tusRSSIVal = -1;
+\t\tusSquelchIndex = 0;
+\t\tlplpower = lplpowertx = 0;
+\t\tusSquelchVal = CC1K_SquelchInit;
+\t\tMCU.restore(mask);
+
+\t\tfor (i = 0; i < CC1K_SquelchTableSize; i++)
+\t\t\tusSquelchTable[i] = CC1K_SquelchInit;
+
+\t\tSPI.writeByte(0xaa); // preamble byte as initial value
+\t\tSPI.setCallback(SpidataReady);
+\t\tSPI.setWorkMode(SPI.sendperByte);
+\t\tSPI.startSlave(); // set spi bus to slave mode
+
+\t\tCC1000Control.init();
+\t\tCC1000Control.SelectLock(0x09);\t\t// Select MANCHESTER VIOLATION
+\t\tbInvertRxData = CC1000Control.GetLOStatus();
+
+\t\tADC.setConvFunc(ADCdataReady);
+\t\tADC.enable();
+
+\t\tLocalAddr = TOS_LOCAL_ADDRESS;
+
+\t\tMCU.enable();
+\t\tfiredTickValue = -1;
+
+\t\treturn true;
+\t}
+
+\tmethod EnableRSSI(): boolean {
+\t\treturn true;
+\t}
+
+\tmethod DisableRSSI(): boolean {
+\t\treturn true;
+\t}
+
+\tmethod GetTransmitMode(): 8 {
+\t\treturn lplpowertx::8;
+\t}
+
+\t/**
+\t * Set the state of low power transmit on the chipcon radio.
+\t * The transmit mode of the sender *must* match the receiver in
+\t * order for the receiver to successfully get the packet.
+\t * <p>
+\t * The default power up state is 0 (radio always on).
+\t * See CC1000Const.h for low power duty cycles and bandwidth
+\t */
+\tmethod SetTransmitMode(power: 8): boolean {
+\t\tlocal mask: 8;
+
+\t\tif ((power::int >= CC1K_LPL_STATES) or (power == lplpowertx)) return false;
+
+\t\t// check if the radio is currently doing something
+\t\tif ((!bTxPending) and\t((RadioState ==\t7 /*POWER_DOWN_STATE*/) or 
+\t\t\t(RadioState == 2 /*IDLE_STATE*/ ) or
+\t\t\t(RadioState == DISABLED_STATE))) {
+\t\t\tmask = MCU.disable();
+\t\t\tlplpowertx = power::int;
+\t\t\tpreamblelen = PRG_RDB(CC1K_LPL_PreambleLength[(lplpowertx*2)]);
+\t\t\tpreamblelen = preamblelen * 256 + PRG_RDB(CC1K_LPL_PreambleLength[((lplpowertx * 2) + 1)]);
+\t\t\tMCU.restore(mask);
+\t\t\treturn true;
+\t\t}
+\t\treturn true;
+\t}
+
+\t/**
+\t * Set the state of low power listening on the chipcon radio.
+\t * <p>
+\t * The default power up state is 0 (radio always on).
+\t * See CC1000Const.h for low power duty cycles and bandwidth
+\t */
+\tmethod SetListeningMode(power: 8): boolean {
+\t\tlocal mask: 8;
+\t\t// valid low power listening values are 0 to 3
+\t\t// 0 is ""always on"" and 3 is lowest duty cycle
+\t\t// 1 and 2 are in the middle
+\t\tif ((power::int >= CC1K_LPL_STATES) or (power == lplpower)) return false;
+
+\t\t// check if the radio is currently doing something
+\t\tif ((!bTxPending) and ((RadioState ==\t7 /*POWER_DOWN_STATE*/) or 
+\t\t\t(RadioState == 2 /*IDLE_STATE*/ ) or
+\t\t\t(RadioState == DISABLED_STATE))) {
+
+\t\t\t// change receiving function in CC1000Radio
+\t\t\t// WakeupTimer.stop();
+\t\t\tWakeupTimerstop();
+\t\t\tmask = MCU.disable();
+\t\t\tif (lplpower == lplpowertx) {
+\t\t\t\tlplpowertx = power::int;
+\t\t\t}
+\t\t\tlplpower = power::int;
+\t\t\tMCU.restore(mask);
+
+\t\t\t// if successful, change power here
+\t\t\tif (RadioState == 2 /*IDLE_STATE*/) {
+\t\t\t\tRadioState = DISABLED_STATE;
+\t\t\t\tstop();
+\t\t\t\tstart();
+\t\t\t}
+\t\t\tif (RadioState == 7 /*POWER_DOWN_STATE*/) {
+\t\t\t\tRadioState = DISABLED_STATE;
+\t\t\t\tstart();
+\t\t\t}
+\t\t} else {
+\t\t\treturn false;
+\t\t}
+\t\treturn true;
+\t}
+
+\tmethod GetListeningMode(): 8 {
+\t\treturn lplpower::8;
+\t} 
+
+
+\tmethod SquelchTimerfired() {
+\t\tlocal currentRadioState: int = RadioState;
+\t\tif (currentRadioState == 1 /*DISABLED_STATE*/) {
+\t\t\tRSSIInitState = currentRadioState;
+\t\t\tADC.startConv(0, true);
+\t\t}
+\t}
+
+\tmethod WakeupTimerfired() {
+\t\tlocal sleeptime: int;
+\t\tlocal tempTxPending: boolean;
+\t\tlocal currentRadioState: int;
+
+\t\tlocal mask: 8;
+
+\t\tif (lplpower == 0) return;
+
+\t\tmask = MCU.disable();
+\t\tcurrentRadioState = RadioState;
+\t\ttempTxPending = bTxPending;
+\t\tMCU.restore(mask);
+
+\t\tswitch (currentRadioState) {
+\t\t\tcase (2 /*IDLE_STATE*/) {
+\t\t\t\tsleeptime = PRG_RDB(CC1K_LPL_SleepTime[lplpower*2]) ;
+\t\t\t\tsleeptime = sleeptime * 256 + PRG_RDB(CC1K_LPL_SleepTime[(lplpower*2)+1]);
+\t\t\t\tif (!tempTxPending) {
+\t\t\t\t\tRadioState = 7 /*POWER_DOWN_STATE*/;
+\t\t\t\t\tWakeupTimerstart(sleeptime);
+\t\t\t\t\tSquelchTimerstop();
+\t\t\t\t\tCC1000Control.stop();
+\t\t\t\t\tSPI.disableIntr();
+\t\t\t\t} else {
+\t\t\t\t\tWakeupTimerstart(CC1K_LPL_PACKET_TIME*2);
+\t\t\t\t}
+\t\t\t}
+\t\t\tcase (7 /*POWER_DOWN_STATE*/) {
+\t\t\t\tsleeptime = PRG_RDB(CC1K_LPL_SleepPreamble[lplpower]);
+\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\tCC1000Control.start();
+\t\t\t\tCC1000Control.BIASOn();
+\t\t\t\tSPI.rxMode();\t\t// SPI to miso
+\t\t\t\tCC1000Control.RxMode();
+\t\t\t\tSPI.enableIntr(); // enable spi interrupt
+
+\t\t\t\tif (iSquelchCount > CC1K_SquelchCount) SquelchTimerstart(CC1K_SquelchIntervalSlow);
+\t\t\t\telse SquelchTimerstart(CC1K_SquelchIntervalFast);
+
+\t\t\t\tWakeupTimerstart(sleeptime);
+\t\t\t}
+\t\t\tdefault {
+\t\t\t\tWakeupTimerstart(CC1K_LPL_PACKET_TIME * 2);
+\t\t\t}
+\t\t}
+\t\treturn;
+\t}
+
+\tmethod stop(): boolean {
+\t\tRadioState = DISABLED_STATE;
+\t\tSquelchTimerstop();
+\t\tWakeupTimerstop();
+\t\tADC.disable();
+\t\tCC1000Control.stop();
+\t\tSPI.disableIntr(); // disable spi interrupt
+\t\treturn true;
+\t}
+
+\tmethod start(): boolean {
+\t\tlocal mask: 8;
+\t\tlocal currentRadioState: int;
+\t\tcurrentRadioState = RadioState;
+\t\tADC.setConvFunc(ADCdataReady);
+\t\tif (currentRadioState == DISABLED_STATE) {
+\t\t\tmask = MCU.disable();
+\t\t\trxbufptr.length = 0x00;
+\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\tbTxPending = bTxBusy = false;
+\t\t\tsMacDelay = -1;
+\t\t\tpreamblelen = PRG_RDB(CC1K_LPL_PreambleLength[lplpowertx * 2]) * 256;
+\t\t\tpreamblelen += PRG_RDB(CC1K_LPL_PreambleLength[(lplpowertx * 2) + 1]);
+\t\t\tMCU.restore(mask);
+\t\t\tif (lplpower == 0) {
+\t\t\t\t// all power on, captain!
+\t\t\t\trxbufptr.length = 0x00;
+\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\tCC1000Control.start();
+\t\t\t\tCC1000Control.BIASOn();
+\t\t\t\tSPI.rxMode();\t\t// SPI to miso
+\t\t\t\tCC1000Control.RxMode();
+
+\t\t\t\tif (iSquelchCount > CC1K_SquelchCount) SquelchTimerstart(CC1K_SquelchIntervalSlow);
+\t\t\t\telse SquelchTimerstart(CC1K_SquelchIntervalFast);
+
+\t\t\t\tSPI.enableIntr(); // enable spi interrupt
+\t\t\t} else {
+\t\t\t\tlocal sleeptime: int;
+\t\t\t\tsleeptime = PRG_RDB(CC1K_LPL_SleepTime[lplpower*2]) *256;
+\t\t\t\tsleeptime = PRG_RDB(CC1K_LPL_SleepTime[(lplpower*2)+1]);
+\t\t\t\tRadioState = 7 /*POWER_DOWN_STATE*/;
+
+\t\t\t\tSquelchTimerstop();
+
+\t\t\t\tWakeupTimerstart(sleeptime);
+\t\t\t}
+\t\t}
+\t\treturn true;
+\t}
+
+\tmethod send(pMsg:TOS_Msg): boolean {
+\t\tlocal mask: 8;
+\t\tlocal Result: boolean = true;
+\t\tlocal currentRadioState: int = 0;
+
+\t\tmask = MCU.disable();
+\t\tif (bTxBusy) {
+\t\t\tResult = false;
+\t\t} else {
+\t\t\tbTxBusy = true;
+\t\t\ttxbufptr = pMsg;
+\t\t\ttxbufptr.ack = 0x00;
+\t\t\ttxlength = (pMsg.length::int + (36 /*MSG_DATA_SIZE*/ - 29 /*DATA_LENGTH*/ - 2))::16; 
+\t\t\t// initially back off [1,32] bytes (approx 2/3 packet)
+\t\t\tbTxPending = true;
+\t\t}
+\t\tcurrentRadioState = RadioState;
+\t\tMCU.restore(mask);
+
+\t\tif (Result) {
+\t\t\t// if we\'re off, start the radio
+\t\t\tif (currentRadioState == 7 /*POWER_DOWN_STATE*/) {
+\t\t\t\t// disable wakeup timer
+\t\t\t\tWakeupTimerstop();
+\t\t\t\tCC1000Control.start();
+\t\t\t\tCC1000Control.BIASOn();
+\t\t\t\tCC1000Control.RxMode();
+\t\t\t\tSPI.rxMode();\t\t// SPI to miso
+\t\t\t\tSPI.enableIntr(); // enable spi interrupt
+\t\t\t\tif (iSquelchCount > CC1K_SquelchCount) SquelchTimerstart(CC1K_SquelchIntervalSlow);
+\t\t\t\telse SquelchTimerstart(CC1K_SquelchIntervalFast);
+\t\t\t\tWakeupTimerstart(CC1K_LPL_PACKET_TIME*2);
+\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t}
+\t\t}
+\t\treturn Result;
+\t}
+
+\t/**********************************************************
+\t * make a spibus interrupt handler
+\t * needs to handle interrupts for transmit delay
+\t * and then go into byte transmit mode with
+\t * timer1 baudrate delay as interrupt handler
+\t * else
+\t * needs to handle interrupts for byte read and detect preamble
+\t * then handle reading a packet
+\t * PB - We can use this interrupt handler as a transmit scheduler
+\t * because the CC1000 continuously clocks in data, regarless
+\t * of whether it\'s good or not.  Thus, this routine will be called
+\t * on every 8 ticks of DCLK. 
+\t **********************************************************/
+\tmethod SpidataReady(data_in: 8) {
+\t\tif (bInvertRxData) data_in = ~data_in;
+
+\t\tswitch (RadioState) {
+\t\t\tcase (0 /*TX_STATE*/) {
+\t\t\t\tSPI.writeByte(NextTxByte);
+\t\t\t\tTxByteCnt++;
+\t\t\t\tswitch (RadioTxState) {
+\t\t\t\t\tcase (2 /*TXSTATE_PREAMBLE*/) {
+\t\t\t\t\t\tif (!(TxByteCnt < preamblelen)) {
+\t\t\t\t\t\t\tNextTxByte = SYNC_BYTE;
+\t\t\t\t\t\t\tRadioTxState = 3 /*TXSTATE_SYNC*/;
+\t\t\t\t\t\t}
+\t\t\t\t\t}
+\t\t\t\t\tcase (3 /*TXSTATE_SYNC*/) {
+\t\t\t\t\t\tNextTxByte = NSYNC_BYTE;
+\t\t\t\t\t\tRadioTxState = 4 /*TXSTATE_DATA*/;
+\t\t\t\t\t\tTxByteCnt = -1;
+\t\t\t\t\t}
+\t\t\t\t\tcase (4 /*TXSTATE_DATA*/) {
+\t\t\t\t\t\tif ((TxByteCnt) < txlength::int) {
+\t\t\t\t\t\t\tNextTxByte = txbufptr.getByte(TxByteCnt);
+\t\t\t\t\t\t\tusRunningCRC = checksum.crcByte(usRunningCRC,NextTxByte);
+\t\t\t\t\t\t} else {
+\t\t\t\t\t\t\tNextTxByte = (usRunningCRC)::8;
+\t\t\t\t\t\t\tRadioTxState =\t5 /*TXSTATE_CRC*/;
+\t\t\t\t\t\t}
+\t\t\t\t\t}
+\t\t\t\t\tcase (5 /*TXSTATE_CRC*/) {
+\t\t\t\t\t\tNextTxByte = (usRunningCRC >> 8)::8;
+\t\t\t\t\t\tRadioTxState = TXSTATE_FLUSH;
+\t\t\t\t\t\tTxByteCnt = 0;
+\t\t\t\t\t}
+\t\t\t\t\tcase (6 /*TXSTATE_FLUSH*/) {
+\t\t\t\t\t\tif (TxByteCnt > 3) {
+\t\t\t\t\t\t\tif ((bAckEnable) and (txbufptr.addr != TOS_BCAST_ADDR)) {
+\t\t\t\t\t\t\t\tTxByteCnt = 0;
+\t\t\t\t\t\t\t\tRadioTxState = TXSTATE_WAIT_FOR_ACK;
+\t\t\t\t\t\t\t} else {
+\t\t\t\t\t\t\t\tRadioTxState = TXSTATE_DONE;
+\t\t\t\t\t\t\t}
+\t\t\t\t\t\t}
+\t\t\t\t\t}
+\t\t\t\t\tcase (7 /*TXSTATE_WAIT_FOR_ACK*/) {
+\t\t\t\t\t\tif (TxByteCnt == 1) {
+\t\t\t\t\t\t\tSPI.rxMode();
+\t\t\t\t\t\t\tCC1000Control.RxMode();
+\t\t\t\t\t\t}
+\t\t\t\t\t\tif (TxByteCnt > 3) {
+\t\t\t\t\t\t\tRadioTxState = TXSTATE_READ_ACK;
+\t\t\t\t\t\t\tTxByteCnt = 0;
+\t\t\t\t\t\t\tsearch_word = 0x0000;
+\t\t\t\t\t\t}
+\t\t\t\t\t}
+\t\t\t\t\tcase (8 /*TXSTATE_READ_ACK*/) {
+\t\t\t\t\t\tlocal i: int;
+\t\t\t\t\t\tfor (i = 0; i < 8; i++) {
+\t\t\t\t\t\t\tsearch_word <<= 1;
+\t\t\t\t\t\t\tif (data_in[7] == 0b1) search_word |= 0x01;
+\t\t\t\t\t\t\tdata_in <<= 1;
+\t\t\t\t\t\t\tif (search_word == 0xba83) {
+\t\t\t\t\t\t\t\ttxbufptr.ack = 0x01;
+\t\t\t\t\t\t\t\tRadioTxState = TXSTATE_DONE;
+\t\t\t\t\t\t\t\treturn;
+\t\t\t\t\t\t\t}
+\t\t\t\t\t\t}
+\t\t\t\t\t}
+\t\t\t\t}
+\t\t\t\tif (TxByteCnt == MAX_ACK_WAIT) {
+\t\t\t\t\ttxbufptr.ack = 0x00;
+\t\t\t\t\tRadioTxState = TXSTATE_DONE;
+\t\t\t\t}
+\t\t\t}
+\t\t\tcase (9 /*TXSTATE_DONE*/) {
+\t\t\t\tbTxPending = false;
+\t\t\t\tPacketSent();
+\t\t\t\tSPI.rxMode();
+\t\t\t\tCC1000Control.RxMode();
+\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\tRSSIInitState = RadioState;
+\t\t\t\tADC.startConv(0, true);
+\t\t\t}
+\t\t\tdefault {
+\t\t\t\tbTxPending = false;
+\t\t\t\tPacketSent();
+\t\t\t\t// If the post operation succeeds, goto Idle
+\t\t\t\t// otherwise, we\'ll try again.
+\t\t\t\tSPI.rxMode();
+\t\t\t\tCC1000Control.RxMode();
+\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\tRSSIInitState = RadioState;
+\t\t\t\t// ADC.getData();
+\t\t\t\tADC.startConv(0, true);
+\t\t\t}
+\t\t\tcase (1 /*DISABLED_STATE*/) {
+\t\t\t\t// do nothing.
+\t\t\t}
+\t\t\tcase (2 /*IDLE_STATE*/ ) { 
+\t\t\t\tif (((data_in == (0xaa)) or (data_in == (0x55)))) {
+\t\t\t\t\tPreambleCount++;
+\t\t\t\t\tif (PreambleCount > CC1K_ValidPrecursor) {
+\t\t\t\t\t\tPreambleCount = SOFCount = 0;
+\t\t\t\t\t\tRxBitOffset = RxByteCnt = 0;
+\t\t\t\t\t\tusRunningCRC = 0x0000;
+\t\t\t\t\t\trxlength = (36 /*MSG_DATA_SIZE*/-2);
+\t\t\t\t\t\tRadioState = SYNC_STATE;
+\t\t\t\t\t}
+\t\t\t\t} else if (bTxPending ) {
+\t\t\t\t\tRadioState = 3 /*PRETX_STATE*/;
+\t\t\t\t\tRSSIInitState = 3 /*PRETX_STATE*/;
+\t\t\t\t\tiRSSIcount = 0;
+\t\t\t\t\tPreambleCount = 0;
+\t\t\t\t\t// ADC.getData();
+\t\t\t\t\tADC.startConv(0, true);
+\t\t\t\t}
+\t\t\t}
+\t\t\tcase (3 /*PRETX_STATE*/) {
+\t\t\t\tif (((data_in == (0xaa)) or (data_in == (0x55)))) {
+\t\t\t\t\t// Back to the penalty box.
+\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\t}\t\t
+\t\t\t}
+\t\t\tcase (4 /*SYNC_STATE*/) {
+\t\t\t\t// draw in the preamble bytes and look for a sync byte
+\t\t\t\t// save the data in a 16 with last byte received as msbyte
+\t\t\t\t// and current byte received as the lsbyte.
+\t\t\t\t// use a bit shift compare to find the byte boundary for the sync byte
+\t\t\t\t// retain the shift value and use it to collect all of the packet data
+\t\t\t\t// check for data inversion, and restore proper polarity 
+\t\t\t\t// XXX-PB: Don\'t do this.
+\t\t\t\tlocal i: int;
+
+\t\t\t\tif ((data_in == 0xaa) or (data_in == 0x55)) {
+\t\t\t\t\t// It is actually possible to have the LAST BIT of the incoming
+\t\t\t\t\t// data be part of the Sync Byte.\tSO, we need to store that
+\t\t\t\t\t// However, the next byte should definitely not have this pattern.
+\t\t\t\t\t// XXX-PB: Do we need to check for excessive preamble?
+\t\t\t\t\t// RxShiftBuf.MSB = data_in;
+\t\t\t\t\tRxShiftBuf = RxShiftBuf & 0x00ff;
+\t\t\t\t\tRxShiftBuf = RxShiftBuf | ((data_in::16) << 8);
+\t\t\t\t} else {
+\t\t\t\t\t// TODO: Modify to be tolerant of bad bits in the preamble...
+\t\t\t\t\tlocal usTmp: 16;
+\t\t\t\t\tswitch (SOFCount) {
+\t\t\t\t\t\tcase (0) {
+\t\t\t\t\t\t\t// RxShiftBuf.LSB = data_in;
+\t\t\t\t\t\t\tRxShiftBuf = RxShiftBuf & (0xff00::16);
+\t\t\t\t\t\t\tRxShiftBuf = RxShiftBuf |((data_in::16)&(0x00ff::16));
+\t\t\t\t\t\t}
+\t\t\t\t\t\tcase (1) {
+\t\t\t\t\t\t\t// bit shift the data in with previous sample to find sync
+\t\t\t\t\t\t\tusTmp = RxShiftBuf;
+\t\t\t\t\t\t\tRxShiftBuf <<= 8;
+\t\t\t\t\t\t\tRxShiftBuf |= (data_in::16) & (0x00ff::16);
+\t\t\t\t\t\t\tfor (i = 0; i < 8; i++) {
+\t\t\t\t\t\t\t\tusTmp <<= 1;
+\t\t\t\t\t\t\t\tif (data_in[7] == 0b1) usTmp |= 0x01;
+\t\t\t\t\t\t\t\tdata_in <<= 1;
+\t\t\t\t\t\t\t\t// check for sync bytes
+\t\t\t\t\t\t\t\tif (usTmp == SYNC_WORD) {
+\t\t\t\t\t\t\t\t\tif (rxbufptr.length != 0) {
+\t\t\t\t\t\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\t\t\t\t\t\t} else {
+\t\t\t\t\t\t\t\t\t\tRadioState = RX_STATE;
+\t\t\t\t\t\t\t\t\t\tRSSIInitState = RX_STATE;
+\t\t\t\t\t\t\t\t\t\tADC.startConv(0, true);
+\t\t\t\t\t\t\t\t\t\tRxBitOffset = 7 - i;
+\t\t\t\t\t\t\t\t\t}
+\t\t\t\t\t\t\t\t\tbreak;
+\t\t\t\t\t\t\t\t}
+\t\t\t\t\t\t\t}
+\t\t\t\t\t\t}
+\t\t\t\t\t\tcase (2) { 
+\t\t\t\t\t\t\t// bit shift the data in with previous sample to find sync
+\t\t\t\t\t\t\tusTmp = RxShiftBuf;
+\t\t\t\t\t\t\tRxShiftBuf <<= 8;
+\t\t\t\t\t\t\tRxShiftBuf |= (data_in::16) & (0x00ff::16);
+\t\t\t\t\t\t\tfor (i = 0; i < 8; i++) {
+\t\t\t\t\t\t\t\tusTmp <<= 1;
+\t\t\t\t\t\t\t\tif (data_in[7] == 0b1) usTmp |= 0x01;
+\t\t\t\t\t\t\t\tdata_in <<= 1;
+\t\t\t\t\t\t\t\t// check for sync bytes
+\t\t\t\t\t\t\t\tif (usTmp == SYNC_WORD) {
+\t\t\t\t\t\t\t\t\tif (rxbufptr.length !=0) {
+\t\t\t\t\t\t\t\t\t\t// Leds.redToggle();
+\t\t\t\t\t\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\t\t\t\t\t\t} else {
+\t\t\t\t\t\t\t\t\t\tRadioState = RX_STATE;
+\t\t\t\t\t\t\t\t\t\tRSSIInitState = RX_STATE;
+\t\t\t\t\t\t\t\t\t\t// ADC.getData();
+\t\t\t\t\t\t\t\t\t\tADC.startConv(0, true);
+\t\t\t\t\t\t\t\t\t\tRxBitOffset = 7 - i;
+\t\t\t\t\t\t\t\t\t}
+\t\t\t\t\t\t\t\t\tbreak;
+\t\t\t\t\t\t\t\t}
+\t\t\t\t\t\t\t}
+\t\t\t\t\t\t}
+\t\t\t\t\t\tdefault {
+\t\t\t\t\t\t\t// We didn\'t find it after a reasonable number of tries, so....
+\t\t\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/;\t// Ensures we wait till the end of the transmission
+\t\t\t\t\t\t}
+\t\t\t\t\t}
+\t\t\t\t\tSOFCount++;
+\t\t\t\t}
+\t\t\t}
+\t\t\tcase (5/*RX_STATE*/) {
+\t\t\t\t// collect the data and shift into double buffer
+\t\t\t\t// shift out data by correct offset
+\t\t\t\t// invert the data if necessary
+\t\t\t\t// stop after the correct packet length is read
+\t\t\t\t// return notification to upper levels
+\t\t\t\t// go back to idle state
+\t\t\t\tlocal Byte: 8;
+
+\t\t\t\tRxShiftBuf <<= 8;
+\t\t\t\tRxShiftBuf |= data_in;
+
+\t\t\t\tByte = ((RxShiftBuf >> RxBitOffset) & 0x00ff)::8;
+
+\t\t\t\trxbufptr.setByte(RxByteCnt, Byte);
+\t\t\t\tRxByteCnt++;
+
+\t\t\t\tif (RxByteCnt < rxlength) {
+\t\t\t\t\tusRunningCRC = checksum.crcByte(usRunningCRC,Byte);
+\t\t\t\t\tif (RxByteCnt == 5) {
+\t\t\t\t\t\trxlength = (rxbufptr.length)::int;
+\t\t\t\t\t\tif (rxlength > 29 /*TOSH_DATA_LENGTH*/) {
+\t\t\t\t\t\t\t// The packet\'s screwed up, so just dump it
+\t\t\t\t\t\t\trxbufptr.length = 0x00;
+\t\t\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/;\t// Waits till end of transmission
+\t\t\t\t\t\t\treturn;
+\t\t\t\t\t\t}
+\t\t\t\t\t\t// Add in the header size
+\t\t\t\t\t\trxlength += 5;
+\t\t\t\t\t\tif (rxbufptr.length == 0) {
+\t\t\t\t\t\t\tRxByteCnt = 5 + 29;
+\t\t\t\t\t\t}
+\t\t\t\t\t}
+\t\t\t\t} else if (RxByteCnt == rxlength) {
+\t\t\t\t\t// usRunningCRC = crcByte(usRunningCRC,Byte);
+\t\t\t\t\tusRunningCRC = checksum.crcByte(usRunningCRC,Byte);
+\t\t\t\t\t// Shift index ahead to the crc field.
+\t\t\t\t\tRxByteCnt = 5 + 29;
+\t\t\t\t} else if (RxByteCnt >= 36 /*MSG_DATA_SIZE*/) { 
+\t\t\t\t\t// Packet filtering based on bad CRC\'s is done at higher layers.
+\t\t\t\t\t// So sayeth the TOS weenies.
+\t\t\t\t\tif (rxbufptr.crc == usRunningCRC) {
+\t\t\t\t\t\trxbufptr.crc = 0x0001;
+\t\t\t\t\t\tif (bAckEnable) {
+\t\t\t\t\t\t\tif (rxbufptr.addr == TOS_LOCAL_ADDRESS) {
+\t\t\t\t\t\t\t\tRadioState = SENDING_ACK; 
+\t\t\t\t\t\t\t\tCC1000Control.TxMode();
+\t\t\t\t\t\t\t\tSPI.txMode();
+\t\t\t\t\t\t\t\tSPI.writeByte(0xaa);
+\t\t\t\t\t\t\t\tRxByteCnt = 0;
+\t\t\t\t\t\t\t\treturn; 
+\t\t\t\t\t\t\t}
+\t\t\t\t\t\t}
+\t\t\t\t\t}
+\t\t\t\t} else {
+\t\t\t\t\trxbufptr.crc = 0::16;
+\t\t\t\t}
+
+\t\t\t\tSPI.disableIntr();
+\t
+\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\trxbufptr.strength = usRSSIVal::16;
+\t\t\t\tif (!(PacketRcvd())) {
+\t\t\t\t\t// If there are insufficient resources to process the incoming packet
+\t\t\t\t\t// we drop it
+\t\t\t\t\trxbufptr.length = 0x00;
+\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\t\tSPI.enableIntr();
+\t\t\t\t}
+\t\t\t}
+\t\t\tcase (6 /*SENDING_ACK*/) {
+\t\t\t\tRxByteCnt++;
+\t\t\t\tif (RxByteCnt >= ACK_LENGTH) { 
+\t\t\t\t\tCC1000Control.RxMode();
+\t\t\t\t\tSPI.rxMode();
+\t\t\t\t\tSPI.disableIntr();
+\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/; //DISABLED_STATE;
+\t\t\t\t\trxbufptr.strength = usRSSIVal::16;
+\t\t\t\t\tif (!PacketRcvd()) {
+\t\t\t\t\t\trxbufptr.length = 0x00;
+\t\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\t\t\tSPI.enableIntr();
+\t\t\t\t\t}
+\t\t\t\t} else if (RxByteCnt >= ACK_LENGTH - 3 /* sizeof(ack_code)*/ - 2) {
+\t\t\t\t\tSPI.writeByte(ack_code[RxByteCnt + 3/* sizeof(ack_code)*/ + 2- ACK_LENGTH]);
+\t\t\t\t}
+\t\t\t}
+\t\t}
+\t}
+
+\tmethod ADCdataReady(data_in: 10) {
+\t\tlocal currentRadioState: int;
+\t\tlocal initRSSIState: int;
+\t\tlocal data: int;
+
+\t\tlocal mask: 8;
+\t\tmask = MCU.disable();
+
+\t\tdata = ((data_in::8) & 0x7f)::int;
+\t\tdata += ((data_in >> 7))::int * 128;
+
+\t\tcurrentRadioState = RadioState; 
+\t\tinitRSSIState = RSSIInitState;
+\t\tMCU.restore(mask);
+\t\t// find the maximum RSSI value over CC1K_MAX_RSSI_SAMPLES
+\t\tswitch (currentRadioState) {
+\t\t\tcase (2 /*IDLE_STATE*/ ) {
+\t\t\t\tif (initRSSIState == 2 /*IDLE_STATE*/ ) {
+\t\t\t\t\tmask = MCU.disable();
+\t\t\t\t\tusTempSquelch = data;
+\t\t\t\t\tMCU.restore(mask);
+\t\t\t\t\tadjustSquelch();
+\t\t\t\t}
+\t\t\t\tmask = MCU.disable();
+\t\t\t\tRSSIInitState = NULL_STATE;
+\t\t\t\tMCU.restore(mask);
+\t\t\t}
+\t\t\tcase (5 /*RX_STATE*/) {
+\t\t\t\tif (initRSSIState == RX_STATE) {
+\t\t\t\t\tmask = MCU.disable();
+\t\t\t\t\tusRSSIVal = data;
+\t\t\t\t\tMCU.restore(mask);
+\t\t\t\t}
+\t\t\t\tmask = MCU.disable();
+\t\t\t\tRSSIInitState = NULL_STATE;
+\t\t\t\tMCU.restore(mask);
+\t\t\t}
+\t\t\tcase (3 /*PRETX_STATE*/) {
+\t\t\t\tlocal data2: int;
+\t\t\t\tiRSSIcount++;
+\t\t\t\tdata2 = (usSquelchVal + CC1K_SquelchBuffer + 1);
+\t
+\t\t\t\t// if the channel is clear, GO GO GO!
+\t\t\t\tif ((data2 > (usSquelchVal + CC1K_SquelchBuffer)) and (initRSSIState == 3 /*PRETX_STATE*/)) { 
+\t\t\t\t\tSPI.writeByte(0xaa);
+\t\t\t\t\tCC1000Control.TxMode();
+\t\t\t\t\tSPI.txMode();
+\t\t\t\t\tmask = MCU.disable();
+\t\t\t\t\tusRSSIVal = data2;
+\t\t\t\t\tiRSSIcount = CC1K_MaxRSSISamples;
+\t\t\t\t\tTxByteCnt = 0;
+\t\t\t\t\tusRunningCRC = 0::16;
+\t\t\t\t\tRadioState = 0 /*TX_STATE*/;
+\t\t\t\t\tRadioTxState = 2 /*TXSTATE_PREAMBLE*/;
+\t\t\t\t\tNextTxByte = 0xaa;
+\t\t\t\t\tRSSIInitState = NULL_STATE;
+\t\t\t\t\tMCU.restore(mask);
+\t\t\t\t\t// Mica2.yellow.toggle();
+\t\t\t\t\treturn;
+\t\t\t\t}
+
+\t\t\t\tmask = MCU.disable();
+\t\t\t\tRSSIInitState = NULL_STATE;
+\t\t\t\tMCU.restore(mask);
+\t\t\t\tif (iRSSIcount == CC1K_MaxRSSISamples) {
+\t\t\t\t\tmask = MCU.disable();
+\t\t\t\t\tRadioState = 2 /*IDLE_STATE*/;
+\t\t\t\t\tMCU.restore(mask);
+\t\t\t\t} else {
+\t\t\t\t\tmask = MCU.disable();
+\t\t\t\t\tRSSIInitState = currentRadioState;
+\t\t\t\t\tMCU.restore(mask);
+\t\t\t\t\t// ADC.getData();
+\t\t\t\t\tADC.startConv(0, true);
+\t\t\t\t}
+\t\t\t}
+\t\t}
+\t}
+
+\tmethod GetSquelch(): 16 {
+\t\treturn usSquelchVal::16;
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: PASS
+
+class field_res08 {
+    field testf: int;
+    
+    method testm() {
+        testf = 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 1
+
+class instof06_a {
+}
+
+class instof06_b extends instof06_a {
+}
+
+class instof06_c extends instof06_b {
+}
+
+component instof06 {
+    field foo: instof06_a = new instof06_c();
+
+    method main(arg: int): int {
+\treturn foo instanceof instof06_b ? 1 : 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: CannotOverrideReturnType @ 9:7
+
+class inh7_a {
+    
+    method testm();
+}
+class inh7_b extends inh7_a {
+    
+    method testm(): int;
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class constr02 {
+    constructor() { }
+}
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class pv05_a {
+    method getf(): int { return val; }
+    private field val: int = 1;
+}
+
+class pv05_b extends pv05_a {
+    private field val: bool = true;
+}
+
+class pv05_c extends pv05_a {
+    private field val: char = '3';
+}
+
+component pv05 {
+    field av: int = new pv05_a().getf();
+    field bv: int = new pv05_b().getf();
+    field cv: int = new pv05_c().getf();
+}
+
+/* 
+heap {
+    record #0:3:pv05 {
+        field av: int = int:1;
+        field bv: int = int:1;
+        field cv: int = int:1;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: promotions of char->int
+// @Result: PASS
+
+component int_char03 {
+    field a: bool = (48 == '0');
+    field b: bool = (10 == '\
+');
+    field c: bool = (247 == '\\367');
+}
+
+/* 
+heap {
+    record #0:3:int_char03 {
+        field a: bool = bool:true;
+        field b: bool = bool:true;
+        field c: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-init
+// @Test: virtual method invocations
+// @Result: PASS
+
+class dg10_a {
+    method val(): int { return 1; }
+}
+
+class dg10_b extends dg10_a {
+    method val(): int { return 2; }
+}
+
+component dg10 {
+    field a: function():int = new dg10_a().val;
+    field b: function():int = new dg10_b().val;
+    field c: function():int = bar;
+    field d: function():int;
+    field av: int = val(a);
+    field bv: int = val(b);
+    field cv: int = val(c);
+    field dv: int = val(d);
+
+    method val(f: function(): int): int {
+\tif ( f == a ) return 11;
+\tif ( f == b ) return 21;
+\tif ( f == c ) return 31;
+\tif ( f == null ) return 42;
+\treturn 77;
+    }
+    method bar(): int {
+\treturn 3;
+    }
+
+}
+
+/* 
+heap {
+    record #0:8:dg10 {
+        field a: function():int = [#1:dg10_a,dg10_a:val()];
+        field b: function():int = [#2:dg10_b,dg10_b:val()];
+        field c: function():int = [#0:dg10,dg10:bar()];
+        field d: function():int = #null;
+        field av: int = int:11;
+        field bv: int = int:21;
+        field cv: int = int:31;
+        field dv: int = int:42;
+    }
+    record #1:0:dg10_a {
+    }
+    record #2:0:dg10_b {
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=2, 3=0, 4=12, 5=12, 6=0
+
+component order14 {
+    field order: int[] = { 0, 0, 0 };
+    field pos: int = 0;
+
+    field data: int[] = { 7 };
+
+    method first(): int[] {
+        order[pos] = 1;
+        pos++;
+        return data;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method third(a: int): int {
+        order[pos] = 3;
+        pos++;
+        return a;
+    }
+
+    method main(arg: int): int {
+        local result = first()[second(0)] = 12;
+\tif ( arg == 1 ) return order[0];
+\tif ( arg == 2 ) return order[1];
+\tif ( arg == 3 ) return order[2];
+\tif ( arg == 4 ) return result;
+\tif ( arg == 5 ) return data[0];
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: statements
+// @Result: NotAStatement @ 6:5
+
+class stmt07 {
+    
+    method testm() {
+        true ? 1:0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeQuery (instanceof) operation
+// @Result: PASS
+
+class instof01b {
+    field bar: instof01b;
+    field foo: bool = bar <: instof01b;
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking > raw types, >> operator
+// @Result: TypeMismatch @ 8:16
+
+class raw_shr02 {
+    field a: 6;
+    field b: 7;
+    field c: 6 = a >> b;
+}
+"
+"// @Harness: v2-init
+// @Test: array index exceptions
+// @Result: BoundsCheckException @ 7:25
+
+component index01 {
+    field foo: int[] = new int[0];
+    field bar: int = foo[0];
+}
+"
+"// @Harness: v2-exec
+// @Test: array rtex_index exceptions
+// @Result: 0=42, 1=BoundsCheckException, 2=13, 3=14, 4=BoundsCheckException, 5=42
+
+component rtex_index03 {
+    field foo: int[] = { 13, 14 };
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return foo[-1];
+\tif ( arg == 2 ) return foo[0];
+\tif ( arg == 3 ) return foo[1];
+\tif ( arg == 4 ) return foo[2];
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: null exceptions
+// @Result: NullCheckException @ 7:25
+
+class null13_obj {
+    field foo: int[];
+    field bar: int = bang();
+    method bang(): int {
+        return foo[0];
+    }
+}
+
+component null13 {
+    field baz: null13_obj = new null13_obj();
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class inh_method02_a<X> extends inh_method02_b<int> {
+  field g: int = f();
+}
+
+class inh_method02_b<X> {
+  method f(): X;
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: BuiltinRedefined @ 5:7
+
+class void {
+    field foo : int;
+}
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 0=1
+
+class instof04_a {
+}
+
+class instof04_b extends instof04_a {
+}
+
+component instof04 {
+    field foo: instof04_a = new instof04_b();
+
+    method main(arg: int): int {
+\treturn foo instanceof instof04_b ? 1 : 0;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 5:12
+
+class field07 {
+    field f: type<T>
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class prepost13_obj {
+    field foo: int = 1;
+    field bar: int = inc();
+    method inc(): int {
+\tlocal i = foo;
+        foo = i++;
+        return i;
+    }
+}
+
+component prepost13 {
+    field foo: prepost13_obj = new prepost13_obj();
+}
+
+/* 
+heap {
+    record #0:1:prepost13 {
+        field foo: prepost13_obj = #1:prepost13_obj;
+    }
+    record #1:2:prepost13_obj {
+        field foo: int = int:1;
+        field bar: int = int:2;
+    }
+}*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class type22 {
+    field f: 1[][];
+    field g: 2[][];
+    field h: 3[][];
+    field i: 4[][];
+    field j: 16[][];
+    field k: 32[][];
+    field l: 64[][];
+}
+"
+"// @Harness: v2-exec
+// @Result: 0=0, 1=0, 2=0, 3=0, 4=1, 5=0, 6=0, 7=0
+
+class A<X> { } 
+class B<X> extends A<int> { }
+
+component ptex_instof06 {
+
+   field a: A<int> = new A<int>();
+   field b: A<int> = new B<int>();
+   field c: A<int> = new B<char>();
+   field d: A<int> = new B<bool>();
+   field e: A<int> = new B<function()>();
+
+   method m(x: A<int>): bool {
+      return x <: (B<char>);
+   }
+
+   method main(arg: int): bool {
+       if ( arg == 1 ) return m(null);
+       if ( arg == 2 ) return m(a);
+       if ( arg == 3 ) return m(b);
+       if ( arg == 4 ) return m(c);
+       if ( arg == 5 ) return m(d);
+       if ( arg == 6 ) return m(e);
+       return false;  
+   }
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=21, 3=31, 4=42, 5=11, 6=21, 7=31, 8=42
+
+class delegate13_a {
+    method val(): int { return 11; }
+}
+
+class delegate13_b extends delegate13_a {
+    method val(): int { return 21; }
+}
+
+class delegate13_c extends delegate13_a {
+    method val(): int { return 31; }
+}
+
+component delegate13 {
+    field a: delegate13_a = new delegate13_a();
+    field b: delegate13_a = new delegate13_b();
+    field c: delegate13_a = new delegate13_c();
+    field am: function():int = a.val;
+    field bm: function():int;
+    field cm: function():int = c.val;
+
+    method main(arg: int): int {
+        local m = m42;
+\tif ( arg == 1 ) m = am;
+\tif ( arg == 2 ) m = null;
+\tif ( arg == 3 ) m = cm;
+
+\tif ( arg == 5 ) m = a.val;
+\tif ( arg == 6 ) m = b.val;
+\tif ( arg == 7 ) m = c.val;
+
+\treturn exec(m);
+    }
+
+    method exec(f: function(): int): int {
+\tif ( f == am ) return 11;
+\tif ( f == bm ) return 21;
+\tif ( f == cm ) return 31;
+\tif ( f == null ) return 42;
+\treturn f();
+    }
+
+    method m42(): int {
+\treturn 42;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_array07 {
+    method test() {
+\tset0(0, null);
+    }
+    method set0<X>(b: X, a: X[]) {
+\ta[0] = b;\t
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 8:28
+
+class unreach14 {
+    
+    method testm(): int {
+        while ( true ) {
+            if ( true ) {
+                continue;
+            }
+            else {
+                continue;
+                {
+                    {
+                        local foo: int = 0;
+                    }
+                    local doo: int = 0;
+                }
+            }
+        }
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: duplicated method names
+// @Result: MemberRedefined @ 6:7 
+
+class method1 {
+    
+    method testm();
+    
+    method testm(): int;
+}
+"
+"// @Harness: v2-init
+// @Test: pre/post increment operations
+// @Result: PASS
+
+class cmpassn09_obj {
+    field foo: 16 = 0x6;
+    field bar: 16 = foo &= 0x5;
+}
+
+component cmpassn09 {
+    field foo: cmpassn09_obj = new cmpassn09_obj();
+}
+
+/* 
+heap {
+    record #0:1:cmpassn09 {
+        field foo: cmpassn09_obj = #1:cmpassn09_obj;
+    }
+    record #1:2:cmpassn09_obj {
+        field foo: int = raw.16:0x4;
+\tfield bar: int = raw.16:0x4;
+    }
+}*/
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class array2 {
+  method f(a: type[]);
+  method g(a: type[][]);
+  method h(a: type[][][]);
+  method i(a: type[], b: type[]);
+}
+"
+"// @Harness: v2-exec
+// @Test: null exceptions
+// @Result: 0=42, 1=NullCheckException, 2=13, 3=NullCheckException, 4=NullCheckException, 5=42
+
+class rtex_null04_obj {
+    field baz: int = 13;
+}
+
+component rtex_null04 {
+    field a: rtex_null04_obj;
+    field b: rtex_null04_obj = new rtex_null04_obj();
+    field c: rtex_null04_obj = null;
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return getf(a);
+\tif ( arg == 2 ) return getf(b);
+\tif ( arg == 3 ) return getf(c);
+\tif ( arg == 4 ) return getf(null);
+\treturn 42;
+    }
+
+    method getf(a: rtex_null04_obj): int {
+\treturn a.baz;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: if statements and ternary expressions
+// @Result: PASS
+
+component while03 {
+    
+    field res_01: int = count(1);
+    field res_02: int = count(2);
+    field res_03: int = count(3);
+    field res_04: int = count(10);
+    field res_05: int = count(100);
+    field res_06: int = count(200);
+
+    method count(max: int): int {
+\tlocal i = 1, cumul = 0;
+        while ( true ) {
+\t    cumul += i;
+\t    if ( i == max ) break;
+\t    i++;
+\t}
+        return cumul;
+    }
+}
+
+/* 
+heap {
+    record #0:6:while03 {
+        field res_01: int = int:1;
+        field res_02: int = int:3;
+        field res_03: int = int:6;
+        field res_04: int = int:55;
+        field res_05: int = int:5050;
+        field res_06: int = int:20100;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class List<X> {
+    method add(x: X) {
+    }
+}
+
+component mp_list04 {
+    method test() {
+\tlocal x = makeList(0, 0);
+    }
+    method makeList<X>(a: X, b: X): List<X> {
+\treturn new List<X>();
+    }
+}
+"
+"// @Harness: v2-seman
+// @Result: TypeParamArityMismatch @ 9:14
+
+class num_params04_a {
+}
+
+component num_params04_b {
+  method m(o: num_params04_a<int, bool>) {
+  }
+}
+"
+"// @Harness: v2-exec
+// @Test: arithmetic operators
+// @Result: 0=0, 1=1, 2=1, 3=1, 4=1, 5=1, 6=1, 7=1, 8=1, 9=1, 10=0
+
+component raw_shl01 {
+    field res_01: 32 = op(0x0f, 1);
+    field res_02: 32 = op(2, 2);
+    field res_03: 32 = op(1, 31);
+    field res_04: 32 = op(0, 8);
+    field res_05: 32 = op(0xf0, 16);
+    field res_06: 32 = op(65535, 2);
+    field res_07: 32 = op(0x10000, 16);
+    field res_08: 32 = op(255, 5);
+    field res_09: 32 = op(0xaa, 0);
+
+    method op(a: 32, b: int): 32 {
+\treturn a << b;
+    }
+
+    method main(arg: int): bool {
+\tif ( arg == 1 )  return op(0xf, 1)      == res_01;
+\tif ( arg == 2 )  return op(2, 2)        == res_02;
+\tif ( arg == 3 )  return op(1, 31)       == res_03;
+\tif ( arg == 4 )  return op(0, 8)        == res_04;
+\tif ( arg == 5 )  return op(0xf0, 16)    == res_05;
+\tif ( arg == 6 )  return op(65535, 2)    == res_06;
+\tif ( arg == 7 )  return op(0x10000, 16) == res_07;
+\tif ( arg == 8 )  return op(255, 5)      == res_08;
+\tif ( arg == 9 )  return op(0xaa, 0)     == res_09;
+\treturn false;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: operation of instanceof construct
+// @Result: 0=42, 1=42, 2=11, 3=42
+
+class cast01_obj {
+    field f: int = 11;
+}
+
+component cast01 {
+    field foo: cast01_obj;
+    field bar: cast01_obj = new cast01_obj();
+    
+    method main(arg: int): int {
+\tlocal o: cast01_obj = null;
+\tif ( arg == 1 ) o = (foo :: cast01_obj);
+\tif ( arg == 2 ) o = (bar :: cast01_obj);
+\treturn o == null ? 42 : o.f;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: TypeQuery (instanceof) operation
+// @Result: ExpectedObjectType @ 7:30
+
+class instof04b_01 {
+    field bar: instof04b_01;
+    field foo: bool = bar <: instof04b_02;
+}
+
+component instof04b_02 {
+}
+"
+"// @Harness: v2-parse
+// @Result: ParseError @ 4:22
+
+class class6 extends function {
+}
+"
+"// @Harness: v2-exec
+// @Test: field initialization
+// @Result: 0=42, 1=104, 2=101, 3=42
+
+component field06a {
+    field a: char = 'h';
+    field b: char = 'e';
+    method main(arg: int): char {
+\tif ( arg == 1 ) return a;
+\tif ( arg == 2 ) return b;
+\treturn '*';
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: duplicate parameter names
+// @Result: ParameterRedefined @ 5:34
+
+class param2 {
+    
+    method testm(a: int, b: int, a: char) {
+        a = 0;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class cast07b {
+   method m() {
+      local y = x :: (Type<function(), Y>);
+   }
+}
+"
+"// @Harness: v2-seman
+// @Test: field resolution
+// @Result: PASS
+
+class field_res03_a {
+    field testf: int;
+}
+class field_res03_b {
+    
+    method testm(arg: field_res03_a) {
+        arg.testf = 0;
+    }
+}
+"
+"/*
+ * The BubbleSort program implements the common but slow ""bubblesort""
+ * algorithm to measure runtime impact of various optimizations.
+ *
+ * @author Akop Palyan
+ */
+program BubbleSort {
+\tentrypoint main = BubbleSort.start;
+\tentrypoint usart0_rx = USART0.rec_handler;
+\tentrypoint usart0_tx = USART0.tran_handler;
+}
+
+component BubbleSort {
+\tfield array: int[] = new int[5];
+
+\tconstructor() {
+\t\tlocal i: int;
+
+\t\tfor (i = 0; i < array.length; i++) {
+\t\t\tarray[i] = array.length - i;
+\t\t}
+\t}
+
+\tmethod start() {
+\t\tMica2.startTerminal();
+\t\tbubblesort();
+\t\tprint();
+\t\tMCU.sleepForever();
+\t}
+
+\tmethod bubblesort() {
+\t\tlocal i: int;
+\t\tlocal j: int;
+\t\tlocal tmp: int;
+
+\t\tfor (i = 0; i < array.length - 1; i++) {
+\t\t\tfor (j = 0; j < array.length - 1; j++) {
+\t\t\t\tif (array[j] > array[j+1]) {
+\t\t\t\t\ttmp = array[j];
+\t\t\t\t\tarray[j] = array[j+1];
+\t\t\t\t\tarray[j+1] = tmp;
+\t\t\t\t}
+\t\t\t}
+\t\t}
+\t}
+
+\tmethod print() {
+\t\tlocal i: int;
+
+\t\tfor (i = 0; i < array.length; i++) {
+\t\t\tTerminal.printInt(array[i]);
+\t\t\tTerminal.nextLine();
+\t\t}
+\t}
+}
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+component mp_unify07 {
+    method test() {
+\tlocal x: int[] = id(null, new int[5]);
+\tlocal y: char[] = id(null, new char[5]);
+\tlocal z: 32[] = id(null, new 32[5]);
+\tlocal w: 8[] = id(null, new 8[5]);
+    }
+    method id<X>(x: X, y: X): X {
+\treturn x;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: arithmetic operators
+// @Result: PASS
+
+component order08 {
+    field order: int[] = { 0, 0 };
+    field pos: int = 0;
+
+    field res_01: int = first()(second(1));
+
+    method first(): function(int): int {
+        order[pos] = 1;
+        pos++;
+        return add;
+    }
+
+    method second(a: int): int {
+        order[pos] = 2;
+        pos++;
+        return a;
+    }
+
+    method add(a: int): int { return a + 2; }
+}
+
+/* 
+heap {
+    record #0:10:order08 {
+        field order: int[] = #1:int[2];
+        field pos: int = int:2;
+        field res_01: int = int:3;
+    }
+    record #1:2:int[2] {
+\tfield 0:int = int:1;
+\tfield 1:int = int:2;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @@Test: ""@Test variable initialization in compound assignment""
+// @Result: VariableNotInitialized @ 7:10
+
+class compound_init01 {
+
+    method testm() {
+        local cntr: int;
+        cntr += 2;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (post-increment operator)
+// @Result: VariableNotInitialized @ 8:15
+
+class init09 {
+    
+    method testm(): int {
+        local a: int;
+        return a;
+    }
+}
+"
+"// @Harness: v2-parse
+// @Result: PASS
+
+class meth05 {
+    method m(): int { return 0; }
+}
+"
+"// @Harness: v2-init
+// @Test: initialization interpreter > raw types > concat operator
+// @Result: PASS
+
+component raw_concat01 {
+    field f1: 8  = 0x0  # 0xf;
+    field f2: 16 = 0xf0 # 0x0f;
+    field f3: 32 = 0xf3f3  # 0x1111;
+    field f4: 14 = 0b1110101  # 0b1111111;
+    field f5: 10 = 0b10101  # 0b10000;
+    field f6: 6  = 0b101  # 0b100;
+    field f7: 32 = 0xFFFF  # 0xF000;
+    field f8: 48 = 0xF0  # 0x00F000F000;
+    field f9: 64 = 0xFFFF  # 0xF000F000F000;
+}
+
+/*
+heap {
+    record #0:1:raw_concat01 {
+\tfield f1: 8  = raw.8:0x0f; 
+\tfield f2: 16 = raw.16:0xf00f; 
+\tfield f3: 32 = raw.32:0xf3f31111; 
+\tfield f4: 14 = raw.14:0x3aff; 
+\tfield f5: 10 = raw.10:0x2b0; 
+\tfield f6: 6  = raw.6:0x2c; 
+\tfield f7: 32 = raw.32:0xfffff000; 
+\tfield f8: 48 = raw.48:0xf000f000f000; 
+\tfield f9: 64 = raw.64:0xfffff000f000f000; 
+    }
+}
+*/
+"
+"// @Harness: v2-init
+// @Test: field initialization
+// @Result: PASS
+
+component array03 {
+    field a_01: char[] =  {\'1\'};
+    field a_02: char[] =  {\'1\', \'2\'};
+    field a_03: char[] =  ""hi"";
+}
+
+/* 
+heap {
+    record #0:3:array03 {
+        field a_01: char[] = #1:char[1];
+        field a_02: char[] = #2:char[2];
+        field a_03: char[] = #3:char[2];
+    }
+    record #1:1:char[1] {
+        field 0:char = char:49;
+    }
+    record #2:2:char[2] {
+        field 0:char = char:49;
+        field 1:char = char:50;
+    }
+    record #3:2:char[2] {
+        field 0:char = char:104;
+        field 1:char = char:105;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Test: return correctness
+// @Result: NonVoidReturn @ 6:12
+
+class return2 {
+    
+    method testm() {
+        return 5;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: variable initialization (order of evaluation)
+// @Result: PASS
+
+class order_init10 {
+    
+    method testm() {
+        local foo: int;
+        local a: int[] = { foo = 0, foo };
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment operations
+// @Result: 0=0, 1=14, 2=14, 3=0
+
+component prepost03 {
+    field foo: int = 13;
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = ++foo;
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: global type resolution
+// @Result: UnresolvedType @ 10:17
+
+component type_res14a {
+    field g: int = type_res14b.f;
+}
+
+component type_res14b {
+    field f: function(unknown);
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; if branches
+// @Result: TypeMismatch @ 6:10
+
+class type17 {
+    
+    method testm() {
+        if ( 0 ) ;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: typechecking; char type
+// @Result: TypeMismatch @ 6:19
+
+class array_raw06 {
+    field a: 7[] = { 0xf, 0b00, 0xfe };
+}
+"
+"// @Harness: v2-seman
+// @Test: class inheritance
+// @Result: CannotOverrideArity @ 13:8
+
+class inh9_a {
+    
+    method testm() {
+    }
+}
+class inh9_b extends inh9_a {
+    
+    method testm() {
+        local foo: int = 0;
+    }
+}
+class inh9_c extends inh9_b {
+    
+    method testm(a: int) {
+        local foo: int = a;
+    }
+}
+"
+"// @Harness: v2-seman
+// @Test: unreachable code
+// @Result: UnreachableCode @ 10:7
+
+class unreach25 {
+    
+    method testm() {
+        do {
+            if ( true ) break;
+            else continue;
+            local foo: int = 2;
+        }
+        while ( false );
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: static method invocations
+// @Result: PASS
+
+component static03 {
+    field av: int = val1();
+    field bv: int = val2();
+    field cv: int = val3();
+
+    method val1(): int { return 1; }
+    method val2(): int { return val1()+1; }
+    method val3(): int { return val2()+1; }
+}
+
+/* 
+heap {
+    record #0:3:static03 {
+        field av: int = int:1;
+        field bv: int = int:2;
+        field cv: int = int:3;
+    }
+} */
+"
+"// @Harness: v2-exec
+// @Test: pre/post increment options
+// @Result: 0=0, 1=5, 2=6, 3=0
+
+component prepost02 {
+    field foo: int = 6;
+    field bar: int;
+
+    method main(arg: int): int {
+\tbar = foo--;
+\tif ( arg == 1 ) return foo;
+\tif ( arg == 2 ) return bar;
+\treturn 0;
+    }
+}
+"
+"// @Harness: v2-exec
+// @Test: static method invocations
+// @Result: 0=42, 1=2, 2=255, 3=0, 4=2, 5=42
+
+component ptex_find03 {
+
+    field iarr: int[] = { 1, 2, 3, 4, 5 };
+    field rarr: 5[] = { 0b00001, 0b10000, 0b01000, 0b00010, 0b00100 };
+
+    method main(arg: int): int {
+        local ieq: function(int, int): bool = equal;
+        local req: function(5, 5): bool = equal;
+
+\tif ( arg == 1 ) return find(iarr, 3, ieq);
+\tif ( arg == 2 ) return find(iarr, 6, ieq);
+        if ( arg == 3 ) return find(rarr, 0b00001, req);
+        if ( arg == 4 ) return find(rarr, 0b01000, req);
+        return 42;
+    }
+
+    method find<T>(arr: T[], val: T, eq: function(T, T): bool): int {
+        local i = 0;
+\tfor ( ; i < arr.length; i++ ) {
+            if ( eq(arr[i], val) ) return i;
+        }
+        return -1;
+    }
+
+    method equal<T>(x: T, y: T): bool {
+        return x == y;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: character comparison operators
+// @Result: PASS
+
+component comp12 {
+    field res_01: bool = op('a', 'b');
+    field res_02: bool = op('b', 'a');
+    field res_03: bool = op('\
+', '1');
+    field res_04: bool = op('\\377', '0');
+    field res_05: bool = op('\
+', '\
+');
+    field res_06: bool = op('\\377', '\\377');
+    field res_07: bool = op('a', 'A');
+    field res_08: bool = op('A', 'Z');
+    field res_09: bool = op('$', 'z');
+    field res_10: bool = op('z', '~');
+
+    method op(a: char, b: char): bool {
+\treturn a != b;
+    }
+}
+
+/* 
+heap {
+    record #0:10:comp12 {
+        field res_01: bool = bool:true;
+        field res_02: bool = bool:true;
+        field res_03: bool = bool:true;
+        field res_04: bool = bool:true;
+        field res_05: bool = bool:false;
+        field res_06: bool = bool:false;
+        field res_07: bool = bool:true;
+        field res_08: bool = bool:true;
+        field res_09: bool = bool:true;
+        field res_10: bool = bool:true;
+    }
+} */
+"
+"// @Harness: v2-seman
+// @Result: PASS
+
+class Transform<R, E> {
+    method visitA(n: A, e: E): R;
+    method visitB(n: B, e: E): R;
+}
+
+class S {
+    method accept<R, E>(v: Transform<R, E>, e: E): R;
+}
+
+class A extends S {
+    method accept<R, E>(v: Transform<R, E>, e: E): R { return v.visitA(this, e); }
+}
+
+class B extends S {
+    method accept<R, E>(v: Transform<R, E>, e: E): R { return v.visitB(this, e); }
+}
+
+class PriceList {
+}
+
+class Jewels {
+}
+
+class Thief extends Transform<Jewels, PriceList> {
+    method visitA(n: A, e: PriceList): Jewels {
+\treturn null;
+    }
+    method visitB(n: B, e: PriceList): Jewels {
+\treturn null;
+    }
+}
+"
+"// @Harness: v2-init
+// @Test: null exceptions
+// @Result: NullCheckException @ 11:24
+
+class null08_obj {
+    field baz: int;
+}
+
+component null08 {
+    field foo: null08_obj = null;
+    field bar: int = (foo.baz = 0);
+}
+"
+"// @Harness: v2-exec
+// @Test: virtual method invocations
+// @Result: 0=42, 1=11, 2=11, 3=11, 4=42
+
+class private09_a {
+    method getf(): int { return val; }
+    private field val: int = 11;
+}
+
+class private09_b extends private09_a {
+    field val: int = 21;
+}
+
+class private09_c extends private09_a {
+    field val: int = 31;
+}
+
+component private09 {
+    field a: private09_a = new private09_a();
+    field b: private09_a = new private09_b();
+    field c: private09_a = new private09_c();
+
+    method main(arg: int): int {
+\tif ( arg == 1 ) return a.getf();
+\tif ( arg == 2 ) return b.getf();
+\tif ( arg == 3 ) return c.getf();
+\treturn 42;
+    }
+}
+"
+"/*
+    `BF.v'
+    Balsa Verilog netlist file
+    Created: Thu Apr 22 18:40:25 BST 2010
+    By: dell@dell-laptop (Linux)
+    With net-verilog (balsa-netlist) version: 3.5.1
+    Using technology: example/four_b_rb
+    Command line : (balsa-netlist -v BF.breeze)
+*/
+
+module AND3 (
+  out,
+  in0,
+  in1,
+  in2
+);
+  output out;
+  input in0;
+  input in1;
+  input in2;
+endmodule
+
+module BALSA_FA (
+  nStart,
+  A,
+  B,
+  nCVi,
+  Ci,
+  nCVo,
+  Co,
+  sum
+);
+  input nStart;
+  input A;
+  input B;
+  input nCVi;
+  input Ci;
+  output nCVo;
+  output Co;
+  output sum;
+endmodule
+
+module BUFF (
+  Z,
+  A
+);
+  output Z;
+  input A;
+endmodule
+
+module INV (
+  out,
+  in
+);
+  output out;
+  input in;
+endmodule
+
+module NOR2 (
+  out,
+  in0,
+  in1
+);
+  output out;
+  input in0;
+  input in1;
+endmodule
+
+module NOR3 (
+  out,
+  in0,
+  in1,
+  in2
+);
+  output out;
+  input in0;
+  input in1;
+  input in2;
+endmodule
+
+module BrzBinaryFunc__Data_8_8_8_s3_Add_s5_False__m7m (
+  go_0r, go_0a,
+  out_0r, out_0a, out_0d,
+  inpA_0r, inpA_0a, inpA_0d,
+  inpB_0r, inpB_0a, inpB_0d
+);
+  input go_0r;
+  output go_0a;
+  input out_0r;
+  output out_0a;
+  output [7:0] out_0d;
+  output inpA_0r;
+  input inpA_0a;
+  input [7:0] inpA_0d;
+  output inpB_0r;
+  input inpB_0a;
+  input [7:0] inpB_0d;
+  wire [2:0] internal_0n;
+  wire start_0n;
+  wire nStart_0n;
+  wire [8:0] nCv_0n;
+  wire [8:0] c_0n;
+  wire [7:0] eq_0n;
+  wire [7:0] addOut_0n;
+  wire [7:0] w_0n;
+  wire [7:0] n_0n;
+  wire v_0n;
+  wire z_0n;
+  wire nz_0n;
+  wire nxv_0n;
+  wire done_0n;
+  supply0 gnd;
+  NOR3 I0 (internal_0n[0], nCv_0n[1], nCv_0n[2], nCv_0n[3]);
+  NOR3 I1 (internal_0n[1], nCv_0n[4], nCv_0n[5], nCv_0n[6]);
+  NOR2 I2 (internal_0n[2], nCv_0n[7], nCv_0n[8]);
+  AND3 I3 (done_0n, internal_0n[0], internal_0n[1], internal_0n[2]);
+  BUFF I4 (out_0d[0], addOut_0n[0]);
+  BUFF I5 (out_0d[1], addOut_0n[1]);
+  BUFF I6 (out_0d[2], addOut_0n[2]);
+  BUFF I7 (out_0d[3], addOut_0n[3]);
+  BUFF I8 (out_0d[4], addOut_0n[4]);
+  BUFF I9 (out_0d[5], addOut_0n[5]);
+  BUFF I10 (out_0d[6], addOut_0n[6]);
+  BUFF I11 (out_0d[7], addOut_0n[7]);
+  BALSA_FA I12 (nStart_0n, n_0n[0], w_0n[0], nCv_0n[0], c_0n[0], nCv_0n[1], c_0n[1], addOut_0n[0]);
+  BALSA_FA I13 (nStart_0n, n_0n[1], w_0n[1], nCv_0n[1], c_0n[1], nCv_0n[2], c_0n[2], addOut_0n[1]);
+  BALSA_FA I14 (nStart_0n, n_0n[2], w_0n[2], nCv_0n[2], c_0n[2], nCv_0n[3], c_0n[3], addOut_0n[2]);
+  BALSA_FA I15 (nStart_0n, n_0n[3], w_0n[3], nCv_0n[3], c_0n[3], nCv_0n[4], c_0n[4], addOut_0n[3]);
+  BALSA_FA I16 (nStart_0n, n_0n[4], w_0n[4], nCv_0n[4], c_0n[4], nCv_0n[5], c_0n[5], addOut_0n[4]);
+  BALSA_FA I17 (nStart_0n, n_0n[5], w_0n[5], nCv_0n[5], c_0n[5], nCv_0n[6], c_0n[6], addOut_0n[5]);
+  BALSA_FA I18 (nStart_0n, n_0n[6], w_0n[6], nCv_0n[6], c_0n[6], nCv_0n[7], c_0n[7], addOut_0n[6]);
+  BALSA_FA I19 (nStart_0n, n_0n[7], w_0n[7], nCv_0n[7], c_0n[7], nCv_0n[8], c_0n[8], addOut_0n[7]);
+  BUFF I20 (nCv_0n[0], nStart_0n);
+  BUFF I21 (c_0n[0], gnd);
+  INV I22 (nStart_0n, start_0n);
+  BUFF I23 (n_0n[0], inpB_0d[0]);
+  BUFF I24 (n_0n[1], inpB_0d[1]);
+  BUFF I25 (n_0n[2], inpB_0d[2]);
+  BUFF I26 (n_0n[3], inpB_0d[3]);
+  BUFF I27 (n_0n[4], inpB_0d[4]);
+  BUFF I28 (n_0n[5], inpB_0d[5]);
+  BUFF I29 (n_0n[6], inpB_0d[6]);
+  BUFF I30 (n_0n[7], inpB_0d[7]);
+  BUFF I31 (w_0n[0], inpA_0d[0]);
+  BUFF I32 (w_0n[1], inpA_0d[1]);
+  BUFF I33 (w_0n[2], inpA_0d[2]);
+  BUFF I34 (w_0n[3], inpA_0d[3]);
+  BUFF I35 (w_0n[4], inpA_0d[4]);
+  BUFF I36 (w_0n[5], inpA_0d[5]);
+  BUFF I37 (w_0n[6], inpA_0d[6]);
+  BUFF I38 (w_0n[7], inpA_0d[7]);
+  BUFF I39 (inpB_0r, inpB_0a);
+  BUFF I40 (inpA_0r, inpA_0a);
+  BUFF I41 (out_0a, out_0r);
+  BUFF I42 (go_0a, done_0n);
+  BUFF I43 (start_0n, go_0r);
+endmodule
+
+module Balsa_BF (
+  go_0r, go_0a,
+  i1_0r, i1_0a, i1_0d,
+  i2_0r, i2_0a, i2_0d,
+  o_0r, o_0a, o_0d
+);
+  input go_0r;
+  output go_0a;
+  output i1_0r;
+  input i1_0a;
+  input [7:0] i1_0d;
+  output i2_0r;
+  input i2_0a;
+  input [7:0] i2_0d;
+  input o_0r;
+  output o_0a;
+  output [7:0] o_0d;
+  BrzBinaryFunc__Data_8_8_8_s3_Add_s5_False__m7m I0 (go_0r, go_0a, o_0r, o_0a, o_0d[7:0], i1_0r, i1_0a, i1_0d[7:0], i2_0r, i2_0a, i2_0d[7:0]);
+endmodule
+
+"
+"module Full_BF (
+  i1_0r, i1_0a, i1_0d,
+  i2_0r, i2_0a, i2_0d,
+  o_0r, o_0a, o_0d
+);
+  wire go_r;
+  wire go_a;
+  wire dummy_o_a;
+  wire dummy_i1_r;
+  wire dummy_i2_r;
+
+  output i1_0r;
+  input i1_0a;
+  input [7:0] i1_0d;
+  output i2_0r;
+  input i2_0a;
+  input [7:0] i2_0d;
+  input o_0r;
+  output o_0a;
+  output [7:0] o_0d;
+  Balsa_BF I0 (go_r, go_a, o_0r, dummy_o_a, o_0d[7:0], dummy_i1_r, i1_0a, i1_0d[7:0], dummy_i2_r, i2_0a, i2_0d[7:0]);
+  Control_BF I1 (go_r, go_a, o_0r, o_0a, i1_0r, i1_0a, i2_0r, i2_0a);
+endmodule
+"
+"fifo_1kx16\tfifo_1kx16_inst (\r
+\t.aclr ( aclr_sig ),\r
+\t.clock ( clock_sig ),\r
+\t.data ( data_sig ),\r
+\t.rdreq ( rdreq_sig ),\r
+\t.wrreq ( wrreq_sig ),\r
+\t.almost_empty ( almost_empty_sig ),\r
+\t.empty ( empty_sig ),\r
+\t.full ( full_sig ),\r
+\t.q ( q_sig ),\r
+\t.usedw ( usedw_sig )\r
+\t);\r
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
+   input        clk_i;
+   input        rst_i;
+   input        ena_i;
+   input        tx_empty_i;
+   input [11:0] tx_delay_i;
+   input [11:0] rx_delay_i;
+   output       atr_tx_o;
+
+   reg [3:0] \tstate;
+   reg [11:0] \tcount;
+
+   `define ST_RX_DELAY 4'b0001
+   `define ST_RX       4'b0010
+   `define ST_TX_DELAY 4'b0100
+   `define ST_TX       4'b1000
+
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       begin
+\t  state <= `ST_RX;
+\t  count <= 12'b0;
+       end
+     else
+       case (state)
+\t `ST_RX:
+\t   if (!tx_empty_i)
+\t     begin
+\t\tstate <= `ST_TX_DELAY;
+\t\tcount <= tx_delay_i;
+\t     end
+
+\t `ST_TX_DELAY:
+\t   if (count == 0)
+\t     state <= `ST_TX;
+\t   else
+\t     count <= count - 1;
+
+\t `ST_TX:
+\t   if (tx_empty_i)
+\t     begin
+\t\tstate <= `ST_RX_DELAY;
+\t\tcount <= rx_delay_i;
+\t     end
+
+\t `ST_RX_DELAY:
+\t   if (count == 0)
+\t     state <= `ST_RX;
+\t   else
+\t     count <= count - 1;
+\t 
+\t default:\t\t// Error
+\t   begin
+\t      state <= `ST_RX;
+\t      count <= 0;
+\t   end
+       endcase
+   
+   assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
+   
+endmodule // atr_delay
+
+"
+"bustri\tbustri_inst (
+\t.data ( data_sig ),
+\t.enabledt ( enabledt_sig ),
+\t.tridata ( tridata_sig )
+\t);
+"
+"addsub16\taddsub16_inst (
+\t.add_sub ( add_sub_sig ),
+\t.dataa ( dataa_sig ),
+\t.datab ( datab_sig ),
+\t.clock ( clock_sig ),
+\t.aclr ( aclr_sig ),
+\t.clken ( clken_sig ),
+\t.result ( result_sig )
+\t);
+"
+"//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module addsub16 (
+\tadd_sub,
+\tdataa,
+\tdatab,
+\tclock,
+\taclr,
+\tclken,
+\tresult)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t  add_sub;
+\tinput\t[15:0]  dataa;
+\tinput\t[15:0]  datab;
+\tinput\t  clock;
+\tinput\t  aclr;
+\tinput\t  clken;
+\toutput\t[15:0]  result;
+
+endmodule
+
+"
+"
+
+module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
+
+   always @(posedge clock)
+     case (addr)
+       3'd0 : data <= #1 -16'd49;
+       3'd1 : data <= #1 16'd165;
+       3'd2 : data <= #1 -16'd412;
+       3'd3 : data <= #1 16'd873;
+       3'd4 : data <= #1 -16'd1681;
+       3'd5 : data <= #1 16'd3135;
+       3'd6 : data <= #1 -16'd6282;
+       3'd7 : data <= #1 16'd20628;
+     endcase // case(addr)
+      
+endmodule // coeff_rom
+
+
+"
+"sub32\tsub32_inst (
+\t.dataa ( dataa_sig ),
+\t.datab ( datab_sig ),
+\t.clock ( clock_sig ),
+\t.aclr ( aclr_sig ),
+\t.clken ( clken_sig ),
+\t.result ( result_sig )
+\t);
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module tx_chain
+  (input clock,
+   input reset,
+   input enable,
+   input wire [7:0] interp_rate,
+   input sample_strobe,
+   input interpolator_strobe,
+   input wire [31:0] freq,
+   input wire [15:0] i_in,
+   input wire [15:0] q_in,
+   output wire [15:0] i_out,
+   output wire [15:0] q_out
+   );
+
+   wire [15:0] bb_i, bb_q;
+
+   cic_interp cic_interp_i
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
+       .signal_in(i_in),.signal_out(bb_i) );
+
+   cic_interp cic_interp_q
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
+       .signal_in(q_in),.signal_out(bb_q) );
+   
+`define NOCORDIC_TX
+`ifdef NOCORDIC_TX
+   assign      i_out = bb_i;
+   assign      q_out = bb_q;
+`else
+   wire [31:0] phase;
+
+   phase_acc phase_acc_tx
+     (.clk(clock),.reset(reset),.enable(enable),
+      .strobe(sample_strobe),.freq(freq),.phase(phase) );
+   
+   cordic tx_cordic_0
+     ( .clock(clock),.reset(reset),.enable(sample_strobe), 
+       .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
+       .xo(i_out),.yo(q_out),.zo() );
+`endif
+
+endmodule // tx_chain
+"
+"
+
+module setting_reg
+  ( input clock, input reset, input strobe, input wire [6:0] addr,
+    input wire [31:0] in, output reg [31:0] out, output reg changed);
+   parameter my_addr = 0;
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+\t  out <= #1 32'd0;
+\t  changed <= #1 1'b0;
+       end
+     else
+       if(strobe & (my_addr==addr))
+\t begin
+\t    out <= #1 in;
+\t    changed <= #1 1'b1;
+\t end
+       else
+\t changed <= #1 1'b0;
+   
+endmodule // setting_reg
+"
+"// Model of FIFO in Altera
+
+module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+\t\t    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+   parameter width = 16;
+   parameter depth = 1024;
+   parameter addr_bits = 10;
+   
+   //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
+   
+   input [width-1:0] data;
+   input \t     wrreq;
+   input \t     rdreq;
+   input \t     rdclk;
+   input \t     wrclk;
+   input \t     aclr;
+   output [width-1:0] q;
+   output \t      rdfull;
+   output \t      rdempty;
+   output reg [addr_bits-1:0]  rdusedw;
+   output wrfull;
+   output wrempty;
+   output reg [addr_bits-1:0]  wrusedw;
+   
+   reg [width-1:0] mem [0:depth-1];
+   reg [addr_bits-1:0] \t      rdptr;
+   reg [addr_bits-1:0] \t      wrptr;
+   
+`ifdef rd_req
+   reg [width-1:0]    q;
+`else
+   wire [width-1:0]   q;
+`endif
+   
+   integer \t      i;
+   
+   always @( aclr)
+     begin
+\twrptr <= #1 0;
+\trdptr <= #1 0;
+\tfor(i=0;i<depth;i=i+1)
+\t  mem[i] <= #1 0;
+     end
+   
+   always @(posedge wrclk)
+     if(wrreq)
+       begin
+\t  wrptr <= #1 wrptr+1;
+\t  mem[wrptr] <= #1 data;
+       end
+   
+   always @(posedge rdclk)
+     if(rdreq)
+       begin
+   \t  rdptr <= #1 rdptr+1;
+`ifdef rd_req
+\t  q <= #1 mem[rdptr];
+`endif
+       end
+   
+`ifdef rd_req
+`else
+   assign q = mem[rdptr];
+`endif
+   
+   // Fix these
+   always @(posedge wrclk)
+     wrusedw <= #1 wrptr - rdptr;
+   
+   always @(posedge rdclk)
+     rdusedw <= #1 wrptr - rdptr;
+   
+   assign wrempty = (wrusedw == 0);
+   assign wrfull = (wrusedw == depth-1);
+   
+   assign rdempty = (rdusedw == 0);
+   assign rdfull = (rdusedw == depth-1);
+   
+endmodule // fifo
+
+
+"
+"// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: clk_doubler.v
+// Megafunction Name(s):
+// \t\t\taltpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.2 Build 156 11/29/2004 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module clk_doubler (
+\tinclk0,
+\tc0);
+
+\tinput\t  inclk0;
+\toutput\t  c0;
+
+\twire [5:0] sub_wire0;
+\twire [0:0] sub_wire4 = 1\'h0;
+\twire [0:0] sub_wire1 = sub_wire0[0:0];
+\twire  c0 = sub_wire1;
+\twire  sub_wire2 = inclk0;
+\twire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+\taltpll\taltpll_component (
+\t\t\t\t.inclk (sub_wire3),
+\t\t\t\t.clk (sub_wire0)
+\t\t\t\t// synopsys translate_off
+\t\t\t\t,
+\t\t\t\t.activeclock (),
+\t\t\t\t.areset (),
+\t\t\t\t.clkbad (),
+\t\t\t\t.clkena (),
+\t\t\t\t.clkloss (),
+\t\t\t\t.clkswitch (),
+\t\t\t\t.enable0 (),
+\t\t\t\t.enable1 (),
+\t\t\t\t.extclk (),
+\t\t\t\t.extclkena (),
+\t\t\t\t.fbin (),
+\t\t\t\t.locked (),
+\t\t\t\t.pfdena (),
+\t\t\t\t.pllena (),
+\t\t\t\t.scanaclr (),
+\t\t\t\t.scanclk (),
+\t\t\t\t.scandata (),
+\t\t\t\t.scandataout (),
+\t\t\t\t.scandone (),
+\t\t\t\t.scanread (),
+\t\t\t\t.scanwrite (),
+\t\t\t\t.sclkout0 (),
+\t\t\t\t.sclkout1 ()
+\t\t\t\t// synopsys translate_on
+\t\t\t\t);
+\tdefparam
+\t\taltpll_component.clk0_duty_cycle = 50,
+\t\taltpll_component.lpm_type = ""altpll"",
+\t\taltpll_component.clk0_multiply_by = 2,
+\t\taltpll_component.inclk0_input_frequency = 15625,
+\t\taltpll_component.clk0_divide_by = 1,
+\t\taltpll_component.pll_type = ""AUTO"",
+\t\taltpll_component.intended_device_family = ""Cyclone"",
+\t\taltpll_component.operation_mode = ""NORMAL"",
+\t\taltpll_component.compensate_clock = ""CLK0"",
+\t\taltpll_component.clk0_phase_shift = ""0"";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING ""0""
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING ""deg""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING ""MHz""
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING ""MHz""
+// Retrieval info: PRIVATE: SPREAD_USE STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC ""1048575""
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING ""0""
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING ""50.00000000""
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING ""0.00000000""
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC ""2""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING ""0.500""
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING ""0""
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING ""0""
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING ""1""
+// Retrieval info: PRIVATE: BANDWIDTH STRING ""1.000""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING ""0""
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING ""8""
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING ""50.000""
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING ""1""
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC ""0""
+// Retrieval info: PRIVATE: USE_CLK0 STRING ""1""
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING ""0""
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING ""0""
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING ""0""
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING ""100.000""
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING ""c0""
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING ""MHz""
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING ""MHz""
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING ""0""
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING ""1""
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING ""e0""
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC ""1""
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING ""1""
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING ""0""
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC ""1""
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING ""1""
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING ""0""
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING ""512.000""
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING ""KHz""
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING ""0""
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING ""64.000""
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING ""0""
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING ""1""
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING ""100.000""
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING ""inclk0""
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING ""0""
+// Retrieval info: PRIVATE: DEV_FAMILY STRING ""Cyclone""
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC ""1""
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING ""Low""
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING ""0""
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING ""deg""
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING ""0""
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC ""11""
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC ""50""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""altpll""
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC ""2""
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC ""15625""
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC ""1""
+// Retrieval info: CONSTANT: PLL_TYPE STRING ""AUTO""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: OPERATION_MODE STRING ""NORMAL""
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING ""CLK0""
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING ""0""
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC ""c0""
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC ""@clk[5..0]""
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND ""inclk0""
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC ""@extclk[3..0]""
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Very simple model for the PLL in the RX buffer
+
+module pll (inclk0,c0);
+   
+   input\t  inclk0;
+   output\t  c0;
+
+   assign \t  c0 = #9 inclk0;
+      
+endmodule // pll
+
+
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003,2004 Matt Ettus
+//  Copyright 2007 Free Software Foundation, Inc.
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+`define TX_IN_BAND
+`define RX_IN_BAND
+
+`include ""config.vh""
+`include ""../../../firmware/include/fpga_regs_common.v""
+`include ""../../../firmware/include/fpga_regs_standard.v""
+
+module usrp_inband_usb
+(output MYSTERY_SIGNAL,
+ input master_clk,
+ input SCLK,
+ input SDI,
+ inout SDO,
+ input SEN_FPGA,
+
+ input FX2_1,
+ output FX2_2,
+ output FX2_3,
+ 
+ input wire [11:0] rx_a_a,
+ input wire [11:0] rx_b_a,
+ //input wire [11:0] rx_a_b,
+ //input wire [11:0] rx_b_b,
+
+ output wire [13:0] tx_a,
+ //output wire [13:0] tx_b,
+
+ output wire TXSYNC_A,
+ //output wire TXSYNC_B,
+ 
+  // USB interface
+ input usbclk,
+ input wire [5:0] usbctl,
+ output wire [1:0] usbrdy,
+ input wire [3:0] usbrdy2,
+
+ inout [15:0] usbdata,  // NB Careful, inout
+
+ // These are the general purpose i/o\'s that go to the daughterboard slots
+ inout wire [15:0] io_tx_a,
+ //inout wire [15:0] io_tx_b,
+ inout wire [15:0] io_rx_a,
+ //inout wire [15:0] io_rx_b
+ output wire test_bit0,\r
+ output wire test_bit1
+ );\t
+   wire [15:0] debugdata,debugctrl;
+   assign MYSTERY_SIGNAL = 1\'b0;
+   
+   wire clk64;
+   assign clk64 = master_clk;
+   
+   wire WR = usbctl[0];
+   wire RD = usbctl[1];
+   wire OE = usbctl[2];
+
+   wire have_space, have_pkt_rdy;
+   assign usbrdy[0] = have_space;
+   assign usbrdy[1] = have_pkt_rdy;
+
+   wire   rx_overrun;    
+   wire   clear_status = FX2_1;
+   assign FX2_2 = rx_overrun;
+   assign FX2_3 = (tx_underrun == 0);
+      
+   wire [15:0] usbdata_out;
+   
+   wire [3:0]  dac0mux,dac1mux,dac2mux,dac3mux;
+   
+   wire        tx_realsignals;
+   wire [3:0]  rx_numchan;
+   wire [2:0]  tx_numchan;
+   
+   wire [7:0]  interp_rate, decim_rate;
+   wire [15:0] tx_debugbus, rx_debugbus;
+   
+   wire        enable_tx, enable_rx;
+   wire        tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
+   wire [7:0]  settings;
+   
+   // Tri-state bus macro
+   bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
+
+   wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
+   wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
+   
+   // TX
+   wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
+   wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1;  // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
+   
+   wire        strobe_interp, tx_sample_strobe;
+   wire        tx_empty;
+   
+   wire        serial_strobe;
+   wire [6:0]  serial_addr;
+   wire [31:0] serial_data;
+
+   reg [15:0] debug_counter;
+   reg [15:0] loopback_i_0,loopback_q_0;
+   
+
+   //Connection RX inband <-> TX inband
+   wire rx_WR;
+   wire [15:0] rx_databus;
+   wire rx_WR_done;
+   wire rx_WR_enabled;
+
+   wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
+   wire [15:0] reg_0,reg_1,reg_2,reg_3;
+   wire [6:0] reg_addr;
+   wire [31:0] reg_data_out;
+   wire [31:0] reg_data_in;
+   wire [1:0] reg_io_enable;
+   wire [31:0] rssi_threshhold;
+   wire [31:0] rssi_wait;
+   wire [6:0] addr_wr;
+   wire [31:0] data_wr;
+   wire strobe_wr;
+   wire [6:0] addr_db;
+   wire [31:0] data_db;
+   wire strobe_db;
+   assign serial_strobe = strobe_db | strobe_wr;
+   assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
+   assign serial_data = (strobe_db)? (data_db) : (data_wr);\t
+   //assign serial_strobe = strobe_db;
+   //assign serial_data = data_db;
+   //assign serial_addr = addr_db;
+
+   //wires for register connection
+\twire [11:0] atr_tx_delay;
+\twire [11:0] atr_rx_delay;
+\twire [7:0]  master_controls;
+\twire [3:0]  debug_en;
+\t
+\twire [15:0] atr_mask_0;
+\twire [15:0] atr_txval_0;
+\twire [15:0] atr_rxval_0;
+\t
+\twire [15:0] atr_mask_1;
+\twire [15:0] atr_txval_1;
+\twire [15:0] atr_rxval_1;
+\t
+\twire [15:0] atr_mask_2;
+\twire [15:0] atr_txval_2;
+\twire [15:0] atr_rxval_2;
+\t
+\twire [15:0] atr_mask_3;
+\twire [15:0] atr_txval_3;
+\twire [15:0] atr_rxval_3;
+\t
+\twire [7:0]  txa_refclk;
+\twire [7:0]  txb_refclk;
+\twire [7:0]  rxa_refclk;
+\twire [7:0]  rxb_refclk;\t
+\t 
+   register_io register_control
+    (.clk(clk64),.reset(1\'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
+     .dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), .strobe_wr(strobe_wr),
+     .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), 
+     .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
+\t .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+     .interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings), 
+\t .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}), 
+\t .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), .master_controls(master_controls), 
+\t .debug_en(debug_en), .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
+\t .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1), 
+\t .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2), 
+\t .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
+\t .txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
+   
+   ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+   // Transmit Side
+`ifdef TX_ON
+   assign      bb_tx_i0 = ch0tx;
+   assign      bb_tx_q0 = ch1tx;
+   assign      bb_tx_i1 = ch2tx;
+   assign      bb_tx_q1 = ch3tx;
+
+wire [1:0] tx_underrun;
+wire stop;
+wire [15:0] stop_time;
+`ifdef TX_IN_BAND
+ \ttx_buffer_inband tx_buffer
+     ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
+       .usbdata(usbdata),.WR(WR),.have_space(have_space),
+       .tx_underrun(tx_underrun),.channels({tx_numchan,1\'b0}),
+       .tx_i_0(ch0tx),.tx_q_0(ch1tx),
+       .tx_i_1(ch2tx),.tx_q_1(ch3tx),
+       .tx_i_2(),.tx_q_2(),
+       .tx_i_3(),.tx_q_3(),
+       .txclk(clk64),.txstrobe(strobe_interp),
+       .clear_status(clear_status),
+       .tx_empty(tx_empty),
+\t   .rx_WR(rx_WR),
+\t   .rx_databus(rx_databus), 
+\t   .rx_WR_done(rx_WR_done),
+\t   .rx_WR_enabled(rx_WR_enabled),
+\t   .reg_addr(reg_addr),
+\t   .reg_data_out(reg_data_out),
+\t   .reg_data_in(reg_data_in),
+\t   .reg_io_enable(reg_io_enable),
+\t   .debugbus(tx_debugbus),
+\t   .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), 
+      .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
+\t   .stop(stop), .stop_time(stop_time),
+      .test_bit0(test_bit0), \r
+\t\t.test_bit1(test_bit1));
+`else
+   tx_buffer tx_buffer
+     ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
+       .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
+       .channels({tx_numchan,1\'b0}),
+       .tx_i_0(ch0tx),.tx_q_0(ch1tx),
+       .tx_i_1(ch2tx),.tx_q_1(ch3tx),
+       .tx_i_2(),.tx_q_2(),
+       .tx_i_3(),.tx_q_3(),
+       .txclk(clk64),.txstrobe(strobe_interp),
+       .clear_status(clear_status),
+       .tx_empty(tx_empty));
+`endif
+
+ `ifdef TX_EN_0
+   tx_chain tx_chain_0
+     ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+       .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+       .interpolator_strobe(strobe_interp),.freq(),
+       .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
+ `else
+   assign      i_out_0=16\'d0;
+   assign      q_out_0=16\'d0;
+ `endif
+
+ `ifdef TX_EN_1
+   tx_chain tx_chain_1
+     ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+       .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
+       .interpolator_strobe(strobe_interp),.freq(),
+       .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
+ `else
+   assign      i_out_1=16\'d0;
+   assign      q_out_1=16\'d0;
+ `endif
+
+   setting_reg #(`FR_TX_MUX) 
+     sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+\t      .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
+   
+   wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16\'b0011111111111111;
+   wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16\'b0011111111111111;
+   //wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16\'b0;
+   //wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16\'b0;
+
+   wire txsync = tx_sample_strobe;
+   assign TXSYNC_A = txsync;
+   //assign TXSYNC_B = txsync;
+
+   assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
+   //assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
+`endif //  `ifdef TX_ON
+   
+   /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+   // Receive Side
+`ifdef RX_ON
+   wire        rx_sample_strobe,strobe_decim,hb_strobe;
+   wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
+\t       bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
+
+   wire loopback = settings[0];
+   wire counter = settings[1];
+
+   always @(posedge clk64)
+     if(rx_dsp_reset)
+       debug_counter <= #1 16\'d0;
+     else if(~enable_rx)
+       debug_counter <= #1 16\'d0;
+     else if(hb_strobe)
+       debug_counter <=#1 debug_counter + 16\'d2;
+   
+   always @(posedge clk64)
+     if(strobe_interp)
+       begin
+\t  loopback_i_0 <= #1 ch0tx;
+\t  loopback_q_0 <= #1 ch1tx;
+       end
+   
+   assign ch0rx = bb_rx_i0;
+   assign ch1rx = bb_rx_q0;
+   assign ch2rx = bb_rx_i1;
+   assign ch3rx = bb_rx_q1;
+   assign ch4rx = bb_rx_i2;
+   assign ch5rx = bb_rx_q2;
+   assign ch6rx = bb_rx_i3;
+   assign ch7rx = bb_rx_q3;
+
+   wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
+   adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1\'b1),
+\t\t\t       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+\t\t\t       .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_a),.rx_b_b(rx_b_a),
+\t\t\t       .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
+\t\t\t       .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
+\t\t\t       .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
+\t\t\t       .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
+\t\t\t       .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
+   `ifdef RX_IN_BAND
+   rx_buffer_inband rx_buffer
+     ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
+       .reset_regs(rx_dsp_reset),
+       .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+       .channels(rx_numchan),
+       .ch_0(ch0rx),.ch_1(ch1rx),
+       .ch_2(ch2rx),.ch_3(ch3rx),
+       .ch_4(ch4rx),.ch_5(ch5rx),
+       .ch_6(ch6rx),.ch_7(ch7rx),
+       .rxclk(clk64),.rxstrobe(hb_strobe),
+       .clear_status(clear_status),
+\t   .rx_WR(rx_WR),
+\t   .rx_databus(rx_databus),
+\t   .rx_WR_done(rx_WR_done),
+\t   .rx_WR_enabled(rx_WR_enabled),
+\t   .debugbus(rx_debugbus),
+\t   .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
+\t   .tx_underrun(tx_underrun));
+   `else
+   rx_buffer rx_buffer
+     ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
+       .reset_regs(rx_dsp_reset),
+       .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+       .channels(rx_numchan),
+       .ch_0(ch0rx),.ch_1(ch1rx),
+       .ch_2(ch2rx),.ch_3(ch3rx),
+       .ch_4(ch4rx),.ch_5(ch5rx),
+       .ch_6(ch6rx),.ch_7(ch7rx),
+       .rxclk(clk64),.rxstrobe(hb_strobe),
+       .clear_status(clear_status),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+   `endif
+   
+ `ifdef RX_EN_0
+   rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
+     ( .clock(clk64),.reset(1\'b0),.enable(enable_rx),
+       .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
+ `else
+   assign      bb_rx_i0=16\'d0;
+   assign      bb_rx_q0=16\'d0;
+ `endif
+   
+ `ifdef RX_EN_1
+   rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
+     ( .clock(clk64),.reset(1\'b0),.enable(enable_rx),
+       .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
+ `else
+   assign      bb_rx_i1=16\'d0;
+   assign      bb_rx_q1=16\'d0;
+ `endif
+   
+ `ifdef RX_EN_2
+   rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
+     ( .clock(clk64),.reset(1\'b0),.enable(enable_rx),
+       .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
+ `else
+   assign      bb_rx_i2=16\'d0;
+   assign      bb_rx_q2=16\'d0;
+ `endif
+
+ `ifdef RX_EN_3
+   rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
+     ( .clock(clk64),.reset(1\'b0),.enable(enable_rx),
+       .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
+ `else
+   assign      bb_rx_i3=16\'d0;
+   assign      bb_rx_q3=16\'d0;
+ `endif
+
+`endif //  `ifdef RX_ON
+   
+   ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+   // Control Functions
+
+   wire [31:0] capabilities;
+   assign      capabilities[7] =   `TX_CAP_HB;
+   assign      capabilities[6:4] = `TX_CAP_NCHAN;
+   assign      capabilities[3] =   `RX_CAP_HB;
+   assign      capabilities[2:0] = `RX_CAP_NCHAN;
+
+   serial_io serial_io
+     ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
+       .enable(SEN_FPGA),.reset(1\'b0),.serial_data_out(SDO),
+       .serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
+       .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_a,io_tx_a}),.readback_2(capabilities),.readback_3(32\'hf0f0931a),
+       .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
+       );
+
+   //implementing freeze mode
+   /*
+   reg [15:0] timestop;
+   wire stop;
+   wire [15:0] stop_time;
+   assign\tclk64 = (timestop == 0) ? master_clk : 0;
+   always @(posedge master_clk)
+\t\tif (timestop[15:0] != 0)
+\t\t\ttimestop <= timestop - 16\'d1;
+\t\telse if (stop)
+\t\t\ttimestop <= stop_time;
+\t*/\t\t\t\t
+
+   
+   master_control master_control
+     ( .master_clk(clk64),.usbclk(usbclk),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+       .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+       .enable_tx(enable_tx),.enable_rx(enable_rx),
+       .interp_rate(interp_rate),.decim_rate(decim_rate),
+       .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+       .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+       .tx_empty(tx_empty), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+\t   .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), 
+\t   .master_controls(master_controls), .debug_en(debug_en), 
+\t   .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
+\t   .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1), 
+\t   .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
+\t   .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3), 
+\t   .txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
+\t   .debug_0(tx_debugbus), .debug_1(rx_debugbus));
+   
+   io_pins io_pins
+     (.io_0(io_tx_a),.io_1(io_rx_a),
+      .reg_0(reg_0),.reg_1(reg_1),
+      .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
+      .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+   
+   ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+   // Misc Settings
+   setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
+   reg forb;
+   always @(posedge usbclk)
+     begin
+         if (strobe_db) forb <= 1;
+     end  
+endmodule // usrp_inband_usb
+"
+"// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub 
+
+// ============================================================
+// File Name: add32.v
+// Megafunction Name(s):
+// \t\t\tlpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
+
+//synthesis_resources = lut 8 
+module  add32_add_sub_nq7
+\t( 
+\tdataa,
+\tdatab,
+\tresult) /* synthesis synthesis_clearbox=1 */;
+\tinput   [7:0]  dataa;
+\tinput   [7:0]  datab;
+\toutput   [7:0]  result;
+
+\twire  [7:0]   wire_add_sub_cella_combout;
+\twire  [0:0]   wire_add_sub_cella_0cout;
+\twire  [0:0]   wire_add_sub_cella_1cout;
+\twire  [0:0]   wire_add_sub_cella_2cout;
+\twire  [0:0]   wire_add_sub_cella_3cout;
+\twire  [0:0]   wire_add_sub_cella_4cout;
+\twire  [0:0]   wire_add_sub_cella_5cout;
+\twire  [0:0]   wire_add_sub_cella_6cout;
+\twire  [7:0]   wire_add_sub_cella_dataa;
+\twire  [7:0]   wire_add_sub_cella_datab;
+
+\tstratix_lcell   add_sub_cella_0
+\t( 
+\t.cin(1\'b0),
+\t.combout(wire_add_sub_cella_combout[0:0]),
+\t.cout(wire_add_sub_cella_0cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[0:0]),
+\t.datab(wire_add_sub_cella_datab[0:0]));
+\tdefparam
+\t\tadd_sub_cella_0.cin_used = ""true"",
+\t\tadd_sub_cella_0.lut_mask = ""96e8"",
+\t\tadd_sub_cella_0.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_0.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_0.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_1
+\t( 
+\t.cin(wire_add_sub_cella_0cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[1:1]),
+\t.cout(wire_add_sub_cella_1cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[1:1]),
+\t.datab(wire_add_sub_cella_datab[1:1]));
+\tdefparam
+\t\tadd_sub_cella_1.cin_used = ""true"",
+\t\tadd_sub_cella_1.lut_mask = ""96e8"",
+\t\tadd_sub_cella_1.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_1.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_1.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_2
+\t( 
+\t.cin(wire_add_sub_cella_1cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[2:2]),
+\t.cout(wire_add_sub_cella_2cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[2:2]),
+\t.datab(wire_add_sub_cella_datab[2:2]));
+\tdefparam
+\t\tadd_sub_cella_2.cin_used = ""true"",
+\t\tadd_sub_cella_2.lut_mask = ""96e8"",
+\t\tadd_sub_cella_2.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_2.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_2.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_3
+\t( 
+\t.cin(wire_add_sub_cella_2cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[3:3]),
+\t.cout(wire_add_sub_cella_3cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[3:3]),
+\t.datab(wire_add_sub_cella_datab[3:3]));
+\tdefparam
+\t\tadd_sub_cella_3.cin_used = ""true"",
+\t\tadd_sub_cella_3.lut_mask = ""96e8"",
+\t\tadd_sub_cella_3.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_3.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_3.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_4
+\t( 
+\t.cin(wire_add_sub_cella_3cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[4:4]),
+\t.cout(wire_add_sub_cella_4cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[4:4]),
+\t.datab(wire_add_sub_cella_datab[4:4]));
+\tdefparam
+\t\tadd_sub_cella_4.cin_used = ""true"",
+\t\tadd_sub_cella_4.lut_mask = ""96e8"",
+\t\tadd_sub_cella_4.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_4.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_4.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_5
+\t( 
+\t.cin(wire_add_sub_cella_4cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[5:5]),
+\t.cout(wire_add_sub_cella_5cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[5:5]),
+\t.datab(wire_add_sub_cella_datab[5:5]));
+\tdefparam
+\t\tadd_sub_cella_5.cin_used = ""true"",
+\t\tadd_sub_cella_5.lut_mask = ""96e8"",
+\t\tadd_sub_cella_5.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_5.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_5.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_6
+\t( 
+\t.cin(wire_add_sub_cella_5cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[6:6]),
+\t.cout(wire_add_sub_cella_6cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[6:6]),
+\t.datab(wire_add_sub_cella_datab[6:6]));
+\tdefparam
+\t\tadd_sub_cella_6.cin_used = ""true"",
+\t\tadd_sub_cella_6.lut_mask = ""96e8"",
+\t\tadd_sub_cella_6.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_6.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_6.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_7
+\t( 
+\t.cin(wire_add_sub_cella_6cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[7:7]),
+\t.dataa(wire_add_sub_cella_dataa[7:7]),
+\t.datab(wire_add_sub_cella_datab[7:7]));
+\tdefparam
+\t\tadd_sub_cella_7.cin_used = ""true"",
+\t\tadd_sub_cella_7.lut_mask = ""9696"",
+\t\tadd_sub_cella_7.operation_mode = ""normal"",
+\t\tadd_sub_cella_7.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_7.lpm_type = ""stratix_lcell"";
+\tassign
+\t\twire_add_sub_cella_dataa = dataa,
+\t\twire_add_sub_cella_datab = datab;
+\tassign
+\t\tresult = wire_add_sub_cella_combout;
+endmodule //add32_add_sub_nq7
+//VALID FILE
+
+
+module add32 (
+\tdataa,
+\tdatab,
+\tresult)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[7:0]  dataa;
+\tinput\t[7:0]  datab;
+\toutput\t[7:0]  result;
+
+\twire [7:0] sub_wire0;
+\twire [7:0] result = sub_wire0[7:0];
+
+\tadd32_add_sub_nq7\tadd32_add_sub_nq7_component (
+\t\t\t\t.dataa (dataa),
+\t\t\t\t.datab (datab),
+\t\t\t\t.result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC ""8""
+// Retrieval info: PRIVATE: Function NUMERIC ""0""
+// Retrieval info: PRIVATE: WhichConstant NUMERIC ""0""
+// Retrieval info: PRIVATE: ConstantA NUMERIC ""0""
+// Retrieval info: PRIVATE: ConstantB NUMERIC ""0""
+// Retrieval info: PRIVATE: ValidCtA NUMERIC ""0""
+// Retrieval info: PRIVATE: ValidCtB NUMERIC ""0""
+// Retrieval info: PRIVATE: CarryIn NUMERIC ""0""
+// Retrieval info: PRIVATE: CarryOut NUMERIC ""0""
+// Retrieval info: PRIVATE: Overflow NUMERIC ""0""
+// Retrieval info: PRIVATE: Latency NUMERIC ""0""
+// Retrieval info: PRIVATE: aclr NUMERIC ""0""
+// Retrieval info: PRIVATE: clken NUMERIC ""0""
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC ""0""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""8""
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING ""ADD""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""LPM_ADD_SUB""
+// Retrieval info: CONSTANT: LPM_HINT STRING ""ONE_INPUT_IS_CONSTANT=NO""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
+// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
+// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
+// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+
+module strobe_gen 
+  ( input clock,
+    input reset,
+    input enable,
+    input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
+    input strobe_in,
+    output wire strobe );
+   
+//   parameter width = 8;
+   
+   reg [7:0] counter;
+   assign strobe = ~|counter && enable && strobe_in;
+   
+   always @(posedge clock)
+     if(reset | ~enable)
+       counter <= #1 8'd0;
+     else if(strobe_in)
+       if(counter == 0)
+\t counter <= #1 rate;
+       else 
+\t counter <= #1 counter - 8'd1;
+   
+endmodule // strobe_gen
+"
+"//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module add32 (
+\tdataa,
+\tdatab,
+\tresult)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[7:0]  dataa;
+\tinput\t[7:0]  datab;
+\toutput\t[7:0]  result;
+
+endmodule
+
+"
+"
+// Model for tristate bus on altera
+// FIXME do we really need to use a megacell for this?
+
+module bustri (data,
+\t       enabledt,
+\t       tridata);
+   
+   input [15:0]  data;
+   input \t enabledt;
+   inout [15:0]  tridata;
+   
+   assign \t tridata = enabledt ? data :16'bz;
+   
+endmodule // bustri
+
+
+"
+"module chan_fifo_reader 
+   (reset, tx_clock, tx_strobe, adc_time, samples_format,
+    fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
+    underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
+
+   input   wire                     reset ;
+   input   wire                     tx_clock ;
+   input   wire                     tx_strobe ; //signal to output tx_i and tx_q
+   input   wire              [31:0] adc_time ; //current time
+   input   wire               [3:0] samples_format ;// not useful at this point
+   input   wire              [31:0] fifodata ; //the data input
+   input   wire                     pkt_waiting ; //signal the next packet is ready
+   output  reg                      rdreq ; //actually an ack to the current fifodata
+   output  reg                      skip ; //finish reading current packet
+   output  reg               [15:0] tx_q ; //top 16 bit output of fifodata
+   output  reg               [15:0] tx_i ; //bottom 16 bit output of fifodata
+   output  reg                      underrun ; 
+   output  reg                      tx_empty ; //cause 0 to be the output
+   input   wire\t\t     [31:0] rssi;
+   input   wire\t\t     [31:0] threshhold;
+   input   wire\t\t     [31:0] rssi_wait;
+
+   output wire [14:0] debug;
+   
+   // Should not be needed if adc clock rate < tx clock rate
+   // Used only to debug
+   `define JITTER                   5
+    
+   //Samples format
+   // 16 bits interleaved complex samples
+   `define QI16                     4'b0
+    
+   // States
+   parameter IDLE           =     3'd0;    
+   parameter HEADER         =     3'd1;
+   parameter TIMESTAMP      =     3'd2;
+   parameter WAIT           =     3'd3;
+   parameter WAITSTROBE     =     3'd4;
+   parameter SEND           =     3'd5;
+
+   // Header format
+   `define PAYLOAD                  8:2
+   `define ENDOFBURST               27
+   `define STARTOFBURST             28
+   `define RSSI_FLAG                26
+\t
+
+   /* State registers */
+   reg                        [2:0] reader_state;
+   /* Local registers */  
+   reg                        [6:0] payload_len;
+   reg                        [6:0] read_len;
+   reg                       [31:0] timestamp;
+   reg                              burst;
+   reg                              trash;
+   reg                              rssi_flag;
+   reg\t\t\t     [31:0] time_wait;
+   
+   assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
+   always @(posedge tx_clock)
+     begin
+       if (reset) 
+         begin
+           reader_state <= IDLE;
+           rdreq <= 0;
+           skip <= 0;
+           underrun <= 0;
+           burst <= 0;
+           tx_empty <= 1;
+           tx_q <= 0;
+           tx_i <= 0;
+           trash <= 0;
+           rssi_flag <= 0;
+           time_wait <= 0;
+         end
+       else 
+         begin
+           case (reader_state)
+             IDLE:
+               begin
+               /*
+\t\t* reset all the variables and wait for a tx_strobe
+\t\t* it is assumed that the ram connected to this fifo_reader 
+\t\t* is a short hand fifo meaning that the header to the next packet
+\t\t* is already available to this fifo_reader when pkt_waiting is on
+\t\t*/
+                 skip <=0;
+                 time_wait <= 0;
+                 if (pkt_waiting == 1)
+                   begin
+                     reader_state <= HEADER;
+                     rdreq <= 1;
+                     underrun <= 0;
+                   end
+                 if (burst == 1 && pkt_waiting == 0)
+                     underrun <= 1;
+                 if (tx_strobe == 1)
+                     tx_empty <= 1 ;
+               end
+
+               /* Process header */
+               HEADER:
+                 begin
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
+                   
+                   rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
+                   //Check Start/End burst flag
+                   if  (fifodata[`STARTOFBURST] == 1 
+                       && fifodata[`ENDOFBURST] == 1)
+                       burst <= 0;
+                   else if (fifodata[`STARTOFBURST] == 1)
+                       burst <= 1;
+                   else if (fifodata[`ENDOFBURST] == 1)
+                       burst <= 0;
+
+                   if (trash == 1 && fifodata[`STARTOFBURST] == 0)
+                     begin
+                       skip <= 1;
+                       reader_state <= IDLE;
+                       rdreq <= 0;
+                     end 
+                   else
+                     begin   
+                       payload_len <= fifodata[`PAYLOAD] ;
+                       read_len <= 0;
+                       rdreq <= 1;
+                       reader_state <= TIMESTAMP;
+                     end
+                 end
+
+               TIMESTAMP: 
+                 begin
+                   timestamp <= fifodata;
+                   reader_state <= WAIT;
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
+                   rdreq <= 0;
+                 end
+\t\t\t\t
+               // Decide if we wait, send or discard samples
+               WAIT: 
+                 begin
+                   if (tx_strobe == 1)
+                       tx_empty <= 1 ;
+                    
+                   time_wait <= time_wait + 32'd1;
+                   // Outdated
+                   if ((timestamp < adc_time) ||
+                      (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
+                     begin
+                       trash <= 1;
+                       reader_state <= IDLE;
+                       skip <= 1;
+                     end  
+                   // Let's send it\t\t\t\t\t
+                   else if ((timestamp <= adc_time + `JITTER 
+                             && timestamp > adc_time)
+                             || timestamp == 32'hFFFFFFFF)
+                     begin
+                       if (rssi <= threshhold || rssi_flag == 0)
+                         begin
+                           trash <= 0;
+                           reader_state <= WAITSTROBE; 
+                         end
+                       else
+                         reader_state <= WAIT;
+                     end
+                   else
+                       reader_state <= WAIT;
+                 end
+                 
+               // Wait for the transmit chain to be ready
+               WAITSTROBE:
+                 begin
+                   // If end of payload...
+                   if (read_len == payload_len)
+                     begin
+                       reader_state <= IDLE;
+                       skip <= 1;
+                       if (tx_strobe == 1)
+                           tx_empty <= 1 ;
+                     end  
+                   else if (tx_strobe == 1)
+                     begin
+                       reader_state <= SEND;
+                       rdreq <= 1;
+                     end
+                 end
+               
+               // Send the samples to the tx_chain
+               SEND:
+                 begin
+                   reader_state <= WAITSTROBE; 
+                   read_len <= read_len + 7'd1;
+                   tx_empty <= 0;
+                   rdreq <= 0;
+                   
+                   case(samples_format)
+                       `QI16:
+                        begin
+                            tx_i <= fifodata[15:0];
+                            tx_q <= fifodata[31:16];
+                        end
+                        
+                        // Assume 16 bits complex samples by default
+                        default:
+                        begin
+                            tx_i <= fifodata[15:0];
+                            tx_q <= fifodata[31:16];
+                        end 
+                   endcase
+                 end
+               
+               default:
+                 begin
+                   //error handling
+                   reader_state <= IDLE;
+                 end
+           endcase
+       end
+   end
+ 
+endmodule
+"
+"//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module dspclkpll (
+\tinclk0,
+\tc0,
+\tc1);
+
+\tinput\t  inclk0;
+\toutput\t  c0;
+\toutput\t  c1;
+
+endmodule
+
+"
+"// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_4k.v
+// Megafunction Name(s):
+// \t\t\tdcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation\'s design tools, logic functions 
+//and other software and tools, and its AMPP partner logic       
+//functions, and any output files any of the foregoing           
+//(including device programming or simulation files), and any    
+//associated documentation or information are expressly subject  
+//to the terms and conditions of the Altera Program License      
+//Subscription Agreement, Altera MegaCore Function License       
+//Agreement, or other applicable license agreement, including,   
+//without limitation, that your use is for the sole purpose of   
+//programming logic devices manufactured by Altera and sold by   
+//Altera or its authorized distributors.  Please refer to the    
+//applicable agreement for further details.
+
+module fifo_4k (
+\tdata,
+\twrreq,
+\trdreq,
+\trdclk,
+\twrclk,
+\taclr,
+\tq,
+\trdempty,
+\trdusedw,
+\twrfull,
+\twrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[15:0]  data;
+\tinput\t  wrreq;
+\tinput\t  rdreq;
+\tinput\t  rdclk;
+\tinput\t  wrclk;
+\tinput\t  aclr;
+\toutput\t[15:0]  q;
+\toutput\t  rdempty;
+\toutput\t[11:0]  rdusedw;
+\toutput\t  wrfull;
+\toutput\t[11:0]  wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC ""16""
+// Retrieval info: PRIVATE: Depth NUMERIC ""4096""
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""
+// Retrieval info: PRIVATE: Full NUMERIC ""1""
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""4096""
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""12""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Following defines conditionally include RX path circuitry
+
+`include ""config.vh""\t// resolved relative to project root
+
+module rx_chain
+  (input clock,
+   input reset,
+   input enable,
+   input wire [7:0] decim_rate,
+   input sample_strobe,
+   input decimator_strobe,
+   output wire hb_strobe,
+   input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
+   input wire [15:0] i_in,
+   input wire [15:0] q_in,
+   output wire [15:0] i_out,
+   output wire [15:0] q_out,
+   output wire [15:0] debugdata,output wire [15:0] debugctrl
+   );
+
+   parameter FREQADDR = 0;
+   parameter PHASEADDR = 0;
+   
+   wire [31:0] phase;
+   wire [15:0] bb_i, bb_q;
+   wire [15:0] hb_in_i, hb_in_q;
+   
+   assign      debugdata = hb_in_i;
+
+`ifdef RX_NCO_ON
+    phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
+     (.clk(clock),.reset(reset),.enable(enable),
+      .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+      .strobe(sample_strobe),.phase(phase) );
+
+   cordic rx_cordic
+     ( .clock(clock),.reset(reset),.enable(enable), 
+       .xi(i_in),.yi(q_in),.zi(phase[31:16]),
+       .xo(bb_i),.yo(bb_q),.zo() );
+`else
+   assign bb_i = i_in;
+   assign bb_q = q_in;
+   assign sample_strobe = 1;
+`endif // !`ifdef RX_NCO_ON
+   
+`ifdef RX_CIC_ON
+   cic_decim cic_decim_i_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_i),.signal_out(hb_in_i) );
+`else
+   assign hb_in_i = bb_i;
+   assign decimator_strobe = sample_strobe;
+`endif
+   
+`ifdef RX_HB_ON
+   halfband_decim hbd_i_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .strobe_in(decimator_strobe),.strobe_out(hb_strobe),
+       .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
+`else
+   assign i_out = hb_in_i;
+   assign hb_strobe = decimator_strobe;
+`endif
+   
+`ifdef RX_CIC_ON
+   cic_decim cic_decim_q_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_q),.signal_out(hb_in_q) );
+`else
+   assign hb_in_q = bb_q;
+`endif
+
+`ifdef RX_HB_ON
+   halfband_decim hbd_q_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .strobe_in(decimator_strobe),.strobe_out(),
+       .data_in(hb_in_q),.data_out(q_out) );   
+`else
+   assign q_out = hb_in_q;
+`endif
+
+
+endmodule // rx_chain
+"
+"
+
+module acc (input clock, input reset, input clear, input enable_in, output reg enable_out,
+\t    input signed [30:0] addend, output reg signed [33:0] sum );
+
+   always @(posedge clock)
+     if(reset)
+       sum <= #1 34'd0;
+     //else if(clear & enable_in)
+     //  sum <= #1 addend;
+     //else if(clear)
+     //  sum <= #1 34'd0;
+     else if(clear)
+       sum <= #1 addend;
+     else if(enable_in)
+       sum <= #1 sum + addend;
+
+   always @(posedge clock)
+     enable_out <= #1 enable_in;
+   
+endmodule // acc
+
+"
+"// megafunction wizard: %FIFO%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: dcfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_4kx16_dc.v\r
+// Megafunction Name(s):\r
+// \t\t\tdcfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module fifo_4kx16_dc (\r
+\taclr,\r
+\tdata,\r
+\trdclk,\r
+\trdreq,\r
+\twrclk,\r
+\twrreq,\r
+\tq,\r
+\trdempty,\r
+\trdusedw,\r
+\twrfull,\r
+\twrusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t[15:0]  data;\r
+\tinput\t  rdclk;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrclk;\r
+\tinput\t  wrreq;\r
+\toutput\t[15:0]  q;\r
+\toutput\t  rdempty;\r
+\toutput\t[11:0]  rdusedw;\r
+\toutput\t  wrfull;\r
+\toutput\t[11:0]  wrusedw;\r
+\r
+\twire  sub_wire0;\r
+\twire [11:0] sub_wire1;\r
+\twire  sub_wire2;\r
+\twire [15:0] sub_wire3;\r
+\twire [11:0] sub_wire4;\r
+\twire  rdempty = sub_wire0;\r
+\twire [11:0] wrusedw = sub_wire1[11:0];\r
+\twire  wrfull = sub_wire2;\r
+\twire [15:0] q = sub_wire3[15:0];\r
+\twire [11:0] rdusedw = sub_wire4[11:0];\r
+\r
+\tdcfifo\tdcfifo_component (\r
+\t\t\t\t.wrclk (wrclk),\r
+\t\t\t\t.rdreq (rdreq),\r
+\t\t\t\t.aclr (aclr),\r
+\t\t\t\t.rdclk (rdclk),\r
+\t\t\t\t.wrreq (wrreq),\r
+\t\t\t\t.data (data),\r
+\t\t\t\t.rdempty (sub_wire0),\r
+\t\t\t\t.wrusedw (sub_wire1),\r
+\t\t\t\t.wrfull (sub_wire2),\r
+\t\t\t\t.q (sub_wire3),\r
+\t\t\t\t.rdusedw (sub_wire4)\r
+\t\t\t\t// synopsys translate_off\r
+\t\t\t\t,\r
+\t\t\t\t.wrempty (),\r
+\t\t\t\t.rdfull ()\r
+\t\t\t\t// synopsys translate_on\r
+\t\t\t\t);\r
+\tdefparam\r
+\t\tdcfifo_component.add_ram_output_register = ""OFF"",\r
+\t\tdcfifo_component.clocks_are_synchronized = ""FALSE"",\r
+\t\tdcfifo_component.intended_device_family = ""Cyclone"",\r
+\t\tdcfifo_component.lpm_numwords = 4096,\r
+\t\tdcfifo_component.lpm_showahead = ""ON"",\r
+\t\tdcfifo_component.lpm_type = ""dcfifo"",\r
+\t\tdcfifo_component.lpm_width = 16,\r
+\t\tdcfifo_component.lpm_widthu = 12,\r
+\t\tdcfifo_component.overflow_checking = ""OFF"",\r
+\t\tdcfifo_component.underflow_checking = ""OFF"",\r
+\t\tdcfifo_component.use_eab = ""ON"";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""4096""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""16""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""4096""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""12""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk\r
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]\r
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk\r
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0\r
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0\r
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0\r
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0\r
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0\r
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE\r
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// DUC block
+
+module duc(input clock,
+\t\t\tinput reset,
+\t\t\tinput enable,
+\t\t\tinput [3:0] rate1,
+\t\t\tinput [3:0] rate2,
+\t\t\toutput strobe,
+\t\t\tinput [31:0] freq,
+\t\t\tinput [15:0] i_in,
+\t\t\tinput [15:0] q_in,
+\t\t\toutput [15:0] i_out,
+\t\t\toutput [15:0] q_out
+\t\t\t);
+   parameter bw = 16;
+   parameter zw = 16;
+   
+\twire [15:0] i_interp_out, q_interp_out;
+\twire [31:0] phase;
+
+\twire strobe1, strobe2;
+\treg [3:0] strobe_ctr1,strobe_ctr2;
+
+\talways @(posedge clock)
+\t\tif(reset | ~enable)
+\t\t\tstrobe_ctr2 <= #1 4'd0;
+\t\telse if(strobe2)
+\t\t\tstrobe_ctr2 <= #1 4'd0;
+\t\telse\t
+\t\t\tstrobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
+\t\t\t\t
+\talways @(posedge clock)
+\t\tif(reset | ~enable)
+\t\t\tstrobe_ctr1 <= #1 4'd0;
+\t\telse if(strobe1)
+\t\t\tstrobe_ctr1 <= #1 4'd0;
+\t\telse if(strobe2)
+\t\t\tstrobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
+\t\t\t\t
+
+\tassign strobe2 = enable & ( strobe_ctr2 == rate2 );
+\tassign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
+
+\tassign strobe = strobe1;
+
+\tfunction [2:0] log_ceil;
+\tinput [3:0] val;
+\t
+\t\tlog_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; 
+\tendfunction\t
+\t
+\twire [2:0] shift1 = log_ceil(rate1);
+\twire [2:0] shift2 = log_ceil(rate2);
+\t
+\tcordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
+\t\tcordic(.clock(clock), .reset(reset), .enable(enable),
+\t\t\t.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]), 
+\t\t\t.xo(i_out), .yo(q_out), .zo()  );
+\t\t
+\tcic_interp_2stage #(.bw(bw),.N(4)) 
+\t\tinterp_i(.clock(clock),.reset(reset),.enable(enable),
+\t\t\t.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
+\t\t\t.signal_in(i_in),.signal_out(i_interp_out));
+
+\tcic_interp_2stage #(.bw(bw),.N(4)) 
+\t\tinterp_q(.clock(clock),.reset(reset),.enable(enable),
+\t\t\t.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
+\t\t\t.signal_in(q_in),.signal_out(q_interp_out));
+\t
+\tphase_acc #(.resolution(32))
+\t\tnco (.clk(clock),.reset(reset),.enable(enable),
+\t\t\t.freq(freq),.phase(phase));
+\t\t
+endmodule
+"
+"
+
+module fifo_1k
+  (  input [15:0] data,
+     input \twrreq,
+     input \trdreq,
+     input \trdclk,
+     input \twrclk,
+     input \taclr,
+     output [15:0] q,
+     output \t rdfull,
+     output \t rdempty,
+     output [9:0] rdusedw,
+     output \t wrfull,
+     output \t wrempty,
+     output [9:0]  wrusedw
+     );
+
+fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_1k
+   
+"
+"
+
+module ram16 (input clock, input write, 
+\t      input [3:0] wr_addr, input [15:0] wr_data,
+\t      input [3:0] rd_addr, output reg [15:0] rd_data);
+
+   reg [15:0] \t\tram_array [0:15];
+
+   always @(posedge clock)
+     rd_data <= #1 ram_array[rd_addr];
+
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram16
+
+"
+"module channel_demux
+ #(parameter NUM_CHAN = 2) (     //usb Side
+   input [31:0]usbdata_final,
+   input WR_final, 
+   // TX Side
+   input reset,
+   input txclk,
+   output reg [NUM_CHAN:0] WR_channel,
+   output reg [31:0] ram_data,
+   output reg [NUM_CHAN:0] WR_done_channel );
+   /* Parse header and forward to ram */
+\t
+    reg [2:0]reader_state;
+    reg [4:0]channel ;
+    reg [6:0]read_length ;
+\t
+\t // States
+    parameter IDLE      =    3'd0;
+    parameter HEADER    =    3'd1;
+    parameter WAIT      =    3'd2;
+    parameter FORWARD   =    3'd3;
+\t
+\t`define CHANNEL 20:16
+\t`define PKT_SIZE 127
+\twire [4:0] true_channel;
+\tassign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
+\t\t\t\t\t\t\tNUM_CHAN : (usbdata_final[`CHANNEL]);
+\t
+\talways @(posedge txclk)
+\t  begin
+\t    if (reset)
+\t      begin
+\t       reader_state <= IDLE;
+\t       WR_channel <= 0;
+\t       WR_done_channel <= 0;
+\t      end
+\t      else
+\t        case (reader_state)
+\t        IDLE: begin
+\t            if (WR_final)
+\t                reader_state <= HEADER; 
+\t            end
+\t       
+            // Store channel and forware header
+\t        HEADER: begin
+\t            channel <= true_channel;
+\t            WR_channel[true_channel] <= 1;
+\t            ram_data <= usbdata_final;
+\t\t\t\tread_length <= 7'd0 ;
+\t\t\t\t
+                reader_state <= WAIT;
+\t        end
+\t       
+\t        WAIT: begin
+\t           WR_channel[channel] <= 0;
+\t
+\t\t\t   if (read_length == `PKT_SIZE)
+\t               reader_state <= IDLE;
+\t           else if (WR_final)
+\t               reader_state <= FORWARD;
+\t        end
+\t       
+\t        FORWARD: begin
+\t           WR_channel[channel] <= 1;
+\t           ram_data <= usbdata_final;
+\t           read_length <= read_length + 7'd1;
+\t           
+\t           reader_state <= WAIT;
+\t        end
+\t
+\t\t\tdefault:
+               begin
+\t\t\t\t\t//error handling
+                   reader_state <= IDLE;
+               end
+\t       endcase
+\t   end
+endmodule
+"
+"// megafunction wizard: %FIFO%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_4k.v
+// Megafunction Name(s):
+// \t\t\tdcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation\'s design tools, logic functions 
+//and other software and tools, and its AMPP partner logic       
+//functions, and any output files any of the foregoing           
+//(including device programming or simulation files), and any    
+//associated documentation or information are expressly subject  
+//to the terms and conditions of the Altera Program License      
+//Subscription Agreement, Altera MegaCore Function License       
+//Agreement, or other applicable license agreement, including,   
+//without limitation, that your use is for the sole purpose of   
+//programming logic devices manufactured by Altera and sold by   
+//Altera or its authorized distributors.  Please refer to the    
+//applicable agreement for further details.
+
+
+//dcfifo ADD_RAM_OUTPUT_REGISTER=""OFF"" CLOCKS_ARE_SYNCHRONIZED=""FALSE"" DEVICE_FAMILY=""Cyclone"" LPM_NUMWORDS=4096 LPM_SHOWAHEAD=""ON"" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING=""OFF"" UNDERFLOW_CHECKING=""OFF"" USE_EAB=""ON"" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+
+//a_gray2bin device_family=""Cyclone"" WIDTH=12 bin gray
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END
+
+//synthesis_resources = 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_a_gray2bin_9m4
+\t( 
+\tbin,
+\tgray) /* synthesis synthesis_clearbox=1 */;
+\toutput   [11:0]  bin;
+\tinput   [11:0]  gray;
+
+\twire  xor0;
+\twire  xor1;
+\twire  xor10;
+\twire  xor2;
+\twire  xor3;
+\twire  xor4;
+\twire  xor5;
+\twire  xor6;
+\twire  xor7;
+\twire  xor8;
+\twire  xor9;
+
+\tassign
+\t\tbin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
+\t\txor0 = (gray[0] ^ xor1),
+\t\txor1 = (gray[1] ^ xor2),
+\t\txor10 = (gray[11] ^ gray[10]),
+\t\txor2 = (gray[2] ^ xor3),
+\t\txor3 = (gray[3] ^ xor4),
+\t\txor4 = (gray[4] ^ xor5),
+\t\txor5 = (gray[5] ^ xor6),
+\t\txor6 = (gray[6] ^ xor7),
+\t\txor7 = (gray[7] ^ xor8),
+\t\txor8 = (gray[8] ^ xor9),
+\t\txor9 = (gray[9] ^ xor10);
+endmodule //fifo_4k_a_gray2bin_9m4
+
+
+//a_graycounter DEVICE_FAMILY=""Cyclone"" WIDTH=12 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 13 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_a_graycounter_826
+\t( 
+\taclr,
+\tclock,
+\tcnt_en,
+\tq) /* synthesis synthesis_clearbox=1 */;
+\tinput   aclr;
+\tinput   clock;
+\tinput   cnt_en;
+\toutput   [11:0]  q;
+
+\twire  [0:0]   wire_countera_0cout;
+\twire  [0:0]   wire_countera_1cout;
+\twire  [0:0]   wire_countera_2cout;
+\twire  [0:0]   wire_countera_3cout;
+\twire  [0:0]   wire_countera_4cout;
+\twire  [0:0]   wire_countera_5cout;
+\twire  [0:0]   wire_countera_6cout;
+\twire  [0:0]   wire_countera_7cout;
+\twire  [0:0]   wire_countera_8cout;
+\twire  [0:0]   wire_countera_9cout;
+\twire  [0:0]   wire_countera_10cout;
+\twire  [11:0]   wire_countera_regout;
+\twire  wire_parity_cout;
+\twire  wire_parity_regout;
+\twire  [11:0]  power_modified_counter_values;
+\twire sclr;
+\twire updown;
+
+\tcyclone_lcell   countera_0
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_parity_cout),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_0cout[0:0]),
+\t.dataa(cnt_en),
+\t.datab(wire_countera_regout[0:0]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[0:0]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_0.cin_used = ""true"",
+\t\tcountera_0.lut_mask = ""c6a0"",
+\t\tcountera_0.operation_mode = ""arithmetic"",
+\t\tcountera_0.sum_lutc_input = ""cin"",
+\t\tcountera_0.synch_mode = ""on"",
+\t\tcountera_0.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_1
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_0cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_1cout[0:0]),
+\t.dataa(power_modified_counter_values[0]),
+\t.datab(power_modified_counter_values[1]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[1:1]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_1.cin_used = ""true"",
+\t\tcountera_1.lut_mask = ""6c50"",
+\t\tcountera_1.operation_mode = ""arithmetic"",
+\t\tcountera_1.sum_lutc_input = ""cin"",
+\t\tcountera_1.synch_mode = ""on"",
+\t\tcountera_1.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_2
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_1cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_2cout[0:0]),
+\t.dataa(power_modified_counter_values[1]),
+\t.datab(power_modified_counter_values[2]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[2:2]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_2.cin_used = ""true"",
+\t\tcountera_2.lut_mask = ""6c50"",
+\t\tcountera_2.operation_mode = ""arithmetic"",
+\t\tcountera_2.sum_lutc_input = ""cin"",
+\t\tcountera_2.synch_mode = ""on"",
+\t\tcountera_2.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_3
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_2cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_3cout[0:0]),
+\t.dataa(power_modified_counter_values[2]),
+\t.datab(power_modified_counter_values[3]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[3:3]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_3.cin_used = ""true"",
+\t\tcountera_3.lut_mask = ""6c50"",
+\t\tcountera_3.operation_mode = ""arithmetic"",
+\t\tcountera_3.sum_lutc_input = ""cin"",
+\t\tcountera_3.synch_mode = ""on"",
+\t\tcountera_3.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_4
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_3cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_4cout[0:0]),
+\t.dataa(power_modified_counter_values[3]),
+\t.datab(power_modified_counter_values[4]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[4:4]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_4.cin_used = ""true"",
+\t\tcountera_4.lut_mask = ""6c50"",
+\t\tcountera_4.operation_mode = ""arithmetic"",
+\t\tcountera_4.sum_lutc_input = ""cin"",
+\t\tcountera_4.synch_mode = ""on"",
+\t\tcountera_4.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_5
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_4cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_5cout[0:0]),
+\t.dataa(power_modified_counter_values[4]),
+\t.datab(power_modified_counter_values[5]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[5:5]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_5.cin_used = ""true"",
+\t\tcountera_5.lut_mask = ""6c50"",
+\t\tcountera_5.operation_mode = ""arithmetic"",
+\t\tcountera_5.sum_lutc_input = ""cin"",
+\t\tcountera_5.synch_mode = ""on"",
+\t\tcountera_5.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_6
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_5cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_6cout[0:0]),
+\t.dataa(power_modified_counter_values[5]),
+\t.datab(power_modified_counter_values[6]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[6:6]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_6.cin_used = ""true"",
+\t\tcountera_6.lut_mask = ""6c50"",
+\t\tcountera_6.operation_mode = ""arithmetic"",
+\t\tcountera_6.sum_lutc_input = ""cin"",
+\t\tcountera_6.synch_mode = ""on"",
+\t\tcountera_6.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_7
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_6cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_7cout[0:0]),
+\t.dataa(power_modified_counter_values[6]),
+\t.datab(power_modified_counter_values[7]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[7:7]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_7.cin_used = ""true"",
+\t\tcountera_7.lut_mask = ""6c50"",
+\t\tcountera_7.operation_mode = ""arithmetic"",
+\t\tcountera_7.sum_lutc_input = ""cin"",
+\t\tcountera_7.synch_mode = ""on"",
+\t\tcountera_7.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_8
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_7cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_8cout[0:0]),
+\t.dataa(power_modified_counter_values[7]),
+\t.datab(power_modified_counter_values[8]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[8:8]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_8.cin_used = ""true"",
+\t\tcountera_8.lut_mask = ""6c50"",
+\t\tcountera_8.operation_mode = ""arithmetic"",
+\t\tcountera_8.sum_lutc_input = ""cin"",
+\t\tcountera_8.synch_mode = ""on"",
+\t\tcountera_8.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_9
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_8cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_9cout[0:0]),
+\t.dataa(power_modified_counter_values[8]),
+\t.datab(power_modified_counter_values[9]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[9:9]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_9.cin_used = ""true"",
+\t\tcountera_9.lut_mask = ""6c50"",
+\t\tcountera_9.operation_mode = ""arithmetic"",
+\t\tcountera_9.sum_lutc_input = ""cin"",
+\t\tcountera_9.synch_mode = ""on"",
+\t\tcountera_9.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_10
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_9cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_10cout[0:0]),
+\t.dataa(power_modified_counter_values[9]),
+\t.datab(power_modified_counter_values[10]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[10:10]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_10.cin_used = ""true"",
+\t\tcountera_10.lut_mask = ""6c50"",
+\t\tcountera_10.operation_mode = ""arithmetic"",
+\t\tcountera_10.sum_lutc_input = ""cin"",
+\t\tcountera_10.synch_mode = ""on"",
+\t\tcountera_10.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_11
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_10cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(),
+\t.dataa(power_modified_counter_values[11]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[11:11]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datab(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_11.cin_used = ""true"",
+\t\tcountera_11.lut_mask = ""5a5a"",
+\t\tcountera_11.operation_mode = ""normal"",
+\t\tcountera_11.sum_lutc_input = ""cin"",
+\t\tcountera_11.synch_mode = ""on"",
+\t\tcountera_11.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   parity
+\t( 
+\t.aclr(aclr),
+\t.cin(updown),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_parity_cout),
+\t.dataa(cnt_en),
+\t.datab(wire_parity_regout),
+\t.ena(1\'b1),
+\t.regout(wire_parity_regout),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tparity.cin_used = ""true"",
+\t\tparity.lut_mask = ""6682"",
+\t\tparity.operation_mode = ""arithmetic"",
+\t\tparity.synch_mode = ""on"",
+\t\tparity.lpm_type = ""cyclone_lcell"";
+\tassign
+\t\tpower_modified_counter_values = {wire_countera_regout[11:0]},
+\t\tq = power_modified_counter_values,
+\t\tsclr = 1\'b0,
+\t\tupdown = 1\'b1;
+endmodule //fifo_4k_a_graycounter_826
+
+
+//a_graycounter DEVICE_FAMILY=""Cyclone"" PVALUE=1 WIDTH=12 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 13 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_a_graycounter_3r6
+\t( 
+\taclr,
+\tclock,
+\tcnt_en,
+\tq) /* synthesis synthesis_clearbox=1 */;
+\tinput   aclr;
+\tinput   clock;
+\tinput   cnt_en;
+\toutput   [11:0]  q;
+
+\twire  [0:0]   wire_countera_0cout;
+\twire  [0:0]   wire_countera_1cout;
+\twire  [0:0]   wire_countera_2cout;
+\twire  [0:0]   wire_countera_3cout;
+\twire  [0:0]   wire_countera_4cout;
+\twire  [0:0]   wire_countera_5cout;
+\twire  [0:0]   wire_countera_6cout;
+\twire  [0:0]   wire_countera_7cout;
+\twire  [0:0]   wire_countera_8cout;
+\twire  [0:0]   wire_countera_9cout;
+\twire  [0:0]   wire_countera_10cout;
+\twire  [11:0]   wire_countera_regout;
+\twire  wire_parity_cout;
+\twire  wire_parity_regout;
+\twire  [11:0]  power_modified_counter_values;
+\twire sclr;
+\twire updown;
+
+\tcyclone_lcell   countera_0
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_parity_cout),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_0cout[0:0]),
+\t.dataa(cnt_en),
+\t.datab(wire_countera_regout[0:0]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[0:0]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_0.cin_used = ""true"",
+\t\tcountera_0.lut_mask = ""c6a0"",
+\t\tcountera_0.operation_mode = ""arithmetic"",
+\t\tcountera_0.sum_lutc_input = ""cin"",
+\t\tcountera_0.synch_mode = ""on"",
+\t\tcountera_0.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_1
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_0cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_1cout[0:0]),
+\t.dataa(power_modified_counter_values[0]),
+\t.datab(power_modified_counter_values[1]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[1:1]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_1.cin_used = ""true"",
+\t\tcountera_1.lut_mask = ""6c50"",
+\t\tcountera_1.operation_mode = ""arithmetic"",
+\t\tcountera_1.sum_lutc_input = ""cin"",
+\t\tcountera_1.synch_mode = ""on"",
+\t\tcountera_1.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_2
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_1cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_2cout[0:0]),
+\t.dataa(power_modified_counter_values[1]),
+\t.datab(power_modified_counter_values[2]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[2:2]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_2.cin_used = ""true"",
+\t\tcountera_2.lut_mask = ""6c50"",
+\t\tcountera_2.operation_mode = ""arithmetic"",
+\t\tcountera_2.sum_lutc_input = ""cin"",
+\t\tcountera_2.synch_mode = ""on"",
+\t\tcountera_2.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_3
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_2cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_3cout[0:0]),
+\t.dataa(power_modified_counter_values[2]),
+\t.datab(power_modified_counter_values[3]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[3:3]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_3.cin_used = ""true"",
+\t\tcountera_3.lut_mask = ""6c50"",
+\t\tcountera_3.operation_mode = ""arithmetic"",
+\t\tcountera_3.sum_lutc_input = ""cin"",
+\t\tcountera_3.synch_mode = ""on"",
+\t\tcountera_3.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_4
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_3cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_4cout[0:0]),
+\t.dataa(power_modified_counter_values[3]),
+\t.datab(power_modified_counter_values[4]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[4:4]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_4.cin_used = ""true"",
+\t\tcountera_4.lut_mask = ""6c50"",
+\t\tcountera_4.operation_mode = ""arithmetic"",
+\t\tcountera_4.sum_lutc_input = ""cin"",
+\t\tcountera_4.synch_mode = ""on"",
+\t\tcountera_4.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_5
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_4cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_5cout[0:0]),
+\t.dataa(power_modified_counter_values[4]),
+\t.datab(power_modified_counter_values[5]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[5:5]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_5.cin_used = ""true"",
+\t\tcountera_5.lut_mask = ""6c50"",
+\t\tcountera_5.operation_mode = ""arithmetic"",
+\t\tcountera_5.sum_lutc_input = ""cin"",
+\t\tcountera_5.synch_mode = ""on"",
+\t\tcountera_5.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_6
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_5cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_6cout[0:0]),
+\t.dataa(power_modified_counter_values[5]),
+\t.datab(power_modified_counter_values[6]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[6:6]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_6.cin_used = ""true"",
+\t\tcountera_6.lut_mask = ""6c50"",
+\t\tcountera_6.operation_mode = ""arithmetic"",
+\t\tcountera_6.sum_lutc_input = ""cin"",
+\t\tcountera_6.synch_mode = ""on"",
+\t\tcountera_6.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_7
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_6cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_7cout[0:0]),
+\t.dataa(power_modified_counter_values[6]),
+\t.datab(power_modified_counter_values[7]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[7:7]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_7.cin_used = ""true"",
+\t\tcountera_7.lut_mask = ""6c50"",
+\t\tcountera_7.operation_mode = ""arithmetic"",
+\t\tcountera_7.sum_lutc_input = ""cin"",
+\t\tcountera_7.synch_mode = ""on"",
+\t\tcountera_7.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_8
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_7cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_8cout[0:0]),
+\t.dataa(power_modified_counter_values[7]),
+\t.datab(power_modified_counter_values[8]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[8:8]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_8.cin_used = ""true"",
+\t\tcountera_8.lut_mask = ""6c50"",
+\t\tcountera_8.operation_mode = ""arithmetic"",
+\t\tcountera_8.sum_lutc_input = ""cin"",
+\t\tcountera_8.synch_mode = ""on"",
+\t\tcountera_8.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_9
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_8cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_9cout[0:0]),
+\t.dataa(power_modified_counter_values[8]),
+\t.datab(power_modified_counter_values[9]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[9:9]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_9.cin_used = ""true"",
+\t\tcountera_9.lut_mask = ""6c50"",
+\t\tcountera_9.operation_mode = ""arithmetic"",
+\t\tcountera_9.sum_lutc_input = ""cin"",
+\t\tcountera_9.synch_mode = ""on"",
+\t\tcountera_9.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_10
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_9cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_10cout[0:0]),
+\t.dataa(power_modified_counter_values[9]),
+\t.datab(power_modified_counter_values[10]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[10:10]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_10.cin_used = ""true"",
+\t\tcountera_10.lut_mask = ""6c50"",
+\t\tcountera_10.operation_mode = ""arithmetic"",
+\t\tcountera_10.sum_lutc_input = ""cin"",
+\t\tcountera_10.synch_mode = ""on"",
+\t\tcountera_10.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_11
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_10cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(),
+\t.dataa(power_modified_counter_values[11]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[11:11]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datab(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_11.cin_used = ""true"",
+\t\tcountera_11.lut_mask = ""5a5a"",
+\t\tcountera_11.operation_mode = ""normal"",
+\t\tcountera_11.sum_lutc_input = ""cin"",
+\t\tcountera_11.synch_mode = ""on"",
+\t\tcountera_11.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   parity
+\t( 
+\t.aclr(aclr),
+\t.cin(updown),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_parity_cout),
+\t.dataa(cnt_en),
+\t.datab((~ wire_parity_regout)),
+\t.ena(1\'b1),
+\t.regout(wire_parity_regout),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tparity.cin_used = ""true"",
+\t\tparity.lut_mask = ""9982"",
+\t\tparity.operation_mode = ""arithmetic"",
+\t\tparity.synch_mode = ""on"",
+\t\tparity.lpm_type = ""cyclone_lcell"";
+\tassign
+\t\tpower_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
+\t\tq = power_modified_counter_values,
+\t\tsclr = 1\'b0,
+\t\tupdown = 1\'b1;
+endmodule //fifo_4k_a_graycounter_3r6
+
+
+//altsyncram ADDRESS_REG_B=""CLOCK1"" DEVICE_FAMILY=""Cyclone"" OPERATION_MODE=""DUAL_PORT"" OUTDATA_REG_B=""UNREGISTERED"" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
+//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = M4K 16 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_altsyncram_8pl
+\t( 
+\taddress_a,
+\taddress_b,
+\tclock0,
+\tclock1,
+\tclocken1,
+\tdata_a,
+\tq_b,
+\twren_a) /* synthesis synthesis_clearbox=1 */;
+\tinput   [11:0]  address_a;
+\tinput   [11:0]  address_b;
+\tinput   clock0;
+\tinput   clock1;
+\tinput   clocken1;
+\tinput   [15:0]  data_a;
+\toutput   [15:0]  q_b;
+\tinput   wren_a;
+
+\twire  [0:0]   wire_ram_block3a_0portbdataout;
+\twire  [0:0]   wire_ram_block3a_1portbdataout;
+\twire  [0:0]   wire_ram_block3a_2portbdataout;
+\twire  [0:0]   wire_ram_block3a_3portbdataout;
+\twire  [0:0]   wire_ram_block3a_4portbdataout;
+\twire  [0:0]   wire_ram_block3a_5portbdataout;
+\twire  [0:0]   wire_ram_block3a_6portbdataout;
+\twire  [0:0]   wire_ram_block3a_7portbdataout;
+\twire  [0:0]   wire_ram_block3a_8portbdataout;
+\twire  [0:0]   wire_ram_block3a_9portbdataout;
+\twire  [0:0]   wire_ram_block3a_10portbdataout;
+\twire  [0:0]   wire_ram_block3a_11portbdataout;
+\twire  [0:0]   wire_ram_block3a_12portbdataout;
+\twire  [0:0]   wire_ram_block3a_13portbdataout;
+\twire  [0:0]   wire_ram_block3a_14portbdataout;
+\twire  [0:0]   wire_ram_block3a_15portbdataout;
+\twire  [11:0]  address_a_wire;
+\twire  [11:0]  address_b_wire;
+
+\tcyclone_ram_block   ram_block3a_0
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[0]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_0.connectivity_checking = ""OFF"",
+\t\tram_block3a_0.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_0.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_0.operation_mode = ""dual_port"",
+\t\tram_block3a_0.port_a_address_width = 12,
+\t\tram_block3a_0.port_a_data_width = 1,
+\t\tram_block3a_0.port_a_first_address = 0,
+\t\tram_block3a_0.port_a_first_bit_number = 0,
+\t\tram_block3a_0.port_a_last_address = 4095,
+\t\tram_block3a_0.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_0.port_a_logical_ram_width = 16,
+\t\tram_block3a_0.port_b_address_clear = ""none"",
+\t\tram_block3a_0.port_b_address_clock = ""clock1"",
+\t\tram_block3a_0.port_b_address_width = 12,
+\t\tram_block3a_0.port_b_data_out_clear = ""none"",
+\t\tram_block3a_0.port_b_data_out_clock = ""none"",
+\t\tram_block3a_0.port_b_data_width = 1,
+\t\tram_block3a_0.port_b_first_address = 0,
+\t\tram_block3a_0.port_b_first_bit_number = 0,
+\t\tram_block3a_0.port_b_last_address = 4095,
+\t\tram_block3a_0.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_0.port_b_logical_ram_width = 16,
+\t\tram_block3a_0.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_0.ram_block_type = ""auto"",
+\t\tram_block3a_0.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_1
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[1]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_1.connectivity_checking = ""OFF"",
+\t\tram_block3a_1.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_1.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_1.operation_mode = ""dual_port"",
+\t\tram_block3a_1.port_a_address_width = 12,
+\t\tram_block3a_1.port_a_data_width = 1,
+\t\tram_block3a_1.port_a_first_address = 0,
+\t\tram_block3a_1.port_a_first_bit_number = 1,
+\t\tram_block3a_1.port_a_last_address = 4095,
+\t\tram_block3a_1.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_1.port_a_logical_ram_width = 16,
+\t\tram_block3a_1.port_b_address_clear = ""none"",
+\t\tram_block3a_1.port_b_address_clock = ""clock1"",
+\t\tram_block3a_1.port_b_address_width = 12,
+\t\tram_block3a_1.port_b_data_out_clear = ""none"",
+\t\tram_block3a_1.port_b_data_out_clock = ""none"",
+\t\tram_block3a_1.port_b_data_width = 1,
+\t\tram_block3a_1.port_b_first_address = 0,
+\t\tram_block3a_1.port_b_first_bit_number = 1,
+\t\tram_block3a_1.port_b_last_address = 4095,
+\t\tram_block3a_1.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_1.port_b_logical_ram_width = 16,
+\t\tram_block3a_1.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_1.ram_block_type = ""auto"",
+\t\tram_block3a_1.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_2
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[2]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_2.connectivity_checking = ""OFF"",
+\t\tram_block3a_2.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_2.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_2.operation_mode = ""dual_port"",
+\t\tram_block3a_2.port_a_address_width = 12,
+\t\tram_block3a_2.port_a_data_width = 1,
+\t\tram_block3a_2.port_a_first_address = 0,
+\t\tram_block3a_2.port_a_first_bit_number = 2,
+\t\tram_block3a_2.port_a_last_address = 4095,
+\t\tram_block3a_2.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_2.port_a_logical_ram_width = 16,
+\t\tram_block3a_2.port_b_address_clear = ""none"",
+\t\tram_block3a_2.port_b_address_clock = ""clock1"",
+\t\tram_block3a_2.port_b_address_width = 12,
+\t\tram_block3a_2.port_b_data_out_clear = ""none"",
+\t\tram_block3a_2.port_b_data_out_clock = ""none"",
+\t\tram_block3a_2.port_b_data_width = 1,
+\t\tram_block3a_2.port_b_first_address = 0,
+\t\tram_block3a_2.port_b_first_bit_number = 2,
+\t\tram_block3a_2.port_b_last_address = 4095,
+\t\tram_block3a_2.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_2.port_b_logical_ram_width = 16,
+\t\tram_block3a_2.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_2.ram_block_type = ""auto"",
+\t\tram_block3a_2.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_3
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[3]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_3.connectivity_checking = ""OFF"",
+\t\tram_block3a_3.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_3.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_3.operation_mode = ""dual_port"",
+\t\tram_block3a_3.port_a_address_width = 12,
+\t\tram_block3a_3.port_a_data_width = 1,
+\t\tram_block3a_3.port_a_first_address = 0,
+\t\tram_block3a_3.port_a_first_bit_number = 3,
+\t\tram_block3a_3.port_a_last_address = 4095,
+\t\tram_block3a_3.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_3.port_a_logical_ram_width = 16,
+\t\tram_block3a_3.port_b_address_clear = ""none"",
+\t\tram_block3a_3.port_b_address_clock = ""clock1"",
+\t\tram_block3a_3.port_b_address_width = 12,
+\t\tram_block3a_3.port_b_data_out_clear = ""none"",
+\t\tram_block3a_3.port_b_data_out_clock = ""none"",
+\t\tram_block3a_3.port_b_data_width = 1,
+\t\tram_block3a_3.port_b_first_address = 0,
+\t\tram_block3a_3.port_b_first_bit_number = 3,
+\t\tram_block3a_3.port_b_last_address = 4095,
+\t\tram_block3a_3.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_3.port_b_logical_ram_width = 16,
+\t\tram_block3a_3.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_3.ram_block_type = ""auto"",
+\t\tram_block3a_3.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_4
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[4]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_4.connectivity_checking = ""OFF"",
+\t\tram_block3a_4.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_4.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_4.operation_mode = ""dual_port"",
+\t\tram_block3a_4.port_a_address_width = 12,
+\t\tram_block3a_4.port_a_data_width = 1,
+\t\tram_block3a_4.port_a_first_address = 0,
+\t\tram_block3a_4.port_a_first_bit_number = 4,
+\t\tram_block3a_4.port_a_last_address = 4095,
+\t\tram_block3a_4.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_4.port_a_logical_ram_width = 16,
+\t\tram_block3a_4.port_b_address_clear = ""none"",
+\t\tram_block3a_4.port_b_address_clock = ""clock1"",
+\t\tram_block3a_4.port_b_address_width = 12,
+\t\tram_block3a_4.port_b_data_out_clear = ""none"",
+\t\tram_block3a_4.port_b_data_out_clock = ""none"",
+\t\tram_block3a_4.port_b_data_width = 1,
+\t\tram_block3a_4.port_b_first_address = 0,
+\t\tram_block3a_4.port_b_first_bit_number = 4,
+\t\tram_block3a_4.port_b_last_address = 4095,
+\t\tram_block3a_4.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_4.port_b_logical_ram_width = 16,
+\t\tram_block3a_4.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_4.ram_block_type = ""auto"",
+\t\tram_block3a_4.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_5
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[5]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_5.connectivity_checking = ""OFF"",
+\t\tram_block3a_5.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_5.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_5.operation_mode = ""dual_port"",
+\t\tram_block3a_5.port_a_address_width = 12,
+\t\tram_block3a_5.port_a_data_width = 1,
+\t\tram_block3a_5.port_a_first_address = 0,
+\t\tram_block3a_5.port_a_first_bit_number = 5,
+\t\tram_block3a_5.port_a_last_address = 4095,
+\t\tram_block3a_5.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_5.port_a_logical_ram_width = 16,
+\t\tram_block3a_5.port_b_address_clear = ""none"",
+\t\tram_block3a_5.port_b_address_clock = ""clock1"",
+\t\tram_block3a_5.port_b_address_width = 12,
+\t\tram_block3a_5.port_b_data_out_clear = ""none"",
+\t\tram_block3a_5.port_b_data_out_clock = ""none"",
+\t\tram_block3a_5.port_b_data_width = 1,
+\t\tram_block3a_5.port_b_first_address = 0,
+\t\tram_block3a_5.port_b_first_bit_number = 5,
+\t\tram_block3a_5.port_b_last_address = 4095,
+\t\tram_block3a_5.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_5.port_b_logical_ram_width = 16,
+\t\tram_block3a_5.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_5.ram_block_type = ""auto"",
+\t\tram_block3a_5.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_6
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[6]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_6.connectivity_checking = ""OFF"",
+\t\tram_block3a_6.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_6.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_6.operation_mode = ""dual_port"",
+\t\tram_block3a_6.port_a_address_width = 12,
+\t\tram_block3a_6.port_a_data_width = 1,
+\t\tram_block3a_6.port_a_first_address = 0,
+\t\tram_block3a_6.port_a_first_bit_number = 6,
+\t\tram_block3a_6.port_a_last_address = 4095,
+\t\tram_block3a_6.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_6.port_a_logical_ram_width = 16,
+\t\tram_block3a_6.port_b_address_clear = ""none"",
+\t\tram_block3a_6.port_b_address_clock = ""clock1"",
+\t\tram_block3a_6.port_b_address_width = 12,
+\t\tram_block3a_6.port_b_data_out_clear = ""none"",
+\t\tram_block3a_6.port_b_data_out_clock = ""none"",
+\t\tram_block3a_6.port_b_data_width = 1,
+\t\tram_block3a_6.port_b_first_address = 0,
+\t\tram_block3a_6.port_b_first_bit_number = 6,
+\t\tram_block3a_6.port_b_last_address = 4095,
+\t\tram_block3a_6.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_6.port_b_logical_ram_width = 16,
+\t\tram_block3a_6.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_6.ram_block_type = ""auto"",
+\t\tram_block3a_6.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_7
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[7]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_7.connectivity_checking = ""OFF"",
+\t\tram_block3a_7.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_7.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_7.operation_mode = ""dual_port"",
+\t\tram_block3a_7.port_a_address_width = 12,
+\t\tram_block3a_7.port_a_data_width = 1,
+\t\tram_block3a_7.port_a_first_address = 0,
+\t\tram_block3a_7.port_a_first_bit_number = 7,
+\t\tram_block3a_7.port_a_last_address = 4095,
+\t\tram_block3a_7.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_7.port_a_logical_ram_width = 16,
+\t\tram_block3a_7.port_b_address_clear = ""none"",
+\t\tram_block3a_7.port_b_address_clock = ""clock1"",
+\t\tram_block3a_7.port_b_address_width = 12,
+\t\tram_block3a_7.port_b_data_out_clear = ""none"",
+\t\tram_block3a_7.port_b_data_out_clock = ""none"",
+\t\tram_block3a_7.port_b_data_width = 1,
+\t\tram_block3a_7.port_b_first_address = 0,
+\t\tram_block3a_7.port_b_first_bit_number = 7,
+\t\tram_block3a_7.port_b_last_address = 4095,
+\t\tram_block3a_7.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_7.port_b_logical_ram_width = 16,
+\t\tram_block3a_7.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_7.ram_block_type = ""auto"",
+\t\tram_block3a_7.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_8
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[8]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_8.connectivity_checking = ""OFF"",
+\t\tram_block3a_8.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_8.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_8.operation_mode = ""dual_port"",
+\t\tram_block3a_8.port_a_address_width = 12,
+\t\tram_block3a_8.port_a_data_width = 1,
+\t\tram_block3a_8.port_a_first_address = 0,
+\t\tram_block3a_8.port_a_first_bit_number = 8,
+\t\tram_block3a_8.port_a_last_address = 4095,
+\t\tram_block3a_8.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_8.port_a_logical_ram_width = 16,
+\t\tram_block3a_8.port_b_address_clear = ""none"",
+\t\tram_block3a_8.port_b_address_clock = ""clock1"",
+\t\tram_block3a_8.port_b_address_width = 12,
+\t\tram_block3a_8.port_b_data_out_clear = ""none"",
+\t\tram_block3a_8.port_b_data_out_clock = ""none"",
+\t\tram_block3a_8.port_b_data_width = 1,
+\t\tram_block3a_8.port_b_first_address = 0,
+\t\tram_block3a_8.port_b_first_bit_number = 8,
+\t\tram_block3a_8.port_b_last_address = 4095,
+\t\tram_block3a_8.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_8.port_b_logical_ram_width = 16,
+\t\tram_block3a_8.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_8.ram_block_type = ""auto"",
+\t\tram_block3a_8.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_9
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[9]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_9.connectivity_checking = ""OFF"",
+\t\tram_block3a_9.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_9.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_9.operation_mode = ""dual_port"",
+\t\tram_block3a_9.port_a_address_width = 12,
+\t\tram_block3a_9.port_a_data_width = 1,
+\t\tram_block3a_9.port_a_first_address = 0,
+\t\tram_block3a_9.port_a_first_bit_number = 9,
+\t\tram_block3a_9.port_a_last_address = 4095,
+\t\tram_block3a_9.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_9.port_a_logical_ram_width = 16,
+\t\tram_block3a_9.port_b_address_clear = ""none"",
+\t\tram_block3a_9.port_b_address_clock = ""clock1"",
+\t\tram_block3a_9.port_b_address_width = 12,
+\t\tram_block3a_9.port_b_data_out_clear = ""none"",
+\t\tram_block3a_9.port_b_data_out_clock = ""none"",
+\t\tram_block3a_9.port_b_data_width = 1,
+\t\tram_block3a_9.port_b_first_address = 0,
+\t\tram_block3a_9.port_b_first_bit_number = 9,
+\t\tram_block3a_9.port_b_last_address = 4095,
+\t\tram_block3a_9.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_9.port_b_logical_ram_width = 16,
+\t\tram_block3a_9.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_9.ram_block_type = ""auto"",
+\t\tram_block3a_9.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_10
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[10]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_10.connectivity_checking = ""OFF"",
+\t\tram_block3a_10.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_10.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_10.operation_mode = ""dual_port"",
+\t\tram_block3a_10.port_a_address_width = 12,
+\t\tram_block3a_10.port_a_data_width = 1,
+\t\tram_block3a_10.port_a_first_address = 0,
+\t\tram_block3a_10.port_a_first_bit_number = 10,
+\t\tram_block3a_10.port_a_last_address = 4095,
+\t\tram_block3a_10.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_10.port_a_logical_ram_width = 16,
+\t\tram_block3a_10.port_b_address_clear = ""none"",
+\t\tram_block3a_10.port_b_address_clock = ""clock1"",
+\t\tram_block3a_10.port_b_address_width = 12,
+\t\tram_block3a_10.port_b_data_out_clear = ""none"",
+\t\tram_block3a_10.port_b_data_out_clock = ""none"",
+\t\tram_block3a_10.port_b_data_width = 1,
+\t\tram_block3a_10.port_b_first_address = 0,
+\t\tram_block3a_10.port_b_first_bit_number = 10,
+\t\tram_block3a_10.port_b_last_address = 4095,
+\t\tram_block3a_10.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_10.port_b_logical_ram_width = 16,
+\t\tram_block3a_10.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_10.ram_block_type = ""auto"",
+\t\tram_block3a_10.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_11
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[11]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_11.connectivity_checking = ""OFF"",
+\t\tram_block3a_11.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_11.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_11.operation_mode = ""dual_port"",
+\t\tram_block3a_11.port_a_address_width = 12,
+\t\tram_block3a_11.port_a_data_width = 1,
+\t\tram_block3a_11.port_a_first_address = 0,
+\t\tram_block3a_11.port_a_first_bit_number = 11,
+\t\tram_block3a_11.port_a_last_address = 4095,
+\t\tram_block3a_11.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_11.port_a_logical_ram_width = 16,
+\t\tram_block3a_11.port_b_address_clear = ""none"",
+\t\tram_block3a_11.port_b_address_clock = ""clock1"",
+\t\tram_block3a_11.port_b_address_width = 12,
+\t\tram_block3a_11.port_b_data_out_clear = ""none"",
+\t\tram_block3a_11.port_b_data_out_clock = ""none"",
+\t\tram_block3a_11.port_b_data_width = 1,
+\t\tram_block3a_11.port_b_first_address = 0,
+\t\tram_block3a_11.port_b_first_bit_number = 11,
+\t\tram_block3a_11.port_b_last_address = 4095,
+\t\tram_block3a_11.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_11.port_b_logical_ram_width = 16,
+\t\tram_block3a_11.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_11.ram_block_type = ""auto"",
+\t\tram_block3a_11.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_12
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[12]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_12.connectivity_checking = ""OFF"",
+\t\tram_block3a_12.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_12.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_12.operation_mode = ""dual_port"",
+\t\tram_block3a_12.port_a_address_width = 12,
+\t\tram_block3a_12.port_a_data_width = 1,
+\t\tram_block3a_12.port_a_first_address = 0,
+\t\tram_block3a_12.port_a_first_bit_number = 12,
+\t\tram_block3a_12.port_a_last_address = 4095,
+\t\tram_block3a_12.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_12.port_a_logical_ram_width = 16,
+\t\tram_block3a_12.port_b_address_clear = ""none"",
+\t\tram_block3a_12.port_b_address_clock = ""clock1"",
+\t\tram_block3a_12.port_b_address_width = 12,
+\t\tram_block3a_12.port_b_data_out_clear = ""none"",
+\t\tram_block3a_12.port_b_data_out_clock = ""none"",
+\t\tram_block3a_12.port_b_data_width = 1,
+\t\tram_block3a_12.port_b_first_address = 0,
+\t\tram_block3a_12.port_b_first_bit_number = 12,
+\t\tram_block3a_12.port_b_last_address = 4095,
+\t\tram_block3a_12.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_12.port_b_logical_ram_width = 16,
+\t\tram_block3a_12.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_12.ram_block_type = ""auto"",
+\t\tram_block3a_12.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_13
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[13]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_13.connectivity_checking = ""OFF"",
+\t\tram_block3a_13.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_13.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_13.operation_mode = ""dual_port"",
+\t\tram_block3a_13.port_a_address_width = 12,
+\t\tram_block3a_13.port_a_data_width = 1,
+\t\tram_block3a_13.port_a_first_address = 0,
+\t\tram_block3a_13.port_a_first_bit_number = 13,
+\t\tram_block3a_13.port_a_last_address = 4095,
+\t\tram_block3a_13.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_13.port_a_logical_ram_width = 16,
+\t\tram_block3a_13.port_b_address_clear = ""none"",
+\t\tram_block3a_13.port_b_address_clock = ""clock1"",
+\t\tram_block3a_13.port_b_address_width = 12,
+\t\tram_block3a_13.port_b_data_out_clear = ""none"",
+\t\tram_block3a_13.port_b_data_out_clock = ""none"",
+\t\tram_block3a_13.port_b_data_width = 1,
+\t\tram_block3a_13.port_b_first_address = 0,
+\t\tram_block3a_13.port_b_first_bit_number = 13,
+\t\tram_block3a_13.port_b_last_address = 4095,
+\t\tram_block3a_13.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_13.port_b_logical_ram_width = 16,
+\t\tram_block3a_13.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_13.ram_block_type = ""auto"",
+\t\tram_block3a_13.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_14
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[14]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_14.connectivity_checking = ""OFF"",
+\t\tram_block3a_14.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_14.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_14.operation_mode = ""dual_port"",
+\t\tram_block3a_14.port_a_address_width = 12,
+\t\tram_block3a_14.port_a_data_width = 1,
+\t\tram_block3a_14.port_a_first_address = 0,
+\t\tram_block3a_14.port_a_first_bit_number = 14,
+\t\tram_block3a_14.port_a_last_address = 4095,
+\t\tram_block3a_14.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_14.port_a_logical_ram_width = 16,
+\t\tram_block3a_14.port_b_address_clear = ""none"",
+\t\tram_block3a_14.port_b_address_clock = ""clock1"",
+\t\tram_block3a_14.port_b_address_width = 12,
+\t\tram_block3a_14.port_b_data_out_clear = ""none"",
+\t\tram_block3a_14.port_b_data_out_clock = ""none"",
+\t\tram_block3a_14.port_b_data_width = 1,
+\t\tram_block3a_14.port_b_first_address = 0,
+\t\tram_block3a_14.port_b_first_bit_number = 14,
+\t\tram_block3a_14.port_b_last_address = 4095,
+\t\tram_block3a_14.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_14.port_b_logical_ram_width = 16,
+\t\tram_block3a_14.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_14.ram_block_type = ""auto"",
+\t\tram_block3a_14.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_15
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[11:0]}),
+\t.portadatain({data_a[15]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[11:0]}),
+\t.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_15.connectivity_checking = ""OFF"",
+\t\tram_block3a_15.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_15.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_15.operation_mode = ""dual_port"",
+\t\tram_block3a_15.port_a_address_width = 12,
+\t\tram_block3a_15.port_a_data_width = 1,
+\t\tram_block3a_15.port_a_first_address = 0,
+\t\tram_block3a_15.port_a_first_bit_number = 15,
+\t\tram_block3a_15.port_a_last_address = 4095,
+\t\tram_block3a_15.port_a_logical_ram_depth = 4096,
+\t\tram_block3a_15.port_a_logical_ram_width = 16,
+\t\tram_block3a_15.port_b_address_clear = ""none"",
+\t\tram_block3a_15.port_b_address_clock = ""clock1"",
+\t\tram_block3a_15.port_b_address_width = 12,
+\t\tram_block3a_15.port_b_data_out_clear = ""none"",
+\t\tram_block3a_15.port_b_data_out_clock = ""none"",
+\t\tram_block3a_15.port_b_data_width = 1,
+\t\tram_block3a_15.port_b_first_address = 0,
+\t\tram_block3a_15.port_b_first_bit_number = 15,
+\t\tram_block3a_15.port_b_last_address = 4095,
+\t\tram_block3a_15.port_b_logical_ram_depth = 4096,
+\t\tram_block3a_15.port_b_logical_ram_width = 16,
+\t\tram_block3a_15.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_15.ram_block_type = ""auto"",
+\t\tram_block3a_15.lpm_type = ""cyclone_ram_block"";
+\tassign
+\t\taddress_a_wire = address_a,
+\t\taddress_b_wire = address_b,
+\t\tq_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
+endmodule //fifo_4k_altsyncram_8pl
+
+
+//dffpipe DELAY=1 WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_dffpipe_bb3
+\t( 
+\tclock,
+\tclrn,
+\td,
+\tq) /* synthesis synthesis_clearbox=1 */
+\t\t/* synthesis ALTERA_ATTRIBUTE=""AUTO_SHIFT_REGISTER_RECOGNITION=OFF"" */;
+\tinput   clock;
+\tinput   clrn;
+\tinput   [11:0]  d;
+\toutput   [11:0]  q;
+
+\twire\t[11:0]\twire_dffe4a_D;
+\treg\t[11:0]\tdffe4a;
+\twire ena;
+\twire prn;
+\twire sclr;
+
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[0:0] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[0:0] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[0:0] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[0:0] <= wire_dffe4a_D[0:0];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[1:1] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[1:1] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[1:1] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[1:1] <= wire_dffe4a_D[1:1];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[2:2] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[2:2] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[2:2] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[2:2] <= wire_dffe4a_D[2:2];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[3:3] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[3:3] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[3:3] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[3:3] <= wire_dffe4a_D[3:3];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[4:4] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[4:4] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[4:4] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[4:4] <= wire_dffe4a_D[4:4];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[5:5] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[5:5] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[5:5] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[5:5] <= wire_dffe4a_D[5:5];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[6:6] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[6:6] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[6:6] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[6:6] <= wire_dffe4a_D[6:6];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[7:7] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[7:7] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[7:7] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[7:7] <= wire_dffe4a_D[7:7];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[8:8] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[8:8] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[8:8] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[8:8] <= wire_dffe4a_D[8:8];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[9:9] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[9:9] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[9:9] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[9:9] <= wire_dffe4a_D[9:9];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[10:10] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[10:10] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[10:10] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[10:10] <= wire_dffe4a_D[10:10];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[11:11] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[11:11] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[11:11] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[11:11] <= wire_dffe4a_D[11:11];
+\tassign
+\t\twire_dffe4a_D = (d & {12{(~ sclr)}});
+\tassign
+\t\tena = 1\'b1,
+\t\tprn = 1\'b1,
+\t\tq = dffe4a,
+\t\tsclr = 1\'b0;
+endmodule //fifo_4k_dffpipe_bb3
+
+
+//dffpipe WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+
+//dffpipe WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_dffpipe_em2
+\t( 
+\tclock,
+\tclrn,
+\td,
+\tq) /* synthesis synthesis_clearbox=1 */
+\t\t/* synthesis ALTERA_ATTRIBUTE=""AUTO_SHIFT_REGISTER_RECOGNITION=OFF"" */;
+\tinput   clock;
+\tinput   clrn;
+\tinput   [11:0]  d;
+\toutput   [11:0]  q;
+
+\twire\t[11:0]\twire_dffe6a_D;
+\treg\t[11:0]\tdffe6a;
+\twire ena;
+\twire prn;
+\twire sclr;
+
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[0:0] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[0:0] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[0:0] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[0:0] <= wire_dffe6a_D[0:0];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[1:1] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[1:1] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[1:1] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[1:1] <= wire_dffe6a_D[1:1];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[2:2] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[2:2] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[2:2] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[2:2] <= wire_dffe6a_D[2:2];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[3:3] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[3:3] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[3:3] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[3:3] <= wire_dffe6a_D[3:3];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[4:4] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[4:4] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[4:4] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[4:4] <= wire_dffe6a_D[4:4];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[5:5] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[5:5] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[5:5] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[5:5] <= wire_dffe6a_D[5:5];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[6:6] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[6:6] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[6:6] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[6:6] <= wire_dffe6a_D[6:6];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[7:7] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[7:7] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[7:7] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[7:7] <= wire_dffe6a_D[7:7];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[8:8] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[8:8] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[8:8] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[8:8] <= wire_dffe6a_D[8:8];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[9:9] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[9:9] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[9:9] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[9:9] <= wire_dffe6a_D[9:9];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[10:10] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[10:10] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[10:10] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[10:10] <= wire_dffe6a_D[10:10];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[11:11] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[11:11] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[11:11] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[11:11] <= wire_dffe6a_D[11:11];
+\tassign
+\t\twire_dffe6a_D = (d & {12{(~ sclr)}});
+\tassign
+\t\tena = 1\'b1,
+\t\tprn = 1\'b1,
+\t\tq = dffe6a,
+\t\tsclr = 1\'b0;
+endmodule //fifo_4k_dffpipe_em2
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_alt_synch_pipe_em2
+\t( 
+\tclock,
+\tclrn,
+\td,
+\tq) /* synthesis synthesis_clearbox=1 */
+\t\t/* synthesis ALTERA_ATTRIBUTE=""X_ON_VIOLATION_OPTION=OFF"" */;
+\tinput   clock;
+\tinput   clrn;
+\tinput   [11:0]  d;
+\toutput   [11:0]  q;
+
+\twire  [11:0]   wire_dffpipe5_q;
+
+\tfifo_4k_dffpipe_em2   dffpipe5
+\t( 
+\t.clock(clock),
+\t.clrn(clrn),
+\t.d(d),
+\t.q(wire_dffpipe5_q));
+\tassign
+\t\tq = wire_dffpipe5_q;
+endmodule //fifo_4k_alt_synch_pipe_em2
+
+
+//lpm_add_sub DEVICE_FAMILY=""Cyclone"" LPM_DIRECTION=""SUB"" LPM_WIDTH=12 dataa datab result
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_add_sub_b18
+\t( 
+\tdataa,
+\tdatab,
+\tresult) /* synthesis synthesis_clearbox=1 */;
+\tinput   [11:0]  dataa;
+\tinput   [11:0]  datab;
+\toutput   [11:0]  result;
+
+\twire  [11:0]   wire_add_sub_cella_combout;
+\twire  [0:0]   wire_add_sub_cella_0cout;
+\twire  [0:0]   wire_add_sub_cella_1cout;
+\twire  [0:0]   wire_add_sub_cella_2cout;
+\twire  [0:0]   wire_add_sub_cella_3cout;
+\twire  [0:0]   wire_add_sub_cella_4cout;
+\twire  [0:0]   wire_add_sub_cella_5cout;
+\twire  [0:0]   wire_add_sub_cella_6cout;
+\twire  [0:0]   wire_add_sub_cella_7cout;
+\twire  [0:0]   wire_add_sub_cella_8cout;
+\twire  [0:0]   wire_add_sub_cella_9cout;
+\twire  [0:0]   wire_add_sub_cella_10cout;
+\twire  [11:0]   wire_add_sub_cella_dataa;
+\twire  [11:0]   wire_add_sub_cella_datab;
+
+\tcyclone_lcell   add_sub_cella_0
+\t( 
+\t.cin(1\'b1),
+\t.combout(wire_add_sub_cella_combout[0:0]),
+\t.cout(wire_add_sub_cella_0cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[0:0]),
+\t.datab(wire_add_sub_cella_datab[0:0]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_0.cin_used = ""true"",
+\t\tadd_sub_cella_0.lut_mask = ""69b2"",
+\t\tadd_sub_cella_0.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_0.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_0.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_1
+\t( 
+\t.cin(wire_add_sub_cella_0cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[1:1]),
+\t.cout(wire_add_sub_cella_1cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[1:1]),
+\t.datab(wire_add_sub_cella_datab[1:1]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_1.cin_used = ""true"",
+\t\tadd_sub_cella_1.lut_mask = ""69b2"",
+\t\tadd_sub_cella_1.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_1.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_1.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_2
+\t( 
+\t.cin(wire_add_sub_cella_1cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[2:2]),
+\t.cout(wire_add_sub_cella_2cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[2:2]),
+\t.datab(wire_add_sub_cella_datab[2:2]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_2.cin_used = ""true"",
+\t\tadd_sub_cella_2.lut_mask = ""69b2"",
+\t\tadd_sub_cella_2.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_2.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_2.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_3
+\t( 
+\t.cin(wire_add_sub_cella_2cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[3:3]),
+\t.cout(wire_add_sub_cella_3cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[3:3]),
+\t.datab(wire_add_sub_cella_datab[3:3]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_3.cin_used = ""true"",
+\t\tadd_sub_cella_3.lut_mask = ""69b2"",
+\t\tadd_sub_cella_3.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_3.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_3.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_4
+\t( 
+\t.cin(wire_add_sub_cella_3cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[4:4]),
+\t.cout(wire_add_sub_cella_4cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[4:4]),
+\t.datab(wire_add_sub_cella_datab[4:4]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_4.cin_used = ""true"",
+\t\tadd_sub_cella_4.lut_mask = ""69b2"",
+\t\tadd_sub_cella_4.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_4.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_4.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_5
+\t( 
+\t.cin(wire_add_sub_cella_4cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[5:5]),
+\t.cout(wire_add_sub_cella_5cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[5:5]),
+\t.datab(wire_add_sub_cella_datab[5:5]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_5.cin_used = ""true"",
+\t\tadd_sub_cella_5.lut_mask = ""69b2"",
+\t\tadd_sub_cella_5.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_5.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_5.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_6
+\t( 
+\t.cin(wire_add_sub_cella_5cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[6:6]),
+\t.cout(wire_add_sub_cella_6cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[6:6]),
+\t.datab(wire_add_sub_cella_datab[6:6]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_6.cin_used = ""true"",
+\t\tadd_sub_cella_6.lut_mask = ""69b2"",
+\t\tadd_sub_cella_6.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_6.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_6.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_7
+\t( 
+\t.cin(wire_add_sub_cella_6cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[7:7]),
+\t.cout(wire_add_sub_cella_7cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[7:7]),
+\t.datab(wire_add_sub_cella_datab[7:7]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_7.cin_used = ""true"",
+\t\tadd_sub_cella_7.lut_mask = ""69b2"",
+\t\tadd_sub_cella_7.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_7.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_7.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_8
+\t( 
+\t.cin(wire_add_sub_cella_7cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[8:8]),
+\t.cout(wire_add_sub_cella_8cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[8:8]),
+\t.datab(wire_add_sub_cella_datab[8:8]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_8.cin_used = ""true"",
+\t\tadd_sub_cella_8.lut_mask = ""69b2"",
+\t\tadd_sub_cella_8.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_8.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_8.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_9
+\t( 
+\t.cin(wire_add_sub_cella_8cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[9:9]),
+\t.cout(wire_add_sub_cella_9cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[9:9]),
+\t.datab(wire_add_sub_cella_datab[9:9]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_9.cin_used = ""true"",
+\t\tadd_sub_cella_9.lut_mask = ""69b2"",
+\t\tadd_sub_cella_9.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_9.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_9.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_10
+\t( 
+\t.cin(wire_add_sub_cella_9cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[10:10]),
+\t.cout(wire_add_sub_cella_10cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[10:10]),
+\t.datab(wire_add_sub_cella_datab[10:10]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_10.cin_used = ""true"",
+\t\tadd_sub_cella_10.lut_mask = ""69b2"",
+\t\tadd_sub_cella_10.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_10.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_10.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_11
+\t( 
+\t.cin(wire_add_sub_cella_10cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[11:11]),
+\t.cout(),
+\t.dataa(wire_add_sub_cella_dataa[11:11]),
+\t.datab(wire_add_sub_cella_datab[11:11]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_11.cin_used = ""true"",
+\t\tadd_sub_cella_11.lut_mask = ""6969"",
+\t\tadd_sub_cella_11.operation_mode = ""normal"",
+\t\tadd_sub_cella_11.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_11.lpm_type = ""cyclone_lcell"";
+\tassign
+\t\twire_add_sub_cella_dataa = dataa,
+\t\twire_add_sub_cella_datab = datab;
+\tassign
+\t\tresult = wire_add_sub_cella_combout;
+endmodule //fifo_4k_add_sub_b18
+
+
+//lpm_compare DEVICE_FAMILY=""Cyclone"" LPM_WIDTH=12 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+
+//lpm_compare DEVICE_FAMILY=""Cyclone"" LPM_WIDTH=12 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 104 M4K 16 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_dcfifo_6cq
+\t( 
+\taclr,
+\tdata,
+\tq,
+\trdclk,
+\trdempty,
+\trdreq,
+\trdusedw,
+\twrclk,
+\twrfull,
+\twrreq,
+\twrusedw) /* synthesis synthesis_clearbox=1 */
+\t\t/* synthesis ALTERA_ATTRIBUTE=""AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \\""rdptr_g|power_modified_counter_values\\"" -to \\""ws_dgrp|dffpipe5|dffe6a\\"" }CUT=ON;{ -from \\""delayed_wrptr_g\\"" -to \\""rs_dgwp|dffpipe5|dffe6a\\"" }CUT=ON"" */;
+\tinput   aclr;
+\tinput   [15:0]  data;
+\toutput   [15:0]  q;
+\tinput   rdclk;
+\toutput   rdempty;
+\tinput   rdreq;
+\toutput   [11:0]  rdusedw;
+\tinput   wrclk;
+\toutput   wrfull;
+\tinput   wrreq;
+\toutput   [11:0]  wrusedw;
+
+\twire  [11:0]   wire_rdptr_g_gray2bin_bin;
+\twire  [11:0]   wire_rs_dgwp_gray2bin_bin;
+\twire  [11:0]   wire_wrptr_g_gray2bin_bin;
+\twire  [11:0]   wire_ws_dgrp_gray2bin_bin;
+\twire  [11:0]   wire_rdptr_g_q;
+\twire  [11:0]   wire_rdptr_g1p_q;
+\twire  [11:0]   wire_wrptr_g1p_q;
+\twire  [15:0]   wire_fifo_ram_q_b;
+\treg\t[11:0]\tdelayed_wrptr_g;
+\treg\t[11:0]\twrptr_g;
+\twire  [11:0]   wire_rs_brp_q;
+\twire  [11:0]   wire_rs_bwp_q;
+\twire  [11:0]   wire_rs_dgwp_q;
+\twire  [11:0]   wire_ws_brp_q;
+\twire  [11:0]   wire_ws_bwp_q;
+\twire  [11:0]   wire_ws_dgrp_q;
+\twire  [11:0]   wire_rdusedw_sub_result;
+\twire  [11:0]   wire_wrusedw_sub_result;
+\treg\twire_rdempty_eq_comp_aeb_int;
+\twire\twire_rdempty_eq_comp_aeb;
+\twire\t[11:0]\twire_rdempty_eq_comp_dataa;
+\twire\t[11:0]\twire_rdempty_eq_comp_datab;
+\treg\twire_wrfull_eq_comp_aeb_int;
+\twire\twire_wrfull_eq_comp_aeb;
+\twire\t[11:0]\twire_wrfull_eq_comp_dataa;
+\twire\t[11:0]\twire_wrfull_eq_comp_datab;
+\twire  int_rdempty;
+\twire  int_wrfull;
+\twire  valid_rdreq;
+\twire  valid_wrreq;
+
+\tfifo_4k_a_gray2bin_9m4   rdptr_g_gray2bin
+\t( 
+\t.bin(wire_rdptr_g_gray2bin_bin),
+\t.gray(wire_rdptr_g_q));
+\tfifo_4k_a_gray2bin_9m4   rs_dgwp_gray2bin
+\t( 
+\t.bin(wire_rs_dgwp_gray2bin_bin),
+\t.gray(wire_rs_dgwp_q));
+\tfifo_4k_a_gray2bin_9m4   wrptr_g_gray2bin
+\t( 
+\t.bin(wire_wrptr_g_gray2bin_bin),
+\t.gray(wrptr_g));
+\tfifo_4k_a_gray2bin_9m4   ws_dgrp_gray2bin
+\t( 
+\t.bin(wire_ws_dgrp_gray2bin_bin),
+\t.gray(wire_ws_dgrp_q));
+\tfifo_4k_a_graycounter_826   rdptr_g
+\t( 
+\t.aclr(aclr),
+\t.clock(rdclk),
+\t.cnt_en(valid_rdreq),
+\t.q(wire_rdptr_g_q));
+\tfifo_4k_a_graycounter_3r6   rdptr_g1p
+\t( 
+\t.aclr(aclr),
+\t.clock(rdclk),
+\t.cnt_en(valid_rdreq),
+\t.q(wire_rdptr_g1p_q));
+\tfifo_4k_a_graycounter_3r6   wrptr_g1p
+\t( 
+\t.aclr(aclr),
+\t.clock(wrclk),
+\t.cnt_en(valid_wrreq),
+\t.q(wire_wrptr_g1p_q));
+\tfifo_4k_altsyncram_8pl   fifo_ram
+\t( 
+\t.address_a(wrptr_g),
+\t.address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
+\t.clock0(wrclk),
+\t.clock1(rdclk),
+\t.clocken1((valid_rdreq | int_rdempty)),
+\t.data_a(data),
+\t.q_b(wire_fifo_ram_q_b),
+\t.wren_a(valid_wrreq));
+\t// synopsys translate_off
+\tinitial
+\t\tdelayed_wrptr_g = 0;
+\t// synopsys translate_on
+\talways @ ( posedge wrclk or  posedge aclr)
+\t\tif (aclr == 1\'b1) delayed_wrptr_g <= 12\'b0;
+\t\telse  delayed_wrptr_g <= wrptr_g;
+\t// synopsys translate_off
+\tinitial
+\t\twrptr_g = 0;
+\t// synopsys translate_on
+\talways @ ( posedge wrclk or  posedge aclr)
+\t\tif (aclr == 1\'b1) wrptr_g <= 12\'b0;
+\t\telse if  (valid_wrreq == 1\'b1)   wrptr_g <= wire_wrptr_g1p_q;
+\tfifo_4k_dffpipe_bb3   rs_brp
+\t( 
+\t.clock(rdclk),
+\t.clrn((~ aclr)),
+\t.d(wire_rdptr_g_gray2bin_bin),
+\t.q(wire_rs_brp_q));
+\tfifo_4k_dffpipe_bb3   rs_bwp
+\t( 
+\t.clock(rdclk),
+\t.clrn((~ aclr)),
+\t.d(wire_rs_dgwp_gray2bin_bin),
+\t.q(wire_rs_bwp_q));
+\tfifo_4k_alt_synch_pipe_em2   rs_dgwp
+\t( 
+\t.clock(rdclk),
+\t.clrn((~ aclr)),
+\t.d(delayed_wrptr_g),
+\t.q(wire_rs_dgwp_q));
+\tfifo_4k_dffpipe_bb3   ws_brp
+\t( 
+\t.clock(wrclk),
+\t.clrn((~ aclr)),
+\t.d(wire_ws_dgrp_gray2bin_bin),
+\t.q(wire_ws_brp_q));
+\tfifo_4k_dffpipe_bb3   ws_bwp
+\t( 
+\t.clock(wrclk),
+\t.clrn((~ aclr)),
+\t.d(wire_wrptr_g_gray2bin_bin),
+\t.q(wire_ws_bwp_q));
+\tfifo_4k_alt_synch_pipe_em2   ws_dgrp
+\t( 
+\t.clock(wrclk),
+\t.clrn((~ aclr)),
+\t.d(wire_rdptr_g_q),
+\t.q(wire_ws_dgrp_q));
+\tfifo_4k_add_sub_b18   rdusedw_sub
+\t( 
+\t.dataa(wire_rs_bwp_q),
+\t.datab(wire_rs_brp_q),
+\t.result(wire_rdusedw_sub_result));
+\tfifo_4k_add_sub_b18   wrusedw_sub
+\t( 
+\t.dataa(wire_ws_bwp_q),
+\t.datab(wire_ws_brp_q),
+\t.result(wire_wrusedw_sub_result));
+\talways @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
+\t\tif (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) 
+\t\t\tbegin
+\t\t\t\twire_rdempty_eq_comp_aeb_int = 1\'b1;
+\t\t\tend
+\t\telse
+\t\t\tbegin
+\t\t\t\twire_rdempty_eq_comp_aeb_int = 1\'b0;
+\t\t\tend
+\tassign
+\t\twire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
+\tassign
+\t\twire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
+\t\twire_rdempty_eq_comp_datab = wire_rd'b'ptr_g_q;
+\talways @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
+\t\tif (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) 
+\t\t\tbegin
+\t\t\t\twire_wrfull_eq_comp_aeb_int = 1\'b1;
+\t\t\tend
+\t\telse
+\t\t\tbegin
+\t\t\t\twire_wrfull_eq_comp_aeb_int = 1\'b0;
+\t\t\tend
+\tassign
+\t\twire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
+\tassign
+\t\twire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
+\t\twire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
+\tassign
+\t\tint_rdempty = wire_rdempty_eq_comp_aeb,
+\t\tint_wrfull = wire_wrfull_eq_comp_aeb,
+\t\tq = wire_fifo_ram_q_b,
+\t\trdempty = int_rdempty,
+\t\trdusedw = wire_rdusedw_sub_result,
+\t\tvalid_rdreq = rdreq,
+\t\tvalid_wrreq = wrreq,
+\t\twrfull = int_wrfull,
+\t\twrusedw = wire_wrusedw_sub_result;
+endmodule //fifo_4k_dcfifo_6cq
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_4k (
+\tdata,
+\twrreq,
+\trdreq,
+\trdclk,
+\twrclk,
+\taclr,
+\tq,
+\trdempty,
+\trdusedw,
+\twrfull,
+\twrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[15:0]  data;
+\tinput\t  wrreq;
+\tinput\t  rdreq;
+\tinput\t  rdclk;
+\tinput\t  wrclk;
+\tinput\t  aclr;
+\toutput\t[15:0]  q;
+\toutput\t  rdempty;
+\toutput\t[11:0]  rdusedw;
+\toutput\t  wrfull;
+\toutput\t[11:0]  wrusedw;
+
+\twire  sub_wire0;
+\twire [11:0] sub_wire1;
+\twire  sub_wire2;
+\twire [15:0] sub_wire3;
+\twire [11:0] sub_wire4;
+\twire  rdempty = sub_wire0;
+\twire [11:0] wrusedw = sub_wire1[11:0];
+\twire  wrfull = sub_wire2;
+\twire [15:0] q = sub_wire3[15:0];
+\twire [11:0] rdusedw = sub_wire4[11:0];
+
+\tfifo_4k_dcfifo_6cq\tfifo_4k_dcfifo_6cq_component (
+\t\t\t\t.wrclk (wrclk),
+\t\t\t\t.rdreq (rdreq),
+\t\t\t\t.aclr (aclr),
+\t\t\t\t.rdclk (rdclk),
+\t\t\t\t.wrreq (wrreq),
+\t\t\t\t.data (data),
+\t\t\t\t.rdempty (sub_wire0),
+\t\t\t\t.wrusedw (sub_wire1),
+\t\t\t\t.wrfull (sub_wire2),
+\t\t\t\t.q (sub_wire3),
+\t\t\t\t.rdusedw (sub_wire4));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC ""16""
+// Retrieval info: PRIVATE: Depth NUMERIC ""4096""
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""
+// Retrieval info: PRIVATE: Full NUMERIC ""1""
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""4096""
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""12""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
+"
+"`timescale 1ns/1ps
+
+module tx_packer
+   (     //FX2 Side
+\t\t\tinput bus_reset, 
+\t\t\tinput usbclk, 
+\t\t\tinput WR_fx2, 
+\t\t\tinput [15:0]usbdata,
+\t\t\t
+\t\t\t// TX Side
+\t\t\tinput reset,
+\t\t\tinput txclk,
+\t\t\toutput reg [31:0] usbdata_final,
+\t\t\toutput reg WR_final,
+         output wire test_bit0,
+ \t\t   output reg test_bit1
+);
+
+\treg [8:0] write_count;
+
+\t/* Fix FX2 bug */
+\talways @(posedge usbclk)
+\tbegin
+    \tif(bus_reset)        // Use bus reset because this is on usbclk
+       \t\twrite_count <= #1 0;
+    \telse if(WR_fx2 & ~write_count[8])
+    \t\twrite_count <= #1 write_count + 9'd1;
+    \telse
+    \t\twrite_count <= #1 WR_fx2 ? write_count : 9'b0;
+\tend
+\t
+\treg WR_fx2_fixed;
+\treg [15:0]usbdata_fixed;
+\t
+\talways @(posedge usbclk) 
+\tbegin
+\t   WR_fx2_fixed <= WR_fx2 & ~write_count[8];
+\t   usbdata_fixed <= usbdata;
+\tend
+
+\t/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
+    reg                             word_complete ;
+    reg     [15:0]         \t\t\tusbdata_delayed ;
+    reg                             writing ;
+\twire\t[31:0]\t\t\t\t\tusbdata_packed ;    
+\twire\t\t\t\t\t\t\tWR_packed ;
+//////////////////////////////////////////////test code
+
+// assign usbdata_xor = ((usbdata_fixed[15] ^ usbdata_fixed[14]) | (usbdata_fixed[13] ^ usbdata_fixed[12]) | 
+//\t\t\t (usbdata_fixed[11] ^ usbdata_fixed[10]) | (usbdata_fixed[9] ^ usbdata_fixed[8])   |
+//\t\t\t (usbdata_fixed[7] ^ usbdata_fixed[6]) |   (usbdata_fixed[5] ^ usbdata_fixed[4])   |
+//  \t                 (usbdata_fixed[3] ^ usbdata_fixed[2]) |   (usbdata_fixed[1] ^ usbdata_fixed[0])   |
+//   \t                 (usbdata_fixed[15] ^ usbdata_fixed[11]) |   (usbdata_fixed[7] ^ usbdata_fixed[3]) |
+//   \t                 (usbdata_fixed[13] ^ usbdata_fixed[9]) |   (usbdata_fixed[5] ^ usbdata_fixed[1])  )
+//                         & WR_fx2_fixed;
+
+  assign usbdata_xor = ((usbdata_fixed[15] & usbdata_fixed[14]) & (usbdata_fixed[13] & usbdata_fixed[12])  & 
+\t\t\t (usbdata_fixed[11] & usbdata_fixed[10]) & (usbdata_fixed[9] & usbdata_fixed[8])   &
+\t\t\t (usbdata_fixed[7] & usbdata_fixed[6]) &   (usbdata_fixed[5] & usbdata_fixed[4])   &
+   \t                 (usbdata_fixed[3] & usbdata_fixed[2]) &   (usbdata_fixed[1] & usbdata_fixed[0])   &
+                          WR_fx2_fixed);
+
+
+ assign test_bit0 = txclk ;\r
+ 
+ //always @(posedge usbclk)
+ //  begin
+ //      test_bit0 <= usbdata_xor;
+ //  end\r
+ \r
+ 
+   
+//////////////////////////////////////////////test code
+   
+   
+    always @(posedge usbclk)
+    begin
+        if (bus_reset)
+          begin
+            word_complete <= 0 ;
+            writing <= 0 ;
+          end
+        else if (WR_fx2_fixed)
+          begin
+            writing <= 1 ;
+            if (word_complete)
+                word_complete <= 0 ;
+            else
+              begin
+                usbdata_delayed <= usbdata_fixed ;
+                word_complete <= 1 ;
+              end
+          end
+        else
+            writing <= 0 ;
+\tend
+    
+\tassign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
+   assign WR_packed = word_complete & writing ;
+
+\t/* Make sure data are sync with usbclk */
+ \treg [31:0]usbdata_usbclk;
+\treg WR_usbclk; 
+    
+    always @(posedge usbclk)
+    begin
+    \tif (WR_packed)
+    \t  usbdata_usbclk <= usbdata_packed;
+        WR_usbclk <= WR_packed;
+    end
+
+\t/* Cross clock boundaries */
+\treg [31:0] usbdata_tx ;
+\treg WR_tx;
+   reg WR_1;
+   reg WR_2;
+  
+\talways @(posedge txclk) usbdata_tx <= usbdata_usbclk;
+
+    always @(posedge txclk) 
+    \tif (reset)
+    \t\tWR_1 <= 0;
+    \telse
+       \t\tWR_1 <= WR_usbclk;
+
+    always @(posedge txclk) 
+    \tif (reset)
+       \t\tWR_2 <= 0;
+    \telse
+      \t\tWR_2 <= WR_1;
+
+\talways @(posedge txclk)
+\tbegin
+\t\tif (reset)
+\t\t\tWR_tx <= 0;
+\t\telse
+\t\t   WR_tx <= WR_1 & ~WR_2;
+\tend
+\t
+\talways @(posedge txclk)
+\tbegin
+\t   if (reset)
+\t      WR_final <= 0;
+\t   else
+\t   begin
+\t      WR_final <= WR_tx; 
+\t      if (WR_tx)
+\t         usbdata_final <= usbdata_tx;
+\t   end
+\tend
+
+///////////////////test output
+\talways @(posedge txclk)
+\tbegin
+\t   if (reset)
+\t     test_bit1 <= 0;
+\t   else if (!WR_final)
+\t     test_bit1 <= test_bit1;
+\t   else if ((usbdata_final == 32'hffff0000))
+    \t           test_bit1 <= 0;
+           else
+    \t           test_bit1 <= 1;
+\t   
+\tend
+
+
+
+   
+
+///////////////////////////////   
+//   always @(posedge usbclk)
+//   begin
+//      if (bus_reset)
+//        begin
+//           test_bit0 <= 1'b0;
+//        end
+//      else if (usbdata_packed[0] ^ usbdata_packed[16])
+//           test_bit0 <= 1'b1;\r
+//\t   else
+//           test_bit0 <= 1'b0;
+//\tend
+   
+\t\r
+\t// Test comparator for 16 bit hi & low data\r
+\t// add new test bit \r
+\t\r
+//\twire    [15:0]   usbpkd_low;\r
+//\twire    [15:0]   usbpkd_hi;\r
+//\t\r
+//\tassign usbpkd_low =  usbdata_delayed;\r
+//\tassign usbpkd_hi =  usbdata_fixed;\r
+//\t\r
+//   always @(posedge usbclk)
+//   begin
+//      if (bus_reset)
+//        begin
+//           test_bit1 <= 1'b0;
+//        end
+//       else\r
+//\t\t   begin\r
+//\t\t\t//  test_bit1 <= (usbpkd_low === usbpkd_hi) ? 1'b1 : 1'b0;\r
+//           if (usbpkd_low == usbpkd_hi)
+//              test_bit1 <= 1'b1;
+//           else
+//              test_bit1 <= 1'b0;\r
+//\t\t\tend\r
+//\tend\r
+
+endmodule
+"
+"//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module accum32 (
+\tdata,
+\tclock,
+\tclken,
+\taclr,
+\tresult)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[31:0]  data;
+\tinput\t  clock;
+\tinput\t  clken;
+\tinput\t  aclr;
+\toutput\t[31:0]  result;
+
+endmodule
+
+"
+"
+
+`include ""../../firmware/include/fpga_regs_common.v""
+`include ""../../firmware/include/fpga_regs_standard.v""
+
+module adc_interface
+  (input clock, input reset, input enable,
+   input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe,
+   input wire [11:0] rx_a_a, input wire [11:0] rx_b_a, input wire [11:0] rx_a_b, input wire [11:0] rx_b_b,
+   output wire [31:0] rssi_0, output wire [31:0] rssi_1, output wire [31:0] rssi_2, output wire [31:0] rssi_3,
+   output reg [15:0] ddc0_in_i, output reg [15:0] ddc0_in_q, 
+   output reg [15:0] ddc1_in_i, output reg [15:0] ddc1_in_q, 
+   output reg [15:0] ddc2_in_i, output reg [15:0] ddc2_in_q, 
+   output reg [15:0] ddc3_in_i, output reg [15:0] ddc3_in_q,
+   output wire [3:0] rx_numchan);
+      
+    // Buffer at input to chip
+   reg [11:0] adc0,adc1,adc2,adc3;
+   always @(posedge clock)
+     begin
+\tadc0 <= #1 rx_a_a;
+\tadc1 <= #1 rx_b_a;
+\tadc2 <= #1 rx_a_b;
+\tadc3 <= #1 rx_b_b;
+     end
+   
+   // then scale and subtract dc offset
+   wire [3:0] dco_en;
+   wire [15:0] \tadc0_corr,adc1_corr,adc2_corr,adc3_corr;
+   
+   setting_reg #(`FR_DC_OFFSET_CL_EN) sr_dco_en(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+\t\t\t\t .out(dco_en));
+
+   rx_dcoffset #(`FR_ADC_OFFSET_0) rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_in({adc0[11],adc0,3\'b0}),.adc_out(adc0_corr),
+\t\t\t\t\t\t.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+   rx_dcoffset #(`FR_ADC_OFFSET_1) rx_dcoffset1(.clock(clock),.enable(dco_en[1]),.reset(reset),.adc_in({adc1[11],adc1,3\'b0}),.adc_out(adc1_corr),
+\t\t\t\t\t\t.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+   rx_dcoffset #(`FR_ADC_OFFSET_2) rx_dcoffset2(.clock(clock),.enable(dco_en[2]),.reset(reset),.adc_in({adc2[11],adc2,3\'b0}),.adc_out(adc2_corr),
+\t\t\t\t\t\t.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+   rx_dcoffset #(`FR_ADC_OFFSET_3) rx_dcoffset3(.clock(clock),.enable(dco_en[3]),.reset(reset),.adc_in({adc3[11],adc3,3\'b0}),.adc_out(adc3_corr),
+\t\t\t\t\t\t.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
+
+   // Level sensing for AGC
+   rssi rssi_block_0 (.clock(clock),.reset(reset),.enable(enable),.adc(adc0),.rssi(rssi_0[15:0]),.over_count(rssi_0[31:16]));
+   rssi rssi_block_1 (.clock(clock),.reset(reset),.enable(enable),.adc(adc1),.rssi(rssi_1[15:0]),.over_count(rssi_1[31:16]));
+   rssi rssi_block_2 (.clock(clock),.reset(reset),.enable(enable),.adc(adc2),.rssi(rssi_2[15:0]),.over_count(rssi_2[31:16]));
+   rssi rssi_block_3 (.clock(clock),.reset(reset),.enable(enable),.adc(adc3),.rssi(rssi_3[15:0]),.over_count(rssi_3[31:16]));
+   
+   // And mux to the appropriate outputs
+   wire [3:0] \tddc3mux,ddc2mux,ddc1mux,ddc0mux;
+   wire \trx_realsignals;
+   
+   setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),
+\t\t\t\t      .in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]}));
+   assign \trx_numchan[0] = 1\'b0;
+   
+   always @(posedge clock)
+     begin
+\tddc0_in_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? adc3_corr : adc2_corr) : (ddc0mux[0] ? adc1_corr : adc0_corr);
+\tddc0_in_q <= #1 rx_realsignals ? 16\'d0 : ddc0mux[3] ? (ddc0mux[2] ? adc3_corr : adc2_corr) : (ddc0mux[2] ? adc1_corr : adc0_corr);
+\tddc1_in_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? adc3_corr : adc2_corr) : (ddc1mux[0] ? adc1_corr : adc0_corr);
+\tddc1_in_q <= #1 rx_realsignals ? 16\'d0 : ddc1mux[3] ? (ddc1mux[2] ? adc3_corr : adc2_corr) : (ddc1mux[2] ? adc1_corr : adc0_corr);
+\tddc2_in_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? adc3_corr : adc2_corr) : (ddc2mux[0] ? adc1_corr : adc0_corr);
+\tddc2_in_q <= #1 rx_realsignals ? 16\'d0 : ddc2mux[3] ? (ddc2mux[2] ? adc3_corr : adc2_corr) : (ddc2mux[2] ? adc1_corr : adc0_corr);
+\tddc3_in_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? adc3_corr : adc2_corr) : (ddc3mux[0] ? adc1_corr : adc0_corr);
+\tddc3_in_q <= #1 rx_realsignals ? 16\'d0 : ddc3mux[3] ? (ddc3mux[2] ? adc3_corr : adc2_corr) : (ddc3mux[2] ? adc1_corr : adc0_corr);
+     end
+
+endmodule // adc_interface
+
+   
+"
+"
+
+module fifo_4k_18
+  (input  [17:0] data,
+   input         wrreq,
+   input         wrclk,
+   output \t wrfull,
+   output \t wrempty,
+   output [11:0] wrusedw,
+
+   output [17:0] q,
+   input         rdreq,
+   input         rdclk,
+   output \t rdfull,
+   output \t rdempty,
+   output [11:0] rdusedw,
+
+   input \t aclr );
+
+fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_4k_18
+
+   
+"
+"// megafunction wizard: %FIFO%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_2k.v
+// Megafunction Name(s):
+// \t\t\tdcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation\'s design tools, logic functions 
+//and other software and tools, and its AMPP partner logic       
+//functions, and any output files any of the foregoing           
+//(including device programming or simulation files), and any    
+//associated documentation or information are expressly subject  
+//to the terms and conditions of the Altera Program License      
+//Subscription Agreement, Altera MegaCore Function License       
+//Agreement, or other applicable license agreement, including,   
+//without limitation, that your use is for the sole purpose of   
+//programming logic devices manufactured by Altera and sold by   
+//Altera or its authorized distributors.  Please refer to the    
+//applicable agreement for further details.
+
+
+//dcfifo ADD_RAM_OUTPUT_REGISTER=""OFF"" CLOCKS_ARE_SYNCHRONIZED=""FALSE"" DEVICE_FAMILY=""Cyclone"" LPM_NUMWORDS=2048 LPM_SHOWAHEAD=""ON"" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING=""OFF"" UNDERFLOW_CHECKING=""OFF"" USE_EAB=""ON"" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+
+//a_gray2bin device_family=""Cyclone"" WIDTH=11 bin gray
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END
+
+//synthesis_resources = 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_a_gray2bin_8m4
+\t( 
+\tbin,
+\tgray) /* synthesis synthesis_clearbox=1 */;
+\toutput   [10:0]  bin;
+\tinput   [10:0]  gray;
+
+\twire  xor0;
+\twire  xor1;
+\twire  xor2;
+\twire  xor3;
+\twire  xor4;
+\twire  xor5;
+\twire  xor6;
+\twire  xor7;
+\twire  xor8;
+\twire  xor9;
+
+\tassign
+\t\tbin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
+\t\txor0 = (gray[0] ^ xor1),
+\t\txor1 = (gray[1] ^ xor2),
+\t\txor2 = (gray[2] ^ xor3),
+\t\txor3 = (gray[3] ^ xor4),
+\t\txor4 = (gray[4] ^ xor5),
+\t\txor5 = (gray[5] ^ xor6),
+\t\txor6 = (gray[6] ^ xor7),
+\t\txor7 = (gray[7] ^ xor8),
+\t\txor8 = (gray[8] ^ xor9),
+\t\txor9 = (gray[10] ^ gray[9]);
+endmodule //fifo_2k_a_gray2bin_8m4
+
+
+//a_graycounter DEVICE_FAMILY=""Cyclone"" WIDTH=11 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_a_graycounter_726
+\t( 
+\taclr,
+\tclock,
+\tcnt_en,
+\tq) /* synthesis synthesis_clearbox=1 */;
+\tinput   aclr;
+\tinput   clock;
+\tinput   cnt_en;
+\toutput   [10:0]  q;
+
+\twire  [0:0]   wire_countera_0cout;
+\twire  [0:0]   wire_countera_1cout;
+\twire  [0:0]   wire_countera_2cout;
+\twire  [0:0]   wire_countera_3cout;
+\twire  [0:0]   wire_countera_4cout;
+\twire  [0:0]   wire_countera_5cout;
+\twire  [0:0]   wire_countera_6cout;
+\twire  [0:0]   wire_countera_7cout;
+\twire  [0:0]   wire_countera_8cout;
+\twire  [0:0]   wire_countera_9cout;
+\twire  [10:0]   wire_countera_regout;
+\twire  wire_parity_cout;
+\twire  wire_parity_regout;
+\twire  [10:0]  power_modified_counter_values;
+\twire sclr;
+\twire updown;
+
+\tcyclone_lcell   countera_0
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_parity_cout),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_0cout[0:0]),
+\t.dataa(cnt_en),
+\t.datab(wire_countera_regout[0:0]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[0:0]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_0.cin_used = ""true"",
+\t\tcountera_0.lut_mask = ""c6a0"",
+\t\tcountera_0.operation_mode = ""arithmetic"",
+\t\tcountera_0.sum_lutc_input = ""cin"",
+\t\tcountera_0.synch_mode = ""on"",
+\t\tcountera_0.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_1
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_0cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_1cout[0:0]),
+\t.dataa(power_modified_counter_values[0]),
+\t.datab(power_modified_counter_values[1]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[1:1]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_1.cin_used = ""true"",
+\t\tcountera_1.lut_mask = ""6c50"",
+\t\tcountera_1.operation_mode = ""arithmetic"",
+\t\tcountera_1.sum_lutc_input = ""cin"",
+\t\tcountera_1.synch_mode = ""on"",
+\t\tcountera_1.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_2
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_1cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_2cout[0:0]),
+\t.dataa(power_modified_counter_values[1]),
+\t.datab(power_modified_counter_values[2]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[2:2]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_2.cin_used = ""true"",
+\t\tcountera_2.lut_mask = ""6c50"",
+\t\tcountera_2.operation_mode = ""arithmetic"",
+\t\tcountera_2.sum_lutc_input = ""cin"",
+\t\tcountera_2.synch_mode = ""on"",
+\t\tcountera_2.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_3
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_2cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_3cout[0:0]),
+\t.dataa(power_modified_counter_values[2]),
+\t.datab(power_modified_counter_values[3]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[3:3]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_3.cin_used = ""true"",
+\t\tcountera_3.lut_mask = ""6c50"",
+\t\tcountera_3.operation_mode = ""arithmetic"",
+\t\tcountera_3.sum_lutc_input = ""cin"",
+\t\tcountera_3.synch_mode = ""on"",
+\t\tcountera_3.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_4
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_3cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_4cout[0:0]),
+\t.dataa(power_modified_counter_values[3]),
+\t.datab(power_modified_counter_values[4]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[4:4]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_4.cin_used = ""true"",
+\t\tcountera_4.lut_mask = ""6c50"",
+\t\tcountera_4.operation_mode = ""arithmetic"",
+\t\tcountera_4.sum_lutc_input = ""cin"",
+\t\tcountera_4.synch_mode = ""on"",
+\t\tcountera_4.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_5
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_4cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_5cout[0:0]),
+\t.dataa(power_modified_counter_values[4]),
+\t.datab(power_modified_counter_values[5]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[5:5]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_5.cin_used = ""true"",
+\t\tcountera_5.lut_mask = ""6c50"",
+\t\tcountera_5.operation_mode = ""arithmetic"",
+\t\tcountera_5.sum_lutc_input = ""cin"",
+\t\tcountera_5.synch_mode = ""on"",
+\t\tcountera_5.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_6
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_5cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_6cout[0:0]),
+\t.dataa(power_modified_counter_values[5]),
+\t.datab(power_modified_counter_values[6]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[6:6]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_6.cin_used = ""true"",
+\t\tcountera_6.lut_mask = ""6c50"",
+\t\tcountera_6.operation_mode = ""arithmetic"",
+\t\tcountera_6.sum_lutc_input = ""cin"",
+\t\tcountera_6.synch_mode = ""on"",
+\t\tcountera_6.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_7
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_6cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_7cout[0:0]),
+\t.dataa(power_modified_counter_values[6]),
+\t.datab(power_modified_counter_values[7]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[7:7]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_7.cin_used = ""true"",
+\t\tcountera_7.lut_mask = ""6c50"",
+\t\tcountera_7.operation_mode = ""arithmetic"",
+\t\tcountera_7.sum_lutc_input = ""cin"",
+\t\tcountera_7.synch_mode = ""on"",
+\t\tcountera_7.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_8
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_7cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_8cout[0:0]),
+\t.dataa(power_modified_counter_values[7]),
+\t.datab(power_modified_counter_values[8]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[8:8]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_8.cin_used = ""true"",
+\t\tcountera_8.lut_mask = ""6c50"",
+\t\tcountera_8.operation_mode = ""arithmetic"",
+\t\tcountera_8.sum_lutc_input = ""cin"",
+\t\tcountera_8.synch_mode = ""on"",
+\t\tcountera_8.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_9
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_8cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_9cout[0:0]),
+\t.dataa(power_modified_counter_values[8]),
+\t.datab(power_modified_counter_values[9]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[9:9]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_9.cin_used = ""true"",
+\t\tcountera_9.lut_mask = ""6c50"",
+\t\tcountera_9.operation_mode = ""arithmetic"",
+\t\tcountera_9.sum_lutc_input = ""cin"",
+\t\tcountera_9.synch_mode = ""on"",
+\t\tcountera_9.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_10
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_9cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(),
+\t.dataa(power_modified_counter_values[10]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[10:10]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datab(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_10.cin_used = ""true"",
+\t\tcountera_10.lut_mask = ""5a5a"",
+\t\tcountera_10.operation_mode = ""normal"",
+\t\tcountera_10.sum_lutc_input = ""cin"",
+\t\tcountera_10.synch_mode = ""on"",
+\t\tcountera_10.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   parity
+\t( 
+\t.aclr(aclr),
+\t.cin(updown),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_parity_cout),
+\t.dataa(cnt_en),
+\t.datab(wire_parity_regout),
+\t.ena(1\'b1),
+\t.regout(wire_parity_regout),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tparity.cin_used = ""true"",
+\t\tparity.lut_mask = ""6682"",
+\t\tparity.operation_mode = ""arithmetic"",
+\t\tparity.synch_mode = ""on"",
+\t\tparity.lpm_type = ""cyclone_lcell"";
+\tassign
+\t\tpower_modified_counter_values = {wire_countera_regout[10:0]},
+\t\tq = power_modified_counter_values,
+\t\tsclr = 1\'b0,
+\t\tupdown = 1\'b1;
+endmodule //fifo_2k_a_graycounter_726
+
+
+//a_graycounter DEVICE_FAMILY=""Cyclone"" PVALUE=1 WIDTH=11 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_a_graycounter_2r6
+\t( 
+\taclr,
+\tclock,
+\tcnt_en,
+\tq) /* synthesis synthesis_clearbox=1 */;
+\tinput   aclr;
+\tinput   clock;
+\tinput   cnt_en;
+\toutput   [10:0]  q;
+
+\twire  [0:0]   wire_countera_0cout;
+\twire  [0:0]   wire_countera_1cout;
+\twire  [0:0]   wire_countera_2cout;
+\twire  [0:0]   wire_countera_3cout;
+\twire  [0:0]   wire_countera_4cout;
+\twire  [0:0]   wire_countera_5cout;
+\twire  [0:0]   wire_countera_6cout;
+\twire  [0:0]   wire_countera_7cout;
+\twire  [0:0]   wire_countera_8cout;
+\twire  [0:0]   wire_countera_9cout;
+\twire  [10:0]   wire_countera_regout;
+\twire  wire_parity_cout;
+\twire  wire_parity_regout;
+\twire  [10:0]  power_modified_counter_values;
+\twire sclr;
+\twire updown;
+
+\tcyclone_lcell   countera_0
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_parity_cout),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_0cout[0:0]),
+\t.dataa(cnt_en),
+\t.datab(wire_countera_regout[0:0]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[0:0]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_0.cin_used = ""true"",
+\t\tcountera_0.lut_mask = ""c6a0"",
+\t\tcountera_0.operation_mode = ""arithmetic"",
+\t\tcountera_0.sum_lutc_input = ""cin"",
+\t\tcountera_0.synch_mode = ""on"",
+\t\tcountera_0.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_1
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_0cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_1cout[0:0]),
+\t.dataa(power_modified_counter_values[0]),
+\t.datab(power_modified_counter_values[1]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[1:1]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_1.cin_used = ""true"",
+\t\tcountera_1.lut_mask = ""6c50"",
+\t\tcountera_1.operation_mode = ""arithmetic"",
+\t\tcountera_1.sum_lutc_input = ""cin"",
+\t\tcountera_1.synch_mode = ""on"",
+\t\tcountera_1.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_2
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_1cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_2cout[0:0]),
+\t.dataa(power_modified_counter_values[1]),
+\t.datab(power_modified_counter_values[2]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[2:2]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_2.cin_used = ""true"",
+\t\tcountera_2.lut_mask = ""6c50"",
+\t\tcountera_2.operation_mode = ""arithmetic"",
+\t\tcountera_2.sum_lutc_input = ""cin"",
+\t\tcountera_2.synch_mode = ""on"",
+\t\tcountera_2.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_3
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_2cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_3cout[0:0]),
+\t.dataa(power_modified_counter_values[2]),
+\t.datab(power_modified_counter_values[3]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[3:3]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_3.cin_used = ""true"",
+\t\tcountera_3.lut_mask = ""6c50"",
+\t\tcountera_3.operation_mode = ""arithmetic"",
+\t\tcountera_3.sum_lutc_input = ""cin"",
+\t\tcountera_3.synch_mode = ""on"",
+\t\tcountera_3.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_4
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_3cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_4cout[0:0]),
+\t.dataa(power_modified_counter_values[3]),
+\t.datab(power_modified_counter_values[4]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[4:4]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_4.cin_used = ""true"",
+\t\tcountera_4.lut_mask = ""6c50"",
+\t\tcountera_4.operation_mode = ""arithmetic"",
+\t\tcountera_4.sum_lutc_input = ""cin"",
+\t\tcountera_4.synch_mode = ""on"",
+\t\tcountera_4.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_5
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_4cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_5cout[0:0]),
+\t.dataa(power_modified_counter_values[4]),
+\t.datab(power_modified_counter_values[5]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[5:5]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_5.cin_used = ""true"",
+\t\tcountera_5.lut_mask = ""6c50"",
+\t\tcountera_5.operation_mode = ""arithmetic"",
+\t\tcountera_5.sum_lutc_input = ""cin"",
+\t\tcountera_5.synch_mode = ""on"",
+\t\tcountera_5.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_6
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_5cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_6cout[0:0]),
+\t.dataa(power_modified_counter_values[5]),
+\t.datab(power_modified_counter_values[6]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[6:6]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_6.cin_used = ""true"",
+\t\tcountera_6.lut_mask = ""6c50"",
+\t\tcountera_6.operation_mode = ""arithmetic"",
+\t\tcountera_6.sum_lutc_input = ""cin"",
+\t\tcountera_6.synch_mode = ""on"",
+\t\tcountera_6.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_7
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_6cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_7cout[0:0]),
+\t.dataa(power_modified_counter_values[6]),
+\t.datab(power_modified_counter_values[7]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[7:7]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_7.cin_used = ""true"",
+\t\tcountera_7.lut_mask = ""6c50"",
+\t\tcountera_7.operation_mode = ""arithmetic"",
+\t\tcountera_7.sum_lutc_input = ""cin"",
+\t\tcountera_7.synch_mode = ""on"",
+\t\tcountera_7.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_8
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_7cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_8cout[0:0]),
+\t.dataa(power_modified_counter_values[7]),
+\t.datab(power_modified_counter_values[8]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[8:8]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_8.cin_used = ""true"",
+\t\tcountera_8.lut_mask = ""6c50"",
+\t\tcountera_8.operation_mode = ""arithmetic"",
+\t\tcountera_8.sum_lutc_input = ""cin"",
+\t\tcountera_8.synch_mode = ""on"",
+\t\tcountera_8.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_9
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_8cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_countera_9cout[0:0]),
+\t.dataa(power_modified_counter_values[8]),
+\t.datab(power_modified_counter_values[9]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[9:9]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_9.cin_used = ""true"",
+\t\tcountera_9.lut_mask = ""6c50"",
+\t\tcountera_9.operation_mode = ""arithmetic"",
+\t\tcountera_9.sum_lutc_input = ""cin"",
+\t\tcountera_9.synch_mode = ""on"",
+\t\tcountera_9.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   countera_10
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_countera_9cout[0:0]),
+\t.clk(clock),
+\t.combout(),
+\t.cout(),
+\t.dataa(power_modified_counter_values[10]),
+\t.ena(1\'b1),
+\t.regout(wire_countera_regout[10:10]),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datab(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tcountera_10.cin_used = ""true"",
+\t\tcountera_10.lut_mask = ""5a5a"",
+\t\tcountera_10.operation_mode = ""normal"",
+\t\tcountera_10.sum_lutc_input = ""cin"",
+\t\tcountera_10.synch_mode = ""on"",
+\t\tcountera_10.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   parity
+\t( 
+\t.aclr(aclr),
+\t.cin(updown),
+\t.clk(clock),
+\t.combout(),
+\t.cout(wire_parity_cout),
+\t.dataa(cnt_en),
+\t.datab((~ wire_parity_regout)),
+\t.ena(1\'b1),
+\t.regout(wire_parity_regout),
+\t.sclr(sclr)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aload(1\'b0),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tparity.cin_used = ""true"",
+\t\tparity.lut_mask = ""9982"",
+\t\tparity.operation_mode = ""arithmetic"",
+\t\tparity.synch_mode = ""on"",
+\t\tparity.lpm_type = ""cyclone_lcell"";
+\tassign
+\t\tpower_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])},
+\t\tq = power_modified_counter_values,
+\t\tsclr = 1\'b0,
+\t\tupdown = 1\'b1;
+endmodule //fifo_2k_a_graycounter_2r6
+
+
+//altsyncram ADDRESS_REG_B=""CLOCK1"" DEVICE_FAMILY=""Cyclone"" OPERATION_MODE=""DUAL_PORT"" OUTDATA_REG_B=""UNREGISTERED"" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
+//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = M4K 8 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_altsyncram_6pl
+\t( 
+\taddress_a,
+\taddress_b,
+\tclock0,
+\tclock1,
+\tclocken1,
+\tdata_a,
+\tq_b,
+\twren_a) /* synthesis synthesis_clearbox=1 */;
+\tinput   [10:0]  address_a;
+\tinput   [10:0]  address_b;
+\tinput   clock0;
+\tinput   clock1;
+\tinput   clocken1;
+\tinput   [15:0]  data_a;
+\toutput   [15:0]  q_b;
+\tinput   wren_a;
+
+\twire  [0:0]   wire_ram_block3a_0portbdataout;
+\twire  [0:0]   wire_ram_block3a_1portbdataout;
+\twire  [0:0]   wire_ram_block3a_2portbdataout;
+\twire  [0:0]   wire_ram_block3a_3portbdataout;
+\twire  [0:0]   wire_ram_block3a_4portbdataout;
+\twire  [0:0]   wire_ram_block3a_5portbdataout;
+\twire  [0:0]   wire_ram_block3a_6portbdataout;
+\twire  [0:0]   wire_ram_block3a_7portbdataout;
+\twire  [0:0]   wire_ram_block3a_8portbdataout;
+\twire  [0:0]   wire_ram_block3a_9portbdataout;
+\twire  [0:0]   wire_ram_block3a_10portbdataout;
+\twire  [0:0]   wire_ram_block3a_11portbdataout;
+\twire  [0:0]   wire_ram_block3a_12portbdataout;
+\twire  [0:0]   wire_ram_block3a_13portbdataout;
+\twire  [0:0]   wire_ram_block3a_14portbdataout;
+\twire  [0:0]   wire_ram_block3a_15portbdataout;
+\twire  [10:0]  address_a_wire;
+\twire  [10:0]  address_b_wire;
+
+\tcyclone_ram_block   ram_block3a_0
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[0]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_0.connectivity_checking = ""OFF"",
+\t\tram_block3a_0.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_0.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_0.operation_mode = ""dual_port"",
+\t\tram_block3a_0.port_a_address_width = 11,
+\t\tram_block3a_0.port_a_data_width = 1,
+\t\tram_block3a_0.port_a_first_address = 0,
+\t\tram_block3a_0.port_a_first_bit_number = 0,
+\t\tram_block3a_0.port_a_last_address = 2047,
+\t\tram_block3a_0.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_0.port_a_logical_ram_width = 16,
+\t\tram_block3a_0.port_b_address_clear = ""none"",
+\t\tram_block3a_0.port_b_address_clock = ""clock1"",
+\t\tram_block3a_0.port_b_address_width = 11,
+\t\tram_block3a_0.port_b_data_out_clear = ""none"",
+\t\tram_block3a_0.port_b_data_out_clock = ""none"",
+\t\tram_block3a_0.port_b_data_width = 1,
+\t\tram_block3a_0.port_b_first_address = 0,
+\t\tram_block3a_0.port_b_first_bit_number = 0,
+\t\tram_block3a_0.port_b_last_address = 2047,
+\t\tram_block3a_0.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_0.port_b_logical_ram_width = 16,
+\t\tram_block3a_0.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_0.ram_block_type = ""auto"",
+\t\tram_block3a_0.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_1
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[1]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_1.connectivity_checking = ""OFF"",
+\t\tram_block3a_1.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_1.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_1.operation_mode = ""dual_port"",
+\t\tram_block3a_1.port_a_address_width = 11,
+\t\tram_block3a_1.port_a_data_width = 1,
+\t\tram_block3a_1.port_a_first_address = 0,
+\t\tram_block3a_1.port_a_first_bit_number = 1,
+\t\tram_block3a_1.port_a_last_address = 2047,
+\t\tram_block3a_1.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_1.port_a_logical_ram_width = 16,
+\t\tram_block3a_1.port_b_address_clear = ""none"",
+\t\tram_block3a_1.port_b_address_clock = ""clock1"",
+\t\tram_block3a_1.port_b_address_width = 11,
+\t\tram_block3a_1.port_b_data_out_clear = ""none"",
+\t\tram_block3a_1.port_b_data_out_clock = ""none"",
+\t\tram_block3a_1.port_b_data_width = 1,
+\t\tram_block3a_1.port_b_first_address = 0,
+\t\tram_block3a_1.port_b_first_bit_number = 1,
+\t\tram_block3a_1.port_b_last_address = 2047,
+\t\tram_block3a_1.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_1.port_b_logical_ram_width = 16,
+\t\tram_block3a_1.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_1.ram_block_type = ""auto"",
+\t\tram_block3a_1.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_2
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[2]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_2.connectivity_checking = ""OFF"",
+\t\tram_block3a_2.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_2.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_2.operation_mode = ""dual_port"",
+\t\tram_block3a_2.port_a_address_width = 11,
+\t\tram_block3a_2.port_a_data_width = 1,
+\t\tram_block3a_2.port_a_first_address = 0,
+\t\tram_block3a_2.port_a_first_bit_number = 2,
+\t\tram_block3a_2.port_a_last_address = 2047,
+\t\tram_block3a_2.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_2.port_a_logical_ram_width = 16,
+\t\tram_block3a_2.port_b_address_clear = ""none"",
+\t\tram_block3a_2.port_b_address_clock = ""clock1"",
+\t\tram_block3a_2.port_b_address_width = 11,
+\t\tram_block3a_2.port_b_data_out_clear = ""none"",
+\t\tram_block3a_2.port_b_data_out_clock = ""none"",
+\t\tram_block3a_2.port_b_data_width = 1,
+\t\tram_block3a_2.port_b_first_address = 0,
+\t\tram_block3a_2.port_b_first_bit_number = 2,
+\t\tram_block3a_2.port_b_last_address = 2047,
+\t\tram_block3a_2.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_2.port_b_logical_ram_width = 16,
+\t\tram_block3a_2.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_2.ram_block_type = ""auto"",
+\t\tram_block3a_2.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_3
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[3]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_3.connectivity_checking = ""OFF"",
+\t\tram_block3a_3.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_3.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_3.operation_mode = ""dual_port"",
+\t\tram_block3a_3.port_a_address_width = 11,
+\t\tram_block3a_3.port_a_data_width = 1,
+\t\tram_block3a_3.port_a_first_address = 0,
+\t\tram_block3a_3.port_a_first_bit_number = 3,
+\t\tram_block3a_3.port_a_last_address = 2047,
+\t\tram_block3a_3.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_3.port_a_logical_ram_width = 16,
+\t\tram_block3a_3.port_b_address_clear = ""none"",
+\t\tram_block3a_3.port_b_address_clock = ""clock1"",
+\t\tram_block3a_3.port_b_address_width = 11,
+\t\tram_block3a_3.port_b_data_out_clear = ""none"",
+\t\tram_block3a_3.port_b_data_out_clock = ""none"",
+\t\tram_block3a_3.port_b_data_width = 1,
+\t\tram_block3a_3.port_b_first_address = 0,
+\t\tram_block3a_3.port_b_first_bit_number = 3,
+\t\tram_block3a_3.port_b_last_address = 2047,
+\t\tram_block3a_3.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_3.port_b_logical_ram_width = 16,
+\t\tram_block3a_3.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_3.ram_block_type = ""auto"",
+\t\tram_block3a_3.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_4
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[4]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_4.connectivity_checking = ""OFF"",
+\t\tram_block3a_4.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_4.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_4.operation_mode = ""dual_port"",
+\t\tram_block3a_4.port_a_address_width = 11,
+\t\tram_block3a_4.port_a_data_width = 1,
+\t\tram_block3a_4.port_a_first_address = 0,
+\t\tram_block3a_4.port_a_first_bit_number = 4,
+\t\tram_block3a_4.port_a_last_address = 2047,
+\t\tram_block3a_4.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_4.port_a_logical_ram_width = 16,
+\t\tram_block3a_4.port_b_address_clear = ""none"",
+\t\tram_block3a_4.port_b_address_clock = ""clock1"",
+\t\tram_block3a_4.port_b_address_width = 11,
+\t\tram_block3a_4.port_b_data_out_clear = ""none"",
+\t\tram_block3a_4.port_b_data_out_clock = ""none"",
+\t\tram_block3a_4.port_b_data_width = 1,
+\t\tram_block3a_4.port_b_first_address = 0,
+\t\tram_block3a_4.port_b_first_bit_number = 4,
+\t\tram_block3a_4.port_b_last_address = 2047,
+\t\tram_block3a_4.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_4.port_b_logical_ram_width = 16,
+\t\tram_block3a_4.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_4.ram_block_type = ""auto"",
+\t\tram_block3a_4.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_5
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[5]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_5.connectivity_checking = ""OFF"",
+\t\tram_block3a_5.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_5.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_5.operation_mode = ""dual_port"",
+\t\tram_block3a_5.port_a_address_width = 11,
+\t\tram_block3a_5.port_a_data_width = 1,
+\t\tram_block3a_5.port_a_first_address = 0,
+\t\tram_block3a_5.port_a_first_bit_number = 5,
+\t\tram_block3a_5.port_a_last_address = 2047,
+\t\tram_block3a_5.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_5.port_a_logical_ram_width = 16,
+\t\tram_block3a_5.port_b_address_clear = ""none"",
+\t\tram_block3a_5.port_b_address_clock = ""clock1"",
+\t\tram_block3a_5.port_b_address_width = 11,
+\t\tram_block3a_5.port_b_data_out_clear = ""none"",
+\t\tram_block3a_5.port_b_data_out_clock = ""none"",
+\t\tram_block3a_5.port_b_data_width = 1,
+\t\tram_block3a_5.port_b_first_address = 0,
+\t\tram_block3a_5.port_b_first_bit_number = 5,
+\t\tram_block3a_5.port_b_last_address = 2047,
+\t\tram_block3a_5.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_5.port_b_logical_ram_width = 16,
+\t\tram_block3a_5.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_5.ram_block_type = ""auto"",
+\t\tram_block3a_5.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_6
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[6]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_6.connectivity_checking = ""OFF"",
+\t\tram_block3a_6.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_6.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_6.operation_mode = ""dual_port"",
+\t\tram_block3a_6.port_a_address_width = 11,
+\t\tram_block3a_6.port_a_data_width = 1,
+\t\tram_block3a_6.port_a_first_address = 0,
+\t\tram_block3a_6.port_a_first_bit_number = 6,
+\t\tram_block3a_6.port_a_last_address = 2047,
+\t\tram_block3a_6.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_6.port_a_logical_ram_width = 16,
+\t\tram_block3a_6.port_b_address_clear = ""none"",
+\t\tram_block3a_6.port_b_address_clock = ""clock1"",
+\t\tram_block3a_6.port_b_address_width = 11,
+\t\tram_block3a_6.port_b_data_out_clear = ""none"",
+\t\tram_block3a_6.port_b_data_out_clock = ""none"",
+\t\tram_block3a_6.port_b_data_width = 1,
+\t\tram_block3a_6.port_b_first_address = 0,
+\t\tram_block3a_6.port_b_first_bit_number = 6,
+\t\tram_block3a_6.port_b_last_address = 2047,
+\t\tram_block3a_6.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_6.port_b_logical_ram_width = 16,
+\t\tram_block3a_6.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_6.ram_block_type = ""auto"",
+\t\tram_block3a_6.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_7
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[7]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_7.connectivity_checking = ""OFF"",
+\t\tram_block3a_7.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_7.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_7.operation_mode = ""dual_port"",
+\t\tram_block3a_7.port_a_address_width = 11,
+\t\tram_block3a_7.port_a_data_width = 1,
+\t\tram_block3a_7.port_a_first_address = 0,
+\t\tram_block3a_7.port_a_first_bit_number = 7,
+\t\tram_block3a_7.port_a_last_address = 2047,
+\t\tram_block3a_7.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_7.port_a_logical_ram_width = 16,
+\t\tram_block3a_7.port_b_address_clear = ""none"",
+\t\tram_block3a_7.port_b_address_clock = ""clock1"",
+\t\tram_block3a_7.port_b_address_width = 11,
+\t\tram_block3a_7.port_b_data_out_clear = ""none"",
+\t\tram_block3a_7.port_b_data_out_clock = ""none"",
+\t\tram_block3a_7.port_b_data_width = 1,
+\t\tram_block3a_7.port_b_first_address = 0,
+\t\tram_block3a_7.port_b_first_bit_number = 7,
+\t\tram_block3a_7.port_b_last_address = 2047,
+\t\tram_block3a_7.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_7.port_b_logical_ram_width = 16,
+\t\tram_block3a_7.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_7.ram_block_type = ""auto"",
+\t\tram_block3a_7.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_8
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[8]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_8.connectivity_checking = ""OFF"",
+\t\tram_block3a_8.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_8.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_8.operation_mode = ""dual_port"",
+\t\tram_block3a_8.port_a_address_width = 11,
+\t\tram_block3a_8.port_a_data_width = 1,
+\t\tram_block3a_8.port_a_first_address = 0,
+\t\tram_block3a_8.port_a_first_bit_number = 8,
+\t\tram_block3a_8.port_a_last_address = 2047,
+\t\tram_block3a_8.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_8.port_a_logical_ram_width = 16,
+\t\tram_block3a_8.port_b_address_clear = ""none"",
+\t\tram_block3a_8.port_b_address_clock = ""clock1"",
+\t\tram_block3a_8.port_b_address_width = 11,
+\t\tram_block3a_8.port_b_data_out_clear = ""none"",
+\t\tram_block3a_8.port_b_data_out_clock = ""none"",
+\t\tram_block3a_8.port_b_data_width = 1,
+\t\tram_block3a_8.port_b_first_address = 0,
+\t\tram_block3a_8.port_b_first_bit_number = 8,
+\t\tram_block3a_8.port_b_last_address = 2047,
+\t\tram_block3a_8.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_8.port_b_logical_ram_width = 16,
+\t\tram_block3a_8.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_8.ram_block_type = ""auto"",
+\t\tram_block3a_8.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_9
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[9]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_9.connectivity_checking = ""OFF"",
+\t\tram_block3a_9.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_9.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_9.operation_mode = ""dual_port"",
+\t\tram_block3a_9.port_a_address_width = 11,
+\t\tram_block3a_9.port_a_data_width = 1,
+\t\tram_block3a_9.port_a_first_address = 0,
+\t\tram_block3a_9.port_a_first_bit_number = 9,
+\t\tram_block3a_9.port_a_last_address = 2047,
+\t\tram_block3a_9.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_9.port_a_logical_ram_width = 16,
+\t\tram_block3a_9.port_b_address_clear = ""none"",
+\t\tram_block3a_9.port_b_address_clock = ""clock1"",
+\t\tram_block3a_9.port_b_address_width = 11,
+\t\tram_block3a_9.port_b_data_out_clear = ""none"",
+\t\tram_block3a_9.port_b_data_out_clock = ""none"",
+\t\tram_block3a_9.port_b_data_width = 1,
+\t\tram_block3a_9.port_b_first_address = 0,
+\t\tram_block3a_9.port_b_first_bit_number = 9,
+\t\tram_block3a_9.port_b_last_address = 2047,
+\t\tram_block3a_9.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_9.port_b_logical_ram_width = 16,
+\t\tram_block3a_9.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_9.ram_block_type = ""auto"",
+\t\tram_block3a_9.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_10
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[10]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_10.connectivity_checking = ""OFF"",
+\t\tram_block3a_10.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_10.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_10.operation_mode = ""dual_port"",
+\t\tram_block3a_10.port_a_address_width = 11,
+\t\tram_block3a_10.port_a_data_width = 1,
+\t\tram_block3a_10.port_a_first_address = 0,
+\t\tram_block3a_10.port_a_first_bit_number = 10,
+\t\tram_block3a_10.port_a_last_address = 2047,
+\t\tram_block3a_10.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_10.port_a_logical_ram_width = 16,
+\t\tram_block3a_10.port_b_address_clear = ""none"",
+\t\tram_block3a_10.port_b_address_clock = ""clock1"",
+\t\tram_block3a_10.port_b_address_width = 11,
+\t\tram_block3a_10.port_b_data_out_clear = ""none"",
+\t\tram_block3a_10.port_b_data_out_clock = ""none"",
+\t\tram_block3a_10.port_b_data_width = 1,
+\t\tram_block3a_10.port_b_first_address = 0,
+\t\tram_block3a_10.port_b_first_bit_number = 10,
+\t\tram_block3a_10.port_b_last_address = 2047,
+\t\tram_block3a_10.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_10.port_b_logical_ram_width = 16,
+\t\tram_block3a_10.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_10.ram_block_type = ""auto"",
+\t\tram_block3a_10.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_11
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[11]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_11.connectivity_checking = ""OFF"",
+\t\tram_block3a_11.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_11.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_11.operation_mode = ""dual_port"",
+\t\tram_block3a_11.port_a_address_width = 11,
+\t\tram_block3a_11.port_a_data_width = 1,
+\t\tram_block3a_11.port_a_first_address = 0,
+\t\tram_block3a_11.port_a_first_bit_number = 11,
+\t\tram_block3a_11.port_a_last_address = 2047,
+\t\tram_block3a_11.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_11.port_a_logical_ram_width = 16,
+\t\tram_block3a_11.port_b_address_clear = ""none"",
+\t\tram_block3a_11.port_b_address_clock = ""clock1"",
+\t\tram_block3a_11.port_b_address_width = 11,
+\t\tram_block3a_11.port_b_data_out_clear = ""none"",
+\t\tram_block3a_11.port_b_data_out_clock = ""none"",
+\t\tram_block3a_11.port_b_data_width = 1,
+\t\tram_block3a_11.port_b_first_address = 0,
+\t\tram_block3a_11.port_b_first_bit_number = 11,
+\t\tram_block3a_11.port_b_last_address = 2047,
+\t\tram_block3a_11.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_11.port_b_logical_ram_width = 16,
+\t\tram_block3a_11.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_11.ram_block_type = ""auto"",
+\t\tram_block3a_11.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_12
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[12]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_12.connectivity_checking = ""OFF"",
+\t\tram_block3a_12.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_12.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_12.operation_mode = ""dual_port"",
+\t\tram_block3a_12.port_a_address_width = 11,
+\t\tram_block3a_12.port_a_data_width = 1,
+\t\tram_block3a_12.port_a_first_address = 0,
+\t\tram_block3a_12.port_a_first_bit_number = 12,
+\t\tram_block3a_12.port_a_last_address = 2047,
+\t\tram_block3a_12.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_12.port_a_logical_ram_width = 16,
+\t\tram_block3a_12.port_b_address_clear = ""none"",
+\t\tram_block3a_12.port_b_address_clock = ""clock1"",
+\t\tram_block3a_12.port_b_address_width = 11,
+\t\tram_block3a_12.port_b_data_out_clear = ""none"",
+\t\tram_block3a_12.port_b_data_out_clock = ""none"",
+\t\tram_block3a_12.port_b_data_width = 1,
+\t\tram_block3a_12.port_b_first_address = 0,
+\t\tram_block3a_12.port_b_first_bit_number = 12,
+\t\tram_block3a_12.port_b_last_address = 2047,
+\t\tram_block3a_12.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_12.port_b_logical_ram_width = 16,
+\t\tram_block3a_12.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_12.ram_block_type = ""auto"",
+\t\tram_block3a_12.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_13
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[13]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_13.connectivity_checking = ""OFF"",
+\t\tram_block3a_13.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_13.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_13.operation_mode = ""dual_port"",
+\t\tram_block3a_13.port_a_address_width = 11,
+\t\tram_block3a_13.port_a_data_width = 1,
+\t\tram_block3a_13.port_a_first_address = 0,
+\t\tram_block3a_13.port_a_first_bit_number = 13,
+\t\tram_block3a_13.port_a_last_address = 2047,
+\t\tram_block3a_13.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_13.port_a_logical_ram_width = 16,
+\t\tram_block3a_13.port_b_address_clear = ""none"",
+\t\tram_block3a_13.port_b_address_clock = ""clock1"",
+\t\tram_block3a_13.port_b_address_width = 11,
+\t\tram_block3a_13.port_b_data_out_clear = ""none"",
+\t\tram_block3a_13.port_b_data_out_clock = ""none"",
+\t\tram_block3a_13.port_b_data_width = 1,
+\t\tram_block3a_13.port_b_first_address = 0,
+\t\tram_block3a_13.port_b_first_bit_number = 13,
+\t\tram_block3a_13.port_b_last_address = 2047,
+\t\tram_block3a_13.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_13.port_b_logical_ram_width = 16,
+\t\tram_block3a_13.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_13.ram_block_type = ""auto"",
+\t\tram_block3a_13.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_14
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[14]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_14.connectivity_checking = ""OFF"",
+\t\tram_block3a_14.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_14.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_14.operation_mode = ""dual_port"",
+\t\tram_block3a_14.port_a_address_width = 11,
+\t\tram_block3a_14.port_a_data_width = 1,
+\t\tram_block3a_14.port_a_first_address = 0,
+\t\tram_block3a_14.port_a_first_bit_number = 14,
+\t\tram_block3a_14.port_a_last_address = 2047,
+\t\tram_block3a_14.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_14.port_a_logical_ram_width = 16,
+\t\tram_block3a_14.port_b_address_clear = ""none"",
+\t\tram_block3a_14.port_b_address_clock = ""clock1"",
+\t\tram_block3a_14.port_b_address_width = 11,
+\t\tram_block3a_14.port_b_data_out_clear = ""none"",
+\t\tram_block3a_14.port_b_data_out_clock = ""none"",
+\t\tram_block3a_14.port_b_data_width = 1,
+\t\tram_block3a_14.port_b_first_address = 0,
+\t\tram_block3a_14.port_b_first_bit_number = 14,
+\t\tram_block3a_14.port_b_last_address = 2047,
+\t\tram_block3a_14.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_14.port_b_logical_ram_width = 16,
+\t\tram_block3a_14.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_14.ram_block_type = ""auto"",
+\t\tram_block3a_14.lpm_type = ""cyclone_ram_block"";
+\tcyclone_ram_block   ram_block3a_15
+\t( 
+\t.clk0(clock0),
+\t.clk1(clock1),
+\t.ena0(wren_a),
+\t.ena1(clocken1),
+\t.portaaddr({address_a_wire[10:0]}),
+\t.portadatain({data_a[15]}),
+\t.portadataout(),
+\t.portawe(1\'b1),
+\t.portbaddr({address_b_wire[10:0]}),
+\t.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
+\t.portbrewe(1\'b1)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.clr0(1\'b0),
+\t.clr1(1\'b0),
+\t.portabyteenamasks(1\'b1),
+\t.portbbyteenamasks(1\'b1),
+\t.portbdatain(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tram_block3a_15.connectivity_checking = ""OFF"",
+\t\tram_block3a_15.logical_ram_name = ""ALTSYNCRAM"",
+\t\tram_block3a_15.mixed_port_feed_through_mode = ""dont_care"",
+\t\tram_block3a_15.operation_mode = ""dual_port"",
+\t\tram_block3a_15.port_a_address_width = 11,
+\t\tram_block3a_15.port_a_data_width = 1,
+\t\tram_block3a_15.port_a_first_address = 0,
+\t\tram_block3a_15.port_a_first_bit_number = 15,
+\t\tram_block3a_15.port_a_last_address = 2047,
+\t\tram_block3a_15.port_a_logical_ram_depth = 2048,
+\t\tram_block3a_15.port_a_logical_ram_width = 16,
+\t\tram_block3a_15.port_b_address_clear = ""none"",
+\t\tram_block3a_15.port_b_address_clock = ""clock1"",
+\t\tram_block3a_15.port_b_address_width = 11,
+\t\tram_block3a_15.port_b_data_out_clear = ""none"",
+\t\tram_block3a_15.port_b_data_out_clock = ""none"",
+\t\tram_block3a_15.port_b_data_width = 1,
+\t\tram_block3a_15.port_b_first_address = 0,
+\t\tram_block3a_15.port_b_first_bit_number = 15,
+\t\tram_block3a_15.port_b_last_address = 2047,
+\t\tram_block3a_15.port_b_logical_ram_depth = 2048,
+\t\tram_block3a_15.port_b_logical_ram_width = 16,
+\t\tram_block3a_15.port_b_read_enable_write_enable_clock = ""clock1"",
+\t\tram_block3a_15.ram_block_type = ""auto"",
+\t\tram_block3a_15.lpm_type = ""cyclone_ram_block"";
+\tassign
+\t\taddress_a_wire = address_a,
+\t\taddress_b_wire = address_b,
+\t\tq_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
+endmodule //fifo_2k_altsyncram_6pl
+
+
+//dffpipe DELAY=1 WIDTH=11 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = lut 11 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_dffpipe_ab3
+\t( 
+\tclock,
+\tclrn,
+\td,
+\tq) /* synthesis synthesis_clearbox=1 */
+\t\t/* synthesis ALTERA_ATTRIBUTE=""AUTO_SHIFT_REGISTER_RECOGNITION=OFF"" */;
+\tinput   clock;
+\tinput   clrn;
+\tinput   [10:0]  d;
+\toutput   [10:0]  q;
+
+\twire\t[10:0]\twire_dffe4a_D;
+\treg\t[10:0]\tdffe4a;
+\twire ena;
+\twire prn;
+\twire sclr;
+
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[0:0] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[0:0] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[0:0] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[0:0] <= wire_dffe4a_D[0:0];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[1:1] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[1:1] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[1:1] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[1:1] <= wire_dffe4a_D[1:1];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[2:2] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[2:2] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[2:2] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[2:2] <= wire_dffe4a_D[2:2];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[3:3] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[3:3] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[3:3] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[3:3] <= wire_dffe4a_D[3:3];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[4:4] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[4:4] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[4:4] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[4:4] <= wire_dffe4a_D[4:4];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[5:5] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[5:5] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[5:5] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[5:5] <= wire_dffe4a_D[5:5];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[6:6] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[6:6] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[6:6] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[6:6] <= wire_dffe4a_D[6:6];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[7:7] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[7:7] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[7:7] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[7:7] <= wire_dffe4a_D[7:7];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[8:8] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[8:8] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[8:8] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[8:8] <= wire_dffe4a_D[8:8];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[9:9] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[9:9] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[9:9] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[9:9] <= wire_dffe4a_D[9:9];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe4a[10:10] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe4a[10:10] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe4a[10:10] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe4a[10:10] <= wire_dffe4a_D[10:10];
+\tassign
+\t\twire_dffe4a_D = (d & {11{(~ sclr)}});
+\tassign
+\t\tena = 1\'b1,
+\t\tprn = 1\'b1,
+\t\tq = dffe4a,
+\t\tsclr = 1\'b0;
+endmodule //fifo_2k_dffpipe_ab3
+
+
+//dffpipe WIDTH=11 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+
+//dffpipe WIDTH=11 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = lut 11 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_dffpipe_dm2
+\t( 
+\tclock,
+\tclrn,
+\td,
+\tq) /* synthesis synthesis_clearbox=1 */
+\t\t/* synthesis ALTERA_ATTRIBUTE=""AUTO_SHIFT_REGISTER_RECOGNITION=OFF"" */;
+\tinput   clock;
+\tinput   clrn;
+\tinput   [10:0]  d;
+\toutput   [10:0]  q;
+
+\twire\t[10:0]\twire_dffe6a_D;
+\treg\t[10:0]\tdffe6a;
+\twire ena;
+\twire prn;
+\twire sclr;
+
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[0:0] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[0:0] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[0:0] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[0:0] <= wire_dffe6a_D[0:0];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[1:1] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[1:1] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[1:1] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[1:1] <= wire_dffe6a_D[1:1];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[2:2] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[2:2] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[2:2] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[2:2] <= wire_dffe6a_D[2:2];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[3:3] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[3:3] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[3:3] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[3:3] <= wire_dffe6a_D[3:3];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[4:4] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[4:4] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[4:4] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[4:4] <= wire_dffe6a_D[4:4];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[5:5] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[5:5] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[5:5] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[5:5] <= wire_dffe6a_D[5:5];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[6:6] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[6:6] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[6:6] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[6:6] <= wire_dffe6a_D[6:6];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[7:7] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[7:7] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[7:7] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[7:7] <= wire_dffe6a_D[7:7];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[8:8] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[8:8] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[8:8] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[8:8] <= wire_dffe6a_D[8:8];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[9:9] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[9:9] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[9:9] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[9:9] <= wire_dffe6a_D[9:9];
+\t// synopsys translate_off
+\tinitial
+\t\tdffe6a[10:10] = 0;
+\t// synopsys translate_on
+\talways @ ( posedge clock or  negedge prn or  negedge clrn)
+\t\tif (prn == 1\'b0) dffe6a[10:10] <= 1\'b1;
+\t\telse if (clrn == 1\'b0) dffe6a[10:10] <= 1\'b0;
+\t\telse if  (ena == 1\'b1)   dffe6a[10:10] <= wire_dffe6a_D[10:10];
+\tassign
+\t\twire_dffe6a_D = (d & {11{(~ sclr)}});
+\tassign
+\t\tena = 1\'b1,
+\t\tprn = 1\'b1,
+\t\tq = dffe6a,
+\t\tsclr = 1\'b0;
+endmodule //fifo_2k_dffpipe_dm2
+
+//synthesis_resources = lut 11 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_alt_synch_pipe_dm2
+\t( 
+\tclock,
+\tclrn,
+\td,
+\tq) /* synthesis synthesis_clearbox=1 */
+\t\t/* synthesis ALTERA_ATTRIBUTE=""X_ON_VIOLATION_OPTION=OFF"" */;
+\tinput   clock;
+\tinput   clrn;
+\tinput   [10:0]  d;
+\toutput   [10:0]  q;
+
+\twire  [10:0]   wire_dffpipe5_q;
+
+\tfifo_2k_dffpipe_dm2   dffpipe5
+\t( 
+\t.clock(clock),
+\t.clrn(clrn),
+\t.d(d),
+\t.q(wire_dffpipe5_q));
+\tassign
+\t\tq = wire_dffpipe5_q;
+endmodule //fifo_2k_alt_synch_pipe_dm2
+
+
+//lpm_add_sub DEVICE_FAMILY=""Cyclone"" LPM_DIRECTION=""SUB"" LPM_WIDTH=11 dataa datab result
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 11 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_add_sub_a18
+\t( 
+\tdataa,
+\tdatab,
+\tresult) /* synthesis synthesis_clearbox=1 */;
+\tinput   [10:0]  dataa;
+\tinput   [10:0]  datab;
+\toutput   [10:0]  result;
+
+\twire  [10:0]   wire_add_sub_cella_combout;
+\twire  [0:0]   wire_add_sub_cella_0cout;
+\twire  [0:0]   wire_add_sub_cella_1cout;
+\twire  [0:0]   wire_add_sub_cella_2cout;
+\twire  [0:0]   wire_add_sub_cella_3cout;
+\twire  [0:0]   wire_add_sub_cella_4cout;
+\twire  [0:0]   wire_add_sub_cella_5cout;
+\twire  [0:0]   wire_add_sub_cella_6cout;
+\twire  [0:0]   wire_add_sub_cella_7cout;
+\twire  [0:0]   wire_add_sub_cella_8cout;
+\twire  [0:0]   wire_add_sub_cella_9cout;
+\twire  [10:0]   wire_add_sub_cella_dataa;
+\twire  [10:0]   wire_add_sub_cella_datab;
+
+\tcyclone_lcell   add_sub_cella_0
+\t( 
+\t.cin(1\'b1),
+\t.combout(wire_add_sub_cella_combout[0:0]),
+\t.cout(wire_add_sub_cella_0cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[0:0]),
+\t.datab(wire_add_sub_cella_datab[0:0]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_0.cin_used = ""true"",
+\t\tadd_sub_cella_0.lut_mask = ""69b2"",
+\t\tadd_sub_cella_0.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_0.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_0.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_1
+\t( 
+\t.cin(wire_add_sub_cella_0cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[1:1]),
+\t.cout(wire_add_sub_cella_1cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[1:1]),
+\t.datab(wire_add_sub_cella_datab[1:1]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_1.cin_used = ""true"",
+\t\tadd_sub_cella_1.lut_mask = ""69b2"",
+\t\tadd_sub_cella_1.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_1.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_1.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_2
+\t( 
+\t.cin(wire_add_sub_cella_1cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[2:2]),
+\t.cout(wire_add_sub_cella_2cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[2:2]),
+\t.datab(wire_add_sub_cella_datab[2:2]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_2.cin_used = ""true"",
+\t\tadd_sub_cella_2.lut_mask = ""69b2"",
+\t\tadd_sub_cella_2.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_2.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_2.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_3
+\t( 
+\t.cin(wire_add_sub_cella_2cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[3:3]),
+\t.cout(wire_add_sub_cella_3cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[3:3]),
+\t.datab(wire_add_sub_cella_datab[3:3]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_3.cin_used = ""true"",
+\t\tadd_sub_cella_3.lut_mask = ""69b2"",
+\t\tadd_sub_cella_3.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_3.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_3.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_4
+\t( 
+\t.cin(wire_add_sub_cella_3cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[4:4]),
+\t.cout(wire_add_sub_cella_4cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[4:4]),
+\t.datab(wire_add_sub_cella_datab[4:4]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_4.cin_used = ""true"",
+\t\tadd_sub_cella_4.lut_mask = ""69b2"",
+\t\tadd_sub_cella_4.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_4.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_4.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_5
+\t( 
+\t.cin(wire_add_sub_cella_4cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[5:5]),
+\t.cout(wire_add_sub_cella_5cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[5:5]),
+\t.datab(wire_add_sub_cella_datab[5:5]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_5.cin_used = ""true"",
+\t\tadd_sub_cella_5.lut_mask = ""69b2"",
+\t\tadd_sub_cella_5.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_5.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_5.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_6
+\t( 
+\t.cin(wire_add_sub_cella_5cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[6:6]),
+\t.cout(wire_add_sub_cella_6cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[6:6]),
+\t.datab(wire_add_sub_cella_datab[6:6]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_6.cin_used = ""true"",
+\t\tadd_sub_cella_6.lut_mask = ""69b2"",
+\t\tadd_sub_cella_6.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_6.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_6.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_7
+\t( 
+\t.cin(wire_add_sub_cella_6cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[7:7]),
+\t.cout(wire_add_sub_cella_7cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[7:7]),
+\t.datab(wire_add_sub_cella_datab[7:7]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_7.cin_used = ""true"",
+\t\tadd_sub_cella_7.lut_mask = ""69b2"",
+\t\tadd_sub_cella_7.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_7.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_7.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_8
+\t( 
+\t.cin(wire_add_sub_cella_7cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[8:8]),
+\t.cout(wire_add_sub_cella_8cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[8:8]),
+\t.datab(wire_add_sub_cella_datab[8:8]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_8.cin_used = ""true"",
+\t\tadd_sub_cella_8.lut_mask = ""69b2"",
+\t\tadd_sub_cella_8.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_8.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_8.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_9
+\t( 
+\t.cin(wire_add_sub_cella_8cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[9:9]),
+\t.cout(wire_add_sub_cella_9cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[9:9]),
+\t.datab(wire_add_sub_cella_datab[9:9]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_9.cin_used = ""true"",
+\t\tadd_sub_cella_9.lut_mask = ""69b2"",
+\t\tadd_sub_cella_9.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_9.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_9.lpm_type = ""cyclone_lcell"";
+\tcyclone_lcell   add_sub_cella_10
+\t( 
+\t.cin(wire_add_sub_cella_9cout[0:0]),
+\t.combout(wire_add_sub_cella_combout[10:10]),
+\t.cout(),
+\t.dataa(wire_add_sub_cella_dataa[10:10]),
+\t.datab(wire_add_sub_cella_datab[10:10]),
+\t.regout()
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_off
+\t`endif
+\t,
+\t.aclr(1\'b0),
+\t.aload(1\'b0),
+\t.clk(1\'b1),
+\t.datac(1\'b1),
+\t.datad(1\'b1),
+\t.ena(1\'b1),
+\t.inverta(1\'b0),
+\t.regcascin(1\'b0),
+\t.sclr(1\'b0),
+\t.sload(1\'b0)
+\t`ifdef FORMAL_VERIFICATION
+\t`else
+\t// synopsys translate_on
+\t`endif
+\t// synopsys translate_off
+\t,
+\t.cin0(),
+\t.cin1(),
+\t.cout0(),
+\t.cout1(),
+\t.devclrn(),
+\t.devpor()
+\t// synopsys translate_on
+\t);
+\tdefparam
+\t\tadd_sub_cella_10.cin_used = ""true"",
+\t\tadd_sub_cella_10.lut_mask = ""6969"",
+\t\tadd_sub_cella_10.operation_mode = ""normal"",
+\t\tadd_sub_cella_10.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_10.lpm_type = ""cyclone_lcell"";
+\tassign
+\t\twire_add_sub_cella_dataa = dataa,
+\t\twire_add_sub_cella_datab = datab;
+\tassign
+\t\tresult = wire_add_sub_cella_combout;
+endmodule //fifo_2k_add_sub_a18
+
+
+//lpm_compare DEVICE_FAMILY=""Cyclone"" LPM_WIDTH=11 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+
+//lpm_compare DEVICE_FAMILY=""Cyclone"" LPM_WIDTH=11 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 97 M4K 8 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_2k_dcfifo_0cq
+\t( 
+\taclr,
+\tdata,
+\tq,
+\trdclk,
+\trdempty,
+\trdreq,
+\trdusedw,
+\twrclk,
+\twrfull,
+\twrreq,
+\twrusedw) /* synthesis synthesis_clearbox=1 */
+\t\t/* synthesis ALTERA_ATTRIBUTE=""AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \\""rdptr_g|power_modified_counter_values\\"" -to \\""ws_dgrp|dffpipe5|dffe6a\\"" }CUT=ON;{ -from \\""delayed_wrptr_g\\"" -to \\""rs_dgwp|dffpipe5|dffe6a\\"" }CUT=ON"" */;
+\tinput   aclr;
+\tinput   [15:0]  data;
+\toutput   [15:0]  q;
+\tinput   rdclk;
+\toutput   rdempty;
+\tinput   rdreq;
+\toutput   [10:0]  rdusedw;
+\tinput   wrclk;
+\toutput   wrfull;
+\tinput   wrreq;
+\toutput   [10:0]  wrusedw;
+
+\twire  [10:0]   wire_rdptr_g_gray2bin_bin;
+\twire  [10:0]   wire_rs_dgwp_gray2bin_bin;
+\twire  [10:0]   wire_wrptr_g_gray2bin_bin;
+\twire  [10:0]   wire_ws_dgrp_gray2bin_bin;
+\twire  [10:0]   wire_rdptr_g_q;
+\twire  [10:0]   wire_rdptr_g1p_q;
+\twire  [10:0]   wire_wrptr_g1p_q;
+\twire  [15:0]   wire_fifo_ram_q_b;
+\treg\t[10:0]\tdelayed_wrptr_g;
+\treg\t[10:0]\twrptr_g;
+\twire  [10:0]   wire_rs_brp_q;
+\twire  [10:0]   wire_rs_bwp_q;
+\twire  [10:0]   wire_rs_dgwp_q;
+\twire  [10:0]   wire_ws_brp_q;
+\twire  [10:0]   wire_ws_bwp_q;
+\twire  [10:0]   wire_ws_dgrp_q;
+\twire  [10:0]   wire_rdusedw_sub_result;
+\twire  [10:0]   wire_wrusedw_sub_result;
+\treg\twire_rdempty_eq_comp_aeb_int;
+\twire\twire_rdempty_eq_comp_aeb;
+\twire\t[10:0]\twire_rdempty_eq_comp_dataa;
+\twire\t[10:0]\twire_rdempty_eq_comp_datab;
+\treg\twire_wrfull_eq_comp_aeb_int;
+\twire\twire_wrfull_eq_comp_aeb;
+\twire\t[10:0]\twire_wrfull_eq_comp_dataa;
+\twire\t[10:0]\twire_wrfull_eq_comp_datab;
+\twire  int_rdempty;
+\twire  int_wrfull;
+\twire  valid_rdreq;
+\twire  valid_wrreq;
+
+\tfifo_2k_a_gray2bin_8m4   rdptr_g_gray2bin
+\t( 
+\t.bin(wire_rdptr_g_gray2bin_bin),
+\t.gray(wire_rdptr_g_q));
+\tfifo_2k_a_gray2bin_8m4   rs_dgwp_gray2bin
+\t( 
+\t.bin(wire_rs_dgwp_gray2bin_bin),
+\t.gray(wire_rs_dgwp_q));
+\tfifo_2k_a_gray2bin_8m4   wrptr_g_gray2bin
+\t( 
+\t.bin(wire_wrptr_g_gray2bin_bin),
+\t.gray(wrptr_g));
+\tfifo_2k_a_gray2bin_8m4   ws_dgrp_gray2bin
+\t( 
+\t.bin(wire_ws_dgrp_gray2bin_bin),
+\t.gray(wire_ws_dgrp_q));
+\tfifo_2k_a_graycounter_726   rdptr_g
+\t( 
+\t.aclr(aclr),
+\t.clock(rdclk),
+\t.cnt_en(valid_rdreq),
+\t.q(wire_rdptr_g_q));
+\tfifo_2k_a_graycounter_2r6   rdptr_g1p
+\t( 
+\t.aclr(aclr),
+\t.clock(rdclk),
+\t.cnt_en(valid_rdreq),
+\t.q(wire_rdptr_g1p_q));
+\tfifo_2k_a_graycounter_2r6   wrptr_g1p
+\t( 
+\t.aclr(aclr),
+\t.clock(wrclk),
+\t.cnt_en(valid_wrreq),
+\t.q(wire_wrptr_g1p_q));
+\tfifo_2k_altsyncram_6pl   fifo_ram
+\t( 
+\t.address_a(wrptr_g),
+\t.address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))),
+\t.clock0(wrclk),
+\t.clock1(rdclk),
+\t.clocken1((valid_rdreq | int_rdempty)),
+\t.data_a(data),
+\t.q_b(wire_fifo_ram_q_b),
+\t.wren_a(valid_wrreq));
+\t// synopsys translate_off
+\tinitial
+\t\tdelayed_wrptr_g = 0;
+\t// synopsys translate_on
+\talways @ ( posedge wrclk or  posedge aclr)
+\t\tif (aclr == 1\'b1) delayed_wrptr_g <= 11\'b0;
+\t\telse  delayed_wrptr_g <= wrptr_g;
+\t// synopsys translate_off
+\tinitial
+\t\twrptr_g = 0;
+\t// synopsys translate_on
+\talways @ ( posedge wrclk or  posedge aclr)
+\t\tif (aclr == 1\'b1) wrptr_g <= 11\'b0;
+\t\telse if  (valid_wrreq == 1\'b1)   wrptr_g <= wire_wrptr_g1p_q;
+\tfifo_2k_dffpipe_ab3   rs_brp
+\t( 
+\t.clock(rdclk),
+\t.clrn((~ aclr)),
+\t.d(wire_rdptr_g_gray2bin_bin),
+\t.q(wire_rs_brp_q));
+\tfifo_2k_dffpipe_ab3   rs_bwp
+\t( 
+\t.clock(rdclk),
+\t.clrn((~ aclr)),
+\t.d(wire_rs_dgwp_gray2bin_bin),
+\t.q(wire_rs_bwp_q));
+\tfifo_2k_alt_synch_pipe_dm2   rs_dgwp
+\t( 
+\t.clock(rdclk),
+\t.clrn((~ aclr)),
+\t.d(delayed_wrptr_g),
+\t.q(wire_rs_dgwp_q));
+\tfifo_2k_dffpipe_ab3   ws_brp
+\t( 
+\t.clock(wrclk),
+\t.clrn((~ aclr)),
+\t.d(wire_ws_dgrp_gray2bin_bin),
+\t.q(wire_ws_brp_q));
+\tfifo_2k_dffpipe_ab3   ws_bwp
+\t( 
+\t.clock(wrclk),
+\t.clrn((~ aclr)),
+\t.d(wire_wrptr_g_gray2bin_bin),
+\t.q(wire_ws_bwp_q));
+\tfifo_2k_alt_synch_pipe_dm2   ws_dgrp
+\t( 
+\t.clock(wrclk),
+\t.clrn((~ aclr)),
+\t.d(wire_rdptr_g_q),
+\t.q(wire_ws_dgrp_q));
+\tfifo_2k_add_sub_a18   rdusedw_sub
+\t( 
+\t.dataa(wire_rs_bwp_q),
+\t.datab(wire_rs_brp_q),
+\t.result(wire_rdusedw_sub_result));
+\tfifo_2k_add_sub_a18   wrusedw_sub
+\t( 
+\t.dataa(wire_ws_bwp_q),
+\t.datab(wire_ws_brp_q),
+\t.result(wire_wrusedw_sub_result));
+\talways @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
+\t\tif (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) 
+\t\t\tbegin
+\t\t\t\twire_rdempty_eq_comp_aeb_int = 1\'b1;
+\t\t\tend
+\t\telse
+\t\t\tbegin
+\t\t\t\twire_rdempty_eq_comp_aeb_int = 1\'b0;
+\t\t\tend
+\tassign
+\t\twire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
+\tassign
+\t\twire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
+\t\twire_rdempty_eq_comp_datab = wire_rdptr_g_q;
+\talways @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
+\t\tif (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) 
+\t\t\tbegin
+\t\t\t\twire_wrfull_eq_comp_aeb_int = 1\'b1;
+\t\t\tend
+\t\telse
+\t\t\tbegin
+\t\t\t\twire_wrfull_eq_comp_aeb_int = 1\'b0;
+\t\t\tend
+\tassign
+\t\twire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
+\tassign
+\t\twire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
+\t\twire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
+\tassign
+\t\tint_rdempty = wire_rdempty_eq_comp_aeb,
+\t\tint_wrfull = wire_wrfull_eq_comp_aeb,
+\t\tq = wire_fifo_ram_q_b,
+\t\trdempty = int_rdempty,
+\t\trdusedw = wire_rdusedw_sub_result,
+\t\tvalid_rdreq = rdreq,
+\t\tvalid_wrreq = wrreq,
+\t\twrfull = int_wrfull,
+\t\twrusedw = wire_wrusedw_sub_result;
+endmodule //fifo_2k_dcfifo_0cq
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_2k (
+\tdata,
+\twrreq,
+\trdreq,
+\trdclk,
+\twrclk,
+\taclr,
+\t'b'q,
+\trdempty,
+\trdusedw,
+\twrfull,
+\twrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[15:0]  data;
+\tinput\t  wrreq;
+\tinput\t  rdreq;
+\tinput\t  rdclk;
+\tinput\t  wrclk;
+\tinput\t  aclr;
+\toutput\t[15:0]  q;
+\toutput\t  rdempty;
+\toutput\t[10:0]  rdusedw;
+\toutput\t  wrfull;
+\toutput\t[10:0]  wrusedw;
+
+\twire  sub_wire0;
+\twire [10:0] sub_wire1;
+\twire  sub_wire2;
+\twire [15:0] sub_wire3;
+\twire [10:0] sub_wire4;
+\twire  rdempty = sub_wire0;
+\twire [10:0] wrusedw = sub_wire1[10:0];
+\twire  wrfull = sub_wire2;
+\twire [15:0] q = sub_wire3[15:0];
+\twire [10:0] rdusedw = sub_wire4[10:0];
+
+\tfifo_2k_dcfifo_0cq\tfifo_2k_dcfifo_0cq_component (
+\t\t\t\t.wrclk (wrclk),
+\t\t\t\t.rdreq (rdreq),
+\t\t\t\t.aclr (aclr),
+\t\t\t\t.rdclk (rdclk),
+\t\t\t\t.wrreq (wrreq),
+\t\t\t\t.data (data),
+\t\t\t\t.rdempty (sub_wire0),
+\t\t\t\t.wrusedw (sub_wire1),
+\t\t\t\t.wrfull (sub_wire2),
+\t\t\t\t.q (sub_wire3),
+\t\t\t\t.rdusedw (sub_wire4));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC ""16""
+// Retrieval info: PRIVATE: Depth NUMERIC ""2048""
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""
+// Retrieval info: PRIVATE: Full NUMERIC ""1""
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""2048""
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""11""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
+"
+"module cmd_reader
+   (//System
+    input reset, input txclk, input [31:0] adc_time,
+    //FX2 Side
+    output reg skip, output reg rdreq, 
+    input [31:0] fifodata, input pkt_waiting,
+    //Rx side
+    input rx_WR_enabled, output reg [15:0] rx_databus,
+    output reg rx_WR, output reg rx_WR_done,
+    //register io
+    input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
+    output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
+    output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
+\t
+   // States
+   parameter IDLE                       =   4'd0;
+   parameter HEADER                     =   4'd1;
+   parameter TIMESTAMP                  =   4'd2;
+   parameter WAIT          \t            =   4'd3;
+   parameter TEST                       =   4'd4;
+   parameter SEND                       =   4'd5;
+   parameter PING                       =   4'd6;
+   parameter WRITE_REG                  =   4'd7;
+   parameter WRITE_REG_MASKED           =   4'd8;
+   parameter READ_REG                   =   4'd9;
+   parameter DELAY                      =   4'd14;\t\t
+
+   `define OP_PING_FIXED                    8'd0
+   `define OP_PING_FIXED_REPLY              8'd1
+   `define OP_WRITE_REG\t                    8'd2
+   `define OP_WRITE_REG_MASKED              8'd3
+   `define OP_READ_REG                      8'd4
+   `define OP_READ_REG_REPLY                8'd5
+   `define OP_DELAY                         8'd12
+\t
+   reg [6:0]   payload;
+   reg [6:0]   payload_read;
+   reg [3:0]   state;
+   reg [15:0]  high;
+   reg [15:0]  low;
+   reg         pending;
+   reg [31:0]  value0;
+   reg [31:0]  value1;
+   reg [31:0]  value2;
+   reg [1:0]   lines_in;
+   reg [1:0]   lines_out;
+   reg [1:0]   lines_out_total;
+\t
+   `define JITTER                           5
+   `define OP_CODE                          31:24
+   `define PAYLOAD                          8:2
+\t
+   wire [7:0] ops;
+   assign ops = value0[`OP_CODE];
+   assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]};
+\t
+   always @(posedge txclk)
+       if (reset)
+         begin
+           pending <= 0;
+           state <= IDLE;
+           skip <= 0;
+           rdreq <= 0;
+           rx_WR <= 0;
+           reg_io_enable <= 0;
+           reg_data_in <= 0;
+           reg_addr <= 0;
+           stop <= 0;
+          end
+        else case (state)
+          IDLE : 
+            begin
+              payload_read <= 0;
+              skip <= 0;
+              lines_in <= 0;
+              if(pkt_waiting)
+                begin
+                  state <= HEADER;
+                  rdreq <= 1;
+                end
+             end
+          
+          HEADER : 
+            begin
+              payload <= fifodata[`PAYLOAD];
+              state <= TIMESTAMP;
+            end
+          
+          TIMESTAMP : 
+            begin
+              value0 <= fifodata;
+              state <= WAIT;
+              rdreq <= 0;
+            end
+\t\t\t
+          WAIT : 
+            begin
+              // Let's send it
+              if ((value0 <= adc_time + `JITTER 
+                 && value0 > adc_time)
+                 || value0 == 32'hFFFFFFFF)
+                  state <= TEST;
+              // Wait a little bit more
+              else if (value0 > adc_time + `JITTER)
+                  state <= WAIT; 
+              // Outdated
+              else if (value0 < adc_time)
+                begin
+                  state <= IDLE;
+                  skip <= 1;
+                end
+            end
+\t\t\t
+          TEST : 
+            begin
+              reg_io_enable <= 0;
+              rx_WR <= 0;
+              rx_WR_done <= 1;
+              stop <= 0;
+              if (payload_read == payload)
+                begin
+                  skip <= 1;
+                  state <= IDLE;
+                  rdreq <= 0;
+                end
+              else
+                begin
+                  value0 <= fifodata;
+                  lines_in <= 2'd1;
+                  rdreq <= 1;
+                  payload_read <= payload_read + 7'd1;
+                  lines_out <= 0;
+                  case (fifodata[`OP_CODE])
+                    `OP_PING_FIXED: 
+                      begin
+                        state <= PING;
+                      end
+                    `OP_WRITE_REG: 
+                      begin
+                        state <= WRITE_REG;
+                        pending <= 1;
+                      end
+                    `OP_WRITE_REG_MASKED: 
+                      begin
+                        state <= WRITE_REG_MASKED;
+                        pending <= 1;
+                      end
+                    `OP_READ_REG: 
+                      begin
+                        state <= READ_REG;
+                      end
+                    `OP_DELAY: 
+                      begin
+                        state <= DELAY;
+                      end
+                    default: 
+                      begin
+                      //error, skip this packet
+                        skip <= 1;
+                        state <= IDLE;
+                      end
+                  endcase
+                end
+              end
+\t\t\t
+            SEND: 
+              begin
+                rdreq <= 0;
+                rx_WR_done <= 0;
+                if (pending)
+                  begin
+                    rx_WR <= 1;
+                    rx_databus <= high;
+                    pending <= 0;
+                    if (lines_out == lines_out_total)
+                        state <= TEST;
+                    else case (ops)
+                        `OP_READ_REG: 
+                          begin
+                            state <= READ_REG;
+                          end
+                         default: 
+                           begin
+                             state <= TEST;
+                           end
+                    endcase
+                  end
+                else
+                  begin
+                    if (rx_WR_enabled)
+                      begin
+                        rx_WR <= 1;
+                        rx_databus <= low;
+                        pending <= 1;
+                        lines_out <= lines_out + 2'd1;
+                      end
+                    else
+                        rx_WR <= 0;
+                  end
+                end
+\t\t\t
+            PING: 
+              begin
+                rx_WR <= 0;
+                rdreq <= 0;
+                rx_WR_done <= 0;
+                lines_out_total <= 2'd1;
+                pending <= 0; 
+                state <= SEND;
+                high <= {`OP_PING_FIXED_REPLY, 8'd2};
+                low <= value0[15:0];\t
+              end
+\t\t\t
+            READ_REG: 
+              begin
+                rx_WR <= 0;
+                rx_WR_done <= 0;
+                rdreq <= 0;
+                lines_out_total <= 2'd2;
+                pending <= 0;
+                state <= SEND;
+                if (lines_out == 0)
+                  begin
+                    high <= {`OP_READ_REG_REPLY, 8'd6};
+                    low <= value0[15:0];
+                    reg_io_enable <= 2'd3;
+                    reg_addr <= value0[6:0];
+                  end
+                else
+                  begin\t\t
+                    high <= reg_data_out[31:16];
+                    low <= reg_data_out[15:0];
+                  end
+             end    
+\t\t\t
+            WRITE_REG: 
+              begin
+                rx_WR <= 0;
+                if (pending)
+                    pending <= 0;
+                else
+                  begin
+                    if (lines_in == 2'd1)
+                      begin
+                        payload_read <= payload_read + 7'd1;
+                        lines_in <= lines_in + 2'd1;
+                        value1 <= fifodata;
+                        rdreq <= 0;
+                      end
+                    else
+                      begin
+                        reg_io_enable <= 2'd2;
+                        reg_data_in <= value1;
+                        reg_addr <= value0[6:0];
+                        state <= TEST;
+                      end
+                  end
+              end
+\t\t\t
+            WRITE_REG_MASKED: 
+              begin
+                rx_WR <= 0;
+                if (pending)
+                    pending <= 0;
+                else
+                  begin
+                    if (lines_in == 2'd1)
+                      begin
+                        rdreq <= 1;
+                        payload_read <= payload_read + 7'd1;
+                        lines_in <= lines_in + 2'd1;
+                        value1 <= fifodata;
+                      end
+                    else if (lines_in == 2'd2)
+                      begin
+                        rdreq <= 0;
+                        payload_read <= payload_read + 7'd1;
+                        lines_in <= lines_in + 2'd1;
+                        value2 <= fifodata;
+                      end
+                    else
+                      begin
+                        reg_io_enable <= 2'd2;
+                        reg_data_in <= (value1 & value2);
+                        reg_addr <= value0[6:0];
+                        state <= TEST;
+                      end
+                  end
+              end
+\t\t\t
+            DELAY : 
+              begin
+                rdreq <= 0;
+                stop <= 1;
+                stop_time <= value0[15:0];
+                state <= TEST;
+              end
+\t\t\t
+            default : 
+              begin
+                //error state handling
+                state <= IDLE;
+              end
+        endcase
+endmodule
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003,2004 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+
+// Serial Control Bus from Cypress chip
+
+module serial_io
+  ( input master_clk,
+    input serial_clock,
+    input serial_data_in,
+    input enable,
+    input reset,
+    inout wire serial_data_out,
+    output reg [6:0] serial_addr,
+    output reg [31:0] serial_data,
+    output wire serial_strobe,
+    input wire [31:0] readback_0,
+    input wire [31:0] readback_1,
+    input wire [31:0] readback_2,
+    input wire [31:0] readback_3,
+    input wire [31:0] readback_4,
+    input wire [31:0] readback_5,
+    input wire [31:0] readback_6,
+    input wire [31:0] readback_7
+    );
+       
+   reg \t      is_read;
+   reg [7:0]  ser_ctr;
+   reg \t      write_done;
+
+   assign serial_data_out = is_read ? serial_data[31] : 1'bz;
+
+   always @(posedge serial_clock, posedge reset, negedge enable)
+     if(reset)
+       ser_ctr <= #1 8'd0;
+     else if(~enable)
+       ser_ctr <= #1 8'd0;
+     else if(ser_ctr == 39)
+       ser_ctr <= #1 8'd0;
+     else
+       ser_ctr <= #1 ser_ctr + 8'd1;
+
+   always @(posedge serial_clock, posedge reset, negedge enable)
+     if(reset)
+       is_read <= #1 1'b0;
+     else if(~enable)
+       is_read <= #1 1'b0;
+     else if((ser_ctr == 7)&&(serial_addr[6]==1))
+       is_read <= #1 1'b1;
+   
+   always @(posedge serial_clock, posedge reset)
+     if(reset)
+       begin
+\t  serial_addr <= #1 7'b0;
+\t  serial_data <= #1 32'b0;
+\t  write_done <= #1 1'b0;
+       end
+     else if(~enable)
+       begin
+\t  //serial_addr <= #1 7'b0;
+\t  //serial_data <= #1 32'b0;
+\t  write_done <= #1 1'b0;
+       end
+     else 
+       begin
+\t  if(~is_read && (ser_ctr == 39))
+\t    write_done <= #1 1'b1;
+\t  else
+\t    write_done <= #1 1'b0;
+\t  if(is_read & (ser_ctr==8))
+\t    case (serial_addr)
+\t      7'd1: serial_data <= #1 readback_0;
+\t      7'd2: serial_data <= #1 readback_1;
+\t      7'd3: serial_data <= #1 readback_2;
+\t      7'd4: serial_data <= #1 readback_3;
+\t      7'd5: serial_data <= #1 readback_4;
+\t      7'd6: serial_data <= #1 readback_5;
+\t      7'd7: serial_data <= #1 readback_6;
+\t      7'd8: serial_data <= #1 readback_7;
+\t      default: serial_data <= #1 32'd0;
+\t    endcase // case(serial_addr)
+\t  else if(ser_ctr >= 8)
+\t    serial_data <= #1 {serial_data[30:0],serial_data_in};
+\t  else if(ser_ctr < 8)
+\t    serial_addr <= #1 {serial_addr[5:0],serial_data_in};
+       end // else: !if(~enable)
+
+   reg enable_d1, enable_d2;
+   always @(posedge master_clk)
+     begin
+\tenable_d1 <= #1 enable;
+\tenable_d2 <= #1 enable_d1;
+     end
+
+   assign serial_strobe = enable_d2 & ~enable_d1;
+   
+endmodule // serial_io
+
+
+"
+"//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module bustri (
+\tdata,
+\tenabledt,
+\ttridata);
+
+\tinput\t[15:0]  data;
+\tinput\t  enabledt;
+\tinout\t[15:0]  tridata;
+
+endmodule
+
+"
+"module usb_fifo_reader (
+      input usbclk,
+      input bus_reset, 
+      input RD,
+      output rdreq,
+      );
+      
+    // FX2 Bug Fix
+    reg [8:0] read_count;
+    always @(negedge usbclk)
+        if(bus_reset)
+            read_count <= #1 9'd0;
+        else if(RD & ~read_count[8])
+            read_count <= #1 read_count + 9'd1;
+        else
+            read_count <= #1 RD ? read_count : 9'b0;
+            
+    assign rdreq = RD & ~read_count[8];
+    
+    
+ 
+endmodule
+       
+   
+   "
+"// megafunction wizard: %FIFO%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: dcfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_4kx16_dc.v\r
+// Megafunction Name(s):\r
+// \t\t\tdcfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module fifo_4kx16_dc (\r
+\taclr,\r
+\tdata,\r
+\trdclk,\r
+\trdreq,\r
+\twrclk,\r
+\twrreq,\r
+\tq,\r
+\trdempty,\r
+\trdusedw,\r
+\twrfull,\r
+\twrusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t[15:0]  data;\r
+\tinput\t  rdclk;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrclk;\r
+\tinput\t  wrreq;\r
+\toutput\t[15:0]  q;\r
+\toutput\t  rdempty;\r
+\toutput\t[11:0]  rdusedw;\r
+\toutput\t  wrfull;\r
+\toutput\t[11:0]  wrusedw;\r
+\r
+\twire  sub_wire0;\r
+\twire [11:0] sub_wire1;\r
+\twire  sub_wire2;\r
+\twire [15:0] sub_wire3;\r
+\twire [11:0] sub_wire4;\r
+\twire  rdempty = sub_wire0;\r
+\twire [11:0] wrusedw = sub_wire1[11:0];\r
+\twire  wrfull = sub_wire2;\r
+\twire [15:0] q = sub_wire3[15:0];\r
+\twire [11:0] rdusedw = sub_wire4[11:0];\r
+\r
+\tdcfifo\tdcfifo_component (\r
+\t\t\t\t.wrclk (wrclk),\r
+\t\t\t\t.rdreq (rdreq),\r
+\t\t\t\t.aclr (aclr),\r
+\t\t\t\t.rdclk (rdclk),\r
+\t\t\t\t.wrreq (wrreq),\r
+\t\t\t\t.data (data),\r
+\t\t\t\t.rdempty (sub_wire0),\r
+\t\t\t\t.wrusedw (sub_wire1),\r
+\t\t\t\t.wrfull (sub_wire2),\r
+\t\t\t\t.q (sub_wire3),\r
+\t\t\t\t.rdusedw (sub_wire4)\r
+\t\t\t\t// synopsys translate_off\r
+\t\t\t\t,\r
+\t\t\t\t.wrempty (),\r
+\t\t\t\t.rdfull ()\r
+\t\t\t\t// synopsys translate_on\r
+\t\t\t\t);\r
+\tdefparam\r
+\t\tdcfifo_component.add_ram_output_register = ""OFF"",\r
+\t\tdcfifo_component.clocks_are_synchronized = ""FALSE"",\r
+\t\tdcfifo_component.intended_device_family = ""Cyclone"",\r
+\t\tdcfifo_component.lpm_numwords = 4096,\r
+\t\tdcfifo_component.lpm_showahead = ""ON"",\r
+\t\tdcfifo_component.lpm_type = ""dcfifo"",\r
+\t\tdcfifo_component.lpm_width = 16,\r
+\t\tdcfifo_component.lpm_widthu = 12,\r
+\t\tdcfifo_component.overflow_checking = ""OFF"",\r
+\t\tdcfifo_component.underflow_checking = ""OFF"",\r
+\t\tdcfifo_component.use_eab = ""ON"";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""4096""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""16""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""4096""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""12""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk\r
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]\r
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk\r
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0\r
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0\r
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0\r
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0\r
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0\r
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE\r
+"
+"module usb_packet_fifo 
+  ( input       reset,
+    input       clock_in,
+    input       clock_out,
+    input       [15:0]ram_data_in,
+    input       write_enable,
+    output  reg [15:0]ram_data_out,
+    output  reg pkt_waiting,
+    output  reg have_space,
+    input       read_enable,
+    input       skip_packet          ) ;
+
+    /* Some parameters for usage later on */
+    parameter DATA_WIDTH = 16 ;
+    parameter NUM_PACKETS = 4 ;
+
+    /* Create the RAM here */
+    reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
+
+    /* Create the address signals */
+    reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
+    reg [7:0] usb_ram_offset ;
+    reg [1:0] usb_ram_packet ;
+
+    wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
+    reg isfull;
+
+    assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
+    
+    // Check if there is one full packet to process
+    always @(usb_ram_ain, usb_ram_aout)
+    begin
+        if (reset)
+            pkt_waiting <= 0;
+        else if (usb_ram_ain == usb_ram_aout)
+            pkt_waiting <= isfull;
+        else if (usb_ram_ain > usb_ram_aout)
+            pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
+        else
+            pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
+    end
+    
+    // Check if there is room
+    always @(usb_ram_ain, usb_ram_aout)
+    begin
+        if (reset)
+            have_space <= 1;
+        else if (usb_ram_ain == usb_ram_aout)
+            have_space <= ~isfull;   
+        else if (usb_ram_ain > usb_ram_aout)
+            have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
+        else
+            have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
+    end
+
+    /* RAM Write Address process */
+    always @(posedge clock_in)
+    begin
+        if( reset )
+            usb_ram_ain <= 0 ;
+        else
+            if( write_enable ) 
+              begin
+                usb_ram_ain <= usb_ram_ain + 1 ;
+                if (usb_ram_ain + 1 == usb_ram_aout)
+                   isfull <= 1;
+              end
+    end
+
+    /* RAM Writing process */
+    always @(posedge clock_in)
+    begin
+        if( write_enable ) 
+          begin
+            usb_ram[usb_ram_ain] <= ram_data_in ;
+          end
+    end
+
+    /* RAM Read Address process */
+    always @(posedge clock_out)
+    begin
+        if( reset ) 
+          begin
+            usb_ram_packet <= 0 ;
+            usb_ram_offset <= 0 ;
+            isfull <= 0;
+          end
+        else
+            if( skip_packet )
+              begin
+                usb_ram_packet <= usb_ram_packet + 1 ;
+                usb_ram_offset <= 0 ;
+              end
+            else if(read_enable)
+                if( usb_ram_offset == 8'b11111111 )
+                  begin
+                    usb_ram_offset <= 0 ;
+                    usb_ram_packet <= usb_ram_packet + 1 ;
+                  end
+                else
+                    usb_ram_offset <= usb_ram_offset + 1 ;
+            if (usb_ram_ain == usb_ram_aout)
+               isfull <= 0;                       
+    end
+
+    /* RAM Reading Process */
+    always @(posedge clock_out)
+    begin
+        ram_data_out <= usb_ram[usb_ram_aout] ;
+    end
+
+endmodule"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module rx_chain_dual
+  (input clock,
+   input clock_2x,
+   input reset,
+   input enable,
+   input wire [7:0] decim_rate,
+   input sample_strobe,
+   input decimator_strobe,
+   input wire [31:0] freq0,
+   input wire [15:0] i_in0,
+   input wire [15:0] q_in0,
+   output wire [15:0] i_out0,
+   output wire [15:0] q_out0,
+   input wire [31:0] freq1,
+   input wire [15:0] i_in1,
+   input wire [15:0] q_in1,
+   output wire [15:0] i_out1,
+   output wire [15:0] q_out1
+   );
+
+   wire [15:0] phase;
+   wire [15:0] bb_i, bb_q;
+   wire [15:0] i_in, q_in;
+   
+   wire [31:0] phase0;
+   wire [31:0] phase1;
+   reg [15:0] bb_i0, bb_q0;
+   reg [15:0] bb_i1, bb_q1;
+
+   // We want to time-share the CORDIC by double-clocking it
+   
+   phase_acc rx_phase_acc_0
+     (.clk(clock),.reset(reset),.enable(enable),
+      .strobe(sample_strobe),.freq(freq0),.phase(phase0) );
+
+   phase_acc rx_phase_acc_1
+     (.clk(clock),.reset(reset),.enable(enable),
+      .strobe(sample_strobe),.freq(freq1),.phase(phase1) );
+   
+   assign phase = clock ? phase0[31:16] : phase1[31:16];
+   assign i_in = clock ? i_in0 : i_in1;
+   assign q_in = clock ? q_in0 : q_in1;
+
+// This appears reversed because of the number of CORDIC stages
+   always @(posedge clock_2x)
+     if(clock)
+       begin
+\t  bb_i1 <= #1 bb_i;
+\t  bb_q1 <= #1 bb_q;
+       end
+     else
+       begin
+\t  bb_i0 <= #1 bb_i;
+\t  bb_q0 <= #1 bb_q;
+       end
+\t
+   cordic rx_cordic
+     ( .clock(clock_2x),.reset(reset),.enable(enable), 
+       .xi(i_in),.yi(q_in),.zi(phase),
+       .xo(bb_i),.yo(bb_q),.zo() );
+   
+   cic_decim cic_decim_i_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_i0),.signal_out(i_out0) );
+
+   cic_decim cic_decim_q_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_q0),.signal_out(q_out0) );
+
+   cic_decim cic_decim_i_1
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_i1),.signal_out(i_out1) );
+
+   cic_decim cic_decim_q_1
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_q1),.signal_out(q_out1) );
+
+endmodule // rx_chain
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+// NOTE   This only works for N=4, max interp rate of 128
+// NOTE   signal ""rate"" is ONE LESS THAN the actual rate
+
+module cic_int_shifter(rate,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 21;
+   
+   input [7:0] rate;
+   input       wire [bw+maxbitgain-1:0] signal_in;
+   output      reg [bw-1:0] signal_out;
+
+   function [4:0] bitgain;
+      input [7:0] rate;
+      case(rate)
+\t// Exact Cases
+\t8\'d4 : bitgain = 6;
+\t8\'d8 : bitgain = 9;
+\t8\'d16 : bitgain = 12;
+\t8\'d32 : bitgain = 15;
+\t8\'d64 : bitgain = 18;
+\t8\'d128 : bitgain = 21;
+\t
+\t// Nearest without overflow
+\t8\'d5 : bitgain = 7;
+\t8\'d6 : bitgain = 8;
+\t8\'d7 : bitgain = 9;
+\t8\'d9,8\'d10 : bitgain = 10;
+\t8\'d11,8\'d12 : bitgain = 11;
+\t8\'d13,8\'d14,8\'d15 : bitgain = 12;
+\t8\'d17,8\'d18,8\'d19,8\'d20 : bitgain = 13;
+\t8\'d21,8\'d22,8\'d23,8\'d24,8\'d25 : bitgain = 14;
+\t8\'d26,8\'d27,8\'d28,8\'d29,8\'d30,8\'d31 : bitgain = 15;
+\t8\'d33,8\'d34,8\'d35,8\'d36,8\'d37,8\'d38,8\'d39,8\'d40 : bitgain = 16;
+\t8\'d41,8\'d42,8\'d43,8\'d44,8\'d45,8\'d46,8\'d47,8\'d48,8\'d49,8\'d50 : bitgain = 17;
+\t8\'d51,8\'d52,8\'d53,8\'d54,8\'d55,8\'d56,8\'d57,8\'d58,8\'d59,8\'d60,8\'d61,8\'d62,8\'d63 : bitgain = 18;
+\t8\'d65,8\'d66,8\'d67,8\'d68,8\'d69,8\'d70,8\'d71,8\'d72,8\'d73,8\'d74,8\'d75,8\'d76,8\'d77,8\'d78,8\'d79,8\'d80 : bitgain = 19;
+\t8\'d81,8\'d82,8\'d83,8\'d84,8\'d85,8\'d86,8\'d87,8\'d88,8\'d89,8\'d90,8\'d91,8\'d92,8\'d93,8\'d94,8\'d95,8\'d96,8\'d97,8\'d98,8\'d99,8\'d100,8\'d101 : bitgain = 20;
+\t
+\tdefault : bitgain = 19;
+      endcase // case(rate)
+   endfunction // bitgain
+   
+   wire [4:0] \t  shift = bitgain(rate+1);
+   
+   // We should be able to do this, but can\'t ....
+   // assign \t  signal_out = signal_in[shift+bw-1:shift];
+   
+   always @*
+     case(shift)
+       5\'d6  : signal_out = signal_in[6+bw-1:6];
+       5\'d9  : signal_out = signal_in[9+bw-1:9];
+       5\'d12 : signal_out = signal_in[12+bw-1:12];
+       5\'d15 : signal_out = signal_in[15+bw-1:15];
+       5\'d18 : signal_out = signal_in[18+bw-1:18];
+       5\'d21 : signal_out = signal_in[21+bw-1:21];
+       
+       5\'d7  : signal_out = signal_in[7+bw-1:7];
+       5\'d8  : signal_out = signal_in[8+bw-1:8];
+       5\'d10 : signal_out = signal_in[10+bw-1:10];
+       5\'d11 : signal_out = signal_in[11+bw-1:11];
+       5\'d13 : signal_out = signal_in[13+bw-1:13];
+       5\'d14 : signal_out = signal_in[14+bw-1:14];
+       5\'d16 : signal_out = signal_in[16+bw-1:16];
+       5\'d17 : signal_out = signal_in[17+bw-1:17];
+       5\'d19 : signal_out = signal_in[19+bw-1:19];
+       5\'d20 : signal_out = signal_in[20+bw-1:20];
+       
+       default : signal_out = signal_in[21+bw-1:21];
+     endcase // case(shift)
+
+endmodule // cic_int_shifter
+
+"
+"// megafunction wizard: %FIFO%VBB%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: scfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_1kx16.v\r
+// Megafunction Name(s):\r
+// \t\t\tscfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+module fifo_1kx16 (\r
+\taclr,\r
+\tclock,\r
+\tdata,\r
+\trdreq,\r
+\twrreq,\r
+\talmost_empty,\r
+\tempty,\r
+\tfull,\r
+\tq,\r
+\tusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t  clock;\r
+\tinput\t[15:0]  data;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrreq;\r
+\toutput\t  almost_empty;\r
+\toutput\t  empty;\r
+\toutput\t  full;\r
+\toutput\t[15:0]  q;\r
+\toutput\t[9:0]  usedw;\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""504""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""1024""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""1""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""2""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""0""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""16""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""0""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC ""504""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_HINT STRING ""RAM_BLOCK_TYPE=M4K""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""1024""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""OFF""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""scfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""10""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""ON""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""ON""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr\r
+// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty\r
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0\r
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0\r
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0\r
+// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE\r
+"
+"module register_io
+\t(clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr,
+\t rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3, 
+     atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate, decim_rate, 
+     atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1,
+     atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3, 
+     txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);   
+\t
+\tinput clk;
+\tinput reset;
+\tinput wire [1:0] enable;
+\tinput wire [6:0] addr; 
+\tinput wire [31:0] datain;
+\toutput reg [31:0] dataout;
+\toutput wire [15:0] debugbus;
+\toutput reg [6:0] addr_wr;
+\toutput reg [31:0] data_wr;
+\toutput wire strobe_wr; 
+\tinput wire [31:0] rssi_0;
+\tinput wire [31:0] rssi_1;
+\tinput wire [31:0] rssi_2; 
+\tinput wire [31:0] rssi_3; 
+\toutput wire [31:0] threshhold;
+\toutput wire [31:0] rssi_wait;
+\tinput wire [15:0] reg_0;
+\tinput wire [15:0] reg_1; 
+\tinput wire [15:0] reg_2; 
+\tinput wire [15:0] reg_3;
+\tinput wire [11:0] atr_tx_delay;
+\tinput wire [11:0] atr_rx_delay;
+\tinput wire [7:0]  master_controls;
+\tinput wire [3:0]  debug_en;
+\tinput wire [15:0] atr_mask_0;
+\tinput wire [15:0] atr_txval_0;
+\tinput wire [15:0] atr_rxval_0;
+\tinput wire [15:0] atr_mask_1;
+\tinput wire [15:0] atr_txval_1;
+\tinput wire [15:0] atr_rxval_1;
+\tinput wire [15:0] atr_mask_2;
+\tinput wire [15:0] atr_txval_2;
+\tinput wire [15:0] atr_rxval_2;
+\tinput wire [15:0] atr_mask_3;
+\tinput wire [15:0] atr_txval_3;
+\tinput wire [15:0] atr_rxval_3;
+\tinput wire [7:0]  txa_refclk;
+\tinput wire [7:0]  txb_refclk;
+\tinput wire [7:0]  rxa_refclk;
+\tinput wire [7:0]  rxb_refclk;
+\tinput wire [7:0]  interp_rate;
+\tinput wire [7:0]  decim_rate;
+\tinput wire [7:0]  misc;
+\tinput wire [31:0] txmux;
+\t
+\twire [31:0] bundle[43:0]; 
+   assign bundle[0] = 32'hFFFFFFFF;
+   assign bundle[1] = 32'hFFFFFFFF;
+   assign bundle[2] = {20'd0, atr_tx_delay};
+   assign bundle[3] = {20'd0, atr_rx_delay};
+   assign bundle[4] = {24'sd0, master_controls};
+   assign bundle[5] = 32'hFFFFFFFF;
+   assign bundle[6] = 32'hFFFFFFFF;
+   assign bundle[7] = 32'hFFFFFFFF;
+   assign bundle[8] = 32'hFFFFFFFF;
+   assign bundle[9] = {15'd0, reg_0};
+   assign bundle[10] = {15'd0, reg_1};
+   assign bundle[11] = {15'd0, reg_2};
+   assign bundle[12] = {15'd0, reg_3};
+   assign bundle[13] = {15'd0, misc};
+   assign bundle[14] = {28'd0, debug_en};
+   assign bundle[15] = 32'hFFFFFFFF;
+   assign bundle[16] = 32'hFFFFFFFF;
+   assign bundle[17] = 32'hFFFFFFFF;
+   assign bundle[18] = 32'hFFFFFFFF;
+   assign bundle[19] = 32'hFFFFFFFF;
+   assign bundle[20] = {16'd0, atr_mask_0};
+   assign bundle[21] = {16'd0, atr_txval_0};
+   assign bundle[22] = {16'd0, atr_rxval_0};
+   assign bundle[23] = {16'd0, atr_mask_1};
+   assign bundle[24] = {16'd0, atr_txval_1};
+   assign bundle[25] = {16'd0, atr_rxval_1};
+   assign bundle[26] = {16'd0, atr_mask_2};
+   assign bundle[27] = {16'd0, atr_txval_2};
+   assign bundle[28] = {16'd0, atr_rxval_2};
+   assign bundle[29] = {16'd0, atr_mask_3};
+   assign bundle[30] = {16'd0, atr_txval_3};
+   assign bundle[31] = {16'd0, atr_rxval_3};
+   assign bundle[32] = {24'd0, interp_rate};
+   assign bundle[33] = {24'd0, decim_rate};
+   assign bundle[34] = 32'hFFFFFFFF;
+   assign bundle[35] = 32'hFFFFFFFF;
+   assign bundle[36] = 32'hFFFFFFFF;
+   assign bundle[37] = 32'hFFFFFFFF;
+   assign bundle[38] = 32'hFFFFFFFF;
+   assign bundle[39] = txmux;
+   assign bundle[40] = {24'd0, txa_refclk};
+   assign bundle[41] = {24'd0, rxa_refclk};
+   assign bundle[42] = {24'd0, txb_refclk};
+   assign bundle[43] = {24'd0, rxb_refclk};  
+
+\treg strobe;
+\twire [31:0] out[7:0];
+\tassign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
+\tassign threshhold = out[1];
+\tassign rssi_wait = out[2];
+\tassign strobe_wr = strobe;
+\t
+\talways @(*)
+        if (reset | ~enable[1])
+           begin
+             strobe <= 0;
+\t\t     dataout <= 0;
+\t\t   end
+\t\telse
+\t\t   begin
+\t         if (enable[0])
+\t           begin
+\t             //read
+\t\t\t\tif (addr <= 7'd43)
+\t\t\t\t\tdataout <= bundle[addr];
+\t\t\t\telse if (addr <= 7'd57 && addr >= 7'd50)
+\t\t\t\t\tdataout <= out[addr-7'd50];
+\t\t\t\telse
+\t\t\t\t\tdataout <= 32'hFFFFFFFF; \t
+\t            strobe <= 0;
+              end
+             else
+               begin
+                 //write
+\t             dataout <= dataout;
+                 strobe <= 1;
+\t\t\t\t data_wr <= datain;
+\t\t\t\t addr_wr <= addr;
+               end
+          end
+
+//register declarations
+    setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));
+    setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
+    setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
+    setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
+    setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
+    setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
+    setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
+    setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));
+endmodule\t
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+
+// DDC block
+
+module ddc(input clock,
+\t\t\tinput reset,
+\t\t\tinput enable,
+\t\t\tinput [3:0] rate1,
+\t\t\tinput [3:0] rate2,
+\t\t\toutput strobe,
+\t\t\tinput [31:0] freq,
+\t\t\tinput [15:0] i_in,
+\t\t\tinput [15:0] q_in,
+\t\t\toutput [15:0] i_out,
+\t\t\toutput [15:0] q_out
+\t\t\t);
+   parameter bw = 16;
+   parameter zw = 16;
+
+\twire [15:0] i_cordic_out, q_cordic_out;
+\twire [31:0] phase;
+
+\twire strobe1, strobe2;
+\treg [3:0] strobe_ctr1,strobe_ctr2;
+
+\talways @(posedge clock)
+\t\tif(reset | ~enable)
+\t\t\tstrobe_ctr2 <= #1 4'd0;
+\t\telse if(strobe2)
+\t\t\tstrobe_ctr2 <= #1 4'd0;
+\t\telse\t
+\t\t\tstrobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
+\t\t\t\t
+\talways @(posedge clock)
+\t\tif(reset | ~enable)
+\t\t\tstrobe_ctr1 <= #1 4'd0;
+\t\telse if(strobe1)
+\t\t\tstrobe_ctr1 <= #1 4'd0;
+\t\telse if(strobe2)
+\t\t\tstrobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
+\t\t\t\t
+
+\tassign strobe2 = enable & ( strobe_ctr2 == rate2 );
+\tassign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
+
+\tassign strobe = strobe1;
+
+\tfunction [2:0] log_ceil;
+\tinput [3:0] val;
+\t
+\t\tlog_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; 
+\tendfunction\t
+\t
+\twire [2:0] shift1 = log_ceil(rate1);
+\twire [2:0] shift2 = log_ceil(rate2);
+\t
+\tcordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
+\t\tcordic(.clock(clock), .reset(reset), .enable(enable),
+\t\t\t.xi(i_in), .yi(q_in), .zi(phase[31:32-zw]), 
+\t\t\t.xo(i_cordic_out), .yo(q_cordic_out), .zo()  );
+\t\t
+\tcic_decim_2stage #(.bw(bw),.N(4)) 
+\t\tdecim_i(.clock(clock),.reset(reset),.enable(enable),
+\t\t\t.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
+\t\t\t.signal_in(i_cordic_out),.signal_out(i_out));
+\t\t\t
+\tcic_decim_2stage #(.bw(bw),.N(4)) 
+\t\tdecim_q(.clock(clock),.reset(reset),.enable(enable),
+\t\t\t.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
+\t\t\t.signal_in(q_cordic_out),.signal_out(q_out));
+\t
+\tphase_acc #(.resolution(32))
+\t\tnco (.clk(clock),.reset(reset),.enable(enable),
+\t\t\t.freq(freq),.phase(phase));
+\t\t
+endmodule
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
+   reg [7:0] counter;
+   
+   // FIXME maybe should use PLL or switch to double edge version\t
+\t
+   always @(posedge in_clk or posedge reset)
+     if(reset)
+       counter <= #1 8'd0;
+     else if(counter == 0)
+       counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
+     else
+       counter <= #1 counter-8'd1;
+   
+   always @(posedge in_clk or posedge reset)
+     if(reset)
+       out_clk <= #1 1'b0;
+     else if(counter == 0)
+       out_clk <= #1 ~out_clk;
+   
+endmodule // clk_divider
+
+"
+"fifo_4kx16_dc\tfifo_4kx16_dc_inst (\r
+\t.aclr ( aclr_sig ),\r
+\t.data ( data_sig ),\r
+\t.rdclk ( rdclk_sig ),\r
+\t.rdreq ( rdreq_sig ),\r
+\t.wrclk ( wrclk_sig ),\r
+\t.wrreq ( wrreq_sig ),\r
+\t.q ( q_sig ),\r
+\t.rdempty ( rdempty_sig ),\r
+\t.rdusedw ( rdusedw_sig ),\r
+\t.wrfull ( wrfull_sig ),\r
+\t.wrusedw ( wrusedw_sig )\r
+\t);\r
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
+   parameter bitwidth = 16;
+   parameter zwidth = 16;
+   
+   input clock;
+   input reset;
+   input enable;
+   input [bitwidth-1:0] xi, yi;
+   output [bitwidth-1:0] xo, yo;
+   input [zwidth-1:0] zi;
+   output [zwidth-1:0] zo;
+   
+   reg [bitwidth+1:0] \t x0,y0;
+   reg [zwidth-2:0] \t z0;
+   wire [bitwidth+1:0] \t x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
+   wire [bitwidth+1:0] \t y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
+   wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
+   
+   wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
+   wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
+
+   // Compute consts.  Would be easier if vlog had atan...
+   // see gen_cordic_consts.py
+   
+`define c00 16'd8192
+`define c01 16'd4836
+`define c02 16'd2555
+`define c03 16'd1297
+`define c04 16'd651
+`define c05 16'd326
+`define c06 16'd163
+`define c07 16'd81
+`define c08 16'd41
+`define c09 16'd20
+`define c10 16'd10
+`define c11 16'd5
+`define c12 16'd3
+`define c13 16'd1
+`define c14 16'd1
+`define c15 16'd0
+`define c16 16'd0
+
+   always @(posedge clock)
+     if(reset)
+       begin
+\t  x0   <= #1 0; y0   <= #1 0;  z0   <= #1 0;
+       end
+     else if(enable)
+       begin
+\t  z0 <= #1 zi[zwidth-2:0];
+\t  case (zi[zwidth-1:zwidth-2])
+\t    2'b00, 2'b11 : 
+\t      begin
+\t\t x0 <= #1 xi_ext;
+\t\t y0 <= #1 yi_ext;
+\t      end
+\t    2'b01, 2'b10 :
+\t      begin
+\t\t x0 <= #1 -xi_ext;
+\t\t y0 <= #1 -yi_ext;
+\t      end
+\t  endcase // case(zi[zwidth-1:zwidth-2])
+       end // else: !if(reset)
+   
+   // FIXME need to handle variable number of stages
+   // FIXME should be able to narrow zwidth but quartus makes it bigger...
+   // This would be easier if arrays worked better in vlog...
+   cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
+   cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
+   cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
+   cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
+   cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
+   cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
+   cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
+   cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
+   cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
+   cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
+   cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
+   cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
+
+   assign xo = x12[bitwidth:1];  
+   assign yo = y12[bitwidth:1];
+   //assign xo = x12[bitwidth+1:2];  // CORDIC gain is ~1.6, plus gain from rotating vectors
+   //assign yo = y12[bitwidth+1:2];
+   assign zo = z12;\t\t  
+
+endmodule // cordic
+
+"
+"//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module mylpm_addsub (
+\tadd_sub,
+\tdataa,
+\tdatab,
+\tclock,
+\tresult);
+
+\tinput\t  add_sub;
+\tinput\t[15:0]  dataa;
+\tinput\t[15:0]  datab;
+\tinput\t  clock;
+\toutput\t[15:0]  result;
+
+endmodule
+
+"
+"add32\tadd32_inst (
+\t.dataa ( dataa_sig ),
+\t.datab ( datab_sig ),
+\t.result ( result_sig )
+\t);
+"
+"
+
+module fifo_2k
+  (  input [15:0] data,
+     input \twrreq,
+     input \trdreq,
+     input \trdclk,
+     input \twrclk,
+     input \taclr,
+     output [15:0] q,
+     output \t rdfull,
+     output \t rdempty,
+     output [10:0] rdusedw,
+     output \t wrfull,
+     output \t wrempty,
+     output [10:0]  wrusedw
+     );
+
+fifo #(.width(16),.depth(2048),.addr_bits(11)) fifo_2k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_1k
+   
+"
+"// megafunction wizard: %FIFO%VBB%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: scfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_1kx16.v\r
+// Megafunction Name(s):\r
+// \t\t\tscfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+module fifo_1kx16 (\r
+\taclr,\r
+\tclock,\r
+\tdata,\r
+\trdreq,\r
+\twrreq,\r
+\talmost_empty,\r
+\tempty,\r
+\tfull,\r
+\tq,\r
+\tusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t  clock;\r
+\tinput\t[15:0]  data;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrreq;\r
+\toutput\t  almost_empty;\r
+\toutput\t  empty;\r
+\toutput\t  full;\r
+\toutput\t[15:0]  q;\r
+\toutput\t[9:0]  usedw;\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""504""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""1024""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""1""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""2""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""0""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""16""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""0""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC ""504""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_HINT STRING ""RAM_BLOCK_TYPE=M4K""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""1024""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""OFF""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""scfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""10""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""ON""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""ON""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr\r
+// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty\r
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0\r
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0\r
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0\r
+// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE\r
+"
+"//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module sub32 (
+\tdataa,
+\tdatab,
+\tclock,
+\taclr,
+\tclken,
+\tresult)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[31:0]  dataa;
+\tinput\t[31:0]  datab;
+\tinput\t  clock;
+\tinput\t  aclr;
+\tinput\t  clken;
+\toutput\t[31:0]  result;
+
+endmodule
+
+"
+"// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub 
+
+// ============================================================
+// File Name: sub32.v
+// Megafunction Name(s):
+// \t\t\tlpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
+
+//synthesis_resources = lut 32 
+module  sub32_add_sub_cqa
+\t( 
+\taclr,
+\tclken,
+\tclock,
+\tdataa,
+\tdatab,
+\tresult) /* synthesis synthesis_clearbox=1 */;
+\tinput   aclr;
+\tinput   clken;
+\tinput   clock;
+\tinput   [31:0]  dataa;
+\tinput   [31:0]  datab;
+\toutput   [31:0]  result;
+
+\twire  [0:0]   wire_add_sub_cella_0cout;
+\twire  [0:0]   wire_add_sub_cella_1cout;
+\twire  [0:0]   wire_add_sub_cella_2cout;
+\twire  [0:0]   wire_add_sub_cella_3cout;
+\twire  [0:0]   wire_add_sub_cella_4cout;
+\twire  [0:0]   wire_add_sub_cella_5cout;
+\twire  [0:0]   wire_add_sub_cella_6cout;
+\twire  [0:0]   wire_add_sub_cella_7cout;
+\twire  [0:0]   wire_add_sub_cella_8cout;
+\twire  [0:0]   wire_add_sub_cella_9cout;
+\twire  [0:0]   wire_add_sub_cella_10cout;
+\twire  [0:0]   wire_add_sub_cella_11cout;
+\twire  [0:0]   wire_add_sub_cella_12cout;
+\twire  [0:0]   wire_add_sub_cella_13cout;
+\twire  [0:0]   wire_add_sub_cella_14cout;
+\twire  [0:0]   wire_add_sub_cella_15cout;
+\twire  [0:0]   wire_add_sub_cella_16cout;
+\twire  [0:0]   wire_add_sub_cella_17cout;
+\twire  [0:0]   wire_add_sub_cella_18cout;
+\twire  [0:0]   wire_add_sub_cella_19cout;
+\twire  [0:0]   wire_add_sub_cella_20cout;
+\twire  [0:0]   wire_add_sub_cella_21cout;
+\twire  [0:0]   wire_add_sub_cella_22cout;
+\twire  [0:0]   wire_add_sub_cella_23cout;
+\twire  [0:0]   wire_add_sub_cella_24cout;
+\twire  [0:0]   wire_add_sub_cella_25cout;
+\twire  [0:0]   wire_add_sub_cella_26cout;
+\twire  [0:0]   wire_add_sub_cella_27cout;
+\twire  [0:0]   wire_add_sub_cella_28cout;
+\twire  [0:0]   wire_add_sub_cella_29cout;
+\twire  [0:0]   wire_add_sub_cella_30cout;
+\twire  [31:0]   wire_add_sub_cella_dataa;
+\twire  [31:0]   wire_add_sub_cella_datab;
+\twire  [31:0]   wire_add_sub_cella_regout;
+
+\tstratix_lcell   add_sub_cella_0
+\t( 
+\t.aclr(aclr),
+\t.cin(1\'b1),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_0cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[0:0]),
+\t.datab(wire_add_sub_cella_datab[0:0]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[0:0]));
+\tdefparam
+\t\tadd_sub_cella_0.cin_used = ""true"",
+\t\tadd_sub_cella_0.lut_mask = ""69b2"",
+\t\tadd_sub_cella_0.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_0.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_0.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_1
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_0cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_1cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[1:1]),
+\t.datab(wire_add_sub_cella_datab[1:1]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[1:1]));
+\tdefparam
+\t\tadd_sub_cella_1.cin_used = ""true"",
+\t\tadd_sub_cella_1.lut_mask = ""69b2"",
+\t\tadd_sub_cella_1.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_1.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_1.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_2
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_1cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_2cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[2:2]),
+\t.datab(wire_add_sub_cella_datab[2:2]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[2:2]));
+\tdefparam
+\t\tadd_sub_cella_2.cin_used = ""true"",
+\t\tadd_sub_cella_2.lut_mask = ""69b2"",
+\t\tadd_sub_cella_2.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_2.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_2.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_3
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_2cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_3cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[3:3]),
+\t.datab(wire_add_sub_cella_datab[3:3]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[3:3]));
+\tdefparam
+\t\tadd_sub_cella_3.cin_used = ""true"",
+\t\tadd_sub_cella_3.lut_mask = ""69b2"",
+\t\tadd_sub_cella_3.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_3.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_3.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_4
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_3cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_4cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[4:4]),
+\t.datab(wire_add_sub_cella_datab[4:4]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[4:4]));
+\tdefparam
+\t\tadd_sub_cella_4.cin_used = ""true"",
+\t\tadd_sub_cella_4.lut_mask = ""69b2"",
+\t\tadd_sub_cella_4.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_4.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_4.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_5
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_4cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_5cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[5:5]),
+\t.datab(wire_add_sub_cella_datab[5:5]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[5:5]));
+\tdefparam
+\t\tadd_sub_cella_5.cin_used = ""true"",
+\t\tadd_sub_cella_5.lut_mask = ""69b2"",
+\t\tadd_sub_cella_5.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_5.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_5.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_6
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_5cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_6cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[6:6]),
+\t.datab(wire_add_sub_cella_datab[6:6]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[6:6]));
+\tdefparam
+\t\tadd_sub_cella_6.cin_used = ""true"",
+\t\tadd_sub_cella_6.lut_mask = ""69b2"",
+\t\tadd_sub_cella_6.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_6.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_6.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_7
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_6cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_7cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[7:7]),
+\t.datab(wire_add_sub_cella_datab[7:7]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[7:7]));
+\tdefparam
+\t\tadd_sub_cella_7.cin_used = ""true"",
+\t\tadd_sub_cella_7.lut_mask = ""69b2"",
+\t\tadd_sub_cella_7.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_7.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_7.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_8
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_7cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_8cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[8:8]),
+\t.datab(wire_add_sub_cella_datab[8:8]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[8:8]));
+\tdefparam
+\t\tadd_sub_cella_8.cin_used = ""true"",
+\t\tadd_sub_cella_8.lut_mask = ""69b2"",
+\t\tadd_sub_cella_8.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_8.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_8.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_9
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_8cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_9cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[9:9]),
+\t.datab(wire_add_sub_cella_datab[9:9]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[9:9]));
+\tdefparam
+\t\tadd_sub_cella_9.cin_used = ""true"",
+\t\tadd_sub_cella_9.lut_mask = ""69b2"",
+\t\tadd_sub_cella_9.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_9.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_9.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_10
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_9cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_10cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[10:10]),
+\t.datab(wire_add_sub_cella_datab[10:10]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[10:10]));
+\tdefparam
+\t\tadd_sub_cella_10.cin_used = ""true"",
+\t\tadd_sub_cella_10.lut_mask = ""69b2"",
+\t\tadd_sub_cella_10.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_10.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_10.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_11
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_10cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_11cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[11:11]),
+\t.datab(wire_add_sub_cella_datab[11:11]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[11:11]));
+\tdefparam
+\t\tadd_sub_cella_11.cin_used = ""true"",
+\t\tadd_sub_cella_11.lut_mask = ""69b2"",
+\t\tadd_sub_cella_11.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_11.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_11.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_12
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_11cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_12cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[12:12]),
+\t.datab(wire_add_sub_cella_datab[12:12]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[12:12]));
+\tdefparam
+\t\tadd_sub_cella_12.cin_used = ""true"",
+\t\tadd_sub_cella_12.lut_mask = ""69b2"",
+\t\tadd_sub_cella_12.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_12.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_12.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_13
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_12cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_13cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[13:13]),
+\t.datab(wire_add_sub_cella_datab[13:13]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[13:13]));
+\tdefparam
+\t\tadd_sub_cella_13.cin_used = ""true"",
+\t\tadd_sub_cella_13.lut_mask = ""69b2"",
+\t\tadd_sub_cella_13.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_13.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_13.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_14
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_13cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_14cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[14:14]),
+\t.datab(wire_add_sub_cella_datab[14:14]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[14:14]));
+\tdefparam
+\t\tadd_sub_cella_14.cin_used = ""true"",
+\t\tadd_sub_cella_14.lut_mask = ""69b2"",
+\t\tadd_sub_cella_14.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_14.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_14.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_15
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_14cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_15cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[15:15]),
+\t.datab(wire_add_sub_cella_datab[15:15]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[15:15]));
+\tdefparam
+\t\tadd_sub_cella_15.cin_used = ""true"",
+\t\tadd_sub_cella_15.lut_mask = ""69b2"",
+\t\tadd_sub_cella_15.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_15.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_15.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_16
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_15cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_16cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[16:16]),
+\t.datab(wire_add_sub_cella_datab[16:16]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[16:16]));
+\tdefparam
+\t\tadd_sub_cella_16.cin_used = ""true"",
+\t\tadd_sub_cella_16.lut_mask = ""69b2"",
+\t\tadd_sub_cella_16.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_16.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_16.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_17
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_16cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_17cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[17:17]),
+\t.datab(wire_add_sub_cella_datab[17:17]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[17:17]));
+\tdefparam
+\t\tadd_sub_cella_17.cin_used = ""true"",
+\t\tadd_sub_cella_17.lut_mask = ""69b2"",
+\t\tadd_sub_cella_17.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_17.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_17.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_18
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_17cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_18cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[18:18]),
+\t.datab(wire_add_sub_cella_datab[18:18]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[18:18]));
+\tdefparam
+\t\tadd_sub_cella_18.cin_used = ""true"",
+\t\tadd_sub_cella_18.lut_mask = ""69b2"",
+\t\tadd_sub_cella_18.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_18.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_18.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_19
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_18cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_19cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[19:19]),
+\t.datab(wire_add_sub_cella_datab[19:19]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[19:19]));
+\tdefparam
+\t\tadd_sub_cella_19.cin_used = ""true"",
+\t\tadd_sub_cella_19.lut_mask = ""69b2"",
+\t\tadd_sub_cella_19.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_19.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_19.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_20
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_19cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_20cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[20:20]),
+\t.datab(wire_add_sub_cella_datab[20:20]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[20:20]));
+\tdefparam
+\t\tadd_sub_cella_20.cin_used = ""true"",
+\t\tadd_sub_cella_20.lut_mask = ""69b2"",
+\t\tadd_sub_cella_20.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_20.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_20.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_21
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_20cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_21cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[21:21]),
+\t.datab(wire_add_sub_cella_datab[21:21]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[21:21]));
+\tdefparam
+\t\tadd_sub_cella_21.cin_used = ""true"",
+\t\tadd_sub_cella_21.lut_mask = ""69b2"",
+\t\tadd_sub_cella_21.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_21.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_21.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_22
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_21cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_22cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[22:22]),
+\t.datab(wire_add_sub_cella_datab[22:22]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[22:22]));
+\tdefparam
+\t\tadd_sub_cella_22.cin_used = ""true"",
+\t\tadd_sub_cella_22.lut_mask = ""69b2"",
+\t\tadd_sub_cella_22.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_22.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_22.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_23
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_22cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_23cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[23:23]),
+\t.datab(wire_add_sub_cella_datab[23:23]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[23:23]));
+\tdefparam
+\t\tadd_sub_cella_23.cin_used = ""true"",
+\t\tadd_sub_cella_23.lut_mask = ""69b2"",
+\t\tadd_sub_cella_23.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_23.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_23.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_24
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_23cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_24cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[24:24]),
+\t.datab(wire_add_sub_cella_datab[24:24]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[24:24]));
+\tdefparam
+\t\tadd_sub_cella_24.cin_used = ""true"",
+\t\tadd_sub_cella_24.lut_mask = ""69b2"",
+\t\tadd_sub_cella_24.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_24.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_24.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_25
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_24cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_25cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[25:25]),
+\t.datab(wire_add_sub_cella_datab[25:25]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[25:25]));
+\tdefparam
+\t\tadd_sub_cella_25.cin_used = ""true"",
+\t\tadd_sub_cella_25.lut_mask = ""69b2"",
+\t\tadd_sub_cella_25.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_25.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_25.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_26
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_25cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_26cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[26:26]),
+\t.datab(wire_add_sub_cella_datab[26:26]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[26:26]));
+\tdefparam
+\t\tadd_sub_cella_26.cin_used = ""true"",
+\t\tadd_sub_cella_26.lut_mask = ""69b2"",
+\t\tadd_sub_cella_26.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_26.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_26.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_27
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_26cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_27cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[27:27]),
+\t.datab(wire_add_sub_cella_datab[27:27]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[27:27]));
+\tdefparam
+\t\tadd_sub_cella_27.cin_used = ""true"",
+\t\tadd_sub_cella_27.lut_mask = ""69b2"",
+\t\tadd_sub_cella_27.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_27.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_27.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_28
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_27cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_28cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[28:28]),
+\t.datab(wire_add_sub_cella_datab[28:28]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[28:28]));
+\tdefparam
+\t\tadd_sub_cella_28.cin_used = ""true"",
+\t\tadd_sub_cella_28.lut_mask = ""69b2"",
+\t\tadd_sub_cella_28.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_28.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_28.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_29
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_28cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_29cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[29:29]),
+\t.datab(wire_add_sub_cella_datab[29:29]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[29:29]));
+\tdefparam
+\t\tadd_sub_cella_29.cin_used = ""true"",
+\t\tadd_sub_cella_29.lut_mask = ""69b2"",
+\t\tadd_sub_cella_29.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_29.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_29.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_30
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_29cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_30cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[30:30]),
+\t.datab(wire_add_sub_cella_datab[30:30]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[30:30]));
+\tdefparam
+\t\tadd_sub_cella_30.cin_used = ""true"",
+\t\tadd_sub_cella_30.lut_mask = ""69b2"",
+\t\tadd_sub_cella_30.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_30.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_30.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_31
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_30cout[0:0]),
+\t.clk(clock),
+\t.dataa(wire_add_sub_cella_dataa[31:31]),
+\t.datab(wire_add_sub_cella_datab[31:31]),
+\t.ena(clken),
+\t.regout(wire_add_sub_cella_regout[31:31]));
+\tdefparam
+\t\tadd_sub_cella_31.cin_used = ""true"",
+\t\tadd_sub_cella_31.lut_mask = ""6969"",
+\t\tadd_sub_cella_31.operation_mode = ""normal"",
+\t\tadd_sub_cella_31.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_31.lpm_type = ""stratix_lcell"";
+\tassign
+\t\twire_add_sub_cella_dataa = dataa,
+\t\twire_add_sub_cella_datab = datab;
+\tassign
+\t\tresult = wire_add_sub_cella_regout;
+endmodule //sub32_add_sub_cqa
+//VALID FILE
+
+
+module sub32 (
+\tdataa,
+\tdatab,
+\tclock,
+\taclr,
+\tclken,
+\tresult)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[31:0]  dataa;
+\tinput\t[31:0]  datab;
+\tinput\t  clock;
+\tinput\t  aclr;
+\tinput\t  clken;
+\toutput\t[31:0]  result;
+
+\twire [31:0] sub_wire0;
+\twire [31:0] result = sub_wire0[31:0];
+
+\tsub32_add_sub_cqa\tsub32_add_sub_cqa_component (
+\t\t\t\t.dataa (dataa),
+\t\t\t\t.datab (datab),
+\t\t\t\t.clken (clken),
+\t\t\t\t.aclr (aclr),
+\t\t\t\t.clock (clock),
+\t\t\t\t.result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC ""32""
+// Retrieval info: PRIVATE: Function NUMERIC ""1""
+// Retrieval info: PRIVATE: WhichConstant NUMERIC ""0""
+// Retrieval info: PRIVATE: ConstantA NUMERIC ""0""
+// Retrieval info: PRIVATE: ConstantB NUMERIC ""0""
+// Retrieval info: PRIVATE: ValidCtA NUMERIC ""0""
+// Retrieval info: PRIVATE: ValidCtB NUMERIC ""0""
+// Retrieval info: PRIVATE: CarryIn NUMERIC ""0""
+// Retrieval info: PRIVATE: CarryOut NUMERIC ""0""
+// Retrieval info: PRIVATE: Overflow NUMERIC ""0""
+// Retrieval info: PRIVATE: Latency NUMERIC ""1""
+// Retrieval info: PRIVATE: aclr NUMERIC ""1""
+// Retrieval info: PRIVATE: clken NUMERIC ""1""
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC ""1""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""32""
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING ""SUB""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""LPM_ADD_SUB""
+// Retrieval info: CONSTANT: LPM_HINT STRING ""ONE_INPUT_IS_CONSTANT=NO""
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC ""1""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
+// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
+// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+"
+"
+
+module rx_dcoffset (input clock, input enable, input reset, 
+\t\t    input signed [15:0] adc_in, output signed [15:0] adc_out,
+\t\t    input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe);
+   parameter \t\t  MYADDR = 0;
+   
+   reg signed [31:0] \t\t integrator;
+   wire signed [15:0] \t\t scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);
+   assign \t\t\t adc_out = adc_in - scaled_integrator;
+
+   // FIXME do we need signed?
+   //FIXME  What do we do when clipping?
+   always @(posedge clock)
+     if(reset)
+       integrator <= #1 32'd0;
+     else if(serial_strobe & (MYADDR == serial_addr))
+       integrator <= #1 {serial_data[15:0],16'd0};
+     else if(enable)
+       integrator <= #1 integrator + adc_out;
+
+endmodule // rx_dcoffset
+"
+"
+
+module fifo_4k
+  (  input [15:0] data,
+     input \twrreq,
+     input \trdreq,
+     input \trdclk,
+     input \twrclk,
+     input \taclr,
+     output [15:0] q,
+     output \t rdfull,
+     output \t rdempty,
+     output [11:0] rdusedw,
+     output \t wrfull,
+     output \t wrempty,
+     output [11:0]  wrusedw
+     );
+
+fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_1k
+   
+"
+"fifo_4kx16_dc\tfifo_4kx16_dc_inst (\r
+\t.aclr ( aclr_sig ),\r
+\t.data ( data_sig ),\r
+\t.rdclk ( rdclk_sig ),\r
+\t.rdreq ( rdreq_sig ),\r
+\t.wrclk ( wrclk_sig ),\r
+\t.wrreq ( wrreq_sig ),\r
+\t.q ( q_sig ),\r
+\t.rdempty ( rdempty_sig ),\r
+\t.rdusedw ( rdusedw_sig ),\r
+\t.wrfull ( wrfull_sig ),\r
+\t.wrusedw ( wrusedw_sig )\r
+\t);\r
+"
+"// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: clk_doubler.v
+// Megafunction Name(s):
+// \t\t\taltpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.2 Build 156 11/29/2004 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+module clk_doubler (
+\tinclk0,
+\tc0);
+
+\tinput\t  inclk0;
+\toutput\t  c0;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING ""0""
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING ""deg""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING ""MHz""
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING ""MHz""
+// Retrieval info: PRIVATE: SPREAD_USE STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC ""1048575""
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING ""0""
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING ""50.00000000""
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING ""0.00000000""
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC ""2""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING ""0.500""
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING ""0""
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING ""0""
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING ""1""
+// Retrieval info: PRIVATE: BANDWIDTH STRING ""1.000""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING ""0""
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING ""8""
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING ""50.000""
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING ""1""
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC ""0""
+// Retrieval info: PRIVATE: USE_CLK0 STRING ""1""
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING ""0""
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING ""0""
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING ""0""
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING ""100.000""
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING ""c0""
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING ""MHz""
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING ""MHz""
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING ""0""
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING ""1""
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING ""e0""
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC ""1""
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING ""1""
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING ""0""
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC ""1""
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING ""1""
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING ""0""
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING ""512.000""
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING ""KHz""
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING ""0""
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING ""64.000""
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING ""0""
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING ""1""
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING ""100.000""
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING ""inclk0""
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING ""0""
+// Retrieval info: PRIVATE: DEV_FAMILY STRING ""Cyclone""
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC ""1""
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING ""Low""
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING ""0""
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING ""deg""
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING ""0""
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC ""11""
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC ""50""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""altpll""
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC ""2""
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC ""15625""
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC ""1""
+// Retrieval info: CONSTANT: PLL_TYPE STRING ""AUTO""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: OPERATION_MODE STRING ""NORMAL""
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING ""CLK0""
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING ""0""
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC ""c0""
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC ""@clk[5..0]""
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND ""inclk0""
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC ""@extclk[3..0]""
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
+"
+"module channel_ram 
+   ( // System
+     input txclk, input reset,
+     // USB side
+     input [31:0] datain, input WR, input WR_done, output have_space,
+     // Reader side 
+     output [31:0] dataout, input RD, input RD_done, output packet_waiting);
+\t
+   reg [6:0] wr_addr, rd_addr;
+   reg [1:0] which_ram_wr, which_ram_rd;
+   reg [2:0] nb_packets;
+\t
+   reg [31:0] ram0 [0:127];
+   reg [31:0] ram1 [0:127];
+   reg [31:0] ram2 [0:127];
+   reg [31:0] ram3 [0:127];
+\t
+   reg [31:0] dataout0;
+   reg [31:0] dataout1;
+   reg [31:0] dataout2;
+   reg [31:0] dataout3;
+\t
+   wire wr_done_int;
+   wire rd_done_int;
+   wire [6:0] rd_addr_final;
+   wire [1:0] which_ram_rd_final;
+\t
+   // USB side
+   always @(posedge txclk)
+       if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
+\t\t\t
+   always @(posedge txclk)
+       if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
+
+   always @(posedge txclk)
+       if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
+
+   always @(posedge txclk)
+       if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
+
+   assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
+   
+   always @(posedge txclk)
+       if(reset)
+           wr_addr <= 0;
+       else if (WR_done)
+           wr_addr <= 0;
+       else if (WR) 
+           wr_addr <= wr_addr + 7'd1;
+\t\t
+   always @(posedge txclk)
+      if(reset)
+          which_ram_wr <= 0;
+      else if (wr_done_int) 
+          which_ram_wr <= which_ram_wr + 2'd1;
+\t
+   assign have_space = (nb_packets < 3'd3);
+\t\t
+   // Reader side
+   // short hand fifo
+   // rd_addr_final is what rd_addr is going to be next clock cycle
+   // which_ram_rd_final is what which_ram_rd is going to be next clock cycle
+   always @(posedge txclk)  dataout0 <= ram0[rd_addr_final];
+   always @(posedge txclk)  dataout1 <= ram1[rd_addr_final];
+   always @(posedge txclk)  dataout2 <= ram2[rd_addr_final];
+   always @(posedge txclk)  dataout3 <= ram3[rd_addr_final];
+\t
+   assign dataout = (which_ram_rd_final[1]) ? 
+                    (which_ram_rd_final[0] ? dataout3 : dataout2) :
+                    (which_ram_rd_final[0] ? dataout1 : dataout0);
+
+   //RD_done is the only way to signal the end of one packet
+   assign rd_done_int = RD_done;   
+
+   always @(posedge txclk)
+       if (reset)
+           rd_addr <= 0;
+       else if (RD_done)
+           rd_addr <= 0;
+       else if (RD) 
+           rd_addr <= rd_addr + 7'd1;
+\t\t\t
+   assign rd_addr_final = (reset|RD_done) ? (6'd0) : 
+\t                  ((RD)?(rd_addr+7'd1):rd_addr); 
+\t
+   always @(posedge txclk)
+       if (reset)
+           which_ram_rd <= 0;
+       else if (rd_done_int)
+           which_ram_rd <= which_ram_rd + 2'd1;
+
+   assign which_ram_rd_final = (reset) ? (2'd0):
+\t                       ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
+\t                        
+   //packet_waiting is set to zero if rd_done_int is high
+   //because there is no guarantee that nb_packets will be pos.
+
+   assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
+   always @(posedge txclk)
+       if (reset)
+           nb_packets <= 0;
+       else if (wr_done_int & ~rd_done_int)
+           nb_packets <= nb_packets + 3'd1;
+       else if (rd_done_int & ~wr_done_int)
+           nb_packets <= nb_packets - 3'd1;
+\t\t\t
+endmodule
+"
+"// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_2k.v
+// Megafunction Name(s):
+// \t\t\tdcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation\'s design tools, logic functions 
+//and other software and tools, and its AMPP partner logic       
+//functions, and any output files any of the foregoing           
+//(including device programming or simulation files), and any    
+//associated documentation or information are expressly subject  
+//to the terms and conditions of the Altera Program License      
+//Subscription Agreement, Altera MegaCore Function License       
+//Agreement, or other applicable license agreement, including,   
+//without limitation, that your use is for the sole purpose of   
+//programming logic devices manufactured by Altera and sold by   
+//Altera or its authorized distributors.  Please refer to the    
+//applicable agreement for further details.
+
+module fifo_2k (
+\tdata,
+\twrreq,
+\trdreq,
+\trdclk,
+\twrclk,
+\taclr,
+\tq,
+\trdempty,
+\trdusedw,
+\twrfull,
+\twrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[15:0]  data;
+\tinput\t  wrreq;
+\tinput\t  rdreq;
+\tinput\t  rdclk;
+\tinput\t  wrclk;
+\tinput\t  aclr;
+\toutput\t[15:0]  q;
+\toutput\t  rdempty;
+\toutput\t[10:0]  rdusedw;
+\toutput\t  wrfull;
+\toutput\t[10:0]  wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC ""16""
+// Retrieval info: PRIVATE: Depth NUMERIC ""2048""
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""
+// Retrieval info: PRIVATE: Full NUMERIC ""1""
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""2048""
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""11""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE
+"
+"
+
+module mac (input clock, input reset, input enable, input clear,
+\t    input signed [15:0] x, input signed [15:0] y,
+\t    input [7:0] shift, output [15:0] z );
+
+   reg signed [30:0] product;
+   reg signed [39:0] z_int;
+   reg signed [15:0] z_shift;
+
+   reg enable_d1;
+   always @(posedge clock)
+     enable_d1 <= #1 enable;
+   
+   always @(posedge clock)
+     if(reset | clear)
+       z_int <= #1 40'd0;
+     else if(enable_d1)
+       z_int <= #1 z_int + {{9{product[30]}},product};
+
+   always @(posedge clock)
+     product <= #1 x*y;
+
+   always @*   // FIXME full case? parallel case?
+     case(shift)
+       //8'd0 : z_shift <= z_int[39:24];
+       //8'd1 : z_shift <= z_int[38:23];
+       //8'd2 : z_shift <= z_int[37:22];
+       //8'd3 : z_shift <= z_int[36:21];
+       //8'd4 : z_shift <= z_int[35:20];
+       //8'd5 : z_shift <= z_int[34:19];
+       8'd6 : z_shift <= z_int[33:18];
+       8'd7 : z_shift <= z_int[32:17];
+       8'd8 : z_shift <= z_int[31:16];
+       8'd9 : z_shift <= z_int[30:15];
+       8'd10 : z_shift <= z_int[29:14];
+       8'd11 : z_shift <= z_int[28:13];
+       //8'd12 : z_shift <= z_int[27:12];
+       //8'd13 : z_shift <= z_int[26:11];
+       //8'd14 : z_shift <= z_int[25:10];
+       //8'd15 : z_shift <= z_int[24:9];
+       //8'd16 : z_shift <= z_int[23:8];
+       //8'd17 : z_shift <= z_int[22:7];
+       //8'd18 : z_shift <= z_int[21:6];
+       //8'd19 : z_shift <= z_int[20:5];
+       //8'd20 : z_shift <= z_int[19:4];
+       //8'd21 : z_shift <= z_int[18:3];
+       //8'd22 : z_shift <= z_int[17:2];
+       //8'd23 : z_shift <= z_int[16:1];
+       //8'd24 : z_shift <= z_int[15:0];
+       default : z_shift <= z_int[15:0];
+     endcase // case(shift)
+   
+   // FIXME do we need to saturate?
+   //assign z = z_shift;
+   assign z = z_int[15:0];
+   
+endmodule // mac
+"
+"// -*- verilog -*-
+// Range Networks \r
+// Unsigned 16-bit greater or equal comparator.\r
+// for test module\r
+\r
+module testcompar\r
+   (\r
+     input usbdata_packed[31:0],\r
+\t  output reg test_bit1\r
+\t);\r
+\tusbdata_packed[15:0] A;
+\tusbdata_packed[31:16] B;
+\tassign test_bit1 = A == B ? 1'b1 : 1'b0;
+\tendmodule "
+"// megafunction wizard: %FIFO%VBB%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: dcfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_4kx16_dc.v\r
+// Megafunction Name(s):\r
+// \t\t\tdcfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+module fifo_4kx16_dc (\r
+\taclr,\r
+\tdata,\r
+\trdclk,\r
+\trdreq,\r
+\twrclk,\r
+\twrreq,\r
+\tq,\r
+\trdempty,\r
+\trdusedw,\r
+\twrfull,\r
+\twrusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t[15:0]  data;\r
+\tinput\t  rdclk;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrclk;\r
+\tinput\t  wrreq;\r
+\toutput\t[15:0]  q;\r
+\toutput\t  rdempty;\r
+\toutput\t[11:0]  rdusedw;\r
+\toutput\t  wrfull;\r
+\toutput\t[11:0]  wrusedw;\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""4096""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""16""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""4096""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""12""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk\r
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]\r
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk\r
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0\r
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0\r
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0\r
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0\r
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0\r
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE\r
+"
+"
+// Model of Pipelined [ZBT] Synchronous SRAM
+
+module ssram(clock,addr,data,wen,ce);
+   parameter addrbits = 19;
+   parameter depth = 524288;
+
+   input clock;
+   input [addrbits-1:0] addr;
+   inout [35:0] data;
+   input wen;
+   input ce;
+
+   reg [35:0] ram [0:depth-1];
+   
+   reg read_d1,read_d2;
+   reg write_d1,write_d2;
+   reg [addrbits-1:0] addr_d1,addr_d2;
+   
+   always @(posedge clock)
+     begin
+\tread_d1 <= #1 ce & ~wen;
+\twrite_d1 <= #1 ce & wen;
+\taddr_d1 <= #1 addr;
+\tread_d2 <= #1 read_d1;
+\twrite_d2 <= #1 write_d1;
+\taddr_d2 <= #1 addr_d1;
+\tif(write_d2)
+\t  ram[addr_d2] = data;
+     end // always @ (posedge clock)
+
+   data = (ce & read_d2) ? ram[addr_d2] : 36\'bz;
+
+   always @(posedge clock)
+     if(~ce & (write_d2 | write_d1 | wen))
+       $display(""$time ERROR:  RAM CE not asserted during write cycle"");
+   
+endmodule // ssram
+"
+"
+
+module tx_buffer_inband 
+  ( //System
+    input wire usbclk, input wire bus_reset, input wire reset, 
+    input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels, 
+    //output transmit signals
+    output wire [15:0] tx_i_0, output wire [15:0] tx_q_0, 
+    output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
+    output wire [15:0] tx_i_2, output wire [15:0] tx_q_2, 
+    output wire [15:0] tx_i_3, output wire [15:0] tx_q_3, 
+    input wire txclk, input wire txstrobe, input wire WR,
+    input wire clear_status, output wire tx_empty, output wire [15:0] debugbus, 
+    //command reader io
+    output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done, 
+    input wire rx_WR_enabled,
+    //register io 
+    output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
+    input wire [31:0] reg_data_out,  
+    //input characteristic signals
+    input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2, 
+    input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold, 
+    output wire [1:0] tx_underrun, 
+    //system stop
+    output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1);
+\t
+
+   /* Debug paramters */
+   parameter STROBE_RATE_0 =   8'd1 ;
+   parameter STROBE_RATE_1 =   8'd2 ;
+   parameter NUM_CHAN\t =      2 ;
+    
+\t
+   /* To generate channel readers */
+   genvar i ;
+    
+   /* These will eventually be external register */
+   reg                  [31:0] adc_time ;
+   wire \t\t\t       datapattern_err;
+   
+   wire                 [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
+   wire\t\t\t        [31:0] rssi [3:0];
+   assign rssi[0] = rssi_0;
+   assign rssi[1] = rssi_1;
+   assign rssi[2] = rssi_2;
+   assign rssi[3] = rssi_3;
+   
+   always @(posedge txclk)
+       if (reset)
+           adc_time <= 0;
+       else if (txstrobe)
+           adc_time <= adc_time + 1;
+
+
+    /* Connections between tx_usb_fifo_reader and
+       cnannel/command processing blocks */
+   wire                  [31:0] tx_data_bus ;
+   wire            [NUM_CHAN:0] chan_WR ;
+   wire            [NUM_CHAN:0] chan_done ;
+    
+    /* Connections between data block and the
+       FX2/TX chains */
+   wire            [NUM_CHAN:0] chan_underrun;
+   wire            [NUM_CHAN:0] chan_txempty;
+   
+   /* Conections between tx_data_packet_fifo and
+       its reader + strobe generator */
+   wire                 [31:0] chan_fifodata [NUM_CHAN:0] ;
+   wire                        chan_pkt_waiting [NUM_CHAN:0] ;
+   wire                        chan_rdreq [NUM_CHAN:0] ;
+   wire                        chan_skip [NUM_CHAN:0] ;
+   wire                        chan_have_space [NUM_CHAN:0] ;
+   wire                        chan_txstrobe [NUM_CHAN-1:0] ;
+
+   wire\t\t        [14:0] debug [NUM_CHAN:0];
+    
+   /* Outputs to transmit chains */
+   wire                 [15:0] tx_i [NUM_CHAN-1:0] ;
+   wire                 [15:0] tx_q [NUM_CHAN-1:0] ;
+   
+    
+   /* TODO: Figure out how to write this genericly */
+   assign have_space = chan_have_space[0];// & chan_have_space[1];
+   assign tx_empty = chan_txempty[0];// & chan_txempty[1] ;
+   assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
+   assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
+   assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
+   assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
+
+   assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty;
+   assign test_bit0 = datapattern_err;
+   
+   /* Debug statement */
+   assign txstrobe_rate[0] = STROBE_RATE_0 ;
+   assign txstrobe_rate[1] = STROBE_RATE_1 ;
+   assign tx_q_2 = 16'b0 ;
+   assign tx_i_2 = 16'b0 ;
+   assign tx_q_3 = 16'b0 ;
+   assign tx_i_3 = 16'b0 ;
+   assign tx_i_3 = 16'b0 ;
+\t
+
+   wire [31:0] usbdata_final;
+   wire\t\tWR_final;
+   assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done, 
+                      chan_pkt_waiting[0], chan_pkt_waiting[1],
+                      chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
+
+   tx_packer tx_usb_packer
+   (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
+    .usbdata(usbdata), .reset(reset), .txclk(txclk),
+    .usbdata_final(usbdata_final), .WR_final(WR_final),
+    .test_bit0(), .test_bit1(test_bit1));
+\t
+   channel_demux channel_demuxer
+   (.usbdata_final(usbdata_final), .WR_final(WR_final),
+    .reset(reset), .txclk(txclk), .WR_channel(chan_WR),
+    .WR_done_channel(chan_done), .ram_data(tx_data_bus));
+\t
+   generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+     begin : generate_channel_readers
+       assign tx_underrun[i] = chan_underrun[i];
+
+       channel_ram tx_data_packet_fifo 
+       (.reset(reset), .txclk(txclk), .datain(tx_data_bus),
+        .WR(chan_WR[i]), .WR_done(chan_done[i]),
+        .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
+        .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
+        .RD_done(chan_skip[i]));
+
+       chan_fifo_reader tx_chan_reader 
+       (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
+        .adc_time(adc_time), .samples_format(4'b0),          
+        .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
+        .skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
+        .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
+        .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
+        .threshhold(threshhold), .rssi_wait(rssi_wait));\t         
+    end
+    endgenerate
+
+
+   channel_ram tx_cmd_packet_fifo 
+   (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
+    .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
+    .dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
+    .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
+
+   cmd_reader tx_cmd_reader
+   (.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]),
+    .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
+    .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
+    .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
+    .reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
+    .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
+\t\t\t\t   
+endmodule // tx_buffer
+
+"
+"// Model of FIFO in Altera
+
+module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+\t\t    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+   parameter width = 32;
+   parameter depth = 4096;
+   //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
+      
+   input [31:0] data;
+   input \twrreq;
+   input \trdreq;
+   input \trdclk;
+   input \twrclk;
+   input \taclr;
+   output [31:0] q;
+   output \t rdfull;
+   output \t rdempty;
+   output [7:0]  rdusedw;
+   output \t wrfull;
+   output \t wrempty;
+   output [7:0]  wrusedw;
+   
+   reg [width-1:0] mem [0:depth-1];
+   reg [7:0] \t   rdptr;
+   reg [7:0] \t   wrptr;
+   
+`ifdef rd_req
+   reg [width-1:0] q;
+`else
+   wire [width-1:0] q;
+`endif
+   
+   reg [7:0] \t    rdusedw;
+   reg [7:0] \t    wrusedw;
+   
+   integer \t    i;
+
+   always @( aclr)
+     begin
+\twrptr <= #1 0;
+\trdptr <= #1 0;
+\tfor(i=0;i<depth;i=i+1)
+\t  mem[i] <= #1 0;
+     end
+   
+   always @(posedge wrclk)
+     if(wrreq)
+       begin
+\t  wrptr <= #1 wrptr+1;
+\t  mem[wrptr] <= #1 data;
+       end
+   
+   always @(posedge rdclk)
+     if(rdreq)
+       begin
+   \t  rdptr <= #1 rdptr+1;
+`ifdef rd_req
+\t  q <= #1 mem[rdptr];
+`endif
+       end
+   
+`ifdef rd_req
+`else
+   assign q = mem[rdptr];
+`endif
+   
+   // Fix these
+   always @(posedge wrclk)
+     wrusedw <= #1 wrptr - rdptr;
+   
+   always @(posedge rdclk)
+     rdusedw <= #1 wrptr - rdptr;
+   
+   
+endmodule // fifo_1c_4k
+"
+"
+
+module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
+\t     input enable_in, output reg enable_out );
+
+   always @(posedge clock)
+     if(enable_in)
+       product <= #1 x*y;
+     else
+       product <= #1 31'd0;
+   
+   always @(posedge clock)
+     enable_out <= #1 enable_in;
+   
+endmodule // mult
+
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003,2005 Matt Ettus
+//  Copyright (C) 2007 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clock, enable, and reset controls for whole system
+
+module master_control
+  ( input master_clk, input usbclk,
+    input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
+    output tx_bus_reset, output rx_bus_reset,
+    output wire tx_dsp_reset, output wire rx_dsp_reset,
+    output wire enable_tx, output wire enable_rx,
+    output wire [7:0] interp_rate, output wire [7:0] decim_rate,
+    output tx_sample_strobe, output strobe_interp,
+    output rx_sample_strobe, output strobe_decim,
+    input tx_empty,
+    input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
+    output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3,
+    //the following output is for register reads only
+    output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output wire [7:0] master_controls,
+    output wire [3:0] debug_en, 
+    output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire [15:0] atr_rxval_0,
+    output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire [15:0] atr_rxval_1,
+    output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire [15:0] atr_rxval_2,
+    output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire [15:0] atr_rxval_3,
+    output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire [7:0] rxa_refclk, output wire [7:0] rxb_refclk
+    );
+   
+   // FIXME need a separate reset for all control settings 
+   // Master Controls assignments
+   //wire [7:0] master_controls;
+   setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
+   assign     enable_tx = master_controls[0];
+   assign     enable_rx = master_controls[1];
+   assign     tx_dsp_reset = master_controls[2];
+   assign     rx_dsp_reset = master_controls[3];
+   // Unused - 4-7
+
+   // Strobe Generators
+   setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate));
+   setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate));
+   
+   strobe_gen da_strobe_gen
+     ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
+       .rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) );
+
+   strobe_gen tx_strobe_gen
+     ( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
+       .rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) );
+
+   assign  rx_sample_strobe = 1'b1;
+   
+   strobe_gen decim_strobe_gen
+     ( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx),
+       .rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) );
+   
+   // Reset syncs for bus (usbclk) side
+   // The RX bus side reset isn't used, the TX bus side one may not be needed
+   reg \t  tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2;
+ \t   
+   always @(posedge usbclk)
+     begin
+   \ttx_reset_bus_sync1 <= #1 tx_dsp_reset;
+   \trx_reset_bus_sync1 <= #1 rx_dsp_reset;
+   \ttx_reset_bus_sync2 <= #1 tx_reset_bus_sync1;
+   \trx_reset_bus_sync2 <= #1 rx_reset_bus_sync1;
+     end
+
+   assign tx_bus_reset = tx_reset_bus_sync2;
+   assign rx_bus_reset = rx_reset_bus_sync2;
+
+   //wire [7:0]   txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
+   wire        txaclk,txbclk,rxaclk,rxbclk;
+   //wire [3:0] debug_en;
+   wire [3:0]  txcvr_ctrl;
+
+   wire [31:0] txcvr_rxlines, txcvr_txlines;
+      
+   setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk));
+   setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk));
+   setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk));
+   setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk));
+
+   setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en));
+         
+   clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0]));
+   clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0]));
+   clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0]));
+   clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0]));
+   
+   reg [15:0]  io_0_reg,io_1_reg,io_2_reg,io_3_reg;
+   // Upper 16 bits are mask for lower 16
+   always @(posedge master_clk)
+     if(serial_strobe)
+       case(serial_addr)
+\t `FR_IO_0 : io_0_reg
+\t   <= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+\t `FR_IO_1 : io_1_reg
+\t   <= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+\t `FR_IO_2 : io_2_reg
+\t   <= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+\t `FR_IO_3 : io_3_reg
+\t   <= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+       endcase // case(serial_addr)
+
+   wire        transmit_now;
+   wire        atr_ctl;
+   //wire [11:0] atr_tx_delay, atr_rx_delay;
+   //wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3;
+      
+   setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
+   setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
+   setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0));
+
+   setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1));
+   setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1));
+   setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1));
+
+   setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2));
+   setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2));
+   setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2));
+
+   setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3));
+   setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3));
+   setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
+
+   //setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
+   setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay));
+   setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay));
+
+   assign      atr_ctl = 1'b1;
+
+   atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty),
+\t\t       .tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now));
+   
+   wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
+   wire [15:0] io_0 = ({{16{atr_ctl}}} &  atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
+   
+   wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1;
+   wire [15:0] io_1 = ({{16{atr_ctl}}} &  atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg);
+   
+   wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2;
+   wire [15:0] io_2 = ({{16{atr_ctl}}} &  atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg);
+   
+   wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3;
+   wire [15:0] io_3 = ({{16{atr_ctl}}} &  atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg);
+   
+   assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0;
+   assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1;
+   assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2;
+   assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3;
+
+   
+endmodule // master_control
+"
+"// megafunction wizard: %LPM_BUSTRI%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_bustri 
+
+// ============================================================
+// File Name: bustri.v
+// Megafunction Name(s):
+// \t\t\tlpm_bustri
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+module bustri (
+\tdata,
+\tenabledt,
+\ttridata);
+
+\tinput\t[15:0]  data;
+\tinput\t  enabledt;
+\tinout\t[15:0]  tridata;
+
+
+\tlpm_bustri\tlpm_bustri_component (
+\t\t\t\t.tridata (tridata),
+\t\t\t\t.enabledt (enabledt),
+\t\t\t\t.data (data));
+\tdefparam
+\t\tlpm_bustri_component.lpm_width = 16,
+\t\tlpm_bustri_component.lpm_type = ""LPM_BUSTRI"";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC ""16""
+// Retrieval info: PRIVATE: BiDir NUMERIC ""0""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""LPM_BUSTRI""
+// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+"
+"
+
+module ram16_2port (input clock, input write, 
+\t\t    input [3:0] wr_addr, input [15:0] wr_data,
+\t\t    input [3:0] rd_addr1, output reg [15:0] rd_data1,
+\t\t    input [3:0] rd_addr2, output reg [15:0] rd_data2);
+   
+   reg [15:0] \t\t\tram_array [0:31];
+   
+   always @(posedge clock)
+     rd_data1 <= #1 ram_array[rd_addr1];
+   
+   always @(posedge clock)
+     rd_data2 <= #1 ram_array[rd_addr2];
+   
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+   
+endmodule // ram16_2port
+
+
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+
+module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
+   parameter depth = 4;
+   parameter width = 16;
+   parameter size = 16;
+   
+   input wclk;
+   input [width-1:0] wdata;
+   input [depth-1:0] waddr;
+   input \t     wen;
+
+   input rclk;
+   output reg [width-1:0] rdata;
+   input [depth-1:0]  raddr;
+   
+   reg [width-1:0]    ram [0:size-1];
+   
+   always @(posedge wclk)
+     if(wen)
+       ram[waddr] <= #1 wdata;
+   
+   always @(posedge rclk)
+     rdata <= #1 ram[raddr];
+   
+endmodule // dpram
+"
+"// megafunction wizard: %FIFO%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: scfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_1kx16.v\r
+// Megafunction Name(s):\r
+// \t\t\tscfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module fifo_1kx16 (\r
+\taclr,\r
+\tclock,\r
+\tdata,\r
+\trdreq,\r
+\twrreq,\r
+\talmost_empty,\r
+\tempty,\r
+\tfull,\r
+\tq,\r
+\tusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t  clock;\r
+\tinput\t[15:0]  data;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrreq;\r
+\toutput\t  almost_empty;\r
+\toutput\t  empty;\r
+\toutput\t  full;\r
+\toutput\t[15:0]  q;\r
+\toutput\t[9:0]  usedw;\r
+\r
+\twire [9:0] sub_wire0;\r
+\twire  sub_wire1;\r
+\twire  sub_wire2;\r
+\twire [15:0] sub_wire3;\r
+\twire  sub_wire4;\r
+\twire [9:0] usedw = sub_wire0[9:0];\r
+\twire  empty = sub_wire1;\r
+\twire  almost_empty = sub_wire2;\r
+\twire [15:0] q = sub_wire3[15:0];\r
+\twire  full = sub_wire4;\r
+\r
+\tscfifo\tscfifo_component (\r
+\t\t\t\t.rdreq (rdreq),\r
+\t\t\t\t.aclr (aclr),\r
+\t\t\t\t.clock (clock),\r
+\t\t\t\t.wrreq (wrreq),\r
+\t\t\t\t.data (data),\r
+\t\t\t\t.usedw (sub_wire0),\r
+\t\t\t\t.empty (sub_wire1),\r
+\t\t\t\t.almost_empty (sub_wire2),\r
+\t\t\t\t.q (sub_wire3),\r
+\t\t\t\t.full (sub_wire4)\r
+\t\t\t\t// synopsys translate_off\r
+\t\t\t\t,\r
+\t\t\t\t.sclr (),\r
+\t\t\t\t.almost_full ()\r
+\t\t\t\t// synopsys translate_on\r
+\t\t\t\t);\r
+\tdefparam\r
+\t\tscfifo_component.add_ram_output_register = ""OFF"",\r
+\t\tscfifo_component.almost_empty_value = 504,\r
+\t\tscfifo_component.intended_device_family = ""Cyclone"",\r
+\t\tscfifo_component.lpm_hint = ""RAM_BLOCK_TYPE=M4K"",\r
+\t\tscfifo_component.lpm_numwords = 1024,\r
+\t\tscfifo_component.lpm_showahead = ""OFF"",\r
+\t\tscfifo_component.lpm_type = ""scfifo"",\r
+\t\tscfifo_component.lpm_width = 16,\r
+\t\tscfifo_component.lpm_widthu = 10,\r
+\t\tscfifo_component.overflow_checking = ""ON"",\r
+\t\tscfifo_component.underflow_checking = ""ON"",\r
+\t\tscfifo_component.use_eab = ""ON"";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""504""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""1024""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""1""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""2""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""0""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""16""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""0""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC ""504""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_HINT STRING ""RAM_BLOCK_TYPE=M4K""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""1024""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""OFF""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""scfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""10""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""ON""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""ON""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr\r
+// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty\r
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0\r
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0\r
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0\r
+// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE\r
+"
+"// megafunction wizard: %FIFO%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: scfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_1kx16.v\r
+// Megafunction Name(s):\r
+// \t\t\tscfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module fifo_1kx16 (\r
+\taclr,\r
+\tclock,\r
+\tdata,\r
+\trdreq,\r
+\twrreq,\r
+\talmost_empty,\r
+\tempty,\r
+\tfull,\r
+\tq,\r
+\tusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t  clock;\r
+\tinput\t[15:0]  data;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrreq;\r
+\toutput\t  almost_empty;\r
+\toutput\t  empty;\r
+\toutput\t  full;\r
+\toutput\t[15:0]  q;\r
+\toutput\t[9:0]  usedw;\r
+\r
+\twire [9:0] sub_wire0;\r
+\twire  sub_wire1;\r
+\twire  sub_wire2;\r
+\twire [15:0] sub_wire3;\r
+\twire  sub_wire4;\r
+\twire [9:0] usedw = sub_wire0[9:0];\r
+\twire  empty = sub_wire1;\r
+\twire  almost_empty = sub_wire2;\r
+\twire [15:0] q = sub_wire3[15:0];\r
+\twire  full = sub_wire4;\r
+\r
+\tscfifo\tscfifo_component (\r
+\t\t\t\t.rdreq (rdreq),\r
+\t\t\t\t.aclr (aclr),\r
+\t\t\t\t.clock (clock),\r
+\t\t\t\t.wrreq (wrreq),\r
+\t\t\t\t.data (data),\r
+\t\t\t\t.usedw (sub_wire0),\r
+\t\t\t\t.empty (sub_wire1),\r
+\t\t\t\t.almost_empty (sub_wire2),\r
+\t\t\t\t.q (sub_wire3),\r
+\t\t\t\t.full (sub_wire4)\r
+\t\t\t\t// synopsys translate_off\r
+\t\t\t\t,\r
+\t\t\t\t.sclr (),\r
+\t\t\t\t.almost_full ()\r
+\t\t\t\t// synopsys translate_on\r
+\t\t\t\t);\r
+\tdefparam\r
+\t\tscfifo_component.add_ram_output_register = ""OFF"",\r
+\t\tscfifo_component.almost_empty_value = 504,\r
+\t\tscfifo_component.intended_device_family = ""Cyclone"",\r
+\t\tscfifo_component.lpm_hint = ""RAM_BLOCK_TYPE=M4K"",\r
+\t\tscfifo_component.lpm_numwords = 1024,\r
+\t\tscfifo_component.lpm_showahead = ""OFF"",\r
+\t\tscfifo_component.lpm_type = ""scfifo"",\r
+\t\tscfifo_component.lpm_width = 16,\r
+\t\tscfifo_component.lpm_widthu = 10,\r
+\t\tscfifo_component.overflow_checking = ""ON"",\r
+\t\tscfifo_component.underflow_checking = ""ON"",\r
+\t\tscfifo_component.use_eab = ""ON"";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""504""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""1024""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""1""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""2""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""0""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""16""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""0""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC ""504""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_HINT STRING ""RAM_BLOCK_TYPE=M4K""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""1024""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""OFF""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""scfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""10""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""ON""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""ON""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr\r
+// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty\r
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0\r
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0\r
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0\r
+// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE\r
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
+   parameter bitwidth = 16;
+   parameter zwidth = 16;
+   parameter shift = 1;
+   
+   input     clock;
+   input     reset;
+   input     enable;
+   input [bitwidth-1:0] xi,yi;
+   input [zwidth-1:0] zi;
+   input [zwidth-1:0] constant;
+   output [bitwidth-1:0] xo,yo;
+   output [zwidth-1:0] zo;
+   
+   wire z_is_pos = ~zi[zwidth-1];
+
+   reg [bitwidth-1:0] \t xo,yo;
+   reg [zwidth-1:0] zo;
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+\t  xo <= #1 0;
+\t  yo <= #1 0;
+\t  zo <= #1 0;
+       end
+     else if(enable)
+       begin
+\t  xo <= #1 z_is_pos ?   
+\t\txi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
+\t\txi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
+\t  yo <= #1 z_is_pos ?   
+\t\tyi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
+\t\tyi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
+\t  zo <= #1 z_is_pos ?   
+\t\tzi - constant :
+\t\tzi + constant;
+       end
+endmodule
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+// NOTE   This only works for N=4, max decim rate of 128
+// NOTE   signal ""rate"" is ONE LESS THAN the actual rate
+
+module cic_dec_shifter(rate,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 28;
+   
+   input [7:0] rate;
+   input       wire [bw+maxbitgain-1:0] signal_in;
+   output      reg [bw-1:0] signal_out;
+
+   function [4:0] bitgain;
+      input [7:0] rate;
+      case(rate)
+\t// Exact Cases -- N*log2(rate)
+\t8\'d4 : bitgain = 8;
+\t8\'d8 : bitgain = 12;
+\t8\'d16 : bitgain = 16;
+\t8\'d32 : bitgain = 20;
+\t8\'d64 : bitgain = 24;
+\t8\'d128 : bitgain = 28;
+\t
+\t// Nearest without overflow -- ceil(N*log2(rate))
+\t8\'d5 : bitgain = 10;
+\t8\'d6 : bitgain = 11;
+\t8\'d7 : bitgain = 12;
+\t8\'d9 : bitgain = 13;
+\t8\'d10,8\'d11 : bitgain = 14;
+\t8\'d12,8\'d13 : bitgain = 15;
+\t8\'d14,8\'d15 : bitgain = 16;
+\t8\'d17,8\'d18,8\'d19 : bitgain = 17;
+\t8\'d20,8\'d21,8\'d22 : bitgain = 18;
+\t8\'d23,8\'d24,8\'d25,8\'d26 : bitgain = 19;
+\t8\'d27,8\'d28,8\'d29,8\'d30,8\'d31 : bitgain = 20;
+\t8\'d33,8\'d34,8\'d35,8\'d36,8\'d37,8\'d38 : bitgain = 21;
+\t8\'d39,8\'d40,8\'d41,8\'d42,8\'d43,8\'d44,8\'d45 : bitgain = 22;
+\t8\'d46,8\'d47,8\'d48,8\'d49,8\'d50,8\'d51,8\'d52,8\'d53 : bitgain = 23;
+\t8\'d54,8\'d55,8\'d56,8\'d57,8\'d58,8\'d59,8\'d60,8\'d61,8\'d62,8\'d63 : bitgain = 24;
+\t8\'d65,8\'d66,8\'d67,8\'d68,8\'d69,8\'d70,8\'d71,8\'d72,8\'d73,8\'d74,8\'d75,8\'d76 : bitgain = 25;
+\t8\'d77,8\'d78,8\'d79,8\'d80,8\'d81,8\'d82,8\'d83,8\'d84,8\'d85,8\'d86,8\'d87,8\'d88,8\'d89,8\'d90 : bitgain = 26;
+\t8\'d91,8\'d92,8\'d93,8\'d94,8\'d95,8\'d96,8\'d97,8\'d98,8\'d99,8\'d100,8\'d101,8\'d102,8\'d103,8\'d104,8\'d105,8\'d106,8\'d107 : bitgain = 27;
+\tdefault : bitgain = 28;
+      endcase // case(rate)
+   endfunction // bitgain
+   
+   wire [4:0] \t  shift = bitgain(rate+1);
+   
+   // We should be able to do this, but can\'t ....
+   // assign \t  signal_out = signal_in[shift+bw-1:shift];
+   
+   always @*
+     case(shift)
+       5\'d8  : signal_out = signal_in[8+bw-1:8];
+       5\'d10 : signal_out = signal_in[10+bw-1:10];
+       5\'d11 : signal_out = signal_in[11+bw-1:11];
+       5\'d12 : signal_out = signal_in[12+bw-1:12];
+       5\'d13 : signal_out = signal_in[13+bw-1:13];
+       5\'d14 : signal_out = signal_in[14+bw-1:14];
+       5\'d15 : signal_out = signal_in[15+bw-1:15];
+       5\'d16 : signal_out = signal_in[16+bw-1:16];
+       5\'d17 : signal_out = signal_in[17+bw-1:17];
+       5\'d18 : signal_out = signal_in[18+bw-1:18];
+       5\'d19 : signal_out = signal_in[19+bw-1:19];
+       5\'d20 : signal_out = signal_in[20+bw-1:20];
+       5\'d21 : signal_out = signal_in[21+bw-1:21];
+       5\'d22 : signal_out = signal_in[22+bw-1:22];
+       5\'d23 : signal_out = signal_in[23+bw-1:23];
+       5\'d24 : signal_out = signal_in[24+bw-1:24];
+       5\'d25 : signal_out = signal_in[25+bw-1:25];
+       5\'d26 : signal_out = signal_in[26+bw-1:26];
+       5\'d27 : signal_out = signal_in[27+bw-1:27];
+       5\'d28 : signal_out = signal_in[28+bw-1:28];
+       
+       default : signal_out = signal_in[28+bw-1:28];
+     endcase // case(shift)
+
+endmodule // cic_dec_shifter
+
+"
+"
+
+module ram32_2sum (input clock, input write, 
+\t\t   input [4:0] wr_addr, input [15:0] wr_data,
+\t\t   input [4:0] rd_addr1, input [4:0] rd_addr2,
+\t\t   output reg [15:0] sum);
+   
+   reg [15:0] \t\t\tram_array [0:31];
+   wire [16:0] \t\t\tsum_int;
+   
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+
+   assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
+
+   always @(posedge clock)
+     sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
+
+   
+endmodule // ram32_2sum
+
+"
+"
+
+module setting_reg_masked
+  ( input clock, input reset, input strobe, input wire [6:0] addr,
+    input wire [31:0] in, output reg [31:0] out, output reg changed);
+/* upper 16 bits are mask, lower 16 bits are value 
+ * Note that you get a 16 bit register, not a 32 bit one */
+
+   parameter my_addr = 0;
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+\t  out <= #1 32'd0;
+\t  changed <= #1 1'b0;
+       end
+     else
+       if(strobe & (my_addr==addr))
+\t begin
+\t    out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );
+\t    changed <= #1 1'b1;
+\t end
+       else
+\t changed <= #1 1'b0;
+   
+endmodule // setting_reg_masked
+"
+"module data_packet_fifo 
+  ( input       reset,
+    input       clock,
+    input       [31:0]ram_data_in,
+    input       write_enable,
+    output  reg have_space,
+    output  reg [31:0]ram_data_out,
+    output  reg pkt_waiting,
+\toutput\treg\tisfull,
+\toutput\treg [1:0]usb_ram_packet_out,
+\toutput\treg [1:0]usb_ram_packet_in,
+    input       read_enable,
+    input       pkt_complete,
+    input       skip_packet) ;
+
+    /* Some parameters for usage later on */
+    parameter DATA_WIDTH = 32 ;
+    parameter PKT_DEPTH = 128 ;
+    parameter NUM_PACKETS = 4 ;
+
+    /* Create the RAM here */
+    reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ;
+
+    /* Create the address signals */
+    reg [6:0] usb_ram_offset_out ;
+    //reg [1:0] usb_ram_packet_out ;
+    reg [6:0] usb_ram_offset_in ;
+    //reg [1:0] usb_ram_packet_in ;
+
+    wire [6-2+NUM_PACKETS:0] usb_ram_aout ;
+    wire [6-2+NUM_PACKETS:0] usb_ram_ain ;
+    //reg isfull;
+
+    assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
+    assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
+    
+    // Check if there is one full packet to process
+    always @(usb_ram_ain, usb_ram_aout, isfull)
+    begin
+        if (usb_ram_ain == usb_ram_aout)
+            pkt_waiting <= isfull ;
+        else if (usb_ram_ain > usb_ram_aout)
+            pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= PKT_DEPTH;
+        else
+            pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >= PKT_DEPTH;
+    end
+ 
+    // Check if there is room
+    always @(usb_ram_ain, usb_ram_aout, isfull)
+    begin
+        if (usb_ram_ain == usb_ram_aout)
+            have_space <= ~isfull;   
+        else if (usb_ram_ain > usb_ram_aout)
+            have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH * (NUM_PACKETS - 1))? 1'b1 : 1'b0;
+        else
+            have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
+    end
+
+
+
+    /* RAM Writing/Reading process */
+    always @(posedge clock)
+    begin
+        if( write_enable ) 
+          begin
+            usb_ram[usb_ram_ain] <= ram_data_in ;
+          end
+\t\tram_data_out <= usb_ram[usb_ram_aout] ;
+    end
+
+    /* RAM Write/Read Address process */
+    always @(posedge clock)
+    begin
+        if( reset ) 
+          begin
+            usb_ram_packet_out <= 0 ;
+            usb_ram_offset_out <= 0 ;
+\t\t\tusb_ram_offset_in <= 0 ;
+            usb_ram_packet_in <= 0 ;
+            isfull <= 0;
+          end
+        else
+\t\t  begin
+            if( skip_packet )
+              begin
+                usb_ram_packet_out <= usb_ram_packet_out + 1 ;
+                usb_ram_offset_out <= 0 ;
+                isfull <= 0;
+              end
+            else if(read_enable) 
+\t\t\t  begin
+                if( usb_ram_offset_out == 7'b1111111 )
+                  begin
+                    isfull <= 0 ;
+                    usb_ram_offset_out <= 0 ;
+                    usb_ram_packet_out <= usb_ram_packet_out + 1 ;
+                  end
+                else
+                    usb_ram_offset_out <= usb_ram_offset_out + 1 ;  
+              end
+\t\t\tif( pkt_complete )
+              begin
+                usb_ram_packet_in <= usb_ram_packet_in + 1 ;
+                usb_ram_offset_in <= 0 ;
+                if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
+                    isfull <= 1 ;
+              end
+            else if( write_enable ) 
+              begin
+                if (usb_ram_offset_in == 7'b1111111)
+                    usb_ram_offset_in <= 7'b1111111 ;    
+                else
+                    usb_ram_offset_in <= usb_ram_offset_in + 1 ;
+              end
+\t\t  end
+    end
+
+endmodule
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+// Sign extension ""macro""
+// bits_out should be greater than bits_in
+
+module sign_extend (in,out);
+\tparameter bits_in=0;  // FIXME Quartus insists on a default
+\tparameter bits_out=0;
+\t
+\tinput [bits_in-1:0] in;
+\toutput [bits_out-1:0] out;
+\t
+\tassign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
+\t
+endmodule
+"
+"// Model of FIFO in Altera
+
+module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+\t\t    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+   parameter width = 32;
+   parameter depth = 2048;
+   //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
+      
+   input [31:0] data;
+   input \twrreq;
+   input \trdreq;
+   input \trdclk;
+   input \twrclk;
+   input \taclr;
+   output [31:0] q;
+   output \t rdfull;
+   output \t rdempty;
+   output [10:0]  rdusedw;
+   output \t wrfull;
+   output \t wrempty;
+   output [10:0]  wrusedw;
+   
+   reg [width-1:0] mem [0:depth-1];
+   reg [7:0] \t   rdptr;
+   reg [7:0] \t   wrptr;
+   
+`ifdef rd_req
+   reg [width-1:0] q;
+`else
+   wire [width-1:0] q;
+`endif
+   
+   reg [10:0] \t    rdusedw;
+   reg [10:0] \t    wrusedw;
+   
+   integer \t    i;
+
+   always @( aclr)
+     begin
+\twrptr <= #1 0;
+\trdptr <= #1 0;
+\tfor(i=0;i<depth;i=i+1)
+\t  mem[i] <= #1 0;
+     end
+   
+   always @(posedge wrclk)
+     if(wrreq)
+       begin
+\t  wrptr <= #1 wrptr+1;
+\t  mem[wrptr] <= #1 data;
+       end
+   
+   always @(posedge rdclk)
+     if(rdreq)
+       begin
+   \t  rdptr <= #1 rdptr+1;
+`ifdef rd_req
+\t  q <= #1 mem[rdptr];
+`endif
+       end
+   
+`ifdef rd_req
+`else
+   assign q = mem[rdptr];
+`endif
+   
+   // Fix these
+   always @(posedge wrclk)
+     wrusedw <= #1 wrptr - rdptr;
+   
+   always @(posedge rdclk)
+     rdusedw <= #1 wrptr - rdptr;
+
+   assign wrempty = (wrusedw == 0);
+   assign wrfull = (wrusedw == depth-1);
+   
+   assign rdempty = (rdusedw == 0);
+   assign rdfull = (rdusedw == depth-1);
+   
+endmodule // fifo_1c_2k
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module gen_sync
+  ( input clock,
+    input reset,
+    input enable,
+    input [7:0] rate,
+    output wire sync );
+   
+//   parameter width = 8;
+   
+   reg [7:0] counter;
+   assign sync = |(((rate+1)>>1)& counter);
+      
+   always @(posedge clock)
+     if(reset || ~enable)
+       counter <= #1 0;
+     else if(counter == rate)
+       counter <= #1 0;
+     else 
+       counter <= #1 counter + 8'd1;
+   
+endmodule // gen_sync
+
+"
+"// Bidirectional registers
+
+module bidir_reg
+  ( inout wire [15:0] tristate,
+    input wire [15:0] oe,
+    input wire [15:0] reg_val );
+
+   // This would be much cleaner if all the tools
+   // supported ""for generate""........
+
+   assign \t tristate[0] = oe[0] ? reg_val[0] : 1\'bz;
+   assign \t tristate[1] = oe[1] ? reg_val[1] : 1\'bz;
+   assign \t tristate[2] = oe[2] ? reg_val[2] : 1\'bz;
+   assign \t tristate[3] = oe[3] ? reg_val[3] : 1\'bz;
+   assign \t tristate[4] = oe[4] ? reg_val[4] : 1\'bz;
+   assign \t tristate[5] = oe[5] ? reg_val[5] : 1\'bz;
+   assign \t tristate[6] = oe[6] ? reg_val[6] : 1\'bz;
+   assign \t tristate[7] = oe[7] ? reg_val[7] : 1\'bz;
+   assign \t tristate[8] = oe[8] ? reg_val[8] : 1\'bz;
+   assign \t tristate[9] = oe[9] ? reg_val[9] : 1\'bz;
+   assign \t tristate[10] = oe[10] ? reg_val[10] : 1\'bz;
+   assign \t tristate[11] = oe[11] ? reg_val[11] : 1\'bz;
+   assign \t tristate[12] = oe[12] ? reg_val[12] : 1\'bz;
+   assign \t tristate[13] = oe[13] ? reg_val[13] : 1\'bz;
+   assign \t tristate[14] = oe[14] ? reg_val[14] : 1\'bz;
+   assign \t tristate[15] = oe[15] ? reg_val[15] : 1\'bz;
+   
+endmodule // bidir_reg
+
+"
+"// megafunction wizard: %ALTACCUMULATE%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altaccumulate 
+
+// ============================================================
+// File Name: accum32.v
+// Megafunction Name(s):
+// \t\t\taltaccumulate
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
+//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
+
+//synthesis_resources = lut 32 
+module  accum32_accum_nta
+\t( 
+\taclr,
+\tclken,
+\tclock,
+\tdata,
+\tresult) /* synthesis synthesis_clearbox=1 */;
+\tinput   aclr;
+\tinput   clken;
+\tinput   clock;
+\tinput   [31:0]  data;
+\toutput   [31:0]  result;
+
+\twire  [0:0]   wire_acc_cella_0cout;
+\twire  [0:0]   wire_acc_cella_1cout;
+\twire  [0:0]   wire_acc_cella_2cout;
+\twire  [0:0]   wire_acc_cella_3cout;
+\twire  [0:0]   wire_acc_cella_4cout;
+\twire  [0:0]   wire_acc_cella_5cout;
+\twire  [0:0]   wire_acc_cella_6cout;
+\twire  [0:0]   wire_acc_cella_7cout;
+\twire  [0:0]   wire_acc_cella_8cout;
+\twire  [0:0]   wire_acc_cella_9cout;
+\twire  [0:0]   wire_acc_cella_10cout;
+\twire  [0:0]   wire_acc_cella_11cout;
+\twire  [0:0]   wire_acc_cella_12cout;
+\twire  [0:0]   wire_acc_cella_13cout;
+\twire  [0:0]   wire_acc_cella_14cout;
+\twire  [0:0]   wire_acc_cella_15cout;
+\twire  [0:0]   wire_acc_cella_16cout;
+\twire  [0:0]   wire_acc_cella_17cout;
+\twire  [0:0]   wire_acc_cella_18cout;
+\twire  [0:0]   wire_acc_cella_19cout;
+\twire  [0:0]   wire_acc_cella_20cout;
+\twire  [0:0]   wire_acc_cella_21cout;
+\twire  [0:0]   wire_acc_cella_22cout;
+\twire  [0:0]   wire_acc_cella_23cout;
+\twire  [0:0]   wire_acc_cella_24cout;
+\twire  [0:0]   wire_acc_cella_25cout;
+\twire  [0:0]   wire_acc_cella_26cout;
+\twire  [0:0]   wire_acc_cella_27cout;
+\twire  [0:0]   wire_acc_cella_28cout;
+\twire  [0:0]   wire_acc_cella_29cout;
+\twire  [0:0]   wire_acc_cella_30cout;
+\twire  [31:0]   wire_acc_cella_dataa;
+\twire  [31:0]   wire_acc_cella_datab;
+\twire  [31:0]   wire_acc_cella_datac;
+\twire  [31:0]   wire_acc_cella_regout;
+\twire sload;
+
+\tstratix_lcell   acc_cella_0
+\t( 
+\t.aclr(aclr),
+\t.cin(1\'b0),
+\t.clk(clock),
+\t.cout(wire_acc_cella_0cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[0:0]),
+\t.datab(wire_acc_cella_datab[0:0]),
+\t.datac(wire_acc_cella_datac[0:0]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[0:0]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_0.cin_used = ""true"",
+\t\tacc_cella_0.lut_mask = ""96e8"",
+\t\tacc_cella_0.operation_mode = ""arithmetic"",
+\t\tacc_cella_0.sum_lutc_input = ""cin"",
+\t\tacc_cella_0.synch_mode = ""on"",
+\t\tacc_cella_0.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_1
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_0cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_1cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[1:1]),
+\t.datab(wire_acc_cella_datab[1:1]),
+\t.datac(wire_acc_cella_datac[1:1]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[1:1]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_1.cin_used = ""true"",
+\t\tacc_cella_1.lut_mask = ""96e8"",
+\t\tacc_cella_1.operation_mode = ""arithmetic"",
+\t\tacc_cella_1.sum_lutc_input = ""cin"",
+\t\tacc_cella_1.synch_mode = ""on"",
+\t\tacc_cella_1.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_2
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_1cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_2cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[2:2]),
+\t.datab(wire_acc_cella_datab[2:2]),
+\t.datac(wire_acc_cella_datac[2:2]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[2:2]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_2.cin_used = ""true"",
+\t\tacc_cella_2.lut_mask = ""96e8"",
+\t\tacc_cella_2.operation_mode = ""arithmetic"",
+\t\tacc_cella_2.sum_lutc_input = ""cin"",
+\t\tacc_cella_2.synch_mode = ""on"",
+\t\tacc_cella_2.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_3
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_2cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_3cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[3:3]),
+\t.datab(wire_acc_cella_datab[3:3]),
+\t.datac(wire_acc_cella_datac[3:3]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[3:3]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_3.cin_used = ""true"",
+\t\tacc_cella_3.lut_mask = ""96e8"",
+\t\tacc_cella_3.operation_mode = ""arithmetic"",
+\t\tacc_cella_3.sum_lutc_input = ""cin"",
+\t\tacc_cella_3.synch_mode = ""on"",
+\t\tacc_cella_3.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_4
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_3cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_4cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[4:4]),
+\t.datab(wire_acc_cella_datab[4:4]),
+\t.datac(wire_acc_cella_datac[4:4]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[4:4]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_4.cin_used = ""true"",
+\t\tacc_cella_4.lut_mask = ""96e8"",
+\t\tacc_cella_4.operation_mode = ""arithmetic"",
+\t\tacc_cella_4.sum_lutc_input = ""cin"",
+\t\tacc_cella_4.synch_mode = ""on"",
+\t\tacc_cella_4.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_5
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_4cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_5cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[5:5]),
+\t.datab(wire_acc_cella_datab[5:5]),
+\t.datac(wire_acc_cella_datac[5:5]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[5:5]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_5.cin_used = ""true"",
+\t\tacc_cella_5.lut_mask = ""96e8"",
+\t\tacc_cella_5.operation_mode = ""arithmetic"",
+\t\tacc_cella_5.sum_lutc_input = ""cin"",
+\t\tacc_cella_5.synch_mode = ""on"",
+\t\tacc_cella_5.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_6
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_5cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_6cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[6:6]),
+\t.datab(wire_acc_cella_datab[6:6]),
+\t.datac(wire_acc_cella_datac[6:6]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[6:6]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_6.cin_used = ""true"",
+\t\tacc_cella_6.lut_mask = ""96e8"",
+\t\tacc_cella_6.operation_mode = ""arithmetic"",
+\t\tacc_cella_6.sum_lutc_input = ""cin"",
+\t\tacc_cella_6.synch_mode = ""on"",
+\t\tacc_cella_6.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_7
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_6cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_7cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[7:7]),
+\t.datab(wire_acc_cella_datab[7:7]),
+\t.datac(wire_acc_cella_datac[7:7]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[7:7]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_7.cin_used = ""true"",
+\t\tacc_cella_7.lut_mask = ""96e8"",
+\t\tacc_cella_7.operation_mode = ""arithmetic"",
+\t\tacc_cella_7.sum_lutc_input = ""cin"",
+\t\tacc_cella_7.synch_mode = ""on"",
+\t\tacc_cella_7.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_8
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_7cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_8cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[8:8]),
+\t.datab(wire_acc_cella_datab[8:8]),
+\t.datac(wire_acc_cella_datac[8:8]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[8:8]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_8.cin_used = ""true"",
+\t\tacc_cella_8.lut_mask = ""96e8"",
+\t\tacc_cella_8.operation_mode = ""arithmetic"",
+\t\tacc_cella_8.sum_lutc_input = ""cin"",
+\t\tacc_cella_8.synch_mode = ""on"",
+\t\tacc_cella_8.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_9
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_8cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_9cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[9:9]),
+\t.datab(wire_acc_cella_datab[9:9]),
+\t.datac(wire_acc_cella_datac[9:9]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[9:9]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_9.cin_used = ""true"",
+\t\tacc_cella_9.lut_mask = ""96e8"",
+\t\tacc_cella_9.operation_mode = ""arithmetic"",
+\t\tacc_cella_9.sum_lutc_input = ""cin"",
+\t\tacc_cella_9.synch_mode = ""on"",
+\t\tacc_cella_9.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_10
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_9cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_10cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[10:10]),
+\t.datab(wire_acc_cella_datab[10:10]),
+\t.datac(wire_acc_cella_datac[10:10]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[10:10]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_10.cin_used = ""true"",
+\t\tacc_cella_10.lut_mask = ""96e8"",
+\t\tacc_cella_10.operation_mode = ""arithmetic"",
+\t\tacc_cella_10.sum_lutc_input = ""cin"",
+\t\tacc_cella_10.synch_mode = ""on"",
+\t\tacc_cella_10.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_11
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_10cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_11cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[11:11]),
+\t.datab(wire_acc_cella_datab[11:11]),
+\t.datac(wire_acc_cella_datac[11:11]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[11:11]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_11.cin_used = ""true"",
+\t\tacc_cella_11.lut_mask = ""96e8"",
+\t\tacc_cella_11.operation_mode = ""arithmetic"",
+\t\tacc_cella_11.sum_lutc_input = ""cin"",
+\t\tacc_cella_11.synch_mode = ""on"",
+\t\tacc_cella_11.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_12
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_11cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_12cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[12:12]),
+\t.datab(wire_acc_cella_datab[12:12]),
+\t.datac(wire_acc_cella_datac[12:12]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[12:12]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_12.cin_used = ""true"",
+\t\tacc_cella_12.lut_mask = ""96e8"",
+\t\tacc_cella_12.operation_mode = ""arithmetic"",
+\t\tacc_cella_12.sum_lutc_input = ""cin"",
+\t\tacc_cella_12.synch_mode = ""on"",
+\t\tacc_cella_12.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_13
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_12cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_13cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[13:13]),
+\t.datab(wire_acc_cella_datab[13:13]),
+\t.datac(wire_acc_cella_datac[13:13]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[13:13]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_13.cin_used = ""true"",
+\t\tacc_cella_13.lut_mask = ""96e8"",
+\t\tacc_cella_13.operation_mode = ""arithmetic"",
+\t\tacc_cella_13.sum_lutc_input = ""cin"",
+\t\tacc_cella_13.synch_mode = ""on"",
+\t\tacc_cella_13.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_14
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_13cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_14cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[14:14]),
+\t.datab(wire_acc_cella_datab[14:14]),
+\t.datac(wire_acc_cella_datac[14:14]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[14:14]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_14.cin_used = ""true"",
+\t\tacc_cella_14.lut_mask = ""96e8"",
+\t\tacc_cella_14.operation_mode = ""arithmetic"",
+\t\tacc_cella_14.sum_lutc_input = ""cin"",
+\t\tacc_cella_14.synch_mode = ""on"",
+\t\tacc_cella_14.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_15
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_14cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_15cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[15:15]),
+\t.datab(wire_acc_cella_datab[15:15]),
+\t.datac(wire_acc_cella_datac[15:15]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[15:15]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_15.cin_used = ""true"",
+\t\tacc_cella_15.lut_mask = ""96e8"",
+\t\tacc_cella_15.operation_mode = ""arithmetic"",
+\t\tacc_cella_15.sum_lutc_input = ""cin"",
+\t\tacc_cella_15.synch_mode = ""on"",
+\t\tacc_cella_15.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_16
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_15cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_16cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[16:16]),
+\t.datab(wire_acc_cella_datab[16:16]),
+\t.datac(wire_acc_cella_datac[16:16]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[16:16]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_16.cin_used = ""true"",
+\t\tacc_cella_16.lut_mask = ""96e8"",
+\t\tacc_cella_16.operation_mode = ""arithmetic"",
+\t\tacc_cella_16.sum_lutc_input = ""cin"",
+\t\tacc_cella_16.synch_mode = ""on"",
+\t\tacc_cella_16.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_17
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_16cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_17cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[17:17]),
+\t.datab(wire_acc_cella_datab[17:17]),
+\t.datac(wire_acc_cella_datac[17:17]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[17:17]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_17.cin_used = ""true"",
+\t\tacc_cella_17.lut_mask = ""96e8"",
+\t\tacc_cella_17.operation_mode = ""arithmetic"",
+\t\tacc_cella_17.sum_lutc_input = ""cin"",
+\t\tacc_cella_17.synch_mode = ""on"",
+\t\tacc_cella_17.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_18
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_17cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_18cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[18:18]),
+\t.datab(wire_acc_cella_datab[18:18]),
+\t.datac(wire_acc_cella_datac[18:18]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[18:18]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_18.cin_used = ""true"",
+\t\tacc_cella_18.lut_mask = ""96e8"",
+\t\tacc_cella_18.operation_mode = ""arithmetic"",
+\t\tacc_cella_18.sum_lutc_input = ""cin"",
+\t\tacc_cella_18.synch_mode = ""on"",
+\t\tacc_cella_18.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_19
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_18cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_19cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[19:19]),
+\t.datab(wire_acc_cella_datab[19:19]),
+\t.datac(wire_acc_cella_datac[19:19]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[19:19]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_19.cin_used = ""true"",
+\t\tacc_cella_19.lut_mask = ""96e8"",
+\t\tacc_cella_19.operation_mode = ""arithmetic"",
+\t\tacc_cella_19.sum_lutc_input = ""cin"",
+\t\tacc_cella_19.synch_mode = ""on"",
+\t\tacc_cella_19.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_20
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_19cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_20cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[20:20]),
+\t.datab(wire_acc_cella_datab[20:20]),
+\t.datac(wire_acc_cella_datac[20:20]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[20:20]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_20.cin_used = ""true"",
+\t\tacc_cella_20.lut_mask = ""96e8"",
+\t\tacc_cella_20.operation_mode = ""arithmetic"",
+\t\tacc_cella_20.sum_lutc_input = ""cin"",
+\t\tacc_cella_20.synch_mode = ""on"",
+\t\tacc_cella_20.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_21
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_20cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_21cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[21:21]),
+\t.datab(wire_acc_cella_datab[21:21]),
+\t.datac(wire_acc_cella_datac[21:21]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[21:21]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_21.cin_used = ""true"",
+\t\tacc_cella_21.lut_mask = ""96e8"",
+\t\tacc_cella_21.operation_mode = ""arithmetic"",
+\t\tacc_cella_21.sum_lutc_input = ""cin"",
+\t\tacc_cella_21.synch_mode = ""on"",
+\t\tacc_cella_21.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_22
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_21cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_22cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[22:22]),
+\t.datab(wire_acc_cella_datab[22:22]),
+\t.datac(wire_acc_cella_datac[22:22]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[22:22]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_22.cin_used = ""true"",
+\t\tacc_cella_22.lut_mask = ""96e8"",
+\t\tacc_cella_22.operation_mode = ""arithmetic"",
+\t\tacc_cella_22.sum_lutc_input = ""cin"",
+\t\tacc_cella_22.synch_mode = ""on"",
+\t\tacc_cella_22.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_23
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_22cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_23cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[23:23]),
+\t.datab(wire_acc_cella_datab[23:23]),
+\t.datac(wire_acc_cella_datac[23:23]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[23:23]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_23.cin_used = ""true"",
+\t\tacc_cella_23.lut_mask = ""96e8"",
+\t\tacc_cella_23.operation_mode = ""arithmetic"",
+\t\tacc_cella_23.sum_lutc_input = ""cin"",
+\t\tacc_cella_23.synch_mode = ""on"",
+\t\tacc_cella_23.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_24
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_23cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_24cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[24:24]),
+\t.datab(wire_acc_cella_datab[24:24]),
+\t.datac(wire_acc_cella_datac[24:24]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[24:24]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_24.cin_used = ""true"",
+\t\tacc_cella_24.lut_mask = ""96e8"",
+\t\tacc_cella_24.operation_mode = ""arithmetic"",
+\t\tacc_cella_24.sum_lutc_input = ""cin"",
+\t\tacc_cella_24.synch_mode = ""on"",
+\t\tacc_cella_24.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_25
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_24cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_25cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[25:25]),
+\t.datab(wire_acc_cella_datab[25:25]),
+\t.datac(wire_acc_cella_datac[25:25]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[25:25]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_25.cin_used = ""true"",
+\t\tacc_cella_25.lut_mask = ""96e8"",
+\t\tacc_cella_25.operation_mode = ""arithmetic"",
+\t\tacc_cella_25.sum_lutc_input = ""cin"",
+\t\tacc_cella_25.synch_mode = ""on"",
+\t\tacc_cella_25.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_26
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_25cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_26cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[26:26]),
+\t.datab(wire_acc_cella_datab[26:26]),
+\t.datac(wire_acc_cella_datac[26:26]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[26:26]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_26.cin_used = ""true"",
+\t\tacc_cella_26.lut_mask = ""96e8"",
+\t\tacc_cella_26.operation_mode = ""arithmetic"",
+\t\tacc_cella_26.sum_lutc_input = ""cin"",
+\t\tacc_cella_26.synch_mode = ""on"",
+\t\tacc_cella_26.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_27
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_26cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_27cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[27:27]),
+\t.datab(wire_acc_cella_datab[27:27]),
+\t.datac(wire_acc_cella_datac[27:27]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[27:27]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_27.cin_used = ""true"",
+\t\tacc_cella_27.lut_mask = ""96e8"",
+\t\tacc_cella_27.operation_mode = ""arithmetic"",
+\t\tacc_cella_27.sum_lutc_input = ""cin"",
+\t\tacc_cella_27.synch_mode = ""on"",
+\t\tacc_cella_27.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_28
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_27cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_28cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[28:28]),
+\t.datab(wire_acc_cella_datab[28:28]),
+\t.datac(wire_acc_cella_datac[28:28]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[28:28]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_28.cin_used = ""true"",
+\t\tacc_cella_28.lut_mask = ""96e8"",
+\t\tacc_cella_28.operation_mode = ""arithmetic"",
+\t\tacc_cella_28.sum_lutc_input = ""cin"",
+\t\tacc_cella_28.synch_mode = ""on"",
+\t\tacc_cella_28.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_29
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_28cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_29cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[29:29]),
+\t.datab(wire_acc_cella_datab[29:29]),
+\t.datac(wire_acc_cella_datac[29:29]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[29:29]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_29.cin_used = ""true"",
+\t\tacc_cella_29.lut_mask = ""96e8"",
+\t\tacc_cella_29.operation_mode = ""arithmetic"",
+\t\tacc_cella_29.sum_lutc_input = ""cin"",
+\t\tacc_cella_29.synch_mode = ""on"",
+\t\tacc_cella_29.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_30
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_29cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_acc_cella_30cout[0:0]),
+\t.dataa(wire_acc_cella_dataa[30:30]),
+\t.datab(wire_acc_cella_datab[30:30]),
+\t.datac(wire_acc_cella_datac[30:30]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[30:30]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_30.cin_used = ""true"",
+\t\tacc_cella_30.lut_mask = ""96e8"",
+\t\tacc_cella_30.operation_mode = ""arithmetic"",
+\t\tacc_cella_30.sum_lutc_input = ""cin"",
+\t\tacc_cella_30.synch_mode = ""on"",
+\t\tacc_cella_30.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   acc_cella_31
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_acc_cella_30cout[0:0]),
+\t.clk(clock),
+\t.dataa(wire_acc_cella_dataa[31:31]),
+\t.datab(wire_acc_cella_datab[31:31]),
+\t.datac(wire_acc_cella_datac[31:31]),
+\t.ena(clken),
+\t.regout(wire_acc_cella_regout[31:31]),
+\t.sload(sload));
+\tdefparam
+\t\tacc_cella_31.cin_used = ""true"",
+\t\tacc_cella_31.lut_mask = ""9696"",
+\t\tacc_cella_31.operation_mode = ""normal"",
+\t\tacc_cella_31.sum_lutc_input = ""cin"",
+\t\tacc_cella_31.synch_mode = ""on"",
+\t\tacc_cella_31.lpm_type = ""stratix_lcell"";
+\tassign
+\t\twire_acc_cella_dataa = data,
+\t\twire_acc_cella_datab = wire_acc_cella_regout,
+\t\twire_acc_cella_datac = data;
+\tassign
+\t\tresult = wire_acc_cella_regout,
+\t\tsload = 1\'b0;
+endmodule //accum32_accum_nta
+//VALID FILE
+
+
+module accum32 (
+\tdata,
+\tclock,
+\tclken,
+\taclr,
+\tresult)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t[31:0]  data;
+\tinput\t  clock;
+\tinput\t  clken;
+\tinput\t  aclr;
+\toutput\t[31:0]  result;
+
+\twire [31:0] sub_wire0;
+\twire [31:0] result = sub_wire0[31:0];
+
+\taccum32_accum_nta\taccum32_accum_nta_component (
+\t\t\t\t.clken (clken),
+\t\t\t\t.aclr (aclr),
+\t\t\t\t.clock (clock),
+\t\t\t\t.data (data),
+\t\t\t\t.result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: WIDTH_IN NUMERIC ""32""
+// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC ""32""
+// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC ""0""
+// Retrieval info: PRIVATE: SLOAD NUMERIC ""0""
+// Retrieval info: PRIVATE: ADD_SUB NUMERIC ""0""
+// Retrieval info: PRIVATE: CIN NUMERIC ""0""
+// Retrieval info: PRIVATE: CLKEN NUMERIC ""1""
+// Retrieval info: PRIVATE: ACLR NUMERIC ""1""
+// Retrieval info: PRIVATE: COUT NUMERIC ""0""
+// Retrieval info: PRIVATE: OVERFLOW NUMERIC ""0""
+// Retrieval info: PRIVATE: LATENCY NUMERIC ""0""
+// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC ""0""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: WIDTH_IN NUMERIC ""32""
+// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC ""32""
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING ""SIGNED""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""altaccumulate""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+
+// Basic Phase accumulator for DDS
+
+
+module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);   
+   parameter FREQADDR = 0;
+   parameter PHASEADDR = 0;
+   parameter resolution = 32;
+   
+   input     clk, reset, enable, strobe;
+   input [6:0] serial_addr;
+   input [31:0] serial_data;
+   input \tserial_strobe;
+   
+   output reg [resolution-1:0] phase;
+   wire [resolution-1:0] freq;
+
+   setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
+
+   always @(posedge clk)
+     if(reset)
+       phase <= #1 32'b0;
+     else if(serial_strobe & (serial_addr == PHASEADDR))
+       phase <= #1 serial_data;
+     else if(enable & strobe)
+       phase <= #1 phase + freq;
+
+endmodule // phase_acc
+
+   
+"
+"
+module usb_fifo_writer
+   #(parameter BUS_WIDTH = 16,
+     parameter NUM_CHAN = 2,
+     parameter FIFO_WIDTH = 32)
+   (     //FX2 Side
+\t\t\tinput bus_reset, 
+\t\t\tinput usbclk, 
+\t\t\tinput WR_fx2, 
+\t\t\tinput [15:0]usbdata,
+\t\t\t
+\t\t\t// TX Side
+\t\t\tinput reset,
+\t\t\tinput txclk,
+\t\t\toutput reg [NUM_CHAN:0] WR_channel,
+\t\t\toutput reg [FIFO_WIDTH-1:0] ram_data,
+\t\t\toutput reg [NUM_CHAN:0] WR_done_channel );
+   
+
+\treg [8:0] write_count;
+
+\t/* Fix FX2 bug */
+\talways @(posedge usbclk)
+    \tif(bus_reset)        // Use bus reset because this is on usbclk
+       \t\twrite_count <= #1 0;
+    \telse if(WR_fx2 & ~write_count[8])
+    \t\twrite_count <= #1 write_count + 9'd1;
+    \telse
+    \t\twrite_count <= #1 WR_fx2 ? write_count : 9'b0;
+
+\treg WR_fx2_fixed;
+\treg [15:0]usbdata_fixed;
+\t
+\talways @(posedge usbclk) 
+\tbegin
+\t   WR_fx2_fixed <= WR_fx2 & ~write_count[8];
+\t   usbdata_fixed <= usbdata;
+\tend
+
+\t/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
+    reg                             word_complete ;
+    reg     [BUS_WIDTH-1:0]         usbdata_delayed ;
+    reg                             writing ;
+\twire\t[FIFO_WIDTH-1:0]\t\tusbdata_packed ;    
+\twire\t\t\t\t\t\t\tWR_packed ;
+   
+    always @(posedge usbclk)
+    begin
+        if (bus_reset)
+          begin
+            word_complete <= 0 ;
+            writing <= 0 ;
+          end
+        else if (WR_fx2_fixed)
+          begin
+            writing <= 1 ;
+            if (word_complete)
+                word_complete <= 0 ;
+            else
+              begin
+                usbdata_delayed <= usbdata_fixed ;
+                word_complete <= 1 ;
+              end
+          end
+        else
+            writing <= 0 ;
+\tend
+    
+\tassign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
+    assign WR_packed = word_complete & writing ;
+
+\t/* Make sure data are sync with usbclk */
+ \treg [31:0]usbdata_usbclk;
+\treg WR_usbclk; 
+    
+    always @(posedge usbclk)
+    begin
+    \tif (WR_packed)
+    \t\tusbdata_usbclk <= usbdata_packed;
+        WR_usbclk <= WR_packed;
+    end
+
+\t/* Cross clock boundaries */
+\treg [FIFO_WIDTH-1:0] usbdata_tx ;
+\treg WR_tx;
+    reg WR_1;
+    reg WR_2;
+\treg [31:0] usbdata_final;
+\treg WR_final;
+   
+\talways @(posedge txclk) usbdata_tx <= usbdata_usbclk;
+
+    always @(posedge txclk) 
+    \tif (reset)
+    \t\tWR_1 <= 0;
+    \telse
+       \t\tWR_1 <= WR_usbclk;
+
+    always @(posedge txclk) 
+    \tif (reset)
+       \t\tWR_2 <= 0;
+    \telse
+      \t\tWR_2 <= WR_1;
+
+\talways @(posedge txclk)
+\tbegin
+\t\tif (reset)
+\t\t\tWR_tx <= 0;
+\t\telse
+\t\t   WR_tx <= WR_1 & ~WR_2;
+\tend
+\t
+\talways @(posedge txclk)
+\tbegin
+\t   if (reset)
+\t      WR_final <= 0;
+\t   else
+\t   begin
+\t      WR_final <= WR_tx; 
+\t      if (WR_tx)
+\t         usbdata_final <= usbdata_tx;
+\t   end
+\tend
+\t     
+\t/* Parse header and forward to ram */
+\treg [3:0]reader_state;
+\treg [4:0]channel ;
+\treg [9:0]read_length ;
+\t
+\tparameter IDLE = 4'd0;
+\tparameter HEADER = 4'd1;
+\tparameter WAIT = 4'd2;
+\tparameter FORWARD = 4'd3;
+\t
+\t`define CHANNEL 20:16
+\t`define PKT_SIZE 512
+\t
+\talways @(posedge txclk)
+\tbegin
+\t    if (reset)
+\t      begin
+\t       reader_state <= 0;
+\t       WR_channel <= 0;
+\t       WR_done_channel <= 0;
+\t      end
+\t      else
+\t        case (reader_state)
+\t        IDLE: begin
+\t            if (WR_final)
+\t                reader_state <= HEADER; 
+\t            end
+\t       
+            // Store channel and forware header
+\t        HEADER: begin
+\t            channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL]) ;
+\t            WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL])] <= 1;
+\t\t\t\t//channel <= usbdata_final[`CHANNEL] ;
+\t            //WR_channel[usbdata_final[`CHANNEL]] <= 1;
+\t            ram_data <= usbdata_final;
+\t\t\t\tread_length <= 10'd4 ;
+\t\t\t\t
+                reader_state <= WAIT;
+\t        end
+\t       
+\t        WAIT: begin
+\t           WR_channel[channel] <= 0;
+\t
+\t\t\t   if (read_length == `PKT_SIZE)
+\t               reader_state <= IDLE;
+\t           else if (WR_final)
+\t               reader_state <= FORWARD;
+\t        end
+\t       
+\t        FORWARD: begin
+\t           WR_channel[channel] <= 1;
+\t           ram_data <= usbdata_final;
+\t           read_length <= read_length + 10'd4;
+\t           
+\t           reader_state <= WAIT;
+\t        end
+\t       endcase
+\tend
+endmodule  "
+"// megafunction wizard: %FIFO%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: dcfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_4k_18.v\r
+// Megafunction Name(s):\r
+// \t\t\tdcfifo\r
+//\r
+// Simulation Library Files(s):\r
+// \t\t\taltera_mf\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2007 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files from any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module fifo_4k_18 (\r
+\taclr,\r
+\tdata,\r
+\trdclk,\r
+\trdreq,\r
+\twrclk,\r
+\twrreq,\r
+\tq,\r
+\trdempty,\r
+\trdusedw,\r
+\twrfull,\r
+\twrusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t[17:0]  data;\r
+\tinput\t  rdclk;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrclk;\r
+\tinput\t  wrreq;\r
+\toutput\t[17:0]  q;\r
+\toutput\t  rdempty;\r
+\toutput\t[11:0]  rdusedw;\r
+\toutput\t  wrfull;\r
+\toutput\t[11:0]  wrusedw;\r
+\r
+\twire  sub_wire0;\r
+\twire [11:0] sub_wire1;\r
+\twire  sub_wire2;\r
+\twire [17:0] sub_wire3;\r
+\twire [11:0] sub_wire4;\r
+\twire  rdempty = sub_wire0;\r
+\twire [11:0] wrusedw = sub_wire1[11:0];\r
+\twire  wrfull = sub_wire2;\r
+\twire [17:0] q = sub_wire3[17:0];\r
+\twire [11:0] rdusedw = sub_wire4[11:0];\r
+\r
+\tdcfifo\tdcfifo_component (\r
+\t\t\t\t.wrclk (wrclk),\r
+\t\t\t\t.rdreq (rdreq),\r
+\t\t\t\t.aclr (aclr),\r
+\t\t\t\t.rdclk (rdclk),\r
+\t\t\t\t.wrreq (wrreq),\r
+\t\t\t\t.data (data),\r
+\t\t\t\t.rdempty (sub_wire0),\r
+\t\t\t\t.wrusedw (sub_wire1),\r
+\t\t\t\t.wrfull (sub_wire2),\r
+\t\t\t\t.q (sub_wire3),\r
+\t\t\t\t.rdusedw (sub_wire4)\r
+\t\t\t\t// synopsys translate_off\r
+\t\t\t\t,\r
+\t\t\t\t.rdfull (),\r
+\t\t\t\t.wrempty ()\r
+\t\t\t\t// synopsys translate_on\r
+\t\t\t\t);\r
+\tdefparam\r
+\t\tdcfifo_component.add_ram_output_register = ""OFF"",\r
+\t\tdcfifo_component.clocks_are_synchronized = ""FALSE"",\r
+\t\tdcfifo_component.intended_device_family = ""Cyclone"",\r
+\t\tdcfifo_component.lpm_numwords = 4096,\r
+\t\tdcfifo_component.lpm_showahead = ""ON"",\r
+\t\tdcfifo_component.lpm_type = ""dcfifo"",\r
+\t\tdcfifo_component.lpm_width = 18,\r
+\t\tdcfifo_component.lpm_widthu = 12,\r
+\t\tdcfifo_component.overflow_checking = ""OFF"",\r
+\t\tdcfifo_component.underflow_checking = ""OFF"",\r
+\t\tdcfifo_component.use_eab = ""ON"";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""4096""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""\r
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING ""0""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""18""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: diff_widths NUMERIC ""0""\r
+// Retrieval info: PRIVATE: msb_usedw NUMERIC ""0""\r
+// Retrieval info: PRIVATE: output_width NUMERIC ""18""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""4096""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""18""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""12""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr\r
+// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]\r
+// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]\r
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk\r
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]\r
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk\r
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]\r
+// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0\r
+// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0\r
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0\r
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0\r
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0\r
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0\r
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE\r
+// Retrieval info: LIB_FILE: altera_mf\r
+"
+"accum32\taccum32_inst (
+\t.data ( data_sig ),
+\t.clock ( clock_sig ),
+\t.clken ( clken_sig ),
+\t.aclr ( aclr_sig ),
+\t.result ( result_sig )
+\t);
+"
+"/* -*- verilog -*-
+ * 
+ *  USRP - Universal Software Radio Peripheral
+ * 
+ *  Copyright (C) 2005 Matt Ettus
+ * 
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ * 
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ * 
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+ */
+
+/*
+ * This implements a 31-tap halfband filter that decimates by two.
+ * The coefficients are symmetric, and with the exception of the middle tap,
+ * every other coefficient is zero.  The middle section of taps looks like this:
+ *
+ *  ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ...
+ *                                             |
+ *                           middle tap -------+
+ *
+ * See coeff_rom.v for the full set.  The taps are scaled relative to 32768,
+ * thus the middle tap equals 1.0.  Not counting the middle tap, there are 8
+ * non-zero taps on each side, and they are symmetric.  A naive implementation
+ * requires a mulitply for each non-zero tap.  Because of symmetry, we can
+ * replace 2 multiplies with 1 add and 1 multiply.  Thus, to compute each output
+ * sample, we need to perform 8 multiplications.  Since the middle tap is 1.0,
+ * we just add the corresponding delay line value.
+ *
+ * About timing: We implement this with a single multiplier, so it takes
+ * 8 cycles to compute a single output.  However, since we\'re decimating by two 
+ * we can accept a new input value every 4 cycles.  strobe_in is asserted when
+ * there\'s a new input sample available.  Depending on the overall decimation
+ * rate, strobe_in may be asserted less frequently than once every 4 clocks.
+ * On the output side, we assert strobe_out when output contains a new sample.
+ *
+ * Implementation: Every time strobe_in is asserted we store the new data into
+ * the delay line.  We split the delay line into two components, one for the
+ * even samples, and one for the odd samples.  ram16_odd is the delay line for
+ * the odd samples.  This ram is written on each odd assertion of strobe_in, and
+ * is read on each clock when we\'re computing the dot product.  ram16_even is
+ * similar, although because it holds the even samples we must be able to read
+ * two samples from different addresses at the same time, while writing the incoming
+ * even samples. Thus it\'s ""triple-ported"".
+ */
+
+module halfband_decim
+  (input clock, input reset, input enable, input strobe_in, output wire strobe_out,
+   input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl);
+
+   reg [3:0] rd_addr1;
+   reg [3:0] rd_addr2;
+   reg [3:0] phase;
+   reg [3:0] base_addr;
+
+   wire      signed [15:0] mac_out,middle_data, sum, coeff;
+   wire      signed [30:0] product;
+   wire      signed [33:0] sum_even;
+   wire      clear;
+   reg \t     store_odd;
+   
+   always @(posedge clock)
+     if(reset)
+       store_odd <= #1 1\'b0;
+     else
+       if(strobe_in)
+\t store_odd <= #1 ~store_odd;
+
+   wire      start = strobe_in & store_odd;
+   always @(posedge clock)
+     if(reset)
+       base_addr <= #1 4\'d0;
+     else if(start)
+       base_addr <= #1 base_addr + 4\'d1;
+
+   always @(posedge clock)
+     if(reset)
+       phase <= #1 4\'d8;
+     else if (start)
+       phase <= #1 4\'d0;
+     else if(phase != 4\'d8)
+       phase <= #1 phase + 4\'d1;
+
+   reg \t     start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD;
+   always @(posedge clock)
+     begin
+\tstart_d1 <= #1 start;
+\tstart_d2 <= #1 start_d1;
+\tstart_d3 <= #1 start_d2;
+\tstart_d4 <= #1 start_d3;
+\tstart_d5 <= #1 start_d4;
+\tstart_d6 <= #1 start_d5;
+\tstart_d7 <= #1 start_d6;
+\tstart_d8 <= #1 start_d7;
+\tstart_d9 <= #1 start_d8;
+\tstart_dA <= #1 start_d9;
+\tstart_dB <= #1 start_dA;
+\tstart_dC <= #1 start_dB;
+\tstart_dD <= #1 start_dC;
+     end // always @ (posedge clock)
+   
+   reg \t  mult_en, mult_en_pre;
+   always @(posedge clock)
+     begin
+\tmult_en_pre <= #1 phase!=8;
+\tmult_en <= #1 mult_en_pre;
+     end
+   
+   assign clear = start_d4; // was dC
+   wire   latch_result = start_d4; // was dC
+   assign strobe_out = start_d5; // was dD
+   wire   acc_en;
+   
+   always @*
+     case(phase[2:0])
+       3\'d0 : begin rd_addr1 = base_addr + 4\'d0; rd_addr2 = base_addr + 4\'d15; end
+       3\'d1 : begin rd_addr1 = base_addr + 4\'d1; rd_addr2 = base_addr + 4\'d14; end
+       3\'d2 : begin rd_addr1 = base_addr + 4\'d2; rd_addr2 = base_addr + 4\'d13; end
+       3\'d3 : begin rd_addr1 = base_addr + 4\'d3; rd_addr2 = base_addr + 4\'d12; end
+       3\'d4 : begin rd_addr1 = base_addr + 4\'d4; rd_addr2 = base_addr + 4\'d11; end
+       3\'d5 : begin rd_addr1 = base_addr + 4\'d5; rd_addr2 = base_addr + 4\'d10; end
+       3\'d6 : begin rd_addr1 = base_addr + 4\'d6; rd_addr2 = base_addr + 4\'d9; end
+       3\'d7 : begin rd_addr1 = base_addr + 4\'d7; rd_addr2 = base_addr + 4\'d8; end
+       default: begin rd_addr1 = base_addr + 4\'d0; rd_addr2 = base_addr + 4\'d15; end
+     endcase // case(phase)
+   
+   coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3\'d1),.data(coeff));
+   
+   ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd),
+\t\t\t  .wr_addr(base_addr),.wr_data(data_in),
+\t\t\t  .rd_addr1(rd_addr1),.rd_addr2(rd_addr2),
+\t\t\t  .sum(sum));
+
+   ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd),  // Holds middle items
+\t\t    .wr_addr(base_addr),.wr_data(data_in),
+\t\t    //.rd_addr(base_addr+4\'d7),.rd_data(middle_data));
+\t\t    .rd_addr(base_addr+4\'d6),.rd_data(middle_data));
+
+   mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en));
+
+   acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(),
+\t   .clear(clear),.addend(product),.sum(sum_even));
+
+   wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14\'b0}; // We already divided product by 2!!!!
+
+   always @(posedge clock)
+     if(reset)
+       data_out <= #1 16\'d0;
+     else if(latch_result)
+       data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]);
+
+   assign  debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase};
+   
+endmodule // halfband_decim
+"
+"
+
+module ram (input clock, input write, 
+\t    input [4:0] wr_addr, input [15:0] wr_data,
+\t    input [4:0] rd_addr, output reg [15:0] rd_data);
+
+   reg [15:0] \t\tram_array [0:31];
+
+   always @(posedge clock)
+     rd_data <= #1 ram_array[rd_addr];
+
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram
+"
+"//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module pll (
+\tinclk0,
+\tc0);
+
+\tinput\t  inclk0;
+\toutput\t  c0;
+
+endmodule
+
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Interface to Cypress FX2 bus
+// A packet is 512 Bytes.  Each fifo line is 2 bytes
+// Fifo has 1024 or 2048 lines
+
+`include ""../../firmware/include/fpga_regs_common.v""
+`include ""../../firmware/include/fpga_regs_standard.v""
+
+module rx_buffer
+  ( input usbclk,
+    input bus_reset,  // Not used in RX
+    input reset,  // DSP side reset (used here), do not reset registers
+    input reset_regs, //Only reset registers
+    output [15:0] usbdata,
+    input RD,
+    output wire have_pkt_rdy,
+    output reg rx_overrun,
+    input wire [3:0] channels,
+    input wire [15:0] ch_0,
+    input wire [15:0] ch_1,
+    input wire [15:0] ch_2,
+    input wire [15:0] ch_3,
+    input wire [15:0] ch_4,
+    input wire [15:0] ch_5,
+    input wire [15:0] ch_6,
+    input wire [15:0] ch_7,
+    input rxclk,
+    input rxstrobe,
+    input clear_status,
+    input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
+    output [15:0] debugbus
+    );
+
+   wire [15:0] fifodata, fifodata_8;
+   reg [15:0]  fifodata_16;
+   
+   wire [11:0] rxfifolevel;
+   wire rx_empty, rx_full;
+
+   wire bypass_hb, want_q;
+   wire [4:0] bitwidth;
+   wire [3:0] bitshift;
+   
+   setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs),
+\t\t\t\t\t    .strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
+\t\t\t\t\t    .out({bypass_hb,want_q,bitwidth,bitshift}));
+
+   // Receive FIFO (ADC --> USB)
+
+   // 257 Bug Fix
+   reg [8:0] read_count;
+   always @(negedge usbclk)
+     if(bus_reset)
+       read_count <= #1 9\'d0;
+     else if(RD & ~read_count[8])
+       read_count <= #1 read_count + 9\'d1;
+     else
+       read_count <= #1 RD ? read_count : 9\'b0;
+   
+   // Detect overrun
+   always @(posedge rxclk)
+     if(reset)
+       rx_overrun <= 1\'b0;
+     else if(rxstrobe & (store_next != 0))
+       rx_overrun <= 1\'b1;
+     else if(clear_status)
+       rx_overrun <= 1\'b0;
+
+   reg [3:0] store_next;
+   always @(posedge rxclk)
+     if(reset)
+       store_next <= #1 4\'d0;
+     else if(rxstrobe & (store_next == 0))
+       store_next <= #1 4\'d1;
+     else if(~rx_full & (store_next == channels))
+       store_next <= #1 4\'d0;
+     else if(~rx_full & (bitwidth == 5\'d8) & (store_next == (channels>>1)))
+       store_next <= #1 4\'d0;
+     else if(~rx_full & (store_next != 0))
+       store_next <= #1 store_next + 4\'d1;
+
+   assign    fifodata = (bitwidth == 5\'d8) ? fifodata_8 : fifodata_16;
+
+   assign    fifodata_8 = {round_8(top),round_8(bottom)};
+   reg [15:0] top,bottom;
+
+   function [7:0] round_8;
+      input [15:0] in_val;
+
+      round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
+   endfunction // round_8
+      
+   always @*
+     case(store_next)
+       4\'d1 : begin
+\t  bottom = ch_0;
+\t  top = ch_1;
+       end
+       4\'d2 : begin
+\t  bottom = ch_2;
+\t  top = ch_3;
+       end
+       4\'d3 : begin
+\t  bottom = ch_4;
+\t  top = ch_5;
+       end
+       4\'d4 : begin
+\t  bottom = ch_6;
+\t  top = ch_7;
+       end
+       default : begin
+\t  top = 16\'hFFFF;
+\t  bottom = 16\'hFFFF;
+       end
+     endcase // case(store_next)
+   
+   always @*
+     case(store_next)
+       4\'d1 : fifodata_16 = ch_0;
+       4\'d2 : fifodata_16 = ch_1;
+       4\'d3 : fifodata_16 = ch_2;
+       4\'d4 : fifodata_16 = ch_3;
+       4\'d5 : fifodata_16 = ch_4;
+       4\'d6 : fifodata_16 = ch_5;
+       4\'d7 : fifodata_16 = ch_6;
+       4\'d8 : fifodata_16 = ch_7;
+       default : fifodata_16 = 16\'hFFFF;
+     endcase // case(store_next)
+   
+   fifo_4k rxfifo 
+     ( .data ( fifodata ),
+       .wrreq (~rx_full & (store_next != 0)),
+       .wrclk ( rxclk ),
+
+       .q ( usbdata ),
+       .rdreq ( RD & ~read_count[8] ), 
+       .rdclk ( ~usbclk ),
+       
+       .aclr ( reset ),  // This one is asynchronous, so we can use either reset
+       
+       .rdempty ( rx_empty ),
+       .rdusedw ( rxfifolevel ),
+       .wrfull ( rx_full ),
+       .wrusedw (  )
+       );
+   
+   assign have_pkt_rdy = (rxfifolevel >= 256);
+
+   // Debugging Aids
+   assign debugbus[0] = RD;
+   assign debugbus[1] = rx_overrun;
+   assign debugbus[2] = read_count[8];
+   assign debugbus[3] = rx_full;
+   assign debugbus[4] = rxstrobe;
+   assign debugbus[5] = usbclk;
+   assign debugbus[6] = have_pkt_rdy;
+   assign debugbus[10:7] = store_next;
+   //assign debugbus[15:11] = rxfifolevel[4:0];
+   assign debugbus[15:11] = bitwidth;
+   
+endmodule // rx_buffer
+
+"
+"// megafunction wizard: %FIFO%VBB%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: dcfifo \r
+\r
+// ============================================================\r
+// File Name: fifo_4kx16_dc.v\r
+// Megafunction Name(s):\r
+// \t\t\tdcfifo\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+//Copyright (C) 1991-2006 Altera Corporation\r
+//Your use of Altera Corporation\'s design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+module fifo_4kx16_dc (\r
+\taclr,\r
+\tdata,\r
+\trdclk,\r
+\trdreq,\r
+\twrclk,\r
+\twrreq,\r
+\tq,\r
+\trdempty,\r
+\trdusedw,\r
+\twrfull,\r
+\twrusedw);\r
+\r
+\tinput\t  aclr;\r
+\tinput\t[15:0]  data;\r
+\tinput\t  rdclk;\r
+\tinput\t  rdreq;\r
+\tinput\t  wrclk;\r
+\tinput\t  wrreq;\r
+\toutput\t[15:0]  q;\r
+\toutput\t  rdempty;\r
+\toutput\t[11:0]  rdusedw;\r
+\toutput\t  wrfull;\r
+\toutput\t[11:0]  wrusedw;\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1""\r
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0""\r
+// Retrieval info: PRIVATE: Clock NUMERIC ""4""\r
+// Retrieval info: PRIVATE: Depth NUMERIC ""4096""\r
+// Retrieval info: PRIVATE: Empty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Full NUMERIC ""1""\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0""\r
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0""\r
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0""\r
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Optimize NUMERIC ""2""\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""\r
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1""\r
+// Retrieval info: PRIVATE: UsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: Width NUMERIC ""16""\r
+// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1""\r
+// Retrieval info: PRIVATE: rsFull NUMERIC ""0""\r
+// Retrieval info: PRIVATE: rsUsedW NUMERIC ""1""\r
+// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0""\r
+// Retrieval info: PRIVATE: wsFull NUMERIC ""1""\r
+// Retrieval info: PRIVATE: wsUsedW NUMERIC ""1""\r
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING ""OFF""\r
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING ""FALSE""\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""\r
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""4096""\r
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON""\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo""\r
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""\r
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""12""\r
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF""\r
+// Retrieval info: CONSTANT: USE_EAB STRING ""ON""\r
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr\r
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]\r
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]\r
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk\r
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty\r
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]\r
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk\r
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull\r
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]\r
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0\r
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0\r
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0\r
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0\r
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0\r
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0\r
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0\r
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0\r
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE\r
+"
+"
+
+module ram16_2sum (input clock, input write, 
+\t\t   input [3:0] wr_addr, input [15:0] wr_data,
+\t\t   input [3:0] rd_addr1, input [3:0] rd_addr2,
+                   output reg [15:0] sum);
+   
+   reg signed [15:0] \t  ram_array [0:15];
+   reg signed [15:0] \t  a,b;
+   wire signed [16:0] \t  sum_int;
+   
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+      
+   always @(posedge clock)
+     begin
+\ta <= #1 ram_array[rd_addr1];
+\tb <= #1 ram_array[rd_addr2];
+     end
+   
+   assign sum_int = {a[15],a} + {b[15],b};
+   
+   always @(posedge clock)
+     sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
+     
+endmodule // ram16_2sum
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2006 Martin Dudok van Heel
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+`include ""config.vh""
+`include ""../../../firmware/include/fpga_regs_common.v""
+`include ""../../../firmware/include/fpga_regs_standard.v""
+// Clock, enable, and reset controls for whole system
+// Modified version to enable multi_usrp synchronisation
+
+module master_control_multi
+  ( input master_clk, input usbclk,
+    input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
+    input wire rx_slave_sync,
+    output tx_bus_reset, output rx_bus_reset,
+    output wire tx_dsp_reset, output wire rx_dsp_reset,
+    output wire enable_tx, output wire enable_rx,
+    output wire sync_rx,
+    output wire [7:0] interp_rate, output wire [7:0] decim_rate,
+    output tx_sample_strobe, output strobe_interp,
+    output rx_sample_strobe, output strobe_decim,
+    input tx_empty,
+    input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
+    output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3
+    );
+   
+   wire [15:0] reg_1_std;
+
+   master_control master_control_standard
+     ( .master_clk(master_clk),.usbclk(usbclk),
+       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+       .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
+       .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
+       .enable_tx(enable_tx),.enable_rx(enable_rx),
+       .interp_rate(interp_rate),.decim_rate(decim_rate),
+       .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
+       .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+       .tx_empty(tx_empty),
+       .debug_0(debug_0),.debug_1(debug_1),
+       .debug_2(debug_2),.debug_3(debug_3),
+       .reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) );
+
+   // FIXME need a separate reset for all control settings 
+   // Master/slave Controls assignments
+   wire [7:0] rx_master_slave_controls;
+   setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1\'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls));
+ 
+   assign     sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync);
+  //sync if we are told by master_control or if we get a hardware slave sync
+  //TODO There can be a one sample difference between master and slave sync. 
+  //     Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger
+  //     Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind)
+  //TODO make output pin not hardwired
+assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]};
+
+   
+endmodule // master_control
+"
+"fifo_1kx16\tfifo_1kx16_inst (\r
+\t.aclr ( aclr_sig ),\r
+\t.clock ( clock_sig ),\r
+\t.data ( data_sig ),\r
+\t.rdreq ( rdreq_sig ),\r
+\t.wrreq ( wrreq_sig ),\r
+\t.almost_empty ( almost_empty_sig ),\r
+\t.empty ( empty_sig ),\r
+\t.full ( full_sig ),\r
+\t.q ( q_sig ),\r
+\t.usedw ( usedw_sig )\r
+\t);\r
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module tx_chain_hb
+  (input clock,
+   input reset,
+   input enable,
+   input wire [7:0] interp_rate,
+   input sample_strobe,
+   input interpolator_strobe,
+   input hb_strobe,
+   input wire [31:0] freq,
+   input wire [15:0] i_in,
+   input wire [15:0] q_in,
+   output wire [15:0] i_out,
+   output wire [15:0] q_out,
+output wire [15:0] debug, output [15:0] hb_i_out
+   );
+assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
+
+   wire [15:0] bb_i, bb_q;
+   wire [15:0] hb_i_out, hb_q_out;
+   
+   halfband_interp hb
+     (.clock(clock),.reset(reset),.enable(enable),
+      .strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
+      .signal_in_i(i_in),.signal_in_q(q_in),
+      .signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
+\t.debug(debug[12:0]));
+      
+   cic_interp cic_interp_i
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
+       .signal_in(hb_i_out),.signal_out(bb_i) );
+
+   cic_interp cic_interp_q
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
+       .signal_in(hb_q_out),.signal_out(bb_q) );
+   
+`define NOCORDIC_TX
+`ifdef NOCORDIC_TX
+   assign      i_out = bb_i;
+   assign      q_out = bb_q;
+`else
+   wire [31:0] phase;
+
+   phase_acc phase_acc_tx
+     (.clk(clock),.reset(reset),.enable(enable),
+      .strobe(sample_strobe),.freq(freq),.phase(phase) );
+   
+   cordic tx_cordic_0
+     ( .clock(clock),.reset(reset),.enable(sample_strobe), 
+       .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
+       .xo(i_out),.yo(q_out),.zo() );
+`endif
+
+endmodule // tx_chain
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Interface to Cypress FX2 bus
+// A packet is 512 Bytes.  Each fifo line is 2 bytes
+// Fifo has 1024 or 2048 lines
+
+module tx_buffer
+  ( input usbclk,
+    input bus_reset,  // Used here for the 257-Hack to fix the FX2 bug
+    input reset,  // standard DSP-side reset
+    input [15:0] usbdata,
+    input wire WR,
+    output wire have_space,
+    output reg tx_underrun,
+    input wire [3:0] channels,
+    output reg [15:0] tx_i_0,
+    output reg [15:0] tx_q_0,
+    output reg [15:0] tx_i_1,
+    output reg [15:0] tx_q_1,
+    output reg [15:0] tx_i_2,
+    output reg [15:0] tx_q_2,
+    output reg [15:0] tx_i_3,
+    output reg [15:0] tx_q_3,
+    input txclk,
+    input txstrobe,
+    input clear_status,
+    output wire tx_empty,
+    output [11:0] debugbus
+    );
+   
+   wire [11:0] txfifolevel;
+   reg [8:0] write_count;
+   wire tx_full;
+   wire [15:0] fifodata;
+   wire rdreq;
+
+   reg [3:0] load_next;
+
+   // DAC Side of FIFO
+   assign    rdreq = ((load_next != channels) & !tx_empty);
+   
+   always @(posedge txclk)
+     if(reset)
+       begin
+\t  {tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
+\t    <= #1 128'h0;
+\t  load_next <= #1 4'd0;
+       end
+     else
+       if(load_next != channels)
+\t begin
+\t    load_next <= #1 load_next + 4'd1;
+\t    case(load_next)
+\t      4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
+\t      4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
+\t      4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
+\t      4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
+\t      4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
+\t      4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
+\t      4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
+\t      4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
+\t    endcase // case(load_next)
+\t end // if (load_next != channels)
+       else if(txstrobe & (load_next == channels))
+\t begin
+\t    load_next <= #1 4'd0;
+\t end
+
+   // USB Side of FIFO
+   assign have_space = (txfifolevel <= (4095-256));
+
+   always @(posedge usbclk)
+     if(bus_reset)        // Use bus reset because this is on usbclk
+       write_count <= #1 0;
+     else if(WR & ~write_count[8])
+       write_count <= #1 write_count + 9'd1;
+     else
+       write_count <= #1 WR ? write_count : 9'b0;
+
+   // Detect Underruns
+   always @(posedge txclk)
+     if(reset)
+       tx_underrun <= 1'b0;
+     else if(txstrobe & (load_next != channels))
+       tx_underrun <= 1'b1;
+     else if(clear_status)
+       tx_underrun <= 1'b0;
+
+   // FIFO
+   fifo_4k txfifo 
+     ( .data ( usbdata ),
+       .wrreq ( WR & ~write_count[8] ),
+       .wrclk ( usbclk ),
+       
+       .q ( fifodata ),\t\t\t
+       .rdreq ( rdreq ),
+       .rdclk ( txclk ),
+       
+       .aclr ( reset ),  // asynch, so we can use either
+       
+       .rdempty ( tx_empty ),
+       .rdusedw (  ),
+       .wrfull ( tx_full ),
+       .wrusedw ( txfifolevel )
+       );
+   
+   // Debugging Aids
+   assign debugbus[0] = WR;
+   assign debugbus[1] = have_space;
+   assign debugbus[2] = tx_empty;
+   assign debugbus[3] = tx_full;
+   assign debugbus[4] = tx_underrun;
+   assign debugbus[5] = write_count[8];
+   assign debugbus[6] = txstrobe;
+   assign debugbus[7] = rdreq;
+   assign debugbus[11:8] = load_next;
+   
+endmodule // tx_buffer
+
+"
+"mylpm_addsub\tmylpm_addsub_inst (
+\t.add_sub ( add_sub_sig ),
+\t.dataa ( dataa_sig ),
+\t.datab ( datab_sig ),
+\t.clock ( clock_sig ),
+\t.result ( result_sig )
+\t);
+"
+"// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: dspclkpll.v
+// Megafunction Name(s):
+// \t\t\taltpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module dspclkpll (
+\tinclk0,
+\tc0,
+\tc1);
+
+\tinput\t  inclk0;
+\toutput\t  c0;
+\toutput\t  c1;
+
+\twire [5:0] sub_wire0;
+\twire [0:0] sub_wire5 = 1\'h0;
+\twire [1:1] sub_wire2 = sub_wire0[1:1];
+\twire [0:0] sub_wire1 = sub_wire0[0:0];
+\twire  c0 = sub_wire1;
+\twire  c1 = sub_wire2;
+\twire  sub_wire3 = inclk0;
+\twire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+\taltpll\taltpll_component (
+\t\t\t\t.inclk (sub_wire4),
+\t\t\t\t.clk (sub_wire0)
+\t\t\t\t// synopsys translate_off
+,
+\t\t\t\t.fbin (),
+\t\t\t\t.pllena (),
+\t\t\t\t.clkswitch (),
+\t\t\t\t.areset (),
+\t\t\t\t.pfdena (),
+\t\t\t\t.clkena (),
+\t\t\t\t.extclkena (),
+\t\t\t\t.scanclk (),
+\t\t\t\t.scanaclr (),
+\t\t\t\t.scandata (),
+\t\t\t\t.scanread (),
+\t\t\t\t.scanwrite (),
+\t\t\t\t.extclk (),
+\t\t\t\t.clkbad (),
+\t\t\t\t.activeclock (),
+\t\t\t\t.locked (),
+\t\t\t\t.clkloss (),
+\t\t\t\t.scandataout (),
+\t\t\t\t.scandone (),
+\t\t\t\t.sclkout1 (),
+\t\t\t\t.sclkout0 (),
+\t\t\t\t.enable0 (),
+\t\t\t\t.enable1 ()
+\t\t\t\t// synopsys translate_on
+
+);
+\tdefparam
+\t\taltpll_component.clk1_divide_by = 1,
+\t\taltpll_component.clk1_phase_shift = ""0"",
+\t\taltpll_component.clk0_duty_cycle = 50,
+\t\taltpll_component.lpm_type = ""altpll"",
+\t\taltpll_component.clk0_multiply_by = 1,
+\t\taltpll_component.inclk0_input_frequency = 15625,
+\t\taltpll_component.clk0_divide_by = 1,
+\t\taltpll_component.clk1_duty_cycle = 50,
+\t\taltpll_component.pll_type = ""AUTO"",
+\t\taltpll_component.clk1_multiply_by = 2,
+\t\taltpll_component.clk0_time_delay = ""0"",
+\t\taltpll_component.intended_device_family = ""Cyclone"",
+\t\taltpll_component.operation_mode = ""NORMAL"",
+\t\taltpll_component.compensate_clock = ""CLK0"",
+\t\taltpll_component.clk1_time_delay = ""0"",
+\t\taltpll_component.clk0_phase_shift = ""0"";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING ""0""
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING ""deg""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING ""MHz""
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING ""MHz""
+// Retrieval info: PRIVATE: SPREAD_USE STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC ""1048575""
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING ""0""
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING ""0""
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING ""deg""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING ""MHz""
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING ""50.00000000""
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING ""0.00000000""
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC ""1""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING ""0.500""
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING ""0""
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING ""0""
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING ""50.00000000""
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING ""0.00000000""
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC ""2""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING ""0""
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING ""0.00000000""
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING ""1""
+// Retrieval info: PRIVATE: BANDWIDTH STRING ""1.000""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING ""0""
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING ""8""
+// Retrieval info: PRIVATE: TIME_SHIFT1 STRING ""0.00000000""
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING ""1""
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING ""50.000""
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING ""1""
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC ""0""
+// Retrieval info: PRIVATE: USE_CLK0 STRING ""1""
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING ""0""
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING ""0""
+// Retrieval info: PRIVATE: USE_CLK1 STRING ""1""
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING ""0""
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING ""100.000""
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING ""c0""
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING ""MHz""
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING ""MHz""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING ""inclk;fbin;pllena;clkswitch;areset""
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING ""0""
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING ""1""
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING ""e0""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING ""pfdena;clkena;extclkena;scanclk;scanaclr""
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC ""1""
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING ""1""
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING ""0""
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC ""1""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING ""scandata;scanread;scanwrite;clk;extclk""
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC ""1""
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING ""1""
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING ""0""
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING ""512.000""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING ""clkbad;activeclock;locked;clkloss;scandataout""
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING ""KHz""
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING ""0""
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING ""64.000""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING ""scandone;sclkout1;sclkout0;enable0;enable1""
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING ""0""
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING ""1""
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING ""100.000""
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING ""inclk0""
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING ""0""
+// Retrieval info: PRIVATE: DEV_FAMILY STRING ""Cyclone""
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING ""100.000""
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC ""1""
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING ""Low""
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING ""0""
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING ""deg""
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING ""0""
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING ""deg""
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING ""0""
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC ""11""
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC ""1""
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING ""0""
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC ""50""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""altpll""
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC ""1""
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC ""15625""
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC ""1""
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC ""50""
+// Retrieval info: CONSTANT: PLL_TYPE STRING ""AUTO""
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC ""2""
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING ""0""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: OPERATION_MODE STRING ""NORMAL""
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING ""CLK0""
+// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING ""0""
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING ""0""
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC ""c0""
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC ""@clk[5..0]""
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC ""c1""
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND ""inclk0""
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC ""@extclk[3..0]""
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dspclkpll_bb.v TRUE FALSE
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
+   parameter bw = 16;
+   parameter N = 4;
+   parameter log2_of_max_rate = 7;
+   parameter maxbitgain = (N-1)*log2_of_max_rate;
+   
+   input clock;
+   input reset;
+   input enable;
+   input [7:0] rate;
+   input strobe_in,strobe_out;\t
+   input [bw-1:0] signal_in;
+   wire [bw-1:0] \tsignal_in;
+   output [bw-1:0] signal_out;
+   wire [bw-1:0]   signal_out;
+
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg [bw+maxbitgain-1:0] integrator [0:N-1];
+   reg [bw+maxbitgain-1:0] differentiator [0:N-1];
+   reg [bw+maxbitgain-1:0] pipeline [0:N-1];
+
+   integer i;
+
+   sign_extend #(bw,bw+maxbitgain) 
+      ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   //FIXME Note that this section has pipe and diff reversed
+   // It still works, but is confusing
+   always @(posedge clock)
+     if(reset)
+       for(i=0;i<N;i=i+1)
+\t integrator[i] <= #1 0;
+     else if (enable & strobe_out)
+       begin
+\t  if(strobe_in)
+\t    integrator[0] <= #1 integrator[0] + pipeline[N-1];
+\t  for(i=1;i<N;i=i+1)
+\t    integrator[i] <= #1 integrator[i] + integrator[i-1];
+       end
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+\t  for(i=0;i<N;i=i+1)
+\t    begin
+\t       differentiator[i] <= #1 0;
+\t       pipeline[i] <= #1 0;
+ \t    end
+       end
+     else if (enable && strobe_in)
+       begin
+\t  differentiator[0] <= #1 signal_in_ext;
+\t  pipeline[0] <= #1 signal_in_ext - differentiator[0];
+\t  for(i=1;i<N;i=i+1)
+\t    begin
+\t       differentiator[i] <= #1 pipeline[i-1];
+\t       pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
+\t    end
+       end
+   
+   wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
+
+   cic_int_shifter #(bw)
+\tcic_int_shifter(rate,signal_out_unnorm,signal_out);
+   
+endmodule // cic_interp
+
+"
+"
+
+module ram64 (input clock, input write, 
+\t      input [5:0] wr_addr, input [15:0] wr_data,
+\t      input [5:0] rd_addr, output reg [15:0] rd_data);
+
+   reg [15:0] \t\tram_array [0:63];
+
+   always @(posedge clock)
+     rd_data <= #1 ram_array[rd_addr];
+
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram64
+"
+"
+
+module rssi (input clock, input reset, input enable,
+\t     input [11:0] adc, output [15:0] rssi, output [15:0] over_count);
+
+   wire \t\t  over_hi = (adc == 12'h7FF);
+   wire \t\t  over_lo = (adc == 12'h800);
+   wire \t\t  over = over_hi | over_lo;
+
+   reg [25:0] \t\t  over_count_int;
+   always @(posedge clock)
+     if(reset | ~enable)
+       over_count_int <= #1 26'd0;
+     else
+       over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10];
+   
+   assign      over_count = over_count_int[25:10];
+   
+   wire [11:0] abs_adc = adc[11] ? ~adc : adc;
+
+   reg [25:0]  rssi_int;
+   always @(posedge clock)
+     if(reset | ~enable)
+       rssi_int <= #1 26'd0;
+     else
+       rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
+
+   assign      rssi = rssi_int[25:10];
+   
+endmodule // rssi
+"
+"// Model of FIFO in Altera
+
+module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+\t\t    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+   parameter width = 32;
+   parameter depth = 1024;
+   //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
+      
+   input [31:0] data;
+   input \twrreq;
+   input \trdreq;
+   input \trdclk;
+   input \twrclk;
+   input \taclr;
+   output [31:0] q;
+   output \t rdfull;
+   output \t rdempty;
+   output [9:0]  rdusedw;
+   output \t wrfull;
+   output \t wrempty;
+   output [9:0]  wrusedw;
+   
+   reg [width-1:0] mem [0:depth-1];
+   reg [7:0] \t   rdptr;
+   reg [7:0] \t   wrptr;
+   
+`ifdef rd_req
+   reg [width-1:0] q;
+`else
+   wire [width-1:0] q;
+`endif
+   
+   reg [9:0] \t    rdusedw;
+   reg [9:0] \t    wrusedw;
+   
+   integer \t    i;
+
+   always @( aclr)
+     begin
+\twrptr <= #1 0;
+\trdptr <= #1 0;
+\tfor(i=0;i<depth;i=i+1)
+\t  mem[i] <= #1 0;
+     end
+   
+   always @(posedge wrclk)
+     if(wrreq)
+       begin
+\t  wrptr <= #1 wrptr+1;
+\t  mem[wrptr] <= #1 data;
+       end
+   
+   always @(posedge rdclk)
+     if(rdreq)
+       begin
+   \t  rdptr <= #1 rdptr+1;
+`ifdef rd_req
+\t  q <= #1 mem[rdptr];
+`endif
+       end
+   
+`ifdef rd_req
+`else
+   assign q = mem[rdptr];
+`endif
+   
+   // Fix these
+   always @(posedge wrclk)
+     wrusedw <= #1 wrptr - rdptr;
+   
+   always @(posedge rdclk)
+     rdusedw <= #1 wrptr - rdptr;
+
+   assign wrempty = (wrusedw == 0);
+   assign wrfull = (wrusedw == depth-1);
+
+   assign rdempty = (rdusedw == 0);
+   assign rdfull = (rdusedw == depth-1);
+   
+endmodule // fifo_1c_1k
+"
+"pll\tpll_inst (
+\t.inclk0 ( inclk0_sig ),
+\t.c0 ( c0_sig )
+\t);
+"
+"
+
+module ram32 (input clock, input write, 
+\t      input [4:0] wr_addr, input [15:0] wr_data,
+\t      input [4:0] rd_addr, output reg [15:0] rd_data);
+
+   reg [15:0] \t\tram_array [0:31];
+
+   always @(posedge clock)
+     rd_data <= #1 ram_array[rd_addr];
+
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram32
+
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+ 
+// Vendor Independent FIFO module
+// Width and Depth should be parameterizable
+// Asynchronous clocks for each side
+// Read side is read-acknowledge, not read-request
+// FIFO does not enforce ""don\'t write when full, don\'t read when empty""
+// That is up to the connecting modules
+// The FIFO only holds 2^N-1 entries, not 2^N
+
+module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
+   parameter width=32;
+   parameter depth=10;
+
+   input reset;  // Asynchronous
+   input [width-1:0] data;
+   input write;
+   input wrclk;
+   output [depth-1:0] wr_used;
+   output [width-1:0] q;
+   input read_ack;
+   input rdclk;
+   output [depth-1:0] rd_used;
+
+   reg [depth-1:0] read_addr, write_addr, 
+\t\t   read_addr_gray, read_addr_gray_sync,
+\t\t   write_addr_gray, write_addr_gray_sync;
+
+   // Pseudo-dual-port RAM
+   dpram #(.depth(10),.width(width),.size(1024))
+         fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
+\t\t   .rclk(rdclk), .rdata(q),.raddr(read_addr) );
+
+   wire [depth-1:0] wag,rag;
+
+   // Keep track of own side\'s pointer
+   always @(posedge wrclk or posedge reset)
+     if(reset) write_addr <= #1 0;
+     else if(write) write_addr <= #1 write_addr + 1;
+
+   always @(posedge rdclk or posedge reset)
+     if(reset) read_addr <= #1 0;
+     else if(read_ack) read_addr <= #1 read_addr + 1;
+
+   // Convert own side pointer to gray
+   bin2gray #(depth) write_b2g (write_addr,wag);
+   bin2gray #(depth) read_b2g (read_addr,rag);
+
+   // Latch it
+   always @(posedge wrclk or posedge reset)
+     if(reset) write_addr_gray <= #1 0;
+     else write_addr_gray <= #1 wag;
+
+   always @(posedge rdclk or posedge reset)
+     if(reset) read_addr_gray <= #1 0;
+     else read_addr_gray <= #1 rag;
+
+   // Send it to other side and latch
+   always @(posedge wrclk or posedge reset)
+     if(reset) read_addr_gray_sync <= #1 0;
+     else read_addr_gray_sync <= #1 read_addr_gray;
+
+   always @(posedge rdclk or posedge reset)
+     if(reset) write_addr_gray_sync <= #1 0;
+     else write_addr_gray_sync <= #1 write_addr_gray;
+
+   wire [depth-1:0] write_addr_sync, read_addr_sync;
+   
+   // Convert back to binary
+   gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
+   gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
+ 
+   assign rd_used = write_addr_sync - read_addr;
+   assign wr_used = write_addr - read_addr_sync;
+   \t\t  
+endmodule // fifo
+
+module bin2gray(bin_val,gray_val);
+   parameter width = 8;
+   input [width-1:0] bin_val;
+   output reg [width-1:0] gray_val;
+   
+   integer i;
+
+   always @*
+     begin
+\tgray_val[width-1] = bin_val[width-1];
+\tfor(i=0;i<width-1;i=i+1)
+\t  gray_val[i] = bin_val[i] ^ bin_val[i+1];
+     end
+endmodule // bin2gray
+
+module gray2bin(gray_val,bin_val);
+   parameter width = 8;
+   input [width-1:0] gray_val;
+   output reg [width-1:0] bin_val;
+
+   integer i;
+   
+   always @*
+     begin
+\tbin_val[width-1] = gray_val[width-1];
+\tfor(i=width-2;i>=0;i=i-1)
+\t  bin_val[i] = bin_val[i+1] ^ gray_val[i];
+     end
+endmodule // gray2bin
+"
+"// megafunction wizard: %LPM_ADD_SUB%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub 
+
+// ============================================================
+// File Name: addsub16.v
+// Megafunction Name(s):
+// \t\t\tlpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result
+//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
+
+//synthesis_resources = lut 17 
+module  addsub16_add_sub_gp9
+\t( 
+\taclr,
+\tadd_sub,
+\tclken,
+\tclock,
+\tdataa,
+\tdatab,
+\tresult) /* synthesis synthesis_clearbox=1 */;
+\tinput   aclr;
+\tinput   add_sub;
+\tinput   clken;
+\tinput   clock;
+\tinput   [15:0]  dataa;
+\tinput   [15:0]  datab;
+\toutput   [15:0]  result;
+
+\twire  [0:0]   wire_add_sub_cella_0cout;
+\twire  [0:0]   wire_add_sub_cella_1cout;
+\twire  [0:0]   wire_add_sub_cella_2cout;
+\twire  [0:0]   wire_add_sub_cella_3cout;
+\twire  [0:0]   wire_add_sub_cella_4cout;
+\twire  [0:0]   wire_add_sub_cella_5cout;
+\twire  [0:0]   wire_add_sub_cella_6cout;
+\twire  [0:0]   wire_add_sub_cella_7cout;
+\twire  [0:0]   wire_add_sub_cella_8cout;
+\twire  [0:0]   wire_add_sub_cella_9cout;
+\twire  [0:0]   wire_add_sub_cella_10cout;
+\twire  [0:0]   wire_add_sub_cella_11cout;
+\twire  [0:0]   wire_add_sub_cella_12cout;
+\twire  [0:0]   wire_add_sub_cella_13cout;
+\twire  [0:0]   wire_add_sub_cella_14cout;
+\twire  [15:0]   wire_add_sub_cella_dataa;
+\twire  [15:0]   wire_add_sub_cella_datab;
+\twire  [15:0]   wire_add_sub_cella_regout;
+\twire  wire_strx_lcell1_cout;
+
+\tstratix_lcell   add_sub_cella_0
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_strx_lcell1_cout),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_0cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[0:0]),
+\t.datab(wire_add_sub_cella_datab[0:0]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[0:0]));
+\tdefparam
+\t\tadd_sub_cella_0.cin_used = ""true"",
+\t\tadd_sub_cella_0.lut_mask = ""96e8"",
+\t\tadd_sub_cella_0.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_0.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_0.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_1
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_0cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_1cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[1:1]),
+\t.datab(wire_add_sub_cella_datab[1:1]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[1:1]));
+\tdefparam
+\t\tadd_sub_cella_1.cin_used = ""true"",
+\t\tadd_sub_cella_1.lut_mask = ""96e8"",
+\t\tadd_sub_cella_1.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_1.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_1.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_2
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_1cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_2cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[2:2]),
+\t.datab(wire_add_sub_cella_datab[2:2]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[2:2]));
+\tdefparam
+\t\tadd_sub_cella_2.cin_used = ""true"",
+\t\tadd_sub_cella_2.lut_mask = ""96e8"",
+\t\tadd_sub_cella_2.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_2.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_2.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_3
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_2cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_3cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[3:3]),
+\t.datab(wire_add_sub_cella_datab[3:3]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[3:3]));
+\tdefparam
+\t\tadd_sub_cella_3.cin_used = ""true"",
+\t\tadd_sub_cella_3.lut_mask = ""96e8"",
+\t\tadd_sub_cella_3.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_3.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_3.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_4
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_3cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_4cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[4:4]),
+\t.datab(wire_add_sub_cella_datab[4:4]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[4:4]));
+\tdefparam
+\t\tadd_sub_cella_4.cin_used = ""true"",
+\t\tadd_sub_cella_4.lut_mask = ""96e8"",
+\t\tadd_sub_cella_4.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_4.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_4.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_5
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_4cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_5cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[5:5]),
+\t.datab(wire_add_sub_cella_datab[5:5]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[5:5]));
+\tdefparam
+\t\tadd_sub_cella_5.cin_used = ""true"",
+\t\tadd_sub_cella_5.lut_mask = ""96e8"",
+\t\tadd_sub_cella_5.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_5.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_5.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_6
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_5cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_6cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[6:6]),
+\t.datab(wire_add_sub_cella_datab[6:6]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[6:6]));
+\tdefparam
+\t\tadd_sub_cella_6.cin_used = ""true"",
+\t\tadd_sub_cella_6.lut_mask = ""96e8"",
+\t\tadd_sub_cella_6.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_6.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_6.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_7
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_6cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_7cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[7:7]),
+\t.datab(wire_add_sub_cella_datab[7:7]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[7:7]));
+\tdefparam
+\t\tadd_sub_cella_7.cin_used = ""true"",
+\t\tadd_sub_cella_7.lut_mask = ""96e8"",
+\t\tadd_sub_cella_7.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_7.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_7.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_8
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_7cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_8cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[8:8]),
+\t.datab(wire_add_sub_cella_datab[8:8]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[8:8]));
+\tdefparam
+\t\tadd_sub_cella_8.cin_used = ""true"",
+\t\tadd_sub_cella_8.lut_mask = ""96e8"",
+\t\tadd_sub_cella_8.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_8.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_8.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_9
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_8cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_9cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[9:9]),
+\t.datab(wire_add_sub_cella_datab[9:9]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[9:9]));
+\tdefparam
+\t\tadd_sub_cella_9.cin_used = ""true"",
+\t\tadd_sub_cella_9.lut_mask = ""96e8"",
+\t\tadd_sub_cella_9.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_9.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_9.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_10
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_9cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_10cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[10:10]),
+\t.datab(wire_add_sub_cella_datab[10:10]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[10:10]));
+\tdefparam
+\t\tadd_sub_cella_10.cin_used = ""true"",
+\t\tadd_sub_cella_10.lut_mask = ""96e8"",
+\t\tadd_sub_cella_10.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_10.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_10.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_11
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_10cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_11cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[11:11]),
+\t.datab(wire_add_sub_cella_datab[11:11]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[11:11]));
+\tdefparam
+\t\tadd_sub_cella_11.cin_used = ""true"",
+\t\tadd_sub_cella_11.lut_mask = ""96e8"",
+\t\tadd_sub_cella_11.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_11.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_11.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_12
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_11cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_12cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[12:12]),
+\t.datab(wire_add_sub_cella_datab[12:12]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[12:12]));
+\tdefparam
+\t\tadd_sub_cella_12.cin_used = ""true"",
+\t\tadd_sub_cella_12.lut_mask = ""96e8"",
+\t\tadd_sub_cella_12.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_12.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_12.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_13
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_12cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_13cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[13:13]),
+\t.datab(wire_add_sub_cella_datab[13:13]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[13:13]));
+\tdefparam
+\t\tadd_sub_cella_13.cin_used = ""true"",
+\t\tadd_sub_cella_13.lut_mask = ""96e8"",
+\t\tadd_sub_cella_13.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_13.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_13.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_14
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_13cout[0:0]),
+\t.clk(clock),
+\t.cout(wire_add_sub_cella_14cout[0:0]),
+\t.dataa(wire_add_sub_cella_dataa[14:14]),
+\t.datab(wire_add_sub_cella_datab[14:14]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[14:14]));
+\tdefparam
+\t\tadd_sub_cella_14.cin_used = ""true"",
+\t\tadd_sub_cella_14.lut_mask = ""96e8"",
+\t\tadd_sub_cella_14.operation_mode = ""arithmetic"",
+\t\tadd_sub_cella_14.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_14.lpm_type = ""stratix_lcell"";
+\tstratix_lcell   add_sub_cella_15
+\t( 
+\t.aclr(aclr),
+\t.cin(wire_add_sub_cella_14cout[0:0]),
+\t.clk(clock),
+\t.dataa(wire_add_sub_cella_dataa[15:15]),
+\t.datab(wire_add_sub_cella_datab[15:15]),
+\t.ena(clken),
+\t.inverta((~ add_sub)),
+\t.regout(wire_add_sub_cella_regout[15:15]));
+\tdefparam
+\t\tadd_sub_cella_15.cin_used = ""true"",
+\t\tadd_sub_cella_15.lut_mask = ""9696"",
+\t\tadd_sub_cella_15.operation_mode = ""normal"",
+\t\tadd_sub_cella_15.sum_lutc_input = ""cin"",
+\t\tadd_sub_cella_15.lpm_type = ""stratix_lcell"";
+\tassign
+\t\twire_add_sub_cella_dataa = datab,
+\t\twire_add_sub_cella_datab = dataa;
+\tstratix_lcell   strx_lcell1
+\t( 
+\t.cout(wire_strx_lcell1_cout),
+\t.dataa(1\'b0),
+\t.datab((~ add_sub)),
+\t.inverta((~ add_sub)));
+\tdefparam
+\t\tstrx_lcell1.cin_used = ""false"",
+\t\tstrx_lcell1.lut_mask = ""00cc"",
+\t\tstrx_lcell1.operation_mode = ""arithmetic"",
+\t\tstrx_lcell1.lpm_type = ""stratix_lcell"";
+\tassign
+\t\tresult = wire_add_sub_cella_regout;
+endmodule //addsub16_add_sub_gp9
+//VALID FILE
+
+
+module addsub16 (
+\tadd_sub,
+\tdataa,
+\tdatab,
+\tclock,
+\taclr,
+\tclken,
+\tresult)/* synthesis synthesis_clearbox = 1 */;
+
+\tinput\t  add_sub;
+\tinput\t[15:0]  dataa;
+\tinput\t[15:0]  datab;
+\tinput\t  clock;
+\tinput\t  aclr;
+\tinput\t  clken;
+\toutput\t[15:0]  result;
+
+\twire [15:0] sub_wire0;
+\twire [15:0] result = sub_wire0[15:0];
+
+\taddsub16_add_sub_gp9\taddsub16_add_sub_gp9_component (
+\t\t\t\t.dataa (dataa),
+\t\t\t\t.add_sub (add_sub),
+\t\t\t\t.datab (datab),
+\t\t\t\t.clken (clken),
+\t\t\t\t.aclr (aclr),
+\t\t\t\t.clock (clock),
+\t\t\t\t.result (sub_wire0));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC ""16""
+// Retrieval info: PRIVATE: Function NUMERIC ""2""
+// Retrieval info: PRIVATE: WhichConstant NUMERIC ""0""
+// Retrieval info: PRIVATE: ConstantA NUMERIC ""0""
+// Retrieval info: PRIVATE: ConstantB NUMERIC ""0""
+// Retrieval info: PRIVATE: ValidCtA NUMERIC ""0""
+// Retrieval info: PRIVATE: ValidCtB NUMERIC ""0""
+// Retrieval info: PRIVATE: CarryIn NUMERIC ""0""
+// Retrieval info: PRIVATE: CarryOut NUMERIC ""0""
+// Retrieval info: PRIVATE: Overflow NUMERIC ""0""
+// Retrieval info: PRIVATE: Latency NUMERIC ""1""
+// Retrieval info: PRIVATE: aclr NUMERIC ""1""
+// Retrieval info: PRIVATE: clken NUMERIC ""1""
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC ""1""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING ""UNUSED""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""LPM_ADD_SUB""
+// Retrieval info: CONSTANT: LPM_HINT STRING ""ONE_INPUT_IS_CONSTANT=NO""
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC ""1""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
+// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
+// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
+// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
+// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+"
+"// megafunction wizard: %LPM_ADD_SUB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_add_sub 
+
+// ============================================================
+// File Name: mylpm_addsub.v
+// Megafunction Name(s):
+// \t\t\tlpm_add_sub
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+module mylpm_addsub (
+\tadd_sub,
+\tdataa,
+\tdatab,
+\tclock,
+\tresult);
+
+\tinput\t  add_sub;
+\tinput\t[15:0]  dataa;
+\tinput\t[15:0]  datab;
+\tinput\t  clock;
+\toutput\t[15:0]  result;
+
+\twire [15:0] sub_wire0;
+\twire [15:0] result = sub_wire0[15:0];
+
+\tlpm_add_sub\tlpm_add_sub_component (
+\t\t\t\t.dataa (dataa),
+\t\t\t\t.add_sub (add_sub),
+\t\t\t\t.datab (datab),
+\t\t\t\t.clock (clock),
+\t\t\t\t.result (sub_wire0));
+\tdefparam
+\t\tlpm_add_sub_component.lpm_width = 16,
+\t\tlpm_add_sub_component.lpm_direction = ""UNUSED"",
+\t\tlpm_add_sub_component.lpm_type = ""LPM_ADD_SUB"",
+\t\tlpm_add_sub_component.lpm_hint = ""ONE_INPUT_IS_CONSTANT=NO"",
+\t\tlpm_add_sub_component.lpm_pipeline = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: nBit NUMERIC ""16""
+// Retrieval info: PRIVATE: Function NUMERIC ""2""
+// Retrieval info: PRIVATE: WhichConstant NUMERIC ""0""
+// Retrieval info: PRIVATE: ConstantA NUMERIC ""0""
+// Retrieval info: PRIVATE: ConstantB NUMERIC ""0""
+// Retrieval info: PRIVATE: ValidCtA NUMERIC ""0""
+// Retrieval info: PRIVATE: ValidCtB NUMERIC ""0""
+// Retrieval info: PRIVATE: CarryIn NUMERIC ""0""
+// Retrieval info: PRIVATE: CarryOut NUMERIC ""0""
+// Retrieval info: PRIVATE: Overflow NUMERIC ""0""
+// Retrieval info: PRIVATE: Latency NUMERIC ""1""
+// Retrieval info: PRIVATE: aclr NUMERIC ""0""
+// Retrieval info: PRIVATE: clken NUMERIC ""0""
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC ""1""
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""16""
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING ""UNUSED""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""LPM_ADD_SUB""
+// Retrieval info: CONSTANT: LPM_HINT STRING ""ONE_INPUT_IS_CONSTANT=NO""
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC ""1""
+// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
+// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
+// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
+// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+"
+"//`include ""../../firmware/include/fpga_regs_common.v""
+//`include ""../../firmware/include/fpga_regs_standard.v""
+module rx_buffer_inband
+  ( input usbclk,
+    input bus_reset,
+    input reset,  // DSP side reset (used here), do not reset registers
+    input reset_regs, //Only reset registers
+    output [15:0] usbdata,
+    input RD,
+    output wire have_pkt_rdy,
+    output reg rx_overrun,
+    input wire [3:0] channels,
+    input wire [15:0] ch_0,
+    input wire [15:0] ch_1,
+    input wire [15:0] ch_2,
+    input wire [15:0] ch_3,
+    input wire [15:0] ch_4,
+    input wire [15:0] ch_5,
+    input wire [15:0] ch_6,
+    input wire [15:0] ch_7,
+    input rxclk,
+    input rxstrobe,
+    input clear_status,
+    input [6:0] serial_addr, 
+    input [31:0] serial_data, 
+    input serial_strobe,
+    output wire [15:0] debugbus,
+\t
+    //Connection with tx_inband
+    input rx_WR,
+    input [15:0] rx_databus,
+    input rx_WR_done,
+    output reg rx_WR_enabled,
+    //signal strength
+    input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+    input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+    input wire [1:0] tx_underrun
+    );
+    
+    parameter NUM_CHAN =1;
+    genvar i ;
+    
+    // FX2 Bug Fix
+    reg [8:0] read_count;
+    always @(negedge usbclk)
+        if(bus_reset)
+            read_count <= #1 9\'d0;
+        else if(RD & ~read_count[8])
+            read_count <= #1 read_count + 9\'d1;
+        else
+            read_count <= #1 RD ? read_count : 9\'b0;
+       
+\t// Time counter
+\treg [31:0] adctime;
+\talways @(posedge rxclk)
+\t\tif (reset)
+\t\t\tadctime <= 0;
+\t\telse if (rxstrobe)
+\t\t\tadctime <= adctime + 1;
+     
+  // USB side fifo
+  wire [11:0] rdusedw;
+  wire [11:0] wrusedw;
+  wire [15:0] fifodata;
+  wire [15:0] fifodata_il;
+  reg [15:0] fifodata_16;
+  wire WR;
+  wire have_space;
+
+  assign fifodata_il = fifodata_16;
+
+  fifo_4kx16_dc\trx_usb_fifo (
+    .aclr ( reset ),
+    .data ( fifodata ),
+    .rdclk ( ~usbclk ),
+    .rdreq ( RD & ~read_count[8] ),
+    .wrclk ( rxclk ),
+    .wrreq ( WR ),
+    .q ( usbdata ),
+    .rdempty (  ),
+    .rdusedw ( rdusedw ),
+    .wrfull (  ),
+    .wrusedw ( wrusedw ) );
+    
+  assign have_pkt_rdy = (rdusedw >= 12\'d256);
+  assign have_space = (wrusedw < 12\'d760);
+\t 
+  // Rx side fifos
+  wire chan_rdreq;
+  wire [15:0] chan_fifodata;
+  wire [9:0] chan_usedw;
+  wire [NUM_CHAN:0] chan_empty;
+  wire [3:0] rd_select;
+  wire [NUM_CHAN:0] rx_full;
+  wire [7:0] debug;\t 
+  packet_builder #(NUM_CHAN) rx_pkt_builer (
+    .rxclk ( rxclk ),
+    .reset ( reset ),
+    .adctime ( adctime ),
+    .channels ( 4\'d1 ), //need to be tested and changed to channels 
+    .chan_rdreq ( chan_rdreq ),
+    .chan_fifodata ( chan_fifodata ),
+    .chan_empty ( chan_empty ),
+    .rd_select ( rd_select ),
+    .chan_usedw ( chan_usedw ),
+    .WR ( WR ),
+    .fifodata ( fifodata ),
+    .have_space ( have_space ),
+      .rssi_0(rssi_0), .rssi_1(rssi_1),
+      .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+      .underrun(tx_underrun));
+\t 
+  // Detect overrun
+  always @(posedge rxclk)
+    if(reset)
+      rx_overrun <= 1\'b0;
+    else if(rx_full[0])
+      rx_overrun <= 1\'b1;
+    else if(clear_status)
+      rx_overrun <= 1\'b0;
+
+\t\t
+  // TODO write this genericly
+  //wire [15:0]ch[NUM_CHAN:0];
+  //assign ch[0] = ch_0;
+\t
+  wire cmd_empty;
+\t
+  always @(posedge rxclk)
+    if(reset)
+      rx_WR_enabled <= 1;
+    else if(cmd_empty)
+      rx_WR_enabled <= 1;
+    else if(rx_WR_done)
+      rx_WR_enabled <= 0;
+
+  // Switching of channels
+  reg [3:0] store_next;
+  always @(posedge rxclk)
+  if(reset)
+    store_next <= #1 4\'d0;
+  else if(rxstrobe & (store_next == 0))
+    store_next <= #1 4\'d1;
+  else if(~rx_full & (store_next == 4\'d2))
+    store_next <= #1 4\'d0;
+  else if(~rx_full & (store_next != 0))
+    store_next <= #1 store_next + 4\'d1;
+
+  always @*
+    case(store_next)
+      4\'d1 : fifodata_16 = ch_0;
+      4\'d2 : fifodata_16 = ch_1;
+      default: fifodata_16 = 16\'hFFFF;
+    endcase
+
+  wire [15:0] dataout [0:NUM_CHAN];
+  wire [9:0]  usedw\t[0:NUM_CHAN];
+  wire empty[0:NUM_CHAN];
+\t
+  generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+    begin : generate_channel_fifos
+
+      wire rdreq;
+
+      assign rdreq = (rd_select == i) & chan_rdreq;
+
+      fifo_1kx16 rx_chan_fifo (
+      .aclr ( reset ),
+      .clock ( rxclk ),
+      .data ( fifodata_il ),
+      .rdreq ( rdreq ),
+      .wrreq ( ~rx_full[i] & (store_next != 0)),
+      .empty (empty[i]),
+      .full (rx_full[i]),
+      .q ( dataout[i]),
+      .usedw ( usedw[i]),
+      .almost_empty(chan_empty[i])
+      );
+    end
+  endgenerate
+\t
+  
+\t 
+  fifo_1kx16 rx_cmd_fifo (
+    .aclr ( reset ),
+    .clock ( rxclk ),
+    .data ( rx_databus ),
+    .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+    .wrreq ( rx_WR & rx_WR_enabled),
+    .empty ( cmd_empty),
+    .full ( rx_full[NUM_CHAN] ),
+    .q ( dataout[NUM_CHAN]),
+    .usedw ( usedw[NUM_CHAN] )
+  );
+\t
+  assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+  assign chan_fifodata = dataout[rd_select];
+  assign chan_usedw = usedw[rd_select];
+  assign debugbus = {4\'d0, rxclk, rxstrobe, store_next[3], store_next[1], store_next[0]};
+
+endmodule
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2005,2006 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+`include ""../../firmware/include/fpga_regs_common.v""
+`include ""../../firmware/include/fpga_regs_standard.v""
+
+module io_pins
+  ( inout wire [15:0] io_0, inout wire [15:0] io_1,
+    input wire [15:0] reg_0, input wire [15:0] reg_1, 
+    input clock, input rx_reset, input tx_reset,
+    input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
+   
+   reg [15:0] io_0_oe,io_1_oe;
+   
+   bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
+   bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
+    
+   // Upper 16 bits are mask for lower 16
+   always @(posedge clock)
+     if(serial_strobe)
+       case(serial_addr)
+\t `FR_OE_0 : io_0_oe
+\t   <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+\t `FR_OE_1 : io_1_oe
+\t   <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
+\t   endcase // case(serial_addr)
+
+endmodule // io_pins
+"
+"// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// \t\t\taltpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+//support information,  device programming or simulation file,  and any other
+//associated  documentation or information  provided by  Altera  or a partner
+//under  Altera\'s   Megafunction   Partnership   Program  may  be  used  only
+//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+//other  use  of such  megafunction  design,  netlist,  support  information,
+//device programming or simulation file,  or any other  related documentation
+//or information  is prohibited  for  any  other purpose,  including, but not
+//limited to  modification,  reverse engineering,  de-compiling, or use  with
+//any other  silicon devices,  unless such use is  explicitly  licensed under
+//a separate agreement with  Altera  or a megafunction partner.  Title to the
+//intellectual property,  including patents,  copyrights,  trademarks,  trade
+//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+//support  information,  device programming or simulation file,  or any other
+//related documentation or information provided by  Altera  or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party\'s intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+\tinclk0,
+\tc0);
+
+\tinput\t  inclk0;
+\toutput\t  c0;
+
+\twire [5:0] sub_wire0;
+\twire [0:0] sub_wire4 = 1\'h0;
+\twire [0:0] sub_wire1 = sub_wire0[0:0];
+\twire  c0 = sub_wire1;
+\twire  sub_wire2 = inclk0;
+\twire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+\taltpll\taltpll_component (
+\t\t\t\t.inclk (sub_wire3),
+\t\t\t\t.clk (sub_wire0)
+\t\t\t\t// synopsys translate_off
+,
+\t\t\t\t.fbin (),
+\t\t\t\t.pllena (),
+\t\t\t\t.clkswitch (),
+\t\t\t\t.areset (),
+\t\t\t\t.pfdena (),
+\t\t\t\t.clkena (),
+\t\t\t\t.extclkena (),
+\t\t\t\t.scanclk (),
+\t\t\t\t.scanaclr (),
+\t\t\t\t.scandata (),
+\t\t\t\t.scanread (),
+\t\t\t\t.scanwrite (),
+\t\t\t\t.extclk (),
+\t\t\t\t.clkbad (),
+\t\t\t\t.activeclock (),
+\t\t\t\t.locked (),
+\t\t\t\t.clkloss (),
+\t\t\t\t.scandataout (),
+\t\t\t\t.scandone (),
+\t\t\t\t.sclkout1 (),
+\t\t\t\t.sclkout0 (),
+\t\t\t\t.enable0 (),
+\t\t\t\t.enable1 ()
+\t\t\t\t// synopsys translate_on
+
+);
+\tdefparam
+\t\taltpll_component.clk0_duty_cycle = 50,
+\t\taltpll_component.lpm_type = ""altpll"",
+\t\taltpll_component.clk0_multiply_by = 1,
+\t\taltpll_component.inclk0_input_frequency = 20833,
+\t\taltpll_component.clk0_divide_by = 1,
+\t\taltpll_component.pll_type = ""AUTO"",
+\t\taltpll_component.clk0_time_delay = ""0"",
+\t\taltpll_component.intended_device_family = ""Cyclone"",
+\t\taltpll_component.operation_mode = ""NORMAL"",
+\t\taltpll_component.compensate_clock = ""CLK0"",
+\t\taltpll_component.clk0_phase_shift = ""-3000"";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING ""0""
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING ""ns""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING ""MHz""
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING ""MHz""
+// Retrieval info: PRIVATE: SPREAD_USE STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC ""1048575""
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING ""0""
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING ""50.00000000""
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING ""-3.00000000""
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC ""1""
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING ""0.500""
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING ""0""
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING ""0""
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING ""0.00000000""
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING ""1""
+// Retrieval info: PRIVATE: BANDWIDTH STRING ""1.000""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING ""0""
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING ""8""
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING ""50.000""
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING ""1""
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC ""0""
+// Retrieval info: PRIVATE: USE_CLK0 STRING ""1""
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING ""0""
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING ""0""
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING ""0""
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING ""100.000""
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING ""c0""
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING ""MHz""
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING ""MHz""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING ""inclk;fbin;pllena;clkswitch;areset""
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING ""0""
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING ""1""
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING ""e0""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING ""pfdena;clkena;extclkena;scanclk;scanaclr""
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC ""1""
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING ""1""
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING ""1""
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING ""0""
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC ""1""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING ""scandata;scanread;scanwrite;clk;extclk""
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING ""1""
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING ""0""
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING ""528.000""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING ""clkbad;activeclock;locked;clkloss;scandataout""
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING ""KHz""
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING ""0""
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING ""48.000""
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING ""scandone;sclkout1;sclkout0;enable0;enable1""
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING ""0""
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING ""1""
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING ""100.000""
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING ""inclk0""
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING ""0""
+// Retrieval info: PRIVATE: DEV_FAMILY STRING ""Cyclone""
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING ""0""
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC ""1""
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING ""Low""
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING ""0""
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING ""0""
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING ""deg""
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING ""0""
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING ""0""
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC ""0""
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC ""11""
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC ""50""
+// Retrieval info: CONSTANT: LPM_TYPE STRING ""altpll""
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC ""1""
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC ""20833""
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC ""1""
+// Retrieval info: CONSTANT: PLL_TYPE STRING ""AUTO""
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING ""0""
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone""
+// Retrieval info: CONSTANT: OPERATION_MODE STRING ""NORMAL""
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING ""CLK0""
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING ""-3000""
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC ""c0""
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC ""@clk[5..0]""
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND ""inclk0""
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC ""@extclk[3..0]""
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE
+"
+"
+
+module halfband_interp 
+  (input clock, input reset, input enable,
+   input strobe_in, input strobe_out,
+   input [15:0] signal_in_i, input [15:0] signal_in_q, 
+   output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
+   output wire [12:0] debug);
+   
+   wire [15:0] \tcoeff_ram_out;
+   wire [15:0] \tdata_ram_out_i;
+   wire [15:0] \tdata_ram_out_q;
+
+   wire [3:0] \tdata_rd_addr;
+   reg [3:0] \tdata_wr_addr;
+   reg [2:0] \tcoeff_rd_addr;
+
+   wire \t\tfilt_done;
+   
+   wire [15:0] \tmac_out_i;
+   wire [15:0] \tmac_out_q;
+   reg [15:0] \tdelayed_middle_i, delayed_middle_q;
+   wire [7:0] \tshift = 8'd9;
+
+   reg \t\tstb_out_happened;
+
+   wire [15:0] \tdata_ram_out_i_b;
+   
+   always @(posedge clock)
+     if(strobe_in)
+       stb_out_happened <= #1 1'b0;
+     else if(strobe_out)
+       stb_out_happened <= #1 1'b1;
+   
+assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
+
+   wire [15:0] \tsignal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
+   wire [15:0] \tsignal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
+
+/*   always @(posedge clock)
+     if(reset)
+       begin
+\t  signal_out_i <= #1 16'd0;
+\t  signal_out_q <= #1 16'd0;
+       end
+     else if(strobe_in)
+       begin
+\t  signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
+\t  signal_out_q <= #1 delayed_middle_q;
+       end
+     //else if(filt_done&stb_out_happened)
+     else if(stb_out_happened)
+       begin
+\t  signal_out_i <= #1 mac_out_i;
+\t  signal_out_q <= #1 mac_out_q;
+       end
+*/
+   
+   always @(posedge clock)
+     if(reset)
+       coeff_rd_addr <= #1 3'd0;
+     else if(coeff_rd_addr != 3'd0)
+       coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
+     else if(strobe_in)
+       coeff_rd_addr <= #1 3'd1;
+
+   reg filt_done_d1;
+   always@(posedge clock)
+     filt_done_d1 <= #1 filt_done;
+   
+   always @(posedge clock)
+     if(reset)
+       data_wr_addr <= #1 4'd0;
+   //else if(strobe_in)
+     else if(filt_done & ~filt_done_d1)
+       data_wr_addr <= #1 data_wr_addr + 4'd1;
+
+   always @(posedge clock)
+     if(coeff_rd_addr == 3'd7)
+       begin
+\t  delayed_middle_i <= #1 data_ram_out_i_b;
+\t//  delayed_middle_q <= #1 data_ram_out_q_b;
+       end
+   
+//   always @(posedge clock)
+//     if(reset)
+//       data_rd_addr <= #1 4'd0;
+//     else if(strobe_in)
+//       data_rd_addr <= #1 data_wr_addr + 4'd1;
+//     else if(!filt_done)
+//       data_rd_addr <= #1 data_rd_addr + 4'd1;
+//     else
+//       data_rd_addr <= #1 data_wr_addr;
+  
+   wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
+   wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
+//   always @(posedge clock)
+//     if(reset)
+//       filt_done <= #1 1'b1;
+//     else if(strobe_in)
+ //      filt_done <= #1 1'b0;
+//     else if(coeff_rd_addr == 4'd0)
+//       filt_done <= #1 1'b1;
+
+   assign filt_done = (coeff_rd_addr == 3'd0);
+   
+   coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
+   
+   ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
+\t\t      .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
+   
+   ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
+\t\t      .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
+   
+   mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
+\t      .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
+   
+   mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
+\t      .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
+
+endmodule // halfband_interp
+"
+"module packet_builder #(parameter NUM_CHAN = 1)(
+    // System
+    input rxclk,
+    input reset,
+\t input [31:0] adctime,
+\t input [3:0] channels,
+    // ADC side
+    input [15:0]chan_fifodata,
+    input [NUM_CHAN:0]chan_empty,
+    input [9:0]chan_usedw,
+    output reg [3:0]rd_select,
+    output reg chan_rdreq,
+    // FX2 side
+    output reg WR,
+    output reg [15:0]fifodata,
+    input have_space, 
+    input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
+    input wire [31:0]rssi_3, output wire [7:0] debugbus,
+    input [NUM_CHAN:0] underrun);
+    
+    
+    // States
+    `define IDLE                     3'd0
+    `define HEADER1                  3'd1
+    `define HEADER2                  3'd2
+    `define TIMESTAMP                3'd3
+    `define FORWARD                  3'd4
+\t
+    `define MAXPAYLOAD 504
+    
+    `define PAYLOAD_LEN 8:0
+    `define TAG 12:9
+    `define MBZ 15:13
+    
+    `define CHAN 4:0
+    `define RSSI 10:5
+    `define BURST 12:11
+    `define DROPPED 13
+    `define UNDERRUN 14
+    `define OVERRUN 15
+    
+    reg [NUM_CHAN:0] overrun;
+    reg [2:0] state;
+    reg [8:0] read_length;
+    reg [8:0] payload_len;
+    reg tstamp_complete;
+    reg [3:0] check_next;
+\t
+    wire [31:0] true_rssi;
+    wire [4:0] true_channel;
+    wire ready_to_send;
+
+    assign debugbus = {chan_empty[0], rd_select[0], have_space, 
+                       (chan_usedw >= 10'd504), (chan_usedw ==0),  
+                       ready_to_send, state[1:0]};
+
+    assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
+\t\t\t\t\t\t\t((rd_select[0]) ? rssi_1:rssi_0);
+    assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
+    //assign true_channel = (check_next == NUM_CHAN ? 5'h1f : {1'd0,check_next});
+    assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) || 
+                           ((rd_select == NUM_CHAN)&&(chan_usedw > 0));
+\t\t
+    always @(posedge rxclk)
+    begin
+        if (reset)
+          begin
+            overrun <= 0;
+            WR <= 0;
+            rd_select <= 0;
+            chan_rdreq <= 0;
+            tstamp_complete <= 0;
+            check_next <= 0;
+            state <= `IDLE;
+          end
+        else case (state)
+        `IDLE: begin
+\t\t\tchan_rdreq <= #1 0;
+\t\t\t//check if the channel is full
+\t\t\tif(~chan_empty[check_next])
+\t\t\t\tbegin
+                  if (have_space)
+                      begin
+                        //transmit if the usb buffer have space
+                       //check if we should send
+                       if (ready_to_send)
+                           state <= #1 `HEADER1;
+\t\t\t\t\t\t    
+                       overrun[check_next] <= 0;
+                       end
+                   else
+                      begin
+                      state <= #1 `IDLE;
+                      overrun[check_next] <= 1;
+                      end
+                  rd_select <= #1 check_next;
+                end
+            check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
+            end  //end of `IDLE
+            
+            `HEADER1: begin
+                fifodata[`PAYLOAD_LEN] <= #1 9'd504;
+                payload_len <= #1 9'd504;
+                fifodata[`TAG] <= #1 0;
+                fifodata[`MBZ] <= #1 0;
+                WR <= #1 1;
+                
+                state <= #1 `HEADER2;
+                read_length <= #1 0;
+            end
+            
+            `HEADER2: begin
+                fifodata[`CHAN] <= #1 true_channel;
+                fifodata[`RSSI] <= #1 true_rssi[5:0];
+                fifodata[`BURST] <= #1 0;
+                fifodata[`DROPPED] <= #1 0;
+                fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
+                fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
+                state <= #1 `TIMESTAMP;
+            end
+            
+            `TIMESTAMP: begin
+                fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]);
+                tstamp_complete <= #1 ~tstamp_complete;
+                
+                if (~tstamp_complete)
+                    chan_rdreq <= #1 1;
+                
+                state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
+            end
+            
+            `FORWARD: begin
+                read_length <= #1 read_length + 9'd2;
+                fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
+                
+                if (read_length >= `MAXPAYLOAD)
+                  begin
+                    WR <= #1 0;
+                    state <= #1 `IDLE;
+\t\t\t\t\tchan_rdreq <= #1 0;
+                  end
+                else if (read_length == payload_len - 4)
+                    chan_rdreq <= #1 0;
+            end
+            
+            default: begin
+\t\t\t\t//handling error state
+                state <= `IDLE;
+            end
+            endcase
+    end
+endmodule
+
+"
+"// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+module cic_decim
+  ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
+   parameter bw = 16;
+   parameter N = 4;
+   parameter log2_of_max_rate = 7;
+   parameter maxbitgain = N * log2_of_max_rate;
+   
+   input clock;
+   input reset;
+   input enable;
+   input [7:0] rate;
+   input strobe_in,strobe_out;\t
+   input [bw-1:0] signal_in;
+   output [bw-1:0] signal_out;
+   reg [bw-1:0] signal_out;
+   wire [bw-1:0] signal_out_unreg;
+   
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg [bw+maxbitgain-1:0]  integrator [0:N-1];
+   reg [bw+maxbitgain-1:0] differentiator [0:N-1];
+   reg [bw+maxbitgain-1:0] pipeline [0:N-1];
+   reg [bw+maxbitgain-1:0] sampler;
+   
+   integer i;
+   
+   sign_extend #(bw,bw+maxbitgain) 
+      ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   always @(posedge clock)
+     if(reset)
+       for(i=0;i<N;i=i+1)
+\t integrator[i] <= #1 0;
+     else if (enable && strobe_in)
+       begin
+\t  integrator[0] <= #1 integrator[0] + signal_in_ext;
+\t  for(i=1;i<N;i=i+1)
+\t    integrator[i] <= #1 integrator[i] + integrator[i-1];
+       end\t
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+\t  sampler <= #1 0;
+\t  for(i=0;i<N;i=i+1)
+\t    begin
+\t       pipeline[i] <= #1 0;
+\t       differentiator[i] <= #1 0;
+\t    end
+       end
+     else if (enable && strobe_out)
+       begin
+\t  sampler <= #1 integrator[N-1];
+\t  differentiator[0] <= #1 sampler;
+\t  pipeline[0] <= #1 sampler - differentiator[0];
+\t  for(i=1;i<N;i=i+1)
+\t    begin
+\t       differentiator[i] <= #1 pipeline[i-1];
+\t       pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
+\t    end
+       end // if (enable && strobe_out)
+      
+   wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
+
+   cic_dec_shifter #(bw)
+\tcic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
+
+   always @(posedge clock)
+     signal_out <= #1 signal_out_unreg;
+   
+endmodule // cic_decim
+
+"
+"// File example.v
+//
+// Below is an example of a comment that is mis-parsed by exuberant ctags.
+// It uses the multi-line comment format, i.e. /* ... */ except that in
+// this case, the character sequence immediately preceeding the closing
+// delimiter is an asterisk. (Any even number of asterisks would have the
+// same problem.
+// The line immediately afterwards is used to demonstrate the problem.
+// the module name 'wahoo' isn't recognised, because the parser mistakenly
+// thinks we are still in a multi-line comment.
+/*
+ * I am a multi-line comment
+ * I happen to end in a strange
+ * (but legal) way: **/
+module wahoo ()
+begin
+end
+"
+"/*
+*
+**/
+module top(outsig, insig);
+output outsig;
+input insig;
+assign outsig = insig;
+endmodule
+"
+"/**************************************************************************
+****
+* test task one
+* the line below has 53 asteriks
+*****************************************************/
+task pass_task_1;
+begin
+end
+endtask
+
+/**************************************************************************
+****
+* test task one
+* the line below has 54 asteriks
+******************************************************/
+task fail_task_2;
+begin
+end
+endtask
+
+/**************************************************************************
+****
+* test function one
+* the line below has 53 asteriks
+*****************************************************/
+function pass_func_1;
+begin
+end
+endfunction
+
+/**************************************************************************
+****
+* test function two
+* the line below has 54 asteriks
+******************************************************/
+function fail_func_2;
+begin
+end
+endfunction
+
+/**************************************************************************
+****
+* test function one
+* the line below has 53 asteriks
+*****************************************************/
+`define pass_define_1 1'b1;
+
+/**************************************************************************
+****
+* test function two
+* the line below has 54 asteriks
+******************************************************/
+`define fail_define_2 1'b1;
+"
+"// Taken from http://www.europa.com/~celiac/fsm_samp.html
+
+// These are the symbolic names for states
+parameter  [1:0]       //synopsys enum state_info
+  S0 = 2'h0,
+  S1 = 2'h1,
+  S2 = 2'h2,
+  S3 = 2'h3;
+
+// These are the current state and next state variables
+reg [1:0] /* synopsys enum state_info */ state;
+reg [1:0] /* synopsys enum state_info */ next_state;
+ 
+ 
+// synopsys state_vector state
+
+always @ (state or y or x)
+begin 
+  next_state = state;
+  case (state)                 // synopsys full_case parallel_case
+    S0: begin 
+      if (x) begin 
+        next_state = S1;
+      end
+      else begin 
+
+        next_state = S2;
+      end
+    end
+    S1: begin 
+      if (y) begin 
+        next_state = S2;
+      end
+      else begin 
+        next_state = S0;
+      end
+    end
+    S2: begin 
+      if (x & y) begin 
+        next_state = S3;
+      end
+      else begin 
+        next_state = S0;
+      end
+    end
+    S3: begin 
+      next_state = S0;
+    end
+  endcase
+end
+
+
+always @ (posedge clk or posedge reset)
+begin 
+  if (reset) begin 
+    state <= S0;
+  end
+  else begin 
+    state <= next_state;
+  end
+end
+"
+"// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
+
+// Digital model of a traffic light
+// By Dan Hyde August 10, 1995
+module traffic;
+parameter on = 1, off = 0, red_tics = 35, 
+          amber_tics = 3, green_tics = 20;
+reg clock, red, amber, green;
+
+// will stop the simulation after 1000 time units
+initial begin: stop_at
+   #1000; $stop;    
+end
+
+// initialize the lights and set up monitoring of registers
+initial begin: Init
+    red = off; amber = off; green = off;
+    $display(""                 Time green amber red"");  
+    $monitor(""%3d    %b     %b    %b"", $time, green, amber, red);
+end
+
+// task to wait for \'tics\' positive edge clocks
+// before turning light off
+task light;
+   output color;
+   input [31:0] tics;
+   begin
+      repeat(tics)  // wait to detect tics positive edges on clock
+         @(posedge clock);
+      color = off;
+   end
+endtask
+
+// waveform for clock period of 2 time units
+always begin: clock_wave
+  #1 clock = 0;
+  #1 clock = 1;
+end
+
+always begin: main_process
+   red = on;
+   light(red, red_tics);  // call task to wait 
+   green = on;
+   light(green, green_tics);
+   amber = on;
+   light(amber, amber_tics);
+end
+
+endmodule
+"
+"parameter ramaddr_0 = {1'b1,9'd0};
+"
+"/*
+ * In Verilog, the following two lines are both valid syntax:
+ *
+ * `define GUEST
+ * `define GUEST <value>
+ *
+ * The first defines ""GUEST"" as existing, but with no assigned 
+ * value.  The second defines ""GUEST"" as existing with an 
+ * assigned value.  Ctags55 correctly handles both cases, but 
+ * Ctags551 - Ctags554 only handles the `define with value 
+ * correctly.  Here is some test code to demonstrate this:
+ */
+`define HOSTA
+`define HOSTB
+`define HOSTC
+`define HOSTD
+
+`define GUESTA 1
+`define GUESTB 2
+`define GUESTC 3
+`define GUESTD 4
+/*
+ * Ctags55 correctly generates a tag for all `defines in the 
+ * code, but Ctags554 does not generate tags for ""HOSTB"" 
+ * or ""HOSTD"".
+ */
+"
+"// somewhat contrived, but i came across a real-life file that caused this
+// crash.
+value=
+hello/
+world;
+"
+"/*
+Bugs item #762027, was opened at 2003-06-27 18:32
+Message generated for change (Tracker Item Submitted) made by Item Submitter
+You can respond by visiting: 
+https://sourceforge.net/tracker/?func=detail&atid=106556&aid=762027&group_id=6556
+
+Category: None
+Group: None
+Status: Open
+Resolution: None
+Priority: 5
+Submitted By: cdic (cdic)
+Assigned to: Nobody/Anonymous (nobody)
+Summary: multi-line definition w/o back-slash will be missing
+
+Initial Comment:
+There is a small bug (language verilog):
+*/
+     wire N_84, N_83;     // is ok.
+  
+     wire N_84,
+          N_83;     // then N_83 will be missing in tags.
+/*
+Thanks for fixing it.
+
+cdic
+*/
+"
+"Module Option.
+  Definition bind {A B} (x : option A) (f : A -> option B) : option B :=
+    match x with
+    | Some x => f x
+    | None => None
+    end.
+
+  Definition map {A B} (x : option A) (f : A -> B) : option B :=
+    match x with
+    | Some x => Some (f x)
+    | None => None
+    end.
+
+  Definition default {A} (x : option A) (d : A) : A :=
+    match x with
+    | Some x => x
+    | None => d
+    end.
+End Option.
+
+Module Sum.
+  Definition bind {E A B} (x : A + E) (f : A -> B + E) : B + E :=
+    match x with
+    | inl x => f x
+    | inr e => inr e
+    end.
+
+  Definition map {E A B} (x : A + E) (f : A -> B) : B + E :=
+    match x with
+    | inl x => inl (f x)
+    | inr e => inr e
+    end.
+
+  Definition default {E A} (x : A + E) (d : A) : A :=
+    match x with
+    | inl x => x
+    | inr _ => d
+    end.
+End Sum.
+"
+"/*
+*
+* Copyright (c) 2011 fpgaminer@bitcoin-mining.com
+*
+*
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.  If not, see <http://www.gnu.org/licenses/>.
+* 
+*/
+
+
+`timescale 1ns/1ps
+
+module e0 (x, y);
+
+\tinput [31:0] x;
+\toutput [31:0] y;
+
+\tassign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
+
+endmodule
+
+
+module e1 (x, y);
+
+\tinput [31:0] x;
+\toutput [31:0] y;
+
+\tassign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
+
+endmodule
+
+
+module ch (x, y, z, o);
+
+\tinput [31:0] x, y, z;
+\toutput [31:0] o;
+
+\tassign o = z ^ (x & (y ^ z));
+
+endmodule
+
+
+module maj (x, y, z, o);
+
+\tinput [31:0] x, y, z;
+\toutput [31:0] o;
+
+\tassign o = (x & y) | (z & (x | y));
+
+endmodule
+
+
+module s0 (x, y);
+
+\tinput [31:0] x;
+\toutput [31:0] y;
+
+\tassign y[31:29] = x[6:4] ^ x[17:15];
+\tassign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
+
+endmodule
+
+
+module s1 (x, y);
+
+\tinput [31:0] x;
+\toutput [31:0] y;
+
+\tassign y[31:22] = x[16:7] ^ x[18:9];
+\tassign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
+
+endmodule
+
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    00:47:09 11/17/2015 
+// Design Name: 
+// Module Name:    MPU9250_defines 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+`define MPU9250_RA_WHO_AM_I         8'h75
+`define MPU9250_RA_ACCEL_XOUT_H     8'h3B
+`define MPU9250_RA_ACCEL_XOUT_L     8'h3C
+`define MPU9250_RA_ACCEL_YOUT_H     8'h3D
+`define MPU9250_RA_ACCEL_YOUT_L     8'h3E
+`define MPU9250_RA_ACCEL_ZOUT_H     8'h3F
+`define MPU9250_RA_ACCEL_ZOUT_L     8'h40
+`define MPU9250_RA_TEMP_OUT_H       8'h41
+`define MPU9250_RA_TEMP_OUT_L       8'h42
+`define MPU9250_RA_GYRO_XOUT_H      8'h43
+`define MPU9250_RA_GYRO_XOUT_L      8'h44
+`define MPU9250_RA_GYRO_YOUT_H      8'h45
+`define MPU9250_RA_GYRO_YOUT_L      8'h46
+`define MPU9250_RA_GYRO_ZOUT_H      8'h47
+`define MPU9250_RA_GYRO_ZOUT_L      8'h48
+
+
+//`define MPU9250_RA_SIGNAL_PATH_RESET    8'h68
+//`define MPU9250_RA_MOT_DETECT_CTRL      8'h69
+//`define MPU9250_RA_USER_CTRL        8'h6A
+//`define MPU9250_RA_PWR_MGMT_1       8'h6B
+//`define MPU9250_RA_PWR_MGMT_2       8'h6C
+//`define MPU9250_RA_BANK_SEL         8'h6D
+//`define MPU9250_RA_MEM_START_ADDR   8'h6E
+//`define MPU9250_RA_MEM_R_W          8'h6F
+//`define MPU9250_RA_DMP_CFG_1        8'h70
+//`define MPU9250_RA_DMP_CFG_2        8'h71
+//`define MPU9250_RA_FIFO_COUNTH      8'h72
+//`define MPU9250_RA_FIFO_COUNTL      8'h73
+//`define MPU9250_RA_FIFO_R_W         8'h74
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:41:38 11/11/2015 
+// Design Name: 
+// Module Name:    top 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+`include ""MPU9250_defines2.v""\t\t//macros for MPUaddress
+
+
+module MPU_accel_controller(
+    input clk,
+    input reset,
+\t output reg [15:0] accel_x,\t//accel_x full data
+ \t output reg [15:0] accel_y,\t//accel_y full data 
+ \t output reg [15:0] accel_z,\t//accel_z full data
+
+\toutput SPI_SS_a,\t\t\t\t\t\t//sleve_select
+\toutput SPI_CK_a,\t\t\t\t\t\t//SCLK
+\toutput SPI_DO_a,\t\t\t\t\t\t//Master out Sleve in\t\t\t\t\t
+\tinput SPI_DI_a,\t\t\t\t\t\t//Master in Slave out \t
+\toutput reg arm_read_enable_a
+\t);
+\t
+//for read_coutner
+\tparameter \tSETUP_ACC_X_H = 0,
+\t\t\t\t\tWAIT_ACC_X_H = 1,
+\t\t\t\t\tREAD_ACC_X_H = 2,
+\t\t\t\t\tSETUP_ACC_X_L = 3,
+\t\t\t\t\tWAIT_ACC_X_L = 4,
+\t\t\t\t\tREAD_ACC_X_L = 5,
+\t\t\t\t\tSETUP_ACC_Y_H = 6,
+\t\t\t\t\tWAIT_ACC_Y_H = 7,
+\t\t\t\t\tREAD_ACC_Y_H = 8,
+\t\t\t\t\tSETUP_ACC_Y_L = 9,
+\t\t\t\t\tWAIT_ACC_Y_L = 10,
+\t\t\t\t\tREAD_ACC_Y_L = 11,
+\t\t\t\t\tSETUP_ACC_Z_H = 12,
+\t\t\t\t\tWAIT_ACC_Z_H = 13,
+\t\t\t\t\tREAD_ACC_Z_H = 14,
+\t\t\t\t\tSETUP_ACC_Z_L = 15,
+\t\t\t\t\tWAIT_ACC_Z_L = 16,
+\t\t\t\t\tREAD_ACC_Z_L = 17;\t\t\t
+\t
+\t
+\twire mpu_busy;\t\t\t\t\t\t//mpu is running,don\'t go next state == 1, else ==0
+\twire [7:0] mpu_read_data;\t\t\t\t//8bit SPI_IN data
+
+\treg [31:0] IDLEcounter = 0;\t\t\t//for IDLE
+\tparameter MAX_IDLEcounter = 32\'d1000000;
+\treg [4:0] state;
+\treg [5:0] read_counter;\t\t\t// high or low , x or y or z
+\t
+\treg [6:0] mpu_address_reg;\t\t//for send address to MPU to read a sensing data from MPU
+\treg [7:0] mpu_write_data;\t\t//for write to MPU 
+\treg mpu_rd_wr_select;\t\t\t//read = 1, write = 0; for MSB of SPI address format
+\treg mpu_start = 0;\t\t\t\t//mpu running start = 1, stop = 0
+\treg [7:0] accel_x_H;\t\t\t\t//accel_x[15:7] buff
+\treg [7:0] accel_y_H;\t\t\t\t//accel_y[15:7] buff
+\treg [7:0] accel_z_H;\t\t\t\t//accel_z[15:7] buff
+\t
+\treg [7:0] whoami;
+\t
+//*******no top.v **********************************\t
+//for SPI_interface instance
+SPI_IF_accel SPI_IF_accel( 
+\t.clk(clk), 
+\t.rst(reset),
+\t.mpu_address(mpu_address_reg),
+\t.mpu_wr_data(mpu_write_data),
+\t.mpu_rd_data(mpu_read_data),//mpu_read_data),
+\t.mpu_rd_wr_sel(mpu_rd_wr_select),
+\t.start(mpu_start),
+\t.busy(mpu_busy),
+\t.SPI_SS_a(SPI_SS_a),\t\t\t\t\t\t//Sleve select 
+\t.SPI_CK_a(SPI_CK_a),\t\t\t\t\t\t//SCLK
+\t.SPI_DO_a(SPI_DO_a),\t\t\t\t\t\t//Master out Sleve in\t\t\t\t\t\t
+\t.SPI_DI_a(SPI_DI_a)\t\t\t\t\t\t//Master in Slave out
+); 
+//********no top.v *************************************
+
+////MPU setup
+//initial begin
+//// write 0x00 to address ""0x6B""
+//// write 0x02 to address ""0x37""
+//end
+
+//for state trans
+always@ (posedge clk)
+begin
+\tif(reset)
+\t\tstate <= 0;
+\telse 
+\tbegin\t
+\t\tcase(state)
+\t\t\t0:if(mpu_busy == 0) state <= 1;\t\t//INIT
+\t\t\t1: state <= 2;\t\t\t\t\t\t\t\t//START setup 
+\t\t\t2:if(mpu_busy == 0) state <= 16;\t\t//WAIT  setup
+\t\t\t16:state <= 17;\t\t\t            //START who am i
+\t\t\t17:if(mpu_busy == 0) state <= 18;\t//WAIT  who am i
+\t\t\t18:state <= 19;\t\t\t\t\t\t\t\t//READ who am i
+\t\t\t
+\t\t\t19:state <= 20;\t\t\t\t\t\t\t//START disable set 
+\t\t\t20:if(mpu_busy == 0) state <= 3;\t//WAIT  disable set\t\t\t\t\t\t\t\t
+\t\t\t
+\t\t\t3:if(mpu_busy == 0)state <= 4;\t\t//start sensing\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t
+ \t\t\t4:if(read_counter == 6 && mpu_busy == 0) state <= 5;\t\t//read accel_x
+\t\t\t5:if(read_counter == 12 && mpu_busy == 0) state <= 6;\t\t//read accel_y
+\t\t\t6:if(read_counter == 18 && mpu_busy == 0) state <= 10;\t\t//read accel_z
+
+\t\t\t10:if(IDLEcounter == MAX_IDLEcounter) state <= 3;
+\t\t\t
+\t\t\t//12: state <= 8;
+\t\t\tdefault state <= 0;
+\t\tendcase
+\tend
+end
+
+
+// 
+always@ (posedge clk)
+begin
+\tif(reset)
+\tbegin
+\t\taccel_x <= 0;
+\t\taccel_y <= 0;
+\t\taccel_z <= 0;
+\t\tmpu_address_reg <= 0;
+\t\tmpu_write_data <= 0;
+\t\tmpu_rd_wr_select <= 1;\t//select read
+\t\tmpu_start <= 0;
+\t\tread_counter <= 0;
+\t\tarm_read_enable_a <= 0;
+\tend
+\t
+\telse
+\tbegin 
+\t\tcase (state)
+\t\t\t0:begin\t\t//INIT
+\t\t\t\t\taccel_x <= 0;
+\t\t\t\t\taccel_y <= 0;
+\t\t\t\t\taccel_z <= 0;
+\t\t\t\t\taccel_x_H <= 0;
+\t\t\t\t\taccel_y_H <= 0;
+\t\t\t\t\taccel_z_H <= 0;
+\t\t\t\t\tmpu_address_reg <= 0;
+\t\t\t\t\tmpu_write_data\t<= 0;
+\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\tread_counter <= 0;
+\t\t\t\t\tIDLEcounter <= 0; 
+\t\t\t\t\tarm_read_enable_a <= 0;
+\t\t\t  end
+\t\t\t1:begin\t\t//START setup
+\t\t\t\tmpu_start <= 1;
+\t\t\t\tmpu_rd_wr_select <= 0; //WRITE
+\t\t\t\tmpu_address_reg <= 8\'h6B;
+\t\t\t\tmpu_write_data <= 8\'h00;
+\t\t\t  end\t\t\t
+\t\t\t2:begin\t\t//WAIT setup
+\t\t\t\tmpu_start <= 0;
+\t\t\t  end
+\t\t\t16:begin\t\t//START whoami
+\t\t\t\tmpu_start <= 1;
+\t\t\t\tmpu_rd_wr_select <= 1; //READ
+\t\t\t\tmpu_address_reg   <= 8\'h75;  // whoami
+\t\t\t end
+\t\t\t17:begin\t\t//WAIT whoami
+\t\t\t\tmpu_start <= 0;
+\t\t\t  end
+\t\t\t18:begin\t\t//READ whoami
+\t\t\t\twhoami <= mpu_read_data;
+\t\t\t  end
+\t\t\t
+\t\t\t19:begin\t\t//START disable set
+\t\t\t\tmpu_start <= 1;
+\t\t\t\tmpu_rd_wr_select <= 0; //WRITE
+\t\t\t\tmpu_address_reg <= 8\'h37; //6c;
+\t\t\t\tmpu_write_data <= 8\'h02;
+\t\t\t  end\t\t\t
+\t\t\t20:begin\t\t//WAIT disable set
+\t\t\t\tmpu_start <= 0;
+\t\t\t   end
+\t\t\t  
+\t\t\t  
+
+
+\t\t\t3:begin\t\t\t//loop start 
+\t\t\t\t\tarm_read_enable_a <= 0;
+\t\t\t\t\taccel_x_H <= 0;
+\t\t\t\t\taccel_y_H <= 0;
+\t\t\t\t\taccel_z_H <= 0;
+\t\t\t\t\tread_counter <= 0;
+\t\t\t\t\tIDLEcounter <= 0; 
+\t\t\t  end
+\t\t\t  
+\t\t\t
+\t\t\t  
+//***********************  A C C E L  ***********************************//\t\t\t  
+\t\t\t4:begin\t\t//read_accel_x
+\t\t\t\t\tcase(read_counter)
+\t\t\t\t\t//start accel_x_H
+\t\t\t\t\t\tSETUP_ACC_X_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_XOUT_H; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_ACC_X_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_ACC_X_H:begin
+\t\t\t\t\t\t\taccel_x_H <= mpu_read_data;
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\t
+\t\t\t\t\t//start accel_x_L
+\t\t\t\t\t\tSETUP_ACC_X_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_XOUT_L; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_ACC_X_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_ACC_X_L:begin
+\t\t\t\t\t\t\taccel_x <= {mpu_read_data,accel_x_H};
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\tendcase
+\t\t\tend
+\t\t\t5:begin\t\t//read_accel_y
+\t\t\t\t\tcase(read_counter)
+\t\t\t\t\t//start accel_y_H
+\t\t\t\t\t\tSETUP_ACC_Y_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_YOUT_H; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_ACC_Y_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_ACC_Y_H:begin
+\t\t\t\t\t\t\taccel_y_H <= mpu_read_data;
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\t
+\t\t\t\t\t//start accel_y_L
+\t\t\t\t\t\tSETUP_ACC_Y_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_YOUT_L; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_ACC_Y_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_ACC_Y_L:begin
+\t\t\t\t\t\t\taccel_y <= {mpu_read_data,accel_y_H};
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\tendcase
+\t\t\tend
+\t\t6:begin\t\t//read_accel_z
+\t\t\t\t\tcase(read_counter)
+\t\t\t\t\t//start accel_z_H
+\t\t\t\t\t\tSETUP_ACC_Z_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_ZOUT_H; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_ACC_Z_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_ACC_Z_H:begin
+\t\t\t\t\t\t\taccel_z_H <= mpu_read_data;
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\t
+\t\t\t\t\t//start accel_y_L
+\t\t\t\t\t\tSETUP_ACC_Z_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_ZOUT_L; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_ACC_Z_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_ACC_Z_L:begin
+\t\t\t\t\t\t\taccel_z <= {mpu_read_data,accel_z_H};
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\tendcase
+\t\t\tend
+\t\t\t
+//*********** G\x81@Y\x81@R\x81@O\x81@S\x81@C\x81@O\x81@P\x81@E **************************//
+//\t\t   7:begin\t\t//read_accel_x
+//\t\t\t\t\tcase(read_counter)
+//\t\t\t\t\t//start gyro_x_H
+//\t\t\t\t\t\tSETUP_GYRO_X_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_XOUT_H; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_GYRO_X_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_GYRO_X_H:begin
+//\t\t\t\t\t\t\tgyro_x_H <= mpu_read_data;
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\t
+//\t\t\t\t\t//start accel_x_L
+//\t\t\t\t\t\tSETUP_GYRO_X_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_XOUT_L; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_GYRO_X_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_GYRO_X_L:begin
+//\t\t\t\t\t\t\tgyro_x <= { mpu_read_data,gyro_x_H};
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\tendcase
+//\t\t\tend
+//\t\t\t8:begin\t\t//read_accel_y
+//\t\t\t\t\tcase(read_counter)
+//\t\t\t\t\t//start accel_y_H
+//\t\t\t\t\t\tSETUP_GYRO_Y_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_YOUT_H; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_GYRO_Y_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_GYRO_Y_H:begin
+//\t\t\t\t\t\t\tgyro_y_H <= mpu_read_data;
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\t
+//\t\t\t\t\t//start accel_y_L
+//\t\t\t\t\t\tSETUP_GYRO_Y_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_YOUT_L; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_GYRO_Y_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_GYRO_Y_L:begin
+//\t\t\t\t\t\t\tgyro_y <= {mpu_read_data,gyro_y_H};
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\tendcase
+//\t\t\tend
+//\t\t\t9:begin\t\t//read_gyro_z
+//\t\t\t\t\tcase(read_counter)
+//\t\t\t\t\t//start gyro_z_H
+//\t\t\t\t\t\tSETUP_GYRO_Z_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_ZOUT_H; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_GYRO_Z_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_GYRO_Z_H:begin
+//\t\t\t\t\t\t\tgyro_z_H <= mpu_read_data;
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\t
+//\t\t\t\t\t//start gyro_y_L
+//\t\t\t\t\t\tSETUP_GYRO_Z_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_ZOUT_L; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_GYRO_Z_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_GYRO_Z_L:begin
+//\t\t\t\t\t\t\tgyro_z <= {mpu_read_data,gyro_z_H};
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\tendcase
+//\t\t\tend
+
+
+\t\t\t
+\t\t\t\t\t\t
+\t\t\t10:begin //IDLE state
+\t\t\t\tif(IDLEcounter == (MAX_IDLEcounter -1000))//32\'d80000)
+\t\t\t\tbegin
+\t\t\t\t\t\tarm_read_enable_a <= 1;
+\t\t\t\t\t\tIDLEcounter <= IDLEcounter + 1;\t\t
+\t\t\t\tend
+\t\t\t\telse begin
+\t\t\t\t\t\tIDLEcounter <= IDLEcounter + 1;\t\t
+\t\t\t\tend
+\t\t\t end
+\t\t\tendcase
+\tend
+end
+
+
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:41:38 11/11/2015 
+// Design Name: 
+// Module Name:    top 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+`include ""MPU9250_defines.v""\t\t//macros for MPUaddress
+
+
+module MPU_gyro_controller(
+    input clk,
+    input reset,
+\toutput reg [15:0] gyro_x,\t\t//gyroscope_x full data
+\toutput reg [15:0] gyro_y,\t\t//gyroscope_y full data
+\toutput reg [15:0] gyro_z,\t\t//gyroscope_z full data
+\toutput SPI_SS_g,\t\t\t\t\t\t//sleve_select
+\toutput SPI_CK_g,\t\t\t\t\t\t//SCLK
+\toutput SPI_DO_g,\t\t\t\t\t\t//Master out Sleve in\t\t\t\t\t
+\tinput SPI_DI_g,\t\t\t\t\t\t//Master in Slave out \t
+\toutput reg arm_read_enable_g
+\t);
+
+\tparameter \tSETUP_GYRO_X_H = 18,
+\t\t\t\t\tWAIT_GYRO_X_H = 19,
+\t\t\t\t\tREAD_GYRO_X_H = 20,
+\t\t\t\t\tSETUP_GYRO_X_L = 21,
+\t\t\t\t\tWAIT_GYRO_X_L = 22,
+\t\t\t\t\tREAD_GYRO_X_L = 23,
+\t\t\t\t\tSETUP_GYRO_Y_H = 24,
+\t\t\t\t\tWAIT_GYRO_Y_H = 25,
+\t\t\t\t\tREAD_GYRO_Y_H = 26,
+\t\t\t\t\tSETUP_GYRO_Y_L = 27,
+\t\t\t\t\tWAIT_GYRO_Y_L = 28,
+\t\t\t\t\tREAD_GYRO_Y_L = 29,
+\t\t\t\t\tSETUP_GYRO_Z_H = 30,
+\t\t\t\t\tWAIT_GYRO_Z_H = 31,
+\t\t\t\t\tREAD_GYRO_Z_H = 32,
+\t\t\t\t\tSETUP_GYRO_Z_L = 33,
+\t\t\t\t\tWAIT_GYRO_Z_L = 34,
+\t\t\t\t\tREAD_GYRO_Z_L = 35;
+\t\t\t\t
+\t
+\twire mpu_busy;\t\t\t\t\t\t//mpu is running,don\'t go next state == 1, else ==0
+\twire [7:0] mpu_read_data;\t\t\t\t//8bit SPI_IN data
+
+\treg [31:0] IDLEcounter = 0;\t\t\t//for IDLE
+\tparameter MAX_IDLEcounter = 32\'d1000000;
+\treg [4:0] state;
+\treg [5:0] read_counter;\t\t\t// high or low , x or y or z
+\t
+\treg [6:0] mpu_address_reg;\t\t//for send address to MPU to read a sensing data from MPU
+\treg [7:0] mpu_write_data;\t\t//for write to MPU 
+\treg mpu_rd_wr_select;\t\t\t//read = 1, write = 0; for MSB of SPI address format
+\treg mpu_start = 0;\t\t\t\t//mpu running start = 1, stop = 0
+\treg [7:0] gyro_x_H;\t\t\t\t//gyro_x[15:7] buff
+\treg [7:0] gyro_y_H;\t\t\t\t//gyro_y[15:7] buff
+\treg [7:0] gyro_z_H;\t\t\t\t//gyro_z[15:7] buff
+\t
+\treg [7:0] whoami;
+\t
+//*******no top.v **********************************\t
+//for SPI_interface instance
+SPI_interface SPI_IF(
+\t.clk(clk), 
+\t.rst(reset),
+\t.mpu_address(mpu_address_reg),
+\t.mpu_wr_data(mpu_write_data),
+\t.mpu_rd_data(mpu_read_data),//mpu_read_data),
+\t.mpu_rd_wr_sel(mpu_rd_wr_select),
+\t.start(mpu_start),
+\t.busy(mpu_busy),
+\t.SPI_SS_g(SPI_SS_g),\t\t\t\t\t\t//Sleve select 
+\t.SPI_CK_g(SPI_CK_g),\t\t\t\t\t\t//SCLK
+\t.SPI_DO_g(SPI_DO_g),\t\t\t\t\t\t//Master out Sleve in\t\t\t\t\t\t
+\t.SPI_DI_g(SPI_DI_g)\t\t\t\t\t\t//Master in Slave out
+); 
+//********no top.v *************************************
+
+
+//for state trans
+always@ (posedge clk)
+begin
+\tif(reset)
+\t\tstate <= 0;
+\telse 
+\tbegin\t
+\t\tcase(state)
+\t\t\t0:if(mpu_busy == 0) state <= 1;\t\t//INIT
+\t\t\t1: state <= 2;\t\t\t\t\t\t\t\t//START setup 
+\t\t\t2:if(mpu_busy == 0) state <= 16;\t\t//WAIT  setup
+\t\t\t16:state <= 17;\t\t\t            //START who am i
+\t\t\t17:if(mpu_busy == 0) state <= 18;\t//WAIT  who am i
+\t\t\t18:state <= 19;\t\t\t\t\t\t\t\t//READ who am i
+\t\t\t
+\t\t\t19:state <= 20;\t\t\t\t\t\t\t//START disable set 
+\t\t\t20:if(mpu_busy == 0) state <= 3;\t//WAIT  disable set\t\t\t\t\t\t\t\t
+\t\t\t
+\t\t\t3:if(mpu_busy == 0)state <= 7;\t\t//start sensing\t\t\t\t\t\t\t\t\t
+\t\t\t
+\t\t\t7:if(read_counter == 24 && mpu_busy == 0) state <= 8;\t\t//read accel_x
+\t\t\t8:if(read_counter == 30 && mpu_busy == 0) state <= 9;\t\t//read accel_y
+\t\t\t9:if(read_counter == 36 && mpu_busy == 0) state <= 10;\t\t//read accel_z
+\t\t\t10:if(IDLEcounter == MAX_IDLEcounter) state <= 3;
+\t\t\tdefault state <= 0;
+\t\tendcase
+\tend
+end
+
+
+// 
+always@ (posedge clk)
+begin
+\tif(reset)
+\tbegin
+\t\tgyro_x <= 0;
+\t\tgyro_y <= 0;
+\t\tgyro_z <= 0;
+\t\tmpu_address_reg <= 0;
+\t\tmpu_write_data <= 0;
+\t\tmpu_rd_wr_select <= 1;\t//select read
+\t\tmpu_start <= 0;
+\t\tread_counter <= 0;
+\t\tarm_read_enable_g <= 0;
+\tend
+\t
+\telse
+\tbegin 
+\t\tcase (state)
+\t\t\t0:begin\t\t//INIT
+\t\t\t\t\tgyro_x <= 0;
+\t\t\t\t\tgyro_y <= 0;
+\t\t\t\t\tgyro_z <= 0;
+\t\t\t\t\tgyro_x_H <= 0;
+\t\t\t\t\tgyro_y_H <= 0;
+\t\t\t\t\tgyro_z_H <= 0;
+\t\t\t\t\tmpu_address_reg <= 0;
+\t\t\t\t\tmpu_write_data\t<= 0;
+\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\tread_counter <= 0;
+\t\t\t\t\tIDLEcounter <= 0; 
+\t\t\t\t\tarm_read_enable_g <= 0;
+\t\t\t  end
+\t\t\t1:begin\t\t//START setup
+\t\t\t\tmpu_start <= 1;
+\t\t\t\tmpu_rd_wr_select <= 0; //WRITE
+\t\t\t\tmpu_address_reg <= 8\'h6B;
+\t\t\t\tmpu_write_data <= 8\'h00;
+\t\t\t  end\t\t\t
+\t\t\t2:begin\t\t//WAIT setup
+\t\t\t\tmpu_start <= 0;
+\t\t\t  end
+\t\t\t16:begin\t\t//START whoami
+\t\t\t\tmpu_start <= 1;
+\t\t\t\tmpu_rd_wr_select <= 1; //READ
+\t\t\t\tmpu_address_reg   <= 8\'h75;  // whoami
+\t\t\t end
+\t\t\t17:begin\t\t//WAIT whoami
+\t\t\t\tmpu_start <= 0;
+\t\t\t  end
+\t\t\t18:begin\t\t//READ whoami
+\t\t\t\twhoami <= mpu_read_data;
+\t\t\t  end
+\t\t\t
+\t\t\t19:begin\t\t//START disable set
+\t\t\t\tmpu_start <= 1;
+\t\t\t\tmpu_rd_wr_select <= 0; //WRITE
+\t\t\t\tmpu_address_reg <= 8\'h37; //6c;
+\t\t\t\tmpu_write_data <= 8\'h02;
+\t\t\t  end\t\t\t
+\t\t\t20:begin\t\t//WAIT disable set
+\t\t\t\tmpu_start <= 0;
+\t\t\t   end
+\t\t\t  
+\t\t\t  
+
+
+\t\t\t3:begin\t\t\t//loop start 
+\t\t\t\t\tarm_read_enable_g <= 0;
+\t\t\t\t\tgyro_x_H <= 0;
+\t\t\t\t\tgyro_y_H <= 0;
+\t\t\t\t\tgyro_z_H <= 0;
+\t\t\t\t\tread_counter <= 18;
+\t\t\t\t\tIDLEcounter <= 0; 
+\t\t\t  end
+\t\t\t  
+\t\t
+//***********************  A C C E L  ***********************************//\t\t\t  
+//\t\t\t4:begin\t\t//read_accel_x
+//\t\t\t\t\tcase(read_counter)
+//\t\t\t\t\t//start accel_x_H
+//\t\t\t\t\t\tSETUP_ACC_X_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_XOUT_H; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_ACC_X_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_ACC_X_H:begin
+//\t\t\t\t\t\t\taccel_x_H <= mpu_read_data;
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\t
+//\t\t\t\t\t//start accel_x_L
+//\t\t\t\t\t\tSETUP_ACC_X_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_XOUT_L; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_ACC_X_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_ACC_X_L:begin
+//\t\t\t\t\t\t\taccel_x <= {mpu_read_data,accel_x_H};
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\tendcase
+//\t\t\tend
+//\t\t\t5:begin\t\t//read_accel_y
+//\t\t\t\t\tcase(read_counter)
+//\t\t\t\t\t//start accel_y_H
+//\t\t\t\t\t\tSETUP_ACC_Y_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_YOUT_H; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_ACC_Y_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_ACC_Y_H:begin
+//\t\t\t\t\t\t\taccel_y_H <= mpu_read_data;
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\t
+//\t\t\t\t\t//start accel_y_L
+//\t\t\t\t\t\tSETUP_ACC_Y_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_YOUT_L; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_ACC_Y_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_ACC_Y_L:begin
+//\t\t\t\t\t\t\taccel_y <= {mpu_read_data,accel_y_H};
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\tendcase
+//\t\t\tend
+//\t\t6:begin\t\t//read_accel_z
+//\t\t\t\t\tcase(read_counter)
+//\t\t\t\t\t//start accel_z_H
+//\t\t\t\t\t\tSETUP_ACC_Z_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_ZOUT_H; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_ACC_Z_H:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_ACC_Z_H:begin
+//\t\t\t\t\t\t\taccel_z_H <= mpu_read_data;
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\t
+//\t\t\t\t\t//start accel_y_L
+//\t\t\t\t\t\tSETUP_ACC_Z_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+//\t\t\t\t\t\t\tbegin
+//\t\t\t\t\t\t\t\tmpu_start <= 1;
+//\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+//\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_ACCEL_ZOUT_L; \t\t//address <= 8\'h3B
+//\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\t\tend
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tWAIT_ACC_Z_L:begin\t\t\t\t\t\t
+//\t\t\t\t\t\t\tmpu_start <= 0;
+//\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\t\tREAD_ACC_Z_L:begin
+//\t\t\t\t\t\t\taccel_z <= {mpu_read_data,accel_z_H};
+//\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+//\t\t\t\t\t\tend
+//\t\t\t\t\tendcase
+//\t\t\tend
+\t\t\t
+//*********** G\x81@Y\x81@R\x81@O\x81@S\x81@C\x81@O\x81@P\x81@E **************************//
+\t\t   7:begin\t\t//read_accel_x
+\t\t\t\t\tcase(read_counter)
+\t\t\t\t\t//start gyro_x_H
+\t\t\t\t\t\tSETUP_GYRO_X_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_XOUT_H; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_GYRO_X_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_GYRO_X_H:begin
+\t\t\t\t\t\t\tgyro_x_H <= mpu_read_data;
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\t
+\t\t\t\t\t//start accel_x_L
+\t\t\t\t\t\tSETUP_GYRO_X_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_XOUT_L; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_GYRO_X_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_GYRO_X_L:begin
+\t\t\t\t\t\t\tgyro_x <= { mpu_read_data,gyro_x_H};
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\tendcase
+\t\t\tend
+\t\t\t8:begin\t\t//read_accel_y
+\t\t\t\t\tcase(read_counter)
+\t\t\t\t\t//start accel_y_H
+\t\t\t\t\t\tSETUP_GYRO_Y_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_YOUT_H; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_GYRO_Y_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_GYRO_Y_H:begin
+\t\t\t\t\t\t\tgyro_y_H <= mpu_read_data;
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\t
+\t\t\t\t\t//start accel_y_L
+\t\t\t\t\t\tSETUP_GYRO_Y_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_YOUT_L; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_GYRO_Y_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_GYRO_Y_L:begin
+\t\t\t\t\t\t\tgyro_y <= {mpu_read_data,gyro_y_H};
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\tendcase
+\t\t\tend
+\t\t\t9:begin\t\t//read_gyro_z
+\t\t\t\t\tcase(read_counter)
+\t\t\t\t\t//start gyro_z_H
+\t\t\t\t\t\tSETUP_GYRO_Z_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_ZOUT_H; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_GYRO_Z_H:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_GYRO_Z_H:begin
+\t\t\t\t\t\t\tgyro_z_H <= mpu_read_data;
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\t
+\t\t\t\t\t//start gyro_y_L
+\t\t\t\t\t\tSETUP_GYRO_Z_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tif(mpu_busy == 0)\t\t//SPIstate == 0 @SPI_IF
+\t\t\t\t\t\t\tbegin
+\t\t\t\t\t\t\t\tmpu_start <= 1;
+\t\t\t\t\t\t\t\tmpu_rd_wr_select <= 1;
+\t\t\t\t\t\t\t\tmpu_address_reg <= `MPU9250_RA_GYRO_ZOUT_L; \t\t//address <= 8\'h3B
+\t\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\t\tend
+\t\t\t\t\t\tend
+\t\t\t\t\t\tWAIT_GYRO_Z_L:begin\t\t\t\t\t\t
+\t\t\t\t\t\t\tmpu_start <= 0;
+\t\t\t\t\t\t\tif(mpu_busy == 0) read_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\t\tREAD_GYRO_Z_L:begin
+\t\t\t\t\t\t\tgyro_z <= {mpu_read_data,gyro_z_H};
+\t\t\t\t\t\t\tread_counter <= read_counter + 1;
+\t\t\t\t\t\tend
+\t\t\t\t\tendcase
+\t\t\tend
+
+
+\t\t\t
+\t\t\t\t\t\t
+\t\t\t10:begin //IDLE state
+\t\t\t\t//if(IDLEcounter == 32\'hFF)//32\'h499999999 
+\t\t\t\tif(IDLEcounter == 32\'d80000)
+\t\t\t\tbegin
+\t\t\t\t\t\tarm_read_enable_g <= 1;
+\t\t\t\t\t\tIDLEcounter <= IDLEcounter + 1;\t\t
+\t\t\t\tend
+\t\t\t\telse begin
+\t\t\t\t\t\tIDLEcounter <= IDLEcounter + 1;\t\t
+\t\t\t\tend
+\t\t\t end
+\t\t\tendcase
+\tend
+end
+
+
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//this code was generated by cReComp
+module sensor_ctl(
+
+input [0:0] clk,
+input rst_32,
+input [31:0] din_32,
+input [0:0] wr_en_32,
+input [0:0] rd_en_32,
+output [31:0] dout_32,
+output [0:0] full_32,
+output [0:0] empty_32,
+input [0:0] SPI_DI_a,
+output [0:0] SPI_SS_a,
+output [0:0] SPI_CK_a,
+output [0:0] SPI_DO_a
+);
+
+parameter INIT_32 \t\t= 0,
+\t\t\tREADY_RCV_32 \t= 1,
+\t\t\tRCV_DATA_32 \t= 2,
+\t\t\tPOSE_32\t\t\t= 3,
+\t\t\tREADY_SND_32\t= 4,
+\t\t\tSND_DATA_32_x\t= 5,
+\t\t\tSND_DATA_32_y\t= 6,
+\t\t\tSND_DATA_32_z\t= 7;
+
+// for input fifo
+wire [31:0] rcv_data_32;
+wire rcv_en_32;
+wire data_empty_32;
+// for output fifo
+wire [31:0] snd_data_32;
+wire snd_en_32;
+wire data_full_32;
+// state register
+reg [3:0] state_32;
+
+wire [15:0] accel_x;
+wire [15:0] accel_y;
+wire [15:0] accel_z;
+
+reg [15:0] accel_x_reg;
+reg [15:0] accel_y_reg;
+reg [15:0] accel_z_reg;
+\r
+wire arm_rd_en_a;\r
+
+////fifo 32bit
+fifo_32x512 input_fifo_32(
+\t.clk(clk),
+\t.srst(rst_32),
+\t
+\t.din(din_32),
+\t.wr_en(wr_en_32),
+\t.full(full_32),
+\t
+\t.dout(rcv_data_32),
+\t.rd_en(rcv_en_32),
+\t.empty(data_empty_32)
+\t);
+\t
+fifo_32x512 output_fifo_32(
+\t.clk(clk),
+\t.srst(rst_32),
+\t
+\t.din(snd_data_32),
+\t.wr_en(snd_en_32),
+\t.full(data_full_32),
+\t
+\t.dout(dout_32),
+\t.rd_en(rd_en_32),
+\t.empty(empty_32)
+\t);
+\t
+//MPU_gyro_controller MPU_gyro_controller(
+//\t.clk(clk),
+//\t.reset(rst_32),
+//\t
+//\t.gyro_x(gyro_x),
+//\t.gyro_y(gyro_y),
+//\t.gyro_z(gyro_z),
+//\t
+//\t.SPI_SS_g(SPI_SS_g),\t\t\t\t\t\t//Sleve select
+//\t.SPI_CK_g(SPI_CK_g),\t\t\t\t\t\t//SCLK
+//\t.SPI_DO_g(SPI_DO_g),\t\t\t\t\t\t//Master out Sleve in
+//\t.SPI_DI_g(SPI_DI_g),\t\t\t\t\t\t//Master in Slave out
+//\t
+//\t.arm_read_enable_g(arm_rd_en_g) \t\t//finish sensing accel_xyz
+//);
+MPU_accel_controller MPU_accel_controller(
+\t.clk(clk),
+\t.reset(rst_32),
+\t
+\t.accel_x(accel_x),
+\t.accel_y(accel_y),
+\t.accel_z(accel_z),
+
+\t.SPI_SS_a(SPI_SS_a),\t\t\t\t\t\t//Sleve select 
+\t.SPI_CK_a(SPI_CK_a),\t\t\t\t\t\t//SCLK
+\t.SPI_DO_a(SPI_DO_a),\t\t\t\t\t\t//Master out Sleve in\t\t\t\t\t\t
+\t.SPI_DI_a(SPI_DI_a),\t\t\t\t\t\t//Master in Slave out
+\t
+\t.arm_read_enable_a(arm_rd_en_a) \t\t\t\t\t\t//finish sensing accel_xyz 
+);
+\r
+
+always @(posedge clk)begin
+\tif(rst_32)
+\t\tstate_32 <= 0;
+\telse
+\t\tcase (state_32)
+\t\t\tINIT_32: \t\t\t\t\t\t\t\t\t\tstate_32 <= READY_RCV_32;
+\t\t\tREADY_RCV_32: if(1) \t\t\t\t\t\t\tstate_32 <= RCV_DATA_32;
+\t\t\tRCV_DATA_32: \t\t\t\t\t\t\t\t\tstate_32 <= POSE_32;
+\t\t\tPOSE_32:\t     if(arm_rd_en_a)\t\t\t\tstate_32 <= READY_SND_32;\r
+//\t\t\tPOSE_32:\t     if(1)\t\t\t\t\t\t\tstate_32 <= READY_SND_32;
+\t\t\tREADY_SND_32: if(data_full_32 == 0)\t\tstate_32 <= SND_DATA_32_x;\r
+//\t\t\tREADY_SND_32: if(1)\t\t\t\t\t\t\tstate_32 <= SND_DATA_32_x;
+\t\t\tSND_DATA_32_x:\t\t\t\t\t\t\t\t\tstate_32 <= SND_DATA_32_y;
+\t\t\tSND_DATA_32_y:\t\t\t\t\t\t\t\t\tstate_32 <= SND_DATA_32_z;
+\t\t\tSND_DATA_32_z:\t\t\t\t\t\t\t\t\tstate_32 <= READY_RCV_32;
+\t\tendcase
+end
+
+assign rcv_en_32 = (state_32 == RCV_DATA_32);
+\r
+assign snd_en_32 = (state_32 > READY_SND_32);\r
+
+assign snd_data_32 = (state_32 == SND_DATA_32_x)? accel_x_reg:
+\t\t\t\t\t\t\t(state_32 == SND_DATA_32_y)? accel_y_reg:
+\t\t\t\t\t\t\t(state_32 == SND_DATA_32_z)? accel_z_reg:0;\r
+
+always @(posedge clk) begin
+\tif (rst_32) begin
+\t\taccel_x_reg <= 0;
+\t\taccel_y_reg <= 0;
+\t\taccel_z_reg <= 0;
+\tend
+\telse
+\t\tcase (state_32)
+\t\t\tINIT_32: begin\r
+\t\t\t\taccel_x_reg <= 0;
+\t\t\t\taccel_y_reg <= 0;
+\t\t\t\taccel_z_reg <= 0;\r
+\t\t\tend
+\t\t\tREADY_RCV_32: begin\r
+\t\t\t\taccel_x_reg <= 0;
+\t\t\t\taccel_y_reg <= 0;
+\t\t\t\taccel_z_reg <= 0;\r
+\t\t\tend\r
+\t\t\tPOSE_32: begin
+\t\t\t\taccel_x_reg <= accel_x;
+\t\t\t\taccel_y_reg <= accel_y;
+\t\t\t\taccel_z_reg <= accel_z;
+\t\t\tend
+\t\tendcase
+end
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    00:45:31 11/17/2015 
+// Design Name: 
+// Module Name:    SPI_interface 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module SPI_interface( 
+\tinput clk,
+\tinput rst,
+\tinput [6:0] mpu_address,\t\t//from MPU9250.v
+\tinput [7:0] mpu_wr_data,\t\t//from MPU9250.v
+\tinput mpu_rd_wr_sel,\t\t\t\t//from MPU9250.v for select read or write 
+\tinput start,\t\t\t\t\t\t//start read/write
+\toutput busy,\t\t\t\t\t//don't be send new address or new data from MPU9250.v 
+\toutput SPI_SS_g,\t\t\t\t\t\t//sleve_select
+\toutput SPI_CK_g,\t\t\t\t\t\t//SCLK
+\toutput SPI_DO_g,\t\t\t\t\t\t//Master out Sleve in\t\t\t\t\t\t
+\tinput SPI_DI_g,\t\t\t\t\t\t//Master in Slave out
+\toutput [7:0] mpu_rd_data\t\t\t\t//for mpu_read_data @MPU9250_controler
+    );
+\t 
+\t reg [7:0] mpu_rd_data_buff; \t\t//for read data baff from MPU
+\t reg [7:0] SPIstate;
+\t reg [11:0] counter;\t\t//for SPI_SS
+\t reg MPUclk;\t\t\t\t//for SPI_SS.  don't stop reversal
+\t reg  do_reg;\t\t\t\t//SPI_DO 
+\t reg  ss_reg;\t\t\t\t//SPI_SS
+\t reg  ck_reg;\t\t\t\t//SPI_CK
+\t reg busy_bf;\t\t\t\t//=MPU_busy buff
+\t reg [4:0] i;\t\t\t\t//counter for mpu_address[i]
+\t reg [4:0] j;\t\t\t\t//counter for mpu_rd_data[j]\r
+\t\r
+\r
+parameter SPI_HALF_CLK = 50; // 50 clks @ 100MHz to make SPI 1MHz\r
+                         // Atlys/Zedboard 50clks = MPU 1clk 
+parameter SPI_CLK = SPI_HALF_CLK*2;\r
+\r
+wire halfCLKpassed = (counter == SPI_HALF_CLK-1);\r
+
+// count 50 clks = SCLK generator
+always@(posedge clk)
+begin
+\tif(rst)
+\tbegin
+\t\tcounter <= 0;
+\t\tMPUclk <= 0;
+\tend
+\telse
+\tbegin\r
+\t\tif(start==1) begin\r
+\t\t\tcounter <= 0;\t\t\r
+\t\t\tMPUclk <= 1;\t\t\t\r
+\t\tend\r
+\t\telse if(halfCLKpassed)begin\t\t\t
+\t\t\tcounter <= 0;\t\t\r
+\t\t\tMPUclk <= ~MPUclk;\r
+\t\t\tend\r
+\t\telse begin\r
+\t\t\tcounter <= counter + 1;
+\t\tend
+\tend
+end
+
+//for state trans 
+always @(posedge clk)
+\tbegin
+\t\tif(rst)
+\t\tbegin
+\t\t\tSPIstate = 0;
+\t\tend
+\t\telse
+\t\tbegin\t\t
+\t\t\tcase(SPIstate)
+\t\t\t\t0:if(start == 1) SPIstate = 1;\t//INIT
+\t\t\t\t1:SPIstate = 3;\t//for SPI_SS = 0
+\t\t\t\t3:begin
+\t\t\t\t\tif(i==0 && mpu_rd_wr_sel == 1)SPIstate = 4;\t\t\t\t//address set
+\t\t\t\t\tif(i==0 && mpu_rd_wr_sel == 0)SPIstate = 5;\t\t\t\t//address set
+\t\t\t\tend
+\t\t\t\t4:if(j==0)SPIstate = 6;\t\t\t\t//read or write data
+\t\t\t\t5:if(j==0)SPIstate = 6;
+\t\t\t\t6:if(halfCLKpassed)SPIstate = 7;\t\t\t\t//HOLD\t\t//FINISH and go to state0 \r
+\t\t\t\t7:SPIstate = 0;\t\t\t//FINISH
+\t\t\tendcase
+\t\tend
+\tend
+ 
+ 
+always @ (posedge clk)
+begin 
+\tif(rst)
+\t\tbegin
+\t\t\tdo_reg = 0;
+\t\t\tck_reg = 1;
+\t\t\tss_reg = 1;
+\t\t\tbusy_bf = 0;
+\t\t\tmpu_rd_data_buff = 0;
+\t\t\ti = 16;
+\t\t\tj = 17;
+\t\tend
+\telse
+\t\tcase(SPIstate)
+\t\t\t0:begin\t\t\t\t\t//INIT
+\t\t\t\tdo_reg = 0;
+\t\t\t\tss_reg = 1; 
+\t\t\t\tbusy_bf = 0;
+\t\t\t   i = 16;
+\t\t\t\tj = 17;
+\t\t\t  end
+\t\t\t1:begin\t\t\t\t\t//ready
+\t\t\t\t\tbusy_bf = 1;
+\t\t\t\t\tss_reg = 0;\r
+\t\t\t\t\tend
+\t\t\t3:begin\t\t\t\t\t//send mpu_address[i] to MPU9250 with SPI
+\t\t\t\tif(halfCLKpassed)
+\t\t\t\tbegin\r
+\t\t\t\t\tcase (i)
+\t\t\t\t\t\t16:do_reg = mpu_rd_wr_sel;
+\t\t\t\t\t\t14:do_reg = mpu_address[6];
+\t\t\t\t\t\t12:do_reg = mpu_address[5];
+\t\t\t\t\t\t10:do_reg = mpu_address[4];
+\t\t\t\t\t\t8: do_reg = mpu_address[3];
+\t\t\t\t\t\t6: do_reg = mpu_address[2];
+\t\t\t\t\t\t4: do_reg = mpu_address[1];
+\t\t\t\t\t\t2: do_reg = mpu_address[0];
+\t\t\t\t\t\t0: do_reg = 0;
+\t\t\t\t\tendcase\r
+\t\t\t\t\tif(i!=0) i=i-1;
+\t\t\t\tend
+\t\t\t  end
+\t\t\t4:begin\t\t\t\t//read SPI_DI from MPU9250 with SPI
+\t\t\t\tif(halfCLKpassed)
+\t\t\t\tbegin
+\t\t\t\t\tcase (j)\r
+\t\t\t\t\t\t16:mpu_rd_data_buff[7] = SPI_DI_g;\r
+\t\t\t\t\t\t14:mpu_rd_data_buff[6] = SPI_DI_g;\r
+\t\t\t\t\t\t12:mpu_rd_data_buff[5] = SPI_DI_g;\r
+\t\t\t\t\t\t10:mpu_rd_data_buff[4] = SPI_DI_g;\r
+\t\t\t\t\t\t8:mpu_rd_data_buff[3] = SPI_DI_g;\r
+\t\t\t\t\t\t6:mpu_rd_data_buff[2] = SPI_DI_g;\r
+\t\t\t\t\t\t4:mpu_rd_data_buff[1] = SPI_DI_g;\r
+\t\t\t\t\t\t2:mpu_rd_data_buff[0] = SPI_DI_g;\t\t\t\t\t\t\r
+\t\t\t\t\tendcase\r
+\t\t\t\t\tif(j!=0) j=j-1;\r
+\t\t\t\tend\r
+\t\t\tend\t
+
+\t\t\t5:begin\t\t\t\t//write data 
+\t\t\t\tif(halfCLKpassed)
+\t\t\t\tbegin
+\t\t\t\t\tcase (j)\r
+\t\t\t\t\t\t16:do_reg = mpu_wr_data[7]; \r
+\t\t\t\t\t\t14:do_reg = mpu_wr_data[6]; \r
+\t\t\t\t\t\t12:do_reg = mpu_wr_data[5]; \r
+\t\t\t\t\t\t10:do_reg = mpu_wr_data[4]; \r
+\t\t\t\t\t\t8:do_reg = mpu_wr_data[3]; \r
+\t\t\t\t\t\t6:do_reg = mpu_wr_data[2]; \r
+\t\t\t\t\t\t4:do_reg = mpu_wr_data[1]; \r
+\t\t\t\t\t\t2:do_reg = mpu_wr_data[0]; \r
+\t\t\t\t\t\t0:do_reg = 0;\r
+\t\t\t\t\tendcase\r
+\t\t\t\t\tif(j!=0) j=j-1;\r
+\t\t\t\tend\r
+\t\t\tend\r
+\t\t\t\t\t\t\t  
+\t\t\t6:begin\t\t\t\t//HOLD
+\t\t\t\tck_reg =1;
+\t\t\t\tdo_reg =0;
+\t\t\t\tss_reg = 1;
+\t\t\t  end\r
+\t\t\t  \r
+\t\t\t7:begin\t\t//FINISH\r
+\t\t\tend
+\t\t\t
+\t\tendcase
+end
+
+
+assign SPI_DO_g = do_reg;
+assign SPI_CK_g = MPUclk | ss_reg;
+assign SPI_SS_g = ss_reg;
+assign busy = busy_bf | start;
+assign mpu_rd_data = mpu_rd_data_buff;
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    00:47:09 11/17/2015 
+// Design Name: 
+// Module Name:    MPU9250_defines 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+`define MPU9250_RA_WHO_AM_I         8'h75
+`define MPU9250_RA_ACCEL_XOUT_H     8'h3B
+`define MPU9250_RA_ACCEL_XOUT_L     8'h3C
+`define MPU9250_RA_ACCEL_YOUT_H     8'h3D
+`define MPU9250_RA_ACCEL_YOUT_L     8'h3E
+`define MPU9250_RA_ACCEL_ZOUT_H     8'h3F
+`define MPU9250_RA_ACCEL_ZOUT_L     8'h40
+`define MPU9250_RA_TEMP_OUT_H       8'h41
+`define MPU9250_RA_TEMP_OUT_L       8'h42
+`define MPU9250_RA_GYRO_XOUT_H      8'h43
+`define MPU9250_RA_GYRO_XOUT_L      8'h44
+`define MPU9250_RA_GYRO_YOUT_H      8'h45
+`define MPU9250_RA_GYRO_YOUT_L      8'h46
+`define MPU9250_RA_GYRO_ZOUT_H      8'h47
+`define MPU9250_RA_GYRO_ZOUT_L      8'h48
+\r
+
+//`define MPU9250_RA_SIGNAL_PATH_RESET    8'h68
+//`define MPU9250_RA_MOT_DETECT_CTRL      8'h69
+//`define MPU9250_RA_USER_CTRL        8'h6A
+//`define MPU9250_RA_PWR_MGMT_1       8'h6B
+//`define MPU9250_RA_PWR_MGMT_2       8'h6C
+//`define MPU9250_RA_BANK_SEL         8'h6D
+//`define MPU9250_RA_MEM_START_ADDR   8'h6E
+//`define MPU9250_RA_MEM_R_W          8'h6F
+//`define MPU9250_RA_DMP_CFG_1        8'h70
+//`define MPU9250_RA_DMP_CFG_2        8'h71
+//`define MPU9250_RA_FIFO_COUNTH      8'h72
+//`define MPU9250_RA_FIFO_COUNTL      8'h73
+//`define MPU9250_RA_FIFO_R_W         8'h74
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    00:45:31 11/17/2015 
+// Design Name: 
+// Module Name:    SPI_interface 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module SPI_IF_accel( 
+\tinput clk,
+\tinput rst,
+\tinput [6:0] mpu_address,\t\t//from MPU9250.v
+\tinput [7:0] mpu_wr_data,\t\t//from MPU9250.v
+\tinput mpu_rd_wr_sel,\t\t\t\t//from MPU9250.v for select read or write 
+\tinput start,\t\t\t\t\t\t//start read/write
+\toutput busy,\t\t\t\t\t//don't be send new address or new data from MPU9250.v 
+\toutput SPI_SS_a,\t\t\t\t\t\t//sleve_select
+\toutput SPI_CK_a,\t\t\t\t\t\t//SCLK
+\toutput SPI_DO_a,\t\t\t\t\t\t//Master out Sleve in\t\t\t\t\t\t
+\tinput SPI_DI_a,\t\t\t\t\t\t//Master in Slave out
+\toutput [7:0] mpu_rd_data\t\t\t\t//for mpu_read_data @MPU9250_controler
+    );
+\t 
+\t reg [7:0] mpu_rd_data_buff; \t\t//for read data baff from MPU
+\t reg [7:0] SPIstate;
+\t reg [11:0] counter;\t\t//for SPI_SS
+\t reg MPUclk;\t\t\t\t//for SPI_SS.  don't stop reversal
+\t reg  do_reg;\t\t\t\t//SPI_DO 
+\t reg  ss_reg;\t\t\t\t//SPI_SS
+\t reg  ck_reg;\t\t\t\t//SPI_CK
+\t reg busy_bf;\t\t\t\t//=MPU_busy buff
+\t reg [4:0] i;\t\t\t\t//counter for mpu_address[i]
+\t reg [4:0] j;\t\t\t\t//counter for mpu_rd_data[j]
+\t
+parameter SPI_HALF_CLK = 50; // 50 clks @ 100MHz to make SPI 1MHz
+                         // Atlys/Zedboard 50clks = MPU 1clk 
+parameter SPI_CLK = SPI_HALF_CLK*2;
+
+wire halfCLKpassed = (counter == SPI_HALF_CLK-1);
+
+// count 50 clks = SCLK generator
+always@(posedge clk)
+begin
+\tif(rst)
+\tbegin
+\t\tcounter <= 0;
+\t\tMPUclk <= 0;
+\tend
+\telse
+\tbegin
+\t\tif(start==1) begin
+\t\t\tcounter <= 0;\t\t
+\t\t\tMPUclk <= 1;\t\t\t
+\t\tend
+\t\telse if(halfCLKpassed)begin\t\t\t
+\t\t\tcounter <= 0;\t\t
+\t\t\tMPUclk <= ~MPUclk;
+\t\t\tend
+\t\telse begin
+\t\t\tcounter <= counter + 1;
+\t\tend
+\tend
+end
+
+//for state trans 
+always @(posedge clk)
+\tbegin
+\t\tif(rst)
+\t\tbegin
+\t\t\tSPIstate = 0;
+\t\tend
+\t\telse
+\t\tbegin\t\t
+\t\t\tcase(SPIstate)
+\t\t\t\t0:if(start == 1) SPIstate = 1;\t//INIT
+\t\t\t\t1:SPIstate = 3;\t//for SPI_SS = 0
+\t\t\t\t3:begin
+\t\t\t\t\tif(i==0 && mpu_rd_wr_sel == 1)SPIstate = 4;\t\t\t\t//address set
+\t\t\t\t\tif(i==0 && mpu_rd_wr_sel == 0)SPIstate = 5;\t\t\t\t//address set
+\t\t\t\tend
+\t\t\t\t4:if(j==0)SPIstate = 6;\t\t\t\t//read or write data
+\t\t\t\t5:if(j==0)SPIstate = 6;
+\t\t\t\t6:if(halfCLKpassed)SPIstate = 7;\t\t\t\t//HOLD\t\t//FINISH and go to state0 
+\t\t\t\t7:SPIstate = 0;\t\t\t//FINISH
+\t\t\tendcase
+\t\tend
+\tend
+ 
+ 
+always @ (posedge clk)
+begin 
+\tif(rst)
+\t\tbegin
+\t\t\tdo_reg = 0;
+\t\t\tck_reg = 1;
+\t\t\tss_reg = 1;
+\t\t\tbusy_bf = 0;
+\t\t\tmpu_rd_data_buff = 0;
+\t\t\ti = 16;
+\t\t\tj = 17;
+\t\tend
+\telse
+\t\tcase(SPIstate)
+\t\t\t0:begin\t\t\t\t\t//INIT
+\t\t\t\tdo_reg = 0;
+\t\t\t\tss_reg = 1; 
+\t\t\t\tbusy_bf = 0;
+\t\t\t   i = 16;
+\t\t\t\tj = 17;
+\t\t\t  end
+\t\t\t1:begin\t\t\t\t\t//ready
+\t\t\t\t\tbusy_bf = 1;
+\t\t\t\t\tss_reg = 0;
+\t\t\t\t\tend
+\t\t\t3:begin\t\t\t\t\t//send mpu_address[i] to MPU9250 with SPI
+\t\t\t\tif(halfCLKpassed)
+\t\t\t\tbegin
+\t\t\t\t\tcase (i)
+\t\t\t\t\t\t16:do_reg = mpu_rd_wr_sel;
+\t\t\t\t\t\t14:do_reg = mpu_address[6];
+\t\t\t\t\t\t12:do_reg = mpu_address[5];
+\t\t\t\t\t\t10:do_reg = mpu_address[4];
+\t\t\t\t\t\t8: do_reg = mpu_address[3];
+\t\t\t\t\t\t6: do_reg = mpu_address[2];
+\t\t\t\t\t\t4: do_reg = mpu_address[1];
+\t\t\t\t\t\t2: do_reg = mpu_address[0];
+\t\t\t\t\t\t0: do_reg = 0;
+\t\t\t\t\tendcase
+\t\t\t\t\tif(i!=0) i=i-1;
+\t\t\t\tend
+\t\t\t  end
+\t\t\t4:begin\t\t\t\t//read SPI_DI from MPU9250 with SPI
+\t\t\t\tif(halfCLKpassed)
+\t\t\t\tbegin
+\t\t\t\t\tcase (j)
+\t\t\t\t\t\t16:mpu_rd_data_buff[7] = SPI_DI_a;
+\t\t\t\t\t\t14:mpu_rd_data_buff[6] = SPI_DI_a;
+\t\t\t\t\t\t12:mpu_rd_data_buff[5] = SPI_DI_a;
+\t\t\t\t\t\t10:mpu_rd_data_buff[4] = SPI_DI_a;
+\t\t\t\t\t\t8:mpu_rd_data_buff[3] = SPI_DI_a;
+\t\t\t\t\t\t6:mpu_rd_data_buff[2] = SPI_DI_a;
+\t\t\t\t\t\t4:mpu_rd_data_buff[1] = SPI_DI_a;
+\t\t\t\t\t\t2:mpu_rd_data_buff[0] = SPI_DI_a;\t\t\t\t\t\t
+\t\t\t\t\tendcase
+\t\t\t\t\tif(j!=0) j=j-1;
+\t\t\t\tend
+\t\t\tend\t
+
+\t\t\t5:begin\t\t\t\t//write data 
+\t\t\t\tif(halfCLKpassed)
+\t\t\t\tbegin
+\t\t\t\t\tcase (j)
+\t\t\t\t\t\t16:do_reg = mpu_wr_data[7]; 
+\t\t\t\t\t\t14:do_reg = mpu_wr_data[6]; 
+\t\t\t\t\t\t12:do_reg = mpu_wr_data[5]; 
+\t\t\t\t\t\t10:do_reg = mpu_wr_data[4]; 
+\t\t\t\t\t\t8:do_reg = mpu_wr_data[3]; 
+\t\t\t\t\t\t6:do_reg = mpu_wr_data[2]; 
+\t\t\t\t\t\t4:do_reg = mpu_wr_data[1]; 
+\t\t\t\t\t\t2:do_reg = mpu_wr_data[0]; 
+\t\t\t\t\t\t0:do_reg = 0;
+\t\t\t\t\tendcase
+\t\t\t\t\tif(j!=0) j=j-1;
+\t\t\t\tend
+\t\t\tend
+\t\t\t\t\t\t\t  
+\t\t\t6:begin\t\t\t\t//HOLD
+\t\t\t\tck_reg =1;
+\t\t\t\tdo_reg =0;
+\t\t\t\tss_reg = 1;
+\t\t\t  end
+\t\t\t  
+\t\t\t7:begin\t\t//FINISH
+\t\t\tend
+\t\t\t
+\t\tendcase
+end
+
+
+assign SPI_DO_a = do_reg;
+assign SPI_CK_a = MPUclk | ss_reg;
+assign SPI_SS_a = ss_reg;
+assign busy = busy_bf | start;
+assign mpu_rd_data = mpu_rd_data_buff;
+endmodule
+"
+"////////////////////////////////////////////////////////////////////////////////\r
+// Original Author: Schuyler Eldridge\r
+// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r
+// button_debounce.v\r
+// Created: 10/10/2009\r
+// Modified: 3/20/2012\r
+//\r
+// Counter based debounce circuit originally written for EC551 (back\r
+// in the day) and then modified (i.e. chagned entirely) into 3 always\r
+// block format. This debouncer generates a signal that goes high for\r
+// 1 clock cycle after the clock sees an asserted value on the button\r
+// line. This action is then disabled until the counter hits a\r
+// specified count value that is determined by the clock frequency and\r
+// desired debounce frequency. An alternative implementation would not\r
+// use a counter, but would use the shift register approach, looking\r
+// for repeated matches (say 5) on the button line.\r
+// \r
+// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
+//\r
+// This program is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License.\r
+//\r
+// This program is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+module button_debounce\r
+  (\r
+   input      clk,     // clock\r
+   input      reset_n, // asynchronous reset \r
+   input      button,  // bouncy button\r
+   output reg debounce // debounced 1-cycle signal\r
+   );\r
+  \r
+  parameter\r
+    CLK_FREQUENCY  = 66000000,\r
+    DEBOUNCE_HZ    = 2;\r
+  // These parameters are specified such that you can choose any power\r
+  // of 2 frequency for a debouncer between 1 Hz and\r
+  // CLK_FREQUENCY. Note, that this will throw errors if you choose a\r
+  // non power of 2 frequency (i.e. count_value evaluates to some\r
+  // number / 3 which isn't interpreted as a logical right shift). I'm\r
+  // assuming this will not work for DEBOUNCE_HZ values less than 1,\r
+  // however, I'm uncertain of the value of a debouncer for fractional\r
+  // hertz button presses.\r
+  localparam\r
+    COUNT_VALUE  = CLK_FREQUENCY / DEBOUNCE_HZ,\r
+    WAIT         = 0,\r
+    FIRE         = 1,\r
+    COUNT        = 2;\r
+\r
+  reg [1:0]   state, next_state;\r
+  reg [25:0]  count;\r
+  \r
+  always @ (posedge clk or negedge reset_n)\r
+    state <= (!reset_n) ? WAIT : next_state;\r
+\r
+  always @ (posedge clk or negedge reset_n) begin\r
+    if (!reset_n) begin\r
+      debounce <= 0;\r
+      count    <= 0;\r
+    end\r
+    else begin\r
+      debounce <= 0;\r
+      count    <= 0;\r
+      case (state)\r
+        WAIT: begin\r
+        end\r
+        FIRE: begin\r
+          debounce <= 1;\r
+        end\r
+        COUNT: begin\r
+          count <= count + 1;\r
+        end\r
+      endcase \r
+    end\r
+  end\r
+\r
+  always @ * begin\r
+    case (state)\r
+      WAIT:    next_state = (button)                  ? FIRE : state;\r
+      FIRE:    next_state = COUNT;\r
+      COUNT:   next_state = (count > COUNT_VALUE - 1) ? WAIT : state;\r
+      default: next_state = WAIT;\r
+    endcase\r
+  end\r
+\r
+endmodule\r
+"
+"////////////////////////////////////////////////////////////////////////////////\r
+// Original Author: Schuyler Eldridge\r
+// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r
+// button_debounce.v\r
+// Created:  4.5.2012\r
+// Modified: 4.5.2012\r
+//\r
+// Testbench for button_debounce.v.\r
+// \r
+// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
+//\r
+// This program is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License.\r
+//\r
+// This program is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+module t_button_debounce();\r
+\r
+  parameter\r
+    CLK_FREQUENCY  = 66000000,\r
+    DEBOUNCE_HZ    = 2;\r
+\r
+  reg clk, reset_n, button;\r
+  wire debounce;\r
+  \r
+  button_debounce\r
+    #(\r
+      .CLK_FREQUENCY(CLK_FREQUENCY),\r
+      .DEBOUNCE_HZ(DEBOUNCE_HZ)\r
+      )\r
+  button_debounce\r
+    (\r
+     .clk(clk),\r
+     .reset_n(reset_n),\r
+     .button(button),\r
+     .debounce(debounce)\r
+     );\r
+\r
+  initial begin\r
+    clk          = 1'bx; reset_n = 1'bx; button = 1'bx;\r
+    #10 reset_n  = 1;\r
+    #10 reset_n  = 0; clk = 0;\r
+    #10 reset_n  = 1;\r
+    #10 button   = 0;\r
+  end\r
+\r
+  always\r
+    #5 clk  = ~clk;\r
+\r
+  always begin\r
+    #100 button  = ~button;\r
+    #0.1 button  = ~button;\r
+    #0.1 button  = ~button;\r
+    #0.1 button  = ~button;\r
+    #0.1 button  = ~button;\r
+    #0.1 button  = ~button;\r
+    #0.1 button  = ~button;\r
+    #0.1 button  = ~button;\r
+    #0.1 button  = ~button;\r
+  end\r
+  \r
+endmodule\r
+"
+"/*
+ *  Copyright (c) 2009  Zeus Gomez Marmolejo <zeus@opencores.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module hex_display (
+    input  [15:0] num,
+    input         en,
+
+    output [6:0] hex0,
+    output [6:0] hex1,
+    output [6:0] hex2,
+    output [6:0] hex3
+  );
+
+  // Module instantiations
+  seg_7 hex_group0 (
+    .num (num[3:0]),
+    .en  (en),
+    .seg (hex0)
+  );
+
+  seg_7 hex_group1 (
+    .num (num[7:4]),
+    .en  (en),
+    .seg (hex1)
+  );
+
+  seg_7 hex_group2 (
+    .num (num[11:8]),
+    .en  (en),
+    .seg (hex2)
+  );
+
+  seg_7 hex_group3 (
+    .num (num[15:12]),
+    .en  (en),
+    .seg (hex3)
+  );
+
+endmodule
+"
+"Require Export Sorted.
+Require Export Mergesort.
+"
+"////////////////////////////////////////////////////////////////////////////////\r
+// Original Author: Schuyler Eldridge\r
+// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r
+// pipeline_registers.v\r
+// Created: 4.4.2012\r
+// Modified: 4.4.2012\r
+//\r
+// Implements a series of pipeline registers specified by the input\r
+// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the\r
+// size of the signal passed through each of the pipeline\r
+// registers. NUMBER_OF_STAGES is the number of pipeline registers\r
+// generated. This accepts values of 0 (yes, it just passes data from\r
+// input to output...) up to however many stages specified.\r
+// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
+//\r
+// This program is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License.\r
+//\r
+// This program is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+module pipeline_registers\r
+  (\r
+   input                      clk,\r
+   input                      reset_n,\r
+   input [BIT_WIDTH-1:0]      pipe_in,\r
+   output reg [BIT_WIDTH-1:0] pipe_out\r
+   );\r
+\r
+  // WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r
+  // LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r
+  // OVERWRITTEN!\r
+  parameter \r
+    BIT_WIDTH         = 10,\r
+    NUMBER_OF_STAGES  = 5;\r
+\r
+  // Main generate function for conditional hardware instantiation\r
+  generate\r
+    genvar                                 i;\r
+    // Pass-through case for the odd event that no pipeline stages are\r
+    // specified.\r
+    if (NUMBER_OF_STAGES == 0) begin\r
+      always @ *\r
+        pipe_out = pipe_in;\r
+    end\r
+    // Single flop case for a single stage pipeline\r
+    else if (NUMBER_OF_STAGES == 1) begin\r
+      always @ (posedge clk or negedge reset_n)\r
+        pipe_out <= (!reset_n) ? 0 : pipe_in;\r
+    end\r
+    // Case for 2 or more pipeline stages\r
+    else begin\r
+      // Create the necessary regs\r
+      reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;\r
+      // Create logic for the initial and final pipeline registers\r
+      always @ (posedge clk or negedge reset_n) begin\r
+        if (!reset_n) begin\r
+          pipe_gen[BIT_WIDTH-1:0] <= 0;\r
+          pipe_out                <= 0;\r
+        end\r
+        else begin\r
+          pipe_gen[BIT_WIDTH-1:0] <= pipe_in;\r
+          pipe_out                <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];\r
+        end\r
+      end\r
+      // Create the intermediate pipeline registers if there are 3 or\r
+      // more pipeline stages\r
+      for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline\r
+        always @ (posedge clk or negedge reset_n)\r
+          pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];\r
+      end\r
+    end\r
+  endgenerate\r
+  \r
+endmodule\r
+"
+"////////////////////////////////////////////////////////////////////////////////\r
+// Original Author: Schuyler Eldridge\r
+// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r
+// div_pipelined.v\r
+// Created: 4.3.2012\r
+// Modified: 4.5.2012\r
+//\r
+// Testbench for div_pipelined.v\r
+//\r
+// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
+//\r
+// This program is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License.\r
+//\r
+// This program is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+module t_div_pipelined();\r
+\r
+  reg clk, start, reset_n;\r
+  reg [7:0] dividend, divisor;\r
+  wire      data_valid, div_by_zero;\r
+  wire [7:0] quotient, quotient_correct;\r
+\r
+  parameter\r
+    BITS  = 8;\r
+\r
+  div_pipelined\r
+    #(\r
+      .BITS(BITS)\r
+      )\r
+  div_pipelined\r
+    (\r
+     .clk(clk),\r
+     .reset_n(reset_n),\r
+     .dividend(dividend),\r
+     .divisor(divisor),\r
+     .quotient(quotient),\r
+     .div_by_zero(div_by_zero),\r
+     //     .quotient_correct(quotient_correct),\r
+     .start(start),\r
+     .data_valid(data_valid)\r
+     );\r
+\r
+  initial begin\r
+    #10 reset_n  = 0;\r
+    #50 reset_n  = 1;\r
+    #1\r
+    clk          = 0;\r
+    dividend     = -1;\r
+    divisor      = 127;\r
+    #1000 $finish;\r
+  end\r
+\r
+//  always\r
+//    #20 dividend  = dividend + 1;\r
+\r
+  always begin\r
+    #10 divisor  = divisor - 1; start = 1;\r
+    #10 start    = 0;\r
+  end\r
+\r
+  always\r
+    #5 clk  = ~clk;\r
+\r
+  \r
+endmodule\r
+  "
+"////////////////////////////////////////////////////////////////////////////////\r
+// Original Author: Schuyler Eldridge\r
+// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r
+// sign_extender.v\r
+// Created: 5.16.2012\r
+// Modified: 5.16.2012\r
+//\r
+// Generic sign extension module\r
+//\r
+// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
+//\r
+// This program is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License.\r
+//\r
+// This program is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns/1ps\r
+module sign_extender\r
+  #(\r
+    parameter\r
+    INPUT_WIDTH = 8,\r
+    OUTPUT_WIDTH = 16\r
+    )\r
+  (\r
+   input [INPUT_WIDTH-1:0] original,\r
+   output reg [OUTPUT_WIDTH-1:0] sign_extended_original\r
+   );\r
+\r
+  wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;\r
+\r
+  generate\r
+    genvar                           i;\r
+    for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend\r
+      assign sign_extend[i]  = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;\r
+    end\r
+  endgenerate\r
+\r
+  always @ * begin\r
+    sign_extended_original  = {sign_extend,original};\r
+  end\r
+\r
+endmodule\r
+"
+"////////////////////////////////////////////////////////////////////////////////\r
+// Original Author: Schuyler Eldridge\r
+// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r
+// sqrt_pipelined.v\r
+// Created: 4.2.2012\r
+// Modified: 4.5.2012\r
+//\r
+// Implements a fixed-point parameterized pipelined square root\r
+// operation on an unsigned input of any bit length. The number of\r
+// stages in the pipeline is equal to the number of output bits in the\r
+// computation. This pipelien sustains a throughput of one computation\r
+// per clock cycle.\r
+// \r
+// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
+//\r
+// This program is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License.\r
+//\r
+// This program is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+module sqrt_pipelined\r
+  (\r
+   input                        clk,        // clock\r
+   input                        reset_n,    // asynchronous reset\r
+   input                        start,      // optional start signal\r
+   input [INPUT_BITS-1:0]       radicand,   // unsigned radicand\r
+   output reg                   data_valid, // optional data valid signal\r
+   output reg [OUTPUT_BITS-1:0] root        // unsigned root \r
+   );\r
+\r
+  // WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r
+  // LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r
+  // OVERWRITTEN!\r
+  parameter\r
+    INPUT_BITS   = 16; // number of input bits (any integer)\r
+  localparam\r
+    OUTPUT_BITS  = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits\r
+  \r
+  reg [OUTPUT_BITS-1:0]         start_gen; // valid data propagation\r
+  reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values\r
+  reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values\r
+  wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values\r
+\r
+  // This is the first stage of the pipeline.\r
+  always @ (posedge clk or negedge reset_n) begin\r
+    if (!reset_n) begin\r
+      start_gen[0]                 <= 0;\r
+      radicand_gen[INPUT_BITS-1:0] <= 0;\r
+      root_gen[INPUT_BITS-1:0]     <= 0;\r
+    end\r
+    else begin\r
+      start_gen[0] <= start;\r
+      if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin\r
+        radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];\r
+        root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];\r
+      end\r
+      else begin\r
+        radicand_gen[INPUT_BITS-1:0] <= radicand;\r
+        root_gen[INPUT_BITS-1:0] <= 0;\r
+      end\r
+    end\r
+  end\r
+\r
+  // Main generate loop to create the masks and pipeline stages.\r
+  generate\r
+    genvar i;\r
+    // Generate all the mask values. These are built up in the\r
+    // following fashion:\r
+    // LAST MASK:  0x00...001 \r
+    //             0x00...004  Increasing # OUTPUT_BITS\r
+    //             0x00...010          |\r
+    //             0x00...040          v\r
+    //                 ...\r
+    // FIRST MASK: 0x10...000  # masks == # OUTPUT_BITS\r
+    // \r
+    // Note that the first mask used can either be of the 0x1... or\r
+    // 0x4... variety. This is purely determined by the number of\r
+    // computation stages. However, the last mask used will always be\r
+    // 0x1 and the second to last mask used will always be 0x4.\r
+    for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4\r
+      if (i % 2) // i is odd, this is a 4 mask\r
+        assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)]  = 4 << 4 * (i/2);\r
+      else // i is even, this is a 1 mask\r
+        assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)]  = 1 << 4 * (i/2);\r
+    end\r
+    // Generate all the pipeline stages to compute the square root of\r
+    // the input radicand stream. The general approach is to compare\r
+    // the current values of the root plus the mask to the\r
+    // radicand. If root/mask sum is greater than the radicand,\r
+    // subtract the mask and the root from the radicand and store the\r
+    // radicand for the next stage. Additionally, the root is\r
+    // increased by the value of the mask and stored for the next\r
+    // stage. If this test fails, then the radicand and the root\r
+    // retain their value through to the next stage. The one weird\r
+    // thing is that the mask indices appear to be incremented by one\r
+    // additional position. This is not the case, however, because the\r
+    // first mask is used in the first stage (always block after the\r
+    // generate statement).\r
+    for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline\r
+      always @ (posedge clk or negedge reset_n) begin : pipeline_stage\r
+        if (!reset_n) begin\r
+          start_gen[i+1]                                    <= 0;\r
+          radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r
+          root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]     <= 0;\r
+        end\r
+        else begin\r
+          start_gen[i+1] <= start_gen[i];\r
+          if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] + \r
+               mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin\r
+\t    radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] - \r
+                                                                 mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] - \r
+                                                                 root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r
+\t    root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) + \r
+                                                             mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];\r
+          end\r
+          else begin\r
+\t    radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r
+\t    root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]     <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;\r
+          end\r
+        end\r
+      end\r
+    end\r
+  endgenerate\r
+\r
+  // This is the final stage which just implements a rounding\r
+  // operation. This stage could be tacked on as a combinational logic\r
+  // stage, but who cares about latency, anyway? This is NOT a true\r
+  // rounding stage. In order to add convergent rounding, you need to\r
+  // increase the input bit width by 2 (increase the number of\r
+  // pipeline stages by 1) and implement rounding in the module that\r
+  // instantiates this one. \r
+  always @ (posedge clk or negedge reset_n) begin\r
+    if (!reset_n) begin\r
+      data_valid <= 0;\r
+      root       <= 0;\r
+    end\r
+    else begin\r
+      data_valid <= start_gen[OUTPUT_BITS-1];\r
+      if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])\r
+        root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;\r
+      else\r
+        root  <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];\r
+    end\r
+  end\r
+\r
+endmodule\r
+"
+"/*
+ *  VGA top level file
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module vga (
+    // Wishbone signals
+    input         wb_clk_i,     // 25 Mhz VDU clock
+    input         wb_rst_i,
+    input  [15:0] wb_dat_i,
+    output [15:0] wb_dat_o,
+    input  [16:1] wb_adr_i,
+    input         wb_we_i,
+    input         wb_tga_i,
+    input  [ 1:0] wb_sel_i,
+    input         wb_stb_i,
+    input         wb_cyc_i,
+    output        wb_ack_o,
+
+    // VGA pad signals
+    output [ 3:0] vga_red_o,
+    output [ 3:0] vga_green_o,
+    output [ 3:0] vga_blue_o,
+    output        horiz_sync,
+    output        vert_sync,
+
+    // CSR SRAM master interface
+    output [17:1] csrm_adr_o,
+    output [ 1:0] csrm_sel_o,
+    output        csrm_we_o,
+    output [15:0] csrm_dat_o,
+    input  [15:0] csrm_dat_i
+  );
+
+
+  // Registers and nets
+  //
+  // csr address
+  reg  [17:1] csr_adr_i;
+  reg         csr_stb_i;
+
+  // Config wires
+  wire [15:0] conf_wb_dat_o;
+  wire        conf_wb_ack_o;
+
+  // Mem wires
+  wire [15:0] mem_wb_dat_o;
+  wire        mem_wb_ack_o;
+
+  // LCD wires
+  wire [17:1] csr_adr_o;
+  wire [15:0] csr_dat_i;
+  wire        csr_stb_o;
+  wire        v_retrace;
+  wire        vh_retrace;
+  wire        w_vert_sync;
+
+  // VGA configuration registers
+  wire        shift_reg1;
+  wire        graphics_alpha;
+  wire        memory_mapping1;
+  wire [ 1:0] write_mode;
+  wire [ 1:0] raster_op;
+  wire        read_mode;
+  wire [ 7:0] bitmask;
+  wire [ 3:0] set_reset;
+  wire [ 3:0] enable_set_reset;
+  wire [ 3:0] map_mask;
+  wire        x_dotclockdiv2;
+  wire        chain_four;
+  wire [ 1:0] read_map_select;
+  wire [ 3:0] color_compare;
+  wire [ 3:0] color_dont_care;
+
+  // Wishbone master to SRAM
+  wire [17:1] wbm_adr_o;
+  wire [ 1:0] wbm_sel_o;
+  wire        wbm_we_o;
+  wire [15:0] wbm_dat_o;
+  wire [15:0] wbm_dat_i;
+  wire        wbm_stb_o;
+  wire        wbm_ack_i;
+
+  wire        stb;
+
+  // CRT wires
+  wire [ 5:0] cur_start;
+  wire [ 5:0] cur_end;
+  wire [15:0] start_addr;
+  wire [ 4:0] vcursor;
+  wire [ 6:0] hcursor;
+  wire [ 6:0] horiz_total;
+  wire [ 6:0] end_horiz;
+  wire [ 6:0] st_hor_retr;
+  wire [ 4:0] end_hor_retr;
+  wire [ 9:0] vert_total;
+  wire [ 9:0] end_vert;
+  wire [ 9:0] st_ver_retr;
+  wire [ 3:0] end_ver_retr;
+
+  // attribute_ctrl wires
+  wire [3:0] pal_addr;
+  wire       pal_we;
+  wire [7:0] pal_read;
+  wire [7:0] pal_write;
+
+  // dac_regs wires
+  wire       dac_we;
+  wire [1:0] dac_read_data_cycle;
+  wire [7:0] dac_read_data_register;
+  wire [3:0] dac_read_data;
+  wire [1:0] dac_write_data_cycle;
+  wire [7:0] dac_write_data_register;
+  wire [3:0] dac_write_data;
+
+  // Module instances
+  //
+  vga_config_iface config_iface (
+    .wb_clk_i (wb_clk_i),
+    .wb_rst_i (wb_rst_i),
+    .wb_dat_i (wb_dat_i),
+    .wb_dat_o (conf_wb_dat_o),
+    .wb_adr_i (wb_adr_i[4:1]),
+    .wb_we_i  (wb_we_i),
+    .wb_sel_i (wb_sel_i),
+    .wb_stb_i (stb & wb_tga_i),
+    .wb_ack_o (conf_wb_ack_o),
+
+    .shift_reg1       (shift_reg1),
+    .graphics_alpha   (graphics_alpha),
+    .memory_mapping1  (memory_mapping1),
+    .write_mode       (write_mode),
+    .raster_op        (raster_op),
+    .read_mode        (read_mode),
+    .bitmask          (bitmask),
+    .set_reset        (set_reset),
+    .enable_set_reset (enable_set_reset),
+    .map_mask         (map_mask),
+    .x_dotclockdiv2   (x_dotclockdiv2),
+    .chain_four       (chain_four),
+    .read_map_select  (read_map_select),
+    .color_compare    (color_compare),
+    .color_dont_care  (color_dont_care),
+
+    .pal_addr  (pal_addr),
+    .pal_we    (pal_we),
+    .pal_read  (pal_read),
+    .pal_write (pal_write),
+
+    .dac_we                  (dac_we),
+    .dac_read_data_cycle     (dac_read_data_cycle),
+    .dac_read_data_register  (dac_read_data_register),
+    .dac_read_data           (dac_read_data),
+    .dac_write_data_cycle    (dac_write_data_cycle),
+    .dac_write_data_register (dac_write_data_register),
+    .dac_write_data          (dac_write_data),
+
+    .cur_start  (cur_start),
+    .cur_end    (cur_end),
+    .start_addr (start_addr),
+    .vcursor    (vcursor),
+    .hcursor    (hcursor),
+
+    .horiz_total  (horiz_total),
+    .end_horiz    (end_horiz),
+    .st_hor_retr  (st_hor_retr),
+    .end_hor_retr (end_hor_retr),
+    .vert_total   (vert_total),
+    .end_vert     (end_vert),
+    .st_ver_retr  (st_ver_retr),
+    .end_ver_retr (end_ver_retr),
+
+    .v_retrace  (v_retrace),
+    .vh_retrace (vh_retrace)
+  );
+
+  vga_lcd lcd (
+    .clk (wb_clk_i),
+    .rst (wb_rst_i),
+
+    .shift_reg1     (shift_reg1),
+    .graphics_alpha (graphics_alpha),
+
+    .pal_addr  (pal_addr),
+    .pal_we    (pal_we),
+    .pal_read  (pal_read),
+    .pal_write (pal_write),
+
+    .dac_we                  (dac_we),
+    .dac_read_data_cycle     (dac_read_data_cycle),
+    .dac_read_data_register  (dac_read_data_register),
+    .dac_read_data           (dac_read_data),
+    .dac_write_data_cycle    (dac_write_data_cycle),
+    .dac_write_data_register (dac_write_data_register),
+    .dac_write_data          (dac_write_data),
+
+    .csr_adr_o (csr_adr_o),
+    .csr_dat_i (csr_dat_i),
+    .csr_stb_o (csr_stb_o),
+
+    .vga_red_o   (vga_red_o),
+    .vga_green_o (vga_green_o),
+    .vga_blue_o  (vga_blue_o),
+    .horiz_sync  (horiz_sync),
+    .vert_sync   (w_vert_sync),
+
+    .cur_start  (cur_start),
+    .cur_end    (cur_end),
+    .vcursor    (vcursor),
+    .hcursor    (hcursor),
+
+    .horiz_total  (horiz_total),
+    .end_horiz    (end_horiz),
+    .st_hor_retr  (st_hor_retr),
+    .end_hor_retr (end_hor_retr),
+    .vert_total   (vert_total),
+    .end_vert     (end_vert),
+    .st_ver_retr  (st_ver_retr),
+    .end_ver_retr (end_ver_retr),
+
+    .x_dotclockdiv2 (x_dotclockdiv2),
+
+    .v_retrace  (v_retrace),
+    .vh_retrace (vh_retrace)
+  );
+
+  vga_cpu_mem_iface cpu_mem_iface (
+    .wb_clk_i (wb_clk_i),
+    .wb_rst_i (wb_rst_i),
+
+    .wbs_adr_i (wb_adr_i),
+    .wbs_sel_i (wb_sel_i),
+    .wbs_we_i  (wb_we_i),
+    .wbs_dat_i (wb_dat_i),
+    .wbs_dat_o (mem_wb_dat_o),
+    .wbs_stb_i (stb & !wb_tga_i),
+    .wbs_ack_o (mem_wb_ack_o),
+
+    .wbm_adr_o (wbm_adr_o),
+    .wbm_sel_o (wbm_sel_o),
+    .wbm_we_o  (wbm_we_o),
+    .wbm_dat_o (wbm_dat_o),
+    .wbm_dat_i (wbm_dat_i),
+    .wbm_stb_o (wbm_stb_o),
+    .wbm_ack_i (wbm_ack_i),
+
+    .chain_four       (chain_four),
+    .memory_mapping1  (memory_mapping1),
+    .write_mode       (write_mode),
+    .raster_op        (raster_op),
+    .read_mode        (read_mode),
+    .bitmask          (bitmask),
+    .set_reset        (set_reset),
+    .enable_set_reset (enable_set_reset),
+    .map_mask         (map_mask),
+    .read_map_select  (read_map_select),
+    .color_compare    (color_compare),
+    .color_dont_care  (color_dont_care)
+  );
+
+  vga_mem_arbitrer mem_arbitrer (
+    .clk_i (wb_clk_i),
+    .rst_i (wb_rst_i),
+
+    .wb_adr_i (wbm_adr_o),
+    .wb_sel_i (wbm_sel_o),
+    .wb_we_i  (wbm_we_o),
+    .wb_dat_i (wbm_dat_o),
+    .wb_dat_o (wbm_dat_i),
+    .wb_stb_i (wbm_stb_o),
+    .wb_ack_o (wbm_ack_i),
+
+    .csr_adr_i (csr_adr_i),
+    .csr_dat_o (csr_dat_i),
+    .csr_stb_i (csr_stb_i),
+
+    .csrm_adr_o (csrm_adr_o),
+    .csrm_sel_o (csrm_sel_o),
+    .csrm_we_o  (csrm_we_o),
+    .csrm_dat_o (csrm_dat_o),
+    .csrm_dat_i (csrm_dat_i)
+  );
+
+  // Continous assignments
+  assign wb_dat_o  = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
+  assign wb_ack_o  = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
+  assign stb       = wb_stb_i & wb_cyc_i;
+  assign vert_sync = ~graphics_alpha ^ w_vert_sync;
+
+  // Behaviour
+  // csr_adr_i
+  always @(posedge wb_clk_i)
+    csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
+
+  // csr_stb_i
+  always @(posedge wb_clk_i)
+    csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
+
+endmodule
+"
+"`timescale 1ns / 1ps
+// Copyright (C) 2008 Schuyler Eldridge, Boston University
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+module control(clk,en,dsp_sel,an);
+        input clk, en;
+        output [1:0]dsp_sel;
+        output [3:0]an;
+        wire a,b,c,d,e,f,g,h,i,j,k,l;
+        
+        assign an[3] = a;
+        assign an[2] = b;
+        assign an[1] = c;
+        assign an[0] = d;
+        
+        assign dsp_sel[1] = e;
+        
+        assign dsp_sel[0] = i;
+        
+        
+                FDRSE #(
+                .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
+                ) DFF3(
+                .Q(a), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(d), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                FDRSE #(
+                .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
+                ) DFF2(
+                .Q(b), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(a), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                FDRSE #(
+                .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
+                ) DFF1(
+                .Q(c), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(b), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                FDRSE #(
+                .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
+                ) DFF0(
+                .Q(d), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(c), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                
+                
+                FDRSE #(
+                .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
+                ) DFF7(
+                .Q(e), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(h), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                FDRSE #(
+                .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
+                ) DFF6(
+                .Q(f), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(e), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );              
+                FDRSE #(
+                .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
+                ) DFF5(
+                .Q(g), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(f), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                FDRSE #(
+                .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
+                ) DFF4(
+                .Q(h), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(g), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                
+                
+                FDRSE #(
+                .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
+                ) DFF11(
+                .Q(i), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(l), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                FDRSE #(
+                .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
+                ) DFF10(
+                .Q(j), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(i), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );              
+                FDRSE #(
+                .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
+                ) DFF9(
+                .Q(k), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(j), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+                FDRSE #(
+                .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
+                ) DFF8(
+                .Q(l), // Data output
+                .C(clk), // Clock input
+                .CE(en), // Clock enable input
+                .D(k), // Data input
+                .R(1'b0), // Synchronous reset input
+                .S(1'b0) // Synchronous set input
+                );
+endmodule
+"
+"/*
+ *  PS2 Mouse Interface
+ *  Copyright (C) 2010  Donna Polehn <dpolehn@verizon.net>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module ps2_mouse (
+    input clk,                // Clock Input
+    input reset,              // Reset Input
+    inout ps2_clk,            // PS2 Clock, Bidirectional
+    inout ps2_dat,            // PS2 Data, Bidirectional
+
+    input  [7:0] the_command,        // Command to send to mouse
+    input        send_command,       // Signal to send
+    output       command_was_sent,   // Signal command finished sending
+    output       error_communication_timed_out,
+
+    output [7:0] received_data,        // Received data
+    output       received_data_en,     // If 1 - new data has been received
+    output       start_receiving_data,
+    output       wait_for_incoming_data
+  );
+
+  // --------------------------------------------------------------------
+  // Internal wires and registers Declarations
+  // --------------------------------------------------------------------
+  wire            ps2_clk_posedge;        // Internal Wires
+  wire            ps2_clk_negedge;
+
+  reg    [7:0]    idle_counter;            // Internal Registers
+  reg             ps2_clk_reg;
+  reg             ps2_data_reg;
+  reg             last_ps2_clk;
+
+  reg    [2:0]    ns_ps2_transceiver;        // State Machine Registers
+  reg    [2:0]    s_ps2_transceiver;
+
+  // --------------------------------------------------------------------
+  // Constant Declarations
+  // --------------------------------------------------------------------
+  localparam  PS2_STATE_0_IDLE            = 3'h0,        // states
+              PS2_STATE_1_DATA_IN         = 3'h1,
+              PS2_STATE_2_COMMAND_OUT     = 3'h2,
+              PS2_STATE_3_END_TRANSFER    = 3'h3,
+              PS2_STATE_4_END_DELAYED     = 3'h4;
+
+  // --------------------------------------------------------------------
+  // Finite State Machine(s)
+  // --------------------------------------------------------------------
+  always @(posedge clk) begin
+    if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
+    else              s_ps2_transceiver <= ns_ps2_transceiver;
+  end
+
+  always @(*) begin
+    ns_ps2_transceiver = PS2_STATE_0_IDLE;        // Defaults
+
+    case (s_ps2_transceiver)
+    PS2_STATE_0_IDLE:
+        begin
+            if((idle_counter == 8'hFF) && (send_command == 1'b1))
+                ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
+            else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
+                ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
+            else ns_ps2_transceiver = PS2_STATE_0_IDLE;
+        end
+    PS2_STATE_1_DATA_IN:
+        begin
+            // if((received_data_en == 1'b1)  && (ps2_clk_posedge == 1'b1))
+            if((received_data_en == 1'b1))   ns_ps2_transceiver = PS2_STATE_0_IDLE;
+            else                             ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
+        end
+    PS2_STATE_2_COMMAND_OUT:
+        begin
+            if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
+                ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
+            else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
+        end
+    PS2_STATE_3_END_TRANSFER:
+        begin
+            if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
+            else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
+                ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
+            else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
+        end
+    PS2_STATE_4_END_DELAYED:
+        begin
+            if(received_data_en == 1'b1) begin
+                if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
+                else                     ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
+            end
+            else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
+        end
+
+    default:
+            ns_ps2_transceiver = PS2_STATE_0_IDLE;
+    endcase
+  end
+
+  // --------------------------------------------------------------------
+  // Sequential logic
+  // --------------------------------------------------------------------
+  always @(posedge clk) begin
+    if(reset == 1'b1)     begin
+        last_ps2_clk    <= 1'b1;
+        ps2_clk_reg     <= 1'b1;
+        ps2_data_reg    <= 1'b1;
+    end
+    else begin
+        last_ps2_clk    <= ps2_clk_reg;
+        ps2_clk_reg     <= ps2_clk;
+        ps2_data_reg    <= ps2_dat;
+    end
+  end
+
+  always @(posedge clk) begin
+    if(reset == 1'b1) idle_counter <= 6'h00;
+    else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
+        idle_counter <= idle_counter + 6'h01;
+    else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
+        idle_counter <= 6'h00;
+  end
+
+  // --------------------------------------------------------------------
+  // Combinational logic
+  // --------------------------------------------------------------------
+  assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
+  assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
+
+  assign start_receiving_data      = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
+  assign wait_for_incoming_data    = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
+
+  // --------------------------------------------------------------------
+  // Internal Modules
+  // --------------------------------------------------------------------
+  ps2_mouse_cmdout mouse_cmdout (
+    .clk                           (clk),            // Inputs
+    .reset                         (reset),
+    .the_command                   (the_command),
+    .send_command                  (send_command),
+    .ps2_clk_posedge               (ps2_clk_posedge),
+    .ps2_clk_negedge               (ps2_clk_negedge),
+    .ps2_clk                       (ps2_clk),        // Bidirectionals
+    .ps2_dat                       (ps2_dat),
+    .command_was_sent              (command_was_sent),    // Outputs
+    .error_communication_timed_out (error_communication_timed_out)
+  );
+
+  ps2_mouse_datain mouse_datain (
+    .clk                    (clk),        // Inputs
+    .reset                  (reset),
+    .wait_for_incoming_data (wait_for_incoming_data),
+    .start_receiving_data   (start_receiving_data),
+    .ps2_clk_posedge        (ps2_clk_posedge),
+    .ps2_clk_negedge        (ps2_clk_negedge),
+    .ps2_data               (ps2_data_reg),
+    .received_data          (received_data),   // Outputs
+    .received_data_en       (received_data_en)
+  );
+
+endmodule
+
+"
+"////////////////////////////////////////////////////////////////////////////////\r
+// Original Author: Schuyler Eldridge\r
+// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r
+// t_sqrt_pipelined.v\r
+// Created: 4.2.2012\r
+// Modified: 4.5.2012\r
+//\r
+// Testbench for generic sqrt operation\r
+// \r
+// Copyright (C) 2012 Schuyler Eldridge, Boston University\r
+//\r
+// This program is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License.\r
+//\r
+// This program is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.\r
+////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+module t_sqrt_pipelined();\r
+\r
+  parameter \r
+    INPUT_BITS  = 4;\r
+  localparam\r
+    OUTPUT_BITS  = INPUT_BITS / 2 + INPUT_BITS % 2;\r
+  \r
+  reg [INPUT_BITS-1:0] radicand;\r
+  reg                  clk, start, reset_n;\r
+\r
+  wire [OUTPUT_BITS-1:0] root;\r
+  wire                   data_valid;\r
+//  wire [7:0] root_good;\r
+\r
+  sqrt_pipelined \r
+    #(\r
+      .INPUT_BITS(INPUT_BITS)\r
+      )\r
+    sqrt_pipelined \r
+      (\r
+       .clk(clk),\r
+       .reset_n(reset_n),\r
+       .start(start),\r
+       .radicand(radicand), \r
+       .data_valid(data_valid),\r
+       .root(root)\r
+       );\r
+\r
+  initial begin\r
+    radicand     = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;\r
+    #10 reset_n  = 0; clk = 0;\r
+    #50 reset_n  = 1; radicand = 0;\r
+//    #40 radicand  = 81; start = 1;\r
+//    #10 radicand  = 16'bx; start = 0;\r
+    #10000 $finish;\r
+  end\r
+\r
+  always\r
+    #5 clk = ~clk;\r
+\r
+  always begin\r
+    #10 radicand  = radicand + 1; start = 1;\r
+    #10 start     = 0;\r
+  end\r
+  \r
+\r
+//  always begin\r
+//    #80 start  = 1;\r
+//    #10 start  = 0;\r
+//  end\r
+\r
+endmodule\r
+\r
+"
+"`timescale 1ns / 1ps
+// Copyright (C) 2008 Schuyler Eldridge, Boston University
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+module mux(opA,opB,sum,dsp_sel,out);
+\tinput [3:0] opA,opB;
+\tinput [4:0] sum;
+\tinput [1:0] dsp_sel;
+\toutput [3:0] out;
+\t
+\treg cout;
+\t
+\talways @ (sum)
+\t\tbegin
+\t\t\tif (sum[4] == 1)
+\t\t\t\tcout <= 4'b0001;
+\t\t\telse
+\t\t\t\tcout <= 4'b0000;
+\t\tend
+\t
+\treg out;
+\t
+\talways @(dsp_sel,sum,cout,opB,opA)
+\t\tbegin
+\t\t\tif (dsp_sel == 2'b00)
+\t\t\t\tout <= sum[3:0];
+\t\t\telse if (dsp_sel == 2'b01)
+\t\t\t\tout <= cout;
+\t\t\telse if (dsp_sel == 2'b10)
+\t\t\t\tout <= opB;
+\t\t\telse if (dsp_sel == 2'b11)
+\t\t\t\tout <= opA;
+\t\tend
+
+endmodule
+"
+"Declare ML Module ""smpl_plugin""."
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:49:15 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, 
+  I2C0_SCL_O, I2C0_SCL_T, SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, 
+  TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, 
+  M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, 
+  M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, 
+  M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, 
+  DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, 
+  DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin=""I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"" */;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input SDIO0_WP;
+  output UART0_TX;
+  input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  input [0:0]IRQ_F2P;
+  output FCLK_CLK0;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:57:55 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_auto_pc_0_stub.v
+// Design      : design_1_auto_pc_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr, 
+  s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, 
+  s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, 
+  s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, 
+  s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, 
+  s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, 
+  s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid, 
+  m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp, 
+  m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready, 
+  m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin=""aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready"" */;
+  input aclk;
+  input aresetn;
+  input [11:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [3:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awqos;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [11:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wlast;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [11:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [11:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [3:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arqos;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [11:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rlast;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output [31:0]m_axi_awaddr;
+  output [2:0]m_axi_awprot;
+  output m_axi_awvalid;
+  input m_axi_awready;
+  output [31:0]m_axi_wdata;
+  output [3:0]m_axi_wstrb;
+  output m_axi_wvalid;
+  input m_axi_wready;
+  input [1:0]m_axi_bresp;
+  input m_axi_bvalid;
+  output m_axi_bready;
+  output [31:0]m_axi_araddr;
+  output [2:0]m_axi_arprot;
+  output m_axi_arvalid;
+  input m_axi_arready;
+  input [31:0]m_axi_rdata;
+  input [1:0]m_axi_rresp;
+  input m_axi_rvalid;
+  output m_axi_rready;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 03:23:40 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_stub.v
+// Design      : design_1_axi_intc_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_intc,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, intr, irq)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,intr[0:0],irq"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [0:0]intr;
+  output irq;
+endmodule
+"
+"// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, ""Critical
+// Applications""). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 11
+
+(* X_CORE_INFO = ""axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4"" *)
+(* CHECK_LICENSE_TYPE = ""design_1_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}"" *)
+(* CORE_GENERATION_INFO = ""design_1_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER\\
+_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}"" *)
+(* DowngradeIPIdentifiedWarnings = ""yes"" *)
+module design_1_auto_pc_0 (
+  aclk,
+  aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLK CLK"" *)
+input wire aclk;
+(* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RST RST"" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWID"" *)
+input wire [11 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWLEN"" *)
+input wire [3 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWBURST"" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"" *)
+input wire [1 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWPROT"" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWQOS"" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WID"" *)
+input wire [11 : 0] s_axi_wid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WLAST"" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BID"" *)
+output wire [11 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARID"" *)
+input wire [11 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARLEN"" *)
+input wire [3 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARBURST"" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"" *)
+input wire [1 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARPROT"" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARQOS"" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RID"" *)
+output wire [11 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RLAST"" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWADDR"" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWPROT"" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWVALID"" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWREADY"" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WDATA"" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WSTRB"" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WVALID"" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WREADY"" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BRESP"" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BVALID"" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BREADY"" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARADDR"" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARPROT"" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARVALID"" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARREADY"" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RDATA"" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RRESP"" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RVALID"" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RREADY"" *)
+output wire m_axi_rready;
+
+  axi_protocol_converter_v2_1_11_axi_protocol_converter #(
+    .C_FAMILY(""zynq""),
+    .C_M_AXI_PROTOCOL(2),
+    .C_S_AXI_PROTOCOL(1),
+    .C_IGNORE_ID(0),
+    .C_AXI_ID_WIDTH(12),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_TRANSLATION_MODE(2)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(4\'H0),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1\'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(s_axi_wid),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1\'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(4\'H0),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1\'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(12\'H000),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1\'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(12\'H000),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(1\'H1),
+    .m_axi_ruser(1\'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:24 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, 
+  TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, 
+  USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, 
+  M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, 
+  M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, 
+  DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, 
+  DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin=""SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"" */;
+  input SDIO0_WP;
+  output UART0_TX;
+  input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output FCLK_CLK0;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule
+"
+"// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Address Write Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   aw_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_aw_atc #
+  (
+   parameter         C_FAMILY                         = ""rtl"", 
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32, 
+                       // Width of all ADDR signals on SI and MI side of checker.
+                       // Range: 32.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_FIFO_DEPTH_LOG                 = 4
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface
+   output reg                                   cmd_w_valid,
+   output wire                                  cmd_w_check,
+   output wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id,
+   input  wire                                  cmd_w_ready,
+   input  wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr,
+   input  wire                                  cmd_b_ready,
+   
+   // Slave Interface Write Address Port
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [4-1:0]                          S_AXI_AWLEN,
+   input  wire [3-1:0]                          S_AXI_AWSIZE,
+   input  wire [2-1:0]                          S_AXI_AWBURST,
+   input  wire [2-1:0]                          S_AXI_AWLOCK,
+   input  wire [4-1:0]                          S_AXI_AWCACHE,
+   input  wire [3-1:0]                          S_AXI_AWPROT,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire                                  S_AXI_AWVALID,
+   output wire                                  S_AXI_AWREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_AWADDR,
+   output wire [4-1:0]                          M_AXI_AWLEN,
+   output wire [3-1:0]                          M_AXI_AWSIZE,
+   output wire [2-1:0]                          M_AXI_AWBURST,
+   output wire [2-1:0]                          M_AXI_AWLOCK,
+   output wire [4-1:0]                          M_AXI_AWCACHE,
+   output wire [3-1:0]                          M_AXI_AWPROT,
+   output wire [C_AXI_AWUSER_WIDTH-1:0]         M_AXI_AWUSER,
+   output wire                                  M_AXI_AWVALID,
+   input  wire                                  M_AXI_AWREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for burst types.
+  localparam [2-1:0] C_FIX_BURST         = 2\'b00;
+  localparam [2-1:0] C_INCR_BURST        = 2\'b01;
+  localparam [2-1:0] C_WRAP_BURST        = 2\'b10;
+  
+  // Constants for size.
+  localparam [3-1:0] C_OPTIMIZED_SIZE    = 3\'b011;
+  
+  // Constants for length.
+  localparam [4-1:0] C_OPTIMIZED_LEN     = 4\'b0011;
+
+  // Constants for cacheline address.
+  localparam [4-1:0] C_NO_ADDR_OFFSET    = 5\'b0;
+  
+  // Command FIFO settings
+  localparam C_FIFO_WIDTH                = C_AXI_ID_WIDTH + 1;
+  localparam C_FIFO_DEPTH                = 2 ** C_FIFO_DEPTH_LOG;
+    
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction properties.
+  wire                                access_is_incr;
+  wire                                access_is_wrap;
+  wire                                access_is_coherent;
+  wire                                access_optimized_size;
+  wire                                incr_addr_boundary;
+  wire                                incr_is_optimized;
+  wire                                wrap_is_optimized;
+  wire                                access_is_optimized;
+  
+  // Command FIFO.
+  wire                                cmd_w_push;
+  reg                                 cmd_full;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         addr_ptr;
+  wire [C_FIFO_DEPTH_LOG-1:0]         all_addr_ptr;
+  reg  [C_FIFO_WIDTH-1:0]             data_srl[C_FIFO_DEPTH-1:0];
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Decode:
+  //
+  // Detect if transaction is of correct typ, size and length to qualify as
+  // an optimized transaction that has to be checked for errors.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction burst type.
+  assign access_is_incr         = ( S_AXI_AWBURST == C_INCR_BURST );
+  assign access_is_wrap         = ( S_AXI_AWBURST == C_WRAP_BURST );
+  
+  // Transaction has to be Coherent.
+  assign access_is_coherent     = ( S_AXI_AWUSER[0]  == 1\'b1 ) &
+                                  ( S_AXI_AWCACHE[1] == 1\'b1 );
+  
+  // Transaction cacheline boundary address.
+  assign incr_addr_boundary     = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
+  
+  // Transaction length & size.
+  assign access_optimized_size  = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & 
+                                  ( S_AXI_AWLEN  == C_OPTIMIZED_LEN  );
+  
+  // Transaction is optimized.
+  assign incr_is_optimized      = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
+  assign wrap_is_optimized      = access_is_wrap & access_is_coherent & access_optimized_size;
+  assign access_is_optimized    = ( incr_is_optimized | wrap_is_optimized );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command FIFO:
+  //
+  // Since supported write interleaving is only 1, it is safe to use only a 
+  // simple SRL based FIFO as a command queue.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+    
+  // Determine when transaction infromation is pushed to the FIFO.
+  assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
+  
+  // SRL FIFO Pointer.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      addr_ptr <= {C_FIFO_DEPTH_LOG{1\'b1}};
+    end else begin
+      if ( cmd_w_push & ~cmd_w_ready ) begin
+        addr_ptr <= addr_ptr + 1;
+      end else if ( ~cmd_w_push & cmd_w_ready ) begin
+        addr_ptr <= addr_ptr - 1;
+      end
+    end
+  end
+  
+  // Total number of buffered commands.
+  assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
+  
+  // FIFO Flags.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_full    <= 1\'b0;
+      cmd_w_valid <= 1\'b0;
+    end else begin
+      if ( cmd_w_push & ~cmd_w_ready ) begin
+        cmd_w_valid <= 1\'b1;
+      end else if ( ~cmd_w_push & cmd_w_ready ) begin
+        cmd_w_valid <= ( addr_ptr != 0 );
+      end
+      if ( cmd_w_push & ~cmd_b_ready ) begin
+        // Going to full.
+        cmd_full    <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
+      end else if ( ~cmd_w_push & cmd_b_ready ) begin
+        // Pop in middle of queue doesn\'t affect full status.
+        cmd_full    <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
+      end
+    end
+  end
+  
+  // Infere SRL for storage.
+  always @ (posedge ACLK) begin
+    if ( cmd_w_push ) begin
+      for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
+        data_srl[index+1] <= data_srl[index];
+      end
+      data_srl[0]   <= {access_is_optimized, S_AXI_AWID};
+    end
+  end
+  
+  // Get current transaction info.
+  assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Stall commands if FIFO is full. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign M_AXI_AWVALID   = S_AXI_AWVALID & ~cmd_full;
+  
+  // Return ready with push back.
+  assign S_AXI_AWREADY   = M_AXI_AWREADY & ~cmd_full;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Address Write propagation:
+  //
+  // All information is simply forwarded on from the SI- to MI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign M_AXI_AWID      = S_AXI_AWID; 
+  assign M_AXI_AWADDR    = S_AXI_AWADDR;
+  assign M_AXI_AWLEN     = S_AXI_AWLEN;
+  assign M_AXI_AWSIZE    = S_AXI_AWSIZE;
+  assign M_AXI_AWBURST   = S_AXI_AWBURST;
+  assign M_AXI_AWLOCK    = S_AXI_AWLOCK;
+  assign M_AXI_AWCACHE   = S_AXI_AWCACHE;
+  assign M_AXI_AWPROT    = S_AXI_AWPROT;
+  assign M_AXI_AWUSER    = S_AXI_AWUSER;
+  
+  
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:01 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_sim_netlist.v
+// Design      : design_1_axi_gpio_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
+   (GPIO2_DBus_i,
+    GPIO_DBus_i,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    ip2bus_rdack_i,
+    ip2bus_wrack_i_D1_reg,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_o,
+    gpio2_io_t,
+    Q,
+    \\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ,
+    Read_Reg_Rst,
+    Read_Reg2_In,
+    s_axi_aclk,
+    Read_Reg_In,
+    SS,
+    bus2ip_rnw,
+    bus2ip_cs,
+    gpio_io_i,
+    gpio2_io_i,
+    E,
+    s_axi_wdata,
+    bus2ip_rnw_i_reg,
+    bus2ip_rnw_i_reg_0,
+    bus2ip_rnw_i_reg_1);
+  output [3:0]GPIO2_DBus_i;
+  output [3:0]GPIO_DBus_i;
+  output GPIO_xferAck_i;
+  output gpio_xferAck_Reg;
+  output ip2bus_rdack_i;
+  output ip2bus_wrack_i_D1_reg;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  output [3:0]gpio2_io_o;
+  output [3:0]gpio2_io_t;
+  output [3:0]Q;
+  output [3:0]\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
+  input Read_Reg_Rst;
+  input [0:3]Read_Reg2_In;
+  input s_axi_aclk;
+  input [0:3]Read_Reg_In;
+  input [0:0]SS;
+  input bus2ip_rnw;
+  input bus2ip_cs;
+  input [3:0]gpio_io_i;
+  input [3:0]gpio2_io_i;
+  input [0:0]E;
+  input [3:0]s_axi_wdata;
+  input [0:0]bus2ip_rnw_i_reg;
+  input [0:0]bus2ip_rnw_i_reg_0;
+  input [0:0]bus2ip_rnw_i_reg_1;
+
+  wire [3:0]\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire [0:0]SS;
+  wire bus2ip_cs;
+  wire bus2ip_rnw;
+  wire [0:0]bus2ip_rnw_i_reg;
+  wire [0:0]bus2ip_rnw_i_reg_0;
+  wire [0:0]bus2ip_rnw_i_reg_1;
+  wire [3:0]gpio2_io_i;
+  wire [0:3]gpio2_io_i_d2;
+  wire [3:0]gpio2_io_o;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_i;
+  wire [0:3]gpio_io_i_d2;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire iGPIO_xferAck;
+  wire ip2bus_rdack_i;
+  wire ip2bus_wrack_i_D1_reg;
+  wire s_axi_aclk;
+  wire [3:0]s_axi_wdata;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \\Dual.INPUT_DOUBLE_REGS4 
+       (.gpio_io_i(gpio_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \\Dual.INPUT_DOUBLE_REGS5 
+       (.gpio2_io_i(gpio2_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3]}));
+  FDRE \\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[0]),
+        .Q(GPIO2_DBus_i[3]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[1]),
+        .Q(GPIO2_DBus_i[2]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[2]),
+        .Q(GPIO2_DBus_i[1]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[3]),
+        .Q(GPIO2_DBus_i[0]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[0]),
+        .Q(GPIO_DBus_i[3]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[1]),
+        .Q(GPIO_DBus_i[2]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[2]),
+        .Q(GPIO_DBus_i[1]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[3]),
+        .Q(GPIO_DBus_i[0]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.gpio2_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[0]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[1]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[2]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[3]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[3]),
+        .Q(gpio2_io_o[3]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[2]),
+        .Q(gpio2_io_o[2]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[1]),
+        .Q(gpio2_io_o[1]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[0]),
+        .Q(gpio2_io_o[0]),
+        .R(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[3]),
+        .Q(gpio2_io_t[3]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[2]),
+        .Q(gpio2_io_t[2]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[1]),
+        .Q(gpio2_io_t[1]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[0]),
+        .Q(gpio2_io_t[0]),
+        .S(SS));
+  FDRE \\Dual.gpio_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[0]),
+        .Q(\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [3]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[1]),
+        .Q(\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [2]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[2]),
+        .Q(\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [1]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[3]),
+        .Q(\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[3]),
+        .Q(gpio_io_o[3]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[2]),
+        .Q(gpio_io_o[2]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[1]),
+        .Q(gpio_io_o[1]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[0]),
+        .Q(gpio_io_o[0]),
+        .R(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[3]),
+        .Q(gpio_io_t[3]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[2]),
+        .Q(gpio_io_t[2]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[1]),
+        .Q(gpio_io_t[1]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[0]),
+        .Q(gpio_io_t[0]),
+        .S(SS));
+  FDRE gpio_xferAck_Reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_xferAck_i),
+        .Q(gpio_xferAck_Reg),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    iGPIO_xferAck_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_cs),
+        .I2(gpio_xferAck_Reg),
+        .O(iGPIO_xferAck));
+  FDRE iGPIO_xferAck_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(iGPIO_xferAck),
+        .Q(GPIO_xferAck_i),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    ip2bus_rdack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_rdack_i));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    ip2bus_wrack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_wrack_i_D1_reg));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
+   (\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    Read_Reg_Rst,
+    s_axi_aclk,
+    Q,
+    is_read,
+    ip2bus_rdack_i_D1,
+    is_write_reg,
+    ip2bus_wrack_i_D1,
+    gpio2_io_t,
+    \\Dual.gpio2_Data_In_reg[0] ,
+    \\bus2ip_addr_i_reg[8] ,
+    bus2ip_rnw_i_reg,
+    rst_reg,
+    GPIO2_DBus_i,
+    GPIO_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    start2,
+    s_axi_aresetn);
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [3:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output Read_Reg_Rst;
+  input s_axi_aclk;
+  input [3:0]Q;
+  input is_read;
+  input ip2bus_rdack_i_D1;
+  input is_write_reg;
+  input ip2bus_wrack_i_D1;
+  input [3:0]gpio2_io_t;
+  input [3:0]\\Dual.gpio2_Data_In_reg[0] ;
+  input [2:0]\\bus2ip_addr_i_reg[8] ;
+  input bus2ip_rnw_i_reg;
+  input rst_reg;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input start2;
+  input s_axi_aresetn;
+
+  wire [3:0]D;
+  wire [3:0]\\Dual.gpio2_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire [2:0]\\bus2ip_addr_i_reg[8] ;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_write_reg;
+  wire rst_reg;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_wready;
+  wire start2;
+
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[28]_i_1 
+       (.I0(gpio2_io_t[3]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[0]));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[29]_i_1 
+       (.I0(gpio2_io_t[2]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[1]));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[30]_i_1 
+       (.I0(gpio2_io_t[1]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[2]));
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_1 
+       (.I0(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I1(gpio_xferAck_Reg),
+        .I2(bus2ip_rnw_i_reg),
+        .I3(GPIO_xferAck_i),
+        .O(Read_Reg_Rst));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_2 
+       (.I0(gpio2_io_t[0]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[3]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1 
+       (.I0(gpio_io_t[3]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[0]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1 
+       (.I0(gpio_io_t[2]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[1]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1 
+       (.I0(gpio_io_t[1]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[2]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1 
+       (.I0(gpio_io_t[0]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[3]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00001000)) 
+    \\Dual.gpio2_Data_Out[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(rst_reg),
+        .O(\\Dual.gpio2_Data_Out_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF10000000)) 
+    \\Dual.gpio2_OE[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(rst_reg),
+        .O(E));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00000100)) 
+    \\Dual.gpio_Data_Out[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(rst_reg),
+        .O(\\Dual.gpio_Data_Out_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00040000)) 
+    \\Dual.gpio_OE[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(rst_reg),
+        .O(\\Dual.gpio_OE_reg[0] ));
+  LUT5 #(
+    .INIT(32\'h000E0000)) 
+    \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1 
+       (.I0(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I1(start2),
+        .I2(s_axi_wready),
+        .I3(s_axi_arready),
+        .I4(s_axi_aresetn),
+        .O(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
+  FDRE \\MEM_DECODE_GEN[0].cs_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
+        .Q(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[28]_i_1 
+       (.I0(GPIO2_DBus_i[3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[3]),
+        .O(D[3]));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[29]_i_1 
+       (.I0(GPIO2_DBus_i[2]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[2]),
+        .O(D[2]));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[30]_i_1 
+       (.I0(GPIO2_DBus_i[1]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[1]),
+        .O(D[1]));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[31]_i_1 
+       (.I0(GPIO2_DBus_i[0]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[0]),
+        .O(D[0]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00020000)) 
+    s_axi_arready_INST_0
+       (.I0(Q[3]),
+        .I1(Q[2]),
+        .I2(Q[1]),
+        .I3(Q[0]),
+        .I4(is_read),
+        .I5(ip2bus_rdack_i_D1),
+        .O(s_axi_arready));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00020000)) 
+    s_axi_wready_INST_0
+       (.I0(Q[3]),
+        .I1(Q[2]),
+        .I2(Q[1]),
+        .I3(Q[0]),
+        .I4(is_write_reg),
+        .I5(ip2bus_wrack_i_D1),
+        .O(s_axi_wready));
+endmodule
+
+(* C_ALL_INPUTS = ""1"" *) (* C_ALL_INPUTS_2 = ""1"" *) (* C_ALL_OUTPUTS = ""0"" *) 
+(* C_ALL_OUTPUTS_2 = ""0"" *) (* C_DOUT_DEFAULT = ""0"" *) (* C_DOUT_DEFAULT_2 = ""0"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_GPIO2_WIDTH = ""4"" *) (* C_GPIO_WIDTH = ""4"" *) 
+(* C_INTERRUPT_PRESENT = ""0"" *) (* C_IS_DUAL = ""1"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* C_TRI_DEFAULT = ""-1"" *) (* C_TRI_DEFAULT_2 = ""-1"" *) 
+(* downgradeipidentifiedwarnings = ""yes"" *) (* ip_group = ""LOGICORE"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_i,
+    gpio2_io_o,
+    gpio2_io_t);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rst"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* sigis = ""INTR_LEVEL_HIGH"" *) output ip2intc_irpt;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  input [3:0]gpio2_io_i;
+  output [3:0]gpio2_io_o;
+  output [3:0]gpio2_io_t;
+
+  wire \\<const0> ;
+  wire AXI_LITE_IPIF_I_n_11;
+  wire AXI_LITE_IPIF_I_n_12;
+  wire AXI_LITE_IPIF_I_n_21;
+  wire AXI_LITE_IPIF_I_n_22;
+  wire [28:31]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus;
+  wire [28:31]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [0:3]gpio2_Data_In;
+  wire [3:0]gpio2_io_i;
+  wire [3:0]gpio2_io_o;
+  wire [3:0]gpio2_io_t;
+  wire [0:3]gpio_Data_In;
+  wire gpio_core_1_n_11;
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]ip2bus_data_i_D1;
+  wire ip2bus_rdack_i;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rst"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  assign ip2intc_irpt = \\<const0> ;
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\<const0> ;
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\<const0> ;
+  assign s_axi_rdata[30] = \\<const0> ;
+  assign s_axi_rdata[29] = \\<const0> ;
+  assign s_axi_rdata[28] = \\<const0> ;
+  assign s_axi_rdata[27] = \\<const0> ;
+  assign s_axi_rdata[26] = \\<const0> ;
+  assign s_axi_rdata[25] = \\<const0> ;
+  assign s_axi_rdata[24] = \\<const0> ;
+  assign s_axi_rdata[23] = \\<const0> ;
+  assign s_axi_rdata[22] = \\<const0> ;
+  assign s_axi_rdata[21] = \\<const0> ;
+  assign s_axi_rdata[20] = \\<const0> ;
+  assign s_axi_rdata[19] = \\<const0> ;
+  assign s_axi_rdata[18] = \\<const0> ;
+  assign s_axi_rdata[17] = \\<const0> ;
+  assign s_axi_rdata[16] = \\<const0> ;
+  assign s_axi_rdata[15] = \\<const0> ;
+  assign s_axi_rdata[14] = \\<const0> ;
+  assign s_axi_rdata[13] = \\<const0> ;
+  assign s_axi_rdata[12] = \\<const0> ;
+  assign s_axi_rdata[11] = \\<const0> ;
+  assign s_axi_rdata[10] = \\<const0> ;
+  assign s_axi_rdata[9] = \\<const0> ;
+  assign s_axi_rdata[8] = \\<const0> ;
+  assign s_axi_rdata[7] = \\<const0> ;
+  assign s_axi_rdata[6] = \\<const0> ;
+  assign s_axi_rdata[5] = \\<const0> ;
+  assign s_axi_rdata[4] = \\<const0> ;
+  assign s_axi_rdata[3:0] = \\^s_axi_rdata [3:0];
+  assign s_axi_rresp[1] = \\<const0> ;
+  assign s_axi_rresp[0] = \\<const0> ;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
+       (.D(GPIO_DBus),
+        .\\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_12),
+        .\\Dual.gpio_Data_In_reg[0] ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .\\Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_22),
+        .\\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_21),
+        .E(AXI_LITE_IPIF_I_n_11),
+        .GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
+        .GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] (ip2bus_data_i_D1),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(\\^s_axi_rdata ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
+       (.\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .E(AXI_LITE_IPIF_I_n_22),
+        .GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
+        .GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .SS(bus2ip_reset),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_rnw(bus2ip_rnw),
+        .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_21),
+        .bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_12),
+        .bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_11),
+        .gpio2_io_i(gpio2_io_i),
+        .gpio2_io_o(gpio2_io_o),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i(ip2bus_rdack_i),
+        .ip2bus_wrack_i_D1_reg(gpio_core_1_n_11),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_wdata(s_axi_wdata[3:0]));
+  FDRE \\ip2bus_data_i_D1_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus[3]),
+        .Q(ip2bus_data_i_D1[3]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus[2]),
+        .Q(ip2bus_data_i_D1[2]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus[1]),
+        .Q(ip2bus_data_i_D1[1]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus[0]),
+        .Q(ip2bus_data_i_D1[0]),
+        .R(bus2ip_reset));
+  FDRE ip2bus_rdack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_i),
+        .Q(ip2bus_rdack_i_D1),
+        .R(bus2ip_reset));
+  FDRE ip2bus_wrack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_core_1_n_11),
+        .Q(ip2bus_wrack_i_D1),
+        .R(bus2ip_reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
+   (bus2ip_reset,
+    bus2ip_rnw,
+    bus2ip_cs,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    Read_Reg_Rst,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    s_axi_bready,
+    s_axi_rready,
+    s_axi_awaddr,
+    s_axi_araddr,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    gpio2_io_t,
+    Q,
+    GPIO2_DBus_i,
+    GPIO_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    s_axi_aresetn,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output bus2ip_reset;
+  output bus2ip_rnw;
+  output bus2ip_cs;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [3:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output Read_Reg_Rst;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input s_axi_bready;
+  input s_axi_rready;
+  input [2:0]s_axi_awaddr;
+  input [2:0]s_axi_araddr;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [3:0]gpio2_io_t;
+  input [3:0]Q;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input s_axi_aresetn;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
+       (.D(D),
+        .\\Dual.gpio2_Data_Out_reg[0] (\\Dual.gpio2_Data_Out_reg[0] ),
+        .\\Dual.gpio2_OE_reg[0] (bus2ip_rnw),
+        .\\Dual.gpio_Data_In_reg[0] (\\Dual.gpio_Data_In_reg[0] ),
+        .\\Dual.gpio_Data_Out_reg[0] (\\Dual.gpio_Data_Out_reg[0] ),
+        .\\Dual.gpio_OE_reg[0] (\\Dual.gpio_OE_reg[0] ),
+        .E(E),
+        .GPIO2_DBus_i(GPIO2_DBus_i),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
+        .Q(Q),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .bus2ip_rnw_i_reg_0(bus2ip_reset),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] (\\ip2bus_data_i_D1_reg[28] ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
+   (scndry_vect_out,
+    gpio_io_i,
+    s_axi_aclk);
+  output [3:0]scndry_vect_out;
+  input [3:0]gpio_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""cdc_sync"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
+   (scndry_vect_out,
+    gpio2_io_i,
+    s_axi_aclk);
+  output [3:0]scndry_vect_out;
+  input [3:0]gpio2_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]gpio2_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_gpio_0_0,axi_gpio,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_gpio,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    gpio_io_i,
+    gpio2_io_i);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_I"" *) input [3:0]gpio_io_i;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO2 TRI_I"" *) input [3:0]gpio2_io_i;
+
+  wire [3:0]gpio2_io_i;
+  wire [3:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire NLW_U0_ip2intc_irpt_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio2_io_o_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio2_io_t_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio_io_o_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio_io_t_UNCONNECTED;
+
+  (* C_ALL_INPUTS = ""1"" *) 
+  (* C_ALL_INPUTS_2 = ""1"" *) 
+  (* C_ALL_OUTPUTS = ""0"" *) 
+  (* C_ALL_OUTPUTS_2 = ""0"" *) 
+  (* C_DOUT_DEFAULT = ""0"" *) 
+  (* C_DOUT_DEFAULT_2 = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_GPIO2_WIDTH = ""4"" *) 
+  (* C_GPIO_WIDTH = ""4"" *) 
+  (* C_INTERRUPT_PRESENT = ""0"" *) 
+  (* C_IS_DUAL = ""1"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_TRI_DEFAULT = ""-1"" *) 
+  (* C_TRI_DEFAULT_2 = ""-1"" *) 
+  (* downgradeipidentifiedwarnings = ""yes"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
+       (.gpio2_io_i(gpio2_io_i),
+        .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[3:0]),
+        .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[3:0]),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[3:0]),
+        .gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[3:0]),
+        .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
+   (bus2ip_rnw_i_reg_0,
+    \\Dual.gpio2_OE_reg[0] ,
+    \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    Read_Reg_Rst,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    s_axi_bready,
+    s_axi_rready,
+    s_axi_awaddr,
+    s_axi_araddr,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    gpio2_io_t,
+    Q,
+    GPIO2_DBus_i,
+    GPIO_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    s_axi_aresetn,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output bus2ip_rnw_i_reg_0;
+  output \\Dual.gpio2_OE_reg[0] ;
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [3:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output Read_Reg_Rst;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input s_axi_bready;
+  input s_axi_rready;
+  input [2:0]s_axi_awaddr;
+  input [2:0]s_axi_araddr;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [3:0]gpio2_io_t;
+  input [3:0]Q;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input s_axi_aresetn;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire \\Dual.gpio2_OE_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire [0:6]bus2ip_addr;
+  wire \\bus2ip_addr_i[2]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[3]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_1_n_0 ;
+  wire bus2ip_rnw_i06_out;
+  wire bus2ip_rnw_i_reg_0;
+  wire clear;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_write;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire [1:0]p_0_out;
+  wire p_1_in;
+  wire [3:0]plusOp;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [3:0]s_axi_rdata;
+  wire s_axi_rdata_i;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire \\state[1]_i_2_n_0 ;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[1]),
+        .I1(state[0]),
+        .O(clear));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(clear));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
+       (.D(D),
+        .\\Dual.gpio2_Data_In_reg[0] (Q),
+        .\\Dual.gpio2_Data_Out_reg[0] (\\Dual.gpio2_Data_Out_reg[0] ),
+        .\\Dual.gpio_Data_In_reg[0] (\\Dual.gpio_Data_In_reg[0] ),
+        .\\Dual.gpio_Data_Out_reg[0] (\\Dual.gpio_Data_Out_reg[0] ),
+        .\\Dual.gpio_OE_reg[0] (\\Dual.gpio_OE_reg[0] ),
+        .E(E),
+        .GPIO2_DBus_i(GPIO2_DBus_i),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .\\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
+        .bus2ip_rnw_i_reg(\\Dual.gpio2_OE_reg[0] ),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .rst_reg(bus2ip_rnw_i_reg_0),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_wready(s_axi_wready),
+        .start2(start2));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_awaddr[0]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[0]),
+        .O(\\bus2ip_addr_i[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_awaddr[1]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[1]),
+        .O(\\bus2ip_addr_i[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_awaddr[2]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .O(\\bus2ip_addr_i[8]_i_1_n_0 ));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(\\bus2ip_addr_i[2]_i_1_n_0 ),
+        .Q(bus2ip_addr[6]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(\\bus2ip_addr_i[3]_i_1_n_0 ),
+        .Q(bus2ip_addr[5]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .Q(bus2ip_addr[0]),
+        .R(bus2ip_rnw_i_reg_0));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT3 #(
+    .INIT(8\'h02)) 
+    bus2ip_rnw_i_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state[0]),
+        .I2(state[1]),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(bus2ip_rnw_i06_out),
+        .Q(\\Dual.gpio2_OE_reg[0] ),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT5 #(
+    .INIT(32\'h3FFA000A)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(\\state[1]_i_2_n_0 ),
+        .I2(state[1]),
+        .I3(state[0]),
+        .I4(is_read),
+        .O(is_read_i_1_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT6 #(
+    .INIT(64\'h1000FFFF10000000)) 
+    is_write_i_1
+       (.I0(state[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_axi_wvalid),
+        .I3(s_axi_awvalid),
+        .I4(is_write),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hF88800000000FFFF)) 
+    is_write_i_2
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .I4(state[1]),
+        .I5(state[0]),
+        .O(is_write));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    rst_i_1
+       (.I0(s_axi_aresetn),
+        .O(p_1_in));
+  FDRE rst_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(bus2ip_rnw_i_reg_0),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_wready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[3]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(s_axi_rdata_i));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[28] [0]),
+        .Q(s_axi_rdata[0]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[28] [1]),
+        .Q(s_axi_rdata[1]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[28] [2]),
+        .Q(s_axi_rdata[2]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[28] [3]),
+        .Q(s_axi_rdata[3]),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_arready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT5 #(
+    .INIT(32\'h000000F8)) 
+    start2_i_1
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(state[1]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT5 #(
+    .INIT(32\'h0FFFAACC)) 
+    \\state[0]_i_1 
+       (.I0(s_axi_wready),
+        .I1(s_axi_arvalid),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(p_0_out[0]));
+  LUT6 #(
+    .INIT(64\'h2E2E2E2ECCCCFFCC)) 
+    \\state[1]_i_1 
+       (.I0(s_axi_arready),
+        .I1(state[1]),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(\\state[1]_i_3_n_0 ),
+        .I4(s_axi_arvalid),
+        .I5(state[0]),
+        .O(p_0_out[1]));
+  LUT4 #(
+    .INIT(16\'hF888)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(\\state[1]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\state[1]_i_3 
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[0]),
+        .Q(state[0]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[1]),
+        .Q(state[1]),
+        .R(bus2ip_rnw_i_reg_0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:53:58 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top design_1_rst_ps7_0_100M_0 -prefix
+//               design_1_rst_ps7_0_100M_0_ design_1_rst_ps7_0_100M_0_sim_netlist.v
+// Design      : design_1_rst_ps7_0_100M_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_rst_ps7_0_100M_0_cdc_sync
+   (lpf_asr_reg,
+    scndry_out,
+    aux_reset_in,
+    lpf_asr,
+    asr_lpf,
+    p_1_in,
+    p_2_in,
+    slowest_sync_clk);
+  output lpf_asr_reg;
+  output scndry_out;
+  input aux_reset_in;
+  input lpf_asr;
+  input [0:0]asr_lpf;
+  input p_1_in;
+  input p_2_in;
+  input slowest_sync_clk;
+
+  wire asr_d1;
+  wire [0:0]asr_lpf;
+  wire aux_reset_in;
+  wire lpf_asr;
+  wire lpf_asr_reg;
+  wire p_1_in;
+  wire p_2_in;
+  wire s_level_out_d1_cdc_to;
+  wire s_level_out_d2;
+  wire s_level_out_d3;
+  wire scndry_out;
+  wire slowest_sync_clk;
+
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(asr_d1),
+        .Q(s_level_out_d1_cdc_to),
+        .R(1\'b0));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 
+       (.I0(aux_reset_in),
+        .O(asr_d1));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d1_cdc_to),
+        .Q(s_level_out_d2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d2),
+        .Q(s_level_out_d3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d3),
+        .Q(scndry_out),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hEAAAAAA8)) 
+    lpf_asr_i_1
+       (.I0(lpf_asr),
+        .I1(asr_lpf),
+        .I2(scndry_out),
+        .I3(p_1_in),
+        .I4(p_2_in),
+        .O(lpf_asr_reg));
+endmodule
+
+(* ORIG_REF_NAME = ""cdc_sync"" *) 
+module design_1_rst_ps7_0_100M_0_cdc_sync_0
+   (lpf_exr_reg,
+    scndry_out,
+    lpf_exr,
+    p_3_out,
+    mb_debug_sys_rst,
+    ext_reset_in,
+    slowest_sync_clk);
+  output lpf_exr_reg;
+  output scndry_out;
+  input lpf_exr;
+  input [2:0]p_3_out;
+  input mb_debug_sys_rst;
+  input ext_reset_in;
+  input slowest_sync_clk;
+
+  wire \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
+  wire ext_reset_in;
+  wire lpf_exr;
+  wire lpf_exr_reg;
+  wire mb_debug_sys_rst;
+  wire [2:0]p_3_out;
+  wire s_level_out_d1_cdc_to;
+  wire s_level_out_d2;
+  wire s_level_out_d3;
+  wire scndry_out;
+  wire slowest_sync_clk;
+
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
+        .Q(s_level_out_d1_cdc_to),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 
+       (.I0(mb_debug_sys_rst),
+        .I1(ext_reset_in),
+        .O(\\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d1_cdc_to),
+        .Q(s_level_out_d2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d2),
+        .Q(s_level_out_d3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d3),
+        .Q(scndry_out),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hEAAAAAA8)) 
+    lpf_exr_i_1
+       (.I0(lpf_exr),
+        .I1(p_3_out[0]),
+        .I2(scndry_out),
+        .I3(p_3_out[1]),
+        .I4(p_3_out[2]),
+        .O(lpf_exr_reg));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_rst_ps7_0_100M_0,proc_sys_reset,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""proc_sys_reset,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module design_1_rst_ps7_0_100M_0
+   (slowest_sync_clk,
+    ext_reset_in,
+    aux_reset_in,
+    mb_debug_sys_rst,
+    dcm_locked,
+    mb_reset,
+    bus_struct_reset,
+    peripheral_reset,
+    interconnect_aresetn,
+    peripheral_aresetn);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 clock CLK"" *) input slowest_sync_clk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 ext_reset RST"" *) input ext_reset_in;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 aux_reset RST"" *) input aux_reset_in;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 dbg_reset RST"" *) input mb_debug_sys_rst;
+  input dcm_locked;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 mb_rst RST"" *) output mb_reset;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 bus_struct_reset RST"" *) output [0:0]bus_struct_reset;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 peripheral_high_rst RST"" *) output [0:0]peripheral_reset;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 interconnect_low_rst RST"" *) output [0:0]interconnect_aresetn;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 peripheral_low_rst RST"" *) output [0:0]peripheral_aresetn;
+
+  wire aux_reset_in;
+  wire [0:0]bus_struct_reset;
+  wire dcm_locked;
+  wire ext_reset_in;
+  wire [0:0]interconnect_aresetn;
+  wire mb_debug_sys_rst;
+  wire mb_reset;
+  wire [0:0]peripheral_aresetn;
+  wire [0:0]peripheral_reset;
+  wire slowest_sync_clk;
+
+  (* C_AUX_RESET_HIGH = ""1\'b0"" *) 
+  (* C_AUX_RST_WIDTH = ""4"" *) 
+  (* C_EXT_RESET_HIGH = ""1\'b0"" *) 
+  (* C_EXT_RST_WIDTH = ""4"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_NUM_BUS_RST = ""1"" *) 
+  (* C_NUM_INTERCONNECT_ARESETN = ""1"" *) 
+  (* C_NUM_PERP_ARESETN = ""1"" *) 
+  (* C_NUM_PERP_RST = ""1"" *) 
+  design_1_rst_ps7_0_100M_0_proc_sys_reset U0
+       (.aux_reset_in(aux_reset_in),
+        .bus_struct_reset(bus_struct_reset),
+        .dcm_locked(dcm_locked),
+        .ext_reset_in(ext_reset_in),
+        .interconnect_aresetn(interconnect_aresetn),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .mb_reset(mb_reset),
+        .peripheral_aresetn(peripheral_aresetn),
+        .peripheral_reset(peripheral_reset),
+        .slowest_sync_clk(slowest_sync_clk));
+endmodule
+
+module design_1_rst_ps7_0_100M_0_lpf
+   (lpf_int,
+    slowest_sync_clk,
+    dcm_locked,
+    aux_reset_in,
+    mb_debug_sys_rst,
+    ext_reset_in);
+  output lpf_int;
+  input slowest_sync_clk;
+  input dcm_locked;
+  input aux_reset_in;
+  input mb_debug_sys_rst;
+  input ext_reset_in;
+
+  wire \\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
+  wire \\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
+  wire Q;
+  wire [0:0]asr_lpf;
+  wire aux_reset_in;
+  wire dcm_locked;
+  wire ext_reset_in;
+  wire lpf_asr;
+  wire lpf_exr;
+  wire lpf_int;
+  wire lpf_int0__0;
+  wire mb_debug_sys_rst;
+  wire p_1_in;
+  wire p_2_in;
+  wire p_3_in1_in;
+  wire [3:0]p_3_out;
+  wire slowest_sync_clk;
+
+  design_1_rst_ps7_0_100M_0_cdc_sync \\ACTIVE_LOW_AUX.ACT_LO_AUX 
+       (.asr_lpf(asr_lpf),
+        .aux_reset_in(aux_reset_in),
+        .lpf_asr(lpf_asr),
+        .lpf_asr_reg(\\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
+        .p_1_in(p_1_in),
+        .p_2_in(p_2_in),
+        .scndry_out(p_3_in1_in),
+        .slowest_sync_clk(slowest_sync_clk));
+  design_1_rst_ps7_0_100M_0_cdc_sync_0 \\ACTIVE_LOW_EXT.ACT_LO_EXT 
+       (.ext_reset_in(ext_reset_in),
+        .lpf_exr(lpf_exr),
+        .lpf_exr_reg(\\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .p_3_out(p_3_out[2:0]),
+        .scndry_out(p_3_out[3]),
+        .slowest_sync_clk(slowest_sync_clk));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\AUX_LPF[1].asr_lpf_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_in1_in),
+        .Q(p_2_in),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\AUX_LPF[2].asr_lpf_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_2_in),
+        .Q(p_1_in),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\AUX_LPF[3].asr_lpf_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(asr_lpf),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\EXT_LPF[1].exr_lpf_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[3]),
+        .Q(p_3_out[2]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\EXT_LPF[2].exr_lpf_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[2]),
+        .Q(p_3_out[1]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\EXT_LPF[3].exr_lpf_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[1]),
+        .Q(p_3_out[0]),
+        .R(1\'b0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""SRL16"" *) 
+  (* srl_name = ""U0/\\EXT_LPF/POR_SRL_I "" *) 
+  SRL16E #(
+    .INIT(16\'hFFFF)) 
+    POR_SRL_I
+       (.A0(1\'b1),
+        .A1(1\'b1),
+        .A2(1\'b1),
+        .A3(1\'b1),
+        .CE(1\'b1),
+        .CLK(slowest_sync_clk),
+        .D(1\'b0),
+        .Q(Q));
+  FDRE #(
+    .INIT(1\'b0)) 
+    lpf_asr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
+        .Q(lpf_asr),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    lpf_exr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
+        .Q(lpf_exr),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hFFEF)) 
+    lpf_int0
+       (.I0(Q),
+        .I1(lpf_asr),
+        .I2(dcm_locked),
+        .I3(lpf_exr),
+        .O(lpf_int0__0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    lpf_int_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(lpf_int0__0),
+        .Q(lpf_int),
+        .R(1\'b0));
+endmodule
+
+(* C_AUX_RESET_HIGH = ""1\'b0"" *) (* C_AUX_RST_WIDTH = ""4"" *) (* C_EXT_RESET_HIGH = ""1\'b0"" *) 
+(* C_EXT_RST_WIDTH = ""4"" *) (* C_FAMILY = ""zynq"" *) (* C_NUM_BUS_RST = ""1"" *) 
+(* C_NUM_INTERCONNECT_ARESETN = ""1"" *) (* C_NUM_PERP_ARESETN = ""1"" *) (* C_NUM_PERP_RST = ""1"" *) 
+module design_1_rst_ps7_0_100M_0_proc_sys_reset
+   (slowest_sync_clk,
+    ext_reset_in,
+    aux_reset_in,
+    mb_debug_sys_rst,
+    dcm_locked,
+    mb_reset,
+    bus_struct_reset,
+    peripheral_reset,
+    interconnect_aresetn,
+    peripheral_aresetn);
+  input slowest_sync_clk;
+  input ext_reset_in;
+  input aux_reset_in;
+  input mb_debug_sys_rst;
+  input dcm_locked;
+  output mb_reset;
+  (* equivalent_register_removal = ""no"" *) output [0:0]bus_struct_reset;
+  (* equivalent_register_removal = ""no"" *) output [0:0]peripheral_reset;
+  (* equivalent_register_removal = ""no"" *) output [0:0]interconnect_aresetn;
+  (* equivalent_register_removal = ""no"" *) output [0:0]peripheral_aresetn;
+
+  wire Core;
+  wire SEQ_n_3;
+  wire SEQ_n_4;
+  wire aux_reset_in;
+  wire bsr;
+  wire [0:0]bus_struct_reset;
+  wire dcm_locked;
+  wire ext_reset_in;
+  wire [0:0]interconnect_aresetn;
+  wire lpf_int;
+  wire mb_debug_sys_rst;
+  wire mb_reset;
+  wire [0:0]peripheral_aresetn;
+  wire [0:0]peripheral_reset;
+  wire pr;
+  wire slowest_sync_clk;
+
+  (* equivalent_register_removal = ""no"" *) 
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(SEQ_n_3),
+        .Q(interconnect_aresetn),
+        .R(1\'b0));
+  (* equivalent_register_removal = ""no"" *) 
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(SEQ_n_4),
+        .Q(peripheral_aresetn),
+        .R(1\'b0));
+  (* equivalent_register_removal = ""no"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\BSR_OUT_DFF[0].bus_struct_reset_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(bsr),
+        .Q(bus_struct_reset),
+        .R(1\'b0));
+  design_1_rst_ps7_0_100M_0_lpf EXT_LPF
+       (.aux_reset_in(aux_reset_in),
+        .dcm_locked(dcm_locked),
+        .ext_reset_in(ext_reset_in),
+        .lpf_int(lpf_int),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .slowest_sync_clk(slowest_sync_clk));
+  (* equivalent_register_removal = ""no"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\PR_OUT_DFF[0].peripheral_reset_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(pr),
+        .Q(peripheral_reset),
+        .R(1\'b0));
+  design_1_rst_ps7_0_100M_0_sequence_psr SEQ
+       (.\\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
+        .\\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
+        .Core(Core),
+        .bsr(bsr),
+        .lpf_int(lpf_int),
+        .pr(pr),
+        .slowest_sync_clk(slowest_sync_clk));
+  FDRE #(
+    .INIT(1\'b0)) 
+    mb_reset_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(Core),
+        .Q(mb_reset),
+        .R(1\'b0));
+endmodule
+
+module design_1_rst_ps7_0_100M_0_sequence_psr
+   (Core,
+    bsr,
+    pr,
+    \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
+    \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
+    lpf_int,
+    slowest_sync_clk);
+  output Core;
+  output bsr;
+  output pr;
+  output \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
+  output \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
+  input lpf_int;
+  input slowest_sync_clk;
+
+  wire \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
+  wire \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
+  wire Core;
+  wire Core_i_1_n_0;
+  wire bsr;
+  wire \\bsr_dec_reg_n_0_[0] ;
+  wire \\bsr_dec_reg_n_0_[2] ;
+  wire bsr_i_1_n_0;
+  wire \\core_dec[0]_i_1_n_0 ;
+  wire \\core_dec[2]_i_1_n_0 ;
+  wire \\core_dec_reg_n_0_[0] ;
+  wire \\core_dec_reg_n_0_[1] ;
+  wire from_sys_i_1_n_0;
+  wire lpf_int;
+  wire p_0_in;
+  wire [2:0]p_3_out;
+  wire [2:0]p_5_out;
+  wire pr;
+  wire pr_dec0__0;
+  wire \\pr_dec_reg_n_0_[0] ;
+  wire \\pr_dec_reg_n_0_[2] ;
+  wire pr_i_1_n_0;
+  wire seq_clr;
+  wire [5:0]seq_cnt;
+  wire seq_cnt_en;
+  wire slowest_sync_clk;
+
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1 
+       (.I0(bsr),
+        .O(\\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1 
+       (.I0(pr),
+        .O(\\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    Core_i_1
+       (.I0(Core),
+        .I1(p_0_in),
+        .O(Core_i_1_n_0));
+  FDSE #(
+    .INIT(1\'b0)) 
+    Core_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(Core_i_1_n_0),
+        .Q(Core),
+        .S(lpf_int));
+  design_1_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
+       (.Q(seq_cnt),
+        .seq_clr(seq_clr),
+        .seq_cnt_en(seq_cnt_en),
+        .slowest_sync_clk(slowest_sync_clk));
+  LUT4 #(
+    .INIT(16\'h0804)) 
+    \\bsr_dec[0]_i_1 
+       (.I0(seq_cnt_en),
+        .I1(seq_cnt[3]),
+        .I2(seq_cnt[5]),
+        .I3(seq_cnt[4]),
+        .O(p_5_out[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\bsr_dec[2]_i_1 
+       (.I0(\\core_dec_reg_n_0_[1] ),
+        .I1(\\bsr_dec_reg_n_0_[0] ),
+        .O(p_5_out[2]));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\bsr_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_5_out[0]),
+        .Q(\\bsr_dec_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\bsr_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_5_out[2]),
+        .Q(\\bsr_dec_reg_n_0_[2] ),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    bsr_i_1
+       (.I0(bsr),
+        .I1(\\bsr_dec_reg_n_0_[2] ),
+        .O(bsr_i_1_n_0));
+  FDSE #(
+    .INIT(1\'b0)) 
+    bsr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(bsr_i_1_n_0),
+        .Q(bsr),
+        .S(lpf_int));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h8040)) 
+    \\core_dec[0]_i_1 
+       (.I0(seq_cnt[4]),
+        .I1(seq_cnt[3]),
+        .I2(seq_cnt[5]),
+        .I3(seq_cnt_en),
+        .O(\\core_dec[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\core_dec[2]_i_1 
+       (.I0(\\core_dec_reg_n_0_[1] ),
+        .I1(\\core_dec_reg_n_0_[0] ),
+        .O(\\core_dec[2]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\core_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\core_dec[0]_i_1_n_0 ),
+        .Q(\\core_dec_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\core_dec_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(pr_dec0__0),
+        .Q(\\core_dec_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\core_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\core_dec[2]_i_1_n_0 ),
+        .Q(p_0_in),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    from_sys_i_1
+       (.I0(Core),
+        .I1(seq_cnt_en),
+        .O(from_sys_i_1_n_0));
+  FDSE #(
+    .INIT(1\'b0)) 
+    from_sys_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(from_sys_i_1_n_0),
+        .Q(seq_cnt_en),
+        .S(lpf_int));
+  LUT4 #(
+    .INIT(16\'h0210)) 
+    pr_dec0
+       (.I0(seq_cnt[0]),
+        .I1(seq_cnt[1]),
+        .I2(seq_cnt[2]),
+        .I3(seq_cnt_en),
+        .O(pr_dec0__0));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h1080)) 
+    \\pr_dec[0]_i_1 
+       (.I0(seq_cnt_en),
+        .I1(seq_cnt[5]),
+        .I2(seq_cnt[3]),
+        .I3(seq_cnt[4]),
+        .O(p_3_out[0]));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\pr_dec[2]_i_1 
+       (.I0(\\core_dec_reg_n_0_[1] ),
+        .I1(\\pr_dec_reg_n_0_[0] ),
+        .O(p_3_out[2]));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\pr_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[0]),
+        .Q(\\pr_dec_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\pr_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[2]),
+        .Q(\\pr_dec_reg_n_0_[2] ),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    pr_i_1
+       (.I0(pr),
+        .I1(\\pr_dec_reg_n_0_[2] ),
+        .O(pr_i_1_n_0));
+  FDSE #(
+    .INIT(1\'b0)) 
+    pr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(pr_i_1_n_0),
+        .Q(pr),
+        .S(lpf_int));
+  FDRE #(
+    .INIT(1\'b0)) 
+    seq_clr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(1\'b1),
+        .Q(seq_clr),
+        .R(lpf_int));
+endmodule
+
+module design_1_rst_ps7_0_100M_0_upcnt_n
+   (Q,
+    seq_clr,
+    seq_cnt_en,
+    slowest_sync_clk);
+  output [5:0]Q;
+  input seq_clr;
+  input seq_cnt_en;
+  input slowest_sync_clk;
+
+  wire [5:0]Q;
+  wire clear;
+  wire [5:0]q_int0;
+  wire seq_clr;
+  wire seq_cnt_en;
+  wire slowest_sync_clk;
+
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\q_int[0]_i_1 
+       (.I0(Q[0]),
+        .O(q_int0[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\q_int[1]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .O(q_int0[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\q_int[2]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .I2(Q[2]),
+        .O(q_int0[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\q_int[3]_i_1 
+       (.I0(Q[1]),
+        .I1(Q[0]),
+        .I2(Q[2]),
+        .I3(Q[3]),
+        .O(q_int0[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h7FFF8000)) 
+    \\q_int[4]_i_1 
+       (.I0(Q[2]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(Q[3]),
+        .I4(Q[4]),
+        .O(q_int0[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\q_int[5]_i_1 
+       (.I0(seq_clr),
+        .O(clear));
+  LUT6 #(
+    .INIT(64\'h7FFFFFFF80000000)) 
+    \\q_int[5]_i_2 
+       (.I0(Q[3]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(Q[2]),
+        .I4(Q[4]),
+        .I5(Q[5]),
+        .O(q_int0[5]));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[0]),
+        .Q(Q[0]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[1]),
+        .Q(Q[1]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[2]),
+        .Q(Q[2]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[3]),
+        .Q(Q[3]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[4] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[4]),
+        .Q(Q[4]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[5] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[5]),
+        .Q(Q[5]),
+        .R(clear));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:56:44 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
+// Design      : design_1_xbar_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, 
+  s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr, 
+  m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, 
+  m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, 
+  m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin=""aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[63:0],m_axi_awprot[5:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_araddr[63:0],m_axi_arprot[5:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rvalid[1:0],m_axi_rready[1:0]"" */;
+  input aclk;
+  input aresetn;
+  input [31:0]s_axi_awaddr;
+  input [2:0]s_axi_awprot;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [31:0]s_axi_araddr;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [63:0]m_axi_awaddr;
+  output [5:0]m_axi_awprot;
+  output [1:0]m_axi_awvalid;
+  input [1:0]m_axi_awready;
+  output [63:0]m_axi_wdata;
+  output [7:0]m_axi_wstrb;
+  output [1:0]m_axi_wvalid;
+  input [1:0]m_axi_wready;
+  input [3:0]m_axi_bresp;
+  input [1:0]m_axi_bvalid;
+  output [1:0]m_axi_bready;
+  output [63:0]m_axi_araddr;
+  output [5:0]m_axi_arprot;
+  output [1:0]m_axi_arvalid;
+  input [1:0]m_axi_arready;
+  input [63:0]m_axi_rdata;
+  input [3:0]m_axi_rresp;
+  input [1:0]m_axi_rvalid;
+  output [1:0]m_axi_rready;
+endmodule
+"
+"//-----------------------------------------------------------------------------
+//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+//--
+//-- This file contains confidential and proprietary information
+//-- of Xilinx, Inc. and is protected under U.S. and
+//-- international copyright and other intellectual property
+//-- laws.
+//--
+//-- DISCLAIMER
+//-- This disclaimer is not a license and does not grant any
+//-- rights to the materials distributed herewith. Except as
+//-- otherwise provided in a valid license issued to you by
+//-- Xilinx, and to the maximum extent permitted by applicable
+//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//-- (2) Xilinx shall not be liable (whether in contract or tort,
+//-- including negligence, or under any other theory of
+//-- liability) for any loss or damage of any kind or nature
+//-- related to, arising under or in connection with these
+//-- materials, including for any direct, or any indirect,
+//-- special, incidental, or consequential loss or damage
+//-- (including loss of data, profits, goodwill, or any type of
+//-- loss or damage suffered as a result of any action brought
+//-- by a third party) even if such damage or loss was
+//-- reasonably foreseeable or Xilinx had been advised of the
+//-- possibility of the same.
+//--
+//-- CRITICAL APPLICATIONS
+//-- Xilinx products are not designed or intended to be fail-
+//-- safe, or for use in any application requiring fail-safe
+//-- performance, such as life-support or safety devices or
+//-- systems, Class III medical devices, nuclear facilities,
+//-- applications related to the deployment of airbags, or any
+//-- other applications that could lead to death, personal
+//-- injury, or severe property or environmental damage
+//-- (individually and collectively, ""Critical
+//-- Applications""). Customer assumes the sole risk and
+//-- liability of any use of Xilinx products in Critical
+//-- Applications, subject only to applicable laws and
+//-- regulations governing limitations on product liability.
+//--
+//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//-- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: ACP Transaction Checker
+// 
+// Check for optimized ACP transactions and flag if they are broken.
+// 
+// 
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   atc
+//     aw_atc
+//     w_atc
+//     b_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+module processing_system7_v5_5_atc #
+  (
+   parameter         C_FAMILY                         = ""rtl"",
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4,
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32,
+                       // Width of all ADDR signals on SI and MI side of checker.
+                       // Range: 32.
+   parameter integer C_AXI_DATA_WIDTH                 = 64,
+                       // Width of all DATA signals on SI and MI side of checker.
+                       // Range: 64.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_ARUSER_WIDTH               = 1,
+                       // Width of ARUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_WUSER_WIDTH                = 1,
+                       // Width of WUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_RUSER_WIDTH                = 1,
+                       // Width of RUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_BUSER_WIDTH                = 1
+                       // Width of BUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                  ACLK,
+   input  wire                                  ARESETN,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [4-1:0]                          S_AXI_AWLEN,
+   input  wire [3-1:0]                          S_AXI_AWSIZE,
+   input  wire [2-1:0]                          S_AXI_AWBURST,
+   input  wire [2-1:0]                          S_AXI_AWLOCK,
+   input  wire [4-1:0]                          S_AXI_AWCACHE,
+   input  wire [3-1:0]                          S_AXI_AWPROT,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire                                  S_AXI_AWVALID,
+   output wire                                  S_AXI_AWREADY,
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_WID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0]         S_AXI_WSTRB,
+   input  wire                                  S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire                                  S_AXI_WVALID,
+   output wire                                  S_AXI_WREADY,
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_BID,
+   output wire [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                  S_AXI_BVALID,
+   input  wire                                  S_AXI_BREADY,
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_ARID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,
+   input  wire [4-1:0]                          S_AXI_ARLEN,
+   input  wire [3-1:0]                          S_AXI_ARSIZE,
+   input  wire [2-1:0]                          S_AXI_ARBURST,
+   input  wire [2-1:0]                          S_AXI_ARLOCK,
+   input  wire [4-1:0]                          S_AXI_ARCACHE,
+   input  wire [3-1:0]                          S_AXI_ARPROT,
+   input  wire [C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,
+   input  wire                                  S_AXI_ARVALID,
+   output wire                                  S_AXI_ARREADY,
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_RID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_RDATA,
+   output wire [2-1:0]                          S_AXI_RRESP,
+   output wire                                  S_AXI_RLAST,
+   output wire [C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,
+   output wire                                  S_AXI_RVALID,
+   input  wire                                  S_AXI_RREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_AWADDR,
+   output wire [4-1:0]                          M_AXI_AWLEN,
+   output wire [3-1:0]                          M_AXI_AWSIZE,
+   output wire [2-1:0]                          M_AXI_AWBURST,
+   output wire [2-1:0]                          M_AXI_AWLOCK,
+   output wire [4-1:0]                          M_AXI_AWCACHE,
+   output wire [3-1:0]                          M_AXI_AWPROT,
+   output wire [C_AXI_AWUSER_WIDTH-1:0]         M_AXI_AWUSER,
+   output wire                                  M_AXI_AWVALID,
+   input  wire                                  M_AXI_AWREADY,
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0]         M_AXI_WSTRB,
+   output wire                                  M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]          M_AXI_WUSER,
+   output wire                                  M_AXI_WVALID,
+   input  wire                                  M_AXI_WREADY,
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_BID,
+   input  wire [2-1:0]                          M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]          M_AXI_BUSER,
+   input  wire                                  M_AXI_BVALID,
+   output wire                                  M_AXI_BREADY,
+   // Master Interface Read Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_ARID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_ARADDR,
+   output wire [4-1:0]                          M_AXI_ARLEN,
+   output wire [3-1:0]                          M_AXI_ARSIZE,
+   output wire [2-1:0]                          M_AXI_ARBURST,
+   output wire [2-1:0]                          M_AXI_ARLOCK,
+   output wire [4-1:0]                          M_AXI_ARCACHE,
+   output wire [3-1:0]                          M_AXI_ARPROT,
+   output wire [C_AXI_ARUSER_WIDTH-1:0]         M_AXI_ARUSER,
+   output wire                                  M_AXI_ARVALID,
+   input  wire                                  M_AXI_ARREADY,
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_RID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_RDATA,
+   input  wire [2-1:0]                          M_AXI_RRESP,
+   input  wire                                  M_AXI_RLAST,
+   input  wire [C_AXI_RUSER_WIDTH-1:0]          M_AXI_RUSER,
+   input  wire                                  M_AXI_RVALID,
+   output wire                                  M_AXI_RREADY,
+   
+   output wire                                  ERROR_TRIGGER,
+   output wire [C_AXI_ID_WIDTH-1:0]             ERROR_TRANSACTION_ID
+   );
+
+   
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  localparam C_FIFO_DEPTH_LOG            = 4;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Internal reset.
+  reg                                   ARESET;
+  
+  // AW->W command queue signals.
+  wire                                  cmd_w_valid;
+  wire                                  cmd_w_check;
+  wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id;
+  wire                                  cmd_w_ready;
+  
+  // W->B command queue signals.
+  wire                                  cmd_b_push;
+  wire                                  cmd_b_error;
+  wire [C_AXI_ID_WIDTH-1:0]             cmd_b_id;
+  wire                                  cmd_b_full;
+  wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr;
+  wire                                  cmd_b_ready;
+  
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Internal Reset
+  /////////////////////////////////////////////////////////////////////////////
+  always @ (posedge ACLK) begin
+    ARESET <= !ARESETN;
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Write Channels (AW/W/B)
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Write Address Channel.
+  processing_system7_v5_5_aw_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
+   .C_AXI_AWUSER_WIDTH          (C_AXI_AWUSER_WIDTH),
+   .C_FIFO_DEPTH_LOG            (C_FIFO_DEPTH_LOG)
+    ) write_addr_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (Out)
+    .cmd_w_valid                (cmd_w_valid),
+    .cmd_w_check                (cmd_w_check),
+    .cmd_w_id                   (cmd_w_id),
+    .cmd_w_ready                (cmd_w_ready),
+    .cmd_b_addr                 (cmd_b_addr),
+    .cmd_b_ready                (cmd_b_ready),
+   
+    // Slave Interface Write Address Ports
+    .S_AXI_AWID                 (S_AXI_AWID),
+    .S_AXI_AWADDR               (S_AXI_AWADDR),
+    .S_AXI_AWLEN                (S_AXI_AWLEN),
+    .S_AXI_AWSIZE               (S_AXI_AWSIZE),
+    .S_AXI_AWBURST              (S_AXI_AWBURST),
+    .S_AXI_AWLOCK               (S_AXI_AWLOCK),
+    .S_AXI_AWCACHE              (S_AXI_AWCACHE),
+    .S_AXI_AWPROT               (S_AXI_AWPROT),
+    .S_AXI_AWUSER               (S_AXI_AWUSER),
+    .S_AXI_AWVALID              (S_AXI_AWVALID),
+    .S_AXI_AWREADY              (S_AXI_AWREADY),
+    
+    // Master Interface Write Address Port
+    .M_AXI_AWID                 (M_AXI_AWID),
+    .M_AXI_AWADDR               (M_AXI_AWADDR),
+    .M_AXI_AWLEN                (M_AXI_AWLEN),
+    .M_AXI_AWSIZE               (M_AXI_AWSIZE),
+    .M_AXI_AWBURST              (M_AXI_AWBURST),
+    .M_AXI_AWLOCK               (M_AXI_AWLOCK),
+    .M_AXI_AWCACHE              (M_AXI_AWCACHE),
+    .M_AXI_AWPROT               (M_AXI_AWPROT),
+    .M_AXI_AWUSER               (M_AXI_AWUSER),
+    .M_AXI_AWVALID              (M_AXI_AWVALID),
+    .M_AXI_AWREADY              (M_AXI_AWREADY)
+   );
+   
+  // Write Data channel.
+  processing_system7_v5_5_w_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
+   .C_AXI_WUSER_WIDTH           (C_AXI_WUSER_WIDTH)
+    ) write_data_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (In)
+    .cmd_w_valid                (cmd_w_valid),
+    .cmd_w_check                (cmd_w_check),
+    .cmd_w_id                   (cmd_w_id),
+    .cmd_w_ready                (cmd_w_ready),
+    
+    // Command Interface (Out)
+    .cmd_b_push                 (cmd_b_push),
+    .cmd_b_error                (cmd_b_error),
+    .cmd_b_id                   (cmd_b_id),
+    .cmd_b_full                 (cmd_b_full),
+    
+    // Slave Interface Write Data Ports
+    .S_AXI_WID                  (S_AXI_WID),
+    .S_AXI_WDATA                (S_AXI_WDATA),
+    .S_AXI_WSTRB                (S_AXI_WSTRB),
+    .S_AXI_WLAST                (S_AXI_WLAST),
+    .S_AXI_WUSER                (S_AXI_WUSER),
+    .S_AXI_WVALID               (S_AXI_WVALID),
+    .S_AXI_WREADY               (S_AXI_WREADY),
+    
+    // Master Interface Write Data Ports
+    .M_AXI_WID                  (M_AXI_WID),
+    .M_AXI_WDATA                (M_AXI_WDATA),
+    .M_AXI_WSTRB                (M_AXI_WSTRB),
+    .M_AXI_WLAST                (M_AXI_WLAST),
+    .M_AXI_WUSER                (M_AXI_WUSER),
+    .M_AXI_WVALID               (M_AXI_WVALID),
+    .M_AXI_WREADY               (M_AXI_WREADY)
+   );
+   
+  // Write Response channel.
+  processing_system7_v5_5_b_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_BUSER_WIDTH           (C_AXI_BUSER_WIDTH),
+   .C_FIFO_DEPTH_LOG            (C_FIFO_DEPTH_LOG)
+    ) write_response_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (In)
+    .cmd_b_push                 (cmd_b_push),
+    .cmd_b_error                (cmd_b_error),
+    .cmd_b_id                   (cmd_b_id),
+    .cmd_b_full                 (cmd_b_full),
+    .cmd_b_addr                 (cmd_b_addr),
+    .cmd_b_ready                (cmd_b_ready),
+    
+    // Slave Interface Write Response Ports
+    .S_AXI_BID                  (S_AXI_BID),
+    .S_AXI_BRESP                (S_AXI_BRESP),
+    .S_AXI_BUSER                (S_AXI_BUSER),
+    .S_AXI_BVALID               (S_AXI_BVALID),
+    .S_AXI_BREADY               (S_AXI_BREADY),
+    
+    // Master Interface Write Response Ports
+    .M_AXI_BID                  (M_AXI_BID),
+    .M_AXI_BRESP                (M_AXI_BRESP),
+    .M_AXI_BUSER                (M_AXI_BUSER),
+    .M_AXI_BVALID               (M_AXI_BVALID),
+    .M_AXI_BREADY               (M_AXI_BREADY),
+    
+    // Trigger detection
+    .ERROR_TRIGGER              (ERROR_TRIGGER),
+    .ERROR_TRANSACTION_ID       (ERROR_TRANSACTION_ID)
+   );
+  
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Read Channels (AR/R)
+  /////////////////////////////////////////////////////////////////////////////
+  // Read Address Port
+  assign M_AXI_ARID     = S_AXI_ARID;
+  assign M_AXI_ARADDR   = S_AXI_ARADDR;
+  assign M_AXI_ARLEN    = S_AXI_ARLEN;
+  assign M_AXI_ARSIZE   = S_AXI_ARSIZE;
+  assign M_AXI_ARBURST  = S_AXI_ARBURST;
+  assign M_AXI_ARLOCK   = S_AXI_ARLOCK;
+  assign M_AXI_ARCACHE  = S_AXI_ARCACHE;
+  assign M_AXI_ARPROT   = S_AXI_ARPROT;
+  assign M_AXI_ARUSER   = S_AXI_ARUSER;
+  assign M_AXI_ARVALID  = S_AXI_ARVALID;
+  assign S_AXI_ARREADY  = M_AXI_ARREADY;
+   
+  // Read Data Port
+  assign S_AXI_RID      = M_AXI_RID;
+  assign S_AXI_RDATA    = M_AXI_RDATA;
+  assign S_AXI_RRESP    = M_AXI_RRESP;
+  assign S_AXI_RLAST    = M_AXI_RLAST;
+  assign S_AXI_RUSER    = M_AXI_RUSER;
+  assign S_AXI_RVALID   = M_AXI_RVALID;
+  assign M_AXI_RREADY   = S_AXI_RREADY;
+  
+  
+endmodule
+`default_nettype wire
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:57:55 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top design_1_auto_pc_0 -prefix
+//               design_1_auto_pc_0_ design_1_auto_pc_0_stub.v
+// Design      : design_1_auto_pc_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4"" *)
+module design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr, 
+  s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, 
+  s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, 
+  s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, 
+  s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, 
+  s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, 
+  s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid, 
+  m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp, 
+  m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready, 
+  m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin=""aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready"" */;
+  input aclk;
+  input aresetn;
+  input [11:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [3:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awqos;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [11:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wlast;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [11:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [11:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [3:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arqos;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [11:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rlast;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output [31:0]m_axi_awaddr;
+  output [2:0]m_axi_awprot;
+  output m_axi_awvalid;
+  input m_axi_awready;
+  output [31:0]m_axi_wdata;
+  output [3:0]m_axi_wstrb;
+  output m_axi_wvalid;
+  input m_axi_wready;
+  input [1:0]m_axi_bresp;
+  input m_axi_bvalid;
+  output m_axi_bready;
+  output [31:0]m_axi_araddr;
+  output [2:0]m_axi_arprot;
+  output m_axi_arvalid;
+  input m_axi_arready;
+  input [31:0]m_axi_rdata;
+  input [1:0]m_axi_rresp;
+  input m_axi_rvalid;
+  output m_axi_rready;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Tue Feb 14 01:38:43 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               D:/Work/vivado/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module design_1_processing_system7_0_0
+   (GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    SDIO0_WP,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    FCLK_CLK0,
+    FCLK_RESET0_N,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I"" *) input [63:0]GPIO_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O"" *) output [63:0]GPIO_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T"" *) output [63:0]GPIO_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *) input SDIO0_WP;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *) output [1:0]USB0_PORT_INDCTL;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *) output USB0_VBUS_PWRSELECT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *) input USB0_VBUS_PWRFAULT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *) output M_AXI_GP0_ARVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *) output M_AXI_GP0_AWVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *) output M_AXI_GP0_BREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *) output M_AXI_GP0_RREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *) output M_AXI_GP0_WLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *) output M_AXI_GP0_WVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *) output [11:0]M_AXI_GP0_ARID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *) output [11:0]M_AXI_GP0_AWID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *) output [11:0]M_AXI_GP0_WID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *) output [1:0]M_AXI_GP0_ARBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *) output [1:0]M_AXI_GP0_ARLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *) output [2:0]M_AXI_GP0_ARSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *) output [1:0]M_AXI_GP0_AWBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *) output [1:0]M_AXI_GP0_AWLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *) output [2:0]M_AXI_GP0_AWSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *) output [2:0]M_AXI_GP0_ARPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *) output [2:0]M_AXI_GP0_AWPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *) output [31:0]M_AXI_GP0_ARADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *) output [31:0]M_AXI_GP0_AWADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *) output [31:0]M_AXI_GP0_WDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *) output [3:0]M_AXI_GP0_ARCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *) output [3:0]M_AXI_GP0_ARLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *) output [3:0]M_AXI_GP0_ARQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *) output [3:0]M_AXI_GP0_AWCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *) output [3:0]M_AXI_GP0_AWLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *) output [3:0]M_AXI_GP0_AWQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *) output [3:0]M_AXI_GP0_WSTRB;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *) input M_AXI_GP0_ACLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *) input M_AXI_GP0_ARREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *) input M_AXI_GP0_AWREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *) input M_AXI_GP0_BVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *) input M_AXI_GP0_RLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *) input M_AXI_GP0_RVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *) input M_AXI_GP0_WREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *) input [11:0]M_AXI_GP0_BID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *) input [11:0]M_AXI_GP0_RID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *) input [1:0]M_AXI_GP0_BRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *) input [1:0]M_AXI_GP0_RRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *) input [31:0]M_AXI_GP0_RDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *) output FCLK_CLK0;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *) output FCLK_RESET0_N;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *) inout [53:0]MIO;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *) inout DDR_CAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *) inout DDR_CKE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *) inout DDR_Clk_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *) inout DDR_Clk;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *) inout DDR_CS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *) inout DDR_DRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *) inout DDR_ODT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *) inout DDR_RAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *) inout DDR_WEB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *) inout [2:0]DDR_BankAddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *) inout [14:0]DDR_Addr;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *) inout DDR_VRN;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *) inout DDR_VRP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *) inout [3:0]DDR_DM;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *) inout [31:0]DDR_DQ;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *) inout [3:0]DDR_DQS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *) inout [3:0]DDR_DQS;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *) inout PS_SRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *) inout PS_CLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *) inout PS_PORB;
+
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire FCLK_CLK0;
+  wire FCLK_RESET0_N;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [2:0]M_AXI_GP0_ARSIZE;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [2:0]M_AXI_GP0_AWSIZE;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_WP;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+  wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+  wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+  wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+  wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+  wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+  wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO0_LED_UNCONNECTED;
+  wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO1_LED_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+  wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+  wire NLW_inst_TRACE_CTL_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+  wire NLW_inst_UART0_DTRN_UNCONNECTED;
+  wire NLW_inst_UART0_RTSN_UNCONNECTED;
+  wire NLW_inst_UART0_TX_UNCONNECTED;
+  wire NLW_inst_UART1_DTRN_UNCONNECTED;
+  wire NLW_inst_UART1_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_TX_UNCONNECTED;
+  wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+  wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+  wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+  wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+  wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+PULLUP pullup_MIO_0
+       (.O(MIO[0]));
+PULLUP pullup_MIO_9
+       (.O(MIO[9]));
+PULLUP pullup_MIO_10
+       (.O(MIO[10]));
+PULLUP pullup_MIO_11
+       (.O(MIO[11]));
+PULLUP pullup_MIO_12
+       (.O(MIO[12]));
+PULLUP pullup_MIO_13
+       (.O(MIO[13]));
+PULLUP pullup_MIO_14
+       (.O(MIO[14]));
+PULLUP pullup_MIO_15
+       (.O(MIO[15]));
+PULLUP pullup_MIO_46
+       (.O(MIO[46]));
+
+  (* C_DM_WIDTH = ""4"" *) 
+  (* C_DQS_WIDTH = ""4"" *) 
+  (* C_DQ_WIDTH = ""32"" *) 
+  (* C_EMIO_GPIO_WIDTH = ""64"" *) 
+  (* C_EN_EMIO_ENET0 = ""0"" *) 
+  (* C_EN_EMIO_ENET1 = ""0"" *) 
+  (* C_EN_EMIO_PJTAG = ""0"" *) 
+  (* C_EN_EMIO_TRACE = ""0"" *) 
+  (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+  (* C_FCLK_CLK1_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK2_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+  (* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+  (* C_INCLUDE_TRACE_BUFFER = ""0"" *) 
+  (* C_IRQ_F2P_MODE = ""DIRECT"" *) 
+  (* C_MIO_PRIMITIVE = ""54"" *) 
+  (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_NUM_F2P_INTR_INPUTS = ""1"" *) 
+  (* C_PACKAGE_NAME = ""clg400"" *) 
+  (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+  (* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+  (* C_S_AXI_GP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP3_ID_WIDTH = ""6"" *) 
+  (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) 
+  (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+  (* C_TRACE_INTERNAL_WIDTH = ""2"" *) 
+  (* C_TRACE_PIPELINE_WIDTH = ""8"" *) 
+  (* C_USE_AXI_NONSECURE = ""0"" *) 
+  (* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) 
+  (* C_USE_M_AXI_GP0 = ""1"" *) 
+  (* C_USE_M_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_ACP = ""0"" *) 
+  (* C_USE_S_AXI_GP0 = ""0"" *) 
+  (* C_USE_S_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP0 = ""0"" *) 
+  (* C_USE_S_AXI_HP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP2 = ""0"" *) 
+  (* C_USE_S_AXI_HP3 = ""0"" *) 
+  (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) 
+  (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+  (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+  design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
+       (.CAN0_PHY_RX(1\'b0),
+        .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+        .CAN1_PHY_RX(1\'b0),
+        .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+        .Core0_nFIQ(1\'b0),
+        .Core0_nIRQ(1\'b0),
+        .Core1_nFIQ(1\'b0),
+        .Core1_nIRQ(1\'b0),
+        .DDR_ARB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .DDR_Addr(DDR_Addr),
+        .DDR_BankAddr(DDR_BankAddr),
+        .DDR_CAS_n(DDR_CAS_n),
+        .DDR_CKE(DDR_CKE),
+        .DDR_CS_n(DDR_CS_n),
+        .DDR_Clk(DDR_Clk),
+        .DDR_Clk_n(DDR_Clk_n),
+        .DDR_DM(DDR_DM),
+        .DDR_DQ(DDR_DQ),
+        .DDR_DQS(DDR_DQS),
+        .DDR_DQS_n(DDR_DQS_n),
+        .DDR_DRSTB(DDR_DRSTB),
+        .DDR_ODT(DDR_ODT),
+        .DDR_RAS_n(DDR_RAS_n),
+        .DDR_VRN(DDR_VRN),
+        .DDR_VRP(DDR_VRP),
+        .DDR_WEB(DDR_WEB),
+        .DMA0_ACLK(1\'b0),
+        .DMA0_DAREADY(1\'b0),
+        .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+        .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+        .DMA0_DRLAST(1\'b0),
+        .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+        .DMA0_DRTYPE({1\'b0,1\'b0}),
+        .DMA0_DRVALID(1\'b0),
+        .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+        .DMA1_ACLK(1\'b0),
+        .DMA1_DAREADY(1\'b0),
+        .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+        .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+        .DMA1_DRLAST(1\'b0),
+        .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+        .DMA1_DRTYPE({1\'b0,1\'b0}),
+        .DMA1_DRVALID(1\'b0),
+        .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+        .DMA2_ACLK(1\'b0),
+        .DMA2_DAREADY(1\'b0),
+        .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+        .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+        .DMA2_DRLAST(1\'b0),
+        .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+        .DMA2_DRTYPE({1\'b0,1\'b0}),
+        .DMA2_DRVALID(1\'b0),
+        .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+        .DMA3_ACLK(1\'b0),
+        .DMA3_DAREADY(1\'b0),
+        .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+        .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+        .DMA3_DRLAST(1\'b0),
+        .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+        .DMA3_DRTYPE({1\'b0,1\'b0}),
+        .DMA3_DRVALID(1\'b0),
+        .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+        .ENET0_EXT_INTIN(1\'b0),
+        .ENET0_GMII_COL(1\'b0),
+        .ENET0_GMII_CRS(1\'b0),
+        .ENET0_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET0_GMII_RX_CLK(1\'b0),
+        .ENET0_GMII_RX_DV(1\'b0),
+        .ENET0_GMII_RX_ER(1\'b0),
+        .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET0_GMII_TX_CLK(1\'b0),
+        .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+        .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+        .ENET0_MDIO_I(1\'b0),
+        .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+        .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+        .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+        .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+        .ENET1_EXT_INTIN(1\'b0),
+        .ENET1_GMII_COL(1\'b0),
+        .ENET1_GMII_CRS(1\'b0),
+        .ENET1_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET1_GMII_RX_CLK(1\'b0),
+        .ENET1_GMII_RX_DV(1\'b0),
+        .ENET1_GMII_RX_ER(1\'b0),
+        .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET1_GMII_TX_CLK(1\'b0),
+        .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+        .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+        .ENET1_MDIO_I(1\'b0),
+        .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+        .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+        .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+        .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+        .EVENT_EVENTI(1\'b0),
+        .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+        .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+        .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+        .FCLK_CLK0(FCLK_CLK0),
+        .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+        .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+        .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+        .FCLK_CLKTRIG0_N(1\'b0),
+        .FCLK_CLKTRIG1_N(1\'b0),
+        .FCLK_CLKTRIG2_N(1\'b0),
+        .FCLK_CLKTRIG3_N(1\'b0),
+        .FCLK_RESET0_N(FCLK_RESET0_N),
+        .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+        .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+        .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+        .FPGA_IDLE_N(1\'b0),
+        .FTMD_TRACEIN_ATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_CLK(1\'b0),
+        .FTMD_TRACEIN_DATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_VALID(1\'b0),
+        .FTMT_F2P_DEBUG({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+        .FTMT_F2P_TRIG_0(1\'b0),
+        .FTMT_F2P_TRIG_1(1\'b0),
+        .FTMT_F2P_TRIG_2(1\'b0),
+        .FTMT_F2P_TRIG_3(1\'b0),
+        .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+        .FTMT_P2F_TRIGACK_0(1\'b0),
+        .FTMT_P2F_TRIGACK_1(1\'b0),
+        .FTMT_P2F_TRIGACK_2(1\'b0),
+        .FTMT_P2F_TRIGACK_3(1\'b0),
+        .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+        .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+        .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+        .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+        .GPIO_I(GPIO_I),
+        .GPIO_O(GPIO_O),
+        .GPIO_T(GPIO_T),
+        .I2C0_SCL_I(1\'b0),
+        .I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
+        .I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
+        .I2C0_SDA_I(1\'b0),
+        .I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
+        .I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
+        .I2C1_SCL_I(1\'b0),
+        .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+        .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+        .I2C1_SDA_I(1\'b0),
+        .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+        .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+        .IRQ_F2P(1\'b0),
+        .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+        .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+        .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+        .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+        .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+        .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+        .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+        .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+        .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+        .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+        .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+        .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+        .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+        .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+        .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+        .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+        .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+        .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+        .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+        .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+        .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+        .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+        .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+        .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+        .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+        .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+        .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+        .MIO(MIO),
+        .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+        .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+        .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+        .M_AXI_GP1_ACLK(1\'b0),
+        .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+        .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARREADY(1\'b0),
+        .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+        .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWREADY(1\'b0),
+        .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+        .M_AXI_GP1_BID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+        .M_AXI_GP1_BRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_BVALID(1\'b0),
+        .M_AXI_GP1_RDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RLAST(1\'b0),
+        .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+        .M_AXI_GP1_RRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_RVALID(1\'b0),
+        .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+        .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+        .M_AXI_GP1_WREADY(1\'b0),
+        .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+        .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+        .PJTAG_TCK(1\'b0),
+        .PJTAG_TDI(1\'b0),
+        .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+        .PJTAG_TMS(1\'b0),
+        .PS_CLK(PS_CLK),
+        .PS_PORB(PS_PORB),
+        .PS_SRSTB(PS_SRSTB),
+        .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+        .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO0_CDN(1\'b0),
+        .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+        .SDIO0_CLK_FB(1\'b0),
+        .SDIO0_CMD_I(1\'b0),
+        .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+        .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+        .SDIO0_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+        .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+        .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+        .SDIO0_WP(SDIO0_WP),
+        .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+        .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO1_CDN(1\'b0),
+        .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+        .SDIO1_CLK_FB(1\'b0),
+        .SDIO1_CMD_I(1\'b0),
+        .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+        .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+        .SDIO1_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+        .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+        .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+        .SDIO1_WP(1\'b0),
+        .SPI0_MISO_I(1\'b0),
+        .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+        .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+        .SPI0_MOSI_I(1\'b0),
+        .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+        .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+        .SPI0_SCLK_I(1\'b0),
+        .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+        .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+        .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+        .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+        .SPI0_SS_I(1\'b0),
+        .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+        .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+        .SPI1_MISO_I(1\'b0),
+        .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+        .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+        .SPI1_MOSI_I(1\'b0),
+        .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+        .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+        .SPI1_SCLK_I(1\'b0),
+        .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+        .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+        .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+        .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+        .SPI1_SS_I(1\'b0),
+        .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+        .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+        .SRAM_INTIN(1\'b0),
+        .S_AXI_ACP_ACLK(1\'b0),
+        .S_AXI_ACP_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+        .S_AXI_ACP_ARID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+        .S_AXI_ACP_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARVALID(1\'b0),
+        .S_AXI_ACP_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+        .S_AXI_ACP_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWVALID(1\'b0),
+        .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_BREADY(1\'b0),
+        .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+        .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+        .S_AXI_ACP_RREADY(1\'b0),
+        .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+        .S_AXI_ACP_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WLAST(1\'b0),
+        .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+        .S_AXI_ACP_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WVALID(1\'b0),
+        .S_AXI_GP0_ACLK(1\'b0),
+        .S_AXI_GP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+        .S_AXI_GP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+        .S_AXI_GP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARVALID(1\'b0),
+        .S_AXI_GP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+        .S_AXI_GP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWVALID(1\'b0),
+        .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_BREADY(1\'b0),
+        .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+        .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+        .S_AXI_GP0_RREADY(1\'b0),
+        .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+        .S_AXI_GP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WLAST(1\'b0),
+        .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+        .S_AXI_GP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WVALID(1\'b0),
+        .S_AXI_GP1_ACLK(1\'b0),
+        .S_AXI_GP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+        .S_AXI_GP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+        .S_AXI_GP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARVALID(1\'b0),
+        .S_AXI_GP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+        .S_AXI_GP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWVALID(1\'b0),
+        .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_BREADY(1\'b0),
+        .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+        .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+        .S_AXI_GP1_RREADY(1\'b0),
+        .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+        .S_AXI_GP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WLAST(1\'b0),
+        .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+        .S_AXI_GP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WVALID(1\'b0),
+        .S_AXI_HP0_ACLK(1\'b0),
+        .S_AXI_HP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+        .S_AXI_HP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+        .S_AXI_HP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARVALID(1\'b0),
+        .S_AXI_HP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+        .S_AXI_HP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWVALID(1\'b0),
+        .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_BREADY(1\'b0),
+        .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+        .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP0_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+        .S_AXI_HP0_RREADY(1\'b0),
+        .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+        .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WLAST(1\'b0),
+        .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+        .S_AXI_HP0_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WVALID(1\'b0),
+        .S_AXI_HP1_ACLK(1\'b0),
+        .S_AXI_HP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+        .S_AXI_HP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+        .S_AXI_HP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARVALID(1\'b0),
+        .S_AXI_HP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+        .S_AXI_HP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWVALID(1\'b0),
+        .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_BREADY(1\'b0),
+        .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+        .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP1_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+        .S_AXI_HP1_RREADY(1\'b0),
+        .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+        .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WLAST(1\'b0),
+        .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+        .S_AXI_HP1_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WVALID(1\'b0),
+        .S_AXI_HP2_ACLK(1\'b0),
+        .S_AXI_HP2_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+        .S_AXI_HP2_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+        .S_AXI_HP2_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARVALID(1\'b0),
+        .S_AXI_HP2_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+        .S_AXI_HP2_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWVALID(1\'b0),
+        .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_BREADY(1\'b0),
+        .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+        .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP2_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+        .S_AXI_HP2_RREADY(1\'b0),
+        .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+        .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WLAST(1\'b0),
+        .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+        .S_AXI_HP2_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WVALID(1\'b0),
+        .S_AXI_HP3_ACLK(1\'b0),
+        .S_AXI_HP3_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+        .S_AXI_HP3_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+        .S_AXI_HP3_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARVALID(1\'b0),
+        .S_AXI_HP3_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+        .S_AXI_HP3_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWVALID(1\'b0),
+        .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_BREADY(1\'b0),
+        .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+        .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP3_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+        .S_AXI_HP3_RREADY(1\'b0),
+        .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+        .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WLAST(1\'b0),
+        .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
+        .S_AXI_HP3_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WVALID(1\'b0),
+        .TRACE_CLK(1\'b0),
+        .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+        .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
+        .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+        .TTC0_CLK0_IN(1\'b0),
+        .TTC0_CLK1_IN(1\'b0),
+        .TTC0_CLK2_IN(1\'b0),
+        .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+        .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+        .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+        .TTC1_CLK0_IN(1\'b0),
+        .TTC1_CLK1_IN(1\'b0),
+        .TTC1_CLK2_IN(1\'b0),
+        .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+        .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+        .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+        .UART0_CTSN(1\'b0),
+        .UART0_DCDN(1\'b0),
+        .UART0_DSRN(1\'b0),
+        .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
+        .UART0_RIN(1\'b0),
+        .UART0_RTSN('b'NLW_inst_UART0_RTSN_UNCONNECTED),
+        .UART0_RX(1\'b1),
+        .UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
+        .UART1_CTSN(1\'b0),
+        .UART1_DCDN(1\'b0),
+        .UART1_DSRN(1\'b0),
+        .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+        .UART1_RIN(1\'b0),
+        .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+        .UART1_RX(1\'b1),
+        .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+        .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+        .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+        .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+        .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+        .USB1_VBUS_PWRFAULT(1\'b0),
+        .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+        .WDT_CLK_IN(1\'b0),
+        .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = ""4"" *) (* C_DQS_WIDTH = ""4"" *) (* C_DQ_WIDTH = ""32"" *) 
+(* C_EMIO_GPIO_WIDTH = ""64"" *) (* C_EN_EMIO_ENET0 = ""0"" *) (* C_EN_EMIO_ENET1 = ""0"" *) 
+(* C_EN_EMIO_PJTAG = ""0"" *) (* C_EN_EMIO_TRACE = ""0"" *) (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+(* C_FCLK_CLK1_BUF = ""FALSE"" *) (* C_FCLK_CLK2_BUF = ""FALSE"" *) (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+(* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+(* C_INCLUDE_TRACE_BUFFER = ""0"" *) (* C_IRQ_F2P_MODE = ""DIRECT"" *) (* C_MIO_PRIMITIVE = ""54"" *) 
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+(* C_NUM_F2P_INTR_INPUTS = ""1"" *) (* C_PACKAGE_NAME = ""clg400"" *) (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+(* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+(* C_S_AXI_GP0_ID_WIDTH = ""6"" *) (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP0_ID_WIDTH = ""6"" *) (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+(* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP3_ID_WIDTH = ""6"" *) (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+(* C_TRACE_INTERNAL_WIDTH = ""2"" *) (* C_TRACE_PIPELINE_WIDTH = ""8"" *) (* C_USE_AXI_NONSECURE = ""0"" *) 
+(* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) (* C_USE_M_AXI_GP0 = ""1"" *) (* C_USE_M_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_ACP = ""0"" *) (* C_USE_S_AXI_GP0 = ""0"" *) (* C_USE_S_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_HP0 = ""0"" *) (* C_USE_S_AXI_HP1 = ""0"" *) (* C_USE_S_AXI_HP2 = ""0"" *) 
+(* C_USE_S_AXI_HP3 = ""0"" *) (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) (* ORIG_REF_NAME = ""processing_system7_v5_5_processing_system7"" *) 
+(* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7
+   (CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TDI,
+    PJTAG_TDO,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    TRACE_CLK_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_PORT_INDCTL,
+    USB1_VBUS_PWRSELECT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARESETN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARESETN,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARESETN,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARESETN,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_ARESETN,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARESETN,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARESETN,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARESETN,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARESETN,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_RSTN,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_RSTN,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_RSTN,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_RSTN,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA3_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DRTYPE,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG_0,
+    FTMT_F2P_TRIGACK_0,
+    FTMT_F2P_TRIG_1,
+    FTMT_F2P_TRIGACK_1,
+    FTMT_F2P_TRIG_2,
+    FTMT_F2P_TRIGACK_2,
+    FTMT_F2P_TRIG_3,
+    FTMT_F2P_TRIGACK_3,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK_0,
+    FTMT_P2F_TRIG_0,
+    FTMT_P2F_TRIGACK_1,
+    FTMT_P2F_TRIG_1,
+    FTMT_P2F_TRIGACK_2,
+    FTMT_P2F_TRIG_2,
+    FTMT_P2F_TRIGACK_3,
+    FTMT_P2F_TRIG_3,
+    FTMT_P2F_DEBUG,
+    FPGA_IDLE_N,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    DDR_ARB,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0]ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input ENET0_EXT_INTIN;
+  input [7:0]ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0]ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input ENET1_EXT_INTIN;
+  input [7:0]ENET1_GMII_RXD;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TDI;
+  output PJTAG_TDO;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0]SDIO0_DATA_I;
+  output [3:0]SDIO0_DATA_O;
+  output [3:0]SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0]SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0]SDIO1_DATA_I;
+  output [3:0]SDIO1_DATA_O;
+  output [3:0]SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0]SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [1:0]TRACE_DATA;
+  output TRACE_CLK_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output [1:0]USB1_PORT_INDCTL;
+  output USB1_VBUS_PWRSELECT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARESETN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARESETN;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [11:0]M_AXI_GP1_ARID;
+  output [11:0]M_AXI_GP1_AWID;
+  output [11:0]M_AXI_GP1_WID;
+  output [1:0]M_AXI_GP1_ARBURST;
+  output [1:0]M_AXI_GP1_ARLOCK;
+  output [2:0]M_AXI_GP1_ARSIZE;
+  output [1:0]M_AXI_GP1_AWBURST;
+  output [1:0]M_AXI_GP1_AWLOCK;
+  output [2:0]M_AXI_GP1_AWSIZE;
+  output [2:0]M_AXI_GP1_ARPROT;
+  output [2:0]M_AXI_GP1_AWPROT;
+  output [31:0]M_AXI_GP1_ARADDR;
+  output [31:0]M_AXI_GP1_AWADDR;
+  output [31:0]M_AXI_GP1_WDATA;
+  output [3:0]M_AXI_GP1_ARCACHE;
+  output [3:0]M_AXI_GP1_ARLEN;
+  output [3:0]M_AXI_GP1_ARQOS;
+  output [3:0]M_AXI_GP1_AWCACHE;
+  output [3:0]M_AXI_GP1_AWLEN;
+  output [3:0]M_AXI_GP1_AWQOS;
+  output [3:0]M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [11:0]M_AXI_GP1_BID;
+  input [11:0]M_AXI_GP1_RID;
+  input [1:0]M_AXI_GP1_BRESP;
+  input [1:0]M_AXI_GP1_RRESP;
+  input [31:0]M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARESETN;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0]S_AXI_GP0_BRESP;
+  output [1:0]S_AXI_GP0_RRESP;
+  output [31:0]S_AXI_GP0_RDATA;
+  output [5:0]S_AXI_GP0_BID;
+  output [5:0]S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0]S_AXI_GP0_ARBURST;
+  input [1:0]S_AXI_GP0_ARLOCK;
+  input [2:0]S_AXI_GP0_ARSIZE;
+  input [1:0]S_AXI_GP0_AWBURST;
+  input [1:0]S_AXI_GP0_AWLOCK;
+  input [2:0]S_AXI_GP0_AWSIZE;
+  input [2:0]S_AXI_GP0_ARPROT;
+  input [2:0]S_AXI_GP0_AWPROT;
+  input [31:0]S_AXI_GP0_ARADDR;
+  input [31:0]S_AXI_GP0_AWADDR;
+  input [31:0]S_AXI_GP0_WDATA;
+  input [3:0]S_AXI_GP0_ARCACHE;
+  input [3:0]S_AXI_GP0_ARLEN;
+  input [3:0]S_AXI_GP0_ARQOS;
+  input [3:0]S_AXI_GP0_AWCACHE;
+  input [3:0]S_AXI_GP0_AWLEN;
+  input [3:0]S_AXI_GP0_AWQOS;
+  input [3:0]S_AXI_GP0_WSTRB;
+  input [5:0]S_AXI_GP0_ARID;
+  input [5:0]S_AXI_GP0_AWID;
+  input [5:0]S_AXI_GP0_WID;
+  output S_AXI_GP1_ARESETN;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0]S_AXI_GP1_BRESP;
+  output [1:0]S_AXI_GP1_RRESP;
+  output [31:0]S_AXI_GP1_RDATA;
+  output [5:0]S_AXI_GP1_BID;
+  output [5:0]S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0]S_AXI_GP1_ARBURST;
+  input [1:0]S_AXI_GP1_ARLOCK;
+  input [2:0]S_AXI_GP1_ARSIZE;
+  input [1:0]S_AXI_GP1_AWBURST;
+  input [1:0]S_AXI_GP1_AWLOCK;
+  input [2:0]S_AXI_GP1_AWSIZE;
+  input [2:0]S_AXI_GP1_ARPROT;
+  input [2:0]S_AXI_GP1_AWPROT;
+  input [31:0]S_AXI_GP1_ARADDR;
+  input [31:0]S_AXI_GP1_AWADDR;
+  input [31:0]S_AXI_GP1_WDATA;
+  input [3:0]S_AXI_GP1_ARCACHE;
+  input [3:0]S_AXI_GP1_ARLEN;
+  input [3:0]S_AXI_GP1_ARQOS;
+  input [3:0]S_AXI_GP1_AWCACHE;
+  input [3:0]S_AXI_GP1_AWLEN;
+  input [3:0]S_AXI_GP1_AWQOS;
+  input [3:0]S_AXI_GP1_WSTRB;
+  input [5:0]S_AXI_GP1_ARID;
+  input [5:0]S_AXI_GP1_AWID;
+  input [5:0]S_AXI_GP1_WID;
+  output S_AXI_ACP_ARESETN;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0]S_AXI_ACP_BRESP;
+  output [1:0]S_AXI_ACP_RRESP;
+  output [2:0]S_AXI_ACP_BID;
+  output [2:0]S_AXI_ACP_RID;
+  output [63:0]S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0]S_AXI_ACP_ARID;
+  input [2:0]S_AXI_ACP_ARPROT;
+  input [2:0]S_AXI_ACP_AWID;
+  input [2:0]S_AXI_ACP_AWPROT;
+  input [2:0]S_AXI_ACP_WID;
+  input [31:0]S_AXI_ACP_ARADDR;
+  input [31:0]S_AXI_ACP_AWADDR;
+  input [3:0]S_AXI_ACP_ARCACHE;
+  input [3:0]S_AXI_ACP_ARLEN;
+  input [3:0]S_AXI_ACP_ARQOS;
+  input [3:0]S_AXI_ACP_AWCACHE;
+  input [3:0]S_AXI_ACP_AWLEN;
+  input [3:0]S_AXI_ACP_AWQOS;
+  input [1:0]S_AXI_ACP_ARBURST;
+  input [1:0]S_AXI_ACP_ARLOCK;
+  input [2:0]S_AXI_ACP_ARSIZE;
+  input [1:0]S_AXI_ACP_AWBURST;
+  input [1:0]S_AXI_ACP_AWLOCK;
+  input [2:0]S_AXI_ACP_AWSIZE;
+  input [4:0]S_AXI_ACP_ARUSER;
+  input [4:0]S_AXI_ACP_AWUSER;
+  input [63:0]S_AXI_ACP_WDATA;
+  input [7:0]S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARESETN;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0]S_AXI_HP0_BRESP;
+  output [1:0]S_AXI_HP0_RRESP;
+  output [5:0]S_AXI_HP0_BID;
+  output [5:0]S_AXI_HP0_RID;
+  output [63:0]S_AXI_HP0_RDATA;
+  output [7:0]S_AXI_HP0_RCOUNT;
+  output [7:0]S_AXI_HP0_WCOUNT;
+  output [2:0]S_AXI_HP0_RACOUNT;
+  output [5:0]S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0]S_AXI_HP0_ARBURST;
+  input [1:0]S_AXI_HP0_ARLOCK;
+  input [2:0]S_AXI_HP0_ARSIZE;
+  input [1:0]S_AXI_HP0_AWBURST;
+  input [1:0]S_AXI_HP0_AWLOCK;
+  input [2:0]S_AXI_HP0_AWSIZE;
+  input [2:0]S_AXI_HP0_ARPROT;
+  input [2:0]S_AXI_HP0_AWPROT;
+  input [31:0]S_AXI_HP0_ARADDR;
+  input [31:0]S_AXI_HP0_AWADDR;
+  input [3:0]S_AXI_HP0_ARCACHE;
+  input [3:0]S_AXI_HP0_ARLEN;
+  input [3:0]S_AXI_HP0_ARQOS;
+  input [3:0]S_AXI_HP0_AWCACHE;
+  input [3:0]S_AXI_HP0_AWLEN;
+  input [3:0]S_AXI_HP0_AWQOS;
+  input [5:0]S_AXI_HP0_ARID;
+  input [5:0]S_AXI_HP0_AWID;
+  input [5:0]S_AXI_HP0_WID;
+  input [63:0]S_AXI_HP0_WDATA;
+  input [7:0]S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARESETN;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0]S_AXI_HP1_BRESP;
+  output [1:0]S_AXI_HP1_RRESP;
+  output [5:0]S_AXI_HP1_BID;
+  output [5:0]S_AXI_HP1_RID;
+  output [63:0]S_AXI_HP1_RDATA;
+  output [7:0]S_AXI_HP1_RCOUNT;
+  output [7:0]S_AXI_HP1_WCOUNT;
+  output [2:0]S_AXI_HP1_RACOUNT;
+  output [5:0]S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0]S_AXI_HP1_ARBURST;
+  input [1:0]S_AXI_HP1_ARLOCK;
+  input [2:0]S_AXI_HP1_ARSIZE;
+  input [1:0]S_AXI_HP1_AWBURST;
+  input [1:0]S_AXI_HP1_AWLOCK;
+  input [2:0]S_AXI_HP1_AWSIZE;
+  input [2:0]S_AXI_HP1_ARPROT;
+  input [2:0]S_AXI_HP1_AWPROT;
+  input [31:0]S_AXI_HP1_ARADDR;
+  input [31:0]S_AXI_HP1_AWADDR;
+  input [3:0]S_AXI_HP1_ARCACHE;
+  input [3:0]S_AXI_HP1_ARLEN;
+  input [3:0]S_AXI_HP1_ARQOS;
+  input [3:0]S_AXI_HP1_AWCACHE;
+  input [3:0]S_AXI_HP1_AWLEN;
+  input [3:0]S_AXI_HP1_AWQOS;
+  input [5:0]S_AXI_HP1_ARID;
+  input [5:0]S_AXI_HP1_AWID;
+  input [5:0]S_AXI_HP1_WID;
+  input [63:0]S_AXI_HP1_WDATA;
+  input [7:0]S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARESETN;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0]S_AXI_HP2_BRESP;
+  output [1:0]S_AXI_HP2_RRESP;
+  output [5:0]S_AXI_HP2_BID;
+  output [5:0]S_AXI_HP2_RID;
+  output [63:0]S_AXI_HP2_RDATA;
+  output [7:0]S_AXI_HP2_RCOUNT;
+  output [7:0]S_AXI_HP2_WCOUNT;
+  output [2:0]S_AXI_HP2_RACOUNT;
+  output [5:0]S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0]S_AXI_HP2_ARBURST;
+  input [1:0]S_AXI_HP2_ARLOCK;
+  input [2:0]S_AXI_HP2_ARSIZE;
+  input [1:0]S_AXI_HP2_AWBURST;
+  input [1:0]S_AXI_HP2_AWLOCK;
+  input [2:0]S_AXI_HP2_AWSIZE;
+  input [2:0]S_AXI_HP2_ARPROT;
+  input [2:0]S_AXI_HP2_AWPROT;
+  input [31:0]S_AXI_HP2_ARADDR;
+  input [31:0]S_AXI_HP2_AWADDR;
+  input [3:0]S_AXI_HP2_ARCACHE;
+  input [3:0]S_AXI_HP2_ARLEN;
+  input [3:0]S_AXI_HP2_ARQOS;
+  input [3:0]S_AXI_HP2_AWCACHE;
+  input [3:0]S_AXI_HP2_AWLEN;
+  input [3:0]S_AXI_HP2_AWQOS;
+  input [5:0]S_AXI_HP2_ARID;
+  input [5:0]S_AXI_HP2_AWID;
+  input [5:0]S_AXI_HP2_WID;
+  input [63:0]S_AXI_HP2_WDATA;
+  input [7:0]S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARESETN;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0]S_AXI_HP3_BRESP;
+  output [1:0]S_AXI_HP3_RRESP;
+  output [5:0]S_AXI_HP3_BID;
+  output [5:0]S_AXI_HP3_RID;
+  output [63:0]S_AXI_HP3_RDATA;
+  output [7:0]S_AXI_HP3_RCOUNT;
+  output [7:0]S_AXI_HP3_WCOUNT;
+  output [2:0]S_AXI_HP3_RACOUNT;
+  output [5:0]S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0]S_AXI_HP3_ARBURST;
+  input [1:0]S_AXI_HP3_ARLOCK;
+  input [2:0]S_AXI_HP3_ARSIZE;
+  input [1:0]S_AXI_HP3_AWBURST;
+  input [1:0]S_AXI_HP3_AWLOCK;
+  input [2:0]S_AXI_HP3_AWSIZE;
+  input [2:0]S_AXI_HP3_ARPROT;
+  input [2:0]S_AXI_HP3_AWPROT;
+  input [31:0]S_AXI_HP3_ARADDR;
+  input [31:0]S_AXI_HP3_AWADDR;
+  input [3:0]S_AXI_HP3_ARCACHE;
+  input [3:0]S_AXI_HP3_ARLEN;
+  input [3:0]S_AXI_HP3_ARQOS;
+  input [3:0]S_AXI_HP3_AWCACHE;
+  input [3:0]S_AXI_HP3_AWLEN;
+  input [3:0]S_AXI_HP3_AWQOS;
+  input [5:0]S_AXI_HP3_ARID;
+  input [5:0]S_AXI_HP3_AWID;
+  input [5:0]S_AXI_HP3_WID;
+  input [63:0]S_AXI_HP3_WDATA;
+  input [7:0]S_AXI_HP3_WSTRB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+  input [0:0]IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output [1:0]DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  output DMA0_RSTN;
+  output [1:0]DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  output DMA1_RSTN;
+  output [1:0]DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  output DMA2_RSTN;
+  output [1:0]DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  output DMA3_RSTN;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input DMA3_DRVALID;
+  input [1:0]DMA0_DRTYPE;
+  input [1:0]DMA1_DRTYPE;
+  input [1:0]DMA2_DRTYPE;
+  input [1:0]DMA3_DRTYPE;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input [31:0]FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0]FTMD_TRACEIN_ATID;
+  input FTMT_F2P_TRIG_0;
+  output FTMT_F2P_TRIGACK_0;
+  input FTMT_F2P_TRIG_1;
+  output FTMT_F2P_TRIGACK_1;
+  input FTMT_F2P_TRIG_2;
+  output FTMT_F2P_TRIGACK_2;
+  input FTMT_F2P_TRIG_3;
+  output FTMT_F2P_TRIGACK_3;
+  input [31:0]FTMT_F2P_DEBUG;
+  input FTMT_P2F_TRIGACK_0;
+  output FTMT_P2F_TRIG_0;
+  input FTMT_P2F_TRIGACK_1;
+  output FTMT_P2F_TRIG_1;
+  input FTMT_P2F_TRIGACK_2;
+  output FTMT_P2F_TRIG_2;
+  input FTMT_P2F_TRIGACK_3;
+  output FTMT_P2F_TRIG_3;
+  output [31:0]FTMT_P2F_DEBUG;
+  input FPGA_IDLE_N;
+  output EVENT_EVENTO;
+  output [1:0]EVENT_STANDBYWFE;
+  output [1:0]EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  input [3:0]DDR_ARB;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+
+  wire \\<const0> ;
+  wire CAN0_PHY_RX;
+  wire CAN0_PHY_TX;
+  wire CAN1_PHY_RX;
+  wire CAN1_PHY_TX;
+  wire Core0_nFIQ;
+  wire Core0_nIRQ;
+  wire Core1_nFIQ;
+  wire Core1_nIRQ;
+  wire [3:0]DDR_ARB;
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire DMA0_ACLK;
+  wire DMA0_DAREADY;
+  wire [1:0]DMA0_DATYPE;
+  wire DMA0_DAVALID;
+  wire DMA0_DRLAST;
+  wire DMA0_DRREADY;
+  wire [1:0]DMA0_DRTYPE;
+  wire DMA0_DRVALID;
+  wire DMA0_RSTN;
+  wire DMA1_ACLK;
+  wire DMA1_DAREADY;
+  wire [1:0]DMA1_DATYPE;
+  wire DMA1_DAVALID;
+  wire DMA1_DRLAST;
+  wire DMA1_DRREADY;
+  wire [1:0]DMA1_DRTYPE;
+  wire DMA1_DRVALID;
+  wire DMA1_RSTN;
+  wire DMA2_ACLK;
+  wire DMA2_DAREADY;
+  wire [1:0]DMA2_DATYPE;
+  wire DMA2_DAVALID;
+  wire DMA2_DRLAST;
+  wire DMA2_DRREADY;
+  wire [1:0]DMA2_DRTYPE;
+  wire DMA2_DRVALID;
+  wire DMA2_RSTN;
+  wire DMA3_ACLK;
+  wire DMA3_DAREADY;
+  wire [1:0]DMA3_DATYPE;
+  wire DMA3_DAVALID;
+  wire DMA3_DRLAST;
+  wire DMA3_DRREADY;
+  wire [1:0]DMA3_DRTYPE;
+  wire DMA3_DRVALID;
+  wire DMA3_RSTN;
+  wire ENET0_EXT_INTIN;
+  wire ENET0_GMII_RX_CLK;
+  wire ENET0_GMII_TX_CLK;
+  wire ENET0_MDIO_I;
+  wire ENET0_MDIO_MDC;
+  wire ENET0_MDIO_O;
+  wire ENET0_MDIO_T;
+  wire ENET0_MDIO_T_n;
+  wire ENET0_PTP_DELAY_REQ_RX;
+  wire ENET0_PTP_DELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_REQ_RX;
+  wire ENET0_PTP_PDELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_RESP_RX;
+  wire ENET0_PTP_PDELAY_RESP_TX;
+  wire ENET0_PTP_SYNC_FRAME_RX;
+  wire ENET0_PTP_SYNC_FRAME_TX;
+  wire ENET0_SOF_RX;
+  wire ENET0_SOF_TX;
+  wire ENET1_EXT_INTIN;
+  wire ENET1_GMII_RX_CLK;
+  wire ENET1_GMII_TX_CLK;
+  wire ENET1_MDIO_I;
+  wire ENET1_MDIO_MDC;
+  wire ENET1_MDIO_O;
+  wire ENET1_MDIO_T;
+  wire ENET1_MDIO_T_n;
+  wire ENET1_PTP_DELAY_REQ_RX;
+  wire ENET1_PTP_DELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_REQ_RX;
+  wire ENET1_PTP_PDELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_RESP_RX;
+  wire ENET1_PTP_PDELAY_RESP_TX;
+  wire ENET1_PTP_SYNC_FRAME_RX;
+  wire ENET1_PTP_SYNC_FRAME_TX;
+  wire ENET1_SOF_RX;
+  wire ENET1_SOF_TX;
+  wire EVENT_EVENTI;
+  wire EVENT_EVENTO;
+  wire [1:0]EVENT_STANDBYWFE;
+  wire [1:0]EVENT_STANDBYWFI;
+  wire FCLK_CLK0;
+  wire FCLK_CLK1;
+  wire FCLK_CLK2;
+  wire FCLK_CLK3;
+  wire [0:0]FCLK_CLK_unbuffered;
+  wire FCLK_RESET0_N;
+  wire FCLK_RESET1_N;
+  wire FCLK_RESET2_N;
+  wire FCLK_RESET3_N;
+  wire FPGA_IDLE_N;
+  wire FTMD_TRACEIN_CLK;
+  wire [31:0]FTMT_F2P_DEBUG;
+  wire FTMT_F2P_TRIGACK_0;
+  wire FTMT_F2P_TRIGACK_1;
+  wire FTMT_F2P_TRIGACK_2;
+  wire FTMT_F2P_TRIGACK_3;
+  wire FTMT_F2P_TRIG_0;
+  wire FTMT_F2P_TRIG_1;
+  wire FTMT_F2P_TRIG_2;
+  wire FTMT_F2P_TRIG_3;
+  wire [31:0]FTMT_P2F_DEBUG;
+  wire FTMT_P2F_TRIGACK_0;
+  wire FTMT_P2F_TRIGACK_1;
+  wire FTMT_P2F_TRIGACK_2;
+  wire FTMT_P2F_TRIGACK_3;
+  wire FTMT_P2F_TRIG_0;
+  wire FTMT_P2F_TRIG_1;
+  wire FTMT_P2F_TRIG_2;
+  wire FTMT_P2F_TRIG_3;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SCL_T_n;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire I2C0_SDA_T_n;
+  wire I2C1_SCL_I;
+  wire I2C1_SCL_O;
+  wire I2C1_SCL_T;
+  wire I2C1_SCL_T_n;
+  wire I2C1_SDA_I;
+  wire I2C1_SDA_O;
+  wire I2C1_SDA_T;
+  wire I2C1_SDA_T_n;
+  wire [0:0]IRQ_F2P;
+  wire IRQ_P2F_CAN0;
+  wire IRQ_P2F_CAN1;
+  wire IRQ_P2F_CTI;
+  wire IRQ_P2F_DMAC0;
+  wire IRQ_P2F_DMAC1;
+  wire IRQ_P2F_DMAC2;
+  wire IRQ_P2F_DMAC3;
+  wire IRQ_P2F_DMAC4;
+  wire IRQ_P2F_DMAC5;
+  wire IRQ_P2F_DMAC6;
+  wire IRQ_P2F_DMAC7;
+  wire IRQ_P2F_DMAC_ABORT;
+  wire IRQ_P2F_ENET0;
+  wire IRQ_P2F_ENET1;
+  wire IRQ_P2F_ENET_WAKE0;
+  wire IRQ_P2F_ENET_WAKE1;
+  wire IRQ_P2F_GPIO;
+  wire IRQ_P2F_I2C0;
+  wire IRQ_P2F_I2C1;
+  wire IRQ_P2F_QSPI;
+  wire IRQ_P2F_SDIO0;
+  wire IRQ_P2F_SDIO1;
+  wire IRQ_P2F_SMC;
+  wire IRQ_P2F_SPI0;
+  wire IRQ_P2F_SPI1;
+  wire IRQ_P2F_UART0;
+  wire IRQ_P2F_UART1;
+  wire IRQ_P2F_USB0;
+  wire IRQ_P2F_USB1;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire M_AXI_GP0_ARESETN;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [1:0]\\^M_AXI_GP0_ARSIZE ;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [1:0]\\^M_AXI_GP0_AWSIZE ;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire M_AXI_GP1_ACLK;
+  wire [31:0]M_AXI_GP1_ARADDR;
+  wire [1:0]M_AXI_GP1_ARBURST;
+  wire [3:0]M_AXI_GP1_ARCACHE;
+  wire M_AXI_GP1_ARESETN;
+  wire [11:0]M_AXI_GP1_ARID;
+  wire [3:0]M_AXI_GP1_ARLEN;
+  wire [1:0]M_AXI_GP1_ARLOCK;
+  wire [2:0]M_AXI_GP1_ARPROT;
+  wire [3:0]M_AXI_GP1_ARQOS;
+  wire M_AXI_GP1_ARREADY;
+  wire [1:0]\\^M_AXI_GP1_ARSIZE ;
+  wire M_AXI_GP1_ARVALID;
+  wire [31:0]M_AXI_GP1_AWADDR;
+  wire [1:0]M_AXI_GP1_AWBURST;
+  wire [3:0]M_AXI_GP1_AWCACHE;
+  wire [11:0]M_AXI_GP1_AWID;
+  wire [3:0]M_AXI_GP1_AWLEN;
+  wire [1:0]M_AXI_GP1_AWLOCK;
+  wire [2:0]M_AXI_GP1_AWPROT;
+  wire [3:0]M_AXI_GP1_AWQOS;
+  wire M_AXI_GP1_AWREADY;
+  wire [1:0]\\^M_AXI_GP1_AWSIZE ;
+  wire M_AXI_GP1_AWVALID;
+  wire [11:0]M_AXI_GP1_BID;
+  wire M_AXI_GP1_BREADY;
+  wire [1:0]M_AXI_GP1_BRESP;
+  wire M_AXI_GP1_BVALID;
+  wire [31:0]M_AXI_GP1_RDATA;
+  wire [11:0]M_AXI_GP1_RID;
+  wire M_AXI_GP1_RLAST;
+  wire M_AXI_GP1_RREADY;
+  wire [1:0]M_AXI_GP1_RRESP;
+  wire M_AXI_GP1_RVALID;
+  wire [31:0]M_AXI_GP1_WDATA;
+  wire [11:0]M_AXI_GP1_WID;
+  wire M_AXI_GP1_WLAST;
+  wire M_AXI_GP1_WREADY;
+  wire [3:0]M_AXI_GP1_WSTRB;
+  wire M_AXI_GP1_WVALID;
+  wire PJTAG_TCK;
+  wire PJTAG_TDI;
+  wire PJTAG_TMS;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_BUSPOW;
+  wire [2:0]SDIO0_BUSVOLT;
+  wire SDIO0_CDN;
+  wire SDIO0_CLK;
+  wire SDIO0_CLK_FB;
+  wire SDIO0_CMD_I;
+  wire SDIO0_CMD_O;
+  wire SDIO0_CMD_T;
+  wire SDIO0_CMD_T_n;
+  wire [3:0]SDIO0_DATA_I;
+  wire [3:0]SDIO0_DATA_O;
+  wire [3:0]SDIO0_DATA_T;
+  wire [3:0]SDIO0_DATA_T_n;
+  wire SDIO0_LED;
+  wire SDIO0_WP;
+  wire SDIO1_BUSPOW;
+  wire [2:0]SDIO1_BUSVOLT;
+  wire SDIO1_CDN;
+  wire SDIO1_CLK;
+  wire SDIO1_CLK_FB;
+  wire SDIO1_CMD_I;
+  wire SDIO1_CMD_O;
+  wire SDIO1_CMD_T;
+  wire SDIO1_CMD_T_n;
+  wire [3:0]SDIO1_DATA_I;
+  wire [3:0]SDIO1_DATA_O;
+  wire [3:0]SDIO1_DATA_T;
+  wire [3:0]SDIO1_DATA_T_n;
+  wire SDIO1_LED;
+  wire SDIO1_WP;
+  wire SPI0_MISO_I;
+  wire SPI0_MISO_O;
+  wire SPI0_MISO_T;
+  wire SPI0_MISO_T_n;
+  wire SPI0_MOSI_I;
+  wire SPI0_MOSI_O;
+  wire SPI0_MOSI_T;
+  wire SPI0_MOSI_T_n;
+  wire SPI0_SCLK_I;
+  wire SPI0_SCLK_O;
+  wire SPI0_SCLK_T;
+  wire SPI0_SCLK_T_n;
+  wire SPI0_SS1_O;
+  wire SPI0_SS2_O;
+  wire SPI0_SS_I;
+  wire SPI0_SS_O;
+  wire SPI0_SS_T;
+  wire SPI0_SS_T_n;
+  wire SPI1_MISO_I;
+  wire SPI1_MISO_O;
+  wire SPI1_MISO_T;
+  wire SPI1_MISO_T_n;
+  wire SPI1_MOSI_I;
+  wire SPI1_MOSI_O;
+  wire SPI1_MOSI_T;
+  wire SPI1_MOSI_T_n;
+  wire SPI1_SCLK_I;
+  wire SPI1_SCLK_O;
+  wire SPI1_SCLK_T;
+  wire SPI1_SCLK_T_n;
+  wire SPI1_SS1_O;
+  wire SPI1_SS2_O;
+  wire SPI1_SS_I;
+  wire SPI1_SS_O;
+  wire SPI1_SS_T;
+  wire SPI1_SS_T_n;
+  wire SRAM_INTIN;
+  wire S_AXI_ACP_ACLK;
+  wire [31:0]S_AXI_ACP_ARADDR;
+  wire [1:0]S_AXI_ACP_ARBURST;
+  wire [3:0]S_AXI_ACP_ARCACHE;
+  wire S_AXI_ACP_ARESETN;
+  wire [2:0]S_AXI_ACP_ARID;
+  wire [3:0]S_AXI_ACP_ARLEN;
+  wire [1:0]S_AXI_ACP_ARLOCK;
+  wire [2:0]S_AXI_ACP_ARPROT;
+  wire [3:0]S_AXI_ACP_ARQOS;
+  wire S_AXI_ACP_ARREADY;
+  wire [2:0]S_AXI_ACP_ARSIZE;
+  wire [4:0]S_AXI_ACP_ARUSER;
+  wire S_AXI_ACP_ARVALID;
+  wire [31:0]S_AXI_ACP_AWADDR;
+  wire [1:0]S_AXI_ACP_AWBURST;
+  wire [3:0]S_AXI_ACP_AWCACHE;
+  wire [2:0]S_AXI_ACP_AWID;
+  wire [3:0]S_AXI_ACP_AWLEN;
+  wire [1:0]S_AXI_ACP_AWLOCK;
+  wire [2:0]S_AXI_ACP_AWPROT;
+  wire [3:0]S_AXI_ACP_AWQOS;
+  wire S_AXI_ACP_AWREADY;
+  wire [2:0]S_AXI_ACP_AWSIZE;
+  wire [4:0]S_AXI_ACP_AWUSER;
+  wire S_AXI_ACP_AWVALID;
+  wire [2:0]S_AXI_ACP_BID;
+  wire S_AXI_ACP_BREADY;
+  wire [1:0]S_AXI_ACP_BRESP;
+  wire S_AXI_ACP_BVALID;
+  wire [63:0]S_AXI_ACP_RDATA;
+  wire [2:0]S_AXI_ACP_RID;
+  wire S_AXI_ACP_RLAST;
+  wire S_AXI_ACP_RREADY;
+  wire [1:0]S_AXI_ACP_RRESP;
+  wire S_AXI_ACP_RVALID;
+  wire [63:0]S_AXI_ACP_WDATA;
+  wire [2:0]S_AXI_ACP_WID;
+  wire S_AXI_ACP_WLAST;
+  wire S_AXI_ACP_WREADY;
+  wire [7:0]S_AXI_ACP_WSTRB;
+  wire S_AXI_ACP_WVALID;
+  wire S_AXI_GP0_ACLK;
+  wire [31:0]S_AXI_GP0_ARADDR;
+  wire [1:0]S_AXI_GP0_ARBURST;
+  wire [3:0]S_AXI_GP0_ARCACHE;
+  wire S_AXI_GP0_ARESETN;
+  wire [5:0]S_AXI_GP0_ARID;
+  wire [3:0]S_AXI_GP0_ARLEN;
+  wire [1:0]S_AXI_GP0_ARLOCK;
+  wire [2:0]S_AXI_GP0_ARPROT;
+  wire [3:0]S_AXI_GP0_ARQOS;
+  wire S_AXI_GP0_ARREADY;
+  wire [2:0]S_AXI_GP0_ARSIZE;
+  wire S_AXI_GP0_ARVALID;
+  wire [31:0]S_AXI_GP0_AWADDR;
+  wire [1:0]S_AXI_GP0_AWBURST;
+  wire [3:0]S_AXI_GP0_AWCACHE;
+  wire [5:0]S_AXI_GP0_AWID;
+  wire [3:0]S_AXI_GP0_AWLEN;
+  wire [1:0]S_AXI_GP0_AWLOCK;
+  wire [2:0]S_AXI_GP0_AWPROT;
+  wire [3:0]S_AXI_GP0_AWQOS;
+  wire S_AXI_GP0_AWREADY;
+  wire [2:0]S_AXI_GP0_AWSIZE;
+  wire S_AXI_GP0_AWVALID;
+  wire [5:0]S_AXI_GP0_BID;
+  wire S_AXI_GP0_BREADY;
+  wire [1:0]S_AXI_GP0_BRESP;
+  wire S_AXI_GP0_BVALID;
+  wire [31:0]S_AXI_GP0_RDATA;
+  wire [5:0]S_AXI_GP0_RID;
+  wire S_AXI_GP0_RLAST;
+  wire S_AXI_GP0_RREADY;
+  wire [1:0]S_AXI_GP0_RRESP;
+  wire S_AXI_GP0_RVALID;
+  wire [31:0]S_AXI_GP0_WDATA;
+  wire [5:0]S_AXI_GP0_WID;
+  wire S_AXI_GP0_WLAST;
+  wire S_AXI_GP0_WREADY;
+  wire [3:0]S_AXI_GP0_WSTRB;
+  wire S_AXI_GP0_WVALID;
+  wire S_AXI_GP1_ACLK;
+  wire [31:0]S_AXI_GP1_ARADDR;
+  wire [1:0]S_AXI_GP1_ARBURST;
+  wire [3:0]S_AXI_GP1_ARCACHE;
+  wire S_AXI_GP1_ARESETN;
+  wire [5:0]S_AXI_GP1_ARID;
+  wire [3:0]S_AXI_GP1_ARLEN;
+  wire [1:0]S_AXI_GP1_ARLOCK;
+  wire [2:0]S_AXI_GP1_ARPROT;
+  wire [3:0]S_AXI_GP1_ARQOS;
+  wire S_AXI_GP1_ARREADY;
+  wire [2:0]S_AXI_GP1_ARSIZE;
+  wire S_AXI_GP1_ARVALID;
+  wire [31:0]S_AXI_GP1_AWADDR;
+  wire [1:0]S_AXI_GP1_AWBURST;
+  wire [3:0]S_AXI_GP1_AWCACHE;
+  wire [5:0]S_AXI_GP1_AWID;
+  wire [3:0]S_AXI_GP1_AWLEN;
+  wire [1:0]S_AXI_GP1_AWLOCK;
+  wire [2:0]S_AXI_GP1_AWPROT;
+  wire [3:0]S_AXI_GP1_AWQOS;
+  wire S_AXI_GP1_AWREADY;
+  wire [2:0]S_AXI_GP1_AWSIZE;
+  wire S_AXI_GP1_AWVALID;
+  wire [5:0]S_AXI_GP1_BID;
+  wire S_AXI_GP1_BREADY;
+  wire [1:0]S_AXI_GP1_BRESP;
+  wire S_AXI_GP1_BVALID;
+  wire [31:0]S_AXI_GP1_RDATA;
+  wire [5:0]S_AXI_GP1_RID;
+  wire S_AXI_GP1_RLAST;
+  wire S_AXI_GP1_RREADY;
+  wire [1:0]S_AXI_GP1_RRESP;
+  wire S_AXI_GP1_RVALID;
+  wire [31:0]S_AXI_GP1_WDATA;
+  wire [5:0]S_AXI_GP1_WID;
+  wire S_AXI_GP1_WLAST;
+  wire S_AXI_GP1_WREADY;
+  wire [3:0]S_AXI_GP1_WSTRB;
+  wire S_AXI_GP1_WVALID;
+  wire S_AXI_HP0_ACLK;
+  wire [31:0]S_AXI_HP0_ARADDR;
+  wire [1:0]S_AXI_HP0_ARBURST;
+  wire [3:0]S_AXI_HP0_ARCACHE;
+  wire S_AXI_HP0_ARESETN;
+  wire [5:0]S_AXI_HP0_ARID;
+  wire [3:0]S_AXI_HP0_ARLEN;
+  wire [1:0]S_AXI_HP0_ARLOCK;
+  wire [2:0]S_AXI_HP0_ARPROT;
+  wire [3:0]S_AXI_HP0_ARQOS;
+  wire S_AXI_HP0_ARREADY;
+  wire [2:0]S_AXI_HP0_ARSIZE;
+  wire S_AXI_HP0_ARVALID;
+  wire [31:0]S_AXI_HP0_AWADDR;
+  wire [1:0]S_AXI_HP0_AWBURST;
+  wire [3:0]S_AXI_HP0_AWCACHE;
+  wire [5:0]S_AXI_HP0_AWID;
+  wire [3:0]S_AXI_HP0_AWLEN;
+  wire [1:0]S_AXI_HP0_AWLOCK;
+  wire [2:0]S_AXI_HP0_AWPROT;
+  wire [3:0]S_AXI_HP0_AWQOS;
+  wire S_AXI_HP0_AWREADY;
+  wire [2:0]S_AXI_HP0_AWSIZE;
+  wire S_AXI_HP0_AWVALID;
+  wire [5:0]S_AXI_HP0_BID;
+  wire S_AXI_HP0_BREADY;
+  wire [1:0]S_AXI_HP0_BRESP;
+  wire S_AXI_HP0_BVALID;
+  wire [2:0]S_AXI_HP0_RACOUNT;
+  wire [7:0]S_AXI_HP0_RCOUNT;
+  wire [63:0]S_AXI_HP0_RDATA;
+  wire S_AXI_HP0_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP0_RID;
+  wire S_AXI_HP0_RLAST;
+  wire S_AXI_HP0_RREADY;
+  wire [1:0]S_AXI_HP0_RRESP;
+  wire S_AXI_HP0_RVALID;
+  wire [5:0]S_AXI_HP0_WACOUNT;
+  wire [7:0]S_AXI_HP0_WCOUNT;
+  wire [63:0]S_AXI_HP0_WDATA;
+  wire [5:0]S_AXI_HP0_WID;
+  wire S_AXI_HP0_WLAST;
+  wire S_AXI_HP0_WREADY;
+  wire S_AXI_HP0_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP0_WSTRB;
+  wire S_AXI_HP0_WVALID;
+  wire S_AXI_HP1_ACLK;
+  wire [31:0]S_AXI_HP1_ARADDR;
+  wire [1:0]S_AXI_HP1_ARBURST;
+  wire [3:0]S_AXI_HP1_ARCACHE;
+  wire S_AXI_HP1_ARESETN;
+  wire [5:0]S_AXI_HP1_ARID;
+  wire [3:0]S_AXI_HP1_ARLEN;
+  wire [1:0]S_AXI_HP1_ARLOCK;
+  wire [2:0]S_AXI_HP1_ARPROT;
+  wire [3:0]S_AXI_HP1_ARQOS;
+  wire S_AXI_HP1_ARREADY;
+  wire [2:0]S_AXI_HP1_ARSIZE;
+  wire S_AXI_HP1_ARVALID;
+  wire [31:0]S_AXI_HP1_AWADDR;
+  wire [1:0]S_AXI_HP1_AWBURST;
+  wire [3:0]S_AXI_HP1_AWCACHE;
+  wire [5:0]S_AXI_HP1_AWID;
+  wire [3:0]S_AXI_HP1_AWLEN;
+  wire [1:0]S_AXI_HP1_AWLOCK;
+  wire [2:0]S_AXI_HP1_AWPROT;
+  wire [3:0]S_AXI_HP1_AWQOS;
+  wire S_AXI_HP1_AWREADY;
+  wire [2:0]S_AXI_HP1_AWSIZE;
+  wire S_AXI_HP1_AWVALID;
+  wire [5:0]S_AXI_HP1_BID;
+  wire S_AXI_HP1_BREADY;
+  wire [1:0]S_AXI_HP1_BRESP;
+  wire S_AXI_HP1_BVALID;
+  wire [2:0]S_AXI_HP1_RACOUNT;
+  wire [7:0]S_AXI_HP1_RCOUNT;
+  wire [63:0]S_AXI_HP1_RDATA;
+  wire S_AXI_HP1_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP1_RID;
+  wire S_AXI_HP1_RLAST;
+  wire S_AXI_HP1_RREADY;
+  wire [1:0]S_AXI_HP1_RRESP;
+  wire S_AXI_HP1_RVALID;
+  wire [5:0]S_AXI_HP1_WACOUNT;
+  wire [7:0]S_AXI_HP1_WCOUNT;
+  wire [63:0]S_AXI_HP1_WDATA;
+  wire [5:0]S_AXI_HP1_WID;
+  wire S_AXI_HP1_WLAST;
+  wire S_AXI_HP1_WREADY;
+  wire S_AXI_HP1_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP1_WSTRB;
+  wire S_AXI_HP1_WVALID;
+  wire S_AXI_HP2_ACLK;
+  wire [31:0]S_AXI_HP2_ARADDR;
+  wire [1:0]S_AXI_HP2_ARBURST;
+  wire [3:0]S_AXI_HP2_ARCACHE;
+  wire S_AXI_HP2_ARESETN;
+  wire [5:0]S_AXI_HP2_ARID;
+  wire [3:0]S_AXI_HP2_ARLEN;
+  wire [1:0]S_AXI_HP2_ARLOCK;
+  wire [2:0]S_AXI_HP2_ARPROT;
+  wire [3:0]S_AXI_HP2_ARQOS;
+  wire S_AXI_HP2_ARREADY;
+  wire [2:0]S_AXI_HP2_ARSIZE;
+  wire S_AXI_HP2_ARVALID;
+  wire [31:0]S_AXI_HP2_AWADDR;
+  wire [1:0]S_AXI_HP2_AWBURST;
+  wire [3:0]S_AXI_HP2_AWCACHE;
+  wire [5:0]S_AXI_HP2_AWID;
+  wire [3:0]S_AXI_HP2_AWLEN;
+  wire [1:0]S_AXI_HP2_AWLOCK;
+  wire [2:0]S_AXI_HP2_AWPROT;
+  wire [3:0]S_AXI_HP2_AWQOS;
+  wire S_AXI_HP2_AWREADY;
+  wire [2:0]S_AXI_HP2_AWSIZE;
+  wire S_AXI_HP2_AWVALID;
+  wire [5:0]S_AXI_HP2_BID;
+  wire S_AXI_HP2_BREADY;
+  wire [1:0]S_AXI_HP2_BRESP;
+  wire S_AXI_HP2_BVALID;
+  wire [2:0]S_AXI_HP2_RACOUNT;
+  wire [7:0]S_AXI_HP2_RCOUNT;
+  wire [63:0]S_AXI_HP2_RDATA;
+  wire S_AXI_HP2_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP2_RID;
+  wire S_AXI_HP2_RLAST;
+  wire S_AXI_HP2_RREADY;
+  wire [1:0]S_AXI_HP2_RRESP;
+  wire S_AXI_HP2_RVALID;
+  wire [5:0]S_AXI_HP2_WACOUNT;
+  wire [7:0]S_AXI_HP2_WCOUNT;
+  wire [63:0]S_AXI_HP2_WDATA;
+  wire [5:0]S_AXI_HP2_WID;
+  wire S_AXI_HP2_WLAST;
+  wire S_AXI_HP2_WREADY;
+  wire S_AXI_HP2_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP2_WSTRB;
+  wire S_AXI_HP2_WVALID;
+  wire S_AXI_HP3_ACLK;
+  wire [31:0]S_AXI_HP3_ARADDR;
+  wire [1:0]S_AXI_HP3_ARBURST;
+  wire [3:0]S_AXI_HP3_ARCACHE;
+  wire S_AXI_HP3_ARESETN;
+  wire [5:0]S_AXI_HP3_ARID;
+  wire [3:0]S_AXI_HP3_ARLEN;
+  wire [1:0]S_AXI_HP3_ARLOCK;
+  wire [2:0]S_AXI_HP3_ARPROT;
+  wire [3:0]S_AXI_HP3_ARQOS;
+  wire S_AXI_HP3_ARREADY;
+  wire [2:0]S_AXI_HP3_ARSIZE;
+  wire S_AXI_HP3_ARVALID;
+  wire [31:0]S_AXI_HP3_AWADDR;
+  wire [1:0]S_AXI_HP3_AWBURST;
+  wire [3:0]S_AXI_HP3_AWCACHE;
+  wire [5:0]S_AXI_HP3_AWID;
+  wire [3:0]S_AXI_HP3_AWLEN;
+  wire [1:0]S_AXI_HP3_AWLOCK;
+  wire [2:0]S_AXI_HP3_AWPROT;
+  wire [3:0]S_AXI_HP3_AWQOS;
+  wire S_AXI_HP3_AWREADY;
+  wire [2:0]S_AXI_HP3_AWSIZE;
+  wire S_AXI_HP3_AWVALID;
+  wire [5:0]S_AXI_HP3_BID;
+  wire S_AXI_HP3_BREADY;
+  wire [1:0]S_AXI_HP3_BRESP;
+  wire S_AXI_HP3_BVALID;
+  wire [2:0]S_AXI_HP3_RACOUNT;
+  wire [7:0]S_AXI_HP3_RCOUNT;
+  wire [63:0]S_AXI_HP3_RDATA;
+  wire S_AXI_HP3_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP3_RID;
+  wire S_AXI_HP3_RLAST;
+  wire S_AXI_HP3_RREADY;
+  wire [1:0]S_AXI_HP3_RRESP;
+  wire S_AXI_HP3_RVALID;
+  wire [5:0]S_AXI_HP3_WACOUNT;
+  wire [7:0]S_AXI_HP3_WCOUNT;
+  wire [63:0]S_AXI_HP3_WDATA;
+  wire [5:0]S_AXI_HP3_WID;
+  wire S_AXI_HP3_WLAST;
+  wire S_AXI_HP3_WREADY;
+  wire S_AXI_HP3_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP3_WSTRB;
+  wire S_AXI_HP3_WVALID;
+  wire TRACE_CLK;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[7] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[7] ;
+  wire TTC0_CLK0_IN;
+  wire TTC0_CLK1_IN;
+  wire TTC0_CLK2_IN;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire TTC1_CLK0_IN;
+  wire TTC1_CLK1_IN;
+  wire TTC1_CLK2_IN;
+  wire TTC1_WAVE0_OUT;
+  wire TTC1_WAVE1_OUT;
+  wire TTC1_WAVE2_OUT;
+  wire UART0_CTSN;
+  wire UART0_DCDN;
+  wire UART0_DSRN;
+  wire UART0_DTRN;
+  wire UART0_RIN;
+  wire UART0_RTSN;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire UART1_CTSN;
+  wire UART1_DCDN;
+  wire UART1_DSRN;
+  wire UART1_DTRN;
+  wire UART1_RIN;
+  wire UART1_RTSN;
+  wire UART1_RX;
+  wire UART1_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire [1:0]USB1_PORT_INDCTL;
+  wire USB1_VBUS_PWRFAULT;
+  wire USB1_VBUS_PWRSELECT;
+  wire WDT_CLK_IN;
+  wire WDT_RST_OUT;
+  wire [14:0]buffered_DDR_Addr;
+  wire [2:0]buffered_DDR_BankAddr;
+  wire buffered_DDR_CAS_n;
+  wire buffered_DDR_CKE;
+  wire buffered_DDR_CS_n;
+  wire buffered_DDR_Clk;
+  wire buffered_DDR_Clk_n;
+  wire [3:0]buffered_DDR_DM;
+  wire [31:0]buffered_DDR_DQ;
+  wire [3:0]buffered_DDR_DQS;
+  wire [3:0]buffered_DDR_DQS_n;
+  wire buffered_DDR_DRSTB;
+  wire buffered_DDR_ODT;
+  wire buffered_DDR_RAS_n;
+  wire buffered_DDR_VRN;
+  wire buffered_DDR_VRP;
+  wire buffered_DDR_WEB;
+  wire [53:0]buffered_MIO;
+  wire buffered_PS_CLK;
+  wire buffered_PS_PORB;
+  wire buffered_PS_SRSTB;
+  wire [63:0]gpio_out_t_n;
+  wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
+  wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+
+  assign ENET0_GMII_TXD'b'[7] = \\<const0> ;
+  assign ENET0_GMII_TXD[6] = \\<const0> ;
+  assign ENET0_GMII_TXD[5] = \\<const0> ;
+  assign ENET0_GMII_TXD[4] = \\<const0> ;
+  assign ENET0_GMII_TXD[3] = \\<const0> ;
+  assign ENET0_GMII_TXD[2] = \\<const0> ;
+  assign ENET0_GMII_TXD[1] = \\<const0> ;
+  assign ENET0_GMII_TXD[0] = \\<const0> ;
+  assign ENET0_GMII_TX_EN = \\<const0> ;
+  assign ENET0_GMII_TX_ER = \\<const0> ;
+  assign ENET1_GMII_TXD[7] = \\<const0> ;
+  assign ENET1_GMII_TXD[6] = \\<const0> ;
+  assign ENET1_GMII_TXD[5] = \\<const0> ;
+  assign ENET1_GMII_TXD[4] = \\<const0> ;
+  assign ENET1_GMII_TXD[3] = \\<const0> ;
+  assign ENET1_GMII_TXD[2] = \\<const0> ;
+  assign ENET1_GMII_TXD[1] = \\<const0> ;
+  assign ENET1_GMII_TXD[0] = \\<const0> ;
+  assign ENET1_GMII_TX_EN = \\<const0> ;
+  assign ENET1_GMII_TX_ER = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[1:0] = \\^M_AXI_GP0_ARSIZE [1:0];
+  assign M_AXI_GP0_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_AWSIZE[1:0] = \\^M_AXI_GP0_AWSIZE [1:0];
+  assign M_AXI_GP1_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_ARSIZE[1:0] = \\^M_AXI_GP1_ARSIZE [1:0];
+  assign M_AXI_GP1_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_AWSIZE[1:0] = \\^M_AXI_GP1_AWSIZE [1:0];
+  assign PJTAG_TDO = \\<const0> ;
+  assign TRACE_CLK_OUT = \\<const0> ;
+  assign TRACE_CTL = \\TRACE_CTL_PIPE[0] ;
+  assign TRACE_DATA[1:0] = \\TRACE_DATA_PIPE[0] ;
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CAS_n_BIBUF
+       (.IO(buffered_DDR_CAS_n),
+        .PAD(DDR_CAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CKE_BIBUF
+       (.IO(buffered_DDR_CKE),
+        .PAD(DDR_CKE));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CS_n_BIBUF
+       (.IO(buffered_DDR_CS_n),
+        .PAD(DDR_CS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_BIBUF
+       (.IO(buffered_DDR_Clk),
+        .PAD(DDR_Clk));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_n_BIBUF
+       (.IO(buffered_DDR_Clk_n),
+        .PAD(DDR_Clk_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_DRSTB_BIBUF
+       (.IO(buffered_DDR_DRSTB),
+        .PAD(DDR_DRSTB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_ODT_BIBUF
+       (.IO(buffered_DDR_ODT),
+        .PAD(DDR_ODT));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_RAS_n_BIBUF
+       (.IO(buffered_DDR_RAS_n),
+        .PAD(DDR_RAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRN_BIBUF
+       (.IO(buffered_DDR_VRN),
+        .PAD(DDR_VRN));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRP_BIBUF
+       (.IO(buffered_DDR_VRP),
+        .PAD(DDR_VRP));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_WEB_BIBUF
+       (.IO(buffered_DDR_WEB),
+        .PAD(DDR_WEB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET0_MDIO_T_INST_0
+       (.I0(ENET0_MDIO_T_n),
+        .O(ENET0_MDIO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET1_MDIO_T_INST_0
+       (.I0(ENET1_MDIO_T_n),
+        .O(ENET1_MDIO_T));
+  GND GND
+       (.G(\\<const0> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[0]_INST_0 
+       (.I0(gpio_out_t_n[0]),
+        .O(GPIO_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[10]_INST_0 
+       (.I0(gpio_out_t_n[10]),
+        .O(GPIO_T[10]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[11]_INST_0 
+       (.I0(gpio_out_t_n[11]),
+        .O(GPIO_T[11]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[12]_INST_0 
+       (.I0(gpio_out_t_n[12]),
+        .O(GPIO_T[12]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[13]_INST_0 
+       (.I0(gpio_out_t_n[13]),
+        .O(GPIO_T[13]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[14]_INST_0 
+       (.I0(gpio_out_t_n[14]),
+        .O(GPIO_T[14]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[15]_INST_0 
+       (.I0(gpio_out_t_n[15]),
+        .O(GPIO_T[15]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[16]_INST_0 
+       (.I0(gpio_out_t_n[16]),
+        .O(GPIO_T[16]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[17]_INST_0 
+       (.I0(gpio_out_t_n[17]),
+        .O(GPIO_T[17]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[18]_INST_0 
+       (.I0(gpio_out_t_n[18]),
+        .O(GPIO_T[18]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[19]_INST_0 
+       (.I0(gpio_out_t_n[19]),
+        .O(GPIO_T[19]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[1]_INST_0 
+       (.I0(gpio_out_t_n[1]),
+        .O(GPIO_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[20]_INST_0 
+       (.I0(gpio_out_t_n[20]),
+        .O(GPIO_T[20]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[21]_INST_0 
+       (.I0(gpio_out_t_n[21]),
+        .O(GPIO_T[21]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[22]_INST_0 
+       (.I0(gpio_out_t_n[22]),
+        .O(GPIO_T[22]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[23]_INST_0 
+       (.I0(gpio_out_t_n[23]),
+        .O(GPIO_T[23]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[24]_INST_0 
+       (.I0(gpio_out_t_n[24]),
+        .O(GPIO_T[24]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[25]_INST_0 
+       (.I0(gpio_out_t_n[25]),
+        .O(GPIO_T[25]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[26]_INST_0 
+       (.I0(gpio_out_t_n[26]),
+        .O(GPIO_T[26]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[27]_INST_0 
+       (.I0(gpio_out_t_n[27]),
+        .O(GPIO_T[27]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[28]_INST_0 
+       (.I0(gpio_out_t_n[28]),
+        .O(GPIO_T[28]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[29]_INST_0 
+       (.I0(gpio_out_t_n[29]),
+        .O(GPIO_T[29]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[2]_INST_0 
+       (.I0(gpio_out_t_n[2]),
+        .O(GPIO_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[30]_INST_0 
+       (.I0(gpio_out_t_n[30]),
+        .O(GPIO_T[30]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[31]_INST_0 
+       (.I0(gpio_out_t_n[31]),
+        .O(GPIO_T[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[32]_INST_0 
+       (.I0(gpio_out_t_n[32]),
+        .O(GPIO_T[32]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[33]_INST_0 
+       (.I0(gpio_out_t_n[33]),
+        .O(GPIO_T[33]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[34]_INST_0 
+       (.I0(gpio_out_t_n[34]),
+        .O(GPIO_T[34]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[35]_INST_0 
+       (.I0(gpio_out_t_n[35]),
+        .O(GPIO_T[35]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[36]_INST_0 
+       (.I0(gpio_out_t_n[36]),
+        .O(GPIO_T[36]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[37]_INST_0 
+       (.I0(gpio_out_t_n[37]),
+        .O(GPIO_T[37]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[38]_INST_0 
+       (.I0(gpio_out_t_n[38]),
+        .O(GPIO_T[38]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[39]_INST_0 
+       (.I0(gpio_out_t_n[39]),
+        .O(GPIO_T[39]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[3]_INST_0 
+       (.I0(gpio_out_t_n[3]),
+        .O(GPIO_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[40]_INST_0 
+       (.I0(gpio_out_t_n[40]),
+        .O(GPIO_T[40]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[41]_INST_0 
+       (.I0(gpio_out_t_n[41]),
+        .O(GPIO_T[41]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[42]_INST_0 
+       (.I0(gpio_out_t_n[42]),
+        .O(GPIO_T[42]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[43]_INST_0 
+       (.I0(gpio_out_t_n[43]),
+        .O(GPIO_T[43]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[44]_INST_0 
+       (.I0(gpio_out_t_n[44]),
+        .O(GPIO_T[44]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[45]_INST_0 
+       (.I0(gpio_out_t_n[45]),
+        .O(GPIO_T[45]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[46]_INST_0 
+       (.I0(gpio_out_t_n[46]),
+        .O(GPIO_T[46]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[47]_INST_0 
+       (.I0(gpio_out_t_n[47]),
+        .O(GPIO_T[47]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[48]_INST_0 
+       (.I0(gpio_out_t_n[48]),
+        .O(GPIO_T[48]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[49]_INST_0 
+       (.I0(gpio_out_t_n[49]),
+        .O(GPIO_T[49]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[4]_INST_0 
+       (.I0(gpio_out_t_n[4]),
+        .O(GPIO_T[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[50]_INST_0 
+       (.I0(gpio_out_t_n[50]),
+        .O(GPIO_T[50]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[51]_INST_0 
+       (.I0(gpio_out_t_n[51]),
+        .O(GPIO_T[51]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[52]_INST_0 
+       (.I0(gpio_out_t_n[52]),
+        .O(GPIO_T[52]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[53]_INST_0 
+       (.I0(gpio_out_t_n[53]),
+        .O(GPIO_T[53]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[54]_INST_0 
+       (.I0(gpio_out_t_n[54]),
+        .O(GPIO_T[54]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[55]_INST_0 
+       (.I0(gpio_out_t_n[55]),
+        .O(GPIO_T[55]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[56]_INST_0 
+       (.I0(gpio_out_t_n[56]),
+        .O(GPIO_T[56]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[57]_INST_0 
+       (.I0(gpio_out_t_n[57]),
+        .O(GPIO_T[57]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[58]_INST_0 
+       (.I0(gpio_out_t_n[58]),
+        .O(GPIO_T[58]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[59]_INST_0 
+       (.I0(gpio_out_t_n[59]),
+        .O(GPIO_T[59]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[5]_INST_0 
+       (.I0(gpio_out_t_n[5]),
+        .O(GPIO_T[5]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[60]_INST_0 
+       (.I0(gpio_out_t_n[60]),
+        .O(GPIO_T[60]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[61]_INST_0 
+       (.I0(gpio_out_t_n[61]),
+        .O(GPIO_T[61]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[62]_INST_0 
+       (.I0(gpio_out_t_n[62]),
+        .O(GPIO_T[62]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[63]_INST_0 
+       (.I0(gpio_out_t_n[63]),
+        .O(GPIO_T[63]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[6]_INST_0 
+       (.I0(gpio_out_t_n[6]),
+        .O(GPIO_T[6]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[7]_INST_0 
+       (.I0(gpio_out_t_n[7]),
+        .O(GPIO_T[7]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[8]_INST_0 
+       (.I0(gpio_out_t_n[8]),
+        .O(GPIO_T[8]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[9]_INST_0 
+       (.I0(gpio_out_t_n[9]),
+        .O(GPIO_T[9]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SCL_T_INST_0
+       (.I0(I2C0_SCL_T_n),
+        .O(I2C0_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SDA_T_INST_0
+       (.I0(I2C0_SDA_T_n),
+        .O(I2C0_SDA_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SCL_T_INST_0
+       (.I0(I2C1_SCL_T_n),
+        .O(I2C1_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SDA_T_INST_0
+       (.I0(I2C1_SDA_T_n),
+        .O(I2C1_SDA_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  PS7 PS7_i
+       (.DDRA(buffered_DDR_Addr),
+        .DDRARB(DDR_ARB),
+        .DDRBA(buffered_DDR_BankAddr),
+        .DDRCASB(buffered_DDR_CAS_n),
+        .DDRCKE(buffered_DDR_CKE),
+        .DDRCKN(buffered_DDR_Clk_n),
+        .DDRCKP(buffered_DDR_Clk),
+        .DDRCSB(buffered_DDR_CS_n),
+        .DDRDM(buffered_DDR_DM),
+        .DDRDQ(buffered_DDR_DQ),
+        .DDRDQSN(buffered_DDR_DQS_n),
+        .DDRDQSP(buffered_DDR_DQS),
+        .DDRDRSTB(buffered_DDR_DRSTB),
+        .DDRODT(buffered_DDR_ODT),
+        .DDRRASB(buffered_DDR_RAS_n),
+        .DDRVRN(buffered_DDR_VRN),
+        .DDRVRP(buffered_DDR_VRP),
+        .DDRWEB(buffered_DDR_WEB),
+        .DMA0ACLK(DMA0_ACLK),
+        .DMA0DAREADY(DMA0_DAREADY),
+        .DMA0DATYPE(DMA0_DATYPE),
+        .DMA0DAVALID(DMA0_DAVALID),
+        .DMA0DRLAST(DMA0_DRLAST),
+        .DMA0DRREADY(DMA0_DRREADY),
+        .DMA0DRTYPE(DMA0_DRTYPE),
+        .DMA0DRVALID(DMA0_DRVALID),
+        .DMA0RSTN(DMA0_RSTN),
+        .DMA1ACLK(DMA1_ACLK),
+        .DMA1DAREADY(DMA1_DAREADY),
+        .DMA1DATYPE(DMA1_DATYPE),
+        .DMA1DAVALID(DMA1_DAVALID),
+        .DMA1DRLAST(DMA1_DRLAST),
+        .DMA1DRREADY(DMA1_DRREADY),
+        .DMA1DRTYPE(DMA1_DRTYPE),
+        .DMA1DRVALID(DMA1_DRVALID),
+        .DMA1RSTN(DMA1_RSTN),
+        .DMA2ACLK(DMA2_ACLK),
+        .DMA2DAREADY(DMA2_DAREADY),
+        .DMA2DATYPE(DMA2_DATYPE),
+        .DMA2DAVALID(DMA2_DAVALID),
+        .DMA2DRLAST(DMA2_DRLAST),
+        .DMA2DRREADY(DMA2_DRREADY),
+        .DMA2DRTYPE(DMA2_DRTYPE),
+        .DMA2DRVALID(DMA2_DRVALID),
+        .DMA2RSTN(DMA2_RSTN),
+        .DMA3ACLK(DMA3_ACLK),
+        .DMA3DAREADY(DMA3_DAREADY),
+        .DMA3DATYPE(DMA3_DATYPE),
+        .DMA3DAVALID(DMA3_DAVALID),
+        .DMA3DRLAST(DMA3_DRLAST),
+        .DMA3DRREADY(DMA3_DRREADY),
+        .DMA3DRTYPE(DMA3_DRTYPE),
+        .DMA3DRVALID(DMA3_DRVALID),
+        .DMA3RSTN(DMA3_RSTN),
+        .EMIOCAN0PHYRX(CAN0_PHY_RX),
+        .EMIOCAN0PHYTX(CAN0_PHY_TX),
+        .EMIOCAN1PHYRX(CAN1_PHY_RX),
+        .EMIOCAN1PHYTX(CAN1_PHY_TX),
+        .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+        .EMIOENET0GMIICOL(1\'b0),
+        .EMIOENET0GMIICRS(1\'b0),
+        .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+        .EMIOENET0GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET0GMIIRXDV(1\'b0),
+        .EMIOENET0GMIIRXER(1\'b0),
+        .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+        .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+        .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+        .EMIOENET0MDIOI(ENET0_MDIO_I),
+        .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+        .EMIOENET0MDIOO(ENET0_MDIO_O),
+        .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+        .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+        .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+        .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+        .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+        .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+        .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+        .EMIOENET0SOFRX(ENET0_SOF_RX),
+        .EMIOENET0SOFTX(ENET0_SOF_TX),
+        .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+        .EMIOENET1GMIICOL(1\'b0),
+        .EMIOENET1GMIICRS(1\'b0),
+        .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+        .EMIOENET1GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET1GMIIRXDV(1\'b0),
+        .EMIOENET1GMIIRXER(1\'b0),
+        .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+        .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+        .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+        .EMIOENET1MDIOI(ENET1_MDIO_I),
+        .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+        .EMIOENET1MDIOO(ENET1_MDIO_O),
+        .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+        .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+        .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+        .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+        .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+        .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+        .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+        .EMIOENET1SOFRX(ENET1_SOF_RX),
+        .EMIOENET1SOFTX(ENET1_SOF_TX),
+        .EMIOGPIOI(GPIO_I),
+        .EMIOGPIOO(GPIO_O),
+        .EMIOGPIOTN(gpio_out_t_n),
+        .EMIOI2C0SCLI(I2C0_SCL_I),
+        .EMIOI2C0SCLO(I2C0_SCL_O),
+        .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+        .EMIOI2C0SDAI(I2C0_SDA_I),
+        .EMIOI2C0SDAO(I2C0_SDA_O),
+        .EMIOI2C0SDATN(I2C0_SDA_T_n),
+        .EMIOI2C1SCLI(I2C1_SCL_I),
+        .EMIOI2C1SCLO(I2C1_SCL_O),
+        .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+        .EMIOI2C1SDAI(I2C1_SDA_I),
+        .EMIOI2C1SDAO(I2C1_SDA_O),
+        .EMIOI2C1SDATN(I2C1_SDA_T_n),
+        .EMIOPJTAGTCK(PJTAG_TCK),
+        .EMIOPJTAGTDI(PJTAG_TDI),
+        .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+        .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+        .EMIOPJTAGTMS(PJTAG_TMS),
+        .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+        .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+        .EMIOSDIO0CDN(SDIO0_CDN),
+        .EMIOSDIO0CLK(SDIO0_CLK),
+        .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+        .EMIOSDIO0CMDI(SDIO0_CMD_I),
+        .EMIOSDIO0CMDO(SDIO0_CMD_O),
+        .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+        .EMIOSDIO0DATAI(SDIO0_DATA_I),
+        .EMIOSDIO0DATAO(SDIO0_DATA_O),
+        .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+        .EMIOSDIO0LED(SDIO0_LED),
+        .EMIOSDIO0WP(SDIO0_WP),
+        .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+        .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+        .EMIOSDIO1CDN(SDIO1_CDN),
+        .EMIOSDIO1CLK(SDIO1_CLK),
+        .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+        .EMIOSDIO1CMDI(SDIO1_CMD_I),
+        .EMIOSDIO1CMDO(SDIO1_CMD_O),
+        .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+        .EMIOSDIO1DATAI(SDIO1_DATA_I),
+        .EMIOSDIO1DATAO(SDIO1_DATA_O),
+        .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+        .EMIOSDIO1LED(SDIO1_LED),
+        .EMIOSDIO1WP(SDIO1_WP),
+        .EMIOSPI0MI(SPI0_MISO_I),
+        .EMIOSPI0MO(SPI0_MOSI_O),
+        .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+        .EMIOSPI0SCLKI(SPI0_SCLK_I),
+        .EMIOSPI0SCLKO(SPI0_SCLK_O),
+        .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+        .EMIOSPI0SI(SPI0_MOSI_I),
+        .EMIOSPI0SO(SPI0_MISO_O),
+        .EMIOSPI0SSIN(SPI0_SS_I),
+        .EMIOSPI0SSNTN(SPI0_SS_T_n),
+        .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+        .EMIOSPI0STN(SPI0_MISO_T_n),
+        .EMIOSPI1MI(SPI1_MISO_I),
+        .EMIOSPI1MO(SPI1_MOSI_O),
+        .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+        .EMIOSPI1SCLKI(SPI1_SCLK_I),
+        .EMIOSPI1SCLKO(SPI1_SCLK_O),
+        .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+        .EMIOSPI1SI(SPI1_MOSI_I),
+        .EMIOSPI1SO(SPI1_MISO_O),
+        .EMIOSPI1SSIN(SPI1_SS_I),
+        .EMIOSPI1SSNTN(SPI1_SS_T_n),
+        .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+        .EMIOSPI1STN(SPI1_MISO_T_n),
+        .EMIOSRAMINTIN(SRAM_INTIN),
+        .EMIOTRACECLK(TRACE_CLK),
+        .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+        .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+        .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+        .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+        .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+        .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+        .EMIOUART0CTSN(UART0_CTSN),
+        .EMIOUART0DCDN(UART0_DCDN),
+        .EMIOUART0DSRN(UART0_DSRN),
+        .EMIOUART0DTRN(UART0_DTRN),
+        .EMIOUART0RIN(UART0_RIN),
+        .EMIOUART0RTSN(UART0_RTSN),
+        .EMIOUART0RX(UART0_RX),
+        .EMIOUART0TX(UART0_TX),
+        .EMIOUART1CTSN(UART1_CTSN),
+        .EMIOUART1DCDN(UART1_DCDN),
+        .EMIOUART1DSRN(UART1_DSRN),
+        .EMIOUART1DTRN(UART1_DTRN),
+        .EMIOUART1RIN(UART1_RIN),
+        .EMIOUART1RTSN(UART1_RTSN),
+        .EMIOUART1RX(UART1_RX),
+        .EMIOUART1TX(UART1_TX),
+        .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+        .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+        .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+        .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+        .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+        .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+        .EMIOWDTCLKI(WDT_CLK_IN),
+        .EMIOWDTRSTO(WDT_RST_OUT),
+        .EVENTEVENTI(EVENT_EVENTI),
+        .EVENTEVENTO(EVENT_EVENTO),
+        .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+        .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+        .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+        .FCLKCLKTRIGN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+        .FPGAIDLEN(FPGA_IDLE_N),
+        .FTMDTRACEINATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+        .FTMDTRACEINDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINVALID(1\'b0),
+        .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+        .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+        .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+        .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+        .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+        .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+        .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,IRQ_F2P}),
+        .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+        .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+        .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+        .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+        .MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
+        .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+        .MAXIGP0ARID(M_AXI_GP0_ARID),
+        .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+        .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+        .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+        .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+        .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+        .MAXIGP0ARSIZE(\\^M_AXI_GP0_ARSIZE ),
+        .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+        .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+        .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+        .MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
+        .MAXIGP0AWID(M_AXI_GP0_AWID),
+        .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+        .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+        .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+        .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+        .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+        .MAXIGP0AWSIZE(\\^M_AXI_GP0_AWSIZE ),
+        .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+        .MAXIGP0BID(M_AXI_GP0_BID),
+        .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+        .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+        .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+        .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+        .MAXIGP0RID(M_AXI_GP0_RID),
+        .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+        .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+        .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+        .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+        .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+        .MAXIGP0WID(M_AXI_GP0_WID),
+        .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+        .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+        .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+        .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+        .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+        .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+        .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+        .MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
+        .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+        .MAXIGP1ARID(M_AXI_GP1_ARID),
+        .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+        .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+        .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+        .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+        .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+        .MAXIGP1ARSIZE(\\^M_AXI_GP1_ARSIZE ),
+        .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+        .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+        .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+        .MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
+        .MAXIGP1AWID(M_AXI_GP1_AWID),
+        .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+        .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+        .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+        .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+        .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+        .MAXIGP1AWSIZE(\\^M_AXI_GP1_AWSIZE ),
+        .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+        .MAXIGP1BID(M_AXI_GP1_BID),
+        .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+        .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+        .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+        .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+        .MAXIGP1RID(M_AXI_GP1_RID),
+        .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+        .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+        .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+        .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+        .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+        .MAXIGP1WID(M_AXI_GP1_WID),
+        .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+        .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+        .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+        .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+        .MIO(buffered_MIO),
+        .PSCLK(buffered_PS_CLK),
+        .PSPORB(buffered_PS_PORB),
+        .PSSRSTB(buffered_PS_SRSTB),
+        .SAXIACPACLK(S_AXI_ACP_ACLK),
+        .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+        .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+        .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+        .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+        .SAXIACPARID(S_AXI_ACP_ARID),
+        .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+        .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+        .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+        .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+        .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+        .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+        .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+        .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+        .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+        .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+        .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+        .SAXIACPAWID(S_AXI_ACP_AWID),
+        .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+        .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+        .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+        .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+        .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+        .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+        .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+        .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+        .SAXIACPBID(S_AXI_ACP_BID),
+        .SAXIACPBREADY(S_AXI_ACP_BREADY),
+        .SAXIACPBRESP(S_AXI_ACP_BRESP),
+        .SAXIACPBVALID(S_AXI_ACP_BVALID),
+        .SAXIACPRDATA(S_AXI_ACP_RDATA),
+        .SAXIACPRID(S_AXI_ACP_RID),
+        .SAXIACPRLAST(S_AXI_ACP_RLAST),
+        .SAXIACPRREADY(S_AXI_ACP_RREADY),
+        .SAXIACPRRESP(S_AXI_ACP_RRESP),
+        .SAXIACPRVALID(S_AXI_ACP_RVALID),
+        .SAXIACPWDATA(S_AXI_ACP_WDATA),
+        .SAXIACPWID(S_AXI_ACP_WID),
+        .SAXIACPWLAST(S_AXI_ACP_WLAST),
+        .SAXIACPWREADY(S_AXI_ACP_WREADY),
+        .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+        .SAXIACPWVALID(S_AXI_ACP_WVALID),
+        .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+        .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+        .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+        .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+        .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+        .SAXIGP0ARID(S_AXI_GP0_ARID),
+        .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+        .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+        .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+        .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+        .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+        .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+        .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+        .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+        .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+        .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+        .SAXIGP0AWID(S_AXI_GP0_AWID),
+        .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+        .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+        .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+        .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+        .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+        .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+        .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+        .SAXIGP0BID(S_AXI_GP0_BID),
+        .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+        .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+        .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+        .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+        .SAXIGP0RID(S_AXI_GP0_RID),
+        .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+        .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+        .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+        .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+        .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+        .SAXIGP0WID(S_AXI_GP0_WID),
+        .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+        .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+        .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+        .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+        .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+        .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+        .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+        .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+        .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+        .SAXIGP1ARID(S_AXI_GP1_ARID),
+        .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+        .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+        .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+        .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+        .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+        .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+        .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+        .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+        .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+        .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+        .SAXIGP1AWID(S_AXI_GP1_AWID),
+        .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+        .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+        .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+        .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+        .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+        .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+        .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+        .SAXIGP1BID(S_AXI_GP1_BID),
+        .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+        .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+        .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+        .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+        .SAXIGP1RID(S_AXI_GP1_RID),
+        .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+        .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+        .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+        .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+        .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+        .SAXIGP1WID(S_AXI_GP1_WID),
+        .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+        .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+        .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+        .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+        .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+        .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+        .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+        .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+        .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+        .SAXIHP0ARID(S_AXI_HP0_ARID),
+        .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+        .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+        .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+        .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+        .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+        .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+        .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+        .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+        .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+        .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+        .SAXIHP0AWID(S_AXI_HP0_AWID),
+        .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+        .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+        .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+        .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+        .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+        .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+        .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+        .SAXIHP0BID(S_AXI_HP0_BID),
+        .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+        .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+        .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+        .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+        .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+        .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+        .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+        .SAXIHP0RID(S_AXI_HP0_RID),
+        .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+        .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+        .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+        .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+        .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+        .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+        .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+        .SAXIHP0WID(S_AXI_HP0_WID),
+        .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+        .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+        .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+        .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+        .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+        .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+        .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+        .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+        .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+        .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+        .SAXIHP1ARID(S_AXI_HP1_ARID),
+        .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+        .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+        .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+        .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+        .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+        .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+        .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+        .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+        .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+        .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+        .SAXIHP1AWID(S_AXI_HP1_AWID),
+        .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+        .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+        .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+        .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+        .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+        .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+        .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+        .SAXIHP1BID(S_AXI_HP1_BID),
+        .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+        .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+        .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+        .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+        .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+        .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+        .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+        .SAXIHP1RID(S_AXI_HP1_RID),
+        .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+        .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+        .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+        .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+        .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+        .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+        .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+        .SAXIHP1WID(S_AXI_HP1_WID),
+        .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+        .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+        .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+        .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+        .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+        .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+        .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+        .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+        .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+        .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+        .SAXIHP2ARID(S_AXI_HP2_ARID),
+        .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+        .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+        .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+        .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+        .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+        .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+        .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+        .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+        .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+        .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+        .SAXIHP2AWID(S_AXI_HP2_AWID),
+        .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+        .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+        .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+        .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+        .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+        .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+        .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+        .SAXIHP2BID(S_AXI_HP2_BID),
+        .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+        .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+        .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+        .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+        .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+        .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+        .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+        .SAXIHP2RID(S_AXI_HP2_RID),
+        .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+        .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+        .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+        .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+        .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+        .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+        .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+        .SAXIHP2WID(S_AXI_HP2_WID),
+        .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+        .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+        .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+        .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+        .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+        .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+        .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+        .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+        .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+        .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+        .SAXIHP3ARID(S_AXI_HP3_ARID),
+        .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+        .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+        .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+        .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+        .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+        .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+        .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+        .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+        .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+        .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+        .SAXIHP3AWID(S_AXI_HP3_AWID),
+        .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+        .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+        .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+        .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+        .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+        .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+        .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+        .SAXIHP3BID(S_AXI_HP3_BID),
+        .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+        .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+        .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+        .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+        .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+        .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+        .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+        .SAXIHP3RID(S_AXI_HP3_RID),
+        .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+        .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+        .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+        .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+        .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+        .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+        .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+        .SAXIHP3WID(S_AXI_HP3_WID),
+        .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+        .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+        .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+        .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+        .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_CLK_BIBUF
+       (.IO(buffered_PS_CLK),
+        .PAD(PS_CLK));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_PORB_BIBUF
+       (.IO(buffered_PS_PORB),
+        .PAD(PS_PORB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_SRSTB_BIBUF
+       (.IO(buffered_PS_SRSTB),
+        .PAD(PS_SRSTB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO0_CMD_T_INST_0
+       (.I0(SDIO0_CMD_T_n),
+        .O(SDIO0_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[0]_INST_0 
+       (.I0(SDIO0_DATA_T_n[0]),
+        .O(SDIO0_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[1]_INST_0 
+       (.I0(SDIO0_DATA_T_n[1]),
+        .O(SDIO0_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[2]_INST_0 
+       (.I0(SDIO0_DATA_T_n[2]),
+        .O(SDIO0_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[3]_INST_0 
+       (.I0(SDIO0_DATA_T_n[3]),
+        .O(SDIO0_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO1_CMD_T_INST_0
+       (.I0(SDIO1_CMD_T_n),
+        .O(SDIO1_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[0]_INST_0 
+       (.I0(SDIO1_DATA_T_n[0]),
+        .O(SDIO1_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[1]_INST_0 
+       (.I0(SDIO1_DATA_T_n[1]),
+        .O(SDIO1_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[2]_INST_0 
+       (.I0(SDIO1_DATA_T_n[2]),
+        .O(SDIO1_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[3]_INST_0 
+       (.I0(SDIO1_DATA_T_n[3]),
+        .O(SDIO1_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MISO_T_INST_0
+       (.I0(SPI0_MISO_T_n),
+        .O(SPI0_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MOSI_T_INST_0
+       (.I0(SPI0_MOSI_T_n),
+        .O(SPI0_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SCLK_T_INST_0
+       (.I0(SPI0_SCLK_T_n),
+        .O(SPI0_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SS_T_INST_0
+       (.I0(SPI0_SS_T_n),
+        .O(SPI0_SS_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MISO_T_INST_0
+       (.I0(SPI1_MISO_T_n),
+        .O(SPI1_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MOSI_T_INST_0
+       (.I0(SPI1_MOSI_T_n),
+        .O(SPI1_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SCLK_T_INST_0
+       (.I0(SPI1_SCLK_T_n),
+        .O(SPI1_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SS_T_INST_0
+       (.I0(SPI1_SS_T_n),
+        .O(SPI1_SS_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BUFG \\buffer_fclk_clk_0.FCLK_CLK_0_BUFG 
+       (.I(FCLK_CLK_unbuffered),
+        .O(FCLK_CLK0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[0].MIO_BIBUF 
+       (.IO(buffered_MIO[0]),
+        .PAD(MIO[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[10].MIO_BIBUF 
+       (.IO(buffered_MIO[10]),
+        .PAD(MIO[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[11].MIO_BIBUF 
+       (.IO(buffered_MIO[11]),
+        .PAD(MIO[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[12].MIO_BIBUF 
+       (.IO(buffered_MIO[12]),
+        .PAD(MIO[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[13].MIO_BIBUF 
+       (.IO(buffered_MIO[13]),
+        .PAD(MIO[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[14].MIO_BIBUF 
+       (.IO(buffered_MIO[14]),
+        .PAD(MIO[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[15].MIO_BIBUF 
+       (.IO(buffered_MIO[15]),
+        .PAD(MIO[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[16].MIO_BIBUF 
+       (.IO(buffered_MIO[16]),
+        .PAD(MIO[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[17].MIO_BIBUF 
+       (.IO(buffered_MIO[17]),
+        .PAD(MIO[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[18].MIO_BIBUF 
+       (.IO(buffered_MIO[18]),
+        .PAD(MIO[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[19].MIO_BIBUF 
+       (.IO(buffered_MIO[19]),
+        .PAD(MIO[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[1].MIO_BIBUF 
+       (.IO(buffered_MIO[1]),
+        .PAD(MIO[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[20].MIO_BIBUF 
+       (.IO(buffered_MIO[20]),
+        .PAD(MIO[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[21].MIO_BIBUF 
+       (.IO(buffered_MIO[21]),
+        .PAD(MIO[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[22].MIO_BIBUF 
+       (.IO(buffered_MIO[22]),
+        .PAD(MIO[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[23].MIO_BIBUF 
+       (.IO(buffered_MIO[23]),
+        .PAD(MIO[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[24].MIO_BIBUF 
+       (.IO(buffered_MIO[24]),
+        .PAD(MIO[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[25].MIO_BIBUF 
+       (.IO(buffered_MIO[25]),
+        .PAD(MIO[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[26].MIO_BIBUF 
+       (.IO(buffered_MIO[26]),
+        .PAD(MIO[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[27].MIO_BIBUF 
+       (.IO(buffered_MIO[27]),
+        .PAD(MIO[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[28].MIO_BIBUF 
+       (.IO(buffered_MIO[28]),
+        .PAD(MIO[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[29].MIO_BIBUF 
+       (.IO(buffered_MIO[29]),
+        .PAD(MIO[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[2].MIO_BIBUF 
+       (.IO(buffered_MIO[2]),
+        .PAD(MIO[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[30].MIO_BIBUF 
+       (.IO(buffered_MIO[30]),
+        .PAD(MIO[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[31].MIO_BIBUF 
+       (.IO(buffered_MIO[31]),
+        .PAD(MIO[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[32].MIO_BIBUF 
+       (.IO(buffered_MIO[32]),
+        .PAD(MIO[32]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[33].MIO_BIBUF 
+       (.IO(buffered_MIO[33]),
+        .PAD(MIO[33]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[34].MIO_BIBUF 
+       (.IO(buffered_MIO[34]),
+        .PAD(MIO[34]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[35].MIO_BIBUF 
+       (.IO(buffered_MIO[35]),
+        .PAD(MIO[35]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[36].MIO_BIBUF 
+       (.IO(buffered_MIO[36]),
+        .PAD(MIO[36]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[37].MIO_BIBUF 
+       (.IO(buffered_MIO[37]),
+        .PAD(MIO[37]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[38].MIO_BIBUF 
+       (.IO(buffered_MIO[38]),
+        .PAD(MIO[38]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[39].MIO_BIBUF 
+       (.IO(buffered_MIO[39]),
+        .PAD(MIO[39]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[3].MIO_BIBUF 
+       (.IO(buffered_MIO[3]),
+        .PAD(MIO[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[40].MIO_BIBUF 
+       (.IO(buffered_MIO[40]),
+        .PAD(MIO[40]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[41].MIO_BIBUF 
+       (.IO(buffered_MIO[41]),
+        .PAD(MIO[41]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[42].MIO_BIBUF 
+       (.IO(buffered_MIO[42]),
+        .PAD(MIO[42]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[43].MIO_BIBUF 
+       (.IO(buffered_MIO[43]),
+        .PAD(MIO[43]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[44].MIO_BIBUF 
+       (.IO(buffered_MIO[44]),
+        .PAD(MIO[44]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[45].MIO_BIBUF 
+       (.IO(buffered_MIO[45]),
+        .PAD(MIO[45]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[46].MIO_BIBUF 
+       (.IO(buffered_MIO[46]),
+        .PAD(MIO[46]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[47].MIO_BIBUF 
+       (.IO(buffered_MIO[47]),
+        .PAD(MIO[47]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[48].MIO_BIBUF 
+       (.IO(buffered_MIO[48]),
+        .PAD(MIO[48]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[49].MIO_BIBUF 
+       (.IO(buffered_MIO[49]),
+        .PAD(MIO[49]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[4].MIO_BIBUF 
+       (.IO(buffered_MIO[4]),
+        .PAD(MIO[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[50].MIO_BIBUF 
+       (.IO(buffered_MIO[50]),
+        .PAD(MIO[50]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[51].MIO_BIBUF 
+       (.IO(buffered_MIO[51]),
+        .PAD(MIO[51]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[52].MIO_BIBUF 
+       (.IO(buffered_MIO[52]),
+        .PAD(MIO[52]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[53].MIO_BIBUF 
+       (.IO(buffered_MIO[53]),
+        .PAD(MIO[53]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[5].MIO_BIBUF 
+       (.IO(buffered_MIO[5]),
+        .PAD(MIO[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[6].MIO_BIBUF 
+       (.IO(buffered_MIO[6]),
+        .PAD(MIO[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[7].MIO_BIBUF 
+       (.IO(buffered_MIO[7]),
+        .PAD(MIO[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[8].MIO_BIBUF 
+       (.IO(buffered_MIO[8]),
+        .PAD(MIO[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[9].MIO_BIBUF 
+       (.IO(buffered_MIO[9]),
+        .PAD(MIO[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[0].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[0]),
+        .PAD(DDR_BankAddr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[1].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[1]),
+        .PAD(DDR_BankAddr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[2].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[2]),
+        .PAD(DDR_BankAddr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[0].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[0]),
+        .PAD(DDR_Addr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[10].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[10]),
+        .PAD(DDR_Addr[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[11].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[11]),
+        .PAD(DDR_Addr[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[12].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[12]),
+        .PAD(DDR_Addr[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[13].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[13]),
+        .PAD(DDR_Addr[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[14].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[14]),
+        .PAD(DDR_Addr[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[1].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[1]),
+        .PAD(DDR_Addr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[2].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[2]),
+        .PAD(DDR_Addr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[3].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[3]),
+        .PAD(DDR_Addr[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[4].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[4]),
+        .PAD(DDR_Addr[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[5].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[5]),
+        .PAD(DDR_Addr[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[6].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[6]),
+        .PAD(DDR_Addr[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[7].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[7]),
+        .PAD(DDR_Addr[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[8].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[8]),
+        .PAD(DDR_Addr[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[9].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[9]),
+        .PAD(DDR_Addr[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[0].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[0]),
+        .PAD(DDR_DM[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[1].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[1]),
+        .PAD(DDR_DM[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[2].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[2]),
+        .PAD(DDR_DM[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[3].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[3]),
+        .PAD(DDR_DM[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[0].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[0]),
+        .PAD(DDR_DQ[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[10].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[10]),
+        .PAD(DDR_DQ[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[11].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[11]),
+        .PAD(DDR_DQ[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[12].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[12]),
+        .PAD(DDR_DQ[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[13].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[13]),
+        .PAD(DDR_DQ[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[14].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[14]),
+        .PAD(DDR_DQ[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[15].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[15]),
+        .PAD(DDR_DQ[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[16].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[16]),
+        .PAD(DDR_DQ[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[17].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[17]),
+        .PAD(DDR_DQ[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[18].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[18]),
+        .PAD(DDR_DQ[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[19].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[19]),
+        .PAD(DDR_DQ[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[1].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[1]),
+        .PAD(DDR_DQ[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[20].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[20]),
+        .PAD(DDR_DQ[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[21].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[21]),
+        .PAD(DDR_DQ[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[22].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[22]),
+        .PAD(DDR_DQ[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[23].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[23]),
+        .PAD(DDR_DQ[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[24].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[24]),
+        .PAD(DDR_DQ[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[25].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[25]),
+        .PAD(DDR_DQ[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[26].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[26]),
+        .PAD(DDR_DQ[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[27].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[27]),
+        .PAD(DDR_DQ[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[28].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[28]),
+        .PAD(DDR_DQ[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[29].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[29]),
+        .PAD(DDR_DQ[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[2].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[2]),
+        .PAD(DDR_DQ[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[30].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[30]),
+        .PAD(DDR_DQ[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[31].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[31]),
+        .PAD(DDR_DQ[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[3].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[3]),
+        .PAD(DDR_DQ[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[4].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[4]),
+        .PAD(DDR_DQ[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[5].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[5]),
+        .PAD(DDR_DQ[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[6].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[6]),
+        .PAD(DDR_DQ[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[7].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[7]),
+        .PAD(DDR_DQ[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[8].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[8]),
+        .PAD(DDR_DQ[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[9].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[9]),
+        .PAD(DDR_DQ[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[0].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[0]),
+        .PAD(DDR_DQS_n[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[1].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[1]),
+        .PAD(DDR_DQS_n[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[2].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[2]),
+        .PAD(DDR_DQS_n[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[3].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[3]),
+        .PAD(DDR_DQS_n[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[0].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[0]),
+        .PAD(DDR_DQS[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[1].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[1]),
+        .PAD(DDR_DQS[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[2].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[2]),
+        .PAD(DDR_DQS[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[3].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[3]),
+        .PAD(DDR_DQS[3]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_0
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[0] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_1
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_10
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_11
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_12
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_13
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_14
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_15
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_16
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_17
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_18
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_19
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_2
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_20
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_21
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_22
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_23
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_3
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[7] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_4
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[6] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_5
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[5] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_6
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[4] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_7
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[3] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_8
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[2] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_9
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Tue Feb 14 01:38:42 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    SDIO0_WP,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    FCLK_CLK0,
+    FCLK_RESET0_N,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I"" *) input [63:0]GPIO_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O"" *) output [63:0]GPIO_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T"" *) output [63:0]GPIO_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *) input SDIO0_WP;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *) output [1:0]USB0_PORT_INDCTL;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *) output USB0_VBUS_PWRSELECT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *) input USB0_VBUS_PWRFAULT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *) output M_AXI_GP0_ARVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *) output M_AXI_GP0_AWVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *) output M_AXI_GP0_BREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *) output M_AXI_GP0_RREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *) output M_AXI_GP0_WLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *) output M_AXI_GP0_WVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *) output [11:0]M_AXI_GP0_ARID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *) output [11:0]M_AXI_GP0_AWID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *) output [11:0]M_AXI_GP0_WID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *) output [1:0]M_AXI_GP0_ARBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *) output [1:0]M_AXI_GP0_ARLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *) output [2:0]M_AXI_GP0_ARSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *) output [1:0]M_AXI_GP0_AWBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *) output [1:0]M_AXI_GP0_AWLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *) output [2:0]M_AXI_GP0_AWSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *) output [2:0]M_AXI_GP0_ARPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *) output [2:0]M_AXI_GP0_AWPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *) output [31:0]M_AXI_GP0_ARADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *) output [31:0]M_AXI_GP0_AWADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *) output [31:0]M_AXI_GP0_WDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *) output [3:0]M_AXI_GP0_ARCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *) output [3:0]M_AXI_GP0_ARLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *) output [3:0]M_AXI_GP0_ARQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *) output [3:0]M_AXI_GP0_AWCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *) output [3:0]M_AXI_GP0_AWLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *) output [3:0]M_AXI_GP0_AWQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *) output [3:0]M_AXI_GP0_WSTRB;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *) input M_AXI_GP0_ACLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *) input M_AXI_GP0_ARREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *) input M_AXI_GP0_AWREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *) input M_AXI_GP0_BVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *) input M_AXI_GP0_RLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *) input M_AXI_GP0_RVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *) input M_AXI_GP0_WREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *) input [11:0]M_AXI_GP0_BID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *) input [11:0]M_AXI_GP0_RID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *) input [1:0]M_AXI_GP0_BRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *) input [1:0]M_AXI_GP0_RRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *) input [31:0]M_AXI_GP0_RDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *) output FCLK_CLK0;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *) output FCLK_RESET0_N;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *) inout [53:0]MIO;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *) inout DDR_CAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *) inout DDR_CKE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *) inout DDR_Clk_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *) inout DDR_Clk;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *) inout DDR_CS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *) inout DDR_DRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *) inout DDR_ODT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *) inout DDR_RAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *) inout DDR_WEB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *) inout [2:0]DDR_BankAddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *) inout [14:0]DDR_Addr;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *) inout DDR_VRN;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *) inout DDR_VRP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *) inout [3:0]DDR_DM;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *) inout [31:0]DDR_DQ;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *) inout [3:0]DDR_DQS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *) inout [3:0]DDR_DQS;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *) inout PS_SRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *) inout PS_CLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *) inout PS_PORB;
+
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire FCLK_CLK0;
+  wire FCLK_RESET0_N;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [2:0]M_AXI_GP0_ARSIZE;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [2:0]M_AXI_GP0_AWSIZE;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_WP;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+  wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+  wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+  wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+  wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+  wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+  wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO0_LED_UNCONNECTED;
+  wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO1_LED_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+  wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+  wire NLW_inst_TRACE_CTL_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+  wire NLW_inst_UART0_DTRN_UNCONNECTED;
+  wire NLW_inst_UART0_RTSN_UNCONNECTED;
+  wire NLW_inst_UART0_TX_UNCONNECTED;
+  wire NLW_inst_UART1_DTRN_UNCONNECTED;
+  wire NLW_inst_UART1_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_TX_UNCONNECTED;
+  wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+  wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+  wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+  wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+  wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+PULLUP pullup_MIO_0
+       (.O(MIO[0]));
+PULLUP pullup_MIO_9
+       (.O(MIO[9]));
+PULLUP pullup_MIO_10
+       (.O(MIO[10]));
+PULLUP pullup_MIO_11
+       (.O(MIO[11]));
+PULLUP pullup_MIO_12
+       (.O(MIO[12]));
+PULLUP pullup_MIO_13
+       (.O(MIO[13]));
+PULLUP pullup_MIO_14
+       (.O(MIO[14]));
+PULLUP pullup_MIO_15
+       (.O(MIO[15]));
+PULLUP pullup_MIO_46
+       (.O(MIO[46]));
+
+  (* C_DM_WIDTH = ""4"" *) 
+  (* C_DQS_WIDTH = ""4"" *) 
+  (* C_DQ_WIDTH = ""32"" *) 
+  (* C_EMIO_GPIO_WIDTH = ""64"" *) 
+  (* C_EN_EMIO_ENET0 = ""0"" *) 
+  (* C_EN_EMIO_ENET1 = ""0"" *) 
+  (* C_EN_EMIO_PJTAG = ""0"" *) 
+  (* C_EN_EMIO_TRACE = ""0"" *) 
+  (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+  (* C_FCLK_CLK1_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK2_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+  (* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+  (* C_INCLUDE_TRACE_BUFFER = ""0"" *) 
+  (* C_IRQ_F2P_MODE = ""DIRECT"" *) 
+  (* C_MIO_PRIMITIVE = ""54"" *) 
+  (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_NUM_F2P_INTR_INPUTS = ""1"" *) 
+  (* C_PACKAGE_NAME = ""clg400"" *) 
+  (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+  (* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+  (* C_S_AXI_GP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP3_ID_WIDTH = ""6"" *) 
+  (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) 
+  (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+  (* C_TRACE_INTERNAL_WIDTH = ""2"" *) 
+  (* C_TRACE_PIPELINE_WIDTH = ""8"" *) 
+  (* C_USE_AXI_NONSECURE = ""0"" *) 
+  (* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) 
+  (* C_USE_M_AXI_GP0 = ""1"" *) 
+  (* C_USE_M_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_ACP = ""0"" *) 
+  (* C_USE_S_AXI_GP0 = ""0"" *) 
+  (* C_USE_S_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP0 = ""0"" *) 
+  (* C_USE_S_AXI_HP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP2 = ""0"" *) 
+  (* C_USE_S_AXI_HP3 = ""0"" *) 
+  (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) 
+  (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+  (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
+       (.CAN0_PHY_RX(1\'b0),
+        .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+        .CAN1_PHY_RX(1\'b0),
+        .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+        .Core0_nFIQ(1\'b0),
+        .Core0_nIRQ(1\'b0),
+        .Core1_nFIQ(1\'b0),
+        .Core1_nIRQ(1\'b0),
+        .DDR_ARB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .DDR_Addr(DDR_Addr),
+        .DDR_BankAddr(DDR_BankAddr),
+        .DDR_CAS_n(DDR_CAS_n),
+        .DDR_CKE(DDR_CKE),
+        .DDR_CS_n(DDR_CS_n),
+        .DDR_Clk(DDR_Clk),
+        .DDR_Clk_n(DDR_Clk_n),
+        .DDR_DM(DDR_DM),
+        .DDR_DQ(DDR_DQ),
+        .DDR_DQS(DDR_DQS),
+        .DDR_DQS_n(DDR_DQS_n),
+        .DDR_DRSTB(DDR_DRSTB),
+        .DDR_ODT(DDR_ODT),
+        .DDR_RAS_n(DDR_RAS_n),
+        .DDR_VRN(DDR_VRN),
+        .DDR_VRP(DDR_VRP),
+        .DDR_WEB(DDR_WEB),
+        .DMA0_ACLK(1\'b0),
+        .DMA0_DAREADY(1\'b0),
+        .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+        .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+        .DMA0_DRLAST(1\'b0),
+        .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+        .DMA0_DRTYPE({1\'b0,1\'b0}),
+        .DMA0_DRVALID(1\'b0),
+        .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+        .DMA1_ACLK(1\'b0),
+        .DMA1_DAREADY(1\'b0),
+        .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+        .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+        .DMA1_DRLAST(1\'b0),
+        .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+        .DMA1_DRTYPE({1\'b0,1\'b0}),
+        .DMA1_DRVALID(1\'b0),
+        .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+        .DMA2_ACLK(1\'b0),
+        .DMA2_DAREADY(1\'b0),
+        .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+        .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+        .DMA2_DRLAST(1\'b0),
+        .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+        .DMA2_DRTYPE({1\'b0,1\'b0}),
+        .DMA2_DRVALID(1\'b0),
+        .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+        .DMA3_ACLK(1\'b0),
+        .DMA3_DAREADY(1\'b0),
+        .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+        .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+        .DMA3_DRLAST(1\'b0),
+        .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+        .DMA3_DRTYPE({1\'b0,1\'b0}),
+        .DMA3_DRVALID(1\'b0),
+        .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+        .ENET0_EXT_INTIN(1\'b0),
+        .ENET0_GMII_COL(1\'b0),
+        .ENET0_GMII_CRS(1\'b0),
+        .ENET0_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET0_GMII_RX_CLK(1\'b0),
+        .ENET0_GMII_RX_DV(1\'b0),
+        .ENET0_GMII_RX_ER(1\'b0),
+        .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET0_GMII_TX_CLK(1\'b0),
+        .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+        .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+        .ENET0_MDIO_I(1\'b0),
+        .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+        .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+        .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+        .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+        .ENET1_EXT_INTIN(1\'b0),
+        .ENET1_GMII_COL(1\'b0),
+        .ENET1_GMII_CRS(1\'b0),
+        .ENET1_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET1_GMII_RX_CLK(1\'b0),
+        .ENET1_GMII_RX_DV(1\'b0),
+        .ENET1_GMII_RX_ER(1\'b0),
+        .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET1_GMII_TX_CLK(1\'b0),
+        .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+        .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+        .ENET1_MDIO_I(1\'b0),
+        .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+        .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+        .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+        .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+        .EVENT_EVENTI(1\'b0),
+        .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+        .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+        .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+        .FCLK_CLK0(FCLK_CLK0),
+        .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+        .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+        .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+        .FCLK_CLKTRIG0_N(1\'b0),
+        .FCLK_CLKTRIG1_N(1\'b0),
+        .FCLK_CLKTRIG2_N(1\'b0),
+        .FCLK_CLKTRIG3_N(1\'b0),
+        .FCLK_RESET0_N(FCLK_RESET0_N),
+        .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+        .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+        .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+        .FPGA_IDLE_N(1\'b0),
+        .FTMD_TRACEIN_ATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_CLK(1\'b0),
+        .FTMD_TRACEIN_DATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_VALID(1\'b0),
+        .FTMT_F2P_DEBUG({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+        .FTMT_F2P_TRIG_0(1\'b0),
+        .FTMT_F2P_TRIG_1(1\'b0),
+        .FTMT_F2P_TRIG_2(1\'b0),
+        .FTMT_F2P_TRIG_3(1\'b0),
+        .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+        .FTMT_P2F_TRIGACK_0(1\'b0),
+        .FTMT_P2F_TRIGACK_1(1\'b0),
+        .FTMT_P2F_TRIGACK_2(1\'b0),
+        .FTMT_P2F_TRIGACK_3(1\'b0),
+        .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+        .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+        .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+        .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+        .GPIO_I(GPIO_I),
+        .GPIO_O(GPIO_O),
+        .GPIO_T(GPIO_T),
+        .I2C0_SCL_I(1\'b0),
+        .I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
+        .I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
+        .I2C0_SDA_I(1\'b0),
+        .I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
+        .I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
+        .I2C1_SCL_I(1\'b0),
+        .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+        .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+        .I2C1_SDA_I(1\'b0),
+        .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+        .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+        .IRQ_F2P(1\'b0),
+        .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+        .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+        .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+        .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+        .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+        .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+        .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+        .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+        .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+        .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+        .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+        .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+        .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+        .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+        .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+        .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+        .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+        .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+        .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+        .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+        .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+        .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+        .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+        .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+        .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+        .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+        .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+        .MIO(MIO),
+        .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+        .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+        .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+        .M_AXI_GP1_ACLK(1\'b0),
+        .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+        .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARREADY(1\'b0),
+        .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+        .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWREADY(1\'b0),
+        .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+        .M_AXI_GP1_BID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+        .M_AXI_GP1_BRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_BVALID(1\'b0),
+        .M_AXI_GP1_RDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RLAST(1\'b0),
+        .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+        .M_AXI_GP1_RRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_RVALID(1\'b0),
+        .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+        .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+        .M_AXI_GP1_WREADY(1\'b0),
+        .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+        .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+        .PJTAG_TCK(1\'b0),
+        .PJTAG_TDI(1\'b0),
+        .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+        .PJTAG_TMS(1\'b0),
+        .PS_CLK(PS_CLK),
+        .PS_PORB(PS_PORB),
+        .PS_SRSTB(PS_SRSTB),
+        .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+        .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO0_CDN(1\'b0),
+        .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+        .SDIO0_CLK_FB(1\'b0),
+        .SDIO0_CMD_I(1\'b0),
+        .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+        .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+        .SDIO0_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+        .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+        .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+        .SDIO0_WP(SDIO0_WP),
+        .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+        .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO1_CDN(1\'b0),
+        .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+        .SDIO1_CLK_FB(1\'b0),
+        .SDIO1_CMD_I(1\'b0),
+        .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+        .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+        .SDIO1_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+        .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+        .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+        .SDIO1_WP(1\'b0),
+        .SPI0_MISO_I(1\'b0),
+        .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+        .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+        .SPI0_MOSI_I(1\'b0),
+        .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+        .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+        .SPI0_SCLK_I(1\'b0),
+        .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+        .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+        .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+        .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+        .SPI0_SS_I(1\'b0),
+        .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+        .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+        .SPI1_MISO_I(1\'b0),
+        .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+        .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+        .SPI1_MOSI_I(1\'b0),
+        .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+        .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+        .SPI1_SCLK_I(1\'b0),
+        .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+        .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+        .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+        .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+        .SPI1_SS_I(1\'b0),
+        .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+        .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+        .SRAM_INTIN(1\'b0),
+        .S_AXI_ACP_ACLK(1\'b0),
+        .S_AXI_ACP_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+        .S_AXI_ACP_ARID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+        .S_AXI_ACP_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARVALID(1\'b0),
+        .S_AXI_ACP_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+        .S_AXI_ACP_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWVALID(1\'b0),
+        .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_BREADY(1\'b0),
+        .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+        .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+        .S_AXI_ACP_RREADY(1\'b0),
+        .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+        .S_AXI_ACP_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WLAST(1\'b0),
+        .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+        .S_AXI_ACP_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WVALID(1\'b0),
+        .S_AXI_GP0_ACLK(1\'b0),
+        .S_AXI_GP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+        .S_AXI_GP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+        .S_AXI_GP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARVALID(1\'b0),
+        .S_AXI_GP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+        .S_AXI_GP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWVALID(1\'b0),
+        .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_BREADY(1\'b0),
+        .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+        .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+        .S_AXI_GP0_RREADY(1\'b0),
+        .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+        .S_AXI_GP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WLAST(1\'b0),
+        .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+        .S_AXI_GP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WVALID(1\'b0),
+        .S_AXI_GP1_ACLK(1\'b0),
+        .S_AXI_GP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+        .S_AXI_GP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+        .S_AXI_GP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARVALID(1\'b0),
+        .S_AXI_GP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+        .S_AXI_GP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWVALID(1\'b0),
+        .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_BREADY(1\'b0),
+        .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+        .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+        .S_AXI_GP1_RREADY(1\'b0),
+        .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+        .S_AXI_GP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WLAST(1\'b0),
+        .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+        .S_AXI_GP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WVALID(1\'b0),
+        .S_AXI_HP0_ACLK(1\'b0),
+        .S_AXI_HP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+        .S_AXI_HP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+        .S_AXI_HP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARVALID(1\'b0),
+        .S_AXI_HP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+        .S_AXI_HP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWVALID(1\'b0),
+        .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_BREADY(1\'b0),
+        .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+        .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP0_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+        .S_AXI_HP0_RREADY(1\'b0),
+        .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+        .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WLAST(1\'b0),
+        .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+        .S_AXI_HP0_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WVALID(1\'b0),
+        .S_AXI_HP1_ACLK(1\'b0),
+        .S_AXI_HP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+        .S_AXI_HP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+        .S_AXI_HP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARVALID(1\'b0),
+        .S_AXI_HP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+        .S_AXI_HP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWVALID(1\'b0),
+        .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_BREADY(1\'b0),
+        .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+        .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP1_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+        .S_AXI_HP1_RREADY(1\'b0),
+        .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+        .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WLAST(1\'b0),
+        .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+        .S_AXI_HP1_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WVALID(1\'b0),
+        .S_AXI_HP2_ACLK(1\'b0),
+        .S_AXI_HP2_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+        .S_AXI_HP2_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+        .S_AXI_HP2_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARVALID(1\'b0),
+        .S_AXI_HP2_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+        .S_AXI_HP2_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWVALID(1\'b0),
+        .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_BREADY(1\'b0),
+        .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+        .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP2_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+        .S_AXI_HP2_RREADY(1\'b0),
+        .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+        .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WLAST(1\'b0),
+        .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+        .S_AXI_HP2_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WVALID(1\'b0),
+        .S_AXI_HP3_ACLK(1\'b0),
+        .S_AXI_HP3_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+        .S_AXI_HP3_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+        .S_AXI_HP3_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARVALID(1\'b0),
+        .S_AXI_HP3_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+        .S_AXI_HP3_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWVALID(1\'b0),
+        .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_BREADY(1\'b0),
+        .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+        .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP3_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+        .S_AXI_HP3_RREADY(1\'b0),
+        .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+        .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WLAST(1\'b0),
+        .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
+        .S_AXI_HP3_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WVALID(1\'b0),
+        .TRACE_CLK(1\'b0),
+        .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+        .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
+        .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+        .TTC0_CLK0_IN(1\'b0),
+        .TTC0_CLK1_IN(1\'b0),
+        .TTC0_CLK2_IN(1\'b0),
+        .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+        .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+        .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+        .TTC1_CLK0_IN(1\'b0),
+        .TTC1_CLK1_IN(1\'b0),
+        .TTC1_CLK2_IN(1\'b0),
+        .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+        .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+        .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+        .UART0_CTSN(1\'b0),
+        .UART0_DCDN(1\'b0),
+        .UART0_DSRN(1\'b0),
+        .UART0_DT'b'RN(NLW_inst_UART0_DTRN_UNCONNECTED),
+        .UART0_RIN(1\'b0),
+        .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
+        .UART0_RX(1\'b1),
+        .UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
+        .UART1_CTSN(1\'b0),
+        .UART1_DCDN(1\'b0),
+        .UART1_DSRN(1\'b0),
+        .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+        .UART1_RIN(1\'b0),
+        .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+        .UART1_RX(1\'b1),
+        .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+        .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+        .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+        .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+        .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+        .USB1_VBUS_PWRFAULT(1\'b0),
+        .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+        .WDT_CLK_IN(1\'b0),
+        .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = ""4"" *) (* C_DQS_WIDTH = ""4"" *) (* C_DQ_WIDTH = ""32"" *) 
+(* C_EMIO_GPIO_WIDTH = ""64"" *) (* C_EN_EMIO_ENET0 = ""0"" *) (* C_EN_EMIO_ENET1 = ""0"" *) 
+(* C_EN_EMIO_PJTAG = ""0"" *) (* C_EN_EMIO_TRACE = ""0"" *) (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+(* C_FCLK_CLK1_BUF = ""FALSE"" *) (* C_FCLK_CLK2_BUF = ""FALSE"" *) (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+(* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+(* C_INCLUDE_TRACE_BUFFER = ""0"" *) (* C_IRQ_F2P_MODE = ""DIRECT"" *) (* C_MIO_PRIMITIVE = ""54"" *) 
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+(* C_NUM_F2P_INTR_INPUTS = ""1"" *) (* C_PACKAGE_NAME = ""clg400"" *) (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+(* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+(* C_S_AXI_GP0_ID_WIDTH = ""6"" *) (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP0_ID_WIDTH = ""6"" *) (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+(* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP3_ID_WIDTH = ""6"" *) (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+(* C_TRACE_INTERNAL_WIDTH = ""2"" *) (* C_TRACE_PIPELINE_WIDTH = ""8"" *) (* C_USE_AXI_NONSECURE = ""0"" *) 
+(* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) (* C_USE_M_AXI_GP0 = ""1"" *) (* C_USE_M_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_ACP = ""0"" *) (* C_USE_S_AXI_GP0 = ""0"" *) (* C_USE_S_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_HP0 = ""0"" *) (* C_USE_S_AXI_HP1 = ""0"" *) (* C_USE_S_AXI_HP2 = ""0"" *) 
+(* C_USE_S_AXI_HP3 = ""0"" *) (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+(* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
+   (CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TDI,
+    PJTAG_TDO,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    TRACE_CLK_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_PORT_INDCTL,
+    USB1_VBUS_PWRSELECT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARESETN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARESETN,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARESETN,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARESETN,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_ARESETN,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARESETN,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARESETN,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARESETN,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARESETN,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_RSTN,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_RSTN,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_RSTN,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_RSTN,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA3_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DRTYPE,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG_0,
+    FTMT_F2P_TRIGACK_0,
+    FTMT_F2P_TRIG_1,
+    FTMT_F2P_TRIGACK_1,
+    FTMT_F2P_TRIG_2,
+    FTMT_F2P_TRIGACK_2,
+    FTMT_F2P_TRIG_3,
+    FTMT_F2P_TRIGACK_3,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK_0,
+    FTMT_P2F_TRIG_0,
+    FTMT_P2F_TRIGACK_1,
+    FTMT_P2F_TRIG_1,
+    FTMT_P2F_TRIGACK_2,
+    FTMT_P2F_TRIG_2,
+    FTMT_P2F_TRIGACK_3,
+    FTMT_P2F_TRIG_3,
+    FTMT_P2F_DEBUG,
+    FPGA_IDLE_N,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    DDR_ARB,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0]ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input ENET0_EXT_INTIN;
+  input [7:0]ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0]ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input ENET1_EXT_INTIN;
+  input [7:0]ENET1_GMII_RXD;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TDI;
+  output PJTAG_TDO;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0]SDIO0_DATA_I;
+  output [3:0]SDIO0_DATA_O;
+  output [3:0]SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0]SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0]SDIO1_DATA_I;
+  output [3:0]SDIO1_DATA_O;
+  output [3:0]SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0]SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [1:0]TRACE_DATA;
+  output TRACE_CLK_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output [1:0]USB1_PORT_INDCTL;
+  output USB1_VBUS_PWRSELECT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARESETN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARESETN;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [11:0]M_AXI_GP1_ARID;
+  output [11:0]M_AXI_GP1_AWID;
+  output [11:0]M_AXI_GP1_WID;
+  output [1:0]M_AXI_GP1_ARBURST;
+  output [1:0]M_AXI_GP1_ARLOCK;
+  output [2:0]M_AXI_GP1_ARSIZE;
+  output [1:0]M_AXI_GP1_AWBURST;
+  output [1:0]M_AXI_GP1_AWLOCK;
+  output [2:0]M_AXI_GP1_AWSIZE;
+  output [2:0]M_AXI_GP1_ARPROT;
+  output [2:0]M_AXI_GP1_AWPROT;
+  output [31:0]M_AXI_GP1_ARADDR;
+  output [31:0]M_AXI_GP1_AWADDR;
+  output [31:0]M_AXI_GP1_WDATA;
+  output [3:0]M_AXI_GP1_ARCACHE;
+  output [3:0]M_AXI_GP1_ARLEN;
+  output [3:0]M_AXI_GP1_ARQOS;
+  output [3:0]M_AXI_GP1_AWCACHE;
+  output [3:0]M_AXI_GP1_AWLEN;
+  output [3:0]M_AXI_GP1_AWQOS;
+  output [3:0]M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [11:0]M_AXI_GP1_BID;
+  input [11:0]M_AXI_GP1_RID;
+  input [1:0]M_AXI_GP1_BRESP;
+  input [1:0]M_AXI_GP1_RRESP;
+  input [31:0]M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARESETN;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0]S_AXI_GP0_BRESP;
+  output [1:0]S_AXI_GP0_RRESP;
+  output [31:0]S_AXI_GP0_RDATA;
+  output [5:0]S_AXI_GP0_BID;
+  output [5:0]S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0]S_AXI_GP0_ARBURST;
+  input [1:0]S_AXI_GP0_ARLOCK;
+  input [2:0]S_AXI_GP0_ARSIZE;
+  input [1:0]S_AXI_GP0_AWBURST;
+  input [1:0]S_AXI_GP0_AWLOCK;
+  input [2:0]S_AXI_GP0_AWSIZE;
+  input [2:0]S_AXI_GP0_ARPROT;
+  input [2:0]S_AXI_GP0_AWPROT;
+  input [31:0]S_AXI_GP0_ARADDR;
+  input [31:0]S_AXI_GP0_AWADDR;
+  input [31:0]S_AXI_GP0_WDATA;
+  input [3:0]S_AXI_GP0_ARCACHE;
+  input [3:0]S_AXI_GP0_ARLEN;
+  input [3:0]S_AXI_GP0_ARQOS;
+  input [3:0]S_AXI_GP0_AWCACHE;
+  input [3:0]S_AXI_GP0_AWLEN;
+  input [3:0]S_AXI_GP0_AWQOS;
+  input [3:0]S_AXI_GP0_WSTRB;
+  input [5:0]S_AXI_GP0_ARID;
+  input [5:0]S_AXI_GP0_AWID;
+  input [5:0]S_AXI_GP0_WID;
+  output S_AXI_GP1_ARESETN;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0]S_AXI_GP1_BRESP;
+  output [1:0]S_AXI_GP1_RRESP;
+  output [31:0]S_AXI_GP1_RDATA;
+  output [5:0]S_AXI_GP1_BID;
+  output [5:0]S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0]S_AXI_GP1_ARBURST;
+  input [1:0]S_AXI_GP1_ARLOCK;
+  input [2:0]S_AXI_GP1_ARSIZE;
+  input [1:0]S_AXI_GP1_AWBURST;
+  input [1:0]S_AXI_GP1_AWLOCK;
+  input [2:0]S_AXI_GP1_AWSIZE;
+  input [2:0]S_AXI_GP1_ARPROT;
+  input [2:0]S_AXI_GP1_AWPROT;
+  input [31:0]S_AXI_GP1_ARADDR;
+  input [31:0]S_AXI_GP1_AWADDR;
+  input [31:0]S_AXI_GP1_WDATA;
+  input [3:0]S_AXI_GP1_ARCACHE;
+  input [3:0]S_AXI_GP1_ARLEN;
+  input [3:0]S_AXI_GP1_ARQOS;
+  input [3:0]S_AXI_GP1_AWCACHE;
+  input [3:0]S_AXI_GP1_AWLEN;
+  input [3:0]S_AXI_GP1_AWQOS;
+  input [3:0]S_AXI_GP1_WSTRB;
+  input [5:0]S_AXI_GP1_ARID;
+  input [5:0]S_AXI_GP1_AWID;
+  input [5:0]S_AXI_GP1_WID;
+  output S_AXI_ACP_ARESETN;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0]S_AXI_ACP_BRESP;
+  output [1:0]S_AXI_ACP_RRESP;
+  output [2:0]S_AXI_ACP_BID;
+  output [2:0]S_AXI_ACP_RID;
+  output [63:0]S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0]S_AXI_ACP_ARID;
+  input [2:0]S_AXI_ACP_ARPROT;
+  input [2:0]S_AXI_ACP_AWID;
+  input [2:0]S_AXI_ACP_AWPROT;
+  input [2:0]S_AXI_ACP_WID;
+  input [31:0]S_AXI_ACP_ARADDR;
+  input [31:0]S_AXI_ACP_AWADDR;
+  input [3:0]S_AXI_ACP_ARCACHE;
+  input [3:0]S_AXI_ACP_ARLEN;
+  input [3:0]S_AXI_ACP_ARQOS;
+  input [3:0]S_AXI_ACP_AWCACHE;
+  input [3:0]S_AXI_ACP_AWLEN;
+  input [3:0]S_AXI_ACP_AWQOS;
+  input [1:0]S_AXI_ACP_ARBURST;
+  input [1:0]S_AXI_ACP_ARLOCK;
+  input [2:0]S_AXI_ACP_ARSIZE;
+  input [1:0]S_AXI_ACP_AWBURST;
+  input [1:0]S_AXI_ACP_AWLOCK;
+  input [2:0]S_AXI_ACP_AWSIZE;
+  input [4:0]S_AXI_ACP_ARUSER;
+  input [4:0]S_AXI_ACP_AWUSER;
+  input [63:0]S_AXI_ACP_WDATA;
+  input [7:0]S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARESETN;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0]S_AXI_HP0_BRESP;
+  output [1:0]S_AXI_HP0_RRESP;
+  output [5:0]S_AXI_HP0_BID;
+  output [5:0]S_AXI_HP0_RID;
+  output [63:0]S_AXI_HP0_RDATA;
+  output [7:0]S_AXI_HP0_RCOUNT;
+  output [7:0]S_AXI_HP0_WCOUNT;
+  output [2:0]S_AXI_HP0_RACOUNT;
+  output [5:0]S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0]S_AXI_HP0_ARBURST;
+  input [1:0]S_AXI_HP0_ARLOCK;
+  input [2:0]S_AXI_HP0_ARSIZE;
+  input [1:0]S_AXI_HP0_AWBURST;
+  input [1:0]S_AXI_HP0_AWLOCK;
+  input [2:0]S_AXI_HP0_AWSIZE;
+  input [2:0]S_AXI_HP0_ARPROT;
+  input [2:0]S_AXI_HP0_AWPROT;
+  input [31:0]S_AXI_HP0_ARADDR;
+  input [31:0]S_AXI_HP0_AWADDR;
+  input [3:0]S_AXI_HP0_ARCACHE;
+  input [3:0]S_AXI_HP0_ARLEN;
+  input [3:0]S_AXI_HP0_ARQOS;
+  input [3:0]S_AXI_HP0_AWCACHE;
+  input [3:0]S_AXI_HP0_AWLEN;
+  input [3:0]S_AXI_HP0_AWQOS;
+  input [5:0]S_AXI_HP0_ARID;
+  input [5:0]S_AXI_HP0_AWID;
+  input [5:0]S_AXI_HP0_WID;
+  input [63:0]S_AXI_HP0_WDATA;
+  input [7:0]S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARESETN;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0]S_AXI_HP1_BRESP;
+  output [1:0]S_AXI_HP1_RRESP;
+  output [5:0]S_AXI_HP1_BID;
+  output [5:0]S_AXI_HP1_RID;
+  output [63:0]S_AXI_HP1_RDATA;
+  output [7:0]S_AXI_HP1_RCOUNT;
+  output [7:0]S_AXI_HP1_WCOUNT;
+  output [2:0]S_AXI_HP1_RACOUNT;
+  output [5:0]S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0]S_AXI_HP1_ARBURST;
+  input [1:0]S_AXI_HP1_ARLOCK;
+  input [2:0]S_AXI_HP1_ARSIZE;
+  input [1:0]S_AXI_HP1_AWBURST;
+  input [1:0]S_AXI_HP1_AWLOCK;
+  input [2:0]S_AXI_HP1_AWSIZE;
+  input [2:0]S_AXI_HP1_ARPROT;
+  input [2:0]S_AXI_HP1_AWPROT;
+  input [31:0]S_AXI_HP1_ARADDR;
+  input [31:0]S_AXI_HP1_AWADDR;
+  input [3:0]S_AXI_HP1_ARCACHE;
+  input [3:0]S_AXI_HP1_ARLEN;
+  input [3:0]S_AXI_HP1_ARQOS;
+  input [3:0]S_AXI_HP1_AWCACHE;
+  input [3:0]S_AXI_HP1_AWLEN;
+  input [3:0]S_AXI_HP1_AWQOS;
+  input [5:0]S_AXI_HP1_ARID;
+  input [5:0]S_AXI_HP1_AWID;
+  input [5:0]S_AXI_HP1_WID;
+  input [63:0]S_AXI_HP1_WDATA;
+  input [7:0]S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARESETN;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0]S_AXI_HP2_BRESP;
+  output [1:0]S_AXI_HP2_RRESP;
+  output [5:0]S_AXI_HP2_BID;
+  output [5:0]S_AXI_HP2_RID;
+  output [63:0]S_AXI_HP2_RDATA;
+  output [7:0]S_AXI_HP2_RCOUNT;
+  output [7:0]S_AXI_HP2_WCOUNT;
+  output [2:0]S_AXI_HP2_RACOUNT;
+  output [5:0]S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0]S_AXI_HP2_ARBURST;
+  input [1:0]S_AXI_HP2_ARLOCK;
+  input [2:0]S_AXI_HP2_ARSIZE;
+  input [1:0]S_AXI_HP2_AWBURST;
+  input [1:0]S_AXI_HP2_AWLOCK;
+  input [2:0]S_AXI_HP2_AWSIZE;
+  input [2:0]S_AXI_HP2_ARPROT;
+  input [2:0]S_AXI_HP2_AWPROT;
+  input [31:0]S_AXI_HP2_ARADDR;
+  input [31:0]S_AXI_HP2_AWADDR;
+  input [3:0]S_AXI_HP2_ARCACHE;
+  input [3:0]S_AXI_HP2_ARLEN;
+  input [3:0]S_AXI_HP2_ARQOS;
+  input [3:0]S_AXI_HP2_AWCACHE;
+  input [3:0]S_AXI_HP2_AWLEN;
+  input [3:0]S_AXI_HP2_AWQOS;
+  input [5:0]S_AXI_HP2_ARID;
+  input [5:0]S_AXI_HP2_AWID;
+  input [5:0]S_AXI_HP2_WID;
+  input [63:0]S_AXI_HP2_WDATA;
+  input [7:0]S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARESETN;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0]S_AXI_HP3_BRESP;
+  output [1:0]S_AXI_HP3_RRESP;
+  output [5:0]S_AXI_HP3_BID;
+  output [5:0]S_AXI_HP3_RID;
+  output [63:0]S_AXI_HP3_RDATA;
+  output [7:0]S_AXI_HP3_RCOUNT;
+  output [7:0]S_AXI_HP3_WCOUNT;
+  output [2:0]S_AXI_HP3_RACOUNT;
+  output [5:0]S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0]S_AXI_HP3_ARBURST;
+  input [1:0]S_AXI_HP3_ARLOCK;
+  input [2:0]S_AXI_HP3_ARSIZE;
+  input [1:0]S_AXI_HP3_AWBURST;
+  input [1:0]S_AXI_HP3_AWLOCK;
+  input [2:0]S_AXI_HP3_AWSIZE;
+  input [2:0]S_AXI_HP3_ARPROT;
+  input [2:0]S_AXI_HP3_AWPROT;
+  input [31:0]S_AXI_HP3_ARADDR;
+  input [31:0]S_AXI_HP3_AWADDR;
+  input [3:0]S_AXI_HP3_ARCACHE;
+  input [3:0]S_AXI_HP3_ARLEN;
+  input [3:0]S_AXI_HP3_ARQOS;
+  input [3:0]S_AXI_HP3_AWCACHE;
+  input [3:0]S_AXI_HP3_AWLEN;
+  input [3:0]S_AXI_HP3_AWQOS;
+  input [5:0]S_AXI_HP3_ARID;
+  input [5:0]S_AXI_HP3_AWID;
+  input [5:0]S_AXI_HP3_WID;
+  input [63:0]S_AXI_HP3_WDATA;
+  input [7:0]S_AXI_HP3_WSTRB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+  input [0:0]IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output [1:0]DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  output DMA0_RSTN;
+  output [1:0]DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  output DMA1_RSTN;
+  output [1:0]DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  output DMA2_RSTN;
+  output [1:0]DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  output DMA3_RSTN;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input DMA3_DRVALID;
+  input [1:0]DMA0_DRTYPE;
+  input [1:0]DMA1_DRTYPE;
+  input [1:0]DMA2_DRTYPE;
+  input [1:0]DMA3_DRTYPE;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input [31:0]FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0]FTMD_TRACEIN_ATID;
+  input FTMT_F2P_TRIG_0;
+  output FTMT_F2P_TRIGACK_0;
+  input FTMT_F2P_TRIG_1;
+  output FTMT_F2P_TRIGACK_1;
+  input FTMT_F2P_TRIG_2;
+  output FTMT_F2P_TRIGACK_2;
+  input FTMT_F2P_TRIG_3;
+  output FTMT_F2P_TRIGACK_3;
+  input [31:0]FTMT_F2P_DEBUG;
+  input FTMT_P2F_TRIGACK_0;
+  output FTMT_P2F_TRIG_0;
+  input FTMT_P2F_TRIGACK_1;
+  output FTMT_P2F_TRIG_1;
+  input FTMT_P2F_TRIGACK_2;
+  output FTMT_P2F_TRIG_2;
+  input FTMT_P2F_TRIGACK_3;
+  output FTMT_P2F_TRIG_3;
+  output [31:0]FTMT_P2F_DEBUG;
+  input FPGA_IDLE_N;
+  output EVENT_EVENTO;
+  output [1:0]EVENT_STANDBYWFE;
+  output [1:0]EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  input [3:0]DDR_ARB;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+
+  wire \\<const0> ;
+  wire CAN0_PHY_RX;
+  wire CAN0_PHY_TX;
+  wire CAN1_PHY_RX;
+  wire CAN1_PHY_TX;
+  wire Core0_nFIQ;
+  wire Core0_nIRQ;
+  wire Core1_nFIQ;
+  wire Core1_nIRQ;
+  wire [3:0]DDR_ARB;
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire DMA0_ACLK;
+  wire DMA0_DAREADY;
+  wire [1:0]DMA0_DATYPE;
+  wire DMA0_DAVALID;
+  wire DMA0_DRLAST;
+  wire DMA0_DRREADY;
+  wire [1:0]DMA0_DRTYPE;
+  wire DMA0_DRVALID;
+  wire DMA0_RSTN;
+  wire DMA1_ACLK;
+  wire DMA1_DAREADY;
+  wire [1:0]DMA1_DATYPE;
+  wire DMA1_DAVALID;
+  wire DMA1_DRLAST;
+  wire DMA1_DRREADY;
+  wire [1:0]DMA1_DRTYPE;
+  wire DMA1_DRVALID;
+  wire DMA1_RSTN;
+  wire DMA2_ACLK;
+  wire DMA2_DAREADY;
+  wire [1:0]DMA2_DATYPE;
+  wire DMA2_DAVALID;
+  wire DMA2_DRLAST;
+  wire DMA2_DRREADY;
+  wire [1:0]DMA2_DRTYPE;
+  wire DMA2_DRVALID;
+  wire DMA2_RSTN;
+  wire DMA3_ACLK;
+  wire DMA3_DAREADY;
+  wire [1:0]DMA3_DATYPE;
+  wire DMA3_DAVALID;
+  wire DMA3_DRLAST;
+  wire DMA3_DRREADY;
+  wire [1:0]DMA3_DRTYPE;
+  wire DMA3_DRVALID;
+  wire DMA3_RSTN;
+  wire ENET0_EXT_INTIN;
+  wire ENET0_GMII_RX_CLK;
+  wire ENET0_GMII_TX_CLK;
+  wire ENET0_MDIO_I;
+  wire ENET0_MDIO_MDC;
+  wire ENET0_MDIO_O;
+  wire ENET0_MDIO_T;
+  wire ENET0_MDIO_T_n;
+  wire ENET0_PTP_DELAY_REQ_RX;
+  wire ENET0_PTP_DELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_REQ_RX;
+  wire ENET0_PTP_PDELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_RESP_RX;
+  wire ENET0_PTP_PDELAY_RESP_TX;
+  wire ENET0_PTP_SYNC_FRAME_RX;
+  wire ENET0_PTP_SYNC_FRAME_TX;
+  wire ENET0_SOF_RX;
+  wire ENET0_SOF_TX;
+  wire ENET1_EXT_INTIN;
+  wire ENET1_GMII_RX_CLK;
+  wire ENET1_GMII_TX_CLK;
+  wire ENET1_MDIO_I;
+  wire ENET1_MDIO_MDC;
+  wire ENET1_MDIO_O;
+  wire ENET1_MDIO_T;
+  wire ENET1_MDIO_T_n;
+  wire ENET1_PTP_DELAY_REQ_RX;
+  wire ENET1_PTP_DELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_REQ_RX;
+  wire ENET1_PTP_PDELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_RESP_RX;
+  wire ENET1_PTP_PDELAY_RESP_TX;
+  wire ENET1_PTP_SYNC_FRAME_RX;
+  wire ENET1_PTP_SYNC_FRAME_TX;
+  wire ENET1_SOF_RX;
+  wire ENET1_SOF_TX;
+  wire EVENT_EVENTI;
+  wire EVENT_EVENTO;
+  wire [1:0]EVENT_STANDBYWFE;
+  wire [1:0]EVENT_STANDBYWFI;
+  wire FCLK_CLK0;
+  wire FCLK_CLK1;
+  wire FCLK_CLK2;
+  wire FCLK_CLK3;
+  wire [0:0]FCLK_CLK_unbuffered;
+  wire FCLK_RESET0_N;
+  wire FCLK_RESET1_N;
+  wire FCLK_RESET2_N;
+  wire FCLK_RESET3_N;
+  wire FPGA_IDLE_N;
+  wire FTMD_TRACEIN_CLK;
+  wire [31:0]FTMT_F2P_DEBUG;
+  wire FTMT_F2P_TRIGACK_0;
+  wire FTMT_F2P_TRIGACK_1;
+  wire FTMT_F2P_TRIGACK_2;
+  wire FTMT_F2P_TRIGACK_3;
+  wire FTMT_F2P_TRIG_0;
+  wire FTMT_F2P_TRIG_1;
+  wire FTMT_F2P_TRIG_2;
+  wire FTMT_F2P_TRIG_3;
+  wire [31:0]FTMT_P2F_DEBUG;
+  wire FTMT_P2F_TRIGACK_0;
+  wire FTMT_P2F_TRIGACK_1;
+  wire FTMT_P2F_TRIGACK_2;
+  wire FTMT_P2F_TRIGACK_3;
+  wire FTMT_P2F_TRIG_0;
+  wire FTMT_P2F_TRIG_1;
+  wire FTMT_P2F_TRIG_2;
+  wire FTMT_P2F_TRIG_3;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SCL_T_n;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire I2C0_SDA_T_n;
+  wire I2C1_SCL_I;
+  wire I2C1_SCL_O;
+  wire I2C1_SCL_T;
+  wire I2C1_SCL_T_n;
+  wire I2C1_SDA_I;
+  wire I2C1_SDA_O;
+  wire I2C1_SDA_T;
+  wire I2C1_SDA_T_n;
+  wire [0:0]IRQ_F2P;
+  wire IRQ_P2F_CAN0;
+  wire IRQ_P2F_CAN1;
+  wire IRQ_P2F_CTI;
+  wire IRQ_P2F_DMAC0;
+  wire IRQ_P2F_DMAC1;
+  wire IRQ_P2F_DMAC2;
+  wire IRQ_P2F_DMAC3;
+  wire IRQ_P2F_DMAC4;
+  wire IRQ_P2F_DMAC5;
+  wire IRQ_P2F_DMAC6;
+  wire IRQ_P2F_DMAC7;
+  wire IRQ_P2F_DMAC_ABORT;
+  wire IRQ_P2F_ENET0;
+  wire IRQ_P2F_ENET1;
+  wire IRQ_P2F_ENET_WAKE0;
+  wire IRQ_P2F_ENET_WAKE1;
+  wire IRQ_P2F_GPIO;
+  wire IRQ_P2F_I2C0;
+  wire IRQ_P2F_I2C1;
+  wire IRQ_P2F_QSPI;
+  wire IRQ_P2F_SDIO0;
+  wire IRQ_P2F_SDIO1;
+  wire IRQ_P2F_SMC;
+  wire IRQ_P2F_SPI0;
+  wire IRQ_P2F_SPI1;
+  wire IRQ_P2F_UART0;
+  wire IRQ_P2F_UART1;
+  wire IRQ_P2F_USB0;
+  wire IRQ_P2F_USB1;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire M_AXI_GP0_ARESETN;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [1:0]\\^M_AXI_GP0_ARSIZE ;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [1:0]\\^M_AXI_GP0_AWSIZE ;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire M_AXI_GP1_ACLK;
+  wire [31:0]M_AXI_GP1_ARADDR;
+  wire [1:0]M_AXI_GP1_ARBURST;
+  wire [3:0]M_AXI_GP1_ARCACHE;
+  wire M_AXI_GP1_ARESETN;
+  wire [11:0]M_AXI_GP1_ARID;
+  wire [3:0]M_AXI_GP1_ARLEN;
+  wire [1:0]M_AXI_GP1_ARLOCK;
+  wire [2:0]M_AXI_GP1_ARPROT;
+  wire [3:0]M_AXI_GP1_ARQOS;
+  wire M_AXI_GP1_ARREADY;
+  wire [1:0]\\^M_AXI_GP1_ARSIZE ;
+  wire M_AXI_GP1_ARVALID;
+  wire [31:0]M_AXI_GP1_AWADDR;
+  wire [1:0]M_AXI_GP1_AWBURST;
+  wire [3:0]M_AXI_GP1_AWCACHE;
+  wire [11:0]M_AXI_GP1_AWID;
+  wire [3:0]M_AXI_GP1_AWLEN;
+  wire [1:0]M_AXI_GP1_AWLOCK;
+  wire [2:0]M_AXI_GP1_AWPROT;
+  wire [3:0]M_AXI_GP1_AWQOS;
+  wire M_AXI_GP1_AWREADY;
+  wire [1:0]\\^M_AXI_GP1_AWSIZE ;
+  wire M_AXI_GP1_AWVALID;
+  wire [11:0]M_AXI_GP1_BID;
+  wire M_AXI_GP1_BREADY;
+  wire [1:0]M_AXI_GP1_BRESP;
+  wire M_AXI_GP1_BVALID;
+  wire [31:0]M_AXI_GP1_RDATA;
+  wire [11:0]M_AXI_GP1_RID;
+  wire M_AXI_GP1_RLAST;
+  wire M_AXI_GP1_RREADY;
+  wire [1:0]M_AXI_GP1_RRESP;
+  wire M_AXI_GP1_RVALID;
+  wire [31:0]M_AXI_GP1_WDATA;
+  wire [11:0]M_AXI_GP1_WID;
+  wire M_AXI_GP1_WLAST;
+  wire M_AXI_GP1_WREADY;
+  wire [3:0]M_AXI_GP1_WSTRB;
+  wire M_AXI_GP1_WVALID;
+  wire PJTAG_TCK;
+  wire PJTAG_TDI;
+  wire PJTAG_TMS;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_BUSPOW;
+  wire [2:0]SDIO0_BUSVOLT;
+  wire SDIO0_CDN;
+  wire SDIO0_CLK;
+  wire SDIO0_CLK_FB;
+  wire SDIO0_CMD_I;
+  wire SDIO0_CMD_O;
+  wire SDIO0_CMD_T;
+  wire SDIO0_CMD_T_n;
+  wire [3:0]SDIO0_DATA_I;
+  wire [3:0]SDIO0_DATA_O;
+  wire [3:0]SDIO0_DATA_T;
+  wire [3:0]SDIO0_DATA_T_n;
+  wire SDIO0_LED;
+  wire SDIO0_WP;
+  wire SDIO1_BUSPOW;
+  wire [2:0]SDIO1_BUSVOLT;
+  wire SDIO1_CDN;
+  wire SDIO1_CLK;
+  wire SDIO1_CLK_FB;
+  wire SDIO1_CMD_I;
+  wire SDIO1_CMD_O;
+  wire SDIO1_CMD_T;
+  wire SDIO1_CMD_T_n;
+  wire [3:0]SDIO1_DATA_I;
+  wire [3:0]SDIO1_DATA_O;
+  wire [3:0]SDIO1_DATA_T;
+  wire [3:0]SDIO1_DATA_T_n;
+  wire SDIO1_LED;
+  wire SDIO1_WP;
+  wire SPI0_MISO_I;
+  wire SPI0_MISO_O;
+  wire SPI0_MISO_T;
+  wire SPI0_MISO_T_n;
+  wire SPI0_MOSI_I;
+  wire SPI0_MOSI_O;
+  wire SPI0_MOSI_T;
+  wire SPI0_MOSI_T_n;
+  wire SPI0_SCLK_I;
+  wire SPI0_SCLK_O;
+  wire SPI0_SCLK_T;
+  wire SPI0_SCLK_T_n;
+  wire SPI0_SS1_O;
+  wire SPI0_SS2_O;
+  wire SPI0_SS_I;
+  wire SPI0_SS_O;
+  wire SPI0_SS_T;
+  wire SPI0_SS_T_n;
+  wire SPI1_MISO_I;
+  wire SPI1_MISO_O;
+  wire SPI1_MISO_T;
+  wire SPI1_MISO_T_n;
+  wire SPI1_MOSI_I;
+  wire SPI1_MOSI_O;
+  wire SPI1_MOSI_T;
+  wire SPI1_MOSI_T_n;
+  wire SPI1_SCLK_I;
+  wire SPI1_SCLK_O;
+  wire SPI1_SCLK_T;
+  wire SPI1_SCLK_T_n;
+  wire SPI1_SS1_O;
+  wire SPI1_SS2_O;
+  wire SPI1_SS_I;
+  wire SPI1_SS_O;
+  wire SPI1_SS_T;
+  wire SPI1_SS_T_n;
+  wire SRAM_INTIN;
+  wire S_AXI_ACP_ACLK;
+  wire [31:0]S_AXI_ACP_ARADDR;
+  wire [1:0]S_AXI_ACP_ARBURST;
+  wire [3:0]S_AXI_ACP_ARCACHE;
+  wire S_AXI_ACP_ARESETN;
+  wire [2:0]S_AXI_ACP_ARID;
+  wire [3:0]S_AXI_ACP_ARLEN;
+  wire [1:0]S_AXI_ACP_ARLOCK;
+  wire [2:0]S_AXI_ACP_ARPROT;
+  wire [3:0]S_AXI_ACP_ARQOS;
+  wire S_AXI_ACP_ARREADY;
+  wire [2:0]S_AXI_ACP_ARSIZE;
+  wire [4:0]S_AXI_ACP_ARUSER;
+  wire S_AXI_ACP_ARVALID;
+  wire [31:0]S_AXI_ACP_AWADDR;
+  wire [1:0]S_AXI_ACP_AWBURST;
+  wire [3:0]S_AXI_ACP_AWCACHE;
+  wire [2:0]S_AXI_ACP_AWID;
+  wire [3:0]S_AXI_ACP_AWLEN;
+  wire [1:0]S_AXI_ACP_AWLOCK;
+  wire [2:0]S_AXI_ACP_AWPROT;
+  wire [3:0]S_AXI_ACP_AWQOS;
+  wire S_AXI_ACP_AWREADY;
+  wire [2:0]S_AXI_ACP_AWSIZE;
+  wire [4:0]S_AXI_ACP_AWUSER;
+  wire S_AXI_ACP_AWVALID;
+  wire [2:0]S_AXI_ACP_BID;
+  wire S_AXI_ACP_BREADY;
+  wire [1:0]S_AXI_ACP_BRESP;
+  wire S_AXI_ACP_BVALID;
+  wire [63:0]S_AXI_ACP_RDATA;
+  wire [2:0]S_AXI_ACP_RID;
+  wire S_AXI_ACP_RLAST;
+  wire S_AXI_ACP_RREADY;
+  wire [1:0]S_AXI_ACP_RRESP;
+  wire S_AXI_ACP_RVALID;
+  wire [63:0]S_AXI_ACP_WDATA;
+  wire [2:0]S_AXI_ACP_WID;
+  wire S_AXI_ACP_WLAST;
+  wire S_AXI_ACP_WREADY;
+  wire [7:0]S_AXI_ACP_WSTRB;
+  wire S_AXI_ACP_WVALID;
+  wire S_AXI_GP0_ACLK;
+  wire [31:0]S_AXI_GP0_ARADDR;
+  wire [1:0]S_AXI_GP0_ARBURST;
+  wire [3:0]S_AXI_GP0_ARCACHE;
+  wire S_AXI_GP0_ARESETN;
+  wire [5:0]S_AXI_GP0_ARID;
+  wire [3:0]S_AXI_GP0_ARLEN;
+  wire [1:0]S_AXI_GP0_ARLOCK;
+  wire [2:0]S_AXI_GP0_ARPROT;
+  wire [3:0]S_AXI_GP0_ARQOS;
+  wire S_AXI_GP0_ARREADY;
+  wire [2:0]S_AXI_GP0_ARSIZE;
+  wire S_AXI_GP0_ARVALID;
+  wire [31:0]S_AXI_GP0_AWADDR;
+  wire [1:0]S_AXI_GP0_AWBURST;
+  wire [3:0]S_AXI_GP0_AWCACHE;
+  wire [5:0]S_AXI_GP0_AWID;
+  wire [3:0]S_AXI_GP0_AWLEN;
+  wire [1:0]S_AXI_GP0_AWLOCK;
+  wire [2:0]S_AXI_GP0_AWPROT;
+  wire [3:0]S_AXI_GP0_AWQOS;
+  wire S_AXI_GP0_AWREADY;
+  wire [2:0]S_AXI_GP0_AWSIZE;
+  wire S_AXI_GP0_AWVALID;
+  wire [5:0]S_AXI_GP0_BID;
+  wire S_AXI_GP0_BREADY;
+  wire [1:0]S_AXI_GP0_BRESP;
+  wire S_AXI_GP0_BVALID;
+  wire [31:0]S_AXI_GP0_RDATA;
+  wire [5:0]S_AXI_GP0_RID;
+  wire S_AXI_GP0_RLAST;
+  wire S_AXI_GP0_RREADY;
+  wire [1:0]S_AXI_GP0_RRESP;
+  wire S_AXI_GP0_RVALID;
+  wire [31:0]S_AXI_GP0_WDATA;
+  wire [5:0]S_AXI_GP0_WID;
+  wire S_AXI_GP0_WLAST;
+  wire S_AXI_GP0_WREADY;
+  wire [3:0]S_AXI_GP0_WSTRB;
+  wire S_AXI_GP0_WVALID;
+  wire S_AXI_GP1_ACLK;
+  wire [31:0]S_AXI_GP1_ARADDR;
+  wire [1:0]S_AXI_GP1_ARBURST;
+  wire [3:0]S_AXI_GP1_ARCACHE;
+  wire S_AXI_GP1_ARESETN;
+  wire [5:0]S_AXI_GP1_ARID;
+  wire [3:0]S_AXI_GP1_ARLEN;
+  wire [1:0]S_AXI_GP1_ARLOCK;
+  wire [2:0]S_AXI_GP1_ARPROT;
+  wire [3:0]S_AXI_GP1_ARQOS;
+  wire S_AXI_GP1_ARREADY;
+  wire [2:0]S_AXI_GP1_ARSIZE;
+  wire S_AXI_GP1_ARVALID;
+  wire [31:0]S_AXI_GP1_AWADDR;
+  wire [1:0]S_AXI_GP1_AWBURST;
+  wire [3:0]S_AXI_GP1_AWCACHE;
+  wire [5:0]S_AXI_GP1_AWID;
+  wire [3:0]S_AXI_GP1_AWLEN;
+  wire [1:0]S_AXI_GP1_AWLOCK;
+  wire [2:0]S_AXI_GP1_AWPROT;
+  wire [3:0]S_AXI_GP1_AWQOS;
+  wire S_AXI_GP1_AWREADY;
+  wire [2:0]S_AXI_GP1_AWSIZE;
+  wire S_AXI_GP1_AWVALID;
+  wire [5:0]S_AXI_GP1_BID;
+  wire S_AXI_GP1_BREADY;
+  wire [1:0]S_AXI_GP1_BRESP;
+  wire S_AXI_GP1_BVALID;
+  wire [31:0]S_AXI_GP1_RDATA;
+  wire [5:0]S_AXI_GP1_RID;
+  wire S_AXI_GP1_RLAST;
+  wire S_AXI_GP1_RREADY;
+  wire [1:0]S_AXI_GP1_RRESP;
+  wire S_AXI_GP1_RVALID;
+  wire [31:0]S_AXI_GP1_WDATA;
+  wire [5:0]S_AXI_GP1_WID;
+  wire S_AXI_GP1_WLAST;
+  wire S_AXI_GP1_WREADY;
+  wire [3:0]S_AXI_GP1_WSTRB;
+  wire S_AXI_GP1_WVALID;
+  wire S_AXI_HP0_ACLK;
+  wire [31:0]S_AXI_HP0_ARADDR;
+  wire [1:0]S_AXI_HP0_ARBURST;
+  wire [3:0]S_AXI_HP0_ARCACHE;
+  wire S_AXI_HP0_ARESETN;
+  wire [5:0]S_AXI_HP0_ARID;
+  wire [3:0]S_AXI_HP0_ARLEN;
+  wire [1:0]S_AXI_HP0_ARLOCK;
+  wire [2:0]S_AXI_HP0_ARPROT;
+  wire [3:0]S_AXI_HP0_ARQOS;
+  wire S_AXI_HP0_ARREADY;
+  wire [2:0]S_AXI_HP0_ARSIZE;
+  wire S_AXI_HP0_ARVALID;
+  wire [31:0]S_AXI_HP0_AWADDR;
+  wire [1:0]S_AXI_HP0_AWBURST;
+  wire [3:0]S_AXI_HP0_AWCACHE;
+  wire [5:0]S_AXI_HP0_AWID;
+  wire [3:0]S_AXI_HP0_AWLEN;
+  wire [1:0]S_AXI_HP0_AWLOCK;
+  wire [2:0]S_AXI_HP0_AWPROT;
+  wire [3:0]S_AXI_HP0_AWQOS;
+  wire S_AXI_HP0_AWREADY;
+  wire [2:0]S_AXI_HP0_AWSIZE;
+  wire S_AXI_HP0_AWVALID;
+  wire [5:0]S_AXI_HP0_BID;
+  wire S_AXI_HP0_BREADY;
+  wire [1:0]S_AXI_HP0_BRESP;
+  wire S_AXI_HP0_BVALID;
+  wire [2:0]S_AXI_HP0_RACOUNT;
+  wire [7:0]S_AXI_HP0_RCOUNT;
+  wire [63:0]S_AXI_HP0_RDATA;
+  wire S_AXI_HP0_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP0_RID;
+  wire S_AXI_HP0_RLAST;
+  wire S_AXI_HP0_RREADY;
+  wire [1:0]S_AXI_HP0_RRESP;
+  wire S_AXI_HP0_RVALID;
+  wire [5:0]S_AXI_HP0_WACOUNT;
+  wire [7:0]S_AXI_HP0_WCOUNT;
+  wire [63:0]S_AXI_HP0_WDATA;
+  wire [5:0]S_AXI_HP0_WID;
+  wire S_AXI_HP0_WLAST;
+  wire S_AXI_HP0_WREADY;
+  wire S_AXI_HP0_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP0_WSTRB;
+  wire S_AXI_HP0_WVALID;
+  wire S_AXI_HP1_ACLK;
+  wire [31:0]S_AXI_HP1_ARADDR;
+  wire [1:0]S_AXI_HP1_ARBURST;
+  wire [3:0]S_AXI_HP1_ARCACHE;
+  wire S_AXI_HP1_ARESETN;
+  wire [5:0]S_AXI_HP1_ARID;
+  wire [3:0]S_AXI_HP1_ARLEN;
+  wire [1:0]S_AXI_HP1_ARLOCK;
+  wire [2:0]S_AXI_HP1_ARPROT;
+  wire [3:0]S_AXI_HP1_ARQOS;
+  wire S_AXI_HP1_ARREADY;
+  wire [2:0]S_AXI_HP1_ARSIZE;
+  wire S_AXI_HP1_ARVALID;
+  wire [31:0]S_AXI_HP1_AWADDR;
+  wire [1:0]S_AXI_HP1_AWBURST;
+  wire [3:0]S_AXI_HP1_AWCACHE;
+  wire [5:0]S_AXI_HP1_AWID;
+  wire [3:0]S_AXI_HP1_AWLEN;
+  wire [1:0]S_AXI_HP1_AWLOCK;
+  wire [2:0]S_AXI_HP1_AWPROT;
+  wire [3:0]S_AXI_HP1_AWQOS;
+  wire S_AXI_HP1_AWREADY;
+  wire [2:0]S_AXI_HP1_AWSIZE;
+  wire S_AXI_HP1_AWVALID;
+  wire [5:0]S_AXI_HP1_BID;
+  wire S_AXI_HP1_BREADY;
+  wire [1:0]S_AXI_HP1_BRESP;
+  wire S_AXI_HP1_BVALID;
+  wire [2:0]S_AXI_HP1_RACOUNT;
+  wire [7:0]S_AXI_HP1_RCOUNT;
+  wire [63:0]S_AXI_HP1_RDATA;
+  wire S_AXI_HP1_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP1_RID;
+  wire S_AXI_HP1_RLAST;
+  wire S_AXI_HP1_RREADY;
+  wire [1:0]S_AXI_HP1_RRESP;
+  wire S_AXI_HP1_RVALID;
+  wire [5:0]S_AXI_HP1_WACOUNT;
+  wire [7:0]S_AXI_HP1_WCOUNT;
+  wire [63:0]S_AXI_HP1_WDATA;
+  wire [5:0]S_AXI_HP1_WID;
+  wire S_AXI_HP1_WLAST;
+  wire S_AXI_HP1_WREADY;
+  wire S_AXI_HP1_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP1_WSTRB;
+  wire S_AXI_HP1_WVALID;
+  wire S_AXI_HP2_ACLK;
+  wire [31:0]S_AXI_HP2_ARADDR;
+  wire [1:0]S_AXI_HP2_ARBURST;
+  wire [3:0]S_AXI_HP2_ARCACHE;
+  wire S_AXI_HP2_ARESETN;
+  wire [5:0]S_AXI_HP2_ARID;
+  wire [3:0]S_AXI_HP2_ARLEN;
+  wire [1:0]S_AXI_HP2_ARLOCK;
+  wire [2:0]S_AXI_HP2_ARPROT;
+  wire [3:0]S_AXI_HP2_ARQOS;
+  wire S_AXI_HP2_ARREADY;
+  wire [2:0]S_AXI_HP2_ARSIZE;
+  wire S_AXI_HP2_ARVALID;
+  wire [31:0]S_AXI_HP2_AWADDR;
+  wire [1:0]S_AXI_HP2_AWBURST;
+  wire [3:0]S_AXI_HP2_AWCACHE;
+  wire [5:0]S_AXI_HP2_AWID;
+  wire [3:0]S_AXI_HP2_AWLEN;
+  wire [1:0]S_AXI_HP2_AWLOCK;
+  wire [2:0]S_AXI_HP2_AWPROT;
+  wire [3:0]S_AXI_HP2_AWQOS;
+  wire S_AXI_HP2_AWREADY;
+  wire [2:0]S_AXI_HP2_AWSIZE;
+  wire S_AXI_HP2_AWVALID;
+  wire [5:0]S_AXI_HP2_BID;
+  wire S_AXI_HP2_BREADY;
+  wire [1:0]S_AXI_HP2_BRESP;
+  wire S_AXI_HP2_BVALID;
+  wire [2:0]S_AXI_HP2_RACOUNT;
+  wire [7:0]S_AXI_HP2_RCOUNT;
+  wire [63:0]S_AXI_HP2_RDATA;
+  wire S_AXI_HP2_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP2_RID;
+  wire S_AXI_HP2_RLAST;
+  wire S_AXI_HP2_RREADY;
+  wire [1:0]S_AXI_HP2_RRESP;
+  wire S_AXI_HP2_RVALID;
+  wire [5:0]S_AXI_HP2_WACOUNT;
+  wire [7:0]S_AXI_HP2_WCOUNT;
+  wire [63:0]S_AXI_HP2_WDATA;
+  wire [5:0]S_AXI_HP2_WID;
+  wire S_AXI_HP2_WLAST;
+  wire S_AXI_HP2_WREADY;
+  wire S_AXI_HP2_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP2_WSTRB;
+  wire S_AXI_HP2_WVALID;
+  wire S_AXI_HP3_ACLK;
+  wire [31:0]S_AXI_HP3_ARADDR;
+  wire [1:0]S_AXI_HP3_ARBURST;
+  wire [3:0]S_AXI_HP3_ARCACHE;
+  wire S_AXI_HP3_ARESETN;
+  wire [5:0]S_AXI_HP3_ARID;
+  wire [3:0]S_AXI_HP3_ARLEN;
+  wire [1:0]S_AXI_HP3_ARLOCK;
+  wire [2:0]S_AXI_HP3_ARPROT;
+  wire [3:0]S_AXI_HP3_ARQOS;
+  wire S_AXI_HP3_ARREADY;
+  wire [2:0]S_AXI_HP3_ARSIZE;
+  wire S_AXI_HP3_ARVALID;
+  wire [31:0]S_AXI_HP3_AWADDR;
+  wire [1:0]S_AXI_HP3_AWBURST;
+  wire [3:0]S_AXI_HP3_AWCACHE;
+  wire [5:0]S_AXI_HP3_AWID;
+  wire [3:0]S_AXI_HP3_AWLEN;
+  wire [1:0]S_AXI_HP3_AWLOCK;
+  wire [2:0]S_AXI_HP3_AWPROT;
+  wire [3:0]S_AXI_HP3_AWQOS;
+  wire S_AXI_HP3_AWREADY;
+  wire [2:0]S_AXI_HP3_AWSIZE;
+  wire S_AXI_HP3_AWVALID;
+  wire [5:0]S_AXI_HP3_BID;
+  wire S_AXI_HP3_BREADY;
+  wire [1:0]S_AXI_HP3_BRESP;
+  wire S_AXI_HP3_BVALID;
+  wire [2:0]S_AXI_HP3_RACOUNT;
+  wire [7:0]S_AXI_HP3_RCOUNT;
+  wire [63:0]S_AXI_HP3_RDATA;
+  wire S_AXI_HP3_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP3_RID;
+  wire S_AXI_HP3_RLAST;
+  wire S_AXI_HP3_RREADY;
+  wire [1:0]S_AXI_HP3_RRESP;
+  wire S_AXI_HP3_RVALID;
+  wire [5:0]S_AXI_HP3_WACOUNT;
+  wire [7:0]S_AXI_HP3_WCOUNT;
+  wire [63:0]S_AXI_HP3_WDATA;
+  wire [5:0]S_AXI_HP3_WID;
+  wire S_AXI_HP3_WLAST;
+  wire S_AXI_HP3_WREADY;
+  wire S_AXI_HP3_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP3_WSTRB;
+  wire S_AXI_HP3_WVALID;
+  wire TRACE_CLK;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[7] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[7] ;
+  wire TTC0_CLK0_IN;
+  wire TTC0_CLK1_IN;
+  wire TTC0_CLK2_IN;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire TTC1_CLK0_IN;
+  wire TTC1_CLK1_IN;
+  wire TTC1_CLK2_IN;
+  wire TTC1_WAVE0_OUT;
+  wire TTC1_WAVE1_OUT;
+  wire TTC1_WAVE2_OUT;
+  wire UART0_CTSN;
+  wire UART0_DCDN;
+  wire UART0_DSRN;
+  wire UART0_DTRN;
+  wire UART0_RIN;
+  wire UART0_RTSN;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire UART1_CTSN;
+  wire UART1_DCDN;
+  wire UART1_DSRN;
+  wire UART1_DTRN;
+  wire UART1_RIN;
+  wire UART1_RTSN;
+  wire UART1_RX;
+  wire UART1_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire [1:0]USB1_PORT_INDCTL;
+  wire USB1_VBUS_PWRFAULT;
+  wire USB1_VBUS_PWRSELECT;
+  wire WDT_CLK_IN;
+  wire WDT_RST_OUT;
+  wire [14:0]buffered_DDR_Addr;
+  wire [2:0]buffered_DDR_BankAddr;
+  wire buffered_DDR_CAS_n;
+  wire buffered_DDR_CKE;
+  wire buffered_DDR_CS_n;
+  wire buffered_DDR_Clk;
+  wire buffered_DDR_Clk_n;
+  wire [3:0]buffered_DDR_DM;
+  wire [31:0]buffered_DDR_DQ;
+  wire [3:0]buffered_DDR_DQS;
+  wire [3:0]buffered_DDR_DQS_n;
+  wire buffered_DDR_DRSTB;
+  wire buffered_DDR_ODT;
+  wire buffered_DDR_RAS_n;
+  wire buffered_DDR_VRN;
+  wire buffered_DDR_VRP;
+  wire buffered_DDR_WEB;
+  wire [53:0]buffered_MIO;
+  wire buffered_PS_CLK;
+  wire buffered_PS_PORB;
+  wire buffered_PS_SRSTB;
+  wire [63:0]gpio_out_t_n;
+  wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+  wire NLW_PS7_i_EMIO'b'TRACECTL_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
+  wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+
+  assign ENET0_GMII_TXD[7] = \\<const0> ;
+  assign ENET0_GMII_TXD[6] = \\<const0> ;
+  assign ENET0_GMII_TXD[5] = \\<const0> ;
+  assign ENET0_GMII_TXD[4] = \\<const0> ;
+  assign ENET0_GMII_TXD[3] = \\<const0> ;
+  assign ENET0_GMII_TXD[2] = \\<const0> ;
+  assign ENET0_GMII_TXD[1] = \\<const0> ;
+  assign ENET0_GMII_TXD[0] = \\<const0> ;
+  assign ENET0_GMII_TX_EN = \\<const0> ;
+  assign ENET0_GMII_TX_ER = \\<const0> ;
+  assign ENET1_GMII_TXD[7] = \\<const0> ;
+  assign ENET1_GMII_TXD[6] = \\<const0> ;
+  assign ENET1_GMII_TXD[5] = \\<const0> ;
+  assign ENET1_GMII_TXD[4] = \\<const0> ;
+  assign ENET1_GMII_TXD[3] = \\<const0> ;
+  assign ENET1_GMII_TXD[2] = \\<const0> ;
+  assign ENET1_GMII_TXD[1] = \\<const0> ;
+  assign ENET1_GMII_TXD[0] = \\<const0> ;
+  assign ENET1_GMII_TX_EN = \\<const0> ;
+  assign ENET1_GMII_TX_ER = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[1:0] = \\^M_AXI_GP0_ARSIZE [1:0];
+  assign M_AXI_GP0_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_AWSIZE[1:0] = \\^M_AXI_GP0_AWSIZE [1:0];
+  assign M_AXI_GP1_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_ARSIZE[1:0] = \\^M_AXI_GP1_ARSIZE [1:0];
+  assign M_AXI_GP1_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_AWSIZE[1:0] = \\^M_AXI_GP1_AWSIZE [1:0];
+  assign PJTAG_TDO = \\<const0> ;
+  assign TRACE_CLK_OUT = \\<const0> ;
+  assign TRACE_CTL = \\TRACE_CTL_PIPE[0] ;
+  assign TRACE_DATA[1:0] = \\TRACE_DATA_PIPE[0] ;
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CAS_n_BIBUF
+       (.IO(buffered_DDR_CAS_n),
+        .PAD(DDR_CAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CKE_BIBUF
+       (.IO(buffered_DDR_CKE),
+        .PAD(DDR_CKE));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CS_n_BIBUF
+       (.IO(buffered_DDR_CS_n),
+        .PAD(DDR_CS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_BIBUF
+       (.IO(buffered_DDR_Clk),
+        .PAD(DDR_Clk));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_n_BIBUF
+       (.IO(buffered_DDR_Clk_n),
+        .PAD(DDR_Clk_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_DRSTB_BIBUF
+       (.IO(buffered_DDR_DRSTB),
+        .PAD(DDR_DRSTB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_ODT_BIBUF
+       (.IO(buffered_DDR_ODT),
+        .PAD(DDR_ODT));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_RAS_n_BIBUF
+       (.IO(buffered_DDR_RAS_n),
+        .PAD(DDR_RAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRN_BIBUF
+       (.IO(buffered_DDR_VRN),
+        .PAD(DDR_VRN));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRP_BIBUF
+       (.IO(buffered_DDR_VRP),
+        .PAD(DDR_VRP));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_WEB_BIBUF
+       (.IO(buffered_DDR_WEB),
+        .PAD(DDR_WEB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET0_MDIO_T_INST_0
+       (.I0(ENET0_MDIO_T_n),
+        .O(ENET0_MDIO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET1_MDIO_T_INST_0
+       (.I0(ENET1_MDIO_T_n),
+        .O(ENET1_MDIO_T));
+  GND GND
+       (.G(\\<const0> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[0]_INST_0 
+       (.I0(gpio_out_t_n[0]),
+        .O(GPIO_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[10]_INST_0 
+       (.I0(gpio_out_t_n[10]),
+        .O(GPIO_T[10]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[11]_INST_0 
+       (.I0(gpio_out_t_n[11]),
+        .O(GPIO_T[11]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[12]_INST_0 
+       (.I0(gpio_out_t_n[12]),
+        .O(GPIO_T[12]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[13]_INST_0 
+       (.I0(gpio_out_t_n[13]),
+        .O(GPIO_T[13]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[14]_INST_0 
+       (.I0(gpio_out_t_n[14]),
+        .O(GPIO_T[14]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[15]_INST_0 
+       (.I0(gpio_out_t_n[15]),
+        .O(GPIO_T[15]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[16]_INST_0 
+       (.I0(gpio_out_t_n[16]),
+        .O(GPIO_T[16]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[17]_INST_0 
+       (.I0(gpio_out_t_n[17]),
+        .O(GPIO_T[17]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[18]_INST_0 
+       (.I0(gpio_out_t_n[18]),
+        .O(GPIO_T[18]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[19]_INST_0 
+       (.I0(gpio_out_t_n[19]),
+        .O(GPIO_T[19]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[1]_INST_0 
+       (.I0(gpio_out_t_n[1]),
+        .O(GPIO_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[20]_INST_0 
+       (.I0(gpio_out_t_n[20]),
+        .O(GPIO_T[20]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[21]_INST_0 
+       (.I0(gpio_out_t_n[21]),
+        .O(GPIO_T[21]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[22]_INST_0 
+       (.I0(gpio_out_t_n[22]),
+        .O(GPIO_T[22]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[23]_INST_0 
+       (.I0(gpio_out_t_n[23]),
+        .O(GPIO_T[23]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[24]_INST_0 
+       (.I0(gpio_out_t_n[24]),
+        .O(GPIO_T[24]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[25]_INST_0 
+       (.I0(gpio_out_t_n[25]),
+        .O(GPIO_T[25]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[26]_INST_0 
+       (.I0(gpio_out_t_n[26]),
+        .O(GPIO_T[26]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[27]_INST_0 
+       (.I0(gpio_out_t_n[27]),
+        .O(GPIO_T[27]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[28]_INST_0 
+       (.I0(gpio_out_t_n[28]),
+        .O(GPIO_T[28]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[29]_INST_0 
+       (.I0(gpio_out_t_n[29]),
+        .O(GPIO_T[29]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[2]_INST_0 
+       (.I0(gpio_out_t_n[2]),
+        .O(GPIO_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[30]_INST_0 
+       (.I0(gpio_out_t_n[30]),
+        .O(GPIO_T[30]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[31]_INST_0 
+       (.I0(gpio_out_t_n[31]),
+        .O(GPIO_T[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[32]_INST_0 
+       (.I0(gpio_out_t_n[32]),
+        .O(GPIO_T[32]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[33]_INST_0 
+       (.I0(gpio_out_t_n[33]),
+        .O(GPIO_T[33]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[34]_INST_0 
+       (.I0(gpio_out_t_n[34]),
+        .O(GPIO_T[34]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[35]_INST_0 
+       (.I0(gpio_out_t_n[35]),
+        .O(GPIO_T[35]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[36]_INST_0 
+       (.I0(gpio_out_t_n[36]),
+        .O(GPIO_T[36]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[37]_INST_0 
+       (.I0(gpio_out_t_n[37]),
+        .O(GPIO_T[37]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[38]_INST_0 
+       (.I0(gpio_out_t_n[38]),
+        .O(GPIO_T[38]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[39]_INST_0 
+       (.I0(gpio_out_t_n[39]),
+        .O(GPIO_T[39]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[3]_INST_0 
+       (.I0(gpio_out_t_n[3]),
+        .O(GPIO_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[40]_INST_0 
+       (.I0(gpio_out_t_n[40]),
+        .O(GPIO_T[40]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[41]_INST_0 
+       (.I0(gpio_out_t_n[41]),
+        .O(GPIO_T[41]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[42]_INST_0 
+       (.I0(gpio_out_t_n[42]),
+        .O(GPIO_T[42]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[43]_INST_0 
+       (.I0(gpio_out_t_n[43]),
+        .O(GPIO_T[43]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[44]_INST_0 
+       (.I0(gpio_out_t_n[44]),
+        .O(GPIO_T[44]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[45]_INST_0 
+       (.I0(gpio_out_t_n[45]),
+        .O(GPIO_T[45]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[46]_INST_0 
+       (.I0(gpio_out_t_n[46]),
+        .O(GPIO_T[46]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[47]_INST_0 
+       (.I0(gpio_out_t_n[47]),
+        .O(GPIO_T[47]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[48]_INST_0 
+       (.I0(gpio_out_t_n[48]),
+        .O(GPIO_T[48]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[49]_INST_0 
+       (.I0(gpio_out_t_n[49]),
+        .O(GPIO_T[49]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[4]_INST_0 
+       (.I0(gpio_out_t_n[4]),
+        .O(GPIO_T[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[50]_INST_0 
+       (.I0(gpio_out_t_n[50]),
+        .O(GPIO_T[50]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[51]_INST_0 
+       (.I0(gpio_out_t_n[51]),
+        .O(GPIO_T[51]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[52]_INST_0 
+       (.I0(gpio_out_t_n[52]),
+        .O(GPIO_T[52]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[53]_INST_0 
+       (.I0(gpio_out_t_n[53]),
+        .O(GPIO_T[53]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[54]_INST_0 
+       (.I0(gpio_out_t_n[54]),
+        .O(GPIO_T[54]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[55]_INST_0 
+       (.I0(gpio_out_t_n[55]),
+        .O(GPIO_T[55]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[56]_INST_0 
+       (.I0(gpio_out_t_n[56]),
+        .O(GPIO_T[56]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[57]_INST_0 
+       (.I0(gpio_out_t_n[57]),
+        .O(GPIO_T[57]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[58]_INST_0 
+       (.I0(gpio_out_t_n[58]),
+        .O(GPIO_T[58]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[59]_INST_0 
+       (.I0(gpio_out_t_n[59]),
+        .O(GPIO_T[59]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[5]_INST_0 
+       (.I0(gpio_out_t_n[5]),
+        .O(GPIO_T[5]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[60]_INST_0 
+       (.I0(gpio_out_t_n[60]),
+        .O(GPIO_T[60]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[61]_INST_0 
+       (.I0(gpio_out_t_n[61]),
+        .O(GPIO_T[61]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[62]_INST_0 
+       (.I0(gpio_out_t_n[62]),
+        .O(GPIO_T[62]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[63]_INST_0 
+       (.I0(gpio_out_t_n[63]),
+        .O(GPIO_T[63]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[6]_INST_0 
+       (.I0(gpio_out_t_n[6]),
+        .O(GPIO_T[6]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[7]_INST_0 
+       (.I0(gpio_out_t_n[7]),
+        .O(GPIO_T[7]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[8]_INST_0 
+       (.I0(gpio_out_t_n[8]),
+        .O(GPIO_T[8]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[9]_INST_0 
+       (.I0(gpio_out_t_n[9]),
+        .O(GPIO_T[9]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SCL_T_INST_0
+       (.I0(I2C0_SCL_T_n),
+        .O(I2C0_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SDA_T_INST_0
+       (.I0(I2C0_SDA_T_n),
+        .O(I2C0_SDA_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SCL_T_INST_0
+       (.I0(I2C1_SCL_T_n),
+        .O(I2C1_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SDA_T_INST_0
+       (.I0(I2C1_SDA_T_n),
+        .O(I2C1_SDA_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  PS7 PS7_i
+       (.DDRA(buffered_DDR_Addr),
+        .DDRARB(DDR_ARB),
+        .DDRBA(buffered_DDR_BankAddr),
+        .DDRCASB(buffered_DDR_CAS_n),
+        .DDRCKE(buffered_DDR_CKE),
+        .DDRCKN(buffered_DDR_Clk_n),
+        .DDRCKP(buffered_DDR_Clk),
+        .DDRCSB(buffered_DDR_CS_n),
+        .DDRDM(buffered_DDR_DM),
+        .DDRDQ(buffered_DDR_DQ),
+        .DDRDQSN(buffered_DDR_DQS_n),
+        .DDRDQSP(buffered_DDR_DQS),
+        .DDRDRSTB(buffered_DDR_DRSTB),
+        .DDRODT(buffered_DDR_ODT),
+        .DDRRASB(buffered_DDR_RAS_n),
+        .DDRVRN(buffered_DDR_VRN),
+        .DDRVRP(buffered_DDR_VRP),
+        .DDRWEB(buffered_DDR_WEB),
+        .DMA0ACLK(DMA0_ACLK),
+        .DMA0DAREADY(DMA0_DAREADY),
+        .DMA0DATYPE(DMA0_DATYPE),
+        .DMA0DAVALID(DMA0_DAVALID),
+        .DMA0DRLAST(DMA0_DRLAST),
+        .DMA0DRREADY(DMA0_DRREADY),
+        .DMA0DRTYPE(DMA0_DRTYPE),
+        .DMA0DRVALID(DMA0_DRVALID),
+        .DMA0RSTN(DMA0_RSTN),
+        .DMA1ACLK(DMA1_ACLK),
+        .DMA1DAREADY(DMA1_DAREADY),
+        .DMA1DATYPE(DMA1_DATYPE),
+        .DMA1DAVALID(DMA1_DAVALID),
+        .DMA1DRLAST(DMA1_DRLAST),
+        .DMA1DRREADY(DMA1_DRREADY),
+        .DMA1DRTYPE(DMA1_DRTYPE),
+        .DMA1DRVALID(DMA1_DRVALID),
+        .DMA1RSTN(DMA1_RSTN),
+        .DMA2ACLK(DMA2_ACLK),
+        .DMA2DAREADY(DMA2_DAREADY),
+        .DMA2DATYPE(DMA2_DATYPE),
+        .DMA2DAVALID(DMA2_DAVALID),
+        .DMA2DRLAST(DMA2_DRLAST),
+        .DMA2DRREADY(DMA2_DRREADY),
+        .DMA2DRTYPE(DMA2_DRTYPE),
+        .DMA2DRVALID(DMA2_DRVALID),
+        .DMA2RSTN(DMA2_RSTN),
+        .DMA3ACLK(DMA3_ACLK),
+        .DMA3DAREADY(DMA3_DAREADY),
+        .DMA3DATYPE(DMA3_DATYPE),
+        .DMA3DAVALID(DMA3_DAVALID),
+        .DMA3DRLAST(DMA3_DRLAST),
+        .DMA3DRREADY(DMA3_DRREADY),
+        .DMA3DRTYPE(DMA3_DRTYPE),
+        .DMA3DRVALID(DMA3_DRVALID),
+        .DMA3RSTN(DMA3_RSTN),
+        .EMIOCAN0PHYRX(CAN0_PHY_RX),
+        .EMIOCAN0PHYTX(CAN0_PHY_TX),
+        .EMIOCAN1PHYRX(CAN1_PHY_RX),
+        .EMIOCAN1PHYTX(CAN1_PHY_TX),
+        .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+        .EMIOENET0GMIICOL(1\'b0),
+        .EMIOENET0GMIICRS(1\'b0),
+        .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+        .EMIOENET0GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET0GMIIRXDV(1\'b0),
+        .EMIOENET0GMIIRXER(1\'b0),
+        .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+        .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+        .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+        .EMIOENET0MDIOI(ENET0_MDIO_I),
+        .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+        .EMIOENET0MDIOO(ENET0_MDIO_O),
+        .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+        .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+        .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+        .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+        .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+        .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+        .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+        .EMIOENET0SOFRX(ENET0_SOF_RX),
+        .EMIOENET0SOFTX(ENET0_SOF_TX),
+        .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+        .EMIOENET1GMIICOL(1\'b0),
+        .EMIOENET1GMIICRS(1\'b0),
+        .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+        .EMIOENET1GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET1GMIIRXDV(1\'b0),
+        .EMIOENET1GMIIRXER(1\'b0),
+        .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+        .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+        .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+        .EMIOENET1MDIOI(ENET1_MDIO_I),
+        .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+        .EMIOENET1MDIOO(ENET1_MDIO_O),
+        .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+        .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+        .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+        .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+        .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+        .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+        .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+        .EMIOENET1SOFRX(ENET1_SOF_RX),
+        .EMIOENET1SOFTX(ENET1_SOF_TX),
+        .EMIOGPIOI(GPIO_I),
+        .EMIOGPIOO(GPIO_O),
+        .EMIOGPIOTN(gpio_out_t_n),
+        .EMIOI2C0SCLI(I2C0_SCL_I),
+        .EMIOI2C0SCLO(I2C0_SCL_O),
+        .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+        .EMIOI2C0SDAI(I2C0_SDA_I),
+        .EMIOI2C0SDAO(I2C0_SDA_O),
+        .EMIOI2C0SDATN(I2C0_SDA_T_n),
+        .EMIOI2C1SCLI(I2C1_SCL_I),
+        .EMIOI2C1SCLO(I2C1_SCL_O),
+        .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+        .EMIOI2C1SDAI(I2C1_SDA_I),
+        .EMIOI2C1SDAO(I2C1_SDA_O),
+        .EMIOI2C1SDATN(I2C1_SDA_T_n),
+        .EMIOPJTAGTCK(PJTAG_TCK),
+        .EMIOPJTAGTDI(PJTAG_TDI),
+        .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+        .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+        .EMIOPJTAGTMS(PJTAG_TMS),
+        .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+        .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+        .EMIOSDIO0CDN(SDIO0_CDN),
+        .EMIOSDIO0CLK(SDIO0_CLK),
+        .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+        .EMIOSDIO0CMDI(SDIO0_CMD_I),
+        .EMIOSDIO0CMDO(SDIO0_CMD_O),
+        .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+        .EMIOSDIO0DATAI(SDIO0_DATA_I),
+        .EMIOSDIO0DATAO(SDIO0_DATA_O),
+        .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+        .EMIOSDIO0LED(SDIO0_LED),
+        .EMIOSDIO0WP(SDIO0_WP),
+        .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+        .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+        .EMIOSDIO1CDN(SDIO1_CDN),
+        .EMIOSDIO1CLK(SDIO1_CLK),
+        .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+        .EMIOSDIO1CMDI(SDIO1_CMD_I),
+        .EMIOSDIO1CMDO(SDIO1_CMD_O),
+        .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+        .EMIOSDIO1DATAI(SDIO1_DATA_I),
+        .EMIOSDIO1DATAO(SDIO1_DATA_O),
+        .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+        .EMIOSDIO1LED(SDIO1_LED),
+        .EMIOSDIO1WP(SDIO1_WP),
+        .EMIOSPI0MI(SPI0_MISO_I),
+        .EMIOSPI0MO(SPI0_MOSI_O),
+        .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+        .EMIOSPI0SCLKI(SPI0_SCLK_I),
+        .EMIOSPI0SCLKO(SPI0_SCLK_O),
+        .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+        .EMIOSPI0SI(SPI0_MOSI_I),
+        .EMIOSPI0SO(SPI0_MISO_O),
+        .EMIOSPI0SSIN(SPI0_SS_I),
+        .EMIOSPI0SSNTN(SPI0_SS_T_n),
+        .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+        .EMIOSPI0STN(SPI0_MISO_T_n),
+        .EMIOSPI1MI(SPI1_MISO_I),
+        .EMIOSPI1MO(SPI1_MOSI_O),
+        .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+        .EMIOSPI1SCLKI(SPI1_SCLK_I),
+        .EMIOSPI1SCLKO(SPI1_SCLK_O),
+        .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+        .EMIOSPI1SI(SPI1_MOSI_I),
+        .EMIOSPI1SO(SPI1_MISO_O),
+        .EMIOSPI1SSIN(SPI1_SS_I),
+        .EMIOSPI1SSNTN(SPI1_SS_T_n),
+        .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+        .EMIOSPI1STN(SPI1_MISO_T_n),
+        .EMIOSRAMINTIN(SRAM_INTIN),
+        .EMIOTRACECLK(TRACE_CLK),
+        .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+        .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+        .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+        .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+        .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+        .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+        .EMIOUART0CTSN(UART0_CTSN),
+        .EMIOUART0DCDN(UART0_DCDN),
+        .EMIOUART0DSRN(UART0_DSRN),
+        .EMIOUART0DTRN(UART0_DTRN),
+        .EMIOUART0RIN(UART0_RIN),
+        .EMIOUART0RTSN(UART0_RTSN),
+        .EMIOUART0RX(UART0_RX),
+        .EMIOUART0TX(UART0_TX),
+        .EMIOUART1CTSN(UART1_CTSN),
+        .EMIOUART1DCDN(UART1_DCDN),
+        .EMIOUART1DSRN(UART1_DSRN),
+        .EMIOUART1DTRN(UART1_DTRN),
+        .EMIOUART1RIN(UART1_RIN),
+        .EMIOUART1RTSN(UART1_RTSN),
+        .EMIOUART1RX(UART1_RX),
+        .EMIOUART1TX(UART1_TX),
+        .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+        .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+        .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+        .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+        .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+        .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+        .EMIOWDTCLKI(WDT_CLK_IN),
+        .EMIOWDTRSTO(WDT_RST_OUT),
+        .EVENTEVENTI(EVENT_EVENTI),
+        .EVENTEVENTO(EVENT_EVENTO),
+        .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+        .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+        .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+        .FCLKCLKTRIGN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+        .FPGAIDLEN(FPGA_IDLE_N),
+        .FTMDTRACEINATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+        .FTMDTRACEINDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINVALID(1\'b0),
+        .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+        .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+        .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+        .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+        .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+        .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+        .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,IRQ_F2P}),
+        .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+        .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+        .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+        .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+        .MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
+        .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+        .MAXIGP0ARID(M_AXI_GP0_ARID),
+        .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+        .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+        .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+        .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+        .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+        .MAXIGP0ARSIZE(\\^M_AXI_GP0_ARSIZE ),
+        .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+        .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+        .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+        .MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
+        .MAXIGP0AWID(M_AXI_GP0_AWID),
+        .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+        .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+        .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+        .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+        .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+        .MAXIGP0AWSIZE(\\^M_AXI_GP0_AWSIZE ),
+        .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+        .MAXIGP0BID(M_AXI_GP0_BID),
+        .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+        .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+        .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+        .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+        .MAXIGP0RID(M_AXI_GP0_RID),
+        .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+        .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+        .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+        .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+        .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+        .MAXIGP0WID(M_AXI_GP0_WID),
+        .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+        .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+        .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+        .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+        .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+        .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+        .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+        .MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
+        .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+        .MAXIGP1ARID(M_AXI_GP1_ARID),
+        .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+        .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+        .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+        .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+        .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+        .MAXIGP1ARSIZE(\\^M_AXI_GP1_ARSIZE ),
+        .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+        .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+        .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+        .MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
+        .MAXIGP1AWID(M_AXI_GP1_AWID),
+        .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+        .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+        .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+        .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+        .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+        .MAXIGP1AWSIZE(\\^M_AXI_GP1_AWSIZE ),
+        .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+        .MAXIGP1BID(M_AXI_GP1_BID),
+        .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+        .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+        .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+        .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+        .MAXIGP1RID(M_AXI_GP1_RID),
+        .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+        .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+        .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+        .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+        .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+        .MAXIGP1WID(M_AXI_GP1_WID),
+        .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+        .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+        .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+        .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+        .MIO(buffered_MIO),
+        .PSCLK(buffered_PS_CLK),
+        .PSPORB(buffered_PS_PORB),
+        .PSSRSTB(buffered_PS_SRSTB),
+        .SAXIACPACLK(S_AXI_ACP_ACLK),
+        .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+        .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+        .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+        .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+        .SAXIACPARID(S_AXI_ACP_ARID),
+        .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+        .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+        .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+        .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+        .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+        .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+        .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+        .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+        .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+        .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+        .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+        .SAXIACPAWID(S_AXI_ACP_AWID),
+        .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+        .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+        .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+        .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+        .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+        .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+        .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+        .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+        .SAXIACPBID(S_AXI_ACP_BID),
+        .SAXIACPBREADY(S_AXI_ACP_BREADY),
+        .SAXIACPBRESP(S_AXI_ACP_BRESP),
+        .SAXIACPBVALID(S_AXI_ACP_BVALID),
+        .SAXIACPRDATA(S_AXI_ACP_RDATA),
+        .SAXIACPRID(S_AXI_ACP_RID),
+        .SAXIACPRLAST(S_AXI_ACP_RLAST),
+        .SAXIACPRREADY(S_AXI_ACP_RREADY),
+        .SAXIACPRRESP(S_AXI_ACP_RRESP),
+        .SAXIACPRVALID(S_AXI_ACP_RVALID),
+        .SAXIACPWDATA(S_AXI_ACP_WDATA),
+        .SAXIACPWID(S_AXI_ACP_WID),
+        .SAXIACPWLAST(S_AXI_ACP_WLAST),
+        .SAXIACPWREADY(S_AXI_ACP_WREADY),
+        .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+        .SAXIACPWVALID(S_AXI_ACP_WVALID),
+        .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+        .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+        .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+        .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+        .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+        .SAXIGP0ARID(S_AXI_GP0_ARID),
+        .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+        .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+        .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+        .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+        .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+        .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+        .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+        .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+        .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+        .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+        .SAXIGP0AWID(S_AXI_GP0_AWID),
+        .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+        .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+        .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+        .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+        .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+        .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+        .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+        .SAXIGP0BID(S_AXI_GP0_BID),
+        .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+        .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+        .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+        .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+        .SAXIGP0RID(S_AXI_GP0_RID),
+        .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+        .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+        .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+        .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+        .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+        .SAXIGP0WID(S_AXI_GP0_WID),
+        .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+        .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+        .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+        .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+        .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+        .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+        .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+        .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+        .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+        .SAXIGP1ARID(S_AXI_GP1_ARID),
+        .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+        .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+        .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+        .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+        .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+        .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+        .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+        .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+        .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+        .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+        .SAXIGP1AWID(S_AXI_GP1_AWID),
+        .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+        .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+        .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+        .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+        .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+        .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+        .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+        .SAXIGP1BID(S_AXI_GP1_BID),
+        .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+        .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+        .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+        .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+        .SAXIGP1RID(S_AXI_GP1_RID),
+        .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+        .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+        .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+        .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+        .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+        .SAXIGP1WID(S_AXI_GP1_WID),
+        .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+        .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+        .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+        .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+        .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+        .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+        .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+        .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+        .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+        .SAXIHP0ARID(S_AXI_HP0_ARID),
+        .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+        .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+        .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+        .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+        .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+        .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+        .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+        .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+        .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+        .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+        .SAXIHP0AWID(S_AXI_HP0_AWID),
+        .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+        .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+        .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+        .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+        .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+        .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+        .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+        .SAXIHP0BID(S_AXI_HP0_BID),
+        .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+        .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+        .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+        .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+        .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+        .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+        .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+        .SAXIHP0RID(S_AXI_HP0_RID),
+        .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+        .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+        .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+        .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+        .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+        .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+        .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+        .SAXIHP0WID(S_AXI_HP0_WID),
+        .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+        .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+        .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+        .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+        .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+        .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+        .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+        .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+        .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+        .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+        .SAXIHP1ARID(S_AXI_HP1_ARID),
+        .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+        .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+        .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+        .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+        .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+        .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+        .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+        .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+        .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+        .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+        .SAXIHP1AWID(S_AXI_HP1_AWID),
+        .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+        .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+        .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+        .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+        .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+        .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+        .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+        .SAXIHP1BID(S_AXI_HP1_BID),
+        .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+        .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+        .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+        .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+        .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+        .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+        .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+        .SAXIHP1RID(S_AXI_HP1_RID),
+        .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+        .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+        .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+        .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+        .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+        .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+        .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+        .SAXIHP1WID(S_AXI_HP1_WID),
+        .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+        .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+        .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+        .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+        .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+        .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+        .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+        .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+        .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+        .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+        .SAXIHP2ARID(S_AXI_HP2_ARID),
+        .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+        .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+        .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+        .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+        .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+        .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+        .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+        .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+        .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+        .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+        .SAXIHP2AWID(S_AXI_HP2_AWID),
+        .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+        .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+        .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+        .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+        .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+        .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+        .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+        .SAXIHP2BID(S_AXI_HP2_BID),
+        .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+        .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+        .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+        .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+        .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+        .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+        .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+        .SAXIHP2RID(S_AXI_HP2_RID),
+        .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+        .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+        .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+        .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+        .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+        .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+        .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+        .SAXIHP2WID(S_AXI_HP2_WID),
+        .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+        .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+        .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+        .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+        .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+        .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+        .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+        .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+        .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+        .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+        .SAXIHP3ARID(S_AXI_HP3_ARID),
+        .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+        .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+        .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+        .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+        .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+        .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+        .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+        .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+        .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+        .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+        .SAXIHP3AWID(S_AXI_HP3_AWID),
+        .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+        .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+        .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+        .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+        .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+        .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+        .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+        .SAXIHP3BID(S_AXI_HP3_BID),
+        .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+        .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+        .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+        .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+        .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+        .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+        .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+        .SAXIHP3RID(S_AXI_HP3_RID),
+        .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+        .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+        .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+        .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+        .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+        .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+        .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+        .SAXIHP3WID(S_AXI_HP3_WID),
+        .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+        .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+        .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+        .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+        .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_CLK_BIBUF
+       (.IO(buffered_PS_CLK),
+        .PAD(PS_CLK));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_PORB_BIBUF
+       (.IO(buffered_PS_PORB),
+        .PAD(PS_PORB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_SRSTB_BIBUF
+       (.IO(buffered_PS_SRSTB),
+        .PAD(PS_SRSTB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO0_CMD_T_INST_0
+       (.I0(SDIO0_CMD_T_n),
+        .O(SDIO0_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[0]_INST_0 
+       (.I0(SDIO0_DATA_T_n[0]),
+        .O(SDIO0_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[1]_INST_0 
+       (.I0(SDIO0_DATA_T_n[1]),
+        .O(SDIO0_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[2]_INST_0 
+       (.I0(SDIO0_DATA_T_n[2]),
+        .O(SDIO0_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[3]_INST_0 
+       (.I0(SDIO0_DATA_T_n[3]),
+        .O(SDIO0_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO1_CMD_T_INST_0
+       (.I0(SDIO1_CMD_T_n),
+        .O(SDIO1_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[0]_INST_0 
+       (.I0(SDIO1_DATA_T_n[0]),
+        .O(SDIO1_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[1]_INST_0 
+       (.I0(SDIO1_DATA_T_n[1]),
+        .O(SDIO1_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[2]_INST_0 
+       (.I0(SDIO1_DATA_T_n[2]),
+        .O(SDIO1_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[3]_INST_0 
+       (.I0(SDIO1_DATA_T_n[3]),
+        .O(SDIO1_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MISO_T_INST_0
+       (.I0(SPI0_MISO_T_n),
+        .O(SPI0_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MOSI_T_INST_0
+       (.I0(SPI0_MOSI_T_n),
+        .O(SPI0_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SCLK_T_INST_0
+       (.I0(SPI0_SCLK_T_n),
+        .O(SPI0_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SS_T_INST_0
+       (.I0(SPI0_SS_T_n),
+        .O(SPI0_SS_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MISO_T_INST_0
+       (.I0(SPI1_MISO_T_n),
+        .O(SPI1_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MOSI_T_INST_0
+       (.I0(SPI1_MOSI_T_n),
+        .O(SPI1_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SCLK_T_INST_0
+       (.I0(SPI1_SCLK_T_n),
+        .O(SPI1_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SS_T_INST_0
+       (.I0(SPI1_SS_T_n),
+        .O(SPI1_SS_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BUFG \\buffer_fclk_clk_0.FCLK_CLK_0_BUFG 
+       (.I(FCLK_CLK_unbuffered),
+        .O(FCLK_CLK0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[0].MIO_BIBUF 
+       (.IO(buffered_MIO[0]),
+        .PAD(MIO[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[10].MIO_BIBUF 
+       (.IO(buffered_MIO[10]),
+        .PAD(MIO[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[11].MIO_BIBUF 
+       (.IO(buffered_MIO[11]),
+        .PAD(MIO[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[12].MIO_BIBUF 
+       (.IO(buffered_MIO[12]),
+        .PAD(MIO[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[13].MIO_BIBUF 
+       (.IO(buffered_MIO[13]),
+        .PAD(MIO[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[14].MIO_BIBUF 
+       (.IO(buffered_MIO[14]),
+        .PAD(MIO[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[15].MIO_BIBUF 
+       (.IO(buffered_MIO[15]),
+        .PAD(MIO[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[16].MIO_BIBUF 
+       (.IO(buffered_MIO[16]),
+        .PAD(MIO[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[17].MIO_BIBUF 
+       (.IO(buffered_MIO[17]),
+        .PAD(MIO[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[18].MIO_BIBUF 
+       (.IO(buffered_MIO[18]),
+        .PAD(MIO[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[19].MIO_BIBUF 
+       (.IO(buffered_MIO[19]),
+        .PAD(MIO[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[1].MIO_BIBUF 
+       (.IO(buffered_MIO[1]),
+        .PAD(MIO[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[20].MIO_BIBUF 
+       (.IO(buffered_MIO[20]),
+        .PAD(MIO[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[21].MIO_BIBUF 
+       (.IO(buffered_MIO[21]),
+        .PAD(MIO[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[22].MIO_BIBUF 
+       (.IO(buffered_MIO[22]),
+        .PAD(MIO[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[23].MIO_BIBUF 
+       (.IO(buffered_MIO[23]),
+        .PAD(MIO[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[24].MIO_BIBUF 
+       (.IO(buffered_MIO[24]),
+        .PAD(MIO[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[25].MIO_BIBUF 
+       (.IO(buffered_MIO[25]),
+        .PAD(MIO[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[26].MIO_BIBUF 
+       (.IO(buffered_MIO[26]),
+        .PAD(MIO[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[27].MIO_BIBUF 
+       (.IO(buffered_MIO[27]),
+        .PAD(MIO[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[28].MIO_BIBUF 
+       (.IO(buffered_MIO[28]),
+        .PAD(MIO[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[29].MIO_BIBUF 
+       (.IO(buffered_MIO[29]),
+        .PAD(MIO[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[2].MIO_BIBUF 
+       (.IO(buffered_MIO[2]),
+        .PAD(MIO[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[30].MIO_BIBUF 
+       (.IO(buffered_MIO[30]),
+        .PAD(MIO[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[31].MIO_BIBUF 
+       (.IO(buffered_MIO[31]),
+        .PAD(MIO[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[32].MIO_BIBUF 
+       (.IO(buffered_MIO[32]),
+        .PAD(MIO[32]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[33].MIO_BIBUF 
+       (.IO(buffered_MIO[33]),
+        .PAD(MIO[33]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[34].MIO_BIBUF 
+       (.IO(buffered_MIO[34]),
+        .PAD(MIO[34]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[35].MIO_BIBUF 
+       (.IO(buffered_MIO[35]),
+        .PAD(MIO[35]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[36].MIO_BIBUF 
+       (.IO(buffered_MIO[36]),
+        .PAD(MIO[36]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[37].MIO_BIBUF 
+       (.IO(buffered_MIO[37]),
+        .PAD(MIO[37]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[38].MIO_BIBUF 
+       (.IO(buffered_MIO[38]),
+        .PAD(MIO[38]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[39].MIO_BIBUF 
+       (.IO(buffered_MIO[39]),
+        .PAD(MIO[39]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[3].MIO_BIBUF 
+       (.IO(buffered_MIO[3]),
+        .PAD(MIO[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[40].MIO_BIBUF 
+       (.IO(buffered_MIO[40]),
+        .PAD(MIO[40]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[41].MIO_BIBUF 
+       (.IO(buffered_MIO[41]),
+        .PAD(MIO[41]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[42].MIO_BIBUF 
+       (.IO(buffered_MIO[42]),
+        .PAD(MIO[42]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[43].MIO_BIBUF 
+       (.IO(buffered_MIO[43]),
+        .PAD(MIO[43]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[44].MIO_BIBUF 
+       (.IO(buffered_MIO[44]),
+        .PAD(MIO[44]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[45].MIO_BIBUF 
+       (.IO(buffered_MIO[45]),
+        .PAD(MIO[45]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[46].MIO_BIBUF 
+       (.IO(buffered_MIO[46]),
+        .PAD(MIO[46]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[47].MIO_BIBUF 
+       (.IO(buffered_MIO[47]),
+        .PAD(MIO[47]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[48].MIO_BIBUF 
+       (.IO(buffered_MIO[48]),
+        .PAD(MIO[48]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[49].MIO_BIBUF 
+       (.IO(buffered_MIO[49]),
+        .PAD(MIO[49]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[4].MIO_BIBUF 
+       (.IO(buffered_MIO[4]),
+        .PAD(MIO[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[50].MIO_BIBUF 
+       (.IO(buffered_MIO[50]),
+        .PAD(MIO[50]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[51].MIO_BIBUF 
+       (.IO(buffered_MIO[51]),
+        .PAD(MIO[51]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[52].MIO_BIBUF 
+       (.IO(buffered_MIO[52]),
+        .PAD(MIO[52]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[53].MIO_BIBUF 
+       (.IO(buffered_MIO[53]),
+        .PAD(MIO[53]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[5].MIO_BIBUF 
+       (.IO(buffered_MIO[5]),
+        .PAD(MIO[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[6].MIO_BIBUF 
+       (.IO(buffered_MIO[6]),
+        .PAD(MIO[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[7].MIO_BIBUF 
+       (.IO(buffered_MIO[7]),
+        .PAD(MIO[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[8].MIO_BIBUF 
+       (.IO(buffered_MIO[8]),
+        .PAD(MIO[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[9].MIO_BIBUF 
+       (.IO(buffered_MIO[9]),
+        .PAD(MIO[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[0].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[0]),
+        .PAD(DDR_BankAddr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[1].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[1]),
+        .PAD(DDR_BankAddr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[2].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[2]),
+        .PAD(DDR_BankAddr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[0].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[0]),
+        .PAD(DDR_Addr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[10].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[10]),
+        .PAD(DDR_Addr[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[11].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[11]),
+        .PAD(DDR_Addr[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[12].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[12]),
+        .PAD(DDR_Addr[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[13].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[13]),
+        .PAD(DDR_Addr[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[14].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[14]),
+        .PAD(DDR_Addr[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[1].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[1]),
+        .PAD(DDR_Addr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[2].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[2]),
+        .PAD(DDR_Addr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[3].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[3]),
+        .PAD(DDR_Addr[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[4].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[4]),
+        .PAD(DDR_Addr[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[5].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[5]),
+        .PAD(DDR_Addr[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[6].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[6]),
+        .PAD(DDR_Addr[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[7].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[7]),
+        .PAD(DDR_Addr[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[8].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[8]),
+        .PAD(DDR_Addr[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[9].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[9]),
+        .PAD(DDR_Addr[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[0].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[0]),
+        .PAD(DDR_DM[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[1].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[1]),
+        .PAD(DDR_DM[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[2].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[2]),
+        .PAD(DDR_DM[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[3].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[3]),
+        .PAD(DDR_DM[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[0].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[0]),
+        .PAD(DDR_DQ[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[10].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[10]),
+        .PAD(DDR_DQ[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[11].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[11]),
+        .PAD(DDR_DQ[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[12].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[12]),
+        .PAD(DDR_DQ[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[13].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[13]),
+        .PAD(DDR_DQ[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[14].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[14]),
+        .PAD(DDR_DQ[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[15].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[15]),
+        .PAD(DDR_DQ[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[16].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[16]),
+        .PAD(DDR_DQ[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[17].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[17]),
+        .PAD(DDR_DQ[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[18].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[18]),
+        .PAD(DDR_DQ[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[19].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[19]),
+        .PAD(DDR_DQ[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[1].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[1]),
+        .PAD(DDR_DQ[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[20].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[20]),
+        .PAD(DDR_DQ[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[21].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[21]),
+        .PAD(DDR_DQ[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[22].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[22]),
+        .PAD(DDR_DQ[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[23].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[23]),
+        .PAD(DDR_DQ[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[24].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[24]),
+        .PAD(DDR_DQ[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[25].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[25]),
+        .PAD(DDR_DQ[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[26].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[26]),
+        .PAD(DDR_DQ[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[27].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[27]),
+        .PAD(DDR_DQ[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[28].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[28]),
+        .PAD(DDR_DQ[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[29].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[29]),
+        .PAD(DDR_DQ[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[2].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[2]),
+        .PAD(DDR_DQ[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[30].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[30]),
+        .PAD(DDR_DQ[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[31].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[31]),
+        .PAD(DDR_DQ[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[3].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[3]),
+        .PAD(DDR_DQ[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[4].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[4]),
+        .PAD(DDR_DQ[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[5].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[5]),
+        .PAD(DDR_DQ[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[6].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[6]),
+        .PAD(DDR_DQ[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[7].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[7]),
+        .PAD(DDR_DQ[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[8].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[8]),
+        .PAD(DDR_DQ[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[9].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[9]),
+        .PAD(DDR_DQ[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[0].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[0]),
+        .PAD(DDR_DQS_n[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[1].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[1]),
+        .PAD(DDR_DQS_n[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[2].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[2]),
+        .PAD(DDR_DQS_n[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[3].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[3]),
+        .PAD(DDR_DQS_n[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[0].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[0]),
+        .PAD(DDR_DQS[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[1].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[1]),
+        .PAD(DDR_DQS[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[2].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[2]),
+        .PAD(DDR_DQS[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[3].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[3]),
+        .PAD(DDR_DQS[3]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_0
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[0] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_1
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_10
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_11
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_12
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_13
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_14
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_15
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_16
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_17
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_18
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_19
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_2
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_20
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_21
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_22
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_23
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_3
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[7] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_4
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[6] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_5
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[5] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_6
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[4] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_7
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[3] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_8
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[2] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_9
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Mon Feb 13 23:24:41 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT, 
+  TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, 
+  USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, 
+  M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, 
+  M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, 
+  DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, 
+  DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin=""GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"" */;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input SDIO0_WP;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  input [0:0]IRQ_F2P;
+  output FCLK_CLK0;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule
+"
+"// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized AND with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_carry_and #
+  (
+   parameter         C_FAMILY                         = ""virtex6""
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   )
+  (
+   input  wire        CIN,
+   input  wire        S,
+   output wire        COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Instantiate or use RTL code
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    if ( C_FAMILY == ""rtl"" ) begin : USE_RTL
+      assign COUT = CIN & S;
+      
+    end else begin : USE_FPGA
+      MUXCY and_inst 
+      (
+       .O (COUT), 
+       .CI (CIN), 
+       .DI (1\'b0), 
+       .S (S)
+      ); 
+      
+    end
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized AND with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_carry_latch_and #
+  (
+   parameter          C_FAMILY                         = ""virtex6""
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   )
+  (
+   input  wire        CIN,
+   input  wire        I,
+   output wire        O
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Instantiate or use RTL code
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    if ( C_FAMILY == ""rtl"" ) begin : USE_RTL
+      assign O = CIN & ~I;
+      
+    end else begin : USE_FPGA
+      wire I_n;
+      
+      assign I_n = ~I;
+    
+      AND2B1L and2b1l_inst 
+        (
+         .O(O),
+         .DI(CIN),
+         .SRI(I_n)
+        );
+      
+    end
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized OR with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_carry_latch_or #
+  (
+   parameter          C_FAMILY                         = ""virtex6""
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   )
+  (
+   input  wire        CIN,
+   input  wire        I,
+   output wire        O
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Instantiate or use RTL code
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    if ( C_FAMILY == ""rtl"" ) begin : USE_RTL
+      assign O = CIN | I;
+      
+    end else begin : USE_FPGA
+      OR2L or2l_inst1
+        (
+         .O(O),
+         .DI(CIN),
+         .SRI(I)
+        );
+      
+    end
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized OR with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_carry_or #
+  (
+   parameter         C_FAMILY                         = ""virtex6""
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   )
+  (
+   input  wire        CIN,
+   input  wire        S,
+   output wire        COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Instantiate or use RTL code
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    if ( C_FAMILY == ""rtl"" ) begin : USE_RTL
+      assign COUT = CIN | S;
+      
+    end else begin : USE_FPGA
+      wire S_n;
+      
+      assign S_n = ~S;
+    
+      MUXCY and_inst 
+      (
+       .O (COUT), 
+       .CI (CIN), 
+       .DI (1\'b1), 
+       .S (S_n)
+      ); 
+      
+    end
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_carry #
+  (
+   parameter         C_FAMILY                         = ""virtex6""
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   )
+  (
+   input  wire        CIN,
+   input  wire        S,
+   input  wire        DI,
+   output wire        COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Instantiate or use RTL code
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    if ( C_FAMILY == ""rtl"" ) begin : USE_RTL
+      assign COUT = (CIN & S) | (DI & ~S);
+      
+    end else begin : USE_FPGA
+    
+      MUXCY and_inst 
+      (
+       .O (COUT), 
+       .CI (CIN), 
+       .DI (DI), 
+       .S (S)
+      ); 
+      
+    end
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized 16/32 word deep FIFO.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_command_fifo #
+  (
+   parameter         C_FAMILY                        = ""virtex6"",
+   parameter integer C_ENABLE_S_VALID_CARRY          = 0,
+   parameter integer C_ENABLE_REGISTERED_OUTPUT      = 0,
+   parameter integer C_FIFO_DEPTH_LOG                = 5,      // FIFO depth = 2**C_FIFO_DEPTH_LOG
+                                                               // Range = [4:5].
+   parameter integer C_FIFO_WIDTH                    = 64      // Width of payload [1:512]
+   )
+  (
+   // Global inputs
+   input  wire                        ACLK,    // Clock
+   input  wire                        ARESET,  // Reset
+   // Information
+   output wire                        EMPTY,   // FIFO empty (all stages)
+   // Slave  Port
+   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Payload (may be any set of channel signals)
+   input  wire                        S_VALID, // FIFO push
+   output wire                        S_READY, // FIFO not full
+   // Master  Port
+   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Payload
+   output wire                        M_VALID, // FIFO not empty
+   input  wire                        M_READY  // FIFO pop
+   );
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for data vector.
+  genvar addr_cnt;
+  genvar bit_cnt;
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIFO_DEPTH_LOG-1:0] addr;
+  wire                        buffer_Full;
+  wire                        buffer_Empty;
+  
+  wire                        next_Data_Exists;
+  reg                         data_Exists_I;
+  
+  wire                        valid_Write;
+  wire                        new_write;
+  
+  wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
+  wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
+  wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
+
+  wire                        buffer_full_early;
+  
+  wire [C_FIFO_WIDTH-1:0]     M_MESG_I;   // Payload
+  wire                        M_VALID_I;  // FIFO not empty
+  wire                        M_READY_I;  // FIFO pop
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Create Flags 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  assign buffer_full_early  = ( (addr == {{C_FIFO_DEPTH_LOG-1{1\'b1}}, 1\'b0}) & valid_Write & ~M_READY_I ) |
+                              ( buffer_Full & ~M_READY_I );
+
+  assign S_READY            = ~buffer_Full;
+
+  assign buffer_Empty       = (addr == {C_FIFO_DEPTH_LOG{1\'b0}});
+
+  assign next_Data_Exists   = (data_Exists_I & ~buffer_Empty) |
+                              (buffer_Empty & S_VALID) |
+                              (data_Exists_I & ~(M_READY_I & data_Exists_I));
+
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      data_Exists_I <= 1\'b0;
+    end else begin
+      data_Exists_I <= next_Data_Exists;
+    end
+  end
+
+  assign M_VALID_I = data_Exists_I;
+  
+  // Select RTL or FPGA optimized instatiations for critical parts.
+  generate
+    if ( C_FAMILY == ""rtl"" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
+      reg                         buffer_Full_q;
+      
+      assign valid_Write = S_VALID & ~buffer_Full;
+      
+      assign new_write = (S_VALID | ~buffer_Empty);
+     
+      assign addr_cy[0] = valid_Write;
+      
+      always @ (posedge ACLK) begin
+        if (ARESET) begin
+          buffer_Full_q <= 1\'b0;
+        end else if ( data_Exists_I ) begin
+          buffer_Full_q <= buffer_full_early;
+        end
+      end
+      assign buffer_Full = buffer_Full_q;
+      
+    end else begin : USE_FPGA_VALID_WRITE
+      wire s_valid_dummy1;
+      wire s_valid_dummy2;
+      wire sel_s_valid;
+      wire sel_new_write;
+      wire valid_Write_dummy1;
+      wire valid_Write_dummy2;
+      
+      assign sel_s_valid = ~buffer_Full;
+      
+      generic_baseblocks_v2_1_0_carry_and #
+        (
+         .C_FAMILY(C_FAMILY)
+         ) s_valid_dummy_inst1
+        (
+         .CIN(S_VALID),
+         .S(1\'b1),
+         .COUT(s_valid_dummy1)
+         );
+      
+      generic_baseblocks_v2_1_0_carry_and #
+        (
+         .C_FAMILY(C_FAMILY)
+         ) s_valid_dummy_inst2
+        (
+         .CIN(s_valid_dummy1),
+         .S(1\'b1),
+         .COUT(s_valid_dummy2)
+         );
+      
+      generic_baseblocks_v2_1_0_carry_and #
+        (
+         .C_FAMILY(C_FAMILY)
+         ) valid_write_inst
+        (
+         .CIN(s_valid_dummy2),
+         .S(sel_s_valid),
+         .COUT(valid_Write)
+         );
+      
+      assign sel_new_write = ~buffer_Empty;
+       
+      generic_baseblocks_v2_1_0_carry_latch_or #
+        (
+         .C_FAMILY(C_FAMILY)
+         ) new_write_inst
+        (
+         .CIN(valid_Write),
+         .I(sel_new_write),
+         .O(new_write)
+         );
+         
+      generic_baseblocks_v2_1_0_carry_and #
+        (
+         .C_FAMILY(C_FAMILY)
+         ) valid_write_dummy_inst1
+        (
+         .CIN(valid_Write),
+         .S(1\'b1),
+         .COUT(valid_Write_dummy1)
+         );
+      
+      generic_baseblocks_v2_1_0_carry_and #
+        (
+         .C_FAMILY(C_FAMILY)
+         ) valid_write_dummy_inst2
+        (
+         .CIN(valid_Write_dummy1),
+         .S(1\'b1),
+         .COUT(valid_Write_dummy2)
+         );
+      
+      generic_baseblocks_v2_1_0_carry_and #
+        (
+         .C_FAMILY(C_FAMILY)
+         ) valid_write_dummy_inst3
+        (
+         .CIN(valid_Write_dummy2),
+         .S(1\'b1),
+         .COUT(addr_cy[0])
+         );
+      
+      FDRE #(
+       .INIT(1\'b0)              // Initial value of register (1\'b0 or 1\'b1)
+       ) FDRE_I1 (
+       .Q(buffer_Full),         // Data output
+       .C(ACLK),                // Clock input
+       .CE(data_Exists_I),      // Clock enable input
+       .R(ARESET),              // Synchronous reset input
+       .D(buffer_full_early)    // Data input
+       );
+       
+    end
+  endgenerate
+      
+    
+  /////////////////////////////////////////////////////////////////////////////
+  // Create address pointer
+  /////////////////////////////////////////////////////////////////////////////
+
+  generate
+    if ( C_FAMILY == ""rtl"" ) begin : USE_RTL_ADDR
+    
+      reg  [C_FIFO_DEPTH_LOG-1:0] addr_q;
+      
+      always @ (posedge ACLK) begin
+        if (ARESET) begin
+          addr_q <= {C_FIFO_DEPTH_LOG{1\'b0}};
+        end else if ( data_Exists_I ) begin
+          if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
+            addr_q <= addr_q + 1\'b1;
+          end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
+            addr_q <= addr_q - 1\'b1;
+          end
+          else begin
+            addr_q <= addr_q;
+          end
+        end
+        else begin
+          addr_q <= addr_q;
+        end
+      end
+      
+      assign addr = addr_q;
+      
+    end else begin : USE_FPGA_ADDR
+      for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
+        assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
+        
+        // Don\'t need the last muxcy, addr_cy(last) is not used anywhere
+        if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
+          MUXCY MUXCY_inst (
+           .DI(addr[addr_cnt]),
+           .CI(addr_cy[addr_cnt]),
+           .S(hsum_A[addr_cnt]),
+           .O(addr_cy[addr_cnt+1])
+           );
+           
+        end
+        else begin : NO_MUXCY
+        end
+        
+        XORCY XORCY_inst (
+         .LI(hsum_A[addr_cnt]),
+         .CI(addr_cy[addr_cnt]),
+         .O(sum_A[addr_cnt])
+         );
+        
+        FDRE #(
+         .INIT(1\'b0)             // Initial value of register (1\'b0 or 1\'b1)
+         ) FDRE_inst (
+         .Q(addr[addr_cnt]),     // Data output
+         .C(ACLK),               // Clock input
+         .CE(data_Exists_I),     // Clock enable input
+         .R(ARESET),             // Synchronous reset input
+         .D(sum_A[addr_cnt])     // Data input
+         );
+        
+      end // end for bit_cnt
+    end // C_FAMILY
+  endgenerate
+      
+      
+  /////////////////////////////////////////////////////////////////////////////
+  // Data storage
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    if ( C_FAMILY == ""rtl"" ) begin : USE_RTL_FIFO
+      reg  [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
+      
+      always @ (posedge ACLK) begin
+        if ( valid_Write ) begin
+          for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
+            data_srl[index+1] <= data_srl[index];
+          end
+          data_srl[0]   <= S_MESG;
+        end
+      end
+      
+      assign M_MESG_I = data_srl[addr];
+      
+    end else begin : USE_FPGA_FIFO
+      for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
+        
+        if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
+            SRLC32E # (
+             .INIT(32\'h00000000)    // Initial Value of Shift Register
+            ) SRLC32E_inst (
+             .Q(M_MESG_I[bit_cnt]), // SRL data output
+             .Q31(),                // SRL cascade output pin
+             .A(addr),              // 5-bit shift depth select input
+             .CE(valid_Write),      // Clock enable input
+             .CLK(ACLK),            // Clock input
+             .D(S_MESG[bit_cnt])    // SRL data input
+            );
+        end else begin : USE_16
+            SRLC16E # (
+             .INIT(32\'h00000000)    // Initial Value of Shift Register
+            ) SRLC16E_inst (
+             .Q(M_MESG_I[bit_cnt]), // SRL data output
+             .Q15(),                // SRL cascade output pin
+             .A0(addr[0]),          // 4-bit shift depth select input 0
+             .A1(addr[1]),          // 4-bit shift depth select input 1
+             .A2(addr[2]),          // 4-bit shift depth select input 2
+             .A3(addr[3]),          // 4-bit shift depth select input 3
+             .CE(valid_Write),      // Clock enable input
+             .CLK(ACLK),            // Clock input
+             .D(S_MESG[bit_cnt])    // SRL data input
+            );
+        end // C_FIFO_DEPTH_LOG
+      
+      end // end for bit_cnt
+    end // C_FAMILY
+  endgenerate
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Pipeline stage
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
+      
+      wire [C_FIFO_WIDTH-1:0]     M_MESG_FF;    // Payload
+      wire                        M_VALID_FF;   // FIFO not empty
+      
+      // Select RTL or FPGA optimized instatiations for critical parts.
+      if ( C_FAMILY == ""rtl"" ) begin : USE_RTL_OUTPUT_PIPELINE
+      
+        reg  [C_FIFO_WIDTH-1:0]     M_MESG_Q;   // Payload
+        reg                         M_VALID_Q;  // FIFO not empty
+        
+        always @ (posedge ACLK) begin
+          if (ARESET) begin
+            M_MESG_Q    <= {C_FIFO_WIDTH{1\'b0}};
+            M_VALID_Q   <= 1\'b0;
+          end else begin
+            if ( M_READY_I ) begin
+              M_MESG_Q    <= M_MESG_I;
+              M_VALID_Q   <= M_VALID_I;
+            end
+          end
+        end
+      
+        assign M_MESG_FF     = M_MESG_Q;
+        assign M_VALID_FF    = M_VALID_Q;
+        
+      end else begin : USE_FPGA_OUTPUT_PIPELINE
+      
+        reg  [C_FIFO_WIDTH-1:0]     M_MESG_CMB;   // Payload
+        reg                         M_VALID_CMB;  // FIFO not empty
+        
+        always @ *
+        begin
+          if ( M_READY_I ) begin
+            M_MESG_CMB  <= M_MESG_I;
+            M_VALID_CMB <= M_VALID_I;
+          end else begin
+            M_MESG_CMB  <= M_MESG_FF;
+            M_VALID_CMB <= M_VALID_FF;
+          end
+        end
+        
+        for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
+              
+          FDRE #(
+           .INIT(1\'b0)                    // Initial value of register (1\'b0 or 1\'b1)
+           ) FDRE_inst (
+           .Q(M_MESG_FF[bit_cnt]),        // Data output
+           .C(ACLK),                      // Clock input
+           .CE(1\'b1),                     // Clock enable input
+           .R(ARESET),                    // Synchronous reset input
+           .D(M_MESG_CMB[bit_cnt])        // Data input
+           );
+        end // end for bit_cnt
+            
+        FDRE #(
+         .INIT(1\'b0)                    // Initial value of register (1\'b0 or 1\'b1)
+         ) FDRE_inst (
+         .Q(M_VALID_FF),                // Data output
+         .C(ACLK),                      // Clock input
+         .CE(1\'b1),                     // Clock enable input
+         .R(ARESET),                    // Synchronous reset input
+         .D(M_VALID_CMB)                // Data input
+         );
+      
+      end
+      
+      assign EMPTY      = ~M_VALID_I & ~M_VALID_FF;
+      assign M_MESG     = M_MESG_FF;
+      assign M_VALID    = M_VALID_FF;
+      assign M_READY_I  = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
+      
+    end else begin : NO_FF_OUT
+      
+      assign EMPTY      = ~M_VALID_I;
+      assign M_MESG     = M_MESG_I;
+      assign M_VALID    = M_VALID_I;
+      assign M_READY_I  = M_READY;
+      
+    end
+  endgenerate
+
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_comparator_mask_static #
+  (
+   parameter         C_FAMILY                         = ""virtex6"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter         C_VALUE                          = 4\'b0,
+                       // Static value to compare against.
+   parameter integer C_DATA_WIDTH                     = 4
+                       // Data width for comparator.
+   )
+  (
+   input  wire                    CIN,
+   input  wire [C_DATA_WIDTH-1:0] A,
+   input  wire [C_DATA_WIDTH-1:0] M,
+   output wire                    COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar lut_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Bits per LUT for this architecture.
+  localparam integer C_BITS_PER_LUT   = 3;
+  
+  // Constants for packing levels.
+  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
+  
+  // 
+  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
+                                        C_DATA_WIDTH;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIX_DATA_WIDTH-1:0] a_local;
+  wire [C_FIX_DATA_WIDTH-1:0] b_local;
+  wire [C_FIX_DATA_WIDTH-1:0] m_local;
+  wire [C_NUM_LUT-1:0]        sel;
+  wire [C_NUM_LUT:0]          carry_local;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    // Assign input to local vectors.
+    assign carry_local[0] = CIN;
+    
+    // Extend input data to fit.
+    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
+      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign b_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+    end else begin : NO_EXTENDED_DATA
+      assign a_local        = A;
+      assign b_local        = C_VALUE;
+      assign m_local        = M;
+    end
+    
+    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.
+    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
+      // Create the local select signal
+      assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == 
+                              ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
+    
+      // Instantiate each LUT level.
+      generic_baseblocks_v2_1_0_carry_and # 
+      (
+       .C_FAMILY(C_FAMILY)
+      ) compare_inst 
+      (
+       .COUT  (carry_local[lut_cnt+1]),
+       .CIN   (carry_local[lut_cnt]),
+       .S     (sel[lut_cnt])
+      ); 
+      
+    end // end for lut_cnt
+    
+    // Assign output from local vector.
+    assign COUT = carry_local[C_NUM_LUT];
+    
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_comparator_mask #
+  (
+   parameter         C_FAMILY                         = ""virtex6"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter integer C_DATA_WIDTH                     = 4
+                       // Data width for comparator.
+   )
+  (
+   input  wire                    CIN,
+   input  wire [C_DATA_WIDTH-1:0] A,
+   input  wire [C_DATA_WIDTH-1:0] B,
+   input  wire [C_DATA_WIDTH-1:0] M,
+   output wire                    COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar lut_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Bits per LUT for this architecture.
+  localparam integer C_BITS_PER_LUT   = 2;
+  
+  // Constants for packing levels.
+  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
+  
+  // 
+  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
+                                        C_DATA_WIDTH;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIX_DATA_WIDTH-1:0] a_local;
+  wire [C_FIX_DATA_WIDTH-1:0] b_local;
+  wire [C_FIX_DATA_WIDTH-1:0] m_local;
+  wire [C_NUM_LUT-1:0]        sel;
+  wire [C_NUM_LUT:0]          carry_local;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    // Assign input to local vectors.
+    assign carry_local[0] = CIN;
+    
+    // Extend input data to fit.
+    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
+      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+    end else begin : NO_EXTENDED_DATA
+      assign a_local        = A;
+      assign b_local        = B;
+      assign m_local        = M;
+    end
+  
+    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.
+    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
+      // Create the local select signal
+      assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == 
+                              ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
+    
+      // Instantiate each LUT level.
+      generic_baseblocks_v2_1_0_carry_and # 
+      (
+       .C_FAMILY(C_FAMILY)
+      ) compare_inst 
+      (
+       .COUT  (carry_local[lut_cnt+1]),
+       .CIN   (carry_local[lut_cnt]),
+       .S     (sel[lut_cnt])
+      ); 
+      
+    end // end for lut_cnt
+    
+    // Assign output from local vector.
+    assign COUT = carry_local[C_NUM_LUT];
+    
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_comparator_sel_mask_static #
+  (
+   parameter         C_FAMILY                         = ""virtex6"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter         C_VALUE                          = 4\'b0,
+                       // Static value to compare against.
+   parameter integer C_DATA_WIDTH                     = 4
+                       // Data width for comparator.
+   )
+  (
+   input  wire                    CIN,
+   input  wire                    S,
+   input  wire [C_DATA_WIDTH-1:0] A,
+   input  wire [C_DATA_WIDTH-1:0] B,
+   input  wire [C_DATA_WIDTH-1:0] M,
+   output wire                    COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar lut_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Bits per LUT for this architecture.
+  localparam integer C_BITS_PER_LUT   = 1;
+  
+  // Constants for packing levels.
+  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
+  
+  // 
+  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
+                                        C_DATA_WIDTH;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIX_DATA_WIDTH-1:0] a_local;
+  wire [C_FIX_DATA_WIDTH-1:0] b_local;
+  wire [C_FIX_DATA_WIDTH-1:0] m_local;
+  wire [C_FIX_DATA_WIDTH-1:0] v_local;
+  wire [C_NUM_LUT-1:0]        sel;
+  wire [C_NUM_LUT:0]          carry_local;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    // Assign input to local vectors.
+    assign carry_local[0] = CIN;
+    
+    // Extend input data to fit.
+    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
+      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign b_local        = {B,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign m_local        = {M,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign v_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+    end else begin : NO_EXTENDED_DATA
+      assign a_local        = A;
+      assign b_local        = B;
+      assign m_local        = M;
+      assign v_local        = C_VALUE;
+    end
+    
+    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.
+    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
+      // Create the local select signal
+      assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
+                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1\'b0 ) ) |
+                            ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
+                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1\'b1 ) );
+    
+      // Instantiate each LUT level.
+      generic_baseblocks_v2_1_0_carry_and # 
+      (
+       .C_FAMILY(C_FAMILY)
+      ) compare_inst 
+      (
+       .COUT  (carry_local[lut_cnt+1]),
+       .CIN   (carry_local[lut_cnt]),
+       .S     (sel[lut_cnt])
+      ); 
+      
+    end // end for lut_cnt
+    
+    // Assign output from local vector.
+    assign COUT = carry_local[C_NUM_LUT];
+    
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_comparator_sel_mask #
+  (
+   parameter         C_FAMILY                         = ""virtex6"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter integer C_DATA_WIDTH                     = 4
+                       // Data width for comparator.
+   )
+  (
+   input  wire                    CIN,
+   input  wire                    S,
+   input  wire [C_DATA_WIDTH-1:0] A,
+   input  wire [C_DATA_WIDTH-1:0] B,
+   input  wire [C_DATA_WIDTH-1:0] M,
+   input  wire [C_DATA_WIDTH-1:0] V,
+   output wire                    COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar lut_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Bits per LUT for this architecture.
+  localparam integer C_BITS_PER_LUT   = 1;
+  
+  // Constants for packing levels.
+  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
+  
+  // 
+  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
+                                        C_DATA_WIDTH;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIX_DATA_WIDTH-1:0] a_local;
+  wire [C_FIX_DATA_WIDTH-1:0] b_local;
+  wire [C_FIX_DATA_WIDTH-1:0] m_local;
+  wire [C_FIX_DATA_WIDTH-1:0] v_local;
+  wire [C_NUM_LUT-1:0]        sel;
+  wire [C_NUM_LUT:0]          carry_local;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    // Assign input to local vectors.
+    assign carry_local[0] = CIN;
+    
+    // Extend input data to fit.
+    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
+      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign m_local        = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign v_local        = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+    end else begin : NO_EXTENDED_DATA
+      assign a_local        = A;
+      assign b_local        = B;
+      assign m_local        = M;
+      assign v_local        = V;
+    end
+    
+    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.
+    for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
+      // Create the local select signal
+      assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
+                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1\'b0 ) ) |
+                            ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
+                                ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
+                                  m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1\'b1 ) );
+    
+      // Instantiate each LUT level.
+      generic_baseblocks_v2_1_0_carry_and # 
+      (
+       .C_FAMILY(C_FAMILY)
+      ) compare_inst 
+      (
+       .COUT  (carry_local[lut_cnt+1]),
+       .CIN   (carry_local[lut_cnt]),
+       .S     (sel[lut_cnt])
+      ); 
+      
+    end // end for lut_cnt
+    
+    // Assign output from local vector.
+    assign COUT = carry_local[C_NUM_LUT];
+    
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_comparator_sel_static #
+  (
+   parameter         C_FAMILY                         = ""virtex6"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter         C_VALUE                          = 4\'b0,
+                       // Static value to compare against.
+   parameter integer C_DATA_WIDTH                     = 4
+                       // Data width for comparator.
+   )
+  (
+   input  wire                    CIN,
+   input  wire                    S,
+   input  wire [C_DATA_WIDTH-1:0] A,
+   input  wire [C_DATA_WIDTH-1:0] B,
+   output wire                    COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar bit_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Bits per LUT for this architecture.
+  localparam integer C_BITS_PER_LUT   = 2;
+  
+  // Constants for packing levels.
+  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
+  
+  // 
+  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
+                                        C_DATA_WIDTH;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIX_DATA_WIDTH-1:0] a_local;
+  wire [C_FIX_DATA_WIDTH-1:0] b_local;
+  wire [C_FIX_DATA_WIDTH-1:0] v_local;
+  wire [C_NUM_LUT-1:0]        sel;
+  wire [C_NUM_LUT:0]          carry_local;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    // Assign input to local vectors.
+    assign carry_local[0] = CIN;
+    
+    // Extend input data to fit.
+    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
+      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign b_local        = {B,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign v_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+    end else begin : NO_EXTENDED_DATA
+      assign a_local        = A;
+      assign b_local        = B;
+      assign v_local        = C_VALUE;
+    end
+    
+    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.
+    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
+      // Create the local select signal
+      assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 
+                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1\'b0 ) ) |
+                            ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 
+                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1\'b1 ) );
+    
+      // Instantiate each LUT level.
+      generic_baseblocks_v2_1_0_carry_and # 
+      (
+       .C_FAMILY(C_FAMILY)
+      ) compare_inst 
+      (
+       .COUT  (carry_local[bit_cnt+1]),
+       .CIN   (carry_local[bit_cnt]),
+       .S     (sel[bit_cnt])
+      ); 
+      
+    end // end for bit_cnt
+    
+    // Assign output from local vector.
+    assign COUT = carry_local[C_NUM_LUT];
+    
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_comparator_sel #
+  (
+   parameter         C_FAMILY                         = ""virtex6"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter integer C_DATA_WIDTH                     = 4
+                       // Data width for comparator.
+   )
+  (
+   input  wire                    CIN,
+   input  wire                    S,
+   input  wire [C_DATA_WIDTH-1:0] A,
+   input  wire [C_DATA_WIDTH-1:0] B,
+   input  wire [C_DATA_WIDTH-1:0] V,
+   output wire                    COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar bit_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Bits per LUT for this architecture.
+  localparam integer C_BITS_PER_LUT   = 1;
+  
+  // Constants for packing levels.
+  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
+  
+  // 
+  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
+                                        C_DATA_WIDTH;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIX_DATA_WIDTH-1:0] a_local;
+  wire [C_FIX_DATA_WIDTH-1:0] b_local;
+  wire [C_FIX_DATA_WIDTH-1:0] v_local;
+  wire [C_NUM_LUT-1:0]        sel;
+  wire [C_NUM_LUT:0]          carry_local;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    // Assign input to local vectors.
+    assign carry_local[0] = CIN;
+    
+    // Extend input data to fit.
+    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
+      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign v_local        = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+    end else begin : NO_EXTENDED_DATA
+      assign a_local        = A;
+      assign b_local        = B;
+      assign v_local        = V;
+    end
+  
+    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.
+    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
+      // Create the local select signal
+      assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 
+                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1\'b0 ) ) |
+                            ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 
+                                v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1\'b1 ) );
+    
+      // Instantiate each LUT level.
+      generic_baseblocks_v2_1_0_carry_and # 
+      (
+       .C_FAMILY(C_FAMILY)
+      ) compare_inst 
+      (
+       .COUT  (carry_local[bit_cnt+1]),
+       .CIN   (carry_local[bit_cnt]),
+       .S     (sel[bit_cnt])
+      ); 
+      
+    end // end for bit_cnt
+    
+    // Assign output from local vector.
+    assign COUT = carry_local[C_NUM_LUT];
+    
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_comparator_static #
+  (
+   parameter         C_FAMILY                         = ""virtex6"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter         C_VALUE                          = 4\'b0,
+                       // Static value to compare against.
+   parameter integer C_DATA_WIDTH                     = 4
+                       // Data width for comparator.
+   )
+  (
+   input  wire                    CIN,
+   input  wire [C_DATA_WIDTH-1:0] A,
+   output wire                    COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar bit_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Bits per LUT for this architecture.
+  localparam integer C_BITS_PER_LUT   = 6;
+  
+  // Constants for packing levels.
+  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
+  
+  // 
+  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
+                                        C_DATA_WIDTH;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIX_DATA_WIDTH-1:0] a_local;
+  wire [C_FIX_DATA_WIDTH-1:0] b_local;
+  wire [C_NUM_LUT-1:0]        sel;
+  wire [C_NUM_LUT:0]          carry_local;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    // Assign input to local vectors.
+    assign carry_local[0] = CIN;
+    
+    // Extend input data to fit.
+    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
+      assign a_local        = {A,       {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign b_local        = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+    end else begin : NO_EXTENDED_DATA
+      assign a_local        = A;
+      assign b_local        = C_VALUE;
+    end
+    
+    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.
+    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
+      // Create the local select signal
+      assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 
+                              b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
+    
+      // Instantiate each LUT level.
+      generic_baseblocks_v2_1_0_carry_and # 
+      (
+       .C_FAMILY(C_FAMILY)
+      ) compare_inst 
+      (
+       .COUT  (carry_local[bit_cnt+1]),
+       .CIN   (carry_local[bit_cnt]),
+       .S     (sel[bit_cnt])
+      ); 
+      
+    end // end for bit_cnt
+    
+    // Assign output from local vector.
+    assign COUT = carry_local[C_NUM_LUT];
+    
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_comparator #
+  (
+   parameter         C_FAMILY                         = ""virtex6"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter integer C_DATA_WIDTH                     = 4
+                       // Data width for comparator.
+   )
+  (
+   input  wire                    CIN,
+   input  wire [C_DATA_WIDTH-1:0] A,
+   input  wire [C_DATA_WIDTH-1:0] B,
+   output wire                    COUT
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar bit_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Bits per LUT for this architecture.
+  localparam integer C_BITS_PER_LUT   = 3;
+  
+  // Constants for packing levels.
+  localparam integer C_NUM_LUT        = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
+  
+  // 
+  localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
+                                        C_DATA_WIDTH;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  wire [C_FIX_DATA_WIDTH-1:0] a_local;
+  wire [C_FIX_DATA_WIDTH-1:0] b_local;
+  wire [C_NUM_LUT-1:0]        sel;
+  wire [C_NUM_LUT:0]          carry_local;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    // Assign input to local vectors.
+    assign carry_local[0] = CIN;
+    
+    // Extend input data to fit.
+    if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
+      assign a_local        = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+      assign b_local        = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1\'b0}}};
+    end else begin : NO_EXTENDED_DATA
+      assign a_local        = A;
+      assign b_local        = B;
+    end
+  
+    // Instantiate one generic_baseblocks_v2_1_0_carry and per level.
+    for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
+      // Create the local select signal
+      assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 
+                              b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
+    
+      // Instantiate each LUT level.
+      generic_baseblocks_v2_1_0_carry_and # 
+      (
+       .C_FAMILY(C_FAMILY)
+      ) compare_inst 
+      (
+       .COUT  (carry_local[bit_cnt+1]),
+       .CIN   (carry_local[bit_cnt]),
+       .S     (sel[bit_cnt])
+      ); 
+      
+    end // end for bit_cnt
+    
+    // Assign output from local vector.
+    assign COUT = carry_local[C_NUM_LUT];
+    
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized Mux using MUXF7/8.
+//  Any generic_baseblocks_v2_1_0_mux ratio.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   mux_enc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_mux_enc #
+  (
+   parameter         C_FAMILY                       = ""rtl"",
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter integer C_RATIO                        = 4,
+                       // Mux select ratio. Can be any binary value (>= 1)
+   parameter integer C_SEL_WIDTH                    = 2,
+                       // Log2-ceiling of C_RATIO (>= 1)
+   parameter integer C_DATA_WIDTH                   = 1
+                       // Data width for generic_baseblocks_v2_1_0_comparator (>= 1)
+   )
+  (
+   input  wire [C_SEL_WIDTH-1:0]                    S,
+   input  wire [C_RATIO*C_DATA_WIDTH-1:0]           A,
+   output wire [C_DATA_WIDTH-1:0]                   O,
+   input  wire                                      OE
+   );
+  
+  wire [C_DATA_WIDTH-1:0] o_i;
+  genvar bit_cnt;
+  
+  function [C_DATA_WIDTH-1:0] f_mux
+    (
+     input [C_SEL_WIDTH-1:0] s,
+     input [C_RATIO*C_DATA_WIDTH-1:0] a
+     );
+    integer i;
+    reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
+    begin
+      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1\'b1:1\'b0}} & a[C_DATA_WIDTH-1:0];
+      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
+        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = 
+          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
+          ({C_DATA_WIDTH{(s==i)?1\'b1:1\'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
+      end
+      f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
+    end
+  endfunction
+  
+  function [C_DATA_WIDTH-1:0] f_mux4
+    (
+     input [1:0] s,
+     input [4*C_DATA_WIDTH-1:0] a
+     );
+    integer i;
+    reg [4*C_DATA_WIDTH-1:0] carry;
+    begin
+      carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1\'b1:1\'b0}} & a[C_DATA_WIDTH-1:0];
+      for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
+        carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] = 
+          carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
+          ({C_DATA_WIDTH{(s==i)?1\'b1:1\'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
+      end
+      f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
+    end
+  endfunction
+  
+  assign O = o_i & {C_DATA_WIDTH{OE}};  // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
+  
+  generate
+    if ( C_RATIO < 2 ) begin : gen_bypass
+      assign o_i = A;
+    end else if ( C_FAMILY == ""rtl"" || C_RATIO < 5 ) begin : gen_rtl
+      assign o_i = f_mux(S, A);
+      
+    end else begin : gen_fpga
+      wire [C_DATA_WIDTH-1:0] l;
+      wire [C_DATA_WIDTH-1:0] h;
+      wire [C_DATA_WIDTH-1:0] ll;
+      wire [C_DATA_WIDTH-1:0] lh;
+      wire [C_DATA_WIDTH-1:0] hl;
+      wire [C_DATA_WIDTH-1:0] hh;
+      
+      case (C_RATIO)
+        1, 5, 9, 13: 
+          assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
+        2, 6, 10, 14:
+          assign hh = S[0] ? 
+            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+            A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
+        3, 7, 11, 15:
+          assign hh = S[1] ? 
+            A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+            (S[0] ? 
+              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
+        4, 8, 12, 16:
+          assign hh = S[1] ? 
+            (S[0] ? 
+              A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
+            (S[0] ? 
+              A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
+        17:
+          assign hh = S[1] ? 
+            (S[0] ? 
+              A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
+            (S[0] ? 
+              A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
+              A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
+        default:
+          assign hh = 0; 
+      endcase
+
+      case (C_RATIO)
+        5, 6, 7, 8: begin
+          assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
+            MUXF7 mux_s2_inst 
+            (
+             .I0  (l[bit_cnt]),
+             .I1  (hh[bit_cnt]),
+             .S   (S[2]),
+             .O   (o_i[bit_cnt])
+            ); 
+          end
+        end
+          
+        9, 10, 11, 12: begin
+          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
+            MUXF7 muxf_s2_low_inst 
+            (
+             .I0  (ll[bit_cnt]),
+             .I1  (lh[bit_cnt]),
+             .S   (S[2]),
+             .O   (l[bit_cnt])
+            ); 
+            MUXF8 muxf_s3_inst 
+            (
+             .I0  (l[bit_cnt]),
+             .I1  (hh[bit_cnt]),
+             .S   (S[3]),
+             .O   (o_i[bit_cnt])
+            ); 
+          end
+        end
+          
+        13,14,15,16: begin
+          assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
+          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
+            MUXF7 muxf_s2_low_inst 
+            (
+             .I0  (ll[bit_cnt]),
+             .I1  (lh[bit_cnt]),
+             .S   (S[2]),
+             .O   (l[bit_cnt])
+            ); 
+            MUXF7 muxf_s2_hi_inst 
+            (
+             .I0  (hl[bit_cnt]),
+             .I1  (hh[bit_cnt]),
+             .S   (S[2]),
+             .O   (h[bit_cnt])
+            );
+          
+            MUXF8 muxf_s3_inst 
+            (
+             .I0  (l[bit_cnt]),
+             .I1  (h[bit_cnt]),
+             .S   (S[3]),
+             .O   (o_i[bit_cnt])
+            ); 
+          end
+        end
+          
+        17: begin
+          assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);  // 5-input mux
+          assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
+          for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
+            MUXF7 muxf_s2_low_inst 
+            (
+             .I0  (ll[bit_cnt]),
+             .I1  (lh[bit_cnt]),
+             .S   (S[2]),
+             .O   (l[bit_cnt])
+            ); 
+            MUXF7 muxf_s2_hi_inst 
+            (
+             .I0  (hl[bit_cnt]),
+             .I1  (hh[bit_cnt]),
+             .S   (S[2]),
+             .O   (h[bit_cnt])
+            ); 
+            MUXF8 muxf_s3_inst 
+            (
+             .I0  (l[bit_cnt]),
+             .I1  (h[bit_cnt]),
+             .S   (S[3]),
+             .O   (o_i[bit_cnt])
+            ); 
+          end
+        end
+          
+        default:  // If RATIO > 17, use RTL
+          assign o_i = f_mux(S, A);
+      endcase
+    end  // gen_fpga
+  endgenerate
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: 
+//  Optimized Mux from 2:1 upto 16:1.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_mux #
+  (
+   parameter         C_FAMILY                         = ""rtl"",
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter integer C_SEL_WIDTH                      = 4,
+                       // Data width for comparator.
+   parameter integer C_DATA_WIDTH                     = 2
+                       // Data width for comparator.
+   )
+  (
+   input  wire [C_SEL_WIDTH-1:0]                    S,
+   input  wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0]  A,
+   output wire [C_DATA_WIDTH-1:0]                   O
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Generate variable for bit vector.
+  genvar bit_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Instantiate or use RTL code
+  /////////////////////////////////////////////////////////////////////////////
+  
+  generate
+    if ( C_FAMILY == ""rtl"" || C_SEL_WIDTH < 3 ) begin : USE_RTL
+      assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
+      
+    end else begin : USE_FPGA
+      
+      wire [C_DATA_WIDTH-1:0] C;
+      wire [C_DATA_WIDTH-1:0] D;
+      
+      // Lower half recursively.
+      generic_baseblocks_v2_1_0_mux # 
+      (
+       .C_FAMILY      (C_FAMILY),
+       .C_SEL_WIDTH   (C_SEL_WIDTH-1),
+       .C_DATA_WIDTH  (C_DATA_WIDTH)
+      ) mux_c_inst 
+      (
+       .S   (S[C_SEL_WIDTH-2:0]),
+       .A   (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
+       .O   (C)
+      ); 
+      
+      // Upper half recursively.
+      generic_baseblocks_v2_1_0_mux # 
+      (
+       .C_FAMILY      (C_FAMILY),
+       .C_SEL_WIDTH   (C_SEL_WIDTH-1),
+       .C_DATA_WIDTH  (C_DATA_WIDTH)
+      ) mux_d_inst 
+      (
+       .S   (S[C_SEL_WIDTH-2:0]),
+       .A   (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
+       .O   (D)
+      ); 
+      
+      // Generate instantiated generic_baseblocks_v2_1_0_mux components as required.
+      for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
+        if ( C_SEL_WIDTH == 4 ) begin : USE_F8
+        
+          MUXF8 muxf8_inst 
+          (
+           .I0  (C[bit_cnt]),
+           .I1  (D[bit_cnt]),
+           .S   (S[C_SEL_WIDTH-1]),
+           .O   (O[bit_cnt])
+          ); 
+          
+        end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
+      
+          MUXF7 muxf7_inst 
+          (
+           .I0  (C[bit_cnt]),
+           .I1  (D[bit_cnt]),
+           .S   (S[C_SEL_WIDTH-1]),
+           .O   (O[bit_cnt])
+          ); 
+          
+        end // C_SEL_WIDTH
+      end // end for bit_cnt
+    
+    end
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: nto1_mux.v
+//
+// Description: N:1 MUX based on either binary-encoded or one-hot select input
+//   One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
+//   Note: All port signals changed to all-upper-case (w.r.t. prior version).
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module generic_baseblocks_v2_1_0_nto1_mux #
+  (
+   parameter integer C_RATIO         =  1,  // Range: >=1
+   parameter integer C_SEL_WIDTH     =  1,  // Range: >=1; recommended: ceil_log2(C_RATIO)
+   parameter integer C_DATAOUT_WIDTH =  1,  // Range: >=1
+   parameter integer C_ONEHOT        =  0   // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
+   )
+  (
+   input  wire [C_RATIO-1:0]                 SEL_ONEHOT,  // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
+   input  wire [C_SEL_WIDTH-1:0]             SEL,         // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
+   input  wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN,          // Data input array (num_selections x data_width)
+   output wire [C_DATAOUT_WIDTH-1:0]         OUT          // Data output vector
+   );
+
+  wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
+  genvar i;
+  
+  generate
+    if (C_ONEHOT == 0) begin : gen_encoded
+      assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1\'b1:1\'b0}} & IN[C_DATAOUT_WIDTH-1:0];
+      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
+        assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] = 
+               carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
+               {C_DATAOUT_WIDTH{(SEL==i)?1\'b1:1\'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
+      end
+    end else begin : gen_onehot
+      assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
+      for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
+        assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] = 
+               carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
+               {C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
+      end
+    end
+  endgenerate
+  assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
+                     C_DATAOUT_WIDTH*(C_RATIO-1)];
+endmodule
+
+`default_nettype wire
+
+
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:35:45 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
+// Design      : design_1_xbar_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, 
+  s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr, 
+  m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, 
+  m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, 
+  m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin=""aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]"" */;
+  input aclk;
+  input aresetn;
+  input [31:0]s_axi_awaddr;
+  input [2:0]s_axi_awprot;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [31:0]s_axi_araddr;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [95:0]m_axi_awaddr;
+  output [8:0]m_axi_awprot;
+  output [2:0]m_axi_awvalid;
+  input [2:0]m_axi_awready;
+  output [95:0]m_axi_wdata;
+  output [11:0]m_axi_wstrb;
+  output [2:0]m_axi_wvalid;
+  input [2:0]m_axi_wready;
+  input [5:0]m_axi_bresp;
+  input [2:0]m_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [95:0]m_axi_araddr;
+  output [8:0]m_axi_arprot;
+  output [2:0]m_axi_arvalid;
+  input [2:0]m_axi_arready;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rvalid;
+  output [2:0]m_axi_rready;
+endmodule
+"
+"// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Generic single-channel AXI FIFO
+// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.
+// Transfers received on the AXI slave port are pushed onto the FIFO.
+// FIFO output, when available, is presented on the AXI master port and
+//   popped when the master port responds (M_READY).
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+// Structure:
+//   axic_fifo
+//     fifo_gen
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_data_fifo_v2_1_10_axic_fifo #
+  (
+   parameter         C_FAMILY          = ""virtex6"",
+   parameter integer C_FIFO_DEPTH_LOG  = 5,      // FIFO depth = 2**C_FIFO_DEPTH_LOG
+                                                 // Range = [5:9] when TYPE=""lut"",
+                                                 // Range = [5:12] when TYPE=""bram"",
+   parameter integer C_FIFO_WIDTH      = 64,     // Width of payload [1:512]
+   parameter         C_FIFO_TYPE       = ""lut""   // ""lut"" = LUT (SRL) based,
+                                                 // ""bram"" = BRAM based
+   )
+  (
+   // Global inputs
+   input  wire                        ACLK,    // Clock
+   input  wire                        ARESET,  // Reset
+   // Slave  Port
+   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Payload (may be any set of channel signals)
+   input  wire                        S_VALID, // FIFO push
+   output wire                        S_READY, // FIFO not full
+   // Master  Port
+   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Payload
+   output wire                        M_VALID, // FIFO not empty
+   input  wire                        M_READY  // FIFO pop
+   );
+
+   axi_data_fifo_v2_1_10_fifo_gen #(
+     .C_FAMILY(C_FAMILY),
+     .C_COMMON_CLOCK(1),
+     .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
+     .C_FIFO_WIDTH(C_FIFO_WIDTH),
+     .C_FIFO_TYPE(C_FIFO_TYPE))
+   inst (
+     .clk(ACLK),
+     .rst(ARESET),
+     .wr_clk(1\'b0),
+     .wr_en(S_VALID),
+     .wr_ready(S_READY),
+     .wr_data(S_MESG),
+     .rd_clk(1\'b0),
+     .rd_en(M_READY),
+     .rd_valid(M_VALID),
+     .rd_data(M_MESG));
+
+endmodule
+
+
+// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------
+
+// The synthesis directives ""translate_off/translate_on"" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the fifo_generator wrapper file when simulating
+// the core. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the ""CORE Generator Help"".
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_data_fifo_v2_1_10_fifo_gen #(
+parameter C_FAMILY          = ""virtex7"",
+parameter integer C_COMMON_CLOCK    = 1,
+parameter integer C_SYNCHRONIZER_STAGE = 3,
+parameter integer C_FIFO_DEPTH_LOG  = 5,
+parameter integer C_FIFO_WIDTH      = 64,
+parameter C_FIFO_TYPE       = ""lut""
+)(
+  clk,
+  rst,
+  wr_clk,
+  wr_en,
+  wr_ready,
+  wr_data,
+  rd_clk,
+  rd_en,
+  rd_valid,
+  rd_data);
+
+input clk;
+input wr_clk;
+input rd_clk;
+input rst;
+input [C_FIFO_WIDTH-1 : 0] wr_data;
+input wr_en;
+input rd_en;
+output [C_FIFO_WIDTH-1 : 0] rd_data;
+output wr_ready;
+output rd_valid;
+
+wire  full;
+wire  empty;
+wire  rd_valid = ~empty;
+wire  wr_ready = ~full;
+
+localparam C_MEMORY_TYPE =  (C_FIFO_TYPE == ""bram"")? 1 : 2;
+
+localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;
+
+  fifo_generator_v13_1_3 #(
+    .C_COMMON_CLOCK(C_COMMON_CLOCK),
+    .C_DIN_WIDTH(C_FIFO_WIDTH),
+    .C_DOUT_WIDTH(C_FIFO_WIDTH),
+    .C_FAMILY(C_FAMILY),
+    .C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),
+    .C_MEMORY_TYPE(C_MEMORY_TYPE),
+    .C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),
+    .C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
+    .C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),
+    .C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_AXIS_TDATA_WIDTH(64),
+    .C_AXIS_TDEST_WIDTH(4),
+    .C_AXIS_TID_WIDTH(8),
+    .C_AXIS_TKEEP_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(4),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TYPE(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_LEN_WIDTH(8),
+    .C_AXI_LOCK_WIDTH(2),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_TYPE(0),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(6),
+    .C_DEFAULT_VALUE(""BlankString""),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_WACH(32),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DOUT_RST_VAL(""0""),
+    .C_ENABLE_RLOCS(0),
+    .C_ENABLE_RST_SYNC(1),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_FULL_FLAGS_RST_VAL(0),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_AXIS_TDATA(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TUSER(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_RD_CHANNEL(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_HAS_AXI_WR_CHANNEL(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MASTER_CE(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_RD_DATA_COUNT(0),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_SRST(0),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(0),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_INTERFACE_TYPE(0),
+    .C_MIF_FILE_NAME(""BlankString""),
+    .C_MSGON_VAL(1),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(0),
+    .C_PRELOAD_REGS(1),
+    .C_PRIM_FIFO_TYPE(""512x36""),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(31),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(30),
+    .C_PROG_FULL_TYPE(0),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_RACH_TYPE(0),
+    .C_RDCH_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(6),
+    .C_RD_FREQ(1),
+    .C_REG_SLICE_MODE_AXIS(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_USE_DOUT_RST(0),
+    .C_USE_ECC(0),
+    .C_USE_ECC_AXIS(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(1),
+    .C_VALID_LOW(0),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WRCH_TYPE(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(6),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_RESPONSE_LATENCY(1)
+    )
+  fifo_gen_inst (
+    .clk(clk),
+    .din(wr_data),
+    .dout(rd_data),
+    .empty(empty),
+    .full(full),
+    .rd_clk(rd_clk),
+    .rd_en(rd_en),
+    .rst(rst),
+    .wr_clk(wr_clk),
+    .wr_en(wr_en),
+    .almost_empty(),
+    .almost_full(),
+    .axi_ar_data_count(),
+    .axi_ar_dbiterr(),
+    .axi_ar_injectdbiterr(1\'b0),
+    .axi_ar_injectsbiterr(1\'b0),
+    .axi_ar_overflow(),
+    .axi_ar_prog_empty(),
+    .axi_ar_prog_empty_thresh(4\'b0),
+    .axi_ar_prog_full(),
+    .axi_ar_prog_full_thresh(4\'b0),
+    .axi_ar_rd_data_count(),
+    .axi_ar_sbiterr(),
+    .axi_ar_underflow(),
+    .axi_ar_wr_data_count(),
+    .axi_aw_data_count(),
+    .axi_aw_dbiterr(),
+    .axi_aw_injectdbiterr(1\'b0),
+    .axi_aw_injectsbiterr(1\'b0),
+    .axi_aw_overflow(),
+    .axi_aw_prog_empty(),
+    .axi_aw_prog_empty_thresh(4\'b0),
+    .axi_aw_prog_full(),
+    .axi_aw_prog_full_thresh(4\'b0),
+    .axi_aw_rd_data_count(),
+    .axi_aw_sbiterr(),
+    .axi_aw_underflow(),
+    .axi_aw_wr_data_count(),
+    .axi_b_data_count(),
+    .axi_b_dbiterr(),
+    .axi_b_injectdbiterr(1\'b0),
+    .axi_b_injectsbiterr(1\'b0),
+    .axi_b_overflow(),
+    .axi_b_prog_empty(),
+    .axi_b_prog_empty_thresh(4\'b0),
+    .axi_b_prog_full(),
+    .axi_b_prog_full_thresh(4\'b0),
+    .axi_b_rd_data_count(),
+    .axi_b_sbiterr(),
+    .axi_b_underflow(),
+    .axi_b_wr_data_count(),
+    .axi_r_data_count(),
+    .axi_r_dbiterr(),
+    .axi_r_injectdbiterr(1\'b0),
+    .axi_r_injectsbiterr(1\'b0),
+    .axi_r_overflow(),
+    .axi_r_prog_empty(),
+    .axi_r_prog_empty_thresh(10\'b0),
+    .axi_r_prog_full(),
+    .axi_r_prog_full_thresh(10\'b0),
+    .axi_r_rd_data_count(),
+    .axi_r_sbiterr(),
+    .axi_r_underflow(),
+    .axi_r_wr_data_count(),
+    .axi_w_data_count(),
+    .axi_w_dbiterr(),
+    .axi_w_injectdbiterr(1\'b0),
+    .axi_w_injectsbiterr(1\'b0),
+    .axi_w_overflow(),
+    .axi_w_prog_empty(),
+    .axi_w_prog_empty_thresh(10\'b0),
+    .axi_w_prog_full(),
+    .axi_w_prog_full_thresh(10\'b0),
+    .axi_w_rd_data_count(),
+    .axi_w_sbiterr(),
+    .axi_w_underflow(),
+    .axi_w_wr_data_count(),
+    .axis_data_count(),
+    .axis_dbiterr(),
+    .axis_injectdbiterr(1\'b0),
+    .axis_injectsbiterr(1\'b0),
+    .axis_overflow(),
+    .axis_prog_empty(),
+    .axis_prog_empty_thresh(10\'b0),
+    .axis_prog_full(),
+    .axis_prog_full_thresh(10\'b0),
+    .axis_rd_data_count(),
+    .axis_sbiterr(),
+    .axis_underflow(),
+    .axis_wr_data_count(),
+    .backup(1\'b0),
+    .backup_marker(1\'b0),
+    .data_count(),
+    .dbiterr(),
+    .injectdbiterr(1\'b0),
+    .injectsbiterr(1\'b0),
+    .int_clk(1\'b0),
+    .m_aclk(1\'b0),
+    .m_aclk_en(1\'b0),
+    .m_axi_araddr(),
+    .m_axi_arburst(),
+    .m_axi_arcache(),
+    .m_axi_arid(),
+    .m_axi_arlen(),
+    .m_axi_arlock(),
+    .m_axi_arprot(),
+    .m_axi_arqos(),
+    .m_axi_arready(1\'b0),
+    .m_axi_arregion(),
+    .m_axi_arsize(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(),
+    .m_axi_awaddr(),
+    .m_axi_awburst(),
+    .m_axi_awcache(),
+    .m_axi_awid(),
+    .m_axi_awlen(),
+    .m_axi_awlock(),
+    .m_axi_awprot(),
+    .m_axi_awqos(),
+    .m_axi_awready(1\'b0),
+    .m_axi_awregion(),
+    .m_axi_awsize(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(),
+    .m_axi_bid(4\'b0),
+    .m_axi_bready(),
+    .m_axi_bresp(2\'b0),
+    .m_axi_buser(1\'b0),
+    .m_axi_bvalid(1\'b0),
+    .m_axi_rdata(64\'b0),
+    .m_axi_rid(4\'b0),
+    .m_axi_rlast(1\'b0),
+    .m_axi_rready(),
+    .m_axi_rresp(2\'b0),
+    .m_axi_ruser(1\'b0),
+    .m_axi_rvalid(1\'b0),
+    .m_axi_wdata(),
+    .m_axi_wid(),
+    .m_axi_wlast(),
+    .m_axi_wready(1\'b0),
+    .m_axi_wstrb(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(),
+    .m_axis_tdata(),
+    .m_axis_tdest(),
+    .m_axis_tid(),
+    .m_axis_tkeep(),
+    .m_axis_tlast(),
+    .m_axis_tready(1\'b0),
+    .m_axis_tstrb(),
+    .m_axis_tuser(),
+    .m_axis_tvalid(),
+    .overflow(),
+    .prog_empty(),
+    .prog_empty_thresh(5\'b0),
+    .prog_empty_thresh_assert(5\'b0),
+    .prog_empty_thresh_negate(5\'b0),
+    .prog_full(),
+    .prog_full_thresh(5\'b0),
+    .prog_full_thresh_assert(5\'b0),
+    .prog_full_thresh_negate(5\'b0),
+    .rd_data_count(),
+    .rd_rst(1\'b0),
+    .s_aclk(1\'b0),
+    .s_aclk_en(1\'b0),
+    .s_aresetn(1\'b0),
+    .s_axi_araddr(32\'b0),
+    .s_axi_arburst(2\'b0),
+    .s_axi_arcache(4\'b0),
+    .s_axi_arid(4\'b0),
+    .s_axi_arlen(8\'b0),
+    .s_axi_arlock(2\'b0),
+    .s_axi_arprot(3\'b0),
+    .s_axi_arqos(4\'b0),
+    .s_axi_arready(),
+    .s_axi_arregion(4\'b0),
+    .s_axi_arsize(3\'b0),
+    .s_axi_aruser(1\'b0),
+    .s_axi_arvalid(1\'b0),
+    .s_axi_awaddr(32\'b0),
+    .s_axi_awburst(2\'b0),
+    .s_axi_awcache(4\'b0),
+    .s_axi_awid(4\'b0),
+    .s_axi_awlen(8\'b0),
+    .s_axi_awlock(2\'b0),
+    .s_axi_awprot(3\'b0),
+    .s_axi_awqos(4\'b0),
+    .s_axi_awready(),
+    .s_axi_awregion(4\'b0),
+    .s_axi_awsize(3\'b0),
+    .s_axi_awuser(1\'b0),
+    .s_axi_awvalid(1\'b0),
+    .s_axi_bid(),
+    .s_axi_bready(1\'b0),
+    .s_axi_bresp(),
+    .s_axi_buser(),
+    .s_axi_bvalid(),
+    .s_axi_rdata(),
+    .s_axi_rid(),
+    .s_axi_rlast(),
+    .s_axi_rready(1\'b0),
+    .s_axi_rresp(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(),
+    .s_axi_wdata(64\'b0),
+    .s_axi_wid(4\'b0),
+    .s_axi_wlast(1\'b0),
+    .s_axi_wready(),
+    .s_axi_wstrb(8\'b0),
+    .s_axi_wuser(1\'b0),
+    .s_axi_wvalid(1\'b0),
+    .s_axis_tdata(64\'b0),
+    .s_axis_tdest(4\'b0),
+    .s_axis_tid(8\'b0),
+    .s_axis_tkeep(4\'b0),
+    .s_axis_tlast(1\'b0),
+    .s_axis_tready(),
+    .s_axis_tstrb(4\'b0),
+    .s_axis_tuser(4\'b0),
+    .s_axis_tvalid(1\'b0),
+    .sbiterr(),
+    .srst(1\'b0),
+    .underflow(),
+    .valid(),
+    .wr_ack(),
+    .wr_data_count(),
+    .wr_rst(1\'b0),
+    .wr_rst_busy(),
+    .rd_rst_busy(),
+    .sleep(1\'b0)
+  );
+
+endmodule
+
+
+
+// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+// Structure:
+//   axic_srl_fifo
+//     ndeep_srl
+//       nto1_mux
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_data_fifo_v2_1_10_axic_srl_fifo #
+  (
+   parameter         C_FAMILY   = ""none"", // FPGA Family
+   parameter integer C_FIFO_WIDTH  = 1, // Width of S_MESG/M_MESG.
+   parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
+                                             // the control logic can be used
+                                             // on before the control logic
+                                             // needs to be replicated.
+   parameter integer C_FIFO_DEPTH_LOG =  2,  // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.  
+                                             // The minimum size fifo generated is 4-deep.
+   parameter         C_USE_FULL =  1         // Prevent overwrite by throttling S_READY.                                              
+   )
+  (
+   input  wire                        ACLK,    // Clock
+   input  wire                        ARESET,  // Reset
+   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Input data
+   input  wire                        S_VALID, // Input data valid
+   output wire                        S_READY, // Input data ready
+   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Output data
+   output wire                        M_VALID, // Output data valid
+   input  wire                        M_READY  // Output data ready
+   );
+  
+  localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
+  localparam P_EMPTY       = {P_FIFO_DEPTH_LOG{1\'b1}};
+  localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1\'b0}};
+  localparam P_ALMOSTFULL_TEMP  = {P_EMPTY, 1\'b0};
+  localparam P_ALMOSTFULL  = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
+  localparam P_NUM_REPS    = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
+                             (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
+                             ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
+
+  (* syn_keep = ""1"" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0]  fifoaddr;
+  (* syn_keep = ""1"" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
+
+  genvar i;
+  genvar j;
+
+  reg  M_VALID_i;
+  reg  S_READY_i;
+  wire push;     // FIFO push
+  wire pop;      // FIFO pop
+  reg  areset_d1; // Reset delay register
+  wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
+
+  assign M_VALID = M_VALID_i;
+  assign S_READY = C_USE_FULL ? S_READY_i : 1\'b1;
+  assign M_MESG = m_axi_mesg_i;
+  assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1\'b1);
+  assign pop  = M_VALID_i & M_READY;
+  
+  always @(posedge ACLK) begin
+    areset_d1 <= ARESET;
+  end
+      
+  generate
+    //---------------------------------------------------------------------------
+    // Create count of number of elements in FIFOs
+    //---------------------------------------------------------------------------
+    for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
+      assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = 
+         push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
+                fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
+      always @(posedge ACLK) begin
+        if (ARESET)
+          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= 
+                {P_FIFO_DEPTH_LOG{1\'b1}};
+        else if (push ^ pop)
+          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= 
+                fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
+      end
+    end
+
+    //---------------------------------------------------------------------------
+    // When FIFO is empty, reset master valid bit.  When not empty set valid bit.
+    // When FIFO is full,  reset slave  ready bit.  When not full  set ready bit.
+    //---------------------------------------------------------------------------
+    
+    always @(posedge ACLK) begin
+      if (ARESET) begin
+        M_VALID_i <= 1\'b0;
+      end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == 
+                               P_ALMOSTEMPTY) && pop && ~push) begin
+        M_VALID_i <= 1\'b0;
+      end else if (push) begin
+        M_VALID_i <= 1\'b1;
+      end
+    end
+      
+    always @(posedge ACLK) begin
+      if (ARESET) begin
+        S_READY_i <= 1\'b0;
+      end else if (areset_d1) begin
+        S_READY_i <= 1\'b1;
+      end else if (C_USE_FULL && 
+        ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == 
+         P_ALMOSTFULL) && push && ~pop)) begin
+        S_READY_i <= 1\'b0;
+      end else if (C_USE_FULL && pop) begin
+        S_READY_i <= 1\'b1;
+      end
+    end
+
+    //---------------------------------------------------------------------------
+    // Instantiate SRLs
+    //---------------------------------------------------------------------------
+    for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
+      for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
+        axi_data_fifo_v2_1_10_ndeep_srl #
+          (
+           .C_FAMILY  (C_FAMILY),
+           .C_A_WIDTH (P_FIFO_DEPTH_LOG)
+          )
+          srl_nx1
+          (
+           .CLK (ACLK),
+           .A   (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
+                          P_FIFO_DEPTH_LOG*(i)]),
+           .CE  (push),
+           .D   (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
+           .Q   (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
+          );
+      end
+    end      
+  endgenerate
+  
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
+//   Interface outputs are synchronized using ordinary flops for improved timing.
+//--------------------------------------------------------------------------
+// Structure:
+//   axic_reg_srl_fifo
+//     ndeep_srl
+//       nto1_mux
+//--------------------------------------------------------------------------
+
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_data_fifo_v2_1_10_axic_reg_srl_fifo #
+  (
+   parameter         C_FAMILY   = ""none"", // FPGA Family
+   parameter integer C_FIFO_WIDTH  = 1, // Width of S_MESG/M_MESG.
+   parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
+                                             // the control logic can be used
+                                             // on before the control logic
+                                             // needs to be replicated.
+   parameter integer C_FIFO_DEPTH_LOG =  2,  // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.  
+                                             // The minimum size fifo generated is 4-deep.
+   parameter         C_USE_FULL =  1         // Prevent overwrite by throttling S_READY.                                              
+   )
+  (
+   input  wire                        ACLK,    // Clock
+   input  wire                        ARESET,  // Reset
+   input  wire [C_FIFO_WIDTH-1:0]     S_MESG,  // Input data
+   input  wire                        S_VALID, // Input data valid
+   output wire                        S_READY, // Input data ready
+   output wire [C_FIFO_WIDTH-1:0]     M_MESG,  // Output data
+   output wire                        M_VALID, // Output data valid
+   input  wire                        M_READY  // Output data ready
+   );
+  
+  localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
+  localparam P_EMPTY       = {P_FIFO_DEPTH_LOG{1\'b1}};
+  localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1\'b0}};
+  localparam P_ALMOSTFULL_TEMP  = {P_EMPTY, 1\'b0};
+  localparam P_ALMOSTFULL  = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
+  localparam P_NUM_REPS    = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
+                             (C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
+                             ((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
+
+  (* syn_keep = ""1"" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0]  fifoaddr;
+  (* syn_keep = ""1"" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
+
+  genvar i;
+  genvar j;
+
+  reg  m_valid_i;
+  reg  s_ready_i;
+  wire push;     // FIFO push
+  wire pop;      // FIFO pop
+  reg  areset_d1; // Reset delay register
+  reg  [C_FIFO_WIDTH-1:0] storage_data1;
+  wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
+  reg                    load_s1;
+  wire                   load_s1_from_s2;
+
+  reg [1:0] state;
+  localparam [1:0] 
+    ZERO = 2\'b10,
+    ONE  = 2\'b11,
+    TWO  = 2\'b01;
+      
+  assign M_VALID = m_valid_i;
+  assign S_READY = C_USE_FULL ? s_ready_i : 1\'b1;
+  assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1\'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
+  assign pop  = M_READY & (state == TWO);
+  assign M_MESG = storage_data1;
+  
+  always @(posedge ACLK) begin
+    areset_d1 <= ARESET;
+  end
+      
+  // Load storage1 with either slave side data or from storage2
+  always @(posedge ACLK) 
+  begin
+    if (load_s1)
+      if (load_s1_from_s2)
+        storage_data1 <= storage_data2;
+      else
+        storage_data1 <= S_MESG;        
+  end
+
+  // Loading s1
+  always @ *
+  begin
+    if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
+         // Load when ONE if we both have read and write at the same time
+         ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
+         // Load when TWO and we have a transaction on Master side
+         ((state == TWO) && (M_READY == 1)))
+      load_s1 = 1\'b1;
+    else
+      load_s1 = 1\'b0;
+  end // always @ *
+
+  assign load_s1_from_s2 = (state == TWO);
+                   
+  // State Machine for handling output signals
+  always @(posedge ACLK) 
+  begin
+    if (areset_d1) begin
+      state <= ZERO;
+      m_valid_i <= 1\'b0;
+    end else begin
+      case (state)
+        // No transaction stored locally
+        ZERO: begin
+          if (S_VALID) begin
+            state <= ONE; // Got one so move to ONE
+            m_valid_i <= 1\'b1;
+          end
+        end
+
+        // One transaction stored locally
+        ONE: begin
+          if (M_READY & ~S_VALID) begin
+            state <= ZERO; // Read out one so move to ZERO
+            m_valid_i <= 1\'b0;
+          end else if (~M_READY & S_VALID) begin
+            state <= TWO;  // Got another one so move to TWO
+            m_valid_i <= 1\'b1;
+          end
+        end
+
+        // TWO transaction stored locally
+        TWO: begin
+          if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == 
+                 P_ALMOSTEMPTY) && pop && ~push) begin
+            state <= ONE; // Read out one so move to ONE
+            m_valid_i <= 1\'b1;
+          end
+        end
+      endcase // case (state)
+    end
+  end // always @ (posedge ACLK)
+      
+  generate
+    //---------------------------------------------------------------------------
+    // Create count of number of elements in FIFOs
+    //---------------------------------------------------------------------------
+    for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
+      assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] = 
+         push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
+                fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
+      always @(posedge ACLK) begin
+        if (ARESET)
+          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= 
+                {P_FIFO_DEPTH_LOG{1\'b1}};
+        else if (push ^ pop)
+          fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <= 
+                fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
+      end
+    end
+
+    always @(posedge ACLK) begin
+      if (ARESET) begin
+        s_ready_i <= 1\'b0;
+      end else if (areset_d1) begin
+        s_ready_i <= 1\'b1;
+      end else if (C_USE_FULL && 
+        ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] == 
+         P_ALMOSTFULL) && push && ~pop)) begin
+        s_ready_i <= 1\'b0;
+      end else if (C_USE_FULL && pop) begin
+        s_ready_i <= 1\'b1;
+      end
+    end
+
+    //---------------------------------------------------------------------------
+    // Instantiate SRLs
+    //---------------------------------------------------------------------------
+    for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
+      for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
+        axi_data_fifo_v2_1_10_ndeep_srl #
+          (
+           .C_FAMILY  (C_FAMILY),
+           .C_A_WIDTH (P_FIFO_DEPTH_LOG)
+          )
+          srl_nx1
+          (
+           .CLK (ACLK),
+           .A   (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
+                          P_FIFO_DEPTH_LOG*(i)]),
+           .CE  (push),
+           .D   (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
+           .Q   (storage_data2[i*C_MAX_CTRL_FANOUT+j])
+          );
+      end
+    end      
+  endgenerate
+  
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: This is a generic n-deep SRL instantiation
+// Verilog-standard:  Verilog 2001
+// $Revision: 
+// $Date: 
+//
+//-----------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_data_fifo_v2_1_10_ndeep_srl #
+  (
+   parameter         C_FAMILY  = ""rtl"", // FPGA Family
+   parameter         C_A_WIDTH = 1          // Address Width (>= 1)
+   )
+  (
+   input  wire                 CLK, // Clock
+   input  wire [C_A_WIDTH-1:0] A,   // Address
+   input  wire                 CE,  // Clock Enable
+   input  wire                 D,   // Input Data
+   output wire                 Q    // Output Data
+   );
+
+  localparam integer P_SRLASIZE = 5;
+  localparam integer P_SRLDEPTH = 32;
+  localparam integer P_NUMSRLS  = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
+  localparam integer P_SHIFT_DEPTH  = 2**C_A_WIDTH;
+  
+  wire [P_NUMSRLS:0]   d_i;
+  wire [P_NUMSRLS-1:0] q_i;
+  wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
+  
+  genvar i;
+  
+  // Instantiate SRLs in carry chain format
+  assign d_i[0] = D;
+  assign a_i = A;
+  
+  generate
+\t\t\t\t\t
+    if (C_FAMILY == ""rtl"") begin : gen_rtl_shifter
+      if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
+        reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1\'b0}};
+        always @(posedge CLK)
+          if (CE)
+            shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
+        assign Q = shift_reg[a_i];
+      end else begin : gen_logic_shifter  // Very wasteful
+        reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1\'b0}};
+        always @(posedge CLK)
+          if (CE)
+            shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
+        assign Q = shift_reg[a_i];
+      end
+    end else begin : gen_primitive_shifter
+      for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
+        SRLC32E
+          srl_inst
+            (
+             .CLK (CLK),
+             .A   (a_i[P_SRLASIZE-1:0]),
+             .CE  (CE),
+             .D   (d_i[i]),
+             .Q   (q_i[i]),
+             .Q31 (d_i[i+1])
+             );
+      end
+      
+      if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
+        generic_baseblocks_v2_1_0_nto1_mux #
+        (
+          .C_RATIO         (2**(C_A_WIDTH-P_SRLASIZE)),
+          .C_SEL_WIDTH     (C_A_WIDTH-P_SRLASIZE),
+          .C_DATAOUT_WIDTH (1),
+          .C_ONEHOT        (0)
+        )
+        srl_q_mux_inst
+        (
+          .SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1\'b0}}),
+          .SEL        (a_i[C_A_WIDTH-1:P_SRLASIZE]),
+          .IN         (q_i),
+          .OUT        (Q)
+        );
+      end else begin : gen_no_srl_mux
+        assign Q = q_i[0];
+      end
+    end
+  endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// AXI data fifo module:    
+//   5-channel memory-mapped AXI4 interfaces.
+//   SRL or BRAM based FIFO on AXI W and/or R channels.
+//   FIFO to accommodate various data flow rates through the AXI interconnect
+//
+// Verilog-standard:  Verilog 2001
+//-----------------------------------------------------------------------------
+//
+// Structure:
+//   axi_data_fifo
+//     fifo_generator
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_data_fifo_v2_1_10_axi_data_fifo #
+  (
+   parameter         C_FAMILY                    = ""virtex7"",
+   parameter integer C_AXI_PROTOCOL              = 0,
+   parameter integer C_AXI_ID_WIDTH              = 4,
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_DATA_WIDTH            = 32,
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
+   parameter integer C_AXI_AWUSER_WIDTH          = 1,
+   parameter integer C_AXI_ARUSER_WIDTH          = 1,
+   parameter integer C_AXI_WUSER_WIDTH           = 1,
+   parameter integer C_AXI_RUSER_WIDTH           = 1,
+   parameter integer C_AXI_BUSER_WIDTH           = 1,
+   parameter integer C_AXI_WRITE_FIFO_DEPTH      = 0,      // Range: (0, 32, 512)
+   parameter         C_AXI_WRITE_FIFO_TYPE       = ""lut"",  // ""lut"" = LUT (SRL) based,
+                                                           // ""bram"" = BRAM based
+   parameter integer C_AXI_WRITE_FIFO_DELAY      = 0,      // 0 = No, 1 = Yes
+                       // Indicates whether AWVALID and WVALID assertion is delayed until:
+                       //   a. the corresponding WLAST is stored in the FIFO, or
+                       //   b. no WLAST is stored and the FIFO is full.
+                       // 0 means AW channel is pass-through and 
+                       //   WVALID is asserted whenever FIFO is not empty.
+   parameter integer C_AXI_READ_FIFO_DEPTH       = 0,      // Range: (0, 32, 512)
+   parameter         C_AXI_READ_FIFO_TYPE        = ""lut"",  // ""lut"" = LUT (SRL) based,
+                                                           // ""bram"" = BRAM based
+   parameter integer C_AXI_READ_FIFO_DELAY       = 0)      // 0 = No, 1 = Yes
+                       // Indicates whether ARVALID assertion is delayed until the 
+                       //   the remaining vacancy of the FIFO is at least the burst length
+                       //   as indicated by ARLEN.
+                       // 0 means AR channel is pass-through.
+   // System Signals
+  (input wire aclk,
+   input wire aresetn,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
+   input  wire [3-1:0]                  s_axi_awsize,
+   input  wire [2-1:0]                  s_axi_awburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
+   input  wire [4-1:0]                  s_axi_awcache,
+   input  wire [3-1:0]                  s_axi_awprot,
+   input  wire [4-1:0]                  s_axi_awregion,
+   input  wire [4-1:0]                  s_axi_awqos,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
+   input  wire                          s_axi_awvalid,
+   output wire                          s_axi_awready,
+
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_wid,
+   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
+   input  wire                          s_axi_wlast,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,
+   input  wire                          s_axi_wvalid,
+   output wire                          s_axi_wready,
+
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     s_axi_bid,
+   output wire [2-1:0]                  s_axi_bresp,
+   output wire [C_AXI_BUSER_WIDTH-1:0]  s_axi_buser,
+   output wire                          s_axi_bvalid,
+   input  wire                          s_axi_bready,
+
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
+   input  wire [3-1:0]                  s_axi_arsize,
+   input  wire [2-1:0]                  s_axi_arburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
+   input  wire [4-1:0]                  s_axi_arcache,
+   input  wire [3-1:0]                  s_axi_arprot,
+   input  wire [4-1:0]                  s_axi_ar'b'region,
+   input  wire [4-1:0]                  s_axi_arqos,
+   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
+   input  wire                          s_axi_arvalid,
+   output wire                          s_axi_arready,
+
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     s_axi_rid,
+   output wire [C_AXI_DATA_WIDTH-1:0]   s_axi_rdata,
+   output wire [2-1:0]                  s_axi_rresp,
+   output wire                          s_axi_rlast,
+   output wire [C_AXI_RUSER_WIDTH-1:0]  s_axi_ruser,
+   output wire                          s_axi_rvalid,
+   input  wire                          s_axi_rready,
+   
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
+   output wire [3-1:0]                  m_axi_awsize,
+   output wire [2-1:0]                  m_axi_awburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
+   output wire [4-1:0]                  m_axi_awcache,
+   output wire [3-1:0]                  m_axi_awprot,
+   output wire [4-1:0]                  m_axi_awregion,
+   output wire [4-1:0]                  m_axi_awqos,
+   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
+   output wire                          m_axi_awvalid,
+   input  wire                          m_axi_awready,
+   
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,
+   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,
+   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
+   output wire                          m_axi_wlast,
+   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,
+   output wire                          m_axi_wvalid,
+   input  wire                          m_axi_wready,
+   
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     m_axi_bid,
+   input  wire [2-1:0]                  m_axi_bresp,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]  m_axi_buser,
+   input  wire                          m_axi_bvalid,
+   output wire                          m_axi_bready,
+   
+   // Master Interface Read Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
+   output wire [3-1:0]                  m_axi_arsize,
+   output wire [2-1:0]                  m_axi_arburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
+   output wire [4-1:0]                  m_axi_arcache,
+   output wire [3-1:0]                  m_axi_arprot,
+   output wire [4-1:0]                  m_axi_arregion,
+   output wire [4-1:0]                  m_axi_arqos,
+   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
+   output wire                          m_axi_arvalid,
+   input  wire                          m_axi_arready,
+   
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     m_axi_rid,
+   input  wire [C_AXI_DATA_WIDTH-1:0]   m_axi_rdata,
+   input  wire [2-1:0]                  m_axi_rresp,
+   input  wire                          m_axi_rlast,
+   input  wire [C_AXI_RUSER_WIDTH-1:0]  m_axi_ruser,
+   input  wire                          m_axi_rvalid,
+   output wire                          m_axi_rready);
+  
+  localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH;
+  localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH;
+  localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH;
+  localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH;
+  localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH;
+  
+  localparam         P_PRIM_FIFO_TYPE = ""512x72"" ;
+  localparam integer P_AXI4 = 0;
+  localparam integer P_AXI3 = 1;
+  localparam integer P_AXILITE = 2;
+  localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1;
+  localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1;
+  
+  // Ceiling of log2(x)
+  function integer f_ceil_log2
+    (
+     input integer x
+     );
+    integer acc;
+    begin
+      acc=0;
+      while ((2**acc) < x)
+        acc = acc + 1;
+      f_ceil_log2 = acc;
+    end
+  endfunction
+
+  generate
+    if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass
+      assign m_axi_awid     = s_axi_awid;
+      assign m_axi_awaddr   = s_axi_awaddr;
+      assign m_axi_awlen    = s_axi_awlen;
+      assign m_axi_awsize   = s_axi_awsize;
+      assign m_axi_awburst  = s_axi_awburst;
+      assign m_axi_awlock   = s_axi_awlock;
+      assign m_axi_awcache  = s_axi_awcache;
+      assign m_axi_awprot   = s_axi_awprot;
+      assign m_axi_awregion = s_axi_awregion;
+      assign m_axi_awqos    = s_axi_awqos;
+      assign m_axi_awuser   = s_axi_awuser;
+      assign m_axi_awvalid  = s_axi_awvalid;
+      assign s_axi_awready  = m_axi_awready;
+      
+      assign m_axi_wid      = s_axi_wid;
+      assign m_axi_wdata    = s_axi_wdata;
+      assign m_axi_wstrb    = s_axi_wstrb;
+      assign m_axi_wlast    = s_axi_wlast;
+      assign m_axi_wuser    = s_axi_wuser;
+      assign m_axi_wvalid   = s_axi_wvalid;
+      assign s_axi_wready   = m_axi_wready;
+    
+      assign s_axi_bid      = m_axi_bid;
+      assign s_axi_bresp    = m_axi_bresp;
+      assign s_axi_buser    = m_axi_buser;
+      assign s_axi_bvalid   = m_axi_bvalid;
+      assign m_axi_bready   = s_axi_bready;
+    
+      assign m_axi_arid     = s_axi_arid;
+      assign m_axi_araddr   = s_axi_araddr;
+      assign m_axi_arlen    = s_axi_arlen;
+      assign m_axi_arsize   = s_axi_arsize;
+      assign m_axi_arburst  = s_axi_arburst;
+      assign m_axi_arlock   = s_axi_arlock;
+      assign m_axi_arcache  = s_axi_arcache;
+      assign m_axi_arprot   = s_axi_arprot;
+      assign m_axi_arregion = s_axi_arregion;
+      assign m_axi_arqos    = s_axi_arqos;
+      assign m_axi_aruser   = s_axi_aruser;
+      assign m_axi_arvalid  = s_axi_arvalid;
+      assign s_axi_arready  = m_axi_arready;
+  
+      assign s_axi_rid      = m_axi_rid;
+      assign s_axi_rdata    = m_axi_rdata;
+      assign s_axi_rresp    = m_axi_rresp;
+      assign s_axi_rlast    = m_axi_rlast;
+      assign s_axi_ruser    = m_axi_ruser;
+      assign s_axi_rvalid   = m_axi_rvalid;
+      assign m_axi_rready   = s_axi_rready;
+      
+    end else begin : gen_fifo
+      
+      wire [4-1:0]                  s_axi_awregion_i;
+      wire [4-1:0]                  s_axi_arregion_i;
+      wire [4-1:0]                  m_axi_awregion_i;
+      wire [4-1:0]                  m_axi_arregion_i;
+      wire [C_AXI_ID_WIDTH-1:0]     s_axi_wid_i;
+      wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid_i;
+      
+      assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4\'b0 : s_axi_awregion;
+      assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4\'b0 : s_axi_arregion;
+      assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4\'b0 : m_axi_awregion_i;
+      assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4\'b0 : m_axi_arregion_i;
+      assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1\'b0}};
+      assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1\'b0}};
+
+
+      fifo_generator_v13_1_3 #(
+          .C_INTERFACE_TYPE(2),
+          .C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3),
+          .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
+          .C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
+          .C_HAS_AXI_ID(1),
+          .C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),
+          .C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),
+          .C_HAS_AXI_ARUSER(1),
+          .C_HAS_AXI_AWUSER(1),
+          .C_HAS_AXI_BUSER(1),
+          .C_HAS_AXI_RUSER(1),
+          .C_HAS_AXI_WUSER(1),
+          .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
+          .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),
+          .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),
+          .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),
+          .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),
+          .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),
+          .C_DIN_WIDTH_RACH(P_WIDTH_RACH),
+          .C_DIN_WIDTH_RDCH(P_WIDTH_RDCH),
+          .C_DIN_WIDTH_WACH(P_WIDTH_WACH),
+          .C_DIN_WIDTH_WDCH(P_WIDTH_WDCH),
+          .C_DIN_WIDTH_WRCH(P_WIDTH_WDCH),
+          .C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2),
+          .C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2),
+          .C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2),
+          .C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2),
+          .C_WRCH_TYPE(2),
+          .C_COMMON_CLOCK(1),
+          .C_ADD_NGC_CONSTRAINT(0),
+          .C_APPLICATION_TYPE_AXIS(0),
+          .C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0),
+          .C_APPLICATION_TYPE_RDCH(0),
+          .C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0),
+          .C_APPLICATION_TYPE_WDCH(0),
+          .C_APPLICATION_TYPE_WRCH(0),
+          .C_AXIS_TDATA_WIDTH(64),
+          .C_AXIS_TDEST_WIDTH(4),
+          .C_AXIS_TID_WIDTH(8),
+          .C_AXIS_TKEEP_WIDTH(4),
+          .C_AXIS_TSTRB_WIDTH(4),
+          .C_AXIS_TUSER_WIDTH(4),
+          .C_AXIS_TYPE(0),
+          .C_COUNT_TYPE(0),
+          .C_DATA_COUNT_WIDTH(10),
+          .C_DEFAULT_VALUE(""BlankString""),
+          .C_DIN_WIDTH(18),
+          .C_DIN_WIDTH_AXIS(1),
+          .C_DOUT_RST_VAL(""0""),
+          .C_DOUT_WIDTH(18),
+          .C_ENABLE_RLOCS(0),
+          .C_ENABLE_RST_SYNC(1),
+          .C_ERROR_INJECTION_TYPE(0),
+          .C_ERROR_INJECTION_TYPE_AXIS(0),
+          .C_ERROR_INJECTION_TYPE_RACH(0),
+          .C_ERROR_INJECTION_TYPE_RDCH(0),
+          .C_ERROR_INJECTION_TYPE_WACH(0),
+          .C_ERROR_INJECTION_TYPE_WDCH(0),
+          .C_ERROR_INJECTION_TYPE_WRCH(0),
+          .C_FAMILY(C_FAMILY),
+          .C_FULL_FLAGS_RST_VAL(1),
+          .C_HAS_ALMOST_EMPTY(0),
+          .C_HAS_ALMOST_FULL(0),
+          .C_HAS_AXI_RD_CHANNEL(1),
+          .C_HAS_AXI_WR_CHANNEL(1),
+          .C_HAS_AXIS_TDATA(0),
+          .C_HAS_AXIS_TDEST(0),
+          .C_HAS_AXIS_TID(0),
+          .C_HAS_AXIS_TKEEP(0),
+          .C_HAS_AXIS_TLAST(0),
+          .C_HAS_AXIS_TREADY(1),
+          .C_HAS_AXIS_TSTRB(0),
+          .C_HAS_AXIS_TUSER(0),
+          .C_HAS_BACKUP(0),
+          .C_HAS_DATA_COUNT(0),
+          .C_HAS_DATA_COUNTS_AXIS(0),
+          .C_HAS_DATA_COUNTS_RACH(0),
+          .C_HAS_DATA_COUNTS_RDCH(0),
+          .C_HAS_DATA_COUNTS_WACH(0),
+          .C_HAS_DATA_COUNTS_WDCH(0),
+          .C_HAS_DATA_COUNTS_WRCH(0),
+          .C_HAS_INT_CLK(0),
+          .C_HAS_MASTER_CE(0),
+          .C_HAS_MEMINIT_FILE(0),
+          .C_HAS_OVERFLOW(0),
+          .C_HAS_PROG_FLAGS_AXIS(0),
+          .C_HAS_PROG_FLAGS_RACH(0),
+          .C_HAS_PROG_FLAGS_RDCH(0),
+          .C_HAS_PROG_FLAGS_WACH(0),
+          .C_HAS_PROG_FLAGS_WDCH(0),
+          .C_HAS_PROG_FLAGS_WRCH(0),
+          .C_HAS_RD_DATA_COUNT(0),
+          .C_HAS_RD_RST(0),
+          .C_HAS_RST(1),
+          .C_HAS_SLAVE_CE(0),
+          .C_HAS_SRST(0),
+          .C_HAS_UNDERFLOW(0),
+          .C_HAS_VALID(0),
+          .C_HAS_WR_ACK(0),
+          .C_HAS_WR_DATA_COUNT(0),
+          .C_HAS_WR_RST(0),
+          .C_IMPLEMENTATION_TYPE(0),
+          .C_IMPLEMENTATION_TYPE_AXIS(1),
+          .C_IMPLEMENTATION_TYPE_RACH(2),
+          .C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == ""bram"") ? 1 : 2),
+          .C_IMPLEMENTATION_TYPE_WACH(2),
+          .C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == ""bram"") ? 1 : 2),
+          .C_IMPLEMENTATION_TYPE_WRCH(2),
+          .C_INIT_WR_PNTR_VAL(0),
+          .C_MEMORY_TYPE(1),
+          .C_MIF_FILE_NAME(""BlankString""),
+          .C_MSGON_VAL(1),
+          .C_OPTIMIZATION_MODE(0),
+          .C_OVERFLOW_LOW(0),
+          .C_PRELOAD_LATENCY(1),
+          .C_PRELOAD_REGS(0),
+          .C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE),
+          .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
+          .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30),
+          .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510),
+          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
+          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510),
+          .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
+          .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
+          .C_PROG_EMPTY_TYPE(0),
+          .C_PROG_EMPTY_TYPE_AXIS(5),
+          .C_PROG_EMPTY_TYPE_RACH(5),
+          .C_PROG_EMPTY_TYPE_RDCH(5),
+          .C_PROG_EMPTY_TYPE_WACH(5),
+          .C_PROG_EMPTY_TYPE_WDCH(5),
+          .C_PROG_EMPTY_TYPE_WRCH(5),
+          .C_PROG_FULL_THRESH_ASSERT_VAL(1022),
+          .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+          .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31),
+          .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511),
+          .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
+          .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511),
+          .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
+          .C_PROG_FULL_THRESH_NEGATE_VAL(1021),
+          .C_PROG_FULL_TYPE(0),
+          .C_PROG_FULL_TYPE_AXIS(5),
+          .C_PROG_FULL_TYPE_RACH(5),
+          .C_PROG_FULL_TYPE_RDCH(5),
+          .C_PROG_FULL_TYPE_WACH(5),
+          .C_PROG_FULL_TYPE_WDCH(5),
+          .C_PROG_FULL_TYPE_WRCH(5),
+          .C_RD_DATA_COUNT_WIDTH(10),
+          .C_RD_DEPTH(1024),
+          .C_RD_FREQ(1),
+          .C_RD_PNTR_WIDTH(10),
+          .C_REG_SLICE_MODE_AXIS(0),
+          .C_REG_SLICE_MODE_RACH(0),
+          .C_REG_SLICE_MODE_RDCH(0),
+          .C_REG_SLICE_MODE_WACH(0),
+          .C_REG_SLICE_MODE_WDCH(0),
+          .C_REG_SLICE_MODE_WRCH(0),
+          .C_UNDERFLOW_LOW(0),
+          .C_USE_COMMON_OVERFLOW(0),
+          .C_USE_COMMON_UNDERFLOW(0),
+          .C_USE_DEFAULT_SETTINGS(0),
+          .C_USE_DOUT_RST(1),
+          .C_USE_ECC(0),
+          .C_USE_ECC_AXIS(0),
+          .C_USE_ECC_RACH(0),
+          .C_USE_ECC_RDCH(0),
+          .C_USE_ECC_WACH(0),
+          .C_USE_ECC_WDCH(0),
+          .C_USE_ECC_WRCH(0),
+          .C_USE_EMBEDDED_REG(0),
+          .C_USE_FIFO16_FLAGS(0),
+          .C_USE_FWFT_DATA_COUNT(0),
+          .C_VALID_LOW(0),
+          .C_WR_ACK_LOW(0),
+          .C_WR_DATA_COUNT_WIDTH(10),
+          .C_WR_DEPTH(1024),
+          .C_WR_DEPTH_AXIS(1024),
+          .C_WR_DEPTH_RACH(32),
+          .C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH),
+          .C_WR_DEPTH_WACH(32),
+          .C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH),
+          .C_WR_DEPTH_WRCH(16),
+          .C_WR_FREQ(1),
+          .C_WR_PNTR_WIDTH(10),
+          .C_WR_PNTR_WIDTH_AXIS(10),
+          .C_WR_PNTR_WIDTH_RACH(5),
+          .C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1),
+          .C_WR_PNTR_WIDTH_WACH(5),
+          .C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1),
+          .C_WR_PNTR_WIDTH_WRCH(4),
+          .C_WR_RESPONSE_LATENCY(1)
+        )
+        fifo_gen_inst (
+          .s_aclk(aclk),
+          .s_aresetn(aresetn),
+          .s_axi_awid(s_axi_awid),
+          .s_axi_awaddr(s_axi_awaddr),
+          .s_axi_awlen(s_axi_awlen),
+          .s_axi_awsize(s_axi_awsize),
+          .s_axi_awburst(s_axi_awburst),
+          .s_axi_awlock(s_axi_awlock),
+          .s_axi_awcache(s_axi_awcache),
+          .s_axi_awprot(s_axi_awprot),
+          .s_axi_awqos(s_axi_awqos),
+          .s_axi_awregion(s_axi_awregion_i),
+          .s_axi_awuser(s_axi_awuser),
+          .s_axi_awvalid(s_axi_awvalid),
+          .s_axi_awready(s_axi_awready),
+          .s_axi_wid(s_axi_wid_i),
+          .s_axi_wdata(s_axi_wdata),
+          .s_axi_wstrb(s_axi_wstrb),
+          .s_axi_wlast(s_axi_wlast),
+          .s_axi_wvalid(s_axi_wvalid),
+          .s_axi_wready(s_axi_wready),
+          .s_axi_bid(s_axi_bid),
+          .s_axi_bresp(s_axi_bresp),
+          .s_axi_bvalid(s_axi_bvalid),
+          .s_axi_bready(s_axi_bready),
+          .m_axi_awid(m_axi_awid),
+          .m_axi_awaddr(m_axi_awaddr),
+          .m_axi_awlen(m_axi_awlen),
+          .m_axi_awsize(m_axi_awsize),
+          .m_axi_awburst(m_axi_awburst),
+          .m_axi_awlock(m_axi_awlock),
+          .m_axi_awcache(m_axi_awcache),
+          .m_axi_awprot(m_axi_awprot),
+          .m_axi_awqos(m_axi_awqos),
+          .m_axi_awregion(m_axi_awregion_i),
+          .m_axi_awuser(m_axi_awuser),
+          .m_axi_awvalid(m_axi_awvalid),
+          .m_axi_awready(m_axi_awready),
+          .m_axi_wid(m_axi_wid_i),
+          .m_axi_wdata(m_axi_wdata),
+          .m_axi_wstrb(m_axi_wstrb),
+          .m_axi_wlast(m_axi_wlast),
+          .m_axi_wvalid(m_axi_wvalid),
+          .m_axi_wready(m_axi_wready),
+          .m_axi_bid(m_axi_bid),
+          .m_axi_bresp(m_axi_bresp),
+          .m_axi_bvalid(m_axi_bvalid),
+          .m_axi_bready(m_axi_bready),
+          .s_axi_arid(s_axi_arid),
+          .s_axi_araddr(s_axi_araddr),
+          .s_axi_arlen(s_axi_arlen),
+          .s_axi_arsize(s_axi_arsize),
+          .s_axi_arburst(s_axi_arburst),
+          .s_axi_arlock(s_axi_arlock),
+          .s_axi_arcache(s_axi_arcache),
+          .s_axi_arprot(s_axi_arprot),
+          .s_axi_arqos(s_axi_arqos),
+          .s_axi_arregion(s_axi_arregion_i),
+          .s_axi_arvalid(s_axi_arvalid),
+          .s_axi_arready(s_axi_arready),
+          .s_axi_rid(s_axi_rid),
+          .s_axi_rdata(s_axi_rdata),
+          .s_axi_rresp(s_axi_rresp),
+          .s_axi_rlast(s_axi_rlast),
+          .s_axi_rvalid(s_axi_rvalid),
+          .s_axi_rready(s_axi_rready),
+          .m_axi_arid(m_axi_arid),
+          .m_axi_araddr(m_axi_araddr),
+          .m_axi_arlen(m_axi_arlen),
+          .m_axi_arsize(m_axi_arsize),
+          .m_axi_arburst(m_axi_arburst),
+          .m_axi_arlock(m_axi_arlock),
+          .m_axi_arcache(m_axi_arcache),
+          .m_axi_arprot(m_axi_arprot),
+          .m_axi_arqos(m_axi_arqos),
+          .m_axi_arregion(m_axi_arregion_i),
+          .m_axi_arvalid(m_axi_arvalid),
+          .m_axi_arready(m_axi_arready),
+          .m_axi_rid(m_axi_rid),
+          .m_axi_rdata(m_axi_rdata),
+          .m_axi_rresp(m_axi_rresp),
+          .m_axi_rlast(m_axi_rlast),
+          .m_axi_rvalid(m_axi_rvalid),
+          .m_axi_rready(m_axi_rready),
+          .m_aclk(aclk),
+          .m_aclk_en(1\'b1),
+          .s_aclk_en(1\'b1),
+          .s_axi_wuser(s_axi_wuser),
+          .s_axi_buser(s_axi_buser),
+          .m_axi_wuser(m_axi_wuser),
+          .m_axi_buser(m_axi_buser),
+          .s_axi_aruser(s_axi_aruser),
+          .s_axi_ruser(s_axi_ruser),
+          .m_axi_aruser(m_axi_aruser),
+          .m_axi_ruser(m_axi_ruser),
+          .almost_empty(),
+          .almost_full(),
+          .axis_data_count(),
+          .axis_dbiterr(),
+          .axis_injectdbiterr(1\'b0),
+          .axis_injectsbiterr(1\'b0),
+          .axis_overflow(),
+          .axis_prog_empty(),
+          .axis_prog_empty_thresh(10\'b0),
+          .axis_prog_full(),
+          .axis_prog_full_thresh(10\'b0),
+          .axis_rd_data_count(),
+          .axis_sbiterr(),
+          .axis_underflow(),
+          .axis_wr_data_count(),
+          .axi_ar_data_count(),
+          .axi_ar_dbiterr(),
+          .axi_ar_injectdbiterr(1\'b0),
+          .axi_ar_injectsbiterr(1\'b0),
+          .axi_ar_overflow(),
+          .axi_ar_prog_empty(),
+          .axi_ar_prog_empty_thresh(5\'b0),
+          .axi_ar_prog_full(),
+          .axi_ar_prog_full_thresh(5\'b0),
+          .axi_ar_rd_data_count(),
+          .axi_ar_sbiterr(),
+          .axi_ar_underflow(),
+          .axi_ar_wr_data_count(),
+          .axi_aw_data_count(),
+          .axi_aw_dbiterr(),
+          .axi_aw_injectdbiterr(1\'b0),
+          .axi_aw_injectsbiterr(1\'b0),
+          .axi_aw_overflow(),
+          .axi_aw_prog_empty(),
+          .axi_aw_prog_empty_thresh(5\'b0),
+          .axi_aw_prog_full(),
+          .axi_aw_prog_full_thresh(5\'b0),
+          .axi_aw_rd_data_count(),
+          .axi_aw_sbiterr(),
+          .axi_aw_underflow(),
+          .axi_aw_wr_data_count(),
+          .axi_b_data_count(),
+          .axi_b_dbiterr(),
+          .axi_b_injectdbiterr(1\'b0),
+          .axi_b_injectsbiterr(1\'b0),
+          .axi_b_overflow(),
+          .axi_b_prog_empty(),
+          .axi_b_prog_empty_thresh(4\'b0),
+          .axi_b_prog_full(),
+          .axi_b_prog_full_thresh(4\'b0),
+          .axi_b_rd_data_count(),
+          .axi_b_sbiterr(),
+          .axi_b_underflow(),
+          .axi_b_wr_data_count(),
+          .axi_r_data_count(),
+          .axi_r_dbiterr(),
+          .axi_r_injectdbiterr(1\'b0),
+          .axi_r_injectsbiterr(1\'b0),
+          .axi_r_overflow(),
+          .axi_r_prog_empty(),
+          .axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1\'b0}}),
+          .axi_r_prog_full(),
+          .axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1\'b0}}),
+          .axi_r_rd_data_count(),
+          .axi_r_sbiterr(),
+          .axi_r_underflow(),
+          .axi_r_wr_data_count(),
+          .axi_w_data_count(),
+          .axi_w_dbiterr(),
+          .axi_w_injectdbiterr(1\'b0),
+          .axi_w_injectsbiterr(1\'b0),
+          .axi_w_overflow(),
+          .axi_w_prog_empty(),
+          .axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1\'b0}}),
+          .axi_w_prog_full(),
+          .axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1\'b0}}),
+          .axi_w_rd_data_count(),
+          .axi_w_sbiterr(),
+          .axi_w_underflow(),
+          .axi_w_wr_data_count(),
+          .backup(1\'b0),
+          .backup_marker(1\'b0),
+          .clk(1\'b0),
+          .data_count(),
+          .dbiterr(),
+          .din(18\'b0),
+          .dout(),
+          .empty(),
+          .full(),
+          .injectdbiterr(1\'b0),
+          .injectsbiterr(1\'b0),
+          .int_clk(1\'b0),
+          .m_axis_tdata(),
+          .m_axis_tdest(),
+          .m_axis_tid(),
+          .m_axis_tkeep(),
+          .m_axis_tlast(),
+          .m_axis_tready(1\'b0),
+          .m_axis_tstrb(),
+          .m_axis_tuser(),
+          .m_axis_tvalid(),
+          .overflow(),
+          .prog_empty(),
+          .prog_empty_thresh(10\'b0),
+          .prog_empty_thresh_assert(10\'b0),
+          .prog_empty_thresh_negate(10\'b0),
+          .prog_full(),
+          .prog_full_thresh(10\'b0),
+          .prog_full_thresh_assert(10\'b0),
+          .prog_full_thresh_negate(10\'b0),
+          .rd_clk(1\'b0),
+          .rd_data_count(),
+          .rd_en(1\'b0),
+          .rd_rst(1\'b0),
+          .rst(1\'b0),
+          .sbiterr(),
+          .srst(1\'b0),
+          .s_axis_tdata(64\'b0),
+          .s_axis_tdest(4\'b0),
+          .s_axis_tid(8\'b0),
+          .s_axis_tkeep(4\'b0),
+          .s_axis_tlast(1\'b0),
+          .s_axis_tready(),
+          .s_axis_tstrb(4\'b0),
+          .s_axis_tuser(4\'b0),
+          .s_axis_tvalid(1\'b0),
+          .underflow(),
+          .valid(),
+          .wr_ack(),
+          .wr_clk(1\'b0),
+          .wr_data_count(),
+          .wr_en(1\'b0),
+          .wr_rst(1\'b0),
+          .wr_rst_busy(),
+          .rd_rst_busy(),
+          .sleep(1\'b0)
+        );
+    end
+  endgenerate
+endmodule
+
+
+
+"
+"// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+//   Generic single-channel AXI pipeline register on forward and/or reverse signal path
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axic_register_slice
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_register_slice_v2_1_11_srl_rtl #
+  (
+   parameter         C_A_WIDTH = 2          // Address Width (>= 1)
+   )
+  (
+   input  wire                 clk, // Clock
+   input  wire [C_A_WIDTH-1:0] a,   // Address
+   input  wire                 ce,  // Clock Enable
+   input  wire                 d,   // Input Data
+   output wire                 q    // Output Data
+   );
+
+  localparam integer P_SRLDEPTH = 2**C_A_WIDTH;
+  
+    reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1\'b0}};
+    always @(posedge clk)
+      if (ce)
+        shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d};
+    assign q = shift_reg[a];
+
+endmodule
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_register_slice_v2_1_11_axic_register_slice #
+  (
+   parameter C_FAMILY     = ""virtex6"",
+   parameter C_DATA_WIDTH = 32,
+   parameter C_REG_CONFIG = 32\'h00000000
+   // C_REG_CONFIG:
+   //   0 => BYPASS    = The channel is just wired through the module.
+   //   1 => FWD_REV   = Both FWD and REV (fully-registered)
+   //   2 => FWD       = The master VALID and payload signals are registrated. 
+   //   3 => REV       = The slave ready signal is registrated
+   //   4 => RESERVED (all outputs driven to 0).
+   //   5 => RESERVED (all outputs driven to 0).
+   //   6 => INPUTS    = Slave and Master side inputs are registrated.
+   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)
+   )
+  (
+   // System Signals
+   input wire ACLK,
+   input wire ARESET,
+
+   // Slave side
+   input  wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
+   input  wire S_VALID,
+   output wire S_READY,
+
+   // Master side
+   output  wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
+   output wire M_VALID,
+   input  wire M_READY
+   );
+
+  (* use_clock_enable = ""yes"" *)
+
+  generate
+  ////////////////////////////////////////////////////////////////////
+  //
+  // C_REG_CONFIG = 0
+  // Bypass mode
+  //
+  ////////////////////////////////////////////////////////////////////
+    if (C_REG_CONFIG == 32\'h00000000) begin
+      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
+      assign M_VALID        = S_VALID;
+      assign S_READY        = M_READY;      
+    end
+    
+  ////////////////////////////////////////////////////////////////////
+  //
+  // C_REG_CONFIG = 9
+  // Source (SI) interface completely registered
+  //
+  ////////////////////////////////////////////////////////////////////
+      
+    else if (C_REG_CONFIG == 32\'h00000009) begin
+      reg [C_DATA_WIDTH-1:0] s_payload_d;
+      wire [C_DATA_WIDTH-1:0] srl_out;
+      reg s_ready_i;
+      reg m_valid_i;
+      reg payld_sel;
+      reg push;
+      reg pop;
+      wire s_handshake_d;
+      (* max_fanout = 66 *) reg s_valid_d;
+      (* max_fanout = 66 *) reg s_ready_d = 1\'b0;
+      (* max_fanout = 66 *) reg s_ready_reg = 1\'b0;
+      (* max_fanout = 66 *) reg [2:0] fifoaddr = 3\'b110;
+      
+      reg areset_d = 1\'b0;
+      always @(posedge ACLK) begin
+        areset_d <= ARESET;
+      end
+      
+      assign s_handshake_d = s_valid_d & s_ready_d;
+
+      always @ * begin
+        case (fifoaddr)
+          3\'b111: begin  // EMPTY: No payload in SRL; pre-assert m_ready
+            s_ready_i = 1\'b1;
+            payld_sel = 1\'b0;
+            pop = 1\'b0;
+            case ({s_handshake_d, M_READY}) 
+              2\'b00, 2\'b01: begin  // Idle
+                m_valid_i = 1\'b0;
+                push = 1\'b0;
+              end
+              2\'b10: begin  // Payload received
+                m_valid_i = 1\'b1;
+                push = 1\'b1;
+              end
+              2\'b11: begin  // Payload received and read out combinatorially
+                m_valid_i = 1\'b1;
+                push = 1\'b0;
+              end
+            endcase
+          end
+
+          3\'b000: begin  // 1 payload item in SRL
+            m_valid_i = 1\'b1;
+            payld_sel = 1\'b1;
+            case ({s_handshake_d, M_READY}) 
+              2\'b00: begin  // Idle
+                s_ready_i = 1\'b1;
+                push = 1\'b0;
+                pop = 1\'b0;
+              end
+              2\'b01: begin  // Pop
+                s_ready_i = 1\'b1;
+                push = 1\'b0;
+                pop = 1\'b1;
+              end
+              2\'b10: begin  // Push
+                s_ready_i = 1\'b0;  // Doesn\'t de-assert on SI until next cycle
+                push = 1\'b1;
+                pop = 1\'b0;
+              end
+              2\'b11: begin  // Push and Pop
+                s_ready_i = 1\'b1;
+                push = 1\'b1;
+                pop = 1\'b1;
+              end
+            endcase
+          end
+
+          3\'b001: begin  // 2 payload items in SRL
+            m_valid_i = 1\'b1;
+            payld_sel = 1\'b1;
+            case ({s_handshake_d, M_READY}) 
+              2\'b00: begin  // Idle
+                s_ready_i = 1\'b0;
+                push = 1\'b0;
+                pop = 1\'b0;
+              end
+              2\'b01: begin  // Pop
+                s_ready_i = 1\'b1;
+                push = 1\'b0;
+                pop = 1\'b1;
+              end
+              2\'b10: begin  // Push (Handshake completes on SI while pushing 2nd item into SRL)
+                s_ready_i = 1\'b0;
+                push = 1\'b1;
+                pop = 1\'b0;
+              end
+              2\'b11: begin  // Push and Pop
+                s_ready_i = 1\'b0;
+                push = 1\'b1;
+                pop = 1\'b1;
+              end
+            endcase
+          end
+
+          3\'b010: begin  // 3 payload items in SRL
+            m_valid_i = 1\'b1;
+            s_ready_i = 1\'b0;
+            payld_sel = 1\'b1;
+            push = 1\'b0;
+            if (M_READY) begin  // Handshake cannot complete on SI
+              pop = 1\'b1;
+            end else begin
+              pop = 1\'b0;
+            end
+          end
+
+          default: begin  // RESET state (fifoaddr = 3\'b110)
+            m_valid_i = 1\'b0;
+            s_ready_i = 1\'b0;
+            payld_sel = 1\'b0;
+            push = 1\'b1;  // Advance to Empty state
+            pop = 1\'b0;
+          end  // RESET
+        endcase
+      end
+
+      always @(posedge ACLK) begin
+        if (areset_d) begin
+          fifoaddr <= 3\'b110;
+          s_ready_reg <= 1\'b0;
+          s_ready_d <= 1\'b0;
+        end else begin
+          s_ready_reg <= s_ready_i;
+          s_ready_d <= s_ready_reg;
+          if (push & ~pop) begin
+            fifoaddr <= fifoaddr + 1;
+          end else if (~push & pop) begin
+            fifoaddr <= fifoaddr - 1;
+          end
+        end
+      end
+
+      always @(posedge ACLK) begin
+        s_valid_d <= S_VALID;
+        s_payload_d <= S_PAYLOAD_DATA;
+      end
+
+      assign S_READY = s_ready_reg;
+      assign M_VALID = m_valid_i;
+      assign M_PAYLOAD_DATA = payld_sel ? srl_out : s_payload_d;
+
+    //---------------------------------------------------------------------------
+    // Instantiate SRLs
+    //---------------------------------------------------------------------------
+      genvar i;
+      for (i=0;i<C_DATA_WIDTH;i=i+1) begin : gen_srls
+        axi_register_slice_v2_1_11_srl_rtl #
+          (
+           .C_A_WIDTH (2)
+          )
+          srl_nx1
+          (
+           .clk (ACLK),
+           .a   (fifoaddr[1:0]),
+           .ce  (push),
+           .d   (s_payload_d[i]),
+           .q   (srl_out[i])
+          );
+      end      
+    end 
+        
+        
+  ////////////////////////////////////////////////////////////////////
+  //
+  // C_REG_CONFIG = 1 (or 8)
+  // Both FWD and REV mode
+  //
+  ////////////////////////////////////////////////////////////////////
+    else if ((C_REG_CONFIG == 32\'h00000001) || (C_REG_CONFIG == 32\'h00000008)) begin
+      reg [C_DATA_WIDTH-1:0] m_payload_i;
+      reg [C_DATA_WIDTH-1:0] skid_buffer;
+      reg                    s_ready_i; 
+      reg                    m_valid_i;
+
+      assign S_READY = s_ready_i;
+      assign M_VALID = m_valid_i;
+      assign M_PAYLOAD_DATA = m_payload_i;
+
+      reg [1:0] aresetn_d = 2\'b00; // Reset delay shifter
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          aresetn_d <= 2\'b00;
+        end else begin
+          aresetn_d <= {aresetn_d[0], ~ARESET};
+        end
+      end
+      
+      always @(posedge ACLK) begin
+        if (~aresetn_d[0]) begin
+          s_ready_i <= 1\'b0;
+        end else begin
+          s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
+        end
+        
+        if (~aresetn_d[1]) begin
+          m_valid_i <= 1\'b0;
+        end else begin
+          m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
+        end
+        
+        if (M_READY | ~m_valid_i) begin
+          m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
+        end
+        
+        if (s_ready_i) begin
+          skid_buffer <= S_PAYLOAD_DATA;
+        end
+      end
+
+    end // if (C_REG_CONFIG == 1)
+    
+    
+  ////////////////////////////////////////////////////////////////////
+  //
+  // C_REG_CONFIG = 2
+  // Only FWD mode
+  //
+  ////////////////////////////////////////////////////////////////////
+    else if (C_REG_CONFIG == 32\'h00000002)
+    begin
+      reg [C_DATA_WIDTH-1:0] storage_data;
+      wire                   s_ready_i; //local signal of output
+      reg                    m_valid_i; //local signal of output
+
+      // assign local signal to its output signal
+      assign S_READY = s_ready_i;
+      assign M_VALID = m_valid_i;
+
+      reg aresetn_d = 1\'b0; // Reset delay register
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          aresetn_d <= 1\'b0;
+        end else begin
+          aresetn_d <= ~ARESET;
+        end
+      end
+      
+      // Save payload data whenever we have a transaction on the slave side
+      always @(posedge ACLK) 
+      begin
+        if (S_VALID & s_ready_i)
+          storage_data <= S_PAYLOAD_DATA;
+      end
+
+      assign M_PAYLOAD_DATA = storage_data;
+      
+      // M_Valid set to high when we have a completed transfer on slave side
+      // Is removed on a M_READY except if we have a new transfer on the slave side
+      always @(posedge ACLK) 
+      begin
+        if (~aresetn_d) 
+          m_valid_i <= 1\'b0;
+        else
+          if (S_VALID) // Always set m_valid_i when slave side is valid
+            m_valid_i <= 1\'b1;
+          else
+            if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
+              m_valid_i <= 1\'b0;
+      end // always @ (posedge ACLK)
+      
+      // Slave Ready is either when Master side drives M_Ready or we have space in our storage data
+      assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
+
+    end // if (C_REG_CONFIG == 2)
+  ////////////////////////////////////////////////////////////////////
+  //
+  // C_REG_CONFIG = 3
+  // Only REV mode
+  //
+  ////////////////////////////////////////////////////////////////////
+    else if (C_REG_CONFIG == 32\'h00000003)
+    begin
+      reg [C_DATA_WIDTH-1:0] storage_data;
+      reg                    s_ready_i; //local signal of output
+      reg                    has_valid_storage_i;
+      reg                    has_valid_storage;
+
+      reg [1:0] aresetn_d = 2\'b00; // Reset delay register
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          aresetn_d <= 2\'b00;
+        end else begin
+          aresetn_d <= {aresetn_d[0], ~ARESET};
+        end
+      end
+      
+      // Save payload data whenever we have a transaction on the slave side
+      always @(posedge ACLK) 
+      begin
+        if (S_VALID & s_ready_i)
+          storage_data <= S_PAYLOAD_DATA;
+      end
+
+      assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
+
+      // Need to determine when we need to save a payload
+      // Need a combinatorial signals since it will also effect S_READY
+      always @ *
+      begin
+        // Set the value if we have a slave transaction but master side is not ready
+        if (S_VALID & s_ready_i & ~M_READY)
+          has_valid_storage_i = 1\'b1;
+        
+        // Clear the value if it\'s set and Master side completes the transaction but we don\'t have a new slave side 
+        // transaction 
+        else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
+          has_valid_storage_i = 1\'b0;
+        else
+          has_valid_storage_i = has_valid_storage;
+      end // always @ *
+
+      always @(posedge ACLK) 
+      begin
+        if (~aresetn_d[0]) 
+          has_valid_storage <= 1\'b0;
+        else
+          has_valid_storage <= has_valid_storage_i;
+      end
+
+      // S_READY is either clocked M_READY or that we have room in local storage
+      always @(posedge ACLK) 
+      begin
+        if (~aresetn_d[0]) 
+          s_ready_i <= 1\'b0;
+        else
+          s_ready_i <= M_READY | ~has_valid_storage_i;
+      end
+
+      // assign local signal to its output signal
+      assign S_READY = s_ready_i;
+
+      // M_READY is either combinatorial S_READY or that we have valid data in local storage
+      assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
+      
+    end // if (C_REG_CONFIG == 3)
+    
+  ////////////////////////////////////////////////////////////////////
+  //
+  // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
+  //
+  ////////////////////////////////////////////////////////////////////
+    else if ((C_REG_CONFIG == 32\'h00000004) || (C_REG_CONFIG == 32\'h00000005))
+    begin
+// synthesis translate_off
+      initial begin  
+        $display (""ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED."");
+      end
+// synthesis translate_on
+      assign M_PAYLOAD_DATA = 0;
+      assign M_VALID        = 1\'b0;
+      assign S_READY        = 1\'b0;    
+    end  
+
+  ////////////////////////////////////////////////////////////////////
+  //
+  // C_REG_CONFIG = 6
+  // INPUTS mode
+  //
+  ////////////////////////////////////////////////////////////////////
+    else if (C_REG_CONFIG == 32\'h00000006)
+    begin
+      reg [1:0] state;
+      reg [1:0] next_state;
+      localparam [1:0] 
+        ZERO = 2\'b00,
+        ONE  = 2\'b01,
+        TWO  = 2\'b11;
+
+      reg [C_DATA_WIDTH-1:0] storage_data1;
+      reg [C_DATA_WIDTH-1:0] storage_data2;
+      reg                    s_valid_d;
+      reg                    s_ready_d;
+      reg                    m_ready_d;
+      reg                    m_valid_d;
+      reg                    load_s2;
+      reg                    sel_s2;
+      wire                   new_access;
+      wire                   access_done;
+      wire                   s_ready_i; //local signal of output
+      reg                    s_ready_ii;
+      reg                    m_valid_i; //local signal of output
+      
+      reg [1:0] aresetn_d = 2\'b00; // Reset delay register
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          aresetn_d <= 2\'b00;
+        end else begin
+          aresetn_d <= {aresetn_d[0], ~ARESET};
+        end
+      end
+      
+      // assign local signal to its output signal
+      assign S_READY = s_ready_i;
+      assign M_VALID = m_valid_i;
+      assign s_ready_i = s_ready_ii & aresetn_d[1];
+
+      // Registrate input control signals
+      always @(posedge ACLK) 
+      begin
+        if (~aresetn_d[0]) begin          
+          s_valid_d <= 1\'b0;
+          s_ready_d <= 1\'b0;
+          m_ready_d <= 1\'b0;
+        end else begin
+          s_valid_d <= S_VALID;
+          s_ready_d <= s_ready_i;
+          m_ready_d <= M_READY;
+        end
+      end // always @ (posedge ACLK)
+
+      // Load storage1 with slave side payload data when slave side ready is high
+      always @(posedge ACLK) 
+      begin
+        if (s_ready_i)
+          storage_data1 <= S_PAYLOAD_DATA;          
+      end
+
+      // Load storage2 with storage data 
+      always @(posedge ACLK) 
+      begin
+        if (load_s2)
+          storage_data2 <= storage_data1;
+      end
+
+      always @(posedge ACLK) 
+      begin
+        if (~aresetn_d[0]) 
+          m_valid_d <= 1\'b0;
+        else 
+          m_valid_d <= m_valid_i;
+      end
+
+      // Local help signals
+      assign new_access  = s_ready_d & s_valid_d;
+      assign access_done = m_ready_d & m_valid_d;
+
+
+      // State Machine for handling output signals
+      always @*
+      begin
+        next_state = state; // Stay in the same state unless we need to move to another state
+        load_s2   = 0;
+        sel_s2    = 0;
+        m_valid_i = 0;
+        s_ready_ii = 0;
+        case (state)
+            // No transaction stored locally
+            ZERO: begin
+              load_s2   = 0;
+              sel_s2    = 0;
+              m_valid_i = 0;
+              s_ready_ii = 1;
+              if (new_access) begin
+                next_state = ONE; // Got one so move to ONE
+                load_s2   = 1;
+                m_valid_i = 0;
+              end
+              else begin
+                next_state = next_state;
+                load_s2   = load_s2;
+                m_valid_i = m_valid_i;
+              end
+
+            end // case: ZERO
+
+            // One transaction stored locally
+            ONE: begin
+              load_s2   = 0;
+              sel_s2    = 1;
+              m_valid_i = 1;
+              s_ready_ii = 1;
+              if (~new_access & access_done) begin
+                next_state = ZERO; // Read out one so move to ZERO
+                m_valid_i = 0;                      
+              end
+              else if (new_access & ~access_done) begin
+                next_state = TWO;  // Got another one so move to TWO
+                s_ready_ii = 0;
+              end
+              else if (new_access & access_done) begin
+                load_s2   = 1;
+                sel_s2    = 0;
+              end
+              else begin
+                load_s2   = load_s2;
+                sel_s2    = sel_s2;
+              end
+
+
+            end // case: ONE
+
+            // TWO transaction stored locally
+            TWO: begin
+              load_s2   = 0;
+              sel_s2    = 1;
+              m_valid_i = 1;
+              s_ready_ii = 0;
+              if (access_done) begin 
+                next_state = ONE; // Read out one so move to ONE
+                s_ready_ii  = 1;
+                load_s2    = 1;
+                sel_s2     = 0;
+              end
+              else begin
+                next_state = next_state;
+                s_ready_ii  = s_ready_ii;
+                load_s2    = load_s2;
+                sel_s2     = sel_s2;
+              end
+            end // case: TWO
+        endcase // case (state)
+      end // always @ *
+
+
+      // State Machine for handling output signals
+      always @(posedge ACLK) 
+      begin
+        if (~aresetn_d[0]) 
+          state <= ZERO;
+        else
+          state <= next_state; // Stay in the same state unless we need to move to another state
+      end
+      
+      // Master Payload mux
+      assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
+
+    end // if (C_REG_CONFIG == 6)
+  ////////////////////////////////////////////////////////////////////
+  //
+  // C_REG_CONFIG = 7
+  // Light-weight mode.
+  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+  // Operates same as 1-deep FIFO
+  //
+  ////////////////////////////////////////////////////////////////////
+    else if (C_REG_CONFIG == 32\'h00000007) begin
+      reg [C_DATA_WIDTH-1:0] m_payload_i;
+      reg                    s_ready_i; 
+      reg                    m_valid_i;
+
+      assign S_READY = s_ready_i;
+      assign M_VALID = m_valid_i;
+      assign M_PAYLOAD_DATA = m_payload_i;
+
+      reg [1:0] aresetn_d = 2\'b00; // Reset delay shifter
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          aresetn_d <= 2\'b00;
+        end else begin
+          aresetn_d <= {aresetn_d[0], ~ARESET};
+        end
+      end
+      
+      always @(posedge ACLK) begin
+        if (~aresetn_d[0]) begin
+          s_ready_i <= 1\'b0;
+        end else if (~aresetn_d[1]) begin
+          s_ready_i <= 1\'b1;
+        end else begin
+          s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
+        end
+        
+        if (~aresetn_d[1]) begin
+          m_valid_i <= 1\'b0;
+        end else begin
+          m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
+        end
+        
+        if (~m_valid_i) begin
+          m_payload_i <= S_PAYLOAD_DATA;
+        end
+      end
+      
+    end // if (C_REG_CONFIG == 7)
+    
+    else begin : default_case
+      // Passthrough
+      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
+      assign M_VALID        = S_VALID;
+      assign S_READY        = M_READY;      
+    end
+
+  endgenerate
+endmodule // reg_slice
+
+
+//  (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, ""Critical
+//  Applications""). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// AXI Register Slice
+//   Register selected channels on the forward and/or reverse signal paths.
+//   5-channel memory-mapped AXI4 interfaces.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axi_register_slice
+//      axic_register_slice
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_register_slice_v2_1_11_axi_register_slice #
+  (
+   parameter C_FAMILY                            = ""virtex6"",
+   parameter C_AXI_PROTOCOL                      = 0,
+   parameter integer C_AXI_ID_WIDTH              = 1,
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_DATA_WIDTH            = 32,
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
+   parameter integer C_AXI_AWUSER_WIDTH          = 1,
+   parameter integer C_AXI_ARUSER_WIDTH          = 1,
+   parameter integer C_AXI_WUSER_WIDTH           = 1,
+   parameter integer C_AXI_RUSER_WIDTH           = 1,
+   parameter integer C_AXI_BUSER_WIDTH           = 1,
+   // C_REG_CONFIG_*:
+   //   0 => BYPASS    = The channel is just wired through the module.
+   //   1 => FWD_REV   = Both FWD and REV (fully-registered)
+   //   2 => FWD       = The master VALID and payload signals are registrated. 
+   //   3 => REV       = The slave ready signal is registrated
+   //   4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
+   //   5 => SLAVE_RDY = All slave side signals and master READY are registrated.
+   //   6 => INPUTS    = Slave and Master side inputs are registrated.
+   //   7 => LIGHT_WT  = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+   //   9 => SI/MI_REG = Source side completely registered (including S_VALID input)
+   parameter integer C_REG_CONFIG_AW = 7,
+   parameter integer C_REG_CONFIG_W  = 1,
+   parameter integer C_REG_CONFIG_B  = 7,
+   parameter integer C_REG_CONFIG_AR = 7,
+   parameter integer C_REG_CONFIG_R  = 1
+   )
+  (
+   // System Signals
+   input wire aclk,
+   input wire aresetn,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,
+   input  wire [3-1:0]                  s_axi_awsize,
+   input  wire [2-1:0]                  s_axi_awburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,
+   input  wire [4-1:0]                  s_axi_awcache,
+   input  wire [3-1:0]                  s_axi_awprot,
+   input  wire [4-1:0]                  s_axi_awregion,
+   input  wire [4-1:0]                  s_axi_awqos,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
+   input  wire                          s_axi_awvalid,
+   output wire                          s_axi_awready,
+
+   // Slave Interface Write Data Ports
+   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,
+   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
+   input  wire                          s_axi_wlast,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,
+   input  wire                          s_axi_wvalid,
+   output wire                          s_axi_wready,
+
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,
+   output wire [2-1:0]                 s_axi_bresp,
+   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
+   output wire                         s_axi_bvalid,
+   input  wire                         s_axi_bready,
+
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,
+   input  wire [3-1:0]                  s_axi_arsize,
+   input  wire [2-1:0]                  s_axi_arburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,
+   input  wire [4-1:0]                  s_axi_arcache,
+   input  wire [3-1:0]                  s_axi_arprot,
+   input  wire [4-1:0]                  s_axi_arregion,
+   input  wire [4-1:0]                  s_axi_arqos,
+   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
+   input  wire                          s_axi_arvalid,
+   output wire                          s_axi_arready,
+
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,
+   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,
+   output wire [2-1:0]                 s_axi_rresp,
+   output wire                         s_axi_rlast,
+   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
+   output wire                         s_axi_rvalid,
+   input  wire                         s_axi_rready,
+   
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,
+   output wire [3-1:0]                  m_axi_awsize,
+   output wire [2-1:0]                  m_axi_awburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,
+   output wire [4-1:0]                  m_axi_awcache,
+   output wire [3-1:0]                  m_axi_awprot,
+   output wire [4-1:0]                  m_axi_awregion,
+   output wire [4-1:0]                  m_axi_awqos,
+   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
+   output wire                          m_axi_awvalid,
+   input  wire                          m_axi_awready,
+   
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,
+   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,
+   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
+   output wire                          m_axi_wlast,
+   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,
+   output wire                          m_axi_wvalid,
+   input  wire                          m_axi_wready,
+   
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,
+   input  wire [2-1:0]                 m_axi_bresp,
+   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
+   input  wire                         m_axi_bvalid,
+   output wire                         m_axi_bready,
+   
+   // Master Interface Read Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,
+   output wire [3-1:0]                  m_axi_arsize,
+   output wire [2-1:0]                  m_axi_arburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,
+   output wire [4-1:0]                  m_axi_arcache,
+   output wire [3-1:0]                  m_axi_arprot,
+   output wire [4-1:0]                  m_axi_arregion,
+   output wire [4-1:0]                  m_axi_arqos,
+   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
+   output wire                          m_axi_arvalid,
+   input  wire                          m_axi_arready,
+   
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,
+   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,
+   input  wire [2-1:0]                 m_axi_rresp,
+   input  wire                         m_axi_rlast,
+   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
+   input  wire                         m_axi_rvalid,
+   output wire                         m_axi_rready
+  );
+
+  wire reset;
+
+  localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;
+  `include ""axi_infrastructure_v1_1_0.vh""
+
+  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;
+  wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;
+  wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;
+  wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;
+  wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;
+  wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;
+  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;
+  wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;
+  wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;
+  wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;
+
+  assign reset = ~aresetn;
+
+  axi_infrastructure_v1_1_0_axi2vector #( 
+    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,
+    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,
+    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,
+    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,
+    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,
+    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
+    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,
+    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,
+    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,
+    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,
+    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,
+    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,
+    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,
+    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,
+    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,
+    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) 
+  )
+  axi_infrastructure_v1_1_0_axi2vector_0 ( 
+    .s_axi_awid      ( s_axi_awid      ) ,
+    .s_axi_awaddr    ( s_axi_awaddr    ) ,
+    .s_axi_awlen     ( s_axi_awlen     ) ,
+    .s_axi_awsize    ( s_axi_awsize    ) ,
+    .s_axi_awburst   ( s_axi_awburst   ) ,
+    .s_axi_awlock    ( s_axi_awlock    ) ,
+    .s_axi_awcache   ( s_axi_awcache   ) ,
+    .s_axi_awprot    ( s_axi_awprot    ) ,
+    .s_axi_awqos     ( s_axi_awqos     ) ,
+    .s_axi_awuser    ( s_axi_awuser    ) ,
+    .s_axi_awregion  ( s_axi_awregion  ) ,
+    .s_axi_wid       ( s_axi_wid       ) ,
+    .s_axi_wdata     ( s_axi_wdata     ) ,
+    .s_axi_wstrb     ( s_axi_wstrb     ) ,
+    .s_axi_wlast     ( s_axi_wlast     ) ,
+    .s_axi_wuser     ( s_axi_wuser     ) ,
+    .s_axi_bid       ( s_axi_bid       ) ,
+    .s_axi_bresp     ( s_axi_bresp     ) ,
+    .s_axi_buser     ( s_axi_buser     ) ,
+    .s_axi_arid      ( s_axi_arid      ) ,
+    .s_axi_araddr    ( s_axi_araddr    ) ,
+    .s_axi_arlen     ( s_axi_arlen     ) ,
+    .s_axi_arsize    ( s_axi_arsize    ) ,
+    .s_axi_arburst   ( s_axi_arburst   ) ,
+    .s_axi_arlock    ( s_axi_arlock    ) ,
+    .s_axi_arcache   ( s_axi_arcache   ) ,
+    .s_axi_arprot    ( s_axi_arprot    ) ,
+    .s_axi_arqos     ( s_axi_arqos     ) ,
+    .s_axi_aruser    ( s_axi_aruser    ) ,
+    .s_axi_arregion  ( s_axi_arregion  ) ,
+    .s_axi_rid       ( s_axi_rid       ) ,
+    .s_axi_rdata     ( s_axi_rdata     ) ,
+    .s_axi_rresp     ( s_axi_rresp     ) ,
+    .s_axi_rlast     ( s_axi_rlast     ) ,
+    .s_axi_ruser     ( s_axi_ruser     ) ,
+    .s_awpayload ( s_awpayload ) ,
+    .s_wpayload  ( s_wpayload  ) ,
+    .s_bpayload  ( s_bpayload  ) ,
+    .s_arpayload ( s_arpayload ) ,
+    .s_rpayload  ( s_rpayload  ) 
+  );
+    
+  axi_register_slice_v2_1_11_axic_register_slice # (
+    .C_FAMILY     ( C_FAMILY              ) ,
+    .C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
+    .C_REG_CONFIG ( C_REG_CONFIG_AW       ) 
+  )
+  aw_pipe (
+    // System Signals
+    .ACLK(aclk),
+    .ARESET(reset),
+
+    // Slave side
+    .S_PAYLOAD_DATA(s_awpayload),
+    .S_VALID(s_axi_awvalid),
+    .S_READY(s_axi_awready),
+
+    // Master side
+    .M_PAYLOAD_DATA(m_awpayload),
+    .M_VALID(m_axi_awvalid),
+    .M_READY(m_axi_awready)
+  );
+    
+  axi_register_slice_v2_1_11_axic_register_slice # (
+    .C_FAMILY     ( C_FAMILY             ) ,
+    .C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
+    .C_REG_CONFIG ( C_REG_CONFIG_W       ) 
+  )
+  w_pipe (
+    // System Signals
+    .ACLK(aclk),
+    .ARESET(reset),
+
+    // Slave side
+    .S_PAYLOAD_DATA(s_wpayload),
+    .S_VALID(s_axi_wvalid),
+    .S_READY(s_axi_wready),
+
+    // Master side
+    .M_PAYLOAD_DATA(m_wpayload),
+    .M_VALID(m_axi_wvalid),
+    .M_READY(m_axi_wready)
+  );
+
+  axi_register_slice_v2_1_11_axic_register_slice # (
+    .C_FAMILY     ( C_FAMILY             ) ,
+    .C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
+    .C_REG_CONFIG ( C_REG_CONFIG_B       ) 
+  )
+  b_pipe (
+    // System Signals
+    .ACLK(aclk),
+    .ARESET(reset),
+
+    // Slave side
+    .S_PAYLOAD_DATA(m_bpayload),
+    .S_VALID(m_axi_bvalid),
+    .S_READY(m_axi_bready),
+
+    // Master side
+    .M_PAYLOAD_DATA(s_bpayload),
+    .M_VALID(s_axi_bvalid),
+    .M_READY(s_axi_bready)
+  );
+ 
+
+  axi_register_slice_v2_1_11_axic_register_slice # (
+    .C_FAMILY     ( C_FAMILY              ) ,
+    .C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
+    .C_REG_CONFIG ( C_REG_CONFIG_AR       ) 
+  )
+  ar_pipe (
+    // System Signals
+    .ACLK(aclk),
+    .ARESET(reset),
+
+    // Slave side
+    .S_PAYLOAD_DATA(s_arpayload),
+    .S_VALID(s_axi_arvalid),
+    .S_READY(s_axi_arready),
+
+    // Master side
+    .M_PAYLOAD_DATA(m_arpayload),
+    .M_VALID(m_axi_arvalid),
+    .M_READY(m_axi_arready)
+  );
+        
+  axi_register_slice_v2_1_11_axic_register_slice # (
+    .C_FAMILY     ( C_FAMILY             ) ,
+    .C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,
+    .C_REG_CONFIG ( C_REG_CONFIG_R       ) 
+  )
+  r_pipe (
+    // System Signals
+    .ACLK(aclk),
+    .ARESET(reset),
+
+    // Slave side
+    .S_PAYLOAD_DATA(m_rpayload),
+    .S_VALID(m_axi_rvalid),
+    .S_READY(m_axi_rready),
+
+    // Master side
+    .M_PAYLOAD_DATA(s_rpayload),
+    .M_VALID(s_axi_rvalid),
+    .M_READY(s_axi_rready)
+  );
+
+  axi_infrastructure_v1_1_0_vector2axi #( 
+    .C_AXI_PROTOCOL                ( C_AXI_PROTOCOL                ) ,
+    .C_AXI_ID_WIDTH                ( C_AXI_ID_WIDTH                ) ,
+    .C_AXI_ADDR_WIDTH              ( C_AXI_ADDR_WIDTH              ) ,
+    .C_AXI_DATA_WIDTH              ( C_AXI_DATA_WIDTH              ) ,
+    .C_AXI_SUPPORTS_USER_SIGNALS   ( C_AXI_SUPPORTS_USER_SIGNALS   ) ,
+    .C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
+    .C_AXI_AWUSER_WIDTH            ( C_AXI_AWUSER_WIDTH            ) ,
+    .C_AXI_ARUSER_WIDTH            ( C_AXI_ARUSER_WIDTH            ) ,
+    .C_AXI_WUSER_WIDTH             ( C_AXI_WUSER_WIDTH             ) ,
+    .C_AXI_RUSER_WIDTH             ( C_AXI_RUSER_WIDTH             ) ,
+    .C_AXI_BUSER_WIDTH             ( C_AXI_BUSER_WIDTH             ) ,
+    .C_AWPAYLOAD_WIDTH             ( G_AXI_AWPAYLOAD_WIDTH         ) ,
+    .C_WPAYLOAD_WIDTH              ( G_AXI_WPAYLOAD_WIDTH          ) ,
+    .C_BPAYLOAD_WIDTH              ( G_AXI_BPAYLOAD_WIDTH          ) ,
+    .C_ARPAYLOAD_WIDTH             ( G_AXI_ARPAYLOAD_WIDTH         ) ,
+    .C_RPAYLOAD_WIDTH              ( G_AXI_RPAYLOAD_WIDTH          ) 
+  )
+  axi_infrastructure_v1_1_0_vector2axi_0 ( 
+    .m_awpayload    ( m_awpayload    ) ,
+    .m_wpayload     ( m_wpayload     ) ,
+    .m_bpayload     ( m_bpayload     ) ,
+    .m_arpayload    ( m_arpayload    ) ,
+    .m_rpayload     ( m_rpayload     ) ,
+    .m_axi_awid     ( m_axi_awid     ) ,
+    .m_axi_awaddr   ( m_axi_awaddr   ) ,
+    .m_axi_awlen    ( m_axi_awlen    ) ,
+    .m_axi_awsize   ( m_axi_awsize   ) ,
+    .m_axi_awburst  ( m_axi_awburst  ) ,
+    .m_axi_awlock   ( m_axi_awlock   ) ,
+    .m_axi_awcache  ( m_axi_awcache  ) ,
+    .m_axi_awprot   ( m_axi_awprot   ) ,
+    .m_axi_awqos    ( m_axi_awqos    ) ,
+    .m_axi_awuser   ( m_axi_awuser   ) ,
+    .m_axi_awregion ( m_axi_awregion ) ,
+    .m_axi_wid      ( m_axi_wid      ) ,
+    .m_axi_wdata    ( m_axi_wdata    ) ,
+    .m_axi_wstrb    ( m_axi_wstrb    ) ,
+    .m_axi_wlast    ( m_axi_wlast    ) ,
+    .m_axi_wuser    ( m_axi_wuser    ) ,
+    .m_axi_bid      ( m_axi_bid      ) ,
+    .m_axi_bresp    ( m_axi_bresp    ) ,
+    .m_axi_buser    ( m_axi_buser    ) ,
+    .m_axi_arid     ( m_axi_arid     ) ,
+    .m_axi_araddr   ( m_axi_araddr   ) ,
+    .m_axi_arlen    ( m_axi_arlen    ) ,
+    .m_axi_arsize   ( m_axi_arsize   ) ,
+    .m_axi_arburst  ( m_axi_arburst  ) ,
+    .m_axi_arlock   ( m_axi_arlock   ) ,
+    .m_axi_arcache  ( m_axi_arcache  ) ,
+    .m_axi_arprot   ( m_axi_arprot   ) ,
+    .m_axi_arqos    ( m_axi_arqos    ) ,
+    .m_axi_aruser   ( m_axi_aruser   ) ,
+    .m_axi_arregion ( m_axi_arregion ) ,
+    .m_axi_rid      ( m_axi_rid      ) ,
+    .m_axi_rdata    ( m_axi_rdata    ) ,
+    .m_axi_rresp    ( m_axi_rresp    ) ,
+    .m_axi_rlast    ( m_axi_rlast    ) ,
+    .m_axi_ruser    ( m_axi_ruser    ) 
+  );
+
+endmodule // axi_register_slice
+
+
+"
+"//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, ""Critical
+//  Applications""). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axis to vector
+//   A generic module to merge all axi signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_infrastructure_v1_1_0_axi2vector #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_AXI_PROTOCOL                = 0,
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 32,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
+  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
+  parameter integer C_AXI_AWUSER_WIDTH            = 1,
+  parameter integer C_AXI_WUSER_WIDTH             = 1,
+  parameter integer C_AXI_BUSER_WIDTH             = 1,
+  parameter integer C_AXI_ARUSER_WIDTH            = 1,
+  parameter integer C_AXI_RUSER_WIDTH             = 1,
+  parameter integer C_AWPAYLOAD_WIDTH             = 61,
+  parameter integer C_WPAYLOAD_WIDTH              = 73,
+  parameter integer C_BPAYLOAD_WIDTH              = 6,
+  parameter integer C_ARPAYLOAD_WIDTH             = 61,
+  parameter integer C_RPAYLOAD_WIDTH              = 69
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave Interface Write Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
+  input  wire [3-1:0]                               s_axi_awsize,
+  input  wire [2-1:0]                               s_axi_awburst,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
+  input  wire [4-1:0]                               s_axi_awcache,
+  input  wire [3-1:0]                               s_axi_awprot,
+  input  wire [4-1:0]                               s_axi_awregion,
+  input  wire [4-1:0]                               s_axi_awqos,
+  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,
+
+  // Slave Interface Write Data Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,
+  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,
+  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,
+  input  wire                                       s_axi_wlast,
+  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,
+
+  // Slave Interface Write Response Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,
+  output wire [2-1:0]                               s_axi_bresp,
+  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,
+
+   // Slave Interface Read Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
+  input  wire [3-1:0]                               s_axi_arsize,
+  input  wire [2-1:0]                               s_axi_arburst,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
+  input  wire [4-1:0]                               s_axi_arcache,
+  input  wire [3-1:0]                               s_axi_arprot,
+  input  wire [4-1:0]                               s_axi_arregion,
+  input  wire [4-1:0]                               s_axi_arqos,
+  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,
+
+  // Slave Interface Read Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,
+  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,
+  output wire [2-1:0]                               s_axi_rresp,
+  output wire                                       s_axi_rlast,
+  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,
+
+  // payloads
+  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,
+  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,
+  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,
+  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,
+  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include ""axi_infrastructure_v1_1_0.vh""
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// AXI4, AXI4LITE, AXI3 packing
+assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
+assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
+
+assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
+assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
+
+assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
+
+assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
+assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
+
+assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
+assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
+
+generate
+  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
+    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;
+    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
+    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
+    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;
+    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;
+    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;
+    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;
+
+    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;
+    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
+      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;
+    end
+    else begin : gen_no_axi3_wid_packing
+    end
+
+    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
+
+    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;
+    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
+    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
+    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;
+    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;
+    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;
+    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;
+
+    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
+    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
+
+    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
+      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
+      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
+    end 
+    else begin : gen_no_region_signals
+    end
+    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
+      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
+      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;
+      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
+      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
+      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
+    end 
+    else begin : gen_no_user_signals
+      assign s_axi_buser = \'b0;
+      assign s_axi_ruser = \'b0;
+    end
+  end
+  else begin : gen_axi4lite_packing
+    assign s_axi_bid = \'b0;
+    assign s_axi_buser = \'b0;
+
+    assign s_axi_rlast = 1\'b1;
+    assign s_axi_rid   = \'b0;
+    assign s_axi_ruser = \'b0;
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+
+
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, ""Critical
+//  Applications""). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+// Description: SRL based FIFO for AXIS/AXI Channels.
+//--------------------------------------------------------------------------
+
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_infrastructure_v1_1_0_axic_srl_fifo #(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter         C_FAMILY     = ""virtex7"",
+  parameter integer C_PAYLOAD_WIDTH = 1,
+  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                        aclk,    // Clock
+  input  wire                        aresetn,  // Reset
+  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data
+  input  wire                        s_valid, // Input data valid
+  output reg                         s_ready, // Input data ready
+  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data
+  output reg                         m_valid, // Output data valid
+  input  wire                        m_ready  // Output data ready
+);
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+// ceiling logb2
+function integer f_clogb2 (input integer size);
+  integer s;
+  begin
+    s = size;
+    s = s - 1;
+    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+          s = s >> 1;
+  end
+endfunction // clogb2
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;
+wire [4-1:0]                        fifo_addr;
+wire                                push;
+wire                                pop ;
+reg                                 areset_r1;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+always @(posedge aclk) begin 
+  areset_r1 <= ~aresetn;
+end
+
+always @(posedge aclk) begin 
+  if (~aresetn) begin
+    fifo_index <= {LP_LOG_FIFO_DEPTH{1\'b1}};
+  end
+  else begin
+    fifo_index <= push & ~pop ? fifo_index + 1\'b1 :
+                  ~push & pop ? fifo_index - 1\'b1 : 
+                  fifo_index;
+  end
+end
+
+assign push = s_valid & s_ready;
+
+always @(posedge aclk) begin 
+  if (~aresetn) begin 
+    s_ready <= 1\'b0;
+  end
+  else begin 
+    s_ready <= areset_r1 ? 1\'b1 : 
+               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2\'d2)) ? 1\'b0 :
+               ~push & pop ? 1\'b1 : 
+               s_ready;
+  end
+end
+
+assign pop = m_valid & m_ready;
+               
+always @(posedge aclk) begin 
+  if (~aresetn) begin 
+    m_valid <= 1\'b0;
+  end
+  else begin 
+    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1\'b0}}) ? 1\'b0 :
+               push & ~pop ? 1\'b1 : 
+               m_valid;
+  end
+end
+
+generate 
+  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
+    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
+    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1\'b0}};
+  end
+  else begin : gen_fifo_addr
+    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
+  end
+endgenerate
+
+
+generate
+  genvar i;
+  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
+    SRL16E 
+    u_srl_fifo(
+      .Q   ( m_payload[i] ) ,
+      .A0  ( fifo_addr[0]     ) ,
+      .A1  ( fifo_addr[1]     ) ,
+      .A2  ( fifo_addr[2]     ) ,
+      .A3  ( fifo_addr[3]     ) ,
+      .CE  ( push              ) ,
+      .CLK ( aclk              ) ,
+      .D   ( s_payload[i] ) 
+    );
+  end
+endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, ""Critical
+//  Applications""). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axi to vector
+//   A generic module to merge all axi signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_infrastructure_v1_1_0_vector2axi #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_AXI_PROTOCOL                = 0,
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 32,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
+  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
+  parameter integer C_AXI_AWUSER_WIDTH            = 1,
+  parameter integer C_AXI_WUSER_WIDTH             = 1,
+  parameter integer C_AXI_BUSER_WIDTH             = 1,
+  parameter integer C_AXI_ARUSER_WIDTH            = 1,
+  parameter integer C_AXI_RUSER_WIDTH             = 1,
+  parameter integer C_AWPAYLOAD_WIDTH             = 61,
+  parameter integer C_WPAYLOAD_WIDTH              = 73,
+  parameter integer C_BPAYLOAD_WIDTH              = 6,
+  parameter integer C_ARPAYLOAD_WIDTH             = 61,
+  parameter integer C_RPAYLOAD_WIDTH              = 69
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave Interface Write Address Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,
+  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,
+  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
+  output wire [3-1:0]                               m_axi_awsize,
+  output wire [2-1:0]                               m_axi_awburst,
+  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
+  output wire [4-1:0]                               m_axi_awcache,
+  output wire [3-1:0]                               m_axi_awprot,
+  output wire [4-1:0]                               m_axi_awregion,
+  output wire [4-1:0]                               m_axi_awqos,
+  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,
+
+  // Slave Interface Write Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,
+  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,
+  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,
+  output wire                                       m_axi_wlast,
+  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,
+
+  // Slave Interface Write Response Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,
+  input  wire [2-1:0]                               m_axi_bresp,
+  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,
+
+   // Slave Interface Read Address Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,
+  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,
+  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
+  output wire [3-1:0]                               m_axi_arsize,
+  output wire [2-1:0]                               m_axi_arburst,
+  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
+  output wire [4-1:0]                               m_axi_arcache,
+  output wire [3-1:0]                               m_axi_arprot,
+  output wire [4-1:0]                               m_axi_arregion,
+  output wire [4-1:0]                               m_axi_arqos,
+  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,
+
+  // Slave Interface Read Data Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,
+  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,
+  input  wire [2-1:0]                               m_axi_rresp,
+  input  wire                                       m_axi_rlast,
+  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,
+
+  // payloads
+  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,
+  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,
+  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,
+  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,
+  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include ""axi_infrastructure_v1_1_0.vh""
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// AXI4, AXI4LITE, AXI3 packing
+assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
+assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
+
+assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
+assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
+
+assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
+
+assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
+assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
+
+assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
+assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
+
+generate
+  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
+    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;
+    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
+    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
+    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;
+    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;
+    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;
+    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;
+
+    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;
+    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
+      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;
+    end
+    else begin : gen_no_axi3_wid_packing
+      assign m_axi_wid = 1\'b0;
+    end
+
+    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
+
+    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;
+    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
+    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
+    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;
+    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;
+    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;
+    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;
+
+    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
+    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;
+
+    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
+      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
+      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
+    end 
+    else begin : gen_no_region_signals
+      assign m_axi_awregion = \'b0;
+      assign m_axi_arregion = \'b0;
+    end
+    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
+      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
+      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;
+      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;
+      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
+      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;
+    end 
+    else begin : gen_no_user_signals
+      assign m_axi_awuser = \'b0;
+      assign m_axi_wuser = \'b0;
+      assign m_axi_aruser = \'b0;
+    end
+  end
+  else begin : gen_axi4lite_packing
+    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3\'d2 : 3\'d3;
+    assign m_axi_awburst = \'b0;
+    assign m_axi_awcache = \'b0;
+    assign m_axi_awlen = \'b0;
+    assign m_axi_awlock = \'b0;
+    assign m_axi_awid = \'b0;
+    assign m_axi_awqos = \'b0;
+
+    assign m_axi_wlast = 1\'b1;
+    assign m_axi_wid = \'b0;
+
+
+    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3\'d2 : 3\'d3;
+    assign m_axi_arburst = \'b0;
+    assign m_axi_arcache = \'b0;
+    assign m_axi_arlen = \'b0;
+    assign m_axi_arlock = \'b0;
+    assign m_axi_arid = \'b0;
+    assign m_axi_arqos = \'b0;
+
+    assign m_axi_awregion = \'b0;
+    assign m_axi_arregion = \'b0;
+
+    assign m_axi_awuser = \'b0;
+    assign m_axi_wuser = \'b0;
+    assign m_axi_aruser = \'b0;
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+
+
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Mon Feb 13 23:24:41 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    SDIO0_WP,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    IRQ_F2P,
+    FCLK_CLK0,
+    FCLK_RESET0_N,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I"" *) input [63:0]GPIO_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O"" *) output [63:0]GPIO_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T"" *) output [63:0]GPIO_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *) input SDIO0_WP;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *) output [1:0]USB0_PORT_INDCTL;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *) output USB0_VBUS_PWRSELECT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *) input USB0_VBUS_PWRFAULT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *) output M_AXI_GP0_ARVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *) output M_AXI_GP0_AWVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *) output M_AXI_GP0_BREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *) output M_AXI_GP0_RREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *) output M_AXI_GP0_WLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *) output M_AXI_GP0_WVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *) output [11:0]M_AXI_GP0_ARID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *) output [11:0]M_AXI_GP0_AWID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *) output [11:0]M_AXI_GP0_WID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *) output [1:0]M_AXI_GP0_ARBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *) output [1:0]M_AXI_GP0_ARLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *) output [2:0]M_AXI_GP0_ARSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *) output [1:0]M_AXI_GP0_AWBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *) output [1:0]M_AXI_GP0_AWLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *) output [2:0]M_AXI_GP0_AWSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *) output [2:0]M_AXI_GP0_ARPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *) output [2:0]M_AXI_GP0_AWPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *) output [31:0]M_AXI_GP0_ARADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *) output [31:0]M_AXI_GP0_AWADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *) output [31:0]M_AXI_GP0_WDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *) output [3:0]M_AXI_GP0_ARCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *) output [3:0]M_AXI_GP0_ARLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *) output [3:0]M_AXI_GP0_ARQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *) output [3:0]M_AXI_GP0_AWCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *) output [3:0]M_AXI_GP0_AWLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *) output [3:0]M_AXI_GP0_AWQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *) output [3:0]M_AXI_GP0_WSTRB;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *) input M_AXI_GP0_ACLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *) input M_AXI_GP0_ARREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *) input M_AXI_GP0_AWREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *) input M_AXI_GP0_BVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *) input M_AXI_GP0_RLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *) input M_AXI_GP0_RVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *) input M_AXI_GP0_WREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *) input [11:0]M_AXI_GP0_BID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *) input [11:0]M_AXI_GP0_RID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *) input [1:0]M_AXI_GP0_BRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *) input [1:0]M_AXI_GP0_RRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *) input [31:0]M_AXI_GP0_RDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT"" *) input [0:0]IRQ_F2P;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *) output FCLK_CLK0;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *) output FCLK_RESET0_N;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *) inout [53:0]MIO;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *) inout DDR_CAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *) inout DDR_CKE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *) inout DDR_Clk_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *) inout DDR_Clk;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *) inout DDR_CS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *) inout DDR_DRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *) inout DDR_ODT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *) inout DDR_RAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *) inout DDR_WEB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *) inout [2:0]DDR_BankAddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *) inout [14:0]DDR_Addr;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *) inout DDR_VRN;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *) inout DDR_VRP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *) inout [3:0]DDR_DM;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *) inout [31:0]DDR_DQ;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *) inout [3:0]DDR_DQS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *) inout [3:0]DDR_DQS;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *) inout PS_SRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *) inout PS_CLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *) inout PS_PORB;
+
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire FCLK_CLK0;
+  wire FCLK_RESET0_N;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire [0:0]IRQ_F2P;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [2:0]M_AXI_GP0_ARSIZE;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [2:0]M_AXI_GP0_AWSIZE;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_WP;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+  wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+  wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+  wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+  wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+  wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+  wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO0_LED_UNCONNECTED;
+  wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO1_LED_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+  wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+  wire NLW_inst_TRACE_CTL_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+  wire NLW_inst_UART0_DTRN_UNCONNECTED;
+  wire NLW_inst_UART0_RTSN_UNCONNECTED;
+  wire NLW_inst_UART0_TX_UNCONNECTED;
+  wire NLW_inst_UART1_DTRN_UNCONNECTED;
+  wire NLW_inst_UART1_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_TX_UNCONNECTED;
+  wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+  wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+  wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+  wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+  wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+PULLUP pullup_MIO_0
+       (.O(MIO[0]));
+PULLUP pullup_MIO_9
+       (.O(MIO[9]));
+PULLUP pullup_MIO_10
+       (.O(MIO[10]));
+PULLUP pullup_MIO_11
+       (.O(MIO[11]));
+PULLUP pullup_MIO_12
+       (.O(MIO[12]));
+PULLUP pullup_MIO_13
+       (.O(MIO[13]));
+PULLUP pullup_MIO_14
+       (.O(MIO[14]));
+PULLUP pullup_MIO_15
+       (.O(MIO[15]));
+PULLUP pullup_MIO_46
+       (.O(MIO[46]));
+
+  (* C_DM_WIDTH = ""4"" *) 
+  (* C_DQS_WIDTH = ""4"" *) 
+  (* C_DQ_WIDTH = ""32"" *) 
+  (* C_EMIO_GPIO_WIDTH = ""64"" *) 
+  (* C_EN_EMIO_ENET0 = ""0"" *) 
+  (* C_EN_EMIO_ENET1 = ""0"" *) 
+  (* C_EN_EMIO_PJTAG = ""0"" *) 
+  (* C_EN_EMIO_TRACE = ""0"" *) 
+  (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+  (* C_FCLK_CLK1_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK2_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+  (* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+  (* C_INCLUDE_TRACE_BUFFER = ""0"" *) 
+  (* C_IRQ_F2P_MODE = ""DIRECT"" *) 
+  (* C_MIO_PRIMITIVE = ""54"" *) 
+  (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_NUM_F2P_INTR_INPUTS = ""1"" *) 
+  (* C_PACKAGE_NAME = ""clg400"" *) 
+  (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+  (* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+  (* C_S_AXI_GP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP3_ID_WIDTH = ""6"" *) 
+  (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) 
+  (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+  (* C_TRACE_INTERNAL_WIDTH = ""2"" *) 
+  (* C_TRACE_PIPELINE_WIDTH = ""8"" *) 
+  (* C_USE_AXI_NONSECURE = ""0"" *) 
+  (* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) 
+  (* C_USE_M_AXI_GP0 = ""1"" *) 
+  (* C_USE_M_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_ACP = ""0"" *) 
+  (* C_USE_S_AXI_GP0 = ""0"" *) 
+  (* C_USE_S_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP0 = ""0"" *) 
+  (* C_USE_S_AXI_HP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP2 = ""0"" *) 
+  (* C_USE_S_AXI_HP3 = ""0"" *) 
+  (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) 
+  (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+  (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
+       (.CAN0_PHY_RX(1\'b0),
+        .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+        .CAN1_PHY_RX(1\'b0),
+        .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+        .Core0_nFIQ(1\'b0),
+        .Core0_nIRQ(1\'b0),
+        .Core1_nFIQ(1\'b0),
+        .Core1_nIRQ(1\'b0),
+        .DDR_ARB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .DDR_Addr(DDR_Addr),
+        .DDR_BankAddr(DDR_BankAddr),
+        .DDR_CAS_n(DDR_CAS_n),
+        .DDR_CKE(DDR_CKE),
+        .DDR_CS_n(DDR_CS_n),
+        .DDR_Clk(DDR_Clk),
+        .DDR_Clk_n(DDR_Clk_n),
+        .DDR_DM(DDR_DM),
+        .DDR_DQ(DDR_DQ),
+        .DDR_DQS(DDR_DQS),
+        .DDR_DQS_n(DDR_DQS_n),
+        .DDR_DRSTB(DDR_DRSTB),
+        .DDR_ODT(DDR_ODT),
+        .DDR_RAS_n(DDR_RAS_n),
+        .DDR_VRN(DDR_VRN),
+        .DDR_VRP(DDR_VRP),
+        .DDR_WEB(DDR_WEB),
+        .DMA0_ACLK(1\'b0),
+        .DMA0_DAREADY(1\'b0),
+        .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+        .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+        .DMA0_DRLAST(1\'b0),
+        .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+        .DMA0_DRTYPE({1\'b0,1\'b0}),
+        .DMA0_DRVALID(1\'b0),
+        .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+        .DMA1_ACLK(1\'b0),
+        .DMA1_DAREADY(1\'b0),
+        .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+        .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+        .DMA1_DRLAST(1\'b0),
+        .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+        .DMA1_DRTYPE({1\'b0,1\'b0}),
+        .DMA1_DRVALID(1\'b0),
+        .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+        .DMA2_ACLK(1\'b0),
+        .DMA2_DAREADY(1\'b0),
+        .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+        .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+        .DMA2_DRLAST(1\'b0),
+        .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+        .DMA2_DRTYPE({1\'b0,1\'b0}),
+        .DMA2_DRVALID(1\'b0),
+        .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+        .DMA3_ACLK(1\'b0),
+        .DMA3_DAREADY(1\'b0),
+        .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+        .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+        .DMA3_DRLAST(1\'b0),
+        .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+        .DMA3_DRTYPE({1\'b0,1\'b0}),
+        .DMA3_DRVALID(1\'b0),
+        .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+        .ENET0_EXT_INTIN(1\'b0),
+        .ENET0_GMII_COL(1\'b0),
+        .ENET0_GMII_CRS(1\'b0),
+        .ENET0_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET0_GMII_RX_CLK(1\'b0),
+        .ENET0_GMII_RX_DV(1\'b0),
+        .ENET0_GMII_RX_ER(1\'b0),
+        .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET0_GMII_TX_CLK(1\'b0),
+        .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+        .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+        .ENET0_MDIO_I(1\'b0),
+        .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+        .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+        .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+        .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+        .ENET1_EXT_INTIN(1\'b0),
+        .ENET1_GMII_COL(1\'b0),
+        .ENET1_GMII_CRS(1\'b0),
+        .ENET1_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET1_GMII_RX_CLK(1\'b0),
+        .ENET1_GMII_RX_DV(1\'b0),
+        .ENET1_GMII_RX_ER(1\'b0),
+        .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET1_GMII_TX_CLK(1\'b0),
+        .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+        .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+        .ENET1_MDIO_I(1\'b0),
+        .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+        .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+        .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+        .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+        .EVENT_EVENTI(1\'b0),
+        .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+        .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+        .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+        .FCLK_CLK0(FCLK_CLK0),
+        .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+        .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+        .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+        .FCLK_CLKTRIG0_N(1\'b0),
+        .FCLK_CLKTRIG1_N(1\'b0),
+        .FCLK_CLKTRIG2_N(1\'b0),
+        .FCLK_CLKTRIG3_N(1\'b0),
+        .FCLK_RESET0_N(FCLK_RESET0_N),
+        .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+        .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+        .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+        .FPGA_IDLE_N(1\'b0),
+        .FTMD_TRACEIN_ATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_CLK(1\'b0),
+        .FTMD_TRACEIN_DATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_VALID(1\'b0),
+        .FTMT_F2P_DEBUG({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+        .FTMT_F2P_TRIG_0(1\'b0),
+        .FTMT_F2P_TRIG_1(1\'b0),
+        .FTMT_F2P_TRIG_2(1\'b0),
+        .FTMT_F2P_TRIG_3(1\'b0),
+        .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+        .FTMT_P2F_TRIGACK_0(1\'b0),
+        .FTMT_P2F_TRIGACK_1(1\'b0),
+        .FTMT_P2F_TRIGACK_2(1\'b0),
+        .FTMT_P2F_TRIGACK_3(1\'b0),
+        .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+        .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+        .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+        .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+        .GPIO_I(GPIO_I),
+        .GPIO_O(GPIO_O),
+        .GPIO_T(GPIO_T),
+        .I2C0_SCL_I(1\'b0),
+        .I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
+        .I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
+        .I2C0_SDA_I(1\'b0),
+        .I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
+        .I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
+        .I2C1_SCL_I(1\'b0),
+        .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+        .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+        .I2C1_SDA_I(1\'b0),
+        .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+        .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+        .IRQ_F2P(IRQ_F2P),
+        .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+        .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+        .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+        .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+        .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+        .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+        .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+        .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+        .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+        .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+        .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+        .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+        .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+        .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+        .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+        .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+        .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+        .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+        .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+        .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+        .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+        .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+        .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+        .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+        .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+        .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+        .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+        .MIO(MIO),
+        .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+        .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+        .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+        .M_AXI_GP1_ACLK(1\'b0),
+        .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+        .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARREADY(1\'b0),
+        .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+        .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWREADY(1\'b0),
+        .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+        .M_AXI_GP1_BID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+        .M_AXI_GP1_BRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_BVALID(1\'b0),
+        .M_AXI_GP1_RDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RLAST(1\'b0),
+        .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+        .M_AXI_GP1_RRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_RVALID(1\'b0),
+        .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+        .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+        .M_AXI_GP1_WREADY(1\'b0),
+        .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+        .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+        .PJTAG_TCK(1\'b0),
+        .PJTAG_TDI(1\'b0),
+        .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+        .PJTAG_TMS(1\'b0),
+        .PS_CLK(PS_CLK),
+        .PS_PORB(PS_PORB),
+        .PS_SRSTB(PS_SRSTB),
+        .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+        .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO0_CDN(1\'b0),
+        .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+        .SDIO0_CLK_FB(1\'b0),
+        .SDIO0_CMD_I(1\'b0),
+        .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+        .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+        .SDIO0_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+        .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+        .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+        .SDIO0_WP(SDIO0_WP),
+        .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+        .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO1_CDN(1\'b0),
+        .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+        .SDIO1_CLK_FB(1\'b0),
+        .SDIO1_CMD_I(1\'b0),
+        .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+        .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+        .SDIO1_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+        .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+        .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+        .SDIO1_WP(1\'b0),
+        .SPI0_MISO_I(1\'b0),
+        .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+        .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+        .SPI0_MOSI_I(1\'b0),
+        .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+        .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+        .SPI0_SCLK_I(1\'b0),
+        .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+        .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+        .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+        .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+        .SPI0_SS_I(1\'b0),
+        .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+        .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+        .SPI1_MISO_I(1\'b0),
+        .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+        .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+        .SPI1_MOSI_I(1\'b0),
+        .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+        .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+        .SPI1_SCLK_I(1\'b0),
+        .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+        .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+        .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+        .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+        .SPI1_SS_I(1\'b0),
+        .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+        .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+        .SRAM_INTIN(1\'b0),
+        .S_AXI_ACP_ACLK(1\'b0),
+        .S_AXI_ACP_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+        .S_AXI_ACP_ARID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+        .S_AXI_ACP_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARVALID(1\'b0),
+        .S_AXI_ACP_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+        .S_AXI_ACP_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWVALID(1\'b0),
+        .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_BREADY(1\'b0),
+        .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+        .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+        .S_AXI_ACP_RREADY(1\'b0),
+        .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+        .S_AXI_ACP_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WLAST(1\'b0),
+        .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+        .S_AXI_ACP_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WVALID(1\'b0),
+        .S_AXI_GP0_ACLK(1\'b0),
+        .S_AXI_GP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+        .S_AXI_GP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+        .S_AXI_GP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARVALID(1\'b0),
+        .S_AXI_GP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+        .S_AXI_GP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWVALID(1\'b0),
+        .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_BREADY(1\'b0),
+        .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+        .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+        .S_AXI_GP0_RREADY(1\'b0),
+        .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+        .S_AXI_GP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WLAST(1\'b0),
+        .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+        .S_AXI_GP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WVALID(1\'b0),
+        .S_AXI_GP1_ACLK(1\'b0),
+        .S_AXI_GP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+        .S_AXI_GP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+        .S_AXI_GP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARVALID(1\'b0),
+        .S_AXI_GP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+        .S_AXI_GP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWVALID(1\'b0),
+        .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_BREADY(1\'b0),
+        .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+        .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+        .S_AXI_GP1_RREADY(1\'b0),
+        .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+        .S_AXI_GP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WLAST(1\'b0),
+        .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+        .S_AXI_GP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WVALID(1\'b0),
+        .S_AXI_HP0_ACLK(1\'b0),
+        .S_AXI_HP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+        .S_AXI_HP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+        .S_AXI_HP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARVALID(1\'b0),
+        .S_AXI_HP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+        .S_AXI_HP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWVALID(1\'b0),
+        .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_BREADY(1\'b0),
+        .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+        .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP0_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+        .S_AXI_HP0_RREADY(1\'b0),
+        .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+        .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WLAST(1\'b0),
+        .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+        .S_AXI_HP0_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WVALID(1\'b0),
+        .S_AXI_HP1_ACLK(1\'b0),
+        .S_AXI_HP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+        .S_AXI_HP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+        .S_AXI_HP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARVALID(1\'b0),
+        .S_AXI_HP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+        .S_AXI_HP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWVALID(1\'b0),
+        .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_BREADY(1\'b0),
+        .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+        .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP1_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+        .S_AXI_HP1_RREADY(1\'b0),
+        .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+        .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WLAST(1\'b0),
+        .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+        .S_AXI_HP1_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WVALID(1\'b0),
+        .S_AXI_HP2_ACLK(1\'b0),
+        .S_AXI_HP2_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+        .S_AXI_HP2_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+        .S_AXI_HP2_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARVALID(1\'b0),
+        .S_AXI_HP2_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+        .S_AXI_HP2_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWVALID(1\'b0),
+        .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_BREADY(1\'b0),
+        .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+        .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP2_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+        .S_AXI_HP2_RREADY(1\'b0),
+        .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+        .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WLAST(1\'b0),
+        .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+        .S_AXI_HP2_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WVALID(1\'b0),
+        .S_AXI_HP3_ACLK(1\'b0),
+        .S_AXI_HP3_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+        .S_AXI_HP3_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+        .S_AXI_HP3_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARVALID(1\'b0),
+        .S_AXI_HP3_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+        .S_AXI_HP3_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWVALID(1\'b0),
+        .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_BREADY(1\'b0),
+        .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+        .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP3_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+        .S_AXI_HP3_RREADY(1\'b0),
+        .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+        .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WLAST(1\'b0),
+        .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
+        .S_AXI_HP3_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WVALID(1\'b0),
+        .TRACE_CLK(1\'b0),
+        .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+        .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
+        .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+        .TTC0_CLK0_IN(1\'b0),
+        .TTC0_CLK1_IN(1\'b0),
+        .TTC0_CLK2_IN(1\'b0),
+        .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+        .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+        .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+        .TTC1_CLK0_IN(1\'b0),
+        .TTC1'b'_CLK1_IN(1\'b0),
+        .TTC1_CLK2_IN(1\'b0),
+        .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+        .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+        .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+        .UART0_CTSN(1\'b0),
+        .UART0_DCDN(1\'b0),
+        .UART0_DSRN(1\'b0),
+        .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
+        .UART0_RIN(1\'b0),
+        .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
+        .UART0_RX(1\'b1),
+        .UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
+        .UART1_CTSN(1\'b0),
+        .UART1_DCDN(1\'b0),
+        .UART1_DSRN(1\'b0),
+        .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+        .UART1_RIN(1\'b0),
+        .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+        .UART1_RX(1\'b1),
+        .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+        .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+        .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+        .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+        .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+        .USB1_VBUS_PWRFAULT(1\'b0),
+        .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+        .WDT_CLK_IN(1\'b0),
+        .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = ""4"" *) (* C_DQS_WIDTH = ""4"" *) (* C_DQ_WIDTH = ""32"" *) 
+(* C_EMIO_GPIO_WIDTH = ""64"" *) (* C_EN_EMIO_ENET0 = ""0"" *) (* C_EN_EMIO_ENET1 = ""0"" *) 
+(* C_EN_EMIO_PJTAG = ""0"" *) (* C_EN_EMIO_TRACE = ""0"" *) (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+(* C_FCLK_CLK1_BUF = ""FALSE"" *) (* C_FCLK_CLK2_BUF = ""FALSE"" *) (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+(* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+(* C_INCLUDE_TRACE_BUFFER = ""0"" *) (* C_IRQ_F2P_MODE = ""DIRECT"" *) (* C_MIO_PRIMITIVE = ""54"" *) 
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+(* C_NUM_F2P_INTR_INPUTS = ""1"" *) (* C_PACKAGE_NAME = ""clg400"" *) (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+(* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+(* C_S_AXI_GP0_ID_WIDTH = ""6"" *) (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP0_ID_WIDTH = ""6"" *) (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+(* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP3_ID_WIDTH = ""6"" *) (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+(* C_TRACE_INTERNAL_WIDTH = ""2"" *) (* C_TRACE_PIPELINE_WIDTH = ""8"" *) (* C_USE_AXI_NONSECURE = ""0"" *) 
+(* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) (* C_USE_M_AXI_GP0 = ""1"" *) (* C_USE_M_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_ACP = ""0"" *) (* C_USE_S_AXI_GP0 = ""0"" *) (* C_USE_S_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_HP0 = ""0"" *) (* C_USE_S_AXI_HP1 = ""0"" *) (* C_USE_S_AXI_HP2 = ""0"" *) 
+(* C_USE_S_AXI_HP3 = ""0"" *) (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+(* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
+   (CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TDI,
+    PJTAG_TDO,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    TRACE_CLK_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_PORT_INDCTL,
+    USB1_VBUS_PWRSELECT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARESETN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARESETN,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARESETN,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARESETN,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_ARESETN,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARESETN,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARESETN,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARESETN,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARESETN,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_RSTN,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_RSTN,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_RSTN,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_RSTN,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA3_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DRTYPE,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG_0,
+    FTMT_F2P_TRIGACK_0,
+    FTMT_F2P_TRIG_1,
+    FTMT_F2P_TRIGACK_1,
+    FTMT_F2P_TRIG_2,
+    FTMT_F2P_TRIGACK_2,
+    FTMT_F2P_TRIG_3,
+    FTMT_F2P_TRIGACK_3,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK_0,
+    FTMT_P2F_TRIG_0,
+    FTMT_P2F_TRIGACK_1,
+    FTMT_P2F_TRIG_1,
+    FTMT_P2F_TRIGACK_2,
+    FTMT_P2F_TRIG_2,
+    FTMT_P2F_TRIGACK_3,
+    FTMT_P2F_TRIG_3,
+    FTMT_P2F_DEBUG,
+    FPGA_IDLE_N,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    DDR_ARB,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0]ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input ENET0_EXT_INTIN;
+  input [7:0]ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0]ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input ENET1_EXT_INTIN;
+  input [7:0]ENET1_GMII_RXD;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TDI;
+  output PJTAG_TDO;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0]SDIO0_DATA_I;
+  output [3:0]SDIO0_DATA_O;
+  output [3:0]SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0]SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0]SDIO1_DATA_I;
+  output [3:0]SDIO1_DATA_O;
+  output [3:0]SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0]SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [1:0]TRACE_DATA;
+  output TRACE_CLK_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output [1:0]USB1_PORT_INDCTL;
+  output USB1_VBUS_PWRSELECT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARESETN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARESETN;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [11:0]M_AXI_GP1_ARID;
+  output [11:0]M_AXI_GP1_AWID;
+  output [11:0]M_AXI_GP1_WID;
+  output [1:0]M_AXI_GP1_ARBURST;
+  output [1:0]M_AXI_GP1_ARLOCK;
+  output [2:0]M_AXI_GP1_ARSIZE;
+  output [1:0]M_AXI_GP1_AWBURST;
+  output [1:0]M_AXI_GP1_AWLOCK;
+  output [2:0]M_AXI_GP1_AWSIZE;
+  output [2:0]M_AXI_GP1_ARPROT;
+  output [2:0]M_AXI_GP1_AWPROT;
+  output [31:0]M_AXI_GP1_ARADDR;
+  output [31:0]M_AXI_GP1_AWADDR;
+  output [31:0]M_AXI_GP1_WDATA;
+  output [3:0]M_AXI_GP1_ARCACHE;
+  output [3:0]M_AXI_GP1_ARLEN;
+  output [3:0]M_AXI_GP1_ARQOS;
+  output [3:0]M_AXI_GP1_AWCACHE;
+  output [3:0]M_AXI_GP1_AWLEN;
+  output [3:0]M_AXI_GP1_AWQOS;
+  output [3:0]M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [11:0]M_AXI_GP1_BID;
+  input [11:0]M_AXI_GP1_RID;
+  input [1:0]M_AXI_GP1_BRESP;
+  input [1:0]M_AXI_GP1_RRESP;
+  input [31:0]M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARESETN;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0]S_AXI_GP0_BRESP;
+  output [1:0]S_AXI_GP0_RRESP;
+  output [31:0]S_AXI_GP0_RDATA;
+  output [5:0]S_AXI_GP0_BID;
+  output [5:0]S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0]S_AXI_GP0_ARBURST;
+  input [1:0]S_AXI_GP0_ARLOCK;
+  input [2:0]S_AXI_GP0_ARSIZE;
+  input [1:0]S_AXI_GP0_AWBURST;
+  input [1:0]S_AXI_GP0_AWLOCK;
+  input [2:0]S_AXI_GP0_AWSIZE;
+  input [2:0]S_AXI_GP0_ARPROT;
+  input [2:0]S_AXI_GP0_AWPROT;
+  input [31:0]S_AXI_GP0_ARADDR;
+  input [31:0]S_AXI_GP0_AWADDR;
+  input [31:0]S_AXI_GP0_WDATA;
+  input [3:0]S_AXI_GP0_ARCACHE;
+  input [3:0]S_AXI_GP0_ARLEN;
+  input [3:0]S_AXI_GP0_ARQOS;
+  input [3:0]S_AXI_GP0_AWCACHE;
+  input [3:0]S_AXI_GP0_AWLEN;
+  input [3:0]S_AXI_GP0_AWQOS;
+  input [3:0]S_AXI_GP0_WSTRB;
+  input [5:0]S_AXI_GP0_ARID;
+  input [5:0]S_AXI_GP0_AWID;
+  input [5:0]S_AXI_GP0_WID;
+  output S_AXI_GP1_ARESETN;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0]S_AXI_GP1_BRESP;
+  output [1:0]S_AXI_GP1_RRESP;
+  output [31:0]S_AXI_GP1_RDATA;
+  output [5:0]S_AXI_GP1_BID;
+  output [5:0]S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0]S_AXI_GP1_ARBURST;
+  input [1:0]S_AXI_GP1_ARLOCK;
+  input [2:0]S_AXI_GP1_ARSIZE;
+  input [1:0]S_AXI_GP1_AWBURST;
+  input [1:0]S_AXI_GP1_AWLOCK;
+  input [2:0]S_AXI_GP1_AWSIZE;
+  input [2:0]S_AXI_GP1_ARPROT;
+  input [2:0]S_AXI_GP1_AWPROT;
+  input [31:0]S_AXI_GP1_ARADDR;
+  input [31:0]S_AXI_GP1_AWADDR;
+  input [31:0]S_AXI_GP1_WDATA;
+  input [3:0]S_AXI_GP1_ARCACHE;
+  input [3:0]S_AXI_GP1_ARLEN;
+  input [3:0]S_AXI_GP1_ARQOS;
+  input [3:0]S_AXI_GP1_AWCACHE;
+  input [3:0]S_AXI_GP1_AWLEN;
+  input [3:0]S_AXI_GP1_AWQOS;
+  input [3:0]S_AXI_GP1_WSTRB;
+  input [5:0]S_AXI_GP1_ARID;
+  input [5:0]S_AXI_GP1_AWID;
+  input [5:0]S_AXI_GP1_WID;
+  output S_AXI_ACP_ARESETN;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0]S_AXI_ACP_BRESP;
+  output [1:0]S_AXI_ACP_RRESP;
+  output [2:0]S_AXI_ACP_BID;
+  output [2:0]S_AXI_ACP_RID;
+  output [63:0]S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0]S_AXI_ACP_ARID;
+  input [2:0]S_AXI_ACP_ARPROT;
+  input [2:0]S_AXI_ACP_AWID;
+  input [2:0]S_AXI_ACP_AWPROT;
+  input [2:0]S_AXI_ACP_WID;
+  input [31:0]S_AXI_ACP_ARADDR;
+  input [31:0]S_AXI_ACP_AWADDR;
+  input [3:0]S_AXI_ACP_ARCACHE;
+  input [3:0]S_AXI_ACP_ARLEN;
+  input [3:0]S_AXI_ACP_ARQOS;
+  input [3:0]S_AXI_ACP_AWCACHE;
+  input [3:0]S_AXI_ACP_AWLEN;
+  input [3:0]S_AXI_ACP_AWQOS;
+  input [1:0]S_AXI_ACP_ARBURST;
+  input [1:0]S_AXI_ACP_ARLOCK;
+  input [2:0]S_AXI_ACP_ARSIZE;
+  input [1:0]S_AXI_ACP_AWBURST;
+  input [1:0]S_AXI_ACP_AWLOCK;
+  input [2:0]S_AXI_ACP_AWSIZE;
+  input [4:0]S_AXI_ACP_ARUSER;
+  input [4:0]S_AXI_ACP_AWUSER;
+  input [63:0]S_AXI_ACP_WDATA;
+  input [7:0]S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARESETN;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0]S_AXI_HP0_BRESP;
+  output [1:0]S_AXI_HP0_RRESP;
+  output [5:0]S_AXI_HP0_BID;
+  output [5:0]S_AXI_HP0_RID;
+  output [63:0]S_AXI_HP0_RDATA;
+  output [7:0]S_AXI_HP0_RCOUNT;
+  output [7:0]S_AXI_HP0_WCOUNT;
+  output [2:0]S_AXI_HP0_RACOUNT;
+  output [5:0]S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0]S_AXI_HP0_ARBURST;
+  input [1:0]S_AXI_HP0_ARLOCK;
+  input [2:0]S_AXI_HP0_ARSIZE;
+  input [1:0]S_AXI_HP0_AWBURST;
+  input [1:0]S_AXI_HP0_AWLOCK;
+  input [2:0]S_AXI_HP0_AWSIZE;
+  input [2:0]S_AXI_HP0_ARPROT;
+  input [2:0]S_AXI_HP0_AWPROT;
+  input [31:0]S_AXI_HP0_ARADDR;
+  input [31:0]S_AXI_HP0_AWADDR;
+  input [3:0]S_AXI_HP0_ARCACHE;
+  input [3:0]S_AXI_HP0_ARLEN;
+  input [3:0]S_AXI_HP0_ARQOS;
+  input [3:0]S_AXI_HP0_AWCACHE;
+  input [3:0]S_AXI_HP0_AWLEN;
+  input [3:0]S_AXI_HP0_AWQOS;
+  input [5:0]S_AXI_HP0_ARID;
+  input [5:0]S_AXI_HP0_AWID;
+  input [5:0]S_AXI_HP0_WID;
+  input [63:0]S_AXI_HP0_WDATA;
+  input [7:0]S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARESETN;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0]S_AXI_HP1_BRESP;
+  output [1:0]S_AXI_HP1_RRESP;
+  output [5:0]S_AXI_HP1_BID;
+  output [5:0]S_AXI_HP1_RID;
+  output [63:0]S_AXI_HP1_RDATA;
+  output [7:0]S_AXI_HP1_RCOUNT;
+  output [7:0]S_AXI_HP1_WCOUNT;
+  output [2:0]S_AXI_HP1_RACOUNT;
+  output [5:0]S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0]S_AXI_HP1_ARBURST;
+  input [1:0]S_AXI_HP1_ARLOCK;
+  input [2:0]S_AXI_HP1_ARSIZE;
+  input [1:0]S_AXI_HP1_AWBURST;
+  input [1:0]S_AXI_HP1_AWLOCK;
+  input [2:0]S_AXI_HP1_AWSIZE;
+  input [2:0]S_AXI_HP1_ARPROT;
+  input [2:0]S_AXI_HP1_AWPROT;
+  input [31:0]S_AXI_HP1_ARADDR;
+  input [31:0]S_AXI_HP1_AWADDR;
+  input [3:0]S_AXI_HP1_ARCACHE;
+  input [3:0]S_AXI_HP1_ARLEN;
+  input [3:0]S_AXI_HP1_ARQOS;
+  input [3:0]S_AXI_HP1_AWCACHE;
+  input [3:0]S_AXI_HP1_AWLEN;
+  input [3:0]S_AXI_HP1_AWQOS;
+  input [5:0]S_AXI_HP1_ARID;
+  input [5:0]S_AXI_HP1_AWID;
+  input [5:0]S_AXI_HP1_WID;
+  input [63:0]S_AXI_HP1_WDATA;
+  input [7:0]S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARESETN;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0]S_AXI_HP2_BRESP;
+  output [1:0]S_AXI_HP2_RRESP;
+  output [5:0]S_AXI_HP2_BID;
+  output [5:0]S_AXI_HP2_RID;
+  output [63:0]S_AXI_HP2_RDATA;
+  output [7:0]S_AXI_HP2_RCOUNT;
+  output [7:0]S_AXI_HP2_WCOUNT;
+  output [2:0]S_AXI_HP2_RACOUNT;
+  output [5:0]S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0]S_AXI_HP2_ARBURST;
+  input [1:0]S_AXI_HP2_ARLOCK;
+  input [2:0]S_AXI_HP2_ARSIZE;
+  input [1:0]S_AXI_HP2_AWBURST;
+  input [1:0]S_AXI_HP2_AWLOCK;
+  input [2:0]S_AXI_HP2_AWSIZE;
+  input [2:0]S_AXI_HP2_ARPROT;
+  input [2:0]S_AXI_HP2_AWPROT;
+  input [31:0]S_AXI_HP2_ARADDR;
+  input [31:0]S_AXI_HP2_AWADDR;
+  input [3:0]S_AXI_HP2_ARCACHE;
+  input [3:0]S_AXI_HP2_ARLEN;
+  input [3:0]S_AXI_HP2_ARQOS;
+  input [3:0]S_AXI_HP2_AWCACHE;
+  input [3:0]S_AXI_HP2_AWLEN;
+  input [3:0]S_AXI_HP2_AWQOS;
+  input [5:0]S_AXI_HP2_ARID;
+  input [5:0]S_AXI_HP2_AWID;
+  input [5:0]S_AXI_HP2_WID;
+  input [63:0]S_AXI_HP2_WDATA;
+  input [7:0]S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARESETN;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0]S_AXI_HP3_BRESP;
+  output [1:0]S_AXI_HP3_RRESP;
+  output [5:0]S_AXI_HP3_BID;
+  output [5:0]S_AXI_HP3_RID;
+  output [63:0]S_AXI_HP3_RDATA;
+  output [7:0]S_AXI_HP3_RCOUNT;
+  output [7:0]S_AXI_HP3_WCOUNT;
+  output [2:0]S_AXI_HP3_RACOUNT;
+  output [5:0]S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0]S_AXI_HP3_ARBURST;
+  input [1:0]S_AXI_HP3_ARLOCK;
+  input [2:0]S_AXI_HP3_ARSIZE;
+  input [1:0]S_AXI_HP3_AWBURST;
+  input [1:0]S_AXI_HP3_AWLOCK;
+  input [2:0]S_AXI_HP3_AWSIZE;
+  input [2:0]S_AXI_HP3_ARPROT;
+  input [2:0]S_AXI_HP3_AWPROT;
+  input [31:0]S_AXI_HP3_ARADDR;
+  input [31:0]S_AXI_HP3_AWADDR;
+  input [3:0]S_AXI_HP3_ARCACHE;
+  input [3:0]S_AXI_HP3_ARLEN;
+  input [3:0]S_AXI_HP3_ARQOS;
+  input [3:0]S_AXI_HP3_AWCACHE;
+  input [3:0]S_AXI_HP3_AWLEN;
+  input [3:0]S_AXI_HP3_AWQOS;
+  input [5:0]S_AXI_HP3_ARID;
+  input [5:0]S_AXI_HP3_AWID;
+  input [5:0]S_AXI_HP3_WID;
+  input [63:0]S_AXI_HP3_WDATA;
+  input [7:0]S_AXI_HP3_WSTRB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+  input [0:0]IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output [1:0]DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  output DMA0_RSTN;
+  output [1:0]DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  output DMA1_RSTN;
+  output [1:0]DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  output DMA2_RSTN;
+  output [1:0]DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  output DMA3_RSTN;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input DMA3_DRVALID;
+  input [1:0]DMA0_DRTYPE;
+  input [1:0]DMA1_DRTYPE;
+  input [1:0]DMA2_DRTYPE;
+  input [1:0]DMA3_DRTYPE;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input [31:0]FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0]FTMD_TRACEIN_ATID;
+  input FTMT_F2P_TRIG_0;
+  output FTMT_F2P_TRIGACK_0;
+  input FTMT_F2P_TRIG_1;
+  output FTMT_F2P_TRIGACK_1;
+  input FTMT_F2P_TRIG_2;
+  output FTMT_F2P_TRIGACK_2;
+  input FTMT_F2P_TRIG_3;
+  output FTMT_F2P_TRIGACK_3;
+  input [31:0]FTMT_F2P_DEBUG;
+  input FTMT_P2F_TRIGACK_0;
+  output FTMT_P2F_TRIG_0;
+  input FTMT_P2F_TRIGACK_1;
+  output FTMT_P2F_TRIG_1;
+  input FTMT_P2F_TRIGACK_2;
+  output FTMT_P2F_TRIG_2;
+  input FTMT_P2F_TRIGACK_3;
+  output FTMT_P2F_TRIG_3;
+  output [31:0]FTMT_P2F_DEBUG;
+  input FPGA_IDLE_N;
+  output EVENT_EVENTO;
+  output [1:0]EVENT_STANDBYWFE;
+  output [1:0]EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  input [3:0]DDR_ARB;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+
+  wire \\<const0> ;
+  wire CAN0_PHY_RX;
+  wire CAN0_PHY_TX;
+  wire CAN1_PHY_RX;
+  wire CAN1_PHY_TX;
+  wire Core0_nFIQ;
+  wire Core0_nIRQ;
+  wire Core1_nFIQ;
+  wire Core1_nIRQ;
+  wire [3:0]DDR_ARB;
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire DMA0_ACLK;
+  wire DMA0_DAREADY;
+  wire [1:0]DMA0_DATYPE;
+  wire DMA0_DAVALID;
+  wire DMA0_DRLAST;
+  wire DMA0_DRREADY;
+  wire [1:0]DMA0_DRTYPE;
+  wire DMA0_DRVALID;
+  wire DMA0_RSTN;
+  wire DMA1_ACLK;
+  wire DMA1_DAREADY;
+  wire [1:0]DMA1_DATYPE;
+  wire DMA1_DAVALID;
+  wire DMA1_DRLAST;
+  wire DMA1_DRREADY;
+  wire [1:0]DMA1_DRTYPE;
+  wire DMA1_DRVALID;
+  wire DMA1_RSTN;
+  wire DMA2_ACLK;
+  wire DMA2_DAREADY;
+  wire [1:0]DMA2_DATYPE;
+  wire DMA2_DAVALID;
+  wire DMA2_DRLAST;
+  wire DMA2_DRREADY;
+  wire [1:0]DMA2_DRTYPE;
+  wire DMA2_DRVALID;
+  wire DMA2_RSTN;
+  wire DMA3_ACLK;
+  wire DMA3_DAREADY;
+  wire [1:0]DMA3_DATYPE;
+  wire DMA3_DAVALID;
+  wire DMA3_DRLAST;
+  wire DMA3_DRREADY;
+  wire [1:0]DMA3_DRTYPE;
+  wire DMA3_DRVALID;
+  wire DMA3_RSTN;
+  wire ENET0_EXT_INTIN;
+  wire ENET0_GMII_RX_CLK;
+  wire ENET0_GMII_TX_CLK;
+  wire ENET0_MDIO_I;
+  wire ENET0_MDIO_MDC;
+  wire ENET0_MDIO_O;
+  wire ENET0_MDIO_T;
+  wire ENET0_MDIO_T_n;
+  wire ENET0_PTP_DELAY_REQ_RX;
+  wire ENET0_PTP_DELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_REQ_RX;
+  wire ENET0_PTP_PDELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_RESP_RX;
+  wire ENET0_PTP_PDELAY_RESP_TX;
+  wire ENET0_PTP_SYNC_FRAME_RX;
+  wire ENET0_PTP_SYNC_FRAME_TX;
+  wire ENET0_SOF_RX;
+  wire ENET0_SOF_TX;
+  wire ENET1_EXT_INTIN;
+  wire ENET1_GMII_RX_CLK;
+  wire ENET1_GMII_TX_CLK;
+  wire ENET1_MDIO_I;
+  wire ENET1_MDIO_MDC;
+  wire ENET1_MDIO_O;
+  wire ENET1_MDIO_T;
+  wire ENET1_MDIO_T_n;
+  wire ENET1_PTP_DELAY_REQ_RX;
+  wire ENET1_PTP_DELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_REQ_RX;
+  wire ENET1_PTP_PDELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_RESP_RX;
+  wire ENET1_PTP_PDELAY_RESP_TX;
+  wire ENET1_PTP_SYNC_FRAME_RX;
+  wire ENET1_PTP_SYNC_FRAME_TX;
+  wire ENET1_SOF_RX;
+  wire ENET1_SOF_TX;
+  wire EVENT_EVENTI;
+  wire EVENT_EVENTO;
+  wire [1:0]EVENT_STANDBYWFE;
+  wire [1:0]EVENT_STANDBYWFI;
+  wire FCLK_CLK0;
+  wire FCLK_CLK1;
+  wire FCLK_CLK2;
+  wire FCLK_CLK3;
+  wire [0:0]FCLK_CLK_unbuffered;
+  wire FCLK_RESET0_N;
+  wire FCLK_RESET1_N;
+  wire FCLK_RESET2_N;
+  wire FCLK_RESET3_N;
+  wire FPGA_IDLE_N;
+  wire FTMD_TRACEIN_CLK;
+  wire [31:0]FTMT_F2P_DEBUG;
+  wire FTMT_F2P_TRIGACK_0;
+  wire FTMT_F2P_TRIGACK_1;
+  wire FTMT_F2P_TRIGACK_2;
+  wire FTMT_F2P_TRIGACK_3;
+  wire FTMT_F2P_TRIG_0;
+  wire FTMT_F2P_TRIG_1;
+  wire FTMT_F2P_TRIG_2;
+  wire FTMT_F2P_TRIG_3;
+  wire [31:0]FTMT_P2F_DEBUG;
+  wire FTMT_P2F_TRIGACK_0;
+  wire FTMT_P2F_TRIGACK_1;
+  wire FTMT_P2F_TRIGACK_2;
+  wire FTMT_P2F_TRIGACK_3;
+  wire FTMT_P2F_TRIG_0;
+  wire FTMT_P2F_TRIG_1;
+  wire FTMT_P2F_TRIG_2;
+  wire FTMT_P2F_TRIG_3;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SCL_T_n;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire I2C0_SDA_T_n;
+  wire I2C1_SCL_I;
+  wire I2C1_SCL_O;
+  wire I2C1_SCL_T;
+  wire I2C1_SCL_T_n;
+  wire I2C1_SDA_I;
+  wire I2C1_SDA_O;
+  wire I2C1_SDA_T;
+  wire I2C1_SDA_T_n;
+  wire [0:0]IRQ_F2P;
+  wire IRQ_P2F_CAN0;
+  wire IRQ_P2F_CAN1;
+  wire IRQ_P2F_CTI;
+  wire IRQ_P2F_DMAC0;
+  wire IRQ_P2F_DMAC1;
+  wire IRQ_P2F_DMAC2;
+  wire IRQ_P2F_DMAC3;
+  wire IRQ_P2F_DMAC4;
+  wire IRQ_P2F_DMAC5;
+  wire IRQ_P2F_DMAC6;
+  wire IRQ_P2F_DMAC7;
+  wire IRQ_P2F_DMAC_ABORT;
+  wire IRQ_P2F_ENET0;
+  wire IRQ_P2F_ENET1;
+  wire IRQ_P2F_ENET_WAKE0;
+  wire IRQ_P2F_ENET_WAKE1;
+  wire IRQ_P2F_GPIO;
+  wire IRQ_P2F_I2C0;
+  wire IRQ_P2F_I2C1;
+  wire IRQ_P2F_QSPI;
+  wire IRQ_P2F_SDIO0;
+  wire IRQ_P2F_SDIO1;
+  wire IRQ_P2F_SMC;
+  wire IRQ_P2F_SPI0;
+  wire IRQ_P2F_SPI1;
+  wire IRQ_P2F_UART0;
+  wire IRQ_P2F_UART1;
+  wire IRQ_P2F_USB0;
+  wire IRQ_P2F_USB1;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire M_AXI_GP0_ARESETN;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [1:0]\\^M_AXI_GP0_ARSIZE ;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [1:0]\\^M_AXI_GP0_AWSIZE ;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire M_AXI_GP1_ACLK;
+  wire [31:0]M_AXI_GP1_ARADDR;
+  wire [1:0]M_AXI_GP1_ARBURST;
+  wire [3:0]M_AXI_GP1_ARCACHE;
+  wire M_AXI_GP1_ARESETN;
+  wire [11:0]M_AXI_GP1_ARID;
+  wire [3:0]M_AXI_GP1_ARLEN;
+  wire [1:0]M_AXI_GP1_ARLOCK;
+  wire [2:0]M_AXI_GP1_ARPROT;
+  wire [3:0]M_AXI_GP1_ARQOS;
+  wire M_AXI_GP1_ARREADY;
+  wire [1:0]\\^M_AXI_GP1_ARSIZE ;
+  wire M_AXI_GP1_ARVALID;
+  wire [31:0]M_AXI_GP1_AWADDR;
+  wire [1:0]M_AXI_GP1_AWBURST;
+  wire [3:0]M_AXI_GP1_AWCACHE;
+  wire [11:0]M_AXI_GP1_AWID;
+  wire [3:0]M_AXI_GP1_AWLEN;
+  wire [1:0]M_AXI_GP1_AWLOCK;
+  wire [2:0]M_AXI_GP1_AWPROT;
+  wire [3:0]M_AXI_GP1_AWQOS;
+  wire M_AXI_GP1_AWREADY;
+  wire [1:0]\\^M_AXI_GP1_AWSIZE ;
+  wire M_AXI_GP1_AWVALID;
+  wire [11:0]M_AXI_GP1_BID;
+  wire M_AXI_GP1_BREADY;
+  wire [1:0]M_AXI_GP1_BRESP;
+  wire M_AXI_GP1_BVALID;
+  wire [31:0]M_AXI_GP1_RDATA;
+  wire [11:0]M_AXI_GP1_RID;
+  wire M_AXI_GP1_RLAST;
+  wire M_AXI_GP1_RREADY;
+  wire [1:0]M_AXI_GP1_RRESP;
+  wire M_AXI_GP1_RVALID;
+  wire [31:0]M_AXI_GP1_WDATA;
+  wire [11:0]M_AXI_GP1_WID;
+  wire M_AXI_GP1_WLAST;
+  wire M_AXI_GP1_WREADY;
+  wire [3:0]M_AXI_GP1_WSTRB;
+  wire M_AXI_GP1_WVALID;
+  wire PJTAG_TCK;
+  wire PJTAG_TDI;
+  wire PJTAG_TMS;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_BUSPOW;
+  wire [2:0]SDIO0_BUSVOLT;
+  wire SDIO0_CDN;
+  wire SDIO0_CLK;
+  wire SDIO0_CLK_FB;
+  wire SDIO0_CMD_I;
+  wire SDIO0_CMD_O;
+  wire SDIO0_CMD_T;
+  wire SDIO0_CMD_T_n;
+  wire [3:0]SDIO0_DATA_I;
+  wire [3:0]SDIO0_DATA_O;
+  wire [3:0]SDIO0_DATA_T;
+  wire [3:0]SDIO0_DATA_T_n;
+  wire SDIO0_LED;
+  wire SDIO0_WP;
+  wire SDIO1_BUSPOW;
+  wire [2:0]SDIO1_BUSVOLT;
+  wire SDIO1_CDN;
+  wire SDIO1_CLK;
+  wire SDIO1_CLK_FB;
+  wire SDIO1_CMD_I;
+  wire SDIO1_CMD_O;
+  wire SDIO1_CMD_T;
+  wire SDIO1_CMD_T_n;
+  wire [3:0]SDIO1_DATA_I;
+  wire [3:0]SDIO1_DATA_O;
+  wire [3:0]SDIO1_DATA_T;
+  wire [3:0]SDIO1_DATA_T_n;
+  wire SDIO1_LED;
+  wire SDIO1_WP;
+  wire SPI0_MISO_I;
+  wire SPI0_MISO_O;
+  wire SPI0_MISO_T;
+  wire SPI0_MISO_T_n;
+  wire SPI0_MOSI_I;
+  wire SPI0_MOSI_O;
+  wire SPI0_MOSI_T;
+  wire SPI0_MOSI_T_n;
+  wire SPI0_SCLK_I;
+  wire SPI0_SCLK_O;
+  wire SPI0_SCLK_T;
+  wire SPI0_SCLK_T_n;
+  wire SPI0_SS1_O;
+  wire SPI0_SS2_O;
+  wire SPI0_SS_I;
+  wire SPI0_SS_O;
+  wire SPI0_SS_T;
+  wire SPI0_SS_T_n;
+  wire SPI1_MISO_I;
+  wire SPI1_MISO_O;
+  wire SPI1_MISO_T;
+  wire SPI1_MISO_T_n;
+  wire SPI1_MOSI_I;
+  wire SPI1_MOSI_O;
+  wire SPI1_MOSI_T;
+  wire SPI1_MOSI_T_n;
+  wire SPI1_SCLK_I;
+  wire SPI1_SCLK_O;
+  wire SPI1_SCLK_T;
+  wire SPI1_SCLK_T_n;
+  wire SPI1_SS1_O;
+  wire SPI1_SS2_O;
+  wire SPI1_SS_I;
+  wire SPI1_SS_O;
+  wire SPI1_SS_T;
+  wire SPI1_SS_T_n;
+  wire SRAM_INTIN;
+  wire S_AXI_ACP_ACLK;
+  wire [31:0]S_AXI_ACP_ARADDR;
+  wire [1:0]S_AXI_ACP_ARBURST;
+  wire [3:0]S_AXI_ACP_ARCACHE;
+  wire S_AXI_ACP_ARESETN;
+  wire [2:0]S_AXI_ACP_ARID;
+  wire [3:0]S_AXI_ACP_ARLEN;
+  wire [1:0]S_AXI_ACP_ARLOCK;
+  wire [2:0]S_AXI_ACP_ARPROT;
+  wire [3:0]S_AXI_ACP_ARQOS;
+  wire S_AXI_ACP_ARREADY;
+  wire [2:0]S_AXI_ACP_ARSIZE;
+  wire [4:0]S_AXI_ACP_ARUSER;
+  wire S_AXI_ACP_ARVALID;
+  wire [31:0]S_AXI_ACP_AWADDR;
+  wire [1:0]S_AXI_ACP_AWBURST;
+  wire [3:0]S_AXI_ACP_AWCACHE;
+  wire [2:0]S_AXI_ACP_AWID;
+  wire [3:0]S_AXI_ACP_AWLEN;
+  wire [1:0]S_AXI_ACP_AWLOCK;
+  wire [2:0]S_AXI_ACP_AWPROT;
+  wire [3:0]S_AXI_ACP_AWQOS;
+  wire S_AXI_ACP_AWREADY;
+  wire [2:0]S_AXI_ACP_AWSIZE;
+  wire [4:0]S_AXI_ACP_AWUSER;
+  wire S_AXI_ACP_AWVALID;
+  wire [2:0]S_AXI_ACP_BID;
+  wire S_AXI_ACP_BREADY;
+  wire [1:0]S_AXI_ACP_BRESP;
+  wire S_AXI_ACP_BVALID;
+  wire [63:0]S_AXI_ACP_RDATA;
+  wire [2:0]S_AXI_ACP_RID;
+  wire S_AXI_ACP_RLAST;
+  wire S_AXI_ACP_RREADY;
+  wire [1:0]S_AXI_ACP_RRESP;
+  wire S_AXI_ACP_RVALID;
+  wire [63:0]S_AXI_ACP_WDATA;
+  wire [2:0]S_AXI_ACP_WID;
+  wire S_AXI_ACP_WLAST;
+  wire S_AXI_ACP_WREADY;
+  wire [7:0]S_AXI_ACP_WSTRB;
+  wire S_AXI_ACP_WVALID;
+  wire S_AXI_GP0_ACLK;
+  wire [31:0]S_AXI_GP0_ARADDR;
+  wire [1:0]S_AXI_GP0_ARBURST;
+  wire [3:0]S_AXI_GP0_ARCACHE;
+  wire S_AXI_GP0_ARESETN;
+  wire [5:0]S_AXI_GP0_ARID;
+  wire [3:0]S_AXI_GP0_ARLEN;
+  wire [1:0]S_AXI_GP0_ARLOCK;
+  wire [2:0]S_AXI_GP0_ARPROT;
+  wire [3:0]S_AXI_GP0_ARQOS;
+  wire S_AXI_GP0_ARREADY;
+  wire [2:0]S_AXI_GP0_ARSIZE;
+  wire S_AXI_GP0_ARVALID;
+  wire [31:0]S_AXI_GP0_AWADDR;
+  wire [1:0]S_AXI_GP0_AWBURST;
+  wire [3:0]S_AXI_GP0_AWCACHE;
+  wire [5:0]S_AXI_GP0_AWID;
+  wire [3:0]S_AXI_GP0_AWLEN;
+  wire [1:0]S_AXI_GP0_AWLOCK;
+  wire [2:0]S_AXI_GP0_AWPROT;
+  wire [3:0]S_AXI_GP0_AWQOS;
+  wire S_AXI_GP0_AWREADY;
+  wire [2:0]S_AXI_GP0_AWSIZE;
+  wire S_AXI_GP0_AWVALID;
+  wire [5:0]S_AXI_GP0_BID;
+  wire S_AXI_GP0_BREADY;
+  wire [1:0]S_AXI_GP0_BRESP;
+  wire S_AXI_GP0_BVALID;
+  wire [31:0]S_AXI_GP0_RDATA;
+  wire [5:0]S_AXI_GP0_RID;
+  wire S_AXI_GP0_RLAST;
+  wire S_AXI_GP0_RREADY;
+  wire [1:0]S_AXI_GP0_RRESP;
+  wire S_AXI_GP0_RVALID;
+  wire [31:0]S_AXI_GP0_WDATA;
+  wire [5:0]S_AXI_GP0_WID;
+  wire S_AXI_GP0_WLAST;
+  wire S_AXI_GP0_WREADY;
+  wire [3:0]S_AXI_GP0_WSTRB;
+  wire S_AXI_GP0_WVALID;
+  wire S_AXI_GP1_ACLK;
+  wire [31:0]S_AXI_GP1_ARADDR;
+  wire [1:0]S_AXI_GP1_ARBURST;
+  wire [3:0]S_AXI_GP1_ARCACHE;
+  wire S_AXI_GP1_ARESETN;
+  wire [5:0]S_AXI_GP1_ARID;
+  wire [3:0]S_AXI_GP1_ARLEN;
+  wire [1:0]S_AXI_GP1_ARLOCK;
+  wire [2:0]S_AXI_GP1_ARPROT;
+  wire [3:0]S_AXI_GP1_ARQOS;
+  wire S_AXI_GP1_ARREADY;
+  wire [2:0]S_AXI_GP1_ARSIZE;
+  wire S_AXI_GP1_ARVALID;
+  wire [31:0]S_AXI_GP1_AWADDR;
+  wire [1:0]S_AXI_GP1_AWBURST;
+  wire [3:0]S_AXI_GP1_AWCACHE;
+  wire [5:0]S_AXI_GP1_AWID;
+  wire [3:0]S_AXI_GP1_AWLEN;
+  wire [1:0]S_AXI_GP1_AWLOCK;
+  wire [2:0]S_AXI_GP1_AWPROT;
+  wire [3:0]S_AXI_GP1_AWQOS;
+  wire S_AXI_GP1_AWREADY;
+  wire [2:0]S_AXI_GP1_AWSIZE;
+  wire S_AXI_GP1_AWVALID;
+  wire [5:0]S_AXI_GP1_BID;
+  wire S_AXI_GP1_BREADY;
+  wire [1:0]S_AXI_GP1_BRESP;
+  wire S_AXI_GP1_BVALID;
+  wire [31:0]S_AXI_GP1_RDATA;
+  wire [5:0]S_AXI_GP1_RID;
+  wire S_AXI_GP1_RLAST;
+  wire S_AXI_GP1_RREADY;
+  wire [1:0]S_AXI_GP1_RRESP;
+  wire S_AXI_GP1_RVALID;
+  wire [31:0]S_AXI_GP1_WDATA;
+  wire [5:0]S_AXI_GP1_WID;
+  wire S_AXI_GP1_WLAST;
+  wire S_AXI_GP1_WREADY;
+  wire [3:0]S_AXI_GP1_WSTRB;
+  wire S_AXI_GP1_WVALID;
+  wire S_AXI_HP0_ACLK;
+  wire [31:0]S_AXI_HP0_ARADDR;
+  wire [1:0]S_AXI_HP0_ARBURST;
+  wire [3:0]S_AXI_HP0_ARCACHE;
+  wire S_AXI_HP0_ARESETN;
+  wire [5:0]S_AXI_HP0_ARID;
+  wire [3:0]S_AXI_HP0_ARLEN;
+  wire [1:0]S_AXI_HP0_ARLOCK;
+  wire [2:0]S_AXI_HP0_ARPROT;
+  wire [3:0]S_AXI_HP0_ARQOS;
+  wire S_AXI_HP0_ARREADY;
+  wire [2:0]S_AXI_HP0_ARSIZE;
+  wire S_AXI_HP0_ARVALID;
+  wire [31:0]S_AXI_HP0_AWADDR;
+  wire [1:0]S_AXI_HP0_AWBURST;
+  wire [3:0]S_AXI_HP0_AWCACHE;
+  wire [5:0]S_AXI_HP0_AWID;
+  wire [3:0]S_AXI_HP0_AWLEN;
+  wire [1:0]S_AXI_HP0_AWLOCK;
+  wire [2:0]S_AXI_HP0_AWPROT;
+  wire [3:0]S_AXI_HP0_AWQOS;
+  wire S_AXI_HP0_AWREADY;
+  wire [2:0]S_AXI_HP0_AWSIZE;
+  wire S_AXI_HP0_AWVALID;
+  wire [5:0]S_AXI_HP0_BID;
+  wire S_AXI_HP0_BREADY;
+  wire [1:0]S_AXI_HP0_BRESP;
+  wire S_AXI_HP0_BVALID;
+  wire [2:0]S_AXI_HP0_RACOUNT;
+  wire [7:0]S_AXI_HP0_RCOUNT;
+  wire [63:0]S_AXI_HP0_RDATA;
+  wire S_AXI_HP0_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP0_RID;
+  wire S_AXI_HP0_RLAST;
+  wire S_AXI_HP0_RREADY;
+  wire [1:0]S_AXI_HP0_RRESP;
+  wire S_AXI_HP0_RVALID;
+  wire [5:0]S_AXI_HP0_WACOUNT;
+  wire [7:0]S_AXI_HP0_WCOUNT;
+  wire [63:0]S_AXI_HP0_WDATA;
+  wire [5:0]S_AXI_HP0_WID;
+  wire S_AXI_HP0_WLAST;
+  wire S_AXI_HP0_WREADY;
+  wire S_AXI_HP0_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP0_WSTRB;
+  wire S_AXI_HP0_WVALID;
+  wire S_AXI_HP1_ACLK;
+  wire [31:0]S_AXI_HP1_ARADDR;
+  wire [1:0]S_AXI_HP1_ARBURST;
+  wire [3:0]S_AXI_HP1_ARCACHE;
+  wire S_AXI_HP1_ARESETN;
+  wire [5:0]S_AXI_HP1_ARID;
+  wire [3:0]S_AXI_HP1_ARLEN;
+  wire [1:0]S_AXI_HP1_ARLOCK;
+  wire [2:0]S_AXI_HP1_ARPROT;
+  wire [3:0]S_AXI_HP1_ARQOS;
+  wire S_AXI_HP1_ARREADY;
+  wire [2:0]S_AXI_HP1_ARSIZE;
+  wire S_AXI_HP1_ARVALID;
+  wire [31:0]S_AXI_HP1_AWADDR;
+  wire [1:0]S_AXI_HP1_AWBURST;
+  wire [3:0]S_AXI_HP1_AWCACHE;
+  wire [5:0]S_AXI_HP1_AWID;
+  wire [3:0]S_AXI_HP1_AWLEN;
+  wire [1:0]S_AXI_HP1_AWLOCK;
+  wire [2:0]S_AXI_HP1_AWPROT;
+  wire [3:0]S_AXI_HP1_AWQOS;
+  wire S_AXI_HP1_AWREADY;
+  wire [2:0]S_AXI_HP1_AWSIZE;
+  wire S_AXI_HP1_AWVALID;
+  wire [5:0]S_AXI_HP1_BID;
+  wire S_AXI_HP1_BREADY;
+  wire [1:0]S_AXI_HP1_BRESP;
+  wire S_AXI_HP1_BVALID;
+  wire [2:0]S_AXI_HP1_RACOUNT;
+  wire [7:0]S_AXI_HP1_RCOUNT;
+  wire [63:0]S_AXI_HP1_RDATA;
+  wire S_AXI_HP1_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP1_RID;
+  wire S_AXI_HP1_RLAST;
+  wire S_AXI_HP1_RREADY;
+  wire [1:0]S_AXI_HP1_RRESP;
+  wire S_AXI_HP1_RVALID;
+  wire [5:0]S_AXI_HP1_WACOUNT;
+  wire [7:0]S_AXI_HP1_WCOUNT;
+  wire [63:0]S_AXI_HP1_WDATA;
+  wire [5:0]S_AXI_HP1_WID;
+  wire S_AXI_HP1_WLAST;
+  wire S_AXI_HP1_WREADY;
+  wire S_AXI_HP1_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP1_WSTRB;
+  wire S_AXI_HP1_WVALID;
+  wire S_AXI_HP2_ACLK;
+  wire [31:0]S_AXI_HP2_ARADDR;
+  wire [1:0]S_AXI_HP2_ARBURST;
+  wire [3:0]S_AXI_HP2_ARCACHE;
+  wire S_AXI_HP2_ARESETN;
+  wire [5:0]S_AXI_HP2_ARID;
+  wire [3:0]S_AXI_HP2_ARLEN;
+  wire [1:0]S_AXI_HP2_ARLOCK;
+  wire [2:0]S_AXI_HP2_ARPROT;
+  wire [3:0]S_AXI_HP2_ARQOS;
+  wire S_AXI_HP2_ARREADY;
+  wire [2:0]S_AXI_HP2_ARSIZE;
+  wire S_AXI_HP2_ARVALID;
+  wire [31:0]S_AXI_HP2_AWADDR;
+  wire [1:0]S_AXI_HP2_AWBURST;
+  wire [3:0]S_AXI_HP2_AWCACHE;
+  wire [5:0]S_AXI_HP2_AWID;
+  wire [3:0]S_AXI_HP2_AWLEN;
+  wire [1:0]S_AXI_HP2_AWLOCK;
+  wire [2:0]S_AXI_HP2_AWPROT;
+  wire [3:0]S_AXI_HP2_AWQOS;
+  wire S_AXI_HP2_AWREADY;
+  wire [2:0]S_AXI_HP2_AWSIZE;
+  wire S_AXI_HP2_AWVALID;
+  wire [5:0]S_AXI_HP2_BID;
+  wire S_AXI_HP2_BREADY;
+  wire [1:0]S_AXI_HP2_BRESP;
+  wire S_AXI_HP2_BVALID;
+  wire [2:0]S_AXI_HP2_RACOUNT;
+  wire [7:0]S_AXI_HP2_RCOUNT;
+  wire [63:0]S_AXI_HP2_RDATA;
+  wire S_AXI_HP2_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP2_RID;
+  wire S_AXI_HP2_RLAST;
+  wire S_AXI_HP2_RREADY;
+  wire [1:0]S_AXI_HP2_RRESP;
+  wire S_AXI_HP2_RVALID;
+  wire [5:0]S_AXI_HP2_WACOUNT;
+  wire [7:0]S_AXI_HP2_WCOUNT;
+  wire [63:0]S_AXI_HP2_WDATA;
+  wire [5:0]S_AXI_HP2_WID;
+  wire S_AXI_HP2_WLAST;
+  wire S_AXI_HP2_WREADY;
+  wire S_AXI_HP2_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP2_WSTRB;
+  wire S_AXI_HP2_WVALID;
+  wire S_AXI_HP3_ACLK;
+  wire [31:0]S_AXI_HP3_ARADDR;
+  wire [1:0]S_AXI_HP3_ARBURST;
+  wire [3:0]S_AXI_HP3_ARCACHE;
+  wire S_AXI_HP3_ARESETN;
+  wire [5:0]S_AXI_HP3_ARID;
+  wire [3:0]S_AXI_HP3_ARLEN;
+  wire [1:0]S_AXI_HP3_ARLOCK;
+  wire [2:0]S_AXI_HP3_ARPROT;
+  wire [3:0]S_AXI_HP3_ARQOS;
+  wire S_AXI_HP3_ARREADY;
+  wire [2:0]S_AXI_HP3_ARSIZE;
+  wire S_AXI_HP3_ARVALID;
+  wire [31:0]S_AXI_HP3_AWADDR;
+  wire [1:0]S_AXI_HP3_AWBURST;
+  wire [3:0]S_AXI_HP3_AWCACHE;
+  wire [5:0]S_AXI_HP3_AWID;
+  wire [3:0]S_AXI_HP3_AWLEN;
+  wire [1:0]S_AXI_HP3_AWLOCK;
+  wire [2:0]S_AXI_HP3_AWPROT;
+  wire [3:0]S_AXI_HP3_AWQOS;
+  wire S_AXI_HP3_AWREADY;
+  wire [2:0]S_AXI_HP3_AWSIZE;
+  wire S_AXI_HP3_AWVALID;
+  wire [5:0]S_AXI_HP3_BID;
+  wire S_AXI_HP3_BREADY;
+  wire [1:0]S_AXI_HP3_BRESP;
+  wire S_AXI_HP3_BVALID;
+  wire [2:0]S_AXI_HP3_RACOUNT;
+  wire [7:0]S_AXI_HP3_RCOUNT;
+  wire [63:0]S_AXI_HP3_RDATA;
+  wire S_AXI_HP3_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP3_RID;
+  wire S_AXI_HP3_RLAST;
+  wire S_AXI_HP3_RREADY;
+  wire [1:0]S_AXI_HP3_RRESP;
+  wire S_AXI_HP3_RVALID;
+  wire [5:0]S_AXI_HP3_WACOUNT;
+  wire [7:0]S_AXI_HP3_WCOUNT;
+  wire [63:0]S_AXI_HP3_WDATA;
+  wire [5:0]S_AXI_HP3_WID;
+  wire S_AXI_HP3_WLAST;
+  wire S_AXI_HP3_WREADY;
+  wire S_AXI_HP3_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP3_WSTRB;
+  wire S_AXI_HP3_WVALID;
+  wire TRACE_CLK;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[7] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[7] ;
+  wire TTC0_CLK0_IN;
+  wire TTC0_CLK1_IN;
+  wire TTC0_CLK2_IN;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire TTC1_CLK0_IN;
+  wire TTC1_CLK1_IN;
+  wire TTC1_CLK2_IN;
+  wire TTC1_WAVE0_OUT;
+  wire TTC1_WAVE1_OUT;
+  wire TTC1_WAVE2_OUT;
+  wire UART0_CTSN;
+  wire UART0_DCDN;
+  wire UART0_DSRN;
+  wire UART0_DTRN;
+  wire UART0_RIN;
+  wire UART0_RTSN;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire UART1_CTSN;
+  wire UART1_DCDN;
+  wire UART1_DSRN;
+  wire UART1_DTRN;
+  wire UART1_RIN;
+  wire UART1_RTSN;
+  wire UART1_RX;
+  wire UART1_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire [1:0]USB1_PORT_INDCTL;
+  wire USB1_VBUS_PWRFAULT;
+  wire USB1_VBUS_PWRSELECT;
+  wire WDT_CLK_IN;
+  wire WDT_RST_OUT;
+  wire [14:0]buffered_DDR_Addr;
+  wire [2:0]buffered_DDR_BankAddr;
+  wire buffered_DDR_CAS_n;
+  wire buffered_DDR_CKE;
+  wire buffered_DDR_CS_n;
+  wire buffered_DDR_Clk;
+  wire buffered_DDR_Clk_n;
+  wire [3:0]buffered_DDR_DM;
+  wire [31:0]buffered_DDR_DQ;
+  wire [3:0]buffered_DDR_DQS;
+  wire [3:0]buffered_DDR_DQS_n;
+  wire buffered_DDR_DRSTB;
+  wire buffered_DDR_ODT;
+  wire buffered_DDR_RAS_n;
+  wire buffered_DDR_VRN;
+  wire buffered_DDR_VRP;
+  wire buffered_DDR_WEB;
+  wire [53:0]buffered_MIO;
+  wire buffered_PS_CLK;
+  wire buffered_PS_PORB;
+  wire buffered_PS_SRSTB;
+  wire [63:0]gpio_out_t_n;
+  wire NLW_PS7_i_EMIO'b'ENET0GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
+  wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+
+  assign ENET0_GMII_TXD[7] = \\<const0> ;
+  assign ENET0_GMII_TXD[6] = \\<const0> ;
+  assign ENET0_GMII_TXD[5] = \\<const0> ;
+  assign ENET0_GMII_TXD[4] = \\<const0> ;
+  assign ENET0_GMII_TXD[3] = \\<const0> ;
+  assign ENET0_GMII_TXD[2] = \\<const0> ;
+  assign ENET0_GMII_TXD[1] = \\<const0> ;
+  assign ENET0_GMII_TXD[0] = \\<const0> ;
+  assign ENET0_GMII_TX_EN = \\<const0> ;
+  assign ENET0_GMII_TX_ER = \\<const0> ;
+  assign ENET1_GMII_TXD[7] = \\<const0> ;
+  assign ENET1_GMII_TXD[6] = \\<const0> ;
+  assign ENET1_GMII_TXD[5] = \\<const0> ;
+  assign ENET1_GMII_TXD[4] = \\<const0> ;
+  assign ENET1_GMII_TXD[3] = \\<const0> ;
+  assign ENET1_GMII_TXD[2] = \\<const0> ;
+  assign ENET1_GMII_TXD[1] = \\<const0> ;
+  assign ENET1_GMII_TXD[0] = \\<const0> ;
+  assign ENET1_GMII_TX_EN = \\<const0> ;
+  assign ENET1_GMII_TX_ER = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[1:0] = \\^M_AXI_GP0_ARSIZE [1:0];
+  assign M_AXI_GP0_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_AWSIZE[1:0] = \\^M_AXI_GP0_AWSIZE [1:0];
+  assign M_AXI_GP1_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_ARSIZE[1:0] = \\^M_AXI_GP1_ARSIZE [1:0];
+  assign M_AXI_GP1_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_AWSIZE[1:0] = \\^M_AXI_GP1_AWSIZE [1:0];
+  assign PJTAG_TDO = \\<const0> ;
+  assign TRACE_CLK_OUT = \\<const0> ;
+  assign TRACE_CTL = \\TRACE_CTL_PIPE[0] ;
+  assign TRACE_DATA[1:0] = \\TRACE_DATA_PIPE[0] ;
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CAS_n_BIBUF
+       (.IO(buffered_DDR_CAS_n),
+        .PAD(DDR_CAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CKE_BIBUF
+       (.IO(buffered_DDR_CKE),
+        .PAD(DDR_CKE));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CS_n_BIBUF
+       (.IO(buffered_DDR_CS_n),
+        .PAD(DDR_CS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_BIBUF
+       (.IO(buffered_DDR_Clk),
+        .PAD(DDR_Clk));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_n_BIBUF
+       (.IO(buffered_DDR_Clk_n),
+        .PAD(DDR_Clk_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_DRSTB_BIBUF
+       (.IO(buffered_DDR_DRSTB),
+        .PAD(DDR_DRSTB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_ODT_BIBUF
+       (.IO(buffered_DDR_ODT),
+        .PAD(DDR_ODT));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_RAS_n_BIBUF
+       (.IO(buffered_DDR_RAS_n),
+        .PAD(DDR_RAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRN_BIBUF
+       (.IO(buffered_DDR_VRN),
+        .PAD(DDR_VRN));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRP_BIBUF
+       (.IO(buffered_DDR_VRP),
+        .PAD(DDR_VRP));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_WEB_BIBUF
+       (.IO(buffered_DDR_WEB),
+        .PAD(DDR_WEB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET0_MDIO_T_INST_0
+       (.I0(ENET0_MDIO_T_n),
+        .O(ENET0_MDIO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET1_MDIO_T_INST_0
+       (.I0(ENET1_MDIO_T_n),
+        .O(ENET1_MDIO_T));
+  GND GND
+       (.G(\\<const0> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[0]_INST_0 
+       (.I0(gpio_out_t_n[0]),
+        .O(GPIO_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[10]_INST_0 
+       (.I0(gpio_out_t_n[10]),
+        .O(GPIO_T[10]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[11]_INST_0 
+       (.I0(gpio_out_t_n[11]),
+        .O(GPIO_T[11]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[12]_INST_0 
+       (.I0(gpio_out_t_n[12]),
+        .O(GPIO_T[12]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[13]_INST_0 
+       (.I0(gpio_out_t_n[13]),
+        .O(GPIO_T[13]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[14]_INST_0 
+       (.I0(gpio_out_t_n[14]),
+        .O(GPIO_T[14]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[15]_INST_0 
+       (.I0(gpio_out_t_n[15]),
+        .O(GPIO_T[15]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[16]_INST_0 
+       (.I0(gpio_out_t_n[16]),
+        .O(GPIO_T[16]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[17]_INST_0 
+       (.I0(gpio_out_t_n[17]),
+        .O(GPIO_T[17]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[18]_INST_0 
+       (.I0(gpio_out_t_n[18]),
+        .O(GPIO_T[18]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[19]_INST_0 
+       (.I0(gpio_out_t_n[19]),
+        .O(GPIO_T[19]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[1]_INST_0 
+       (.I0(gpio_out_t_n[1]),
+        .O(GPIO_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[20]_INST_0 
+       (.I0(gpio_out_t_n[20]),
+        .O(GPIO_T[20]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[21]_INST_0 
+       (.I0(gpio_out_t_n[21]),
+        .O(GPIO_T[21]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[22]_INST_0 
+       (.I0(gpio_out_t_n[22]),
+        .O(GPIO_T[22]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[23]_INST_0 
+       (.I0(gpio_out_t_n[23]),
+        .O(GPIO_T[23]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[24]_INST_0 
+       (.I0(gpio_out_t_n[24]),
+        .O(GPIO_T[24]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[25]_INST_0 
+       (.I0(gpio_out_t_n[25]),
+        .O(GPIO_T[25]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[26]_INST_0 
+       (.I0(gpio_out_t_n[26]),
+        .O(GPIO_T[26]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[27]_INST_0 
+       (.I0(gpio_out_t_n[27]),
+        .O(GPIO_T[27]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[28]_INST_0 
+       (.I0(gpio_out_t_n[28]),
+        .O(GPIO_T[28]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[29]_INST_0 
+       (.I0(gpio_out_t_n[29]),
+        .O(GPIO_T[29]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[2]_INST_0 
+       (.I0(gpio_out_t_n[2]),
+        .O(GPIO_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[30]_INST_0 
+       (.I0(gpio_out_t_n[30]),
+        .O(GPIO_T[30]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[31]_INST_0 
+       (.I0(gpio_out_t_n[31]),
+        .O(GPIO_T[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[32]_INST_0 
+       (.I0(gpio_out_t_n[32]),
+        .O(GPIO_T[32]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[33]_INST_0 
+       (.I0(gpio_out_t_n[33]),
+        .O(GPIO_T[33]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[34]_INST_0 
+       (.I0(gpio_out_t_n[34]),
+        .O(GPIO_T[34]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[35]_INST_0 
+       (.I0(gpio_out_t_n[35]),
+        .O(GPIO_T[35]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[36]_INST_0 
+       (.I0(gpio_out_t_n[36]),
+        .O(GPIO_T[36]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[37]_INST_0 
+       (.I0(gpio_out_t_n[37]),
+        .O(GPIO_T[37]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[38]_INST_0 
+       (.I0(gpio_out_t_n[38]),
+        .O(GPIO_T[38]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[39]_INST_0 
+       (.I0(gpio_out_t_n[39]),
+        .O(GPIO_T[39]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[3]_INST_0 
+       (.I0(gpio_out_t_n[3]),
+        .O(GPIO_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[40]_INST_0 
+       (.I0(gpio_out_t_n[40]),
+        .O(GPIO_T[40]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[41]_INST_0 
+       (.I0(gpio_out_t_n[41]),
+        .O(GPIO_T[41]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[42]_INST_0 
+       (.I0(gpio_out_t_n[42]),
+        .O(GPIO_T[42]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[43]_INST_0 
+       (.I0(gpio_out_t_n[43]),
+        .O(GPIO_T[43]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[44]_INST_0 
+       (.I0(gpio_out_t_n[44]),
+        .O(GPIO_T[44]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[45]_INST_0 
+       (.I0(gpio_out_t_n[45]),
+        .O(GPIO_T[45]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[46]_INST_0 
+       (.I0(gpio_out_t_n[46]),
+        .O(GPIO_T[46]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[47]_INST_0 
+       (.I0(gpio_out_t_n[47]),
+        .O(GPIO_T[47]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[48]_INST_0 
+       (.I0(gpio_out_t_n[48]),
+        .O(GPIO_T[48]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[49]_INST_0 
+       (.I0(gpio_out_t_n[49]),
+        .O(GPIO_T[49]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[4]_INST_0 
+       (.I0(gpio_out_t_n[4]),
+        .O(GPIO_T[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[50]_INST_0 
+       (.I0(gpio_out_t_n[50]),
+        .O(GPIO_T[50]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[51]_INST_0 
+       (.I0(gpio_out_t_n[51]),
+        .O(GPIO_T[51]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[52]_INST_0 
+       (.I0(gpio_out_t_n[52]),
+        .O(GPIO_T[52]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[53]_INST_0 
+       (.I0(gpio_out_t_n[53]),
+        .O(GPIO_T[53]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[54]_INST_0 
+       (.I0(gpio_out_t_n[54]),
+        .O(GPIO_T[54]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[55]_INST_0 
+       (.I0(gpio_out_t_n[55]),
+        .O(GPIO_T[55]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[56]_INST_0 
+       (.I0(gpio_out_t_n[56]),
+        .O(GPIO_T[56]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[57]_INST_0 
+       (.I0(gpio_out_t_n[57]),
+        .O(GPIO_T[57]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[58]_INST_0 
+       (.I0(gpio_out_t_n[58]),
+        .O(GPIO_T[58]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[59]_INST_0 
+       (.I0(gpio_out_t_n[59]),
+        .O(GPIO_T[59]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[5]_INST_0 
+       (.I0(gpio_out_t_n[5]),
+        .O(GPIO_T[5]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[60]_INST_0 
+       (.I0(gpio_out_t_n[60]),
+        .O(GPIO_T[60]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[61]_INST_0 
+       (.I0(gpio_out_t_n[61]),
+        .O(GPIO_T[61]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[62]_INST_0 
+       (.I0(gpio_out_t_n[62]),
+        .O(GPIO_T[62]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[63]_INST_0 
+       (.I0(gpio_out_t_n[63]),
+        .O(GPIO_T[63]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[6]_INST_0 
+       (.I0(gpio_out_t_n[6]),
+        .O(GPIO_T[6]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[7]_INST_0 
+       (.I0(gpio_out_t_n[7]),
+        .O(GPIO_T[7]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[8]_INST_0 
+       (.I0(gpio_out_t_n[8]),
+        .O(GPIO_T[8]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[9]_INST_0 
+       (.I0(gpio_out_t_n[9]),
+        .O(GPIO_T[9]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SCL_T_INST_0
+       (.I0(I2C0_SCL_T_n),
+        .O(I2C0_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SDA_T_INST_0
+       (.I0(I2C0_SDA_T_n),
+        .O(I2C0_SDA_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SCL_T_INST_0
+       (.I0(I2C1_SCL_T_n),
+        .O(I2C1_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SDA_T_INST_0
+       (.I0(I2C1_SDA_T_n),
+        .O(I2C1_SDA_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  PS7 PS7_i
+       (.DDRA(buffered_DDR_Addr),
+        .DDRARB(DDR_ARB),
+        .DDRBA(buffered_DDR_BankAddr),
+        .DDRCASB(buffered_DDR_CAS_n),
+        .DDRCKE(buffered_DDR_CKE),
+        .DDRCKN(buffered_DDR_Clk_n),
+        .DDRCKP(buffered_DDR_Clk),
+        .DDRCSB(buffered_DDR_CS_n),
+        .DDRDM(buffered_DDR_DM),
+        .DDRDQ(buffered_DDR_DQ),
+        .DDRDQSN(buffered_DDR_DQS_n),
+        .DDRDQSP(buffered_DDR_DQS),
+        .DDRDRSTB(buffered_DDR_DRSTB),
+        .DDRODT(buffered_DDR_ODT),
+        .DDRRASB(buffered_DDR_RAS_n),
+        .DDRVRN(buffered_DDR_VRN),
+        .DDRVRP(buffered_DDR_VRP),
+        .DDRWEB(buffered_DDR_WEB),
+        .DMA0ACLK(DMA0_ACLK),
+        .DMA0DAREADY(DMA0_DAREADY),
+        .DMA0DATYPE(DMA0_DATYPE),
+        .DMA0DAVALID(DMA0_DAVALID),
+        .DMA0DRLAST(DMA0_DRLAST),
+        .DMA0DRREADY(DMA0_DRREADY),
+        .DMA0DRTYPE(DMA0_DRTYPE),
+        .DMA0DRVALID(DMA0_DRVALID),
+        .DMA0RSTN(DMA0_RSTN),
+        .DMA1ACLK(DMA1_ACLK),
+        .DMA1DAREADY(DMA1_DAREADY),
+        .DMA1DATYPE(DMA1_DATYPE),
+        .DMA1DAVALID(DMA1_DAVALID),
+        .DMA1DRLAST(DMA1_DRLAST),
+        .DMA1DRREADY(DMA1_DRREADY),
+        .DMA1DRTYPE(DMA1_DRTYPE),
+        .DMA1DRVALID(DMA1_DRVALID),
+        .DMA1RSTN(DMA1_RSTN),
+        .DMA2ACLK(DMA2_ACLK),
+        .DMA2DAREADY(DMA2_DAREADY),
+        .DMA2DATYPE(DMA2_DATYPE),
+        .DMA2DAVALID(DMA2_DAVALID),
+        .DMA2DRLAST(DMA2_DRLAST),
+        .DMA2DRREADY(DMA2_DRREADY),
+        .DMA2DRTYPE(DMA2_DRTYPE),
+        .DMA2DRVALID(DMA2_DRVALID),
+        .DMA2RSTN(DMA2_RSTN),
+        .DMA3ACLK(DMA3_ACLK),
+        .DMA3DAREADY(DMA3_DAREADY),
+        .DMA3DATYPE(DMA3_DATYPE),
+        .DMA3DAVALID(DMA3_DAVALID),
+        .DMA3DRLAST(DMA3_DRLAST),
+        .DMA3DRREADY(DMA3_DRREADY),
+        .DMA3DRTYPE(DMA3_DRTYPE),
+        .DMA3DRVALID(DMA3_DRVALID),
+        .DMA3RSTN(DMA3_RSTN),
+        .EMIOCAN0PHYRX(CAN0_PHY_RX),
+        .EMIOCAN0PHYTX(CAN0_PHY_TX),
+        .EMIOCAN1PHYRX(CAN1_PHY_RX),
+        .EMIOCAN1PHYTX(CAN1_PHY_TX),
+        .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+        .EMIOENET0GMIICOL(1\'b0),
+        .EMIOENET0GMIICRS(1\'b0),
+        .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+        .EMIOENET0GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET0GMIIRXDV(1\'b0),
+        .EMIOENET0GMIIRXER(1\'b0),
+        .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+        .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+        .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+        .EMIOENET0MDIOI(ENET0_MDIO_I),
+        .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+        .EMIOENET0MDIOO(ENET0_MDIO_O),
+        .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+        .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+        .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+        .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+        .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+        .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+        .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+        .EMIOENET0SOFRX(ENET0_SOF_RX),
+        .EMIOENET0SOFTX(ENET0_SOF_TX),
+        .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+        .EMIOENET1GMIICOL(1\'b0),
+        .EMIOENET1GMIICRS(1\'b0),
+        .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+        .EMIOENET1GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET1GMIIRXDV(1\'b0),
+        .EMIOENET1GMIIRXER(1\'b0),
+        .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+        .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+        .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+        .EMIOENET1MDIOI(ENET1_MDIO_I),
+        .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+        .EMIOENET1MDIOO(ENET1_MDIO_O),
+        .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+        .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+        .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+        .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+        .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+        .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+        .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+        .EMIOENET1SOFRX(ENET1_SOF_RX),
+        .EMIOENET1SOFTX(ENET1_SOF_TX),
+        .EMIOGPIOI(GPIO_I),
+        .EMIOGPIOO(GPIO_O),
+        .EMIOGPIOTN(gpio_out_t_n),
+        .EMIOI2C0SCLI(I2C0_SCL_I),
+        .EMIOI2C0SCLO(I2C0_SCL_O),
+        .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+        .EMIOI2C0SDAI(I2C0_SDA_I),
+        .EMIOI2C0SDAO(I2C0_SDA_O),
+        .EMIOI2C0SDATN(I2C0_SDA_T_n),
+        .EMIOI2C1SCLI(I2C1_SCL_I),
+        .EMIOI2C1SCLO(I2C1_SCL_O),
+        .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+        .EMIOI2C1SDAI(I2C1_SDA_I),
+        .EMIOI2C1SDAO(I2C1_SDA_O),
+        .EMIOI2C1SDATN(I2C1_SDA_T_n),
+        .EMIOPJTAGTCK(PJTAG_TCK),
+        .EMIOPJTAGTDI(PJTAG_TDI),
+        .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+        .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+        .EMIOPJTAGTMS(PJTAG_TMS),
+        .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+        .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+        .EMIOSDIO0CDN(SDIO0_CDN),
+        .EMIOSDIO0CLK(SDIO0_CLK),
+        .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+        .EMIOSDIO0CMDI(SDIO0_CMD_I),
+        .EMIOSDIO0CMDO(SDIO0_CMD_O),
+        .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+        .EMIOSDIO0DATAI(SDIO0_DATA_I),
+        .EMIOSDIO0DATAO(SDIO0_DATA_O),
+        .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+        .EMIOSDIO0LED(SDIO0_LED),
+        .EMIOSDIO0WP(SDIO0_WP),
+        .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+        .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+        .EMIOSDIO1CDN(SDIO1_CDN),
+        .EMIOSDIO1CLK(SDIO1_CLK),
+        .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+        .EMIOSDIO1CMDI(SDIO1_CMD_I),
+        .EMIOSDIO1CMDO(SDIO1_CMD_O),
+        .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+        .EMIOSDIO1DATAI(SDIO1_DATA_I),
+        .EMIOSDIO1DATAO(SDIO1_DATA_O),
+        .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+        .EMIOSDIO1LED(SDIO1_LED),
+        .EMIOSDIO1WP(SDIO1_WP),
+        .EMIOSPI0MI(SPI0_MISO_I),
+        .EMIOSPI0MO(SPI0_MOSI_O),
+        .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+        .EMIOSPI0SCLKI(SPI0_SCLK_I),
+        .EMIOSPI0SCLKO(SPI0_SCLK_O),
+        .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+        .EMIOSPI0SI(SPI0_MOSI_I),
+        .EMIOSPI0SO(SPI0_MISO_O),
+        .EMIOSPI0SSIN(SPI0_SS_I),
+        .EMIOSPI0SSNTN(SPI0_SS_T_n),
+        .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+        .EMIOSPI0STN(SPI0_MISO_T_n),
+        .EMIOSPI1MI(SPI1_MISO_I),
+        .EMIOSPI1MO(SPI1_MOSI_O),
+        .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+        .EMIOSPI1SCLKI(SPI1_SCLK_I),
+        .EMIOSPI1SCLKO(SPI1_SCLK_O),
+        .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+        .EMIOSPI1SI(SPI1_MOSI_I),
+        .EMIOSPI1SO(SPI1_MISO_O),
+        .EMIOSPI1SSIN(SPI1_SS_I),
+        .EMIOSPI1SSNTN(SPI1_SS_T_n),
+        .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+        .EMIOSPI1STN(SPI1_MISO_T_n),
+        .EMIOSRAMINTIN(SRAM_INTIN),
+        .EMIOTRACECLK(TRACE_CLK),
+        .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+        .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+        .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+        .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+        .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+        .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+        .EMIOUART0CTSN(UART0_CTSN),
+        .EMIOUART0DCDN(UART0_DCDN),
+        .EMIOUART0DSRN(UART0_DSRN),
+        .EMIOUART0DTRN(UART0_DTRN),
+        .EMIOUART0RIN(UART0_RIN),
+        .EMIOUART0RTSN(UART0_RTSN),
+        .EMIOUART0RX(UART0_RX),
+        .EMIOUART0TX(UART0_TX),
+        .EMIOUART1CTSN(UART1_CTSN),
+        .EMIOUART1DCDN(UART1_DCDN),
+        .EMIOUART1DSRN(UART1_DSRN),
+        .EMIOUART1DTRN(UART1_DTRN),
+        .EMIOUART1RIN(UART1_RIN),
+        .EMIOUART1RTSN(UART1_RTSN),
+        .EMIOUART1RX(UART1_RX),
+        .EMIOUART1TX(UART1_TX),
+        .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+        .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+        .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+        .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+        .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+        .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+        .EMIOWDTCLKI(WDT_CLK_IN),
+        .EMIOWDTRSTO(WDT_RST_OUT),
+        .EVENTEVENTI(EVENT_EVENTI),
+        .EVENTEVENTO(EVENT_EVENTO),
+        .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+        .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+        .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+        .FCLKCLKTRIGN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+        .FPGAIDLEN(FPGA_IDLE_N),
+        .FTMDTRACEINATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+        .FTMDTRACEINDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINVALID(1\'b0),
+        .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+        .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+        .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+        .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+        .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+        .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+        .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,IRQ_F2P}),
+        .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+        .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+        .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+        .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+        .MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
+        .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+        .MAXIGP0ARID(M_AXI_GP0_ARID),
+        .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+        .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+        .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+        .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+        .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+        .MAXIGP0ARSIZE(\\^M_AXI_GP0_ARSIZE ),
+        .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+        .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+        .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+        .MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
+        .MAXIGP0AWID(M_AXI_GP0_AWID),
+        .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+        .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+        .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+        .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+        .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+        .MAXIGP0AWSIZE(\\^M_AXI_GP0_AWSIZE ),
+        .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+        .MAXIGP0BID(M_AXI_GP0_BID),
+        .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+        .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+        .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+        .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+        .MAXIGP0RID(M_AXI_GP0_RID),
+        .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+        .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+        .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+        .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+        .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+        .MAXIGP0WID(M_AXI_GP0_WID),
+        .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+        .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+        .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+        .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+        .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+        .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+        .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+        .MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
+        .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+        .MAXIGP1ARID(M_AXI_GP1_ARID),
+        .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+        .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+        .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+        .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+        .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+        .MAXIGP1ARSIZE(\\^M_AXI_GP1_ARSIZE ),
+        .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+        .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+        .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+        .MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
+        .MAXIGP1AWID(M_AXI_GP1_AWID),
+        .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+        .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+        .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+        .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+        .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+        .MAXIGP1AWSIZE(\\^M_AXI_GP1_AWSIZE ),
+        .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+        .MAXIGP1BID(M_AXI_GP1_BID),
+        .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+        .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+        .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+        .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+        .MAXIGP1RID(M_AXI_GP1_RID),
+        .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+        .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+        .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+        .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+        .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+        .MAXIGP1WID(M_AXI_GP1_WID),
+        .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+        .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+        .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+        .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+        .MIO(buffered_MIO),
+        .PSCLK(buffered_PS_CLK),
+        .PSPORB(buffered_PS_PORB),
+        .PSSRSTB(buffered_PS_SRSTB),
+        .SAXIACPACLK(S_AXI_ACP_ACLK),
+        .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+        .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+        .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+        .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+        .SAXIACPARID(S_AXI_ACP_ARID),
+        .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+        .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+        .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+        .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+        .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+        .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+        .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+        .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+        .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+        .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+        .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+        .SAXIACPAWID(S_AXI_ACP_AWID),
+        .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+        .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+        .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+        .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+        .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+        .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+        .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+        .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+        .SAXIACPBID(S_AXI_ACP_BID),
+        .SAXIACPBREADY(S_AXI_ACP_BREADY),
+        .SAXIACPBRESP(S_AXI_ACP_BRESP),
+        .SAXIACPBVALID(S_AXI_ACP_BVALID),
+        .SAXIACPRDATA(S_AXI_ACP_RDATA),
+        .SAXIACPRID(S_AXI_ACP_RID),
+        .SAXIACPRLAST(S_AXI_ACP_RLAST),
+        .SAXIACPRREADY(S_AXI_ACP_RREADY),
+        .SAXIACPRRESP(S_AXI_ACP_RRESP),
+        .SAXIACPRVALID(S_AXI_ACP_RVALID),
+        .SAXIACPWDATA(S_AXI_ACP_WDATA),
+        .SAXIACPWID(S_AXI_ACP_WID),
+        .SAXIACPWLAST(S_AXI_ACP_WLAST),
+        .SAXIACPWREADY(S_AXI_ACP_WREADY),
+        .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+        .SAXIACPWVALID(S_AXI_ACP_WVALID),
+        .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+        .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+        .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+        .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+        .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+        .SAXIGP0ARID(S_AXI_GP0_ARID),
+        .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+        .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+        .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+        .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+        .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+        .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+        .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+        .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+        .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+        .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+        .SAXIGP0AWID(S_AXI_GP0_AWID),
+        .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+        .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+        .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+        .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+        .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+        .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+        .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+        .SAXIGP0BID(S_AXI_GP0_BID),
+        .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+        .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+        .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+        .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+        .SAXIGP0RID(S_AXI_GP0_RID),
+        .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+        .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+        .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+        .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+        .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+        .SAXIGP0WID(S_AXI_GP0_WID),
+        .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+        .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+        .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+        .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+        .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+        .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+        .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+        .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+        .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+        .SAXIGP1ARID(S_AXI_GP1_ARID),
+        .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+        .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+        .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+        .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+        .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+        .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+        .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+        .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+        .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+        .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+        .SAXIGP1AWID(S_AXI_GP1_AWID),
+        .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+        .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+        .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+        .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+        .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+        .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+        .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+        .SAXIGP1BID(S_AXI_GP1_BID),
+        .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+        .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+        .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+        .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+        .SAXIGP1RID(S_AXI_GP1_RID),
+        .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+        .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+        .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+        .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+        .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+        .SAXIGP1WID(S_AXI_GP1_WID),
+        .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+        .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+        .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+        .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+        .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+        .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+        .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+        .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+        .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+        .SAXIHP0ARID(S_AXI_HP0_ARID),
+        .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+        .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+        .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+        .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+        .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+        .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+        .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+        .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+        .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+        .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+        .SAXIHP0AWID(S_AXI_HP0_AWID),
+        .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+        .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+        .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+        .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+        .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+        .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+        .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+        .SAXIHP0BID(S_AXI_HP0_BID),
+        .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+        .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+        .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+        .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+        .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+        .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+        .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+        .SAXIHP0RID(S_AXI_HP0_RID),
+        .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+        .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+        .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+        .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+        .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+        .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+        .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+        .SAXIHP0WID(S_AXI_HP0_WID),
+        .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+        .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+        .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+        .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+        .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+        .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+        .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+        .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+        .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+        .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+        .SAXIHP1ARID(S_AXI_HP1_ARID),
+        .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+        .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+        .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+        .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+        .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+        .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+        .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+        .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+        .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+        .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+        .SAXIHP1AWID(S_AXI_HP1_AWID),
+        .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+        .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+        .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+        .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+        .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+        .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+        .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+        .SAXIHP1BID(S_AXI_HP1_BID),
+        .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+        .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+        .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+        .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+        .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+        .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+        .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+        .SAXIHP1RID(S_AXI_HP1_RID),
+        .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+        .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+        .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+        .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+        .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+        .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+        .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+        .SAXIHP1WID(S_AXI_HP1_WID),
+        .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+        .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+        .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+        .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+        .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+        .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+        .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+        .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+        .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+        .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+        .SAXIHP2ARID(S_AXI_HP2_ARID),
+        .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+        .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+        .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+        .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+        .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+        .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+        .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+        .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+        .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+        .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+        .SAXIHP2AWID(S_AXI_HP2_AWID),
+        .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+        .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+        .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+        .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+        .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+        .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+        .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+        .SAXIHP2BID(S_AXI_HP2_BID),
+        .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+        .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+        .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+        .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+        .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+        .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+        .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+        .SAXIHP2RID(S_AXI_HP2_RID),
+        .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+        .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+        .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+        .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+        .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+        .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+        .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+        .SAXIHP2WID(S_AXI_HP2_WID),
+        .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+        .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+        .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+        .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+        .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+        .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+        .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+        .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+        .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+        .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+        .SAXIHP3ARID(S_AXI_HP3_ARID),
+        .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+        .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+        .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+        .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+        .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+        .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+        .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+        .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+        .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+        .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+        .SAXIHP3AWID(S_AXI_HP3_AWID),
+        .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+        .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+        .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+        .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+        .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+        .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+        .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+        .SAXIHP3BID(S_AXI_HP3_BID),
+        .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+        .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+        .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+        .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+        .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+        .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+        .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+        .SAXIHP3RID(S_AXI_HP3_RID),
+        .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+        .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+        .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+        .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+        .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+        .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+        .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+        .SAXIHP3WID(S_AXI_HP3_WID),
+        .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+        .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+        .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+        .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+        .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_CLK_BIBUF
+       (.IO(buffered_PS_CLK),
+        .PAD(PS_CLK));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_PORB_BIBUF
+       (.IO(buffered_PS_PORB),
+        .PAD(PS_PORB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_SRSTB_BIBUF
+       (.IO(buffered_PS_SRSTB),
+        .PAD(PS_SRSTB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO0_CMD_T_INST_0
+       (.I0(SDIO0_CMD_T_n),
+        .O(SDIO0_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[0]_INST_0 
+       (.I0(SDIO0_DATA_T_n[0]),
+        .O(SDIO0_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[1]_INST_0 
+       (.I0(SDIO0_DATA_T_n[1]),
+        .O(SDIO0_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[2]_INST_0 
+       (.I0(SDIO0_DATA_T_n[2]),
+        .O(SDIO0_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[3]_INST_0 
+       (.I0(SDIO0_DATA_T_n[3]),
+        .O(SDIO0_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO1_CMD_T_INST_0
+       (.I0(SDIO1_CMD_T_n),
+        .O(SDIO1_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[0]_INST_0 
+       (.I0(SDIO1_DATA_T_n[0]),
+        .O(SDIO1_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[1]_INST_0 
+       (.I0(SDIO1_DATA_T_n[1]),
+        .O(SDIO1_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[2]_INST_0 
+       (.I0(SDIO1_DATA_T_n[2]),
+        .O(SDIO1_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[3]_INST_0 
+       (.I0(SDIO1_DATA_T_n[3]),
+        .O(SDIO1_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MISO_T_INST_0
+       (.I0(SPI0_MISO_T_n),
+        .O(SPI0_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MOSI_T_INST_0
+       (.I0(SPI0_MOSI_T_n),
+        .O(SPI0_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SCLK_T_INST_0
+       (.I0(SPI0_SCLK_T_n),
+        .O(SPI0_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SS_T_INST_0
+       (.I0(SPI0_SS_T_n),
+        .O(SPI0_SS_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MISO_T_INST_0
+       (.I0(SPI1_MISO_T_n),
+        .O(SPI1_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MOSI_T_INST_0
+       (.I0(SPI1_MOSI_T_n),
+        .O(SPI1_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SCLK_T_INST_0
+       (.I0(SPI1_SCLK_T_n),
+        .O(SPI1_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SS_T_INST_0
+       (.I0(SPI1_SS_T_n),
+        .O(SPI1_SS_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BUFG \\buffer_fclk_clk_0.FCLK_CLK_0_BUFG 
+       (.I(FCLK_CLK_unbuffered),
+        .O(FCLK_CLK0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[0].MIO_BIBUF 
+       (.IO(buffered_MIO[0]),
+        .PAD(MIO[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[10].MIO_BIBUF 
+       (.IO(buffered_MIO[10]),
+        .PAD(MIO[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[11].MIO_BIBUF 
+       (.IO(buffered_MIO[11]),
+        .PAD(MIO[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[12].MIO_BIBUF 
+       (.IO(buffered_MIO[12]),
+        .PAD(MIO[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[13].MIO_BIBUF 
+       (.IO(buffered_MIO[13]),
+        .PAD(MIO[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[14].MIO_BIBUF 
+       (.IO(buffered_MIO[14]),
+        .PAD(MIO[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[15].MIO_BIBUF 
+       (.IO(buffered_MIO[15]),
+        .PAD(MIO[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[16].MIO_BIBUF 
+       (.IO(buffered_MIO[16]),
+        .PAD(MIO[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[17].MIO_BIBUF 
+       (.IO(buffered_MIO[17]),
+        .PAD(MIO[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[18].MIO_BIBUF 
+       (.IO(buffered_MIO[18]),
+        .PAD(MIO[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[19].MIO_BIBUF 
+       (.IO(buffered_MIO[19]),
+        .PAD(MIO[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[1].MIO_BIBUF 
+       (.IO(buffered_MIO[1]),
+        .PAD(MIO[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[20].MIO_BIBUF 
+       (.IO(buffered_MIO[20]),
+        .PAD(MIO[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[21].MIO_BIBUF 
+       (.IO(buffered_MIO[21]),
+        .PAD(MIO[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[22].MIO_BIBUF 
+       (.IO(buffered_MIO[22]),
+        .PAD(MIO[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[23].MIO_BIBUF 
+       (.IO(buffered_MIO[23]),
+        .PAD(MIO[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[24].MIO_BIBUF 
+       (.IO(buffered_MIO[24]),
+        .PAD(MIO[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[25].MIO_BIBUF 
+       (.IO(buffered_MIO[25]),
+        .PAD(MIO[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[26].MIO_BIBUF 
+       (.IO(buffered_MIO[26]),
+        .PAD(MIO[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[27].MIO_BIBUF 
+       (.IO(buffered_MIO[27]),
+        .PAD(MIO[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[28].MIO_BIBUF 
+       (.IO(buffered_MIO[28]),
+        .PAD(MIO[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[29].MIO_BIBUF 
+       (.IO(buffered_MIO[29]),
+        .PAD(MIO[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[2].MIO_BIBUF 
+       (.IO(buffered_MIO[2]),
+        .PAD(MIO[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[30].MIO_BIBUF 
+       (.IO(buffered_MIO[30]),
+        .PAD(MIO[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[31].MIO_BIBUF 
+       (.IO(buffered_MIO[31]),
+        .PAD(MIO[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[32].MIO_BIBUF 
+       (.IO(buffered_MIO[32]),
+        .PAD(MIO[32]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[33].MIO_BIBUF 
+       (.IO(buffered_MIO[33]),
+        .PAD(MIO[33]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[34].MIO_BIBUF 
+       (.IO(buffered_MIO[34]),
+        .PAD(MIO[34]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[35].MIO_BIBUF 
+       (.IO(buffered_MIO[35]),
+        .PAD(MIO[35]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[36].MIO_BIBUF 
+       (.IO(buffered_MIO[36]),
+        .PAD(MIO[36]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[37].MIO_BIBUF 
+       (.IO(buffered_MIO[37]),
+        .PAD(MIO[37]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[38].MIO_BIBUF 
+       (.IO(buffered_MIO[38]),
+        .PAD(MIO[38]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[39].MIO_BIBUF 
+       (.IO(buffered_MIO[39]),
+        .PAD(MIO[39]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[3].MIO_BIBUF 
+       (.IO(buffered_MIO[3]),
+        .PAD(MIO[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[40].MIO_BIBUF 
+       (.IO(buffered_MIO[40]),
+        .PAD(MIO[40]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[41].MIO_BIBUF 
+       (.IO(buffered_MIO[41]),
+        .PAD(MIO[41]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[42].MIO_BIBUF 
+       (.IO(buffered_MIO[42]),
+        .PAD(MIO[42]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[43].MIO_BIBUF 
+       (.IO(buffered_MIO[43]),
+        .PAD(MIO[43]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[44].MIO_BIBUF 
+       (.IO(buffered_MIO[44]),
+        .PAD(MIO[44]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[45].MIO_BIBUF 
+       (.IO(buffered_MIO[45]),
+        .PAD(MIO[45]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[46].MIO_BIBUF 
+       (.IO(buffered_MIO[46]),
+        .PAD(MIO[46]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[47].MIO_BIBUF 
+       (.IO(buffered_MIO[47]),
+        .PAD(MIO[47]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[48].MIO_BIBUF 
+       (.IO(buffered_MIO[48]),
+        .PAD(MIO[48]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[49].MIO_BIBUF 
+       (.IO(buffered_MIO[49]),
+        .PAD(MIO[49]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[4].MIO_BIBUF 
+       (.IO(buffered_MIO[4]),
+        .PAD(MIO[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[50].MIO_BIBUF 
+       (.IO(buffered_MIO[50]),
+        .PAD(MIO[50]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[51].MIO_BIBUF 
+       (.IO(buffered_MIO[51]),
+        .PAD(MIO[51]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[52].MIO_BIBUF 
+       (.IO(buffered_MIO[52]),
+        .PAD(MIO[52]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[53].MIO_BIBUF 
+       (.IO(buffered_MIO[53]),
+        .PAD(MIO[53]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[5].MIO_BIBUF 
+       (.IO(buffered_MIO[5]),
+        .PAD(MIO[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[6].MIO_BIBUF 
+       (.IO(buffered_MIO[6]),
+        .PAD(MIO[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[7].MIO_BIBUF 
+       (.IO(buffered_MIO[7]),
+        .PAD(MIO[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[8].MIO_BIBUF 
+       (.IO(buffered_MIO[8]),
+        .PAD(MIO[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[9].MIO_BIBUF 
+       (.IO(buffered_MIO[9]),
+        .PAD(MIO[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[0].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[0]),
+        .PAD(DDR_BankAddr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[1].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[1]),
+        .PAD(DDR_BankAddr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[2].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[2]),
+        .PAD(DDR_BankAddr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[0].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[0]),
+        .PAD(DDR_Addr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[10].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[10]),
+        .PAD(DDR_Addr[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[11].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[11]),
+        .PAD(DDR_Addr[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[12].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[12]),
+        .PAD(DDR_Addr[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[13].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[13]),
+        .PAD(DDR_Addr[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[14].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[14]),
+        .PAD(DDR_Addr[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[1].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[1]),
+        .PAD(DDR_Addr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[2].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[2]),
+        .PAD(DDR_Addr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[3].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[3]),
+        .PAD(DDR_Addr[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[4].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[4]),
+        .PAD(DDR_Addr[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[5].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[5]),
+        .PAD(DDR_Addr[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[6].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[6]),
+        .PAD(DDR_Addr[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[7].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[7]),
+        .PAD(DDR_Addr[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[8].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[8]),
+        .PAD(DDR_Addr[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[9].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[9]),
+        .PAD(DDR_Addr[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[0].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[0]),
+        .PAD(DDR_DM[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[1].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[1]),
+        .PAD(DDR_DM[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[2].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[2]),
+        .PAD(DDR_DM[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[3].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[3]),
+        .PAD(DDR_DM[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[0].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[0]),
+        .PAD(DDR_DQ[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[10].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[10]),
+        .PAD(DDR_DQ[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[11].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[11]),
+        .PAD(DDR_DQ[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[12].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[12]),
+        .PAD(DDR_DQ[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[13].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[13]),
+        .PAD(DDR_DQ[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[14].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[14]),
+        .PAD(DDR_DQ[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[15].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[15]),
+        .PAD(DDR_DQ[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[16].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[16]),
+        .PAD(DDR_DQ[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[17].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[17]),
+        .PAD(DDR_DQ[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[18].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[18]),
+        .PAD(DDR_DQ[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[19].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[19]),
+        .PAD(DDR_DQ[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[1].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[1]),
+        .PAD(DDR_DQ[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[20].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[20]),
+        .PAD(DDR_DQ[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[21].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[21]),
+        .PAD(DDR_DQ[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[22].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[22]),
+        .PAD(DDR_DQ[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[23].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[23]),
+        .PAD(DDR_DQ[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[24].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[24]),
+        .PAD(DDR_DQ[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[25].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[25]),
+        .PAD(DDR_DQ[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[26].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[26]),
+        .PAD(DDR_DQ[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[27].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[27]),
+        .PAD(DDR_DQ[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[28].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[28]),
+        .PAD(DDR_DQ[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[29].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[29]),
+        .PAD(DDR_DQ[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[2].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[2]),
+        .PAD(DDR_DQ[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[30].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[30]),
+        .PAD(DDR_DQ[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[31].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[31]),
+        .PAD(DDR_DQ[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[3].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[3]),
+        .PAD(DDR_DQ[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[4].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[4]),
+        .PAD(DDR_DQ[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[5].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[5]),
+        .PAD(DDR_DQ[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[6].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[6]),
+        .PAD(DDR_DQ[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[7].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[7]),
+        .PAD(DDR_DQ[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[8].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[8]),
+        .PAD(DDR_DQ[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[9].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[9]),
+        .PAD(DDR_DQ[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[0].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[0]),
+        .PAD(DDR_DQS_n[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[1].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[1]),
+        .PAD(DDR_DQS_n[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[2].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[2]),
+        .PAD(DDR_DQS_n[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[3].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[3]),
+        .PAD(DDR_DQS_n[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[0].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[0]),
+        .PAD(DDR_DQS[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[1].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[1]),
+        .PAD(DDR_DQS[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[2].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[2]),
+        .PAD(DDR_DQS[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[3].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[3]),
+        .PAD(DDR_DQS[3]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_0
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[0] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_1
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_10
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_11
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_12
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_13
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_14
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_15
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_16
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_17
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_18
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_19
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_2
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_20
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_21
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_22
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_23
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_3
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[7] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_4
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[6] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_5
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[5] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_6
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[4] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_7
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[3] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_8
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[2] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_9
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:35:14 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_2_0_sim_netlist.v
+// Design      : design_1_axi_gpio_2_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
+   (ip2bus_data,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    GPIO_intr,
+    Q,
+    gpio_io_o,
+    gpio_io_t,
+    Read_Reg_Rst,
+    \\Not_Dual.gpio_OE_reg[7]_0 ,
+    s_axi_aclk,
+    \\Not_Dual.gpio_OE_reg[6]_0 ,
+    \\Not_Dual.gpio_OE_reg[5]_0 ,
+    \\Not_Dual.gpio_OE_reg[4]_0 ,
+    \\Not_Dual.gpio_OE_reg[3]_0 ,
+    \\Not_Dual.gpio_OE_reg[2]_0 ,
+    \\Not_Dual.gpio_OE_reg[1]_0 ,
+    GPIO_DBus_i,
+    bus2ip_reset,
+    bus2ip_cs,
+    gpio_io_i,
+    E,
+    D,
+    bus2ip_rnw_i_reg);
+  output [7:0]ip2bus_data;
+  output GPIO_xferAck_i;
+  output gpio_xferAck_Reg;
+  output GPIO_intr;
+  output [7:0]Q;
+  output [7:0]gpio_io_o;
+  output [7:0]gpio_io_t;
+  input Read_Reg_Rst;
+  input \\Not_Dual.gpio_OE_reg[7]_0 ;
+  input s_axi_aclk;
+  input \\Not_Dual.gpio_OE_reg[6]_0 ;
+  input \\Not_Dual.gpio_OE_reg[5]_0 ;
+  input \\Not_Dual.gpio_OE_reg[4]_0 ;
+  input \\Not_Dual.gpio_OE_reg[3]_0 ;
+  input \\Not_Dual.gpio_OE_reg[2]_0 ;
+  input \\Not_Dual.gpio_OE_reg[1]_0 ;
+  input [0:0]GPIO_DBus_i;
+  input bus2ip_reset;
+  input [0:0]bus2ip_cs;
+  input [7:0]gpio_io_i;
+  input [0:0]E;
+  input [7:0]D;
+  input [0:0]bus2ip_rnw_i_reg;
+
+  wire [7:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_intr;
+  wire GPIO_xferAck_i;
+  wire \\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ;
+  wire \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ;
+  wire \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ;
+  wire \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[7] ;
+  wire \\Not_Dual.gpio_OE_reg[1]_0 ;
+  wire \\Not_Dual.gpio_OE_reg[2]_0 ;
+  wire \\Not_Dual.gpio_OE_reg[3]_0 ;
+  wire \\Not_Dual.gpio_OE_reg[4]_0 ;
+  wire \\Not_Dual.gpio_OE_reg[5]_0 ;
+  wire \\Not_Dual.gpio_OE_reg[6]_0 ;
+  wire \\Not_Dual.gpio_OE_reg[7]_0 ;
+  wire [7:0]Q;
+  wire Read_Reg_Rst;
+  wire [0:0]bus2ip_cs;
+  wire bus2ip_reset;
+  wire [0:0]bus2ip_rnw_i_reg;
+  wire [0:7]gpio_data_in_xor;
+  wire [7:0]gpio_io_i;
+  wire [0:7]gpio_io_i_d2;
+  wire [7:0]gpio_io_o;
+  wire [7:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire iGPIO_xferAck;
+  wire [7:0]ip2bus_data;
+  wire or_ints;
+  wire p_1_in;
+  wire p_2_in;
+  wire p_3_in;
+  wire p_4_in;
+  wire p_5_in;
+  wire s_axi_aclk;
+
+  LUT5 #(
+    .INIT(32\'hFFFFFFFE)) 
+    \\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1 
+       (.I0(p_2_in),
+        .I1(p_3_in),
+        .I2(p_1_in),
+        .I3(\\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
+        .I4(\\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ),
+        .O(or_ints));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2 
+       (.I0(p_5_in),
+        .I1(p_4_in),
+        .I2(\\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
+        .I3(\\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[7] ),
+        .O(\\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ));
+  FDRE \\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(or_ints),
+        .Q(GPIO_intr),
+        .R(bus2ip_reset));
+  FDRE \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[0]),
+        .Q(\\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
+        .R(bus2ip_reset));
+  FDRE \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[1]),
+        .Q(\\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
+        .R(bus2ip_reset));
+  FDRE \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[2]),
+        .Q(p_1_in),
+        .R(bus2ip_reset));
+  FDRE \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[3]),
+        .Q(p_2_in),
+        .R(bus2ip_reset));
+  FDRE \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[4]),
+        .Q(p_3_in),
+        .R(bus2ip_reset));
+  FDRE \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[5]),
+        .Q(p_4_in),
+        .R(bus2ip_reset));
+  FDRE \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[6]),
+        .Q(p_5_in),
+        .R(bus2ip_reset));
+  FDRE \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[7]),
+        .Q(\\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[7] ),
+        .R(bus2ip_reset));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \\Not_Dual.INPUT_DOUBLE_REGS3 
+       (.D({gpio_data_in_xor[0],gpio_data_in_xor[1],gpio_data_in_xor[2],gpio_data_in_xor[3],gpio_data_in_xor[4],gpio_data_in_xor[5],gpio_data_in_xor[6],gpio_data_in_xor[7]}),
+        .Q(Q),
+        .gpio_io_i(gpio_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7]}));
+  FDRE \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[24] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus_i),
+        .Q(ip2bus_data[7]),
+        .R(Read_Reg_Rst));
+  FDRE \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_OE_reg[1]_0 ),
+        .Q(ip2bus_data[6]),
+        .R(Read_Reg_Rst));
+  FDRE \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_OE_reg[2]_0 ),
+        .Q(ip2bus_data[5]),
+        .R(Read_Reg_Rst));
+  FDRE \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_OE_reg[3]_0 ),
+        .Q(ip2bus_data[4]),
+        .R(Read_Reg_Rst));
+  FDRE \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_OE_reg[4]_0 ),
+        .Q(ip2bus_data[3]),
+        .R(Read_Reg_Rst));
+  FDRE \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_OE_reg[5]_0 ),
+        .Q(ip2bus_data[2]),
+        .R(Read_Reg_Rst));
+  FDRE \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_OE_reg[6]_0 ),
+        .Q(ip2bus_data[1]),
+        .R(Read_Reg_Rst));
+  FDRE \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_OE_reg[7]_0 ),
+        .Q(ip2bus_data[0]),
+        .R(Read_Reg_Rst));
+  FDRE \\Not_Dual.gpio_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[0]),
+        .Q(Q[7]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[1]),
+        .Q(Q[6]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[2]),
+        .Q(Q[5]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[3]),
+        .Q(Q[4]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[4]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[5]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[6]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[7]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[7]),
+        .Q(gpio_io_o[7]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[6]),
+        .Q(gpio_io_o[6]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[5]),
+        .Q(gpio_io_o[5]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[4]),
+        .Q(gpio_io_o[4]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[3]),
+        .Q(gpio_io_o[3]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[2]),
+        .Q(gpio_io_o[2]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[1]),
+        .Q(gpio_io_o[1]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[0]),
+        .Q(gpio_io_o[0]),
+        .R(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(D[7]),
+        .Q(gpio_io_t[7]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(D[6]),
+        .Q(gpio_io_t[6]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(D[5]),
+        .Q(gpio_io_t[5]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(D[4]),
+        .Q(gpio_io_t[4]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(D[3]),
+        .Q(gpio_io_t[3]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(D[2]),
+        .Q(gpio_io_t[2]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(D[1]),
+        .Q(gpio_io_t[1]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(D[0]),
+        .Q(gpio_io_t[0]),
+        .S(bus2ip_reset));
+  FDRE gpio_xferAck_Reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_xferAck_i),
+        .Q(gpio_xferAck_Reg),
+        .R(bus2ip_reset));
+  LUT3 #(
+    .INIT(8\'h10)) 
+    iGPIO_xferAck_i_1
+       (.I0(gpio_xferAck_Reg),
+        .I1(GPIO_xferAck_i),
+        .I2(bus2ip_cs),
+        .O(iGPIO_xferAck));
+  FDRE iGPIO_xferAck_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(iGPIO_xferAck),
+        .Q(GPIO_xferAck_i),
+        .R(bus2ip_reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
+   (\\ip2bus_data_i_D1_reg[0] ,
+    \\Not_Dual.gpio_Data_Out_reg[7] ,
+    \\ip_irpt_enable_reg_reg[0] ,
+    s_axi_arready,
+    s_axi_wready,
+    D,
+    \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ,
+    \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ,
+    GPIO_DBus_i,
+    E,
+    \\Not_Dual.gpio_Data_Out_reg[0] ,
+    \\ip2bus_data_i_D1_reg[0]_0 ,
+    intr2bus_rdack0,
+    irpt_rdack,
+    irpt_wrack,
+    interrupt_wrce_strb,
+    Read_Reg_Rst,
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
+    intr_rd_ce_or_reduce,
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
+    intr_wr_ce_or_reduce,
+    \\ip_irpt_enable_reg_reg[0]_0 ,
+    ipif_glbl_irpt_enable_reg_reg,
+    start2,
+    s_axi_aclk,
+    s_axi_aresetn,
+    Q,
+    is_read,
+    ip2bus_rdack_i_D1,
+    is_write_reg,
+    ip2bus_wrack_i_D1,
+    s_axi_wdata,
+    \\bus2ip_addr_i_reg[8] ,
+    gpio_io_t,
+    \\Not_Dual.gpio_Data_In_reg[0] ,
+    bus2ip_rnw_i_reg,
+    bus2ip_reset,
+    p_0_in,
+    irpt_rdack_d1,
+    irpt_wrack_d1,
+    ip2bus_data,
+    p_3_in,
+    p_1_in,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    ip2Bus_RdAck_intr_reg_hole_d1,
+    ip2Bus_WrAck_intr_reg_hole_d1);
+  output \\ip2bus_data_i_D1_reg[0] ;
+  output \\Not_Dual.gpio_Data_Out_reg[7] ;
+  output \\ip_irpt_enable_reg_reg[0] ;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [7:0]D;
+  output \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
+  output \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
+  output [0:0]GPIO_DBus_i;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_Data_Out_reg[0] ;
+  output [1:0]\\ip2bus_data_i_D1_reg[0]_0 ;
+  output intr2bus_rdack0;
+  output irpt_rdack;
+  output irpt_wrack;
+  output interrupt_wrce_strb;
+  output Read_Reg_Rst;
+  output \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  output intr_rd_ce_or_reduce;
+  output \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  output intr_wr_ce_or_reduce;
+  output \\ip_irpt_enable_reg_reg[0]_0 ;
+  output ipif_glbl_irpt_enable_reg_reg;
+  input start2;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [3:0]Q;
+  input is_read;
+  input ip2bus_rdack_i_D1;
+  input is_write_reg;
+  input ip2bus_wrack_i_D1;
+  input [15:0]s_axi_wdata;
+  input [6:0]\\bus2ip_addr_i_reg[8] ;
+  input [7:0]gpio_io_t;
+  input [7:0]\\Not_Dual.gpio_Data_In_reg[0] ;
+  input bus2ip_rnw_i_reg;
+  input bus2ip_reset;
+  input [0:0]p_0_in;
+  input irpt_rdack_d1;
+  input irpt_wrack_d1;
+  input [0:0]ip2bus_data;
+  input [0:0]p_3_in;
+  input [0:0]p_1_in;
+  input GPIO_xferAck_i;
+  input gpio_xferAck_Reg;
+  input ip2Bus_RdAck_intr_reg_hole_d1;
+  input ip2Bus_WrAck_intr_reg_hole_d1;
+
+  wire Bus_RNW_reg_i_1_n_0;
+  wire [7:0]D;
+  wire [0:0]E;
+  wire \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ;
+  wire \\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
+  wire \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
+  wire [7:0]\\Not_Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Not_Dual.gpio_Data_Out_reg[0] ;
+  wire \\Not_Dual.gpio_Data_Out_reg[7] ;
+  wire [3:0]Q;
+  wire Read_Reg_Rst;
+  wire [6:0]\\bus2ip_addr_i_reg[8] ;
+  wire bus2ip_reset;
+  wire bus2ip_rnw_i_reg;
+  wire [7:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack0;
+  wire intr_rd_ce_or_reduce;
+  wire intr_wr_ce_or_reduce;
+  wire ip2Bus_RdAck_intr_reg_hole_d1;
+  wire ip2Bus_WrAck_intr_reg_hole_d1;
+  wire [0:0]ip2bus_data;
+  wire \\ip2bus_data_i_D1_reg[0] ;
+  wire [1:0]\\ip2bus_data_i_D1_reg[0]_0 ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire \\ip_irpt_enable_reg_reg[0] ;
+  wire \\ip_irpt_enable_reg_reg[0]_0 ;
+  wire ipif_glbl_irpt_enable_reg_reg;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire is_read;
+  wire is_write_reg;
+  wire [0:0]p_0_in;
+  wire p_10_in;
+  wire p_10_out;
+  wire p_11_in;
+  wire p_11_out;
+  wire p_12_in;
+  wire p_12_out;
+  wire p_13_in;
+  wire p_13_out;
+  wire p_14_in;
+  wire p_14_out;
+  wire p_15_in;
+  wire p_15_out;
+  wire p_16_in;
+  wire [0:0]p_1_in;
+  wire p_2_in;
+  wire [0:0]p_3_in;
+  wire p_3_in_0;
+  wire p_4_in;
+  wire p_4_out;
+  wire p_5_in;
+  wire p_5_out;
+  wire p_6_in;
+  wire p_6_out;
+  wire p_7_in;
+  wire p_7_out;
+  wire p_8_out;
+  wire p_9_in;
+  wire p_9_out;
+  wire pselect_hit_i_1;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire [15:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire start2;
+
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    Bus_RNW_reg_i_1
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(start2),
+        .I2(\\ip_irpt_enable_reg_reg[0] ),
+        .O(Bus_RNW_reg_i_1_n_0));
+  FDRE Bus_RNW_reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_i_1_n_0),
+        .Q(\\ip_irpt_enable_reg_reg[0] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h0040000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_9_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_9_out),
+        .Q(p_10_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h4000000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_8_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_8_out),
+        .Q(p_9_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0004000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_7_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_7_out),
+        .Q(\\ip2bus_data_i_D1_reg[0] ),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0400000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_6_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_6_out),
+        .Q(p_7_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0008000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_5_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_5_out),
+        .Q(p_6_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0800000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_4_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_4_out),
+        .Q(p_5_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0008000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ),
+        .Q(p_4_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0800000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(\\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(\\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ),
+        .Q(p_3_in_0),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0080000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(\\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(\\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ),
+        .Q(p_2_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT3 #(
+    .INIT(8\'hFD)) 
+    \\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1 
+       (.I0(s_axi_aresetn),
+        .I1(s_axi_arready),
+        .I2(s_axi_wready),
+        .O(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h8000000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_15_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_15_out),
+        .Q(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0001000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(\\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(\\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
+        .Q(p_16_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0100000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_14_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_14_out),
+        .Q(p_15_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0002000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_13_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_13_out),
+        .Q(p_14_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0200000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_12_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_12_out),
+        .Q(p_13_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0004000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_11_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_11_out),
+        .Q(p_12_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0400000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_10_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_10_out),
+        .Q(p_11_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'hFE00)) 
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1 
+       (.I0(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
+        .I1(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
+        .I2(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
+        .I3(\\ip_irpt_enable_reg_reg[0] ),
+        .O(intr_rd_ce_or_reduce));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h00FE0000)) 
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1 
+       (.I0(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
+        .I1(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
+        .I2(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
+        .I3(ip2Bus_RdAck_intr_reg_hole_d1),
+        .I4(\\ip_irpt_enable_reg_reg[0] ),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT4 #(
+    .INIT(16\'h00FE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1 
+       (.I0(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
+        .I1(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
+        .I2(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
+        .I3(\\ip_irpt_enable_reg_reg[0] ),
+        .O(intr_wr_ce_or_reduce));
+  LUT5 #(
+    .INIT(32\'hFFFFFFFE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2 
+       (.I0(p_16_in),
+        .I1(p_2_in),
+        .I2(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
+        .I3(p_14_in),
+        .I4(p_15_in),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3 
+       (.I0(p_12_in),
+        .I1(p_13_in),
+        .I2(p_10_in),
+        .I3(p_11_in),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4 
+       (.I0(p_5_in),
+        .I1(p_7_in),
+        .I2(p_3_in_0),
+        .I3(p_4_in),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'h000000FE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1 
+       (.I0(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
+        .I1(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
+        .I2(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
+        .I3(\\ip_irpt_enable_reg_reg[0] ),
+        .I4(ip2Bus_WrAck_intr_reg_hole_d1),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ));
+  LUT6 #(
+    .INIT(64\'h0000000000000002)) 
+    \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1 
+       (.I0(start2),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\bus2ip_addr_i_reg[8] [4]),
+        .I3(\\bus2ip_addr_i_reg[8] [5]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .I5(\\bus2ip_addr_i_reg[8] [2]),
+        .O(pselect_hit_i_1));
+  FDRE \\MEM_DECODE_GEN[0].cs_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(pselect_hit_i_1),
+        .Q(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[24]_i_1 
+       (.I0(gpio_io_t[7]),
+        .I1(\\Not_Dual.gpio_Data_In_reg[0] [7]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(GPIO_DBus_i));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[25]_i_1 
+       (.I0(gpio_io_t[6]),
+        .I1(\\Not_Dual.gpio_Data_In_reg[0] [6]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[26]_i_1 
+       (.I0(gpio_io_t[5]),
+        .I1(\\Not_Dual.gpio_Data_In_reg[0] [5]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[27]_i_1 
+       (.I0(gpio_io_t[4]),
+        .I1(\\Not_Dual.gpio_Data_In_reg[0] [4]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[28]_i_1 
+       (.I0(gpio_io_t[3]),
+        .I1(\\Not_Dual.gpio_Data_In_reg[0] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(\\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[29]_i_1 
+       (.I0(gpio_io_t[2]),
+        .I1(\\Not_Dual.gpio_Data_In_reg[0] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(\\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[30]_i_1 
+       (.I0(gpio_io_t[1]),
+        .I1(\\Not_Dual.gpio_Data_In_reg[0] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(\\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ));
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I1(GPIO_xferAck_i),
+        .I2(bus2ip_rnw_i_reg),
+        .I3(gpio_xferAck_Reg),
+        .O(Read_Reg_Rst));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[31]_i_2 
+       (.I0(gpio_io_t[0]),
+        .I1(\\Not_Dual.gpio_Data_In_reg[0] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(\\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00000100)) 
+    \\Not_Dual.gpio_Data_Out[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(bus2ip_reset),
+        .O(\\Not_Dual.gpio_Data_Out_reg[0] ));
+  LUT4 #(
+    .INIT(16\'hBA8A)) 
+    \\Not_Dual.gpio_Data_Out[0]_i_2 
+       (.I0(s_axi_wdata[15]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I3(s_axi_wdata[7]),
+        .O(D[7]));
+  LUT4 #(
+    .INIT(16\'hBA8A)) 
+    \\Not_Dual.gpio_Data_Out[1]_i_1 
+       (.I0(s_axi_wdata[14]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I3(s_axi_wdata[6]),
+        .O(D[6]));
+  LUT4 #(
+    .INIT(16\'hBA8A)) 
+    \\Not_Dual.gpio_Data_Out[2]_i_1 
+       (.I0(s_axi_wdata[13]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I3(s_axi_wdata[5]),
+        .O(D[5]));
+  LUT4 #(
+    .INIT(16\'hBA8A)) 
+    \\Not_Dual.gpio_Data_Out[3]_i_1 
+       (.I0(s_axi_wdata[12]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I3(s_axi_wdata[4]),
+        .O(D[4]));
+  LUT4 #(
+    .INIT(16\'hBA8A)) 
+    \\Not_Dual.gpio_Data_Out[4]_i_1 
+       (.I0(s_axi_wdata[11]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I3(s_axi_wdata[3]),
+        .O(D[3]));
+  LUT4 #(
+    .INIT(16\'hBA8A)) 
+    \\Not_Dual.gpio_Data_Out[5]_i_1 
+       (.I0(s_axi_wdata[10]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I3(s_axi_wdata[2]),
+        .O(D[2]));
+  LUT4 #(
+    .INIT(16\'hBA8A)) 
+    \\Not_Dual.gpio_Data_Out[6]_i_1 
+       (.I0(s_axi_wdata[9]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I3(s_axi_wdata[1]),
+        .O(D[1]));
+  LUT4 #(
+    .INIT(16\'hBA8A)) 
+    \\Not_Dual.gpio_Data_Out[7]_i_1 
+       (.I0(s_axi_wdata[8]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I3(s_axi_wdata[0]),
+        .O(D[0]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF01000000)) 
+    \\Not_Dual.gpio_OE[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(bus2ip_reset),
+        .O(E));
+  LUT5 #(
+    .INIT(32\'h44444440)) 
+    intr2bus_rdack_i_1
+       (.I0(irpt_rdack_d1),
+        .I1(\\ip_irpt_enable_reg_reg[0] ),
+        .I2(p_9_in),
+        .I3(\\ip2bus_data_i_D1_reg[0] ),
+        .I4(p_6_in),
+        .O(intr2bus_rdack0));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h000000FE)) 
+    intr2bus_wrack_i_1
+       (.I0(p_9_in),
+        .I1(\\ip2bus_data_i_D1_reg[0] ),
+        .I2(p_6_in),
+        .I3(\\ip_irpt_enable_reg_reg[0] ),
+        .I4(irpt_wrack_d1),
+        .O(interrupt_wrce_strb));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00000080)) 
+    \\ip2bus_data_i_D1[0]_i_1 
+       (.I0(p_0_in),
+        .I1(p_9_in),
+        .I2(\\ip_irpt_enable_reg_reg[0] ),
+        .I3(p_6_in),
+        .I4(\\ip2bus_data_i_D1_reg[0] ),
+        .O(\\ip2bus_data_i_D1_reg[0]_0 [1]));
+  LUT6 #(
+    .INIT(64\'hEEEEAAAAFAAAAAAA)) 
+    \\ip2bus_data_i_D1[31]_i_1 
+       (.I0(ip2bus_data),
+        .I1(p_3_in),
+        .I2(p_1_in),
+        .I3(p_6_in),
+        .I4(\\ip_irpt_enable_reg_reg[0] ),
+        .I5(\\ip2bus_data_i_D1_reg[0] ),
+        .O(\\ip2bus_data_i_D1_reg[0]_0 [0]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\ip_irpt_enable_reg[0]_i_1 
+       (.I0(s_axi_wdata[0]),
+        .I1(p_6_in),
+        .I2(\\ip_irpt_enable_reg_reg[0] ),
+        .I3(p_1_in),
+        .O(\\ip_irpt_enable_reg_reg[0]_0 ));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    ipif_glbl_irpt_enable_reg_i_1
+       (.I0(s_axi_wdata[15]),
+        .I1(p_9_in),
+        .I2(\\ip_irpt_enable_reg_reg[0] ),
+        .I3(p_0_in),
+        .O(ipif_glbl_irpt_enable_reg_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT4 #(
+    .INIT(16\'hFE00)) 
+    irpt_rdack_d1_i_1
+       (.I0(p_9_in),
+        .I1(\\ip2bus_data_i_D1_reg[0] ),
+        .I2(p_6_in),
+        .I3(\\ip_irpt_enable_reg_reg[0] ),
+        .O(irpt_rdack));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT4 #(
+    .INIT(16\'h00FE)) 
+    irpt_wrack_d1_i_1
+       (.I0(p_9_in),
+        .I1(\\ip2bus_data_i_D1_reg[0] ),
+        .I2(p_6_in),
+        .I3(\\ip_irpt_enable_reg_reg[0] ),
+        .O(irpt_wrack));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00020000)) 
+    s_axi_arready_INST_0
+       (.I0(Q[3]),
+        .I1(Q[2]),
+        .I2(Q[1]),
+        .I3(Q[0]),
+        .I4(is_read),
+        .I5(ip2bus_rdack_i_D1),
+        .O(s_axi_arready));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00020000)) 
+    s_axi_wready_INST_0
+       (.I0(Q[3]),
+        .I1(Q[2]),
+        .I2(Q[1]),
+        .I3(Q[0]),
+        .I4(is_write_reg),
+        .I5(ip2bus_wrack_i_D1),
+        .O(s_axi_wready));
+endmodule
+
+(* C_ALL_INPUTS = ""0"" *) (* C_ALL_INPUTS_2 = ""0"" *) (* C_ALL_OUTPUTS = ""0"" *) 
+(* C_ALL_OUTPUTS_2 = ""0"" *) (* C_DOUT_DEFAULT = ""0"" *) (* C_DOUT_DEFAULT_2 = ""0"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_GPIO2_WIDTH = ""32"" *) (* C_GPIO_WIDTH = ""8"" *) 
+(* C_INTERRUPT_PRESENT = ""1"" *) (* C_IS_DUAL = ""0"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* C_TRI_DEFAULT = ""-1"" *) (* C_TRI_DEFAULT_2 = ""-1"" *) 
+(* downgradeipidentifiedwarnings = ""yes"" *) (* ip_group = ""LOGICORE"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_i,
+    gpio2_io_o,
+    gpio2_io_t);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rst"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* sigis = ""INTR_LEVEL_HIGH"" *) output ip2intc_irpt;
+  input [7:0]gpio_io_i;
+  output [7:0]gpio_io_o;
+  output [7:0]gpio_io_t;
+  input [31:0]gpio2_io_i;
+  output [31:0]gpio2_io_o;
+  output [31:0]gpio2_io_t;
+
+  wire \\<const0> ;
+  wire \\<const1> ;
+  wire AXI_LITE_IPIF_I_n_16;
+  wire AXI_LITE_IPIF_I_n_17;
+  wire AXI_LITE_IPIF_I_n_18;
+  wire AXI_LITE_IPIF_I_n_19;
+  wire AXI_LITE_IPIF_I_n_20;
+  wire AXI_LITE_IPIF_I_n_21;
+  wire AXI_LITE_IPIF_I_n_22;
+  wire AXI_LITE_IPIF_I_n_24;
+  wire AXI_LITE_IPIF_I_n_25;
+  wire AXI_LITE_IPIF_I_n_33;
+  wire AXI_LITE_IPIF_I_n_35;
+  wire AXI_LITE_IPIF_I_n_37;
+  wire AXI_LITE_IPIF_I_n_38;
+  wire [0:7]DBus_Reg;
+  wire [24:24]GPIO_DBus_i;
+  wire GPIO_intr;
+  wire GPIO_xferAck_i;
+  wire IP2INTC_Irpt_i;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ;
+  wire Read_Reg_Rst;
+  wire [1:1]bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_reset_i_1_n_0;
+  wire bus2ip_rnw;
+  wire [0:7]gpio_Data_In;
+  wire [7:0]gpio_io_i;
+  wire [7:0]gpio_io_o;
+  wire [7:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack0;
+  wire intr_rd_ce_or_reduce;
+  wire intr_wr_ce_or_reduce;
+  wire ip2Bus_RdAck_intr_reg_hole;
+  wire ip2Bus_RdAck_intr_reg_hole_d1;
+  wire ip2Bus_WrAck_intr_reg_hole;
+  wire ip2Bus_WrAck_intr_reg_hole_d1;
+  wire [24:31]ip2bus_data;
+  wire [31:31]ip2bus_data_i;
+  wire [0:31]ip2bus_data_i_D1;
+  wire ip2bus_rdack_i;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i;
+  wire ip2bus_wrack_i_D1;
+  wire ip2intc_irpt;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire [31:31]p_0_in;
+  wire [0:0]p_0_out;
+  wire [0:0]p_1_in;
+  wire [0:0]p_3_in;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rst"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [31:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  assign gpio2_io_o[31] = \\<const0> ;
+  assign gpio2_io_o[30] = \\<const0> ;
+  assign gpio2_io_o[29] = \\<const0> ;
+  assign gpio2_io_o[28] = \\<const0> ;
+  assign gpio2_io_o[27] = \\<const0> ;
+  assign gpio2_io_o[26] = \\<const0> ;
+  assign gpio2_io_o[25] = \\<const0> ;
+  assign gpio2_io_o[24] = \\<const0> ;
+  assign gpio2_io_o[23] = \\<const0> ;
+  assign gpio2_io_o[22] = \\<const0> ;
+  assign gpio2_io_o[21] = \\<const0> ;
+  assign gpio2_io_o[20] = \\<const0> ;
+  assign gpio2_io_o[19] = \\<const0> ;
+  assign gpio2_io_o[18] = \\<const0> ;
+  assign gpio2_io_o[17] = \\<const0> ;
+  assign gpio2_io_o[16] = \\<const0> ;
+  assign gpio2_io_o[15] = \\<const0> ;
+  assign gpio2_io_o[14] = \\<const0> ;
+  assign gpio2_io_o[13] = \\<const0> ;
+  assign gpio2_io_o[12] = \\<const0> ;
+  assign gpio2_io_o[11] = \\<const0> ;
+  assign gpio2_io_o[10] = \\<const0> ;
+  assign gpio2_io_o[9] = \\<const0> ;
+  assign gpio2_io_o[8] = \\<const0> ;
+  assign gpio2_io_o[7] = \\<const0> ;
+  assign gpio2_io_o[6] = \\<const0> ;
+  assign gpio2_io_o[5] = \\<const0> ;
+  assign gpio2_io_o[4] = \\<const0> ;
+  assign gpio2_io_o[3] = \\<const0> ;
+  assign gpio2_io_o[2] = \\<const0> ;
+  assign gpio2_io_o[1] = \\<const0> ;
+  assign gpio2_io_o[0] = \\<const0> ;
+  assign gpio2_io_t[31] = \\<const1> ;
+  assign gpio2_io_t[30] = \\<const1> ;
+  assign gpio2_io_t[29] = \\<const1> ;
+  assign gpio2_io_t[28] = \\<const1> ;
+  assign gpio2_io_t[27] = \\<const1> ;
+  assign gpio2_io_t[26] = \\<const1> ;
+  assign gpio2_io_t[25] = \\<const1> ;
+  assign gpio2_io_t[24] = \\<const1> ;
+  assign gpio2_io_t[23] = \\<const1> ;
+  assign gpio2_io_t[22] = \\<const1> ;
+  assign gpio2_io_t[21] = \\<const1> ;
+  assign gpio2_io_t[20] = \\<const1> ;
+  assign gpio2_io_t[19] = \\<const1> ;
+  assign gpio2_io_t[18] = \\<const1> ;
+  assign gpio2_io_t[17] = \\<const1> ;
+  assign gpio2_io_t[16] = \\<const1> ;
+  assign gpio2_io_t[15] = \\<const1> ;
+  assign gpio2_io_t[14] = \\<const1> ;
+  assign gpio2_io_t[13] = \\<const1> ;
+  assign gpio2_io_t[12] = \\<const1> ;
+  assign gpio2_io_t[11] = \\<const1> ;
+  assign gpio2_io_t[10] = \\<const1> ;
+  assign gpio2_io_t[9] = \\<const1> ;
+  assign gpio2_io_t[8] = \\<const1> ;
+  assign gpio2_io_t[7] = \\<const1> ;
+  assign gpio2_io_t[6] = \\<const1> ;
+  assign gpio2_io_t[5] = \\<const1> ;
+  assign gpio2_io_t[4] = \\<const1> ;
+  assign gpio2_io_t[3] = \\<const1> ;
+  assign gpio2_io_t[2] = \\<const1> ;
+  assign gpio2_io_t[1] = \\<const1> ;
+  assign gpio2_io_t[0] = \\<const1> ;
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\<const0> ;
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\^s_axi_rdata [31];
+  assign s_axi_rdata[30] = \\<const0> ;
+  assign s_axi_rdata[29] = \\<const0> ;
+  assign s_axi_rdata[28] = \\<const0> ;
+  assign s_axi_rdata[27] = \\<const0> ;
+  assign s_axi_rdata[26] = \\<const0> ;
+  assign s_axi_rdata[25] = \\<const0> ;
+  assign s_axi_rdata[24] = \\<const0> ;
+  assign s_axi_rdata[23] = \\<const0> ;
+  assign s_axi_rdata[22] = \\<const0> ;
+  assign s_axi_rdata[21] = \\<const0> ;
+  assign s_axi_rdata[20] = \\<const0> ;
+  assign s_axi_rdata[19] = \\<const0> ;
+  assign s_axi_rdata[18] = \\<const0> ;
+  assign s_axi_rdata[17] = \\<const0> ;
+  assign s_axi_rdata[16] = \\<const0> ;
+  assign s_axi_rdata[15] = \\<const0> ;
+  assign s_axi_rdata[14] = \\<const0> ;
+  assign s_axi_rdata[13] = \\<const0> ;
+  assign s_axi_rdata[12] = \\<const0> ;
+  assign s_axi_rdata[11] = \\<const0> ;
+  assign s_axi_rdata[10] = \\<const0> ;
+  assign s_axi_rdata[9] = \\<const0> ;
+  assign s_axi_rdata[8] = \\<const0> ;
+  assign s_axi_rdata[7:0] = \\^s_axi_rdata [7:0];
+  assign s_axi_rresp[1] = \\<const0> ;
+  assign s_axi_rresp[0] = \\<const0> ;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
+       (.Bus_RNW_reg(\\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+        .D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
+        .E(AXI_LITE_IPIF_I_n_24),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_33),
+        .\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_35),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] (AXI_LITE_IPIF_I_n_22),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] (AXI_LITE_IPIF_I_n_21),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_20),
+        .\\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_19),
+        .\\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_18),
+        .\\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_17),
+        .\\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_16),
+        .\\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_25),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7]}),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .interrupt_wrce_strb(interrupt_wrce_strb),
+        .intr2bus_rdack0(intr2bus_rdack0),
+        .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
+        .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
+        .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
+        .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
+        .ip2bus_data(ip2bus_data[31]),
+        .\\ip2bus_data_i_D1_reg[0] ({p_0_out,ip2bus_data_i}),
+        .\\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .\\ip_irpt_enable_reg_reg[0] (AXI_LITE_IPIF_I_n_37),
+        .ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_38),
+        .irpt_rdack(irpt_rdack),
+        .irpt_rdack_d1(irpt_rdack_d1),
+        .irpt_wrack(irpt_wrack),
+        .irpt_wrack_d1(irpt_wrack_d1),
+        .p_0_in(p_0_in),
+        .p_1_in(p_1_in),
+        .p_3_in(p_3_in),
+        .p_8_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr[8:2]),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr[8:2]),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata({\\^s_axi_rdata [31],\\^s_axi_rdata [7:0]}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata({s_axi_wdata[31:24],s_axi_wdata[7:0]}),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control \\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I 
+       (.Bus_RNW_reg(\\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+        .\\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_38),
+        .\\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] (AXI_LITE_IPIF_I_n_37),
+        .GPIO_intr(GPIO_intr),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .IP2INTC_Irpt_i(IP2INTC_Irpt_i),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .interrupt_wrce_strb(interrupt_wrce_strb),
+        .intr2bus_rdack0(intr2bus_rdack0),
+        .ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole),
+        .ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole),
+        .ip2bus_rdack_i(ip2bus_rdack_i),
+        .ip2bus_wrack_i(ip2bus_wrack_i),
+        .irpt_rdack(irpt_rdack),
+        .irpt_rdack_d1(irpt_rdack_d1),
+        .irpt_wrack(irpt_wrack),
+        .irpt_wrack_d1(irpt_wrack_d1),
+        .p_0_in(p_0_in),
+        .p_1_in(p_1_in),
+        .p_3_in(p_3_in),
+        .p_8_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_wdata(s_axi_wdata[0]));
+  FDRE \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(intr_rd_ce_or_reduce),
+        .Q(ip2Bus_RdAck_intr_reg_hole_d1),
+        .R(bus2ip_reset));
+  FDRE \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(AXI_LITE_IPIF_I_n_33),
+        .Q(ip2Bus_RdAck_intr_reg_hole),
+        .R(bus2ip_reset));
+  FDRE \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(intr_wr_ce_or_reduce),
+        .Q(ip2Bus_WrAck_intr_reg_hole_d1),
+        .R(bus2ip_reset));
+  FDRE \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(AXI_LITE_IPIF_I_n_35),
+        .Q(ip2Bus_WrAck_intr_reg_hole),
+        .R(bus2ip_reset));
+  (* sigis = ""INTR_LEVEL_HIGH"" *) 
+  FDRE \\INTR_CTRLR_GEN.ip2intc_irpt_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(IP2INTC_Irpt_i),
+        .Q(ip2intc_irpt),
+        .R(bus2ip_reset));
+  VCC VCC
+       (.P(\\<const1> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    bus2ip_reset_i_1
+       (.I0(s_axi_aresetn),
+        .O(bus2ip_reset_i_1_n_0));
+  FDRE bus2ip_reset_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(bus2ip_reset_i_1_n_0),
+        .Q(bus2ip_reset),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
+       (.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
+        .E(AXI_LITE_IPIF_I_n_25),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_intr(GPIO_intr),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\Not_Dual.gpio_OE_reg[1]_0 (AXI_LITE_IPIF_I_n_22),
+        .\\Not_Dual.gpio_OE_reg[2]_0 (AXI_LITE_IPIF_I_n_21),
+        .\\Not_Dual.gpio_OE_reg[3]_0 (AXI_LITE_IPIF_I_n_20),
+        .\\Not_Dual.gpio_OE_reg[4]_0 (AXI_LITE_IPIF_I_n_19),
+        .\\Not_Dual.gpio_OE_reg[5]_0 (AXI_LITE_IPIF_I_n_18),
+        .\\Not_Dual.gpio_OE_reg[6]_0 (AXI_LITE_IPIF_I_n_17),
+        .\\Not_Dual.gpio_OE_reg[7]_0 (AXI_LITE_IPIF_I_n_16),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7]}),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_24),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_data({ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
+        .s_axi_aclk(s_axi_aclk));
+  FDRE \\ip2bus_data_i_D1_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out),
+        .Q(ip2bus_data_i_D1[0]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[24] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[24]),
+        .Q(ip2bus_data_i_D1[24]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[25] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[25]),
+        .Q(ip2bus_data_i_D1[25]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[26] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[26]),
+        .Q(ip2bus_data_i_D1[26]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[27] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[27]),
+        .Q(ip2bus_data_i_D1[27]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[28]),
+        .Q(ip2bus_data_i_D1[28]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[29]),
+        .Q(ip2bus_data_i_D1[29]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[30]),
+        .Q(ip2bus_data_i_D1[30]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data_i),
+        .Q(ip2bus_data_i_D1[31]),
+        .R(bus2ip_reset));
+  FDRE ip2bus_rdack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_i),
+        .Q(ip2bus_rdack_i_D1),
+        .R(bus2ip_reset));
+  FDRE ip2bus_wrack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_wrack_i),
+        .Q(ip2bus_wrack_i_D1),
+        .R(bus2ip_reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
+   (p_8_in,
+    bus2ip_rnw,
+    bus2ip_cs,
+    Bus_RNW_reg,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    s_axi_wready,
+    D,
+    \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ,
+    \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ,
+    GPIO_DBus_i,
+    E,
+    \\Not_Dual.gpio_Data_Out_reg[0] ,
+    \\ip2bus_data_i_D1_reg[0] ,
+    intr2bus_rdack0,
+    irpt_rdack,
+    irpt_wrack,
+    interrupt_wrce_strb,
+    Read_Reg_Rst,
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
+    intr_rd_ce_or_reduce,
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
+    intr_wr_ce_or_reduce,
+    \\ip_irpt_enable_reg_reg[0] ,
+    ipif_glbl_irpt_enable_reg_reg,
+    s_axi_rdata,
+    bus2ip_reset,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_aresetn,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    s_axi_bready,
+    s_axi_rready,
+    s_axi_awaddr,
+    s_axi_araddr,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_wdata,
+    gpio_io_t,
+    Q,
+    p_0_in,
+    irpt_rdack_d1,
+    irpt_wrack_d1,
+    ip2bus_data,
+    p_3_in,
+    p_1_in,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    ip2Bus_RdAck_intr_reg_hole_d1,
+    ip2Bus_WrAck_intr_reg_hole_d1,
+    \\ip2bus_data_i_D1_reg[0]_0 );
+  output p_8_in;
+  output bus2ip_rnw;
+  output [0:0]bus2ip_cs;
+  output Bus_RNW_reg;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [7:0]D;
+  output \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
+  output \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
+  output [0:0]GPIO_DBus_i;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_Data_Out_reg[0] ;
+  output [1:0]\\ip2bus_data_i_D1_reg[0] ;
+  output intr2bus_rdack0;
+  output irpt_rdack;
+  output irpt_wrack;
+  output interrupt_wrce_strb;
+  output Read_Reg_Rst;
+  output \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  output intr_rd_ce_or_reduce;
+  output \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  output intr_wr_ce_or_reduce;
+  output \\ip_irpt_enable_reg_reg[0] ;
+  output ipif_glbl_irpt_enable_reg_reg;
+  output [8:0]s_axi_rdata;
+  input bus2ip_reset;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_aresetn;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input s_axi_bready;
+  input s_axi_rready;
+  input [6:0]s_axi_awaddr;
+  input [6:0]s_axi_araddr;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [15:0]s_axi_wdata;
+  input [7:0]gpio_io_t;
+  input [7:0]Q;
+  input [0:0]p_0_in;
+  input irpt_rdack_d1;
+  input irpt_wrack_d1;
+  input [0:0]ip2bus_data;
+  input [0:0]p_3_in;
+  input [0:0]p_1_in;
+  input GPIO_xferAck_i;
+  input gpio_xferAck_Reg;
+  input ip2Bus_RdAck_intr_reg_hole_d1;
+  input ip2Bus_WrAck_intr_reg_hole_d1;
+  input [8:0]\\ip2bus_data_i_D1_reg[0]_0 ;
+
+  wire Bus_RNW_reg;
+  wire [7:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
+  wire \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
+  wire [0:0]\\Not_Dual.gpio_Data_Out_reg[0] ;
+  wire [7:0]Q;
+  wire Read_Reg_Rst;
+  wire [0:0]bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [7:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack0;
+  wire intr_rd_ce_or_reduce;
+  wire intr_wr_ce_or_reduce;
+  wire ip2Bus_RdAck_intr_reg_hole_d1;
+  wire ip2Bus_WrAck_intr_reg_hole_d1;
+  wire [0:0]ip2bus_data;
+  wire [1:0]\\ip2bus_data_i_D1_reg[0] ;
+  wire [8:0]\\ip2bus_data_i_D1_reg[0]_0 ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire \\ip_irpt_enable_reg_reg[0] ;
+  wire ipif_glbl_irpt_enable_reg_reg;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire [0:0]p_0_in;
+  wire [0:0]p_1_in;
+  wire [0:0]p_3_in;
+  wire p_8_in;
+  wire s_axi_aclk;
+  wire [6:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [6:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [8:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [15:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
+       (.D(D),
+        .E(E),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
+        .\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] (\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] (\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] (\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ),
+        .\\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] (\\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ),
+        .\\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] (\\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ),
+        .\\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] (\\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ),
+        .\\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] (\\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ),
+        .\\Not_Dual.gpio_Data_Out_reg[0] (\\Not_Dual.gpio_Data_Out_reg[0] ),
+        .\\Not_Dual.gpio_Data_Out_reg[7] (bus2ip_cs),
+        .\\Not_Dual.gpio_OE_reg[0] (bus2ip_rnw),
+        .Q(Q),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .bus2ip_reset(bus2ip_reset),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .interrupt_wrce_strb(interrupt_wrce_strb),
+        .intr2bus_rdack0(intr2bus_rdack0),
+        .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
+        .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
+        .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
+        .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
+        .ip2bus_data(ip2bus_data),
+        .\\ip2bus_data_i_D1_reg[0] (p_8_in),
+        .\\ip2bus_data_i_D1_reg[0]_0 (\\ip2bus_data_i_D1_reg[0] ),
+        .\\ip2bus_data_i_D1_reg[0]_1 (\\ip2bus_data_i_D1_reg[0]_0 ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .\\ip_irpt_enable_reg_reg[0] (Bus_RNW_reg),
+        .\\ip_irpt_enable_reg_reg[0]_0 (\\ip_irpt_enable_reg_reg[0] ),
+        .ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
+        .irpt_rdack(irpt_rdack),
+        .irpt_rdack_d1(irpt_rdack_d1),
+        .irpt_wrack(irpt_wrack),
+        .irpt_wrack_d1(irpt_wrack_d1),
+        .p_0_in(p_0_in),
+        .p_1_in(p_1_in),
+        .p_3_in(p_3_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
+   (D,
+    scndry_vect_out,
+    Q,
+    gpio_io_i,
+    s_axi_aclk);
+  output [7:0]D;
+  output [7:0]scndry_vect_out;
+  input [7:0]Q;
+  input [7:0]gpio_io_i;
+  input s_axi_aclk;
+
+  wire [7:0]D;
+  wire [7:0]Q;
+  wire [7:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d1_cdc_to_4;
+  wire s_level_out_bus_d1_cdc_to_5;
+  wire s_level_out_bus_d1_cdc_to_6;
+  wire s_level_out_bus_d1_cdc_to_7;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d2_4;
+  wire s_level_out_bus_d2_5;
+  wire s_level_out_bus_d2_6;
+  wire s_level_out_bus_d2_7;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire s_level_out_bus_d3_4;
+  wire s_level_out_bus_d3_5;
+  wire s_level_out_bus_d3_6;
+  wire s_level_out_bus_d3_7;
+  wire [7:0]scndry_vect_out;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_4),
+        .Q(s_level_out_bus_d2_4),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_5),
+        .Q(s_level_out_bus_d2_5),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_6),
+        .Q(s_level_out_bus_d2_6),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_7),
+        .Q(s_level_out_bus_d2_7),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_4),
+        .Q(s_level_out_bus_d3_4),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_5),
+        .Q(s_level_out_bus_d3_5),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_6),
+        .Q(s_level_out_bus_d3_6),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_7),
+        .Q(s_level_out_bus_d3_7),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_4),
+        .Q(scndry_vect_out[4]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_5),
+        .Q(scndry_vect_out[5]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_6),
+        .Q(scndry_vect_out[6]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_7),
+        .Q(scndry_vect_out[7]),
+        .R('b'1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[4]),
+        .Q(s_level_out_bus_d1_cdc_to_4),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[5]),
+        .Q(s_level_out_bus_d1_cdc_to_5),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[6]),
+        .Q(s_level_out_bus_d1_cdc_to_6),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[7]),
+        .Q(s_level_out_bus_d1_cdc_to_7),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1 
+       (.I0(Q[7]),
+        .I1(scndry_vect_out[7]),
+        .O(D[7]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1 
+       (.I0(Q[6]),
+        .I1(scndry_vect_out[6]),
+        .O(D[6]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1 
+       (.I0(Q[5]),
+        .I1(scndry_vect_out[5]),
+        .O(D[5]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1 
+       (.I0(Q[4]),
+        .I1(scndry_vect_out[4]),
+        .O(D[4]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1 
+       (.I0(Q[3]),
+        .I1(scndry_vect_out[3]),
+        .O(D[3]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1 
+       (.I0(Q[2]),
+        .I1(scndry_vect_out[2]),
+        .O(D[2]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1 
+       (.I0(Q[1]),
+        .I1(scndry_vect_out[1]),
+        .O(D[1]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1 
+       (.I0(Q[0]),
+        .I1(scndry_vect_out[0]),
+        .O(D[0]));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_gpio_2_0,axi_gpio,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_gpio,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"" *) output ip2intc_irpt;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_I"" *) input [7:0]gpio_io_i;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_O"" *) output [7:0]gpio_io_o;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_T"" *) output [7:0]gpio_io_t;
+
+  wire [7:0]gpio_io_i;
+  wire [7:0]gpio_io_o;
+  wire [7:0]gpio_io_t;
+  wire ip2intc_irpt;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
+  wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
+
+  (* C_ALL_INPUTS = ""0"" *) 
+  (* C_ALL_INPUTS_2 = ""0"" *) 
+  (* C_ALL_OUTPUTS = ""0"" *) 
+  (* C_ALL_OUTPUTS_2 = ""0"" *) 
+  (* C_DOUT_DEFAULT = ""0"" *) 
+  (* C_DOUT_DEFAULT_2 = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_GPIO2_WIDTH = ""32"" *) 
+  (* C_GPIO_WIDTH = ""8"" *) 
+  (* C_INTERRUPT_PRESENT = ""1"" *) 
+  (* C_IS_DUAL = ""0"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_TRI_DEFAULT = ""-1"" *) 
+  (* C_TRI_DEFAULT_2 = ""-1"" *) 
+  (* downgradeipidentifiedwarnings = ""yes"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
+       (.gpio2_io_i({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
+        .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .ip2intc_irpt(ip2intc_irpt),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control
+   (irpt_wrack_d1,
+    p_3_in,
+    irpt_rdack_d1,
+    p_1_in,
+    p_0_in,
+    IP2INTC_Irpt_i,
+    ip2bus_wrack_i,
+    ip2bus_rdack_i,
+    bus2ip_reset,
+    irpt_wrack,
+    s_axi_aclk,
+    GPIO_intr,
+    interrupt_wrce_strb,
+    irpt_rdack,
+    intr2bus_rdack0,
+    \\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ,
+    \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ,
+    p_8_in,
+    s_axi_wdata,
+    Bus_RNW_reg,
+    ip2Bus_WrAck_intr_reg_hole,
+    bus2ip_rnw,
+    GPIO_xferAck_i,
+    ip2Bus_RdAck_intr_reg_hole);
+  output irpt_wrack_d1;
+  output [0:0]p_3_in;
+  output irpt_rdack_d1;
+  output [0:0]p_1_in;
+  output [0:0]p_0_in;
+  output IP2INTC_Irpt_i;
+  output ip2bus_wrack_i;
+  output ip2bus_rdack_i;
+  input bus2ip_reset;
+  input irpt_wrack;
+  input s_axi_aclk;
+  input GPIO_intr;
+  input interrupt_wrce_strb;
+  input irpt_rdack;
+  input intr2bus_rdack0;
+  input \\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
+  input \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
+  input p_8_in;
+  input [0:0]s_axi_wdata;
+  input Bus_RNW_reg;
+  input ip2Bus_WrAck_intr_reg_hole;
+  input bus2ip_rnw;
+  input GPIO_xferAck_i;
+  input ip2Bus_RdAck_intr_reg_hole;
+
+  wire Bus_RNW_reg;
+  wire \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
+  wire \\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
+  wire \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ;
+  wire \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ;
+  wire GPIO_intr;
+  wire GPIO_xferAck_i;
+  wire IP2INTC_Irpt_i;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack;
+  wire intr2bus_rdack0;
+  wire intr2bus_wrack;
+  wire ip2Bus_RdAck_intr_reg_hole;
+  wire ip2Bus_WrAck_intr_reg_hole;
+  wire ip2bus_rdack_i;
+  wire ip2bus_wrack_i;
+  wire irpt_dly1;
+  wire irpt_dly2;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire [0:0]p_0_in;
+  wire [0:0]p_1_in;
+  wire [0:0]p_3_in;
+  wire p_8_in;
+  wire s_axi_aclk;
+  wire [0:0]s_axi_wdata;
+
+  FDSE \\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_intr),
+        .Q(irpt_dly1),
+        .S(bus2ip_reset));
+  FDSE \\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(irpt_dly1),
+        .Q(irpt_dly2),
+        .S(bus2ip_reset));
+  LUT6 #(
+    .INIT(64\'hF4F4F4F44FF4F4F4)) 
+    \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1 
+       (.I0(irpt_dly2),
+        .I1(irpt_dly1),
+        .I2(p_3_in),
+        .I3(p_8_in),
+        .I4(s_axi_wdata),
+        .I5(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ),
+        .O(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ));
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2 
+       (.I0(irpt_wrack_d1),
+        .I1(Bus_RNW_reg),
+        .O(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ));
+  FDRE \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ),
+        .Q(p_3_in),
+        .R(bus2ip_reset));
+  LUT3 #(
+    .INIT(8\'h80)) 
+    \\INTR_CTRLR_GEN.ip2intc_irpt_i_1 
+       (.I0(p_3_in),
+        .I1(p_1_in),
+        .I2(p_0_in),
+        .O(IP2INTC_Irpt_i));
+  FDRE intr2bus_rdack_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(intr2bus_rdack0),
+        .Q(intr2bus_rdack),
+        .R(bus2ip_reset));
+  FDRE intr2bus_wrack_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(interrupt_wrce_strb),
+        .Q(intr2bus_wrack),
+        .R(bus2ip_reset));
+  LUT4 #(
+    .INIT(16\'hFEEE)) 
+    ip2bus_rdack_i_D1_i_1
+       (.I0(ip2Bus_RdAck_intr_reg_hole),
+        .I1(intr2bus_rdack),
+        .I2(bus2ip_rnw),
+        .I3(GPIO_xferAck_i),
+        .O(ip2bus_rdack_i));
+  LUT4 #(
+    .INIT(16\'hEFEE)) 
+    ip2bus_wrack_i_D1_i_1
+       (.I0(ip2Bus_WrAck_intr_reg_hole),
+        .I1(intr2bus_wrack),
+        .I2(bus2ip_rnw),
+        .I3(GPIO_xferAck_i),
+        .O(ip2bus_wrack_i));
+  FDRE \\ip_irpt_enable_reg_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ),
+        .Q(p_1_in),
+        .R(bus2ip_reset));
+  FDRE ipif_glbl_irpt_enable_reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ),
+        .Q(p_0_in),
+        .R(bus2ip_reset));
+  FDRE irpt_rdack_d1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(irpt_rdack),
+        .Q(irpt_rdack_d1),
+        .R(bus2ip_reset));
+  FDRE irpt_wrack_d1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(irpt_wrack),
+        .Q(irpt_wrack_d1),
+        .R(bus2ip_reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
+   (\\ip2bus_data_i_D1_reg[0] ,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    \\Not_Dual.gpio_Data_Out_reg[7] ,
+    \\ip_irpt_enable_reg_reg[0] ,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    s_axi_wready,
+    D,
+    \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ,
+    \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ,
+    GPIO_DBus_i,
+    E,
+    \\Not_Dual.gpio_Data_Out_reg[0] ,
+    \\ip2bus_data_i_D1_reg[0]_0 ,
+    intr2bus_rdack0,
+    irpt_rdack,
+    irpt_wrack,
+    interrupt_wrce_strb,
+    Read_Reg_Rst,
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
+    intr_rd_ce_or_reduce,
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
+    intr_wr_ce_or_reduce,
+    \\ip_irpt_enable_reg_reg[0]_0 ,
+    ipif_glbl_irpt_enable_reg_reg,
+    s_axi_rdata,
+    bus2ip_reset,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_aresetn,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    s_axi_bready,
+    s_axi_rready,
+    s_axi_awaddr,
+    s_axi_araddr,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_wdata,
+    gpio_io_t,
+    Q,
+    p_0_in,
+    irpt_rdack_d1,
+    irpt_wrack_d1,
+    ip2bus_data,
+    p_3_in,
+    p_1_in,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    ip2Bus_RdAck_intr_reg_hole_d1,
+    ip2Bus_WrAck_intr_reg_hole_d1,
+    \\ip2bus_data_i_D1_reg[0]_1 );
+  output \\ip2bus_data_i_D1_reg[0] ;
+  output \\Not_Dual.gpio_OE_reg[0] ;
+  output \\Not_Dual.gpio_Data_Out_reg[7] ;
+  output \\ip_irpt_enable_reg_reg[0] ;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [7:0]D;
+  output \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
+  output \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
+  output [0:0]GPIO_DBus_i;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_Data_Out_reg[0] ;
+  output [1:0]\\ip2bus_data_i_D1_reg[0]_0 ;
+  output intr2bus_rdack0;
+  output irpt_rdack;
+  output irpt_wrack;
+  output interrupt_wrce_strb;
+  output Read_Reg_Rst;
+  output \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  output intr_rd_ce_or_reduce;
+  output \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  output intr_wr_ce_or_reduce;
+  output \\ip_irpt_enable_reg_reg[0]_0 ;
+  output ipif_glbl_irpt_enable_reg_reg;
+  output [8:0]s_axi_rdata;
+  input bus2ip_reset;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_aresetn;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input s_axi_bready;
+  input s_axi_rready;
+  input [6:0]s_axi_awaddr;
+  input [6:0]s_axi_araddr;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [15:0]s_axi_wdata;
+  input [7:0]gpio_io_t;
+  input [7:0]Q;
+  input [0:0]p_0_in;
+  input irpt_rdack_d1;
+  input irpt_wrack_d1;
+  input [0:0]ip2bus_data;
+  input [0:0]p_3_in;
+  input [0:0]p_1_in;
+  input GPIO_xferAck_i;
+  input gpio_xferAck_Reg;
+  input ip2Bus_RdAck_intr_reg_hole_d1;
+  input ip2Bus_WrAck_intr_reg_hole_d1;
+  input [8:0]\\ip2bus_data_i_D1_reg[0]_1 ;
+
+  wire [7:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ;
+  wire \\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ;
+  wire [0:0]\\Not_Dual.gpio_Data_Out_reg[0] ;
+  wire \\Not_Dual.gpio_Data_Out_reg[7] ;
+  wire \\Not_Dual.gpio_OE_reg[0] ;
+  wire [7:0]Q;
+  wire Read_Reg_Rst;
+  wire [0:6]bus2ip_addr;
+  wire bus2ip_reset;
+  wire bus2ip_rnw_i06_out;
+  wire clear;
+  wire [7:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack0;
+  wire intr_rd_ce_or_reduce;
+  wire intr_wr_ce_or_reduce;
+  wire ip2Bus_RdAck_intr_reg_hole_d1;
+  wire ip2Bus_WrAck_intr_reg_hole_d1;
+  wire [0:0]ip2bus_data;
+  wire \\ip2bus_data_i_D1_reg[0] ;
+  wire [1:0]\\ip2bus_data_i_D1_reg[0]_0 ;
+  wire [8:0]\\ip2bus_data_i_D1_reg[0]_1 ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire \\ip_irpt_enable_reg_reg[0] ;
+  wire \\ip_irpt_enable_reg_reg[0]_0 ;
+  wire ipif_glbl_irpt_enable_reg_reg;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_write;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire [0:0]p_0_in;
+  wire [1:0]p_0_out__0;
+  wire [0:0]p_1_in;
+  wire [8:2]p_1_in__0;
+  wire [0:0]p_3_in;
+  wire [3:0]plusOp;
+  wire s_axi_aclk;
+  wire [6:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [6:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [8:0]s_axi_rdata;
+  wire s_axi_rdata_i;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire [15:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire \\state[1]_i_2_n_0 ;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[1]),
+        .I1(state[0]),
+        .O(clear));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(clear));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
+       (.D(D),
+        .E(E),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
+        .\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] (\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[25] ),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] (\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[26] ),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] (\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[27] ),
+        .\\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] (\\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[28] ),
+        .\\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] (\\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[29] ),
+        .\\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] (\\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[30] ),
+        .\\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] (\\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[31] ),
+        .\\Not_Dual.gpio_Data_In_reg[0] (Q),
+        .\\Not_Dual.gpio_Data_Out_reg[0] (\\Not_Dual.gpio_Data_Out_reg[0] ),
+        .\\Not_Dual.gpio_Data_Out_reg[7] (\\Not_Dual.gpio_Data_Out_reg[7] ),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .\\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw_i_reg(\\Not_Dual.gpio_OE_reg[0] ),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .interrupt_wrce_strb(interrupt_wrce_strb),
+        .intr2bus_rdack0(intr2bus_rdack0),
+        .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
+        .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
+        .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
+        .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
+        .ip2bus_data(ip2bus_data),
+        .\\ip2bus_data_i_D1_reg[0] (\\ip2bus_data_i_D1_reg[0] ),
+        .\\ip2bus_data_i_D1_reg[0]_0 (\\ip2bus_data_i_D1_reg[0]_0 ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .\\ip_irpt_enable_reg_reg[0] (\\ip_irpt_enable_reg_reg[0] ),
+        .\\ip_irpt_enable_reg_reg[0]_0 (\\ip_irpt_enable_reg_reg[0]_0 ),
+        .ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
+        .irpt_rdack(irpt_rdack),
+        .irpt_rdack_d1(irpt_rdack_d1),
+        .irpt_wrack(irpt_wrack),
+        .irpt_wrack_d1(irpt_wrack_d1),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .p_0_in(p_0_in),
+        .p_1_in(p_1_in),
+        .p_3_in(p_3_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .start2(start2));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_awaddr[0]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[0]),
+        .O(p_1_in__0[2]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_awaddr[1]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[1]),
+        .O(p_1_in__0[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[4]_i_1 
+       (.I0(s_axi_awaddr[2]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .O(p_1_in__0[4]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[5]_i_1 
+       (.I0(s_axi_awaddr[3]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[3]),
+        .O(p_1_in__0[5]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[6]_i_1 
+       (.I0(s_axi_awaddr[4]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[4]),
+        .O(p_1_in__0[6]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[7]_i_1 
+       (.I0(s_axi_awaddr[5]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[5]),
+        .O(p_1_in__0[7]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_awaddr[6]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[6]),
+        .O(p_1_in__0[8]));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[2]),
+        .Q(bus2ip_addr[6]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[3]),
+        .Q(bus2ip_addr[5]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[4]),
+        .Q(bus2ip_addr[4]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[5]),
+        .Q(bus2ip_addr[3]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[6]),
+        .Q(bus2ip_addr[2]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[7]),
+        .Q(bus2ip_addr[1]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[8]),
+        .Q(bus2ip_addr[0]),
+        .R(bus2ip_reset));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'h02)) 
+    bus2ip_rnw_i_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state[0]),
+        .I2(state[1]),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(bus2ip_rnw_i06_out),
+        .Q(\\Not_Dual.gpio_OE_reg[0] ),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h3FFA000A)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(\\state[1]_i_2_n_0 ),
+        .I2(state[1]),
+        .I3(state[0]),
+        .I4(is_read),
+        .O(is_read_i_1_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(bus2ip_reset));
+  LUT6 #(
+    .INIT(64\'h1000FFFF10000000)) 
+    is_write_i_1
+       (.I0(state[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_axi_wvalid),
+        .I3(s_axi_awvalid),
+        .I4(is_write),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hF88800000000FFFF)) 
+    is_write_i_2
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .I4(state[1]),
+        .I5(state[0]),
+        .O(is_write));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_wready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(bus2ip_reset));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[31]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(s_axi_rdata_i));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [0]),
+        .Q(s_axi_rdata[0]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [1]),
+        .Q(s_axi_rdata[1]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [2]),
+        .Q(s_axi_rdata[2]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [8]),
+        .Q(s_axi_rdata[8]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [3]),
+        .Q(s_axi_rdata[3]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [4]),
+        .Q(s_axi_rdata[4]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [5]),
+        .Q(s_axi_rdata[5]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [6]),
+        .Q(s_axi_rdata[6]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_1 [7]),
+        .Q(s_axi_rdata[7]),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_arready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h000000F8)) 
+    start2_i_1
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(state[1]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h0FFFAACC)) 
+    \\state[0]_i_1 
+       (.I0(s_axi_wready),
+        .I1(s_axi_arvalid),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(p_0_out__0[0]));
+  LUT6 #(
+    .INIT(64\'h2E2E2E2ECCCCFFCC)) 
+    \\state[1]_i_1 
+       (.I0(s_axi_arready),
+        .I1(state[1]),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(\\state[1]_i_3_n_0 ),
+        .I4(s_axi_arvalid),
+        .I5(state[0]),
+        .O(p_0_out__0[1]));
+  LUT4 #(
+    .INIT(16\'hF888)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(\\state[1]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\state[1]_i_3 
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out__0[0]),
+        .Q(state[0]),
+        .R(bus2ip_reset));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out__0[1]),
+        .Q(state[1]),
+        .R(bus2ip_reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, ""Critical
+// Applications""). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:processing_system7:5.5
+// IP Revision: 3
+
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *)
+(* CORE_GENERATION_INFO = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CH\\
+ECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C\\
+_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_TXN=0,C_GP1_EN_MODIF\\
+IABLE_TXN=0}"" *)
+(* DowngradeIPIdentifiedWarnings = ""yes"" *)
+module design_1_processing_system7_0_0 (
+  GPIO_I,
+  GPIO_O,
+  GPIO_T,
+  SDIO0_WP,
+  TTC0_WAVE0_OUT,
+  TTC0_WAVE1_OUT,
+  TTC0_WAVE2_OUT,
+  USB0_PORT_INDCTL,
+  USB0_VBUS_PWRSELECT,
+  USB0_VBUS_PWRFAULT,
+  M_AXI_GP0_ARVALID,
+  M_AXI_GP0_AWVALID,
+  M_AXI_GP0_BREADY,
+  M_AXI_GP0_RREADY,
+  M_AXI_GP0_WLAST,
+  M_AXI_GP0_WVALID,
+  M_AXI_GP0_ARID,
+  M_AXI_GP0_AWID,
+  M_AXI_GP0_WID,
+  M_AXI_GP0_ARBURST,
+  M_AXI_GP0_ARLOCK,
+  M_AXI_GP0_ARSIZE,
+  M_AXI_GP0_AWBURST,
+  M_AXI_GP0_AWLOCK,
+  M_AXI_GP0_AWSIZE,
+  M_AXI_GP0_ARPROT,
+  M_AXI_GP0_AWPROT,
+  M_AXI_GP0_ARADDR,
+  M_AXI_GP0_AWADDR,
+  M_AXI_GP0_WDATA,
+  M_AXI_GP0_ARCACHE,
+  M_AXI_GP0_ARLEN,
+  M_AXI_GP0_ARQOS,
+  M_AXI_GP0_AWCACHE,
+  M_AXI_GP0_AWLEN,
+  M_AXI_GP0_AWQOS,
+  M_AXI_GP0_WSTRB,
+  M_AXI_GP0_ACLK,
+  M_AXI_GP0_ARREADY,
+  M_AXI_GP0_AWREADY,
+  M_AXI_GP0_BVALID,
+  M_AXI_GP0_RLAST,
+  M_AXI_GP0_RVALID,
+  M_AXI_GP0_WREADY,
+  M_AXI_GP0_BID,
+  M_AXI_GP0_RID,
+  M_AXI_GP0_BRESP,
+  M_AXI_GP0_RRESP,
+  M_AXI_GP0_RDATA,
+  FCLK_CLK0,
+  FCLK_RESET0_N,
+  MIO,
+  DDR_CAS_n,
+  DDR_CKE,
+  DDR_Clk_n,
+  DDR_Clk,
+  DDR_CS_n,
+  DDR_DRSTB,
+  DDR_ODT,
+  DDR_RAS_n,
+  DDR_WEB,
+  DDR_BankAddr,
+  DDR_Addr,
+  DDR_VRN,
+  DDR_VRP,
+  DDR_DM,
+  DDR_DQ,
+  DDR_DQS_n,
+  DDR_DQS,
+  PS_SRSTB,
+  PS_CLK,
+  PS_PORB
+);
+
+(* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I"" *)
+input wire [63 : 0] GPIO_I;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O"" *)
+output wire [63 : 0] GPIO_O;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T"" *)
+output wire [63 : 0] GPIO_T;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *)
+input wire SDIO0_WP;
+output wire TTC0_WAVE0_OUT;
+output wire TTC0_WAVE1_OUT;
+output wire TTC0_WAVE2_OUT;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *)
+output wire [1 : 0] USB0_PORT_INDCTL;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *)
+output wire USB0_VBUS_PWRSELECT;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *)
+input wire USB0_VBUS_PWRFAULT;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *)
+output wire M_AXI_GP0_ARVALID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *)
+output wire M_AXI_GP0_AWVALID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *)
+output wire M_AXI_GP0_BREADY;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *)
+output wire M_AXI_GP0_RREADY;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *)
+output wire M_AXI_GP0_WLAST;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *)
+output wire M_AXI_GP0_WVALID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *)
+output wire [11 : 0] M_AXI_GP0_ARID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *)
+output wire [11 : 0] M_AXI_GP0_AWID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *)
+output wire [11 : 0] M_AXI_GP0_WID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *)
+output wire [1 : 0] M_AXI_GP0_ARBURST;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *)
+output wire [1 : 0] M_AXI_GP0_ARLOCK;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *)
+output wire [2 : 0] M_AXI_GP0_ARSIZE;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *)
+output wire [1 : 0] M_AXI_GP0_AWBURST;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *)
+output wire [1 : 0] M_AXI_GP0_AWLOCK;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *)
+output wire [2 : 0] M_AXI_GP0_AWSIZE;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *)
+output wire [2 : 0] M_AXI_GP0_ARPROT;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *)
+output wire [2 : 0] M_AXI_GP0_AWPROT;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *)
+output wire [31 : 0] M_AXI_GP0_ARADDR;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *)
+output wire [31 : 0] M_AXI_GP0_AWADDR;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *)
+output wire [31 : 0] M_AXI_GP0_WDATA;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *)
+output wire [3 : 0] M_AXI_GP0_ARCACHE;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *)
+output wire [3 : 0] M_AXI_GP0_ARLEN;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *)
+output wire [3 : 0] M_AXI_GP0_ARQOS;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *)
+output wire [3 : 0] M_AXI_GP0_AWCACHE;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *)
+output wire [3 : 0] M_AXI_GP0_AWLEN;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *)
+output wire [3 : 0] M_AXI_GP0_AWQOS;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *)
+output wire [3 : 0] M_AXI_GP0_WSTRB;
+(* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *)
+input wire M_AXI_GP0_ACLK;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *)
+input wire M_AXI_GP0_ARREADY;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *)
+input wire M_AXI_GP0_AWREADY;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *)
+input wire M_AXI_GP0_BVALID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *)
+input wire M_AXI_GP0_RLAST;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *)
+input wire M_AXI_GP0_RVALID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *)
+input wire M_AXI_GP0_WREADY;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *)
+input wire [11 : 0] M_AXI_GP0_BID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *)
+input wire [11 : 0] M_AXI_GP0_RID;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *)
+input wire [1 : 0] M_AXI_GP0_BRESP;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *)
+input wire [1 : 0] M_AXI_GP0_RRESP;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *)
+input wire [31 : 0] M_AXI_GP0_RDATA;
+(* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *)
+output wire FCLK_CLK0;
+(* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *)
+output wire FCLK_RESET0_N;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *)
+inout wire [53 : 0] MIO;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *)
+inout wire DDR_CAS_n;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *)
+inout wire DDR_CKE;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *)
+inout wire DDR_Clk_n;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *)
+inout wire DDR_Clk;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *)
+inout wire DDR_CS_n;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *)
+inout wire DDR_DRSTB;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *)
+inout wire DDR_ODT;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *)
+inout wire DDR_RAS_n;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *)
+inout wire DDR_WEB;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *)
+inout wire [2 : 0] DDR_BankAddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *)
+inout wire [14 : 0] DDR_Addr;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *)
+inout wire DDR_VRN;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *)
+inout wire DDR_VRP;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *)
+inout wire [3 : 0] DDR_DM;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *)
+inout wire [31 : 0] DDR_DQ;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *)
+inout wire [3 : 0] DDR_DQS_n;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *)
+inout wire [3 : 0] DDR_DQS;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *)
+inout wire PS_SRSTB;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *)
+inout wire PS_CLK;
+(* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *)
+inout wire PS_PORB;
+
+  processing_system7_v5_5_processing_system7 #(
+    .C_EN_EMIO_PJTAG(0),
+    .C_EN_EMIO_ENET0(0),
+    .C_EN_EMIO_ENET1(0),
+    .C_EN_EMIO_TRACE(0),
+    .C_INCLUDE_TRACE_BUFFER(0),
+    .C_TRACE_BUFFER_FIFO_SIZE(128),
+    .USE_TRACE_DATA_EDGE_DETECTOR(0),
+    .C_TRACE_PIPELINE_WIDTH(8),
+    .C_TRACE_BUFFER_CLOCK_DELAY(12),
+    .C_EMIO_GPIO_WIDTH(64),
+    .C_INCLUDE_ACP_TRANS_CHECK(0),
+    .C_USE_DEFAULT_ACP_USER_VAL(0),
+    .C_S_AXI_ACP_ARUSER_VAL(31),
+    .C_S_AXI_ACP_AWUSER_VAL(31),
+    .C_M_AXI_GP0_ID_WIDTH(12),
+    .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
+    .C_M_AXI_GP1_ID_WIDTH(12),
+    .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
+    .C_S_AXI_GP0_ID_WIDTH(6),
+    .C_S_AXI_GP1_ID_WIDTH(6),
+    .C_S_AXI_ACP_ID_WIDTH(3),
+    .C_S_AXI_HP0_ID_WIDTH(6),
+    .C_S_AXI_HP0_DATA_WIDTH(64),
+    .C_S_AXI_HP1_ID_WIDTH(6),
+    .C_S_AXI_HP1_DATA_WIDTH(64),
+    .C_S_AXI_HP2_ID_WIDTH(6),
+    .C_S_AXI_HP2_DATA_WIDTH(64),
+    .C_S_AXI_HP3_ID_WIDTH(6),
+    .C_S_AXI_HP3_DATA_WIDTH(64),
+    .C_M_AXI_GP0_THREAD_ID_WIDTH(12),
+    .C_M_AXI_GP1_THREAD_ID_WIDTH(12),
+    .C_NUM_F2P_INTR_INPUTS(1),
+    .C_IRQ_F2P_MODE(""DIRECT""),
+    .C_DQ_WIDTH(32),
+    .C_DQS_WIDTH(4),
+    .C_DM_WIDTH(4),
+    .C_MIO_PRIMITIVE(54),
+    .C_TRACE_INTERNAL_WIDTH(2),
+    .C_USE_AXI_NONSECURE(0),
+    .C_USE_M_AXI_GP0(1),
+    .C_USE_M_AXI_GP1(0),
+    .C_USE_S_AXI_GP0(0),
+    .C_USE_S_AXI_HP0(0),
+    .C_USE_S_AXI_HP1(0),
+    .C_USE_S_AXI_HP2(0),
+    .C_USE_S_AXI_HP3(0),
+    .C_USE_S_AXI_ACP(0),
+    .C_PS7_SI_REV(""PRODUCTION""),
+    .C_FCLK_CLK0_BUF(""TRUE""),
+    .C_FCLK_CLK1_BUF(""FALSE""),
+    .C_FCLK_CLK2_BUF(""FALSE""),
+    .C_FCLK_CLK3_BUF(""FALSE""),
+    .C_PACKAGE_NAME(""clg400""),
+    .C_GP0_EN_MODIFIABLE_TXN(0),
+    .C_GP1_EN_MODIFIABLE_TXN(0)
+  ) inst (
+    .CAN0_PHY_TX(),
+    .CAN0_PHY_RX(1\'B0),
+    .CAN1_PHY_TX(),
+    .CAN1_PHY_RX(1\'B0),
+    .ENET0_GMII_TX_EN(),
+    .ENET0_GMII_TX_ER(),
+    .ENET0_MDIO_MDC(),
+    .ENET0_MDIO_O(),
+    .ENET0_MDIO_T(),
+    .ENET0_PTP_DELAY_REQ_RX(),
+    .ENET0_PTP_DELAY_REQ_TX(),
+    .ENET0_PTP_PDELAY_REQ_RX(),
+    .ENET0_PTP_PDELAY_REQ_TX(),
+    .ENET0_PTP_PDELAY_RESP_RX(),
+    .ENET0_PTP_PDELAY_RESP_TX(),
+    .ENET0_PTP_SYNC_FRAME_RX(),
+    .ENET0_PTP_SYNC_FRAME_TX(),
+    .ENET0_SOF_RX(),
+    .ENET0_SOF_TX(),
+    .ENET0_GMII_TXD(),
+    .ENET0_GMII_COL(1\'B0),
+    .ENET0_GMII_CRS(1\'B0),
+    .ENET0_GMII_RX_CLK(1\'B0),
+    .ENET0_GMII_RX_DV(1\'B0),
+    .ENET0_GMII_RX_ER(1\'B0),
+    .ENET0_GMII_TX_CLK(1\'B0),
+    .ENET0_MDIO_I(1\'B0),
+    .ENET0_EXT_INTIN(1\'B0),
+    .ENET0_GMII_RXD(8\'B0),
+    .ENET1_GMII_TX_EN(),
+    .ENET1_GMII_TX_ER(),
+    .ENET1_MDIO_MDC(),
+    .ENET1_MDIO_O(),
+    .ENET1_MDIO_T(),
+    .ENET1_PTP_DELAY_REQ_RX(),
+    .ENET1_PTP_DELAY_REQ_TX(),
+    .ENET1_PTP_PDELAY_REQ_RX(),
+    .ENET1_PTP_PDELAY_REQ_TX(),
+    .ENET1_PTP_PDELAY_RESP_RX(),
+    .ENET1_PTP_PDELAY_RESP_TX(),
+    .ENET1_PTP_SYNC_FRAME_RX(),
+    .ENET1_PTP_SYNC_FRAME_TX(),
+    .ENET1_SOF_RX(),
+    .ENET1_SOF_TX(),
+    .ENET1_GMII_TXD(),
+    .ENET1_GMII_COL(1\'B0),
+    .ENET1_GMII_CRS(1\'B0),
+    .ENET1_GMII_RX_CLK(1\'B0),
+    .ENET1_GMII_RX_DV(1\'B0),
+    .ENET1_GMII_RX_ER(1\'B0),
+    .ENET1_GMII_TX_CLK(1\'B0),
+    .ENET1_MDIO_I(1\'B0),
+    .ENET1_EXT_INTIN(1\'B0),
+    .ENET1_GMII_RXD(8\'B0),
+    .GPIO_I(GPIO_I),
+    .GPIO_O(GPIO_O),
+    .GPIO_T(GPIO_T),
+    .I2C0_SDA_I(1\'B0),
+    .I2C0_SDA_O(),
+    .I2C0_SDA_T(),
+    .I2C0_SCL_I(1\'B0),
+    .I2C0_SCL_O(),
+    .I2C0_SCL_T(),
+    .I2C1_SDA_I(1\'B0),
+    .I2C1_SDA_O(),
+    .I2C1_SDA_T(),
+    .I2C1_SCL_I(1\'B0),
+    .I2C1_SCL_O(),
+    .I2C1_SCL_T(),
+    .PJTAG_TCK(1\'B0),
+    .PJTAG_TMS(1\'B0),
+    .PJTAG_TDI(1\'B0),
+    .PJTAG_TDO(),
+    .SDIO0_CLK(),
+    .SDIO0_CLK_FB(1\'B0),
+    .SDIO0_CMD_O(),
+    .SDIO0_CMD_I(1\'B0),
+    .SDIO0_CMD_T(),
+    .SDIO0_DATA_I(4\'B0),
+    .SDIO0_DATA_O(),
+    .SDIO0_DATA_T(),
+    .SDIO0_LED(),
+    .SDIO0_CDN(1\'B0),
+    .SDIO0_WP(SDIO0_WP),
+    .SDIO0_BUSPOW(),
+    .SDIO0_BUSVOLT(),
+    .SDIO1_CLK(),
+    .SDIO1_CLK_FB(1\'B0),
+    .SDIO1_CMD_O(),
+    .SDIO1_CMD_I(1\'B0),
+    .SDIO1_CMD_T(),
+    .SDIO1_DATA_I(4\'B0),
+    .SDIO1_DATA_O(),
+    .SDIO1_DATA_T(),
+    .SDIO1_LED(),
+    .SDIO1_CDN(1\'B0),
+    .SDIO1_WP(1\'B0),
+    .SDIO1_BUSPOW(),
+    .SDIO1_BUSVOLT(),
+    .SPI0_SCLK_I(1\'B0),
+    .SPI0_SCLK_O(),
+    .SPI0_SCLK_T(),
+    .SPI0_MOSI_I(1\'B0),
+    .SPI0_MOSI_O(),
+    .SPI0_MOSI_T(),
+    .SPI0_MISO_I(1\'B0),
+    .SPI0_MISO_O(),
+    .SPI0_MISO_T(),
+    .SPI0_SS_I(1\'B0),
+    .SPI0_SS_O(),
+    .SPI0_SS1_O(),
+    .SPI0_SS2_O(),
+    .SPI0_SS_T(),
+    .SPI1_SCLK_I(1\'B0),
+    .SPI1_SCLK_O(),
+    .SPI1_SCLK_T(),
+    .SPI1_MOSI_I(1\'B0),
+    .SPI1_MOSI_O(),
+    .SPI1_MOSI_T(),
+    .SPI1_MISO_I(1\'B0),
+    .SPI1_MISO_O(),
+    .SPI1_MISO_T(),
+    .SPI1_SS_I(1\'B0),
+    .SPI1_SS_O(),
+    .SPI1_SS1_O(),
+    .SPI1_SS2_O(),
+    .SPI1_SS_T(),
+    .UART0_DTRN(),
+    .UART0_RTSN(),
+    .UART0_TX(),
+    .UART0_CTSN(1\'B0),
+    .UART0_DCDN(1\'B0),
+    .UART0_DSRN(1\'B0),
+    .UART0_RIN(1\'B0),
+    .UART0_RX(1\'B1),
+    .UART1_DTRN(),
+    .UART1_RTSN(),
+    .UART1_TX(),
+    .UART1_CTSN(1\'B0),
+    .UART1_DCDN(1\'B0),
+    .UART1_DSRN(1\'B0),
+    .UART1_RIN(1\'B0),
+    .UART1_RX(1\'B1),
+    .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+    .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+    .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+    .TTC0_CLK0_IN(1\'B0),
+    .TTC0_CLK1_IN(1\'B0),
+    .TTC0_CLK2_IN(1\'B0),
+    .TTC1_WAVE0_OUT(),
+    .TTC1_WAVE1_OUT(),
+    .TTC1_WAVE2_OUT(),
+    .TTC1_CLK0_IN(1\'B0),
+    .TTC1_CLK1_IN(1\'B0),
+    .TTC1_CLK2_IN(1\'B0),
+    .WDT_CLK_IN(1\'B0),
+    .WDT_RST_OUT(),
+    .TRACE_CLK(1\'B0),
+    .TRACE_CLK_OUT(),
+    .TRACE_CTL(),
+    .TRACE_DATA(),
+    .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+    .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+    .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+    .USB1_PORT_INDCTL(),
+    .USB1_VBUS_PWRSELECT(),
+    .USB1_VBUS_PWRFAULT(1\'B0),
+    .SRAM_INTIN(1\'B0),
+    .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+    .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+    .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+    .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+    .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+    .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+    .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+    .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+    .M_AXI_GP0_WID(M_AXI_GP0_WID),
+    .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+    .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+    .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+    .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+    .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+    .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+    .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+    .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+    .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+    .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+    .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+    .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+    .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+    .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+    .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+    .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+    .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+    .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+    .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+    .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+    .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+    .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+    .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+    .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+    .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+    .M_AXI_GP0_BID(M_AXI_GP0_BID),
+    .M_AXI_GP0_RID(M_AXI_GP0_RID),
+    .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+    .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+    .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+    .M_AXI_GP1_ARVALID(),
+    .M_AXI_GP1_AWVALID(),
+    .M_AXI_GP1_BREADY(),
+    .M_AXI_GP1_RREADY(),
+    .M_AXI_GP1_WLAST(),
+    .M_AXI_GP1_WVALID(),
+    .M_AXI_GP1_ARID(),
+    .M_AXI_GP1_AWID(),
+    .M_AXI_GP1_WID(),
+    .M_AXI_GP1_ARBURST(),
+    .M_AXI_GP1_ARLOCK(),
+    .M_AXI_GP1_ARSIZE(),
+    .M_AXI_GP1_AWBURST(),
+    .M_AXI_GP1_AWLOCK(),
+    .M_AXI_GP1_AWSIZE(),
+    .M_AXI_GP1_ARPROT(),
+    .M_AXI_GP1_AWPROT(),
+    .M_AXI_GP1_ARADDR(),
+    .M_AXI_GP1_AWADDR(),
+    .M_AXI_GP1_WDATA(),
+    .M_AXI_GP1_ARCACHE(),
+    .M_AXI_GP1_ARLEN(),
+    .M_AXI_GP1_ARQOS(),
+    .M_AXI_GP1_AWCACHE(),
+    .M_AXI_GP1_AWLEN(),
+    .M_AXI_GP1_AWQOS(),
+    .M_AXI_GP1_WSTRB(),
+    .M_AXI_GP1_ACLK(1\'B0),
+    .M_AXI_GP1_ARREADY(1\'B0),
+    .M_AXI_GP1_AWREADY(1\'B0),
+    .M_AXI_GP1_BVALID(1\'B0),
+    .M_AXI_GP1_RLAST(1\'B0),
+    .M_AXI_GP1_RVALID(1\'B0),
+    .M_AXI_GP1_WREADY(1\'B0),
+    .M_AXI_GP1_BID(12\'B0),
+    .M_AXI_GP1_RID(12\'B0),
+    .M_AXI_GP1_BRESP(2\'B0),
+    .M_AXI_GP1_RRESP(2\'B0),
+    .M_AXI_GP1_RDATA(32\'B0),
+    .S_AXI_GP0_ARREADY(),
+    .S_AXI_GP0_AWREADY(),
+    .S_AXI_GP0_BVALID(),
+    .S_AXI_GP0_RLAST(),
+    .S_AXI_GP0_RVALID(),
+    .S_AXI_GP0_WREADY(),
+    .S_AXI_GP0_BRESP(),
+    .S_AXI_GP0_RRESP(),
+    .S_AXI_GP0_RDATA(),
+    .S_AXI_GP0_BID(),
+    .S_AXI_GP0_RID(),
+    .S_AXI_GP0_ACLK(1\'B0),
+    .S_AXI_GP0_ARVALID(1\'B0),
+    .S_AXI_GP0_AWVALID(1\'B0),
+    .S_AXI_GP0_BREADY(1\'B0),
+    .S_AXI_GP0_RREADY(1\'B0),
+    .S_AXI_GP0_WLAST(1\'B0),
+    .S_AXI_GP0_WVALID(1\'B0),
+    .S_AXI_GP0_ARBURST(2\'B0),
+    .S_AXI_GP0_ARLOCK(2\'B0),
+    .S_AXI_GP0_ARSIZE(3\'B0),
+    .S_AXI_GP0_AWBURST(2\'B0),
+    .S_AXI_GP0_AWLOCK(2\'B0),
+    .S_AXI_GP0_AWSIZE(3\'B0),
+    .S_AXI_GP0_ARPROT(3\'B0),
+    .S_AXI_GP0_AWPROT(3\'B0),
+    .S_AXI_GP0_ARADDR(32\'B0),
+    .S_AXI_GP0_AWADDR(32\'B0),
+    .S_AXI_GP0_WDATA(32\'B0),
+    .S_AXI_GP0_ARCACHE(4\'B0),
+    .S_AXI_GP0_ARLEN(4\'B0),
+    .S_AXI_GP0_ARQOS(4\'B0),
+    .S_AXI_GP0_AWCACHE(4\'B0),
+    .S_AXI_GP0_AWLEN(4\'B0),
+    .S_AXI_GP0_AWQOS(4\'B0),
+    .S_AXI_GP0_WSTRB(4\'B0),
+    .S_AXI_GP0_ARID(6\'B0),
+    .S_AXI_GP0_AWID(6\'B0),
+    .S_AXI_GP0_WID(6\'B0),
+    .S_AXI_GP1_ARREADY(),
+    .S_AXI_GP1_AWREADY(),
+    .S_AXI_GP1_BVALID(),
+    .S_AXI_GP1_RLAST(),
+    .S_AXI_GP1_RVALID(),
+    .S_AXI_GP1_WREADY(),
+    .S_AXI_GP1_BRESP(),
+    .S_AXI_GP1_RRESP(),
+    .S_AXI_GP1_RDATA(),
+    .S_AXI_GP1_BID(),
+    .S_AXI_GP1_RID(),
+    .S_AXI_GP1_ACLK(1\'B0),
+    .S_AXI_GP1_ARVALID(1\'B0),
+    .S_AXI_GP1_AWVALID(1\'B0),
+    .S_AXI_GP1_BREADY(1\'B0),
+    .S_AXI_GP1_RREADY(1\'B0),
+    .S_AXI_GP1_WLAST(1\'B0),
+    .S_AXI_GP1_WVALID(1\'B0),
+    .S_AXI_GP1_ARBURST(2\'B0),
+    .S_AXI_GP1_ARLOCK(2\'B0),
+    .S_AXI_GP1_ARSIZE(3\'B0),
+    .S_AXI_GP1_AWBURST(2\'B0),
+    .S_AXI_GP1_AWLOCK(2\'B0),
+    .S_AXI_GP1_AWSIZE(3\'B0),
+    .S_AXI_GP1_ARPROT(3\'B0),
+    .S_AXI_GP1_AWPROT(3\'B0),
+    .S_AXI_GP1_ARADDR(32\'B0),
+    .S_AXI_GP1_AWADDR(32\'B0),
+    .S_AXI_GP1_WDATA(32\'B0),
+    .S_AXI_GP1_ARCACHE(4\'B0),
+    .S_AXI_GP1_ARLEN(4\'B0),
+    .S_AXI_GP1_ARQOS(4\'B0),
+    .S_AXI_GP1_AWCACHE(4\'B0),
+    .S_AXI_GP1_AWLEN(4\'B0),
+    .S_AXI_GP1_AWQOS(4\'B0),
+    .S_AXI_GP1_WSTRB(4\'B0),
+    .S_AXI_GP1_ARID(6\'B0),
+    .S_AXI_GP1_AWID(6\'B0),
+    .S_AXI_GP1_WID(6\'B0),
+    .S_AXI_ACP_ARREADY(),
+    .S_AXI_ACP_AWREADY(),
+    .S_AXI_ACP_BVALID(),
+    .S_AXI_ACP_RLAST(),
+    .S_AXI_ACP_RVALID(),
+    .S_AXI_ACP_WREADY(),
+    .S_AXI_ACP_BRESP(),
+    .S_AXI_ACP_RRESP(),
+    .S_AXI_ACP_BID(),
+    .S_AXI_ACP_RID(),
+    .S_AXI_ACP_RDATA(),
+    .S_AXI_ACP_ACLK(1\'B0),
+    .S_AXI_ACP_ARVALID(1\'B0),
+    .S_AXI_ACP_AWVALID(1\'B0),
+    .S_AXI_ACP_BREADY(1\'B0),
+    .S_AXI_ACP_RREADY(1\'B0),
+    .S_AXI_ACP_WLAST(1\'B0),
+    .S_AXI_ACP_WVALID(1\'B0),
+    .S_AXI_ACP_ARID(3\'B0),
+    .S_AXI_ACP_ARPROT(3\'B0),
+    .S_AXI_ACP_AWID(3\'B0),
+    .S_AXI_ACP_AWPROT(3\'B0),
+    .S_AXI_ACP_WID(3\'B0),
+    .S_AXI_ACP_ARADDR(32\'B0),
+    .S_AXI_ACP_AWADDR(32\'B0),
+    .S_AXI_ACP_ARCACHE(4\'B0),
+    .S_AXI_ACP_ARLEN(4\'B0),
+    .S_AXI_ACP_ARQOS(4\'B0),
+    .S_AXI_ACP_AWCACHE(4\'B0),
+    .S_AXI_ACP_AWLEN(4\'B0),
+    .S_AXI_ACP_AWQOS(4\'B0),
+    .S_AXI_ACP_ARBURST(2\'B0),
+    .S_AXI_ACP_ARLOCK(2\'B0),
+    .S_AXI_ACP_ARSIZE(3\'B0),
+    .S_AXI_ACP_AWBURST(2\'B0),
+    .S_AXI_ACP_AWLOCK(2\'B0),
+    .S_AXI_ACP_AWSIZE(3\'B0),
+    .S_AXI_ACP_ARUSER(5\'B0),
+    .S_AXI_ACP_AWUSER(5\'B0),
+    .S_AXI_ACP_WDATA(64\'B0),
+    .S_AXI_ACP_WSTRB(8\'B0),
+    .S_AXI_HP0_ARREADY(),
+    .S_AXI_HP0_AWREADY(),
+    .S_AXI_HP0_BVALID(),
+    .S_AXI_HP0_RLAST(),
+    .S_AXI_HP0_RVALID(),
+    .S_AXI_HP0_WREADY(),
+    .S_AXI_HP0_BRESP(),
+    .S_AXI_HP0_RRESP(),
+    .S_AXI_HP0_BID(),
+    .S_AXI_HP0_RID(),
+    .S_AXI_HP0_RDATA(),
+    .S_AXI_HP0_RCOUNT(),
+    .S_AXI_HP0_WCOUNT(),
+    .S_AXI_HP0_RACOUNT(),
+    .S_AXI_HP0_WACOUNT(),
+    .S_AXI_HP0_ACLK(1\'B0),
+    .S_AXI_HP0_ARVALID(1\'B0),
+    .S_AXI_HP0_AWVALID(1\'B0),
+    .S_AXI_HP0_BREADY(1\'B0),
+    .S_AXI_HP0_RDISSUECAP1_EN(1\'B0),
+    .S_AXI_HP0_RREADY(1\'B0),
+    .S_AXI_HP0_WLAST(1\'B0),
+    .S_AXI_HP0_WRISSUECAP1_EN(1\'B0),
+    .S_AXI_HP0_WVALID(1\'B0),
+    .S_AXI_HP0_ARBURST(2\'B0),
+    .S_AXI_HP0_ARLOCK(2\'B0),
+    .S_AXI_HP0_ARSIZE(3\'B0),
+    .S_AXI_HP0_AWBURST(2\'B0),
+    .S_AXI_HP0_AWLOCK(2\'B0),
+    .S_AXI_HP0_AWSIZE(3\'B0),
+    .S_AXI_HP0_ARPROT(3\'B0),
+    .S_AXI_HP0_AWPROT(3\'B0),
+    .S_AXI_HP0_ARADDR(32\'B0),
+    .S_AXI_HP0_AWADDR(32\'B0),
+    .S_AXI_HP0_ARCACHE(4\'B0),
+    .S_AXI_HP0_ARLEN(4\'B0),
+    .S_AXI_HP0_ARQOS(4\'B0),
+    .S_AXI_HP0_AWCACHE(4\'B0),
+    .S_AXI_HP0_AWLEN(4\'B0),
+    .S_AXI_HP0_AWQOS(4\'B0),
+    .S_AXI_HP0_ARID(6\'B0),
+    .S_AXI_HP0_AWID(6\'B0),
+    .S_AXI_HP0_WID(6\'B0),
+    .S_AXI_HP0_WDATA(64\'B0),
+    .S_AXI_HP0_WSTRB(8\'B0),
+    .S_AXI_HP1_ARREADY(),
+    .S_AXI_HP1_AWREADY(),
+    .S_AXI_HP1_BVALID(),
+    .S_AXI_HP1_RLAST(),
+    .S_AXI_HP1_RVALID(),
+    .S_AXI_HP1_WREADY(),
+    .S_AXI_HP1_BRESP(),
+    .S_AXI_HP1_RRESP(),
+    .S_AXI_HP1_BID(),
+    .S_AXI_HP1_RID(),
+    .S_AXI_HP1_RDATA(),
+    .S_AXI_HP1_RCOUNT(),
+    .S_AXI_HP1_WCOUNT(),
+    .S_AXI_HP1_RACOUNT(),
+    .S_AXI_HP1_WACOUNT(),
+    .S_AXI_HP1_ACLK(1\'B0),
+    .S_AXI_HP1_ARVALID(1\'B0),
+    .S_AXI_HP1_AWVALID(1\'B0),
+    .S_AXI_HP1_BREADY(1\'B0),
+    .S_AXI_HP1_RDISSUECAP1_EN(1\'B0),
+    .S_AXI_HP1_RREADY(1\'B0),
+    .S_AXI_HP1_WLAST(1\'B0),
+    .S_AXI_HP1_WRISSUECAP1_EN(1\'B0),
+    .S_AXI_HP1_WVALID(1\'B0),
+    .S_AXI_HP1_ARBURST(2\'B0),
+    .S_AXI_HP1_ARLOCK(2\'B0),
+    .S_AXI_HP1_ARSIZE(3\'B0),
+    .S_AXI_HP1_AWBURST(2\'B0),
+    .S_AXI_HP1_AWLOCK(2\'B0),
+    .S_AXI_HP1_AWSIZE(3\'B0),
+    .S_AXI_HP1_ARPROT(3\'B0),
+    .S_AXI_HP1_AWPROT(3\'B0),
+    .S_AXI_HP1_ARADDR(32\'B0),
+    .S_AXI_HP1_AWADDR(32\'B0),
+    .S_AXI_HP1_ARCACHE(4\'B0),
+    .S_AXI_HP1_ARLEN(4\'B0),
+    .S_AXI_HP1_ARQOS(4\'B0),
+    .S_AXI_HP1_AWCACHE(4\'B0),
+    .S_AXI_HP1_AWLEN(4\'B0),
+    .S_AXI_HP1_AWQOS(4\'B0),
+    .S_AXI_HP1_ARID(6\'B0),
+    .S_AXI_HP1_AWID(6\'B0),
+    .S_AXI_HP1_WID(6\'B0),
+    .S_AXI_HP1_WDATA(64\'B0),
+    .S_AXI_HP1_WSTRB(8\'B0),
+    .S_AXI_HP2_ARREADY(),
+    .S_AXI_HP2_AWREADY(),
+    .S_AXI_HP2_BVALID(),
+    .S_AXI_HP2_RLAST(),
+    .S_AXI_HP2_RVALID(),
+    .S_AXI_HP2_WREADY(),
+    .S_AXI_HP2_BRESP(),
+    .S_AXI_HP2_RRESP(),
+    .S_AXI_HP2_BID(),
+    .S_AXI_HP2_RID(),
+    .S_AXI_HP2_RDATA(),
+    .S_AXI_HP2_RCOUNT(),
+    .S_AXI_HP2_WCOUNT(),
+    .S_AXI_HP2_RACOUNT(),
+    .S_AXI_HP2_WACOUNT(),
+    .S_AXI_HP2_ACLK(1\'B0),
+    .S_AXI_HP2_ARVALID(1\'B0),
+    .S_AXI_HP2_AWVALID(1\'B0),
+    .S_AXI_HP2_BREADY(1\'B0),
+    .S_AXI_HP2_RDISSUECAP1_EN(1\'B0),
+    .S_AXI_HP2_RREADY(1\'B0),
+    .S_AXI_HP2_WLAST(1\'B0),
+    .S_AXI_HP2_WRISSUECAP1_EN(1\'B0),
+    .S_AXI_HP2_WVALID(1\'B0),
+    .S_AXI_HP2_ARBURST(2\'B0),
+    .S_AXI_HP2_ARLOCK(2\'B0),
+    .S_AXI_HP2_ARSIZE(3\'B0),
+    .S_AXI_HP2_AWBURST(2\'B0),
+    .S_AXI_HP2_AWLOCK(2\'B0),
+    .S_AXI_HP2_AWSIZE(3\'B0),
+    .S_AXI_HP2_ARPROT(3\'B0),
+    .S_AXI_HP2_AWPROT(3\'B0),
+    .S_AXI_HP2_ARADDR(32\'B0),
+    .S_AXI_HP2_AWADDR(32\'B0),
+    .S_AXI_HP2_ARCACHE(4\'B0),
+    .S_AXI_HP2_ARLEN(4\'B0),
+    .S_AXI_HP2_ARQOS(4\'B0),
+    .S_AXI_HP2_AWCACHE(4\'B0),
+    .S_AXI_HP2_AWLEN(4\'B0),
+    .S_AXI_HP2_AWQOS(4\'B0),
+    .S_AXI_HP2_ARID(6\'B0),
+    .S_AXI_HP2_AWID(6\'B0),
+    .S_AXI_HP2_WID(6\'B0),
+    .S_AXI_HP2_WDATA(64\'B0),
+    .S_AXI_HP2_WSTRB(8\'B0),
+    .S_AXI_HP3_ARREADY(),
+    .S_AXI_HP3_AWREADY(),
+    .S_AXI_HP3_BVALID(),
+    .S_AXI_HP3_RLAST(),
+    .S_AXI_HP3_RVALID(),
+    .S_AXI_HP3_WREADY(),
+    .S_AXI_HP3_BRESP(),
+    .S_AXI_HP3_RRESP(),
+    .S_AXI_HP3_BID(),
+    .S_AXI_HP3_RID(),
+    .S_AXI_HP3_RDATA(),
+    .S_AXI_HP3_RCOUNT(),
+    .S_AXI_HP3_WCOUNT(),
+    .S_AXI_HP3_RACOUNT(),
+    .S_AXI_HP3_WACOUNT(),
+    .S_AXI_HP3_ACLK(1\'B0),
+    .S_AXI_HP3_ARVALID(1\'B0),
+    .S_AXI_HP3_AWVALID(1\'B0),
+    .S_AXI_HP3_BREADY(1\'B0),
+    .S_AXI_HP3_RDISSUECAP1_EN(1\'B0),
+    .S_AXI_HP3_RREADY(1\'B0),
+    .S_AXI_HP3_WLAST(1\'B0),
+    .S_AXI_HP3_WRISSUECAP1_EN(1\'B0),
+    .S_AXI_HP3_WVALID(1\'B0),
+    .S_AXI_HP3_ARBURST(2\'B0),
+    .S_AXI_HP3_ARLOCK(2\'B0),
+    .S_AXI_HP3_ARSIZE(3\'B0),
+    .S_AXI_HP3_AWBURST(2\'B0),
+    .S_AXI_HP3_AWLOCK(2\'B0),
+    .S_AXI_HP3_AWSIZE(3\'B0),
+    .S_AXI_HP3_ARPROT(3\'B0),
+    .S_AXI_HP3_AWPROT(3\'B0),
+    .S_AXI_HP3_ARADDR(32\'B0),
+    .S_AXI_HP3_AWADDR(32\'B0),
+    .S_AXI_HP3_ARCACHE(4\'B0),
+    .S_AXI_HP3_ARLEN(4\'B0),
+    .S_AXI_HP3_ARQOS(4\'B0),
+    .S_AXI_HP3_AWCACHE(4\'B0),
+    .S_AXI_HP3_AWLEN(4\'B0),
+    .S_AXI_HP3_AWQOS(4\'B0),
+    .S_AXI_HP3_ARID(6\'B0),
+    .S_AXI_HP3_AWID(6\'B0),
+    .S_AXI_HP3_WID(6\'B0),
+    .S_AXI_HP3_WDATA(64\'B0),
+    .S_AXI_HP3_WSTRB(8\'B0),
+    .IRQ_P2F_DMAC_ABORT(),
+    .IRQ_P2F_DMAC0(),
+    .IRQ_P2F_DMAC1(),
+    .IRQ_P2F_DMAC2(),
+    .IRQ_P2F_DMAC3(),
+    .IRQ_P2F_DMAC4(),
+    .IRQ_P2F_DMAC5(),
+    .IRQ_P2F_DMAC6(),
+    .IRQ_P2F_DMAC7(),
+    .IRQ_P2F_SMC(),
+    .IRQ_P2F_QSPI(),
+    .IRQ_P2F_CTI(),
+    .IRQ_P2F_GPIO(),
+    .IRQ_P2F_USB0(),
+    .IRQ_P2F_ENET0(),
+    .IRQ_P2F_ENET_WAKE0(),
+    .IRQ_P2F_SDIO0(),
+    .IRQ_P2F_I2C0(),
+    .IRQ_P2F_SPI0(),
+    .IRQ_P2F_UART0(),
+    .IRQ_P2F_CAN0(),
+    .IRQ_P2F_USB1(),
+    .IRQ_P2F_ENET1(),
+    .IRQ_P2F_ENET_WAKE1(),
+    .IRQ_P2F_SDIO1(),
+    .IRQ_P2F_I2C1(),
+    .IRQ_P2F_SPI1(),
+    .IRQ_P2F_UART1(),
+    .IRQ_P2F_CAN1(),
+    .IRQ_F2P(1\'B0),
+    .Core0_nFIQ(1\'B0),
+    .Core0_nIRQ(1\'B0),
+    .Core1_nFIQ(1\'B0),
+    .Core1_nIRQ(1\'B0),
+    .DMA0_DATYPE(),
+    .DMA0_DAVALID(),
+    .DMA0_DRREADY(),
+    .DMA1_DATYPE(),
+    .DMA1_DAVALID(),
+    .DMA1_DRREADY(),
+    .DMA2_DATYPE(),
+    .DMA2_DAVALID(),
+    .DMA2_DRREADY(),
+    .DMA3_DATYPE(),
+    .DMA3_DAVALID(),
+    .DMA3_DRREADY(),
+    .DMA0_ACLK(1\'B0),
+    .DMA0_DAREADY(1\'B0),
+    .DMA0_DRLAST(1\'B0),
+    .DMA0_DRVALID(1\'B0),
+    .DMA1_ACLK(1\'B0),
+    .DMA1_DAREADY(1\'B0),
+    .DMA1_DRLAST(1\'B0),
+    .DMA1_DRVALID(1\'B0),
+    .DMA2_ACLK(1\'B0),
+    .DMA2_DAREADY(1\'B0),
+    .DMA2_DRLAST(1\'B0),
+    .DMA2_DRVALID(1\'B0),
+    .DMA3_ACLK(1\'B0),
+    .DMA3_DAREADY(1\'B0),
+    .DMA3_DRLAST(1\'B0),
+    .DMA3_DRVALID(1\'B0),
+    .DMA0_DRTYPE(2\'B0),
+    .DMA1_DRTYPE(2\'B0),
+    .DMA2_DRTYPE(2\'B0),
+    .DMA3_DRTYPE(2\'B0),
+    .FCLK_CLK0(FCLK_CLK0),
+    .FCLK_CLK1(),
+    .FCLK_CLK2(),
+    .FCLK_CLK3(),
+    .FCLK_CLKTRIG0_N(1\'B0),
+    .FCLK_CLKTRIG1_N(1\'B0),
+    .FCLK_CLKTRIG2_N(1\'B0),
+    .FCLK_CLKTRIG3_N(1\'B0),
+    .FCLK_RESET0_N(FCLK_RESET0_N),
+    .FCLK_RESET1_N(),
+    .FCLK_RESET2_N(),
+    .FCLK_RESET3_N(),
+    .FTMD_TRACEIN_DATA(32\'B0),
+    .FTMD_TRACEIN_VALID(1\'B0),
+    .FTMD_TRACEIN_CLK(1\'B0),
+    .FTMD_TRACEIN_ATID(4\'B0),
+    .FTMT_F2P_TRIG_0(1\'B0),
+    .FTMT_F2P_TRIGACK_0(),
+    .FTMT_F2P_TRIG_1(1\'B0),
+    .FTMT_F2P_TRIGACK_1(),
+    .FTMT_F2P_TRIG_2(1\'B0),
+    .FTMT_F2P_TRIGACK_2(),
+    .FTMT_F2P_TRIG_3(1\'B0),
+    .FTMT_F2P_TRIGACK_3(),
+    .FTMT_F2P_DEBUG(32\'B0),
+    .FTMT_P2F_TRIGACK_0(1\'B0),
+    .FTMT_P2F_TRIG_0(),
+    .FTMT_P2F_TRIGACK_1(1\'B0),
+    .FTMT_P2F_TRIG_1(),
+    .FTMT_P2F_TRIGACK_2(1\'B0),
+    .FTMT_P2F_TRIG_2(),
+    .FTMT_P2F_TRIGACK_3(1\'B0),
+    .FTMT_P2F_TRIG_3(),
+    .FTMT_P2F_DEBUG(),
+    .FPGA_IDLE_N(1\'B0),
+    .EVENT_EVENTO(),
+    .EVENT_STANDBYWFE(),
+    .EVENT_STANDBYWFI(),
+    .EVENT_EVENTI(1\'B0),
+    .DDR_ARB(4\'B0),
+    .MIO(MIO),
+    .DDR_CAS_n(DDR_CAS_n),
+    .DDR_CKE(DDR_CKE),
+    .DDR_Clk_n(DDR_Clk_n),
+    .DDR_Clk(DDR_Clk),
+    .DDR_CS_n(DDR_CS_n),
+    .DDR_DRSTB(DDR_DRSTB),
+    .DDR_ODT(DDR_ODT),
+    .DDR_RAS_n(DDR_RAS_n),
+    .DDR_WEB(DDR_WEB),
+    .DDR_BankAddr(DDR_BankAddr),
+    .DDR_Addr(DDR_Addr),
+    .DDR_VRN(DDR_VRN),
+    .DDR_VRP(DDR_VRP),
+    .DDR_DM(DDR_DM),
+    .DDR_DQ(DDR_DQ),
+    .DDR_DQS_n(DDR_DQS_n),
+    .DDR_DQS(DDR_DQS),
+    .PS_SRSTB(PS_SRSTB),
+    .PS_CLK(PS_CLK),
+    .PS_PORB(PS_PORB)
+  );
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 03:23:40 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_sim_netlist.v
+// Design      : design_1_axi_intc_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
+   (p_15_in,
+    p_17_in,
+    \\mer_int_reg[0] ,
+    D,
+    ip2bus_wrack_prev2,
+    ip2bus_rdack_prev2,
+    Or128_vec2stdlogic19_out,
+    \\mer_int_reg[0]_0 ,
+    \\mer_int_reg[1] ,
+    \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
+    \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
+    ip2bus_wrack_int_d1_reg,
+    Q,
+    s_axi_aclk,
+    is_write_reg,
+    ip2bus_wrack,
+    s_axi_aresetn,
+    ip2bus_rdack,
+    is_read,
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
+    \\bus2ip_addr_i_reg[8] ,
+    \\IPR_GEN.ipr_reg[0] ,
+    \\bus2ip_addr_i_reg[3] ,
+    \\bus2ip_addr_i_reg[2] ,
+    \\IVR_GEN.ivr_reg[0] ,
+    ip2bus_wrack_int_d1,
+    ip2bus_rdack_int_d1,
+    s_axi_wdata,
+    \\mer_int_reg[0]_1 ,
+    p_0_in,
+    sie,
+    cie,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ,
+    bus2ip_rnw_i_reg);
+  output p_15_in;
+  output p_17_in;
+  output \\mer_int_reg[0] ;
+  output [2:0]D;
+  output ip2bus_wrack_prev2;
+  output ip2bus_rdack_prev2;
+  output Or128_vec2stdlogic19_out;
+  output \\mer_int_reg[0]_0 ;
+  output \\mer_int_reg[1] ;
+  output \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  output \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  output \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  output ip2bus_wrack_int_d1_reg;
+  input Q;
+  input s_axi_aclk;
+  input is_write_reg;
+  input ip2bus_wrack;
+  input s_axi_aresetn;
+  input ip2bus_rdack;
+  input is_read;
+  input [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  input [6:0]\\bus2ip_addr_i_reg[8] ;
+  input \\IPR_GEN.ipr_reg[0] ;
+  input \\bus2ip_addr_i_reg[3] ;
+  input \\bus2ip_addr_i_reg[2] ;
+  input \\IVR_GEN.ivr_reg[0] ;
+  input ip2bus_wrack_int_d1;
+  input ip2bus_rdack_int_d1;
+  input [1:0]s_axi_wdata;
+  input \\mer_int_reg[0]_1 ;
+  input p_0_in;
+  input sie;
+  input cie;
+  input \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+  input bus2ip_rnw_i_reg;
+
+  wire Bus_RNW_reg_i_1_n_0;
+  wire \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  wire [2:0]D;
+  wire \\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ;
+  wire \\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  wire \\IPR_GEN.ipr_reg[0] ;
+  wire \\IVR_GEN.ivr_reg[0] ;
+  wire Or128_vec2stdlogic19_out;
+  wire Q;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+  wire \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  wire \\bus2ip_addr_i_reg[2] ;
+  wire \\bus2ip_addr_i_reg[3] ;
+  wire [6:0]\\bus2ip_addr_i_reg[8] ;
+  wire bus2ip_rnw_i_reg;
+  wire cie;
+  wire cs_ce_clr;
+  wire ip2bus_rdack;
+  wire ip2bus_rdack_int_d1;
+  wire ip2bus_rdack_prev2;
+  wire ip2bus_wrack;
+  wire ip2bus_wrack_int_d1;
+  wire ip2bus_wrack_int_d1_i_2_n_0;
+  wire ip2bus_wrack_int_d1_i_3_n_0;
+  wire ip2bus_wrack_int_d1_reg;
+  wire ip2bus_wrack_prev2;
+  wire is_read;
+  wire is_write_reg;
+  wire \\mer_int_reg[0] ;
+  wire \\mer_int_reg[0]_0 ;
+  wire \\mer_int_reg[0]_1 ;
+  wire \\mer_int_reg[1] ;
+  wire p_0_in;
+  wire p_10_in;
+  wire p_11_in;
+  wire p_12_in;
+  wire p_13_in;
+  wire p_14_in;
+  wire p_14_out;
+  wire p_15_in;
+  wire p_15_out;
+  wire p_16_in;
+  wire p_17_in;
+  wire p_1_out;
+  wire p_2_in;
+  wire p_2_out;
+  wire p_3_in;
+  wire p_3_out;
+  wire p_4_in;
+  wire p_4_out;
+  wire p_5_in;
+  wire p_5_out;
+  wire p_6_in;
+  wire p_6_out;
+  wire p_7_in;
+  wire p_7_out;
+  wire p_8_in;
+  wire p_8_out;
+  wire p_9_in;
+  wire p_9_out;
+  wire pselect_hit_i_0;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire \\s_axi_rdata_i[0]_i_2_n_0 ;
+  wire \\s_axi_rdata_i[31]_i_3_n_0 ;
+  wire \\s_axi_rdata_i[31]_i_4_n_0 ;
+  wire [1:0]s_axi_wdata;
+  wire sie;
+
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    Bus_RNW_reg_i_1
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(Q),
+        .I2(\\mer_int_reg[0] ),
+        .O(Bus_RNW_reg_i_1_n_0));
+  FDRE Bus_RNW_reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_i_1_n_0),
+        .Q(\\mer_int_reg[0] ),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h02000000)) 
+    \\CIE_GEN.CIE_BIT_GEN[0].cie[0]_i_1 
+       (.I0(s_axi_aresetn),
+        .I1(cie),
+        .I2(\\mer_int_reg[0] ),
+        .I3(p_12_in),
+        .I4(s_axi_wdata[0]),
+        .O(\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00010000)) 
+    \\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [0]),
+        .I3(\\bus2ip_addr_i_reg[8] [3]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(\\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ),
+        .Q(p_17_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h00400000)) 
+    \\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [2]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(p_5_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_5_out),
+        .Q(p_7_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h40000000)) 
+    \\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [2]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .O(p_4_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_4_out),
+        .Q(p_6_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'h00400000)) 
+    \\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(p_3_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_3_out),
+        .Q(p_5_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h40000000)) 
+    \\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .O(p_2_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_2_out),
+        .Q(p_4_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'h00800000)) 
+    \\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(p_1_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_1_out),
+        .Q(p_3_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h80000000)) 
+    \\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .O(p_15_out));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'h0002)) 
+    \\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2 
+       (.I0(Q),
+        .I1(\\bus2ip_addr_i_reg[8] [5]),
+        .I2(\\bus2ip_addr_i_reg[8] [4]),
+        .I3(\\bus2ip_addr_i_reg[8] [6]),
+        .O(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_15_out),
+        .Q(p_2_in),
+        .R(cs_ce_clr));
+  LUT6 #(
+    .INIT(64\'hFFCFFFFFFFCFFFEF)) 
+    \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1 
+       (.I0(is_write_reg),
+        .I1(ip2bus_wrack),
+        .I2(s_axi_aresetn),
+        .I3(ip2bus_rdack),
+        .I4(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ),
+        .I5(is_read),
+        .O(cs_ce_clr));
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_2 
+       (.I0(Q),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\bus2ip_addr_i_reg[8] [5]),
+        .O(pselect_hit_i_0));
+  LUT4 #(
+    .INIT(16\'hFFFD)) 
+    \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
+        .O(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(pselect_hit_i_0),
+        .Q(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT5 #(
+    .INIT(32\'h01000000)) 
+    \\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(p_14_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_14_out),
+        .Q(p_16_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT5 #(
+    .INIT(32\'h00100000)) 
+    \\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [0]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .O(\\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1_n_0 ),
+        .Q(p_15_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT5 #(
+    .INIT(32\'h00400000)) 
+    \\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .O(\\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ),
+        .Q(p_14_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT5 #(
+    .INIT(32\'h00100000)) 
+    \\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [0]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(\\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
+        .Q(p_13_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT5 #(
+    .INIT(32\'h00400000)) 
+    \\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(\\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ),
+        .Q(p_12_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h10000000)) 
+    \\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [0]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(p_9_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_9_out),
+        .Q(p_11_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT5 #(
+    .INIT(32\'h40000000)) 
+    \\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(p_8_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_8_out),
+        .Q(p_10_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h00100000)) 
+    \\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(p_7_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_7_out),
+        .Q(p_9_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h02000000)) 
+    \\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1 
+       (.I0(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .O(p_6_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_6_out),
+        .Q(p_8_in),
+        .R(cs_ce_clr));
+  LUT5 #(
+    .INIT(32\'h00004000)) 
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar[0]_i_1 
+       (.I0(\\mer_int_reg[0] ),
+        .I1(s_axi_wdata[0]),
+        .I2(p_14_in),
+        .I3(s_axi_aresetn),
+        .I4(\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
+        .O(\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ));
+  LUT5 #(
+    .INIT(32\'h00004000)) 
+    \\SIE_GEN.SIE_BIT_GEN[0].sie[0]_i_1 
+       (.I0(\\mer_int_reg[0] ),
+        .I1(p_13_in),
+        .I2(s_axi_wdata[0]),
+        .I3(s_axi_aresetn),
+        .I4(sie),
+        .O(\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ));
+  LUT6 #(
+    .INIT(64\'h00000000FFFB0000)) 
+    ip2bus_rdack_i_1
+       (.I0(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I1(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I2(ip2bus_wrack_int_d1_i_3_n_0),
+        .I3(ip2bus_wrack_int_d1_i_2_n_0),
+        .I4(\\mer_int_reg[0] ),
+        .I5(ip2bus_rdack_int_d1),
+        .O(ip2bus_rdack_prev2));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAAA8AA)) 
+    ip2bus_rdack_int_d1_i_1
+       (.I0(\\mer_int_reg[0] ),
+        .I1(ip2bus_wrack_int_d1_i_2_n_0),
+        .I2(ip2bus_wrack_int_d1_i_3_n_0),
+        .I3(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I4(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .O(Or128_vec2stdlogic19_out));
+  LUT6 #(
+    .INIT(64\'h000000000000FFFB)) 
+    ip2bus_wrack_i_1
+       (.I0(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I1(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I2(ip2bus_wrack_int_d1_i_3_n_0),
+        .I3(ip2bus_wrack_int_d1_i_2_n_0),
+        .I4(\\mer_int_reg[0] ),
+        .I5(ip2bus_wrack_int_d1),
+        .O(ip2bus_wrack_prev2));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'h55555455)) 
+    ip2bus_wrack_int_d1_i_1
+       (.I0(\\mer_int_reg[0] ),
+        .I1(ip2bus_wrack_int_d1_i_2_n_0),
+        .I2(ip2bus_wrack_int_d1_i_3_n_0),
+        .I3(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I4(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .O(ip2bus_wrack_int_d1_reg));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    ip2bus_wrack_int_d1_i_2
+       (.I0(p_4_in),
+        .I1(p_3_in),
+        .I2(p_6_in),
+        .I3(p_2_in),
+        .O(ip2bus_wrack_int_d1_i_2_n_0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFFFFFFFE)) 
+    ip2bus_wrack_int_d1_i_3
+       (.I0(p_12_in),
+        .I1(p_14_in),
+        .I2(p_13_in),
+        .I3(p_7_in),
+        .I4(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
+        .I5(p_5_in),
+        .O(ip2bus_wrack_int_d1_i_3_n_0));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\mer_int[0]_i_1 
+       (.I0(s_axi_wdata[0]),
+        .I1(p_10_in),
+        .I2(\\mer_int_reg[0] ),
+        .I3(\\mer_int_reg[0]_1 ),
+        .O(\\mer_int_reg[0]_0 ));
+  LUT4 #(
+    .INIT(16\'hFF20)) 
+    \\mer_int[1]_i_1 
+       (.I0(s_axi_wdata[1]),
+        .I1(\\mer_int_reg[0] ),
+        .I2(p_10_in),
+        .I3(p_0_in),
+        .O(\\mer_int_reg[1] ));
+  LUT6 #(
+    .INIT(64\'h5151510051515151)) 
+    \\s_axi_rdata_i[0]_i_1 
+       (.I0(\\s_axi_rdata_i[31]_i_3_n_0 ),
+        .I1(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I2(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I3(\\IPR_GEN.ipr_reg[0] ),
+        .I4(\\bus2ip_addr_i_reg[3] ),
+        .I5(\\bus2ip_addr_i_reg[2] ),
+        .O(D[0]));
+  LUT3 #(
+    .INIT(8\'h01)) 
+    \\s_axi_rdata_i[0]_i_2 
+       (.I0(p_8_in),
+        .I1(p_11_in),
+        .I2(p_9_in),
+        .O(\\s_axi_rdata_i[0]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0000000055555554)) 
+    \\s_axi_rdata_i[1]_i_1 
+       (.I0(\\s_axi_rdata_i[31]_i_3_n_0 ),
+        .I1(p_9_in),
+        .I2(p_11_in),
+        .I3(p_8_in),
+        .I4(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I5(\\IVR_GEN.ivr_reg[0] ),
+        .O(D[1]));
+  LUT6 #(
+    .INIT(64\'h0000000055555554)) 
+    \\s_axi_rdata_i[31]_i_2 
+       (.I0(\\s_axi_rdata_i[31]_i_3_n_0 ),
+        .I1(p_9_in),
+        .I2(p_11_in),
+        .I3(p_8_in),
+        .I4(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I5(\\bus2ip_addr_i_reg[2] ),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'hFEFF)) 
+    \\s_axi_rdata_i[31]_i_3 
+       (.I0(\\bus2ip_addr_i_reg[8] [5]),
+        .I1(\\bus2ip_addr_i_reg[8] [4]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\mer_int_reg[0] ),
+        .O(\\s_axi_rdata_i[31]_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\s_axi_rdata_i[31]_i_4 
+       (.I0(p_15_in),
+        .I1(p_17_in),
+        .I2(p_16_in),
+        .I3(p_10_in),
+        .O(\\s_axi_rdata_i[31]_i_4_n_0 ));
+endmodule
+
+(* C_ASYNC_INTR = ""-2"" *) (* C_CASCADE_MASTER = ""0"" *) (* C_DISABLE_SYNCHRONIZERS = ""0"" *) 
+(* C_ENABLE_ASYNC = ""0"" *) (* C_EN_CASCADE_MODE = ""0"" *) (* C_FAMILY = ""zynq"" *) 
+(* C_HAS_CIE = ""1"" *) (* C_HAS_FAST = ""0"" *) (* C_HAS_ILR = ""0"" *) 
+(* C_HAS_IPR = ""1"" *) (* C_HAS_IVR = ""1"" *) (* C_HAS_SIE = ""1"" *) 
+(* C_INSTANCE = ""design_1_axi_intc_0_0"" *) (* C_IRQ_ACTIVE = ""1\'b1"" *) (* C_IRQ_IS_LEVEL = ""0"" *) 
+(* C_IVAR_RESET_VALUE = ""16"" *) (* C_KIND_OF_EDGE = ""-1"" *) (* C_KIND_OF_INTR = ""-2"" *) 
+(* C_KIND_OF_LVL = ""-1"" *) (* C_MB_CLK_NOT_CONNECTED = ""1"" *) (* C_NUM_INTR_INPUTS = ""1"" *) 
+(* C_NUM_SW_INTR = ""0"" *) (* C_NUM_SYNC_FF = ""2"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* hdl = ""VHDL"" *) (* imp_netlist = ""TRUE"" *) 
+(* ip_group = ""LOGICORE"" *) (* iptype = ""PERIPHERAL"" *) (* run_ngcbuild = ""TRUE"" *) 
+(* style = ""HDL"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_intc
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    intr,
+    processor_clk,
+    processor_rst,
+    irq,
+    processor_ack,
+    interrupt_address,
+    irq_in,
+    interrupt_address_in,
+    processor_ack_out);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rstn"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* BUFFER_TYPE = ""none"" *) input [0:0]intr;
+  input processor_clk;
+  input processor_rst;
+  output irq;
+  input [1:0]processor_ack;
+  output [31:0]interrupt_address;
+  input irq_in;
+  input [31:0]interrupt_address_in;
+  output [1:0]processor_ack_out;
+
+  wire \\<const0> ;
+  wire AXI_LITE_IPIF_I_n_12;
+  wire AXI_LITE_IPIF_I_n_13;
+  wire AXI_LITE_IPIF_I_n_14;
+  wire AXI_LITE_IPIF_I_n_15;
+  wire AXI_LITE_IPIF_I_n_16;
+  wire AXI_LITE_IPIF_I_n_17;
+  wire INTC_CORE_I_n_1;
+  wire INTC_CORE_I_n_2;
+  wire INTC_CORE_I_n_6;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ;
+  wire Or128_vec2stdlogic19_out;
+  wire cie;
+  wire ier;
+  wire [0:0]intr;
+  wire ip2bus_rdack;
+  wire ip2bus_rdack_int_d1;
+  wire ip2bus_rdack_prev2;
+  wire ip2bus_wrack;
+  wire ip2bus_wrack_int_d1;
+  wire ip2bus_wrack_prev2;
+  wire [0:0]ipr;
+  wire irq;
+  wire isr;
+  wire ivr;
+  wire p_0_in;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rstn"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:1]\\^s_axi_bresp ;
+  wire s_axi_bvalid;
+  wire [30:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire [1:1]\\^s_axi_rresp ;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire sie;
+
+  assign interrupt_address[31] = \\<const0> ;
+  assign interrupt_address[30] = \\<const0> ;
+  assign interrupt_address[29] = \\<const0> ;
+  assign interrupt_address[28] = \\<const0> ;
+  assign interrupt_address[27] = \\<const0> ;
+  assign interrupt_address[26] = \\<const0> ;
+  assign interrupt_address[25] = \\<const0> ;
+  assign interrupt_address[24] = \\<const0> ;
+  assign interrupt_address[23] = \\<const0> ;
+  assign interrupt_address[22] = \\<const0> ;
+  assign interrupt_address[21] = \\<const0> ;
+  assign interrupt_address[20] = \\<const0> ;
+  assign interrupt_address[19] = \\<const0> ;
+  assign interrupt_address[18] = \\<const0> ;
+  assign interrupt_address[17] = \\<const0> ;
+  assign interrupt_address[16] = \\<const0> ;
+  assign interrupt_address[15] = \\<const0> ;
+  assign interrupt_address[14] = \\<const0> ;
+  assign interrupt_address[13] = \\<const0> ;
+  assign interrupt_address[12] = \\<const0> ;
+  assign interrupt_address[11] = \\<const0> ;
+  assign interrupt_address[10] = \\<const0> ;
+  assign interrupt_address[9] = \\<const0> ;
+  assign interrupt_address[8] = \\<const0> ;
+  assign interrupt_address[7] = \\<const0> ;
+  assign interrupt_address[6] = \\<const0> ;
+  assign interrupt_address[5] = \\<const0> ;
+  assign interrupt_address[4] = \\<const0> ;
+  assign interrupt_address[3] = \\<const0> ;
+  assign interrupt_address[2] = \\<const0> ;
+  assign interrupt_address[1] = \\<const0> ;
+  assign interrupt_address[0] = \\<const0> ;
+  assign processor_ack_out[1] = \\<const0> ;
+  assign processor_ack_out[0] = \\<const0> ;
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\^s_axi_bresp [1];
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[30] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[29] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[28] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[27] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[26] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[25] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[24] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[23] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[22] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[21] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[20] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[19] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[18] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[17] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[16] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[15] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[14] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[13] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[12] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[11] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[10] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[9] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[8] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[7] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[6] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[5] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[4] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[3] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[2] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[1:0] = \\^s_axi_rdata [1:0];
+  assign s_axi_rresp[1] = \\^s_axi_rresp [1];
+  assign s_axi_rresp[0] = \\<const0> ;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
+       (.Bus_RNW_reg(\\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+        .\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (AXI_LITE_IPIF_I_n_15),
+        .Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (AXI_LITE_IPIF_I_n_16),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (INTC_CORE_I_n_2),
+        .\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (AXI_LITE_IPIF_I_n_14),
+        .cie(cie),
+        .ier(ier),
+        .ip2bus_rdack(ip2bus_rdack),
+        .ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
+        .ip2bus_rdack_prev2(ip2bus_rdack_prev2),
+        .ip2bus_wrack(ip2bus_wrack),
+        .ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
+        .ip2bus_wrack_int_d1_reg(AXI_LITE_IPIF_I_n_17),
+        .ip2bus_wrack_prev2(ip2bus_wrack_prev2),
+        .ipr(ipr),
+        .isr(isr),
+        .ivr(ivr),
+        .\\mer_int_reg[0] (AXI_LITE_IPIF_I_n_12),
+        .\\mer_int_reg[0]_0 (INTC_CORE_I_n_6),
+        .\\mer_int_reg[1] (AXI_LITE_IPIF_I_n_13),
+        .p_0_in(p_0_in),
+        .p_15_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ),
+        .p_17_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr[8:2]),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_aresetn_0(INTC_CORE_I_n_1),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr[8:2]),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(\\^s_axi_bresp ),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata({\\^s_axi_rdata [30],\\^s_axi_rdata [1:0]}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(\\^s_axi_rresp ),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata[1:0]),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid),
+        .sie(sie));
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_intc_core INTC_CORE_I
+       (.Bus_RNW_reg(\\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+        .Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_16),
+        .Bus_RNW_reg_reg_0(AXI_LITE_IPIF_I_n_13),
+        .Bus_RNW_reg_reg_1(AXI_LITE_IPIF_I_n_14),
+        .\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 (AXI_LITE_IPIF_I_n_15),
+        .\\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] (AXI_LITE_IPIF_I_n_12),
+        .\\IPR_GEN.ipr_reg[0]_0 (INTC_CORE_I_n_1),
+        .\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 (INTC_CORE_I_n_6),
+        .ack_or_reg_0(INTC_CORE_I_n_2),
+        .cie(cie),
+        .ier(ier),
+        .intr(intr),
+        .ipr(ipr),
+        .irq(irq),
+        .isr(isr),
+        .ivr(ivr),
+        .p_0_in(p_0_in),
+        .p_15_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ),
+        .p_17_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_wdata(s_axi_wdata[0]),
+        .sie(sie));
+  FDRE ip2bus_rdack_int_d1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Or128_vec2stdlogic19_out),
+        .Q(ip2bus_rdack_int_d1),
+        .R(INTC_CORE_I_n_1));
+  FDRE ip2bus_rdack_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_prev2),
+        .Q(ip2bus_rdack),
+        .R(INTC_CORE_I_n_1));
+  FDRE ip2bus_wrack_int_d1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(AXI_LITE_IPIF_I_n_17),
+        .Q(ip2bus_wrack_int_d1),
+        .R(INTC_CORE_I_n_1));
+  FDRE ip2bus_wrack_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_wrack_prev2),
+        .Q(ip2bus_wrack),
+        .R(INTC_CORE_I_n_1));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
+   (p_15_in,
+    p_17_in,
+    s_axi_rresp,
+    Bus_RNW_reg,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_bresp,
+    s_axi_wready,
+    s_axi_arready,
+    ip2bus_wrack_prev2,
+    ip2bus_rdack_prev2,
+    Or128_vec2stdlogic19_out,
+    \\mer_int_reg[0] ,
+    \\mer_int_reg[1] ,
+    \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
+    \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
+    ip2bus_wrack_int_d1_reg,
+    s_axi_rdata,
+    s_axi_aresetn_0,
+    s_axi_aclk,
+    s_axi_arvalid,
+    ip2bus_wrack,
+    s_axi_aresetn,
+    ip2bus_rdack,
+    s_axi_rready,
+    s_axi_bready,
+    s_axi_wvalid,
+    s_axi_awvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    ipr,
+    ier,
+    ivr,
+    p_0_in,
+    \\mer_int_reg[0]_0 ,
+    isr,
+    ip2bus_wrack_int_d1,
+    ip2bus_rdack_int_d1,
+    s_axi_wstrb,
+    s_axi_wdata,
+    sie,
+    cie,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 );
+  output p_15_in;
+  output p_17_in;
+  output [0:0]s_axi_rresp;
+  output Bus_RNW_reg;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output [0:0]s_axi_bresp;
+  output s_axi_wready;
+  output s_axi_arready;
+  output ip2bus_wrack_prev2;
+  output ip2bus_rdack_prev2;
+  output Or128_vec2stdlogic19_out;
+  output \\mer_int_reg[0] ;
+  output \\mer_int_reg[1] ;
+  output \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  output \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  output \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  output ip2bus_wrack_int_d1_reg;
+  output [2:0]s_axi_rdata;
+  input s_axi_aresetn_0;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input ip2bus_wrack;
+  input s_axi_aresetn;
+  input ip2bus_rdack;
+  input s_axi_rready;
+  input s_axi_bready;
+  input s_axi_wvalid;
+  input s_axi_awvalid;
+  input [6:0]s_axi_araddr;
+  input [6:0]s_axi_awaddr;
+  input [0:0]ipr;
+  input ier;
+  input ivr;
+  input p_0_in;
+  input \\mer_int_reg[0]_0 ;
+  input isr;
+  input ip2bus_wrack_int_d1;
+  input ip2bus_rdack_int_d1;
+  input [3:0]s_axi_wstrb;
+  input [1:0]s_axi_wdata;
+  input sie;
+  input cie;
+  input \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+
+  wire Bus_RNW_reg;
+  wire \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  wire Or128_vec2stdlogic19_out;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+  wire \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  wire cie;
+  wire ier;
+  wire ip2bus_rdack;
+  wire ip2bus_rdack_int_d1;
+  wire ip2bus_rdack_prev2;
+  wire ip2bus_wrack;
+  wire ip2bus_wrack_int_d1;
+  wire ip2bus_wrack_int_d1_reg;
+  wire ip2bus_wrack_prev2;
+  wire [0:0]ipr;
+  wire isr;
+  wire ivr;
+  wire \\mer_int_reg[0] ;
+  wire \\mer_int_reg[0]_0 ;
+  wire \\mer_int_reg[1] ;
+  wire p_0_in;
+  wire p_15_in;
+  wire p_17_in;
+  wire s_axi_aclk;
+  wire [6:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_aresetn_0;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [6:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [0:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [2:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [0:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [1:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire sie;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
+       (.\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
+        .Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
+        .\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
+        .cie(cie),
+        .ier(ier),
+        .ip2bus_rdack(ip2bus_rdack),
+        .ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
+        .ip2bus_rdack_prev2(ip2bus_rdack_prev2),
+        .ip2bus_wrack(ip2bus_wrack),
+        .ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
+        .ip2bus_wrack_int_d1_reg(ip2bus_wrack_int_d1_reg),
+        .ip2bus_wrack_prev2(ip2bus_wrack_prev2),
+        .ipr(ipr),
+        .isr(isr),
+        .ivr(ivr),
+        .\\mer_int_reg[0] (Bus_RNW_reg),
+        .\\mer_int_reg[0]_0 (\\mer_int_reg[0] ),
+        .\\mer_int_reg[0]_1 (\\mer_int_reg[0]_0 ),
+        .\\mer_int_reg[1] (\\mer_int_reg[1] ),
+        .p_0_in(p_0_in),
+        .p_15_in(p_15_in),
+        .p_17_in(p_17_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_aresetn_0(s_axi_aresetn_0),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid),
+        .sie(sie));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_intc_0_0,axi_intc,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_intc,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    intr,
+    irq);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 s_axi_aclk CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 s_resetn RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi AWVALID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT"" *) input [0:0]intr;
+  (* x_interface_info = ""xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT"" *) output irq;
+
+  wire [0:0]intr;
+  wire irq;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire [31:0]NLW_U0_interrupt_address_UNCONNECTED;
+  wire [1:0]NLW_U0_processor_ack_out_UNCONNECTED;
+
+  (* C_ASYNC_INTR = ""-2"" *) 
+  (* C_CASCADE_MASTER = ""0"" *) 
+  (* C_DISABLE_SYNCHRONIZERS = ""0"" *) 
+  (* C_ENABLE_ASYNC = ""0"" *) 
+  (* C_EN_CASCADE_MODE = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_HAS_CIE = ""1"" *) 
+  (* C_HAS_FAST = ""0"" *) 
+  (* C_HAS_ILR = ""0"" *) 
+  (* C_HAS_IPR = ""1"" *) 
+  (* C_HAS_IVR = ""1"" *) 
+  (* C_HAS_SIE = ""1"" *) 
+  (* C_INSTANCE = ""design_1_axi_intc_0_0"" *) 
+  (* C_IRQ_ACTIVE = ""1\'b1"" *) 
+  (* C_IRQ_IS_LEVEL = ""0"" *) 
+  (* C_IVAR_RESET_VALUE = ""16"" *) 
+  (* C_KIND_OF_EDGE = ""-1"" *) 
+  (* C_KIND_OF_INTR = ""-2"" *) 
+  (* C_KIND_OF_LVL = ""-1"" *) 
+  (* C_MB_CLK_NOT_CONNECTED = ""1"" *) 
+  (* C_NUM_INTR_INPUTS = ""1"" *) 
+  (* C_NUM_SW_INTR = ""0"" *) 
+  (* C_NUM_SYNC_FF = ""2"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* hdl = ""VHDL"" *) 
+  (* imp_netlist = ""TRUE"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  (* iptype = ""PERIPHERAL"" *) 
+  (* run_ngcbuild = ""TRUE"" *) 
+  (* style = ""HDL"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_intc U0
+       (.interrupt_address(NLW_U0_interrupt_address_UNCONNECTED[31:0]),
+        .interrupt_address_in({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .intr(intr),
+        .irq(irq),
+        .irq_in(1\'b0),
+        .processor_ack({1\'b0,1\'b0}),
+        .processor_ack_out(NLW_U0_processor_ack_out_UNCONNECTED[1:0]),
+        .processor_clk(1\'b0),
+        .processor_rst(1\'b0),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_intc_core
+   (ier,
+    \\IPR_GEN.ipr_reg[0]_0 ,
+    ack_or_reg_0,
+    irq,
+    ipr,
+    ivr,
+    \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ,
+    p_0_in,
+    isr,
+    sie,
+    cie,
+    s_axi_aclk,
+    Bus_RNW_reg_reg,
+    \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ,
+    Bus_RNW_reg_reg_0,
+    Bus_RNW_reg_reg_1,
+    \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ,
+    s_axi_aresetn,
+    s_axi_wdata,
+    p_15_in,
+    Bus_RNW_reg,
+    p_17_in,
+    intr);
+  output ier;
+  output \\IPR_GEN.ipr_reg[0]_0 ;
+  output ack_or_reg_0;
+  output irq;
+  output [0:0]ipr;
+  output ivr;
+  output \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ;
+  output p_0_in;
+  output isr;
+  output sie;
+  output cie;
+  input s_axi_aclk;
+  input Bus_RNW_reg_reg;
+  input \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
+  input Bus_RNW_reg_reg_0;
+  input Bus_RNW_reg_reg_1;
+  input \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
+  input s_axi_aresetn;
+  input [0:0]s_axi_wdata;
+  input p_15_in;
+  input Bus_RNW_reg;
+  input p_17_in;
+  input [0:0]intr;
+
+  wire Bus_RNW_reg;
+  wire Bus_RNW_reg_reg;
+  wire Bus_RNW_reg_reg_0;
+  wire Bus_RNW_reg_reg_1;
+  wire \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
+  wire \\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ;
+  wire \\IPR_GEN.ipr[0]_i_1_n_0 ;
+  wire \\IPR_GEN.ipr_reg[0]_0 ;
+  wire \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_2_n_0 ;
+  wire \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ;
+  wire \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ;
+  wire \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ;
+  wire \\REG_GEN[0].ier[0]_i_2_n_0 ;
+  wire \\REG_GEN[0].isr[0]_i_1_n_0 ;
+  wire \\REG_GEN[0].isr[0]_i_2_n_0 ;
+  wire ack_or;
+  wire ack_or_reg_0;
+  wire cie;
+  wire [1:0]current_state;
+  wire hw_intr;
+  wire ier;
+  wire [0:0]intr;
+  wire [0:0]ipr;
+  wire irq;
+  wire isr;
+  wire ivr;
+  wire p_0_in;
+  wire p_15_in;
+  wire p_17_in;
+  wire p_1_in;
+  wire p_5_out;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire [0:0]s_axi_wdata;
+  wire sie;
+
+  FDRE \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ),
+        .Q(cie),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT4 #(
+    .INIT(16\'h00E0)) 
+    \\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1 
+       (.I0(hw_intr),
+        .I1(intr),
+        .I2(s_axi_aresetn),
+        .I3(ack_or_reg_0),
+        .O(\\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ));
+  FDRE \\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ),
+        .Q(hw_intr),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\IPR_GEN.ipr[0]_i_1 
+       (.I0(ier),
+        .I1(isr),
+        .O(\\IPR_GEN.ipr[0]_i_1_n_0 ));
+  FDRE \\IPR_GEN.ipr_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\IPR_GEN.ipr[0]_i_1_n_0 ),
+        .Q(ipr),
+        .R(\\IPR_GEN.ipr_reg[0]_0 ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_1 
+       (.I0(s_axi_aresetn),
+        .O(\\IPR_GEN.ipr_reg[0]_0 ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_2 
+       (.I0(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ),
+        .I1(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ),
+        .O(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_2_n_0 ));
+  FDRE \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_2_n_0 ),
+        .Q(irq),
+        .R(\\IPR_GEN.ipr_reg[0]_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT4 #(
+    .INIT(16\'h1000)) 
+    \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state[0]_i_1 
+       (.I0(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ),
+        .I1(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ),
+        .I2(ipr),
+        .I3(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ),
+        .O(current_state[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hBA)) 
+    \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state[1]_i_1 
+       (.I0(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ),
+        .I1(ack_or),
+        .I2(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ),
+        .O(current_state[1]));
+  FDRE \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(current_state[0]),
+        .Q(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ),
+        .R(\\IPR_GEN.ipr_reg[0]_0 ));
+  FDRE \\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(current_state[1]),
+        .Q(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ),
+        .R(\\IPR_GEN.ipr_reg[0]_0 ));
+  LUT2 #(
+    .INIT(4\'h7)) 
+    \\IVR_GEN.ivr[0]_i_1 
+       (.I0(isr),
+        .I1(ier),
+        .O(p_1_in));
+  FDSE \\IVR_GEN.ivr_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(ivr),
+        .S(\\IPR_GEN.ipr_reg[0]_0 ));
+  FDRE \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_reg),
+        .Q(ack_or_reg_0),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAA8A0080)) 
+    \\REG_GEN[0].ier[0]_i_1 
+       (.I0(\\REG_GEN[0].ier[0]_i_2_n_0 ),
+        .I1(s_axi_wdata),
+        .I2(p_15_in),
+        .I3(Bus_RNW_reg),
+        .I4(ier),
+        .I5(sie),
+        .O(p_5_out));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\REG_GEN[0].ier[0]_i_2 
+       (.I0(s_axi_aresetn),
+        .I1(cie),
+        .O(\\REG_GEN[0].ier[0]_i_2_n_0 ));
+  FDRE \\REG_GEN[0].ier_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_5_out),
+        .Q(ier),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\REG_GEN[0].isr[0]_i_1 
+       (.I0(\\REG_GEN[0].isr[0]_i_2_n_0 ),
+        .I1(s_axi_aresetn),
+        .I2(ack_or_reg_0),
+        .O(\\REG_GEN[0].isr[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAFACAFAFA0ACA0A0)) 
+    \\REG_GEN[0].isr[0]_i_2 
+       (.I0(hw_intr),
+        .I1(s_axi_wdata),
+        .I2(p_0_in),
+        .I3(Bus_RNW_reg),
+        .I4(p_17_in),
+        .I5(isr),
+        .O(\\REG_GEN[0].isr[0]_i_2_n_0 ));
+  FDRE \\REG_GEN[0].isr_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\REG_GEN[0].isr[0]_i_1_n_0 ),
+        .Q(isr),
+        .R(1\'b0));
+  FDRE \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_reg_1),
+        .Q(sie),
+        .R(1\'b0));
+  FDRE ack_or_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ack_or_reg_0),
+        .Q(ack_or),
+        .R(\\IPR_GEN.ipr_reg[0]_0 ));
+  FDRE \\mer_int_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ),
+        .Q(\\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ),
+        .R(\\IPR_GEN.ipr_reg[0]_0 ));
+  FDRE \\mer_int_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_reg_0),
+        .Q(p_0_in),
+        .R(\\IPR_GEN.ipr_reg[0]_0 ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
+   (p_15_in,
+    p_17_in,
+    s_axi_rresp,
+    \\mer_int_reg[0] ,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_bresp,
+    s_axi_wready,
+    s_axi_arready,
+    ip2bus_wrack_prev2,
+    ip2bus_rdack_prev2,
+    Or128_vec2stdlogic19_out,
+    \\mer_int_reg[0]_0 ,
+    \\mer_int_reg[1] ,
+    \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
+    \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
+    ip2bus_wrack_int_d1_reg,
+    s_axi_rdata,
+    s_axi_aresetn_0,
+    s_axi_aclk,
+    s_axi_arvalid,
+    ip2bus_wrack,
+    s_axi_aresetn,
+    ip2bus_rdack,
+    s_axi_rready,
+    s_axi_bready,
+    s_axi_wvalid,
+    s_axi_awvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    ipr,
+    ier,
+    ivr,
+    p_0_in,
+    \\mer_int_reg[0]_1 ,
+    isr,
+    ip2bus_wrack_int_d1,
+    ip2bus_rdack_int_d1,
+    s_axi_wstrb,
+    s_axi_wdata,
+    sie,
+    cie,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 );
+  output p_15_in;
+  output p_17_in;
+  output [0:0]s_axi_rresp;
+  output \\mer_int_reg[0] ;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output [0:0]s_axi_bresp;
+  output s_axi_wready;
+  output s_axi_arready;
+  output ip2bus_wrack_prev2;
+  output ip2bus_rdack_prev2;
+  output Or128_vec2stdlogic19_out;
+  output \\mer_int_reg[0]_0 ;
+  output \\mer_int_reg[1] ;
+  output \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  output \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  output \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  output ip2bus_wrack_int_d1_reg;
+  output [2:0]s_axi_rdata;
+  input s_axi_aresetn_0;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input ip2bus_wrack;
+  input s_axi_aresetn;
+  input ip2bus_rdack;
+  input s_axi_rready;
+  input s_axi_bready;
+  input s_axi_wvalid;
+  input s_axi_awvalid;
+  input [6:0]s_axi_araddr;
+  input [6:0]s_axi_awaddr;
+  input [0:0]ipr;
+  input ier;
+  input ivr;
+  input p_0_in;
+  input \\mer_int_reg[0]_1 ;
+  input isr;
+  input ip2bus_wrack_int_d1;
+  input ip2bus_rdack_int_d1;
+  input [3:0]s_axi_wstrb;
+  input [1:0]s_axi_wdata;
+  input sie;
+  input cie;
+  input \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+
+  wire \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  wire \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire [31:0]IP2Bus_Data;
+  wire Or128_vec2stdlogic19_out;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+  wire \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  wire [8:2]bus2ip_addr;
+  wire \\bus2ip_addr_i[2]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[3]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[4]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[5]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[6]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[7]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_2_n_0 ;
+  wire bus2ip_rnw_i06_out;
+  wire bus2ip_rnw_i_reg_n_0;
+  wire cie;
+  wire ier;
+  wire ip2bus_error;
+  wire ip2bus_rdack;
+  wire ip2bus_rdack_int_d1;
+  wire ip2bus_rdack_prev2;
+  wire ip2bus_wrack;
+  wire ip2bus_wrack_int_d1;
+  wire ip2bus_wrack_int_d1_reg;
+  wire ip2bus_wrack_prev2;
+  wire [0:0]ipr;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_read_i_2_n_0;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire isr;
+  wire ivr;
+  wire \\mer_int_reg[0] ;
+  wire \\mer_int_reg[0]_0 ;
+  wire \\mer_int_reg[0]_1 ;
+  wire \\mer_int_reg[1] ;
+  wire p_0_in;
+  wire p_15_in;
+  wire p_17_in;
+  wire [3:0]plusOp;
+  wire rst;
+  wire s_axi_aclk;
+  wire [6:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_aresetn_0;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [6:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [0:0]s_axi_bresp;
+  wire \\s_axi_bresp_i[1]_i_1_n_0 ;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [2:0]s_axi_rdata;
+  wire s_axi_rdata_i;
+  wire \\s_axi_rdata_i[0]_i_3_n_0 ;
+  wire \\s_axi_rdata_i[0]_i_4_n_0 ;
+  wire \\s_axi_rdata_i[1]_i_2_n_0 ;
+  wire \\s_axi_rdata_i[31]_i_5_n_0 ;
+  wire s_axi_rready;
+  wire [0:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire [1:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire sie;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire \\state[0]_i_1_n_0 ;
+  wire \\state[0]_i_2_n_0 ;
+  wire \\state[1]_i_1_n_0 ;
+  wire \\state[1]_i_2_n_0 ;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[1]),
+        .I1(state[0]),
+        .O(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT4 #(
+    .INIT(16\'h6AAA)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
+       (.\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
+        .D({IP2Bus_Data[31],IP2Bus_Data[1:0]}),
+        .\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .\\IPR_GEN.ipr_reg[0] (\\s_axi_rdata_i[0]_i_3_n_0 ),
+        .\\IVR_GEN.ivr_reg[0] (\\s_axi_rdata_i[1]_i_2_n_0 ),
+        .Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
+        .Q(start2),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
+        .\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
+        .\\bus2ip_addr_i_reg[2] (\\s_axi_rdata_i[31]_i_5_n_0 ),
+        .\\bus2ip_addr_i_reg[3] (\\s_axi_rdata_i[0]_i_4_n_0 ),
+        .\\bus2ip_addr_i_reg[8] (bus2ip_addr),
+        .bus2ip_rnw_i_reg(bus2ip_rnw_i_reg_n_0),
+        .cie(cie),
+        .ip2bus_rdack(ip2bus_rdack),
+        .ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
+        .ip2bus_rdack_prev2(ip2bus_rdack_prev2),
+        .ip2bus_wrack(ip2bus_wrack),
+        .ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
+        .ip2bus_wrack_int_d1_reg(ip2bus_wrack_int_d1_reg),
+        .ip2bus_wrack_prev2(ip2bus_wrack_prev2),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .\\mer_int_reg[0] (\\mer_int_reg[0] ),
+        .\\mer_int_reg[0]_0 (\\mer_int_reg[0]_0 ),
+        .\\mer_int_reg[0]_1 (\\mer_int_reg[0]_1 ),
+        .\\mer_int_reg[1] (\\mer_int_reg[1] ),
+        .p_0_in(p_0_in),
+        .p_15_in(p_15_in),
+        .p_17_in(p_17_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_wdata(s_axi_wdata),
+        .sie(sie));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[0]),
+        .O(\\bus2ip_addr_i[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[1]),
+        .O(\\bus2ip_addr_i[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[4]_i_1 
+       (.I0(s_axi_araddr[2]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[2]),
+        .O(\\bus2ip_addr_i[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[5]_i_1 
+       (.I0(s_axi_araddr[3]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[3]),
+        .O(\\bus2ip_addr_i[5]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[6]_i_1 
+       (.I0(s_axi_araddr[4]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[4]),
+        .O(\\bus2ip_addr_i[6]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[7]_i_1 
+       (.I0(s_axi_araddr[5]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[5]),
+        .O(\\bus2ip_addr_i[7]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h000000EA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_awvalid),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(\\bus2ip_addr_i[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[8]_i_2 
+       (.I0(s_axi_araddr[6]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[6]),
+        .O(\\bus2ip_addr_i[8]_i_2_n_0 ));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[2]_i_1_n_0 ),
+        .Q(bus2ip_addr[2]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[3]_i_1_n_0 ),
+        .Q(bus2ip_addr[3]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[4]_i_1_n_0 ),
+        .Q(bus2ip_addr[4]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[5]_i_1_n_0 ),
+        .Q(bus2ip_addr[5]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[6]_i_1_n_0 ),
+        .Q(bus2ip_addr[6]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[7]_i_1_n_0 ),
+        .Q(bus2ip_addr[7]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[8]_i_2_n_0 ),
+        .Q(bus2ip_addr[8]),
+        .R(rst));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    bus2ip_rnw_i_i_1
+       (.I0(state[1]),
+        .I1(s_axi_arvalid),
+        .I2(state[0]),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(bus2ip_rnw_i06_out),
+        .Q(bus2ip_rnw_i_reg_n_0),
+        .R(rst));
+  LUT4 #(
+    .INIT(16\'h2F20)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state[1]),
+        .I2(is_read_i_2_n_0),
+        .I3(is_read),
+        .O(is_read_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hAA80808055555555)) 
+    is_read_i_2
+       (.I0(state[0]),
+        .I1(s_axi_bready),
+        .I2(s_axi_bvalid),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .I5(state[1]),
+        .O(is_read_i_2_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(rst));
+  LUT6 #(
+    .INIT(64\'h0040FFFF00400000)) 
+    is_write_i_1
+       (.I0(state[1]),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_awvalid),
+        .I3(s_axi_arvalid),
+        .I4(is_read_i_2_n_0),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(rst));
+  FDRE rst_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_aresetn_0),
+        .Q(rst),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAEAAAAAAAA)) 
+    s_axi_arready_INST_0
+       (.I0(ip2bus_rdack),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I5(is_read),
+        .O(s_axi_arready));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\s_axi_bresp_i[1]_i_1 
+       (.I0(ip2bus_error),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bresp),
+        .O(\\s_axi_bresp_i[1]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_bresp_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\s_axi_bresp_i[1]_i_1_n_0 ),
+        .Q(s_axi_bresp),
+        .R(rst));
+  LUT5 #(
+    .INIT(32\'h5D550C00)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_bready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_wready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(rst));
+  LUT6 #(
+    .INIT(64\'h000000000300A0A0)) 
+    \\s_axi_rdata_i[0]_i_3 
+       (.I0(ipr),
+        .I1(bus2ip_addr[5]),
+        .I2(bus2ip_addr[2]),
+        .I3(ier),
+        .I4(bus2ip_addr[3]),
+        .I5(bus2ip_addr[4]),
+        .O(\\s_axi_rdata_i[0]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0000000081018000)) 
+    \\s_axi_rdata_i[0]_i_4 
+       (.I0(bus2ip_addr[3]),
+        .I1(bus2ip_addr[4]),
+        .I2(bus2ip_addr[2]),
+        .I3(\\mer_int_reg[0]_1 ),
+        .I4(isr),
+        .I5(bus2ip_addr[5]),
+        .O(\\s_axi_rdata_i[0]_i_4_n_0 ));
+  LUT6 #(
+    .INIT(64\'hCDFDFFFFFFFF3F3F)) 
+    \\s_axi_rdata_i[1]_i_2 
+       (.I0(ivr),
+        .I1(bus2ip_addr[5]),
+        .I2(bus2ip_addr[2]),
+        .I3(p_0_in),
+        .I4(bus2ip_addr[3]),
+        .I5(bus2ip_addr[4]),
+        .O(\\s_axi_rdata_i[1]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[31]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(s_axi_rdata_i));
+  LUT5 #(
+    .INIT(32\'hEFFFFF77)) 
+    \\s_axi_rdata_i[31]_i_5 
+       (.I0(bus2ip_addr[2]),
+        .I1(bus2ip_addr[5]),
+        .I2(ivr),
+        .I3(bus2ip_addr[3]),
+        .I4(bus2ip_addr[4]),
+        .O(\\s_axi_rdata_i[31]_i_5_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(IP2Bus_Data[0]),
+        .Q(s_axi_rdata[0]),
+        .R(rst));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(IP2Bus_Data[1]),
+        .Q(s_axi_rdata[1]),
+        .R(rst));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(IP2Bus_Data[31]),
+        .Q(s_axi_rdata[2]),
+        .R(rst));
+  LUT5 #(
+    .INIT(32\'h070F0F0F)) 
+    \\s_axi_rresp_i[1]_i_1 
+       (.I0(s_axi_wstrb[1]),
+        .I1(s_axi_wstrb[2]),
+        .I2(bus2ip_rnw_i_reg_n_0),
+        .I3(s_axi_wstrb[0]),
+        .I4(s_axi_wstrb[3]),
+        .O(ip2bus_error));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rresp_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(ip2bus_error),
+        .Q(s_axi_rresp),
+        .R(rst));
+  LUT5 #(
+    .INIT(32\'h5D550C00)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_rready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_arready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(rst));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAEAAAAAAAA)) 
+    s_axi_wready_INST_0
+       (.I0(ip2bus_wrack),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I5(is_write_reg_n_0),
+        .O(s_axi_wready));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT5 #(
+    .INIT(32\'h00000F08)) 
+    start2_i_1
+       (.I0(s_axi_wvalid),
+        .I1(s_axi_awvalid),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(state[1]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(rst));
+  LUT5 #(
+    .INIT(32\'hF4F4FFF0)) 
+    \\state[0]_i_1 
+       (.I0(state[0]),
+        .I1(s_axi_wready),
+        .I2(\\state[0]_i_2_n_0 ),
+        .I3(s_axi_arvalid),
+        .I4(state[1]),
+        .O(\\state[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h557F7F7F00000000)) 
+    \\state[0]_i_2 
+       (.I0(state[1]),
+        .I1(s_axi_rvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_bvalid),
+        .I4(s_axi_bready),
+        .I5(state[0]),
+        .O(\\state[0]_i_2_n_0 ));
+  LUT5 #(
+    .INIT(32\'h22CFEECF)) 
+    \\state[1]_i_1 
+       (.I0(s_axi_arready),
+        .I1(state[1]),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(state[0]),
+        .I4(\\state[1]_i_3_n_0 ),
+        .O(\\state[1]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT3 #(
+    .INIT(8\'hBF)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_wvalid),
+        .O(\\state[1]_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hF888'b"")) 
+    \\state[1]_i_3 
+       (.I0(s_axi_rvalid),
+        .I1(s_axi_rready),
+        .I2(s_axi_bvalid),
+        .I3(s_axi_bready),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\\state[0]_i_1_n_0 ),
+        .Q(state[0]),
+        .R(rst));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\\state[1]_i_1_n_0 ),
+        .Q(state[1]),
+        .R(rst));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1'b1;
+\tPRLD_int = 1'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1'b0;
+\tPRLD_int = 1'b0;
+    end
+
+    initial begin
+\tGTS_int = 1'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1'b0;
+    end
+
+endmodule
+`endif
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_reg_params.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Parameters for Register Address and Default values.
+ *
+ *****************************************************************************/
+
+// Register default value info for chip pele_ps
+// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012
+// 54 modules, 2532 registers.
+
+
+// ************************************************************
+//   Module afi0 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter afi0__AFI_RDCHAN_CTRL = 32'hF8008000;
+parameter val_afi0__AFI_RDCHAN_CTRL = 32'h00000000;
+parameter mask_afi0__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi0__AFI_RDCHAN_ISSUINGCAP = 32'hF8008004;
+parameter val_afi0__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi0__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi0__AFI_RDQOS = 32'hF8008008;
+parameter val_afi0__AFI_RDQOS = 32'h00000000;
+parameter mask_afi0__AFI_RDQOS = 32'hFFFFFFFF;
+
+parameter afi0__AFI_RDDATAFIFO_LEVEL = 32'hF800800C;
+parameter val_afi0__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi0__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi0__AFI_RDDEBUG = 32'hF8008010;
+parameter val_afi0__AFI_RDDEBUG = 32'h00000000;
+parameter mask_afi0__AFI_RDDEBUG = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRCHAN_CTRL = 32'hF8008014;
+parameter val_afi0__AFI_WRCHAN_CTRL = 32'h00000F00;
+parameter mask_afi0__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRCHAN_ISSUINGCAP = 32'hF8008018;
+parameter val_afi0__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi0__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRQOS = 32'hF800801C;
+parameter val_afi0__AFI_WRQOS = 32'h00000000;
+parameter mask_afi0__AFI_WRQOS = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRDATAFIFO_LEVEL = 32'hF8008020;
+parameter val_afi0__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi0__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRDEBUG = 32'hF8008024;
+parameter val_afi0__AFI_WRDEBUG = 32'h00000000;
+parameter mask_afi0__AFI_WRDEBUG = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module afi1 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter afi1__AFI_RDCHAN_CTRL = 32'hF8009000;
+parameter val_afi1__AFI_RDCHAN_CTRL = 32'h00000000;
+parameter mask_afi1__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi1__AFI_RDCHAN_ISSUINGCAP = 32'hF8009004;
+parameter val_afi1__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi1__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi1__AFI_RDQOS = 32'hF8009008;
+parameter val_afi1__AFI_RDQOS = 32'h00000000;
+parameter mask_afi1__AFI_RDQOS = 32'hFFFFFFFF;
+
+parameter afi1__AFI_RDDATAFIFO_LEVEL = 32'hF800900C;
+parameter val_afi1__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi1__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi1__AFI_RDDEBUG = 32'hF8009010;
+parameter val_afi1__AFI_RDDEBUG = 32'h00000000;
+parameter mask_afi1__AFI_RDDEBUG = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRCHAN_CTRL = 32'hF8009014;
+parameter val_afi1__AFI_WRCHAN_CTRL = 32'h00000F00;
+parameter mask_afi1__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRCHAN_ISSUINGCAP = 32'hF8009018;
+parameter val_afi1__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi1__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRQOS = 32'hF800901C;
+parameter val_afi1__AFI_WRQOS = 32'h00000000;
+parameter mask_afi1__AFI_WRQOS = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRDATAFIFO_LEVEL = 32'hF8009020;
+parameter val_afi1__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi1__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRDEBUG = 32'hF8009024;
+parameter val_afi1__AFI_WRDEBUG = 32'h00000000;
+parameter mask_afi1__AFI_WRDEBUG = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module afi2 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter afi2__AFI_RDCHAN_CTRL = 32'hF800A000;
+parameter val_afi2__AFI_RDCHAN_CTRL = 32'h00000000;
+parameter mask_afi2__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi2__AFI_RDCHAN_ISSUINGCAP = 32'hF800A004;
+parameter val_afi2__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi2__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi2__AFI_RDQOS = 32'hF800A008;
+parameter val_afi2__AFI_RDQOS = 32'h00000000;
+parameter mask_afi2__AFI_RDQOS = 32'hFFFFFFFF;
+
+parameter afi2__AFI_RDDATAFIFO_LEVEL = 32'hF800A00C;
+parameter val_afi2__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi2__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi2__AFI_RDDEBUG = 32'hF800A010;
+parameter val_afi2__AFI_RDDEBUG = 32'h00000000;
+parameter mask_afi2__AFI_RDDEBUG = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRCHAN_CTRL = 32'hF800A014;
+parameter val_afi2__AFI_WRCHAN_CTRL = 32'h00000F00;
+parameter mask_afi2__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRCHAN_ISSUINGCAP = 32'hF800A018;
+parameter val_afi2__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi2__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRQOS = 32'hF800A01C;
+parameter val_afi2__AFI_WRQOS = 32'h00000000;
+parameter mask_afi2__AFI_WRQOS = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRDATAFIFO_LEVEL = 32'hF800A020;
+parameter val_afi2__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi2__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRDEBUG = 32'hF800A024;
+parameter val_afi2__AFI_WRDEBUG = 32'h00000000;
+parameter mask_afi2__AFI_WRDEBUG = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module afi3 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter afi3__AFI_RDCHAN_CTRL = 32'hF800B000;
+parameter val_afi3__AFI_RDCHAN_CTRL = 32'h00000000;
+parameter mask_afi3__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi3__AFI_RDCHAN_ISSUINGCAP = 32'hF800B004;
+parameter val_afi3__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi3__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi3__AFI_RDQOS = 32'hF800B008;
+parameter val_afi3__AFI_RDQOS = 32'h00000000;
+parameter mask_afi3__AFI_RDQOS = 32'hFFFFFFFF;
+
+parameter afi3__AFI_RDDATAFIFO_LEVEL = 32'hF800B00C;
+parameter val_afi3__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi3__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi3__AFI_RDDEBUG = 32'hF800B010;
+parameter val_afi3__AFI_RDDEBUG = 32'h00000000;
+parameter mask_afi3__AFI_RDDEBUG = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRCHAN_CTRL = 32'hF800B014;
+parameter val_afi3__AFI_WRCHAN_CTRL = 32'h00000F00;
+parameter mask_afi3__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRCHAN_ISSUINGCAP = 32'hF800B018;
+parameter val_afi3__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi3__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRQOS = 32'hF800B01C;
+parameter val_afi3__AFI_WRQOS = 32'h00000000;
+parameter mask_afi3__AFI_WRQOS = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRDATAFIFO_LEVEL = 32'hF800B020;
+parameter val_afi3__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi3__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRDEBUG = 32'hF800B024;
+parameter val_afi3__AFI_WRDEBUG = 32'h00000000;
+parameter mask_afi3__AFI_WRDEBUG = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module can0 can
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter can0__SRR = 32'hE0008000;
+parameter val_can0__SRR = 32'h00000000;
+parameter mask_can0__SRR = 32'hFFFFFFFF;
+
+parameter can0__MSR = 32'hE0008004;
+parameter val_can0__MSR = 32'h00000000;
+parameter mask_can0__MSR = 32'hFFFFFFFF;
+
+parameter can0__BRPR = 32'hE0008008;
+parameter val_can0__BRPR = 32'h00000000;
+parameter mask_can0__BRPR = 32'hFFFFFFFF;
+
+parameter can0__BTR = 32'hE000800C;
+parameter val_can0__BTR = 32'h00000000;
+parameter mask_can0__BTR = 32'hFFFFFFFF;
+
+parameter can0__ECR = 32'hE0008010;
+parameter val_can0__ECR = 32'h00000000;
+parameter mask_can0__ECR = 32'hFFFFFFFF;
+
+parameter can0__ESR = 32'hE0008014;
+parameter val_can0__ESR = 32'h00000000;
+parameter mask_can0__ESR = 32'hFFFFFFFF;
+
+parameter can0__SR = 32'hE0008018;
+parameter val_can0__SR = 32'h00000001;
+parameter mask_can0__SR = 32'hFFFFFFFF;
+
+parameter can0__ISR = 32'hE000801C;
+parameter val_can0__ISR = 32'h00006000;
+parameter mask_can0__ISR = 32'hFFFFFFFF;
+
+parameter can0__IER = 32'hE0008020;
+parameter val_can0__IER = 32'h00000000;
+parameter mask_can0__IER = 32'hFFFFFFFF;
+
+parameter can0__ICR = 32'hE0008024;
+parameter val_can0__ICR = 32'h00000000;
+parameter mask_can0__ICR = 32'hFFFFFFFF;
+
+parameter can0__TCR = 32'hE0008028;
+parameter val_can0__TCR = 32'h00000000;
+parameter mask_can0__TCR = 32'hFFFFFFFF;
+
+parameter can0__WIR = 32'hE000802C;
+parameter val_can0__WIR = 32'h00003F3F;
+parameter mask_can0__WIR = 32'hFFFFFFFF;
+
+parameter can0__TXFIFO_ID = 32'hE0008030;
+parameter val_can0__TXFIFO_ID = 32'h00000000;
+parameter mask_can0__TXFIFO_ID = 32'hFFFFFFFF;
+
+parameter can0__TXFIFO_DLC = 32'hE0008034;
+parameter val_can0__TXFIFO_DLC = 32'h00000000;
+parameter mask_can0__TXFIFO_DLC = 32'hFFFFFFFF;
+
+parameter can0__TXFIFO_DATA1 = 32'hE0008038;
+parameter val_can0__TXFIFO_DATA1 = 32'h00000000;
+parameter mask_can0__TXFIFO_DATA1 = 32'hFFFFFFFF;
+
+parameter can0__TXFIFO_DATA2 = 32'hE000803C;
+parameter val_can0__TXFIFO_DATA2 = 32'h00000000;
+parameter mask_can0__TXFIFO_DATA2 = 32'hFFFFFFFF;
+
+parameter can0__TXHPB_ID = 32'hE0008040;
+parameter val_can0__TXHPB_ID = 32'h00000000;
+parameter mask_can0__TXHPB_ID = 32'hFFFFFFFF;
+
+parameter can0__TXHPB_DLC = 32'hE0008044;
+parameter val_can0__TXHPB_DLC = 32'h00000000;
+parameter mask_can0__TXHPB_DLC = 32'hFFFFFFFF;
+
+parameter can0__TXHPB_DATA1 = 32'hE0008048;
+parameter val_can0__TXHPB_DATA1 = 32'h00000000;
+parameter mask_can0__TXHPB_DATA1 = 32'hFFFFFFFF;
+
+parameter can0__TXHPB_DATA2 = 32'hE000804C;
+parameter val_can0__TXHPB_DATA2 = 32'h00000000;
+parameter mask_can0__TXHPB_DATA2 = 32'hFFFFFFFF;
+
+parameter can0__RXFIFO_ID = 32'hE0008050;
+parameter val_can0__RXFIFO_ID = 32'h00000000;
+parameter mask_can0__RXFIFO_ID = 32'h00000000;
+
+parameter can0__RXFIFO_DLC = 32'hE0008054;
+parameter val_can0__RXFIFO_DLC = 32'h00000000;
+parameter mask_can0__RXFIFO_DLC = 32'h00000000;
+
+parameter can0__RXFIFO_DATA1 = 32'hE0008058;
+parameter val_can0__RXFIFO_DATA1 = 32'h00000000;
+parameter mask_can0__RXFIFO_DATA1 = 32'h00000000;
+
+parameter can0__RXFIFO_DATA2 = 32'hE000805C;
+parameter val_can0__RXFIFO_DATA2 = 32'h00000000;
+parameter mask_can0__RXFIFO_DATA2 = 32'h00000000;
+
+parameter can0__AFR = 32'hE0008060;
+parameter val_can0__AFR = 32'h00000000;
+parameter mask_can0__AFR = 32'hFFFFFFFF;
+
+parameter can0__AFMR1 = 32'hE0008064;
+parameter val_can0__AFMR1 = 32'h00000000;
+parameter mask_can0__AFMR1 = 32'h00000000;
+
+parameter can0__AFIR1 = 32'hE0008068;
+parameter val_can0__AFIR1 = 32'h00000000;
+parameter mask_can0__AFIR1 = 32'h00000000;
+
+parameter can0__AFMR2 = 32'hE000806C;
+parameter val_can0__AFMR2 = 32'h00000000;
+parameter mask_can0__AFMR2 = 32'h00000000;
+
+parameter can0__AFIR2 = 32'hE0008070;
+parameter val_can0__AFIR2 = 32'h00000000;
+parameter mask_can0__AFIR2 = 32'h00000000;
+
+parameter can0__AFMR3 = 32'hE0008074;
+parameter val_can0__AFMR3 = 32'h00000000;
+parameter mask_can0__AFMR3 = 32'h00000000;
+
+parameter can0__AFIR3 = 32'hE0008078;
+parameter val_can0__AFIR3 = 32'h00000000;
+parameter mask_can0__AFIR3 = 32'h00000000;
+
+parameter can0__AFMR4 = 32'hE000807C;
+parameter val_can0__AFMR4 = 32'h00000000;
+parameter mask_can0__AFMR4 = 32'h00000000;
+
+parameter can0__AFIR4 = 32'hE0008080;
+parameter val_can0__AFIR4 = 32'h00000000;
+parameter mask_can0__AFIR4 = 32'h00000000;
+
+
+// ************************************************************
+//   Module can1 can
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter can1__SRR = 32'hE0009000;
+parameter val_can1__SRR = 32'h00000000;
+parameter mask_can1__SRR = 32'hFFFFFFFF;
+
+parameter can1__MSR = 32'hE0009004;
+parameter val_can1__MSR = 32'h00000000;
+parameter mask_can1__MSR = 32'hFFFFFFFF;
+
+parameter can1__BRPR = 32'hE0009008;
+parameter val_can1__BRPR = 32'h00000000;
+parameter mask_can1__BRPR = 32'hFFFFFFFF;
+
+parameter can1__BTR = 32'hE000900C;
+parameter val_can1__BTR = 32'h00000000;
+parameter mask_can1__BTR = 32'hFFFFFFFF;
+
+parameter can1__ECR = 32'hE0009010;
+parameter val_can1__ECR = 32'h00000000;
+parameter mask_can1__ECR = 32'hFFFFFFFF;
+
+parameter can1__ESR = 32'hE0009014;
+parameter val_can1__ESR = 32'h00000000;
+parameter mask_can1__ESR = 32'hFFFFFFFF;
+
+parameter can1__SR = 32'hE0009018;
+parameter val_can1__SR = 32'h00000001;
+parameter mask_can1__SR = 32'hFFFFFFFF;
+
+parameter can1__ISR = 32'hE000901C;
+parameter val_can1__ISR = 32'h00006000;
+parameter mask_can1__ISR = 32'hFFFFFFFF;
+
+parameter can1__IER = 32'hE0009020;
+parameter val_can1__IER = 32'h00000000;
+parameter mask_can1__IER = 32'hFFFFFFFF;
+
+parameter can1__ICR = 32'hE0009024;
+parameter val_can1__ICR = 32'h00000000;
+parameter mask_can1__ICR = 32'hFFFFFFFF;
+
+parameter can1__TCR = 32'hE0009028;
+parameter val_can1__TCR = 32'h00000000;
+parameter mask_can1__TCR = 32'hFFFFFFFF;
+
+parameter can1__WIR = 32'hE000902C;
+parameter val_can1__WIR = 32'h00003F3F;
+parameter mask_can1__WIR = 32'hFFFFFFFF;
+
+parameter can1__TXFIFO_ID = 32'hE0009030;
+parameter val_can1__TXFIFO_ID = 32'h00000000;
+parameter mask_can1__TXFIFO_ID = 32'hFFFFFFFF;
+
+parameter can1__TXFIFO_DLC = 32'hE0009034;
+parameter val_can1__TXFIFO_DLC = 32'h00000000;
+parameter mask_can1__TXFIFO_DLC = 32'hFFFFFFFF;
+
+parameter can1__TXFIFO_DATA1 = 32'hE0009038;
+parameter val_can1__TXFIFO_DATA1 = 32'h00000000;
+parameter mask_can1__TXFIFO_DATA1 = 32'hFFFFFFFF;
+
+parameter can1__TXFIFO_DATA2 = 32'hE000903C;
+parameter val_can1__TXFIFO_DATA2 = 32'h00000000;
+parameter mask_can1__TXFIFO_DATA2 = 32'hFFFFFFFF;
+
+parameter can1__TXHPB_ID = 32'hE0009040;
+parameter val_can1__TXHPB_ID = 32'h00000000;
+parameter mask_can1__TXHPB_ID = 32'hFFFFFFFF;
+
+parameter can1__TXHPB_DLC = 32'hE0009044;
+parameter val_can1__TXHPB_DLC = 32'h00000000;
+parameter mask_can1__TXHPB_DLC = 32'hFFFFFFFF;
+
+parameter can1__TXHPB_DATA1 = 32'hE0009048;
+parameter val_can1__TXHPB_DATA1 = 32'h00000000;
+parameter mask_can1__TXHPB_DATA1 = 32'hFFFFFFFF;
+
+parameter can1__TXHPB_DATA2 = 32'hE000904C;
+parameter val_can1__TXHPB_DATA2 = 32'h00000000;
+parameter mask_can1__TXHPB_DATA2 = 32'hFFFFFFFF;
+
+parameter can1__RXFIFO_ID = 32'hE0009050;
+parameter val_can1__RXFIFO_ID = 32'h00000000;
+parameter mask_can1__RXFIFO_ID = 32'h00000000;
+
+parameter can1__RXFIFO_DLC = 32'hE0009054;
+parameter val_can1__RXFIFO_DLC = 32'h00000000;
+parameter mask_can1__RXFIFO_DLC = 32'h00000000;
+
+parameter can1__RXFIFO_DATA1 = 32'hE0009058;
+parameter val_can1__RXFIFO_DATA1 = 32'h00000000;
+parameter mask_can1__RXFIFO_DATA1 = 32'h00000000;
+
+parameter can1__RXFIFO_DATA2 = 32'hE000905C;
+parameter val_can1__RXFIFO_DATA2 = 32'h00000000;
+parameter mask_can1__RXFIFO_DATA2 = 32'h00000000;
+
+parameter can1__AFR = 32'hE0009060;
+parameter val_can1__AFR = 32'h00000000;
+parameter mask_can1__AFR = 32'hFFFFFFFF;
+
+parameter can1__AFMR1 = 32'hE0009064;
+parameter val_can1__AFMR1 = 32'h00000000;
+parameter mask_can1__AFMR1 = 32'h00000000;
+
+parameter can1__AFIR1 = 32'hE0009068;
+parameter val_can1__AFIR1 = 32'h00000000;
+parameter mask_can1__AFIR1 = 32'h00000000;
+
+parameter can1__AFMR2 = 32'hE000906C;
+parameter val_can1__AFMR2 = 32'h00000000;
+parameter mask_can1__AFMR2 = 32'h00000000;
+
+parameter can1__AFIR2 = 32'hE0009070;
+parameter val_can1__AFIR2 = 32'h00000000;
+parameter mask_can1__AFIR2 = 32'h00000000;
+
+parameter can1__AFMR3 = 32'hE0009074;
+parameter val_can1__AFMR3 = 32'h00000000;
+parameter mask_can1__AFMR3 = 32'h00000000;
+
+parameter can1__AFIR3 = 32'hE0009078;
+parameter val_can1__AFIR3 = 32'h00000000;
+parameter mask_can1__AFIR3 = 32'h00000000;
+
+parameter can1__AFMR4 = 32'hE000907C;
+parameter val_can1__AFMR4 = 32'h00000000;
+parameter mask_can1__AFMR4 = 32'h00000000;
+
+parameter can1__AFIR4 = 32'hE0009080;
+parameter val_can1__AFIR4 = 32'h00000000;
+parameter mask_can1__AFIR4 = 32'h00000000;
+
+
+// ************************************************************
+//   Module ddrc ddrc
+//   doc version: 1.25
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter ddrc__ddrc_ctrl = 32'hF8006000;
+parameter val_ddrc__ddrc_ctrl = 32'h00000200;
+parameter mask_ddrc__ddrc_ctrl = 32'hFFFFFFFF;
+
+parameter ddrc__Two_rank_cfg = 32'hF8006004;
+parameter val_ddrc__Two_rank_cfg = 32'h000C1076;
+parameter mask_ddrc__Two_rank_cfg = 32'h1FFFFFFF;
+
+parameter ddrc__HPR_reg = 32'hF8006008;
+parameter val_ddrc__HPR_reg = 32'h03C0780F;
+parameter mask_ddrc__HPR_reg = 32'h03FFFFFF;
+
+parameter ddrc__LPR_reg = 32'hF800600C;
+parameter val_ddrc__LPR_reg = 32'h03C0780F;
+parameter mask_ddrc__LPR_reg = 32'h03FFFFFF;
+
+parameter ddrc__WR_reg = 32'hF8006010;
+parameter val_ddrc__WR_reg = 32'h0007F80F;
+parameter mask_ddrc__WR_reg = 32'h03FFFFFF;
+
+parameter ddrc__DRAM_param_reg0 = 32'hF8006014;
+parameter val_ddrc__DRAM_param_reg0 = 32'h00041016;
+parameter mask_ddrc__DRAM_param_reg0 = 32'h001FFFFF;
+
+parameter ddrc__DRAM_param_reg1 = 32'hF8006018;
+parameter val_ddrc__DRAM_param_reg1 = 32'h351B48D9;
+parameter mask_ddrc__DRAM_param_reg1 = 32'hF7FFFFFF;
+
+parameter ddrc__DRAM_param_reg2 = 32'hF800601C;
+parameter val_ddrc__DRAM_param_reg2 = 32'h83015904;
+parameter mask_ddrc__DRAM_param_reg2 = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_param_reg3 = 32'hF8006020;
+parameter val_ddrc__DRAM_param_reg3 = 32'h250882D0;
+parameter mask_ddrc__DRAM_param_reg3 = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_param_reg4 = 32'hF8006024;
+parameter val_ddrc__DRAM_param_reg4 = 32'h0000003C;
+parameter mask_ddrc__DRAM_param_reg4 = 32'h0FFFFFFF;
+
+parameter ddrc__DRAM_init_param = 32'hF8006028;
+parameter val_ddrc__DRAM_init_param = 32'h00002007;
+parameter mask_ddrc__DRAM_init_param = 32'h00003FFF;
+
+parameter ddrc__DRAM_EMR_reg = 32'hF800602C;
+parameter val_ddrc__DRAM_EMR_reg = 32'h00000008;
+parameter mask_ddrc__DRAM_EMR_reg = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_EMR_MR_reg = 32'hF8006030;
+parameter val_ddrc__DRAM_EMR_MR_reg = 32'h00000940;
+parameter mask_ddrc__DRAM_EMR_MR_reg = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_burst8_rdwr = 32'hF8006034;
+parameter val_ddrc__DRAM_burst8_rdwr = 32'h00020034;
+parameter mask_ddrc__DRAM_burst8_rdwr = 32'h1FFFFFFF;
+
+parameter ddrc__DRAM_disable_DQ = 32'hF8006038;
+parameter val_ddrc__DRAM_disable_DQ = 32'h00000000;
+parameter mask_ddrc__DRAM_disable_DQ = 32'h00001FFF;
+
+parameter ddrc__DRAM_addr_map_bank = 32'hF800603C;
+parameter val_ddrc__DRAM_addr_map_bank = 32'h00000F77;
+parameter mask_ddrc__DRAM_addr_map_bank = 32'h000FFFFF;
+
+parameter ddrc__DRAM_addr_map_col = 32'hF8006040;
+parameter val_ddrc__DRAM_addr_map_col = 32'hFFF00000;
+parameter mask_ddrc__DRAM_addr_map_col = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_addr_map_row = 32'hF8006044;
+parameter val_ddrc__DRAM_addr_map_row = 32'h0FF55555;
+parameter mask_ddrc__DRAM_addr_map_row = 32'h0FFFFFFF;
+
+parameter ddrc__DRAM_ODT_reg = 32'hF8006048;
+parameter val_ddrc__DRAM_ODT_reg = 32'h00000249;
+parameter mask_ddrc__DRAM_ODT_reg = 32'h3FFFFFFF;
+
+parameter ddrc__phy_dbg_reg = 32'hF800604C;
+parameter val_ddrc__phy_dbg_reg = 32'h00000000;
+parameter mask_ddrc__phy_dbg_reg = 32'h000FFFFF;
+
+parameter ddrc__phy_cmd_timeout_rddata_cpt = 32'hF8006050;
+parameter val_ddrc__phy_cmd_timeout_rddata_cpt = 32'h00010200;
+parameter mask_ddrc__phy_cmd_timeout_rddata_cpt = 32'hFFFFFFFF;
+
+parameter ddrc__mode_sts_reg = 32'hF8006054;
+parameter val_ddrc__mode_sts_reg = 32'h00000000;
+parameter mask_ddrc__mode_sts_reg = 32'h001FFFFF;
+
+parameter ddrc__DLL_calib = 32'hF8006058;
+parameter val_ddrc__DLL_calib = 32'h00000101;
+parameter mask_ddrc__DLL_calib = 32'h0001FFFF;
+
+parameter ddrc__ODT_delay_hold = 32'hF800605C;
+parameter val_ddrc__ODT_delay_hold = 32'h00000023;
+parameter mask_ddrc__ODT_delay_hold = 32'h0000FFFF;
+
+parameter ddrc__ctrl_reg1 = 32'hF8006060;
+parameter val_ddrc__ctrl_reg1 = 32'h0000003E;
+parameter mask_ddrc__ctrl_reg1 = 32'h00001FFF;
+
+parameter ddrc__ctrl_reg2 = 32'hF8006064;
+parameter val_ddrc__ctrl_reg2 = 32'h00020000;
+parameter mask_ddrc__ctrl_reg2 = 32'h0003FFFF;
+
+parameter ddrc__ctrl_reg3 = 32'hF8006068;
+parameter val_ddrc__ctrl_reg3 = 32'h00284027;
+parameter mask_ddrc__ctrl_reg3 = 32'h03FFFFFF;
+
+parameter ddrc__ctrl_reg4 = 32'hF800606C;
+parameter val_ddrc__ctrl_reg4 = 32'h00001610;
+parameter mask_ddrc__ctrl_reg4 = 32'h0000FFFF;
+
+parameter ddrc__ctrl_reg5 = 32'hF8006078;
+parameter val_ddrc__ctrl_reg5 = 32'h00455111;
+parameter mask_ddrc__ctrl_reg5 = 32'hFFFFFFFF;
+
+parameter ddrc__ctrl_reg6 = 32'hF800607C;
+parameter val_ddrc__ctrl_reg6 = 32'h00032222;
+parameter mask_ddrc__ctrl_reg6 = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_REFRESH_TIMER01 = 32'hF80060A0;
+parameter val_ddrc__CHE_REFRESH_TIMER01 = 32'h00008000;
+parameter mask_ddrc__CHE_REFRESH_TIMER01 = 32'h00FFFFFF;
+
+parameter ddrc__CHE_T_ZQ = 32'hF80060A4;
+parameter val_ddrc__CHE_T_ZQ = 32'h10300802;
+parameter mask_ddrc__CHE_T_ZQ = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'hF80060A8;
+parameter val_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0020003A;
+parameter mask_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0FFFFFFF;
+
+parameter ddrc__deep_pwrdwn_reg = 32'hF80060AC;
+parameter val_ddrc__deep_pwrdwn_reg = 32'h00000000;
+parameter mask_ddrc__deep_pwrdwn_reg = 32'h000001FF;
+
+parameter ddrc__reg_2c = 32'hF80060B0;
+parameter val_ddrc__reg_2c = 32'h00000000;
+parameter mask_ddrc__reg_2c = 32'h1FFFFFFF;
+
+parameter ddrc__reg_2d = 32'hF80060B4;
+parameter val_ddrc__reg_2d = 32'h00000200;
+parameter mask_ddrc__reg_2d = 32'h000007FF;
+
+parameter ddrc__dfi_timing = 32'hF80060B8;
+parameter val_ddrc__dfi_timing = 32'h00200067;
+parameter mask_ddrc__dfi_timing = 32'h01FFFFFF;
+
+parameter ddrc__refresh_timer_2 = 32'hF80060BC;
+parameter val_ddrc__refresh_timer_2 = 32'h00000000;
+parameter mask_ddrc__refresh_timer_2 = 32'h00FFFFFF;
+
+parameter ddrc__nc_timing = 32'hF80060C0;
+parameter val_ddrc__nc_timing = 32'h00000000;
+parameter mask_ddrc__nc_timing = 32'h003FFFFF;
+
+parameter ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'hF80060C4;
+parameter val_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000003;
+
+parameter ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'hF80060C8;
+parameter val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h000000FF;
+
+parameter ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'hF80060CC;
+parameter val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF;
+
+parameter ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060D0;
+parameter val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060D4;
+parameter val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060D8;
+parameter val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF;
+
+parameter ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'hF80060DC;
+parameter val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000001;
+
+parameter ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'hF80060E0;
+parameter val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF;
+
+parameter ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060E4;
+parameter val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060E8;
+parameter val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060EC;
+parameter val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF;
+
+parameter ddrc__CHE_ECC_STATS_REG_OFFSET = 32'hF80060F0;
+parameter val_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h0000FFFF;
+
+parameter ddrc__ECC_scrub = 32'hF80060F4;
+parameter val_ddrc__ECC_scrub = 32'h00000008;
+parameter mask_ddrc__ECC_scrub = 32'h0000000F;
+
+parameter ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hF80060F8;
+parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hF80060FC;
+parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__phy_rcvr_enable = 32'hF8006114;
+parameter val_ddrc__phy_rcvr_enable = 32'h00000000;
+parameter mask_ddrc__phy_rcvr_enable = 32'h000000FF;
+
+parameter ddrc__PHY_Config0 = 32'hF8006118;
+parameter val_ddrc__PHY_Config0 = 32'h40000001;
+parameter mask_ddrc__PHY_Config0 = 32'h7FFFFFFF;
+
+parameter ddrc__PHY_Config1 = 32'hF800611C;
+parameter val_ddrc__PHY_Config1 = 32'h40000001;
+parameter mask_ddrc__PHY_Config1 = 32'h7FFFFFFF;
+
+parameter ddrc__PHY_Config2 = 32'hF8006120;
+parameter val_ddrc__PHY_Config2 = 32'h40000001;
+parameter mask_ddrc__PHY_Config2 = 32'h7FFFFFFF;
+
+parameter ddrc__PHY_Config3 = 32'hF8006124;
+parameter val_ddrc__PHY_Config3 = 32'h40000001;
+parameter mask_ddrc__PHY_Config3 = 32'h7FFFFFFF;
+
+parameter ddrc__phy_init_ratio0 = 32'hF800612C;
+parameter val_ddrc__phy_init_ratio0 = 32'h00000000;
+parameter mask_ddrc__phy_init_ratio0 = 32'h000FFFFF;
+
+parameter ddrc__phy_init_ratio1 = 32'hF8006130;
+parameter val_ddrc__phy_init_ratio1 = 32'h00000000;
+parameter mask_ddrc__phy_init_ratio1 = 32'h000FFFFF;
+
+parameter ddrc__phy_init_ratio2 = 32'hF8006134;
+parameter val_ddrc__phy_init_ratio2 = 32'h00000000;
+parameter mask_ddrc__phy_init_ratio2 = 32'h000FFFFF;
+
+parameter ddrc__phy_init_ratio3 = 32'hF8006138;
+parameter val_ddrc__phy_init_ratio3 = 32'h00000000;
+parameter mask_ddrc__phy_init_ratio3 = 32'h000FFFFF;
+
+parameter ddrc__phy_rd_dqs_cfg0 = 32'hF8006140;
+parameter val_ddrc__phy_rd_dqs_cfg0 = 32'h00000040;
+parameter mask_ddrc__phy_rd_dqs_cfg0 = 32'h000FFFFF;
+
+parameter ddrc__phy_rd_dqs_cfg1 = 32'hF8006144;
+parameter val_ddrc__phy_rd_dqs_cfg1 = 32'h00000040;
+parameter mask_ddrc__phy_rd_dqs_cfg1 = 32'h000FFFFF;
+
+parameter ddrc__phy_rd_dqs_cfg2 = 32'hF8006148;
+parameter val_ddrc__phy_rd_dqs_cfg2 = 32'h00000040;
+parameter mask_ddrc__phy_rd_dqs_cfg2 = 32'h000FFFFF;
+
+parameter ddrc__phy_rd_dqs_cfg3 = 32'hF800614C;
+parameter val_ddrc__phy_rd_dqs_cfg3 = 32'h00000040;
+parameter mask_ddrc__phy_rd_dqs_cfg3 = 32'h000FFFFF;
+
+parameter ddrc__phy_wr_dqs_cfg0 = 32'hF8006154;
+parameter val_ddrc__phy_wr_dqs_cfg0 = 32'h00000000;
+parameter mask_ddrc__phy_wr_dqs_cfg0 = 32'h000FFFFF;
+
+parameter ddrc__phy_wr_dqs_cfg1 = 32'hF8006158;
+parameter val_ddrc__phy_wr_dqs_cfg1 = 32'h00000000;
+parameter mask_ddrc__phy_wr_dqs_cfg1 = 32'h000FFFFF;
+
+parameter ddrc__phy_wr_dqs_cfg2 = 32'hF800615C;
+parameter val_ddrc__phy_wr_dqs_cfg2 = 32'h00000000;
+parameter mask_ddrc__phy_wr_dqs_cfg2 = 32'h000FFFFF;
+
+parameter ddrc__phy_wr_dqs_cfg3 = 32'hF8006160;
+parameter val_ddrc__phy_wr_dqs_cfg3 = 32'h00000000;
+parameter mask_ddrc__phy_wr_dqs_cfg3 = 32'h000FFFFF;
+
+parameter ddrc__phy_we_cfg0 = 32'hF8006168;
+parameter val_ddrc__phy_we_cfg0 = 32'h00000040;
+parameter mask_ddrc__phy_we_cfg0 = 32'h001FFFFF;
+
+parameter ddrc__phy_we_cfg1 = 32'hF800616C;
+parameter val_ddrc__phy_we_cfg1 = 32'h00000040;
+parameter mask_ddrc__phy_we_cfg1 = 32'h001FFFFF;
+
+parameter ddrc__phy_we_cfg2 = 32'hF8006170;
+parameter val_ddrc__phy_we_cfg2 = 32'h00000040;
+parameter mask_ddrc__phy_we_cfg2 = 32'h001FFFFF;
+
+parameter ddrc__phy_we_cfg3 = 32'hF8006174;
+parameter val_ddrc__phy_we_cfg3 = 32'h00000040;
+parameter mask_ddrc__phy_we_cfg3 = 32'h001FFFFF;
+
+parameter ddrc__wr_data_slv0 = 32'hF800617C;
+parameter val_ddrc__wr_data_slv0 = 32'h00000080;
+parameter mask_ddrc__wr_data_slv0 = 32'h000FFFFF;
+
+parameter ddrc__wr_data_slv1 = 32'hF8006180;
+parameter val_ddrc__wr_data_slv1 = 32'h00000080;
+parameter mask_ddrc__wr_data_slv1 = 32'h000FFFFF;
+
+parameter ddrc__wr_data_slv2 = 32'hF8006184;
+parameter val_ddrc__wr_data_slv2 = 32'h00000080;
+parameter mask_ddrc__wr_data_slv2 = 32'h000FFFFF;
+
+parameter ddrc__wr_data_slv3 = 32'hF8006188;
+parameter val_ddrc__wr_data_slv3 = 32'h00000080;
+parameter mask_ddrc__wr_data_slv3 = 32'h000FFFFF;
+
+parameter ddrc__reg_64 = 32'hF8006190;
+parameter val_ddrc__reg_64 = 32'h10020000;
+parameter mask_ddrc__reg_64 = 32'hFFFFFFFF;
+
+parameter ddrc__reg_65 = 32'hF8006194;
+parameter val_ddrc__reg_65 = 32'h00000000;
+parameter mask_ddrc__reg_65 = 32'h000FFFFF;
+
+parameter ddrc__reg69_6a0 = 32'hF80061A4;
+parameter val_ddrc__reg69_6a0 = 32'h000F0000;
+parameter mask_ddrc__reg69_6a0 = 32'h1FFFFFFF;
+
+parameter ddrc__reg69_6a1 = 32'hF80061A8;
+parameter val_ddrc__reg69_6a1 = 32'h000F0000;
+parameter mask_ddrc__reg69_6a1 = 32'h1FFFFFFF;
+
+parameter ddrc__reg6c_6d2 = 32'hF80061B0;
+parameter val_ddrc__reg6c_6d2 = 32'h000F0000;
+parameter mask_ddrc__reg6c_6d2 = 32'h1FFFFFFF;
+
+parameter ddrc__reg6c_6d3 = 32'hF80061B4;
+parameter val_ddrc__reg6c_6d3 = 32'h000F0000;
+parameter mask_ddrc__reg6c_6d3 = 32'h1FFFFFFF;
+
+parameter ddrc__reg6e_710 = 32'hF80061B8;
+parameter val_ddrc__reg6e_710 = 32'h00000000;
+parameter mask_ddrc__reg6e_710 = 32'h00000000;
+
+parameter ddrc__reg6e_711 = 32'hF80061BC;
+parameter val_ddrc__reg6e_711 = 32'h00000000;
+parameter mask_ddrc__reg6e_711 = 32'h00000000;
+
+parameter ddrc__reg6e_712 = 32'hF80061C0;
+parameter val_ddrc__reg6e_712 = 32'h00000000;
+parameter mask_ddrc__reg6e_712 = 32'h00000000;
+
+parameter ddrc__reg6e_713 = 32'hF80061C4;
+parameter val_ddrc__reg6e_713 = 32'h00000000;
+parameter mask_ddrc__reg6e_713 = 32'h00000000;
+
+parameter ddrc__phy_dll_sts0 = 32'hF80061CC;
+parameter val_ddrc__phy_dll_sts0 = 32'h00000000;
+parameter mask_ddrc__phy_dll_sts0 = 32'h07FFFFFF;
+
+parameter ddrc__phy_dll_sts1 = 32'hF80061D0;
+parameter val_ddrc__phy_dll_sts1 = 32'h00000000;
+parameter mask_ddrc__phy_dll_sts1 = 32'h07FFFFFF;
+
+parameter ddrc__phy_dll_sts2 = 32'hF80061D4;
+parameter val_ddrc__phy_dll_sts2 = 32'h00000000;
+parameter mask_ddrc__phy_dll_sts2 = 32'h07FFFFFF;
+
+parameter ddrc__phy_dll_sts3 = 32'hF80061D8;
+parameter val_ddrc__phy_dll_sts3 = 32'h00000000;
+parameter mask_ddrc__phy_dll_sts3 = 32'h07FFFFFF;
+
+parameter ddrc__dll_lock_sts = 32'hF80061E0;
+parameter val_ddrc__dll_lock_sts = 32'h00000000;
+parameter mask_ddrc__dll_lock_sts = 32'h00FFFFFF;
+
+parameter ddrc__phy_ctrl_sts = 32'hF80061E4;
+parameter val_ddrc__phy_ctrl_sts = 32'h00000000;
+parameter mask_ddrc__phy_ctrl_sts = 32'h3FF80000;
+
+parameter ddrc__phy_ctrl_sts_reg2 = 32'hF80061E8;
+parameter val_ddrc__phy_ctrl_sts_reg2 = 32'h00000000;
+parameter mask_ddrc__phy_ctrl_sts_reg2 = 32'h07FFFFFF;
+
+parameter ddrc__axi_id = 32'hF8006200;
+parameter val_ddrc__axi_id = 32'h00153042;
+parameter mask_ddrc__axi_id = 32'h03FFFFFF;
+
+parameter ddrc__page_mask = 32'hF8006204;
+parameter val_ddrc__page_mask = 32'h00000000;
+parameter mask_ddrc__page_mask = 32'hFFFFFFFF;
+
+parameter ddrc__axi_priority_wr_port0 = 32'hF8006208;
+parameter val_ddrc__axi_priority_wr_port0 = 32'h000803FF;
+parameter mask_ddrc__axi_priority_wr_port0 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_wr_port1 = 32'hF800620C;
+parameter val_ddrc__axi_priority_wr_port1 = 32'h000803FF;
+parameter mask_ddrc__axi_priority_wr_port1 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_wr_port2 = 32'hF8006210;
+parameter val_ddrc__axi_priority_wr_port2 = 32'h000803FF;
+parameter mask_ddrc__axi_priority_wr_port2 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_wr_port3 = 32'hF8006214;
+parameter val_ddrc__axi_priority_wr_port3 = 32'h000803FF;
+parameter mask_ddrc__axi_priority_wr_port3 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_rd_port0 = 32'hF8006218;
+parameter val_ddrc__axi_priority_rd_port0 = 32'h000003FF;
+parameter mask_ddrc__axi_priority_rd_port0 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_rd_port1 = 32'hF800621C;
+parameter val_ddrc__axi_priority_rd_port1 = 32'h000003FF;
+parameter mask_ddrc__axi_priority_rd_port1 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_rd_port2 = 32'hF8006220;
+parameter val_ddrc__axi_priority_rd_port2 = 32'h000003FF;
+parameter mask_ddrc__axi_priority_rd_port2 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_rd_port3 = 32'hF8006224;
+parameter val_ddrc__axi_priority_rd_port3 = 32'h000003FF;
+parameter mask_ddrc__axi_priority_rd_port3 = 32'h000FFFFF;
+
+parameter ddrc__AHB_priority_cfg0 = 32'hF8006248;
+parameter val_ddrc__AHB_priority_cfg0 = 32'h000003FF;
+parameter mask_ddrc__AHB_priority_cfg0 = 32'h000FFFFF;
+
+parameter ddrc__AHB_priority_cfg1 = 32'hF800624C;
+parameter val_ddrc__AHB_priority_cfg1 = 32'h000003FF;
+parameter mask_ddrc__AHB_priority_cfg1 = 32'h000FFFFF;
+
+parameter ddrc__AHB_priority_cfg2 = 32'hF8006250;
+parameter val_ddrc__AHB_priority_cfg2 = 32'h000003FF;
+parameter mask_ddrc__AHB_priority_cfg2 = 32'h000FFFFF;
+
+parameter ddrc__AHB_priority_cfg3 = 32'hF8006254;
+parameter val_ddrc__AHB_priority_cfg3 = 32'h000003FF;
+parameter mask_ddrc__AHB_priority_cfg3 = 32'h000FFFFF;
+
+parameter ddrc__perf_mon0 = 32'hF8006260;
+parameter val_ddrc__perf_mon0 = 32'h00000000;
+parameter mask_ddrc__perf_mon0 = 32'h7FFFFFFF;
+
+parameter ddrc__perf_mon1 = 32'hF8006264;
+parameter val_ddrc__perf_mon1 = 32'h00000000;
+parameter mask_ddrc__perf_mon1 = 32'h7FFFFFFF;
+
+parameter ddrc__perf_mon2 = 32'hF8006268;
+parameter val_ddrc__perf_mon2 = 32'h00000000;
+parameter mask_ddrc__perf_mon2 = 32'h7FFFFFFF;
+
+parameter ddrc__perf_mon3 = 32'hF800626C;
+parameter val_ddrc__perf_mon3 = 32'h00000000;
+parameter mask_ddrc__perf_mon3 = 32'h7FFFFFFF;
+
+parameter ddrc__perf_mon20 = 32'hF8006270;
+parameter val_ddrc__perf_mon20 = 32'h00000000;
+parameter mask_ddrc__perf_mon20 = 32'hFFFFFFFF;
+
+parameter ddrc__perf_mon21 = 32'hF8006274;
+parameter val_ddrc__perf_mon21 = 32'h00000000;
+parameter mask_ddrc__perf_mon21 = 32'hFFFFFFFF;
+
+parameter ddrc__perf_mon22 = 32'hF8006278;
+parameter val_ddrc__perf_mon22 = 32'h00000000;
+parameter mask_ddrc__perf_mon22 = 32'hFFFFFFFF;
+
+parameter ddrc__perf_mon23 = 32'hF800627C;
+parameter val_ddrc__perf_mon23 = 32'h00000000;
+parameter mask_ddrc__perf_mon23 = 32'hFFFFFFFF;
+
+parameter ddrc__perf_mon30 = 32'hF8006280;
+parameter val_ddrc__perf_mon30 = 32'h00000000;
+parameter mask_ddrc__perf_mon30 = 32'h0000FFFF;
+
+parameter ddrc__perf_mon31 = 32'hF8006284;
+parameter val_ddrc__perf_mon31 = 32'h00000000;
+parameter mask_ddrc__perf_mon31 = 32'h0000FFFF;
+
+parameter ddrc__perf_mon32 = 32'hF8006288;
+parameter val_ddrc__perf_mon32 = 32'h00000000;
+parameter mask_ddrc__perf_mon32 = 32'h0000FFFF;
+
+parameter ddrc__perf_mon33 = 32'hF800628C;
+parameter val_ddrc__perf_mon33 = 32'h00000000;
+parameter mask_ddrc__perf_mon33 = 32'h0000FFFF;
+
+parameter ddrc__trusted_mem_cfg = 32'hF8006290;
+parameter val_ddrc__trusted_mem_cfg = 32'h00000000;
+parameter mask_ddrc__trusted_mem_cfg = 32'h0000FFFF;
+
+parameter ddrc__excl_access_cfg0 = 32'hF8006294;
+parameter val_ddrc__excl_access_cfg0 = 32'h00000000;
+parameter mask_ddrc__excl_access_cfg0 = 32'h0003FFFF;
+
+parameter ddrc__excl_access_cfg1 = 32'hF8006298;
+parameter val_ddrc__excl_access_cfg1 = 32'h00000000;
+parameter mask_ddrc__excl_access_cfg1 = 32'h0003FFFF;
+
+parameter ddrc__excl_access_cfg2 = 32'hF800629C;
+parameter val_ddrc__excl_access_cfg2 = 32'h00000000;
+parameter mask_ddrc__excl_access_cfg2 = 32'h0003FFFF;
+
+parameter ddrc__excl_access_cfg3 = 32'hF80062A0;
+parameter val_ddrc__excl_access_cfg3 = 32'h00000000;
+parameter mask_ddrc__excl_access_cfg3 = 32'h0003FFFF;
+
+parameter ddrc__mode_reg_read = 32'hF80062A4;
+parameter val_ddrc__mode_reg_read = 32'h00000000;
+parameter mask_ddrc__mode_reg_read = 32'hFFFFFFFF;
+
+parameter ddrc__lpddr_ctrl0 = 32'hF80062A8;
+parameter val_ddrc__lpddr_ctrl0 = 32'h00000000;
+parameter mask_ddrc__lpddr_ctrl0 = 32'h00000FFF;
+
+parameter ddrc__lpddr_ctrl1 = 32'hF80062AC;
+parameter val_ddrc__lpddr_ctrl1 = 32'h00000000;
+parameter mask_ddrc__lpddr_ctrl1 = 32'hFFFFFFFF;
+
+parameter ddrc__lpddr_ctrl2 = 32'hF80062B0;
+parameter val_ddrc__lpddr_ctrl2 = 32'h003C0015;
+parameter mask_ddrc__lpddr_ctrl2 = 32'h003FFFFF;
+
+parameter ddrc__lpddr_ctrl3 = 32'hF80062B4;
+parameter val_ddrc__lpddr_ctrl3 = 32'h00000601;
+parameter mask_ddrc__lpddr_ctrl3 = 32'h0003FFFF;
+
+parameter ddrc__phy_wr_lvl_fsm = 32'hF80062B8;
+parameter val_ddrc__phy_wr_lvl_fsm = 32'h00004444;
+parameter mask_ddrc__phy_wr_lvl_fsm = 32'h00007FFF;
+
+parameter ddrc__phy_rd_lvl_fsm = 32'hF80062BC;
+parameter val_ddrc__phy_rd_lvl_fsm = 32'h00008888;
+parameter mask_ddrc__phy_rd_lvl_fsm = 32'h0000FFFF;
+
+parameter ddrc__phy_gate_lvl_fsm = 32'hF80062C0;
+parameter val_ddrc__phy_gate_lvl_fsm = 32'h00004444;
+parameter mask_ddrc__phy_gate_lvl_fsm = 32'h00007FFF;
+
+
+// ************************************************************
+//   Module debug_axim axim
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_axim__GLOBAL_CTRL = 32'hF880C000;
+parameter val_debug_axim__GLOBAL_CTRL = 32'h00000002;
+parameter mask_debug_axim__GLOBAL_CTRL = 32'h00000003;
+
+parameter debug_axim__GLOBAL_STATUS = 32'hF880C004;
+parameter val_debug_axim__GLOBAL_STATUS = 32'h00001000;
+parameter mask_debug_axim__GLOBAL_STATUS = 32'h00001FC3;
+
+parameter debug_axim__FILTER_CTRL = 32'hF880C010;
+parameter val_debug_axim__FILTER_CTRL = 32'h00000000;
+parameter mask_debug_axim__FILTER_CTRL = 32'h0000007F;
+
+parameter debug_axim__TRIGGER_CTRL = 32'hF880C020;
+parameter val_debug_axim__TRIGGER_CTRL = 32'h00000000;
+parameter mask_debug_axim__TRIGGER_CTRL = 32'h0000FFFF;
+
+parameter debug_axim__TRIGGER_STATUS = 32'hF880C024;
+parameter val_debug_axim__TRIGGER_STATUS = 32'h00000000;
+parameter mask_debug_axim__TRIGGER_STATUS = 32'h00000003;
+
+parameter debug_axim__PACKET_CTRL = 32'hF880C030;
+parameter val_debug_axim__PACKET_CTRL = 32'h00070000;
+parameter mask_debug_axim__PACKET_CTRL = 32'h0007FFFF;
+
+parameter debug_axim__TOUT_CTRL = 32'hF880C040;
+parameter val_debug_axim__TOUT_CTRL = 32'h00000000;
+parameter mask_debug_axim__TOUT_CTRL = 32'h0000007F;
+
+parameter debug_axim__TOUT_THRESH = 32'hF880C044;
+parameter val_debug_axim__TOUT_THRESH = 32'h00008000;
+parameter mask_debug_axim__TOUT_THRESH = 32'hFFFFFFFF;
+
+parameter debug_axim__FIFO_CURRENT = 32'hF880C050;
+parameter val_debug_axim__FIFO_CURRENT = 32'h80000000;
+parameter mask_debug_axim__FIFO_CURRENT = 32'hFFFFFFFF;
+
+parameter debug_axim__FIFO_HYSTER = 32'hF880C054;
+parameter val_debug_axim__FIFO_HYSTER = 32'h00000100;
+parameter mask_debug_axim__FIFO_HYSTER = 32'h000003FF;
+
+parameter debug_axim__SYNC_CURRENT = 32'hF880C060;
+parameter val_debug_axim__SYNC_CURRENT = 32'h00000000;
+parameter mask_debug_axim__SYNC_CURRENT = 32'h00000FFF;
+
+parameter debug_axim__SYNC_RELOAD = 32'hF880C064;
+parameter val_debug_axim__SYNC_RELOAD = 32'h00000800;
+parameter mask_debug_axim__SYNC_RELOAD = 32'h00000FFF;
+
+parameter debug_axim__TSTMP_CURRENT = 32'hF880C070;
+parameter val_debug_axim__TSTMP_CURRENT = 32'h00000000;
+parameter mask_debug_axim__TSTMP_CURRENT = 32'h00000000;
+
+parameter debug_axim__ADDR0_MASK = 32'hF880C200;
+parameter val_debug_axim__ADDR0_MASK = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR0_MASK = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR0_LOWER = 32'hF880C204;
+parameter val_debug_axim__ADDR0_LOWER = 32'h00000000;
+parameter mask_debug_axim__ADDR0_LOWER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR0_UPPER = 32'hF880C208;
+parameter val_debug_axim__ADDR0_UPPER = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR0_UPPER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR0_MISC = 32'hF880C20C;
+parameter val_debug_axim__ADDR0_MISC = 32'h00000000;
+parameter mask_debug_axim__ADDR0_MISC = 32'h00007FFF;
+
+parameter debug_axim__ADDR1_MASK = 32'hF880C210;
+parameter val_debug_axim__ADDR1_MASK = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR1_MASK = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR1_LOWER = 32'hF880C214;
+parameter val_debug_axim__ADDR1_LOWER = 32'h00000000;
+parameter mask_debug_axim__ADDR1_LOWER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR1_UPPER = 32'hF880C218;
+parameter val_debug_axim__ADDR1_UPPER = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR1_UPPER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR1_MISC = 32'hF880C21C;
+parameter val_debug_axim__ADDR1_MISC = 32'h00000000;
+parameter mask_debug_axim__ADDR1_MISC = 32'h00007FFF;
+
+parameter debug_axim__ADDR2_MASK = 32'hF880C220;
+parameter val_debug_axim__ADDR2_MASK = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR2_MASK = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR2_LOWER = 32'hF880C224;
+parameter val_debug_axim__ADDR2_LOWER = 32'h00000000;
+parameter mask_debug_axim__ADDR2_LOWER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR2_UPPER = 32'hF880C228;
+parameter val_debug_axim__ADDR2_UPPER = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR2_UPPER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR2_MISC = 32'hF880C22C;
+parameter val_debug_axim__ADDR2_MISC = 32'h00000000;
+parameter mask_debug_axim__ADDR2_MISC = 32'h00007FFF;
+
+parameter debug_axim__ADDR3_MASK = 32'hF880C230;
+parameter val_debug_axim__ADDR3_MASK = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR3_MASK = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR3_LOWER = 32'hF880C234;
+parameter val_debug_axim__ADDR3_LOWER = 32'h00000000;
+parameter mask_debug_axim__ADDR3_LOWER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR3_UPPER = 32'hF880C238;
+parameter val_debug_axim__ADDR3_UPPER = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR3_UPPER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR3_MISC = 32'hF880C23C;
+parameter val_debug_axim__ADDR3_MISC = 32'h00000000;
+parameter mask_debug_axim__ADDR3_MISC = 32'h00007FFF;
+
+parameter debug_axim__ID0_MASK = 32'hF880C300;
+parameter val_debug_axim__ID0_MASK = 32'h000003FF;
+parameter mask_debug_axim__ID0_MASK = 32'h000003FF;
+
+parameter debug_axim__ID0_LOWER = 32'hF880C304;
+parameter val_debug_axim__ID0_LOWER = 32'h00000000;
+parameter mask_debug_axim__ID0_LOWER = 32'h000003FF;
+
+parameter debug_axim__ID0_UPPER = 32'hF880C308;
+parameter val_debug_axim__ID0_UPPER = 32'h000003FF;
+parameter mask_debug_axim__ID0_UPPER = 32'h000003FF;
+
+parameter debug_axim__ID0_MISC = 32'hF880C30C;
+parameter val_debug_axim__ID0_MISC = 32'h00000000;
+parameter mask_debug_axim__ID0_MISC = 32'h00003FFF;
+
+parameter debug_axim__ID1_MASK = 32'hF880C310;
+parameter val_debug_axim__ID1_MASK = 32'h000003FF;
+parameter mask_debug_axim__ID1_MASK = 32'h000003FF;
+
+parameter debug_axim__ID1_LOWER = 32'hF880C314;
+parameter val_debug_axim__ID1_LOWER = 32'h00000000;
+parameter mask_debug_axim__ID1_LOWER = 32'h000003FF;
+
+parameter debug_axim__ID1_UPPER = 32'hF880C318;
+parameter val_debug_axim__ID1_UPPER = 32'h000003FF;
+parameter mask_debug_axim__ID1_UPPER = 32'h000003FF;
+
+parameter debug_axim__ID1_MISC = 32'hF880C31C;
+parameter val_debug_axim__ID1_MISC = 32'h00000000;
+parameter mask_debug_axim__ID1_MISC = 32'h00003FFF;
+
+parameter debug_axim__ID2_MASK = 32'hF880C320;
+parameter val_debug_axim__ID2_MASK = 32'h000003FF;
+parameter mask_debug_axim__ID2_MASK = 32'h000003FF;
+
+parameter debug_axim__ID2_LOWER = 32'hF880C324;
+parameter val_debug_axim__ID2_LOWER = 32'h00000000;
+parameter mask_debug_axim__ID2_LOWER = 32'h000003FF;
+
+parameter debug_axim__ID2_UPPER = 32'hF880C328;
+parameter val_debug_axim__ID2_UPPER = 32'h000003FF;
+parameter mask_debug_axim__ID2_UPPER = 32'h000003FF;
+
+parameter debug_axim__ID2_MISC = 32'hF880C32C;
+parameter val_debug_axim__ID2_MISC = 32'h00000000;
+parameter mask_debug_axim__ID2_MISC = 32'h00003FFF;
+
+parameter debug_axim__ID3_MASK = 32'hF880C330;
+parameter val_debug_axim__ID3_MASK = 32'h000003FF;
+parameter mask_debug_axim__ID3_MASK = 32'h000003FF;
+
+parameter debug_axim__ID3_LOWER = 32'hF880C334;
+parameter val_debug_axim__ID3_LOWER = 32'h00000000;
+parameter mask_debug_axim__ID3_LOWER = 32'h000003FF;
+
+parameter debug_axim__ID3_UPPER = 32'hF880C338;
+parameter val_debug_axim__ID3_UPPER = 32'h000003FF;
+parameter mask_debug_axim__ID3_UPPER = 32'h000003FF;
+
+parameter debug_axim__ID3_MISC = 32'hF880C33C;
+parameter val_debug_axim__ID3_MISC = 32'h00000000;
+parameter mask_debug_axim__ID3_MISC = 32'h00003FFF;
+
+parameter debug_axim__AXI_SEL = 32'hF880C800;
+parameter val_debug_axim__AXI_SEL = 32'h00000000;
+parameter mask_debug_axim__AXI_SEL = 32'h00000007;
+
+parameter debug_axim__IT_TRIGOUT = 32'hF880CED0;
+parameter val_debug_axim__IT_TRIGOUT = 32'h00000000;
+parameter mask_debug_axim__IT_TRIGOUT = 32'h00000001;
+
+parameter debug_axim__IT_TRIGOUTACK = 32'hF880CED4;
+parameter val_debug_axim__IT_TRIGOUTACK = 32'h00000000;
+parameter mask_debug_axim__IT_TRIGOUTACK = 32'h00000000;
+
+parameter debug_axim__IT_TRIGIN = 32'hF880CED8;
+parameter val_debug_axim__IT_TRIGIN = 32'h00000000;
+parameter mask_debug_axim__IT_TRIGIN = 32'h00000000;
+
+parameter debug_axim__IT_TRIGINACK = 32'hF880CEDC;
+parameter val_debug_axim__IT_TRIGINACK = 32'h00000000;
+parameter mask_debug_axim__IT_TRIGINACK = 32'h00000001;
+
+parameter debug_axim__IT_ATBDATA = 32'hF880CEEC;
+parameter val_debug_axim__IT_ATBDATA = 32'h00000000;
+parameter mask_debug_axim__IT_ATBDATA = 32'h0000001F;
+
+parameter debug_axim__IT_ATBSTATUS = 32'hF880CEF0;
+parameter val_debug_axim__IT_ATBSTATUS = 32'h00000000;
+parameter mask_debug_axim__IT_ATBSTATUS = 32'h00000000;
+
+parameter debug_axim__IT_ATBCTRL1 = 32'hF880CEF4;
+parameter val_debug_axim__IT_ATBCTRL1 = 32'h00000000;
+parameter mask_debug_axim__IT_ATBCTRL1 = 32'h0000007F;
+
+parameter debug_axim__IT_ATBCTRL0 = 32'hF880CEF8;
+parameter val_debug_axim__IT_ATBCTRL0 = 32'h00000000;
+parameter mask_debug_axim__IT_ATBCTRL0 = 32'h000003FF;
+
+parameter debug_axim__IT_CTRL = 32'hF880CF00;
+parameter val_debug_axim__IT_CTRL = 32'h00000000;
+parameter mask_debug_axim__IT_CTRL = 32'h00000001;
+
+parameter debug_axim__CLAIM_SET = 32'hF880CFA0;
+parameter val_debug_axim__CLAIM_SET = 32'h00000001;
+parameter mask_debug_axim__CLAIM_SET = 32'h0000000F;
+
+parameter debug_axim__CLAIM_CLEAR = 32'hF880CFA4;
+parameter val_debug_axim__CLAIM_CLEAR = 32'h00000000;
+parameter mask_debug_axim__CLAIM_CLEAR = 32'h0000000F;
+
+parameter debug_axim__LOCK_ACCESS = 32'hF880CFB0;
+parameter val_debug_axim__LOCK_ACCESS = 32'h00000000;
+parameter mask_debug_axim__LOCK_ACCESS = 32'hFFFFFFFF;
+
+parameter debug_axim__LOCK_STATUS = 32'hF880CFB4;
+parameter val_debug_axim__LOCK_STATUS = 32'h00000003;
+parameter mask_debug_axim__LOCK_STATUS = 32'h00000007;
+
+parameter debug_axim__AUTH_STATUS = 32'hF880CFB8;
+parameter val_debug_axim__AUTH_STATUS = 32'h00000000;
+parameter mask_debug_axim__AUTH_STATUS = 32'h00000033;
+
+parameter debug_axim__DEV_ID = 32'hF880CFC8;
+parameter val_debug_axim__DEV_ID = 32'h00000000;
+parameter mask_debug_axim__DEV_ID = 32'hFFFFFFFF;
+
+parameter debug_axim__DEV_TYPE = 32'hF880CFCC;
+parameter val_debug_axim__DEV_TYPE = 32'h00000043;
+parameter mask_debug_axim__DEV_TYPE = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID4 = 32'hF880CFD0;
+parameter val_debug_axim__PERIPHID4 = 32'h00000003;
+parameter mask_debug_axim__PERIPHID4 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID5 = 32'hF880CFD4;
+parameter val_debug_axim__PERIPHID5 = 32'h00000000;
+parameter mask_debug_axim__PERIPHID5 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID6 = 32'hF880CFD8;
+parameter val_debug_axim__PERIPHID6 = 32'h00000000;
+parameter mask_debug_axim__PERIPHID6 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID7 = 32'hF880CFDC;
+parameter val_debug_axim__PERIPHID7 = 32'h00000000;
+parameter mask_debug_axim__PERIPHID7 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID0 = 32'hF880CFE0;
+parameter val_debug_axim__PERIPHID0 = 32'h000000B2;
+parameter mask_debug_axim__PERIPHID0 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID1 = 32'hF880CFE4;
+parameter val_debug_axim__PERIPHID1 = 32'h00000093;
+parameter mask_debug_axim__PERIPHID1 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID2 = 32'hF880CFE8;
+parameter val_debug_axim__PERIPHID2 = 32'h00000008;
+parameter mask_debug_axim__PERIPHID2 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID3 = 32'hF880CFEC;
+parameter val_debug_axim__PERIPHID3 = 32'h00000002;
+parameter mask_debug_axim__PERIPHID3 = 32'hFFFFFFFF;
+
+parameter debug_axim__COMPID0 = 32'hF880CFF0;
+parameter val_debug_axim__COMPID0 = 32'h0000000D;
+parameter mask_debug_axim__COMPID0 = 32'hFFFFFFFF;
+
+parameter debug_axim__COMPID1 = 32'hF880CFF4;
+parameter val_debug_axim__COMPID1 = 32'h00000090;
+parameter mask_debug_axim__COMPID1 = 32'hFFFFFFFF;
+
+parameter debug_axim__COMPID2 = 32'hF880CFF8;
+parameter val_debug_axim__COMPID2 = 32'h00000005;
+parameter mask_debug_axim__COMPID2 = 32'hFFFFFFFF;
+
+parameter debug_axim__COMPID3 = 32'hF880CFFC;
+parameter val_debug_axim__COMPID3 = 32'h000000B1;
+parameter mask_debug_axim__COMPID3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module debug_cpu_cti0 cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_cti0__CTICONTROL = 32'hF8898000;
+parameter val_debug_cpu_cti0__CTICONTROL = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTICONTROL = 32'h00000001;
+
+parameter debug_cpu_cti0__CTIINTACK = 32'hF8898010;
+parameter val_debug_cpu_cti0__CTIINTACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINTACK = 32'h000000FF;
+
+parameter debug_cpu_cti0__CTIAPPSET = 32'hF8898014;
+parameter val_debug_cpu_cti0__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIAPPCLEAR = 32'hF8898018;
+parameter val_debug_cpu_cti0__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIAPPPULSE = 32'hF889801C;
+parameter val_debug_cpu_cti0__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN0 = 32'hF8898020;
+parameter val_debug_cpu_cti0__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN1 = 32'hF8898024;
+parameter val_debug_cpu_cti0__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN2 = 32'hF8898028;
+parameter val_debug_cpu_cti0__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN3 = 32'hF889802C;
+parameter val_debug_cpu_cti0__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN4 = 32'hF8898030;
+parameter val_debug_cpu_cti0__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN5 = 32'hF8898034;
+parameter val_debug_cpu_cti0__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN6 = 32'hF8898038;
+parameter val_debug_cpu_cti0__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN7 = 32'hF889803C;
+parameter val_debug_cpu_cti0__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN0 = 32'hF88980A0;
+parameter val_debug_cpu_cti0__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN1 = 32'hF88980A4;
+parameter val_debug_cpu_cti0__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN2 = 32'hF88980A8;
+parameter val_debug_cpu_cti0__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN3 = 32'hF88980AC;
+parameter val_debug_cpu_cti0__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN4 = 32'hF88980B0;
+parameter val_debug_cpu_cti0__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN5 = 32'hF88980B4;
+parameter val_debug_cpu_cti0__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN6 = 32'hF88980B8;
+parameter val_debug_cpu_cti0__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN7 = 32'hF88980BC;
+parameter val_debug_cpu_cti0__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTITRIGINSTATUS = 32'hF8898130;
+parameter val_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cpu_cti0__CTITRIGOUTSTATUS = 32'hF8898134;
+parameter val_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cpu_cti0__CTICHINSTATUS = 32'hF8898138;
+parameter val_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cpu_cti0__CTICHOUTSTATUS = 32'hF889813C;
+parameter val_debug_cpu_cti0__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIGATE = 32'hF8898140;
+parameter val_debug_cpu_cti0__CTIGATE = 32'h0000000F;
+parameter mask_debug_cpu_cti0__CTIGATE = 32'h0000000F;
+
+parameter debug_cpu_cti0__ASICCTL = 32'hF8898144;
+parameter val_debug_cpu_cti0__ASICCTL = 32'h00000000;
+parameter mask_debug_cpu_cti0__ASICCTL = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCHINACK = 32'hF8898EDC;
+parameter val_debug_cpu_cti0__ITCHINACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCHINACK = 32'h0000000F;
+
+parameter debug_cpu_cti0__ITTRIGINACK = 32'hF8898EE0;
+parameter val_debug_cpu_cti0__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCHOUT = 32'hF8898EE4;
+parameter val_debug_cpu_cti0__ITCHOUT = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCHOUT = 32'h0000000F;
+
+parameter debug_cpu_cti0__ITTRIGOUT = 32'hF8898EE8;
+parameter val_debug_cpu_cti0__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCHOUTACK = 32'hF8898EEC;
+parameter val_debug_cpu_cti0__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cpu_cti0__ITTRIGOUTACK = 32'hF8898EF0;
+parameter val_debug_cpu_cti0__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCHIN = 32'hF8898EF4;
+parameter val_debug_cpu_cti0__ITCHIN = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCHIN = 32'h0000000F;
+
+parameter debug_cpu_cti0__ITTRIGIN = 32'hF8898EF8;
+parameter val_debug_cpu_cti0__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCTRL = 32'hF8898F00;
+parameter val_debug_cpu_cti0__ITCTRL = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCTRL = 32'h00000001;
+
+parameter debug_cpu_cti0__CTSR = 32'hF8898FA0;
+parameter val_debug_cpu_cti0__CTSR = 32'h0000000F;
+parameter mask_debug_cpu_cti0__CTSR = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTCR = 32'hF8898FA4;
+parameter val_debug_cpu_cti0__CTCR = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTCR = 32'h0000000F;
+
+parameter debug_cpu_cti0__LAR = 32'hF8898FB0;
+parameter val_debug_cpu_cti0__LAR = 32'h00000000;
+parameter mask_debug_cpu_cti0__LAR = 32'hFFFFFFFF;
+
+parameter debug_cpu_cti0__LSR = 32'hF8898FB4;
+parameter val_debug_cpu_cti0__LSR = 32'h00000003;
+parameter mask_debug_cpu_cti0__LSR = 32'h00000007;
+
+parameter debug_cpu_cti0__ASR = 32'hF8898FB8;
+parameter val_debug_cpu_cti0__ASR = 32'h00000005;
+parameter mask_debug_cpu_cti0__ASR = 32'h00000005;
+
+parameter debug_cpu_cti0__DEVID = 32'hF8898FC8;
+parameter val_debug_cpu_cti0__DEVID = 32'h00040800;
+parameter mask_debug_cpu_cti0__DEVID = 32'h000FFFFF;
+
+parameter debug_cpu_cti0__DTIR = 32'hF8898FCC;
+parameter val_debug_cpu_cti0__DTIR = 32'h00000014;
+parameter mask_debug_cpu_cti0__DTIR = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID4 = 32'hF8898FD0;
+parameter val_debug_cpu_cti0__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cpu_cti0__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID5 = 32'hF8898FD4;
+parameter val_debug_cpu_cti0__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cpu_cti0__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID6 = 32'hF8898FD8;
+parameter val_debug_cpu_cti0__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cpu_cti0__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID7 = 32'hF8898FDC;
+parameter val_debug_cpu_cti0__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cpu_cti0__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID0 = 32'hF8898FE0;
+parameter val_debug_cpu_cti0__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cpu_cti0__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID1 = 32'hF8898FE4;
+parameter val_debug_cpu_cti0__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cpu_cti0__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID2 = 32'hF8898FE8;
+parameter val_debug_cpu_cti0__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cpu_cti0__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID3 = 32'hF8898FEC;
+parameter val_debug_cpu_cti0__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cpu_cti0__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cpu_cti0__COMPID0 = 32'hF8898FF0;
+parameter val_debug_cpu_cti0__COMPID0 = 32'h0000000D;
+parameter mask_debug_cpu_cti0__COMPID0 = 32'h000000FF;
+
+parameter debug_cpu_cti0__COMPID1 = 32'hF8898FF4;
+parameter val_debug_cpu_cti0__COMPID1 = 32'h00000090;
+parameter mask_debug_cpu_cti0__COMPID1 = 32'h000000FF;
+
+parameter debug_cpu_cti0__COMPID2 = 32'hF8898FF8;
+parameter val_debug_cpu_cti0__COMPID2 = 32'h00000005;
+parameter mask_debug_cpu_cti0__COMPID2 = 32'h000000FF;
+
+parameter debug_cpu_cti0__COMPID3 = 32'hF8898FFC;
+parameter val_debug_cpu_cti0__COMPID3 = 32'h000000B1;
+parameter mask_debug_cpu_cti0__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cpu_cti1 cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_cti1__CTICONTROL = 32'hF8899000;
+parameter val_debug_cpu_cti1__CTICONTROL = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTICONTROL = 32'h00000001;
+
+parameter debug_cpu_cti1__CTIINTACK = 32'hF8899010;
+parameter val_debug_cpu_cti1__CTIINTACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINTACK = 32'h000000FF;
+
+parameter debug_cpu_cti1__CTIAPPSET = 32'hF8899014;
+parameter val_debug_cpu_cti1__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIAPPCLEAR = 32'hF8899018;
+parameter val_debug_cpu_cti1__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIAPPPULSE = 32'hF889901C;
+parameter val_debug_cpu_cti1__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN0 = 32'hF8899020;
+parameter val_debug_cpu_cti1__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN1 = 32'hF8899024;
+parameter val_debug_cpu_cti1__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN2 = 32'hF8899028;
+parameter val_debug_cpu_cti1__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN3 = 32'hF889902C;
+parameter val_debug_cpu_cti1__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN4 = 32'hF8899030;
+parameter val_debug_cpu_cti1__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN5 = 32'hF8899034;
+parameter val_debug_cpu_cti1__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN6 = 32'hF8899038;
+parameter val_debug_cpu_cti1__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN7 = 32'hF889903C;
+parameter val_debug_cpu_cti1__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN0 = 32'hF88990A0;
+parameter val_debug_cpu_cti1__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN1 = 32'hF88990A4;
+parameter val_debug_cpu_cti1__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN2 = 32'hF88990A8;
+parameter val_debug_cpu_cti1__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN3 = 32'hF88990AC;
+parameter val_debug_cpu_cti1__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN4 = 32'hF88990B0;
+parameter val_debug_cpu_cti1__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN5 = 32'hF88990B4;
+parameter val_debug_cpu_cti1__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN6 = 32'hF88990B8;
+parameter val_debug_cpu_cti1__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN7 = 32'hF88990BC;
+parameter val_debug_cpu_cti1__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTITRIGINSTATUS = 32'hF8899130;
+parameter val_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cpu_cti1__CTITRIGOUTSTATUS = 32'hF8899134;
+parameter val_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cpu_cti1__CTICHINSTATUS = 32'hF8899138;
+parameter val_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cpu_cti1__CTICHOUTSTATUS = 32'hF889913C;
+parameter val_debug_cpu_cti1__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIGATE = 32'hF8899140;
+parameter val_debug_cpu_cti1__CTIGATE = 32'h0000000F;
+parameter mask_debug_cpu_cti1__CTIGATE = 32'h0000000F;
+
+parameter debug_cpu_cti1__ASICCTL = 32'hF8899144;
+parameter val_debug_cpu_cti1__ASICCTL = 32'h00000000;
+parameter mask_debug_cpu_cti1__ASICCTL = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCHINACK = 32'hF8899EDC;
+parameter val_debug_cpu_cti1__ITCHINACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCHINACK = 32'h0000000F;
+
+parameter debug_cpu_cti1__ITTRIGINACK = 32'hF8899EE0;
+parameter val_debug_cpu_cti1__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCHOUT = 32'hF8899EE4;
+parameter val_debug_cpu_cti1__ITCHOUT = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCHOUT = 32'h0000000F;
+
+parameter debug_cpu_cti1__ITTRIGOUT = 32'hF8899EE8;
+parameter val_debug_cpu_cti1__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCHOUTACK = 32'hF8899EEC;
+parameter val_debug_cpu_cti1__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cpu_cti1__ITTRIGOUTACK = 32'hF8899EF0;
+parameter val_debug_cpu_cti1__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCHIN = 32'hF8899EF4;
+parameter val_debug_cpu_cti1__ITCHIN = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCHIN = 32'h0000000F;
+
+parameter debug_cpu_cti1__ITTRIGIN = 32'hF8899EF8;
+parameter val_debug_cpu_cti1__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCTRL = 32'hF8899F00;
+parameter val_debug_cpu_cti1__ITCTRL = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCTRL = 32'h00000001;
+
+parameter debug_cpu_cti1__CTSR = 32'hF8899FA0;
+parameter val_debug_cpu_cti1__CTSR = 32'h0000000F;
+parameter mask_debug_cpu_cti1__CTSR = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTCR = 32'hF8899FA4;
+parameter val_debug_cpu_cti1__CTCR = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTCR = 32'h0000000F;
+
+parameter debug_cpu_cti1__LAR = 32'hF8899FB0;
+parameter val_debug_cpu_cti1__LAR = 32'h00000000;
+parameter mask_debug_cpu_cti1__LAR = 32'hFFFFFFFF;
+
+parameter debug_cpu_cti1__LSR = 32'hF8899FB4;
+parameter val_debug_cpu_cti1__LSR = 32'h00000003;
+parameter mask_debug_cpu_cti1__LSR = 32'h00000007;
+
+parameter debug_cpu_cti1__ASR = 32'hF8899FB8;
+parameter val_debug_cpu_cti1__ASR = 32'h00000005;
+parameter mask_debug_cpu_cti1__ASR = 32'h00000005;
+
+parameter debug_cpu_cti1__DEVID = 32'hF8899FC8;
+parameter val_debug_cpu_cti1__DEVID = 32'h00040800;
+parameter mask_debug_cpu_cti1__DEVID = 32'h000FFFFF;
+
+parameter debug_cpu_cti1__DTIR = 32'hF8899FCC;
+parameter val_debug_cpu_cti1__DTIR = 32'h00000014;
+parameter mask_debug_cpu_cti1__DTIR = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID4 = 32'hF8899FD0;
+parameter val_debug_cpu_cti1__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cpu_cti1__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID5 = 32'hF8899FD4;
+parameter val_debug_cpu_cti1__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cpu_cti1__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID6 = 32'hF8899FD8;
+parameter val_debug_cpu_cti1__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cpu_cti1__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID7 = 32'hF8899FDC;
+parameter val_debug_cpu_cti1__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cpu_cti1__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID0 = 32'hF8899FE0;
+parameter val_debug_cpu_cti1__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cpu_cti1__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID1 = 32'hF8899FE4;
+parameter val_debug_cpu_cti1__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cpu_cti1__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID2 = 32'hF8899FE8;
+parameter val_debug_cpu_cti1__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cpu_cti1__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID3 = 32'hF8899FEC;
+parameter val_debug_cpu_cti1__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cpu_cti1__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cpu_cti1__COMPID0 = 32'hF8899FF0;
+parameter val_debug_cpu_cti1__COMPID0 = 32'h0000000D;
+parameter mask_debug_cpu_cti1__COMPID0 = 32'h000000FF;
+
+parameter debug_cpu_cti1__COMPID1 = 32'hF8899FF4;
+parameter val_debug_cpu_cti1__COMPID1 = 32'h00000090;
+parameter mask_debug_cpu_cti1__COMPID1 = 32'h000000FF;
+
+parameter debug_cpu_cti1__COMPID2 = 32'hF8899FF8;
+parameter val_debug_cpu_cti1__COMPID2 = 32'h00000005;
+parameter mask_debug_cpu_cti1__COMPID2 = 32'h000000FF;
+
+parameter debug_cpu_cti1__COMPID3 = 32'hF8899FFC;
+parameter val_debug_cpu_cti1__COMPID3 = 32'h000000B1;
+parameter mask_debug_cpu_cti1__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cpu_pmu0 cortexa9_pmu
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_pmu0__PMXEVCNTR0 = 32'hF8891000;
+parameter val_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR1 = 32'hF8891004;
+parameter val_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR2 = 32'hF8891008;
+parameter val_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR3 = 32'hF889100C;
+parameter val_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR4 = 32'hF8891010;
+parameter val_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR5 = 32'hF8891014;
+parameter val_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMCCNTR = 32'hF889107C;
+parameter val_debug_cpu_pmu0__PMCCNTR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMCCNTR = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER0 = 32'hF8891400;
+parameter val_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER1 = 32'hF8891404;
+parameter val_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER2 = 32'hF8891408;
+parameter val_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER3 = 32'hF889140C;
+parameter val_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER4 = 32'hF8891410;
+parameter val_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER5 = 32'hF8891414;
+parameter val_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMCNTENSET = 32'hF8891C00;
+parameter val_debug_cpu_pmu0__PMCNTENSET = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMCNTENSET = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMCNTENCLR = 32'hF8891C20;
+parameter val_debug_cpu_pmu0__PMCNTENCLR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMCNTENCLR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMINTENSET = 32'hF8891C40;
+parameter val_debug_cpu_pmu0__PMINTENSET = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMINTENSET = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMINTENCLR = 32'hF8891C60;
+parameter val_debug_cpu_pmu0__PMINTENCLR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMINTENCLR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMOVSR = 32'hF8891C80;
+parameter val_debug_cpu_pmu0__PMOVSR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMOVSR = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMSWINC = 32'hF8891CA0;
+parameter val_debug_cpu_pmu0__PMSWINC = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMSWINC = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMCR = 32'hF8891E04;
+parameter val_debug_cpu_pmu0__PMCR = 32'h41093000;
+parameter mask_debug_cpu_pmu0__PMCR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMUSERENR = 32'hF8891E08;
+parameter val_debug_cpu_pmu0__PMUSERENR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMUSERENR = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module debug_cpu_pmu1 cortexa9_pmu
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_pmu1__PMXEVCNTR0 = 32'hF8893000;
+parameter val_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR1 = 32'hF8893004;
+parameter val_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR2 = 32'hF8893008;
+parameter val_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR3 = 32'hF889300C;
+parameter val_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR4 = 32'hF8893010;
+parameter val_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR5 = 32'hF8893014;
+parameter val_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMCCNTR = 32'hF889307C;
+parameter val_debug_cpu_pmu1__PMCCNTR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMCCNTR = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER0 = 32'hF8893400;
+parameter val_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER1 = 32'hF8893404;
+parameter val_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER2 = 32'hF8893408;
+parameter val_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER3 = 32'hF889340C;
+parameter val_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER4 = 32'hF8893410;
+parameter val_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER5 = 32'hF8893414;
+parameter val_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMCNTENSET = 32'hF8893C00;
+parameter val_debug_cpu_pmu1__PMCNTENSET = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMCNTENSET = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMCNTENCLR = 32'hF8893C20;
+parameter val_debug_cpu_pmu1__PMCNTENCLR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMCNTENCLR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMINTENSET = 32'hF8893C40;
+parameter val_debug_cpu_pmu1__PMINTENSET = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMINTENSET = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMINTENCLR = 32'hF8893C60;
+parameter val_debug_cpu_pmu1__PMINTENCLR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMINTENCLR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMOVSR = 32'hF8893C80;
+parameter val_debug_cpu_pmu1__PMOVSR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMOVSR = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMSWINC = 32'hF8893CA0;
+parameter val_debug_cpu_pmu1__PMSWINC = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMSWINC = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMCR = 32'hF8893E04;
+parameter val_debug_cpu_pmu1__PMCR = 32'h41093000;
+parameter mask_debug_cpu_pmu1__PMCR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMUSERENR = 32'hF8893E08;
+parameter val_debug_cpu_pmu1__PMUSERENR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMUSERENR = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module debug_cpu_ptm0 ptm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_ptm0__ETMCR = 32'hF889C000;
+parameter val_debug_cpu_ptm0__ETMCR = 32'h00000400;
+parameter mask_debug_cpu_ptm0__ETMCR = 32'h3FFFFFFF;
+
+parameter debug_cpu_ptm0__ETMCCR = 32'hF889C004;
+parameter val_debug_cpu_ptm0__ETMCCR = 32'h8D294004;
+parameter mask_debug_cpu_ptm0__ETMCCR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMTRIGGER = 32'hF889C008;
+parameter val_debug_cpu_ptm0__ETMTRIGGER = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMTRIGGER = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSR = 32'hF889C010;
+parameter val_debug_cpu_ptm0__ETMSR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSR = 32'h0000000F;
+
+parameter debug_cpu_ptm0__ETMSCR = 32'hF889C014;
+parameter val_debug_cpu_ptm0__ETMSCR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSCR = 32'h00007FFF;
+
+parameter debug_cpu_ptm0__ETMTSSCR = 32'hF889C018;
+parameter val_debug_cpu_ptm0__ETMTSSCR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMTSSCR = 32'h00FFFFFF;
+
+parameter debug_cpu_ptm0__ETMTECR1 = 32'hF889C024;
+parameter val_debug_cpu_ptm0__ETMTECR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMTECR1 = 32'h03FFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR1 = 32'hF889C040;
+parameter val_debug_cpu_ptm0__ETMACVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR1 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR2 = 32'hF889C044;
+parameter val_debug_cpu_ptm0__ETMACVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR2 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR3 = 32'hF889C048;
+parameter val_debug_cpu_ptm0__ETMACVR3 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR3 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR4 = 32'hF889C04C;
+parameter val_debug_cpu_ptm0__ETMACVR4 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR4 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR5 = 32'hF889C050;
+parameter val_debug_cpu_ptm0__ETMACVR5 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR5 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR6 = 32'hF889C054;
+parameter val_debug_cpu_ptm0__ETMACVR6 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR6 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR7 = 32'hF889C058;
+parameter val_debug_cpu_ptm0__ETMACVR7 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR7 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR8 = 32'hF889C05C;
+parameter val_debug_cpu_ptm0__ETMACVR8 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR8 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACTR1 = 32'hF889C080;
+parameter val_debug_cpu_ptm0__ETMACTR1 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR1 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR2 = 32'hF889C084;
+parameter val_debug_cpu_ptm0__ETMACTR2 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR2 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR3 = 32'hF889C088;
+parameter val_debug_cpu_ptm0__ETMACTR3 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR3 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR4 = 32'hF889C08C;
+parameter val_debug_cpu_ptm0__ETMACTR4 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR4 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR5 = 32'hF889C090;
+parameter val_debug_cpu_ptm0__ETMACTR5 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR5 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR6 = 32'hF889C094;
+parameter val_debug_cpu_ptm0__ETMACTR6 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR6 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR7 = 32'hF889C098;
+parameter val_debug_cpu_ptm0__ETMACTR7 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR7 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR8 = 32'hF889C09C;
+parameter val_debug_cpu_ptm0__ETMACTR8 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR8 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMCNTRLDVR1 = 32'hF889C140;
+parameter val_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTRLDVR2 = 32'hF889C144;
+parameter val_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTENR1 = 32'hF889C150;
+parameter val_debug_cpu_ptm0__ETMCNTENR1 = 32'h00020000;
+parameter mask_debug_cpu_ptm0__ETMCNTENR1 = 32'h0003FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTENR2 = 32'hF889C154;
+parameter val_debug_cpu_ptm0__ETMCNTENR2 = 32'h00020000;
+parameter mask_debug_cpu_ptm0__ETMCNTENR2 = 32'h0003FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'hF889C160;
+parameter val_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'hF889C164;
+parameter val_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTVR1 = 32'hF889C170;
+parameter val_debug_cpu_ptm0__ETMCNTVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTVR1 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTVR2 = 32'hF889C174;
+parameter val_debug_cpu_ptm0__ETMCNTVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTVR2 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ12EVR = 32'hF889C180;
+parameter val_debug_cpu_ptm0__ETMSQ12EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ12EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ21EVR = 32'hF889C184;
+parameter val_debug_cpu_ptm0__ETMSQ21EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ21EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ23EVR = 32'hF889C188;
+parameter val_debug_cpu_ptm0__ETMSQ23EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ23EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ31EVR = 32'hF889C18C;
+parameter val_debug_cpu_ptm0__ETMSQ31EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ31EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ32EVR = 32'hF889C190;
+parameter val_debug_cpu_ptm0__ETMSQ32EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ32EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ13EVR = 32'hF889C194;
+parameter val_debug_cpu_ptm0__ETMSQ13EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ13EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQR = 32'hF889C19C;
+parameter val_debug_cpu_ptm0__ETMSQR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQR = 32'h00000003;
+
+parameter debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'hF889C1A0;
+parameter val_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'hF889C1A4;
+parameter val_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMCIDCVR1 = 32'hF889C1B0;
+parameter val_debug_cpu_ptm0__ETMCIDCVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMC""b""IDCVR1 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMCIDCMR = 32'hF889C1BC;
+parameter val_debug_cpu_ptm0__ETMCIDCMR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCIDCMR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMSYNCFR = 32'hF889C1E0;
+parameter val_debug_cpu_ptm0__ETMSYNCFR = 32'h00000400;
+parameter mask_debug_cpu_ptm0__ETMSYNCFR = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMIDR = 32'hF889C1E4;
+parameter val_debug_cpu_ptm0__ETMIDR = 32'h411CF300;
+parameter mask_debug_cpu_ptm0__ETMIDR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMCCER = 32'hF889C1E8;
+parameter val_debug_cpu_ptm0__ETMCCER = 32'h00C019A2;
+parameter mask_debug_cpu_ptm0__ETMCCER = 32'h03FFFFFF;
+
+parameter debug_cpu_ptm0__ETMEXTINSELR = 32'hF889C1EC;
+parameter val_debug_cpu_ptm0__ETMEXTINSELR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMEXTINSELR = 32'h00003FFF;
+
+parameter debug_cpu_ptm0__ETMAUXCR = 32'hF889C1FC;
+parameter val_debug_cpu_ptm0__ETMAUXCR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMAUXCR = 32'h0000000F;
+
+parameter debug_cpu_ptm0__ETMTRACEIDR = 32'hF889C200;
+parameter val_debug_cpu_ptm0__ETMTRACEIDR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMTRACEIDR = 32'h0000007F;
+
+parameter debug_cpu_ptm0__OSLSR = 32'hF889C304;
+parameter val_debug_cpu_ptm0__OSLSR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__OSLSR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMPDSR = 32'hF889C314;
+parameter val_debug_cpu_ptm0__ETMPDSR = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMPDSR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ITMISCOUT = 32'hF889CEDC;
+parameter val_debug_cpu_ptm0__ITMISCOUT = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITMISCOUT = 32'h000003FF;
+
+parameter debug_cpu_ptm0__ITMISCIN = 32'hF889CEE0;
+parameter val_debug_cpu_ptm0__ITMISCIN = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITMISCIN = 32'h00000020;
+
+parameter debug_cpu_ptm0__ITTRIGGER = 32'hF889CEE8;
+parameter val_debug_cpu_ptm0__ITTRIGGER = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITTRIGGER = 32'h00000001;
+
+parameter debug_cpu_ptm0__ITATBDATA0 = 32'hF889CEEC;
+parameter val_debug_cpu_ptm0__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITATBDATA0 = 32'h0000001F;
+
+parameter debug_cpu_ptm0__ITATBCTR2 = 32'hF889CEF0;
+parameter val_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000;
+
+parameter debug_cpu_ptm0__ITATBID = 32'hF889CEF4;
+parameter val_debug_cpu_ptm0__ITATBID = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITATBID = 32'h0000007F;
+
+parameter debug_cpu_ptm0__ITATBCTR0 = 32'hF889CEF8;
+parameter val_debug_cpu_ptm0__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITATBCTR0 = 32'h000003FF;
+
+parameter debug_cpu_ptm0__ETMITCTRL = 32'hF889CF00;
+parameter val_debug_cpu_ptm0__ETMITCTRL = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMITCTRL = 32'h00000001;
+
+parameter debug_cpu_ptm0__CTSR = 32'hF889CFA0;
+parameter val_debug_cpu_ptm0__CTSR = 32'h000000FF;
+parameter mask_debug_cpu_ptm0__CTSR = 32'h000000FF;
+
+parameter debug_cpu_ptm0__CTCR = 32'hF889CFA4;
+parameter val_debug_cpu_ptm0__CTCR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__CTCR = 32'h000000FF;
+
+parameter debug_cpu_ptm0__LAR = 32'hF889CFB0;
+parameter val_debug_cpu_ptm0__LAR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__LAR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__LSR = 32'hF889CFB4;
+parameter val_debug_cpu_ptm0__LSR = 32'h00000003;
+parameter mask_debug_cpu_ptm0__LSR = 32'h00000007;
+
+parameter debug_cpu_ptm0__ASR = 32'hF889CFB8;
+parameter val_debug_cpu_ptm0__ASR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ASR = 32'h000000F3;
+
+parameter debug_cpu_ptm0__DEVID = 32'hF889CFC8;
+parameter val_debug_cpu_ptm0__DEVID = 32'h00000000;
+parameter mask_debug_cpu_ptm0__DEVID = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__DTIR = 32'hF889CFCC;
+parameter val_debug_cpu_ptm0__DTIR = 32'h00000013;
+parameter mask_debug_cpu_ptm0__DTIR = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID4 = 32'hF889CFD0;
+parameter val_debug_cpu_ptm0__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cpu_ptm0__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID5 = 32'hF889CFD4;
+parameter val_debug_cpu_ptm0__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID6 = 32'hF889CFD8;
+parameter val_debug_cpu_ptm0__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID7 = 32'hF889CFDC;
+parameter val_debug_cpu_ptm0__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID0 = 32'hF889CFE0;
+parameter val_debug_cpu_ptm0__PERIPHID0 = 32'h00000050;
+parameter mask_debug_cpu_ptm0__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID1 = 32'hF889CFE4;
+parameter val_debug_cpu_ptm0__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cpu_ptm0__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID2 = 32'hF889CFE8;
+parameter val_debug_cpu_ptm0__PERIPHID2 = 32'h0000001B;
+parameter mask_debug_cpu_ptm0__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID3 = 32'hF889CFEC;
+parameter val_debug_cpu_ptm0__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__COMPID0 = 32'hF889CFF0;
+parameter val_debug_cpu_ptm0__COMPID0 = 32'h0000000D;
+parameter mask_debug_cpu_ptm0__COMPID0 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__COMPID1 = 32'hF889CFF4;
+parameter val_debug_cpu_ptm0__COMPID1 = 32'h00000090;
+parameter mask_debug_cpu_ptm0__COMPID1 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__COMPID2 = 32'hF889CFF8;
+parameter val_debug_cpu_ptm0__COMPID2 = 32'h00000005;
+parameter mask_debug_cpu_ptm0__COMPID2 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__COMPID3 = 32'hF889CFFC;
+parameter val_debug_cpu_ptm0__COMPID3 = 32'h000000B1;
+parameter mask_debug_cpu_ptm0__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cpu_ptm1 ptm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_ptm1__ETMCR = 32'hF889D000;
+parameter val_debug_cpu_ptm1__ETMCR = 32'h00000400;
+parameter mask_debug_cpu_ptm1__ETMCR = 32'h3FFFFFFF;
+
+parameter debug_cpu_ptm1__ETMCCR = 32'hF889D004;
+parameter val_debug_cpu_ptm1__ETMCCR = 32'h8D294004;
+parameter mask_debug_cpu_ptm1__ETMCCR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMTRIGGER = 32'hF889D008;
+parameter val_debug_cpu_ptm1__ETMTRIGGER = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMTRIGGER = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSR = 32'hF889D010;
+parameter val_debug_cpu_ptm1__ETMSR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSR = 32'h0000000F;
+
+parameter debug_cpu_ptm1__ETMSCR = 32'hF889D014;
+parameter val_debug_cpu_ptm1__ETMSCR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSCR = 32'h00007FFF;
+
+parameter debug_cpu_ptm1__ETMTSSCR = 32'hF889D018;
+parameter val_debug_cpu_ptm1__ETMTSSCR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMTSSCR = 32'h00FFFFFF;
+
+parameter debug_cpu_ptm1__ETMTECR1 = 32'hF889D024;
+parameter val_debug_cpu_ptm1__ETMTECR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMTECR1 = 32'h03FFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR1 = 32'hF889D040;
+parameter val_debug_cpu_ptm1__ETMACVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR1 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR2 = 32'hF889D044;
+parameter val_debug_cpu_ptm1__ETMACVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR2 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR3 = 32'hF889D048;
+parameter val_debug_cpu_ptm1__ETMACVR3 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR3 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR4 = 32'hF889D04C;
+parameter val_debug_cpu_ptm1__ETMACVR4 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR4 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR5 = 32'hF889D050;
+parameter val_debug_cpu_ptm1__ETMACVR5 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR5 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR6 = 32'hF889D054;
+parameter val_debug_cpu_ptm1__ETMACVR6 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR6 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR7 = 32'hF889D058;
+parameter val_debug_cpu_ptm1__ETMACVR7 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR7 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR8 = 32'hF889D05C;
+parameter val_debug_cpu_ptm1__ETMACVR8 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR8 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACTR1 = 32'hF889D080;
+parameter val_debug_cpu_ptm1__ETMACTR1 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR1 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR2 = 32'hF889D084;
+parameter val_debug_cpu_ptm1__ETMACTR2 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR2 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR3 = 32'hF889D088;
+parameter val_debug_cpu_ptm1__ETMACTR3 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR3 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR4 = 32'hF889D08C;
+parameter val_debug_cpu_ptm1__ETMACTR4 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR4 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR5 = 32'hF889D090;
+parameter val_debug_cpu_ptm1__ETMACTR5 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR5 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR6 = 32'hF889D094;
+parameter val_debug_cpu_ptm1__ETMACTR6 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR6 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR7 = 32'hF889D098;
+parameter val_debug_cpu_ptm1__ETMACTR7 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR7 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR8 = 32'hF889D09C;
+parameter val_debug_cpu_ptm1__ETMACTR8 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR8 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMCNTRLDVR1 = 32'hF889D140;
+parameter val_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTRLDVR2 = 32'hF889D144;
+parameter val_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTENR1 = 32'hF889D150;
+parameter val_debug_cpu_ptm1__ETMCNTENR1 = 32'h00020000;
+parameter mask_debug_cpu_ptm1__ETMCNTENR1 = 32'h0003FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTENR2 = 32'hF889D154;
+parameter val_debug_cpu_ptm1__ETMCNTENR2 = 32'h00020000;
+parameter mask_debug_cpu_ptm1__ETMCNTENR2 = 32'h0003FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'hF889D160;
+parameter val_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'hF889D164;
+parameter val_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTVR1 = 32'hF889D170;
+parameter val_debug_cpu_ptm1__ETMCNTVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTVR1 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTVR2 = 32'hF889D174;
+parameter val_debug_cpu_ptm1__ETMCNTVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTVR2 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ12EVR = 32'hF889D180;
+parameter val_debug_cpu_ptm1__ETMSQ12EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ12EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ21EVR = 32'hF889D184;
+parameter val_debug_cpu_ptm1__ETMSQ21EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ21EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ23EVR = 32'hF889D188;
+parameter val_debug_cpu_ptm1__ETMSQ23EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ23EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ31EVR = 32'hF889D18C;
+parameter val_debug_cpu_ptm1__ETMSQ31EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ31EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ32EVR = 32'hF889D190;
+parameter val_debug_cpu_ptm1__ETMSQ32EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ32EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ13EVR = 32'hF889D194;
+parameter val_debug_cpu_ptm1__ETMSQ13EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ13EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQR = 32'hF889D19C;
+parameter val_debug_cpu_ptm1__ETMSQR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQR = 32'h00000003;
+
+parameter debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'hF889D1A0;
+parameter val_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'hF889D1A4;
+parameter val_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMCIDCVR1 = 32'hF889D1B0;
+parameter val_debug_cpu_ptm1__ETMCIDCVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCIDCVR1 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMCIDCMR = 32'hF889D1BC;
+parameter val_debug_cpu_ptm1__ETMCIDCMR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCIDCMR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMSYNCFR = 32'hF889D1E0;
+parameter val_debug_cpu_ptm1__ETMSYNCFR = 32'h00000400;
+parameter mask_debug_cpu_ptm1__ETMSYNCFR = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMIDR = 32'hF889D1E4;
+parameter val_debug_cpu_ptm1__ETMIDR = 32'h411CF300;
+parameter mask_debug_cpu_ptm1__ETMIDR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMCCER = 32'hF889D1E8;
+parameter val_debug_cpu_ptm1__ETMCCER = 32'h00C019A2;
+parameter mask_debug_cpu_ptm1__ETMCCER = 32'h03FFFFFF;
+
+parameter debug_cpu_ptm1__ETMEXTINSELR = 32'hF889D1EC;
+parameter val_debug_cpu_ptm1__ETMEXTINSELR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMEXTINSELR = 32'h00003FFF;
+
+parameter debug_cpu_ptm1__ETMAUXCR = 32'hF889D1FC;
+parameter val_debug_cpu_ptm1__ETMAUXCR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMAUXCR = 32'h0000000F;
+
+parameter debug_cpu_ptm1__ETMTRACEIDR = 32'hF889D200;
+parameter val_debug_cpu_ptm1__ETMTRACEIDR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMTRACEIDR = 32'h0000007F;
+
+parameter debug_cpu_ptm1__OSLSR = 32'hF889D304;
+parameter val_debug_cpu_ptm1__OSLSR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__OSLSR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMPDSR = 32'hF889D314;
+parameter val_debug_cpu_ptm1__ETMPDSR = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMPDSR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ITMISCOUT = 32'hF889DEDC;
+parameter val_debug_cpu_ptm1__ITMISCOUT = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITMISCOUT = 32'h000003FF;
+
+parameter debug_cpu_ptm1__ITMISCIN = 32'hF889DEE0;
+parameter val_debug_cpu_ptm1__ITMISCIN = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITMISCIN = 32'h00000020;
+
+parameter debug_cpu_ptm1__ITTRIGGER = 32'hF889DEE8;
+parameter val_debug_cpu_ptm1__ITTRIGGER = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITTRIGGER = 32'h00000001;
+
+parameter debug_cpu_ptm1__ITATBDATA0 = 32'hF889DEEC;
+parameter val_debug_cpu_ptm1__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITATBDATA0 = 32'h0000001F;
+
+parameter debug_cpu_ptm1__ITATBCTR2 = 32'hF889DEF0;
+parameter val_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000;
+
+parameter debug_cpu_ptm1__ITATBID = 32'hF889DEF4;
+parameter val_debug_cpu_ptm1__ITATBID = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITATBID = 32'h0000007F;
+
+parameter debug_cpu_ptm1__ITATBCTR0 = 32'hF889DEF8;
+parameter val_debug_cpu_ptm1__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITATBCTR0 = 32'h000003FF;
+
+parameter debug_cpu_ptm1__ETMITCTRL = 32'hF889DF00;
+parameter val_debug_cpu_ptm1__ETMITCTRL = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMITCTRL = 32'h00000001;
+
+parameter debug_cpu_ptm1__CTSR = 32'hF889DFA0;
+parameter val_debug_cpu_ptm1__CTSR = 32'h000000FF;
+parameter mask_debug_cpu_ptm1__CTSR = 32'h000000FF;
+
+parameter debug_cpu_ptm1__CTCR = 32'hF889DFA4;
+parameter val_debug_cpu_ptm1__CTCR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__CTCR = 32'h000000FF;
+
+parameter debug_cpu_ptm1__LAR = 32'hF889DFB0;
+parameter val_debug_cpu_ptm1__LAR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__LAR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__LSR = 32'hF889DFB4;
+parameter val_debug_cpu_ptm1__LSR = 32'h00000003;
+parameter mask_debug_cpu_ptm1__LSR = 32'h00000007;
+
+parameter debug_cpu_ptm1__ASR = 32'hF889DFB8;
+parameter val_debug_cpu_ptm1__ASR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ASR = 32'h000000F3;
+
+parameter debug_cpu_ptm1__DEVID = 32'hF889DFC8;
+parameter val_debug_cpu_ptm1__DEVID = 32'h00000000;
+parameter mask_debug_cpu_ptm1__DEVID = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__DTIR = 32'hF889DFCC;
+parameter val_debug_cpu_ptm1__DTIR = 32'h00000013;
+parameter mask_debug_cpu_ptm1__DTIR = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID4 = 32'hF889DFD0;
+parameter val_debug_cpu_ptm1__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cpu_ptm1__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID5 = 32'hF889DFD4;
+parameter val_debug_cpu_ptm1__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID6 = 32'hF889DFD8;
+parameter val_debug_cpu_ptm1__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID7 = 32'hF889DFDC;
+parameter val_debug_cpu_ptm1__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID0 = 32'hF889DFE0;
+parameter val_debug_cpu_ptm1__PERIPHID0 = 32'h00000050;
+parameter mask_debug_cpu_ptm1__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID1 = 32'hF889DFE4;
+parameter val_debug_cpu_ptm1__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cpu_ptm1__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID2 = 32'hF889DFE8;
+parameter val_debug_cpu_ptm1__PERIPHID2 = 32'h0000001B;
+parameter mask_debug_cpu_ptm1__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID3 = 32'hF889DFEC;
+parameter val_debug_cpu_ptm1__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__COMPID0 = 32'hF889DFF0;
+parameter val_debug_cpu_ptm1__COMPID0 = 32'h0000000D;
+parameter mask_debug_cpu_ptm1__COMPID0 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__COMPID1 = 32'hF889DFF4;
+parameter val_debug_cpu_ptm1__COMPID1 = 32'h00000090;
+parameter mask_debug_cpu_ptm1__COMPID1 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__COMPID2 = 32'hF889DFF8;
+parameter val_debug_cpu_ptm1__COMPID2 = 32'h00000005;
+parameter mask_debug_cpu_ptm1__COMPID2 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__COMPID3 = 32'hF889DFFC;
+parameter val_debug_cpu_ptm1__COMPID3 = 32'h000000B1;
+parameter mask_debug_cpu_ptm1__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cti_axim cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cti_axim__CTICONTROL = 32'hF880A000;
+parameter val_debug_cti_axim__CTICONTROL = 32'h00000000;
+parameter mask_debug_cti_axim__CTICONTROL = 32'h00000001;
+
+parameter debug_cti_axim__CTIINTACK = 32'hF880A010;
+parameter val_debug_cti_axim__CTIINTACK = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINTACK = 32'h000000FF;
+
+parameter debug_cti_axim__CTIAPPSET = 32'hF880A014;
+parameter val_debug_cti_axim__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cti_axim__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cti_axim__CTIAPPCLEAR = 32'hF880A018;
+parameter val_debug_cti_axim__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cti_axim__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cti_axim__CTIAPPPULSE = 32'hF880A01C;
+parameter val_debug_cti_axim__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cti_axim__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN0 = 32'hF880A020;
+parameter val_debug_cti_axim__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN1 = 32'hF880A024;
+parameter val_debug_cti_axim__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN2 = 32'hF880A028;
+parameter val_debug_cti_axim__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN3 = 32'hF880A02C;
+parameter val_debug_cti_axim__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN4 = 32'hF880A030;
+parameter val_debug_cti_axim__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN5 = 32'hF880A034;
+parameter val_debug_cti_axim__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN6 = 32'hF880A038;
+parameter val_debug_cti_axim__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN7 = 32'hF880A03C;
+parameter val_debug_cti_axim__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN0 = 32'hF880A0A0;
+parameter val_debug_cti_axim__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN1 = 32'hF880A0A4;
+parameter val_debug_cti_axim__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN2 = 32'hF880A0A8;
+parameter val_debug_cti_axim__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN3 = 32'hF880A0AC;
+parameter val_debug_cti_axim__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN4 = 32'hF880A0B0;
+parameter val_debug_cti_axim__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN5 = 32'hF880A0B4;
+parameter val_debug_cti_axim__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN6 = 32'hF880A0B8;
+parameter val_debug_cti_axim__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN7 = 32'hF880A0BC;
+parameter val_debug_cti_axim__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cti_axim__CTITRIGINSTATUS = 32'hF880A130;
+parameter val_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cti_axim__CTITRIGOUTSTATUS = 32'hF880A134;
+parameter val_debug_cti_axim__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_axim__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cti_axim__CTICHINSTATUS = 32'hF880A138;
+parameter val_debug_cti_axim__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cti_axim__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cti_axim__CTICHOUTSTATUS = 32'hF880A13C;
+parameter val_debug_cti_axim__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_axim__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cti_axim__CTIGATE = 32'hF880A140;
+parameter val_debug_cti_axim__CTIGATE = 32'h0000000F;
+parameter mask_debug_cti_axim__CTIGATE = 32'h0000000F;
+
+parameter debug_cti_axim__ASICCTL = 32'hF880A144;
+parameter val_debug_cti_axim__ASICCTL = 32'h00000000;
+parameter mask_debug_cti_axim__ASICCTL = 32'h000000FF;
+
+parameter debug_cti_axim__ITCHINACK = 32'hF880AEDC;
+parameter val_debug_cti_axim__ITCHINACK = 32'h00000000;
+parameter mask_debug_cti_axim__ITCHINACK = 32'h0000000F;
+
+parameter debug_cti_axim__ITTRIGINACK = 32'hF880AEE0;
+parameter val_debug_cti_axim__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cti_axim__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cti_axim__ITCHOUT = 32'hF880AEE4;
+parameter val_debug_cti_axim__ITCHOUT = 32'h00000000;
+parameter mask_debug_cti_axim__ITCHOUT = 32'h0000000F;
+
+parameter debug_cti_axim__ITTRIGOUT = 32'hF880AEE8;
+parameter val_debug_cti_axim__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cti_axim__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cti_axim__ITCHOUTACK = 32'hF880AEEC;
+parameter val_debug_cti_axim__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cti_axim__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cti_axim__ITTRIGOUTACK = 32'hF880AEF0;
+parameter val_debug_cti_axim__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cti_axim__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cti_axim__ITCHIN = 32'hF880AEF4;
+parameter val_debug_cti_axim__ITCHIN = 32'h00000000;
+parameter mask_debug_cti_axim__ITCHIN = 32'h0000000F;
+
+parameter debug_cti_axim__ITTRIGIN = 32'hF880AEF8;
+parameter val_debug_cti_axim__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cti_axim__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cti_axim__ITCTRL = 32'hF880AF00;
+parameter val_debug_cti_axim__ITCTRL = 32'h00000000;
+parameter mask_debug_cti_axim__ITCTRL = 32'h00000001;
+
+parameter debug_cti_axim__CTSR = 32'hF880AFA0;
+parameter val_debug_cti_axim__CTSR = 32'h0000000F;
+parameter mask_debug_cti_axim__CTSR = 32'h0000000F;
+
+parameter debug_cti_axim__CTCR = 32'hF880AFA4;
+parameter val_debug_cti_axim__CTCR = 32'h00000000;
+parameter mask_debug_cti_axim__CTCR = 32'h0000000F;
+
+parameter debug_cti_axim__LAR = 32'hF880AFB0;
+parameter val_debug_cti_axim__LAR = 32'h00000000;
+parameter mask_debug_cti_axim__LAR = 32'hFFFFFFFF;
+
+parameter debug_cti_axim__LSR = 32'hF880AFB4;
+parameter val_debug_cti_axim__LSR = 32'h00000003;
+parameter mask_debug_cti_axim__LSR = 32'h00000007;
+
+parameter debug_cti_axim__ASR = 32'hF880AFB8;
+parameter val_debug_cti_axim__ASR = 32'h00000005;
+parameter mask_debug_cti_axim__ASR = 32'h00000005;
+
+parameter debug_cti_axim__DEVID = 32'hF880AFC8;
+parameter val_debug_cti_axim__DEVID = 32'h00040800;
+parameter mask_debug_cti_axim__DEVID = 32'h000FFFFF;
+
+parameter debug_cti_axim__DTIR = 32'hF880AFCC;
+parameter val_debug_cti_axim__DTIR = 32'h00000014;
+parameter mask_debug_cti_axim__DTIR = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID4 = 32'hF880AFD0;
+parameter val_debug_cti_axim__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cti_axim__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID5 = 32'hF880AFD4;
+parameter val_debug_cti_axim__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cti_axim__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID6 = 32'hF880AFD8;
+parameter val_debug_cti_axim__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cti_axim__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID7 = 32'hF880AFDC;
+parameter val_debug_cti_axim__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cti_axim__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID0 = 32'hF880AFE0;
+parameter val_debug_cti_axim__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cti_axim__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID1 = 32'hF880AFE4;
+parameter val_debug_cti_axim__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cti_axim__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID2 = 32'hF880AFE8;
+parameter val_debug_cti_axim__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cti_axim__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID3 = 32'hF880AFEC;
+parameter val_debug_cti_axim__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cti_axim__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cti_axim__COMPID0 = 32'hF880AFF0;
+parameter val_debug_cti_axim__COMPID0 = 32'h0000000D;
+parameter mask_debug_cti_axim__COMPID0 = 32'h000000FF;
+
+parameter debug_cti_axim__COMPID1 = 32'hF880AFF4;
+parameter val_debug_cti_axim__COMPID1 = 32'h00000090;
+parameter mask_debug_cti_axim__COMPID1 = 32'h000000FF;
+
+parameter debug_cti_axim__COMPID2 = 32'hF880AFF8;
+parameter val_debug_cti_axim__COMPID2 = 32'h00000005;
+parameter mask_debug_cti_axim__COMPID2 = 32'h000000FF;
+
+parameter debug_cti_axim__COMPID3 = 32'hF880AFFC;
+parameter val_debug_cti_axim__COMPID3 = 32'h000000B1;
+parameter mask_debug_cti_axim__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cti_etb_tpiu cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cti_etb_tpiu__CTICONTROL = 32'hF8802000;
+parameter val_debug_cti_etb_tpiu__CTICONTROL = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTICONTROL = 32'h00000001;
+
+parameter debug_cti_etb_tpiu__CTIINTACK = 32'hF8802010;
+parameter val_debug_cti_etb_tpiu__CTIINTACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINTACK = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__CTIAPPSET = 32'hF8802014;
+parameter val_debug_cti_etb_tpiu__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIAPPCLEAR = 32'hF8802018;
+parameter val_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIAPPPULSE = 32'hF880201C;
+parameter val_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN0 = 32'hF8802020;
+parameter val_debug_cti_etb_tpiu__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN1 = 32'hF8802024;
+parameter val_debug_cti_etb_tpiu__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN2 = 32'hF8802028;
+parameter val_debug_cti_etb_tpiu__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN3 = 32'hF880202C;
+parameter val_debug_cti_etb_tpiu__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN4 = 32'hF8802030;
+parameter val_debug_cti_etb_tpiu__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN5 = 32'hF8802034;
+parameter val_debug_cti_etb_tpiu__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN6 = 32'hF8802038;
+parameter val_debug_cti_etb_tpiu__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN7 = 32'hF880203C;
+parameter val_debug_cti_etb_tpiu__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN0 = 32'hF88020A0;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN1 = 32'hF88020A4;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN2 = 32'hF88020A8;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN3 = 32'hF88020AC;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN4 = 32'hF88020B0;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN5 = 32'hF88020B4;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN6 = 32'hF88020B8;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN7 = 32'hF88020BC;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'hF8802130;
+parameter val_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'hF8802134;
+parameter val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__CTICHINSTATUS = 32'hF8802138;
+parameter val_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'hF880213C;
+parameter val_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIGATE = 32'hF8802140;
+parameter val_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F;
+parameter mask_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ASICCTL = 32'hF8802144;
+parameter val_debug_cti_etb_tpiu__ASICCTL = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ASICCTL = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCHINACK = 32'hF8802EDC;
+parameter val_debug_cti_etb_tpiu__ITCHINACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCHINACK = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ITTRIGINACK = 32'hF8802EE0;
+parameter val_debug_cti_etb_tpiu__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCHOUT = 32'hF8802EE4;
+parameter val_debug_cti_etb_tpiu__ITCHOUT = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCHOUT = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ITTRIGOUT = 32'hF8802EE8;
+parameter val_debug_cti_etb_tpiu__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCHOUTACK = 32'hF8802EEC;
+parameter val_debug_cti_etb_tpiu__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ITTRIGOUTACK = 32'hF8802EF0;
+parameter val_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCHIN = 32'hF8802EF4;
+parameter val_debug_cti_etb_tpiu__ITCHIN = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCHIN = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ITTRIGIN = 32'hF8802EF8;
+parameter val_debug_cti_etb_tpiu__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCTRL = 32'hF8802F00;
+parameter val_debug_cti_etb_tpiu__ITCTRL = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCTRL = 32'h00000001;
+
+parameter debug_cti_etb_tpiu__CTSR = 32'hF8802FA0;
+parameter val_debug_cti_etb_tpiu__CTSR = 32'h0000000F;
+parameter mask_debug_cti_etb_tpiu__CTSR = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTCR = 32'hF8802FA4;
+parameter val_debug_cti_etb_tpiu__CTCR = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTCR = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__LAR = 32'hF8802FB0;
+parameter val_debug_cti_etb_tpiu__LAR = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__LAR = 32'hFFFFFFFF;
+
+parameter debug_cti_etb_tpiu__LSR = 32'hF8802FB4;
+parameter val_debug_cti_etb_tpiu__LSR = 32'h00000003;
+parameter mask_debug_cti_etb_tpiu__LSR = 32'h00000007;
+
+parameter debug_cti_etb_tpiu__ASR = 32'hF8802FB8;
+parameter val_debug_cti_etb_tpiu__ASR = 32'h00000005;
+parameter mask_debug_cti_etb_tpiu__ASR = 32'h00000005;
+
+parameter debug_cti_etb_tpiu__DEVID = 32'hF8802FC8;
+parameter val_debug_cti_etb_tpiu__DEVID = 32'h00040800;
+parameter mask_debug_cti_etb_tpiu__DEVID = 32'h000FFFFF;
+
+parameter debug_cti_etb_tpiu__DTIR = 32'hF8802FCC;
+parameter val_debug_cti_etb_tpiu__DTIR = 32'h00000014;
+parameter mask_debug_cti_etb_tpiu__DTIR = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID4 = 32'hF8802FD0;
+parameter val_debug_cti_etb_tpiu__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cti_etb_tpiu__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID5 = 32'hF8802FD4;
+parameter val_debug_cti_etb_tpiu__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID6 = 32'hF8802FD8;
+parameter val_debug_cti_etb_tpiu__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID7 = 32'hF8802FDC;
+parameter val_debug_cti_etb_tpiu__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID0 = 32'hF8802FE0;
+parameter val_debug_cti_etb_tpiu__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cti_etb_tpiu__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID1 = 32'hF8802FE4;
+parameter val_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID2 = 32'hF8802FE8;
+parameter val_debug_cti_etb_tpiu__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cti_etb_tpiu__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID3 = 32'hF8802FEC;
+parameter val_debug_cti_etb_tpiu__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__COMPID0 = 32'hF8802FF0;
+parameter val_debug_cti_etb_tpiu__COMPID0 = 32'h0000000D;
+parameter mask_debug_cti_etb_tpiu__COMPID0 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__COMPID1 = 32'hF8802FF4;
+parameter val_debug_cti_etb_tpiu__COMPID1 = 32'h00000090;
+parameter mask_debug_cti_etb_tpiu__COMPID1 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__COMPID2 = 32'hF8802FF8;
+parameter val_debug_cti_etb_tpiu__COMPID2 = 32'h00000005;
+parameter mask_debug_cti_etb_tpiu__COMPID2 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__COMPID3 = 32'hF8802FFC;
+parameter val_debug_cti_etb_tpiu__COMPID3 = 32'h000000B1;
+parameter mask_debug_cti_etb_tpiu__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cti_ftm cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cti_ftm__CTICONTROL = 32'hF8809000;
+parameter val_debug_cti_ftm__CTICONTROL = 32'h00000000;
+parameter mask_debug_cti_ftm__CTICONTROL = 32'h00000001;
+
+parameter debug_cti_ftm__CTIINTACK = 32'hF8809010;
+parameter val_debug_cti_ftm__CTIINTACK = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINTACK = 32'h000000FF;
+
+parameter debug_cti_ftm__CTIAPPSET = 32'hF8809014;
+parameter val_debug_cti_ftm__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIAPPCLEAR = 32'hF8809018;
+parameter val_debug_cti_ftm__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIAPPPULSE = 32'hF880901C;
+parameter val_debug_cti_ftm__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN0 = 32'hF8809020;
+parameter val_debug_cti_ftm__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN1 = 32'hF8809024;
+parameter val_debug_cti_ftm__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN2 = 32'hF8809028;
+parameter val_debug_cti_ftm__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN3 = 32'hF880902C;
+parameter val_debug_cti_ftm__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN4 = 32'hF8809030;
+parameter val_debug_cti_ftm__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN5 = 32'hF8809034;
+parameter val_debug_cti_ftm__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN6 = 32'hF8809038;
+parameter val_debug_cti_ftm__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN7 = 32'hF880903C;
+parameter val_debug_cti_ftm__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN0 = 32'hF88090A0;
+parameter val_debug_cti_ftm__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN1 = 32'hF88090A4;
+parameter val_debug_cti_ftm__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN2 = 32'hF88090A8;
+parameter val_debug_cti_ftm__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN3 = 32'hF88090AC;
+parameter val_debug_cti_ftm__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN4 = 32'hF88090B0;
+parameter val_debug_cti_ftm__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN5 = 32'hF88090B4;
+parameter val_debug_cti_ftm__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN6 = 32'hF88090B8;
+parameter val_debug_cti_ftm__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN7 = 32'hF88090BC;
+parameter val_debug_cti_ftm__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTITRIGINSTATUS = 32'hF8809130;
+parameter val_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cti_ftm__CTITRIGOUTSTATUS = 32'hF8809134;
+parameter val_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cti_ftm__CTICHINSTATUS = 32'hF8809138;
+parameter val_debug_cti_ftm__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cti_ftm__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cti_ftm__CTICHOUTSTATUS = 32'hF880913C;
+parameter val_debug_cti_ftm__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_ftm__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIGATE = 32'hF8809140;
+parameter val_debug_cti_ftm__CTIGATE = 32'h0000000F;
+parameter mask_debug_cti_ftm__CTIGATE = 32'h0000000F;
+
+parameter debug_cti_ftm__ASICCTL = 32'hF8809144;
+parameter val_debug_cti_ftm__ASICCTL = 32'h00000000;
+parameter mask_debug_cti_ftm__ASICCTL = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCHINACK = 32'hF8809EDC;
+parameter val_debug_cti_ftm__ITCHINACK = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCHINACK = 32'h0000000F;
+
+parameter debug_cti_ftm__ITTRIGINACK = 32'hF8809EE0;
+parameter val_debug_cti_ftm__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cti_ftm__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCHOUT = 32'hF8809EE4;
+parameter val_debug_cti_ftm__ITCHOUT = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCHOUT = 32'h0000000F;
+
+parameter debug_cti_ftm__ITTRIGOUT = 32'hF8809EE8;
+parameter val_debug_cti_ftm__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cti_ftm__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCHOUTACK = 32'hF8809EEC;
+parameter val_debug_cti_ftm__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cti_ftm__ITTRIGOUTACK = 32'hF8809EF0;
+parameter val_debug_cti_ftm__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cti_ftm__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCHIN = 32'hF8809EF4;
+parameter val_debug_cti_ftm__ITCHIN = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCHIN = 32'h0000000F;
+
+parameter debug_cti_ftm__ITTRIGIN = 32'hF8809EF8;
+parameter val_debug_cti_ftm__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cti_ftm__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCTRL = 32'hF8809F00;
+parameter val_debug_cti_ftm__ITCTRL = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCTRL = 32'h00000001;
+
+parameter debug_cti_ftm__CTSR = 32'hF8809FA0;
+parameter val_debug_cti_ftm__CTSR = 32'h0000000F;
+parameter mask_debug_cti_ftm__CTSR = 32'h0000000F;
+
+parameter debug_cti_ftm__CTCR = 32'hF8809FA4;
+parameter val_debug_cti_ftm__CTCR = 32'h00000000;
+parameter mask_debug_cti_ftm__CTCR = 32'h0000000F;
+
+parameter debug_cti_ftm__LAR = 32'hF8809FB0;
+parameter val_debug_cti_ftm__LAR = 32'h00000000;
+parameter mask_debug_cti_ftm__LAR = 32'hFFFFFFFF;
+
+parameter debug_cti_ftm__LSR = 32'hF8809FB4;
+parameter val_debug_cti_ftm__LSR = 32'h00000003;
+parameter mask_debug_cti_ftm__LSR = 32'h00000007;
+
+parameter debug_cti_ftm__ASR = 32'hF8809FB8;
+parameter val_debug_cti_ftm__ASR = 32'h00000005;
+parameter mask_debug_cti_ftm__ASR = 32'h00000005;
+
+parameter debug_cti_ftm__DEVID = 32'hF8809FC8;
+parameter val_debug_cti_ftm__DEVID = 32'h00040800;
+parameter mask_debug_cti_ftm__DEVID = 32'h000FFFFF;
+
+parameter debug_cti_ftm__DTIR = 32'hF8809FCC;
+parameter val_debug_cti_ftm__DTIR = 32'h00000014;
+parameter mask_debug_cti_ftm__DTIR = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID4 = 32'hF8809FD0;
+parameter val_debug_cti_ftm__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cti_ftm__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID5 = 32'hF8809FD4;
+parameter val_debug_cti_ftm__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cti_ftm__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID6 = 32'hF8809FD8;
+parameter val_debug_cti_ftm__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cti_ftm__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID7 = 32'hF8809FDC;
+parameter val_debug_cti_ftm__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cti_ftm__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID0 = 32'hF8809FE0;
+parameter val_debug_cti_ftm__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cti_ftm__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID1 = 32'hF8809FE4;
+parameter val_debug_cti_ftm__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cti_ftm__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID2 = 32'hF8809FE8;
+parameter val_debug_cti_ftm__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cti_ftm__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID3 = 32'hF8809FEC;
+parameter val_debug_cti_ftm__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cti_ftm__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cti_ftm__COMPID0 = 32'hF8809FF0;
+parameter val_debug_cti_ftm__COMPID0 = 32'h0000000D;
+parameter mask_debug_cti_ftm__COMPID0 = 32'h000000FF;
+
+parameter debug_cti_ftm__COMPID1 = 32'hF8809FF4;
+parameter val_debug_cti_ftm__COMPID1 = 32'h00000090;
+parameter mask_debug_cti_ftm__COMPID1 = 32'h000000FF;
+
+parameter debug_cti_ftm__COMPID2 = 32'hF8809FF8;
+parameter val_debug_cti_ftm__COMPID2 = 32'h00000005;
+parameter mask_debug_cti_ftm__COMPID2 = 32'h000000FF;
+
+parameter debug_cti_ftm__COMPID3 = 32'hF8809FFC;
+parameter val_debug_cti_ftm__COMPID3 = 32'h000000B1;
+parameter mask_debug_cti_ftm__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_dap_rom dap
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_dap_rom__ROMENTRY00 = 32'hF8800000;
+parameter val_debug_dap_rom__ROMENTRY00 = 32'h00001003;
+parameter mask_debug_dap_rom__ROMENTRY00 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY01 = 32'hF8800004;
+parameter val_debug_dap_rom__ROMENTRY01 = 32'h00002003;
+parameter mask_debug_dap_rom__ROMENTRY01 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY02 = 32'hF8800008;
+parameter val_debug_dap_rom__ROMENTRY02 = 32'h00003003;
+parameter mask_debug_dap_rom__ROMENTRY02 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY03 = 32'hF880000C;
+parameter val_debug_dap_rom__ROMENTRY03 = 32'h00004003;
+parameter mask_debug_dap_rom__ROMENTRY03 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY04 = 32'hF8800010;
+parameter val_debug_dap_rom__ROMENTRY04 = 32'h00005003;
+parameter mask_debug_dap_rom__ROMENTRY04 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY05 = 32'hF8800014;
+parameter val_debug_dap_rom__ROMENTRY05 = 32'h00009003;
+parameter mask_debug_dap_rom__ROMENTRY05 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY06 = 32'hF8800018;
+parameter val_debug_dap_rom__ROMENTRY06 = 32'h0000A003;
+parameter mask_debug_dap_rom__ROMENTRY06 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY07 = 32'hF880001C;
+parameter val_debug_dap_rom__ROMENTRY07 = 32'h0000B003;
+parameter mask_debug_dap_rom__ROMENTRY07 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY08 = 32'hF8800020;
+parameter val_debug_dap_rom__ROMENTRY08 = 32'h0000C003;
+parameter mask_debug_dap_rom__ROMENTRY08 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY09 = 32'hF8800024;
+parameter val_debug_dap_rom__ROMENTRY09 = 32'h00080003;
+parameter mask_debug_dap_rom__ROMENTRY09 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY10 = 32'hF8800028;
+parameter val_debug_dap_rom__ROMENTRY10 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY10 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY11 = 32'hF880002C;
+parameter val_debug_dap_rom__ROMENTRY11 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY11 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY12 = 32'hF8800030;
+parameter val_debug_dap_rom__ROMENTRY12 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY12 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY13 = 32'hF8800034;
+parameter val_debug_dap_rom__ROMENTRY13 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY13 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY14 = 32'hF8800038;
+parameter val_debug_dap_rom__ROMENTRY14 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY14 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY15 = 32'hF880003C;
+parameter val_debug_dap_rom__ROMENTRY15 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY15 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__PERIPHID4 = 32'hF8800FD0;
+parameter val_debug_dap_rom__PERIPHID4 = 32'h00000003;
+parameter mask_debug_dap_rom__PERIPHID4 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID5 = 32'hF8800FD4;
+parameter val_debug_dap_rom__PERIPHID5 = 32'h00000000;
+parameter mask_debug_dap_rom__PERIPHID5 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID6 = 32'hF8800FD8;
+parameter val_debug_dap_rom__PERIPHID6 = 32'h00000000;
+parameter mask_debug_dap_rom__PERIPHID6 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID7 = 32'hF8800FDC;
+parameter val_debug_dap_rom__PERIPHID7 = 32'h00000000;
+parameter mask_debug_dap_rom__PERIPHID7 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID0 = 32'hF8800FE0;
+parameter val_debug_dap_rom__PERIPHID0 = 32'h000000B2;
+parameter mask_debug_dap_rom__PERIPHID0 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID1 = 32'hF8800FE4;
+parameter val_debug_dap_rom__PERIPHID1 = 32'h00000093;
+parameter mask_debug_dap_rom__PERIPHID1 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID2 = 32'hF8800FE8;
+parameter val_debug_dap_rom__PERIPHID2 = 32'h00000008;
+parameter mask_debug_dap_rom__PERIPHID2 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID3 = 32'hF8800FEC;
+parameter val_debug_dap_rom__PERIPHID3 = 32'h00000000;
+parameter mask_debug_dap_rom__PERIPHID3 = 32'h000000FF;
+
+parameter debug_dap_rom__COMPID0 = 32'hF8800FF0;
+parameter val_debug_dap_rom__COMPID0 = 32'h0000000D;
+parameter mask_debug_dap_rom__COMPID0 = 32'h000000FF;
+
+parameter debug_dap_rom__COMPID1 = 32'hF8800FF4;
+parameter val_debug_dap_rom__COMPID1 = 32'h00000010;
+parameter mask_debug_dap_rom__COMPID1 = 32'h000000FF;
+
+parameter debug_dap_rom__COMPID2 = 32'hF8800FF8;
+parameter val_debug_dap_rom__COMPID2 = 32'h00000005;
+parameter mask_debug_dap_rom__COMPID2 = 32'h000000FF;
+
+parameter debug_dap_rom__COMPID3 = 32'hF8800FFC;
+parameter val_debug_dap_rom__COMPID3 = 32'h000000B1;
+parameter mask_debug_dap_rom__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_etb etb
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_etb__RDP = 32'hF8801004;
+parameter val_debug_etb__RDP = 32'h00000400;
+parameter mask_debug_etb__RDP = 32'hFFFFFFFF;
+
+parameter debug_etb__STS = 32'hF880100C;
+parameter val_debug_etb__STS = 32'h00000000;
+parameter mask_debug_etb__STS = 32'h0000000F;
+
+parameter debug_etb__RRD = 32'hF8801010;
+parameter val_debug_etb__RRD = 32'h00000000;
+parameter mask_debug_etb__RRD = 32'hFFFFFFFF;
+
+parameter debug_etb__RRP = 32'hF8801014;
+parameter val_debug_etb__RRP = 32'h00000000;
+parameter mask_debug_etb__RRP = 32'h000003FF;
+
+parameter debug_etb__RWP = 32'hF8801018;
+parameter val_debug_etb__RWP = 32'h00000000;
+parameter mask_debug_etb__RWP = 32'h000003FF;
+
+parameter debug_etb__TRG = 32'hF880101C;
+parameter val_debug_etb__TRG = 32'h00000000;
+parameter mask_debug_etb__TRG = 32'h000003FF;
+
+parameter debug_etb__CTL = 32'hF8801020;
+parameter val_debug_etb__CTL = 32'h00000000;
+parameter mask_debug_etb__CTL = 32'h00000001;
+
+parameter debug_etb__RWD = 32'hF8801024;
+parameter val_debug_etb__RWD = 32'h00000000;
+parameter mask_debug_etb__RWD = 32'hFFFFFFFF;
+
+parameter debug_etb__FFSR = 32'hF8801300;
+parameter val_debug_etb__FFSR = 32'h00000000;
+parameter mask_debug_etb__FFSR = 32'h00000003;
+
+parameter debug_etb__FFCR = 32'hF8801304;
+parameter val_debug_etb__FFCR = 32'h00000200;
+parameter mask_debug_etb__FFCR = 32'h00003FFF;
+
+parameter debug_etb__ITMISCOP0 = 32'hF8801EE0;
+parameter val_debug_etb__ITMISCOP0 = 32'h00000000;
+parameter mask_debug_etb__ITMISCOP0 = 32'h00000003;
+
+parameter debug_etb__ITTRFLINACK = 32'hF8801EE4;
+parameter val_debug_etb__ITTRFLINACK = 32'h00000000;
+parameter mask_debug_etb__ITTRFLINACK = 32'h00000003;
+
+parameter debug_etb__ITTRFLIN = 32'hF8801EE8;
+parameter val_debug_etb__ITTRFLIN = 32'h00000000;
+parameter mask_debug_etb__ITTRFLIN = 32'h00000003;
+
+parameter debug_etb__ITATBDATA0 = 32'hF8801EEC;
+parameter val_debug_etb__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_etb__ITATBDATA0 = 32'h0000001F;
+
+parameter debug_etb__ITATBCTR2 = 32'hF8801EF0;
+parameter val_debug_etb__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_etb__ITATBCTR2 = 32'h00000003;
+
+parameter debug_etb__ITATBCTR1 = 32'hF8801EF4;
+parameter val_debug_etb__ITATBCTR1 = 32'h00000000;
+parameter mask_debug_etb__ITATBCTR1 = 32'h0000007F;
+
+parameter debug_etb__ITATBCTR0 = 32'hF8801EF8;
+parameter val_debug_etb__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_etb__ITATBCTR0 = 32'h000003FF;
+
+parameter debug_etb__IMCR = 32'hF8801F00;
+parameter val_debug_etb__IMCR = 32'h00000000;
+parameter mask_debug_etb__IMCR = 32'h00000001;
+
+parameter debug_etb__CTSR = 32'hF8801FA0;
+parameter val_debug_etb__CTSR = 32'h0000000F;
+parameter mask_debug_etb__CTSR = 32'h0000000F;
+
+parameter debug_etb__CTCR = 32'hF8801FA4;
+parameter val_debug_etb__CTCR = 32'h00000000;
+parameter mask_debug_etb__CTCR = 32'h0000000F;
+
+parameter debug_etb__LAR = 32'hF8801FB0;
+parameter val_debug_etb__LAR = 32'h00000000;
+parameter mask_debug_etb__LAR = 32'hFFFFFFFF;
+
+parameter debug_etb__LSR = 32'hF8801FB4;
+parameter val_debug_etb__LSR = 32'h00000003;
+parameter mask_debug_etb__LSR = 32'h00000007;
+
+parameter debug_etb__ASR = 32'hF8801FB8;
+parameter val_debug_etb__ASR = 32'h00000000;
+parameter mask_debug_etb__ASR = 32'h000000FF;
+
+parameter debug_etb__DEVID = 32'hF8801FC8;
+parameter val_debug_etb__DEVID = 32'h00000000;
+parameter mask_debug_etb__DEVID = 32'h0000003F;
+
+parameter debug_etb__DTIR = 32'hF8801FCC;
+parameter val_debug_etb__DTIR = 32'h00000021;
+parameter mask_debug_etb__DTIR = 32'h000000FF;
+
+parameter debug_etb__PERIPHID4 = 32'hF8801FD0;
+parameter val_debug_etb__PERIPHID4 = 32'h00000004;
+parameter mask_debug_etb__PERIPHID4 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID5 = 32'hF8801FD4;
+parameter val_debug_etb__PERIPHID5 = 32'h00000000;
+parameter mask_debug_etb__PERIPHID5 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID6 = 32'hF8801FD8;
+parameter val_debug_etb__PERIPHID6 = 32'h00000000;
+parameter mask_debug_etb__PERIPHID6 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID7 = 32'hF8801FDC;
+parameter val_debug_etb__PERIPHID7 = 32'h00000000;
+parameter mask_debug_etb__PERIPHID7 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID0 = 32'hF8801FE0;
+parameter val_debug_etb__PERIPHID0 = 32'h00000007;
+parameter mask_debug_etb__PERIPHID0 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID1 = 32'hF8801FE4;
+parameter val_debug_etb__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_etb__PERIPHID1 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID2 = 32'hF8801FE8;
+parameter val_debug_etb__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_etb__PERIPHID2 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID3 = 32'hF8801FEC;
+parameter val_debug_etb__PERIPHID3 = 32'h00000000;
+parameter mask_debug_etb__PERIPHID3 = 32'h000000FF;
+
+parameter debug_etb__COMPID0 = 32'hF8801FF0;
+parameter val_debug_etb__COMPID0 = 32'h0000000D;
+parameter mask_debug_etb__COMPID0 = 32'h000000FF;
+
+parameter debug_etb__COMPID1 = 32'hF8801FF4;
+parameter val_debug_etb__COMPID1 = 32'h00000090;
+parameter mask_debug_etb__COMPID1 = 32'h000000FF;
+
+parameter debug_etb__COMPID2 = 32'hF8801FF8;
+parameter val_debug_etb__COMPID2 = 32'h00000005;
+parameter mask_debug_etb__COMPID2 = 32'h000000FF;
+
+parameter debug_etb__COMPID3 = 32'hF8801FFC;
+parameter val_debug_etb__COMPID3 = 32'h000000B1;
+parameter mask_debug_etb__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_ftm ftm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_ftm__FTMGLBCTRL = 32'hF880B000;
+parameter val_debug_ftm__FTMGLBCTRL = 32'h00000000;
+parameter mask_debug_ftm__FTMGLBCTRL = 32'h00000001;
+
+parameter debug_ftm__FTMSTATUS = 32'hF880B004;
+parameter val_debug_ftm__FTMSTATUS = 32'h00000082;
+parameter mask_debug_ftm__FTMSTATUS = 32'h000000FF;
+
+parameter debug_ftm__FTMCONTROL = 32'hF880B008;
+parameter val_debug_ftm__FTMCONTROL = 32'h00000000;
+parameter mask_debug_ftm__FTMCONTROL = 32'h00000007;
+
+parameter debug_ftm__FTMP2FDBG0 = 32'hF880B00C;
+parameter val_debug_ftm__FTMP2FDBG0 = 32'h00000000;
+parameter mask_debug_ftm__FTMP2FDBG0 = 32'h000000FF;
+
+parameter debug_ftm__FTMP2FDBG1 = 32'hF880B010;
+parameter val_debug_ftm__FTMP2FDBG1 = 32'h00000000;
+parameter mask_debug_ftm__FTMP2FDBG1 = 32'h000000FF;
+
+parameter debug_ftm__FTMP2FDBG2 = 32'hF880B014;
+parameter val_debug_ftm__FTMP2FDBG2 = 32'h00000000;
+parameter mask_debug_ftm__FTMP2FDBG2 = 32'h000000FF;
+
+parameter debug_ftm__FTMP2FDBG3 = 32'hF880B018;
+parameter val_debug_ftm__FTMP2FDBG3 = 32'h00000000;
+parameter mask_debug_ftm__FTMP2FDBG3 = 32'h000000FF;
+
+parameter debug_ftm__FTMF2PDBG0 = 32'hF880B01C;
+parameter val_debug_ftm__FTMF2PDBG0 = 32'h00000000;
+parameter mask_debug_ftm__FTMF2PDBG0 = 32'h000000FF;
+
+parameter debug_ftm__FTMF2PDBG1 = 32'hF880B020;
+parameter val_debug_ftm__FTMF2PDBG1 = 32'h00000000;
+parameter mask_debug_ftm__FTMF2PDBG1 = 32'h000000FF;
+
+parameter debug_ftm__FTMF2PDBG2 = 32'hF880B024;
+parameter val_debug_ftm__FTMF2PDBG2 = 32'h00000000;
+parameter mask_debug_ftm__FTMF2PDBG2 = 32'h000000FF;
+
+parameter debug_ftm__FTMF2PDBG3 = 32'hF880B028;
+parameter val_debug_ftm__FTMF2PDBG3 = 32'h00000000;
+parameter mask_debug_ftm__FTMF2PDBG3 = 32'h000000FF;
+
+parameter debug_ftm__CYCOUNTPRE = 32'hF880B02C;
+parameter val_debug_ftm__CYCOUNTPRE = 32'h00000000;
+parameter mask_debug_ftm__CYCOUNTPRE = 32'h0000000F;
+
+parameter debug_ftm__FTMSYNCRELOAD = 32'hF880B030;
+parameter val_debug_ftm__FTMSYNCRELOAD = 32'h00000000;
+parameter mask_debug_ftm__FTMSYNCRELOAD = 32'h00000FFF;
+
+parameter debug_ftm__FTMSYNCCOUT = 32'hF880B034;
+parameter val_debug_ftm__FTMSYNCCOUT = 32'h00000000;
+parameter mask_debug_ftm__FTMSYNCCOUT = 32'h00000FFF;
+
+parameter debug_ftm__FTMATID = 32'hF880B400;
+parameter val_debug_ftm__FTMATID = 32'h00000000;
+parameter mask_debug_ftm__FTMATID = 32'h0000007F;
+
+parameter debug_ftm__FTMITTRIGOUTACK = 32'hF880BED0;
+parameter val_debug_ftm__FTMITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_ftm__FTMITTRIGOUTACK = 32'h0000000F;
+
+parameter debug_ftm__FTMITTRIGGER = 32'hF880BED4;
+parameter val_debug_ftm__FTMITTRIGGER = 32'h00000000;
+parameter mask_debug_ftm__FTMITTRIGGER = 32'h0000000F;
+
+parameter debug_ftm__FTMITTRACEDIS = 32'hF880BED8;
+parameter val_debug_ftm__FTMITTRACEDIS = 32'h00000000;
+parameter mask_debug_ftm__FTMITTRACEDIS = 32'h00000001;
+
+parameter debug_ftm__FTMITCYCCOUNT = 32'hF880BEDC;
+parameter val_debug_ftm__FTMITCYCCOUNT = 32'h00000001;
+parameter mask_debug_ftm__FTMITCYCCOUNT = 32'hFFFFFFFF;
+
+parameter debug_ftm__FTMITATBDATA0 = 32'hF880BEEC;
+parameter val_debug_ftm__FTMITATBDATA0 = 32'h00000000;
+parameter mask_debug_ftm__FTMITATBDATA0 = 32'h0000001F;
+
+parameter debug_ftm__FTMITATBCTR2 = 32'hF880BEF0;
+parameter val_debug_ftm__FTMITATBCTR2 = 32'h00000001;
+parameter mask_debug_ftm__FTMITATBCTR2 = 32'h00000003;
+
+parameter debug_ftm__FTMITATBCTR1 = 32'hF880BEF4;
+parameter val_debug_ftm__FTMITATBCTR1 = 32'h00000000;
+parameter mask_debug_ftm__FTMITATBCTR1 = 32'h0000007F;
+
+parameter debug_ftm__FTMITATBCTR0 = 32'hF880BEF8;
+parameter val_debug_ftm__FTMITATBCTR0 = 32'h00000000;
+parameter mask_debug_ftm__FTMITATBCTR0 = 32'h000003FF;
+
+parameter debug_ftm__FTMITCR = 32'hF880BF00;
+parameter val_debug_ftm__FTMITCR = 32'h00000000;
+parameter mask_debug_ftm__FTMITCR = 32'h00000001;
+
+parameter debug_ftm__CLAIMTAGSET = 32'hF880BFA0;
+parameter val_debug_ftm__CLAIMTAGSET = 32'h000000FF;
+parameter mask_debug_ftm__CLAIMTAGSET = 32'h000000FF;
+
+parameter debug_ftm__CLAIMTAGCLR = 32'hF880BFA4;
+parameter val_debug_ftm__CLAIMTAGCLR = 32'h000000FF;
+parameter mask_debug_ftm__CLAIMTAGCLR = 32'h000000FF;
+
+parameter debug_ftm__LOCK_ACCESS = 32'hF880BFB0;
+parameter val_debug_ftm__LOCK_ACCESS = 32'h00000000;
+parameter mask_debug_ftm__LOCK_ACCESS = 32'hFFFFFFFF;
+
+parameter debug_ftm__LOCK_STATUS = 32'hF880BFB4;
+parameter val_debug_ftm__LOCK_STATUS = 32'h00000003;
+parameter mask_debug_ftm__LOCK_STATUS = 32'h00000007;
+
+parameter debug_ftm__FTMAUTHSTATUS = 32'hF880BFB8;
+parameter val_debug_ftm__FTMAUTHSTATUS = 32'h00000088;
+parameter mask_debug_ftm__FTMAUTHSTATUS = 32'h000000FF;
+
+parameter debug_ftm__FTMDEVID = 32'hF880BFC8;
+parameter val_debug_ftm__FTMDEVID = 32'h00000000;
+parameter mask_debug_ftm__FTMDEVID = 32'h00000001;
+
+parameter debug_ftm__FTMDEV_TYPE = 32'hF880BFCC;
+parameter val_debug_ftm__FTMDEV_TYPE = 32'h00000033;
+parameter mask_debug_ftm__FTMDEV_TYPE = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID4 = 32'hF880BFD0;
+parameter val_debug_ftm__FTMPERIPHID4 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID4 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID5 = 32'hF880BFD4;
+parameter val_debug_ftm__FTMPERIPHID5 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID5 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID6 = 32'hF880BFD8;
+parameter val_debug_ftm__FTMPERIPHID6 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID6 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID7 = 32'hF880BFDC;
+parameter val_debug_ftm__FTMPERIPHID7 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID7 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID0 = 32'hF880BFE0;
+parameter val_debug_ftm__FTMPERIPHID0 = 32'h00000001;
+parameter mask_debug_ftm__FTMPERIPHID0 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID1 = 32'hF880BFE4;
+parameter val_debug_ftm__FTMPERIPHID1 = 32'h00000090;
+parameter mask_debug_ftm__FTMPERIPHID1 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID2 = 32'hF880BFE8;
+parameter val_debug_ftm__FTMPERIPHID2 = 32'h0000000C;
+parameter mask_debug_ftm__FTMPERIPHID2 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID3 = 32'hF880BFEC;
+parameter val_debug_ftm__FTMPERIPHID3 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID3 = 32'h000000FF;
+
+parameter debug_ftm__FTMCOMPONID0 = 32'hF880BFF0;
+parameter val_debug_ftm__FTMCOMPONID0 = 32'h0000000D;
+parameter mask_debug_ftm__FTMCOMPONID0 = 32'h000000FF;
+
+parameter debug_ftm__FTMCOMPONID1 = 32'hF880BFF4;
+parameter val_debug_ftm__FTMCOMPONID1 = 32'h00000090;
+parameter mask_debug_ftm__FTMCOMPONID1 = 32'h000000FF;
+
+parameter debug_ftm__FTMCOMPONID2 = 32'hF880BFF8;
+parameter val_debug_ftm__FTMCOMPONID2 = 32'h00000005;
+parameter mask_debug_ftm__FTMCOMPONID2 = 32'h000000FF;
+
+parameter debug_ftm__FTMCOMPONID3 = 32'hF880BFFC;
+parameter val_debug_ftm__FTMCOMPONID3 = 32'h000000B1;
+parameter mask_debug_ftm__FTMCOMPONID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_funnel funnel
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_funnel__Control = 32'hF8804000;
+parameter val_debug_funnel__Control = 32'h00000300;
+parameter mask_debug_funnel__Control = 32'h00000FFF;
+
+parameter debug_funnel__PriControl = 32'hF8804004;
+parameter val_debug_funnel__PriControl = 32'h00FAC688;
+parameter mask_debug_funnel__PriControl = 32'h00FFFFFF;
+
+parameter debug_funnel__ITATBDATA0 = 32'hF8804EEC;
+parameter val_debug_funnel__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_funnel__ITATBDATA0 = 32'h0000001F;
+
+parameter debug_funnel__ITATBCTR2 = 32'hF8804EF0;
+parameter val_debug_funnel__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_funnel__ITATBCTR2 = 32'h00000003;
+
+parameter debug_funnel__ITATBCTR1 = 32'hF8804EF4;
+parameter val_debug_funnel__ITATBCTR1 = 32'h00000000;
+parameter mask_debug_funnel__ITATBCTR1 = 32'h0000007F;
+
+parameter debug_funnel__ITATBCTR0 = 32'hF8804EF8;
+parameter val_debug_funnel__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_funnel__ITATBCTR0 = 32'h000003FF;
+
+parameter debug_funnel__IMCR = 32'hF8804F00;
+parameter val_debug_funnel__IMCR = 32'h00000000;
+parameter mask_debug_funnel__IMCR = 32'h00000001;
+
+parameter debug_funnel__CTSR = 32'hF8804FA0;
+parameter val_debug_funnel__CTSR = 32'h0000000F;
+parameter mask_debug_funnel__CTSR = 32'h0000000F;
+
+parameter debug_funnel__CTCR = 32'hF8804FA4;
+parameter val_debug_funnel__CTCR = 32'h00000000;
+parameter mask_debug_funnel__CTCR = 32'h0000000F;
+
+parameter debug_funnel__LAR = 32'hF8804FB0;
+parameter val_debug_funnel__LAR = 32'h00000000;
+parameter mask_debug_funnel__LAR = 32'hFFFFFFFF;
+
+parameter debug_funnel__LSR = 32'hF8804FB4;
+parameter val_debug_funnel__LSR = 32'h00000003;
+parameter mask_debug_funnel__LSR = 32'h00000007;
+
+parameter debug_funnel__ASR = 32'hF8804FB8;
+parameter val_debug_funnel__ASR = 32'h00000000;
+parameter mask_debug_funnel__ASR = 32'h000000FF;
+
+parameter debug_funnel__DEVID = 32'hF8804FC8;
+parameter val_debug_funnel__DEVID = 32'h00000028;
+parameter mask_debug_funnel__DEVID = 32'h000000FF;
+
+parameter debug_funnel__DTIR = 32'hF8804FCC;
+parameter val_debug_funnel__DTIR = 32'h00000012;
+parameter mask_debug_funnel__DTIR = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID4 = 32'hF8804FD0;
+parameter val_debug_funnel__PERIPHID4 = 32'h00000004;
+parameter mask_debug_funnel__PERIPHID4 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID5 = 32'hF8804FD4;
+parameter val_debug_funnel__PERIPHID5 = 32'h00000000;
+parameter mask_debug_funnel__PERIPHID5 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID6 = 32'hF8804FD8;
+parameter val_debug_funnel__PERIPHID6 = 32'h00000000;
+parameter mask_debug_funnel__PERIPHID6 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID7 = 32'hF8804FDC;
+parameter val_debug_funnel__PERIPHID7 = 32'h00000000;
+parameter mask_debug_funnel__PERIPHID7 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID0 = 32'hF8804FE0;
+parameter val_debug_funnel__PERIPHID0 = 32'h00000008;
+parameter mask_debug_funnel__PERIPHID0 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID1 = 32'hF8804FE4;
+parameter val_debug_funnel__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_funnel__PERIPHID1 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID2 = 32'hF8804FE8;
+parameter val_debug_funnel__PERIPHID2 = 32'h0000001B;
+parameter mask_debug_funnel__PERIPHID2 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID3 = 32'hF8804FEC;
+parameter val_debug_funnel__PERIPHID3 = 32'h00000000;
+parameter mask_debug_funnel__PERIPHID3 = 32'h000000FF;
+
+parameter debug_funnel__COMPID0 = 32'hF8804FF0;
+parameter val_debug_funnel__COMPID0 = 32'h0000000D;
+parameter mask_debug_funnel__COMPID0 = 32'h000000FF;
+
+parameter debug_funnel__COMPID1 = 32'hF8804FF4;
+parameter val_debug_funnel__COMPID1 = 32'h00000090;
+parameter mask_debug_funnel__COMPID1 = 32'h000000FF;
+
+parameter debug_funnel__COMPID2 = 32'hF8804FF8;
+parameter val_debug_funnel__COMPID2 = 32'h00000005;
+parameter mask_debug_funnel__COMPID2 = 32'h000000FF;
+
+parameter debug_funnel__COMPID3 = 32'hF8804FFC;
+parameter val_debug_funnel__COMPID3 = 32'h000000B1;
+parameter mask_debug_funnel__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_itm itm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_itm__StimPort00 = 32'hF8805000;
+parameter val_debug_itm__StimPort00 = 32'h00000000;
+parameter mask_debug_itm__StimPort00 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort01 = 32'hF8805004;
+parameter val_debug_itm__StimPort01 = 32'h00000000;
+parameter mask_debug_itm__StimPort01 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort02 = 32'hF8805008;
+parameter val_debug_itm__StimPort02 = 32'h00000000;
+parameter mask_debug_itm__StimPort02 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort03 = 32'hF880500C;
+parameter val_debug_itm__StimPort03 = 32'h00000000;
+parameter mask_debug_itm__StimPort03 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort04 = 32'hF8805010;
+parameter val_debug_itm__StimPort04 = 32'h00000000;
+parameter mask_debug_itm__StimPort04 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort05 = 32'hF8805014;
+parameter val_debug_itm__StimPort05 = 32'h00000000;
+parameter mask_debug_itm__StimPort05 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort06 = 32'hF8805018;
+parameter val_debug_itm__StimPort06 = 32'h00000000;
+parameter mask_debug_itm__StimPort06 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort07 = 32'hF880501C;
+parameter val_debug_itm__StimPort07 = 32'h00000000;
+parameter mask_debug_itm__StimPort07 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort08 = 32'hF8805020;
+parameter val_debug_itm__StimPort08 = 32'h00000000;
+parameter mask_debug_itm__StimPort08 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort09 = 32'hF8805024;
+parameter val_debug_itm__StimPort09 = 32'h00000000;
+parameter mask_debug_itm__StimPort09 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort10 = 32'hF8805028;
+parameter val_debug_itm__StimPort10 = 32'h00000000;
+parameter mask_debug_itm__StimPort10 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort11 = 32'hF880502C;
+parameter val_debug_itm__StimPort11 = 32'h00000000;
+parameter mask_debug_itm__StimPort11 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort12 = 32'hF8805030;
+parameter val_debug_itm__StimPort12 = 32'h00000000;
+parameter mask_debug_itm__StimPort12 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort13 = 32'hF8805034;
+parameter val_debug_itm__StimPort13 = 32'h00000000;
+parameter mask_debug_itm__StimPort13 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort14 = 32'hF8805038;
+parameter val_debug_itm__StimPort14 = 32'h00000000;
+parameter mask_debug_itm__StimPort14 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort15 = 32'hF880503C;
+parameter val_debug_itm__StimPort15 = 32'h00000000;
+parameter mask_debug_itm__StimPort15 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort16 = 32'hF8805040;
+parameter val_debug_itm__StimPort16 = 32'h00000000;
+parameter mask_debug_itm__StimPort16 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort17 = 32'hF8805044;
+parameter val_debug_itm__StimPort17 = 32'h00000000;
+parameter mask_debug_itm__StimPort17 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort18 = 32'hF8805048;
+parameter val_debug_itm__StimPort18 = 32'h00000000;
+parameter mask_debug_itm__StimPort18 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort19 = 32'hF880504C;
+parameter val_debug_itm__StimPort19 = 32'h00000000;
+parameter mask_debug_itm__StimPort19 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort20 = 32'hF8805050;
+parameter val_debug_itm__StimPort20 = 32'h00000000;
+parameter mask_debug_itm__StimPort20 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort21 = 32'hF8805054;
+parameter val_debug_itm__StimPort21 = 32'h00000000;
+parameter mask_debug_itm__StimPort21 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort22 = 32'hF8805058;
+parameter val_debug_itm__StimPort22 = 32'h00000000;
+parameter mask_debug_itm__StimPort22 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort23 = 32'hF880505C;
+parameter val_debug_itm__StimPort23 = 32'h00000000;
+parameter mask_debug_itm__StimPort23 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort24 = 32'hF8805060;
+parameter val_debug_itm__StimPort24 = 32'h00000000;
+parameter mask_debug_itm__StimPort24 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort25 = 32'hF8805064;
+parameter val_debug_itm__StimPort25 = 32'h00000000;
+parameter mask_debug_itm__StimPort25 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort26 = 32'hF8805068;
+parameter val_debug_itm__StimPort26 = 32'h00000000;
+parameter mask_debug_itm__StimPort26 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort27 = 32'hF880506C;
+parameter val_debug_itm__StimPort27 = 32'h00000000;
+parameter mask_debug_itm__StimPort27 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort28 = 32'hF8805070;
+parameter val_debug_itm__StimPort28 = 32'h00000000;
+parameter mask_debug_itm__StimPort28 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort29 = 32'hF8805074;
+parameter val_debug_itm__StimPort29 = 32'h00000000;
+parameter mask_debug_itm__StimPort29 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort30 = 32'hF8805078;
+parameter val_debug_itm__StimPort30 = 32'h00000000;
+parameter mask_debug_itm__StimPort30 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort31 = 32'hF880507C;
+parameter val_debug_itm__StimPort31 = 32'h00000000;
+parameter mask_debug_itm__StimPort31 = 32'hFFFFFFFF;
+
+parameter debug_itm__TER = 32'hF8805E00;
+parameter val_debug_itm__TER = 32'h00000000;
+parameter mask_debug_itm__TER = 32'hFFFFFFFF;
+
+parameter debug_itm__TTR = 32'hF8805E20;
+parameter val_debug_itm__TTR = 32'h00000000;
+parameter mask_debug_itm__TTR = 32'hFFFFFFFF;
+
+parameter debug_itm__CR = 32'hF8805E80;
+parameter val_debug_itm__CR = 32'h00000004;
+parameter mask_debug_itm__CR = 32'h00FFFFFF;
+
+parameter debug_itm__SCR = 32'hF8805E90;
+parameter val_debug_itm__SCR = 32'h00000400;
+parameter mask_debug_itm__SCR = 32'h00000FFF;
+
+parameter debug_itm__ITTRIGOUTACK = 32'hF8805EE4;
+parameter val_debug_itm__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_itm__ITTRIGOUTACK = 32'h00000001;
+
+parameter debug_itm__ITTRIGOUT = 32'hF8805EE8;
+parameter val_debug_itm__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_itm__ITTRIGOUT = 32'h00000001;
+
+parameter debug_itm__ITATBDATA0 = 32'hF8805EEC;
+parameter val_debug_itm__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_itm__ITATBDATA0 = 32'h00000003;
+
+parameter debug_itm__ITATBCTR2 = 32'hF8805EF0;
+parameter val_debug_itm__ITATBCTR2 = 32'h00000001;
+parameter mask_debug_itm__ITATBCTR2 = 32'h00000001;
+
+parameter debug_itm__ITATABCTR1 = 32'hF8805EF4;
+parameter val_debug_itm__ITATABCTR1 = 32'h00000000;
+parameter mask_debug_itm__ITATABCTR1 = 32'h0000007F;
+
+parameter debug_itm__ITATBCTR0 = 32'hF8805EF8;
+parameter val_debug_itm__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_itm__ITATBCTR0 = 32'h00000003;
+
+parameter debug_itm__IMCR = 32'hF8805F00;
+parameter val_debug_itm__IMCR = 32'h00000000;
+parameter mask_debug_itm__IMCR = 32'h00000001;
+
+parameter debug_itm__CTSR = 32'hF8805FA0;
+parameter val_debug_itm__CTSR = 32'h000000FF;
+parameter mask_debug_itm__CTSR = 32'h000000FF;
+
+parameter debug_itm__CTCR = 32'hF8805FA4;
+parameter val_debug_itm__CTCR = 32'h00000000;
+parameter mask_debug_itm__CTCR = 32'h000000FF;
+
+parameter debug_itm__LAR = 32'hF8805FB0;
+parameter val_debug_itm__LAR = 32'h00000000;
+parameter mask_debug_itm__LAR = 32'hFFFFFFFF;
+
+parameter debug_itm__LSR = 32'hF8805FB4;
+parameter val_debug_itm__LSR = 32'h00000003;
+parameter mask_debug_itm__LSR = 32'h00000007;
+
+parameter debug_itm__ASR = 32'hF8805FB8;
+parameter val_debug_itm__ASR = 32'h00000088;
+parameter mask_debug_itm__ASR = 32'h000000FF;
+
+parameter debug_itm__DEVID = 32'hF8805FC8;
+parameter val_debug_itm__DEVID = 32'h00000020;
+parameter mask_debug_itm__DEVID = 32'h00001FFF;
+
+parameter debug_itm__DTIR = 32'hF8805FCC;
+parameter val_debug_itm__DTIR = 32'h00000043;
+parameter mask_debug_itm__DTIR = 32'h000000FF;
+
+parameter debug_itm__PERIPHID4 = 32'hF8805FD0;
+parameter val_debug_itm__PERIPHID4 = 32'h00000004;
+parameter mask_debug_itm__PERIPHID4 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID5 = 32'hF8805FD4;
+parameter val_debug_itm__PERIPHID5 = 32'h00000000;
+parameter mask_debug_itm__PERIPHID5 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID6 = 32'hF8805FD8;
+parameter val_debug_itm__PERIPHID6 = 32'h00000000;
+parameter mask_debug_itm__PERIPHID6 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID7 = 32'hF8805FDC;
+parameter val_debug_itm__PERIPHID7 = 32'h00000000;
+parameter mask_debug_itm__PERIPHID7 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID0 = 32'hF8805FE0;
+parameter val_debug_itm__PERIPHID0 = 32'h00000013;
+parameter mask_debug_itm__PERIPHID0 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID1 = 32'hF8805FE4;
+parameter val_debug_itm__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_itm__PERIPHID1 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID2 = 32'hF8805FE8;
+parameter val_debug_itm__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_itm__PERIPHID2 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID3 = 32'hF8805FEC;
+parameter val_debug_itm__PERIPHID3 = 32'h00000000;
+parameter mask_debug_itm__PERIPHID3 = 32'h000000FF;
+
+parameter debug_itm__COMPID0 = 32'hF8805FF0;
+parameter val_debug_itm__COMPID0 = 32'h0000000D;
+parameter mask_debug_itm__COMPID0 = 32'h000000FF;
+
+parameter debug_itm__COMPID1 = 32'hF8805FF4;
+parameter val_debug_itm__COMPID1 = 32'h00000090;
+parameter mask_debug_itm__COMPID1 = 32'h000000FF;
+
+parameter debug_itm__COMPID2 = 32'hF8805FF8;
+parameter val_debug_itm__COMPID2 = 32'h00000005;
+parameter mask_debug_itm__COMPID2 = 32'h000000FF;
+
+parameter debug_itm__COMPID3 = 32'hF8805FFC;
+parameter val_debug_itm__COMPID3 = 32'h000000B1;
+parameter mask_debug_itm__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_tpiu tpiu
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_tpiu__SuppSize = 32'hF8803000;
+parameter val_debug_tpiu__SuppSize = 32'hFFFFFFFF;
+parameter mask_debug_tpiu__SuppSize = 32'hFFFFFFFF;
+
+parameter debug_tpiu__CurrentSize = 32'hF8803004;
+parameter val_debug_tpiu__CurrentSize = 32'h00000001;
+parameter mask_debug_tpiu__CurrentSize = 32'hFFFFFFFF;
+
+parameter debug_tpiu__SuppTrigMode = 32'hF8803100;
+parameter val_debug_tpiu__SuppTrigMode = 32'h0000011F;
+parameter mask_debug_tpiu__SuppTrigMode = 32'h0003FFFF;
+
+parameter debug_tpiu__TrigCount = 32'hF8803104;
+parameter val_debug_tpiu__TrigCount = 32'h00000000;
+parameter mask_debug_tpiu__TrigCount = 32'h000000FF;
+
+parameter debug_tpiu__TrigMult = 32'hF8803108;
+parameter val_debug_tpiu__TrigMult = 32'h00000000;
+parameter mask_debug_tpiu__TrigMult = 32'h0000001F;
+
+parameter debug_tpiu__SuppTest = 32'hF8803200;
+parameter val_debug_tpiu__SuppTest = 32'h0003000F;
+parameter mask_debug_tpiu__SuppTest = 32'h0003FFFF;
+
+parameter debug_tpiu__CurrentTest = 32'hF8803204;
+parameter val_debug_tpiu__CurrentTest = 32'h00000000;
+parameter mask_debug_tpiu__CurrentTest = 32'h0003FFFF;
+
+parameter debug_tpiu__TestRepeatCount = 32'hF8803208;
+parameter val_debug_tpiu__TestRepeatCount = 32'h00000000;
+parameter mask_debug_tpiu__TestRepeatCount = 32'h000000FF;
+
+parameter debug_tpiu__FFSR = 32'hF8803300;
+parameter val_debug_tpiu__FFSR = 32'h00000006;
+parameter mask_debug_tpiu__FFSR = 32'h00000007;
+
+parameter debug_tpiu__FFCR = 32'hF8803304;
+parameter val_debug_tpiu__FFCR = 32'h00000000;
+parameter mask_debug_tpiu__FFCR = 32'h00003FFF;
+
+parameter debug_tpiu__FormatSyncCount = 32'hF8803308;
+parameter val_debug_tpiu__FormatSyncCount = 32'h00000040;
+parameter mask_debug_tpiu__FormatSyncCount = 32'h00000FFF;
+
+parameter debug_tpiu__EXTCTLIn = 32'hF8803400;
+parameter val_debug_tpiu__EXTCTLIn = 32'h00000000;
+parameter mask_debug_tpiu__EXTCTLIn = 32'h000000FF;
+
+parameter debug_tpiu__EXTCTLOut = 32'hF8803404;
+parameter val_debug_tpiu__EXTCTLOut = 32'h00000000;
+parameter mask_debug_tpiu__EXTCTLOut = 32'h000000FF;
+
+parameter debug_tpiu__ITTRFLINACK = 32'hF8803EE4;
+parameter val_debug_tpiu__ITTRFLINACK = 32'h00000000;
+parameter mask_debug_tpiu__ITTRFLINACK = 32'h00000003;
+
+parameter debug_tpiu__ITTRFLIN = 32'hF8803EE8;
+parameter val_debug_tpiu__ITTRFLIN = 32'h00000000;
+parameter mask_debug_tpiu__ITTRFLIN = 32'h00000000;
+
+parameter debug_tpiu__ITATBDATA0 = 32'hF8803EEC;
+parameter val_debug_tpiu__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_tpiu__ITATBDATA0 = 32'h00000000;
+
+parameter debug_tpiu__ITATBCTR2 = 32'hF8803EF0;
+parameter val_debug_tpiu__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_tpiu__ITATBCTR2 = 32'h00000003;
+
+parameter debug_tpiu__ITATBCTR1 = 32'hF8803EF4;
+parameter val_debug_tpiu__ITATBCTR1 = 32'h00000000;
+parameter mask_debug_tpiu__ITATBCTR1 = 32'h00000000;
+
+parameter debug_tpiu__ITATBCTR0 = 32'hF8803EF8;
+parameter val_debug_tpiu__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_tpiu__ITATBCTR0 = 32'h00000000;
+
+parameter debug_tpiu__IMCR = 32'hF8803F00;
+parameter val_debug_tpiu__IMCR = 32'h00000000;
+parameter mask_debug_tpiu__IMCR = 32'h00000001;
+
+parameter debug_tpiu__CTSR = 32'hF8803FA0;
+parameter val_debug_tpiu__CTSR = 32'h0000000F;
+parameter mask_debug_tpiu__CTSR = 32'h0000000F;
+
+parameter debug_tpiu__CTCR = 32'hF8803FA4;
+parameter val_debug_tpiu__CTCR = 32'h00000000;
+parameter mask_debug_tpiu__CTCR = 32'h0000000F;
+
+parameter debug_tpiu__LAR = 32'hF8803FB0;
+parameter val_debug_tpiu__LAR = 32'h00000000;
+parameter mask_debug_tpiu__LAR = 32'hFFFFFFFF;
+
+parameter debug_tpiu__LSR = 32'hF8803FB4;
+parameter val_debug_tpiu__LSR = 32'h00000003;
+parameter mask_debug_tpiu__LSR = 32'h00000007;
+
+parameter debug_tpiu__ASR = 32'hF8803FB8;
+parameter val_debug_tpiu__ASR = 32'h00000000;
+parameter mask_debug_tpiu__ASR = 32'h000000FF;
+
+parameter debug_tpiu__DEVID = 32'hF8803FC8;
+parameter val_debug_tpiu__DEVID = 32'h000000A0;
+parameter mask_debug_tpiu__DEVID = 32'h00000FFF;
+
+parameter debug_tpiu__DTIR = 32'hF8803FCC;
+parameter val_debug_tpiu__DTIR = 32'h00000011;
+parameter mask_debug_tpiu__DTIR = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID4 = 32'hF8803FD0;
+parameter val_debug_tpiu__PERIPHID4 = 32'h00000004;
+parameter mask_debug_tpiu__PERIPHID4 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID5 = 32'hF8803FD4;
+parameter val_debug_tpiu__PERIPHID5 = 32'h00000000;
+parameter mask_debug_tpiu__PERIPHID5 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID6 = 32'hF8803FD8;
+parameter val_debug_tpiu__PERIPHID6 = 32'h00000000;
+parameter mask_debug_tpiu__PERIPHID6 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID7 = 32'hF8803FDC;
+parameter val_debug_tpiu__PERIPHID7 = 32'h00000000;
+parameter mask_debug_tpiu__PERIPHID7 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID0 = 32'hF8803FE0;
+parameter val_debug_tpiu__PERIPHID0 = 32'h00000012;
+parameter mask_debug_tpiu__PERIPHID0 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID1 = 32'hF8803FE4;
+parameter val_debug_tpiu__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_tpiu__PERIPHID1 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID2 = 32'hF8803FE8;
+parameter val_debug_tpiu__PERIPHID2 = 32'h0000004B;
+parameter mask_debug_tpiu__PERIPHID2 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID3 = 32'hF8803FEC;
+parameter val_debug_tpiu__PERIPHID3 = 32'h00000000;
+parameter mask_debug_tpiu__PERIPHID3 = 32'h000000FF;
+
+parameter debug_tpiu__COMPID0 = 32'hF8803FF0;
+parameter val_debug_tpiu__COMPID0 = 32'h0000000D;
+parameter mask_debug_tpiu__COMPID0 = 32'h000000FF;
+
+parameter debug_tpiu__COMPID1 = 32'hF8803FF4;
+parameter val_debug_tpiu__COMPID1 = 32'h00000090;
+parameter mask_debug_tpiu__COMPID1 = 32'h000000FF;
+
+parameter debug_tpiu__COMPID2 = 32'hF8803FF8;
+parameter val_debug_tpiu__COMPID2 = 32'h00000005;
+parameter mask_debug_tpiu__COMPID2 = 32'h000000FF;
+
+parameter debug_tpiu__COMPID3 = 32'hF8803FFC;
+parameter val_debug_tpiu__COMPID3 = 32'h000000B1;
+parameter mask_debug_tpiu__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module devcfg devcfg
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter devcfg__CTRL = 32'hF8007000;
+parameter val_devcfg__CTRL = 32'h0C000000;
+parameter mask_devcfg__CTRL = 32'hFFFFFFFF;
+
+parameter devcfg__LOCK = 32'hF8007004;
+parameter val_devcfg__LOCK = 32'h00000000;
+parameter mask_devcfg__LOCK = 32'hFFFFFFFF;
+
+parameter devcfg__CFG = 32'hF8007008;
+parameter val_devcfg__CFG = 32'h0000050B;
+parameter mask_devcfg__CFG = 32'hFFFFFFFF;
+
+parameter devcfg__INT_STS = 32'hF800700C;
+parameter val_devcfg__INT_STS = 32'h00000000;
+parameter mask_devcfg__INT_STS = 32'hFFFFFFFF;
+
+parameter devcfg__INT_MASK = 32'hF8007010;
+parameter val_devcfg__INT_MASK = 32'hFFFFFFFF;
+parameter mask_devcfg__INT_MASK = 32'hFFFFFFFF;
+
+parameter devcfg__STATUS = 32'hF8007014;
+parameter val_devcfg__STATUS = 32'h40000820;
+parameter mask_devcfg__STATUS = 32'hFFFFFFFF;
+
+parameter devcfg__DMA_SRC_ADDR = 32'hF8007018;
+parameter val_devcfg__DMA_SRC_ADDR = 32'h00000000;
+parameter mask_devcfg__DMA_SRC_ADDR = 32'hFFFFFFFF;
+
+parameter devcfg__DMA_DST_ADDR = 32'hF800701C;
+parameter val_devcfg__DMA_DST_ADDR = 32'h00000000;
+parameter mask_devcfg__DMA_DST_ADDR = 32'hFFFFFFFF;
+
+parameter devcfg__DMA_SRC_LEN = 32'hF8007020;
+parameter val_devcfg__DMA_SRC_LEN = 32'h00000000;
+parameter mask_devcfg__DMA_SRC_LEN = 32'hFFFFFFFF;
+
+parameter devcfg__DMA_DEST_LEN = 32'hF8007024;
+parameter val_devcfg__DMA_DEST_LEN = 32'h00000000;
+parameter mask_devcfg__DMA_DEST_LEN = 32'hFFFFFFFF;
+
+parameter devcfg__ROM_SHADOW = 32'hF8007028;
+parameter val_devcfg__ROM_SHADOW = 32'h00000000;
+parameter mask_devcfg__ROM_SHADOW = 32'hFFFFFFFF;
+
+parameter devcfg__MULTIBOOT_ADDR = 32'hF800702C;
+parameter val_devcfg__MULTIBOOT_ADDR = 32'h00000000;
+parameter mask_devcfg__MULTIBOOT_ADDR = 32'hFFFFFFFF;
+
+parameter devcfg__SW_ID = 32'hF8007030;
+parameter val_devcfg__SW_ID = 32'h00000000;
+parameter mask_devcfg__SW_ID = 32'hFFFFFFFF;
+
+parameter devcfg__UNLOCK = 32'hF8007034;
+parameter val_devcfg__UNLOCK = 32'h00000000;
+parameter mask_devcfg__UNLOCK = 32'hFFFFFFFF;
+
+parameter devcfg__MCTRL = 32'hF8007080;
+parameter val_devcfg__MCTRL = 32'h00800000;
+parameter mask_devcfg__MCTRL = 32'h0FFFFFFF;
+
+parameter devcfg__XADCIF_CFG = 32'hF8007100;
+parameter val_devcfg__XADCIF_CFG = 32'h00001114;
+parameter mask_devcfg__XADCIF_CFG = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_INT_STS = 32'hF8007104;
+parameter val_devcfg__XADCIF_INT_STS = 32'h00000200;
+parameter mask_devcfg__XADCIF_INT_STS = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_INT_MASK = 32'hF8007108;
+parameter val_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF;
+parameter mask_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_MSTS = 32'hF800710C;
+parameter val_devcfg__XADCIF_MSTS = 32'h00000500;
+parameter mask_devcfg__XADCIF_MSTS = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_CMDFIFO = 32'hF8007110;
+parameter val_devcfg__XADCIF_CMDFIFO = 32'h00000000;
+parameter mask_devcfg__XADCIF_CMDFIFO = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_RDFIFO = 32'hF8007114;
+parameter val_devcfg__XADCIF_RDFIFO = 32'h00000000;
+parameter mask_devcfg__XADCIF_RDFIFO = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_MCTL = 32'hF8007118;
+parameter val_devcfg__XADCIF_MCTL = 32'h00000010;
+parameter mask_devcfg__XADCIF_MCTL = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module dmac0_ns dmac
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter dmac0_ns__DSR = 32'hF8004000;
+parameter val_dmac0_ns__DSR = 32'h00000000;
+parameter mask_dmac0_ns__DSR = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DPC = 32'hF8004004;
+parameter val_dmac0_ns__DPC = 32'h00000000;
+parameter mask_dmac0_ns__DPC = 32'hFFFFFFFF;
+
+parameter dmac0_ns__INTEN = 32'hF8004020;
+parameter val_dmac0_ns__INTEN = 32'h00000000;
+parameter mask_dmac0_ns__INTEN = 32'hFFFFFFFF;
+
+parameter dmac0_ns__INT_EVENT_RIS = 32'hF8004024;
+parameter val_dmac0_ns__INT_EVENT_RIS = 32'h00000000;
+parameter mask_dmac0_ns__INT_EVENT_RIS = 32'hFFFFFFFF;
+
+parameter dmac0_ns__INTMIS = 32'hF8004028;
+parameter val_dmac0_ns__INTMIS = 32'h00000000;
+parameter mask_dmac0_ns__INTMIS = 32'hFFFFFFFF;
+
+parameter dmac0_ns__INTCLR = 32'hF800402C;
+parameter val_dmac0_ns__INTCLR = 32'h00000000;
+parameter mask_dmac0_ns__INTCLR = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FSRD = 32'hF8004030;
+parameter val_dmac0_ns__FSRD = 32'h00000000;
+parameter mask_dmac0_ns__FSRD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FSRC = 32'hF8004034;
+parameter val_dmac0_ns__FSRC = 32'h00000000;
+parameter mask_dmac0_ns__FSRC = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTRD = 32'hF8004038;
+parameter val_dmac0_ns__FTRD = 32'h00000000;
+parameter mask_dmac0_ns__FTRD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR0 = 32'hF8004040;
+parameter val_dmac0_ns__FTR0 = 32'h00000000;
+parameter mask_dmac0_ns__FTR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR1 = 32'hF8004044;
+parameter val_dmac0_ns__FTR1 = 32'h00000000;
+parameter mask_dmac0_ns__FTR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR2 = 32'hF8004048;
+parameter val_dmac0_ns__FTR2 = 32'h00000000;
+parameter mask_dmac0_ns__FTR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR3 = 32'hF800404C;
+parameter val_dmac0_ns__FTR3 = 32'h00000000;
+parameter mask_dmac0_ns__FTR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR4 = 32'hF8004050;
+parameter val_dmac0_ns__FTR4 = 32'h00000000;
+parameter mask_dmac0_ns__FTR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR5 = 32'hF8004054;
+parameter val_dmac0_ns__FTR5 = 32'h00000000;
+parameter mask_dmac0_ns__FTR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR6 = 32'hF8004058;
+parameter val_dmac0_ns__FTR6 = 32'h00000000;
+parameter mask_dmac0_ns__FTR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR7 = 32'hF800405C;
+parameter val_dmac0_ns__FTR7 = 32'h00000000;
+parameter mask_dmac0_ns__FTR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR0 = 32'hF8004100;
+parameter val_dmac0_ns__CSR0 = 32'h00000000;
+parameter mask_dmac0_ns__CSR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC0 = 32'hF8004104;
+parameter val_dmac0_ns__CPC0 = 32'h00000000;
+parameter mask_dmac0_ns__CPC0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR1 = 32'hF8004108;
+parameter val_dmac0_ns__CSR1 = 32'h00000000;
+parameter mask_dmac0_ns__CSR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC1 = 32'hF800410C;
+parameter val_dmac0_ns__CPC1 = 32'h00000000;
+parameter mask_dmac0_ns__CPC1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR2 = 32'hF8004110;
+parameter val_dmac0_ns__CSR2 = 32'h00000000;
+parameter mask_dmac0_ns__CSR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC2 = 32'hF8004114;
+parameter val_dmac0_ns__CPC2 = 32'h00000000;
+parameter mask_dmac0_ns__CPC2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR3 = 32'hF8004118;
+parameter val_dmac0_ns__CSR3 = 32'h00000000;
+parameter mask_dmac0_ns__CSR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC3 = 32'hF800411C;
+parameter val_dmac0_ns__CPC3 = 32'h00000000;
+parameter mask_dmac0_ns__CPC3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR4 = 32'hF8004120;
+parameter val_dmac0_ns__CSR4 = 32'h00000000;
+parameter mask_dmac0_ns__CSR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC4 = 32'hF8004124;
+parameter val_dmac0_ns__CPC4 = 32'h00000000;
+parameter mask_dmac0_ns__CPC4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR5 = 32'hF8004128;
+parameter val_dmac0_ns__CSR5 = 32'h00000000;
+parameter mask_dmac0_ns__""b""CSR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC5 = 32'hF800412C;
+parameter val_dmac0_ns__CPC5 = 32'h00000000;
+parameter mask_dmac0_ns__CPC5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR6 = 32'hF8004130;
+parameter val_dmac0_ns__CSR6 = 32'h00000000;
+parameter mask_dmac0_ns__CSR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC6 = 32'hF8004134;
+parameter val_dmac0_ns__CPC6 = 32'h00000000;
+parameter mask_dmac0_ns__CPC6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR7 = 32'hF8004138;
+parameter val_dmac0_ns__CSR7 = 32'h00000000;
+parameter mask_dmac0_ns__CSR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC7 = 32'hF800413C;
+parameter val_dmac0_ns__CPC7 = 32'h00000000;
+parameter mask_dmac0_ns__CPC7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR0 = 32'hF8004400;
+parameter val_dmac0_ns__SAR0 = 32'h00000000;
+parameter mask_dmac0_ns__SAR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR0 = 32'hF8004404;
+parameter val_dmac0_ns__DAR0 = 32'h00000000;
+parameter mask_dmac0_ns__DAR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR0 = 32'hF8004408;
+parameter val_dmac0_ns__CCR0 = 32'h00000000;
+parameter mask_dmac0_ns__CCR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_0 = 32'hF800440C;
+parameter val_dmac0_ns__LC0_0 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_0 = 32'hF8004410;
+parameter val_dmac0_ns__LC1_0 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR1 = 32'hF8004420;
+parameter val_dmac0_ns__SAR1 = 32'h00000000;
+parameter mask_dmac0_ns__SAR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR1 = 32'hF8004424;
+parameter val_dmac0_ns__DAR1 = 32'h00000000;
+parameter mask_dmac0_ns__DAR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR1 = 32'hF8004428;
+parameter val_dmac0_ns__CCR1 = 32'h00000000;
+parameter mask_dmac0_ns__CCR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_1 = 32'hF800442C;
+parameter val_dmac0_ns__LC0_1 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_1 = 32'hF8004430;
+parameter val_dmac0_ns__LC1_1 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR2 = 32'hF8004440;
+parameter val_dmac0_ns__SAR2 = 32'h00000000;
+parameter mask_dmac0_ns__SAR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR2 = 32'hF8004444;
+parameter val_dmac0_ns__DAR2 = 32'h00000000;
+parameter mask_dmac0_ns__DAR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR2 = 32'hF8004448;
+parameter val_dmac0_ns__CCR2 = 32'h00000000;
+parameter mask_dmac0_ns__CCR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_2 = 32'hF800444C;
+parameter val_dmac0_ns__LC0_2 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_2 = 32'hF8004450;
+parameter val_dmac0_ns__LC1_2 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR3 = 32'hF8004460;
+parameter val_dmac0_ns__SAR3 = 32'h00000000;
+parameter mask_dmac0_ns__SAR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR3 = 32'hF8004464;
+parameter val_dmac0_ns__DAR3 = 32'h00000000;
+parameter mask_dmac0_ns__DAR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR3 = 32'hF8004468;
+parameter val_dmac0_ns__CCR3 = 32'h00000000;
+parameter mask_dmac0_ns__CCR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_3 = 32'hF800446C;
+parameter val_dmac0_ns__LC0_3 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_3 = 32'hF8004470;
+parameter val_dmac0_ns__LC1_3 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR4 = 32'hF8004480;
+parameter val_dmac0_ns__SAR4 = 32'h00000000;
+parameter mask_dmac0_ns__SAR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR4 = 32'hF8004484;
+parameter val_dmac0_ns__DAR4 = 32'h00000000;
+parameter mask_dmac0_ns__DAR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR4 = 32'hF8004488;
+parameter val_dmac0_ns__CCR4 = 32'h00000000;
+parameter mask_dmac0_ns__CCR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_4 = 32'hF800448C;
+parameter val_dmac0_ns__LC0_4 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_4 = 32'hF8004490;
+parameter val_dmac0_ns__LC1_4 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR5 = 32'hF80044A0;
+parameter val_dmac0_ns__SAR5 = 32'h00000000;
+parameter mask_dmac0_ns__SAR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR5 = 32'hF80044A4;
+parameter val_dmac0_ns__DAR5 = 32'h00000000;
+parameter mask_dmac0_ns__DAR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR5 = 32'hF80044A8;
+parameter val_dmac0_ns__CCR5 = 32'h00000000;
+parameter mask_dmac0_ns__CCR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_5 = 32'hF80044AC;
+parameter val_dmac0_ns__LC0_5 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_5 = 32'hF80044B0;
+parameter val_dmac0_ns__LC1_5 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR6 = 32'hF80044C0;
+parameter val_dmac0_ns__SAR6 = 32'h00000000;
+parameter mask_dmac0_ns__SAR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR6 = 32'hF80044C4;
+parameter val_dmac0_ns__DAR6 = 32'h00000000;
+parameter mask_dmac0_ns__DAR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR6 = 32'hF80044C8;
+parameter val_dmac0_ns__CCR6 = 32'h00000000;
+parameter mask_dmac0_ns__CCR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_6 = 32'hF80044CC;
+parameter val_dmac0_ns__LC0_6 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_6 = 32'hF80044D0;
+parameter val_dmac0_ns__LC1_6 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR7 = 32'hF80044E0;
+parameter val_dmac0_ns__SAR7 = 32'h00000000;
+parameter mask_dmac0_ns__SAR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR7 = 32'hF80044E4;
+parameter val_dmac0_ns__DAR7 = 32'h00000000;
+parameter mask_dmac0_ns__DAR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR7 = 32'hF80044E8;
+parameter val_dmac0_ns__CCR7 = 32'h00000000;
+parameter mask_dmac0_ns__CCR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_7 = 32'hF80044EC;
+parameter val_dmac0_ns__LC0_7 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_7 = 32'hF80044F0;
+parameter val_dmac0_ns__LC1_7 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DBGSTATUS = 32'hF8004D00;
+parameter val_dmac0_ns__DBGSTATUS = 32'h00000000;
+parameter mask_dmac0_ns__DBGSTATUS = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DBGCMD = 32'hF8004D04;
+parameter val_dmac0_ns__DBGCMD = 32'h00000000;
+parameter mask_dmac0_ns__DBGCMD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DBGINST0 = 32'hF8004D08;
+parameter val_dmac0_ns__DBGINST0 = 32'h00000000;
+parameter mask_dmac0_ns__DBGINST0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DBGINST1 = 32'hF8004D0C;
+parameter val_dmac0_ns__DBGINST1 = 32'h00000000;
+parameter mask_dmac0_ns__DBGINST1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR0 = 32'hF8004E00;
+parameter val_dmac0_ns__CR0 = 32'h00000000;
+parameter mask_dmac0_ns__CR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR1 = 32'hF8004E04;
+parameter val_dmac0_ns__CR1 = 32'h00000000;
+parameter mask_dmac0_ns__CR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR2 = 32'hF8004E08;
+parameter val_dmac0_ns__CR2 = 32'h00000000;
+parameter mask_dmac0_ns__CR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR3 = 32'hF8004E0C;
+parameter val_dmac0_ns__CR3 = 32'h00000000;
+parameter mask_dmac0_ns__CR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR4 = 32'hF8004E10;
+parameter val_dmac0_ns__CR4 = 32'h00000000;
+parameter mask_dmac0_ns__CR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CRD = 32'hF8004E14;
+parameter val_dmac0_ns__CRD = 32'h00000000;
+parameter mask_dmac0_ns__CRD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__WD = 32'hF8004E80;
+parameter val_dmac0_ns__WD = 32'h00000000;
+parameter mask_dmac0_ns__WD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__periph_id_0 = 32'hF8004FE0;
+parameter val_dmac0_ns__periph_id_0 = 32'h00000000;
+parameter mask_dmac0_ns__periph_id_0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__periph_id_1 = 32'hF8004FE4;
+parameter val_dmac0_ns__periph_id_1 = 32'h00000000;
+parameter mask_dmac0_ns__periph_id_1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__periph_id_2 = 32'hF8004FE8;
+parameter val_dmac0_ns__periph_id_2 = 32'h00000000;
+parameter mask_dmac0_ns__periph_id_2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__periph_id_3 = 32'hF8004FEC;
+parameter val_dmac0_ns__periph_id_3 = 32'h00000000;
+parameter mask_dmac0_ns__periph_id_3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__pcell_id_0 = 32'hF8004FF0;
+parameter val_dmac0_ns__pcell_id_0 = 32'h00000000;
+parameter mask_dmac0_ns__pcell_id_0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__pcell_id_1 = 32'hF8004FF4;
+parameter val_dmac0_ns__pcell_id_1 = 32'h00000000;
+parameter mask_dmac0_ns__pcell_id_1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__pcell_id_2 = 32'hF8004FF8;
+parameter val_dmac0_ns__pcell_id_2 = 32'h00000000;
+parameter mask_dmac0_ns__pcell_id_2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__pcell_id_3 = 32'hF8004FFC;
+parameter val_dmac0_ns__pcell_id_3 = 32'h00000000;
+parameter mask_dmac0_ns__pcell_id_3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module dmac0_s dmac
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter dmac0_s__DSR = 32'hF8003000;
+parameter val_dmac0_s__DSR = 32'h00000000;
+parameter mask_dmac0_s__DSR = 32'hFFFFFFFF;
+
+parameter dmac0_s__DPC = 32'hF8003004;
+parameter val_dmac0_s__DPC = 32'h00000000;
+parameter mask_dmac0_s__DPC = 32'hFFFFFFFF;
+
+parameter dmac0_s__INTEN = 32'hF8003020;
+parameter val_dmac0_s__INTEN = 32'h00000000;
+parameter mask_dmac0_s__INTEN = 32'hFFFFFFFF;
+
+parameter dmac0_s__INT_EVENT_RIS = 32'hF8003024;
+parameter val_dmac0_s__INT_EVENT_RIS = 32'h00000000;
+parameter mask_dmac0_s__INT_EVENT_RIS = 32'hFFFFFFFF;
+
+parameter dmac0_s__INTMIS = 32'hF8003028;
+parameter val_dmac0_s__INTMIS = 32'h00000000;
+parameter mask_dmac0_s__INTMIS = 32'hFFFFFFFF;
+
+parameter dmac0_s__INTCLR = 32'hF800302C;
+parameter val_dmac0_s__INTCLR = 32'h00000000;
+parameter mask_dmac0_s__INTCLR = 32'hFFFFFFFF;
+
+parameter dmac0_s__FSRD = 32'hF8003030;
+parameter val_dmac0_s__FSRD = 32'h00000000;
+parameter mask_dmac0_s__FSRD = 32'hFFFFFFFF;
+
+parameter dmac0_s__FSRC = 32'hF8003034;
+parameter val_dmac0_s__FSRC = 32'h00000000;
+parameter mask_dmac0_s__FSRC = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTRD = 32'hF8003038;
+parameter val_dmac0_s__FTRD = 32'h00000000;
+parameter mask_dmac0_s__FTRD = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR0 = 32'hF8003040;
+parameter val_dmac0_s__FTR0 = 32'h00000000;
+parameter mask_dmac0_s__FTR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR1 = 32'hF8003044;
+parameter val_dmac0_s__FTR1 = 32'h00000000;
+parameter mask_dmac0_s__FTR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR2 = 32'hF8003048;
+parameter val_dmac0_s__FTR2 = 32'h00000000;
+parameter mask_dmac0_s__FTR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR3 = 32'hF800304C;
+parameter val_dmac0_s__FTR3 = 32'h00000000;
+parameter mask_dmac0_s__FTR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR4 = 32'hF8003050;
+parameter val_dmac0_s__FTR4 = 32'h00000000;
+parameter mask_dmac0_s__FTR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR5 = 32'hF8003054;
+parameter val_dmac0_s__FTR5 = 32'h00000000;
+parameter mask_dmac0_s__FTR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR6 = 32'hF8003058;
+parameter val_dmac0_s__FTR6 = 32'h00000000;
+parameter mask_dmac0_s__FTR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR7 = 32'hF800305C;
+parameter val_dmac0_s__FTR7 = 32'h00000000;
+parameter mask_dmac0_s__FTR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR0 = 32'hF8003100;
+parameter val_dmac0_s__CSR0 = 32'h00000000;
+parameter mask_dmac0_s__CSR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC0 = 32'hF8003104;
+parameter val_dmac0_s__CPC0 = 32'h00000000;
+parameter mask_dmac0_s__CPC0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR1 = 32'hF8003108;
+parameter val_dmac0_s__CSR1 = 32'h00000000;
+parameter mask_dmac0_s__CSR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC1 = 32'hF800310C;
+parameter val_dmac0_s__CPC1 = 32'h00000000;
+parameter mask_dmac0_s__CPC1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR2 = 32'hF8003110;
+parameter val_dmac0_s__CSR2 = 32'h00000000;
+parameter mask_dmac0_s__CSR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC2 = 32'hF8003114;
+parameter val_dmac0_s__CPC2 = 32'h00000000;
+parameter mask_dmac0_s__CPC2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR3 = 32'hF8003118;
+parameter val_dmac0_s__CSR3 = 32'h00000000;
+parameter mask_dmac0_s__CSR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC3 = 32'hF800311C;
+parameter val_dmac0_s__CPC3 = 32'h00000000;
+parameter mask_dmac0_s__CPC3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR4 = 32'hF8003120;
+parameter val_dmac0_s__CSR4 = 32'h00000000;
+parameter mask_dmac0_s__CSR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC4 = 32'hF8003124;
+parameter val_dmac0_s__CPC4 = 32'h00000000;
+parameter mask_dmac0_s__CPC4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR5 = 32'hF8003128;
+parameter val_dmac0_s__CSR5 = 32'h00000000;
+parameter mask_dmac0_s__CSR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC5 = 32'hF800312C;
+parameter val_dmac0_s__CPC5 = 32'h00000000;
+parameter mask_dmac0_s__CPC5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR6 = 32'hF8003130;
+parameter val_dmac0_s__CSR6 = 32'h00000000;
+parameter mask_dmac0_s__CSR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC6 = 32'hF8003134;
+parameter val_dmac0_s__CPC6 = 32'h00000000;
+parameter mask_dmac0_s__CPC6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR7 = 32'hF8003138;
+parameter val_dmac0_s__CSR7 = 32'h00000000;
+parameter mask_dmac0_s__CSR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC7 = 32'hF800313C;
+parameter val_dmac0_s__CPC7 = 32'h00000000;
+parameter mask_dmac0_s__CPC7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR0 = 32'hF8003400;
+parameter val_dmac0_s__SAR0 = 32'h00000000;
+parameter mask_dmac0_s__SAR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR0 = 32'hF8003404;
+parameter val_dmac0_s__DAR0 = 32'h00000000;
+parameter mask_dmac0_s__DAR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR0 = 32'hF8003408;
+parameter val_dmac0_s__CCR0 = 32'h00800200;
+parameter mask_dmac0_s__CCR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_0 = 32'hF800340C;
+parameter val_dmac0_s__LC0_0 = 32'h00000000;
+parameter mask_dmac0_s__LC0_0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_0 = 32'hF8003410;
+parameter val_dmac0_s__LC1_0 = 32'h00000000;
+parameter mask_dmac0_s__LC1_0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR1 = 32'hF8003420;
+parameter val_dmac0_s__SAR1 = 32'h00000000;
+parameter mask_dmac0_s__SAR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR1 = 32'hF8003424;
+parameter val_dmac0_s__DAR1 = 32'h00000000;
+parameter mask_dmac0_s__DAR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR1 = 32'hF8003428;
+parameter val_dmac0_s__CCR1 = 32'h00800200;
+parameter mask_dmac0_s__CCR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_1 = 32'hF800342C;
+parameter val_dmac0_s__LC0_1 = 32'h00000000;
+parameter mask_dmac0_s__LC0_1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_1 = 32'hF8003430;
+parameter val_dmac0_s__LC1_1 = 32'h00000000;
+parameter mask_dmac0_s__LC1_1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR2 = 32'hF8003440;
+parameter val_dmac0_s__SAR2 = 32'h00000000;
+parameter mask_dmac0_s__SAR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR2 = 32'hF8003444;
+parameter val_dmac0_s__DAR2 = 32'h00000000;
+parameter mask_dmac0_s__DAR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR2 = 32'hF8003448;
+parameter val_dmac0_s__CCR2 = 32'h00800200;
+parameter mask_dmac0_s__CCR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_2 = 32'hF800344C;
+parameter val_dmac0_s__LC0_2 = 32'h00000000;
+parameter mask_dmac0_s__LC0_2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_2 = 32'hF8003450;
+parameter val_dmac0_s__LC1_2 = 32'h00000000;
+parameter mask_dmac0_s__LC1_2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR3 = 32'hF8003460;
+parameter val_dmac0_s__SAR3 = 32'h00000000;
+parameter mask_dmac0_s__SAR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR3 = 32'hF8003464;
+parameter val_dmac0_s__DAR3 = 32'h00000000;
+parameter mask_dmac0_s__DAR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR3 = 32'hF8003468;
+parameter val_dmac0_s__CCR3 = 32'h00800200;
+parameter mask_dmac0_s__CCR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_3 = 32'hF800346C;
+parameter val_dmac0_s__LC0_3 = 32'h00000000;
+parameter mask_dmac0_s__LC0_3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_3 = 32'hF8003470;
+parameter val_dmac0_s__LC1_3 = 32'h00000000;
+parameter mask_dmac0_s__LC1_3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR4 = 32'hF8003480;
+parameter val_dmac0_s__SAR4 = 32'h00000000;
+parameter mask_dmac0_s__SAR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR4 = 32'hF8003484;
+parameter val_dmac0_s__DAR4 = 32'h00000000;
+parameter mask_dmac0_s__DAR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR4 = 32'hF8003488;
+parameter val_dmac0_s__CCR4 = 32'h00800200;
+parameter mask_dmac0_s__CCR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_4 = 32'hF800348C;
+parameter val_dmac0_s__LC0_4 = 32'h00000000;
+parameter mask_dmac0_s__LC0_4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_4 = 32'hF8003490;
+parameter val_dmac0_s__LC1_4 = 32'h00000000;
+parameter mask_dmac0_s__LC1_4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR5 = 32'hF80034A0;
+parameter val_dmac0_s__SAR5 = 32'h00000000;
+parameter mask_dmac0_s__SAR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR5 = 32'hF80034A4;
+parameter val_dmac0_s__DAR5 = 32'h00000000;
+parameter mask_dmac0_s__DAR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR5 = 32'hF80034A8;
+parameter val_dmac0_s__CCR5 = 32'h00800200;
+parameter mask_dmac0_s__CCR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_5 = 32'hF80034AC;
+parameter val_dmac0_s__LC0_5 = 32'h00000000;
+parameter mask_dmac0_s__LC0_5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_5 = 32'hF80034B0;
+parameter val_dmac0_s__LC1_5 = 32'h00000000;
+parameter mask_dmac0_s__LC1_5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR6 = 32'hF80034C0;
+parameter val_dmac0_s__SAR6 = 32'h00000000;
+parameter mask_dmac0_s__SAR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR6 = 32'hF80034C4;
+parameter val_dmac0_s__DAR6 = 32'h00000000;
+parameter mask_dmac0_s__DAR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR6 = 32'hF80034C8;
+parameter val_dmac0_s__CCR6 = 32'h00800200;
+parameter mask_dmac0_s__CCR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_6 = 32'hF80034CC;
+parameter val_dmac0_s__LC0_6 = 32'h00000000;
+parameter mask_dmac0_s__LC0_6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_6 = 32'hF80034D0;
+parameter val_dmac0_s__LC1_6 = 32'h00000000;
+parameter mask_dmac0_s__LC1_6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR7 = 32'hF80034E0;
+parameter val_dmac0_s__SAR7 = 32'h00000000;
+parameter mask_dmac0_s__SAR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR7 = 32'hF80034E4;
+parameter val_dmac0_s__DAR7 = 32'h00000000;
+parameter mask_dmac0_s__DAR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR7 = 32'hF80034E8;
+parameter val_dmac0_s__CCR7 = 32'h00800200;
+parameter mask_dmac0_s__CCR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_7 = 32'hF80034EC;
+parameter val_dmac0_s__LC0_7 = 32'h00000000;
+parameter mask_dmac0_s__LC0_7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_7 = 32'hF80034F0;
+parameter val_dmac0_s__LC1_7 = 32'h00000000;
+parameter mask_dmac0_s__LC1_7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DBGSTATUS = 32'hF8003D00;
+parameter val_dmac0_s__DBGSTATUS = 32'h00000000;
+parameter mask_dmac0_s__DBGSTATUS = 32'hFFFFFFFF;
+
+parameter dmac0_s__DBGCMD = 32'hF8003D04;
+parameter val_dmac0_s__DBGCMD = 32'h00000000;
+parameter mask_dmac0_s__DBGCMD = 32'hFFFFFFFF;
+
+parameter dmac0_s__DBGINST0 = 32'hF8003D08;
+parameter val_dmac0_s__DBGINST0 = 32'h00000000;
+parameter mask_dmac0_s__DBGINST0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DBGINST1 = 32'hF8003D0C;
+parameter val_dmac0_s__DBGINST1 = 32'h00000000;
+parameter mask_dmac0_s__DBGINST1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR0 = 32'hF8003E00;
+parameter val_dmac0_s__CR0 = 32'h001E3071;
+parameter mask_dmac0_s__CR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR1 = 32'hF8003E04;
+parameter val_dmac0_s__CR1 = 32'h00000074;
+parameter mask_dmac0_s__CR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR2 = 32'hF8003E08;
+parameter val_dmac0_s__CR2 = 32'h00000000;
+parameter mask_dmac0_s__CR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR3 = 32'hF8003E0C;
+parameter val_dmac0_s__CR3 = 32'h00000000;
+parameter mask_dmac0_s__CR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR4 = 32'hF8003E10;
+parameter val_dmac0_s__CR4 = 32'h00000000;
+parameter mask_dmac0_s__CR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CRD = 32'hF8003E14;
+parameter val_dmac0_s__CRD = 32'h07FF7F73;
+parameter mask_dmac0_s__CRD = 32'hFFFFFFFF;
+
+parameter dmac0_s__WD = 32'hF8003E80;
+parameter val_dmac0_s__WD = 32'h00000000;
+parameter mask_dmac0_s__WD = 32'hFFFFFFFF;
+
+parameter dmac0_s__periph_id_0 = 32'hF8003FE0;
+parameter val_dmac0_s__periph_id_0 = 32'h00000030;
+parameter mask_dmac0_s__periph_id_0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__periph_id_1 = 32'hF8003FE4;
+parameter val_dmac0_s__periph_id_1 = 32'h00000013;
+parameter mask_dmac0_s__periph_id_1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__periph_id_2 = 32'hF8003FE8;
+parameter val_dmac0_s__periph_id_2 = 32'h00000024;
+parameter mask_dmac0_s__periph_id_2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__periph_id_3 = 32'hF8003FEC;
+parameter val_dmac0_s__periph_id_3 = 32'h00000000;
+parameter mask_dmac0_s__periph_id_3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__pcell_id_0 = 32'hF8003FF0;
+parameter val_dmac0_s__pcell_id_0 = 32'h0000000D;
+parameter mask_dmac0_s__pcell_id_0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__pcell_id_1 = 32'hF8003FF4;
+parameter val_dmac0_s__pcell_id_1 = 32'h000000F0;
+parameter mask_dmac0_s__pcell_id_1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__pcell_id_2 = 32'hF8003FF8;
+parameter val_dmac0_s__pcell_id_2 = 32'h00000005;
+parameter mask_dmac0_s__pcell_id_2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__pcell_id_3 = 32'hF8003FFC;
+parameter val_dmac0_s__pcell_id_3 = 32'h000000B1;
+parameter mask_dmac0_s__pcell_id_3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module efuse_ctrl efuse_ctrl
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter efuse_ctrl__WR_LOCK = 32'hF800D000;
+parameter val_efuse_ctrl__WR_LOCK = 32'h00000000;
+parameter mask_efuse_ctrl__WR_LOCK = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__WR_UNLOCK = 32'hF800D004;
+parameter val_efuse_ctrl__WR_UNLOCK = 32'h00000000;
+parameter mask_efuse_ctrl__WR_UNLOCK = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__WR_LOCKSTA = 32'hF800D008;
+parameter val_efuse_ctrl__WR_LOCKSTA = 32'h00000001;
+parameter mask_efuse_ctrl__WR_LOCKSTA = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__CFG = 32'hF800D00C;
+parameter val_efuse_ctrl__CFG = 32'h00010F00;
+parameter mask_efuse_ctrl__CFG = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__STATUS = 32'hF800D010;
+parameter val_efuse_ctrl__STATUS = 32'h00100000;
+parameter mask_efuse_ctrl__STATUS = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__CONTROL = 32'hF800D014;
+parameter val_efuse_ctrl__CONTROL = 32'h00000003;
+parameter mask_efuse_ctrl__CONTROL = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__PGM_STBW = 32'hF800D018;
+parameter val_efuse_ctrl__PGM_STBW = 32'h000002D0;
+parameter mask_efuse_ctrl__PGM_STBW = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__RD_STBW = 32'hF800D01C;
+parameter val_efuse_ctrl__RD_STBW = 32'h0000000B;
+parameter mask_efuse_ctrl__RD_STBW = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module gem0 GEM
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gem0__net_ctrl = 32'hE000B000;
+parameter val_gem0__net_ctrl = 32'h00000000;
+parameter mask_gem0__net_ctrl = 32'hFFFFFFFF;
+
+parameter gem0__net_cfg = 32'hE000B004;
+parameter val_gem0__net_cfg = 32'h00080000;
+parameter mask_gem0__net_cfg = 32'hFFFFFFFF;
+
+parameter gem0__net_status = 32'hE000B008;
+parameter val_gem0__net_status = 32'h00000004;
+parameter mask_gem0__net_status = 32'hFFFFFFFD;
+
+parameter gem0__user_io = 32'hE000B00C;
+parameter val_gem0__user_io = 32'h00000000;
+parameter mask_gem0__user_io = 32'h0000FFFF;
+
+parameter gem0__dma_cfg = 32'hE000B010;
+parameter val_gem0__dma_cfg = 32'h00020784;
+parameter mask_gem0__dma_cfg = 32'hFFFFFFFF;
+
+parameter gem0__tx_status = 32'hE000B014;
+parameter val_gem0__tx_status = 32'h00000000;
+parameter mask_gem0__tx_status = 32'hFFFFFFFF;
+
+parameter gem0__rx_qbar = 32'hE000B018;
+parameter val_gem0__rx_qbar = 32'h00000000;
+parameter mask_gem0__rx_qbar = 32'hFFFFFFFF;
+
+parameter gem0__tx_qbar = 32'hE000B01C;
+parameter val_gem0__tx_qbar = 32'h00000000;
+parameter mask_gem0__tx_qbar = 32'hFFFFFFFF;
+
+parameter gem0__rx_status = 32'hE000B020;
+parameter val_gem0__rx_status = 32'h00000000;
+parameter mask_gem0__rx_status = 32'hFFFFFFFF;
+
+parameter gem0__intr_status = 32'hE000B024;
+parameter val_gem0__intr_status = 32'h00000000;
+parameter mask_gem0__intr_status = 32'hFFFFFFFF;
+
+parameter gem0__intr_en = 32'hE000B028;
+parameter val_gem0__intr_en = 32'h00000000;
+parameter mask_gem0__intr_en = 32'h00000000;
+
+parameter gem0__intr_dis = 32'hE000B02C;
+parameter val_gem0__intr_dis = 32'h00000000;
+parameter mask_gem0__intr_dis = 32'h00000000;
+
+parameter gem0__intr_mask = 32'hE000B030;
+parameter val_gem0__intr_mask = 32'h0001FFFF;
+parameter mask_gem0__intr_mask = 32'hFC01FFFF;
+
+parameter gem0__phy_maint = 32'hE000B034;
+parameter val_gem0__phy_maint = 32'h00000000;
+parameter mask_gem0__phy_maint = 32'hFFFFFFFF;
+
+parameter gem0__rx_pauseq = 32'hE000B038;
+parameter val_gem0__rx_pauseq = 32'h00000000;
+parameter mask_gem0__rx_pauseq = 32'hFFFFFFFF;
+
+parameter gem0__tx_pauseq = 32'hE000B03C;
+parameter val_gem0__tx_pauseq = 32'h0000FFFF;
+parameter mask_gem0__tx_pauseq = 32'hFFFFFFFF;
+
+parameter gem0__tx_partial_st_fwd = 32'hE000B040;
+parameter val_gem0__tx_partial_st_fwd = 32'h000003FF;
+parameter mask_gem0__tx_partial_st_fwd = 32'hFFFFFFFF;
+
+parameter gem0__rx_partial_st_fwd = 32'hE000B044;
+parameter val_gem0__rx_partial_st_fwd = 32'h000003FF;
+parameter mask_gem0__rx_partial_st_fwd = 32'hFFFFFFFF;
+
+parameter gem0__hash_bot = 32'hE000B080;
+parameter val_gem0__hash_bot = 32'h00000000;
+parameter mask_gem0__hash_bot = 32'hFFFFFFFF;
+
+parameter gem0__hash_top = 32'hE000B084;
+parameter val_gem0__hash_top = 32'h00000000;
+parameter mask_gem0__hash_top = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr1_bot = 32'hE000B088;
+parameter val_gem0__spec_addr1_bot = 32'h00000000;
+parameter mask_gem0__spec_addr1_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr1_top = 32'hE000B08C;
+parameter val_gem0__spec_addr1_top = 32'h00000000;
+parameter mask_gem0__spec_addr1_top = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr2_bot = 32'hE000B090;
+parameter val_gem0__spec_addr2_bot = 32'h00000000;
+parameter mask_gem0__spec_addr2_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr2_top = 32'hE000B094;
+parameter val_gem0__spec_addr2_top = 32'h00000000;
+parameter mask_gem0__spec_addr2_top = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr3_bot = 32'hE000B098;
+parameter val_gem0__spec_addr3_bot = 32'h00000000;
+parameter mask_gem0__spec_addr3_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr3_top = 32'hE000B09C;
+parameter val_gem0__spec_addr3_top = 32'h00000000;
+parameter mask_gem0__spec_addr3_top = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr4_bot = 32'hE000B0A0;
+parameter val_gem0__spec_addr4_bot = 32'h00000000;
+parameter mask_gem0__spec_addr4_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr4_top = 32'hE000B0A4;
+parameter val_gem0__spec_addr4_top = 32'h00000000;
+parameter mask_gem0__spec_addr4_top = 32'hFFFFFFFF;
+
+parameter gem0__type_id_match1 = 32'hE000B0A8;
+parameter val_gem0__type_id_match1 = 32'h00000000;
+parameter mask_gem0__type_id_match1 = 32'hFFFFFFFF;
+
+parameter gem0__type_id_match2 = 32'hE000B0AC;
+parameter val_gem0__type_id_match2 = 32'h00000000;
+parameter mask_gem0__type_id_match2 = 32'hFFFFFFFF;
+
+parameter gem0__type_id_match3 = 32'hE000B0B0;
+parameter val_gem0__type_id_match3 = 32'h00000000;
+parameter mask_gem0__type_id_match3 = 32'hFFFFFFFF;
+
+parameter gem0__type_id_match4 = 32'hE000B0B4;
+parameter val_gem0__type_id_match4 = 32'h00000000;
+parameter mask_gem0__type_id_match4 = 32'hFFFFFFFF;
+
+parameter gem0__wake_on_lan = 32'hE000B0B8;
+parameter val_gem0__wake_on_lan = 32'h00000000;
+parameter mask_gem0__wake_on_lan = 32'hFFFFFFFF;
+
+parameter gem0__ipg_stretch = 32'hE000B0BC;
+parameter val_gem0__ipg_stretch = 32'h00000000;
+parameter mask_gem0__ipg_stretch = 32'hFFFFFFFF;
+
+parameter gem0__stacked_vlan = 32'hE000B0C0;
+parameter val_gem0__stacked_vlan = 32'h00000000;
+parameter mask_gem0__stacked_vlan = 32'hFFFFFFFF;
+
+parameter gem0__tx_pfc_pause = 32'hE000B0C4;
+parameter val_gem0__tx_pfc_pause = 32'h00000000;
+parameter mask_gem0__tx_pfc_pause = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr1_mask_bot = 32'hE000B0C8;
+parameter val_gem0__spec_addr1_mask_bot = 32'h00000000;
+parameter mask_gem0__spec_addr1_mask_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr1_mask_top = 32'hE000B0CC;
+parameter val_gem0__spec_addr1_mask_top = 32'h00000000;
+parameter mask_gem0__spec_addr1_mask_top = 32'hFFFFFFFF;
+
+parameter gem0__module_id = 32'hE000B0FC;
+parameter val_gem0__module_id = 32'h00020118;
+parameter mask_gem0__module_id = 32'hFFFFFFFF;
+
+parameter gem0__octets_tx_bot = 32'hE000B100;
+parameter val_gem0__octets_tx_bot = 32'h00000000;
+parameter mask_gem0__octets_tx_bot = 32'hFFFFFFFF;
+
+parameter gem0__octets_tx_top = 32'hE000B104;
+parameter val_gem0__octets_tx_top = 32'h00000000;
+parameter mask_gem0__octets_tx_top = 32'hFFFFFFFF;
+
+parameter gem0__frames_tx = 32'hE000B108;
+parameter val_gem0__frames_tx = 32'h00000000;
+parameter mask_gem0__frames_tx = 32'hFFFFFFFF;
+
+parameter gem0__broadcast_frames_tx = 32'hE000B10C;
+parameter val_gem0__broadcast_frames_tx = 32'h00000000;
+parameter mask_gem0__broadcast_frames_tx = 32'hFFFFFFFF;
+
+parameter gem0__multi_frames_tx = 32'hE000B110;
+parameter val_gem0__multi_frames_tx = 32'h00000000;
+parameter mask_gem0__multi_frames_tx = 32'hFFFFFFFF;
+
+parameter gem0__pause_frames_tx = 32'hE000B114;
+parameter val_gem0__pause_frames_tx = 32'h00000000;
+parameter mask_gem0__pause_frames_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_64b_tx = 32'hE000B118;
+parameter val_gem0__frames_64b_tx = 32'h00000000;
+parameter mask_gem0__frames_64b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_65to127b_tx = 32'hE000B11C;
+parameter val_gem0__frames_65to127b_tx = 32'h00000000;
+parameter mask_gem0__frames_65to127b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_128to255b_tx = 32'hE000B120;
+parameter val_gem0__frames_128to255b_tx = 32'h00000000;
+parameter mask_gem0__frames_128to255b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_256to511b_tx = 32'hE000B124;
+parameter val_gem0__frames_256to511b_tx = 32'h00000000;
+parameter mask_gem0__frames_256to511b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_512to1023b_tx = 32'hE000B128;
+parameter val_gem0__frames_512to1023b_tx = 32'h00000000;
+parameter mask_gem0__frames_512to1023b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_1024to1518b_tx = 32'hE000B12C;
+parameter val_gem0__frames_1024to1518b_tx = 32'h00000000;
+parameter mask_gem0__frames_1024to1518b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_gt1518b_tx = 32'hE000B130;
+parameter val_gem0__frames_gt1518b_tx = 32'h00000000;
+parameter mask_gem0__frames_gt1518b_tx = 32'hFFFFFFFF;
+
+parameter gem0__tx_under_runs = 32'hE000B134;
+parameter val_gem0__tx_under_runs = 32'h00000000;
+parameter mask_gem0__tx_under_runs = 32'hFFFFFFFF;
+
+parameter gem0__single_collisn_frames = 32'hE000B138;
+parameter val_gem0__single_collisn_frames = 32'h00000000;
+parameter mask_gem0__single_collisn_frames = 32'hFFFFFFFF;
+
+parameter gem0__multi_collisn_frames = 32'hE000B13C;
+parameter val_gem0__multi_collisn_frames = 32'h00000000;
+parameter mask_gem0__multi_collisn_frames = 32'hFFFFFFFF;
+
+parameter gem0__excessive_collisns = 32'hE000B140;
+parameter val_gem0__excessive_collisns = 32'h00000000;
+parameter mask_gem0__excessive_collisns = 32'hFFFFFFFF;
+
+parameter gem0__late_collisns = 32'hE000B144;
+parameter val_gem0__late_collisns = 32'h00000000;
+parameter mask_gem0__late_collisns = 32'hFFFFFFFF;
+
+parameter gem0__deferred_tx_frames = 32'hE000B148;
+parameter val_gem0__deferred_tx_frames = 32'h00000000;
+parameter mask_gem0__deferred_tx_frames = 32'hFFFFFFFF;
+
+parameter gem0__carrier_sense_errs = 32'hE000B14C;
+parameter val_gem0__carrier_sense_errs = 32'h00000000;
+parameter mask_gem0__carrier_sense_errs = 32'hFFFFFFFF;
+
+parameter gem0__octets_rx_bot = 32'hE000B150;
+parameter val_gem0__octets_rx_bot = 32'h00000000;
+parameter mask_gem0__octets_rx_bot = 32'hFFFFFFFF;
+
+parameter gem0__octets_rx_top = 32'hE000B154;
+parameter val_gem0__octets_rx_top = 32'h00000000;
+parameter mask_gem0__octets_rx_top = 32'hFFFFFFFF;
+
+parameter gem0__frames_rx = 32'hE000B158;
+parameter val_gem0__frames_rx = 32'h00000000;
+parameter mask_gem0__frames_rx = 32'hFFFFFFFF;
+
+parameter gem0__bdcast_fames_rx = 32'hE000B15C;
+parameter val_gem0__bdcast_fames_rx = 32'h00000000;
+parameter mask_gem0__bdcast_fames_rx = 32'hFFFFFFFF;
+
+parameter gem0__multi_frames_rx = 32'hE000B160;
+parameter val_gem0__multi_frames_rx = 32'h00000000;
+parameter mask_gem0__multi_frames_rx = 32'hFFFFFFFF;
+
+parameter gem0__pause_rx = 32'hE000B164;
+parameter val_gem0__pause_rx = 32'h00000000;
+parameter mask_gem0__pause_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_64b_rx = 32'hE000B168;
+parameter val_gem0__frames_64b_rx = 32'h00000000;
+parameter mask_gem0__frames_64b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_65to127b_rx = 32'hE000B16C;
+parameter val_gem0__frames_65to127b_rx = 32'h00000000;
+parameter mask_gem0__frames_65to127b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_128to255b_rx = 32'hE000B170;
+parameter val_gem0__frames_128to255b_rx = 32'h00000000;
+parameter mask_gem0__frames_128to255b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_256to511b_rx = 32'hE000B174;
+parameter val_gem0__frames_256to511b_rx = 32'h00000000;
+parameter mask_gem0__frames_256to511b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_512to1023b_rx = 32'hE000B178;
+parameter val_gem0__frames_512to1023b_rx = 32'h00000000;
+parameter mask_gem0__frames_512to1023b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_1024to1518b_rx = 32'hE000B17C;
+parameter val_gem0__frames_1024to1518b_rx = 32'h00000000;
+parameter mask_gem0__frames_1024to1518b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_gt1518b_rx = 32'hE000B180;
+parameter val_gem0__frames_gt1518b_rx = 32'h00000000;
+parameter mask_gem0__frames_gt1518b_rx = 32'hFFFFFFFF;
+
+parameter gem0__undersz_rx = 32'hE000B184;
+parameter val_gem0__undersz_rx = 32'h00000000;
+parameter mask_gem0__undersz_rx = 32'hFFFFFFFF;
+
+parameter gem0__oversz_rx = 32'hE000B188;
+parameter val_gem0__oversz_rx = 32'h00000000;
+parameter mask_gem0__oversz_rx = 32'hFFFFFFFF;
+
+parameter gem0__jab_rx = 32'hE000B18C;
+parameter val_gem0__jab_rx = 32'h00000000;
+parameter mask_gem0__jab_rx = 32'hFFFFFFFF;
+
+parameter gem0__fcs_errors = 32'hE000B190;
+parameter val_gem0__fcs_errors = 32'h00000000;
+parameter mask_gem0__fcs_errors = 32'hFFFFFFFF;
+
+parameter gem0__length_field_errors = 32'hE000B194;
+parameter val_gem0__length_field_errors = 32'h00000000;
+parameter mask_gem0__length_field_errors = 32'hFFFFFFFF;
+
+parameter gem0__rx_symbol_errors = 32'hE000B198;
+parameter val_gem0__rx_symbol_errors = 32'h00000000;
+parameter mask_gem0__rx_symbol_errors = 32'hFFFFFFFF;
+
+parameter gem0__align_errors = 32'hE000B19C;
+parameter val_gem0__align_errors = 32'h00000000;
+parameter mask_gem0__align_errors = 32'hFFFFFFFF;
+
+parameter gem0__rx_resource_errors = 32'hE000B1A0;
+parameter val_gem0__rx_resource_errors = 32'h00000000;
+parameter mask_gem0__rx_resource_errors = 32'hFFFFFFFF;
+
+parameter gem0__rx_overrun_errors = 32'hE000B1A4;
+parameter val_gem0__rx_overrun_errors = 32'h00000000;
+parameter mask_gem0__rx_overrun_errors = 32'hFFFFFFFF;
+
+parameter gem0__ip_hdr_csum_errors = 32'hE000B1A8;
+parameter val_gem0__ip_hdr_csum_errors = 32'h00000000;
+parameter mask_gem0__ip_hdr_csum_errors = 32'hFFFFFFFF;
+
+parameter gem0__tcp_csum_errors = 32'hE000B1AC;
+parameter val_gem0__tcp_csum_errors = 32'h00000000;
+parameter mask_gem0__tcp_csum_errors = 32'hFFFFFFFF;
+
+parameter gem0__udp_csum_errors = 32'hE000B1B0;
+parameter val_gem0__udp_csum_errors = 32'h00000000;
+parameter mask_gem0__udp_csum_errors = 32'hFFFFFFFF;
+
+parameter gem0__timer_strobe_s = 32'hE000B1C8;
+parameter val_gem0__timer_strobe_s = 32'h00000000;
+parameter mask_gem0__timer_strobe_s = 32'hFFFFFFFF;
+
+parameter gem0__timer_strobe_ns = 32'hE000B1CC;
+parameter val_gem0__timer_strobe_ns = 32'h00000000;
+parameter mask_gem0__timer_strobe_ns = 32'hFFFFFFFF;
+
+parameter gem0__timer_s = 32'hE000B1D0;
+parameter val_gem0__timer_s = 32'h00000000;
+parameter mask_gem0__timer_s = 32'hFFFFFFFF;
+
+parameter gem0__timer_ns = 32'hE000B1D4;
+parameter val_gem0__timer_ns = 32'h00000000;
+parameter mask_gem0__timer_ns = 32'hFFFFFFFF;
+
+parameter gem0__timer_adjust = 32'hE000B1D8;
+parameter val_gem0__timer_adjust = 32'h00000000;
+parameter mask_gem0__timer_adjust = 32'hFFFFFFFF;
+
+parameter gem0__timer_incr = 32'hE000B1DC;
+parameter val_gem0__timer_incr = 32'h00000000;
+parameter mask_gem0__timer_incr = 32'hFFFFFFFF;
+
+parameter gem0__ptp_tx_s = 32'hE000B1E0;
+parameter val_gem0__ptp_tx_s = 32'h00000000;
+parameter mask_gem0__ptp_tx_s = 32'hFFFFFFFF;
+
+parameter gem0__ptp_tx_ns = 32'hE000B1E4;
+parameter val_gem0__ptp_tx_ns = 32'h00000000;
+parameter mask_gem0__ptp_tx_ns = 32'hFFFFFFFF;
+
+parameter gem0__ptp_rx_s = 32'hE000B1E8;
+parameter val_gem0__ptp_rx_s = 32'h00000000;
+parameter mask_gem0__ptp_rx_s = 32'hFFFFFFFF;
+
+parameter gem0__ptp_rx_ns = 32'hE000B1EC;
+parameter val_gem0__ptp_rx_ns = 32'h00000000;
+parameter mask_gem0__ptp_rx_ns = 32'hFFFFFFFF;
+
+parameter gem0__ptp_peer_tx_s = 32'hE000B1F0;
+parameter val_gem0__ptp_peer_tx_s = 32'h00000000;
+parameter mask_gem0__ptp_peer_tx_s = 32'hFFFFFFFF;
+
+parameter gem0__ptp_peer_tx_ns = 32'hE000B1F4;
+parameter val_gem0__ptp_peer_tx_ns = 32'h00000000;
+parameter mask_gem0__ptp_peer_tx_ns = 32'hFFFFFFFF;
+
+parameter gem0__ptp_peer_rx_s = 32'hE000B1F8;
+parameter val_gem0__ptp_peer_rx_s = 32'h00000000;
+parameter mask_gem0__ptp_peer_rx_s = 32'hFFFFFFFF;
+
+parameter gem0__ptp_peer_rx_ns = 32'hE000B1FC;
+parameter val_gem0__ptp_peer_rx_ns = 32'h00000000;
+parameter mask_gem0__ptp_peer_rx_ns = 32'hFFFFFFFF;
+
+parameter gem0__pcs_ctrl = 32'hE000B200;
+parameter val_gem0__pcs_ctrl = 32'h00000000;
+parameter mask_gem0__pcs_ctrl = 32'h00000000;
+
+parameter gem0__pcs_status = 32'hE000B204;
+parameter val_gem0__pcs_status = 32'h00000000;
+parameter mask_gem0__pcs_status = 32'h00000000;
+
+parameter gem0__pcs_upper_phy_id = 32'hE000B208;
+parameter val_gem0__pcs_upper_phy_id = 32'h00000000;
+parameter mask_gem0__pcs_upper_phy_id = 32'h00000000;
+
+parameter gem0__pcs_lower_phy_id = 32'hE000B20C;
+parameter val_gem0__pcs_lower_phy_id = 32'h00000000;
+parameter mask_gem0__pcs_lower_phy_id = 32'h00000000;
+
+parameter gem0__pcs_autoneg_ad = 32'hE000B210;
+parameter val_gem0__pcs_autoneg_ad = 32'h00000000;
+parameter mask_gem0__pcs_autoneg_ad = 32'h00000000;
+
+parameter gem0__pcs_autoneg_ability = 32'hE000B214;
+parameter val_gem0__pcs_autoneg_ability = 32'h00000000;
+parameter mask_gem0__pcs_autoneg_ability = 32'h00000000;
+
+parameter gem0__pcs_autonec_exp = 32'hE000B218;
+parameter val_gem0__pcs_autonec_exp = 32'h00000000;
+parameter mask_gem0__pcs_autonec_exp = 32'h00000000;
+
+parameter gem0__pcs_autoneg_next_pg = 32'hE000B21C;
+parameter val_gem0__pcs_autoneg_next_pg = 32'h00000000;
+parameter mask_gem0__pcs_autoneg_next_pg = 32'h00000000;
+
+parameter gem0__pcs_autoneg_pnext_pg = 32'hE000B220;
+parameter val_gem0__pcs_autoneg_pnext_pg = 32'h00000000;
+parameter mask_gem0__pcs_autoneg_pnext_pg = 32'h00000000;
+
+parameter gem0__pcs_extended_status = 32'hE000B23C;
+parameter val_gem0__pcs_extended_status = 32'h00000000;
+parameter mask_gem0__pcs_extended_status = 32'h00000000;
+
+parameter gem0__design_cfg1 = 32'hE000B280;
+parameter val_gem0__design_cfg1 = 32'h02000000;
+parameter mask_gem0__design_cfg1 = 32'h0E000000;
+
+parameter gem0__design_cfg2 = 32'hE000B284;
+parameter val_gem0__design_cfg2 = 32'h2A813FFF;
+parameter mask_gem0__design_cfg2 = 32'h3FCFFFFF;
+
+parameter gem0__design_cfg3 = 32'hE000B288;
+parameter val_gem0__design_cfg3 = 32'h00000000;
+parameter mask_gem0__design_cfg3 = 32'hFFFFFFFF;
+
+parameter gem0__design_cfg4 = 32'hE000B28C;
+parameter val_gem0__design_cfg4 = 32'h00000000;
+parameter mask_gem0__design_cfg4 = 32'hFFFFFFFF;
+
+parameter gem0__design_cfg5 = 32'hE000B290;
+parameter val_gem0__design_cfg5 = 32'h002F2045;
+parameter mask_gem0__design_cfg5 = 32'h0FFFFCFF;
+
+parameter gem0__design_cfg6 = 32'hE000B294;
+parameter val_gem0__design_cfg6 = 32'h00000000;
+parameter mask_gem0__design_cfg6 = 32'h00000000;
+
+parameter gem0__design_cfg7 = 32'hE000B298;
+parameter val_gem0__design_cfg7 = 32'h00000000;
+parameter mask_gem0__design_cfg7 = 32'h00000000;
+
+parameter gem0__isr_pq1 = 32'hE000B400;
+parameter val_gem0__isr_pq1 = 32'h00000000;
+parameter mask_gem0__isr_pq1 = 32'h00000000;
+
+parameter gem0__isr_pq2 = 32'hE000B404;
+parameter val_gem0__isr_pq2 = 32'h00000000;
+parameter mask_gem0__isr_pq2 = 32'h00000000;
+
+parameter gem0__isr_pq3 = 32'hE000B408;
+parameter val_gem0__isr_pq3 = 32'h00000000;
+parameter mask_gem0__isr_pq3 = 32'h00000000;
+
+parameter gem0__isr_pq4 = 32'hE000B40C;
+parameter val_gem0__isr_pq4 = 32'h00000000;
+parameter mask_gem0__isr_pq4 = 32'h00000000;
+
+parameter gem0__isr_pq5 = 32'hE000B410;
+parameter val_gem0__isr_pq5 = 32'h00000000;
+parameter mask_gem0__isr_pq5 = 32'h00000000;
+
+parameter gem0__isr_pq6 = 32'hE000B414;
+parameter val_gem0__isr_pq6 = 32'h00000000;
+parameter mask_gem0__isr_pq6 = 32'h00000000;
+
+parameter gem0__isr_pq7 = 32'hE000B418;
+parameter val_gem0__isr_pq7 = 32'h00000000;
+parameter mask_gem0__isr_pq7 = 32'h00000000;
+
+parameter gem0__tx_qbar_q1 = 32'hE000B440;
+parameter val_gem0__tx_qbar_q1 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q1 = 32'h00000000;
+
+parameter gem0__tx_qbar_q2 = 32'hE000B444;
+parameter val_gem0__tx_qbar_q2 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q2 = 32'h00000000;
+
+parameter gem0__tx_qbar_q3 = 32'hE000B448;
+parameter val_gem0__tx_qbar_q3 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q3 = 32'h00000000;
+
+parameter gem0__tx_qbar_q4 = 32'hE000B44C;
+parameter val_gem0__tx_qbar_q4 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q4 = 32'h00000000;
+
+parameter gem0__tx_qbar_q5 = 32'hE000B450;
+parameter val_gem0__tx_qbar_q5 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q5 = 32'h00000000;
+
+parameter gem0__tx_qbar_q6 = 32'hE000B454;
+parameter val_gem0__tx_qbar_q6 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q6 = 32'h00000000;
+
+parameter gem0__tx_qbar_q7 = 32'hE000B458;
+parameter val_gem0__tx_qbar_q7 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q7 = 32'h00000000;
+
+parameter gem0__rx_qbar_q1 = 32'hE000B480;
+parameter val_gem0__rx_qbar_q1 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q1 = 32'h00000000;
+
+parameter gem0__rx_qbar_q2 = 32'hE000B484;
+parameter val_gem0__rx_qbar_q2 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q2 = 32'h00000000;
+
+parameter gem0__rx_qbar_q3 = 32'hE000B488;
+parameter val_gem0__rx_qbar_q3 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q3 = 32'h00000000;
+
+parameter gem0__rx_qbar_q4 = 32'hE000B48C;
+parameter val_gem0__rx_qbar_q4 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q4 = 32'h00000000;
+
+parameter gem0__rx_qbar_q5 = 32'hE000B490;
+parameter val_gem0__rx_qbar_q5 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q5 = 32'h00000000;
+
+parameter gem0__rx_qbar_q6 = 32'hE000B494;
+parameter val_gem0__rx_qbar_q6 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q6 = 32'h00000000;
+
+parameter gem0__rx_qbar_q7 = 32'hE000B498;
+parameter val_gem0__rx_qbar_q7 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q7 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q1 = 32'hE000B4A0;
+parameter val_gem0__rx_bufsz_q1 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q1 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q2 = 32'hE000B4A4;
+parameter val_gem0__rx_bufsz_q2 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q2 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q3 = 32'hE000B4A8;
+parameter val_gem0__rx_bufsz_q3 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q3 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q4 = 32'hE000B4AC;
+parameter val_gem0__rx_bufsz_q4 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q4 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q5 = 32'hE000B4B0;
+parameter val_gem0__rx_bufsz_q5 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q5 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q6 = 32'hE000B4B4;
+parameter val_gem0__rx_bufsz_q6 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q6 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q7 = 32'hE000B4B8;
+parameter val_gem0__rx_bufsz_q7 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q7 = 32'h00000000;
+
+parameter gem0__screen_t1_r0 = 32'hE000B500;
+parameter val_gem0__screen_t1_r0 = 32'h00000000;
+parameter mask_gem0__screen_t1_r0 = 32'h00000000;
+
+parameter gem0__screen_t1_r1 = 32'hE000B504;
+parameter val_gem0__screen_t1_r1 = 32'h00000000;
+parameter mask_gem0__screen_t1_r1 = 32'h00000000;
+
+parameter gem0__screen_t1_r2 = 32'hE000B508;
+parameter val_gem0__screen_t1_r2 = 32'h00000000;
+parameter mask_gem0__screen_t1_r2 = 32'h00000000;
+
+parameter gem0__screen_t1_r3 = 32'hE000B50C;
+parameter val_gem0__screen_t1_r3 = 32'h00000000;
+parameter mask_gem0__screen_t1_r3 = 32'h00000000;
+
+parameter gem0__screen_t1_r4 = 32'hE000B510;
+parameter val_gem0__screen_t1_r4 = 32'h00000000;
+parameter mask_gem0__screen_t1_r4 = 32'h00000000;
+
+parameter gem0__screen_t1_r5 = 32'hE000B514;
+parameter val_gem0__screen_t1_r5 = 32'h00000000;
+parameter mask_gem0__screen_t1_r5 = 32'h00000000;
+
+parameter gem0__screen_t1_r6 = 32'hE000B518;
+parameter val_gem0__screen_t1_r6 = 32'h00000000;
+parameter mask_gem0__screen_t1_r6 = 32'h00000000;
+
+parameter gem0__screen_t1_r7 = 32'hE000B51C;
+parameter val_gem0__screen_t1_r7 = 32'h00000000;
+parameter mask_gem0__screen_t1_r7 = 32'h00000000;
+
+parameter gem0__screen_t1_r8 = 32'hE000B520;
+parameter val_gem0__screen_t1_r8 = 32'h00000000;
+parameter mask_gem0__screen_t1_r8 = 32'h00000000;
+
+parameter gem0__screen_t1_r9 = 32'hE000B524;
+parameter val_gem0__screen_t1_r9 = 32'h00000000;
+parameter mask_gem0__screen_t1_r9 = 32'h00000000;
+
+parameter gem0__screen_t1_r10 = 32'hE000B528;
+parameter val_gem0__screen_t1_r10 = 32'h00000000;
+parameter mask_gem0__screen_t1_r10 = 32'h00000000;
+
+parameter gem0__screen_t1_r11 = 32'hE000B52C;
+parameter val_gem0__screen_t1_r11 = 32'h00000000;
+parameter mask_gem0__screen_t1_r11 = 32'h00000000;
+
+parameter gem0__screen_t1_r12 = 32'hE000B530;
+parameter val_gem0__screen_t1_r12 = 32'h00000000;
+parameter mask_gem0__screen_t1_r12 = 32'h00000000;
+
+parameter gem0__screen_t1_r13 = 32'hE000B534;
+parameter val_gem0__screen_t1_r13 = 32'h00000000;
+parameter mask_gem0__screen_t1_r13 = 32'h00000000;
+
+parameter gem0__screen_t1_r14 = 32'hE000B538;
+parameter val_gem0__screen_t1_r14 = 32'h00000000;
+parameter mask_gem0__screen_t1_r14 = 32'h00000000;
+
+parameter gem0__screen_t1_r15 = 32'hE000B53C;
+parameter val_gem0__screen_t1_r15 = 32'h00000000;
+parameter mask_gem0__screen_t1_r15 = 32'h00000000;
+
+parameter gem0__screen_t2_r0 = 32'hE000B540;
+parameter val_gem0__screen_t2_r0 = 32'h00000000;
+parameter mask_gem0__screen_t2_r0 = 32'h00000000;
+
+parameter gem0__screen_t2_r1 = 32'hE000B544;
+parameter val_gem0__screen_t2_r1 = 32'h00000000;
+parameter mask_gem0__screen_t2_r1 = 32'h00000000;
+
+parameter gem0__screen_t2_r2 = 32'hE000B548;
+parameter val_gem0__screen_t2_r2 = 32'h00000000;
+parameter mask_gem0__screen_t2_r2 = 32'h00000000;
+
+parameter gem0__screen_t2_r3 = 32'hE000B54C;
+parameter val_gem0__screen_t2_r3 = 32'h00000000;
+parameter mask_gem0__screen_t2_r3 = 32'h00000000;
+
+parameter gem0__screen_t2_r4 = 32'hE000B550;
+parameter val_gem0__screen_t2_r4 = 32'h00000000;
+parameter mask_gem0__screen_t2_r4 = 32'h00000000;
+
+parameter gem0__screen_t2_r5 = 32'hE000B554;
+parameter val_gem0__screen_t2_r5 = 32'h00000000;
+parameter mask_gem0__screen_t2_r5 = 32'h00000000;
+
+parameter gem0__screen_t2_r6 = 32'hE000B558;
+parameter val_gem0__screen_t2_r6 = 32'h00000000;
+parameter mask_gem0__screen_t2_r6 = 32'h00000000;
+
+parameter gem0__screen_t2_r7 = 32'hE000B55C;
+parameter val_gem0__screen_t2_r7 = 32'h00000000;
+parameter mask_gem0__screen_t2_r7 = 32'h00000000;
+
+parameter gem0__screen_t2_r8 = 32'hE000B560;
+parameter val_gem0__screen_t2_r8 = 32'h00000000;
+parameter mask_gem0__screen_t2_r8 = 32'h00000000;
+
+parameter gem0__screen_t2_r9 = 32'hE000B564;
+parameter val_gem0__screen_t2_r9 = 32'h00000000;
+parameter mask_gem0__screen_t2_r9 = 32'h00000000;
+
+parameter gem0__screen_t2_r10 = 32'hE000B568;
+parameter val_gem0__screen_t2_r10 = 32'h00000000;
+parameter mask_gem0__screen_t2_r10 = 32'h00000000;
+
+parameter gem0__screen_t2_r11 = 32'hE000B56C;
+parameter val_gem0__screen_t2_r11 = 32'h00000000;
+parameter mask_gem0__screen_t2_r11 = 32'h00000000;
+
+parameter gem0__screen_t2_r12 = 32'hE000B570;
+parameter val_gem0__screen_t2_r12 = 32'h00000000;
+parameter mask_gem0__screen_t2_r12 = 32'h00000000;
+
+parameter gem0__screen_t2_r13 = 32'hE000B574;
+parameter val_gem0__screen_t2_r13 = 32'h00000000;
+parameter mask_gem0__screen_t2_r13 = 32'h00000000;
+
+parameter gem0__screen_t2_r14 = 32'hE000B578;
+parameter val_gem0__screen_t2_r14 = 32'h00000000;
+parameter mask_gem0__screen_t2_r14 = 32'h00000000;
+
+parameter gem0__screen_t2_r15 = 32'hE000B57C;
+parameter val_gem0__screen_t2_r15 = 32'h00000000;
+parameter mask_gem0__screen_t2_r15 = 32'h00000000;
+
+parameter gem0__intr_en_pq1 = 32'hE000B600;
+parameter val_gem0__intr_en_pq1 = 32'h00000000;
+parameter mask_gem0__intr_en_pq1 = 32'h00000000;
+
+parameter gem0__intr_en_pq2 = 32'hE000B604;
+parameter val_gem0__intr_en_pq2 = 32'h00000000;
+parameter mask_gem0__intr_en_pq2 = 32'h00000000;
+
+parameter gem0__intr_en_pq3 = 32'hE000B608;
+parameter val_gem0__intr_en_pq3 = 32'h00000000;
+parameter mask_gem0__intr_en_pq3 = 32'h00000000;
+
+parameter gem0__intr_en_pq4 = 32'hE000B60C;
+parameter val_gem0__intr_en_pq4 = 32'h00000000;
+parameter mask_gem0__intr_en_pq4 = 32'h00000000;
+
+parameter gem0__intr_en_pq5 = 32'hE000B610;
+parameter val_gem0__intr_en_pq5 = 32'h00000000;
+parameter mask_gem0__intr_en_pq5 = 32'h00000000;
+
+parameter gem0__intr_en_pq6 = 32'hE000B614;
+parameter val_gem0__intr_en_pq6 = 32'h00000000;
+parameter mask_gem0__intr_en_pq6 = 32'h00000000;
+
+parameter gem0__intr_en_pq7 = 32'hE000B618;
+parameter val_gem0__intr_en_pq7 = 32'h00000000;
+parameter mask_gem0__intr_en_pq7 = 32'h00000000;
+
+parameter gem0__intr_dis_pq1 = 32'hE000B620;
+parameter val_gem0__intr_dis_pq1 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq1 = 32'h00000000;
+
+parameter gem0__intr_dis_pq2 = 32'hE000B624;
+parameter val_gem0__intr_dis_pq2 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq2 = 32'h00000000;
+
+parameter gem0__intr_dis_pq3 = 32'hE000B628;
+parameter val_gem0__intr_dis_pq3 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq3 = 32'h00000000;
+
+parameter gem0__intr_dis_pq4 = 32'hE000B62C;
+parameter val_gem0__intr_dis_pq4 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq4 = 32'h00000000;
+
+parameter gem0__intr_dis_pq5 = 32'hE000B630;
+parameter val_gem0__intr_dis_pq5 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq5 = 32'h00000000;
+
+parameter gem0__intr_dis_pq6 = 32'hE000B634;
+parameter val_gem0__intr_dis_pq6 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq6 = 32'h00000000;
+
+parameter gem0__intr_dis_pq7 = 32'hE000B638;
+parameter val_gem0__intr_dis_pq7 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq7 = 32'h00000000;
+
+parameter gem0__intr_mask_pq1 = 32'hE000B640;
+parameter val_gem0__intr_mask_pq1 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq1 = 32'h00000000;
+
+parameter gem0__intr_mask_pq2 = 32'hE000B644;
+parameter val_gem0__intr_mask_pq2 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq2 = 32'h00000000;
+
+parameter gem0__intr_mask_pq3 = 32'hE000B648;
+parameter val_gem0__intr_mask_pq3 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq3 = 32'h00000000;
+
+parameter gem0__intr_mask_pq4 = 32'hE000B64C;
+parameter val_gem0__intr_mask_pq4 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq4 = 32'h00000000;
+
+parameter gem0__intr_mask_pq5 = 32'hE000B650;
+parameter val_gem0__intr_mask_pq5 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq5 = 32'h00000000;
+
+parameter gem0__intr_mask_pq6 = 32'hE000B654;
+parameter val_gem0__intr_mask_pq6 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq6 = 32'h00000000;
+
+parameter gem0__intr_mask_pq7 = 32'hE000B658;
+parameter val_gem0__intr_mask_pq7 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq7 = 32'h00000000;
+
+
+// ************************************************************
+//   Module gem1 GEM
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gem1__net_ctrl = 32'hE000C000;
+parameter val_gem1__net_ctrl = 32'h00000000;
+parameter mask_gem1__net_ctrl = 32'hFFFFFFFF;
+
+parameter gem1__net_cfg = 32'hE000C004;
+parameter val_gem1__net_cfg = 32'h00080000;
+parameter mask_gem1__net_cfg = 32'hFFFFFFFF;
+
+parameter gem1__net_status = 32'hE000C008;
+parameter val_gem1__net_status = 32'h00000004;
+parameter mask_gem1__net_status = 32'hFFFFFFFD;
+
+parameter gem1__user_io = 32'hE000C00C;
+parameter val_gem1__user_io = 32'h00000000;
+parameter mask_gem1__user_io = 32'h0000FFFF;
+
+parameter gem1__dma_cfg = 32'hE000C010;
+parameter val_gem1__dma_cfg = 32'h00020784;
+parameter mask_gem1__dma_cfg = 32'hFFFFFFFF;
+
+parameter gem1__tx_status = 32'hE000C014;
+parameter val_gem1__tx_status = 32'h00000000;
+parameter mask_gem1__tx_status = 32'hFFFFFFFF;
+
+parameter gem1__rx_qbar = 32'hE000C018;
+parameter val_gem1__rx_qbar = 32'h00000000;
+parameter mask_gem1__rx_qbar = 32'hFFFFFFFF;
+
+parameter gem1__tx_qbar = 32'hE000C01C;
+parameter val_gem1__tx_qbar = 32'h00000000;
+parameter mask_gem1__tx_qbar = 32'hFFFFFFFF;
+
+parameter gem1__rx_status = 32'hE000C020;
+parameter val_gem1__rx_status = 32'h00000000;
+parameter mask_gem1__rx_status = 32'hFFFFFFFF;
+
+parameter gem1__intr_status = 32'hE000C024;
+parameter val_gem1__intr_status = 32'h00000000;
+parameter mask_gem1__intr_status = 32'hFFFFFFFF;
+
+parameter gem1__intr_en = 32'hE000C028;
+parameter val_gem1__intr_en = 32'h00000000;
+parameter mask_gem1__intr_en = 32'h00000000;
+
+parameter gem1__intr_dis = 32'hE000C02C;
+parameter val_gem1__intr_dis = 32'h00000000;
+parameter mask_gem1__intr_dis = 32'h00000000;
+
+parameter gem1__intr_mask = 32'hE000C030;
+parameter val_gem1__intr_mask = 32'h0001FFFF;
+parameter mask_gem1__intr_mask = 32'hFC01FFFF;
+
+parameter gem1__phy_maint = 32'hE000C034;
+parameter val_gem1__phy_maint = 32'h00000000;
+parameter mask_gem1__phy_maint = 32'hFFFFFFFF;
+
+parameter gem1__rx_pauseq = 32'hE000C038;
+parameter val_gem1__rx_pauseq = 32'h00000000;
+parameter mask_gem1__rx_pauseq = 32'hFFFFFFFF;
+
+parameter gem1__tx_pauseq = 32'hE000C03C;
+parameter val_gem1__tx_pauseq = 32'h0000FFFF;
+parameter mask_gem1__tx_pauseq = 32'hFFFFFFFF;
+
+parameter gem1__tx_partial_st_fwd = 32'hE000C040;
+parameter val_gem1__tx_partial_st_fwd = 32'h000003FF;
+parameter mask_gem1__tx_partial_st_fwd = 32'hFFFFFFFF;
+
+parameter gem1__rx_partial_st_fwd = 32'hE000C044;
+parameter val_gem1__rx_partial_st_fwd = 32'h000003FF;
+parameter mask_gem1__rx_partial_st_fwd = 32'hFFFFFFFF;
+
+parameter gem1__hash_bot = 32'hE000C080;
+parameter val_gem1__hash_bot = 32'h00000000;
+parameter mask_gem1__hash_bot = 32'hFFFFFFFF;
+
+parameter gem1__hash_top = 32'hE000C084;
+parameter val_gem1__hash_top = 32'h00000000;
+parameter mask_gem1__hash_top = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr1_bot = 32'hE000C088;
+parameter val_gem1__spec_addr1_bot = 32'h00000000;
+parameter mask_gem1__spec_addr1_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr1_top = 32'hE000C08C;
+parameter val_gem1__spec_addr1_top = 32'h00000000;
+parameter mask_gem1__spec_addr1_top = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr2_bot = 32'hE000C090;
+parameter val_gem1__spec_addr2_bot = 32'h00000000;
+parameter mask_gem1__spec_addr2_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr2_top = 32'hE000C094;
+parameter val_gem1__spec_addr2_top = 32'h00000000;
+parameter mask_gem1__spec_addr2_top = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr3_bot = 32'hE000C098;
+parameter val_gem1__spec_addr3_bot = 32'h00000000;
+parameter mask_gem1__spec_addr3_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr3_top = 32'hE000C09C;
+parameter val_gem1__spec_addr3_top = 32'h00000000;
+parameter mask_gem1__spec_addr3_top = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr4_bot = 32'hE000C0A0;
+parameter val_gem1__spec_addr4_bot = 32'h00000000;
+parameter mask_gem1__spec_addr4_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr4_top = 32'hE000C0A4;
+parameter val_gem1__spec_addr4_top = 32'h00000000;
+parameter mask_gem1__spec_addr4_top = 32'hFFFFFFFF;
+
+parameter gem1__type_id_match1 = 32'hE000C0A8;
+parameter val_gem1__type_id_match1 = 32'h00000000;
+parameter mask_gem1__type_id_match1 = 32'hFFFFFFFF;
+
+parameter gem1__type_id_match2 = 32'hE000C0AC;
+parameter val_gem1__type_id_match2 = 32'h00000000;
+parameter mask_gem1__type_id_match2 = 32'hFFFFFFFF;
+
+parameter gem1__type_id_match3 = 32'hE000C0B0;
+parameter val_gem1__type_id_match3 = 32'h00000000;
+parameter mask_gem1__type_id_match3 = 32'hFFFFFFFF;
+
+parameter gem1__type_id_match4 = 32'hE000C0B4;
+parameter val_gem1__type_id_match4 = 32'h00000000;
+parameter mask_gem1__type_id_match4 = 32'hFFFFFFFF;
+
+parameter gem1__wake_on_lan = 32'hE000C0B8;
+parameter val_gem1__wake_on_lan = 32'h00000000;
+parameter mask_gem1__wake_on_lan = 32'hFFFFFFFF;
+
+parameter gem1__ipg_stretch = 32'hE000C0BC;
+parameter val_gem1__ipg_stretch = 32'h00000000;
+parameter mask_gem1__ipg_stretch = 32'hFFFFFFFF;
+
+parameter gem1__stacked_vlan = 32'hE000C0C0;
+parameter val_gem1__stacked_vlan = 32'h00000000;
+parameter mask_gem1__stacked_vlan = 32'hFFFFFFFF;
+
+parameter gem1__tx_pfc_pause = 32'hE000C0C4;
+parameter val_gem1__tx_pfc_pause = 32'h00000000;
+parameter mask_gem1__tx_pfc_pause = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr1_mask_bot = 32'hE000C0C8;
+parameter val_gem1__spec_addr1_mask_bot = 32'h00000000;
+parameter mask_gem1__spec_addr1_mask_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr1_mask_top = 32'hE000C0CC;
+parameter val_gem1__spec_addr1_mask_top = 32'h00000000;
+parameter mask_gem1__spec_addr1_mask_top = 32'hFFFFFFFF;
+
+parameter gem1__module_id = 32'hE000C0FC;
+parameter val_gem1__module_id = 32'h00020118;
+parameter mask_gem1__module_id = 32'hFFFFFFFF;
+
+parameter gem1__octets_tx_bot = 32'hE000C100;
+parameter val_gem1__octets_tx_bot = 32'h00000000;
+parameter mask_gem1__octets_tx_bot = 32'hFFFFFFFF;
+
+parameter gem1__octets_tx_top = 32'hE000C104;
+parameter val_gem1__octets_tx_top = 32'h00000000;
+parameter mask_gem1__octets_tx_top = 32'hFFFFFFFF;
+
+parameter gem1__frames_tx = 32'hE000C108;
+parameter val_gem1__frames_tx = 32'h00000000;
+parameter mask_gem1__frames_tx = 32'hFFFFFFFF;
+
+parameter gem1__broadcast_frames_tx = 32'hE000C10C;
+parameter val_gem1__broadcast_frames_tx = 32'h00000000;
+parameter mask_gem1__broadcast_frames_tx = 32'hFFFFFFFF;
+
+parameter gem1__multi_frames_tx = 32'hE000C110;
+parameter val_gem1__multi_frames_tx = 32'h00000000;
+parameter mask_gem1__multi_frames_tx = 32'hFFFFFFFF;
+
+parameter gem1__pause_frames_tx = 32'hE000C114;
+parameter val_gem1__pause_frames_tx = 32'h00000000;
+parameter mask_gem1__pause_frames_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_64b_tx = 32'hE000C118;
+parameter val_gem1__frames_64b_tx = 32'h00000000;
+parameter mask_gem1__frames_64b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_65to127b_tx = 32'hE000C11C;
+parameter val_gem1__frames_65to127b_tx = 32'h00000000;
+parameter mask_gem1__frames_65to127b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_128to255b_tx = 32'hE000C120;
+parameter val_gem1__frames_128to255b_tx = 32'h00000000;
+parameter mask_gem1__frames_128to255b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_256to511b_tx = 32'hE000C124;
+parameter val_gem1__frames_256to511b_tx = 32'h00000000;
+parameter mask_gem1__frames_256to511b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_512to1023b_tx = 32'hE000C128;
+parameter val_gem1__frames_512to1023b_tx = 32'h00000000;
+parameter mask_gem1__frames_512to1023b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_1024to1518b_tx = 32'hE000C12C;
+parameter val_gem1__frames_1024to1518b_tx = 32'h00000000;
+parameter mask_gem1__frames_1024to1518b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_gt1518b_tx = 32'hE000C130;
+parameter val_gem1__frames_gt1518b_tx = 32'h00000000;
+parameter mask_gem1__frames_gt1518b_tx = 32'hFFFFFFFF;
+
+parameter gem1__tx_under_runs = 32'hE000C134;
+parameter val_gem1__tx_under_runs = 32'h00000000;
+parameter mask_gem1__tx_under_runs = 32'hFFFFFFFF;
+
+parameter gem1__single_collisn_frames = 32'hE000C138;
+parameter val_gem1__single_collisn_frames = 32'h00000000;
+parameter mask_gem1__single_collisn_frames = 32'hFFFFFFFF;
+
+parameter gem1__multi_collisn_frames = 32'hE000C13C;
+parameter val_gem1__multi_collisn_frames = 32'h00000000;
+parameter mask_gem1__multi_collisn_frames = 32'hFFFFFFFF;
+
+parameter gem1__excessive_collisns = 32'hE000C140;
+parameter val_gem1__excessive_collisns = 32'h00000000;
+parameter mask_gem1__excessive_collisns = 32'hFFFFFFFF;
+
+parameter gem1__late_collisns = 32'hE000C144;
+parameter val_gem1__late_collisns = 32'h00000000;
+parameter mask_gem1__late_collisns = 32'hFFFFFFFF;
+
+parameter gem1__deferred_tx_frames = 32'hE000C148;
+parameter val_gem1__deferred_tx_frames = 32'h00000000;
+parameter mask_gem1__deferred_tx_frames = 32'hFFFFFFFF;
+
+parameter gem1__carrier_sense_errs = 32'hE000C14C;
+parameter val_gem1__carrier_sense_errs = 32'h00000000;
+parameter mask_gem1__carrier_sense_errs = 32'hFFFFFFFF;
+
+parameter gem1__octets_rx_bot = 32'hE000C150;
+parameter val_gem1__octets_rx_bot = 32'h00000000;
+parameter mask_gem1__octets_rx_bot = 32'hFFFFFFFF;
+
+parameter gem1__octets_rx_top = 32'hE000C154;
+parameter val_gem1__octets_rx_top = 32'h00000000;
+parameter mask_gem1__octets_rx_top = 32'hFFFFFFFF;
+
+parameter gem1__frames_rx = 32'hE000C158;
+parameter val_gem1__frames_rx = 32'h00000000;
+parameter mask_gem1__frames_rx = 32'hFFFFFFFF;
+
+parameter gem1__bdcast_fames_rx = 32'hE000C15C;
+parameter val_gem1__bdcast_fames_rx = 32'h00000000;
+parameter mask_gem1__bdcast_fames_rx = 32'hFFFFFFFF;
+
+parameter gem1__multi_frames_rx = 32'hE000C160;
+parameter val_gem1__multi_frames_rx = 32'h00000000;
+parameter mask_gem1__multi_frames_rx = 32'hFFFFFFFF;
+
+parameter gem1__pause_rx = 32'hE000C164;
+parameter val_gem1__pause_rx = 32'h00000000;
+parameter mask_gem1__pause_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_64b_rx = 32'hE000C168;
+parameter val_gem1__frames_64b_rx = 32'h00000000;
+parameter mask_gem1__frames_64b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_65to127b_rx = 32'hE000C16C;
+parameter val_gem1__frames_65to127b_rx = 32'h00000000;
+parameter mask_gem1__frames_65to127b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_128to255b_rx = 32'hE000C170;
+parameter val_gem1__frames_128to255b_rx = 32'h00000000;
+parameter mask_gem1__frames_128to255b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_256to511b_rx = 32'hE000C174;
+parameter val_gem1__frames_256to511b_rx = 32'h00000000;
+parameter mask_gem1__frames_256to511b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_512to1023b_rx = 32'hE000C178;
+parameter val_gem1__frames_512to1023b_rx = 32'h00000000;
+parameter mask_gem1__frames_512to1023b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_1024to1518b_rx = 32'hE000C17C;
+parameter val_gem1__frames_1024to1518b_rx = 32'h00000000;
+parameter mask_gem1__frames_1024to1518b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_gt1518b_rx = 32'hE000C180;
+parameter val_gem1__frames_gt1518b_rx = 32'h00000000;
+parameter mask_gem1__frames_gt1518b_rx = 32'hFFFFFFFF;
+
+parameter gem1__undersz_rx = 32'hE000C184;
+parameter val_gem1__undersz_rx = 32'h00000000;
+parameter mask_gem1__undersz_rx = 32'hFFFFFFFF;
+
+parameter gem1__oversz_rx = 32'hE000C188;
+parameter val_gem1__oversz_rx = 32'h00000000;
+parameter mask_gem1__oversz_rx = 32'hFFFFFFFF;
+
+parameter gem1__jab_rx = 32'hE000C18C;
+parameter val_gem1__jab_rx = 32'h00000000;
+parameter mask_gem1__jab_rx = 32'hFFFFFFFF;
+
+parameter gem1__fcs_errors = 32'hE000C190;
+parameter val_gem1__fcs_errors = 32'h00000000;
+parameter mask_gem1__fcs_errors = 32'hFFFFFFFF;
+
+parameter gem1__length_field_errors = 32'hE000C194;
+parameter val_gem1__length_field_errors = 32'h00000000;
+parameter mask_gem1__length_field_errors = 32'hFFFFFFFF;
+
+parameter gem1__rx_symbol_errors = 32'hE000C198;
+parameter val_gem1__rx_symbol_errors = 32'h00000000;
+parameter mask_gem1__rx_symbol_errors = 32'hFFFFFFFF;
+
+parameter gem1__align_errors = 32'hE000C19C;
+parameter val_gem1__align_errors = 32'h00000000;
+parameter mask_gem1__align_errors = 32'hFFFFFFFF;
+
+parameter gem1__rx_resource_errors = 32'hE000C1A0;
+parameter val_gem1__rx_resource_errors = 32'h00000000;
+parameter mask_gem1__rx_resource_errors = 32'hFFFFFFFF;
+
+parameter gem1__rx_overrun_errors = 32'hE000C1A4;
+parameter val_gem1__rx_overrun_errors = 32'h00000000;
+parameter mask_gem1__rx_overrun_errors = 32'hFFFFFFFF;
+
+parameter gem1__ip_hdr_csum_errors = 32'hE000C1A8;
+parameter val_gem1__ip_hdr_csum_errors = 32'h00000000;
+parameter mask_gem1__ip_hdr_csum_errors = 32'hFFFFFFFF;
+
+parameter gem1__tcp_csum_errors = 32'hE000C1AC;
+parameter val_gem1__tcp_csum_errors = 32'h00000000;
+parameter mask_gem1__tcp_csum_errors = 32'hFFFFFFFF;
+
+parameter gem1__udp_csum_errors = 32'hE000C1B0;
+parameter val_gem1__udp_csum_errors = 32'h00000000;
+parameter mask_gem1__udp_csum_errors = 32'hFFFFFFFF;
+
+parameter gem1__timer_strobe_s = 32'hE000C1C8;
+parameter val_gem1__timer_strobe_s = 32'h00000000;
+parameter mask_gem1__timer_strobe_s = 32'hFFFFFFFF;
+
+parameter gem1__timer_strobe_ns = 32'hE000C1CC;
+parameter val_gem1__timer_strobe_ns = 32'h00000000;
+parameter mask_gem1__timer_strobe_ns = 32'hFFFFFFFF;
+
+parameter gem1__timer_s = 32'hE000C1D0;
+parameter val_gem1__timer_s = 32'h00000000;
+parameter mask_gem1__timer_s = 32'hFFFFFFFF;
+
+parameter gem1__timer_ns = 32'hE000C1D4;
+parameter val_gem1__timer_ns = 32'h00000000;
+parameter mask_gem1__timer_ns = 32'hFFFFFFFF;
+
+parameter gem1__timer_adjust = 32'hE000C1D8;
+parameter val_gem1__timer_adjust = 32'h00000000;
+parameter mask_gem1__timer_adjust = 32'hFFFFFFFF;
+
+parameter gem1__timer_incr = 32'hE000C1DC;
+parameter val_gem1__timer_incr = 32'h00000000;
+parameter mask_gem1__timer_incr = 32'hFFFFFFFF;
+
+parameter gem1__ptp_tx_s = 32'hE000C1E0;
+parameter val_gem1__ptp_tx_s = 32'h00000000;
+parameter mask_gem1__ptp_tx_s = 32'hFFFFFFFF;
+
+parameter gem1__ptp_tx_ns = 32'hE000C1E4;
+parameter val_gem1__ptp_tx_ns = 32'h00000000;
+parameter mask_gem1__ptp_tx_ns = 32'hFFFFFFFF;
+
+parameter gem1__ptp_rx_s = 32'hE000C1E8;
+parameter val_gem1__ptp_rx_s = 32'h00000000;
+parameter mask_gem1__ptp_rx_s = 32'hFFFFFFFF;
+
+parameter gem1__ptp_rx_ns = 32'hE000C1EC;
+parameter val_gem1__ptp_rx_ns = 32'h00000000;
+parameter mask_gem1__ptp_rx_ns = 32'hFFFFFFFF;
+
+parameter gem1__ptp_peer_tx_s = 32'hE000C1F0;
+parameter val_gem1__ptp_peer_tx_s = 32'h00000000;
+parameter mask_gem1__ptp_peer_tx_s = 32'hFFFFFFFF;
+
+parameter gem1__ptp_peer_tx_ns = 32'hE000C1F4;
+parameter val_gem1__ptp_peer_tx_ns = 32'h00000000;
+parameter mask_gem1__ptp_peer_tx_ns = 32'hFFFFFFFF;
+
+parameter gem1__ptp_peer_rx_s = 32'hE000C1F8;
+parameter val_gem1__ptp_peer_rx_s = 32'h00000000;
+parameter mask_gem1__ptp_peer_rx_s = 32'hFFFFFFFF;
+
+parameter gem1__ptp_peer_rx_ns = 32'hE000C1FC;
+parameter val_gem1__ptp_peer_rx_ns = 32'h00000000;
+parameter mask_gem1__ptp_peer_rx_ns = 32'hFFFFFFFF;
+
+parameter gem1__pcs_ctrl = 32'hE000C200;
+parameter val_gem1__pcs_ctrl = 32'h00000000;
+parameter mask_gem1__pcs_ctrl = 32'h00000000;
+
+parameter gem1__pcs_status = 32'hE000C204;
+parameter val_gem1__pcs_status = 32'h00000000;
+parameter mask_gem1__pcs_status = 32'h00000000;
+
+parameter gem1__pcs_upper_phy_id = 32'hE000C208;
+parameter val_gem1__pcs_upper_phy_id = 32'h00000000;
+parameter mask_gem1__pcs_upper_phy_id = 32'h00000000;
+
+parameter gem1__pcs_lower_phy_id = 32'hE000C20C;
+parameter val_gem1__pcs_lower_phy_id = 32'h00000000;
+parameter mask_gem1__pcs_lower_phy_id = 32'h00000000;
+
+parameter gem1__pcs_autoneg_ad = 32'hE000C210;
+parameter val_gem1__pcs_autoneg_ad = 32'h00000000;
+parameter mask_gem1__pcs_autoneg_ad = 32'h00000000;
+
+parameter gem1__pcs_autoneg_ability = 32'hE000C214;
+parameter val_gem1__pcs_autoneg_ability = 32'h00000000;
+parameter mask_gem1__pcs_autoneg_ability = 32'h00000000;
+
+parameter gem1__pcs_autonec_exp = 32'hE000C218;
+parameter val_gem1__pcs_autonec_exp = 32'h00000000;
+parameter mask_gem1__pcs_autonec_exp = 32'h00000000;
+
+parameter gem1__pcs_autoneg_next_pg = 32'hE000C21C;
+parameter val_gem1__pcs_autoneg_next_pg = 32'h00000000;
+parameter mask_gem1__pcs_autoneg_next_pg = 32'h00000000;
+
+parameter gem1__pcs_autoneg_pnext_pg = 32'hE000C220;
+parameter val_gem1__pcs_autoneg_pnext_pg = 32'h00000000;
+parameter mask_gem1__pcs_autoneg_pnext_pg = 32'h00000000;
+
+parameter gem1__pcs_extended_status = 32'hE000C23C;
+parameter val_gem1__pcs_extended_status = 32'h00000000;
+parameter mask_gem1__pcs_extended_status = 32'h00000000;
+
+parameter gem1__design_cfg1 = 32'hE000C280;
+parameter val_gem1__design_cfg1 = 32'h02000000;
+parameter mask_gem1__design_cfg1 = 32'h0E000000;
+
+parameter gem1__design_cfg2 = 32'hE000C284;
+parameter val_gem1__design_cfg2 = 32'h2A813FFF;
+parameter mask_gem1__design_cfg2 = 32'h3FCFFFFF;
+
+parameter gem1__design_cfg3 = 32'hE000C288;
+parameter val_gem1__design_cfg3 = 32'h00000000;
+parameter mask_gem1__design_cfg3 = 32'hFFFFFFFF;
+
+parameter gem1__design_cfg4 = 32'hE000C28C;
+parameter val_gem1__design_cfg4 = 32'h00000000;
+parameter mask_gem1__design_cfg4 = 32'hFFFFFFFF;
+
+parameter gem1__design_cfg5 = 32'hE000C290;
+parameter val_gem1__design_cfg5 = 32'h002F2045;
+parameter mask_gem1__design_cfg5 = 32'h0FFFFCFF;
+
+parameter gem1__design_cfg6 = 32'hE000C294;
+parameter val_gem1__design_cfg6 = 32'h00000000;
+parameter mask_gem1__design_cfg6 = 32'h00000000;
+
+parameter gem1__design_cfg7 = 32'hE000C298;
+parameter val_gem1__design_cfg7 = 32'h00000000;
+parameter mask_gem1__design_cfg7 = 32'h00000000;
+
+parameter gem1__isr_pq1 = 32'hE000C400;
+parameter val_gem1__isr_pq1 = 32'h00000000;
+parameter mask_gem1__isr_pq1 = 32'h00000000;
+
+parameter gem1__isr_pq2 = 32'hE000C404;
+parameter val_gem1__isr_pq2 = 32'h00000000;
+parameter mask_gem1__isr_pq2 = 32'h00000000;
+
+parameter gem1__isr_pq3 = 32'hE000C408;
+parameter val_gem1__isr_pq3 = 32'h00000000;
+parameter mask_gem1__isr_pq3 = 32'h00000000;
+
+parameter gem1__isr_pq4 = 32'hE000C40C;
+parameter val_gem1__isr_pq4 = 32'h00000000;
+parameter mask_gem1__isr_pq4 = 32'h00000000;
+
+parameter gem1__isr_pq5 = 32'hE000C410;
+parameter val_gem1__isr_pq5 = 32'h00000000;
+parameter mask_gem1__isr_pq5 = 32'h00000000;
+
+parameter gem1__isr_pq6 = 32'hE000C414;
+parameter val_gem1__isr_pq6 = 32'h00000000;
+parameter mask_gem1__isr_pq6 = 32'h00000000;
+
+parameter gem1__isr_pq7 = 32'hE000C418;
+parameter val_gem1__isr_pq7 = 32'h00000000;
+parameter mask_gem1__isr_pq7 = 32'h00000000;
+
+parameter gem1__tx_qbar_q1 = 32'hE000C440;
+parameter val_gem1__tx_qbar_q1 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q1 = 32'h00000000;
+
+parameter gem1__tx_qbar_q2 = 32'hE000C444;
+parameter val_gem1__tx_qbar_q2 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q2 = 32'h00000000;
+
+parameter gem1__tx_qbar_q3 = 32'hE000C448;
+parameter val_gem1__tx_qbar_q3 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q3 = 32'h00000000;
+
+parameter gem1__tx_qbar_q4 = 32'hE000C44C;
+parameter val_gem1__tx_qbar_q4 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q4 = 32'h00000000;
+
+parameter gem1__tx_qbar_q5 = 32'hE000C450;
+parameter val_gem1__tx_qbar_q5 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q5 = 32'h00000000;
+
+parameter gem1__tx_qbar_q6 = 32'hE000C454;
+parameter val_gem1__tx_qbar_q6 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q6 = 32'h00000000;
+
+parameter gem1__tx_qbar_q7 = 32'hE000C458;
+parameter val_gem1__tx_qbar_q7 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q7 = 32'h00000000;
+
+parameter gem1__rx_qbar_q1 = 32'hE000C480;
+parameter val_gem1__rx_qbar_q1 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q1 = 32'h00000000;
+
+parameter gem1__rx_qbar_q2 = 32'hE000C484;
+parameter val_gem1__rx_qbar_q2 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q2 = 32'h00000000;
+
+parameter gem1__rx_qbar_q3 = 32'hE000C488;
+parameter val_gem1__rx_qbar_q3 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q3 = 32'h00000000;
+
+parameter gem1__rx_qbar_q4 = 32'hE000C48C;
+parameter val_gem1__rx_qbar_q4 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q4 = 32'h00000000;
+
+parameter gem1__rx_qbar_q5 = 32'hE000C490;
+parameter val_gem1__rx_qbar_q5 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q5 = 32'h00000000;
+
+parameter gem1__rx_qbar_q6 = 32'hE000C494;
+parameter val_gem1__rx_qbar_q6 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q6 = 32'h00000000;
+
+parameter gem1__rx_qbar_q7 = 32'hE000C498;
+parameter val_gem1__rx_qbar_q7 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q7 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q1 = 32'hE000C4A0;
+parameter val_gem1__rx_bufsz_q1 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q1 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q2 = 32'hE000C4A4;
+parameter val_gem1__rx_bufsz_q2 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q2 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q3 = 32'hE000C4A8;
+parameter val_gem1__rx_bufsz_q3 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q3 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q4 = 32'hE000C4AC;
+parameter val_gem1__rx_bufsz_q4 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q4 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q5 = 32'hE000C4B0;
+parameter val_gem1__rx_bufsz_q5 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q5 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q6 = 32'hE000C4B4;
+parameter val_gem1__rx_bufsz_q6 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q6 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q7 = 32'hE000C4B8;
+parameter val_gem1__rx_bufsz_q7 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q7 = 32'h00000000;
+
+parameter gem1__screen_t1_r0 = 32'hE000C500;
+parameter val_gem1__screen_t1_r0 = 32'h00000000;
+parameter mask_gem1__screen_t1_r0 = 32'h00000000;
+
+parameter gem1__screen_t1_r1 = 32'hE000C504;
+parameter val_gem1__screen_t1_r1 = 32'h00000000;
+parameter mask_gem1__screen_t1_r1 = 32'h00000000;
+
+parameter gem1__screen_t1_r2 = 32'hE000C508;
+parameter val_gem1__screen_t1_r2 = 32'h00000000;
+parameter mask_gem1__screen_t1_r2 = 32'h00000000;
+
+parameter gem1__screen_t1_r3 = 32'hE000C50C;
+parameter val_gem1__screen_t1_r3 = 32'h00000000;
+parameter mask_gem1__screen_t1_r3 = 32'h00000000;
+
+parameter gem1__screen_t1_r4 = 32'hE000C510;
+parameter val_gem1__screen_t1_r4 = 32'h00000000;
+parameter mask_gem1__screen_t1_r4 = 32'h00000000;
+
+parameter gem1__screen_t1_r5 = 32'hE000C514;
+parameter val_gem1__screen_t1_r5 = 32'h00000000;
+parameter mask_gem1__screen_t1_r5 = 32'h00000000;
+
+parameter gem1__screen_t1_r6 = 32'hE000C518;
+parameter val_gem1__screen_t1_r6 = 32'h00000000;
+parameter mask_gem1__screen_t1_r6 = 32'h00000000;
+
+parameter gem1__screen_t1_r7 = 32'hE000C51C;
+parameter val_gem1__screen_t1_r7 = 32'h00000000;
+parameter mask_gem1__screen_t1_r7 = 32'h00000000;
+
+parameter gem1__screen_t1_r8 = 32'hE000C520;
+parameter val_gem1__screen_t1_r8 = 32'h00000000;
+parameter mask_gem1__screen_t1_r8 = 32'h00000000;
+
+parameter gem1__screen_t1_r9 = 32'hE000C524;
+parameter val_gem1__screen_t1_r9 = 32'h00000000;
+parameter mask_gem1__screen_t1_r9 = 32'h00000000;
+
+parameter gem1__screen_t1_r10 = 32'hE000C528;
+parameter val_gem1__screen_t1_r10 = 32'h00000000;
+parameter mask_gem1__screen_t1_r10 = 32'h00000000;
+
+parameter gem1__screen_t1_r11 = 32'hE000C52C;
+parameter val_gem1__screen_t1_r11 = 32'h00000000;
+parameter mask_gem1__screen_t1_r11 = 32'h00000000;
+
+parameter gem1__screen_t1_r12 = 32'hE000C530;
+parameter val_gem1__screen_t1_r12 = 32'h00000000;
+parameter mask_gem1__screen_t1_r12 = 32'h00000000;
+
+parameter gem1__screen_t1_r13 = 32'hE000C534;
+parameter val_gem1__screen_t1_r13 = 32'h00000000;
+parameter mask_gem1__screen_t1_r13 = 32'h00000000;
+
+parameter gem1__screen_t1_r14 = 32'hE000C538;
+parameter val_gem1__screen_t1_r14 = 32'h00000000;
+parameter mask_gem1__screen_t1_r14 = 32'h00000000;
+
+parameter gem1__screen_t1_r15 = 32'hE000C53C;
+parameter val_gem1__screen_t1_r15 = 32'h00000000;
+parameter mask_gem1__screen_t1_r15 = 32'h00000000;
+
+parameter gem1__screen_t2_r0 = 32'hE000C540;
+parameter val_gem1__screen_t2_r0 = 32'h00000000;
+parameter mask_gem1__screen_t2_r0 = 32'h00000000;
+
+parameter gem1__screen_t2_r1 = 32'hE000C544;
+parameter val_gem1__screen_t2_r1 = 32'h00000000;
+parameter mask_gem1__screen_t2_r1 = 32'h00000000;
+
+parameter gem1__screen_t2_r2 = 32'hE000C548;
+parameter val_gem1__screen_t2_r2 = 32'h00000000;
+parameter mask_gem1__screen_t2_r2 = 32'h00000000;
+
+parameter gem1__screen_t2_r3 = 32'hE000C54C;
+parameter val_gem1__screen_t2_r3 = 32'h00000000;
+parameter mask_gem1__screen_t2_r3 = 32'h00000000;
+
+parameter gem1__screen_t2_r4 = 32'hE000C550;
+parameter val_gem1__screen_t2_r4 = 32'h00000000;
+parameter mask_gem1__screen_t2_r4 = 32'h00000000;
+
+parameter gem1__screen_t2_r5 = 32'hE000C554;
+parameter val_gem1__screen_t2_r5 = 32'h00000000;
+parameter mask_gem1__screen_t2_r5 = 32'h00000000;
+
+parameter gem1__screen_t2_r6 = 32'hE000C558;
+parameter val_gem1__screen_t2_r6 = 32'h00000000;
+parameter mask_gem1__screen_t2_r6 = 32'h00000000;
+
+parameter gem1__screen_t2_r7 = 32'hE000C55C;
+parameter val_gem1__screen_t2_r7 = 32'h00000000;
+parameter mask_gem1__screen_t2_r7 = 32'h00000000;
+
+parameter gem1__screen_t2_r8 = 32'hE000C560;
+parameter val_gem1__screen_t2_r8 = 32'h00000000;
+parameter mask_gem1__screen_t2_r8 = 32'h00000000;
+
+parameter gem1__screen_t2_r9 = 32'hE000C564;
+parameter val_gem1__screen_t2_r9 = 32'h00000000;
+parameter mask_gem1__screen_t2_r9 = 32'h00000000;
+
+parameter gem1__screen_t2_r10 = 32'hE000C568;
+parameter val_gem1__screen_t2_r10 = 32'h00000000;
+parameter mask_gem1__screen_t2_r10 = 32'h00000000;
+
+parameter gem1__screen_t2_r11 = 32'hE000C56C;
+parameter val_gem1__screen_t2_r11 = 32'h00000000;
+parameter mask_gem1__screen_t2_r11 = 32'h00000000;
+
+parameter gem1__screen_t2_r12 = 32'hE000C570;
+parameter val_gem1__screen_t2_r12 = 32'h00000000;
+parameter mask_gem1__screen_t2_r12 = 32'h00000000;
+
+parameter gem1__screen_t2_r13 = 32'hE000C574;
+parameter val_gem1__screen_t2_r13 = 32'h00000000;
+parameter mask_gem1__screen_t2_r13 = 32'h00000000;
+
+parameter gem1__screen_t2_r14 = 32'hE000C578;
+parameter val_gem1__screen_t2_r14 = 32'h00000000;
+parameter mask_gem1__screen_t2_r14 = 32'h00000000;
+
+parameter gem1__screen_t2_r15 = 32'hE000C57C;
+parameter val_gem1__screen_t2_r15 = 32'h00000000;
+parameter mask_gem1__screen_t2_r15 = 32'h00000000;
+
+parameter gem1__intr_en_pq1 = 32'hE000C600;
+parameter val_gem1__intr_en_pq1 = 32'h00000000;
+parameter mask_gem1__intr_en_pq1 = 32'h00000000;
+
+parameter gem1__intr_en_pq2 = 32'hE000C604;
+parameter val_gem1__intr_en_pq2 = 32'h00000000;
+parameter mask_gem1__intr_en_pq2 = 32'h00000000;
+
+parameter gem1__intr_en_pq3 = 32'hE000C608;
+parameter val_gem1__intr_en_pq3 = 32'h00000000;
+parameter mask_gem1__intr_en_pq3 = 32'h00000000;
+
+parameter gem1__intr_en_pq4 = 32'hE000C60C;
+parameter val_gem1__intr_en_pq4 = 32'h00000000;
+parameter mask_gem1__intr_en_pq4 = 32'h00000000;
+
+parameter gem1__intr_en_pq5 = 32'hE000C610;
+parameter val_gem1__intr_en_pq5 = 32'h00000000;
+parameter mask_gem1__intr_en_pq5 = 32'h00000000;
+
+parameter gem1__intr_en_pq6 = 32'hE000C614;
+parameter val_gem1__intr_en_pq6 = 32'h00000000;
+parameter mask_gem1__intr_en_pq6 = 32'h00000000;
+
+parameter gem1__intr_en_pq7 = 32'hE000C618;
+parameter val_gem1__intr_en_pq7 = 32'h00000000;
+parameter mask_gem1__intr_en_pq7 = 32'h00000000;
+
+parameter gem1__intr_dis_pq1 = 32'hE000C620;
+parameter val_gem1__intr_dis_pq1 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq1 = 32'h00000000;
+
+parameter gem1__intr_dis_pq2 = 32'hE000C624;
+parameter val_gem1__intr_dis_pq2 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq2 = 32'h00000000;
+
+parameter gem1__intr_dis_pq3 = 32'hE000C628;
+parameter val_gem1__intr_dis_pq3 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq3 = 32'h00000000;
+
+parameter gem1__intr_dis_pq4 = 32'hE000C62C;
+parameter val_gem1__intr_dis_pq4 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq4 = 32'h00000000;
+
+parameter gem1__intr_dis_pq5 = 32'hE000C630;
+parameter val_gem1__intr_dis_pq5 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq5 = 32'h00000000;
+
+parameter gem1__intr_dis_pq6 = 32'hE000C634;
+parameter val_gem1__intr_dis_pq6 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq6 = 32'h00000000;
+
+parameter gem1__intr_dis_pq7 = 32'hE000C638;
+parameter val_gem1__intr_dis_pq7 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq7 = 32'h00000000;
+
+parameter gem1__intr_mask_pq1 = 32'hE000C640;
+parameter val_gem1__intr_mask_pq1 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq1 = 32'h00000000;
+
+parameter gem1__intr_mask_pq2 = 32'hE000C644;
+parameter val_gem1__intr_mask_pq2 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq2 = 32'h00000000;
+
+parameter gem1__intr_mask_pq3 = 32'hE000C648;
+parameter val_gem1__intr_mask_pq3 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq3 = 32'h00000000;
+
+parameter gem1__intr_mask_pq4 = 32'hE000C64C;
+parameter val_gem1__intr_mask_pq4 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq4 = 32'h00000000;
+
+parameter gem1__intr_mask_pq5 = 32'hE000C650;
+parameter val_gem1__intr_mask_pq5 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq5 = 32'h00000000;
+
+parameter gem1__intr_mask_pq6 = 32'hE000C654;
+parameter val_gem1__intr_mask_pq6 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq6 = 32'h00000000;
+
+parameter gem1__intr_mask_pq7 = 32'hE000C658;
+parameter val_gem1__intr_mask_pq7 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq7 = 32'h00000000;
+
+
+// ************************************************************
+//   Module gpio gpio
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpio__MASK_DATA_0_LSW = 32'hE000A000;
+parameter val_gpio__MASK_DATA_0_LSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_0_LSW = 32'hFFFF0000;
+
+parameter gpio__MASK_DATA_0_MSW = 32'hE000A004;
+parameter val_gpio__MASK_DATA_0_MSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_0_MSW = 32'hFFFF0000;
+
+parameter gpio__MASK_DATA_1_LSW = 32'hE000A008;
+parameter val_gpio__MASK_DATA_1_LSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_1_LSW = 32'hFFFF0000;
+
+parameter gpio__MASK_DATA_1_MSW = 32'hE000A00C;
+parameter val_gpio__MASK_DATA_1_MSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_1_MSW = 32'h003FFFC0;
+
+parameter gpio__MASK_DATA_2_LSW = 32'hE000A010;
+parameter val_gpio__MASK_DATA_2_LSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_2_LSW = 32'hFFFFFFFF;
+
+parameter gpio__MASK_DATA_2_MSW = 32'hE000A014;
+parameter val_gpio__MASK_DATA_2_MSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_2_MSW = 32'hFFFFFFFF;
+
+parameter gpio__MASK_DATA_3_LSW = 32'hE000A018;
+parameter val_gpio__MASK_DATA_3_LSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_3_LSW = 32'hFFFFFFFF;
+
+parameter gpio__MASK_DATA_3_MSW = 32'hE000A01C;
+parameter val_gpio__MASK_DATA_3_MSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_3_MSW = 32'hFFFFFFFF;
+
+parameter gpio__DATA_0 = 32'hE000A040;
+parameter val_gpio__DATA_0 = 32'h00000000;
+parameter mask_gpio__DATA_0 = 32'h00000000;
+
+parameter gpio__DATA_1 = 32'hE000A044;
+parameter val_gpio__DATA_1 = 32'h00000000;
+parameter mask_gpio__DATA_1 = 32'h00000000;
+
+parameter gpio__DATA_2 = 32'hE000A048;
+parameter val_gpio__DATA_2 = 32'h00000000;
+parameter mask_gpio__DATA_2 = 32'hFFFFFFFF;
+
+parameter gpio__DATA_3 = 32'hE000A04C;
+parameter val_gpio__DATA_3 = 32'h00000000;
+parameter mask_gpio__DATA_3 = 32'hFFFFFFFF;
+
+parameter gpio__DATA_0_RO = 32'hE000A060;
+parameter val_gpio__DATA_0_RO = 32'h00000000;
+parameter mask_gpio__DATA_0_RO = 32'h00000000;
+
+parameter gpio__DATA_1_RO = 32'hE000A064;
+parameter val_gpio__DATA_1_RO = 32'h00000000;
+parameter mask_gpio__DATA_1_RO = 32'h00000000;
+
+parameter gpio__DATA_2_RO = 32'hE000A068;
+parameter val_gpio__DATA_2_RO = 32'h00000000;
+parameter mask_gpio__DATA_2_RO = 32'hFFFFFFFF;
+
+parameter gpio__DATA_3_RO = 32'hE000A06C;
+parameter val_gpio__DATA_3_RO = 32'h00000000;
+parameter mask_gpio__DATA_3_RO = 32'hFFFFFFFF;
+
+parameter gpio__BYPM_0 = 32'hE000A200;
+parameter val_gpio__BYPM_0 = 32'h00000000;
+parameter mask_gpio__BYPM_0 = 32'hFFFFFFFF;
+
+parameter gpio__DIRM_0 = 32'hE000A204;
+parameter val_gpio__DIRM_0 = 32'h00000000;
+parameter mask_gpio__DIRM_0 = 32'hFFFFFFFF;
+
+parameter gpio__OEN_0 = 32'hE000A208;
+parameter val_gpio__OEN_0 = 32'h00000000;
+parameter mask_gpio__OEN_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_MASK_0 = 32'hE000A20C;
+parameter val_gpio__INT_MASK_0 = 32'h00000000;
+parameter mask_gpio__INT_MASK_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_EN_0 = 32'hE000A210;
+parameter val_gpio__INT_EN_0 = 32'h00000000;
+parameter mask_gpio__INT_EN_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_DIS_0 = 32'hE000A214;
+parameter val_gpio__INT_DIS_0 = 32'h00000000;
+parameter mask_gpio__INT_DIS_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_STAT_0 = 32'hE000A218;
+parameter val_gpio__INT_STAT_0 = 32'h00000000;
+parameter mask_gpio__INT_STAT_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_TYPE_0 = 32'hE000A21C;
+parameter val_gpio__INT_TYPE_0 = 32'hFFFFFFFF;
+parameter mask_gpio__INT_TYPE_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_POLARITY_0 = 32'hE000A220;
+parameter val_gpio__INT_POLARITY_0 = 32'h00000000;
+parameter mask_gpio__INT_POLARITY_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_ANY_0 = 32'hE000A224;
+parameter val_gpio__INT_ANY_0 = 32'h00000000;
+parameter mask_gpio__INT_ANY_0 = 32'hFFFFFFFF;
+
+parameter gpio__BYPM_1 = 32'hE000A240;
+parameter val_gpio__BYPM_1 = 32'h00000000;
+parameter mask_gpio__BYPM_1 = 32'h003FFFFF;
+
+parameter gpio__DIRM_1 = 32'hE000A244;
+parameter val_gpio__DIRM_1 = 32'h00000000;
+parameter mask_gpio__DIRM_1 = 32'h003FFFFF;
+
+parameter gpio__OEN_1 = 32'hE000A248;
+parameter val_gpio__OEN_1 = 32'h00000000;
+parameter mask_gpio__OEN_1 = 32'h003FFFFF;
+
+parameter gpio__INT_MASK_1 = 32'hE000A24C;
+parameter val_gpio__INT_MASK_1 = 32'h00000000;
+parameter mask_gpio__INT_MASK_1 = 32'h003FFFFF;
+
+parameter gpio__INT_EN_1 = 32'hE000A250;
+parameter val_gpio__INT_EN_1 = 32'h00000000;
+parameter mask_gpio__INT_EN_1 = 32'h003FFFFF;
+
+parameter gpio__INT_DIS_1 = 32'hE000A254;
+parameter val_gpio__INT_DIS_1 = 32'h00000000;
+parameter mask_gpio__INT_DIS_1 = 32'h003FFFFF;
+
+parameter gpio__INT_STAT_1 = 32'hE000A258;
+parameter val_gpio__INT_STAT_1 = 32'h00000000;
+parameter mask_gpio__INT_STAT_1 = 32'h003FFFFF;
+
+parameter gpio__INT_TYPE_1 = 32'hE000A25C;
+parameter val_gpio__INT_TYPE_1 = 32'h003FFFFF;
+parameter mask_gpio__INT_TYPE_1 = 32'h003FFFFF;
+
+parameter gpio__INT_POLARITY_1 = 32'hE000A260;
+parameter val_gpio__INT_POLARITY_1 = 32'h00000000;
+parameter mask_gpio__INT_POLARITY_1 = 32'h003FFFFF;
+
+parameter gpio__INT_ANY_1 = 32'hE000A264;
+parameter val_gpio__INT_ANY_1 = 32'h00000000;
+parameter mask_gpio__INT_ANY_1 = 32'h003FFFFF;
+
+parameter gpio__BYPM_2 = 32'hE000A280;
+parameter val_gpio__BYPM_2 = 32'h00000000;
+parameter mask_gpio__BYPM_2 = 32'hFFFFFFFF;
+
+parameter gpio__DIRM_2 = 32'hE000A284;
+parameter val_gpio__DIRM_2 = 32'h00000000;
+parameter mask_gpio__DIRM_2 = 32'hFFFFFFFF;
+
+parameter gpio__OEN_2 = 32'hE000A288;
+parameter val_gpio__OEN_2 = 32'h00000000;
+parameter mask_gpio__OEN_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_MASK_2 = 32'hE000A28C;
+parameter val_gpio__INT_MASK_2 = 32'h00000000;
+parameter mask_gpio__INT_MASK_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_EN_2 = 32'hE000A290;
+parameter val_gpio__INT_EN_2 = 32'h00000000;
+parameter mask_gpio__INT_EN_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_DIS_2 = 32'hE000A294;
+parameter val_gpio__INT_DIS_2 = 32'h00000000;
+parameter mask_gpio__INT_DIS_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_STAT_2 = 32'hE000A298;
+parameter val_gpio__INT_STAT_2 = 32'h00000000;
+parameter mask_gpio__INT_STAT_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_TYPE_2 = 32'hE000A29""b""C;
+parameter val_gpio__INT_TYPE_2 = 32'hFFFFFFFF;
+parameter mask_gpio__INT_TYPE_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_POLARITY_2 = 32'hE000A2A0;
+parameter val_gpio__INT_POLARITY_2 = 32'h00000000;
+parameter mask_gpio__INT_POLARITY_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_ANY_2 = 32'hE000A2A4;
+parameter val_gpio__INT_ANY_2 = 32'h00000000;
+parameter mask_gpio__INT_ANY_2 = 32'hFFFFFFFF;
+
+parameter gpio__BYPM_3 = 32'hE000A2C0;
+parameter val_gpio__BYPM_3 = 32'h00000000;
+parameter mask_gpio__BYPM_3 = 32'hFFFFFFFF;
+
+parameter gpio__DIRM_3 = 32'hE000A2C4;
+parameter val_gpio__DIRM_3 = 32'h00000000;
+parameter mask_gpio__DIRM_3 = 32'hFFFFFFFF;
+
+parameter gpio__OEN_3 = 32'hE000A2C8;
+parameter val_gpio__OEN_3 = 32'h00000000;
+parameter mask_gpio__OEN_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_MASK_3 = 32'hE000A2CC;
+parameter val_gpio__INT_MASK_3 = 32'h00000000;
+parameter mask_gpio__INT_MASK_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_EN_3 = 32'hE000A2D0;
+parameter val_gpio__INT_EN_3 = 32'h00000000;
+parameter mask_gpio__INT_EN_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_DIS_3 = 32'hE000A2D4;
+parameter val_gpio__INT_DIS_3 = 32'h00000000;
+parameter mask_gpio__INT_DIS_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_STAT_3 = 32'hE000A2D8;
+parameter val_gpio__INT_STAT_3 = 32'h00000000;
+parameter mask_gpio__INT_STAT_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_TYPE_3 = 32'hE000A2DC;
+parameter val_gpio__INT_TYPE_3 = 32'hFFFFFFFF;
+parameter mask_gpio__INT_TYPE_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_POLARITY_3 = 32'hE000A2E0;
+parameter val_gpio__INT_POLARITY_3 = 32'h00000000;
+parameter mask_gpio__INT_POLARITY_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_ANY_3 = 32'hE000A2E4;
+parameter val_gpio__INT_ANY_3 = 32'h00000000;
+parameter mask_gpio__INT_ANY_3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module gpv_iou_switch gpv_iou_switch
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_iou_switch__Remap = 32'hE0200000;
+parameter val_gpv_iou_switch__Remap = 32'h00000000;
+parameter mask_gpv_iou_switch__Remap = 32'h000000FF;
+
+parameter gpv_iou_switch__security2_sdio0 = 32'hE0200008;
+parameter val_gpv_iou_switch__security2_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__security2_sdio0 = 32'h00000001;
+
+parameter gpv_iou_switch__security3_sdio1 = 32'hE020000C;
+parameter val_gpv_iou_switch__security3_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__security3_sdio1 = 32'h00000001;
+
+parameter gpv_iou_switch__security4_qspi = 32'hE0200010;
+parameter val_gpv_iou_switch__security4_qspi = 32'h00000000;
+parameter mask_gpv_iou_switch__security4_qspi = 32'h00000001;
+
+parameter gpv_iou_switch__security5_miou = 32'hE0200014;
+parameter val_gpv_iou_switch__security5_miou = 32'h00000000;
+parameter mask_gpv_iou_switch__security5_miou = 32'h00000001;
+
+parameter gpv_iou_switch__security6_apb_slaves = 32'hE0200018;
+parameter val_gpv_iou_switch__security6_apb_slaves = 32'h00000000;
+parameter mask_gpv_iou_switch__security6_apb_slaves = 32'h00007FFF;
+
+parameter gpv_iou_switch__security7_smc = 32'hE020001C;
+parameter val_gpv_iou_switch__security7_smc = 32'h00000000;
+parameter mask_gpv_iou_switch__security7_smc = 32'h00000001;
+
+parameter gpv_iou_switch__peripheral_id4 = 32'hE0201FD0;
+parameter val_gpv_iou_switch__peripheral_id4 = 32'h00000004;
+parameter mask_gpv_iou_switch__peripheral_id4 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id5 = 32'hE0201FD4;
+parameter val_gpv_iou_switch__peripheral_id5 = 32'h00000000;
+parameter mask_gpv_iou_switch__peripheral_id5 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id6 = 32'hE0201FD8;
+parameter val_gpv_iou_switch__peripheral_id6 = 32'h00000000;
+parameter mask_gpv_iou_switch__peripheral_id6 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id7 = 32'hE0201FDC;
+parameter val_gpv_iou_switch__peripheral_id7 = 32'h00000000;
+parameter mask_gpv_iou_switch__peripheral_id7 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id0 = 32'hE0201FE0;
+parameter val_gpv_iou_switch__peripheral_id0 = 32'h00000001;
+parameter mask_gpv_iou_switch__peripheral_id0 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id1 = 32'hE0201FE4;
+parameter val_gpv_iou_switch__peripheral_id1 = 32'h000000B3;
+parameter mask_gpv_iou_switch__peripheral_id1 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id2 = 32'hE0201FE8;
+parameter val_gpv_iou_switch__peripheral_id2 = 32'h0000005B;
+parameter mask_gpv_iou_switch__peripheral_id2 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id3 = 32'hE0201FEC;
+parameter val_gpv_iou_switch__peripheral_id3 = 32'h00000000;
+parameter mask_gpv_iou_switch__peripheral_id3 = 32'h000000FF;
+
+parameter gpv_iou_switch__component_id0 = 32'hE0201FF0;
+parameter val_gpv_iou_switch__component_id0 = 32'h0000000D;
+parameter mask_gpv_iou_switch__component_id0 = 32'h000000FF;
+
+parameter gpv_iou_switch__component_id1 = 32'hE0201FF4;
+parameter val_gpv_iou_switch__component_id1 = 32'h000000F0;
+parameter mask_gpv_iou_switch__component_id1 = 32'h000000FF;
+
+parameter gpv_iou_switch__component_id2 = 32'hE0201FF8;
+parameter val_gpv_iou_switch__component_id2 = 32'h00000005;
+parameter mask_gpv_iou_switch__component_id2 = 32'h000000FF;
+
+parameter gpv_iou_switch__component_id3 = 32'hE0201FFC;
+parameter val_gpv_iou_switch__component_id3 = 32'h000000B1;
+parameter mask_gpv_iou_switch__component_id3 = 32'h000000FF;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'hE0202008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000003;
+
+parameter gpv_iou_switch__ahb_cntl_sdio0 = 32'hE0202044;
+parameter val_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'hE0203008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000003;
+
+parameter gpv_iou_switch__ahb_cntl_sdio1 = 32'hE0203044;
+parameter val_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_qspi = 32'hE0204008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_miou = 32'hE0205008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_smc = 32'hE0207008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_gem0 = 32'hE0242028;
+parameter val_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_gem0 = 32'hE0242100;
+parameter val_gpv_iou_switch__read_qos_gem0 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_gem0 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_gem0 = 32'hE0242104;
+parameter val_gpv_iou_switch__write_qos_gem0 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_gem0 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_gem0 = 32'hE0242108;
+parameter val_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_gem1 = 32'hE0243028;
+parameter val_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_gem1 = 32'hE0243100;
+parameter val_gpv_iou_switch__read_qos_gem1 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_gem1 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_gem1 = 32'hE0243104;
+parameter val_gpv_iou_switch__write_qos_gem1 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_gem1 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_gem1 = 32'hE0243108;
+parameter val_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_usb0 = 32'hE0244028;
+parameter val_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_usb0 = 32'hE0244100;
+parameter val_gpv_iou_switch__read_qos_usb0 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_usb0 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_usb0 = 32'hE0244104;
+parameter val_gpv_iou_switch__write_qos_usb0 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_usb0 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_usb0 = 32'hE0244108;
+parameter val_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_usb1 = 32'hE0245028;
+parameter val_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_usb1 = 32'hE0245100;
+parameter val_gpv_iou_switch__read_qos_usb1 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_usb1 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_usb1 = 32'hE0245104;
+parameter val_gpv_iou_switch__write_qos_usb1 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_usb1 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_usb1 = 32'hE0245108;
+parameter val_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_sdio0 = 32'hE0246028;
+parameter val_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_sdio0 = 32'hE0246100;
+parameter val_gpv_iou_switch__read_qos_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_sdio0 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_sdio0 = 32'hE0246104;
+parameter val_gpv_iou_switch__write_qos_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_sdio0 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_sdio0 = 32'hE0246108;
+parameter val_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_sdio1 = 32'hE0247028;
+parameter val_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_sdio1 = 32'hE0247100;
+parameter val_gpv_iou_switch__read_qos_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_sdio1 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_sdio1 = 32'hE0247104;
+parameter val_gpv_iou_switch__write_qos_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_sdio1 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_sdio1 = 32'hE0247108;
+parameter val_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_iss_siou = 32'hE0249108;
+parameter val_gpv_iou_switch__fn_mod_iss_siou = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_siou = 32'h00000003;
+
+
+// ************************************************************
+//   Module gpv_qos301_cpu qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_qos301_cpu__qos_cntl = 32'hF894610C;
+parameter val_gpv_qos301_cpu__qos_cntl = 32'h00000000;
+parameter mask_gpv_qos301_cpu__qos_cntl = 32'h000000FF;
+
+parameter gpv_qos301_cpu__max_ot = 32'hF8946110;
+parameter val_gpv_qos301_cpu__max_ot = 32'h00000000;
+parameter mask_gpv_qos301_cpu__max_ot = 32'h3FFF3FFF;
+
+parameter gpv_qos301_cpu__max_comb_ot = 32'hF8946114;
+parameter val_gpv_qos301_cpu__max_comb_ot = 32'h00000000;
+parameter mask_gpv_qos301_cpu__max_comb_ot = 32'h00007FFF;
+
+parameter gpv_qos301_cpu__aw_p = 32'hF8946118;
+parameter val_gpv_qos301_cpu__aw_p = 32'h00000000;
+parameter mask_gpv_qos301_cpu__aw_p = 32'hFF000000;
+
+parameter gpv_qos301_cpu__aw_b = 32'hF894611C;
+parameter val_gpv_qos301_cpu__aw_b = 32'h00000000;
+parameter mask_gpv_qos301_cpu__aw_b = 32'h0000FFFF;
+
+parameter gpv_qos301_cpu__aw_r = 32'hF8946120;
+parameter val_gpv_qos301_cpu__aw_r = 32'h00000000;
+parameter mask_gpv_qos301_cpu__aw_r = 32'hFFF00000;
+
+parameter gpv_qos301_cpu__ar_p = 32'hF8946124;
+parameter val_gpv_qos301_cpu__ar_p = 32'h00000000;
+parameter mask_gpv_qos301_cpu__ar_p = 32'hFF000000;
+
+parameter gpv_qos301_cpu__ar_b = 32'hF8946128;
+parameter val_gpv_qos301_cpu__ar_b = 32'h00000000;
+parameter mask_gpv_qos301_cpu__ar_b = 32'h0000FFFF;
+
+parameter gpv_qos301_cpu__ar_r = 32'hF894612C;
+parameter val_gpv_qos301_cpu__ar_r = 32'h00000000;
+parameter mask_gpv_qos301_cpu__ar_r = 32'hFFF00000;
+
+
+// ************************************************************
+//   Module gpv_qos301_dmac qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_qos301_dmac__qos_cntl = 32'hF894710C;
+parameter val_gpv_qos301_dmac__qos_cntl = 32'h00000000;
+parameter mask_gpv_qos301_dmac__qos_cntl = 32'h000000FF;
+
+parameter gpv_qos301_dmac__max_ot = 32'hF8947110;
+parameter val_gpv_qos301_dmac__max_ot = 32'h00000000;
+parameter mask_gpv_qos301_dmac__max_ot = 32'h3FFF3FFF;
+
+parameter gpv_qos301_dmac__max_comb_ot = 32'hF8947114;
+parameter val_gpv_qos301_dmac__max_comb_ot = 32'h00000000;
+parameter mask_gpv_qos301_dmac__max_comb_ot = 32'h00007FFF;
+
+parameter gpv_qos301_dmac__aw_p = 32'hF8947118;
+parameter val_gpv_qos301_dmac__aw_p = 32'h00000000;
+parameter mask_gpv_qos301_dmac__aw_p = 32'hFF000000;
+
+parameter gpv_qos301_dmac__aw_b = 32'hF894711C;
+parameter val_gpv_qos301_dmac__aw_b = 32'h00000000;
+parameter mask_gpv_qos301_dmac__aw_b = 32'h0000FFFF;
+
+parameter gpv_qos301_dmac__aw_r = 32'hF8947120;
+parameter val_gpv_qos301_dmac__aw_r = 32'h00000000;
+parameter mask_gpv_qos301_dmac__aw_r = 32'hFFF00000;
+
+parameter gpv_qos301_dmac__ar_p = 32'hF8947124;
+parameter val_gpv_qos301_dmac__ar_p = 32'h00000000;
+parameter mask_gpv_qos301_dmac__ar_p = 32'hFF000000;
+
+parameter gpv_qos301_dmac__ar_b = 32'hF8947128;
+parameter val_gpv_qos301_dmac__ar_b = 32'h00000000;
+parameter mask_gpv_qos301_dmac__ar_b = 32'h0000FFFF;
+
+parameter gpv_qos301_dmac__ar_r = 32'hF894712C;
+parameter val_gpv_qos301_dmac__ar_r = 32'h00000000;
+parameter mask_gpv_qos301_dmac__ar_r = 32'hFFF00000;
+
+
+// ************************************************************
+//   Module gpv_qos301_iou qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_qos301_iou__qos_cntl = 32'hF894810C;
+parameter val_gpv_qos301_iou__qos_cntl = 32'h00000000;
+parameter mask_gpv_qos301_iou__qos_cntl = 32'h000000FF;
+
+parameter gpv_qos301_iou__max_ot = 32'hF8948110;
+parameter val_gpv_qos301_iou__max_ot = 32'h00000000;
+parameter mask_gpv_qos301_iou__max_ot = 32'h3FFF3FFF;
+
+parameter gpv_qos301_iou__max_comb_ot = 32'hF8948114;
+parameter val_gpv_qos301_iou__max_comb_ot = 32'h00000000;
+parameter mask_gpv_qos301_iou__max_comb_ot = 32'h00007FFF;
+
+parameter gpv_qos301_iou__aw_p = 32'hF8948118;
+parameter val_gpv_qos301_iou__aw_p = 32'h00000000;
+parameter mask_gpv_qos301_iou__aw_p = 32'hFF000000;
+
+parameter gpv_qos301_iou__aw_b = 32'hF894811C;
+parameter val_gpv_qos301_iou__aw_b = 32'h00000000;
+parameter mask_gpv_qos301_iou__aw_b = 32'h0000FFFF;
+
+parameter gpv_qos301_iou__aw_r = 32'hF8948120;
+parameter val_gpv_qos301_iou__aw_r = 32'h00000000;
+parameter mask_gpv_qos301_iou__aw_r = 32'hFFF00000;
+
+parameter gpv_qos301_iou__ar_p = 32'hF8948124;
+parameter val_gpv_qos301_iou__ar_p = 32'h00000000;
+parameter mask_gpv_qos301_iou__ar_p = 32'hFF000000;
+
+parameter gpv_qos301_iou__ar_b = 32'hF8948128;
+parameter val_gpv_qos301_iou__ar_b = 32'h00000000;
+parameter mask_gpv_qos301_iou__ar_b = 32'h0000FFFF;
+
+parameter gpv_qos301_iou__ar_r = 32'hF894812C;
+parameter val_gpv_qos301_iou__ar_r = 32'h00000000;
+parameter mask_gpv_qos301_iou__ar_r = 32'hFFF00000;
+
+
+// ************************************************************
+//   Module gpv_trustzone nic301_addr_region_ctrl_registers
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_trustzone__Remap = 32'hF8900000;
+parameter val_gpv_trustzone__Remap = 32'h00000000;
+parameter mask_gpv_trustzone__Remap = 32'h000000C0;
+
+parameter gpv_trustzone__security_fssw_s0 = 32'hF890001C;
+parameter val_gpv_trustzone__security_fssw_s0 = 32'h00000000;
+parameter mask_gpv_trustzone__security_fssw_s0 = 32'h00000001;
+
+parameter gpv_trustzone__security_fssw_s1 = 32'hF8900020;
+parameter val_gpv_trustzone__security_fssw_s1 = 32'h00000000;
+parameter mask_gpv_trustzone__security_fssw_s1 = 32'h00000001;
+
+parameter gpv_trustzone__security_apb = 32'hF8900028;
+parameter val_gpv_trustzone__security_apb = 32'h00000000;
+parameter mask_gpv_trustzone__security_apb = 32'h0000003F;
+
+
+// ************************************************************
+//   Module i2c0 IIC
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter i2c0__Control_reg0 = 32'hE0004000;
+parameter val_i2c0__Control_reg0 = 32'h00000000;
+parameter mask_i2c0__Control_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Status_reg0 = 32'hE0004004;
+parameter val_i2c0__Status_reg0 = 32'h00000000;
+parameter mask_i2c0__Status_reg0 = 32'h0000FFFF;
+
+parameter i2c0__I2C_address_reg0 = 32'hE0004008;
+parameter val_i2c0__I2C_address_reg0 = 32'h00000000;
+parameter mask_i2c0__I2C_address_reg0 = 32'h0000FFFF;
+
+parameter i2c0__I2C_data_reg0 = 32'hE000400C;
+parameter val_i2c0__I2C_data_reg0 = 32'h00000000;
+parameter mask_i2c0__I2C_data_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Interrupt_status_reg0 = 32'hE0004010;
+parameter val_i2c0__Interrupt_status_reg0 = 32'h00000000;
+parameter mask_i2c0__Interrupt_status_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Transfer_size_reg0 = 32'hE0004014;
+parameter val_i2c0__Transfer_size_reg0 = 32'h00000000;
+parameter mask_i2c0__Transfer_size_reg0 = 32'h000000FF;
+
+parameter i2c0__Slave_mon_pause_reg0 = 32'hE0004018;
+parameter val_i2c0__Slave_mon_pause_reg0 = 32'h00000000;
+parameter mask_i2c0__Slave_mon_pause_reg0 = 32'h000000FF;
+
+parameter i2c0__Time_out_reg0 = 32'hE000401C;
+parameter val_i2c0__Time_out_reg0 = 32'h0000001F;
+parameter mask_i2c0__Time_out_reg0 = 32'h000000FF;
+
+parameter i2c0__Intrpt_mask_reg0 = 32'hE0004020;
+parameter val_i2c0__Intrpt_mask_reg0 = 32'h000002FF;
+parameter mask_i2c0__Intrpt_mask_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Intrpt_enable_reg0 = 32'hE0004024;
+parameter val_i2c0__Intrpt_enable_reg0 = 32'h00000000;
+parameter mask_i2c0__Intrpt_enable_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Intrpt_disable_reg0 = 32'hE0004028;
+parameter val_i2c0__Intrpt_disable_reg0 = 32'h00000000;
+parameter mask_i2c0__Intrpt_disable_reg0 = 32'h0000FFFF;
+
+
+// ************************************************************
+//   Module i2c1 IIC
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter i2c1__Control_reg0 = 32'hE0005000;
+parameter val_i2c1__Control_reg0 = 32'h00000000;
+parameter mask_i2c1__Control_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Status_reg0 = 32'hE0005004;
+parameter val_i2c1__Status_reg0 = 32'h00000000;
+parameter mask_i2c1__Status_reg0 = 32'h0000FFFF;
+
+parameter i2c1__I2C_address_reg0 = 32'hE0005008;
+parameter val_i2c1__I2C_address_reg0 = 32'h00000000;
+parameter mask_i2c1__I2C_address_reg0 = 32'h0000FFFF;
+
+parameter i2c1__I2C_data_reg0 = 32'hE000500C;
+parameter val_i2c1__I2C_data_reg0 = 32'h00000000;
+parameter mask_i2c1__I2C_data_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Interrupt_status_reg0 = 32'hE0005010;
+parameter val_i2c1__Interrupt_status_reg0 = 32'h00000000;
+parameter mask_i2c1__Interrupt_status_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Transfer_size_reg0 = 32'hE0005014;
+parameter val_i2c1__Transfer_size_reg0 = 32'h00000000;
+parameter mask_i2c1__Transfer_size_reg0 = 32'h000000FF;
+
+parameter i2c1__Slave_mon_pause_reg0 = 32'hE0005018;
+parameter val_i2c1__Slave_mon_pause_reg0 = 32'h00000000;
+parameter mask_i2c1__Slave_mon_pause_reg0 = 32'h000000FF;
+
+parameter i2c1__Time_out_reg0 = 32'hE000501C;
+parameter val_i2c1__Time_out_reg0 = 32'h0000001F;
+parameter mask_i2c1__Time_out_reg0 = 32'h000000FF;
+
+parameter i2c1__Intrpt_mask_reg0 = 32'hE0005020;
+parameter val_i2c1__Intrpt_mask_reg0 = 32'h000002FF;
+parameter mask_i2c1__Intrpt_mask_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Intrpt_enable_reg0 = 32'hE0005024;
+parameter val_i2c1__Intrpt_enable_reg0 = 32'h00000000;
+parameter mask_i2c1__Intrpt_enable_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Intrpt_disable_reg0 = 32'hE0005028;
+parameter val_i2c1__Intrpt_disable_reg0 = 32'h00000000;
+parameter mask_i2c1__Intrpt_disable_reg0 = 32'h0000FFFF;
+
+
+// ************************************************************
+//   Module l2cache L2Cpl310
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter l2cache__reg0_cache_id = 32'hF8F02000;
+parameter val_l2cache__reg0_cache_id = 32'h410000C8;
+parameter mask_l2cache__reg0_cache_id = 32'hFFFFFFFF;
+
+parameter l2cache__reg0_cache_type = 32'hF8F02004;
+parameter val_l2cache__reg0_cache_type = 32'h9E300300;
+parameter mask_l2cache__reg0_cache_type = 32'hFFFFFFFF;
+
+parameter l2cache__reg1_control = 32'hF8F02100;
+parameter val_l2cache__reg1_control = 32'h00000000;
+parameter mask_l2cache__reg1_control = 32'h7FFFFFFF;
+
+parameter l2cache__reg1_aux_control = 32'hF8F02104;
+parameter val_l2cache__reg1_aux_control = 32'h02050000;
+parameter mask_l2cache__reg1_aux_control = 32'hFFFFFFFF;
+
+parameter l2cache__reg1_tag_ram_control = 32'hF8F02108;
+parameter val_l2cache__reg1_tag_ram_control = 32'h00000777;
+parameter mask_l2cache__reg1_tag_ram_control = 32'hFFFFFFFF;
+
+parameter l2cache__reg1_data_ram_control = 32'hF8F0210C;
+parameter val_l2cache__reg1_data_ram_control = 32'h00000777;
+parameter mask_l2cache__reg1_data_ram_control = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter_ctrl = 32'hF8F02200;
+parameter val_l2cache__reg2_ev_counter_ctrl = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter_ctrl = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter1_cfg = 32'hF8F02204;
+parameter val_l2cache__reg2_ev_counter1_cfg = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter1_cfg = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter0_cfg = 32'hF8F02208;
+parameter val_l2cache__reg2_ev_counter0_cfg = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter0_cfg = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter1 = 32'hF8F0220C;
+parameter val_l2cache__reg2_ev_counter1 = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter1 = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter0 = 32'hF8F02210;
+parameter val_l2cache__reg2_ev_counter0 = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter0 = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_int_mask = 32'hF8F02214;
+parameter val_l2cache__reg2_int_mask = 32'h00000000;
+parameter mask_l2cache__reg2_int_mask = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_int_mask_status = 32'hF8F02218;
+parameter val_l2cache__reg2_int_mask_status = 32'h00000000;
+parameter mask_l2cache__reg2_int_mask_status = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_int_raw_status = 32'hF8F0221C;
+parameter val_l2cache__reg2_int_raw_status = 32'h00000000;
+parameter mask_l2cache__reg2_int_raw_status = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_int_clear = 32'hF8F02220;
+parameter val_l2cache__reg2_int_clear = 32'h00000000;
+parameter mask_l2cache__reg2_int_clear = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_cache_sync = 32'hF8F02730;
+parameter val_l2cache__reg7_cache_sync = 32'h00000000;
+parameter mask_l2cache__reg7_cache_sync = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_inv_pa = 32'hF8F02770;
+parameter val_l2cache__reg7_inv_pa = 32'h00000000;
+parameter mask_l2cache__reg7_inv_pa = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_inv_way = 32'hF8F0277C;
+parameter val_l2cache__reg7_inv_way = 32'h00000000;
+parameter mask_l2cache__reg7_inv_way = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_pa = 32'hF8F027B0;
+parameter val_l2cache__reg7_clean_pa = 32'h00000000;
+parameter mask_l2cache__reg7_clean_pa = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_index = 32'hF8F027B8;
+parameter val_l2cache__reg7_clean_index = 32'h00000000;
+parameter mask_l2cache__reg7_clean_index = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_way = 32'hF8F027BC;
+parameter val_l2cache__reg7_clean_way = 32'h00000000;
+parameter mask_l2cache__reg7_clean_way = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_inv_pa = 32'hF8F027F0;
+parameter val_l2cache__reg7_clean_inv_pa = 32'h00000000;
+parameter mask_l2cache__reg7_clean_inv_pa = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_inv_index = 32'hF8F027F8;
+parameter val_l2cache__reg7_clean_inv_index = 32'h00000000;
+parameter mask_l2cache__reg7_clean_inv_index = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_inv_way = 32'hF8F027FC;
+parameter val_l2cache__reg7_clean_inv_way = 32'h00000000;
+parameter mask_l2cache__reg7_clean_inv_way = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown0 = 32'hF8F02900;
+parameter val_l2cache__reg9_d_lockdown0 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown0 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown0 = 32'hF8F02904;
+parameter val_l2cache__reg9_i_lockdown0 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown0 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown1 = 32'hF8F02908;
+parameter val_l2cache__reg9_d_lockdown1 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown1 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown1 = 32'hF8F0290C;
+parameter val_l2cache__reg9_i_lockdown1 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown1 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown2 = 32'hF8F02910;
+parameter val_l2cache__reg9_d_lockdown2 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown2 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown2 = 32'hF8F02914;
+parameter val_l2cache__reg9_i_lockdown2 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown2 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown3 = 32'hF8F02918;
+parameter val_l2cache__reg9_d_lockdown3 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown3 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown3 = 32'hF8F0291C;
+parameter val_l2cache__reg9_i_lockdown3 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown3 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown4 = 32'hF8F02920;
+parameter val_l2cache__reg9_d_lockdown4 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown4 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown4 = 32'hF8F02924;
+parameter val_l2cache__reg9_i_lockdown4 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown4 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown5 = 32'hF8F02928;
+parameter val_l2cache__reg9_d_lockdown5 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown5 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown5 = 32'hF8F0292C;
+parameter val_l2cache__reg9_i_lockdown5 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown5 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown6 = 32'hF8F02930;
+parameter val_l2cache__reg9_d_lockdown6 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown6 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown6 = 32'hF8F02934;
+parameter val_l2cache__reg9_i_lockdown6 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown6 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown7 = 32'hF8F02938;
+parameter val_l2cache__reg9_d_lockdown7 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown7 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown7 = 32'hF8F0293C;
+parameter val_l2cache__reg9_i_lockdown7 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown7 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_lock_line_en = 32'hF8F02950;
+parameter val_l2cache__reg9_lock_line_en = 32'h00000000;
+parameter mask_l2cache__reg9_lock_line_en = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_unlock_way = 32'hF8F02954;
+parameter val_l2cache__reg9_unlock_way = 32'h00000000;
+parameter mask_l2cache__reg9_unlock_way = 32'hFFFFFFFF;
+
+parameter l2cache__reg12_addr_filtering_start = 32'hF8F02C00;
+parameter val_l2cache__reg12_addr_filtering_start = 32'h40000001;
+parameter mask_l2cache__reg12_addr_filtering_start = 32'hFFFFFFFF;
+
+parameter l2cache__reg12_addr_filtering_end = 32'hF8F02C04;
+parameter val_l2cache__reg12_addr_filtering_end = 32'hFFF00000;
+parameter mask_l2cache__reg12_addr_filtering_end = 32'hFFFFFFFF;
+
+parameter l2cache__reg15_debug_ctrl = 32'hF8F02F40;
+parameter val_l2cache__reg15_debug_ctrl = 32'h00000000;
+parameter mask_l2cache__reg15_debug_ctrl = 32'hFFFFFFFF;
+
+parameter l2cache__reg15_prefetch_ctrl = 32'hF8F02F60;
+parameter val_l2cache__reg15_prefetch_ctrl = 32'h00000000;
+parameter mask_l2cache__reg15_prefetch_ctrl = 32'hFFFFFFFF;
+
+parameter l2cache__reg15_power_ctrl = 32'hF8F02F80;
+parameter val_l2cache__reg15_power_ctrl = 32'h00000000;
+parameter mask_l2cache__reg15_power_ctrl = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module mpcore mpcore
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter mpcore__SCU_CONTROL_REGISTER = 32'hF8F00000;
+parameter val_mpcore__SCU_CONTROL_REGISTER = 32'h00000002;
+parameter mask_mpcore__SCU_CONTROL_REGISTER = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_CONFIGURATION_REGISTER = 32'hF8F00004;
+parameter val_mpcore__SCU_CONFIGURATION_REGISTER = 32'h00000501;
+parameter mask_mpcore__SCU_CONFIGURATION_REGISTER = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_CPU_Power_Status_Register = 32'hF8F00008;
+parameter val_mpcore__SCU_CPU_Power_Status_Register = 32'h00000000;
+parameter mask_mpcore__SCU_CPU_Power_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hF8F0000C;
+parameter val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'h00000000;
+parameter mask_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hFFFFFFFF;
+
+parameter mpcore__Filtering_Start_Address_Register = 32'hF8F00040;
+parameter val_mpcore__Filtering_Start_Address_Register = 32'h00100000;
+parameter mask_mpcore__Filtering_Start_Address_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Filtering_End_Address_Register = 32'hF8F00044;
+parameter val_mpcore__Filtering_End_Address_Register = 32'h00000000;
+parameter mask_mpcore__Filtering_End_Address_Register = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_Access_Control_Register_SAC = 32'hF8F00050;
+parameter val_mpcore__SCU_Access_Control_Register_SAC = 32'h0000000F;
+parameter mask_mpcore__SCU_Access_Control_Register_SAC = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_Non_secure_Access_Control_Register = 32'hF8F00054;
+parameter val_mpcore__SCU_Non_secure_Access_Control_Register = 32'h00000000;
+parameter mask_mpcore__SCU_Non_secure_Access_Control_Register = 32'hFFFFFFFF;
+
+parameter mpcore__ICCICR = 32'hF8F00100;
+parameter val_mpcore__ICCICR = 32'h00000000;
+parameter mask_mpcore__ICCICR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCPMR = 32'hF8F00104;
+parameter val_mpcore__ICCPMR = 32'h00000000;
+parameter mask_mpcore__ICCPMR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCBPR = 32'hF8F00108;
+parameter val_mpcore__ICCBPR = 32'h00000002;
+parameter mask_mpcore__ICCBPR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIAR = 32'hF8F0010C;
+parameter val_mpcore__ICCIAR = 32'h000003FF;
+parameter mask_mpcore__ICCIAR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCEOIR = 32'hF8F00110;
+parameter val_mpcore__ICCEOIR = 32'h00000000;
+parameter mask_mpcore__ICCEOIR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCRPR = 32'hF8F00114;
+parameter val_mpcore__ICCRPR = 32'h000000FF;
+parameter mask_mpcore__ICCRPR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCHPIR = 32'hF8F00118;
+parameter val_mpcore__ICCHPIR = 32'h000003FF;
+parameter mask_mpcore__ICCHPIR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCABPR = 32'hF8F0011C;
+parameter val_mpcore__ICCABPR = 32'h00000003;
+parameter mask_mpcore__ICCABPR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR = 32'hF8F001FC;
+parameter val_mpcore__ICCIDR = 32'h3901243B;
+parameter mask_mpcore__ICCIDR = 32'hFFFFFFFF;
+
+parameter mpcore__Global_Timer_Counter_Register0 = 32'hF8F00200;
+parameter val_mpcore__Global_Timer_Counter_Register0 = 32'h00000000;
+parameter mask_mpcore__Global_Timer_Counter_Register0 = 32'hFFFFFFFF;
+
+parameter mpcore__Global_Timer_Counter_Register1 = 32'hF8F00204;
+parameter val_mpcore__Global_Timer_Counter_Register1 = 32'h00000000;
+parameter mask_mpcore__Global_Timer_Counter_Register1 = 32'hFFFFFFFF;
+
+parameter mpcore__Global_Timer_Control_Register = 32'hF8F00208;
+parameter val_mpcore__Global_Timer_Control_Register = 32'h00000000;
+parameter mask_mpcore__Global_Timer_Control_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Global_Timer_Interrupt_Status_Register = 32'hF8F0020C;
+parameter val_mpcore__Global_Timer_Interrupt_Status_Register = 32'h00000000;
+parameter mask_mpcore__Global_Timer_Interrupt_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Comparator_Value_Register0 = 32'hF8F00210;
+parameter val_mpcore__Comparator_Value_Register0 = 32'h00000000;
+parameter mask_mpcore__Comparator_Value_Register0 = 32'hFFFFFFFF;
+
+parameter mpcore__Comparator_Value_Register1 = 32'hF8F00214;
+parameter val_mpcore__Comparator_Value_Register1 = 32'h00000000;
+parameter mask_mpcore__Comparator_Value_Register1 = 32'hFFFFFFFF;
+
+parameter mpcore__Auto_increment_Register = 32'hF8F00218;
+parameter val_mpcore__Auto_increment_Register = 32'h00000000;
+parameter mask_mpcore__Auto_increment_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Private_Timer_Load_Register = 32'hF8F00600;
+parameter val_mpcore__Private_Timer_Load_Register = 32'h00000000;
+parameter mask_mpcore__Private_Timer_Load_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Private_Timer_Counter_Register = 32'hF8F00604;
+parameter val_mpcore__Private_Timer_Counter_Register = 32'h00000000;
+parameter mask_mpcore__Private_Timer_Counter_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Private_Timer_Control_Register = 32'hF8F00608;
+parameter val_mpcore__Private_Timer_Control_Register = 32'h00000000;
+parameter mask_mpcore__Private_Timer_Control_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Private_Timer_Interrupt_Status_Register = 32'hF8F0060C;
+parameter val_mpcore__Private_Timer_Interrupt_Status_Register = 32'h00000000;
+parameter mask_mpcore__Private_Timer_Interrupt_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Load_Register = 32'hF8F00620;
+parameter val_mpcore__Watchdog_Load_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Load_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Counter_Register = 32'hF8F00624;
+parameter val_mpcore__Watchdog_Counter_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Counter_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Control_Register = 32'hF8F00628;
+parameter val_mpcore__Watchdog_Control_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Control_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Interrupt_Status_Register = 32'hF8F0062C;
+parameter val_mpcore__Watchdog_Interrupt_Status_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Interrupt_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Reset_Status_Register = 32'hF8F00630;
+parameter val_mpcore__Watchdog_Reset_Status_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Reset_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Disable_Register = 32'hF8F00634;
+parameter val_mpcore__Watchdog_Disable_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Disable_Register = 32'hFFFFFFFF;
+
+parameter mpcore__ICDDCR = 32'hF8F01000;
+parameter val_mpcore__ICDDCR = 32'h00000000;
+parameter mask_mpcore__ICDDCR = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICTR = 32'hF8F01004;
+parameter val_mpcore__ICDICTR = 32'h00000C22;
+parameter mask_mpcore__ICDICTR = 32'hE000FFFF;
+
+parameter mpcore__ICDIIDR = 32'hF8F01008;
+parameter val_mpcore__ICDIIDR = 32'h0102043B;
+parameter mask_mpcore__ICDIIDR = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISR0 = 32'hF8F01080;
+parameter val_mpcore__ICDISR0 = 32'h00000000;
+parameter mask_mpcore__ICDISR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISR1 = 32'hF8F01084;
+parameter val_mpcore__ICDISR1 = 32'h00000000;
+parameter mask_mpcore__ICDISR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISR2 = 32'hF8F01088;
+parameter val_mpcore__ICDISR2 = 32'h00000000;
+parameter mask_mpcore__ICDISR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISER0 = 32'hF8F01100;
+parameter val_mpcore__ICDISER0 = 32'h0000FFFF;
+parameter mask_mpcore__ICDISER0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISER1 = 32'hF8F01104;
+parameter val_mpcore__ICDISER1 = 32'h00000000;
+parameter mask_mpcore__ICDISER1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISER2 = 32'hF8F01108;
+parameter val_mpcore__ICDISER2 = 32'h00000000;
+parameter mask_mpcore__ICDISER2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICER0 = 32'hF8F01180;
+parameter val_mpcore__ICDICER0 = 32'h0000FFFF;
+parameter mask_mpcore__ICDICER0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICER1 = 32'hF8F01184;
+parameter val_mpcore__ICDICER1 = 32'h00000000;
+parameter mask_mpcore__ICDICER1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICER2 = 32'hF8F01188;
+parameter val_mpcore__ICDICER2 = 32'h00000000;
+parameter mask_mpcore__ICDICER2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISPR0 = 32'hF8F01200;
+parameter val_mpcore__ICDISPR0 = 32'h00000000;
+parameter mask_mpcore__ICDISPR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISPR1 = 32'hF8F01204;
+parameter val_mpcore__ICDISPR1 = 32'h00000000;
+parameter mask_mpcore__ICDISPR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISPR2 = 32'hF8F01208;
+parameter val_mpcore__ICDISPR2 = 32'h00000000;
+parameter mask_mpcore__ICDISPR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICPR0 = 32'hF8F01280;
+parameter val_mpcore__ICDICPR0 = 32'h00000000;
+parameter mask_mpcore__ICDICPR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICPR1 = 32'hF8F01284;
+parameter val_mpcore__ICDICPR1 = 32'h00000000;
+parameter mask_mpcore__ICDICPR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICPR2 = 32'hF8F01288;
+parameter val_mpcore__ICDICPR2 = 32'h00000000;
+parameter mask_mpcore__ICDICPR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDABR0 = 32'hF8F01300;
+parameter val_mpcore__ICDABR0 = 32'h00000000;
+parameter mask_mpcore__ICDABR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDABR1 = 32'hF8F01304;
+parameter val_mpcore__ICDABR1 = 32'h00000000;
+parameter mask_mpcore__ICDABR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDABR2 = 32'hF8F01308;
+parameter val_mpcore__ICDABR2 = 32'h00000000;
+parameter mask_mpcore__ICDABR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR0 = 32'hF8F01400;
+parameter val_mpcore__ICDIPR0 = 32'h00000000;
+parameter mask_mpcore__ICDIPR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR1 = 32'hF8F01404;
+parameter val_mpcore__ICDIPR1 = 32'h00000000;
+parameter mask_mpcore__ICDIPR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR2 = 32'hF8F01408;
+parameter val_mpcore__ICDIPR2 = 32'h00000000;
+parameter mask_mpcore__ICDIPR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR3 = 32'hF8F0140C;
+parameter val_mpcore__ICDIPR3 = 32'h00000000;
+parameter mask_mpcore__ICDIPR3 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR4 = 32'hF8F01410;
+parameter val_mpcore__ICDIPR4 = 32'h00000000;
+parameter mask_mpcore__ICDIPR4 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR5 = 32'hF8F01414;
+parameter val_mpcore__ICDIPR5 = 32'h00000000;
+parameter mask_mpcore__ICDIPR5 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR6 = 32'hF8F01418;
+parameter val_mpcore__ICDIPR6 = 32'h00000000;
+parameter mask_mpcore__ICDIPR6 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR7 = 32'hF8F0141C;
+parameter val_mpcore__ICDIPR7 = 32'h00000000;
+parameter mask_mpcore__ICDIPR7 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR8 = 32'hF8F01420;
+parameter val_mpcore__ICDIPR8 = 32'h00000000;
+parameter mask_mpcore__ICDIPR8 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR9 = 32'hF8F01424;
+parameter val_mpcore__ICDIPR9 = 32'h00000000;
+parameter mask_mpcore__ICDIPR9 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR10 = 32'hF8F01428;
+parameter val_mpcore__ICDIPR10 = 32'h00000000;
+parameter mask_mpcore__ICDIPR10 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR11 = 32'hF8F0142C;
+parameter val_mpcore__ICDIPR11 = 32'h00000000;
+parameter mask_mpcore__ICDIPR11 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR12 = 32'hF8F01430;
+parameter val_mpcore__ICDIPR12 = 32'h00000000;
+parameter mask_mpcore__ICDIPR12 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR13 = 32'hF8F01434;
+parameter val_mpcore__ICDIPR13 = 32'h00000000;
+parameter mask_mpcore__ICDIPR13 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR14 = 32'hF8F01438;
+parameter val_mpcore__ICDIPR14 = 32'h00000000;
+parameter mask_mpcore__ICDIPR14 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR15 = 32'hF8F0143C;
+parameter val_mpcore__ICDIPR15 = 32'h00000000;
+parameter mask_mpcore__ICDIPR15 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR16 = 32'hF8F01440;
+parameter val_mpcore__ICDIPR16 = 32'h00000000;
+parameter mask_mpcore__ICDIPR16 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR17 = 32'hF8F01444;
+parameter val_mpcore__ICDIPR17 = 32'h00000000;
+parameter mask_mpcore__ICDIPR17 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR18 = 32'hF8F01448;
+parameter val_mpcore__ICDIPR18 = 32'h00000000;
+parameter mask_mpcore__ICDIPR18 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR19 = 32'hF8F0144C;
+parameter val_mpcore__ICDIPR19 = 32'h00000000;
+parameter mask_mpcore__ICDIPR19 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR20 = 32'hF8F01450;
+parameter val_mpcore__ICDIPR20 = 32'h00000000;
+parameter mask_mpcore__ICDIPR20 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR21 = 32'hF8F01454;
+parameter val_mpcore__ICDIPR21 = 32'h00000000;
+parameter mask_mpcore__ICDIPR21 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR22 = 32'hF8F01458;
+parameter val_mpcore__ICDIPR22 = 32'h00000000;
+parameter mask_mpcore__ICDIPR22 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR23 = 32'hF8F0145C;
+parameter val_mpcore__ICDIPR23 = 32'h00000000;
+parameter mask_mpcore__ICDIPR23 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR0 = 32'hF8F01800;
+parameter val_mpcore__ICDIPTR0 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR1 = 32'hF8F01804;
+parameter val_mpcore__ICDIPTR1 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR2 = 32'hF8F01808;
+parameter val_mpcore__ICDIPTR2 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR3 = 32'hF8F0180C;
+parameter val_mpcore__ICDIPTR3 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR3 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR4 = 32'hF8F01810;
+parameter val_mpcore__ICDIPTR4 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR4 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR5 = 32'hF8F01814;
+parameter val_mpcore__ICDIPTR5 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR5 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR6 = 32'hF8F01818;
+parameter val_mpcore__ICDIPTR6 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR6 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR7 = 32'hF8F0181C;
+parameter val_mpcore__ICDIPTR7 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR7 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR8 = 32'hF8F01820;
+parameter val_mpcore__ICDIPTR8 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR8 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR9 = 32'hF8F01824;
+parameter val_mpcore__ICDIPTR9 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR9 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR10 = 32'hF8F01828;
+parameter val_mpcore__ICDIPTR10 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR10 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR11 = 32'hF8F0182C;
+parameter val_mpcore__ICDIPTR11 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR11 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR12 = 32'hF8F01830;
+parameter val_mpcore__ICDIPTR12 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR12 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR13 = 32'hF8F01834;
+parameter val_mpcore__ICDIPTR13 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR13 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR14 = 32'hF8F01838;
+parameter val_mpcore__ICDIPTR14 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR14 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR15 = 32'hF8F0183C;
+parameter val_mpcore__ICDIPTR15 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR15 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR16 = 32'hF8F01840;
+parameter val_mpcore__ICDIPTR16 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR16 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR17 = 32'hF8F01844;
+parameter val_mpcore__ICDIPTR17 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR17 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR18 = 32'hF8F01848;
+parameter val_mpcore__ICDIPTR18 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR18 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR19 = 32'hF8F0184C;
+parameter val_mpcore__ICDIPTR19 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR19 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR20 = 32'hF8F01850;
+parameter val_mpcore__ICDIPTR20 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR20 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR21 = 32'hF8F01854;
+parameter val_mpcore__ICDIPTR21 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR21 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR22 = 32'hF8F01858;
+parameter val_mpcore__ICDIPTR22 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR22 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR23 = 32'hF8F0185C;
+parameter val_mpcore__ICDIPTR23 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR23 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR0 = 32'hF8F01C00;
+parameter val_mpcore__ICDICFR0 = 32'hAAAAAAAA;
+parameter mask_mpcore__ICDICFR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR1 = 32'hF8F01C04;
+parameter val_mpcore__ICDICFR1 = 32'h7DC00000;
+parameter mask_mpcore__ICDICFR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR2 = 32'hF8F01C08;
+parameter val_mpcore__ICDICFR2 = 32'h55555555;
+parameter mask_mpcore__ICDICFR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR3 = 32'hF8F01C0C;
+parameter val_mpcore__ICDICFR3 = 32'h55555555;
+parameter mask_mpcore__ICDICFR3 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR4 = 32'hF8F01C10;
+parameter val_mpcore__ICDICFR4 = 32'h55555555;
+parameter mask_mpcore__ICDICFR4 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR5 = 32'hF8F01C14;
+parameter val_mpcore__ICDICFR5 = 32'h55555555;
+parameter mask_mpcore__ICDICFR5 = 32'hFFFFFFFF;
+
+parameter mpcore__ppi_status = 32'hF8F01D00;
+parameter val_mpcore__ppi_status = 32'h00000000;
+parameter mask_mpcore__ppi_status = 32'hFFFFFFFF;
+
+parameter mpcore__spi_status_0 = 32'hF8F01D04;
+parameter val_mpcore__spi_status_0 = 32'h00000000;
+parameter mask_mpcore__spi_status_0 = 32'hFFFFFFFF;
+
+parameter mpcore__spi_status_1 = 32'hF8F01D08;
+parameter val_mpcore__spi_status_1 = 32'h00000000;
+parameter mask_mpcore__spi_status_1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDSGIR = 32'hF8F01F00;
+parameter val_mpcore__ICDSGIR = 32'h00000000;
+parameter mask_mpcore__ICDSGIR = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR4 = 32'hF8F01FD0;
+parameter val_mpcore__ICPIDR4 = 32'h00000004;
+parameter mask_mpcore__ICPIDR4 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR5 = 32'hF8F01FD4;
+parameter val_mpcore__ICPIDR5 = 32'h00000000;
+parameter mask_mpcore__ICPIDR5 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR6 = 32'hF8F01FD8;
+parameter val_mpcore__ICPIDR6 = 32'h00000000;
+parameter mask_mpcore__ICPIDR6 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR7 = 32'hF8F01FDC;
+parameter val_mpcore__ICPIDR7 = 32'h00000000;
+parameter mask_mpcore__ICPIDR7 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR0 = 32'hF8F01FE0;
+parameter val_mpcore__ICPIDR0 = 32'h00000090;
+parameter mask_mpcore__ICPIDR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR1 = 32'hF8F01FE4;
+parameter val_mpcore__ICPIDR1 = 32'h000000B3;
+parameter mask_mpcore__ICPIDR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR2 = 32'hF8F01FE8;
+parameter val_mpcore__ICPIDR2 = 32'h0000001B;
+parameter mask_mpcore__ICPIDR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR3 = 32'hF8F01FEC;
+parameter val_mpcore__ICPIDR3 = 32'h00000000;
+parameter mask_mpcore__ICPIDR3 = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR0 = 32'hF8F01FF0;
+parameter val_mpcore__ICCIDR0 = 32'h0000000D;
+parameter mask_mpcore__ICCIDR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR1 = 32'hF8F01FF4;
+parameter val_mpcore__ICCIDR1 = 32'h000000F0;
+parameter mask_mpcore__ICCIDR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR2 = 32'hF8F01FF8;
+parameter val_mpcore__ICCIDR2 = 32'h00000005;
+parameter mask_mpcore__ICCIDR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR3 = 32'hF8F01FFC;
+parameter val_mpcore__ICCIDR3 = 32'h000000B1;
+parameter mask_mpcore__ICCIDR3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module ocm ocm
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter ocm__OCM_PARITY_CTRL = 32'hF800C000;
+parameter val_ocm__OCM_PARITY_CTRL = 32'h00000000;
+parameter mask_ocm__OCM_PARITY_CTRL = 32'hFFFFFFFF;
+
+parameter ocm__OCM_PARITY_ERRADDRESS = 32'hF800C004;
+parameter val_ocm__OCM_PARITY_ERRADDRESS = 32'h00000000;
+parameter mask_ocm__OCM_PARITY_ERRADDRESS = 32'hFFFFFFFF;
+
+parameter ocm__OCM_IRQ_STS = 32'hF800C008;
+parameter val_ocm__OCM_IRQ_STS = 32'h00000000;
+parameter mask_ocm__OCM_IRQ_STS = 32'hFFFFFFFF;
+
+parameter ocm__OCM_CONTROL = 32'hF800C00C;
+parameter val_ocm__OCM_CONTROL = 32'h00000000;
+parameter mask_ocm__OCM_CONTROL = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module qspi qspi
+//   doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller
+//   Design Specification document
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter qspi__Config_reg = 32'hE000D000;
+parameter val_qspi__Config_reg = 32'h80000000;
+parameter mask_qspi__Config_reg = 32'hFFFDFFFF;
+
+parameter qspi__Intr_status_REG = 32'hE000D004;
+parameter val_qspi__Intr_status_REG = 32'h00000004;
+parameter mask_qspi__Intr_status_REG = 32'hFFFFFFFF;
+
+parameter qspi__Intrpt_en_REG = 32'hE000D008;
+parameter val_qspi__Intrpt_en_REG = 32'h00000000;
+parameter mask_qspi__Intrpt_en_REG = 32'hFFFFFFFF;
+
+parameter qspi__Intrpt_dis_REG = 32'hE000D00C;
+parameter val_qspi__Intrpt_dis_REG = 32'h00000000;
+parameter mask_qspi__Intrpt_dis_REG = 32'hFFFFFFFF;
+
+parameter qspi__Intrpt_mask_REG = 32'hE000D010;
+parameter val_qspi__Intrpt_mask_REG = 32'h00000000;
+parameter mask_qspi__Intrpt_mask_REG = 32'hFFFFFFFF;
+
+parameter qspi__En_REG = 32'hE000D014;
+parameter val_qspi__En_REG = 32'h00000000;
+parameter mask_qspi__En_REG = 32'hFFFFFFFF;
+
+parameter qspi__Delay_REG = 32'hE000D018;
+parameter val_qspi__Delay_REG = 32'h00000000;
+parameter mask_qspi__Delay_REG = 32'hFFFFFFFF;
+
+parameter qspi__TXD0 = 32'hE000D01C;
+parameter val_qspi__TXD0 = 32'h00000000;
+parameter mask_qspi__TXD0 = 32'hFFFFFFFF;
+
+parameter qspi__Rx_data_REG = 32'hE000D020;
+parameter val_qspi__Rx_data_REG = 32'h00000000;
+parameter mask_qspi__Rx_data_REG = 32'hFFFFFFFF;
+
+parameter qspi__Slave_Idle_count_REG = 32'hE000D024;
+parameter val_qspi__Slave_Idle_count_REG = 32'h000000FF;
+parameter mask_qspi__Slave_Idle_count_REG = 32'hFFFFFFFF;
+
+parameter qspi__TX_thres_REG = 32'hE000D028;
+parameter val_qspi__TX_thres_REG = 32'h00000001;
+parameter mask_qspi__TX_thres_REG = 32'hFFFFFFFF;
+
+parameter qspi__RX_thres_REG = 32'hE000D02C;
+parameter val_qspi__RX_thres_REG = 32'h00000001;
+parameter mask_qspi__RX_thres_REG = 32'hFFFFFFFF;
+
+parameter qspi__GPIO = 32'hE000D030;
+parameter val_qspi__GPIO = 32'h00000001;
+parameter mask_qspi__GPIO = 32'hFFFFFFFF;
+
+parameter qspi__LPBK_DLY_ADJ = 32'hE000D038;
+parameter val_qspi__LPBK_DLY_ADJ = 32'h00000033;
+parameter mask_qspi__LPBK_DLY_ADJ = 32'hFFFFFFFF;
+
+parameter qspi__TXD1 = 32'hE000D080;
+parameter val_qspi__TXD1 = 32'h00000000;
+parameter mask_qspi__TXD1 = 32'hFFFFFFFF;
+
+parameter qspi__TXD2 = 32'hE000D084;
+parameter val_qspi__TXD2 = 32'h00000000;
+parameter mask_qspi__TXD2 = 32'hFFFFFFFF;
+
+parameter qspi__TXD3 = 32'hE000D088;
+parameter val_qspi__TXD3 = 32'h00000000;
+parameter mask_qspi__TXD3 = 32'hFFFFFFFF;
+
+parameter qspi__LQSPI_CFG = 32'hE000D0A0;
+parameter val_qspi__LQSPI_CFG = 32'h03A002EB;
+parameter mask_qspi__LQSPI_CFG = 32'hFBFF07FF;
+
+parameter qspi__LQSPI_STS = 32'hE000D0A4;
+parameter val_qspi__LQSPI_STS = 32'h00000000;
+parameter mask_qspi__LQSPI_STS = 32'h000001FF;
+
+parameter qspi__MOD_ID = 32'hE000D0FC;
+parameter val_qspi__MOD_ID = 32'h01090101;
+parameter mask_qspi__MOD_ID = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module sd0 sdio
+//   doc version: 4.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter sd0__SDMA_system_address_register = 32'hE0100000;
+parameter val_sd0__SDMA_system_address_register = 32'h00000000;
+parameter mask_sd0__SDMA_system_address_register = 32'hFFFFFFFF;
+
+parameter sd0__Block_Size_Block_Count = 32'hE0100004;
+parameter val_sd0__Block_Size_Block_Count = 32'h00000000;
+parameter mask_sd0__Block_Size_Block_Count = 32'hFFFFFFFF;
+
+parameter sd0__Argument = 32'hE0100008;
+parameter val_sd0__Argument = 32'h00000000;
+parameter mask_sd0__Argument = 32'hFFFFFFFF;
+
+parameter sd0__Transfer_Mode_Command = 32'hE010000C;
+parameter val_sd0__Transfer_Mode_Command = 32'h00000000;
+parameter mask_sd0__Transfer_Mode_Command = 32'h1FFFFFFF;
+
+parameter sd0__Response0 = 32'hE0100010;
+parameter val_sd0__Response0 = 32'h00000000;
+parameter mask_sd0__Response0 = 32'hFFFFFFFF;
+
+parameter sd0__Response1 = 32'hE0100014;
+parameter val_sd0__Response1 = 32'h00000000;
+parameter mask_sd0__Response1 = 32'hFFFFFFFF;
+
+parameter sd0__Response2 = 32'hE0100018;
+parameter val_sd0__Response2 = 32'h00000000;
+parameter mask_sd0__Response2 = 32'hFFFFFFFF;
+
+parameter sd0__Response3 = 32'hE010001C;
+parameter val_sd0__Response3 = 32'h00000000;
+parameter mask_sd0__Response3 = 32'hFFFFFFFF;
+
+parameter sd0__Buffer_Data_Port = 32'hE0100020;
+parameter val_sd0__Buffer_Data_Port = 32'h00000000;
+parameter mask_sd0__Buffer_Data_Port = 32'hFFFFFFFF;
+
+parameter sd0__Present_State = 32'hE0100024;
+parameter val_sd0__Present_State = 32'h01F20000;
+parameter mask_sd0__Present_State = 32'h01FFFFFF;
+
+parameter sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0100028;
+parameter val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000;
+parameter mask_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF;
+
+parameter sd0__Clock_Control_Timeout_control_Software_reset = 32'hE010002C;
+parameter val_sd0__Clock_Control_Timeout_control_Software_reset = 32'h00000000;
+parameter mask_sd0__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF;
+
+parameter sd0__Normal_interrupt_status_Error_interrupt_status = 32'hE0100030;
+parameter val_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h00000000;
+parameter mask_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF;
+
+parameter sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0100034;
+parameter val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000;
+parameter mask_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF;
+
+parameter sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0100038;
+parameter val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000;
+parameter mask_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF;
+
+parameter sd0__Auto_CMD12_error_status = 32'hE010003C;
+parameter val_sd0__Auto_CMD12_error_status = 32'h00000000;
+parameter mask_sd0__Auto_CMD12_error_status = 32'h000000FF;
+
+parameter sd0__Capabilities = 32'hE0100040;
+parameter val_sd0__Capabilities = 32'h69EC0080;
+parameter mask_sd0__Capabilities = 32'h7FFFFFFF;
+
+parameter sd0__Maximum_current_capabilities = 32'hE0100048;
+parameter val_sd0__Maximum_current_capabilities = 32'h00000001;
+parameter mask_sd0__Maximum_current_capabilities = 32'h00FFFFFF;
+
+parameter sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0100050;
+parameter val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000;
+parameter mask_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF;
+
+parameter sd0__ADMA_error_status = 32'hE0100054;
+parameter val_sd0__ADMA_error_status = 32'h00000000;
+parameter mask_sd0__ADMA_error_status = 32'h00000007;
+
+parameter sd0__ADMA_system_address = 32'hE0100058;
+parameter val_sd0__ADMA_system_address = 32'h00000000;
+parameter mask_sd0__ADMA_system_address = 32'hFFFFFFFF;
+
+parameter sd0__Boot_Timeout_control = 32'hE0100060;
+parameter val_sd0__Boot_Timeout_control = 32'h00000000;
+parameter mask_sd0__Boot_Timeout_control = 32'hFFFFFFFF;
+
+parameter sd0__Debug_Selection = 32'hE0100064;
+parameter val_sd0__Debug_Selection = 32'h00000000;
+parameter mask_sd0__Debug_Selection = 32'h00000001;
+
+parameter sd0__SPI_interrupt_support = 32'hE01000F0;
+parameter val_sd0__SPI_interrupt_support = 32'h00000000;
+parameter mask_sd0__SPI_interrupt_support = 32'h000000FF;
+
+parameter sd0__Slot_interrupt_status_Host_controller_version = 32'hE01000FC;
+parameter val_sd0__Slot_interrupt_status_Host_controller_version = 32'h89010000;
+parameter mask_sd0__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module sd1 sdio
+//   doc version: 4.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter sd1__SDMA_system_address_register = 32'hE0101000;
+parameter val_sd1__SDMA_system_address_register = 32'h00000000;
+parameter mask_sd1__SDMA_system_address_register = 32'hFFFFFFFF;
+
+parameter sd1__Block_Size_Block_Count = 32'hE0101004;
+parameter val_sd1__Block_Size_Block_Count = 32'h00000000;
+parameter mask_sd1__Block_Size_Block_Count = 32'hFFFFFFFF;
+
+parameter sd1__Argument = 32'hE0101008;
+parameter val_sd1__Argument = 32'h00000000;
+parameter mask_sd1__Argument = 32'hFFFFFFFF;
+
+parameter sd1__Transfer_Mode_Command = 32'hE010100C;
+parameter val_sd1__Transfer_Mode_Command = 32'h00000000;
+parameter mask_sd1__Transfer_Mode_Command = 32'h1FFFFFFF;
+
+parameter sd1__Response0 = 32'hE0101010;
+parameter val_sd1__Response0 = 32'h00000000;
+parameter mask_sd1__Response0 = 32'hFFFFFFFF;
+
+parameter sd1__Response1 = 32'hE0101014;
+parameter val_sd1__Response1 = 32'h00000000;
+parameter mask_sd1__Response1 = 32'hFFFFFFFF;
+
+parameter sd1__Response2 = 32'hE0101018;
+parameter val_sd1__Response2 = 32'h00000000;
+parameter mask_sd1__Response2 = 32'hFFFFFFFF;
+
+parameter sd1__Response3 = 32'hE010101C;
+parameter val_sd1__Response3 = 32'h00000000;
+parameter mask_sd1__Response3 = 32'hFFFFFFFF;
+
+parameter sd1__Buffer_Data_Port = 32'hE0101020;
+parameter val_sd1__Buffer_Data_Port = 32'h00000000;
+parameter mask_sd1__Buffer_Data_Port = 32'hFFFFFFFF;
+
+parameter sd1__Present_State = 32'hE0101024;
+parameter val_sd1__Present_State = 32'h01F20000;
+parameter mask_sd1__Present_State = 32'h01FFFFFF;
+
+parameter sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0101028;
+parameter val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000;
+parameter mask_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF;
+
+parameter sd1__Clock_Control_Timeout_control_Software_reset = 32'hE010102C;
+parameter val_sd1__Clock_Control_Timeout_control_Software_reset = 32'h00000000;
+parameter mask_sd1__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF;
+
+parameter sd1__Normal_interrupt_status_Error_interrupt_status = 32'hE0101030;
+parameter val_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h00000000;
+parameter mask_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF;
+
+parameter sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0101034;
+parameter val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000;
+parameter mask_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF;
+
+parameter sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0101038;
+parameter val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000;
+parameter mask_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF;
+
+parameter sd1__Auto_CMD12_error_status = 32'hE010103C;
+parameter val_sd1__Auto_CMD12_error_status = 32'h00000000;
+parameter mask_sd1__Auto_CMD12_error_status = 32'h000000FF;
+
+parameter sd1__Capabilities = 32'hE0101040;
+parameter val_sd1__Capabilities = 32'h69EC0080;
+parameter mask_sd1__Capabilities = 32'h7FFFFFFF;
+
+parameter sd1__Maximum_current_capabilities = 32'hE0101048;
+parameter val_sd1__Maximum_current_capabilities = 32'h00000001;
+parameter mask_sd1__Maximum_current_capabilities = 32'h00FFFFFF;
+
+parameter sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0101050;
+parameter val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000;
+parameter mask_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF;
+
+parameter sd1__ADMA_error_status = 32'hE0101054;
+parameter val_sd1__ADMA_error_status = 32'h00000000;
+parameter mask_sd1__ADMA_error_status = 32'h00000007;
+
+parameter sd1__ADMA_system_address = 32'hE0101058;
+parameter val_sd1__ADMA_system_address = 32'h00000000;
+parameter mask_sd1__ADMA_system_address = 32'hFFFFFFFF;
+
+parameter sd1__Boot_Timeout_control = 32'hE0101060;
+parameter val_sd1__Boot_Timeout_control = 32'h00000000;
+parameter mask_sd1__Boot_Timeout_control = 32'hFFFFFFFF;
+
+parameter sd1__Debug_Selection = 32'hE0101064;
+parameter val_sd1__Debug_Selection = 32'h00000000;
+parameter mask_sd1__Debug_Selection = 32'h00000001;
+
+parameter sd1__SPI_interrupt_support = 32'hE01010F0;
+parameter val_sd1__SPI_interrupt_support = 32'h00000000;
+parameter mask_sd1__SPI_interrupt_support = 32'h000000FF;
+
+parameter sd1__Slot_interrupt_status_Host_controller_version = 32'hE01010FC;
+parameter val_sd1__Slot_interrupt_status_Host_controller_version = 32'h89010000;
+parameter mask_sd1__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module slcr slcr
+//   doc version: 1.3, based on 11/18/2010 SLCR_spec.doc
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter slcr__SCL = 32'hF8000000;
+parameter val_slcr__SCL = 32'h00000000;
+parameter mask_slcr__SCL = 32'hFFFFFFFF;
+
+parameter slcr__SLCR_LOCK = 32'hF8000004;
+parameter val_slcr__SLCR_LOCK = 32'h00000000;
+parameter mask_slcr__SLCR_LOCK = 32'hFFFFFFFF;
+
+parameter slcr__SLCR_UNLOCK = 32'hF8000008;
+parameter val_slcr__SLCR_UNLOCK = 32'h00000000;
+parameter mask_slcr__SLCR_UNLOCK = 32'hFFFFFFFF;
+
+parameter slcr__SLCR_LOCKSTA = 32'hF800000C;
+parameter val_slcr__SLCR_LOCKSTA = 32'h00000001;
+parameter mask_slcr__SLCR_LOCKSTA = 32'hFFFFFFFF;
+
+parameter slcr__ARM_PLL_CTRL = 32'hF8000100;
+parameter val_slcr__ARM_PLL_CTRL = 32'h0001A008;
+parameter mask_slcr__ARM_PLL_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDR_PLL_CTRL = 32'hF8000104;
+parameter val_slcr__DDR_PLL_CTRL = 32'h0001A008;
+parameter mask_slcr__DDR_PLL_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__IO_PLL_CTRL = 32'hF8000108;
+parameter val_slcr__IO_PLL_CTRL = 32'h0001A008;
+parameter mask_slcr__IO_PLL_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__PLL_STATUS = 32'hF800010C;
+parameter val_slcr__PLL_STATUS = 32'h0000003F;
+parameter mask_slcr__PLL_STATUS = 32'hFFFFFFFF;
+
+parameter slcr__ARM_PLL_CFG = 32'hF8000110;
+parameter val_slcr__ARM_PLL_CFG = 32'h00177EA0;
+parameter mask_slcr__ARM_PLL_CFG = 32'hFFFFFFFF;
+
+parameter slcr__DDR_PLL_CFG = 32'hF8000114;
+parameter val_slcr__DDR_PLL_CFG = 32'h00177EA0;
+parameter mask_slcr__DDR_PLL_CFG = 32'hFFFFFFFF;
+
+parameter slcr__IO_PLL_CFG = 32'hF8000118;
+parameter val_slcr__IO_PLL_CFG = 32'h00177EA0;
+parameter mask_slcr__IO_PLL_CFG = 32'hFFFFFFFF;
+
+parameter slcr__PLL_BG_CTRL = 32'hF800011C;
+parameter val_slcr__PLL_BG_CTRL = 32'h00000000;
+parameter mask_slcr__PLL_BG_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__ARM_CLK_CTRL = 32'hF8000120;
+parameter val_slcr__ARM_CLK_CTRL = 32'h1F000400;
+parameter mask_slcr__ARM_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDR_CLK_CTRL = 32'hF8000124;
+parameter val_slcr__DDR_CLK_CTRL = 32'h18400003;
+parameter mask_slcr__DDR_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DCI_CLK_CTRL = 32'hF8000128;
+parameter val_slcr__DCI_CLK_CTRL = 32'h01E03201;
+parameter mask_slcr__DCI_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__APER_CLK_CTRL = 32'hF800012C;
+parameter val_slcr__APER_CLK_CTRL = 32'h01FFCCCD;
+parameter mask_slcr__APER_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__USB0_CLK_CTRL = 32'hF8000130;
+parameter val_slcr__USB0_CLK_CTRL = 32'h00101941;
+parameter mask_slcr__USB0_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__USB1_CLK_CTRL = 32'hF8000134;
+parameter val_slcr__USB1_CLK_CTRL = 32'h00101941;
+parameter mask_slcr__USB1_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM0_RCLK_CTRL = 32'hF8000138;
+parameter val_slcr__GEM0_RCLK_CTRL = 32'h00000001;
+parameter mask_slcr__GEM0_RCLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM1_RCLK_CTRL = 32'hF800013C;
+parameter val_slcr__GEM1_RCLK_CTRL = 32'h00000001;
+parameter mask_slcr__GEM1_RCLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM0_CLK_CTRL = 32'hF8000140;
+parameter val_slcr__GEM0_CLK_CTRL = 32'h00003C01;
+parameter mask_slcr__GEM0_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM1_CLK_CTRL = 32'hF8000144;
+parameter val_slcr__GEM1_CLK_CTRL = 32'h00003C01;
+parameter mask_slcr__GEM1_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SMC_CLK_CTRL = 32'hF8000148;
+parameter val_slcr__SMC_CLK_CTRL = 32'h00003C21;
+parameter mask_slcr__SMC_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__LQSPI_CLK_CTRL = 32'hF800014C;
+parameter val_slcr__LQSPI_CLK_CTRL = 32'h00002821;
+parameter mask_slcr__LQSPI_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SDIO_CLK_CTRL = 32'hF8000150;
+parameter val_slcr__SDIO_CLK_CTRL = 32'h00001E03;
+parameter mask_slcr__SDIO_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__UART_CLK_CTRL = 32'hF8000154;
+parameter val_slcr__UART_CLK_CTRL = 32'h00003F03;
+parameter mask_slcr__UART_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SPI_CLK_CTRL = 32'hF8000158;
+parameter val_slcr__SPI_CLK_CTRL = 32'h00003F03;
+parameter mask_slcr__SPI_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__CAN_CLK_CTRL = 32'hF800015C;
+parameter val_slcr__CAN_CLK_CTRL = 32'h00501903;
+parameter mask_slcr__CAN_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__CAN_MIOCLK_CTRL = 32'hF8000160;
+parameter val_slcr__CAN_MIOCLK_CTRL = 32'h00000000;
+parameter mask_slcr__CAN_MIOCLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DBG_CLK_CTRL = 32'hF8000164;
+parameter val_slcr__DBG_CLK_CTRL = 32'h00000F03;
+parameter mask_slcr__DBG_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__PCAP_CLK_CTRL = 32'hF8000168;
+parameter val_slcr__PCAP_CLK_CTRL = 32'h00000F01;
+parameter mask_slcr__PCAP_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__TOPSW_CLK_CTRL = 32'hF800016C;
+parameter val_slcr__TOPSW_CLK_CTRL = 32'h00000000;
+parameter mask_slcr__TOPSW_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA0_CLK_CTRL = 32'hF8000170;
+parameter val_slcr__FPGA0_CLK_CTRL = 32'h00101800;
+parameter mask_slcr__FPGA0_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA0_THR_CTRL = 32'hF8000174;
+parameter val_slcr__FPGA0_THR_CTRL = 32'h00000000;
+parameter mask_slcr__FPGA0_THR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA0_THR_CNT = 32'hF8000178;
+parameter val_slcr__FPGA0_THR_CNT = 32'h00000000;
+parameter mask_slcr__FPGA0_THR_CNT = 32'hFFFFFFFF;
+
+parameter slcr__FPGA0_THR_STA = 32'hF800017C;
+parameter val_slcr__FPGA0_THR_STA = 32'h00010000;
+parameter mask_slcr__FPGA0_THR_STA = 32'hFFFFFFFF;
+
+parameter slcr__FPGA1_CLK_CTRL = 32'hF8000180;
+parameter val_slcr__FPGA1_CLK_CTRL = 32'h00101800;
+parameter mask_slcr__FPGA1_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA1_THR_CTRL = 32'hF8000184;
+parameter val_slcr__FPGA1_THR_CTRL = 32'h00000000;
+parameter mask_slcr__FPGA1_THR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA1_THR_CNT = 32'hF8000188;
+parameter val_slcr__FPGA1_THR_CNT = 32'h00000000;
+parameter mask_slcr__FPGA1_THR_CNT = 32'hFFFFFFFF;
+
+parameter slcr__FPGA1_THR_STA = 32'hF800018C;
+parameter val_slcr__FPGA1_THR_STA = 32'h00010000;
+parameter mask_slcr__FPGA1_THR_STA = 32'hFFFFFFFF;
+
+parameter slcr__FPGA2_CLK_CTRL = 32'hF8000190;
+parameter val_slcr__FPGA2_CLK_CTRL = 32'h00101800;
+parameter mask_slcr__FPGA2_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA2_THR_CTRL = 32'hF8000194;
+parameter val_slcr__FPGA2_THR_CTRL = 32'h00000000;
+parameter mask_slcr__FPGA2_THR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA2_THR_CNT = 32'hF8000198;
+parameter val_slcr__FPGA2_THR_CNT = 32'h00000000;
+parameter mask_slcr__FPGA2_THR_CNT = 32'hFFFFFFFF;
+
+parameter slcr__FPGA2_THR_STA = 32'hF800019C;
+parameter val_slcr__FPGA2_THR_STA = 32'h00010000;
+parameter mask_slcr__FPGA2_THR_STA = 32'hFFFFFFFF;
+
+parameter slcr__FPGA3_CLK_CTRL = 32'hF80001A0;
+parameter val_slcr__FPGA3_CLK_CTRL = 32'h00101800;
+parameter mask_slcr__FPGA3_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA3_THR_CTRL = 32'hF80001A4;
+parameter val_slcr__FPGA3_THR_CTRL = 32'h00000000;
+parameter mask_slcr__FPGA3_THR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA3_THR_CNT = 32'hF80001A8;
+parameter val_slcr__FPGA3_THR_CNT = 32'h00000000;
+parameter mask_slcr__FPGA3_THR_CNT = 32'hFFFFFFFF;
+
+parameter slcr__FPGA3_THR_STA = 32'hF80001AC;
+parameter val_slcr__FPGA3_THR_STA = 32'h00010000;
+parameter mask_slcr__FPGA3_THR_STA = 32'hFFFFFFFF;
+
+parameter slcr__SRST_UART_CTRL = 32'hF80001B0;
+parameter val_slcr__SRST_UART_CTRL = 32'h00000000;
+parameter mask_slcr__SRST_UART_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__BANDGAP_TRIM = 32'hF80001B8;
+parameter val_slcr__BANDGAP_TRIM = 32'h0000001F;
+parameter mask_slcr__BANDGAP_TRIM = 32'hFFFFFFFF;
+
+parameter slcr__CC_TEST = 32'hF80001BC;
+parameter val_slcr__CC_TEST = 32'h00000000;
+parameter mask_slcr__CC_TEST = 32'hFFFFFFFF;
+
+parameter slcr__PLL_PREDIVISOR = 32'hF80001C0;
+parameter val_slcr__PLL_PREDIVISOR = 32'h00000001;
+parameter mask_slcr__PLL_PREDIVISOR = 32'hFFFFFFFF;
+
+parameter slcr__CLK_621_TRUE = 32'hF80001C4;
+parameter val_slcr__CLK_621_TRUE = 32'h00000001;
+parameter mask_slcr__CLK_621_TRUE = 32'hFFFFFFC1;
+
+parameter slcr__PICTURE_DBG = 32'hF80001D0;
+parameter val_slcr__PICTURE_DBG = 32'h00000000;
+parameter mask_slcr__PICTURE_DBG = 32'hFFFFFFFF;
+
+parameter slcr__PICTURE_DBG_UCNT = 32'hF80001D4;
+parameter val_slcr__PICTURE_DBG_UCNT = 32'h00000000;
+parameter mask_slcr__PICTURE_DBG_UCNT = 32'hFFFFFFFF;
+
+parameter slcr__PICTURE_DBG_LCNT = 32'hF80001D8;
+parameter val_slcr__PICTURE_DBG_LCNT = 32'h00000000;
+parameter mask_slcr__PICTURE_DBG_LCNT = 32'hFFFFFFFF;
+
+parameter slcr__PSS_RST_CTRL = 32'hF8000200;
+parameter val_slcr__PSS_RST_CTRL = 32'h00000000;
+parameter mask_slcr__PSS_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDR_RST_CTRL = 32'hF8000204;
+parameter val_slcr__DDR_RST_CTRL = 32'h00000000;
+parameter mask_slcr__DDR_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__TOPSW_RST_CTRL = 32'hF8000208;
+parameter val_slcr__TOPSW_RST_CTRL = 32'h00000000;
+parameter mask_slcr__TOPSW_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DMAC_RST_CTRL = 32'hF800020C;
+parameter val_slcr__DMAC_RST_CTRL = 32'h00000000;
+parameter mask_slcr__DMAC_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__USB_RST_CTRL = 32'hF8000210;
+parameter val_slcr__USB_RST_CTRL = 32'h00000000;
+parameter mask_slcr__USB_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM_RST_CTRL = 32'hF8000214;
+parameter val_slcr__GEM_RST_CTRL = 32'h00000000;
+parameter mask_slcr__GEM_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SDIO_RST_CTRL = 32'hF8000218;
+parameter val_slcr__SDIO_RST_CTRL = 32'h00000000;
+parameter mask_slcr__SDIO_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SPI_RST_CTRL = 32'hF800021C;
+parameter val_slcr__SPI_RST_CTRL = 32'h00000000;
+parameter mask_slcr__SPI_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__CAN_RST_CTRL = 32'hF8000220;
+parameter val_slcr__CAN_RST_CTRL = 32'h00000000;
+parameter mask_slcr__CAN_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__I2C_RST_CTRL = 32'hF8000224;
+parameter val_slcr__I2C_RST_CTRL = 32'h00000000;
+parameter mask_slcr__I2C_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__UART_RST_CTRL = 32'hF8000228;
+parameter val_slcr__UART_RST_CTRL = 32'h00000000;
+parameter mask_slcr__UART_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GPIO_RST_CTRL = 32'hF800022C;
+parameter val_slcr__GPIO_RST_CTRL = 32'h00000000;
+parameter mask_slcr__GPIO_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__LQSPI_RST_CTRL = 32'hF8000230;
+parameter val_slcr__LQSPI_RST_CTRL = 32'h00000000;
+parameter mask_slcr__LQSPI_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SMC_RST_CTRL = 32'hF8000234;
+parameter val_slcr__SMC_RST_CTRL = 32'h00000000;
+parameter mask_slcr__SMC_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__OCM_RST_CTRL = 32'hF8000238;
+parameter val_slcr__OCM_RST_CTRL = 32'h00000000;
+parameter mask_slcr__OCM_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DEVCI_RST_CTRL = 32'hF800023C;
+parameter val_slcr__DEVCI_RST_CTRL = 32'h00000000;
+parameter mask_slcr__DEVCI_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA_RST_CTRL = 32'hF8000240;
+parameter val_slcr__FPGA_RST_CTRL = 32'h01F33F0F;
+parameter mask_slcr__FPGA_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__A9_CPU_RST_CTRL = 32'hF8000244;
+parameter val_slcr__A9_CPU_RST_CTRL = 32'h00000000;
+parameter mask_slcr__A9_CPU_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__RS_AWDT_CTRL = 32'hF800024C;
+parameter val_slcr__RS_AWDT_CTRL = 32'h00000000;
+parameter mask_slcr__RS_AWDT_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__RST_REASON = 32'hF8000250;
+parameter val_slcr__RST_REASON = 32'h00000040;
+parameter mask_slcr__RST_REASON = 32'hFFFFFFFF;
+
+parameter slcr__RST_REASON_CLR = 32'hF8000254;
+parameter val_slcr__RST_REASON_CLR = 32'h00000000;
+parameter mask_slcr__RST_REASON_CLR = 32'hFFFFFFFF;
+
+parameter slcr__REBOOT_STATUS = 32'hF8000258;
+parameter val_slcr__REBOOT_STATUS = 32'h00400000;
+parameter mask_slcr__REBOOT_STATUS = 32'hFFFFFFFF;
+
+parameter slcr__BOOT_MODE = 32'hF800025C;
+parameter val_slcr__BOOT_MODE = 32'h00000000;
+parameter mask_slcr__BOOT_MODE = 32'hFFFFFFF0;
+
+parameter slcr__APU_CTRL = 32'hF8000300;
+parameter val_slcr__APU_CTRL = 32'h00000000;
+parameter mask_slcr__APU_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__WDT_CLK_SEL = 32'hF8000304;
+parameter val_slcr__WDT_CLK_SEL = 32'h00000000;
+parameter mask_slcr__WDT_CLK_SEL = 32'hFFFFFFFF;
+
+parameter slcr__TZ_OCM_RAM0 = 32'hF8000400;
+parameter val_slcr__TZ_OCM_RAM0 = 32'h00000000;
+parameter mask_slcr__TZ_OCM_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__TZ_OCM_RAM1 = 32'hF8000404;
+parameter val_slcr__TZ_OCM_RAM1 = 32'h00000000;
+parameter mask_slcr__TZ_OCM_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__TZ_OCM_ROM = 32'hF8000408;
+parameter val_slcr__TZ_OCM_ROM = 32'h00000000;
+parameter mask_slcr__TZ_OCM_ROM = 32'hFFFFFFFF;
+
+parameter slcr__TZ_DDR_RAM = 32'hF8000430;
+parameter val_slcr__TZ_DDR_RAM = 32'h00000000;
+parameter mask_slcr__TZ_DDR_RAM = 32'h00000001;
+
+parameter slcr__TZ_DMA_NS = 32'hF8000440;
+parameter val_slcr__TZ_DMA_NS = 32'h00000000;
+parameter mask_slcr__TZ_DMA_NS = 32'hFFFFFFFF;
+
+parameter slcr__TZ_DMA_IRQ_NS = 32'hF8000444;
+parameter val_slcr__TZ_DMA_IRQ_NS = 32'h00000000;
+parameter mask_slcr__TZ_DMA_IRQ_NS = 32'hFFFFFFFF;
+
+parameter slcr__TZ_DMA_PERIPH_NS = 32'hF8000448;
+parameter val_slcr__TZ_DMA_PERIPH_NS = 32'h00000000;
+parameter mask_slcr__TZ_DMA_PERIPH_NS = 32'hFFFFFFFF;
+
+parameter slcr__TZ_GEM = 32'hF8000450;
+parameter val_slcr__TZ_GEM = 32'h00000000;
+parameter mask_slcr__TZ_GEM = 32'hFFFFFFFF;
+
+parameter slcr__TZ_SDIO = 32'hF8000454;
+parameter val_slcr__TZ_SDIO = 32'h00000000;
+parameter mask_slcr__TZ_SDIO = 32'hFFFFFFFF;
+
+parameter slcr__TZ_USB = 32'hF8000458;
+parameter val_slcr__TZ_USB = 32'h00000000;
+parameter mask_slcr__TZ_USB = 32'hFFFFFFFF;
+
+parameter slcr__TZ_FPGA_M = 32'hF8000484;
+parameter val_slcr__TZ_FPGA_M = 32'h00000000;
+parameter mask_slcr__TZ_FPGA_M = 32'hFFFFFFFF;
+
+parameter slcr__TZ_FPGA_AFI = 32'hF8000488;
+parameter val_slcr__TZ_FPGA_AFI = 32'h00000000;
+parameter mask_slcr__TZ_FPGA_AFI = 32'hFFFFFFFF;
+
+parameter slcr__DBG_CTRL = 32'hF8000500;
+parameter val_slcr__DBG_CTRL = 32'h00000000;
+parameter mask_slcr__DBG_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__PSS_IDCODE = 32'hF8000530;
+parameter val_slcr__PSS_IDCODE = 32'h03720093;
+parameter mask_slcr__PSS_IDCODE = 32'h0FFE0FFF;
+
+parameter slcr__DDR_URGENT = 32'hF8000600;
+parameter val_slcr__DDR_URGENT = 32'h00000000;
+parameter mask_slcr__DDR_URGENT = 32'hFFFFFFFF;
+
+parameter slcr__DDR_CAL_START = 32'hF800060C;
+parameter val_slcr__DDR_CAL_START = 32'h00000000;
+parameter mask_slcr__DDR_CAL_START = 32'hFFFFFFFF;
+
+parameter slcr__DDR_REF_START = 32'hF8000614;
+parameter val_slcr__DDR_REF_START = 32'h00000000;
+parameter mask_slcr__DDR_REF_START = 32'hFFFFFFFF;
+
+parameter slcr__DDR_CMD_STA = 32'hF8000618;
+parameter val_slcr__DDR_CMD_STA = 32'h00000000;
+parameter mask_slcr__DDR_CMD_STA = 32'hFFFFFFFF;
+
+parameter slcr__DDR_URGENT_SEL = 32'hF800061C;
+parameter val_slcr__DDR_URGENT_SEL = 32'h00000000;
+parameter mask_slcr__DDR_URGENT_SEL = 32'hFFFFFFFF;
+
+parameter slcr__DDR_DFI_STATUS = 32'hF8000620;
+parameter val_slcr__DDR_DFI_STATUS = 32'h00000000;
+parameter mask_slcr__DDR_DFI_STATUS = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_00 = 32'hF8000700;
+parameter val_slcr__MIO_PIN_00 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_00 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_01 = 32'hF8000704;
+parameter val_slcr__MIO_PIN_01 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_01 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_02 = 32'hF8000708;
+parameter val_slcr__MIO_PIN_02 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_02 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_03 = 32'hF800070C;
+parameter val_slcr__MIO_PIN_03 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_03 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_04 = 32'hF8000710;
+parameter val_slcr__MIO_PIN_04 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_04 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_05 = 32'hF8000714;
+parameter val_slcr__MIO_PIN_05 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_05 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_06 = 32'hF8000718;
+parameter val_slcr__MIO_PIN_06 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_06 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_07 = 32'hF800071C;
+parameter val_slcr__MIO_PIN_07 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_07 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_08 = 32'hF8000720;
+parameter val_slcr__MIO_PIN_08 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_08 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_09 = 32'hF8000724;
+parameter val_slcr__MIO_PIN_09 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_09 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_10 = 32'hF8000728;
+parameter val_slcr__MIO_PIN_10 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_10 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_11 = 32'hF800072C;
+parameter val_slcr__MIO_PIN_11 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_11 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_12 = 32'hF8000730;
+parameter val_slcr__MIO_PIN_12 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_12 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_13 = 32'hF8000734;
+parameter val_slcr__MIO_PIN_13 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_13 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_14 = 32'hF8000738;
+parameter val_slcr__MIO_PIN_14 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_14 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_15 = 32'hF800073C;
+parameter val_slcr__MIO_PIN_15 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_15 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_16 = 32'hF8000740;
+parameter val_slcr__MIO_PIN_16 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_16 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_17 = 32'hF8000744;
+parameter val_slcr__MIO_PIN_17 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_17 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_18 = 32'hF8000748;
+parameter val_slcr__MIO_PIN_18 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_18 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_19 = 32'hF800074C;
+parameter val_slcr__MIO_PIN_19 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_19 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_20 = 32'hF8000750;
+parameter val_slcr__MIO_PIN_20 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_20 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_21 = 32'hF8000754;
+parameter val_slcr__MIO_PIN_21 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_21 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_22 = 32'hF8000758;
+parameter val_slcr__MIO_PIN_22 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_22 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_23 = 32'hF800075C;
+parameter val_slcr__MIO_PIN_23 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_23 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_24 = 32'hF8000760;
+parameter val_slcr__MIO_PIN_24 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_24 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_25 = 32'hF8000764;
+parameter val_slcr__MIO_PIN_25 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_25 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_26 = 32'hF8000768;
+parameter val_slcr__MIO_PIN_26 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_26 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_27 = 32'hF800076C;
+parameter val_slcr__MIO_PIN_27 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_27 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_28 = 32'hF8000770;
+parameter val_slcr__MIO_PIN_28 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_28 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_2""b""9 = 32'hF8000774;
+parameter val_slcr__MIO_PIN_29 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_29 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_30 = 32'hF8000778;
+parameter val_slcr__MIO_PIN_30 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_30 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_31 = 32'hF800077C;
+parameter val_slcr__MIO_PIN_31 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_31 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_32 = 32'hF8000780;
+parameter val_slcr__MIO_PIN_32 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_32 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_33 = 32'hF8000784;
+parameter val_slcr__MIO_PIN_33 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_33 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_34 = 32'hF8000788;
+parameter val_slcr__MIO_PIN_34 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_34 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_35 = 32'hF800078C;
+parameter val_slcr__MIO_PIN_35 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_35 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_36 = 32'hF8000790;
+parameter val_slcr__MIO_PIN_36 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_36 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_37 = 32'hF8000794;
+parameter val_slcr__MIO_PIN_37 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_37 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_38 = 32'hF8000798;
+parameter val_slcr__MIO_PIN_38 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_38 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_39 = 32'hF800079C;
+parameter val_slcr__MIO_PIN_39 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_39 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_40 = 32'hF80007A0;
+parameter val_slcr__MIO_PIN_40 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_40 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_41 = 32'hF80007A4;
+parameter val_slcr__MIO_PIN_41 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_41 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_42 = 32'hF80007A8;
+parameter val_slcr__MIO_PIN_42 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_42 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_43 = 32'hF80007AC;
+parameter val_slcr__MIO_PIN_43 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_43 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_44 = 32'hF80007B0;
+parameter val_slcr__MIO_PIN_44 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_44 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_45 = 32'hF80007B4;
+parameter val_slcr__MIO_PIN_45 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_45 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_46 = 32'hF80007B8;
+parameter val_slcr__MIO_PIN_46 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_46 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_47 = 32'hF80007BC;
+parameter val_slcr__MIO_PIN_47 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_47 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_48 = 32'hF80007C0;
+parameter val_slcr__MIO_PIN_48 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_48 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_49 = 32'hF80007C4;
+parameter val_slcr__MIO_PIN_49 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_49 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_50 = 32'hF80007C8;
+parameter val_slcr__MIO_PIN_50 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_50 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_51 = 32'hF80007CC;
+parameter val_slcr__MIO_PIN_51 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_51 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_52 = 32'hF80007D0;
+parameter val_slcr__MIO_PIN_52 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_52 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_53 = 32'hF80007D4;
+parameter val_slcr__MIO_PIN_53 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_53 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_FMIO_GEM_SEL = 32'hF8000800;
+parameter val_slcr__MIO_FMIO_GEM_SEL = 32'h00000000;
+parameter mask_slcr__MIO_FMIO_GEM_SEL = 32'hFFFFFFFF;
+
+parameter slcr__MIO_LOOPBACK = 32'hF8000804;
+parameter val_slcr__MIO_LOOPBACK = 32'h00000000;
+parameter mask_slcr__MIO_LOOPBACK = 32'hFFFFFFFF;
+
+parameter slcr__MIO_MST_TRI0 = 32'hF800080C;
+parameter val_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF;
+parameter mask_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_MST_TRI1 = 32'hF8000810;
+parameter val_slcr__MIO_MST_TRI1 = 32'h003FFFFF;
+parameter mask_slcr__MIO_MST_TRI1 = 32'hFFFFFFFF;
+
+parameter slcr__SD0_WP_CD_SEL = 32'hF8000830;
+parameter val_slcr__SD0_WP_CD_SEL = 32'h00000000;
+parameter mask_slcr__SD0_WP_CD_SEL = 32'hFFFFFFFF;
+
+parameter slcr__SD1_WP_CD_SEL = 32'hF8000834;
+parameter val_slcr__SD1_WP_CD_SEL = 32'h00000000;
+parameter mask_slcr__SD1_WP_CD_SEL = 32'hFFFFFFFF;
+
+parameter slcr__LVL_SHFTR_EN = 32'hF8000900;
+parameter val_slcr__LVL_SHFTR_EN = 32'h00000000;
+parameter mask_slcr__LVL_SHFTR_EN = 32'hFFFFFFFF;
+
+parameter slcr__OCM_CFG = 32'hF8000910;
+parameter val_slcr__OCM_CFG = 32'h00000000;
+parameter mask_slcr__OCM_CFG = 32'hFFFFFFFF;
+
+parameter slcr__CPU0_RAM0 = 32'hF8000A00;
+parameter val_slcr__CPU0_RAM0 = 32'h00020202;
+parameter mask_slcr__CPU0_RAM0 = 32'h00FFFFFF;
+
+parameter slcr__CPU0_RAM1 = 32'hF8000A04;
+parameter val_slcr__CPU0_RAM1 = 32'h00020202;
+parameter mask_slcr__CPU0_RAM1 = 32'h00FFFFFF;
+
+parameter slcr__CPU0_RAM2 = 32'hF8000A08;
+parameter val_slcr__CPU0_RAM2 = 32'h02020202;
+parameter mask_slcr__CPU0_RAM2 = 32'hFFFFFFFF;
+
+parameter slcr__CPU1_RAM0 = 32'hF8000A0C;
+parameter val_slcr__CPU1_RAM0 = 32'h00020202;
+parameter mask_slcr__CPU1_RAM0 = 32'h00FFFFFF;
+
+parameter slcr__CPU1_RAM1 = 32'hF8000A10;
+parameter val_slcr__CPU1_RAM1 = 32'h00020202;
+parameter mask_slcr__CPU1_RAM1 = 32'h00FFFFFF;
+
+parameter slcr__CPU1_RAM2 = 32'hF8000A14;
+parameter val_slcr__CPU1_RAM2 = 32'h02020202;
+parameter mask_slcr__CPU1_RAM2 = 32'hFFFFFFFF;
+
+parameter slcr__SCU_RAM = 32'hF8000A18;
+parameter val_slcr__SCU_RAM = 32'h00000002;
+parameter mask_slcr__SCU_RAM = 32'h000000FF;
+
+parameter slcr__L2C_RAM = 32'hF8000A1C;
+parameter val_slcr__L2C_RAM = 32'h00020202;
+parameter mask_slcr__L2C_RAM = 32'h00FFFFFF;
+
+parameter slcr__IOU_RAM_GEM01 = 32'hF8000A30;
+parameter val_slcr__IOU_RAM_GEM01 = 32'h09090909;
+parameter mask_slcr__IOU_RAM_GEM01 = 32'hFFFFFFFF;
+
+parameter slcr__IOU_RAM_USB01 = 32'hF8000A34;
+parameter val_slcr__IOU_RAM_USB01 = 32'h09090909;
+parameter mask_slcr__IOU_RAM_USB01 = 32'hFFFFFFFF;
+
+parameter slcr__IOU_RAM_SDIO0 = 32'hF8000A38;
+parameter val_slcr__IOU_RAM_SDIO0 = 32'h09090909;
+parameter mask_slcr__IOU_RAM_SDIO0 = 32'hFFFFFFFF;
+
+parameter slcr__IOU_RAM_SDIO1 = 32'hF8000A3C;
+parameter val_slcr__IOU_RAM_SDIO1 = 32'h09090909;
+parameter mask_slcr__IOU_RAM_SDIO1 = 32'hFFFFFFFF;
+
+parameter slcr__IOU_RAM_CAN0 = 32'hF8000A40;
+parameter val_slcr__IOU_RAM_CAN0 = 32'h00090909;
+parameter mask_slcr__IOU_RAM_CAN0 = 32'h00FFFFFF;
+
+parameter slcr__IOU_RAM_CAN1 = 32'hF8000A44;
+parameter val_slcr__IOU_RAM_CAN1 = 32'h00090909;
+parameter mask_slcr__IOU_RAM_CAN1 = 32'h00FFFFFF;
+
+parameter slcr__IOU_RAM_LQSPI = 32'hF8000A48;
+parameter val_slcr__IOU_RAM_LQSPI = 32'h00000909;
+parameter mask_slcr__IOU_RAM_LQSPI = 32'h0000FFFF;
+
+parameter slcr__DMAC_RAM = 32'hF8000A50;
+parameter val_slcr__DMAC_RAM = 32'h00000009;
+parameter mask_slcr__DMAC_RAM = 32'h000000FF;
+
+parameter slcr__AFI0_RAM0 = 32'hF8000A60;
+parameter val_slcr__AFI0_RAM0 = 32'h09090909;
+parameter mask_slcr__AFI0_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__AFI0_RAM1 = 32'hF8000A64;
+parameter val_slcr__AFI0_RAM1 = 32'h09090909;
+parameter mask_slcr__AFI0_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__AFI0_RAM2 = 32'hF8000A68;
+parameter val_slcr__AFI0_RAM2 = 32'h00000909;
+parameter mask_slcr__AFI0_RAM2 = 32'h0000FFFF;
+
+parameter slcr__AFI1_RAM0 = 32'hF8000A6C;
+parameter val_slcr__AFI1_RAM0 = 32'h09090909;
+parameter mask_slcr__AFI1_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__AFI1_RAM1 = 32'hF8000A70;
+parameter val_slcr__AFI1_RAM1 = 32'h09090909;
+parameter mask_slcr__AFI1_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__AFI1_RAM2 = 32'hF8000A74;
+parameter val_slcr__AFI1_RAM2 = 32'h00000909;
+parameter mask_slcr__AFI1_RAM2 = 32'h0000FFFF;
+
+parameter slcr__AFI2_RAM0 = 32'hF8000A78;
+parameter val_slcr__AFI2_RAM0 = 32'h09090909;
+parameter mask_slcr__AFI2_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__AFI2_RAM1 = 32'hF8000A7C;
+parameter val_slcr__AFI2_RAM1 = 32'h09090909;
+parameter mask_slcr__AFI2_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__AFI2_RAM2 = 32'hF8000A80;
+parameter val_slcr__AFI2_RAM2 = 32'h00000909;
+parameter mask_slcr__AFI2_RAM2 = 32'h0000FFFF;
+
+parameter slcr__AFI3_RAM0 = 32'hF8000A84;
+parameter val_slcr__AFI3_RAM0 = 32'h09090909;
+parameter mask_slcr__AFI3_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__AFI3_RAM1 = 32'hF8000A88;
+parameter val_slcr__AFI3_RAM1 = 32'h09090909;
+parameter mask_slcr__AFI3_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__AFI3_RAM2 = 32'hF8000A8C;
+parameter val_slcr__AFI3_RAM2 = 32'h00000909;
+parameter mask_slcr__AFI3_RAM2 = 32'h0000FFFF;
+
+parameter slcr__OCM_RAM = 32'hF8000A90;
+parameter val_slcr__OCM_RAM = 32'h01010101;
+parameter mask_slcr__OCM_RAM = 32'hFFFFFFFF;
+
+parameter slcr__OCM_ROM0 = 32'hF8000A94;
+parameter val_slcr__OCM_ROM0 = 32'h09090909;
+parameter mask_slcr__OCM_ROM0 = 32'hFFFFFFFF;
+
+parameter slcr__OCM_ROM1 = 32'hF8000A98;
+parameter val_slcr__OCM_ROM1 = 32'h09090909;
+parameter mask_slcr__OCM_ROM1 = 32'hFFFFFFFF;
+
+parameter slcr__DEVCI_RAM = 32'hF8000AA0;
+parameter val_slcr__DEVCI_RAM = 32'h00000909;
+parameter mask_slcr__DEVCI_RAM = 32'h0000FFFF;
+
+parameter slcr__CSG_RAM = 32'hF8000AB0;
+parameter val_slcr__CSG_RAM = 32'h00000001;
+parameter mask_slcr__CSG_RAM = 32'h000000FF;
+
+parameter slcr__GPIOB_CTRL = 32'hF8000B00;
+parameter val_slcr__GPIOB_CTRL = 32'h00000000;
+parameter mask_slcr__GPIOB_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_CMOS18 = 32'hF8000B04;
+parameter val_slcr__GPIOB_CFG_CMOS18 = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_CMOS18 = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_CMOS25 = 32'hF8000B08;
+parameter val_slcr__GPIOB_CFG_CMOS25 = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_CMOS25 = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_CMOS33 = 32'hF8000B0C;
+parameter val_slcr__GPIOB_CFG_CMOS33 = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_CMOS33 = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_LVTTL = 32'hF8000B10;
+parameter val_slcr__GPIOB_CFG_LVTTL = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_LVTTL = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_HSTL = 32'hF8000B14;
+parameter val_slcr__GPIOB_CFG_HSTL = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_HSTL = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_DRVR_BIAS_CTRL = 32'hF8000B18;
+parameter val_slcr__GPIOB_DRVR_BIAS_CTRL = 32'h00000000;
+parameter mask_slcr__GPIOB_DRVR_BIAS_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_ADDR0 = 32'hF8000B40;
+parameter val_slcr__DDRIOB_ADDR0 = 32'h00000800;
+parameter mask_slcr__DDRIOB_ADDR0 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_ADDR1 = 32'hF8000B44;
+parameter val_slcr__DDRIOB_ADDR1 = 32'h00000800;
+parameter mask_slcr__DDRIOB_ADDR1 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DATA0 = 32'hF8000B48;
+parameter val_slcr__DDRIOB_DATA0 = 32'h00000800;
+parameter mask_slcr__DDRIOB_DATA0 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DATA1 = 32'hF8000B4C;
+parameter val_slcr__DDRIOB_DATA1 = 32'h00000800;
+parameter mask_slcr__DDRIOB_DATA1 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DIFF0 = 32'hF8000B50;
+parameter val_slcr__DDRIOB_DIFF0 = 32'h00000800;
+parameter mask_slcr__DDRIOB_DIFF0 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DIFF1 = 32'hF8000B54;
+parameter val_slcr__DDRIOB_DIFF1 = 32'h00000800;
+parameter mask_slcr__DDRIOB_DIFF1 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_CLOCK = 32'hF8000B58;
+parameter val_slcr__DDRIOB_CLOCK = 32'h00000800;
+parameter mask_slcr__DDRIOB_CLOCK = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hF8000B5C;
+parameter val_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'h00000000;
+parameter mask_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hF8000B60;
+parameter val_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'h00000000;
+parameter mask_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hF8000B64;
+parameter val_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'h00000000;
+parameter mask_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hF8000B68;
+parameter val_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'h00000000;
+parameter mask_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DDR_CTRL = 32'hF8000B6C;
+parameter val_slcr__DDRIOB_DDR_CTRL = 32'h00000000;
+parameter mask_slcr__DDRIOB_DDR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DCI_CTRL = 32'hF8000B70;
+parameter val_slcr__DDRIOB_DCI_CTRL = 32'h00000020;
+parameter mask_slcr__DDRIOB_DCI_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DCI_STATUS = 32'hF8000B74;
+parameter val_slcr__DDRIOB_DCI_STATUS = 32'h00000000;
+parameter mask_slcr__DDRIOB_DCI_STATUS = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module smcc pl353
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter smcc__memc_status = 32'hE000E000;
+parameter val_smcc__memc_status = 32'h00000000;
+parameter mask_smcc__memc_status = 32'h00001FFF;
+
+parameter smcc__memif_cfg = 32'hE000E004;
+parameter val_smcc__memif_cfg = 32'h00011205;
+parameter mask_smcc__memif_cfg = 32'h0003FFFF;
+
+parameter smcc__memc_cfg_set = 32'hE000E008;
+parameter val_smcc__memc_cfg_set = 32'h00000000;
+parameter mask_smcc__memc_cfg_set = 32'h00000000;
+
+parameter smcc__memc_cfg_clr = 32'hE000E00C;
+parameter val_smcc__memc_cfg_clr = 32'h00000000;
+parameter mask_smcc__memc_cfg_clr = 32'h00000000;
+
+parameter smcc__direct_cmd = 32'hE000E010;
+parameter val_smcc__direct_cmd = 32'h00000000;
+parameter mask_smcc__direct_cmd = 32'h00000000;
+
+parameter smcc__set_cycles = 32'hE000E014;
+parameter val_smcc__set_cycles = 32'h00000000;
+parameter mask_smcc__set_cycles = 32'h00000000;
+
+parameter smcc__set_opmode = 32'hE000E018;
+parameter val_smcc__set_opmode = 32'h00000000;
+parameter mask_smcc__set_opmode = 32'h00000000;
+
+parameter smcc__refresh_period_0 = 32'hE000E020;
+parameter val_smcc__refresh_period_0 = 32'h00000000;
+parameter mask_smcc__refresh_period_0 = 32'h0000000F;
+
+parameter smcc__refresh_period_1 = 32'hE000E024;
+parameter val_smcc__refresh_period_1 = 32'h00000000;
+parameter mask_smcc__refresh_period_1 = 32'h0000000F;
+
+parameter smcc__sram_cycles0_0 = 32'hE000E100;
+parameter val_smcc__sram_cycles0_0 = 32'h0002B3CC;
+parameter mask_smcc__sram_cycles0_0 = 32'h001FFFFF;
+
+parameter smcc__opmode0_0 = 32'hE000E104;
+parameter val_smcc__opmode0_0 = 32'hE2FE0800;
+parameter mask_smcc__opmode0_0 = 32'hFFFFFFFF;
+
+parameter smcc__sram_cycles0_1 = 32'hE000E120;
+parameter val_smcc__sram_cycles0_1 = 32'h0002B3CC;
+parameter mask_smcc__sram_cycles0_1 = 32'h001FFFFF;
+
+parameter smcc__opmode0_1 = 32'hE000E124;
+parameter val_smcc__opmode0_1 = 32'hE4FE0800;
+parameter mask_smcc__opmode0_1 = 32'hFFFFFFFF;
+
+parameter smcc__nand_cycles1_0 = 32'hE000E180;
+parameter val_smcc__nand_cycles1_0 = 32'h0024ABCC;
+parameter mask_smcc__nand_cycles1_0 = 32'h00FFFFFF;
+
+parameter smcc__opmode1_0 = 32'hE000E184;
+parameter val_smcc__opmode1_0 = 32'hE1FF0001;
+parameter mask_smcc__opmode1_0 = 32'hFFFFFFFF;
+
+parameter smcc__user_status = 32'hE000E200;
+parameter val_smcc__user_status = 32'h00000000;
+parameter mask_smcc__user_status = 32'h000000FF;
+
+parameter smcc__user_config = 32'hE000E204;
+parameter val_smcc__user_config = 32'h00000000;
+parameter mask_smcc__user_config = 32'h00000000;
+
+parameter smcc__ecc_status_0 = 32'hE000E300;
+parameter val_smcc__ecc_status_0 = 32'h00000000;
+parameter mask_smcc__ecc_status_0 = 32'h3FFFFFFF;
+
+parameter smcc__ecc_memcfg_0 = 32'hE000E304;
+parameter val_smcc__ecc_memcfg_0 = 32'h00000000;
+parameter mask_smcc__ecc_memcfg_0 = 32'h00001FFF;
+
+parameter smcc__ecc_memcommand1_0 = 32'hE000E308;
+parameter val_smcc__ecc_memcommand1_0 = 32'h00000000;
+parameter mask_smcc__ecc_memcommand1_0 = 32'h01FFFFFF;
+
+parameter smcc__ecc_memcommand2_0 = 32'hE000E30C;
+parameter val_smcc__ecc_memcommand2_0 = 32'h00000000;
+parameter mask_smcc__ecc_memcommand2_0 = 32'h01FFFFFF;
+
+parameter smcc__ecc_addr0_0 = 32'hE000E310;
+parameter val_smcc__ecc_addr0_0 = 32'h00000000;
+parameter mask_smcc__ecc_addr0_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_addr1_0 = 32'hE000E314;
+parameter val_smcc__ecc_addr1_0 = 32'h00000000;
+parameter mask_smcc__ecc_addr1_0 = 32'h00FFFFFF;
+
+parameter smcc__ecc_value0_0 = 32'hE000E318;
+parameter val_smcc__ecc_value0_0 = 32'h00000000;
+parameter mask_smcc__ecc_value0_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value1_0 = 32'hE000E31C;
+parameter val_smcc__ecc_value1_0 = 32'h00000000;
+parameter mask_smcc__ecc_value1_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value2_0 = 32'hE000E320;
+parameter val_smcc__ecc_value2_0 = 32'h00000000;
+parameter mask_smcc__ecc_value2_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value3_0 = 32'hE000E324;
+parameter val_smcc__ecc_value3_0 = 32'h00000000;
+parameter mask_smcc__ecc_value3_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_status_1 = 32'hE000E400;
+parameter val_smcc__ecc_status_1 = 32'h00000000;
+parameter mask_smcc__ecc_status_1 = 32'h3FFFFFFF;
+
+parameter smcc__ecc_memcfg_1 = 32'hE000E404;
+parameter val_smcc__ecc_memcfg_1 = 32'h00000043;
+parameter mask_smcc__ecc_memcfg_1 = 32'h00001FFF;
+
+parameter smcc__ecc_memcommand1_1 = 32'hE000E408;
+parameter val_smcc__ecc_memcommand1_1 = 32'h01300080;
+parameter mask_smcc__ecc_memcommand1_1 = 32'h01FFFFFF;
+
+parameter smcc__ecc_memcommand2_1 = 32'hE000E40C;
+parameter val_smcc__ecc_memcommand2_1 = 32'h01E00585;
+parameter mask_smcc__ecc_memcommand2_1 = 32'h01FFFFFF;
+
+parameter smcc__ecc_addr0_1 = 32'hE000E410;
+parameter val_smcc__ecc_addr0_1 = 32'h00000000;
+parameter mask_smcc__ecc_addr0_1 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_addr1_1 = 32'hE000E414;
+parameter val_smcc__ecc_addr1_1 = 32'h00000000;
+parameter mask_smcc__ecc_addr1_1 = 32'h00FFFFFF;
+
+parameter smcc__ecc_value0_1 = 32'hE000E418;
+parameter val_smcc__ecc_value0_1 = 32'h00000000;
+parameter mask_smcc__ecc_value0_1 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value1_1 = 32'hE000E41C;
+parameter val_smcc__ecc_value1_1 = 32'h00000000;
+parameter mask_smcc__ecc_value1_1 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value2_1 = 32'hE000E420;
+parameter val_smcc__ecc_value2_1 = 32'h00000000;
+parameter mask_smcc__ecc_value2_1 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value3_1 = 32'hE000E424;
+parameter val_smcc__ecc_value3_1 = 32'h00000000;
+parameter mask_smcc__ecc_value3_1 = 32'hFFFFFFFF;
+
+parameter smcc__integration_test = 32'hE000EE00;
+parameter val_smcc__integration_test = 32'h00000000;
+parameter mask_smcc__integration_test = 32'hFFFFFFFF;
+
+parameter smcc__periph_id_0 = 32'hE000EFE0;
+parameter val_smcc__periph_id_0 = 32'h00000053;
+parameter mask_smcc__periph_id_0 = 32'h000000FF;
+
+parameter smcc__periph_id_1 = 32'hE000EFE4;
+parameter val_smcc__periph_id_1 = 32'h00000013;
+parameter mask_smcc__periph_id_1 = 32'h000000FF;
+
+parameter smcc__periph_id_2 = 32'hE000EFE8;
+parameter val_smcc__periph_id_2 = 32'h00000054;
+parameter mask_smcc__periph_id_2 = 32'h000000FF;
+
+parameter smcc__periph_id_3 = 32'hE000EFEC;
+parameter val_smcc__periph_id_3 = 32'h00000000;
+parameter mask_smcc__periph_id_3 = 32'h00000001;
+
+parameter smcc__pcell_id_0 = 32'hE000EFF0;
+parameter val_smcc__pcell_id_0 = 32'h0000000D;
+parameter mask_smcc__pcell_id_0 = 32'h000000FF;
+
+parameter smcc__pcell_id_1 = 32'hE000EFF4;
+parameter val_smcc__pcell_id_1 = 32'h000000F0;
+parameter mask_smcc__pcell_id_1 = 32'h000000FF;
+
+parameter smcc__pcell_id_2 = 32'hE000EFF8;
+parameter val_smcc__pcell_id_2 = 32'h00000005;
+parameter mask_smcc__pcell_id_2 = 32'h000000FF;
+
+parameter smcc__pcell_id_3 = 32'hE000EFFC;
+parameter val_smcc__pcell_id_3 = 32'h000000B1;
+parameter mask_smcc__pcell_id_3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module spi0 SPI
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter spi0__Config_reg0 = 32'hE0006000;
+parameter val_spi0__Config_reg0 = 32'h00020000;
+parameter mask_spi0__Config_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Intr_status_reg0 = 32'hE0006004;
+parameter val_spi0__Intr_status_reg0 = 32'h00000004;
+parameter mask_spi0__Intr_status_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Intrpt_en_reg0 = 32'hE0006008;
+parameter val_spi0__Intrpt_en_reg0 = 32'h00000000;
+parameter mask_spi0__Intrpt_en_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Intrpt_dis_reg0 = 32'hE000600C;
+parameter val_spi0__Intrpt_dis_reg0 = 32'h00000000;
+parameter mask_spi0__Intrpt_dis_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Intrpt_mask_reg0 = 32'hE0006010;
+parameter val_spi0__Intrpt_mask_reg0 = 32'h00000000;
+parameter mask_spi0__Intrpt_mask_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__En_reg0 = 32'hE0006014;
+parameter val_spi0__En_reg0 = 32'h00000000;
+parameter mask_spi0__En_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Delay_reg0 = 32'hE0006018;
+parameter val_spi0__Delay_reg0 = 32'h00000000;
+parameter mask_spi0__Delay_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Tx_data_reg0 = 32'hE000601C;
+parameter val_spi0__Tx_data_reg0 = 32'h00000000;
+parameter mask_spi0__Tx_data_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Rx_data_reg0 = 32'hE0006020;
+parameter val_spi0__Rx_data_reg0 = 32'h00000000;
+parameter mask_spi0__Rx_data_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Slave_Idle_count_reg0 = 32'hE0006024;
+parameter val_spi0__Slave_Idle_count_reg0 = 32'h000000FF;
+parameter mask_spi0__Slave_Idle_count_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__TX_thres_reg0 = 32'hE0006028;
+parameter val_spi0__TX_thres_reg0 = 32'h00000001;
+parameter mask_spi0__TX_thres_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__RX_thres_reg0 = 32'hE000602C;
+parameter val_spi0__RX_thres_reg0 = 32'h00000001;
+parameter mask_spi0__RX_thres_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Mod_id_reg0 = 32'hE00060FC;
+parameter val_spi0__Mod_id_reg0 = 32'h00090106;
+parameter mask_spi0__Mod_id_reg0 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module spi1 SPI
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter spi1__Config_reg0 = 32'hE0007000;
+parameter val_spi1__Config_reg0 = 32'h00020000;
+parameter mask_spi1__Config_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Intr_status_reg0 = 32'hE0007004;
+parameter val_spi1__Intr_status_reg0 = 32'h00000004;
+parameter mask_spi1__Intr_status_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Intrpt_en_reg0 = 32'hE0007008;
+parameter val_spi1__Intrpt_en_reg0 = 32'h00000000;
+parameter mask_spi1__Intrpt_en_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Intrpt_dis_reg0 = 32'hE000700C;
+parameter val_spi1__Intrpt_dis_reg0 = 32'h00000000;
+parameter mask_spi1__Intrpt_dis_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Intrpt_mask_reg0 = 32'hE0007010;
+parameter val_spi1__Intrpt_mask_reg0 = 32'h00000000;
+parameter mask_spi1__Intrpt_mask_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__En_reg0 = 32'hE0007014;
+parameter val_spi1__En_reg0 = 32'h00000000;
+parameter mask_spi1__En_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Delay_reg0 = 32'hE0007018;
+parameter val_spi1__Delay_reg0 = 32'h00000000;
+parameter mask_spi1__Delay_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Tx_data_reg0 = 32'hE000701C;
+parameter val_spi1__Tx_data_reg0 = 32'h00000000;
+parameter mask_spi1__Tx_data_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Rx_data_reg0 = 32'hE0007020;
+parameter val_spi1__Rx_data_reg0 = 32'h00000000;
+parameter mask_spi1__Rx_data_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Slave_Idle_count_reg0 = 32'hE0007024;
+parameter val_spi1__Slave_Idle_count_reg0 = 32'h000000FF;
+parameter mask_spi1__Slave_Idle_count_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__TX_thres_reg0 = 32'hE0007028;
+parameter val_spi1__TX_thres_reg0 = 32'h00000001;
+parameter mask_spi1__TX_thres_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__RX_thres_reg0 = 32'hE000702C;
+parameter val_spi1__RX_thres_reg0 = 32'h00000001;
+parameter mask_spi1__RX_thres_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Mod_id_reg0 = 32'hE00070FC;
+parameter val_spi1__Mod_id_reg0 = 32'h00090106;
+parameter mask_spi1__Mod_id_reg0 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module swdt swdt
+//   doc version: 2.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter swdt__MODE = 32'hF8005000;
+parameter val_swdt__MODE = 32'h000001C2;
+parameter mask_swdt__MODE = 32'h00FFFFFF;
+
+parameter swdt__CONTROL = 32'hF8005004;
+parameter val_swdt__CONTROL = 32'h03FFC3FC;
+parameter mask_swdt__CONTROL = 32'h03FFFFFF;
+
+parameter swdt__RESTART = 32'hF8005008;
+parameter val_swdt__RESTART = 32'h00000000;
+parameter mask_swdt__RESTART = 32'h0000FFFF;
+
+parameter swdt__STATUS = 32'hF800500C;
+parameter val_swdt__STATUS = 32'h00000000;
+parameter mask_swdt__STATUS = 32'h00000001;
+
+
+// ************************************************************
+//   Module ttc0 ttc
+//   doc version: 2.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter ttc0__Clock_Control_1 = 32'hF8001000;
+parameter val_ttc0__Clock_Control_1 = 32'h00000000;
+parameter mask_ttc0__Clock_Control_1 = 32'h0000007F;
+
+parameter ttc0__Clock_Control_2 = 32'hF8001004;
+parameter val_ttc0__Clock_Control_2 = 32'h00000000;
+parameter mask_ttc0__Clock_Control_2 = 32'h0000007F;
+
+parameter ttc0__Clock_Control_3 = 32'hF8001008;
+parameter val_ttc0__Clock_Control_3 = 32'h00000000;
+parameter mask_ttc0__Clock_Control_3 = 32'h0000007F;
+
+parameter ttc0__Counter_Control_1 = 32'hF800100C;
+parameter val_ttc0__Counter_Control_1 = 32'h00000021;
+parameter mask_ttc0__Counter_Control_1 = 32'h0000007F;
+
+parameter ttc0__Counter_Control_2 = 32'hF8001010;
+parameter val_ttc0__Counter_Control_2 = 32'h00000021;
+parameter mask_ttc0__Counter_Control_2 = 32'h0000007F;
+
+parameter ttc0__Counter_Control_3 = 32'hF8001014;
+parameter val_ttc0__Counter_Control_3 = 32'h00000021;
+parameter mask_ttc0__Counter_Control_3 = 32'h0000007F;
+
+parameter ttc0__Counter_Value_1 = 32'hF8001018;
+parameter val_ttc0__Counter_Value_1 = 32'h00000000;
+parameter mask_ttc0__Counter_Value_1 = 32'h0000FFFF;
+
+parameter ttc0__Counter_Value_2 = 32'hF800101C;
+parameter val_ttc0__Counter_Value_2 = 32'h00000000;
+parameter mask_ttc0__Counter_Value_2 = 32'h0000FFFF;
+
+parameter ttc0__Counter_Value_3 = 32'hF8001020;
+parameter val_ttc0__Counter_Value_3 = 32'h00000000;
+parameter mask_ttc0__Counter_Value_3 = 32'h0000FFFF;
+
+parameter ttc0__Interval_Counter_1 = 32'hF8001024;
+parameter val_ttc0__Interval_Counter_1 = 32'h00000000;
+parameter mask_ttc0__Interval_Counter_1 = 32'h0000FFFF;
+
+parameter ttc0__Interval_Counter_2 = 32'hF8001028;
+parameter val_ttc0__Interval_Counter_2 = 32'h00000000;
+parameter mask_ttc0__Interval_Counter_2 = 32'h0000FFFF;
+
+parameter ttc0__Interval_Counter_3 = 32'hF800102C;
+parameter val_ttc0__Interval_Counter_3 = 32'h00000000;
+parameter mask_ttc0__Interval_Counter_3 = 32'h0000FFFF;
+
+parameter ttc0__Match_1_Counter_1 = 32'hF8001030;
+parameter val_ttc0__Match_1_Counter_1 = 32'h00000000;
+parameter mask_ttc0__Match_1_Counter_1 = 32'h0000FFFF;
+
+parameter ttc0__Match_1_Counter_2 = 32'hF8001034;
+parameter val_ttc0__Match_1_Counter_2 = 32'h00000000;
+parameter mask_ttc0__Match_1_Counter_2 = 32'h0000FFFF;
+
+parameter ttc0__Match_1_Counter_3 = 32'hF8001038;
+parameter val_ttc0__Match_1_Counter_3 = 32'h00000000;
+parameter mask_ttc0__Match_1_Counter_3 = 32'h0000FFFF;
+
+parameter ttc0__Match_2_Counter_1 = 32'hF800103C;
+parameter val_ttc0__Match_2_Counter_1 = 32'h00000000;
+parameter mask_ttc0__Match_2_Counter_1 = 32'h0000FFFF;
+
+parameter ttc0__Match_2_Counter_2 = 32'hF8001040;
+parameter val_ttc0__Match_2_Counter_2 = 32'h00000000;
+parameter mask_ttc0__Match_2_Counter_2 = 32'h0000FFFF;
+
+parameter ttc0__Match_2_Counter_3 = 32'hF8001044;
+parameter val_ttc0__Match_2_Counter_3 = 32'h00000000;
+parameter mask_ttc0__Match_2_Counter_3 = 32'h0000FFFF;
+
+parameter ttc0__Match_3_Counter_1 = 32'hF8001048;
+parameter val_ttc0__Match_3_Counter_1 = 32'h00000000;
+parameter mask_ttc0__Match_3_Counter_1 = 32'h0000FFFF;
+
+parameter ttc0__Match_3_Counter_2 = 32'hF800104C;
+parameter val_ttc0__Match_3_Counter_2 = 32'h00000000;
+parameter mask_ttc0__Match_3_Counter_2 = 32'h0000FFFF;
+
+parameter ttc0__Match_3_Counter_3 = 32'hF8001050;
+parameter val_ttc0__Match_3_Counter_3 = 32'h00000000;
+parameter mask_ttc0__Match_3_Counter_3 = 32'h0000FFFF;
+
+parameter ttc0__Interrupt_Register_1 = 32'hF8001054;
+parameter val_ttc0__Interrupt_Register_1 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Register_1 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Register_2 = 32'hF8001058;
+parameter val_ttc0__Interrupt_Register_2 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Register_2 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Register_3 = 32'hF800105C;
+parameter val_ttc0__Interrupt_Register_3 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Register_3 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Enable_1 = 32'hF8001060;
+parameter val_ttc0__Interrupt_Enable_1 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Enable_1 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Enable_2 = 32'hF8001064;
+parameter val_ttc0__Interrupt_Enable_2 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Enable_2 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Enable_3 = 32'hF8001068;
+parameter val_ttc0__Interrupt_Enable_3 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Enable_3 = 32'h0000003F;
+
+parameter ttc0__Event_Control_Timer_1 = 32'hF800106C;
+parameter val_ttc0__Event_Control_Timer_1 = 32'h00000000;
+parameter mask_ttc0__Event_Control_Timer_1 = 32'h00000007;
+
+parameter ttc0__Event_Control_Timer_2 = 32'hF8001070;
+parameter val_ttc0__Event_Control_Timer_2 = 32'h00000000;
+parameter mask_ttc0__Event_Control_Timer_2 = 32'h00000007;
+
+parameter ttc0__Event_Control_Timer_3 = 32'hF8001074;
+parameter val_ttc0__Event_Control_Timer_3 = 32'h00000000;
+parameter mask_ttc0__Event_Control_Timer_3 = 32'h00000007;
+
+parameter ttc0__Event_Register_1 = 32'hF8001078;
+parameter val_ttc0__Event_Register_1 = 32'h00000000;
+parameter mask_ttc0__Event_Register_1 = 32'h0000FFFF;
+
+parameter ttc0__Event_Register_2 = 32'hF800107C;
+parameter val_ttc0__Event_Register_2 = 32'h00000000;
+parameter mask_ttc0__Event_Register_2 = 32'h0000FFFF;
+
+parameter ttc0__Event_Register_3 = 32'hF8001080;
+parameter val_ttc0__Event_Register_3 = 32'h00000000;
+parameter mask_ttc0__Event_Register_3 = 32'h0000FFFF;
+
+
+// ************************************************************
+//   Module ttc1 ttc
+//   doc version: 2.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter ttc1__Clock_Control_1 = 32'hF8002000;
+parameter val_ttc1__Clock_Control_1 = 32'h00000000;
+parameter mask_ttc1__Clock_Control_1 = 32'h0000007F;
+
+parameter ttc1__Clock_Control_2 = 32'hF8002004;
+parameter val_ttc1__Clock_Control_2 = 32'h00000000;
+parameter mask_ttc1__Clock_Control_2 = 32'h0000007F;
+
+parameter ttc1__Clock_Control_3 = 32'hF8002008;
+parameter val_ttc1__Clock_Control_3 = 32'h00000000;
+parameter mask_ttc1__Clock_Control_3 = 32'h0000007F;
+
+parameter ttc1__Counter_Control_1 = 32'hF800200C;
+parameter val_ttc1__Counter_Control_1 = 32'h00000021;
+parameter mask_ttc1__Counter_Control_1 = 32'h0000007F;
+
+parameter ttc1__Counter_Control_2 = 32'hF8002010;
+parameter val_ttc1__Counter_Control_2 = 32'h00000021;
+parameter mask_ttc1__Counter_Control_2 = 32'h0000007F;
+
+parameter ttc1__Counter_Control_3 = 32'hF8002014;
+parameter val_ttc1__Counter_Control_3 = 32'h00000021;
+parameter mask_ttc1__Counter_Control_3 = 32'h0000007F;
+
+parameter ttc1__Counter_Value_1 = 32'hF8002018;
+parameter val_ttc1__Counter_Value_1 = 32'h00000000;
+parameter mask_ttc1__Counter_Value_1 = 32'h0000FFFF;
+
+parameter ttc1__Counter_Value_2 = 32'hF800201C;
+parameter val_ttc1__Counter_Value_2 = 32'h00000000;
+parameter mask_ttc1__Counter_Value_2 = 32'h0000FFFF;
+
+parameter ttc1__Counter_Value_3 = 32'hF8002020;
+parameter val_ttc1__Counter_Value_3 = 32'h00000000;
+parameter mask_ttc1__Counter_Value_3 = 32'h0000FFFF;
+
+parameter ttc1__Interval_Counter_1 = 32'hF8002024;
+parameter val_ttc1__Interval_Counter_1 = 32'h00000000;
+parameter mask_ttc1__Interval_Counter_1 = 32'h0000FFFF;
+
+parameter ttc1__Interval_Counter_2 = 32'hF8002028;
+parameter val_ttc1__Interval_Counter_2 = 32'h00000000;
+parameter mask_ttc1__Interval_Counter_2 = 32'h0000FFFF;
+
+parameter ttc1__Interval_Counter_3 = 32'hF800202C;
+parameter val_ttc1__Interval_Counter_3 = 32'h00000000;
+parameter mask_ttc1__Interval_Counter_3 = 32'h0000FFFF;
+
+parameter ttc1__Match_1_Counter_1 = 32'hF8002030;
+parameter val_ttc1__Match_1_Counter_1 = 32'h00000000;
+parameter mask_ttc1__Match_1_Counter_1 = 32'h0000FFFF;
+
+parameter ttc1__Match_1_Counter_2 = 32'hF8002034;
+parameter val_ttc1__Match_1_Counter_2 = 32'h00000000;
+parameter mask_ttc1__Match_1_Counter_2 = 32'h0000FFFF;
+
+parameter ttc1__Match_1_Counter_3 = 32'hF8002038;
+parameter val_ttc1__Match_1_Counter_3 = 32'h00000000;
+parameter mask_ttc1__Match_1_Counter_3 = 32'h0000FFFF;
+
+parameter ttc1__Match_2_Counter_1 = 32'hF800203C;
+parameter val_ttc1__Match_2_Counter_1 = 32'h00000000;
+parameter mask_ttc1__Match_2_Counter_1 = 32'h0000FFFF;
+
+parameter ttc1__Match_2_Counter_2 = 32'hF8002040;
+parameter val_ttc1__Match_2_Counter_2 = 32'h00000000;
+parameter mask_ttc1__Match_2_Counter_2 = 32'h0000FFFF;
+
+parameter ttc1__Match_2_Counter_3 = 32'hF8002044;
+parameter val_ttc1__Match_2_Counter_3 = 32'h00000000;
+parameter mask_ttc1__Match_2_Counter_3 = 32'h0000FFFF;
+
+parameter ttc1__Match_3_Counter_1 = 32'hF8002048;
+parameter val_ttc1__Match_3_Counter_1 = 32'h00000000;
+parameter mask_ttc1__Match_3_Counter_1 = 32'h0000FFFF;
+
+parameter ttc1__Match_3_Counter_2 = 32'hF800204C;
+parameter val_ttc1__Match_3_Counter_2 = 32'h00000000;
+parameter mask_ttc1__Match_3_Counter_2 = 32'h0000FFFF;
+
+parameter ttc1__Match_3_Counter_3 = 32'hF8002050;
+parameter val_ttc1__Match_3_Counter_3 = 32'h00000000;
+parameter mask_ttc1__Match_3_Counter_3 = 32'h0000FFFF;
+
+parameter ttc1__Interrupt_Register_1 = 32'hF8002054;
+parameter val_ttc1__Interrupt_Register_1 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Register_1 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Register_2 = 32'hF8002058;
+parameter val_ttc1__Interrupt_Register_2 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Register_2 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Register_3 = 32'hF800205C;
+parameter val_ttc1__Interrupt_Register_3 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Register_3 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Enable_1 = 32'hF8002060;
+parameter val_ttc1__Interrupt_Enable_1 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Enable_1 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Enable_2 = 32'hF8002064;
+parameter val_ttc1__Interrupt_Enable_2 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Enable_2 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Enable_3 = 32'hF8002068;
+parameter val_ttc1__Interrupt_Enable_3 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Enable_3 = 32'h0000003F;
+
+parameter ttc1__Event_Control_Timer_1 = 32'hF800206C;
+parameter val_ttc1__Event_Control_Timer_1 = 32'h00000000;
+parameter mask_ttc1__Event_Control_Timer_1 = 32'h00000007;
+
+parameter ttc1__Event_Control_Timer_2 = 32'hF8002070;
+parameter val_ttc1__Event_Control_Timer_2 = 32'h00000000;
+parameter mask_ttc1__Event_Control_Timer_2 = 32'h00000007;
+
+parameter ttc1__Event_Control_Timer_3 = 32'hF8002074;
+parameter val_ttc1__Event_Control_Timer_3 = 32'h00000000;
+parameter mask_ttc1__Event_Control_Timer_3 = 32'h00000007;
+
+parameter ttc1__Event_Register_1 = 32'hF8002078;
+parameter val_ttc1__Event_Register_1 = 32'h00000000;
+parameter mask_ttc1__Event_Register_1 = 32'h0000FFFF;
+
+parameter ttc1__Event_Register_2 = 32'hF800207C;
+parameter val_ttc1__Event_Register_2 = 32'h00000000;
+parameter mask_ttc1__Event_Register_2 = 32'h0000FFFF;
+
+parameter ttc1__Event_Register_3 = 32'hF8002080;
+parameter val_ttc1__Event_Register_3 = 32'h00000000;
+parameter mask_ttc1__Event_Register_3 = 32'h0000FFFF;
+
+
+// ************************************************************
+//   Module uart0 UART
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter uart0__Control_reg0 = 32'hE0000000;
+parameter val_uart0__Control_reg0 = 32'h00000128;
+parameter mask_uart0__Control_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__mode_reg0 = 32'hE0000004;
+parameter val_uart0__mode_reg0 = 32'h00000000;
+parameter mask_uart0__mode_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Intrpt_en_reg0 = 32'hE0000008;
+parameter val_uart0__Intrpt_en_reg0 = 32'h00000000;
+parameter mask_uart0__Intrpt_en_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Intrpt_dis_reg0 = 32'hE000000C;
+parameter val_uart0__Intrpt_dis_reg0 = 32'h00000000;
+parameter mask_uart0__Intrpt_dis_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Intrpt_mask_reg0 = 32'hE0000010;
+parameter val_uart0__Intrpt_mask_reg0 = 32'h00000000;
+parameter mask_uart0__Intrpt_mask_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Chnl_int_sts_reg0 = 32'hE0000014;
+parameter val_uart0__Chnl_int_sts_reg0 = 32'h00000200;
+parameter mask_uart0__Chnl_int_sts_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Baud_rate_gen_reg0 = 32'hE0000018;
+parameter val_uart0__Baud_rate_gen_reg0 = 32'h0000028B;
+parameter mask_uart0__Baud_rate_gen_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Rcvr_timeout_reg0 = 32'hE000001C;
+parameter val_uart0__Rcvr_timeout_reg0 = 32'h00000000;
+parameter mask_uart0__Rcvr_timeout_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Rcvr_FIFO_trigger_level0 = 32'hE0000020;
+parameter val_uart0__Rcvr_FIFO_trigger_level0 = 32'h00000020;
+parameter mask_uart0__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF;
+
+parameter uart0__Modem_ctrl_reg0 = 32'hE0000024;
+parameter val_uart0__Modem_ctrl_reg0 = 32'h00000000;
+parameter mask_uart0__Modem_ctrl_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Modem_sts_reg0 = 32'hE0000028;
+parameter val_uart0__Modem_sts_reg0 = 32'h00000000;
+parameter mask_uart0__Modem_sts_reg0 = 32'h00000000;
+
+parameter uart0__Channel_sts_reg0 = 32'hE000002C;
+parameter val_uart0__Channel_sts_reg0 = 32'h00000000;
+parameter mask_uart0__Channel_sts_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__TX_RX_FIFO0 = 32'hE0000030;
+parameter val_uart0__TX_RX_FIFO0 = 32'h00000000;
+parameter mask_uart0__TX_RX_FIFO0 = 32'hFFFFFFFF;
+
+parameter uart0__Baud_rate_divider_reg0 = 32'hE0000034;
+parameter val_uart0__Baud_rate_divider_reg0 = 32'h0000000F;
+parameter mask_uart0__Baud_rate_divider_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Flow_delay_reg0 = 32'hE0000038;
+parameter val_uart0__Flow_delay_reg0 = 32'h00000000;
+parameter mask_uart0__Flow_delay_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__IR_min_rcv_pulse_wdth0 = 32'hE000003C;
+parameter val_uart0__IR_min_rcv_pulse_wdth0 = 32'h00000000;
+parameter mask_uart0__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF;
+
+parameter uart0__IR_transmitted_pulse_wdth0 = 32'hE0000040;
+parameter val_uart0__IR_transmitted_pulse_wdth0 = 32'h00000000;
+parameter mask_uart0__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF;
+
+parameter uart0__Tx_FIFO_trigger_level0 = 32'hE0000044;
+parameter val_uart0__Tx_FIFO_trigger_level0 = 32'h00000020;
+parameter mask_uart0__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module uart1 UART
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter uart1__Control_reg0 = 32'hE0001000;
+parameter val_uart1__Control_reg0 = 32'h00000128;
+parameter mask_uart1__Control_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__mode_reg0 = 32'hE0001004;
+parameter val_uart1__mode_reg0 = 32'h00000000;
+parameter mask_uart1__mode_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Intrpt_en_reg0 = 32'hE0001008;
+parameter val_uart1__Intrpt_en_reg0 = 32'h00000000;
+parameter mask_uart1__Intrpt_en_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Intrpt_dis_reg0 = 32'hE000100C;
+parameter val_uart1__Intrpt_dis_reg0 = 32'h00000000;
+parameter mask_uart1__Intrpt_dis_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Intrpt_mask_reg0 = 32'hE0001010;
+parameter val_uart1__Intrpt_mask_reg0 = 32'h00000000;
+parameter mask_uart1__Intrpt_mask_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Chnl_int_sts_reg0 = 32'hE0001014;
+parameter val_uart1__Chnl_int_sts_reg0 = 32'h00000200;
+parameter mask_uart1__Chnl_int_sts_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Baud_rate_gen_reg0 = 32'hE0001018;
+parameter val_uart1__Baud_rate_gen_reg0 = 32'h0000028B;
+parameter mask_uart1__Baud_rate_gen_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Rcvr_timeout_reg0 = 32'hE000101C;
+parameter val_uart1__Rcvr_timeout_reg0 = 32'h00000000;
+parameter mask_uart1__Rcvr_timeout_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Rcvr_FIFO_trigger_level0 = 32'hE0001020;
+parameter val_uart1__Rcvr_FIFO_trigger_level0 = 32'h00000020;
+parameter mask_uart1__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF;
+
+parameter uart1__Modem_ctrl_reg0 = 32'hE0001024;
+parameter val_uart1__Modem_ctrl_reg0 = 32'h00000000;
+parameter mask_uart1__Modem_ctrl_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Modem_sts_reg0 = 32'hE0001028;
+parameter val_uart1__Modem_sts_reg0 = 32'h00000000;
+parameter mask_uart1__Modem_sts_reg0 = 32'h00000000;
+
+parameter uart1__Channel_sts_reg0 = 32'hE000102C;
+parameter val_uart1__Channel_sts_reg0 = 32'h00000000;
+parameter mask_uart1__Channel_sts_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__TX_RX_FIFO0 = 32'hE0001030;
+parameter val_uart1__TX_RX_FIFO0 = 32'h00000000;
+parameter mask_uart1__TX_RX_FIFO0 = 32'hFFFFFFFF;
+
+parameter uart1__Baud_rate_divider_reg0 = 32'hE0001034;
+parameter val_uart1__Baud_rate_divider_reg0 = 32'h0000000F;
+parameter mask_uart1__Baud_rate_divider_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Flow_delay_reg0 = 32'hE0001038;
+parameter val_uart1__Flow_delay_reg0 = 32'h00000000;
+parameter mask_uart1__Flow_delay_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__IR_min_rcv_pulse_wdth0 = 32'hE000103C;
+parameter val_uart1__IR_min_rcv_pulse_wdth0 = 32'h00000000;
+parameter mask_uart1__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF;
+
+parameter uart1__IR_transmitted_pulse_wdth0 = 32'hE0001040;
+parameter val_uart1__IR_transmitted_pulse_wdth0 = 32'h00000000;
+parameter mask_uart1__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF;
+
+parameter uart1__Tx_FIFO_trigger_level0 = 32'hE0001044;
+parameter val_uart1__Tx_FIFO_trigger_level0 = 32'h00000020;
+parameter mask_uart1__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module usb0 usb
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter usb0__ID = 32'hE0002000;
+parameter val_usb0__ID = 32'hE441FA05;
+parameter mask_usb0__ID = 32'hFFFFFFFF;
+
+parameter usb0__HWGENERAL = 32'hE0002004;
+parameter val_usb0__HWGENERAL = 32'h00000083;
+parameter mask_usb0__HWGENERAL = 32'h00000FFF;
+
+parameter usb0__HWHOST = 32'hE0002008;
+parameter val_usb0__HWHOST = 32'h10020001;
+parameter mask_usb0__HWHOST = 32'hFFFFFFFF;
+
+parameter usb0__HWDEVICE = 32'hE000200C;
+parameter val_usb0__HWDEVICE = 32'h00000019;
+parameter mask_usb0__HWDEVICE = 32'h0000003F;
+
+parameter usb0__HWTXBUF = 32'hE0002010;
+parameter val_usb0__HWTXBUF = 32'h80060A10;
+parameter mask_usb0__HWTXBUF = 32'hFFFFFFFF;
+
+parameter usb0__HWRXBUF = 32'hE0002014;
+parameter val_usb0__HWRXBUF = 32'h00000A10;
+parameter mask_usb0__HWRXBUF = 32'hFF00FFFF;
+
+parameter usb0__GPTIMER0LD = 32'hE0002080;
+parameter val_usb0__GPTIMER0LD = 32'h00000000;
+parameter mask_usb0__GPTIMER0LD = 32'h00FFFFFF;
+
+parameter usb0__GPTIMER0CTRL = 32'hE0002084;
+parameter val_usb0__GPTIMER0CTRL = 32'h00000000;
+parameter mask_usb0__GPTIMER0CTRL = 32'hFFFFFFFF;
+
+parameter usb0__GPTIMER1LD = 32'hE0002088;
+parameter val_usb0__GPTIMER1LD = 32'h00000000;
+parameter mask_usb0__GPTIMER1LD = 32'h00FFFFFF;
+
+parameter usb0__GPTIMER1CTRL = 32'hE000208C;
+parameter val_usb0__GPTIMER1CTRL = 32'h00000000;
+parameter mask_usb0__GPTIMER1CTRL = 32'hFFFFFFFF;
+
+parameter usb0__SBUSCFG = 32'hE0002090;
+parameter val_usb0__SBUSCFG = 32'h00000003;
+parameter mask_usb0__SBUSCFG = 32'h00000007;
+
+parameter usb0__CAPLENGTH_HCIVERSION = 32'hE0002100;
+parameter val_usb0__CAPLENGTH_HCIVERSION = 32'h01000040;
+parameter mask_usb0__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF;
+
+parameter usb0__HCSPARAMS = 32'hE0002104;
+parameter val_usb0__HCSPARAMS = 32'h00010011;
+parameter mask_usb0__HCSPARAMS = 32'h0FFFFFFF;
+
+parameter usb0__HCCPARAMS = 32'hE0002108;
+parameter val_usb0__HCCPARAMS = 32'h00000006;
+parameter mask_usb0__HCCPARAMS = 32'h0000FFFF;
+
+parameter usb0__DCIVERSION = 32'hE0002120;
+parameter val_usb0__DCIVERSION = 32'h00000001;
+parameter mask_usb0__DCIVERSION = 32'h0000FFFF;
+
+parameter usb0__DCCPARAMS = 32'hE0002124;
+parameter val_usb0__DCCPARAMS = 32'h0000018C;
+parameter mask_usb0__DCCPARAMS = 32'h000001FF;
+
+parameter usb0__USBCMD = 32'hE0002140;
+parameter val_usb0__USBCMD = 32'h00000B00;
+parameter mask_usb0__USBCMD = 32'h00FFFFFF;
+
+parameter usb0__USBSTS = 32'hE0002144;
+parameter val_usb0__USBSTS = 32'h00000000;
+parameter mask_usb0__USBSTS = 32'h03FFFFFF;
+
+parameter usb0__USBINTR = 32'hE0002148;
+parameter val_usb0__USBINTR = 32'h00000000;
+parameter mask_usb0__USBINTR = 32'h03FF0FFF;
+
+parameter usb0__FRINDEX = 32'hE000214C;
+parameter val_usb0__FRINDEX = 32'h00000000;
+parameter mask_usb0__FRINDEX = 32'h00003FFF;
+
+parameter usb0__PERIODICLISTBASE_DEVICEADDR = 32'hE0002154;
+parameter val_usb0__PERIODICLISTBASE_DEVICEADDR = 32'h00000000;
+parameter mask_usb0__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF;
+
+parameter usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0002158;
+parameter val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000;
+parameter mask_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF;
+
+parameter usb0__TTCTRL = 32'hE000215C;
+parameter val_usb0__TTCTRL = 32'h00000000;
+parameter mask_usb0__TTCTRL = 32'hFFFFFFFF;
+
+parameter usb0__BURSTSIZE = 32'hE0002160;
+parameter val_usb0__BURSTSIZE = 32'h00001010;
+parameter mask_usb0__BURSTSIZE = 32'h0001FFFF;
+
+parameter usb0__TXFILLTUNING = 32'hE0002164;
+parameter val_usb0__TXFILLTUNING = 32'h00020000;
+parameter mask_usb0__TXFILLTUNING = 32'h003FFFFF;
+
+parameter usb0__TXTTFILLTUNING = 32'hE0002168;
+parameter val_usb0__TXTTFILLTUNING = 32'h00000000;
+parameter mask_usb0__TXTTFILLTUNING = 32'h00001FFF;
+
+parameter usb0__IC_USB = 32'hE000216C;
+parameter val_usb0__IC_USB = 32'h00000000;
+parameter mask_usb0__IC_USB = 32'hFFFFFFFF;
+
+parameter usb0__ULPI_VIEWPORT = 32'hE0002170;
+parameter val_usb0__ULPI_VIEWPORT = 32'h00000000;
+parameter mask_usb0__ULPI_VIEWPORT = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTNAK = 32'hE0002178;
+parameter val_usb0__ENDPTNAK = 32'h00000000;
+parameter mask_usb0__ENDPTNAK = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTNAKEN = 32'hE000217C;
+parameter val_usb0__ENDPTNAKEN = 32'h00000000;
+parameter mask_usb0__ENDPTNAKEN = 32'hFFFFFFFF;
+
+parameter usb0__CONFIGFLAG = 32'hE0002180;
+parameter val_usb0__CONFIGFLAG = 32'h00000001;
+parameter mask_usb0__CONFIGFLAG = 32'hFFFFFFFF;
+
+parameter usb0__PORTSC1 = 32'hE0002184;
+parameter val_usb0__PORTSC1 = 32'h00000000;
+parameter mask_usb0__PORTSC1 = 32'hFFFFFFFF;
+
+parameter usb0__OTGSC = 32'hE00021A4;
+parameter val_usb0__OTGSC = 32'h00000020;
+parameter mask_usb0__OTGSC = 32'hFFFFFFFF;
+
+parameter usb0__USBMODE = 32'hE00021A8;
+parameter val_usb0__USBMODE = 32'h00000000;
+parameter mask_usb0__USBMODE = 32'h0000FFFF;
+
+parameter usb0__ENDPTSETUPSTAT = 32'hE00021AC;
+parameter val_usb0__ENDPTSETUPSTAT = 32'h00000000;
+parameter mask_usb0__ENDPTSETUPSTAT = 32'h0000FFFF;
+
+parameter usb0__ENDPTPRIME = 32'hE00021B0;
+parameter val_usb0__ENDPTPRIME = 32'h00000000;
+parameter mask_usb0__ENDPTPRIME = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTFLUSH = 32'hE00021B4;
+parameter val_usb0__ENDPTFLUSH = 32'h00000000;
+parameter mask_usb0__ENDPTFLUSH = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTSTAT = 32'hE00021B8;
+parameter val_usb0__ENDPTSTAT = 32'h00000000;
+parameter mask_usb0__ENDPTSTAT = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTCOMPLETE = 32'hE00021BC;
+parameter val_usb0__ENDPTCOMPLETE = 32'h00000000;
+parameter mask_usb0__ENDPTCOMPLETE = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTCTRL0 = 32'hE00021C0;
+parameter val_usb0__ENDPTCTRL0 = 32'h00800080;
+parameter mask_usb0__ENDPTCTRL0 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL1 = 32'hE00021C4;
+parameter val_usb0__ENDPTCTRL1 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL1 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL2 = 32'hE00021C8;
+parameter val_usb0__ENDPTCTRL2 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL2 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL3 = 32'hE00021CC;
+parameter val_usb0__ENDPTCTRL3 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL3 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL4 = 32'hE00021D0;
+parameter val_usb0__ENDPTCTRL4 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL4 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL5 = 32'hE00021D4;
+parameter val_usb0__ENDPTCTRL5 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL5 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL6 = 32'hE00021D8;
+parameter val_usb0__ENDPTCTRL6 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL6 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL7 = 32'hE00021DC;
+parameter val_usb0__ENDPTCTRL7 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL7 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL8 = 32'hE00021E0;
+parameter val_usb0__ENDPTCTRL8 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL8 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL9 = 32'hE00021E4;
+parameter val_usb0__ENDPTCTRL9 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL9 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL10 = 32'hE00021E8;
+parameter val_usb0__ENDPTCTRL10 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL10 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL11 = 32'hE00021EC;
+parameter val_usb0__ENDPTCTRL11 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL11 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL12 = 32'hE00021F0;
+parameter val_usb0__ENDPTCTRL12 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL12 = 32'h00FFFFFF;
+
+
+// ************************************************************
+//   Module usb1 usb
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter usb1__ID = 32'hE0003000;
+parameter val_usb1__ID = 32'hE441FA05;
+parameter mask_usb1__ID = 32'hFFFFFFFF;
+
+parameter usb1__HWGENERAL = 32'hE0003004;
+parameter val_usb1__HWGENERAL = 32'h00000083;
+parameter mask_usb1__HWGENERAL = 32'h00000FFF;
+
+parameter usb1__HWHOST = 32'hE0003008;
+parameter val_usb1__HWHOST = 32'h10020001;
+parameter mask_usb1__HWHOST = 32'hFFFFFFFF;
+
+parameter usb1__HWDEVICE = 32'hE000300C;
+parameter val_usb1__HWDEVICE = 32'h00000019;
+parameter mask_usb1__HWDEVICE = 32'h0000003F;
+
+parameter usb1__HWTXBUF = 32'hE0003010;
+parameter val_usb1__HWTXBUF = 32'h80060A10;
+parameter mask_usb1__HWTXBUF = 32'hFFFFFFFF;
+
+parameter usb1__HWRXBUF = 32'hE0003014;
+parameter val_usb1__HWRXBUF = 32'h00000A10;
+parameter mask_usb1__HWRXBUF = 32'hFF00FFFF;
+
+parameter usb1__GPTIMER0LD = 32'hE0003080;
+parameter val_usb1__GPTIMER0LD = 32'h00000000;
+parameter mask_usb1__GPTIMER0LD = 32'h00FFFFFF;
+
+parameter usb1__GPTIMER0CTRL = 32'hE0003084;
+parameter val_usb1__GPTIMER0CTRL = 32'h00000000;
+parameter mask_usb1__GPTIMER0CTRL = 32'hFFFFFFFF;
+
+parameter usb1__GPTIMER1LD = 32'hE0003088;
+parameter val_usb1__GPTIMER1LD = 32'h00000000;
+parameter mask_usb1__GPTIMER1LD = 32'h00FFFFFF;
+
+parameter usb1__GPTIMER1CTRL = 32'hE000308C;
+parameter val_usb1__GPTIMER1CTRL = 32'h00000000;
+parameter mask_usb1__GPTIMER1CTRL = 32'hFFFFFFFF;
+
+parameter usb1__SBUSCFG = 32'hE0003090;
+parameter val_usb1__SBUSCFG = 32'h00000003;
+parameter mask_usb1__SBUSCFG = 32'h00000007;
+
+parameter usb1__CAPLENGTH_HCIVERSION = 32'hE0003100;
+parameter val_usb1__CAPLENGTH_HCIVERSION = 32'h01000040;
+parameter mask_usb1__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF;
+
+parameter usb1__HCSPARAMS = 32'hE0003104;
+parameter val_usb1__HCSPARAMS = 32'h00010011;
+parameter mask_usb1__HCSPARAMS = 32'h0FFFFFFF;
+
+parameter usb1__HCCPARAMS = 32'hE0003108;
+parameter val_usb1__HCCPARAMS = 32'h00000006;
+parameter mask_usb1__HCCPARAMS = 32'h0000FFFF;
+
+parameter usb1__DCIVERSION = 32'hE0003120;
+parameter val_usb1__DCIVERSION = 32'h00000001;
+parameter mask_usb1__DCIVERSION = 32'h0000FFFF;
+
+parameter usb1__DCCPARAMS = 32'hE0003124;
+parameter val_usb1__DCCPARAMS = 32'h0000018C;
+parameter mask_usb1__DCCPARAMS = 32'h000001FF;
+
+parameter usb1__USBCMD = 32'hE0003140;
+parameter val_usb1__USBCMD = 32'h00000B00;
+parameter mask_usb1__USBCMD = 32'h00FFFFFF;
+
+parameter usb1__USBSTS = 32'hE0003144;
+parameter val_usb1__USBSTS = 32'h00000000;
+parameter mask_usb1__USBSTS = 32'h03FFFFFF;
+
+parameter usb1__USBINTR = 32'hE0003148;
+parameter val_usb1__USBINTR = 32'h00000000;
+parameter mask_usb1__USBINTR = 32'h03FF0FFF;
+
+parameter usb1__FRINDEX = 32'hE000314C;
+parameter val_usb1__FRINDEX = 32'h00000000;
+parameter mask_usb1__FRINDEX = 32'h00003FFF;
+
+parameter usb1__PERIODICLISTBASE_DEVICEADDR = 32'hE0003154;
+parameter val_usb1__PERIODICLISTBASE_DEVICEADDR = 32'h00000000;
+parameter mask_usb1__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF;
+
+parameter usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0003158;
+parameter val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000;
+parameter mask_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF;
+
+parameter usb1__TTCTRL = 32'hE000315C;
+parameter val_usb1__TTCTRL = 32'h00000000;
+parameter mask_usb1__TTCTRL = 32'hFFFFFFFF;
+
+parameter usb1__BURSTSIZE = 32'hE0003160;
+parameter val_usb1__BURSTSIZE = 32'h00001010;
+parameter mask_usb1__BURSTSIZE = 32'h0001FFFF;
+
+parameter usb1__TXFILLTUNING = 32'hE0003164;
+parameter val_usb1__TXFILLTUNING = 32'h00020000;
+parameter mask_usb1__TXFILLTUNING = 32'h003FFFFF;
+
+parameter usb1__TXTTFILLTUNING = 32'hE0003168;
+parameter val_usb1__TXTTFILLTUNING = 32'h00000000;
+parameter mask_usb1__TXTTFILLTUNING = 32'h00001FFF;
+
+parameter usb1__IC_USB = 32'hE000316C;
+parameter val_usb1__IC_USB = 32'h00000000;
+parameter mask_usb1__IC_USB = 32'hFFFFFFFF;
+
+parameter usb1__ULPI_VIEWPORT = 32'hE0003170;
+parameter val_usb1__ULPI_VIEWPORT = 32'h00000000;
+parameter mask_usb1__ULPI_VIEWPORT = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTNAK = 32'hE0003178;
+parameter val_usb1__ENDPTNAK = 32'h00000000;
+parameter mask_usb1__ENDPTNAK = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTNAKEN = 32'hE000317C;
+parameter val_usb1__ENDPTNAKEN = 32'h00000000;
+parameter mask_usb1__ENDPTNAKEN = 32'hFFFFFFFF;
+
+parameter usb1__CONFIGFLAG = 32'hE0003180;
+parameter val_usb1__CONFIGFLAG = 32'h00000001;
+parameter mask_usb1__CONFIGFLAG = 32'hFFFFFFFF;
+
+parameter usb1__PORTSC1 = 32'hE0003184;
+parameter val_usb1__PORTSC1 = 32'h00000000;
+parameter mask_usb1__PORTSC1 = 32'hFFFFFFFF;
+
+parameter usb1__OTGSC = 32'hE00031A4;
+parameter val_usb1__OTGSC = 32'h00000020;
+parameter mask_usb1__OTGSC = 32'hFFFFFFFF;
+
+parameter usb1__USBMODE = 32'hE00031A8;
+parameter val_usb1__USBMODE = 32'h00000000;
+parameter mask_usb1__USBMODE = 32'h0000FFFF;
+
+parameter usb1__ENDPTSETUPSTAT = 32'hE00031AC;
+parameter val_usb1__ENDPTSETUPSTAT = 32'h00000000;
+parameter mask_usb1__ENDPTSETUPSTAT = 32'h0000FFFF;
+
+parameter usb1__ENDPTPRIME = 32'hE00031B0;
+parameter val_usb1__ENDPTPRIME = 32'h00000000;
+parameter mask_usb1__ENDPTPRIME = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTFLUSH = 32'hE00031B4;
+parameter val_usb1__ENDPTFLUSH = 32'h00000000;
+parameter mask_usb1__ENDPTFLUSH = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTSTAT = 32'hE00031B8;
+parameter val_usb1__ENDPTSTAT = 32'h00000000;
+parameter mask_usb1__ENDPTSTAT = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTCOMPLETE = 32'hE00031BC;
+parameter val_usb1__ENDPTCOMPLETE = 32'h00000000;
+parameter mask_usb1__ENDPTCOMPLETE = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTCTRL0 = 32'hE00031C0;
+parameter val_usb1__ENDPTCTRL0 = 32'h00800080;
+parameter mask_usb1__ENDPTCTRL0 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL1 = 32'hE00031C4;
+parameter val_usb1__ENDPTCTRL1 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL1 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL2 = 32'hE00031C8;
+parameter val_usb1__ENDPTCTRL2 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL2 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL3 = 32'hE00031CC;
+parameter val_usb1__ENDPTCTRL3 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL3 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL4 = 32'hE00031D0;
+parameter val_usb1__ENDPTCTRL4 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL4 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL5 = 32'hE00031D4;
+parameter val_usb1__ENDPTCTRL5 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL5 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL6 = 32'hE00031D8;
+parameter val_usb1__ENDPTCTRL6 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL6 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL7 = 32'hE00031DC;
+parameter val_usb1__ENDPTCTRL7 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL7 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL8 = 32'hE00031E0;
+parameter val_usb1__ENDPTCTRL8 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL8 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL9 = 32'hE00031E4;
+parameter val_usb1__ENDPTCTRL9 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL9 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL10 = 32'hE00031E8;
+parameter val_usb1__ENDPTCTRL10 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL10 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL11 = 32'hE00031EC;
+parameter val_usb1__ENDPTCTRL11 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL11 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL12 = 32'hE00031F0;
+parameter val_usb1__ENDPTCTRL12 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL12 = 32'h00FFFFFF;
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Wed Feb 01 18:22:40 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, 
+  I2C0_SCL_O, I2C0_SCL_T, SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, 
+  TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, 
+  M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, 
+  M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, 
+  M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, 
+  DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, 
+  DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin=""I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"" */;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input SDIO0_WP;
+  output UART0_TX;
+  input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output FCLK_CLK0;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:11:41 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, 
+  I2C0_SCL_O, I2C0_SCL_T, SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, 
+  TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, 
+  M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, 
+  M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, 
+  M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, 
+  DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, 
+  DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin=""I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"" */;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input SDIO0_WP;
+  output UART0_TX;
+  input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output FCLK_CLK0;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:01 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top design_1_axi_gpio_0_0 -prefix
+//               design_1_axi_gpio_0_0_ design_1_axi_gpio_0_0_stub.v
+// Design      : design_1_axi_gpio_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_gpio,Vivado 2016.4"" *)
+module design_1_axi_gpio_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio2_io_i)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio2_io_i[3:0]"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [3:0]gpio_io_i;
+  input [3:0]gpio2_io_i;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:53:58 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_100M_0_stub.v
+// Design      : design_1_rst_ps7_0_100M_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""proc_sys_reset,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in, 
+  mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset, 
+  interconnect_aresetn, peripheral_aresetn)
+/* synthesis syn_black_box black_box_pad_pin=""slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]"" */;
+  input slowest_sync_clk;
+  input ext_reset_in;
+  input aux_reset_in;
+  input mb_debug_sys_rst;
+  input dcm_locked;
+  output mb_reset;
+  output [0:0]bus_struct_reset;
+  output [0:0]peripheral_reset;
+  output [0:0]interconnect_aresetn;
+  output [0:0]peripheral_aresetn;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:25 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (SDIO0_WP,
+    UART0_TX,
+    UART0_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    FCLK_CLK0,
+    FCLK_RESET0_N,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *) input SDIO0_WP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 TxD"" *) output UART0_TX;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 RxD"" *) input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *) output [1:0]USB0_PORT_INDCTL;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *) output USB0_VBUS_PWRSELECT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *) input USB0_VBUS_PWRFAULT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *) output M_AXI_GP0_ARVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *) output M_AXI_GP0_AWVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *) output M_AXI_GP0_BREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *) output M_AXI_GP0_RREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *) output M_AXI_GP0_WLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *) output M_AXI_GP0_WVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *) output [11:0]M_AXI_GP0_ARID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *) output [11:0]M_AXI_GP0_AWID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *) output [11:0]M_AXI_GP0_WID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *) output [1:0]M_AXI_GP0_ARBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *) output [1:0]M_AXI_GP0_ARLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *) output [2:0]M_AXI_GP0_ARSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *) output [1:0]M_AXI_GP0_AWBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *) output [1:0]M_AXI_GP0_AWLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *) output [2:0]M_AXI_GP0_AWSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *) output [2:0]M_AXI_GP0_ARPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *) output [2:0]M_AXI_GP0_AWPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *) output [31:0]M_AXI_GP0_ARADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *) output [31:0]M_AXI_GP0_AWADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *) output [31:0]M_AXI_GP0_WDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *) output [3:0]M_AXI_GP0_ARCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *) output [3:0]M_AXI_GP0_ARLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *) output [3:0]M_AXI_GP0_ARQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *) output [3:0]M_AXI_GP0_AWCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *) output [3:0]M_AXI_GP0_AWLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *) output [3:0]M_AXI_GP0_AWQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *) output [3:0]M_AXI_GP0_WSTRB;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *) input M_AXI_GP0_ACLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *) input M_AXI_GP0_ARREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *) input M_AXI_GP0_AWREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *) input M_AXI_GP0_BVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *) input M_AXI_GP0_RLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *) input M_AXI_GP0_RVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *) input M_AXI_GP0_WREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *) input [11:0]M_AXI_GP0_BID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *) input [11:0]M_AXI_GP0_RID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *) input [1:0]M_AXI_GP0_BRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *) input [1:0]M_AXI_GP0_RRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *) input [31:0]M_AXI_GP0_RDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *) output FCLK_CLK0;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *) output FCLK_RESET0_N;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *) inout [53:0]MIO;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *) inout DDR_CAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *) inout DDR_CKE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *) inout DDR_Clk_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *) inout DDR_Clk;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *) inout DDR_CS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *) inout DDR_DRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *) inout DDR_ODT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *) inout DDR_RAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *) inout DDR_WEB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *) inout [2:0]DDR_BankAddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *) inout [14:0]DDR_Addr;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *) inout DDR_VRN;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *) inout DDR_VRP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *) inout [3:0]DDR_DM;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *) inout [31:0]DDR_DQ;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *) inout [3:0]DDR_DQS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *) inout [3:0]DDR_DQS;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *) inout PS_SRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *) inout PS_CLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *) inout PS_PORB;
+
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire FCLK_CLK0;
+  wire FCLK_RESET0_N;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [2:0]M_AXI_GP0_ARSIZE;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [2:0]M_AXI_GP0_AWSIZE;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_WP;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+  wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+  wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+  wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+  wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+  wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+  wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO0_LED_UNCONNECTED;
+  wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO1_LED_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+  wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+  wire NLW_inst_TRACE_CTL_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+  wire NLW_inst_UART0_DTRN_UNCONNECTED;
+  wire NLW_inst_UART0_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_DTRN_UNCONNECTED;
+  wire NLW_inst_UART1_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_TX_UNCONNECTED;
+  wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+  wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+  wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+  wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+  wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+PULLUP pullup_MIO_0
+       (.O(MIO[0]));
+PULLUP pullup_MIO_9
+       (.O(MIO[9]));
+PULLUP pullup_MIO_10
+       (.O(MIO[10]));
+PULLUP pullup_MIO_11
+       (.O(MIO[11]));
+PULLUP pullup_MIO_12
+       (.O(MIO[12]));
+PULLUP pullup_MIO_13
+       (.O(MIO[13]));
+PULLUP pullup_MIO_14
+       (.O(MIO[14]));
+PULLUP pullup_MIO_15
+       (.O(MIO[15]));
+PULLUP pullup_MIO_46
+       (.O(MIO[46]));
+
+  (* C_DM_WIDTH = ""4"" *) 
+  (* C_DQS_WIDTH = ""4"" *) 
+  (* C_DQ_WIDTH = ""32"" *) 
+  (* C_EMIO_GPIO_WIDTH = ""64"" *) 
+  (* C_EN_EMIO_ENET0 = ""0"" *) 
+  (* C_EN_EMIO_ENET1 = ""0"" *) 
+  (* C_EN_EMIO_PJTAG = ""0"" *) 
+  (* C_EN_EMIO_TRACE = ""0"" *) 
+  (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+  (* C_FCLK_CLK1_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK2_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+  (* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+  (* C_INCLUDE_TRACE_BUFFER = ""0"" *) 
+  (* C_IRQ_F2P_MODE = ""DIRECT"" *) 
+  (* C_MIO_PRIMITIVE = ""54"" *) 
+  (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_NUM_F2P_INTR_INPUTS = ""1"" *) 
+  (* C_PACKAGE_NAME = ""clg400"" *) 
+  (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+  (* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+  (* C_S_AXI_GP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP3_ID_WIDTH = ""6"" *) 
+  (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) 
+  (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+  (* C_TRACE_INTERNAL_WIDTH = ""2"" *) 
+  (* C_TRACE_PIPELINE_WIDTH = ""8"" *) 
+  (* C_USE_AXI_NONSECURE = ""0"" *) 
+  (* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) 
+  (* C_USE_M_AXI_GP0 = ""1"" *) 
+  (* C_USE_M_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_ACP = ""0"" *) 
+  (* C_USE_S_AXI_GP0 = ""0"" *) 
+  (* C_USE_S_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP0 = ""0"" *) 
+  (* C_USE_S_AXI_HP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP2 = ""0"" *) 
+  (* C_USE_S_AXI_HP3 = ""0"" *) 
+  (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) 
+  (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+  (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
+       (.CAN0_PHY_RX(1\'b0),
+        .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+        .CAN1_PHY_RX(1\'b0),
+        .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+        .Core0_nFIQ(1\'b0),
+        .Core0_nIRQ(1\'b0),
+        .Core1_nFIQ(1\'b0),
+        .Core1_nIRQ(1\'b0),
+        .DDR_ARB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .DDR_Addr(DDR_Addr),
+        .DDR_BankAddr(DDR_BankAddr),
+        .DDR_CAS_n(DDR_CAS_n),
+        .DDR_CKE(DDR_CKE),
+        .DDR_CS_n(DDR_CS_n),
+        .DDR_Clk(DDR_Clk),
+        .DDR_Clk_n(DDR_Clk_n),
+        .DDR_DM(DDR_DM),
+        .DDR_DQ(DDR_DQ),
+        .DDR_DQS(DDR_DQS),
+        .DDR_DQS_n(DDR_DQS_n),
+        .DDR_DRSTB(DDR_DRSTB),
+        .DDR_ODT(DDR_ODT),
+        .DDR_RAS_n(DDR_RAS_n),
+        .DDR_VRN(DDR_VRN),
+        .DDR_VRP(DDR_VRP),
+        .DDR_WEB(DDR_WEB),
+        .DMA0_ACLK(1\'b0),
+        .DMA0_DAREADY(1\'b0),
+        .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+        .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+        .DMA0_DRLAST(1\'b0),
+        .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+        .DMA0_DRTYPE({1\'b0,1\'b0}),
+        .DMA0_DRVALID(1\'b0),
+        .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+        .DMA1_ACLK(1\'b0),
+        .DMA1_DAREADY(1\'b0),
+        .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+        .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+        .DMA1_DRLAST(1\'b0),
+        .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+        .DMA1_DRTYPE({1\'b0,1\'b0}),
+        .DMA1_DRVALID(1\'b0),
+        .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+        .DMA2_ACLK(1\'b0),
+        .DMA2_DAREADY(1\'b0),
+        .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+        .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+        .DMA2_DRLAST(1\'b0),
+        .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+        .DMA2_DRTYPE({1\'b0,1\'b0}),
+        .DMA2_DRVALID(1\'b0),
+        .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+        .DMA3_ACLK(1\'b0),
+        .DMA3_DAREADY(1\'b0),
+        .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+        .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+        .DMA3_DRLAST(1\'b0),
+        .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+        .DMA3_DRTYPE({1\'b0,1\'b0}),
+        .DMA3_DRVALID(1\'b0),
+        .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+        .ENET0_EXT_INTIN(1\'b0),
+        .ENET0_GMII_COL(1\'b0),
+        .ENET0_GMII_CRS(1\'b0),
+        .ENET0_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET0_GMII_RX_CLK(1\'b0),
+        .ENET0_GMII_RX_DV(1\'b0),
+        .ENET0_GMII_RX_ER(1\'b0),
+        .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET0_GMII_TX_CLK(1\'b0),
+        .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+        .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+        .ENET0_MDIO_I(1\'b0),
+        .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+        .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+        .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+        .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+        .ENET1_EXT_INTIN(1\'b0),
+        .ENET1_GMII_COL(1\'b0),
+        .ENET1_GMII_CRS(1\'b0),
+        .ENET1_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET1_GMII_RX_CLK(1\'b0),
+        .ENET1_GMII_RX_DV(1\'b0),
+        .ENET1_GMII_RX_ER(1\'b0),
+        .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET1_GMII_TX_CLK(1\'b0),
+        .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+        .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+        .ENET1_MDIO_I(1\'b0),
+        .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+        .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+        .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+        .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+        .EVENT_EVENTI(1\'b0),
+        .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+        .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+        .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+        .FCLK_CLK0(FCLK_CLK0),
+        .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+        .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+        .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+        .FCLK_CLKTRIG0_N(1\'b0),
+        .FCLK_CLKTRIG1_N(1\'b0),
+        .FCLK_CLKTRIG2_N(1\'b0),
+        .FCLK_CLKTRIG3_N(1\'b0),
+        .FCLK_RESET0_N(FCLK_RESET0_N),
+        .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+        .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+        .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+        .FPGA_IDLE_N(1\'b0),
+        .FTMD_TRACEIN_ATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_CLK(1\'b0),
+        .FTMD_TRACEIN_DATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_VALID(1\'b0),
+        .FTMT_F2P_DEBUG({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+        .FTMT_F2P_TRIG_0(1\'b0),
+        .FTMT_F2P_TRIG_1(1\'b0),
+        .FTMT_F2P_TRIG_2(1\'b0),
+        .FTMT_F2P_TRIG_3(1\'b0),
+        .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+        .FTMT_P2F_TRIGACK_0(1\'b0),
+        .FTMT_P2F_TRIGACK_1(1\'b0),
+        .FTMT_P2F_TRIGACK_2(1\'b0),
+        .FTMT_P2F_TRIGACK_3(1\'b0),
+        .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+        .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+        .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+        .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+        .GPIO_I({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
+        .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
+        .I2C0_SCL_I(1\'b0),
+        .I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
+        .I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
+        .I2C0_SDA_I(1\'b0),
+        .I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
+        .I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
+        .I2C1_SCL_I(1\'b0),
+        .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+        .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+        .I2C1_SDA_I(1\'b0),
+        .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+        .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+        .IRQ_F2P(1\'b0),
+        .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+        .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+        .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+        .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+        .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+        .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+        .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+        .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+        .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+        .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+        .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+        .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+        .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+        .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+        .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+        .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+        .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+        .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+        .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+        .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+        .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+        .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+        .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+        .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+        .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+        .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+        .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+        .MIO(MIO),
+        .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+        .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+        .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+        .M_AXI_GP1_ACLK(1\'b0),
+        .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+        .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARREADY(1\'b0),
+        .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+        .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWREADY(1\'b0),
+        .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+        .M_AXI_GP1_BID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+        .M_AXI_GP1_BRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_BVALID(1\'b0),
+        .M_AXI_GP1_RDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RLAST(1\'b0),
+        .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+        .M_AXI_GP1_RRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_RVALID(1\'b0),
+        .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+        .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+        .M_AXI_GP1_WREADY(1\'b0),
+        .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+        .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+        .PJTAG_TCK(1\'b0),
+        .PJTAG_TDI(1\'b0),
+        .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+        .PJTAG_TMS(1\'b0),
+        .PS_CLK(PS_CLK),
+        .PS_PORB(PS_PORB),
+        .PS_SRSTB(PS_SRSTB),
+        .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+        .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO0_CDN(1\'b0),
+        .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+        .SDIO0_CLK_FB(1\'b0),
+        .SDIO0_CMD_I(1\'b0),
+        .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+        .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+        .SDIO0_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+        .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+        .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+        .SDIO0_WP(SDIO0_WP),
+        .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+        .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO1_CDN(1\'b0),
+        .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+        .SDIO1_CLK_FB(1\'b0),
+        .SDIO1_CMD_I(1\'b0),
+        .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+        .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+        .SDIO1_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+        .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+        .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+        .SDIO1_WP(1\'b0),
+        .SPI0_MISO_I(1\'b0),
+        .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+        .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+        .SPI0_MOSI_I(1\'b0),
+        .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+        .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+        .SPI0_SCLK_I(1\'b0),
+        .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+        .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+        .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+        .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+        .SPI0_SS_I(1\'b0),
+        .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+        .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+        .SPI1_MISO_I(1\'b0),
+        .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+        .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+        .SPI1_MOSI_I(1\'b0),
+        .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+        .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+        .SPI1_SCLK_I(1\'b0),
+        .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+        .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+        .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+        .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+        .SPI1_SS_I(1\'b0),
+        .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+        .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+        .SRAM_INTIN(1\'b0),
+        .S_AXI_ACP_ACLK(1\'b0),
+        .S_AXI_ACP_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+        .S_AXI_ACP_ARID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+        .S_AXI_ACP_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARVALID(1\'b0),
+        .S_AXI_ACP_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+        .S_AXI_ACP_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWVALID(1\'b0),
+        .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_BREADY(1\'b0),
+        .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+        .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+        .S_AXI_ACP_RREADY(1\'b0),
+        .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+        .S_AXI_ACP_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WLAST(1\'b0),
+        .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+        .S_AXI_ACP_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WVALID(1\'b0),
+        .S_AXI_GP0_ACLK(1\'b0),
+        .S_AXI_GP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+        .S_AXI_GP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+        .S_AXI_GP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARVALID(1\'b0),
+        .S_AXI_GP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+        .S_AXI_GP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWVALID(1\'b0),
+        .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_BREADY(1\'b0),
+        .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+        .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+        .S_AXI_GP0_RREADY(1\'b0),
+        .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+        .S_AXI_GP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WLAST(1\'b0),
+        .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+        .S_AXI_GP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WVALID(1\'b0),
+        .S_AXI_GP1_ACLK(1\'b0),
+        .S_AXI_GP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+        .S_AXI_GP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+        .S_AXI_GP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARVALID(1\'b0),
+        .S_AXI_GP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+        .S_AXI_GP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWVALID(1\'b0),
+        .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_BREADY(1\'b0),
+        .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+        .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+        .S_AXI_GP1_RREADY(1\'b0),
+        .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+        .S_AXI_GP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WLAST(1\'b0),
+        .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+        .S_AXI_GP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WVALID(1\'b0),
+        .S_AXI_HP0_ACLK(1\'b0),
+        .S_AXI_HP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+        .S_AXI_HP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+        .S_AXI_HP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARVALID(1\'b0),
+        .S_AXI_HP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+        .S_AXI_HP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWVALID(1\'b0),
+        .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_BREADY(1\'b0),
+        .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+        .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP0_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+        .S_AXI_HP0_RREADY(1\'b0),
+        .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+        .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WLAST(1\'b0),
+        .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+        .S_AXI_HP0_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WVALID(1\'b0),
+        .S_AXI_HP1_ACLK(1\'b0),
+        .S_AXI_HP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+        .S_AXI_HP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+        .S_AXI_HP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARVALID(1\'b0),
+        .S_AXI_HP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+        .S_AXI_HP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWVALID(1\'b0),
+        .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_BREADY(1\'b0),
+        .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+        .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP1_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+        .S_AXI_HP1_RREADY(1\'b0),
+        .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+        .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WLAST(1\'b0),
+        .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+        .S_AXI_HP1_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WVALID(1\'b0),
+        .S_AXI_HP2_ACLK(1\'b0),
+        .S_AXI_HP2_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+        .S_AXI_HP2_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+        .S_AXI_HP2_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARVALID(1\'b0),
+        .S_AXI_HP2_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+        .S_AXI_HP2_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWVALID(1\'b0),
+        .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_BREADY(1\'b0),
+        .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+        .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP2_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+        .S_AXI_HP2_RREADY(1\'b0),
+        .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+        .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WLAST(1\'b0),
+        .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+        .S_AXI_HP2_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WVALID(1\'b0),
+        .S_AXI_HP3_ACLK(1\'b0),
+        .S_AXI_HP3_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+        .S_AXI_HP3_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+        .S_AXI_HP3_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARVALID(1\'b0),
+        .S_AXI_HP3_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+        .S_AXI_HP3_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWVALID(1\'b0),
+        .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_BREADY(1\'b0),
+        .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+        .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP3_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+        .S_AXI_HP3_RREADY(1\'b0),
+        .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+        .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WLAST(1\'b0),
+        .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
+        .S_AXI_HP3_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WVALID(1\'b0),
+        .TRACE_CLK(1\'b0),
+        .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+        .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
+        .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+        .TTC0_CLK0_IN(1\'b0),
+        .TTC0_CLK1_IN(1\'b0),
+        .TTC0_CLK2_IN(1\'b0),
+        .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+        .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+        .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+        .TTC1_CLK0_IN(1\'b0),
+        .TTC1_CLK1_IN(1\'b0),
+        .TTC1_CLK2_IN(1\'b0),
+        .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+        .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+        .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+        .UART0_CTSN(1\'b0),
+        .UART0_DCDN(1\'b0),
+        .UART0_DSRN(1\'b0),
+        .UART0_DTRN(NLW_inst_UART0_DTRN'b'_UNCONNECTED),
+        .UART0_RIN(1\'b0),
+        .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
+        .UART0_RX(UART0_RX),
+        .UART0_TX(UART0_TX),
+        .UART1_CTSN(1\'b0),
+        .UART1_DCDN(1\'b0),
+        .UART1_DSRN(1\'b0),
+        .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+        .UART1_RIN(1\'b0),
+        .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+        .UART1_RX(1\'b1),
+        .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+        .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+        .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+        .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+        .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+        .USB1_VBUS_PWRFAULT(1\'b0),
+        .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+        .WDT_CLK_IN(1\'b0),
+        .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = ""4"" *) (* C_DQS_WIDTH = ""4"" *) (* C_DQ_WIDTH = ""32"" *) 
+(* C_EMIO_GPIO_WIDTH = ""64"" *) (* C_EN_EMIO_ENET0 = ""0"" *) (* C_EN_EMIO_ENET1 = ""0"" *) 
+(* C_EN_EMIO_PJTAG = ""0"" *) (* C_EN_EMIO_TRACE = ""0"" *) (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+(* C_FCLK_CLK1_BUF = ""FALSE"" *) (* C_FCLK_CLK2_BUF = ""FALSE"" *) (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+(* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+(* C_INCLUDE_TRACE_BUFFER = ""0"" *) (* C_IRQ_F2P_MODE = ""DIRECT"" *) (* C_MIO_PRIMITIVE = ""54"" *) 
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+(* C_NUM_F2P_INTR_INPUTS = ""1"" *) (* C_PACKAGE_NAME = ""clg400"" *) (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+(* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+(* C_S_AXI_GP0_ID_WIDTH = ""6"" *) (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP0_ID_WIDTH = ""6"" *) (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+(* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP3_ID_WIDTH = ""6"" *) (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+(* C_TRACE_INTERNAL_WIDTH = ""2"" *) (* C_TRACE_PIPELINE_WIDTH = ""8"" *) (* C_USE_AXI_NONSECURE = ""0"" *) 
+(* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) (* C_USE_M_AXI_GP0 = ""1"" *) (* C_USE_M_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_ACP = ""0"" *) (* C_USE_S_AXI_GP0 = ""0"" *) (* C_USE_S_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_HP0 = ""0"" *) (* C_USE_S_AXI_HP1 = ""0"" *) (* C_USE_S_AXI_HP2 = ""0"" *) 
+(* C_USE_S_AXI_HP3 = ""0"" *) (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+(* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
+   (CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TDI,
+    PJTAG_TDO,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    TRACE_CLK_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_PORT_INDCTL,
+    USB1_VBUS_PWRSELECT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARESETN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARESETN,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARESETN,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARESETN,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_ARESETN,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARESETN,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARESETN,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARESETN,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARESETN,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_RSTN,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_RSTN,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_RSTN,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_RSTN,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA3_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DRTYPE,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG_0,
+    FTMT_F2P_TRIGACK_0,
+    FTMT_F2P_TRIG_1,
+    FTMT_F2P_TRIGACK_1,
+    FTMT_F2P_TRIG_2,
+    FTMT_F2P_TRIGACK_2,
+    FTMT_F2P_TRIG_3,
+    FTMT_F2P_TRIGACK_3,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK_0,
+    FTMT_P2F_TRIG_0,
+    FTMT_P2F_TRIGACK_1,
+    FTMT_P2F_TRIG_1,
+    FTMT_P2F_TRIGACK_2,
+    FTMT_P2F_TRIG_2,
+    FTMT_P2F_TRIGACK_3,
+    FTMT_P2F_TRIG_3,
+    FTMT_P2F_DEBUG,
+    FPGA_IDLE_N,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    DDR_ARB,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0]ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input ENET0_EXT_INTIN;
+  input [7:0]ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0]ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input ENET1_EXT_INTIN;
+  input [7:0]ENET1_GMII_RXD;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TDI;
+  output PJTAG_TDO;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0]SDIO0_DATA_I;
+  output [3:0]SDIO0_DATA_O;
+  output [3:0]SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0]SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0]SDIO1_DATA_I;
+  output [3:0]SDIO1_DATA_O;
+  output [3:0]SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0]SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [1:0]TRACE_DATA;
+  output TRACE_CLK_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output [1:0]USB1_PORT_INDCTL;
+  output USB1_VBUS_PWRSELECT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARESETN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARESETN;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [11:0]M_AXI_GP1_ARID;
+  output [11:0]M_AXI_GP1_AWID;
+  output [11:0]M_AXI_GP1_WID;
+  output [1:0]M_AXI_GP1_ARBURST;
+  output [1:0]M_AXI_GP1_ARLOCK;
+  output [2:0]M_AXI_GP1_ARSIZE;
+  output [1:0]M_AXI_GP1_AWBURST;
+  output [1:0]M_AXI_GP1_AWLOCK;
+  output [2:0]M_AXI_GP1_AWSIZE;
+  output [2:0]M_AXI_GP1_ARPROT;
+  output [2:0]M_AXI_GP1_AWPROT;
+  output [31:0]M_AXI_GP1_ARADDR;
+  output [31:0]M_AXI_GP1_AWADDR;
+  output [31:0]M_AXI_GP1_WDATA;
+  output [3:0]M_AXI_GP1_ARCACHE;
+  output [3:0]M_AXI_GP1_ARLEN;
+  output [3:0]M_AXI_GP1_ARQOS;
+  output [3:0]M_AXI_GP1_AWCACHE;
+  output [3:0]M_AXI_GP1_AWLEN;
+  output [3:0]M_AXI_GP1_AWQOS;
+  output [3:0]M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [11:0]M_AXI_GP1_BID;
+  input [11:0]M_AXI_GP1_RID;
+  input [1:0]M_AXI_GP1_BRESP;
+  input [1:0]M_AXI_GP1_RRESP;
+  input [31:0]M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARESETN;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0]S_AXI_GP0_BRESP;
+  output [1:0]S_AXI_GP0_RRESP;
+  output [31:0]S_AXI_GP0_RDATA;
+  output [5:0]S_AXI_GP0_BID;
+  output [5:0]S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0]S_AXI_GP0_ARBURST;
+  input [1:0]S_AXI_GP0_ARLOCK;
+  input [2:0]S_AXI_GP0_ARSIZE;
+  input [1:0]S_AXI_GP0_AWBURST;
+  input [1:0]S_AXI_GP0_AWLOCK;
+  input [2:0]S_AXI_GP0_AWSIZE;
+  input [2:0]S_AXI_GP0_ARPROT;
+  input [2:0]S_AXI_GP0_AWPROT;
+  input [31:0]S_AXI_GP0_ARADDR;
+  input [31:0]S_AXI_GP0_AWADDR;
+  input [31:0]S_AXI_GP0_WDATA;
+  input [3:0]S_AXI_GP0_ARCACHE;
+  input [3:0]S_AXI_GP0_ARLEN;
+  input [3:0]S_AXI_GP0_ARQOS;
+  input [3:0]S_AXI_GP0_AWCACHE;
+  input [3:0]S_AXI_GP0_AWLEN;
+  input [3:0]S_AXI_GP0_AWQOS;
+  input [3:0]S_AXI_GP0_WSTRB;
+  input [5:0]S_AXI_GP0_ARID;
+  input [5:0]S_AXI_GP0_AWID;
+  input [5:0]S_AXI_GP0_WID;
+  output S_AXI_GP1_ARESETN;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0]S_AXI_GP1_BRESP;
+  output [1:0]S_AXI_GP1_RRESP;
+  output [31:0]S_AXI_GP1_RDATA;
+  output [5:0]S_AXI_GP1_BID;
+  output [5:0]S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0]S_AXI_GP1_ARBURST;
+  input [1:0]S_AXI_GP1_ARLOCK;
+  input [2:0]S_AXI_GP1_ARSIZE;
+  input [1:0]S_AXI_GP1_AWBURST;
+  input [1:0]S_AXI_GP1_AWLOCK;
+  input [2:0]S_AXI_GP1_AWSIZE;
+  input [2:0]S_AXI_GP1_ARPROT;
+  input [2:0]S_AXI_GP1_AWPROT;
+  input [31:0]S_AXI_GP1_ARADDR;
+  input [31:0]S_AXI_GP1_AWADDR;
+  input [31:0]S_AXI_GP1_WDATA;
+  input [3:0]S_AXI_GP1_ARCACHE;
+  input [3:0]S_AXI_GP1_ARLEN;
+  input [3:0]S_AXI_GP1_ARQOS;
+  input [3:0]S_AXI_GP1_AWCACHE;
+  input [3:0]S_AXI_GP1_AWLEN;
+  input [3:0]S_AXI_GP1_AWQOS;
+  input [3:0]S_AXI_GP1_WSTRB;
+  input [5:0]S_AXI_GP1_ARID;
+  input [5:0]S_AXI_GP1_AWID;
+  input [5:0]S_AXI_GP1_WID;
+  output S_AXI_ACP_ARESETN;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0]S_AXI_ACP_BRESP;
+  output [1:0]S_AXI_ACP_RRESP;
+  output [2:0]S_AXI_ACP_BID;
+  output [2:0]S_AXI_ACP_RID;
+  output [63:0]S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0]S_AXI_ACP_ARID;
+  input [2:0]S_AXI_ACP_ARPROT;
+  input [2:0]S_AXI_ACP_AWID;
+  input [2:0]S_AXI_ACP_AWPROT;
+  input [2:0]S_AXI_ACP_WID;
+  input [31:0]S_AXI_ACP_ARADDR;
+  input [31:0]S_AXI_ACP_AWADDR;
+  input [3:0]S_AXI_ACP_ARCACHE;
+  input [3:0]S_AXI_ACP_ARLEN;
+  input [3:0]S_AXI_ACP_ARQOS;
+  input [3:0]S_AXI_ACP_AWCACHE;
+  input [3:0]S_AXI_ACP_AWLEN;
+  input [3:0]S_AXI_ACP_AWQOS;
+  input [1:0]S_AXI_ACP_ARBURST;
+  input [1:0]S_AXI_ACP_ARLOCK;
+  input [2:0]S_AXI_ACP_ARSIZE;
+  input [1:0]S_AXI_ACP_AWBURST;
+  input [1:0]S_AXI_ACP_AWLOCK;
+  input [2:0]S_AXI_ACP_AWSIZE;
+  input [4:0]S_AXI_ACP_ARUSER;
+  input [4:0]S_AXI_ACP_AWUSER;
+  input [63:0]S_AXI_ACP_WDATA;
+  input [7:0]S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARESETN;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0]S_AXI_HP0_BRESP;
+  output [1:0]S_AXI_HP0_RRESP;
+  output [5:0]S_AXI_HP0_BID;
+  output [5:0]S_AXI_HP0_RID;
+  output [63:0]S_AXI_HP0_RDATA;
+  output [7:0]S_AXI_HP0_RCOUNT;
+  output [7:0]S_AXI_HP0_WCOUNT;
+  output [2:0]S_AXI_HP0_RACOUNT;
+  output [5:0]S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0]S_AXI_HP0_ARBURST;
+  input [1:0]S_AXI_HP0_ARLOCK;
+  input [2:0]S_AXI_HP0_ARSIZE;
+  input [1:0]S_AXI_HP0_AWBURST;
+  input [1:0]S_AXI_HP0_AWLOCK;
+  input [2:0]S_AXI_HP0_AWSIZE;
+  input [2:0]S_AXI_HP0_ARPROT;
+  input [2:0]S_AXI_HP0_AWPROT;
+  input [31:0]S_AXI_HP0_ARADDR;
+  input [31:0]S_AXI_HP0_AWADDR;
+  input [3:0]S_AXI_HP0_ARCACHE;
+  input [3:0]S_AXI_HP0_ARLEN;
+  input [3:0]S_AXI_HP0_ARQOS;
+  input [3:0]S_AXI_HP0_AWCACHE;
+  input [3:0]S_AXI_HP0_AWLEN;
+  input [3:0]S_AXI_HP0_AWQOS;
+  input [5:0]S_AXI_HP0_ARID;
+  input [5:0]S_AXI_HP0_AWID;
+  input [5:0]S_AXI_HP0_WID;
+  input [63:0]S_AXI_HP0_WDATA;
+  input [7:0]S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARESETN;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0]S_AXI_HP1_BRESP;
+  output [1:0]S_AXI_HP1_RRESP;
+  output [5:0]S_AXI_HP1_BID;
+  output [5:0]S_AXI_HP1_RID;
+  output [63:0]S_AXI_HP1_RDATA;
+  output [7:0]S_AXI_HP1_RCOUNT;
+  output [7:0]S_AXI_HP1_WCOUNT;
+  output [2:0]S_AXI_HP1_RACOUNT;
+  output [5:0]S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0]S_AXI_HP1_ARBURST;
+  input [1:0]S_AXI_HP1_ARLOCK;
+  input [2:0]S_AXI_HP1_ARSIZE;
+  input [1:0]S_AXI_HP1_AWBURST;
+  input [1:0]S_AXI_HP1_AWLOCK;
+  input [2:0]S_AXI_HP1_AWSIZE;
+  input [2:0]S_AXI_HP1_ARPROT;
+  input [2:0]S_AXI_HP1_AWPROT;
+  input [31:0]S_AXI_HP1_ARADDR;
+  input [31:0]S_AXI_HP1_AWADDR;
+  input [3:0]S_AXI_HP1_ARCACHE;
+  input [3:0]S_AXI_HP1_ARLEN;
+  input [3:0]S_AXI_HP1_ARQOS;
+  input [3:0]S_AXI_HP1_AWCACHE;
+  input [3:0]S_AXI_HP1_AWLEN;
+  input [3:0]S_AXI_HP1_AWQOS;
+  input [5:0]S_AXI_HP1_ARID;
+  input [5:0]S_AXI_HP1_AWID;
+  input [5:0]S_AXI_HP1_WID;
+  input [63:0]S_AXI_HP1_WDATA;
+  input [7:0]S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARESETN;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0]S_AXI_HP2_BRESP;
+  output [1:0]S_AXI_HP2_RRESP;
+  output [5:0]S_AXI_HP2_BID;
+  output [5:0]S_AXI_HP2_RID;
+  output [63:0]S_AXI_HP2_RDATA;
+  output [7:0]S_AXI_HP2_RCOUNT;
+  output [7:0]S_AXI_HP2_WCOUNT;
+  output [2:0]S_AXI_HP2_RACOUNT;
+  output [5:0]S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0]S_AXI_HP2_ARBURST;
+  input [1:0]S_AXI_HP2_ARLOCK;
+  input [2:0]S_AXI_HP2_ARSIZE;
+  input [1:0]S_AXI_HP2_AWBURST;
+  input [1:0]S_AXI_HP2_AWLOCK;
+  input [2:0]S_AXI_HP2_AWSIZE;
+  input [2:0]S_AXI_HP2_ARPROT;
+  input [2:0]S_AXI_HP2_AWPROT;
+  input [31:0]S_AXI_HP2_ARADDR;
+  input [31:0]S_AXI_HP2_AWADDR;
+  input [3:0]S_AXI_HP2_ARCACHE;
+  input [3:0]S_AXI_HP2_ARLEN;
+  input [3:0]S_AXI_HP2_ARQOS;
+  input [3:0]S_AXI_HP2_AWCACHE;
+  input [3:0]S_AXI_HP2_AWLEN;
+  input [3:0]S_AXI_HP2_AWQOS;
+  input [5:0]S_AXI_HP2_ARID;
+  input [5:0]S_AXI_HP2_AWID;
+  input [5:0]S_AXI_HP2_WID;
+  input [63:0]S_AXI_HP2_WDATA;
+  input [7:0]S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARESETN;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0]S_AXI_HP3_BRESP;
+  output [1:0]S_AXI_HP3_RRESP;
+  output [5:0]S_AXI_HP3_BID;
+  output [5:0]S_AXI_HP3_RID;
+  output [63:0]S_AXI_HP3_RDATA;
+  output [7:0]S_AXI_HP3_RCOUNT;
+  output [7:0]S_AXI_HP3_WCOUNT;
+  output [2:0]S_AXI_HP3_RACOUNT;
+  output [5:0]S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0]S_AXI_HP3_ARBURST;
+  input [1:0]S_AXI_HP3_ARLOCK;
+  input [2:0]S_AXI_HP3_ARSIZE;
+  input [1:0]S_AXI_HP3_AWBURST;
+  input [1:0]S_AXI_HP3_AWLOCK;
+  input [2:0]S_AXI_HP3_AWSIZE;
+  input [2:0]S_AXI_HP3_ARPROT;
+  input [2:0]S_AXI_HP3_AWPROT;
+  input [31:0]S_AXI_HP3_ARADDR;
+  input [31:0]S_AXI_HP3_AWADDR;
+  input [3:0]S_AXI_HP3_ARCACHE;
+  input [3:0]S_AXI_HP3_ARLEN;
+  input [3:0]S_AXI_HP3_ARQOS;
+  input [3:0]S_AXI_HP3_AWCACHE;
+  input [3:0]S_AXI_HP3_AWLEN;
+  input [3:0]S_AXI_HP3_AWQOS;
+  input [5:0]S_AXI_HP3_ARID;
+  input [5:0]S_AXI_HP3_AWID;
+  input [5:0]S_AXI_HP3_WID;
+  input [63:0]S_AXI_HP3_WDATA;
+  input [7:0]S_AXI_HP3_WSTRB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+  input [0:0]IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output [1:0]DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  output DMA0_RSTN;
+  output [1:0]DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  output DMA1_RSTN;
+  output [1:0]DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  output DMA2_RSTN;
+  output [1:0]DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  output DMA3_RSTN;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input DMA3_DRVALID;
+  input [1:0]DMA0_DRTYPE;
+  input [1:0]DMA1_DRTYPE;
+  input [1:0]DMA2_DRTYPE;
+  input [1:0]DMA3_DRTYPE;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input [31:0]FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0]FTMD_TRACEIN_ATID;
+  input FTMT_F2P_TRIG_0;
+  output FTMT_F2P_TRIGACK_0;
+  input FTMT_F2P_TRIG_1;
+  output FTMT_F2P_TRIGACK_1;
+  input FTMT_F2P_TRIG_2;
+  output FTMT_F2P_TRIGACK_2;
+  input FTMT_F2P_TRIG_3;
+  output FTMT_F2P_TRIGACK_3;
+  input [31:0]FTMT_F2P_DEBUG;
+  input FTMT_P2F_TRIGACK_0;
+  output FTMT_P2F_TRIG_0;
+  input FTMT_P2F_TRIGACK_1;
+  output FTMT_P2F_TRIG_1;
+  input FTMT_P2F_TRIGACK_2;
+  output FTMT_P2F_TRIG_2;
+  input FTMT_P2F_TRIGACK_3;
+  output FTMT_P2F_TRIG_3;
+  output [31:0]FTMT_P2F_DEBUG;
+  input FPGA_IDLE_N;
+  output EVENT_EVENTO;
+  output [1:0]EVENT_STANDBYWFE;
+  output [1:0]EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  input [3:0]DDR_ARB;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+
+  wire \\<const0> ;
+  wire CAN0_PHY_RX;
+  wire CAN0_PHY_TX;
+  wire CAN1_PHY_RX;
+  wire CAN1_PHY_TX;
+  wire Core0_nFIQ;
+  wire Core0_nIRQ;
+  wire Core1_nFIQ;
+  wire Core1_nIRQ;
+  wire [3:0]DDR_ARB;
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire DMA0_ACLK;
+  wire DMA0_DAREADY;
+  wire [1:0]DMA0_DATYPE;
+  wire DMA0_DAVALID;
+  wire DMA0_DRLAST;
+  wire DMA0_DRREADY;
+  wire [1:0]DMA0_DRTYPE;
+  wire DMA0_DRVALID;
+  wire DMA0_RSTN;
+  wire DMA1_ACLK;
+  wire DMA1_DAREADY;
+  wire [1:0]DMA1_DATYPE;
+  wire DMA1_DAVALID;
+  wire DMA1_DRLAST;
+  wire DMA1_DRREADY;
+  wire [1:0]DMA1_DRTYPE;
+  wire DMA1_DRVALID;
+  wire DMA1_RSTN;
+  wire DMA2_ACLK;
+  wire DMA2_DAREADY;
+  wire [1:0]DMA2_DATYPE;
+  wire DMA2_DAVALID;
+  wire DMA2_DRLAST;
+  wire DMA2_DRREADY;
+  wire [1:0]DMA2_DRTYPE;
+  wire DMA2_DRVALID;
+  wire DMA2_RSTN;
+  wire DMA3_ACLK;
+  wire DMA3_DAREADY;
+  wire [1:0]DMA3_DATYPE;
+  wire DMA3_DAVALID;
+  wire DMA3_DRLAST;
+  wire DMA3_DRREADY;
+  wire [1:0]DMA3_DRTYPE;
+  wire DMA3_DRVALID;
+  wire DMA3_RSTN;
+  wire ENET0_EXT_INTIN;
+  wire ENET0_GMII_RX_CLK;
+  wire ENET0_GMII_TX_CLK;
+  wire ENET0_MDIO_I;
+  wire ENET0_MDIO_MDC;
+  wire ENET0_MDIO_O;
+  wire ENET0_MDIO_T;
+  wire ENET0_MDIO_T_n;
+  wire ENET0_PTP_DELAY_REQ_RX;
+  wire ENET0_PTP_DELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_REQ_RX;
+  wire ENET0_PTP_PDELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_RESP_RX;
+  wire ENET0_PTP_PDELAY_RESP_TX;
+  wire ENET0_PTP_SYNC_FRAME_RX;
+  wire ENET0_PTP_SYNC_FRAME_TX;
+  wire ENET0_SOF_RX;
+  wire ENET0_SOF_TX;
+  wire ENET1_EXT_INTIN;
+  wire ENET1_GMII_RX_CLK;
+  wire ENET1_GMII_TX_CLK;
+  wire ENET1_MDIO_I;
+  wire ENET1_MDIO_MDC;
+  wire ENET1_MDIO_O;
+  wire ENET1_MDIO_T;
+  wire ENET1_MDIO_T_n;
+  wire ENET1_PTP_DELAY_REQ_RX;
+  wire ENET1_PTP_DELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_REQ_RX;
+  wire ENET1_PTP_PDELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_RESP_RX;
+  wire ENET1_PTP_PDELAY_RESP_TX;
+  wire ENET1_PTP_SYNC_FRAME_RX;
+  wire ENET1_PTP_SYNC_FRAME_TX;
+  wire ENET1_SOF_RX;
+  wire ENET1_SOF_TX;
+  wire EVENT_EVENTI;
+  wire EVENT_EVENTO;
+  wire [1:0]EVENT_STANDBYWFE;
+  wire [1:0]EVENT_STANDBYWFI;
+  wire FCLK_CLK0;
+  wire FCLK_CLK1;
+  wire FCLK_CLK2;
+  wire FCLK_CLK3;
+  wire [0:0]FCLK_CLK_unbuffered;
+  wire FCLK_RESET0_N;
+  wire FCLK_RESET1_N;
+  wire FCLK_RESET2_N;
+  wire FCLK_RESET3_N;
+  wire FPGA_IDLE_N;
+  wire FTMD_TRACEIN_CLK;
+  wire [31:0]FTMT_F2P_DEBUG;
+  wire FTMT_F2P_TRIGACK_0;
+  wire FTMT_F2P_TRIGACK_1;
+  wire FTMT_F2P_TRIGACK_2;
+  wire FTMT_F2P_TRIGACK_3;
+  wire FTMT_F2P_TRIG_0;
+  wire FTMT_F2P_TRIG_1;
+  wire FTMT_F2P_TRIG_2;
+  wire FTMT_F2P_TRIG_3;
+  wire [31:0]FTMT_P2F_DEBUG;
+  wire FTMT_P2F_TRIGACK_0;
+  wire FTMT_P2F_TRIGACK_1;
+  wire FTMT_P2F_TRIGACK_2;
+  wire FTMT_P2F_TRIGACK_3;
+  wire FTMT_P2F_TRIG_0;
+  wire FTMT_P2F_TRIG_1;
+  wire FTMT_P2F_TRIG_2;
+  wire FTMT_P2F_TRIG_3;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SCL_T_n;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire I2C0_SDA_T_n;
+  wire I2C1_SCL_I;
+  wire I2C1_SCL_O;
+  wire I2C1_SCL_T;
+  wire I2C1_SCL_T_n;
+  wire I2C1_SDA_I;
+  wire I2C1_SDA_O;
+  wire I2C1_SDA_T;
+  wire I2C1_SDA_T_n;
+  wire [0:0]IRQ_F2P;
+  wire IRQ_P2F_CAN0;
+  wire IRQ_P2F_CAN1;
+  wire IRQ_P2F_CTI;
+  wire IRQ_P2F_DMAC0;
+  wire IRQ_P2F_DMAC1;
+  wire IRQ_P2F_DMAC2;
+  wire IRQ_P2F_DMAC3;
+  wire IRQ_P2F_DMAC4;
+  wire IRQ_P2F_DMAC5;
+  wire IRQ_P2F_DMAC6;
+  wire IRQ_P2F_DMAC7;
+  wire IRQ_P2F_DMAC_ABORT;
+  wire IRQ_P2F_ENET0;
+  wire IRQ_P2F_ENET1;
+  wire IRQ_P2F_ENET_WAKE0;
+  wire IRQ_P2F_ENET_WAKE1;
+  wire IRQ_P2F_GPIO;
+  wire IRQ_P2F_I2C0;
+  wire IRQ_P2F_I2C1;
+  wire IRQ_P2F_QSPI;
+  wire IRQ_P2F_SDIO0;
+  wire IRQ_P2F_SDIO1;
+  wire IRQ_P2F_SMC;
+  wire IRQ_P2F_SPI0;
+  wire IRQ_P2F_SPI1;
+  wire IRQ_P2F_UART0;
+  wire IRQ_P2F_UART1;
+  wire IRQ_P2F_USB0;
+  wire IRQ_P2F_USB1;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire M_AXI_GP0_ARESETN;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [1:0]\\^M_AXI_GP0_ARSIZE ;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [1:0]\\^M_AXI_GP0_AWSIZE ;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire M_AXI_GP1_ACLK;
+  wire [31:0]M_AXI_GP1_ARADDR;
+  wire [1:0]M_AXI_GP1_ARBURST;
+  wire [3:0]M_AXI_GP1_ARCACHE;
+  wire M_AXI_GP1_ARESETN;
+  wire [11:0]M_AXI_GP1_ARID;
+  wire [3:0]M_AXI_GP1_ARLEN;
+  wire [1:0]M_AXI_GP1_ARLOCK;
+  wire [2:0]M_AXI_GP1_ARPROT;
+  wire [3:0]M_AXI_GP1_ARQOS;
+  wire M_AXI_GP1_ARREADY;
+  wire [1:0]\\^M_AXI_GP1_ARSIZE ;
+  wire M_AXI_GP1_ARVALID;
+  wire [31:0]M_AXI_GP1_AWADDR;
+  wire [1:0]M_AXI_GP1_AWBURST;
+  wire [3:0]M_AXI_GP1_AWCACHE;
+  wire [11:0]M_AXI_GP1_AWID;
+  wire [3:0]M_AXI_GP1_AWLEN;
+  wire [1:0]M_AXI_GP1_AWLOCK;
+  wire [2:0]M_AXI_GP1_AWPROT;
+  wire [3:0]M_AXI_GP1_AWQOS;
+  wire M_AXI_GP1_AWREADY;
+  wire [1:0]\\^M_AXI_GP1_AWSIZE ;
+  wire M_AXI_GP1_AWVALID;
+  wire [11:0]M_AXI_GP1_BID;
+  wire M_AXI_GP1_BREADY;
+  wire [1:0]M_AXI_GP1_BRESP;
+  wire M_AXI_GP1_BVALID;
+  wire [31:0]M_AXI_GP1_RDATA;
+  wire [11:0]M_AXI_GP1_RID;
+  wire M_AXI_GP1_RLAST;
+  wire M_AXI_GP1_RREADY;
+  wire [1:0]M_AXI_GP1_RRESP;
+  wire M_AXI_GP1_RVALID;
+  wire [31:0]M_AXI_GP1_WDATA;
+  wire [11:0]M_AXI_GP1_WID;
+  wire M_AXI_GP1_WLAST;
+  wire M_AXI_GP1_WREADY;
+  wire [3:0]M_AXI_GP1_WSTRB;
+  wire M_AXI_GP1_WVALID;
+  wire PJTAG_TCK;
+  wire PJTAG_TDI;
+  wire PJTAG_TMS;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_BUSPOW;
+  wire [2:0]SDIO0_BUSVOLT;
+  wire SDIO0_CDN;
+  wire SDIO0_CLK;
+  wire SDIO0_CLK_FB;
+  wire SDIO0_CMD_I;
+  wire SDIO0_CMD_O;
+  wire SDIO0_CMD_T;
+  wire SDIO0_CMD_T_n;
+  wire [3:0]SDIO0_DATA_I;
+  wire [3:0]SDIO0_DATA_O;
+  wire [3:0]SDIO0_DATA_T;
+  wire [3:0]SDIO0_DATA_T_n;
+  wire SDIO0_LED;
+  wire SDIO0_WP;
+  wire SDIO1_BUSPOW;
+  wire [2:0]SDIO1_BUSVOLT;
+  wire SDIO1_CDN;
+  wire SDIO1_CLK;
+  wire SDIO1_CLK_FB;
+  wire SDIO1_CMD_I;
+  wire SDIO1_CMD_O;
+  wire SDIO1_CMD_T;
+  wire SDIO1_CMD_T_n;
+  wire [3:0]SDIO1_DATA_I;
+  wire [3:0]SDIO1_DATA_O;
+  wire [3:0]SDIO1_DATA_T;
+  wire [3:0]SDIO1_DATA_T_n;
+  wire SDIO1_LED;
+  wire SDIO1_WP;
+  wire SPI0_MISO_I;
+  wire SPI0_MISO_O;
+  wire SPI0_MISO_T;
+  wire SPI0_MISO_T_n;
+  wire SPI0_MOSI_I;
+  wire SPI0_MOSI_O;
+  wire SPI0_MOSI_T;
+  wire SPI0_MOSI_T_n;
+  wire SPI0_SCLK_I;
+  wire SPI0_SCLK_O;
+  wire SPI0_SCLK_T;
+  wire SPI0_SCLK_T_n;
+  wire SPI0_SS1_O;
+  wire SPI0_SS2_O;
+  wire SPI0_SS_I;
+  wire SPI0_SS_O;
+  wire SPI0_SS_T;
+  wire SPI0_SS_T_n;
+  wire SPI1_MISO_I;
+  wire SPI1_MISO_O;
+  wire SPI1_MISO_T;
+  wire SPI1_MISO_T_n;
+  wire SPI1_MOSI_I;
+  wire SPI1_MOSI_O;
+  wire SPI1_MOSI_T;
+  wire SPI1_MOSI_T_n;
+  wire SPI1_SCLK_I;
+  wire SPI1_SCLK_O;
+  wire SPI1_SCLK_T;
+  wire SPI1_SCLK_T_n;
+  wire SPI1_SS1_O;
+  wire SPI1_SS2_O;
+  wire SPI1_SS_I;
+  wire SPI1_SS_O;
+  wire SPI1_SS_T;
+  wire SPI1_SS_T_n;
+  wire SRAM_INTIN;
+  wire S_AXI_ACP_ACLK;
+  wire [31:0]S_AXI_ACP_ARADDR;
+  wire [1:0]S_AXI_ACP_ARBURST;
+  wire [3:0]S_AXI_ACP_ARCACHE;
+  wire S_AXI_ACP_ARESETN;
+  wire [2:0]S_AXI_ACP_ARID;
+  wire [3:0]S_AXI_ACP_ARLEN;
+  wire [1:0]S_AXI_ACP_ARLOCK;
+  wire [2:0]S_AXI_ACP_ARPROT;
+  wire [3:0]S_AXI_ACP_ARQOS;
+  wire S_AXI_ACP_ARREADY;
+  wire [2:0]S_AXI_ACP_ARSIZE;
+  wire [4:0]S_AXI_ACP_ARUSER;
+  wire S_AXI_ACP_ARVALID;
+  wire [31:0]S_AXI_ACP_AWADDR;
+  wire [1:0]S_AXI_ACP_AWBURST;
+  wire [3:0]S_AXI_ACP_AWCACHE;
+  wire [2:0]S_AXI_ACP_AWID;
+  wire [3:0]S_AXI_ACP_AWLEN;
+  wire [1:0]S_AXI_ACP_AWLOCK;
+  wire [2:0]S_AXI_ACP_AWPROT;
+  wire [3:0]S_AXI_ACP_AWQOS;
+  wire S_AXI_ACP_AWREADY;
+  wire [2:0]S_AXI_ACP_AWSIZE;
+  wire [4:0]S_AXI_ACP_AWUSER;
+  wire S_AXI_ACP_AWVALID;
+  wire [2:0]S_AXI_ACP_BID;
+  wire S_AXI_ACP_BREADY;
+  wire [1:0]S_AXI_ACP_BRESP;
+  wire S_AXI_ACP_BVALID;
+  wire [63:0]S_AXI_ACP_RDATA;
+  wire [2:0]S_AXI_ACP_RID;
+  wire S_AXI_ACP_RLAST;
+  wire S_AXI_ACP_RREADY;
+  wire [1:0]S_AXI_ACP_RRESP;
+  wire S_AXI_ACP_RVALID;
+  wire [63:0]S_AXI_ACP_WDATA;
+  wire [2:0]S_AXI_ACP_WID;
+  wire S_AXI_ACP_WLAST;
+  wire S_AXI_ACP_WREADY;
+  wire [7:0]S_AXI_ACP_WSTRB;
+  wire S_AXI_ACP_WVALID;
+  wire S_AXI_GP0_ACLK;
+  wire [31:0]S_AXI_GP0_ARADDR;
+  wire [1:0]S_AXI_GP0_ARBURST;
+  wire [3:0]S_AXI_GP0_ARCACHE;
+  wire S_AXI_GP0_ARESETN;
+  wire [5:0]S_AXI_GP0_ARID;
+  wire [3:0]S_AXI_GP0_ARLEN;
+  wire [1:0]S_AXI_GP0_ARLOCK;
+  wire [2:0]S_AXI_GP0_ARPROT;
+  wire [3:0]S_AXI_GP0_ARQOS;
+  wire S_AXI_GP0_ARREADY;
+  wire [2:0]S_AXI_GP0_ARSIZE;
+  wire S_AXI_GP0_ARVALID;
+  wire [31:0]S_AXI_GP0_AWADDR;
+  wire [1:0]S_AXI_GP0_AWBURST;
+  wire [3:0]S_AXI_GP0_AWCACHE;
+  wire [5:0]S_AXI_GP0_AWID;
+  wire [3:0]S_AXI_GP0_AWLEN;
+  wire [1:0]S_AXI_GP0_AWLOCK;
+  wire [2:0]S_AXI_GP0_AWPROT;
+  wire [3:0]S_AXI_GP0_AWQOS;
+  wire S_AXI_GP0_AWREADY;
+  wire [2:0]S_AXI_GP0_AWSIZE;
+  wire S_AXI_GP0_AWVALID;
+  wire [5:0]S_AXI_GP0_BID;
+  wire S_AXI_GP0_BREADY;
+  wire [1:0]S_AXI_GP0_BRESP;
+  wire S_AXI_GP0_BVALID;
+  wire [31:0]S_AXI_GP0_RDATA;
+  wire [5:0]S_AXI_GP0_RID;
+  wire S_AXI_GP0_RLAST;
+  wire S_AXI_GP0_RREADY;
+  wire [1:0]S_AXI_GP0_RRESP;
+  wire S_AXI_GP0_RVALID;
+  wire [31:0]S_AXI_GP0_WDATA;
+  wire [5:0]S_AXI_GP0_WID;
+  wire S_AXI_GP0_WLAST;
+  wire S_AXI_GP0_WREADY;
+  wire [3:0]S_AXI_GP0_WSTRB;
+  wire S_AXI_GP0_WVALID;
+  wire S_AXI_GP1_ACLK;
+  wire [31:0]S_AXI_GP1_ARADDR;
+  wire [1:0]S_AXI_GP1_ARBURST;
+  wire [3:0]S_AXI_GP1_ARCACHE;
+  wire S_AXI_GP1_ARESETN;
+  wire [5:0]S_AXI_GP1_ARID;
+  wire [3:0]S_AXI_GP1_ARLEN;
+  wire [1:0]S_AXI_GP1_ARLOCK;
+  wire [2:0]S_AXI_GP1_ARPROT;
+  wire [3:0]S_AXI_GP1_ARQOS;
+  wire S_AXI_GP1_ARREADY;
+  wire [2:0]S_AXI_GP1_ARSIZE;
+  wire S_AXI_GP1_ARVALID;
+  wire [31:0]S_AXI_GP1_AWADDR;
+  wire [1:0]S_AXI_GP1_AWBURST;
+  wire [3:0]S_AXI_GP1_AWCACHE;
+  wire [5:0]S_AXI_GP1_AWID;
+  wire [3:0]S_AXI_GP1_AWLEN;
+  wire [1:0]S_AXI_GP1_AWLOCK;
+  wire [2:0]S_AXI_GP1_AWPROT;
+  wire [3:0]S_AXI_GP1_AWQOS;
+  wire S_AXI_GP1_AWREADY;
+  wire [2:0]S_AXI_GP1_AWSIZE;
+  wire S_AXI_GP1_AWVALID;
+  wire [5:0]S_AXI_GP1_BID;
+  wire S_AXI_GP1_BREADY;
+  wire [1:0]S_AXI_GP1_BRESP;
+  wire S_AXI_GP1_BVALID;
+  wire [31:0]S_AXI_GP1_RDATA;
+  wire [5:0]S_AXI_GP1_RID;
+  wire S_AXI_GP1_RLAST;
+  wire S_AXI_GP1_RREADY;
+  wire [1:0]S_AXI_GP1_RRESP;
+  wire S_AXI_GP1_RVALID;
+  wire [31:0]S_AXI_GP1_WDATA;
+  wire [5:0]S_AXI_GP1_WID;
+  wire S_AXI_GP1_WLAST;
+  wire S_AXI_GP1_WREADY;
+  wire [3:0]S_AXI_GP1_WSTRB;
+  wire S_AXI_GP1_WVALID;
+  wire S_AXI_HP0_ACLK;
+  wire [31:0]S_AXI_HP0_ARADDR;
+  wire [1:0]S_AXI_HP0_ARBURST;
+  wire [3:0]S_AXI_HP0_ARCACHE;
+  wire S_AXI_HP0_ARESETN;
+  wire [5:0]S_AXI_HP0_ARID;
+  wire [3:0]S_AXI_HP0_ARLEN;
+  wire [1:0]S_AXI_HP0_ARLOCK;
+  wire [2:0]S_AXI_HP0_ARPROT;
+  wire [3:0]S_AXI_HP0_ARQOS;
+  wire S_AXI_HP0_ARREADY;
+  wire [2:0]S_AXI_HP0_ARSIZE;
+  wire S_AXI_HP0_ARVALID;
+  wire [31:0]S_AXI_HP0_AWADDR;
+  wire [1:0]S_AXI_HP0_AWBURST;
+  wire [3:0]S_AXI_HP0_AWCACHE;
+  wire [5:0]S_AXI_HP0_AWID;
+  wire [3:0]S_AXI_HP0_AWLEN;
+  wire [1:0]S_AXI_HP0_AWLOCK;
+  wire [2:0]S_AXI_HP0_AWPROT;
+  wire [3:0]S_AXI_HP0_AWQOS;
+  wire S_AXI_HP0_AWREADY;
+  wire [2:0]S_AXI_HP0_AWSIZE;
+  wire S_AXI_HP0_AWVALID;
+  wire [5:0]S_AXI_HP0_BID;
+  wire S_AXI_HP0_BREADY;
+  wire [1:0]S_AXI_HP0_BRESP;
+  wire S_AXI_HP0_BVALID;
+  wire [2:0]S_AXI_HP0_RACOUNT;
+  wire [7:0]S_AXI_HP0_RCOUNT;
+  wire [63:0]S_AXI_HP0_RDATA;
+  wire S_AXI_HP0_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP0_RID;
+  wire S_AXI_HP0_RLAST;
+  wire S_AXI_HP0_RREADY;
+  wire [1:0]S_AXI_HP0_RRESP;
+  wire S_AXI_HP0_RVALID;
+  wire [5:0]S_AXI_HP0_WACOUNT;
+  wire [7:0]S_AXI_HP0_WCOUNT;
+  wire [63:0]S_AXI_HP0_WDATA;
+  wire [5:0]S_AXI_HP0_WID;
+  wire S_AXI_HP0_WLAST;
+  wire S_AXI_HP0_WREADY;
+  wire S_AXI_HP0_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP0_WSTRB;
+  wire S_AXI_HP0_WVALID;
+  wire S_AXI_HP1_ACLK;
+  wire [31:0]S_AXI_HP1_ARADDR;
+  wire [1:0]S_AXI_HP1_ARBURST;
+  wire [3:0]S_AXI_HP1_ARCACHE;
+  wire S_AXI_HP1_ARESETN;
+  wire [5:0]S_AXI_HP1_ARID;
+  wire [3:0]S_AXI_HP1_ARLEN;
+  wire [1:0]S_AXI_HP1_ARLOCK;
+  wire [2:0]S_AXI_HP1_ARPROT;
+  wire [3:0]S_AXI_HP1_ARQOS;
+  wire S_AXI_HP1_ARREADY;
+  wire [2:0]S_AXI_HP1_ARSIZE;
+  wire S_AXI_HP1_ARVALID;
+  wire [31:0]S_AXI_HP1_AWADDR;
+  wire [1:0]S_AXI_HP1_AWBURST;
+  wire [3:0]S_AXI_HP1_AWCACHE;
+  wire [5:0]S_AXI_HP1_AWID;
+  wire [3:0]S_AXI_HP1_AWLEN;
+  wire [1:0]S_AXI_HP1_AWLOCK;
+  wire [2:0]S_AXI_HP1_AWPROT;
+  wire [3:0]S_AXI_HP1_AWQOS;
+  wire S_AXI_HP1_AWREADY;
+  wire [2:0]S_AXI_HP1_AWSIZE;
+  wire S_AXI_HP1_AWVALID;
+  wire [5:0]S_AXI_HP1_BID;
+  wire S_AXI_HP1_BREADY;
+  wire [1:0]S_AXI_HP1_BRESP;
+  wire S_AXI_HP1_BVALID;
+  wire [2:0]S_AXI_HP1_RACOUNT;
+  wire [7:0]S_AXI_HP1_RCOUNT;
+  wire [63:0]S_AXI_HP1_RDATA;
+  wire S_AXI_HP1_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP1_RID;
+  wire S_AXI_HP1_RLAST;
+  wire S_AXI_HP1_RREADY;
+  wire [1:0]S_AXI_HP1_RRESP;
+  wire S_AXI_HP1_RVALID;
+  wire [5:0]S_AXI_HP1_WACOUNT;
+  wire [7:0]S_AXI_HP1_WCOUNT;
+  wire [63:0]S_AXI_HP1_WDATA;
+  wire [5:0]S_AXI_HP1_WID;
+  wire S_AXI_HP1_WLAST;
+  wire S_AXI_HP1_WREADY;
+  wire S_AXI_HP1_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP1_WSTRB;
+  wire S_AXI_HP1_WVALID;
+  wire S_AXI_HP2_ACLK;
+  wire [31:0]S_AXI_HP2_ARADDR;
+  wire [1:0]S_AXI_HP2_ARBURST;
+  wire [3:0]S_AXI_HP2_ARCACHE;
+  wire S_AXI_HP2_ARESETN;
+  wire [5:0]S_AXI_HP2_ARID;
+  wire [3:0]S_AXI_HP2_ARLEN;
+  wire [1:0]S_AXI_HP2_ARLOCK;
+  wire [2:0]S_AXI_HP2_ARPROT;
+  wire [3:0]S_AXI_HP2_ARQOS;
+  wire S_AXI_HP2_ARREADY;
+  wire [2:0]S_AXI_HP2_ARSIZE;
+  wire S_AXI_HP2_ARVALID;
+  wire [31:0]S_AXI_HP2_AWADDR;
+  wire [1:0]S_AXI_HP2_AWBURST;
+  wire [3:0]S_AXI_HP2_AWCACHE;
+  wire [5:0]S_AXI_HP2_AWID;
+  wire [3:0]S_AXI_HP2_AWLEN;
+  wire [1:0]S_AXI_HP2_AWLOCK;
+  wire [2:0]S_AXI_HP2_AWPROT;
+  wire [3:0]S_AXI_HP2_AWQOS;
+  wire S_AXI_HP2_AWREADY;
+  wire [2:0]S_AXI_HP2_AWSIZE;
+  wire S_AXI_HP2_AWVALID;
+  wire [5:0]S_AXI_HP2_BID;
+  wire S_AXI_HP2_BREADY;
+  wire [1:0]S_AXI_HP2_BRESP;
+  wire S_AXI_HP2_BVALID;
+  wire [2:0]S_AXI_HP2_RACOUNT;
+  wire [7:0]S_AXI_HP2_RCOUNT;
+  wire [63:0]S_AXI_HP2_RDATA;
+  wire S_AXI_HP2_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP2_RID;
+  wire S_AXI_HP2_RLAST;
+  wire S_AXI_HP2_RREADY;
+  wire [1:0]S_AXI_HP2_RRESP;
+  wire S_AXI_HP2_RVALID;
+  wire [5:0]S_AXI_HP2_WACOUNT;
+  wire [7:0]S_AXI_HP2_WCOUNT;
+  wire [63:0]S_AXI_HP2_WDATA;
+  wire [5:0]S_AXI_HP2_WID;
+  wire S_AXI_HP2_WLAST;
+  wire S_AXI_HP2_WREADY;
+  wire S_AXI_HP2_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP2_WSTRB;
+  wire S_AXI_HP2_WVALID;
+  wire S_AXI_HP3_ACLK;
+  wire [31:0]S_AXI_HP3_ARADDR;
+  wire [1:0]S_AXI_HP3_ARBURST;
+  wire [3:0]S_AXI_HP3_ARCACHE;
+  wire S_AXI_HP3_ARESETN;
+  wire [5:0]S_AXI_HP3_ARID;
+  wire [3:0]S_AXI_HP3_ARLEN;
+  wire [1:0]S_AXI_HP3_ARLOCK;
+  wire [2:0]S_AXI_HP3_ARPROT;
+  wire [3:0]S_AXI_HP3_ARQOS;
+  wire S_AXI_HP3_ARREADY;
+  wire [2:0]S_AXI_HP3_ARSIZE;
+  wire S_AXI_HP3_ARVALID;
+  wire [31:0]S_AXI_HP3_AWADDR;
+  wire [1:0]S_AXI_HP3_AWBURST;
+  wire [3:0]S_AXI_HP3_AWCACHE;
+  wire [5:0]S_AXI_HP3_AWID;
+  wire [3:0]S_AXI_HP3_AWLEN;
+  wire [1:0]S_AXI_HP3_AWLOCK;
+  wire [2:0]S_AXI_HP3_AWPROT;
+  wire [3:0]S_AXI_HP3_AWQOS;
+  wire S_AXI_HP3_AWREADY;
+  wire [2:0]S_AXI_HP3_AWSIZE;
+  wire S_AXI_HP3_AWVALID;
+  wire [5:0]S_AXI_HP3_BID;
+  wire S_AXI_HP3_BREADY;
+  wire [1:0]S_AXI_HP3_BRESP;
+  wire S_AXI_HP3_BVALID;
+  wire [2:0]S_AXI_HP3_RACOUNT;
+  wire [7:0]S_AXI_HP3_RCOUNT;
+  wire [63:0]S_AXI_HP3_RDATA;
+  wire S_AXI_HP3_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP3_RID;
+  wire S_AXI_HP3_RLAST;
+  wire S_AXI_HP3_RREADY;
+  wire [1:0]S_AXI_HP3_RRESP;
+  wire S_AXI_HP3_RVALID;
+  wire [5:0]S_AXI_HP3_WACOUNT;
+  wire [7:0]S_AXI_HP3_WCOUNT;
+  wire [63:0]S_AXI_HP3_WDATA;
+  wire [5:0]S_AXI_HP3_WID;
+  wire S_AXI_HP3_WLAST;
+  wire S_AXI_HP3_WREADY;
+  wire S_AXI_HP3_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP3_WSTRB;
+  wire S_AXI_HP3_WVALID;
+  wire TRACE_CLK;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[7] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[7] ;
+  wire TTC0_CLK0_IN;
+  wire TTC0_CLK1_IN;
+  wire TTC0_CLK2_IN;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire TTC1_CLK0_IN;
+  wire TTC1_CLK1_IN;
+  wire TTC1_CLK2_IN;
+  wire TTC1_WAVE0_OUT;
+  wire TTC1_WAVE1_OUT;
+  wire TTC1_WAVE2_OUT;
+  wire UART0_CTSN;
+  wire UART0_DCDN;
+  wire UART0_DSRN;
+  wire UART0_DTRN;
+  wire UART0_RIN;
+  wire UART0_RTSN;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire UART1_CTSN;
+  wire UART1_DCDN;
+  wire UART1_DSRN;
+  wire UART1_DTRN;
+  wire UART1_RIN;
+  wire UART1_RTSN;
+  wire UART1_RX;
+  wire UART1_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire [1:0]USB1_PORT_INDCTL;
+  wire USB1_VBUS_PWRFAULT;
+  wire USB1_VBUS_PWRSELECT;
+  wire WDT_CLK_IN;
+  wire WDT_RST_OUT;
+  wire [14:0]buffered_DDR_Addr;
+  wire [2:0]buffered_DDR_BankAddr;
+  wire buffered_DDR_CAS_n;
+  wire buffered_DDR_CKE;
+  wire buffered_DDR_CS_n;
+  wire buffered_DDR_Clk;
+  wire buffered_DDR_Clk_n;
+  wire [3:0]buffered_DDR_DM;
+  wire [31:0]buffered_DDR_DQ;
+  wire [3:0]buffered_DDR_DQS;
+  wire [3:0]buffered_DDR_DQS_n;
+  wire buffered_DDR_DRSTB;
+  wire buffered_DDR_ODT;
+  wire buffered_DDR_RAS_n;
+  wire buffered_DDR_VRN;
+  wire buffered_DDR_VRP;
+  wire buffered_DDR_WEB;
+  wire [53:0]buffered_MIO;
+  wire buffered_PS_CLK;
+  wire buffered_PS_PORB;
+  wire buffered_PS_SRSTB;
+  wire [63:0]gpio_out_t_n;
+  wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET1'b'GMIITXD_UNCONNECTED;
+  wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+
+  assign ENET0_GMII_TXD[7] = \\<const0> ;
+  assign ENET0_GMII_TXD[6] = \\<const0> ;
+  assign ENET0_GMII_TXD[5] = \\<const0> ;
+  assign ENET0_GMII_TXD[4] = \\<const0> ;
+  assign ENET0_GMII_TXD[3] = \\<const0> ;
+  assign ENET0_GMII_TXD[2] = \\<const0> ;
+  assign ENET0_GMII_TXD[1] = \\<const0> ;
+  assign ENET0_GMII_TXD[0] = \\<const0> ;
+  assign ENET0_GMII_TX_EN = \\<const0> ;
+  assign ENET0_GMII_TX_ER = \\<const0> ;
+  assign ENET1_GMII_TXD[7] = \\<const0> ;
+  assign ENET1_GMII_TXD[6] = \\<const0> ;
+  assign ENET1_GMII_TXD[5] = \\<const0> ;
+  assign ENET1_GMII_TXD[4] = \\<const0> ;
+  assign ENET1_GMII_TXD[3] = \\<const0> ;
+  assign ENET1_GMII_TXD[2] = \\<const0> ;
+  assign ENET1_GMII_TXD[1] = \\<const0> ;
+  assign ENET1_GMII_TXD[0] = \\<const0> ;
+  assign ENET1_GMII_TX_EN = \\<const0> ;
+  assign ENET1_GMII_TX_ER = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[1:0] = \\^M_AXI_GP0_ARSIZE [1:0];
+  assign M_AXI_GP0_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_AWSIZE[1:0] = \\^M_AXI_GP0_AWSIZE [1:0];
+  assign M_AXI_GP1_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_ARSIZE[1:0] = \\^M_AXI_GP1_ARSIZE [1:0];
+  assign M_AXI_GP1_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_AWSIZE[1:0] = \\^M_AXI_GP1_AWSIZE [1:0];
+  assign PJTAG_TDO = \\<const0> ;
+  assign TRACE_CLK_OUT = \\<const0> ;
+  assign TRACE_CTL = \\TRACE_CTL_PIPE[0] ;
+  assign TRACE_DATA[1:0] = \\TRACE_DATA_PIPE[0] ;
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CAS_n_BIBUF
+       (.IO(buffered_DDR_CAS_n),
+        .PAD(DDR_CAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CKE_BIBUF
+       (.IO(buffered_DDR_CKE),
+        .PAD(DDR_CKE));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CS_n_BIBUF
+       (.IO(buffered_DDR_CS_n),
+        .PAD(DDR_CS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_BIBUF
+       (.IO(buffered_DDR_Clk),
+        .PAD(DDR_Clk));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_n_BIBUF
+       (.IO(buffered_DDR_Clk_n),
+        .PAD(DDR_Clk_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_DRSTB_BIBUF
+       (.IO(buffered_DDR_DRSTB),
+        .PAD(DDR_DRSTB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_ODT_BIBUF
+       (.IO(buffered_DDR_ODT),
+        .PAD(DDR_ODT));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_RAS_n_BIBUF
+       (.IO(buffered_DDR_RAS_n),
+        .PAD(DDR_RAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRN_BIBUF
+       (.IO(buffered_DDR_VRN),
+        .PAD(DDR_VRN));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRP_BIBUF
+       (.IO(buffered_DDR_VRP),
+        .PAD(DDR_VRP));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_WEB_BIBUF
+       (.IO(buffered_DDR_WEB),
+        .PAD(DDR_WEB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET0_MDIO_T_INST_0
+       (.I0(ENET0_MDIO_T_n),
+        .O(ENET0_MDIO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET1_MDIO_T_INST_0
+       (.I0(ENET1_MDIO_T_n),
+        .O(ENET1_MDIO_T));
+  GND GND
+       (.G(\\<const0> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[0]_INST_0 
+       (.I0(gpio_out_t_n[0]),
+        .O(GPIO_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[10]_INST_0 
+       (.I0(gpio_out_t_n[10]),
+        .O(GPIO_T[10]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[11]_INST_0 
+       (.I0(gpio_out_t_n[11]),
+        .O(GPIO_T[11]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[12]_INST_0 
+       (.I0(gpio_out_t_n[12]),
+        .O(GPIO_T[12]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[13]_INST_0 
+       (.I0(gpio_out_t_n[13]),
+        .O(GPIO_T[13]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[14]_INST_0 
+       (.I0(gpio_out_t_n[14]),
+        .O(GPIO_T[14]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[15]_INST_0 
+       (.I0(gpio_out_t_n[15]),
+        .O(GPIO_T[15]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[16]_INST_0 
+       (.I0(gpio_out_t_n[16]),
+        .O(GPIO_T[16]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[17]_INST_0 
+       (.I0(gpio_out_t_n[17]),
+        .O(GPIO_T[17]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[18]_INST_0 
+       (.I0(gpio_out_t_n[18]),
+        .O(GPIO_T[18]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[19]_INST_0 
+       (.I0(gpio_out_t_n[19]),
+        .O(GPIO_T[19]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[1]_INST_0 
+       (.I0(gpio_out_t_n[1]),
+        .O(GPIO_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[20]_INST_0 
+       (.I0(gpio_out_t_n[20]),
+        .O(GPIO_T[20]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[21]_INST_0 
+       (.I0(gpio_out_t_n[21]),
+        .O(GPIO_T[21]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[22]_INST_0 
+       (.I0(gpio_out_t_n[22]),
+        .O(GPIO_T[22]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[23]_INST_0 
+       (.I0(gpio_out_t_n[23]),
+        .O(GPIO_T[23]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[24]_INST_0 
+       (.I0(gpio_out_t_n[24]),
+        .O(GPIO_T[24]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[25]_INST_0 
+       (.I0(gpio_out_t_n[25]),
+        .O(GPIO_T[25]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[26]_INST_0 
+       (.I0(gpio_out_t_n[26]),
+        .O(GPIO_T[26]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[27]_INST_0 
+       (.I0(gpio_out_t_n[27]),
+        .O(GPIO_T[27]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[28]_INST_0 
+       (.I0(gpio_out_t_n[28]),
+        .O(GPIO_T[28]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[29]_INST_0 
+       (.I0(gpio_out_t_n[29]),
+        .O(GPIO_T[29]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[2]_INST_0 
+       (.I0(gpio_out_t_n[2]),
+        .O(GPIO_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[30]_INST_0 
+       (.I0(gpio_out_t_n[30]),
+        .O(GPIO_T[30]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[31]_INST_0 
+       (.I0(gpio_out_t_n[31]),
+        .O(GPIO_T[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[32]_INST_0 
+       (.I0(gpio_out_t_n[32]),
+        .O(GPIO_T[32]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[33]_INST_0 
+       (.I0(gpio_out_t_n[33]),
+        .O(GPIO_T[33]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[34]_INST_0 
+       (.I0(gpio_out_t_n[34]),
+        .O(GPIO_T[34]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[35]_INST_0 
+       (.I0(gpio_out_t_n[35]),
+        .O(GPIO_T[35]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[36]_INST_0 
+       (.I0(gpio_out_t_n[36]),
+        .O(GPIO_T[36]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[37]_INST_0 
+       (.I0(gpio_out_t_n[37]),
+        .O(GPIO_T[37]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[38]_INST_0 
+       (.I0(gpio_out_t_n[38]),
+        .O(GPIO_T[38]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[39]_INST_0 
+       (.I0(gpio_out_t_n[39]),
+        .O(GPIO_T[39]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[3]_INST_0 
+       (.I0(gpio_out_t_n[3]),
+        .O(GPIO_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[40]_INST_0 
+       (.I0(gpio_out_t_n[40]),
+        .O(GPIO_T[40]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[41]_INST_0 
+       (.I0(gpio_out_t_n[41]),
+        .O(GPIO_T[41]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[42]_INST_0 
+       (.I0(gpio_out_t_n[42]),
+        .O(GPIO_T[42]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[43]_INST_0 
+       (.I0(gpio_out_t_n[43]),
+        .O(GPIO_T[43]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[44]_INST_0 
+       (.I0(gpio_out_t_n[44]),
+        .O(GPIO_T[44]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[45]_INST_0 
+       (.I0(gpio_out_t_n[45]),
+        .O(GPIO_T[45]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[46]_INST_0 
+       (.I0(gpio_out_t_n[46]),
+        .O(GPIO_T[46]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[47]_INST_0 
+       (.I0(gpio_out_t_n[47]),
+        .O(GPIO_T[47]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[48]_INST_0 
+       (.I0(gpio_out_t_n[48]),
+        .O(GPIO_T[48]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[49]_INST_0 
+       (.I0(gpio_out_t_n[49]),
+        .O(GPIO_T[49]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[4]_INST_0 
+       (.I0(gpio_out_t_n[4]),
+        .O(GPIO_T[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[50]_INST_0 
+       (.I0(gpio_out_t_n[50]),
+        .O(GPIO_T[50]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[51]_INST_0 
+       (.I0(gpio_out_t_n[51]),
+        .O(GPIO_T[51]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[52]_INST_0 
+       (.I0(gpio_out_t_n[52]),
+        .O(GPIO_T[52]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[53]_INST_0 
+       (.I0(gpio_out_t_n[53]),
+        .O(GPIO_T[53]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[54]_INST_0 
+       (.I0(gpio_out_t_n[54]),
+        .O(GPIO_T[54]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[55]_INST_0 
+       (.I0(gpio_out_t_n[55]),
+        .O(GPIO_T[55]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[56]_INST_0 
+       (.I0(gpio_out_t_n[56]),
+        .O(GPIO_T[56]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[57]_INST_0 
+       (.I0(gpio_out_t_n[57]),
+        .O(GPIO_T[57]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[58]_INST_0 
+       (.I0(gpio_out_t_n[58]),
+        .O(GPIO_T[58]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[59]_INST_0 
+       (.I0(gpio_out_t_n[59]),
+        .O(GPIO_T[59]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[5]_INST_0 
+       (.I0(gpio_out_t_n[5]),
+        .O(GPIO_T[5]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[60]_INST_0 
+       (.I0(gpio_out_t_n[60]),
+        .O(GPIO_T[60]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[61]_INST_0 
+       (.I0(gpio_out_t_n[61]),
+        .O(GPIO_T[61]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[62]_INST_0 
+       (.I0(gpio_out_t_n[62]),
+        .O(GPIO_T[62]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[63]_INST_0 
+       (.I0(gpio_out_t_n[63]),
+        .O(GPIO_T[63]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[6]_INST_0 
+       (.I0(gpio_out_t_n[6]),
+        .O(GPIO_T[6]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[7]_INST_0 
+       (.I0(gpio_out_t_n[7]),
+        .O(GPIO_T[7]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[8]_INST_0 
+       (.I0(gpio_out_t_n[8]),
+        .O(GPIO_T[8]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[9]_INST_0 
+       (.I0(gpio_out_t_n[9]),
+        .O(GPIO_T[9]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SCL_T_INST_0
+       (.I0(I2C0_SCL_T_n),
+        .O(I2C0_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SDA_T_INST_0
+       (.I0(I2C0_SDA_T_n),
+        .O(I2C0_SDA_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SCL_T_INST_0
+       (.I0(I2C1_SCL_T_n),
+        .O(I2C1_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SDA_T_INST_0
+       (.I0(I2C1_SDA_T_n),
+        .O(I2C1_SDA_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  PS7 PS7_i
+       (.DDRA(buffered_DDR_Addr),
+        .DDRARB(DDR_ARB),
+        .DDRBA(buffered_DDR_BankAddr),
+        .DDRCASB(buffered_DDR_CAS_n),
+        .DDRCKE(buffered_DDR_CKE),
+        .DDRCKN(buffered_DDR_Clk_n),
+        .DDRCKP(buffered_DDR_Clk),
+        .DDRCSB(buffered_DDR_CS_n),
+        .DDRDM(buffered_DDR_DM),
+        .DDRDQ(buffered_DDR_DQ),
+        .DDRDQSN(buffered_DDR_DQS_n),
+        .DDRDQSP(buffered_DDR_DQS),
+        .DDRDRSTB(buffered_DDR_DRSTB),
+        .DDRODT(buffered_DDR_ODT),
+        .DDRRASB(buffered_DDR_RAS_n),
+        .DDRVRN(buffered_DDR_VRN),
+        .DDRVRP(buffered_DDR_VRP),
+        .DDRWEB(buffered_DDR_WEB),
+        .DMA0ACLK(DMA0_ACLK),
+        .DMA0DAREADY(DMA0_DAREADY),
+        .DMA0DATYPE(DMA0_DATYPE),
+        .DMA0DAVALID(DMA0_DAVALID),
+        .DMA0DRLAST(DMA0_DRLAST),
+        .DMA0DRREADY(DMA0_DRREADY),
+        .DMA0DRTYPE(DMA0_DRTYPE),
+        .DMA0DRVALID(DMA0_DRVALID),
+        .DMA0RSTN(DMA0_RSTN),
+        .DMA1ACLK(DMA1_ACLK),
+        .DMA1DAREADY(DMA1_DAREADY),
+        .DMA1DATYPE(DMA1_DATYPE),
+        .DMA1DAVALID(DMA1_DAVALID),
+        .DMA1DRLAST(DMA1_DRLAST),
+        .DMA1DRREADY(DMA1_DRREADY),
+        .DMA1DRTYPE(DMA1_DRTYPE),
+        .DMA1DRVALID(DMA1_DRVALID),
+        .DMA1RSTN(DMA1_RSTN),
+        .DMA2ACLK(DMA2_ACLK),
+        .DMA2DAREADY(DMA2_DAREADY),
+        .DMA2DATYPE(DMA2_DATYPE),
+        .DMA2DAVALID(DMA2_DAVALID),
+        .DMA2DRLAST(DMA2_DRLAST),
+        .DMA2DRREADY(DMA2_DRREADY),
+        .DMA2DRTYPE(DMA2_DRTYPE),
+        .DMA2DRVALID(DMA2_DRVALID),
+        .DMA2RSTN(DMA2_RSTN),
+        .DMA3ACLK(DMA3_ACLK),
+        .DMA3DAREADY(DMA3_DAREADY),
+        .DMA3DATYPE(DMA3_DATYPE),
+        .DMA3DAVALID(DMA3_DAVALID),
+        .DMA3DRLAST(DMA3_DRLAST),
+        .DMA3DRREADY(DMA3_DRREADY),
+        .DMA3DRTYPE(DMA3_DRTYPE),
+        .DMA3DRVALID(DMA3_DRVALID),
+        .DMA3RSTN(DMA3_RSTN),
+        .EMIOCAN0PHYRX(CAN0_PHY_RX),
+        .EMIOCAN0PHYTX(CAN0_PHY_TX),
+        .EMIOCAN1PHYRX(CAN1_PHY_RX),
+        .EMIOCAN1PHYTX(CAN1_PHY_TX),
+        .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+        .EMIOENET0GMIICOL(1\'b0),
+        .EMIOENET0GMIICRS(1\'b0),
+        .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+        .EMIOENET0GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET0GMIIRXDV(1\'b0),
+        .EMIOENET0GMIIRXER(1\'b0),
+        .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+        .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+        .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+        .EMIOENET0MDIOI(ENET0_MDIO_I),
+        .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+        .EMIOENET0MDIOO(ENET0_MDIO_O),
+        .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+        .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+        .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+        .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+        .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+        .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+        .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+        .EMIOENET0SOFRX(ENET0_SOF_RX),
+        .EMIOENET0SOFTX(ENET0_SOF_TX),
+        .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+        .EMIOENET1GMIICOL(1\'b0),
+        .EMIOENET1GMIICRS(1\'b0),
+        .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+        .EMIOENET1GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET1GMIIRXDV(1\'b0),
+        .EMIOENET1GMIIRXER(1\'b0),
+        .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+        .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+        .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+        .EMIOENET1MDIOI(ENET1_MDIO_I),
+        .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+        .EMIOENET1MDIOO(ENET1_MDIO_O),
+        .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+        .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+        .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+        .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+        .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+        .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+        .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+        .EMIOENET1SOFRX(ENET1_SOF_RX),
+        .EMIOENET1SOFTX(ENET1_SOF_TX),
+        .EMIOGPIOI(GPIO_I),
+        .EMIOGPIOO(GPIO_O),
+        .EMIOGPIOTN(gpio_out_t_n),
+        .EMIOI2C0SCLI(I2C0_SCL_I),
+        .EMIOI2C0SCLO(I2C0_SCL_O),
+        .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+        .EMIOI2C0SDAI(I2C0_SDA_I),
+        .EMIOI2C0SDAO(I2C0_SDA_O),
+        .EMIOI2C0SDATN(I2C0_SDA_T_n),
+        .EMIOI2C1SCLI(I2C1_SCL_I),
+        .EMIOI2C1SCLO(I2C1_SCL_O),
+        .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+        .EMIOI2C1SDAI(I2C1_SDA_I),
+        .EMIOI2C1SDAO(I2C1_SDA_O),
+        .EMIOI2C1SDATN(I2C1_SDA_T_n),
+        .EMIOPJTAGTCK(PJTAG_TCK),
+        .EMIOPJTAGTDI(PJTAG_TDI),
+        .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+        .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+        .EMIOPJTAGTMS(PJTAG_TMS),
+        .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+        .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+        .EMIOSDIO0CDN(SDIO0_CDN),
+        .EMIOSDIO0CLK(SDIO0_CLK),
+        .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+        .EMIOSDIO0CMDI(SDIO0_CMD_I),
+        .EMIOSDIO0CMDO(SDIO0_CMD_O),
+        .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+        .EMIOSDIO0DATAI(SDIO0_DATA_I),
+        .EMIOSDIO0DATAO(SDIO0_DATA_O),
+        .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+        .EMIOSDIO0LED(SDIO0_LED),
+        .EMIOSDIO0WP(SDIO0_WP),
+        .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+        .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+        .EMIOSDIO1CDN(SDIO1_CDN),
+        .EMIOSDIO1CLK(SDIO1_CLK),
+        .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+        .EMIOSDIO1CMDI(SDIO1_CMD_I),
+        .EMIOSDIO1CMDO(SDIO1_CMD_O),
+        .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+        .EMIOSDIO1DATAI(SDIO1_DATA_I),
+        .EMIOSDIO1DATAO(SDIO1_DATA_O),
+        .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+        .EMIOSDIO1LED(SDIO1_LED),
+        .EMIOSDIO1WP(SDIO1_WP),
+        .EMIOSPI0MI(SPI0_MISO_I),
+        .EMIOSPI0MO(SPI0_MOSI_O),
+        .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+        .EMIOSPI0SCLKI(SPI0_SCLK_I),
+        .EMIOSPI0SCLKO(SPI0_SCLK_O),
+        .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+        .EMIOSPI0SI(SPI0_MOSI_I),
+        .EMIOSPI0SO(SPI0_MISO_O),
+        .EMIOSPI0SSIN(SPI0_SS_I),
+        .EMIOSPI0SSNTN(SPI0_SS_T_n),
+        .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+        .EMIOSPI0STN(SPI0_MISO_T_n),
+        .EMIOSPI1MI(SPI1_MISO_I),
+        .EMIOSPI1MO(SPI1_MOSI_O),
+        .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+        .EMIOSPI1SCLKI(SPI1_SCLK_I),
+        .EMIOSPI1SCLKO(SPI1_SCLK_O),
+        .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+        .EMIOSPI1SI(SPI1_MOSI_I),
+        .EMIOSPI1SO(SPI1_MISO_O),
+        .EMIOSPI1SSIN(SPI1_SS_I),
+        .EMIOSPI1SSNTN(SPI1_SS_T_n),
+        .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+        .EMIOSPI1STN(SPI1_MISO_T_n),
+        .EMIOSRAMINTIN(SRAM_INTIN),
+        .EMIOTRACECLK(TRACE_CLK),
+        .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+        .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+        .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+        .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+        .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+        .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+        .EMIOUART0CTSN(UART0_CTSN),
+        .EMIOUART0DCDN(UART0_DCDN),
+        .EMIOUART0DSRN(UART0_DSRN),
+        .EMIOUART0DTRN(UART0_DTRN),
+        .EMIOUART0RIN(UART0_RIN),
+        .EMIOUART0RTSN(UART0_RTSN),
+        .EMIOUART0RX(UART0_RX),
+        .EMIOUART0TX(UART0_TX),
+        .EMIOUART1CTSN(UART1_CTSN),
+        .EMIOUART1DCDN(UART1_DCDN),
+        .EMIOUART1DSRN(UART1_DSRN),
+        .EMIOUART1DTRN(UART1_DTRN),
+        .EMIOUART1RIN(UART1_RIN),
+        .EMIOUART1RTSN(UART1_RTSN),
+        .EMIOUART1RX(UART1_RX),
+        .EMIOUART1TX(UART1_TX),
+        .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+        .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+        .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+        .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+        .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+        .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+        .EMIOWDTCLKI(WDT_CLK_IN),
+        .EMIOWDTRSTO(WDT_RST_OUT),
+        .EVENTEVENTI(EVENT_EVENTI),
+        .EVENTEVENTO(EVENT_EVENTO),
+        .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+        .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+        .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+        .FCLKCLKTRIGN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+        .FPGAIDLEN(FPGA_IDLE_N),
+        .FTMDTRACEINATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+        .FTMDTRACEINDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINVALID(1\'b0),
+        .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+        .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+        .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+        .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+        .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+        .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+        .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,IRQ_F2P}),
+        .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+        .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+        .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+        .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+        .MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
+        .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+        .MAXIGP0ARID(M_AXI_GP0_ARID),
+        .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+        .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+        .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+        .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+        .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+        .MAXIGP0ARSIZE(\\^M_AXI_GP0_ARSIZE ),
+        .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+        .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+        .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+        .MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
+        .MAXIGP0AWID(M_AXI_GP0_AWID),
+        .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+        .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+        .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+        .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+        .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+        .MAXIGP0AWSIZE(\\^M_AXI_GP0_AWSIZE ),
+        .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+        .MAXIGP0BID(M_AXI_GP0_BID),
+        .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+        .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+        .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+        .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+        .MAXIGP0RID(M_AXI_GP0_RID),
+        .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+        .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+        .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+        .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+        .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+        .MAXIGP0WID(M_AXI_GP0_WID),
+        .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+        .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+        .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+        .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+        .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+        .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+        .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+        .MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
+        .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+        .MAXIGP1ARID(M_AXI_GP1_ARID),
+        .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+        .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+        .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+        .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+        .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+        .MAXIGP1ARSIZE(\\^M_AXI_GP1_ARSIZE ),
+        .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+        .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+        .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+        .MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
+        .MAXIGP1AWID(M_AXI_GP1_AWID),
+        .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+        .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+        .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+        .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+        .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+        .MAXIGP1AWSIZE(\\^M_AXI_GP1_AWSIZE ),
+        .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+        .MAXIGP1BID(M_AXI_GP1_BID),
+        .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+        .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+        .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+        .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+        .MAXIGP1RID(M_AXI_GP1_RID),
+        .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+        .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+        .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+        .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+        .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+        .MAXIGP1WID(M_AXI_GP1_WID),
+        .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+        .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+        .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+        .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+        .MIO(buffered_MIO),
+        .PSCLK(buffered_PS_CLK),
+        .PSPORB(buffered_PS_PORB),
+        .PSSRSTB(buffered_PS_SRSTB),
+        .SAXIACPACLK(S_AXI_ACP_ACLK),
+        .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+        .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+        .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+        .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+        .SAXIACPARID(S_AXI_ACP_ARID),
+        .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+        .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+        .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+        .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+        .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+        .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+        .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+        .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+        .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+        .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+        .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+        .SAXIACPAWID(S_AXI_ACP_AWID),
+        .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+        .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+        .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+        .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+        .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+        .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+        .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+        .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+        .SAXIACPBID(S_AXI_ACP_BID),
+        .SAXIACPBREADY(S_AXI_ACP_BREADY),
+        .SAXIACPBRESP(S_AXI_ACP_BRESP),
+        .SAXIACPBVALID(S_AXI_ACP_BVALID),
+        .SAXIACPRDATA(S_AXI_ACP_RDATA),
+        .SAXIACPRID(S_AXI_ACP_RID),
+        .SAXIACPRLAST(S_AXI_ACP_RLAST),
+        .SAXIACPRREADY(S_AXI_ACP_RREADY),
+        .SAXIACPRRESP(S_AXI_ACP_RRESP),
+        .SAXIACPRVALID(S_AXI_ACP_RVALID),
+        .SAXIACPWDATA(S_AXI_ACP_WDATA),
+        .SAXIACPWID(S_AXI_ACP_WID),
+        .SAXIACPWLAST(S_AXI_ACP_WLAST),
+        .SAXIACPWREADY(S_AXI_ACP_WREADY),
+        .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+        .SAXIACPWVALID(S_AXI_ACP_WVALID),
+        .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+        .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+        .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+        .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+        .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+        .SAXIGP0ARID(S_AXI_GP0_ARID),
+        .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+        .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+        .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+        .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+        .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+        .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+        .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+        .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+        .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+        .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+        .SAXIGP0AWID(S_AXI_GP0_AWID),
+        .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+        .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+        .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+        .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+        .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+        .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+        .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+        .SAXIGP0BID(S_AXI_GP0_BID),
+        .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+        .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+        .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+        .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+        .SAXIGP0RID(S_AXI_GP0_RID),
+        .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+        .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+        .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+        .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+        .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+        .SAXIGP0WID(S_AXI_GP0_WID),
+        .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+        .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+        .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+        .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+        .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+        .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+        .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+        .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+        .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+        .SAXIGP1ARID(S_AXI_GP1_ARID),
+        .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+        .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+        .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+        .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+        .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+        .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+        .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+        .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+        .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+        .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+        .SAXIGP1AWID(S_AXI_GP1_AWID),
+        .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+        .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+        .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+        .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+        .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+        .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+        .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+        .SAXIGP1BID(S_AXI_GP1_BID),
+        .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+        .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+        .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+        .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+        .SAXIGP1RID(S_AXI_GP1_RID),
+        .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+        .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+        .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+        .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+        .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+        .SAXIGP1WID(S_AXI_GP1_WID),
+        .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+        .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+        .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+        .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+        .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+        .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+        .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+        .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+        .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+        .SAXIHP0ARID(S_AXI_HP0_ARID),
+        .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+        .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+        .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+        .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+        .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+        .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+        .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+        .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+        .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+        .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+        .SAXIHP0AWID(S_AXI_HP0_AWID),
+        .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+        .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+        .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+        .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+        .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+        .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+        .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+        .SAXIHP0BID(S_AXI_HP0_BID),
+        .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+        .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+        .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+        .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+        .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+        .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+        .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+        .SAXIHP0RID(S_AXI_HP0_RID),
+        .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+        .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+        .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+        .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+        .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+        .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+        .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+        .SAXIHP0WID(S_AXI_HP0_WID),
+        .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+        .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+        .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+        .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+        .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+        .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+        .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+        .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+        .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+        .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+        .SAXIHP1ARID(S_AXI_HP1_ARID),
+        .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+        .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+        .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+        .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+        .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+        .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+        .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+        .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+        .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+        .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+        .SAXIHP1AWID(S_AXI_HP1_AWID),
+        .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+        .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+        .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+        .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+        .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+        .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+        .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+        .SAXIHP1BID(S_AXI_HP1_BID),
+        .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+        .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+        .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+        .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+        .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+        .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+        .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+        .SAXIHP1RID(S_AXI_HP1_RID),
+        .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+        .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+        .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+        .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+        .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+        .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+        .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+        .SAXIHP1WID(S_AXI_HP1_WID),
+        .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+        .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+        .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+        .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+        .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+        .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+        .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+        .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+        .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+        .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+        .SAXIHP2ARID(S_AXI_HP2_ARID),
+        .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+        .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+        .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+        .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+        .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+        .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+        .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+        .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+        .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+        .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+        .SAXIHP2AWID(S_AXI_HP2_AWID),
+        .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+        .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+        .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+        .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+        .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+        .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+        .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+        .SAXIHP2BID(S_AXI_HP2_BID),
+        .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+        .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+        .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+        .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+        .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+        .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+        .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+        .SAXIHP2RID(S_AXI_HP2_RID),
+        .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+        .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+        .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+        .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+        .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+        .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+        .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+        .SAXIHP2WID(S_AXI_HP2_WID),
+        .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+        .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+        .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+        .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+        .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+        .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+        .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+        .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+        .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+        .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+        .SAXIHP3ARID(S_AXI_HP3_ARID),
+        .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+        .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+        .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+        .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+        .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+        .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+        .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+        .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+        .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+        .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+        .SAXIHP3AWID(S_AXI_HP3_AWID),
+        .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+        .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+        .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+        .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+        .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+        .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+        .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+        .SAXIHP3BID(S_AXI_HP3_BID),
+        .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+        .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+        .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+        .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+        .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+        .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+        .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+        .SAXIHP3RID(S_AXI_HP3_RID),
+        .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+        .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+        .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+        .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+        .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+        .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+        .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+        .SAXIHP3WID(S_AXI_HP3_WID),
+        .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+        .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+        .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+        .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+        .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_CLK_BIBUF
+       (.IO(buffered_PS_CLK),
+        .PAD(PS_CLK));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_PORB_BIBUF
+       (.IO(buffered_PS_PORB),
+        .PAD(PS_PORB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_SRSTB_BIBUF
+       (.IO(buffered_PS_SRSTB),
+        .PAD(PS_SRSTB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO0_CMD_T_INST_0
+       (.I0(SDIO0_CMD_T_n),
+        .O(SDIO0_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[0]_INST_0 
+       (.I0(SDIO0_DATA_T_n[0]),
+        .O(SDIO0_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[1]_INST_0 
+       (.I0(SDIO0_DATA_T_n[1]),
+        .O(SDIO0_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[2]_INST_0 
+       (.I0(SDIO0_DATA_T_n[2]),
+        .O(SDIO0_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[3]_INST_0 
+       (.I0(SDIO0_DATA_T_n[3]),
+        .O(SDIO0_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO1_CMD_T_INST_0
+       (.I0(SDIO1_CMD_T_n),
+        .O(SDIO1_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[0]_INST_0 
+       (.I0(SDIO1_DATA_T_n[0]),
+        .O(SDIO1_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[1]_INST_0 
+       (.I0(SDIO1_DATA_T_n[1]),
+        .O(SDIO1_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[2]_INST_0 
+       (.I0(SDIO1_DATA_T_n[2]),
+        .O(SDIO1_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[3]_INST_0 
+       (.I0(SDIO1_DATA_T_n[3]),
+        .O(SDIO1_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MISO_T_INST_0
+       (.I0(SPI0_MISO_T_n),
+        .O(SPI0_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MOSI_T_INST_0
+       (.I0(SPI0_MOSI_T_n),
+        .O(SPI0_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SCLK_T_INST_0
+       (.I0(SPI0_SCLK_T_n),
+        .O(SPI0_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SS_T_INST_0
+       (.I0(SPI0_SS_T_n),
+        .O(SPI0_SS_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MISO_T_INST_0
+       (.I0(SPI1_MISO_T_n),
+        .O(SPI1_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MOSI_T_INST_0
+       (.I0(SPI1_MOSI_T_n),
+        .O(SPI1_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SCLK_T_INST_0
+       (.I0(SPI1_SCLK_T_n),
+        .O(SPI1_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SS_T_INST_0
+       (.I0(SPI1_SS_T_n),
+        .O(SPI1_SS_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BUFG \\buffer_fclk_clk_0.FCLK_CLK_0_BUFG 
+       (.I(FCLK_CLK_unbuffered),
+        .O(FCLK_CLK0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[0].MIO_BIBUF 
+       (.IO(buffered_MIO[0]),
+        .PAD(MIO[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[10].MIO_BIBUF 
+       (.IO(buffered_MIO[10]),
+        .PAD(MIO[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[11].MIO_BIBUF 
+       (.IO(buffered_MIO[11]),
+        .PAD(MIO[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[12].MIO_BIBUF 
+       (.IO(buffered_MIO[12]),
+        .PAD(MIO[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[13].MIO_BIBUF 
+       (.IO(buffered_MIO[13]),
+        .PAD(MIO[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[14].MIO_BIBUF 
+       (.IO(buffered_MIO[14]),
+        .PAD(MIO[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[15].MIO_BIBUF 
+       (.IO(buffered_MIO[15]),
+        .PAD(MIO[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[16].MIO_BIBUF 
+       (.IO(buffered_MIO[16]),
+        .PAD(MIO[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[17].MIO_BIBUF 
+       (.IO(buffered_MIO[17]),
+        .PAD(MIO[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[18].MIO_BIBUF 
+       (.IO(buffered_MIO[18]),
+        .PAD(MIO[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[19].MIO_BIBUF 
+       (.IO(buffered_MIO[19]),
+        .PAD(MIO[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[1].MIO_BIBUF 
+       (.IO(buffered_MIO[1]),
+        .PAD(MIO[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[20].MIO_BIBUF 
+       (.IO(buffered_MIO[20]),
+        .PAD(MIO[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[21].MIO_BIBUF 
+       (.IO(buffered_MIO[21]),
+        .PAD(MIO[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[22].MIO_BIBUF 
+       (.IO(buffered_MIO[22]),
+        .PAD(MIO[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[23].MIO_BIBUF 
+       (.IO(buffered_MIO[23]),
+        .PAD(MIO[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[24].MIO_BIBUF 
+       (.IO(buffered_MIO[24]),
+        .PAD(MIO[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[25].MIO_BIBUF 
+       (.IO(buffered_MIO[25]),
+        .PAD(MIO[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[26].MIO_BIBUF 
+       (.IO(buffered_MIO[26]),
+        .PAD(MIO[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[27].MIO_BIBUF 
+       (.IO(buffered_MIO[27]),
+        .PAD(MIO[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[28].MIO_BIBUF 
+       (.IO(buffered_MIO[28]),
+        .PAD(MIO[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[29].MIO_BIBUF 
+       (.IO(buffered_MIO[29]),
+        .PAD(MIO[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[2].MIO_BIBUF 
+       (.IO(buffered_MIO[2]),
+        .PAD(MIO[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[30].MIO_BIBUF 
+       (.IO(buffered_MIO[30]),
+        .PAD(MIO[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[31].MIO_BIBUF 
+       (.IO(buffered_MIO[31]),
+        .PAD(MIO[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[32].MIO_BIBUF 
+       (.IO(buffered_MIO[32]),
+        .PAD(MIO[32]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[33].MIO_BIBUF 
+       (.IO(buffered_MIO[33]),
+        .PAD(MIO[33]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[34].MIO_BIBUF 
+       (.IO(buffered_MIO[34]),
+        .PAD(MIO[34]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[35].MIO_BIBUF 
+       (.IO(buffered_MIO[35]),
+        .PAD(MIO[35]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[36].MIO_BIBUF 
+       (.IO(buffered_MIO[36]),
+        .PAD(MIO[36]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[37].MIO_BIBUF 
+       (.IO(buffered_MIO[37]),
+        .PAD(MIO[37]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[38].MIO_BIBUF 
+       (.IO(buffered_MIO[38]),
+        .PAD(MIO[38]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[39].MIO_BIBUF 
+       (.IO(buffered_MIO[39]),
+        .PAD(MIO[39]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[3].MIO_BIBUF 
+       (.IO(buffered_MIO[3]),
+        .PAD(MIO[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[40].MIO_BIBUF 
+       (.IO(buffered_MIO[40]),
+        .PAD(MIO[40]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[41].MIO_BIBUF 
+       (.IO(buffered_MIO[41]),
+        .PAD(MIO[41]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[42].MIO_BIBUF 
+       (.IO(buffered_MIO[42]),
+        .PAD(MIO[42]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[43].MIO_BIBUF 
+       (.IO(buffered_MIO[43]),
+        .PAD(MIO[43]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[44].MIO_BIBUF 
+       (.IO(buffered_MIO[44]),
+        .PAD(MIO[44]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[45].MIO_BIBUF 
+       (.IO(buffered_MIO[45]),
+        .PAD(MIO[45]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[46].MIO_BIBUF 
+       (.IO(buffered_MIO[46]),
+        .PAD(MIO[46]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[47].MIO_BIBUF 
+       (.IO(buffered_MIO[47]),
+        .PAD(MIO[47]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[48].MIO_BIBUF 
+       (.IO(buffered_MIO[48]),
+        .PAD(MIO[48]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[49].MIO_BIBUF 
+       (.IO(buffered_MIO[49]),
+        .PAD(MIO[49]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[4].MIO_BIBUF 
+       (.IO(buffered_MIO[4]),
+        .PAD(MIO[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[50].MIO_BIBUF 
+       (.IO(buffered_MIO[50]),
+        .PAD(MIO[50]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[51].MIO_BIBUF 
+       (.IO(buffered_MIO[51]),
+        .PAD(MIO[51]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[52].MIO_BIBUF 
+       (.IO(buffered_MIO[52]),
+        .PAD(MIO[52]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[53].MIO_BIBUF 
+       (.IO(buffered_MIO[53]),
+        .PAD(MIO[53]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[5].MIO_BIBUF 
+       (.IO(buffered_MIO[5]),
+        .PAD(MIO[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[6].MIO_BIBUF 
+       (.IO(buffered_MIO[6]),
+        .PAD(MIO[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[7].MIO_BIBUF 
+       (.IO(buffered_MIO[7]),
+        .PAD(MIO[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[8].MIO_BIBUF 
+       (.IO(buffered_MIO[8]),
+        .PAD(MIO[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[9].MIO_BIBUF 
+       (.IO(buffered_MIO[9]),
+        .PAD(MIO[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[0].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[0]),
+        .PAD(DDR_BankAddr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[1].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[1]),
+        .PAD(DDR_BankAddr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[2].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[2]),
+        .PAD(DDR_BankAddr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[0].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[0]),
+        .PAD(DDR_Addr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[10].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[10]),
+        .PAD(DDR_Addr[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[11].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[11]),
+        .PAD(DDR_Addr[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[12].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[12]),
+        .PAD(DDR_Addr[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[13].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[13]),
+        .PAD(DDR_Addr[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[14].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[14]),
+        .PAD(DDR_Addr[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[1].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[1]),
+        .PAD(DDR_Addr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[2].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[2]),
+        .PAD(DDR_Addr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[3].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[3]),
+        .PAD(DDR_Addr[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[4].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[4]),
+        .PAD(DDR_Addr[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[5].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[5]),
+        .PAD(DDR_Addr[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[6].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[6]),
+        .PAD(DDR_Addr[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[7].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[7]),
+        .PAD(DDR_Addr[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[8].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[8]),
+        .PAD(DDR_Addr[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[9].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[9]),
+        .PAD(DDR_Addr[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[0].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[0]),
+        .PAD(DDR_DM[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[1].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[1]),
+        .PAD(DDR_DM[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[2].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[2]),
+        .PAD(DDR_DM[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[3].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[3]),
+        .PAD(DDR_DM[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[0].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[0]),
+        .PAD(DDR_DQ[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[10].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[10]),
+        .PAD(DDR_DQ[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[11].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[11]),
+        .PAD(DDR_DQ[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[12].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[12]),
+        .PAD(DDR_DQ[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[13].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[13]),
+        .PAD(DDR_DQ[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[14].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[14]),
+        .PAD(DDR_DQ[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[15].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[15]),
+        .PAD(DDR_DQ[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[16].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[16]),
+        .PAD(DDR_DQ[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[17].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[17]),
+        .PAD(DDR_DQ[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[18].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[18]),
+        .PAD(DDR_DQ[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[19].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[19]),
+        .PAD(DDR_DQ[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[1].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[1]),
+        .PAD(DDR_DQ[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[20].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[20]),
+        .PAD(DDR_DQ[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[21].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[21]),
+        .PAD(DDR_DQ[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[22].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[22]),
+        .PAD(DDR_DQ[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[23].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[23]),
+        .PAD(DDR_DQ[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[24].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[24]),
+        .PAD(DDR_DQ[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[25].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[25]),
+        .PAD(DDR_DQ[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[26].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[26]),
+        .PAD(DDR_DQ[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[27].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[27]),
+        .PAD(DDR_DQ[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[28].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[28]),
+        .PAD(DDR_DQ[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[29].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[29]),
+        .PAD(DDR_DQ[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[2].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[2]),
+        .PAD(DDR_DQ[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[30].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[30]),
+        .PAD(DDR_DQ[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[31].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[31]),
+        .PAD(DDR_DQ[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[3].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[3]),
+        .PAD(DDR_DQ[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[4].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[4]),
+        .PAD(DDR_DQ[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[5].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[5]),
+        .PAD(DDR_DQ[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[6].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[6]),
+        .PAD(DDR_DQ[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[7].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[7]),
+        .PAD(DDR_DQ[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[8].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[8]),
+        .PAD(DDR_DQ[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[9].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[9]),
+        .PAD(DDR_DQ[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[0].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[0]),
+        .PAD(DDR_DQS_n[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[1].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[1]),
+        .PAD(DDR_DQS_n[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[2].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[2]),
+        .PAD(DDR_DQS_n[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[3].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[3]),
+        .PAD(DDR_DQS_n[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[0].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[0]),
+        .PAD(DDR_DQS[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[1].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[1]),
+        .PAD(DDR_DQS[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[2].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[2]),
+        .PAD(DDR_DQS[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[3].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[3]),
+        .PAD(DDR_DQS[3]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_0
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[0] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_1
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_10
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_11
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_12
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_13
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_14
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_15
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_16
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_17
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_18
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_19
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_2
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_20
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_21
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_22
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_23
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_3
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[7] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_4
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[6] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_5
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[5] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_6
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[4] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_7
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[3] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_8
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[2] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_9
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:01 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_stub.v
+// Design      : design_1_axi_gpio_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_gpio,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio2_io_i)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio2_io_i[3:0]"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [3:0]gpio_io_i;
+  input [3:0]gpio2_io_i;
+endmodule
+"
+" 
+
+
+// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, ""Critical
+// Applications""). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
+// IP Revision: 1
+
+`timescale 1ns/1ps
+
+module design_1_processing_system7_0_0 (
+GPIO_I, 
+GPIO_O, 
+GPIO_T, 
+SDIO0_WP, 
+TTC0_WAVE0_OUT, 
+TTC0_WAVE1_OUT, 
+TTC0_WAVE2_OUT, 
+USB0_PORT_INDCTL, 
+USB0_VBUS_PWRSELECT, 
+USB0_VBUS_PWRFAULT, 
+M_AXI_GP0_ARVALID, 
+M_AXI_GP0_AWVALID, 
+M_AXI_GP0_BREADY, 
+M_AXI_GP0_RREADY, 
+M_AXI_GP0_WLAST, 
+M_AXI_GP0_WVALID, 
+M_AXI_GP0_ARID, 
+M_AXI_GP0_AWID, 
+M_AXI_GP0_WID, 
+M_AXI_GP0_ARBURST, 
+M_AXI_GP0_ARLOCK, 
+M_AXI_GP0_ARSIZE, 
+M_AXI_GP0_AWBURST, 
+M_AXI_GP0_AWLOCK, 
+M_AXI_GP0_AWSIZE, 
+M_AXI_GP0_ARPROT, 
+M_AXI_GP0_AWPROT, 
+M_AXI_GP0_ARADDR, 
+M_AXI_GP0_AWADDR, 
+M_AXI_GP0_WDATA, 
+M_AXI_GP0_ARCACHE, 
+M_AXI_GP0_ARLEN, 
+M_AXI_GP0_ARQOS, 
+M_AXI_GP0_AWCACHE, 
+M_AXI_GP0_AWLEN, 
+M_AXI_GP0_AWQOS, 
+M_AXI_GP0_WSTRB, 
+M_AXI_GP0_ACLK, 
+M_AXI_GP0_ARREADY, 
+M_AXI_GP0_AWREADY, 
+M_AXI_GP0_BVALID, 
+M_AXI_GP0_RLAST, 
+M_AXI_GP0_RVALID, 
+M_AXI_GP0_WREADY, 
+M_AXI_GP0_BID, 
+M_AXI_GP0_RID, 
+M_AXI_GP0_BRESP, 
+M_AXI_GP0_RRESP, 
+M_AXI_GP0_RDATA, 
+FCLK_CLK0, 
+FCLK_RESET0_N, 
+MIO, 
+DDR_CAS_n, 
+DDR_CKE, 
+DDR_Clk_n, 
+DDR_Clk, 
+DDR_CS_n, 
+DDR_DRSTB, 
+DDR_ODT, 
+DDR_RAS_n, 
+DDR_WEB, 
+DDR_BankAddr, 
+DDR_Addr, 
+DDR_VRN, 
+DDR_VRP, 
+DDR_DM, 
+DDR_DQ, 
+DDR_DQS_n, 
+DDR_DQS, 
+PS_SRSTB, 
+PS_CLK, 
+PS_PORB 
+);
+input [63 : 0] GPIO_I;
+output [63 : 0] GPIO_O;
+output [63 : 0] GPIO_T;
+input SDIO0_WP;
+output TTC0_WAVE0_OUT;
+output TTC0_WAVE1_OUT;
+output TTC0_WAVE2_OUT;
+output [1 : 0] USB0_PORT_INDCTL;
+output USB0_VBUS_PWRSELECT;
+input USB0_VBUS_PWRFAULT;
+output M_AXI_GP0_ARVALID;
+output M_AXI_GP0_AWVALID;
+output M_AXI_GP0_BREADY;
+output M_AXI_GP0_RREADY;
+output M_AXI_GP0_WLAST;
+output M_AXI_GP0_WVALID;
+output [11 : 0] M_AXI_GP0_ARID;
+output [11 : 0] M_AXI_GP0_AWID;
+output [11 : 0] M_AXI_GP0_WID;
+output [1 : 0] M_AXI_GP0_ARBURST;
+output [1 : 0] M_AXI_GP0_ARLOCK;
+output [2 : 0] M_AXI_GP0_ARSIZE;
+output [1 : 0] M_AXI_GP0_AWBURST;
+output [1 : 0] M_AXI_GP0_AWLOCK;
+output [2 : 0] M_AXI_GP0_AWSIZE;
+output [2 : 0] M_AXI_GP0_ARPROT;
+output [2 : 0] M_AXI_GP0_AWPROT;
+output [31 : 0] M_AXI_GP0_ARADDR;
+output [31 : 0] M_AXI_GP0_AWADDR;
+output [31 : 0] M_AXI_GP0_WDATA;
+output [3 : 0] M_AXI_GP0_ARCACHE;
+output [3 : 0] M_AXI_GP0_ARLEN;
+output [3 : 0] M_AXI_GP0_ARQOS;
+output [3 : 0] M_AXI_GP0_AWCACHE;
+output [3 : 0] M_AXI_GP0_AWLEN;
+output [3 : 0] M_AXI_GP0_AWQOS;
+output [3 : 0] M_AXI_GP0_WSTRB;
+input M_AXI_GP0_ACLK;
+input M_AXI_GP0_ARREADY;
+input M_AXI_GP0_AWREADY;
+input M_AXI_GP0_BVALID;
+input M_AXI_GP0_RLAST;
+input M_AXI_GP0_RVALID;
+input M_AXI_GP0_WREADY;
+input [11 : 0] M_AXI_GP0_BID;
+input [11 : 0] M_AXI_GP0_RID;
+input [1 : 0] M_AXI_GP0_BRESP;
+input [1 : 0] M_AXI_GP0_RRESP;
+input [31 : 0] M_AXI_GP0_RDATA;
+output FCLK_CLK0;
+output FCLK_RESET0_N;
+input [53 : 0] MIO;
+input DDR_CAS_n;
+input DDR_CKE;
+input DDR_Clk_n;
+input DDR_Clk;
+input DDR_CS_n;
+input DDR_DRSTB;
+input DDR_ODT;
+input DDR_RAS_n;
+input DDR_WEB;
+input [2 : 0] DDR_BankAddr;
+input [14 : 0] DDR_Addr;
+input DDR_VRN;
+input DDR_VRP;
+input [3 : 0] DDR_DM;
+input [31 : 0] DDR_DQ;
+input [3 : 0] DDR_DQS_n;
+input [3 : 0] DDR_DQS;
+input PS_SRSTB;
+input PS_CLK;
+input PS_PORB;
+
+  processing_system7_bfm_v2_0_5_processing_system7_bfm #(
+    .C_USE_M_AXI_GP0(1),
+    .C_USE_M_AXI_GP1(0),
+    .C_USE_S_AXI_ACP(0),
+    .C_USE_S_AXI_GP0(0),
+    .C_USE_S_AXI_GP1(0),
+    .C_USE_S_AXI_HP0(0),
+    .C_USE_S_AXI_HP1(0),
+    .C_USE_S_AXI_HP2(0),
+    .C_USE_S_AXI_HP3(0),
+    .C_S_AXI_HP0_DATA_WIDTH(64),
+    .C_S_AXI_HP1_DATA_WIDTH(64),
+    .C_S_AXI_HP2_DATA_WIDTH(64),
+    .C_S_AXI_HP3_DATA_WIDTH(64),
+    .C_HIGH_OCM_EN(0),
+    .C_FCLK_CLK0_FREQ(100.0),
+    .C_FCLK_CLK1_FREQ(10.0),
+    .C_FCLK_CLK2_FREQ(10.0),
+    .C_FCLK_CLK3_FREQ(10.0),
+\t.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
+\t.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
+\t.C_M_AXI_GP0_THREAD_ID_WIDTH (12), 
+\t.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
+  ) inst (
+    .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+    .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+    .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+    .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+    .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+    .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+    .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+    .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+    .M_AXI_GP0_WID(M_AXI_GP0_WID),
+    .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+    .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+    .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+    .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+    .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+    .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+    .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+    .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+    .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+    .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+    .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+    .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+    .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+    .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+    .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+    .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+    .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+    .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+    .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+    .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+    .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+    .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+    .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+    .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+    .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+    .M_AXI_GP0_BID(M_AXI_GP0_BID),
+    .M_AXI_GP0_RID(M_AXI_GP0_RID),
+    .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+    .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+    .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+    .M_AXI_GP1_ARVALID(),
+    .M_AXI_GP1_AWVALID(),
+    .M_AXI_GP1_BREADY(),
+    .M_AXI_GP1_RREADY(),
+    .M_AXI_GP1_WLAST(),
+    .M_AXI_GP1_WVALID(),
+    .M_AXI_GP1_ARID(),
+    .M_AXI_GP1_AWID(),
+    .M_AXI_GP1_WID(),
+    .M_AXI_GP1_ARBURST(),
+    .M_AXI_GP1_ARLOCK(),
+    .M_AXI_GP1_ARSIZE(),
+    .M_AXI_GP1_AWBURST(),
+    .M_AXI_GP1_AWLOCK(),
+    .M_AXI_GP1_AWSIZE(),
+    .M_AXI_GP1_ARPROT(),
+    .M_AXI_GP1_AWPROT(),
+    .M_AXI_GP1_ARADDR(),
+    .M_AXI_GP1_AWADDR(),
+    .M_AXI_GP1_WDATA(),
+    .M_AXI_GP1_ARCACHE(),
+    .M_AXI_GP1_ARLEN(),
+    .M_AXI_GP1_ARQOS(),
+    .M_AXI_GP1_AWCACHE(),
+    .M_AXI_GP1_AWLEN(),
+    .M_AXI_GP1_AWQOS(),
+    .M_AXI_GP1_WSTRB(),
+    .M_AXI_GP1_ACLK(1\'B0),
+    .M_AXI_GP1_ARREADY(1\'B0),
+    .M_AXI_GP1_AWREADY(1\'B0),
+    .M_AXI_GP1_BVALID(1\'B0),
+    .M_AXI_GP1_RLAST(1\'B0),
+    .M_AXI_GP1_RVALID(1\'B0),
+    .M_AXI_GP1_WREADY(1\'B0),
+    .M_AXI_GP1_BID(12\'B0),
+    .M_AXI_GP1_RID(12\'B0),
+    .M_AXI_GP1_BRESP(2\'B0),
+    .M_AXI_GP1_RRESP(2\'B0),
+    .M_AXI_GP1_RDATA(32\'B0),
+    .S_AXI_GP0_ARREADY(),
+    .S_AXI_GP0_AWREADY(),
+    .S_AXI_GP0_BVALID(),
+    .S_AXI_GP0_RLAST(),
+    .S_AXI_GP0_RVALID(),
+    .S_AXI_GP0_WREADY(),
+    .S_AXI_GP0_BRESP(),
+    .S_AXI_GP0_RRESP(),
+    .S_AXI_GP0_RDATA(),
+    .S_AXI_GP0_BID(),
+    .S_AXI_GP0_RID(),
+    .S_AXI_GP0_ACLK(1\'B0),
+    .S_AXI_GP0_ARVALID(1\'B0),
+    .S_AXI_GP0_AWVALID(1\'B0),
+    .S_AXI_GP0_BREADY(1\'B0),
+    .S_AXI_GP0_RREADY(1\'B0),
+    .S_AXI_GP0_WLAST(1\'B0),
+    .S_AXI_GP0_WVALID(1\'B0),
+    .S_AXI_GP0_ARBURST(2\'B0),
+    .S_AXI_GP0_ARLOCK(2\'B0),
+    .S_AXI_GP0_ARSIZE(3\'B0),
+    .S_AXI_GP0_AWBURST(2\'B0),
+    .S_AXI_GP0_AWLOCK(2\'B0),
+    .S_AXI_GP0_AWSIZE(3\'B0),
+    .S_AXI_GP0_ARPROT(3\'B0),
+    .S_AXI_GP0_AWPROT(3\'B0),
+    .S_AXI_GP0_ARADDR(32\'B0),
+    .S_AXI_GP0_AWADDR(32\'B0),
+    .S_AXI_GP0_WDATA(32\'B0),
+    .S_AXI_GP0_ARCACHE(4\'B0),
+    .S_AXI_GP0_ARLEN(4\'B0),
+    .S_AXI_GP0_ARQOS(4\'B0),
+    .S_AXI_GP0_AWCACHE(4\'B0),
+    .S_AXI_GP0_AWLEN(4\'B0),
+    .S_AXI_GP0_AWQOS(4\'B0),
+    .S_AXI_GP0_WSTRB(4\'B0),
+    .S_AXI_GP0_ARID(6\'B0),
+    .S_AXI_GP0_AWID(6\'B0),
+    .S_AXI_GP0_WID(6\'B0),
+    .S_AXI_GP1_ARREADY(),
+    .S_AXI_GP1_AWREADY(),
+    .S_AXI_GP1_BVALID(),
+    .S_AXI_GP1_RLAST(),
+    .S_AXI_GP1_RVALID(),
+    .S_AXI_GP1_WREADY(),
+    .S_AXI_GP1_BRESP(),
+    .S_AXI_GP1_RRESP(),
+    .S_AXI_GP1_RDATA(),
+    .S_AXI_GP1_BID(),
+    .S_AXI_GP1_RID(),
+    .S_AXI_GP1_ACLK(1\'B0),
+    .S_AXI_GP1_ARVALID(1\'B0),
+    .S_AXI_GP1_AWVALID(1\'B0),
+    .S_AXI_GP1_BREADY(1\'B0),
+    .S_AXI_GP1_RREADY(1\'B0),
+    .S_AXI_GP1_WLAST(1\'B0),
+    .S_AXI_GP1_WVALID(1\'B0),
+    .S_AXI_GP1_ARBURST(2\'B0),
+    .S_AXI_GP1_ARLOCK(2\'B0),
+    .S_AXI_GP1_ARSIZE(3\'B0),
+    .S_AXI_GP1_AWBURST(2\'B0),
+    .S_AXI_GP1_AWLOCK(2\'B0),
+    .S_AXI_GP1_AWSIZE(3\'B0),
+    .S_AXI_GP1_ARPROT(3\'B0),
+    .S_AXI_GP1_AWPROT(3\'B0),
+    .S_AXI_GP1_ARADDR(32\'B0),
+    .S_AXI_GP1_AWADDR(32\'B0),
+    .S_AXI_GP1_WDATA(32\'B0),
+    .S_AXI_GP1_ARCACHE(4\'B0),
+    .S_AXI_GP1_ARLEN(4\'B0),
+    .S_AXI_GP1_ARQOS(4\'B0),
+    .S_AXI_GP1_AWCACHE(4\'B0),
+    .S_AXI_GP1_AWLEN(4\'B0),
+    .S_AXI_GP1_AWQOS(4\'B0),
+    .S_AXI_GP1_WSTRB(4\'B0),
+    .S_AXI_GP1_ARID(6\'B0),
+    .S_AXI_GP1_AWID(6\'B0),
+    .S_AXI_GP1_WID(6\'B0),
+    .S_AXI_ACP_ARREADY(),
+    .S_AXI_ACP_AWREADY(),
+    .S_AXI_ACP_BVALID(),
+    .S_AXI_ACP_RLAST(),
+    .S_AXI_ACP_RVALID(),
+    .S_AXI_ACP_WREADY(),
+    .S_AXI_ACP_BRESP(),
+    .S_AXI_ACP_RRESP(),
+    .S_AXI_ACP_BID(),
+    .S_AXI_ACP_RID(),
+    .S_AXI_ACP_RDATA(),
+    .S_AXI_ACP_ACLK(1\'B0),
+    .S_AXI_ACP_ARVALID(1\'B0),
+    .S_AXI_ACP_AWVALID(1\'B0),
+    .S_AXI_ACP_BREADY(1\'B0),
+    .S_AXI_ACP_RREADY(1\'B0),
+    .S_AXI_ACP_WLAST(1\'B0),
+    .S_AXI_ACP_WVALID(1\'B0),
+    .S_AXI_ACP_ARID(3\'B0),
+    .S_AXI_ACP_ARPROT(3\'B0),
+    .S_AXI_ACP_AWID(3\'B0),
+    .S_AXI_ACP_AWPROT(3\'B0),
+    .S_AXI_ACP_WID(3\'B0),
+    .S_AXI_ACP_ARADDR(32\'B0),
+    .S_AXI_ACP_AWADDR(32\'B0),
+    .S_AXI_ACP_ARCACHE(4\'B0),
+    .S_AXI_ACP_ARLEN(4\'B0),
+    .S_AXI_ACP_ARQOS(4\'B0),
+    .S_AXI_ACP_AWCACHE(4\'B0),
+    .S_AXI_ACP_AWLEN(4\'B0),
+    .S_AXI_ACP_AWQOS(4\'B0),
+    .S_AXI_ACP_ARBURST(2\'B0),
+    .S_AXI_ACP_ARLOCK(2\'B0),
+    .S_AXI_ACP_ARSIZE(3\'B0),
+    .S_AXI_ACP_AWBURST(2\'B0),
+    .S_AXI_ACP_AWLOCK(2\'B0),
+    .S_AXI_ACP_AWSIZE(3\'B0),
+    .S_AXI_ACP_ARUSER(5\'B0),
+    .S_AXI_ACP_AWUSER(5\'B0),
+    .S_AXI_ACP_WDATA(64\'B0),
+    .S_AXI_ACP_WSTRB(8\'B0),
+    .S_AXI_HP0_ARREADY(),
+    .S_AXI_HP0_AWREADY(),
+    .S_AXI_HP0_BVALID(),
+    .S_AXI_HP0_RLAST(),
+    .S_AXI_HP0_RVALID(),
+    .S_AXI_HP0_WREADY(),
+    .S_AXI_HP0_BRESP(),
+    .S_AXI_HP0_RRESP(),
+    .S_AXI_HP0_BID(),
+    .S_AXI_HP0_RID(),
+    .S_AXI_HP0_RDATA(),
+    .S_AXI_HP0_ACLK(1\'B0),
+    .S_AXI_HP0_ARVALID(1\'B0),
+    .S_AXI_HP0_AWVALID(1\'B0),
+    .S_AXI_HP0_BREADY(1\'B0),
+    .S_AXI_HP0_RREADY(1\'B0),
+    .S_AXI_HP0_WLAST(1\'B0),
+    .S_AXI_HP0_WVALID(1\'B0),
+    .S_AXI_HP0_ARBURST(2\'B0),
+    .S_AXI_HP0_ARLOCK(2\'B0),
+    .S_AXI_HP0_ARSIZE(3\'B0),
+    .S_AXI_HP0_AWBURST(2\'B0),
+    .S_AXI_HP0_AWLOCK(2\'B0),
+    .S_AXI_HP0_AWSIZE(3\'B0),
+    .S_AXI_HP0_ARPROT(3\'B0),
+    .S_AXI_HP0_AWPROT(3\'B0),
+    .S_AXI_HP0_ARADDR(32\'B0),
+    .S_AXI_HP0_AWADDR(32\'B0),
+    .S_AXI_HP0_ARCACHE(4\'B0),
+    .S_AXI_HP0_ARLEN(4\'B0),
+    .S_AXI_HP0_ARQOS(4\'B0),
+    .S_AXI_HP0_AWCACHE(4\'B0),
+    .S_AXI_HP0_AWLEN(4\'B0),
+    .S_AXI_HP0_AWQOS(4\'B0),
+    .S_AXI_HP0_ARID(6\'B0),
+    .S_AXI_HP0_AWID(6\'B0),
+    .S_AXI_HP0_WID(6\'B0),
+    .S_AXI_HP0_WDATA(64\'B0),
+    .S_AXI_HP0_WSTRB(8\'B0),
+    .S_AXI_HP1_ARREADY(),
+    .S_AXI_HP1_AWREADY(),
+    .S_AXI_HP1_BVALID(),
+    .S_AXI_HP1_RLAST(),
+    .S_AXI_HP1_RVALID(),
+    .S_AXI_HP1_WREADY(),
+    .S_AXI_HP1_BRESP(),
+    .S_AXI_HP1_RRESP(),
+    .S_AXI_HP1_BID(),
+    .S_AXI_HP1_RID(),
+    .S_AXI_HP1_RDATA(),
+    .S_AXI_HP1_ACLK(1\'B0),
+    .S_AXI_HP1_ARVALID(1\'B0),
+    .S_AXI_HP1_AWVALID(1\'B0),
+    .S_AXI_HP1_BREADY(1\'B0),
+    .S_AXI_HP1_RREADY(1\'B0),
+    .S_AXI_HP1_WLAST(1\'B0),
+    .S_AXI_HP1_WVALID(1\'B0),
+    .S_AXI_HP1_ARBURST(2\'B0),
+    .S_AXI_HP1_ARLOCK(2\'B0),
+    .S_AXI_HP1_ARSIZE(3\'B0),
+    .S_AXI_HP1_AWBURST(2\'B0),
+    .S_AXI_HP1_AWLOCK(2\'B0),
+    .S_AXI_HP1_AWSIZE(3\'B0),
+    .S_AXI_HP1_ARPROT(3\'B0),
+    .S_AXI_HP1_AWPROT(3\'B0),
+    .S_AXI_HP1_ARADDR(32\'B0),
+    .S_AXI_HP1_AWADDR(32\'B0),
+    .S_AXI_HP1_ARCACHE(4\'B0),
+    .S_AXI_HP1_ARLEN(4\'B0),
+    .S_AXI_HP1_ARQOS(4\'B0),
+    .S_AXI_HP1_AWCACHE(4\'B0),
+    .S_AXI_HP1_AWLEN(4\'B0),
+    .S_AXI_HP1_AWQOS(4\'B0),
+    .S_AXI_HP1_ARID(6\'B0),
+    .S_AXI_HP1_AWID(6\'B0),
+    .S_AXI_HP1_WID(6\'B0),
+    .S_AXI_HP1_WDATA(64\'B0),
+    .S_AXI_HP1_WSTRB(8\'B0),
+    .S_AXI_HP2_ARREADY(),
+    .S_AXI_HP2_AWREADY(),
+    .S_AXI_HP2_BVALID(),
+    .S_AXI_HP2_RLAST(),
+    .S_AXI_HP2_RVALID(),
+    .S_AXI_HP2_WREADY(),
+    .S_AXI_HP2_BRESP(),
+    .S_AXI_HP2_RRESP(),
+    .S_AXI_HP2_BID(),
+    .S_AXI_HP2_RID(),
+    .S_AXI_HP2_RDATA(),
+    .S_AXI_HP2_ACLK(1\'B0),
+    .S_AXI_HP2_ARVALID(1\'B0),
+    .S_AXI_HP2_AWVALID(1\'B0),
+    .S_AXI_HP2_BREADY(1\'B0),
+    .S_AXI_HP2_RREADY(1\'B0),
+    .S_AXI_HP2_WLAST(1\'B0),
+    .S_AXI_HP2_WVALID(1\'B0),
+    .S_AXI_HP2_ARBURST(2\'B0),
+    .S_AXI_HP2_ARLOCK(2\'B0),
+    .S_AXI_HP2_ARSIZE(3\'B0),
+    .S_AXI_HP2_AWBURST(2\'B0),
+    .S_AXI_HP2_AWLOCK(2\'B0),
+    .S_AXI_HP2_AWSIZE(3\'B0),
+    .S_AXI_HP2_ARPROT(3\'B0),
+    .S_AXI_HP2_AWPROT(3\'B0),
+    .S_AXI_HP2_ARADDR(32\'B0),
+    .S_AXI_HP2_AWADDR(32\'B0),
+    .S_AXI_HP2_ARCACHE(4\'B0),
+    .S_AXI_HP2_ARLEN(4\'B0),
+    .S_AXI_HP2_ARQOS(4\'B0),
+    .S_AXI_HP2_AWCACHE(4\'B0),
+    .S_AXI_HP2_AWLEN(4\'B0),
+    .S_AXI_HP2_AWQOS(4\'B0),
+    .S_AXI_HP2_ARID(6\'B0),
+    .S_AXI_HP2_AWID(6\'B0),
+    .S_AXI_HP2_WID(6\'B0),
+    .S_AXI_HP2_WDATA(64\'B0),
+    .S_AXI_HP2_WSTRB(8\'B0),
+    .S_AXI_HP3_ARREADY(),
+    .S_AXI_HP3_AWREADY(),
+    .S_AXI_HP3_BVALID(),
+    .S_AXI_HP3_RLAST(),
+    .S_AXI_HP3_RVALID(),
+    .S_AXI_HP3_WREADY(),
+    .S_AXI_HP3_BRESP(),
+    .S_AXI_HP3_RRESP(),
+    .S_AXI_HP3_BID(),
+    .S_AXI_HP3_RID(),
+    .S_AXI_HP3_RDATA(),
+    .S_AXI_HP3_ACLK(1\'B0),
+    .S_AXI_HP3_ARVALID(1\'B0),
+    .S_AXI_HP3_AWVALID(1\'B0),
+    .S_AXI_HP3_BREADY(1\'B0),
+    .S_AXI_HP3_RREADY(1\'B0),
+    .S_AXI_HP3_WLAST(1\'B0),
+    .S_AXI_HP3_WVALID(1\'B0),
+    .S_AXI_HP3_ARBURST(2\'B0),
+    .S_AXI_HP3_ARLOCK(2\'B0),
+    .S_AXI_HP3_ARSIZE(3\'B0),
+    .S_AXI_HP3_AWBURST(2\'B0),
+    .S_AXI_HP3_AWLOCK(2\'B0),
+    .S_AXI_HP3_AWSIZE(3\'B0),
+    .S_AXI_HP3_ARPROT(3\'B0),
+    .S_AXI_HP3_AWPROT(3\'B0),
+    .S_AXI_HP3_ARADDR(32\'B0),
+    .S_AXI_HP3_AWADDR(32\'B0),
+    .S_AXI_HP3_ARCACHE(4\'B0),
+    .S_AXI_HP3_ARLEN(4\'B0),
+    .S_AXI_HP3_ARQOS(4\'B0),
+    .S_AXI_HP3_AWCACHE(4\'B0),
+    .S_AXI_HP3_AWLEN(4\'B0),
+    .S_AXI_HP3_AWQOS(4\'B0),
+    .S_AXI_HP3_ARID(6\'B0),
+    .S_AXI_HP3_AWID(6\'B0),
+    .S_AXI_HP3_WID(6\'B0),
+    .S_AXI_HP3_WDATA(64\'B0),
+    .S_AXI_HP3_WSTRB(8\'B0),
+    .FCLK_CLK0(FCLK_CLK0),
+\t
+    .FCLK_CLK1(),
+\t
+    .FCLK_CLK2(),
+\t
+    .FCLK_CLK3(),
+    .FCLK_RESET0_N(FCLK_RESET0_N),
+    .FCLK_RESET1_N(),
+    .FCLK_RESET2_N(),
+    .FCLK_RESET3_N(),
+    .IRQ_F2P(16\'B0),
+    .PS_SRSTB(PS_SRSTB),
+    .PS_CLK(PS_CLK),
+    .PS_PORB(PS_PORB)
+  );
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Tue Feb 14 01:38:43 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               D:/Work/vivado/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+module design_1_processing_system7_0_0(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT, 
+  TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, 
+  USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, 
+  M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, 
+  M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, 
+  DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, 
+  DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin=""GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"" */;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input SDIO0_WP;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output FCLK_CLK0;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_apis.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Set of Zynq BFM APIs that are used for writing tests.
+ *                
+ *****************************************************************************/
+
+  /* API for setting the STOP_ON_ERROR*/  
+  task automatic set_stop_on_error;
+    input LEVEL;
+    begin
+      $display(""[%0d] : %0s : Setting Stop On Error as %0b"",$time, DISP_INFO, LEVEL);
+      STOP_ON_ERROR = LEVEL;
+      M_AXI_GP0.master.set_stop_on_error(LEVEL);
+      M_AXI_GP1.master.set_stop_on_error(LEVEL);
+      S_AXI_GP0.slave.set_stop_on_error(LEVEL);
+      S_AXI_GP1.slave.set_stop_on_error(LEVEL);
+      S_AXI_HP0.slave.set_stop_on_error(LEVEL);
+      S_AXI_HP1.slave.set_stop_on_error(LEVEL);
+      S_AXI_HP2.slave.set_stop_on_error(LEVEL);
+      S_AXI_HP3.slave.set_stop_on_error(LEVEL);
+      S_AXI_ACP.slave.set_stop_on_error(LEVEL);
+      M_AXI_GP0.STOP_ON_ERROR = LEVEL;
+      M_AXI_GP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_GP0.STOP_ON_ERROR = LEVEL;
+      S_AXI_GP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP0.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP2.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP3.STOP_ON_ERROR = LEVEL;
+      S_AXI_ACP.STOP_ON_ERROR = LEVEL;
+
+    end
+  endtask 
+
+  /* API for setting the verbosity for channel level info*/  
+  task automatic set_channel_level_info;
+    input [1023:0] name;
+    input LEVEL;
+    begin
+     $display(""[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b"",$time, DISP_INFO,  name , LEVEL);
+     case(name)
+      ""M_AXI_GP0"" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
+      ""M_AXI_GP1"" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
+      ""S_AXI_GP0"" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
+      ""S_AXI_GP1"" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
+      ""S_AXI_HP0"" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
+      ""S_AXI_HP1"" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
+      ""S_AXI_HP2"" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
+      ""S_AXI_HP3"" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
+      ""S_AXI_ACP"" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
+      ""ALL""       : begin
+                      M_AXI_GP0.master.set_channel_level_info(LEVEL);
+                      M_AXI_GP1.master.set_channel_level_info(LEVEL);
+                      S_AXI_GP0.slave.set_channel_level_info(LEVEL);
+                      S_AXI_GP1.slave.set_channel_level_info(LEVEL);
+                      S_AXI_HP0.slave.set_channel_level_info(LEVEL);
+                      S_AXI_HP1.slave.set_channel_level_info(LEVEL);
+                      S_AXI_HP2.slave.set_channel_level_info(LEVEL);
+                      S_AXI_HP3.slave.set_channel_level_info(LEVEL);
+                      S_AXI_ACP.slave.set_channel_level_info(LEVEL);
+                    end
+      default     : $display(""[%0d] : %0s : Invalid Port name (%0s)"",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting the verbosity for function level info*/  
+  task automatic set_function_level_info;
+    input [1023:0] name;
+    input LEVEL;
+    begin
+     $display(""[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b"",$time, DISP_INFO,  name , LEVEL);
+     case(name)
+      ""M_AXI_GP0"" : M_AXI_GP0.master.set_function_level_info(LEVEL);
+      ""M_AXI_GP1"" : M_AXI_GP1.master.set_function_level_info(LEVEL);
+      ""S_AXI_GP0"" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
+      ""S_AXI_GP1"" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
+      ""S_AXI_HP0"" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
+      ""S_AXI_HP1"" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
+      ""S_AXI_HP2"" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
+      ""S_AXI_HP3"" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
+      ""S_AXI_ACP"" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
+      ""ALL""       : begin
+                      M_AXI_GP0.master.set_function_level_info(LEVEL);
+                      M_AXI_GP1.master.set_function_level_info(LEVEL);
+                      S_AXI_GP0.slave.set_function_level_info(LEVEL);
+                      S_AXI_GP1.slave.set_function_level_info(LEVEL);
+                      S_AXI_HP0.slave.set_function_level_info(LEVEL);
+                      S_AXI_HP1.slave.set_function_level_info(LEVEL);
+                      S_AXI_HP2.slave.set_function_level_info(LEVEL);
+                      S_AXI_HP3.slave.set_function_level_info(LEVEL);
+                      S_AXI_ACP.slave.set_function_level_info(LEVEL);
+                    end
+      default     : $display(""[%0d] : %0s : Invalid Port name (%0s)"",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting the Message verbosity */  
+  task automatic set_debug_level_info;
+    input LEVEL;
+    begin
+      $display(""[%0d] : %0s : Setting Debug Level Info as %0b"",$time, DISP_INFO,  LEVEL);
+      DEBUG_INFO = LEVEL;
+      M_AXI_GP0.DEBUG_INFO = LEVEL;
+      M_AXI_GP1.DEBUG_INFO = LEVEL;
+      S_AXI_GP0.DEBUG_INFO = LEVEL;
+      S_AXI_GP1.DEBUG_INFO = LEVEL;
+      S_AXI_HP0.DEBUG_INFO = LEVEL;
+      S_AXI_HP1.DEBUG_INFO = LEVEL;
+      S_AXI_HP2.DEBUG_INFO = LEVEL;
+      S_AXI_HP3.DEBUG_INFO = LEVEL;
+      S_AXI_ACP.DEBUG_INFO = LEVEL; 
+    end
+  endtask
+
+  /* API for setting ARQos Values */  
+  task automatic set_arqos;
+    input [1023:0] name;
+    input [axi_qos_width-1:0] value;
+    begin
+     $display(""[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b"",$time, DISP_INFO,  name , value);
+     case(name)
+      ""S_AXI_GP0"" : S_AXI_GP0.set_arqos(value);
+      ""S_AXI_GP1"" : S_AXI_GP1.set_arqos(value);
+      ""S_AXI_HP0"" : S_AXI_HP0.set_arqos(value);
+      ""S_AXI_HP1"" : S_AXI_HP1.set_arqos(value);
+      ""S_AXI_HP2"" : S_AXI_HP2.set_arqos(value);
+      ""S_AXI_HP3"" : S_AXI_HP3.set_arqos(value);
+      ""S_AXI_ACP"" : S_AXI_ACP.set_arqos(value);
+      default     : $display(""[%0d] : %0s : Invalid Slave Port name (%0s)"",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting AWQos Values */  
+  task automatic set_awqos;
+    input [1023:0] name;
+    input [axi_qos_width-1:0] value;
+    begin
+     $display(""[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b"",$time, DISP_INFO,  name , value);
+     case(name)
+      ""S_AXI_GP0"" : S_AXI_GP0.set_awqos(value);
+      ""S_AXI_GP1"" : S_AXI_GP1.set_awqos(value);
+      ""S_AXI_HP0"" : S_AXI_HP0.set_awqos(value);
+      ""S_AXI_HP1"" : S_AXI_HP1.set_awqos(value);
+      ""S_AXI_HP2"" : S_AXI_HP2.set_awqos(value);
+      ""S_AXI_HP3"" : S_AXI_HP3.set_awqos(value);
+      ""S_AXI_ACP"" : S_AXI_ACP.set_awqos(value);
+      default     : $display(""[%0d] : %0s : Invalid Slave Port (%0s)"",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for soft reset control */
+  task automatic fpga_soft_reset;
+    input[data_width-1:0] reset_ctrl;
+    begin
+      if(DEBUG_INFO) $display(""[%0d] : %0s : FPGA Soft Reset called for 0x%0h"",$time, DISP_INFO,  reset_ctrl); 
+      gen_rst.fpga_soft_reset(reset_ctrl);  
+    end
+  endtask
+
+  /* API for pre-loading memories from (DDR/OCM model) */
+  task automatic pre_load_mem_from_file;
+    input [(max_chars*8)-1:0] file_name;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      succ = $fopen(file_name,""r"");
+      if(succ == 0) begin
+        $display(""[%0d] : %0s : \'%0s\' doesn\'t exist. \'pre_load_mem_from_file\' call failed ...\
+"",$time, DISP_ERR, file_name); 
+        if(STOP_ON_ERROR) $stop; 
+      end   
+      else if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display(""[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s"",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display(""[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s"",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        default : begin
+                  $display(""[%0d] : %0s : Address(0x%0h) is out-of-range. \'pre_load_mem_from_file\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'pre_load_mem_from_file\' call failed ..."",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+ 
+  /* API for pre-loading memories (DDR/OCM) */
+  task automatic pre_load_mem;
+    input [1:0] data_type;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+\t\t          if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display(""[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data"",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end
+        DDR_MEM : begin
+                  ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display(""[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data"",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end
+        default : begin
+                  $display(""[%0d] : %0s : Address(0x%0h) is out-of-range. \'pre_load_mem\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end
+        endcase
+      end else begin 
+        $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'pre_load_mem\' call failed ..."",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR) $stop; 
+      end
+    end
+  endtask
+
+  /* API for backdoor write to memories (DDR/OCM) */
+  task automatic write_mem;
+    input [max_burst_bits-1 :0] data;
+    input [addr_width-1:0] start_addr;
+    input [max_burst_bytes_width:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+\t\t          if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.write_mem(data,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display(""[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory"",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.write_mem(data,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display(""[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory"",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end 
+        default : begin
+                  $display(""[%0d] : %0s : Address(0x%0h) is out-of-range. \'write_mem\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'write_mem\' call failed ..."",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+
+    /* read_memory */
+    task automatic read_mem;
+      input [addr_width-1:0] start_addr;
+      input [max_burst_bytes_width :0] no_of_bytes;
+      output[max_burst_bits-1 :0] data;
+      reg [1:0] mem_type;
+      integer succ;
+      begin
+        mem_type = decode_address(start_addr);
+        if(check_addr_aligned(start_addr)) begin    
+          case(mem_type)
+          OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.read_mem(data,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                    if(DEBUG_INFO)
+                      $display(""[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory "",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                    end 
+          DDR_MEM : begin
+                    ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
+                    if(DEBUG_INFO)
+                      $display(""[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory"",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                    end 
+          default : begin
+                    $display(""[%0d] : %0s : Address(0x%0h) is out-of-range. \'read_mem\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+                    if(STOP_ON_ERROR) $stop; 
+                    end 
+          endcase
+        end else begin 
+          $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'read_mem\' call failed ..."",$time, DISP_ERR, start_addr);
+          if(STOP_ON_ERROR)
+            $stop; 
+        end
+      end
+  endtask
+
+  /* API for backdoor read to memories (DDR/OCM) */
+  task automatic peek_mem_to_file;
+    input [(max_chars*8)-1:0] file_name;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display(""[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s"",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display(""[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s"",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        default : begin
+                  $display(""[%0d] : %0s : Address(0x%0h) is out-of-range. \'peek_mem_to_file\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'peek_mem_to_file\' call failed ..."",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+
+  /* API to read interrupt status */
+  task automatic read_interrupt;
+    output[irq_width-1:0] irq_status;
+    begin
+      irq_status = IRQ_F2P;
+      if(DEBUG_INFO) $display(""[%0d] : %0s : Reading Interrupt Status as 0x%0h"",$time, DISP_INFO,  irq_status);
+    end
+  endtask
+
+  /* API to wait on interrup */
+  task automatic wait_interrupt;
+    input [3:0] irq;
+    output[irq_width-1:0] irq_status;
+    begin
+      if(DEBUG_INFO) $display(""[%0d] : %0s : Waiting on Interrupt irq[%0d]"",$time, DISP_INFO,  irq);
+
+      case(irq) 
+      0 :  wait(IRQ_F2P[0] === 1\'b1);
+      1 :  wait(IRQ_F2P[1] === 1\'b1);
+      2 :  wait(IRQ_F2P[2] === 1\'b1);
+      3 :  wait(IRQ_F2P[3] === 1\'b1);
+      4 :  wait(IRQ_F2P[4] === 1\'b1);
+      5 :  wait(IRQ_F2P[5] === 1\'b1);
+      6 :  wait(IRQ_F2P[6] === 1\'b1);
+      7 :  wait(IRQ_F2P[7] === 1\'b1);
+      8 :  wait(IRQ_F2P[8] === 1\'b1);
+      8 :  wait(IRQ_F2P[9] === 1\'b1);
+      10:  wait(IRQ_F2P[10] === 1\'b1);
+      11:  wait(IRQ_F2P[11] === 1\'b1);
+      12:  wait(IRQ_F2P[12] === 1\'b1);
+      13:  wait(IRQ_F2P[13] === 1\'b1);
+      14:  wait(IRQ_F2P[14] === 1\'b1);
+      15:  wait(IRQ_F2P[15] === 1\'b1);
+      default : $display(""[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported"",$time, DISP_ERR);
+      endcase
+      if(DEBUG_INFO) $display(""[%0d] : %0s : Received Interrupt irq[%0d]"",$time, DISP_INFO,  irq);
+      irq_status = IRQ_F2P;
+    end
+  endtask
+
+  /* API to wait for a certain match pattern*/ 
+  task automatic wait_mem_update;
+    input[addr_width-1:0] address;
+    input[data_width-1:0] data_in;
+    output[data_width-1:0] data_out;
+    reg[data_width-1:0] datao;
+    begin
+      if(mem_update_key) begin
+        mem_update_key = 0;
+        if(DEBUG_INFO) $display(""[%0d] : %0s : \'wait_mem_update\' called for Address(0x%0h) , Match Pattern(0x%0h) \
+"",$time, DISP_INFO, address, data_in); 
+        if(check_addr_aligned(address)) begin
+         ddrc.ddr.wait_mem_update(address, datao);
+         if(datao != data_in)begin 
+           $display(""[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \
+"",$time, DISP_ERR, address, data_in,datao);
+           $stop;
+         end else
+           $display(""[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \
+"",$time, DISP_INFO,  address, data_in);
+         data_out = datao;
+        end else begin
+           $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'wait_mem_update\' call failed ...\
+"",$time, DISP_ERR,  address); 
+           if(STOP_ON_ERROR) $stop;
+        end
+        mem_update_key = 1;
+      end else 
+        $display(""[%0d] : %0s : One instance of \'wait_mem_update\' thread is already running.Only one instance can be called at a time ...\
+"",$time, DISP_WARN); 
+    end
+  endtask
+
+
+ /* API to initiate a WRITE transaction on one of the AXI-Master ports*/ 
+ task automatic write_from_file;
+   input [(max_chars*8)-1:0] file_name;
+   input [addr_width-1:0] start_addr;
+   input [int_width-1:0] wr_size;
+   output [axi_rsp_width-1:0] response;
+   integer succ;
+   begin
+      succ = $fopen(file_name,""r"");
+      if(succ == 0) begin
+        $display(""[%0d] : %0s : \'%0s\' doesn\'t exist. \'write_from_file\' call failed ...\
+"",$time, DISP_ERR, file_name); 
+        if(STOP_ON_ERROR) $stop; 
+      end   
+      else if(!check_master_address(start_addr)) begin
+         $display(""[%0d] : %0s : Master Address(0x%0h) is out of range\
+"",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+      end else if(check_addr_aligned(start_addr)) begin
+         $fclose(succ);
+         case(start_addr[31:30])
+          GP_M0 : begin
+            if(DEBUG_INFO)
+              $display(""[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s"",$time, DISP_INFO,  start_addr, wr_size, file_name); 
+            M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
+            if(DEBUG_INFO)
+              $display(""[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)"",$time, DISP_INFO,  start_addr); 
+          end
+          GP_M1 : begin
+            if(DEBUG_INFO)
+              $display(""[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s"",$time, DISP_INFO,  start_addr, wr_size, file_name); 
+            M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
+            if(DEBUG_INFO)
+              $display(""[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)"",$time, DISP_INFO,  start_addr); 
+          end 
+          default : begin
+           $display(""[%0d] : %0s : Invalid Address(0x%0h)  \'write_from_file\' call failed ...\
+"",$time, DISP_ERR, start_addr); 
+          end
+         endcase
+      end else begin
+          $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'write_from_file\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+          if(STOP_ON_ERROR) $stop;
+      end
+   end
+ endtask
+
+ /* API to initiate a READ transaction on one of the AXI-Master ports*/ 
+ task automatic read_to_file;
+   input [(max_chars*8)-1:0] file_name;
+   input [addr_width-1:0] start_addr;
+   input [int_width-1:0] rd_size;
+   output [axi_rsp_width-1:0] response;
+   begin
+      if(!check_master_address(start_addr)) begin
+         $display(""[%0d] : %0s : Master Address(0x%0h) is out of range\
+"",$time, DISP_ERR ,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+      end else if(check_addr_aligned(start_addr)) begin
+         case(start_addr[31:30])
+          GP_M0 : begin
+            if(DEBUG_INFO)
+               $display(""[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s"",$time, DISP_INFO,  start_addr, rd_size, file_name); 
+            M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
+            if(DEBUG_INFO)
+               $display(""[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)"",$time, DISP_INFO,  start_addr); 
+          end
+          GP_M1 : begin
+            if(DEBUG_INFO)
+               $display(""[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s"",$time, DISP_INFO,  start_addr, rd_size, file_name); 
+            M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
+            if(DEBUG_INFO)
+               $display(""[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)"",$time, DISP_INFO,  start_addr); 
+          end
+          default : $display(""[%0d] : %0s : Invalid Address(0x%0h) \'read_to_file\' call failed ...\
+"",$time, DISP_ERR, start_addr); 
+         endcase
+      end else begin
+          $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'read_to_file\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+          if(STOP_ON_ERROR) $stop;
+      end
+   end
+ endtask
+
+ /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/ 
+ task automatic write_data;
+   input [addr_width-1:0] start_addr;
+   input [max_transfer_bytes_width:0] wr_size;
+   input [(max_transfer_bytes*8)-1:0] w_data;
+   output [axi_rsp_width-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+         $display(""[%0d] : %0s : Master Address(0x%0h) is out of range. \'write_data\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(wr_size > max_transfer_bytes) begin
+         $display(""[%0d] : %0s : Byte Size supported is 128 bytes only. \'write_data\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes"",$time, DISP_INFO,  start_addr, wr_size); 
+       M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes"",$time, DISP_INFO,  start_addr, wr_size); 
+       M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display(""[%0d] : %0s : Invalid Address(0x%0h) \'write_data\' call failed ...\
+"",$time, DISP_ERR, start_addr); 
+   end
+ endtask
+
+ /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/ 
+ task automatic read_data;
+   input [addr_width-1:0] start_addr;
+   input [max_transfer_bytes_width:0] rd_size;
+   output[(max_transfer_bytes*8)-1:0] rd_data;
+   output [axi_rsp_width-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display(""[%0d] : %0s : Master Address(0x%0h) is out of range \'read_data\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(rd_size > max_transfer_bytes) begin
+         $display(""[%0d] : %0s : Byte Size supported is 128 bytes only.\'read_data\' call failed ... \
+"",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes"",$time, DISP_INFO,  start_addr, rd_size); 
+       M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes"",$time, DISP_INFO,  start_addr, rd_size); 
+       M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display(""[%0d] : %0s : Invalid Address(0x%0h) \'read_data\' call failed ...\
+"",$time, DISP_ERR, start_addr); 
+    end
+ endtask
+
+/* Hooks to call to BFM APIs */
+ task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display(""[%0d] : %0s : Master Address(0x%0h) is out of range. \'write_burst\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes"",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes"",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display(""[%0d] : %0s : Invalid Address(0x%0h) \'write_burst\' call failed ... \
+"",$time, DISP_ERR, start_addr); 
+   end
+ endtask 
+
+ task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+   reg[511:0] rsp; /// string for response
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display(""[%0d] : %0s : Master Address(0x%0h) is out of range. \'write_burst_concurrent\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes"",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes"",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display(""[%0d] : %0s : Invalid Address(0x%0h) \'write_burst_concurrent\' call failed ... \
+"",$time, DISP_ERR, start_addr); 
+   end
+ endtask 
+
+ task automatic read_burst;
+   input [addr_width-1:0] start_addr;
+   input [axi_len_width-1:0] len;
+   input [axi_size_width-1:0] siz;
+   input [axi_brst_type_width-1:0] burst;
+   input [axi_lock_width-1:0] lck;
+   input [axi_cache_width-1:0] cache;
+   input [axi_prot_width-1:0] prot;
+   output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
+   output [(axi_rsp_width*axi_burst_len)-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display(""[%0d] : %0s : Master Address(0x%0h) is out of range. \'read_burst\' call failed ...\
+"",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read"",$time, DISP_INFO,  start_addr); 
+       M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read"",$time, DISP_INFO,  start_addr); 
+       M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response \'%0s\'"",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display(""[%0d] : %0s : Invalid Address(0x%0h) \'read_burst\' call failed ... \
+"",$time, DISP_ERR, start_addr); 
+    end
+ endtask 
+
+ task automatic wait_reg_update;
+   input [addr_width-1:0] addr;
+   input [data_width-1:0] data_i;
+   input [data_width-1:0] mask_i;
+   input [int_width-1:0] time_interval;
+   input [int_width-1:0] time_out;
+   output [data_width-1:0] data_o;
+
+   reg upd_done0;
+   reg upd_done1;
+   begin
+    if(!check_master_address(addr)) begin
+       $display(""[%0d] : %0s : Address(0x%0h) is out of range. \'wait_reg_update\' call failed ...\
+"",$time, DISP_ERR,  addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(addr[31:30] === GP_M0) begin
+     if(reg_update_key_0) begin
+       reg_update_key_0 = 0;
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP0 : %0s : \'wait_reg_update\' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \
+ "",$time, DISP_INFO, addr, mask_i, data_i); 
+       M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
+       if(DEBUG_INFO && upd_done0)
+         $display(""[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated "",$time, DISP_INFO, addr); 
+       reg_update_key_0 = 1;
+     end else
+       $display(""[%0d] : M_AXI_GP0 : One instance of \'wait_reg_update\' thread is already running.Only one instance can be called at a time ...\
+"",$time, DISP_WARN); 
+    end else if(addr[31:30] === GP_M1) begin
+     if(reg_update_key_1) begin
+       reg_update_key_1 = 0;
+       if(DEBUG_INFO)
+         $display(""[%0d] : M_AXI_GP1 : %0s : \'wait_reg_update\' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \
+ "",$time, DISP_INFO, addr, mask_i, data_i); 
+       M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
+       if(DEBUG_INFO && upd_done1)
+         $display(""[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated "",$time, DISP_INFO,  addr); 
+       reg_update_key_1 = 1;
+     end else
+       $display(""[%0d] : M_AXI_GP1 : One instance of \'wait_reg_update\' thread is already running.Only one instance can be called at a time ...\
+"",$time, DISP_WARN); 
+    end else
+       $display(""[%0d] : %0s : Invalid Address(0x%0h) \'wait_reg_update\' call failed ... \
+"",$time, DISP_ERR, addr); 
+   end
+ endtask 
+
+/* API to read register map */
+ task read_register_map;
+   input [addr_width-1:0] start_addr;
+   input [max_regs_width:0] no_of_registers;
+   output[max_burst_bits-1 :0] data;
+   reg [max_regs_width:0] no_of_regs;
+   begin
+    no_of_regs = no_of_registers;
+    if(no_of_registers > 32) begin
+      $display(""[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\
+ Only 32 registers will be read."",$time, DISP_ERR, start_addr);
+      no_of_regs = 32;
+    end
+    if(check_addr_aligned(start_addr)) begin
+      if(decode_address(start_addr) == REG_MEM) begin
+        if(DEBUG_INFO)  $display(""[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers"",$time, DISP_INFO,  start_addr,no_of_regs ); 
+        regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
+        if(DEBUG_INFO)  $display(""[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)"",$time, DISP_INFO,  start_addr, data ); 
+      end else begin
+       $display(""[%0d] : %0s : Invalid Address(0x%0h) for Register Read. \'read_register_map\' call failed ..."",$time, DISP_ERR, start_addr);
+      end
+    end else begin
+       data = 0;
+       $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'read_register_map\' call failed ..."",$time, DISP_ERR, start_addr);
+    end
+   end
+ endtask
+
+/* API to read single register */
+ task read_register;
+   input [addr_width-1:0] addr;
+   output[data_width-1:0] data;
+   begin
+    if(check_addr_aligned(addr)) begin
+       if(decode_address(addr) == REG_MEM) begin
+         if(DEBUG_INFO)  $display(""[%0d] : %0s : Reading Register (0x%0h) "",$time, DISP_INFO,  addr ); 
+         regc.regm.get_data(addr >> 2, data);
+         if(DEBUG_INFO)  $display(""[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)"",$time, DISP_INFO,  addr, data ); 
+       end else begin
+         $display(""[%0d] : %0s : Invalid Address(0x%0h) for Register Read. \'read_register\' call failed ..."",$time, DISP_ERR, addr);
+       end
+    end else begin
+       data = 0;
+       $display(""[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. \'read_register\' call failed ..."",$time, DISP_ERR, addr);
+    end
+
+   end
+ endtask
+
+  /* API to set the AXI-Slave profile*/ 
+ task automatic set_slave_profile;
+    input[1023:0] name;
+    input[1:0] latency ;
+    begin 
+     if(DEBUG_INFO) $display(""[%0d] : %0s : %0s Port/s : Setting Slave profile"",$time, DISP_INFO,  name);
+     case(name)
+      ""S_AXI_GP0"" : S_AXI_GP0.set_latency_type(latency);
+      ""S_AXI_GP1"" : S_AXI_GP1.set_latency_type(latency);
+      ""S_AXI_HP0"" : S_AXI_HP0.set_latency_type(latency);
+      ""S_AXI_HP1"" : S_AXI_HP1.set_latency_type(latency);
+      ""S_AXI_HP2"" : S_AXI_HP2.set_latency_type(latency);
+      ""S_AXI_HP3"" : S_AXI_HP3.set_latency_type(latency);
+      ""S_AXI_ACP"" : S_AXI_ACP.set_latency_type(latency);
+      ""ALL""       : begin
+                     S_AXI_GP0.set_latency_type(latency);
+                     S_AXI_GP1.set_latency_type(latency);
+                     S_AXI_HP0.set_latency_type(latency);
+                     S_AXI_HP1.set_latency_type(latency);
+                     S_AXI_HP2.set_latency_type(latency);
+                     S_AXI_HP3.set_latency_type(latency);
+                     S_AXI_ACP.set_latency_type(latency);
+                    end  
+     endcase
+    end
+ endtask
+
+
+/*------------------------------ LOCAL APIs ------------------------------------------------ */
+
+  /* local API for address decoding*/
+  function automatic [1:0] decode_address;
+    input [addr_width-1:0] address;
+    begin
+      if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr )) 
+        decode_address = OCM_MEM; /// OCM 
+      else if(address >= ddr_start_addr && address <= ddr_end_addr)
+        decode_address = DDR_MEM; /// DDR 
+      else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
+        decode_address = OCM_MEM; /// OCM 
+      else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
+        decode_address = REG_MEM; /// Register Map
+      else
+        decode_address = INVALID_MEM_TYPE; /// ERROR in Address 
+    end
+  endfunction 
+
+  /* local API for checking address is 32-bit (4-byte) aligned */
+  function automatic check_addr_aligned;
+    input [addr_width-1:0] address;
+    begin 
+      if((address%4) !=0 ) begin // 
+        check_addr_aligned = 0; ///not_aligned
+      end else
+        check_addr_aligned = 1;
+    end
+  endfunction
+
+ /* local API to check address for GP Masters */
+ function check_master_address; 
+   input [addr_width-1:0] address;
+   begin
+     if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr) 
+       check_master_address = 1\'b1; 
+     else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr) 
+       check_master_address = 1\'b1; 
+     else
+       check_master_address = 1\'b0; /// ERROR in Address 
+   end
+ endfunction
+
+ /* Response decode */
+ function automatic [511:0] get_resp;
+   input[axi_rsp_width-1:0] response;
+   begin 
+    case(response)
+     2\'b00 : get_resp = ""OKAY"";
+     2\'b01 : get_resp = ""EXOKAY"";
+     2\'b10 : get_resp = ""SLVERR"";
+     2\'b11 : get_resp = ""DECERR"";
+    endcase
+   end
+ endfunction 
+"
+"// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+// Filename:      trace_buffer.v
+// Description:   Trace port buffer 
+//-----------------------------------------------------------------------------
+// Structure:   This section shows the hierarchical structure of 
+//              pss_wrapper.
+//
+//              --processing_system7
+//\t\t\t\t\t\t\t |\t
+//\t\t\t\t\t\t\t --trace_buffer
+//-----------------------------------------------------------------------------
+
+
+module processing_system7_v5_5_trace_buffer #
+  (
+   parameter integer FIFO_SIZE = 128,
+\tparameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
+   parameter integer C_DELAY_CLKS = 12
+   )
+  (
+   input wire TRACE_CLK,
+   input wire RST,
+   input wire TRACE_VALID_IN,
+   input wire [3:0] TRACE_ATID_IN,
+   input wire [31:0] TRACE_DATA_IN,
+   output wire TRACE_VALID_OUT,
+   output wire [3:0] TRACE_ATID_OUT,
+   output wire [31:0] TRACE_DATA_OUT
+  );
+
+//------------------------------------------------------------
+// Architecture section
+//------------------------------------------------------------
+
+// function called clogb2 that returns an integer which has the 
+// value of the ceiling of the log base 2.
+
+function integer clogb2 (input integer bit_depth);
+ integer i;
+ integer temp_log;
+ begin
+  temp_log = 0;
+  for(i=bit_depth; i > 0; i = i>>1)
+  clogb2 = temp_log;
+  temp_log=temp_log+1;\t\t
+ end
+endfunction
+
+localparam DEPTH  = clogb2(FIFO_SIZE-1);
+
+wire [31:0] reset_zeros;
+reg  [31:0] trace_pedge; // write enable for FIFO
+reg  [31:0] ti;
+reg  [31:0] tom;
+
+reg  [3:0] atid;
+
+reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory 
+
+reg  [4:0]  dly_ctr;
+reg  [DEPTH-1:0]  fifo_wp;
+reg  [DEPTH-1:0]  fifo_rp;
+
+reg         fifo_re;
+wire        fifo_empty;
+wire        fifo_full;
+reg         fifo_full_reg;
+
+assign reset_zeros = 32\'h0;  
+
+
+// Pipeline Stage for Traceport ATID ports
+  always @(posedge TRACE_CLK) begin
+    // process pedge_ti
+    // rising clock edge
+    if((RST == 1\'b1)) begin
+      atid <= reset_zeros;
+    end
+    else begin\t 
+      atid <= TRACE_ATID_IN;
+\t end
+  end
+
+  assign TRACE_ATID_OUT = atid;
+  
+  /////////////////////////////////////////////
+  // Generate FIFO data based on TRACE_VALID_IN
+  /////////////////////////////////////////////
+  generate
+    if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
+  /////////////////////////////////////////////
+        
+\t\t  // memory update process
+\t\t  // Update memory when positive edge detected and FIFO not full
+\t\t  always @(posedge TRACE_CLK) begin
+\t\t\t\tif (TRACE_VALID_IN == 1\'b1 && fifo_full_reg != 1\'b1) begin
+\t\t\t\t\ttrace_fifo[fifo_wp]  <= TRACE_DATA_IN;
+\t\t\t\tend
+\t\t  end
+
+\t\t  // fifo write pointer
+\t\t  always @(posedge TRACE_CLK) begin
+\t\t\t\t// process
+\t\t\t if(RST == 1\'b1) begin
+\t\t\t\tfifo_wp <= {DEPTH{1\'b0}};
+\t\t\t end
+\t\t\t else if(TRACE_VALID_IN ) begin
+\t\t\t\tif(fifo_wp == (FIFO_SIZE - 1)) begin
+\t\t\t\t  if (fifo_empty) begin
+\t\t\t\t\t fifo_wp <= {DEPTH{1\'b0}};
+\t\t\t\t  end
+\t\t\t\tend
+\t\t\t\telse begin
+\t\t\t\t  fifo_wp <= fifo_wp + 1;
+\t\t\t\tend
+\t\t\t end
+\t\t  end
+
+
+  /////////////////////////////////////////////
+  // Generate FIFO data based on data edge
+  /////////////////////////////////////////////
+    end else begin : gen_data_edge_detector
+  /////////////////////////////////////////////
+
+
+\t\t  // purpose: check for pos edge on any trace input
+\t\t  always @(posedge TRACE_CLK) begin
+\t\t\t // process pedge_ti
+\t\t\t // rising clock edge
+\t\t\t if((RST == 1\'b1)) begin
+\t\t\t\tti          <= reset_zeros;
+\t\t\t\ttrace_pedge <= reset_zeros;
+\t\t\t end
+\t\t\t else begin
+\t\t\t\tti          <= TRACE_DATA_IN;
+\t\t\t\ttrace_pedge <= (~ti & TRACE_DATA_IN);
+\t\t\t\t//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) &  ~ti;
+\t\t\t\t// posedge only
+\t\t\t end
+\t\t  end
+\t\t  
+\t\t  // memory update process
+\t\t  // Update memory when positive edge detected and FIFO not full
+\t\t  always @(posedge TRACE_CLK) begin
+\t\t\t if(|(trace_pedge)  == 1\'b1 && fifo_full_reg != 1\'b1) begin
+\t\t\t\ttrace_fifo[fifo_wp]  <= trace_pedge;
+\t\t\t end
+\t\t  end
+
+\t\t  // fifo write pointer
+\t\t  always @(posedge TRACE_CLK) begin
+\t\t\t\t// process
+\t\t\t if(RST == 1\'b1) begin
+\t\t\t\tfifo_wp <= {DEPTH{1\'b0}};
+\t\t\t end
+\t\t\t else if(|(trace_pedge)  == 1\'b1) begin
+\t\t\t\tif(fifo_wp == (FIFO_SIZE - 1)) begin
+\t\t\t\t  if (fifo_empty) begin
+\t\t\t\t\t fifo_wp <= {DEPTH{1\'b0}};
+\t\t\t\t  end
+\t\t\t\tend
+\t\t\t\telse begin
+\t\t\t\t  fifo_wp <= fifo_wp + 1;
+\t\t\t\tend
+\t\t\t end
+\t\t  end
+
+
+    end
+  endgenerate
+
+
+  always @(posedge TRACE_CLK) begin
+    tom <= trace_fifo[fifo_rp] ;
+  end
+
+
+//  // fifo write pointer
+//  always @(posedge TRACE_CLK) begin
+//      // process
+//    if(RST == 1\'b1) begin
+//      fifo_wp <= {DEPTH{1\'b0}};
+//    end
+//    else if(|(trace_pedge)  == 1\'b1) begin
+//      if(fifo_wp == (FIFO_SIZE - 1)) begin
+//        fifo_wp <= {DEPTH{1\'b0}};
+//      end
+//      else begin
+//        fifo_wp <= fifo_wp + 1;
+//      end
+//    end
+//  end
+
+
+  // fifo read pointer update
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1\'b1) begin
+      fifo_rp <= {DEPTH{1\'b0}};
+      fifo_re <= 1\'b0;
+    end
+    else if(fifo_empty != 1\'b1 && dly_ctr == 5\'b00000 && fifo_re == 1\'b0) begin
+      fifo_re <= 1\'b1;
+      if(fifo_rp == (FIFO_SIZE - 1)) begin
+        fifo_rp <= {DEPTH{1\'b0}};
+      end
+      else begin
+        fifo_rp <= fifo_rp + 1;
+      end
+    end
+    else begin
+      fifo_re <= 1\'b0;
+    end
+  end
+  
+  // delay counter update
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1\'b1) begin
+      dly_ctr <= 5\'h0;
+    end
+    else if (fifo_re == 1\'b1) begin
+      dly_ctr <= C_DELAY_CLKS-1;
+    end
+    else if(dly_ctr != 5\'h0) begin
+      dly_ctr <= dly_ctr - 1;
+    end
+  end
+
+  // fifo empty update
+  assign fifo_empty = (fifo_wp == fifo_rp) ? 1\'b1 : 1\'b0;
+
+  // fifo full update
+  assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1\'b1 : 1\'b0;
+
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1\'b1) begin
+      fifo_full_reg <= 1\'b0;
+    end
+    else if (fifo_empty) begin
+      fifo_full_reg <= 1\'b0;
+\t end else begin\t
+      fifo_full_reg <= fifo_full;
+    end
+  end  
+  
+//  always @(posedge TRACE_CLK) begin
+//    if(RST == 1\'b1) begin
+//      fifo_full_reg <= 1\'b0;
+//    end
+//    else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1\'b1)) begin
+//      fifo_full_reg <= 1\'b1;
+//    end
+//\t else begin
+//        fifo_full_reg <= 1\'b0;
+//    end
+//  end  
+//  
+  assign TRACE_DATA_OUT     = tom;
+  
+  assign TRACE_VALID_OUT    = fifo_re;  
+  
+  
+
+
+endmodule
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_unused_ports.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Semantic checks for unused ports.
+ *
+ *****************************************************************************/
+
+/* CAN */
+assign CAN0_PHY_TX = 0;
+assign CAN1_PHY_TX = 0;
+always @(CAN0_PHY_RX or CAN1_PHY_RX)
+begin 
+ if(CAN0_PHY_RX | CAN1_PHY_RX)
+  $display(""[%0d] : %0s : CAN Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* ETHERNET */
+/* ------------------------------------------- */
+
+assign ENET0_GMII_TX_EN = 0;
+assign ENET0_GMII_TX_ER = 0;
+assign ENET0_MDIO_MDC = 0;
+assign ENET0_MDIO_O = 0; /// confirm
+assign ENET0_MDIO_T = 0;
+assign ENET0_PTP_DELAY_REQ_RX = 0;
+assign ENET0_PTP_DELAY_REQ_TX = 0;
+assign ENET0_PTP_PDELAY_REQ_RX = 0;
+assign ENET0_PTP_PDELAY_REQ_TX = 0;
+assign ENET0_PTP_PDELAY_RESP_RX = 0;
+assign ENET0_PTP_PDELAY_RESP_TX = 0;
+assign ENET0_PTP_SYNC_FRAME_RX = 0;
+assign ENET0_PTP_SYNC_FRAME_TX = 0;
+assign ENET0_SOF_RX = 0;
+assign ENET0_SOF_TX = 0;
+assign ENET0_GMII_TXD = 0;
+always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or 
+        ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
+        ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
+begin 
+ if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN | 
+        ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
+        ENET0_GMII_TX_CLK | ENET0_MDIO_I )
+  $display(""[%0d] : %0s : ETHERNET Interface is not supported."",$time, DISP_ERR);
+end
+
+assign ENET1_GMII_TX_EN = 0;
+assign ENET1_GMII_TX_ER = 0;
+assign ENET1_MDIO_MDC = 0;
+assign ENET1_MDIO_O = 0;/// confirm
+assign ENET1_MDIO_T = 0;
+assign ENET1_PTP_DELAY_REQ_RX = 0;
+assign ENET1_PTP_DELAY_REQ_TX = 0;
+assign ENET1_PTP_PDELAY_REQ_RX = 0;
+assign ENET1_PTP_PDELAY_REQ_TX = 0;
+assign ENET1_PTP_PDELAY_RESP_RX = 0;
+assign ENET1_PTP_PDELAY_RESP_TX = 0;
+assign ENET1_PTP_SYNC_FRAME_RX = 0;
+assign ENET1_PTP_SYNC_FRAME_TX = 0;
+assign ENET1_SOF_RX = 0;
+assign ENET1_SOF_TX = 0;
+assign ENET1_GMII_TXD = 0;
+always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or 
+        ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
+        ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
+begin 
+ if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN | 
+        ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
+        ENET1_GMII_TX_CLK | ENET1_MDIO_I )
+  $display(""[%0d] : %0s : ETHERNET Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* GPIO */
+/* ------------------------------------------- */
+
+assign GPIO_O = 0;
+assign GPIO_T = 0;
+always@(GPIO_I)
+begin
+if(GPIO_I !== 0)
+ $display(""[%0d] : %0s : GPIO Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* I2C */
+/* ------------------------------------------- */
+
+assign I2C0_SDA_O = 0;
+assign I2C0_SDA_T = 0;
+assign I2C0_SCL_O = 0;
+assign I2C0_SCL_T = 0;
+assign I2C1_SDA_O = 0;
+assign I2C1_SDA_T = 0;
+assign I2C1_SCL_O = 0;
+assign I2C1_SCL_T = 0;
+always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
+begin
+ if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
+  $display(""[%0d] : %0s : I2C Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* JTAG  */
+/* ------------------------------------------- */
+
+assign PJTAG_TD_T = 0;
+assign PJTAG_TD_O = 0;
+always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
+begin
+ if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
+  $display(""[%0d] : %0s : JTAG Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* SDIO  */
+/* ------------------------------------------- */
+
+assign SDIO0_CLK = 0;
+assign SDIO0_CMD_O = 0;
+assign SDIO0_CMD_T = 0;
+assign SDIO0_DATA_O = 0;
+assign SDIO0_DATA_T = 0;
+assign SDIO0_LED = 0;
+assign SDIO0_BUSPOW = 0;
+assign SDIO0_BUSVOLT = 0;
+always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
+begin
+ if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
+  $display(""[%0d] : %0s : SDIO Interface is not supported."",$time, DISP_ERR);
+end
+
+assign SDIO1_CLK = 0;
+assign SDIO1_CMD_O = 0;
+assign SDIO1_CMD_T = 0;
+assign SDIO1_DATA_O = 0;
+assign SDIO1_DATA_T = 0;
+assign SDIO1_LED = 0;
+assign SDIO1_BUSPOW = 0;
+assign SDIO1_BUSVOLT = 0;
+always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
+begin
+ if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
+  $display(""[%0d] : %0s : SDIO Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* SPI  */
+/* ------------------------------------------- */
+
+assign SPI0_SCLK_O = 0;
+assign SPI0_SCLK_T = 0;
+assign SPI0_MOSI_O = 0;
+assign SPI0_MOSI_T = 0;
+assign SPI0_MISO_O = 0;
+assign SPI0_MISO_T = 0;
+assign SPI0_SS_O = 0; /// confirm
+assign SPI0_SS1_O = 0;/// confirm
+assign SPI0_SS2_O = 0;/// confirm
+assign SPI0_SS_T = 0;
+always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
+begin
+ if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
+  $display(""[%0d] : %0s : SPI Interface is not supported."",$time, DISP_ERR);
+end
+
+assign SPI1_SCLK_O = 0;
+assign SPI1_SCLK_T = 0;
+assign SPI1_MOSI_O = 0;
+assign SPI1_MOSI_T = 0;
+assign SPI1_MISO_O = 0;
+assign SPI1_MISO_T = 0;
+assign SPI1_SS_O = 0;
+assign SPI1_SS1_O = 0;
+assign SPI1_SS2_O = 0;
+assign SPI1_SS_T = 0;
+always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
+begin
+ if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
+  $display(""[%0d] : %0s : SPI Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* UART  */
+/* ------------------------------------------- */
+/// confirm
+assign UART0_DTRN = 0;
+assign UART0_RTSN = 0;
+assign UART0_TX = 0;
+always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
+begin
+ if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
+  $display(""[%0d] : %0s : UART Interface is not supported."",$time, DISP_ERR);
+end
+
+assign UART1_DTRN = 0;
+assign UART1_RTSN = 0;
+assign UART1_TX = 0;
+always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
+begin
+ if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
+  $display(""[%0d] : %0s : UART Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* TTC  */
+/* ------------------------------------------- */
+
+assign TTC0_WAVE0_OUT = 0;
+assign TTC0_WAVE1_OUT = 0;
+assign TTC0_WAVE2_OUT = 0;
+always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
+begin
+ if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
+  $display(""[%0d] : %0s : TTC Interface is not supported."",$time, DISP_ERR);
+end
+
+assign TTC1_WAVE0_OUT = 0;
+assign TTC1_WAVE1_OUT = 0;
+assign TTC1_WAVE2_OUT = 0;
+always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
+begin
+ if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
+  $display(""[%0d] : %0s : TTC Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* WDT  */
+/* ------------------------------------------- */
+
+assign WDT_RST_OUT = 0;
+always@(WDT_CLK_IN)
+begin
+ if(WDT_CLK_IN)
+  $display(""[%0d] : %0s : WDT Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* TRACE  */
+/* ------------------------------------------- */
+
+assign TRACE_CTL = 0;
+assign TRACE_DATA = 0;
+always@(TRACE_CLK)
+begin
+ if(TRACE_CLK)
+  $display(""[%0d] : %0s : TRACE Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* USB  */
+/* ------------------------------------------- */
+assign USB0_PORT_INDCTL = 0;
+assign USB0_VBUS_PWRSELECT = 0;
+always@(USB0_VBUS_PWRFAULT)
+begin
+ if(USB0_VBUS_PWRFAULT)
+  $display(""[%0d] : %0s : USB Interface is not supported."",$time, DISP_ERR);
+end
+
+assign USB1_PORT_INDCTL = 0;
+assign USB1_VBUS_PWRSELECT = 0;
+always@(USB1_VBUS_PWRFAULT)
+begin
+ if(USB1_VBUS_PWRFAULT)
+  $display(""[%0d] : %0s : USB Interface is not supported."",$time, DISP_ERR);
+end
+
+always@(SRAM_INTIN)
+begin
+ if(SRAM_INTIN)
+  $display(""[%0d] : %0s : SRAM_INTIN is not supported."",$time, DISP_ERR);
+end 
+
+/* ------------------------------------------- */
+/* DMA  */
+/* ------------------------------------------- */
+
+assign DMA0_DATYPE = 0;
+assign DMA0_DAVALID = 0;
+assign DMA0_DRREADY = 0;
+assign DMA0_RSTN = 0;
+always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
+begin
+ if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
+  $display(""[%0d] : %0s : DMA Interface is not supported."",$time, DISP_ERR);
+end
+
+assign DMA1_DATYPE = 0;
+assign DMA1_DAVALID = 0;
+assign DMA1_DRREADY = 0;
+assign DMA1_RSTN = 0;
+always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
+begin
+ if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
+  $display(""[%0d] : %0s : DMA Interface is not supported."",$time, DISP_ERR);
+end
+
+assign DMA2_DATYPE = 0;
+assign DMA2_DAVALID = 0;
+assign DMA2_DRREADY = 0;
+assign DMA2_RSTN = 0;
+always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
+begin
+ if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
+  $display(""[%0d] : %0s : DMA Interface is not supported."",$time, DISP_ERR);
+end
+
+assign DMA3_DATYPE = 0;
+assign DMA3_DAVALID = 0;
+assign DMA3_DRREADY = 0;
+assign DMA3_RSTN = 0;
+always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
+begin
+ if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
+  $display(""[%0d] : %0s : DMA Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* FTM  */
+/* ------------------------------------------- */
+
+assign FTMT_F2P_TRIGACK = 0;
+assign FTMT_P2F_TRIG = 0;
+assign FTMT_P2F_DEBUG = 0;
+always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or 
+        FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
+begin
+ if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
+  $display(""[%0d] : %0s : FTM Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* EVENT  */
+/* ------------------------------------------- */
+
+assign EVENT_EVENTO = 0;
+assign EVENT_STANDBYWFE = 0;  
+assign EVENT_STANDBYWFI = 0;
+always@(EVENT_EVENTI)
+begin
+ if(EVENT_EVENTI)
+  $display(""[%0d] : %0s : EVENT Interface is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* MIO */
+/* ------------------------------------------- */
+
+always@(MIO)
+begin
+  if(MIO !== 0)
+  $display(""[%0d] : %0s : MIO is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* FCLK_TRIG */
+/* ------------------------------------------- */
+
+always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
+begin
+ if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
+  $display(""[%0d] : %0s : FCLK_TRIG is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* MISC */
+/* ------------------------------------------- */
+
+always@(FPGA_IDLE_N)
+begin
+ if(FPGA_IDLE_N)
+  $display(""[%0d] : %0s : FPGA_IDLE_N is not supported."",$time, DISP_ERR);
+end
+
+always@(DDR_ARB)
+begin
+ if(DDR_ARB !== 0)
+  $display(""[%0d] : %0s : DDR_ARB is not supported."",$time, DISP_ERR);
+end
+
+always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
+begin
+ if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ) 
+  $display(""[%0d] : %0s : CORE FIQ,IRQ is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* DDR */
+/* ------------------------------------------- */
+
+assign DDR_WEB = 0;
+always@(DDR_Clk or DDR_CS_n)
+begin
+if(!DDR_CS_n)
+ $display(""[%0d] : %0s : EXTERNAL DDR is not supported."",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* IRQ_P2F */
+/* ------------------------------------------- */
+
+assign IRQ_P2F_DMAC_ABORT = 0;
+assign IRQ_P2F_DMAC0 = 0;
+assign IRQ_P2F_DMAC1 = 0;
+assign IRQ_P2F_DMAC2 = 0;
+assign IRQ_P2F_DMAC3 = 0;
+assign IRQ_P2F_DMAC4 = 0;
+assign IRQ_P2F_DMAC5 = 0;
+assign IRQ_P2F_DMAC6 = 0;
+assign IRQ_P2F_DMAC7 = 0;
+assign IRQ_P2F_SMC = 0;
+assign IRQ_P2F_QSPI = 0;
+assign IRQ_P2F_CTI = 0;
+assign IRQ_P2F_GPIO = 0;
+assign IRQ_P2F_USB0 = 0;
+assign IRQ_P2F_ENET0 = 0;
+assign IRQ_P2F_ENET_WAKE0 = 0;
+assign IRQ_P2F_SDIO0 = 0;
+assign IRQ_P2F_I2C0 = 0;
+assign IRQ_P2F_SPI0 = 0;
+assign IRQ_P2F_UART0 = 0;
+assign IRQ_P2F_CAN0 = 0;
+assign IRQ_P2F_USB1 = 0;
+assign IRQ_P2F_ENET1 = 0;
+assign IRQ_P2F_ENET_WAKE1 = 0;
+assign IRQ_P2F_SDIO1 = 0;
+assign IRQ_P2F_I2C1 = 0;
+assign IRQ_P2F_SPI1 = 0;
+assign IRQ_P2F_UART1 = 0;
+assign IRQ_P2F_CAN1 = 0;
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Tue Feb 14 01:38:42 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT, 
+  TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, 
+  USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, 
+  M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, 
+  M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, 
+  DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, 
+  DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin=""GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"" */;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input SDIO0_WP;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output FCLK_CLK0;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:35:35 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, 
+  I2C0_SCL_O, I2C0_SCL_T, SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, 
+  TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, 
+  M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, 
+  M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, 
+  M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, 
+  M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, 
+  M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, 
+  M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, 
+  M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, 
+  M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, 
+  M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, 
+  DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, 
+  DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
+/* synthesis syn_black_box black_box_pad_pin=""I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"" */;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input SDIO0_WP;
+  output UART0_TX;
+  input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  input [1:0]IRQ_F2P;
+  output FCLK_CLK0;
+  output FCLK_RESET0_N;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:44:08 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_sim_netlist.v
+// Design      : design_1_xbar_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd
+   (m_valid_i,
+    SR,
+    aa_grant_rnw,
+    D,
+    any_error,
+    Q,
+    \\m_ready_d_reg[2] ,
+    s_axi_bvalid,
+    m_ready_d0,
+    m_axi_bready,
+    \\gen_axilite.s_axi_bvalid_i_reg ,
+    s_axi_wready,
+    m_axi_wvalid,
+    \\m_ready_d_reg[2]_0 ,
+    \\gen_axilite.s_axi_awready_i_reg ,
+    m_axi_awvalid,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
+    s_ready_i_reg,
+    E,
+    m_axi_arvalid,
+    s_ready_i_reg_0,
+    s_axi_awready,
+    s_axi_arready,
+    s_axi_rvalid,
+    aclk,
+    aresetn_d,
+    m_ready_d,
+    \\gen_axilite.s_axi_awready_i_reg_0 ,
+    \\gen_axilite.s_axi_bvalid_i_reg_0 ,
+    s_axi_bready,
+    \\m_atarget_hot_reg[1] ,
+    \\gen_axilite.s_axi_awready_i_reg_1 ,
+    s_axi_wvalid,
+    m_valid_i_reg,
+    m_ready_d_0,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    aa_rready,
+    \\gen_axilite.s_axi_rvalid_i_reg ,
+    s_axi_rready,
+    sr_rvalid,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    \\m_ready_d_reg[1] ,
+    s_axi_awvalid);
+  output m_valid_i;
+  output [0:0]SR;
+  output aa_grant_rnw;
+  output [2:0]D;
+  output any_error;
+  output [34:0]Q;
+  output \\m_ready_d_reg[2] ;
+  output [0:0]s_axi_bvalid;
+  output [0:0]m_ready_d0;
+  output [1:0]m_axi_bready;
+  output \\gen_axilite.s_axi_bvalid_i_reg ;
+  output [0:0]s_axi_wready;
+  output [1:0]m_axi_wvalid;
+  output \\m_ready_d_reg[2]_0 ;
+  output \\gen_axilite.s_axi_awready_i_reg ;
+  output [1:0]m_axi_awvalid;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  output s_ready_i_reg;
+  output [0:0]E;
+  output [1:0]m_axi_arvalid;
+  output s_ready_i_reg_0;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rvalid;
+  input aclk;
+  input aresetn_d;
+  input [2:0]m_ready_d;
+  input \\gen_axilite.s_axi_awready_i_reg_0 ;
+  input \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  input [0:0]s_axi_bready;
+  input [1:0]\\m_atarget_hot_reg[1] ;
+  input \\gen_axilite.s_axi_awready_i_reg_1 ;
+  input [0:0]s_axi_wvalid;
+  input m_valid_i_reg;
+  input [1:0]m_ready_d_0;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input aa_rready;
+  input \\gen_axilite.s_axi_rvalid_i_reg ;
+  input [0:0]s_axi_rready;
+  input sr_rvalid;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input \\m_ready_d_reg[1] ;
+  input [0:0]s_axi_awvalid;
+
+  wire [2:0]D;
+  wire [0:0]E;
+  wire [34:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire any_error;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg_0 ;
+  wire \\gen_axilite.s_axi_awready_i_reg_1 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  wire \\gen_axilite.s_axi_rvalid_i_reg ;
+  wire \\gen_no_arbiter.grant_rnw_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  wire \\gen_no_arbiter.m_valid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_valid_i_i_2_n_0 ;
+  wire \\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
+  wire \\m_atarget_enc[1]_i_2_n_0 ;
+  wire \\m_atarget_enc[1]_i_3_n_0 ;
+  wire \\m_atarget_enc[1]_i_4_n_0 ;
+  wire [1:0]\\m_atarget_hot_reg[1] ;
+  wire [1:0]m_axi_arvalid;
+  wire [1:0]m_axi_awvalid;
+  wire [1:0]m_axi_bready;
+  wire [1:0]m_axi_wvalid;
+  wire [2:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire [1:0]m_ready_d_0;
+  wire \\m_ready_d_reg[1] ;
+  wire \\m_ready_d_reg[2] ;
+  wire \\m_ready_d_reg[2]_0 ;
+  wire m_valid_i;
+  wire m_valid_i_reg;
+  wire p_0_in1_in;
+  wire [48:1]s_amesg;
+  wire \\s_arvalid_reg[0]_i_1_n_0 ;
+  wire \\s_arvalid_reg_reg_n_0_[0] ;
+  wire s_awvalid_reg;
+  wire \\s_awvalid_reg[0]_i_1_n_0 ;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [0:0]s_axi_bvalid;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire s_ready_i;
+  wire s_ready_i_reg;
+  wire s_ready_i_reg_0;
+  wire sr_rvalid;
+
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT4 #(
+    .INIT(16\'hFBFF)) 
+    \\gen_axilite.s_axi_awready_i_i_2 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d[1]),
+        .I3(s_axi_wvalid),
+        .O(\\gen_axilite.s_axi_awready_i_reg ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\gen_axilite.s_axi_bvalid_i_i_2 
+       (.I0(s_axi_bready),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[0]),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg ));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT2 #(
+    .INIT(4\'h7)) 
+    \\gen_axilite.s_axi_rvalid_i_i_2 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .O(s_ready_i_reg_0));
+  LUT6 #(
+    .INIT(64\'hFFFFFF5300000050)) 
+    \\gen_no_arbiter.grant_rnw_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_arvalid),
+        .I3(aa_grant_any),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\gen_no_arbiter.grant_rnw_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.grant_rnw_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.grant_rnw_i_1_n_0 ),
+        .Q(aa_grant_rnw),
+        .R(SR));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[10]_i_1 
+       (.I0(s_axi_araddr[9]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[9]),
+        .O(s_amesg[10]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[11]_i_1 
+       (.I0(s_axi_araddr[10]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[10]),
+        .O(s_amesg[11]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[12]_i_1 
+       (.I0(s_axi_araddr[11]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[11]),
+        .O(s_amesg[12]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[13]_i_1 
+       (.I0(s_axi_araddr[12]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[12]),
+        .O(s_amesg[13]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[14]_i_1 
+       (.I0(s_axi_araddr[13]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[13]),
+        .O(s_amesg[14]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[15]_i_1 
+       (.I0(s_axi_araddr[14]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[14]),
+        .O(s_amesg[15]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[16]_i_1 
+       (.I0(s_axi_araddr[15]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[15]),
+        .O(s_amesg[16]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[17]_i_1 
+       (.I0(s_axi_araddr[16]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[16]),
+        .O(s_amesg[17]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[18]_i_1 
+       (.I0(s_axi_araddr[17]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[17]),
+        .O(s_amesg[18]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[19]_i_1 
+       (.I0(s_axi_araddr[18]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[18]),
+        .O(s_amesg[19]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[1]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[0]),
+        .O(s_amesg[1]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[20]_i_1 
+       (.I0(s_axi_araddr[19]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[19]),
+        .O(s_amesg[20]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[21]_i_1 
+       (.I0(s_axi_araddr[20]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[20]),
+        .O(s_amesg[21]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[22]_i_1 
+       (.I0(s_axi_araddr[21]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[21]),
+        .O(s_amesg[22]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[23]_i_1 
+       (.I0(s_axi_araddr[22]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[22]),
+        .O(s_amesg[23]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[24]_i_1 
+       (.I0(s_axi_araddr[23]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[23]),
+        .O(s_amesg[24]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[25]_i_1 
+       (.I0(s_axi_araddr[24]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[24]),
+        .O(s_amesg[25]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[26]_i_1 
+       (.I0(s_axi_araddr[25]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[25]),
+        .O(s_amesg[26]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[27]_i_1 
+       (.I0(s_axi_araddr[26]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[26]),
+        .O(s_amesg[27]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[28]_i_1 
+       (.I0(s_axi_araddr[27]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[27]),
+        .O(s_amesg[28]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[29]_i_1 
+       (.I0(s_axi_araddr[28]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[28]),
+        .O(s_amesg[29]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[2]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[1]),
+        .O(s_amesg[2]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[30]_i_1 
+       (.I0(s_axi_araddr[29]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[29]),
+        .O(s_amesg[30]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[31]_i_1 
+       (.I0(s_axi_araddr[30]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[30]),
+        .O(s_amesg[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_1 
+       (.I0(aresetn_d),
+        .O(SR));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_2 
+       (.I0(aa_grant_any),
+        .O(p_0_in1_in));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_3 
+       (.I0(s_axi_araddr[31]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[31]),
+        .O(s_amesg[32]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[3]_i_1 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[2]),
+        .O(s_amesg[3]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[46]_i_1 
+       (.I0(s_axi_arprot[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[0]),
+        .O(s_amesg[46]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[47]_i_1 
+       (.I0(s_axi_arprot[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[1]),
+        .O(s_amesg[47]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[48]_i_1 
+       (.I0(s_axi_arprot[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[2]),
+        .O(s_amesg[48]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[4]_i_1 
+       (.I0(s_axi_araddr[3]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[3]),
+        .O(s_amesg[4]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[5]_i_1 
+       (.I0(s_axi_araddr[4]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[4]),
+        .O(s_amesg[5]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[6]_i_1 
+       (.I0(s_axi_araddr[5]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[5]),
+        .O(s_amesg[6]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[7]_i_1 
+       (.I0(s_axi_araddr[6]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[6]),
+        .O(s_amesg[7]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[8]_i_1 
+       (.I0(s_axi_araddr[7]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[7]),
+        .O(s_amesg[8]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[9]_i_1 
+       (.I0(s_axi_araddr[8]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[8]),
+        .O(s_amesg[9]));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[10] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[10]),
+        .Q(Q[9]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[11] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[11]),
+        .Q(Q[10]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[12] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[12]),
+        .Q(Q[11]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[13] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[13]),
+        .Q(Q[12]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[14] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[14]),
+        .Q(Q[13]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[15] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[15]),
+        .Q(Q[14]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[16] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[16]),
+        .Q(Q[15]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[17] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[17]),
+        .Q(Q[16]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[18] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[18]),
+        .Q(Q[17]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[19] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[19]),
+        .Q(Q[18]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[1] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[1]),
+        .Q(Q[0]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[20] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[20]),
+        .Q(Q[19]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[21] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[21]),
+        .Q(Q[20]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[22] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[22]),
+        .Q(Q[21]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[23] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[23]),
+        .Q(Q[22]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[24] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[24]),
+        .Q(Q[23]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[25] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[25]),
+        .Q(Q[24]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[26] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[26]),
+        .Q(Q[25]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[27] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[27]),
+        .Q(Q[26]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[28] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[28]),
+        .Q(Q[27]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[29] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[29]),
+        .Q(Q[28]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[2] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[2]),
+        .Q(Q[1]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[30] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[30]),
+        .Q(Q[29]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[31] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[31]),
+        .Q(Q[30]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[32] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[32]),
+        .Q(Q[31]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[3] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[3]),
+        .Q(Q[2]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[46] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[46]),
+        .Q(Q[32]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[47] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[47]),
+        .Q(Q[33]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[48] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[48]),
+        .Q(Q[34]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[4] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[4]),
+        .Q(Q[3]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[5] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[5]),
+        .Q(Q[4]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[6] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[6]),
+        .Q(Q[5]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[7] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[7]),
+        .Q(Q[6]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[8] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[8]),
+        .Q(Q[7]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[9] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[9]),
+        .Q(Q[8]),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0000000088888088)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_1 
+       (.I0(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
+        .I1(aresetn_d),
+        .I2(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
+        .I3(m_ready_d0),
+        .I4(\\m_ready_d_reg[1] ),
+        .I5(\\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT4 #(
+    .INIT(16\'hF0FE)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_2 
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_arvalid),
+        .I2(aa_grant_any),
+        .I3(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_3 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h54000000)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_5 
+       (.I0(m_valid_i_reg),
+        .I1(m_ready_d_0[1]),
+        .I2(\\gen_axilite.s_axi_arready_i_reg ),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ));
+  FDRE \\gen_no_arbiter.m_grant_hot_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
+        .Q(aa_grant_any),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h3AFA3A0A3AFA3AFA)) 
+    \\gen_no_arbiter.m_valid_i_i_1 
+       (.I0(aa_grant_any),
+        .I1(\\gen_no_arbiter.m_valid_i_i_2_n_0 ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(\\m_ready_d_reg[1] ),
+        .I5(m_ready_d0),
+        .O(\\gen_no_arbiter.m_valid_i_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h0000FF80)) 
+    \\gen_no_arbiter.m_valid_i_i_2 
+       (.I0(\\gen_axilite.s_axi_arready_i_reg ),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(m_ready_d_0[1]),
+        .I4(m_valid_i_reg),
+        .O(\\gen_no_arbiter.m_valid_i_i_2_n_0 ));
+  FDRE \\gen_no_arbiter.m_valid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_valid_i_i_1_n_0 ),
+        .Q(m_valid_i),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT3 #(
+    .INIT(8\'h40)) 
+    \\gen_no_arbiter.s_ready_i[0]_i_1 
+       (.I0(m_valid_i),
+        .I1(aa_grant_any),
+        .I2(aresetn_d),
+        .O(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.s_ready_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
+        .Q(s_ready_i),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFFFFFEFF)) 
+    \\m_atarget_enc[1]_i_1 
+       (.I0(\\m_atarget_enc[1]_i_2_n_0 ),
+        .I1(\\m_atarget_enc[1]_i_3_n_0 ),
+        .I2(\\m_atarget_enc[1]_i_4_n_0 ),
+        .I3(Q[30]),
+        .I4(Q[23]),
+        .I5(Q[27]),
+        .O(any_error));
+  LUT4 #(
+    .INIT(16\'hFFEF)) 
+    \\m_atarget_enc[1]_i_2 
+       (.I0(Q[25]),
+        .I1(Q[20]),
+        .I2(Q[21]),
+        .I3(Q[29]),
+        .O(\\m_atarget_enc[1]_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFD)) 
+    \\m_atarget_enc[1]_i_3 
+       (.I0(Q[24]),
+        .I1(Q[26]),
+        .I2(Q[19]),
+        .I3(Q[18]),
+        .O(\\m_atarget_enc[1]_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\m_atarget_enc[1]_i_4 
+       (.I0(Q[17]),
+        .I1(Q[31]),
+        .I2(Q[22]),
+        .I3(Q[28]),
+        .O(\\m_atarget_enc[1]_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\m_atarget_hot[0]_i_1 
+       (.I0(Q[16]),
+        .I1(aa_grant_any),
+        .I2(any_error),
+        .O(D[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\m_atarget_hot[1]_i_1 
+       (.I0(Q[16]),
+        .I1(aa_grant_any),
+        .I2(any_error),
+        .O(D[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_atarget_hot[3]_i_1 
+       (.I0(any_error),
+        .I1(aa_grant_any),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[1]));
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[0]));
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[1]));
+  LUT5 #(
+    .INIT(32\'h0080FFFF)) 
+    \\m_payload_i[34]_i_1 
+       (.I0(s_axi_rready),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[0]),
+        .I4(sr_rvalid),
+        .O(E));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'hF4F0F0F0)) 
+    \\m_ready_d[2]_i_2 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d[0]),
+        .I3(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .I4(s_axi_bready),
+        .O(m_ready_d0));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h4555)) 
+    \\m_ready_d[2]_i_3 
+       (.I0(m_ready_d[2]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(\\gen_axilite.s_axi_awready_i_reg_0 ),
+        .O(\\m_ready_d_reg[2] ));
+  LUT5 #(
+    .INIT(32\'h0B0F0F0F)) 
+    \\m_ready_d[2]_i_4 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d[1]),
+        .I3(s_axi_wvalid),
+        .I4(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .O(\\m_ready_d_reg[2]_0 ));
+  LUT5 #(
+    .INIT(32\'h8AAAAAAA)) 
+    m_valid_i_i_2
+       (.I0(aa_rready),
+        .I1(m_ready_d_0[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(\\gen_axilite.s_axi_rvalid_i_reg ),
+        .O(s_ready_i_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT4 #(
+    .INIT(16\'h0040)) 
+    \\s_arvalid_reg[0]_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_arvalid),
+        .I2(aresetn_d),
+        .I3(s_ready_i),
+        .O(\\s_arvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_arvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_arvalid_reg[0]_i_1_n_0 ),
+        .Q(\\s_arvalid_reg_reg_n_0_[0] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h0000000000D00000)) 
+    \\s_awvalid_reg[0]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_awvalid_reg),
+        .I2(s_axi_awvalid),
+        .I3(\\s_arvalid_reg_reg_n_0_[0] ),
+        .I4(aresetn_d),
+        .I5(s_ready_i),
+        .O(\\s_awvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_awvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_awvalid_reg[0]_i_1_n_0 ),
+        .Q(s_awvalid_reg),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_arready[0]_INST_0 
+       (.I0(s_ready_i),
+        .I1(aa_grant_rnw),
+        .O(s_axi_arready));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_awready[0]_INST_0 
+       (.I0(s_ready_i),
+        .I1(aa_grant_rnw),
+        .O(s_axi_awready));
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\s_axi_bvalid[0]_INST_0 
+       (.I0(aa_grant_any),
+        .I1(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .I2(m_ready_d[0]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(s_axi_bvalid));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_rvalid[0]_INST_0 
+       (.I0(aa_grant_any),
+        .I1(sr_rvalid),
+        .O(s_axi_rvalid));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\s_axi_wready[0]_INST_0 
+       (.I0(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .I1(aa_grant_any),
+        .I2(m_ready_d[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(s_axi_wready));
+endmodule
+
+(* C_AXI_ADDR_WIDTH = ""32"" *) (* C_AXI_ARUSER_WIDTH = ""1"" *) (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+(* C_AXI_BUSER_WIDTH = ""1"" *) (* C_AXI_DATA_WIDTH = ""32"" *) (* C_AXI_ID_WIDTH = ""1"" *) 
+(* C_AXI_PROTOCOL = ""2"" *) (* C_AXI_RUSER_WIDTH = ""1"" *) (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+(* C_AXI_WUSER_WIDTH = ""1"" *) (* C_CONNECTIVITY_MODE = ""0"" *) (* C_DEBUG = ""1"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_M_AXI_ADDR_WIDTH = ""96\'b000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000"" *) (* C_M_AXI_BASE_ADDR = ""192\'b111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+(* C_M_AXI_READ_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_READ_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_SECURE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+(* C_M_AXI_WRITE_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_WRITE_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_NUM_ADDR_RANGES = ""1"" *) 
+(* C_NUM_MASTER_SLOTS = ""3"" *) (* C_NUM_SLAVE_SLOTS = ""1"" *) (* C_R_REGISTER = ""1"" *) 
+(* C_S_AXI_ARB_PRIORITY = ""0"" *) (* C_S_AXI_BASE_ID = ""0"" *) (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+(* C_S_AXI_SINGLE_THREAD = ""1"" *) (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+(* DowngradeIPIdentifiedWarnings = ""yes"" *) (* P_ADDR_DECODE = ""1"" *) (* P_AXI3 = ""1"" *) 
+(* P_AXI4 = ""0"" *) (* P_AXILITE = ""2"" *) (* P_AXILITE_SIZE = ""3\'b010"" *) 
+(* P_FAMILY = ""zynq"" *) (* P_INCR = ""2\'b01"" *) (* P_LEN = ""8"" *) 
+(* P_LOCK = ""1"" *) (* P_M_AXI_ERR_MODE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) (* P_M_AXI_SUPPORTS_READ = ""3\'b111"" *) 
+(* P_M_AXI_SUPPORTS_WRITE = ""3\'b111"" *) (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) (* P_RANGE_CHECK = ""1"" *) 
+(* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+(* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awqos,
+    s_axi_awuser,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wuser,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_buser,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arqos,
+    s_axi_aruser,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_ruser,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awid,
+    m_axi_awaddr,
+    m_axi_awlen,
+    m_axi_awsize,
+    m_axi_awburst,
+    m_axi_awlock,
+    m_axi_awcache,
+    m_axi_awprot,
+    m_axi_awregion,
+    m_axi_awqos,
+    m_axi_awuser,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wid,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wlast,
+    m_axi_wuser,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bid,
+    m_axi_bresp,
+    m_axi_buser,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_arid,
+    m_axi_araddr,
+    m_axi_arlen,
+    m_axi_arsize,
+    m_axi_arburst,
+    m_axi_arlock,
+    m_axi_arcache,
+    m_axi_arprot,
+    m_axi_arregion,
+    m_axi_arqos,
+    m_axi_aruser,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rlast,
+    m_axi_ruser,
+    m_axi_rvalid,
+    m_axi_rready);
+  input aclk;
+  input aresetn;
+  input [0:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [7:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [0:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awqos;
+  input [0:0]s_axi_awuser;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [0:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wlast;
+  input [0:0]s_axi_wuser;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [0:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_buser;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [0:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [7:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [0:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arqos;
+  input [0:0]s_axi_aruser;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rlast;
+  output [0:0]s_axi_ruser;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [2:0]m_axi_awid;
+  output [95:0]m_axi_awaddr;
+  output [23:0]m_axi_awlen;
+  output [8:0]m_axi_awsize;
+  output [5:0]m_axi_awburst;
+  output [2:0]m_axi_awlock;
+  output [11:0]m_axi_awcache;
+  output [8:0]m_axi_awprot;
+  output [11:0]m_axi_awregion;
+  output [11:0]m_axi_awqos;
+  output [2:0]m_axi_awuser;
+  output [2:0]m_axi_awvalid;
+  input [2:0]m_axi_awready;
+  output [2:0]m_axi_wid;
+  output [95:0]m_axi_wdata;
+  output [11:0]m_axi_wstrb;
+  output [2:0]m_axi_wlast;
+  output [2:0]m_axi_wuser;
+  output [2:0]m_axi_wvalid;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bid;
+  input [5:0]m_axi_bresp;
+  input [2:0]m_axi_buser;
+  input [2:0]m_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [2:0]m_axi_arid;
+  output [95:0]m_axi_araddr;
+  output [23:0]m_axi_arlen;
+  output [8:0]m_axi_arsize;
+  output [5:0]m_axi_arburst;
+  output [2:0]m_axi_arlock;
+  output [11:0]m_axi_arcache;
+  output [8:0]m_axi_arprot;
+  output [11:0]m_axi_arregion;
+  output [11:0]m_axi_arqos;
+  output [2:0]m_axi_aruser;
+  output [2:0]m_axi_arvalid;
+  input [2:0]m_axi_arready;
+  input [2:0]m_axi_rid;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rlast;
+  input [2:0]m_axi_ruser;
+  input [2:0]m_axi_rvalid;
+  output [2:0]m_axi_rready;
+
+  wire \\<const0> ;
+  wire aclk;
+  wire aresetn;
+  wire [15:0]\\^m_axi_araddr ;
+  wire [2:0]\\^m_axi_arprot ;
+  wire [2:0]m_axi_arready;
+  wire [1:0]\\^m_axi_arvalid ;
+  wire [95:80]\\^m_axi_awaddr ;
+  wire [2:0]m_axi_awready;
+  wire [1:0]\\^m_axi_awvalid ;
+  wire [1:0]\\^m_axi_bready ;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [1:0]\\^m_axi_rready ;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [1:0]\\^m_axi_wvalid ;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+
+  assign m_axi_araddr[95:80] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[79:64] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[63:48] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[31:16] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_arburst[5] = \\<const0> ;
+  assign m_axi_arburst[4] = \\<const0> ;
+  assign m_axi_arburst[3] = \\<const0> ;
+  assign m_axi_arburst[2] = \\<const0> ;
+  assign m_axi_arburst[1] = \\<const0> ;
+  assign m_axi_arburst[0] = \\<const0> ;
+  assign m_axi_arcache[11] = \\<const0> ;
+  assign m_axi_arcache[10] = \\<const0> ;
+  assign m_axi_arcache[9] = \\<const0> ;
+  assign m_axi_arcache[8] = \\<const0> ;
+  assign m_axi_arcache[7] = \\<const0> ;
+  assign m_axi_arcache[6] = \\<const0> ;
+  assign m_axi_arcache[5] = \\<const0> ;
+  assign m_axi_arcache[4] = \\<const0> ;
+  assign m_axi_arcache[3] = \\<const0> ;
+  assign m_axi_arcache[2] = \\<const0> ;
+  assign m_axi_arcache[1] = \\<const0> ;
+  assign m_axi_arcache[0] = \\<const0> ;
+  assign m_axi_arid[2] = \\<const0> ;
+  assign m_axi_arid[1] = \\<const0> ;
+  assign m_axi_arid[0] = \\<const0> ;
+  assign m_axi_arlen[23] = \\<const0> ;
+  assign m_axi_arlen[22] = \\<const0> ;
+  assign m_axi_arlen[21] = \\<const0> ;
+  assign m_axi_arlen[20] = \\<const0> ;
+  assign m_axi_arlen[19] = \\<const0> ;
+  assign m_axi_arlen[18] = \\<const0> ;
+  assign m_axi_arlen[17] = \\<const0> ;
+  assign m_axi_arlen[16] = \\<const0> ;
+  assign m_axi_arlen[15] = \\<const0> ;
+  assign m_axi_arlen[14] = \\<const0> ;
+  assign m_axi_arlen[13] = \\<const0> ;
+  assign m_axi_arlen[12] = \\<const0> ;
+  assign m_axi_arlen[11] = \\<const0> ;
+  assign m_axi_arlen[10] = \\<const0> ;
+  assign m_axi_arlen[9] = \\<const0> ;
+  assign m_axi_arlen[8] = \\<const0> ;
+  assign m_axi_arlen[7] = \\<const0> ;
+  assign m_axi_arlen[6] = \\<const0> ;
+  assign m_axi_arlen[5] = \\<const0> ;
+  assign m_axi_arlen[4] = \\<const0> ;
+  assign m_axi_arlen[3] = \\<const0> ;
+  assign m_axi_arlen[2] = \\<const0> ;
+  assign m_axi_arlen[1] = \\<const0> ;
+  assign m_axi_arlen[0] = \\<const0> ;
+  assign m_axi_arlock[2] = \\<const0> ;
+  assign m_axi_arlock[1] = \\<const0> ;
+  assign m_axi_arlock[0] = \\<const0> ;
+  assign m_axi_arprot[8:6] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_arqos[11] = \\<const0> ;
+  assign m_axi_arqos[10] = \\<const0> ;
+  assign m_axi_arqos[9] = \\<const0> ;
+  assign m_axi_arqos[8] = \\<const0> ;
+  assign m_axi_arqos[7] = \\<const0> ;
+  assign m_axi_arqos[6] = \\<const0> ;
+  assign m_axi_arqos[5] = \\<const0> ;
+  assign m_axi_arqos[4] = \\<const0> ;
+  assign m_axi_arqos[3] = \\<const0> ;
+  assign m_axi_arqos[2] = \\<const0> ;
+  assign m_axi_arqos[1] = \\<const0> ;
+  assign m_axi_arqos[0] = \\<const0> ;
+  assign m_axi_arregion[11] = \\<const0> ;
+  assign m_axi_arregion[10] = \\<const0> ;
+  assign m_axi_arregion[9] = \\<const0> ;
+  assign m_axi_arregion[8] = \\<const0> ;
+  assign m_axi_arregion[7] = \\<const0> ;
+  assign m_axi_arregion[6] = \\<const0> ;
+  assign m_axi_arregion[5] = \\<const0> ;
+  assign m_axi_arregion[4] = \\<const0> ;
+  assign m_axi_arregion[3] = \\<const0> ;
+  assign m_axi_arregion[2] = \\<const0> ;
+  assign m_axi_arregion[1] = \\<const0> ;
+  assign m_axi_arregion[0] = \\<const0> ;
+  assign m_axi_arsize[8] = \\<const0> ;
+  assign m_axi_arsize[7] = \\<const0> ;
+  assign m_axi_arsize[6] = \\<const0> ;
+  assign m_axi_arsize[5] = \\<const0> ;
+  assign m_axi_arsize[4] = \\<const0> ;
+  assign m_axi_arsize[3] = \\<const0> ;
+  assign m_axi_arsize[2] = \\<const0> ;
+  assign m_axi_arsize[1] = \\<const0> ;
+  assign m_axi_arsize[0] = \\<const0> ;
+  assign m_axi_aruser[2] = \\<const0> ;
+  assign m_axi_aruser[1] = \\<const0> ;
+  assign m_axi_aruser[0] = \\<const0> ;
+  assign m_axi_arvalid[2] = \\<const0> ;
+  assign m_axi_arvalid[1:0] = \\^m_axi_arvalid [1:0];
+  assign m_axi_awaddr[95:80] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[79:64] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[63:48] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[31:16] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_awburst[5] = \\<const0> ;
+  assign m_axi_awburst[4] = \\<const0> ;
+  assign m_axi_awburst[3] = \\<const0> ;
+  assign m_axi_awburst[2] = \\<const0> ;
+  assign m_axi_awburst[1] = \\<const0> ;
+  assign m_axi_awburst[0] = \\<const0> ;
+  assign m_axi_awcache[11] = \\<const0> ;
+  assign m_axi_awcache[10] = \\<const0> ;
+  assign m_axi_awcache[9] = \\<const0> ;
+  assign m_axi_awcache[8] = \\<const0> ;
+  assign m_axi_awcache[7] = \\<const0> ;
+  assign m_axi_awcache[6] = \\<const0> ;
+  assign m_axi_awcache[5] = \\<const0> ;
+  assign m_axi_awcache[4] = \\<const0> ;
+  assign m_axi_awcache[3] = \\<const0> ;
+  assign m_axi_awcache[2] = \\<const0> ;
+  assign m_axi_awcache[1] = \\<const0> ;
+  assign m_axi_awcache[0] = \\<const0> ;
+  assign m_axi_awid[2] = \\<const0> ;
+  assign m_axi_awid[1] = \\<const0> ;
+  assign m_axi_awid[0] = \\<const0> ;
+  assign m_axi_awlen[23] = \\<const0> ;
+  assign m_axi_awlen[22] = \\<const0> ;
+  assign m_axi_awlen[21] = \\<const0> ;
+  assign m_axi_awlen[20] = \\<const0> ;
+  assign m_axi_awlen[19] = \\<const0> ;
+  assign m_axi_awlen[18] = \\<const0> ;
+  assign m_axi_awlen[17] = \\<const0> ;
+  assign m_axi_awlen[16] = \\<const0> ;
+  assign m_axi_awlen[15] = \\<const0> ;
+  assign m_axi_awlen[14] = \\<const0> ;
+  assign m_axi_awlen[13] = \\<const0> ;
+  assign m_axi_awlen[12] = \\<const0> ;
+  assign m_axi_awlen[11] = \\<const0> ;
+  assign m_axi_awlen[10] = \\<const0> ;
+  assign m_axi_awlen[9] = \\<const0> ;
+  assign m_axi_awlen[8] = \\<const0> ;
+  assign m_axi_awlen[7] = \\<const0> ;
+  assign m_axi_awlen[6] = \\<const0> ;
+  assign m_axi_awlen[5] = \\<const0> ;
+  assign m_axi_awlen[4] = \\<const0> ;
+  assign m_axi_awlen[3] = \\<const0> ;
+  assign m_axi_awlen[2] = \\<const0> ;
+  assign m_axi_awlen[1] = \\<const0> ;
+  assign m_axi_awlen[0] = \\<const0> ;
+  assign m_axi_awlock[2] = \\<const0> ;
+  assign m_axi_awlock[1] = \\<const0> ;
+  assign m_axi_awlock[0] = \\<const0> ;
+  assign m_axi_awprot[8:6] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_awqos[11] = \\<const0> ;
+  assign m_axi_awqos[10] = \\<const0> ;
+  assign m_axi_awqos[9] = \\<const0> ;
+  assign m_axi_awqos[8] = \\<const0> ;
+  assign m_axi_awqos[7] = \\<const0> ;
+  assign m_axi_awqos[6] = \\<const0> ;
+  assign m_axi_awqos[5] = \\<const0> ;
+  assign m_axi_awqos[4] = \\<const0> ;
+  assign m_axi_awqos[3] = \\<const0> ;
+  assign m_axi_awqos[2] = \\<const0> ;
+  assign m_axi_awqos[1] = \\<const0> ;
+  assign m_axi_awqos[0] = \\<const0> ;
+  assign m_axi_awregion[11] = \\<const0> ;
+  assign m_axi_awregion[10] = \\<const0> ;
+  assign m_axi_awregion[9] = \\<const0> ;
+  assign m_axi_awregion[8] = \\<const0> ;
+  assign m_axi_awregion[7] = \\<const0> ;
+  assign m_axi_awregion[6] = \\<const0> ;
+  assign m_axi_awregion[5] = \\<const0> ;
+  assign m_axi_awregion[4] = \\<const0> ;
+  assign m_axi_awregion[3] = \\<const0> ;
+  assign m_axi_awregion[2] = \\<const0> ;
+  assign m_axi_awregion[1] = \\<const0> ;
+  assign m_axi_awregion[0] = \\<const0> ;
+  assign m_axi_awsize[8] = \\<const0> ;
+  assign m_axi_awsize[7] = \\<const0> ;
+  assign m_axi_awsize[6] = \\<const0> ;
+  assign m_axi_awsize[5] = \\<const0> ;
+  assign m_axi_awsize[4] = \\<const0> ;
+  assign m_axi_awsize[3] = \\<const0> ;
+  assign m_axi_awsize[2] = \\<const0> ;
+  assign m_axi_awsize[1] = \\<const0> ;
+  assign m_axi_awsize[0] = \\<const0> ;
+  assign m_axi_awuser[2] = \\<const0> ;
+  assign m_axi_awuser[1] = \\<const0> ;
+  assign m_axi_awuser[0] = \\<const0> ;
+  assign m_axi_awvalid[2] = \\<const0> ;
+  assign m_axi_awvalid[1:0] = \\^m_axi_awvalid [1:0];
+  assign m_axi_bready[2] = \\<const0> ;
+  assign m_axi_bready[1:0] = \\^m_axi_bready [1:0];
+  assign m_axi_rready[2] = \\<const0> ;
+  assign m_axi_rready[1:0] = \\^m_axi_rready [1:0];
+  assign m_axi_wdata[95:64] = s_axi_wdata;
+  assign m_axi_wdata[63:32] = s_axi_wdata;
+  assign m_axi_wdata[31:0] = s_axi_wdata;
+  assign m_axi_wid[2] = \\<const0> ;
+  assign m_axi_wid[1] = \\<const0> ;
+  assign m_axi_wid[0] = \\<const0> ;
+  assign m_axi_wlast[2] = \\<const0> ;
+  assign m_axi_wlast[1] = \\<const0> ;
+  assign m_axi_wlast[0] = \\<const0> ;
+  assign m_axi_wstrb[11:8] = s_axi_wstrb;
+  assign m_axi_wstrb[7:4] = s_axi_wstrb;
+  assign m_axi_wstrb[3:0] = s_axi_wstrb;
+  assign m_axi_wuser[2] = \\<const0> ;
+  assign m_axi_wuser[1] = \\<const0> ;
+  assign m_axi_wuser[0] = \\<const0> ;
+  assign m_axi_wvalid[2] = \\<const0> ;
+  assign m_axi_wvalid[1:0] = \\^m_axi_wvalid [1:0];
+  assign s_axi_bid[0] = \\<const0> ;
+  assign s_axi_buser[0] = \\<const0> ;
+  assign s_axi_rid[0] = \\<const0> ;
+  assign s_axi_rlast[0] = \\<const0> ;
+  assign s_axi_ruser[0] = \\<const0> ;
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd \\gen_sasd.crossbar_sasd_0 
+       (.Q({\\^m_axi_arprot ,\\^m_axi_awaddr ,\\^m_axi_araddr }),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(\\^m_axi_arvalid ),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(\\^m_axi_awvalid ),
+        .m_axi_bready(\\^m_axi_bready ),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(\\^m_axi_rready ),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wvalid(\\^m_axi_wvalid ),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd
+   (Q,
+    \\s_axi_rdata[31] ,
+    s_axi_bvalid,
+    m_axi_bready,
+    s_axi_wready,
+    m_axi_wvalid,
+    m_axi_awvalid,
+    m_axi_arvalid,
+    s_axi_awready,
+    s_axi_arready,
+    s_axi_rvalid,
+    m_axi_rready,
+    s_axi_bresp,
+    s_axi_rready,
+    aresetn,
+    aclk,
+    s_axi_wvalid,
+    s_axi_bready,
+    m_axi_arready,
+    m_axi_awready,
+    m_axi_wready,
+    m_axi_bvalid,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    m_axi_rvalid,
+    m_axi_rresp,
+    m_axi_rdata,
+    m_axi_bresp,
+    s_axi_awvalid);
+  output [34:0]Q;
+  output [33:0]\\s_axi_rdata[31] ;
+  output [0:0]s_axi_bvalid;
+  output [1:0]m_axi_bready;
+  output [0:0]s_axi_wready;
+  output [1:0]m_axi_wvalid;
+  output [1:0]m_axi_awvalid;
+  output [1:0]m_axi_arvalid;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rvalid;
+  output [1:0]m_axi_rready;
+  output [1:0]s_axi_bresp;
+  input [0:0]s_axi_rready;
+  input aresetn;
+  input aclk;
+  input [0:0]s_axi_wvalid;
+  input [0:0]s_axi_bready;
+  input [2:0]m_axi_arready;
+  input [2:0]m_axi_awready;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bvalid;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input [2:0]m_axi_rvalid;
+  input [5:0]m_axi_rresp;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_bresp;
+  input [0:0]s_axi_awvalid;
+
+  wire [34:0]Q;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire addr_arbiter_inst_n_3;
+  wire addr_arbiter_inst_n_42;
+  wire addr_arbiter_inst_n_47;
+  wire addr_arbiter_inst_n_51;
+  wire addr_arbiter_inst_n_52;
+  wire addr_arbiter_inst_n_55;
+  wire addr_arbiter_inst_n_56;
+  wire addr_arbiter_inst_n_60;
+  wire any_error;
+  wire aresetn;
+  wire aresetn_d;
+  wire \\gen_decerr.decerr_slave_inst_n_0 ;
+  wire \\gen_decerr.decerr_slave_inst_n_1 ;
+  wire \\gen_decerr.decerr_slave_inst_n_2 ;
+  wire \\gen_decerr.decerr_slave_inst_n_3 ;
+  wire \\gen_decerr.decerr_slave_inst_n_4 ;
+  wire \\gen_decerr.decerr_slave_inst_n_5 ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc[0]_i_1_n_0 ;
+  wire [3:0]m_atarget_hot;
+  wire [1:0]m_atarget_hot0;
+  wire [2:0]m_axi_arready;
+  wire [1:0]m_axi_arvalid;
+  wire [2:0]m_axi_awready;
+  wire [1:0]m_axi_awvalid;
+  wire [1:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [1:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [1:0]m_axi_wvalid;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire [2:0]m_ready_d_0;
+  wire m_valid_i;
+  wire p_1_in;
+  wire reg_slice_r_n_2;
+  wire reset;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire splitter_aw_n_0;
+  wire sr_rvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd addr_arbiter_inst
+       (.D({addr_arbiter_inst_n_3,m_atarget_hot0}),
+        .E(p_1_in),
+        .Q(Q),
+        .SR(reset),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .any_error(any_error),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_arready_i_reg (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\gen_axilite.s_axi_awready_i_reg (addr_arbiter_inst_n_52),
+        .\\gen_axilite.s_axi_awready_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_2 ),
+        .\\gen_axilite.s_axi_awready_i_reg_1 (\\gen_decerr.decerr_slave_inst_n_1 ),
+        .\\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_47),
+        .\\gen_axilite.s_axi_bvalid_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\gen_axilite.s_axi_rvalid_i_reg (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (addr_arbiter_inst_n_55),
+        .\\m_atarget_hot_reg[1] (m_atarget_hot[1:0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_wvalid(m_axi_wvalid),
+        .m_ready_d(m_ready_d_0),
+        .m_ready_d0(m_ready_d0),
+        .m_ready_d_0(m_ready_d),
+        .\\m_ready_d_reg[1] (\\gen_decerr.decerr_slave_inst_n_0 ),
+        .\\m_ready_d_reg[2] (addr_arbiter_inst_n_42),
+        .\\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_51),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg(reg_slice_r_n_2),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid),
+        .s_ready_i_reg(addr_arbiter_inst_n_56),
+        .s_ready_i_reg_0(addr_arbiter_inst_n_60),
+        .sr_rvalid(sr_rvalid));
+  FDRE #(
+    .INIT(1\'b0)) 
+    aresetn_d_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(aresetn),
+        .Q(aresetn_d),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave \\gen_decerr.decerr_slave_inst 
+       (.Q(m_atarget_enc),
+        .SR(reset),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_55),
+        .\\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_47),
+        .\\gen_no_arbiter.grant_rnw_reg_1 (addr_arbiter_inst_n_60),
+        .\\gen_no_arbiter.grant_rnw_reg_2 (addr_arbiter_inst_n_52),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0] (\\gen_decerr.decerr_slave_inst_n_0 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (\\gen_decerr.decerr_slave_inst_n_1 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_1 (\\gen_decerr.decerr_slave_inst_n_2 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_2 (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\m_atarget_hot_reg[3] (m_atarget_hot[3]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_ready_d(m_ready_d_0[2:1]),
+        .m_ready_d_0(m_ready_d[1]),
+        .\\m_ready_d_reg[1] (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\m_ready_d_reg[1]_0 (splitter_aw_n_0),
+        .s_axi_wvalid(s_axi_wvalid),
+        .s_ready_i_reg(\\gen_decerr.decerr_slave_inst_n_5 ));
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\m_atarget_enc[0]_i_1 
+       (.I0(Q[16]),
+        .I1(any_error),
+        .O(\\m_atarget_enc[0]_i_1_n_0 ));
+  FDRE \\m_atarget_enc_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_enc[0]_i_1_n_0 ),
+        .Q(m_atarget_enc[0]),
+        .R(reset));
+  FDRE \\m_atarget_enc_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(any_error),
+        .Q(m_atarget_enc[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_atarget_hot0[0]),
+        .Q(m_atarget_hot[0]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_atarget_hot0[1]),
+        .Q(m_atarget_hot[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_3),
+        .Q(m_atarget_hot[3]),
+        .R(reset));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice reg_slice_r
+       (.E(p_1_in),
+        .Q(m_atarget_hot[1:0]),
+        .SR(reset),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_60),
+        .\\m_atarget_enc_reg[1] (m_atarget_enc),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_ready_d(m_ready_d[0]),
+        .\\m_ready_d_reg[1] (reg_slice_r_n_2),
+        .m_valid_i(m_valid_i),
+        .\\s_axi_rdata[31] (\\s_axi_rdata[31] ),
+        .s_axi_rready(s_axi_rready),
+        .s_ready_i_reg_0(addr_arbiter_inst_n_56),
+        .sr_rvalid(sr_rvalid));
+  LUT5 #(
+    .INIT(32\'hFEF2CEC2)) 
+    \\s_axi_bresp[0]_INST_0 
+       (.I0(m_axi_bresp[0]),
+        .I1(m_atarget_enc[1]),
+        .I2(m_atarget_enc[0]),
+        .I3(m_axi_bresp[4]),
+        .I4(m_axi_bresp[2]),
+        .O(s_axi_bresp[0]));
+  LUT5 #(
+    .INIT(32\'hFEF2CEC2)) 
+    \\s_axi_bresp[1]_INST_0 
+       (.I0(m_axi_bresp[1]),
+        .I1(m_atarget_enc[1]),
+        .I2(m_atarget_enc[0]),
+        .I3(m_axi_bresp[5]),
+        .I4(m_axi_bresp[3]),
+        .O(s_axi_bresp[1]));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0 splitter_ar
+       (.aa_grant_rnw(aa_grant_rnw),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_arready_i_reg (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .m_ready_d(m_ready_d),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg(reg_slice_r_n_2));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter splitter_aw
+       (.Q(m_atarget_hot[3]),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_bvalid_i_reg (splitter_aw_n_0),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_51),
+        .m_ready_d(m_ready_d_0),
+        .m_ready_d0(m_ready_d0),
+        .\\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_42),
+        .m_valid_i(m_valid_i),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave
+   (\\gen_no_arbiter.m_grant_hot_i_reg[0] ,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ,
+    \\m_ready_d_reg[1] ,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ,
+    s_ready_i_reg,
+    SR,
+    aclk,
+    s_axi_wvalid,
+    m_ready_d,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    m_axi_arready,
+    Q,
+    m_axi_awready,
+    m_axi_wready,
+    m_axi_bvalid,
+    m_axi_rvalid,
+    \\m_atarget_hot_reg[3] ,
+    \\gen_no_arbiter.grant_rnw_reg_0 ,
+    \\m_ready_d_reg[1]_0 ,
+    m_ready_d_0,
+    \\gen_no_arbiter.grant_rnw_reg_1 ,
+    aa_rready,
+    aresetn_d,
+    \\gen_no_arbiter.grant_rnw_reg_2 );
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0] ;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ;
+  output \\m_ready_d_reg[1] ;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ;
+  output s_ready_i_reg;
+  input [0:0]SR;
+  input aclk;
+  input [0:0]s_axi_wvalid;
+  input [1:0]m_ready_d;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input [2:0]m_axi_arready;
+  input [1:0]Q;
+  input [2:0]m_axi_awready;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bvalid;
+  input [2:0]m_axi_rvalid;
+  input [0:0]\\m_atarget_hot_reg[3] ;
+  input \\gen_no_arbiter.grant_rnw_reg_0 ;
+  input \\m_ready_d_reg[1]_0 ;
+  input [0:0]m_ready_d_0;
+  input \\gen_no_arbiter.grant_rnw_reg_1 ;
+  input aa_rready;
+  input aresetn_d;
+  input \\gen_no_arbiter.grant_rnw_reg_2 ;
+
+  wire [1:0]Q;
+  wire [0:0]SR;
+  wire aa_rready;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_awready_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_bvalid_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg_0 ;
+  wire \\gen_no_arbiter.grant_rnw_reg_1 ;
+  wire \\gen_no_arbiter.grant_rnw_reg_2 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0] ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ;
+  wire [0:0]\\m_atarget_hot_reg[3] ;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_bvalid;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d_0;
+  wire \\m_ready_d_reg[1] ;
+  wire \\m_ready_d_reg[1]_0 ;
+  wire [3:3]mi_arready;
+  wire [3:3]mi_bvalid;
+  wire [3:3]mi_rvalid;
+  wire [3:3]mi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire s_ready_i_reg;
+
+  LUT6 #(
+    .INIT(64\'hAAAAA8AA0000AAAA)) 
+    \\gen_axilite.s_axi_arready_i_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_no_arbiter.grant_rnw_reg_1 ),
+        .I2(m_ready_d_0),
+        .I3(\\m_atarget_hot_reg[3] ),
+        .I4(mi_rvalid),
+        .I5(mi_arready),
+        .O(\\gen_axilite.s_axi_arready_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_arready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_arready_i_i_1_n_0 ),
+        .Q(mi_arready),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFEF00000010)) 
+    \\gen_axilite.s_axi_awready_i_i_1 
+       (.I0(mi_bvalid),
+        .I1(\\gen_no_arbiter.grant_rnw_reg_2 ),
+        .I2(\\m_atarget_hot_reg[3] ),
+        .I3(m_ready_d[1]),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(mi_wready),
+        .O(\\gen_axilite.s_axi_awready_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_awready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_awready_i_i_1_n_0 ),
+        .Q(mi_wready),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h77F07700)) 
+    \\gen_axilite.s_axi_bvalid_i_i_1 
+       (.I0(\\m_atarget_hot_reg[3] ),
+        .I1(\\gen_no_arbiter.grant_rnw_reg_0 ),
+        .I2(mi_wready),
+        .I3(mi_bvalid),
+        .I4(\\m_ready_d_reg[1]_0 ),
+        .O(\\gen_axilite.s_axi_bvalid_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_bvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_bvalid_i_i_1_n_0 ),
+        .Q(mi_bvalid),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h00FFFFFF02020000)) 
+    \\gen_axilite.s_axi_rvalid_i_i_1 
+       (.I0(mi_arready),
+        .I1(m_ready_d_0),
+        .I2(\\gen_no_arbiter.grant_rnw_reg_1 ),
+        .I3(aa_rready),
+        .I4(\\m_atarget_hot_reg[3] ),
+        .I5(mi_rvalid),
+        .O(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_rvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
+        .Q(mi_rvalid),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0F0F0707FFFF07FF)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_4 
+       (.I0(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d[0]),
+        .I3(\\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(m_ready_d[1]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\m_ready_d[1]_i_2 
+       (.I0(mi_arready),
+        .I1(m_axi_arready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_arready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_arready[0]),
+        .O(\\m_ready_d_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\m_ready_d[2]_i_5 
+       (.I0(mi_wready),
+        .I1(m_axi_awready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_awready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_awready[0]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    m_valid_i_i_3
+       (.I0(mi_rvalid),
+        .I1(m_axi_rvalid[1]),
+        .I2(Q[0]),
+        .I3(m_axi_rvalid[2]),
+        .I4(Q[1]),
+        .I5(m_axi_rvalid[0]),
+        .O(s_ready_i_reg));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\s_axi_bvalid[0]_INST_0_i_1 
+       (.I0(mi_bvalid),
+        .I1(m_axi_bvalid[1]),
+        .I2(Q[0]),
+        .I3(m_axi_bvalid[2]),
+        .I4(Q[1]),
+        .I5(m_axi_bvalid[0]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\s_axi_wready[0]_INST_0_i_1 
+       (.I0(mi_wready),
+        .I1(m_axi_wready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_wready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_wready[0]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter
+   (\\gen_axilite.s_axi_bvalid_i_reg ,
+    m_ready_d,
+    s_axi_wvalid,
+    Q,
+    m_valid_i,
+    aa_grant_rnw,
+    aresetn_d,
+    m_ready_d0,
+    \\m_ready_d_reg[2]_0 ,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    aclk);
+  output \\gen_axilite.s_axi_bvalid_i_reg ;
+  output [2:0]m_ready_d;
+  input [0:0]s_axi_wvalid;
+  input [0:0]Q;
+  input m_valid_i;
+  input aa_grant_rnw;
+  input aresetn_d;
+  input [0:0]m_ready_d0;
+  input \\m_ready_d_reg[2]_0 ;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input aclk;
+
+  wire [0:0]Q;
+  wire aa_grant_rnw;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire [2:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire \\m_ready_d[2]_i_1_n_0 ;
+  wire \\m_ready_d_reg[2]_0 ;
+  wire m_valid_i;
+  wire [0:0]s_axi_wvalid;
+
+  LUT6 #(
+    .INIT(64\'h0000000000200000)) 
+    \\gen_axilite.s_axi_bvalid_i_i_3 
+       (.I0(s_axi_wvalid),
+        .I1(m_ready_d[1]),
+        .I2(Q),
+        .I3(m_ready_d[2]),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg ));
+  LUT4 #(
+    .INIT(16\'h8880)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\m_ready_d_reg[2]_0 ),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT4 #(
+    .INIT(16\'h00A2)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\m_ready_d_reg[2]_0 ),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT4 #(
+    .INIT(16\'h0A02)) 
+    \\m_ready_d[2]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\m_ready_d_reg[2]_0 ),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .O(\\m_ready_d[2]_i_1_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[2]_i_1_n_0 ),
+        .Q(m_ready_d[2]),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_crossbar_v2_1_12_splitter"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0
+   (m_ready_d,
+    aresetn_d,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    m_valid_i,
+    aa_grant_rnw,
+    m_valid_i_reg,
+    aclk);
+  output [1:0]m_ready_d;
+  input aresetn_d;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input m_valid_i;
+  input aa_grant_rnw;
+  input m_valid_i_reg;
+  input aclk;
+
+  wire aa_grant_rnw;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire [1:0]m_ready_d;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire m_valid_i;
+  wire m_valid_i_reg;
+
+  LUT6 #(
+    .INIT(64\'h0000000000002AAA)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(m_ready_d[1]),
+        .I5('b'm_valid_i_reg),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAA800000000000)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(m_ready_d[1]),
+        .I5(m_valid_i_reg),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice
+   (sr_rvalid,
+    aa_rready,
+    \\m_ready_d_reg[1] ,
+    m_axi_rready,
+    \\s_axi_rdata[31] ,
+    aclk,
+    m_ready_d,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    s_axi_rready,
+    s_ready_i_reg_0,
+    aa_grant_rnw,
+    m_valid_i,
+    Q,
+    m_axi_rresp,
+    \\m_atarget_enc_reg[1] ,
+    m_axi_rdata,
+    SR,
+    E);
+  output sr_rvalid;
+  output aa_rready;
+  output \\m_ready_d_reg[1] ;
+  output [1:0]m_axi_rready;
+  output [33:0]\\s_axi_rdata[31] ;
+  input aclk;
+  input [0:0]m_ready_d;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input [0:0]s_axi_rready;
+  input s_ready_i_reg_0;
+  input aa_grant_rnw;
+  input m_valid_i;
+  input [1:0]Q;
+  input [5:0]m_axi_rresp;
+  input [1:0]\\m_atarget_enc_reg[1] ;
+  input [95:0]m_axi_rdata;
+  input [0:0]SR;
+  input [0:0]E;
+
+  wire [0:0]E;
+  wire [1:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire \\aresetn_d_reg_n_0_[0] ;
+  wire \\aresetn_d_reg_n_0_[1] ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire [1:0]\\m_atarget_enc_reg[1] ;
+  wire [95:0]m_axi_rdata;
+  wire [1:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire \\m_payload_i[1]_i_2_n_0 ;
+  wire \\m_payload_i[2]_i_2_n_0 ;
+  wire \\m_payload_i_reg_n_0_[0] ;
+  wire [0:0]m_ready_d;
+  wire \\m_ready_d_reg[1] ;
+  wire m_valid_i;
+  wire m_valid_i_i_1_n_0;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire s_ready_i_i_1_n_0;
+  wire s_ready_i_reg_0;
+  wire [34:0]skid_buffer;
+  wire \\skid_buffer[10]_i_1_n_0 ;
+  wire \\skid_buffer[11]_i_1_n_0 ;
+  wire \\skid_buffer[12]_i_1_n_0 ;
+  wire \\skid_buffer[13]_i_1_n_0 ;
+  wire \\skid_buffer[14]_i_1_n_0 ;
+  wire \\skid_buffer[15]_i_1_n_0 ;
+  wire \\skid_buffer[16]_i_1_n_0 ;
+  wire \\skid_buffer[17]_i_1_n_0 ;
+  wire \\skid_buffer[18]_i_1_n_0 ;
+  wire \\skid_buffer[19]_i_1_n_0 ;
+  wire \\skid_buffer[20]_i_1_n_0 ;
+  wire \\skid_buffer[21]_i_1_n_0 ;
+  wire \\skid_buffer[22]_i_1_n_0 ;
+  wire \\skid_buffer[23]_i_1_n_0 ;
+  wire \\skid_buffer[24]_i_1_n_0 ;
+  wire \\skid_buffer[25]_i_1_n_0 ;
+  wire \\skid_buffer[26]_i_1_n_0 ;
+  wire \\skid_buffer[27]_i_1_n_0 ;
+  wire \\skid_buffer[28]_i_1_n_0 ;
+  wire \\skid_buffer[29]_i_1_n_0 ;
+  wire \\skid_buffer[30]_i_1_n_0 ;
+  wire \\skid_buffer[31]_i_1_n_0 ;
+  wire \\skid_buffer[32]_i_1_n_0 ;
+  wire \\skid_buffer[33]_i_1_n_0 ;
+  wire \\skid_buffer[34]_i_1_n_0 ;
+  wire \\skid_buffer[3]_i_1_n_0 ;
+  wire \\skid_buffer[4]_i_1_n_0 ;
+  wire \\skid_buffer[5]_i_1_n_0 ;
+  wire \\skid_buffer[6]_i_1_n_0 ;
+  wire \\skid_buffer[7]_i_1_n_0 ;
+  wire \\skid_buffer[8]_i_1_n_0 ;
+  wire \\skid_buffer[9]_i_1_n_0 ;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire sr_rvalid;
+
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(1\'b1),
+        .Q(\\aresetn_d_reg_n_0_[0] ),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\aresetn_d_reg_n_0_[0] ),
+        .Q(\\aresetn_d_reg_n_0_[1] ),
+        .R(SR));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[0]_INST_0 
+       (.I0(aa_rready),
+        .I1(Q[0]),
+        .O(m_axi_rready[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[1]_INST_0 
+       (.I0(aa_rready),
+        .I1(Q[1]),
+        .O(m_axi_rready[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1 
+       (.I0(\\skid_buffer[10]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(skid_buffer[10]));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1 
+       (.I0(\\skid_buffer[11]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(skid_buffer[11]));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1 
+       (.I0(\\skid_buffer[12]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(skid_buffer[12]));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1 
+       (.I0(\\skid_buffer[13]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(skid_buffer[13]));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1 
+       (.I0(\\skid_buffer[14]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(skid_buffer[14]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1 
+       (.I0(\\skid_buffer[15]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(skid_buffer[15]));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1 
+       (.I0(\\skid_buffer[16]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(skid_buffer[16]));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1 
+       (.I0(\\skid_buffer[17]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(skid_buffer[17]));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1 
+       (.I0(\\skid_buffer[18]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(skid_buffer[18]));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1 
+       (.I0(\\skid_buffer[19]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(skid_buffer[19]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'h0E)) 
+    \\m_payload_i[1]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[1] ),
+        .I1(aa_rready),
+        .I2(\\m_payload_i[1]_i_2_n_0 ),
+        .O(skid_buffer[1]));
+  LUT6 #(
+    .INIT(64\'h0055330F00000000)) 
+    \\m_payload_i[1]_i_2 
+       (.I0(m_axi_rresp[4]),
+        .I1(m_axi_rresp[2]),
+        .I2(m_axi_rresp[0]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(\\m_atarget_enc_reg[1] [1]),
+        .I5(aa_rready),
+        .O(\\m_payload_i[1]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1 
+       (.I0(\\skid_buffer[20]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(skid_buffer[20]));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1 
+       (.I0(\\skid_buffer[21]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(skid_buffer[21]));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1 
+       (.I0(\\skid_buffer[22]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(skid_buffer[22]));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1 
+       (.I0(\\skid_buffer[23]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(skid_buffer[23]));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1 
+       (.I0(\\skid_buffer[24]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(skid_buffer[24]));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1 
+       (.I0(\\skid_buffer[25]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(skid_buffer[25]));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1 
+       (.I0(\\skid_buffer[26]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(skid_buffer[26]));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1 
+       (.I0(\\skid_buffer[27]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(skid_buffer[27]));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1 
+       (.I0(\\skid_buffer[28]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(skid_buffer[28]));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1 
+       (.I0(\\skid_buffer[29]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(skid_buffer[29]));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'h0E)) 
+    \\m_payload_i[2]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[2] ),
+        .I1(aa_rready),
+        .I2(\\m_payload_i[2]_i_2_n_0 ),
+        .O(skid_buffer[2]));
+  LUT6 #(
+    .INIT(64\'h00220A0000220AAA)) 
+    \\m_payload_i[2]_i_2 
+       (.I0(aa_rready),
+        .I1(m_axi_rresp[5]),
+        .I2(m_axi_rresp[3]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(\\m_atarget_enc_reg[1] [1]),
+        .I5(m_axi_rresp[1]),
+        .O(\\m_payload_i[2]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1 
+       (.I0(\\skid_buffer[30]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(skid_buffer[30]));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_1 
+       (.I0(\\skid_buffer[31]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(skid_buffer[31]));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1 
+       (.I0(\\skid_buffer[32]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(skid_buffer[32]));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1 
+       (.I0(\\skid_buffer[33]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(skid_buffer[33]));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_2 
+       (.I0(\\skid_buffer[34]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(skid_buffer[34]));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1 
+       (.I0(\\skid_buffer[3]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(skid_buffer[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1 
+       (.I0(\\skid_buffer[4]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(skid_buffer[4]));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1 
+       (.I0(\\skid_buffer[5]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(skid_buffer[5]));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1 
+       (.I0(\\skid_buffer[6]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(skid_buffer[6]));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1 
+       (.I0(\\skid_buffer[7]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(skid_buffer[7]));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1 
+       (.I0(\\skid_buffer[8]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(skid_buffer[8]));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1 
+       (.I0(\\skid_buffer[9]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(skid_buffer[9]));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[0]),
+        .Q(\\m_payload_i_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[10]),
+        .Q(\\s_axi_rdata[31] [9]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[11]),
+        .Q(\\s_axi_rdata[31] [10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[12]),
+        .Q(\\s_axi_rdata[31] [11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[13]),
+        .Q(\\s_axi_rdata[31] [12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[14]),
+        .Q(\\s_axi_rdata[31] [13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[15]),
+        .Q(\\s_axi_rdata[31] [14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[16]),
+        .Q(\\s_axi_rdata[31] [15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[17]),
+        .Q(\\s_axi_rdata[31] [16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[18]),
+        .Q(\\s_axi_rdata[31] [17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[19]),
+        .Q(\\s_axi_rdata[31] [18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[1]),
+        .Q(\\s_axi_rdata[31] [0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[20]),
+        .Q(\\s_axi_rdata[31] [19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[21]),
+        .Q(\\s_axi_rdata[31] [20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[22]),
+        .Q(\\s_axi_rdata[31] [21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[23]),
+        .Q(\\s_axi_rdata[31] [22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[24]),
+        .Q(\\s_axi_rdata[31] [23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[25]),
+        .Q(\\s_axi_rdata[31] [24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[26]),
+        .Q(\\s_axi_rdata[31] [25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[27]),
+        .Q(\\s_axi_rdata[31] [26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[28]),
+        .Q(\\s_axi_rdata[31] [27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[29]),
+        .Q(\\s_axi_rdata[31] [28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[2]),
+        .Q(\\s_axi_rdata[31] [1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[30]),
+        .Q(\\s_axi_rdata[31] [29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[31]),
+        .Q(\\s_axi_rdata[31] [30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[32]),
+        .Q(\\s_axi_rdata[31] [31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[33]),
+        .Q(\\s_axi_rdata[31] [32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[34]),
+        .Q(\\s_axi_rdata[31] [33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[3]),
+        .Q(\\s_axi_rdata[31] [2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[4]),
+        .Q(\\s_axi_rdata[31] [3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[5]),
+        .Q(\\s_axi_rdata[31] [4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[6]),
+        .Q(\\s_axi_rdata[31] [5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[7]),
+        .Q(\\s_axi_rdata[31] [6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[8]),
+        .Q(\\s_axi_rdata[31] [7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[9]),
+        .Q(\\s_axi_rdata[31] [8]),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h000000007FFFFFFF)) 
+    \\m_ready_d[1]_i_3 
+       (.I0(sr_rvalid),
+        .I1(\\m_payload_i_reg_n_0_[0] ),
+        .I2(s_axi_rready),
+        .I3(aa_grant_rnw),
+        .I4(m_valid_i),
+        .I5(m_ready_d),
+        .O(\\m_ready_d_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hA2A2A222A2A2A2A2)) 
+    m_valid_i_i_1
+       (.I0(\\aresetn_d_reg_n_0_[1] ),
+        .I1(s_ready_i_reg_0),
+        .I2(sr_rvalid),
+        .I3(m_ready_d),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(s_axi_rready),
+        .O(m_valid_i_i_1_n_0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i_i_1_n_0),
+        .Q(sr_rvalid),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAA222A2222)) 
+    s_ready_i_i_1
+       (.I0(\\aresetn_d_reg_n_0_[0] ),
+        .I1(sr_rvalid),
+        .I2(m_ready_d),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .I4(s_axi_rready),
+        .I5(s_ready_i_reg_0),
+        .O(s_ready_i_i_1_n_0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i_i_1_n_0),
+        .Q(aa_rready),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\skid_buffer[0]_i_1 
+       (.I0(aa_rready),
+        .I1(\\skid_buffer_reg_n_0_[0] ),
+        .O(skid_buffer[0]));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[10]_i_1 
+       (.I0(m_axi_rdata[7]),
+        .I1(m_axi_rdata[39]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[71]),
+        .O(\\skid_buffer[10]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[11]_i_1 
+       (.I0(m_axi_rdata[8]),
+        .I1(m_axi_rdata[40]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[72]),
+        .O(\\skid_buffer[11]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[12]_i_1 
+       (.I0(m_axi_rdata[9]),
+        .I1(m_axi_rdata[41]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[73]),
+        .O(\\skid_buffer[12]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[13]_i_1 
+       (.I0(m_axi_rdata[10]),
+        .I1(m_axi_rdata[74]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[42]),
+        .O(\\skid_buffer[13]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[14]_i_1 
+       (.I0(m_axi_rdata[11]),
+        .I1(m_axi_rdata[43]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[75]),
+        .O(\\skid_buffer[14]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[15]_i_1 
+       (.I0(m_axi_rdata[12]),
+        .I1(m_axi_rdata[44]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[76]),
+        .O(\\skid_buffer[15]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[16]_i_1 
+       (.I0(m_axi_rdata[13]),
+        .I1(m_axi_rdata[45]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[77]),
+        .O(\\skid_buffer[16]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[17]_i_1 
+       (.I0(m_axi_rdata[14]),
+        .I1(m_axi_rdata[46]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[78]),
+        .O(\\skid_buffer[17]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[18]_i_1 
+       (.I0(m_axi_rdata[15]),
+        .I1(m_axi_rdata[47]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[79]),
+        .O(\\skid_buffer[18]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[19]_i_1 
+       (.I0(m_axi_rdata[16]),
+        .I1(m_axi_rdata[48]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[80]),
+        .O(\\skid_buffer[19]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[20]_i_1 
+       (.I0(m_axi_rdata[17]),
+        .I1(m_axi_rdata[49]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[81]),
+        .O(\\skid_buffer[20]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[21]_i_1 
+       (.I0(m_axi_rdata[18]),
+        .I1(m_axi_rdata[50]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[82]),
+        .O(\\skid_buffer[21]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[22]_i_1 
+       (.I0(m_axi_rdata[19]),
+        .I1(m_axi_rdata[51]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[83]),
+        .O(\\skid_buffer[22]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[23]_i_1 
+       (.I0(m_axi_rdata[20]),
+        .I1(m_axi_rdata[52]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[84]),
+        .O(\\skid_buffer[23]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0CAF0CA0)) 
+    \\skid_buffer[24]_i_1 
+       (.I0(m_axi_rdata[85]),
+        .I1(m_axi_rdata[53]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[21]),
+        .O(\\skid_buffer[24]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[25]_i_1 
+       (.I0(m_axi_rdata[22]),
+        .I1(m_axi_rdata[54]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[86]),
+        .O(\\skid_buffer[25]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[26]_i_1 
+       (.I0(m_axi_rdata[23]),
+        .I1(m_axi_rdata[55]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[87]),
+        .O(\\skid_buffer[26]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[27]_i_1 
+       (.I0(m_axi_rdata[24]),
+        .I1(m_axi_rdata[56]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[88]),
+        .O(\\skid_buffer[27]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[28]_i_1 
+       (.I0(m_axi_rdata[25]),
+        .I1(m_axi_rdata[89]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[57]),
+        .O(\\skid_buffer[28]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[29]_i_1 
+       (.I0(m_axi_rdata[26]),
+        .I1(m_axi_rdata[58]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[90]),
+        .O(\\skid_buffer[29]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[30]_i_1 
+       (.I0(m_axi_rdata[27]),
+        .I1(m_axi_rdata[59]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[91]),
+        .O(\\skid_buffer[30]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[31]_i_1 
+       (.I0(m_axi_rdata[28]),
+        .I1(m_axi_rdata[60]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[92]),
+        .O(\\skid_buffer[31]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[32]_i_1 
+       (.I0(m_axi_rdata[29]),
+        .I1(m_axi_rdata[61]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[93]),
+        .O(\\skid_buffer[32]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[33]_i_1 
+       (.I0(m_axi_rdata[30]),
+        .I1(m_axi_rdata[62]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[94]),
+        .O(\\skid_buffer[33]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[34]_i_1 
+       (.I0(m_axi_rdata[31]),
+        .I1(m_axi_rdata[63]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[95]),
+        .O(\\skid_buffer[34]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[3]_i_1 
+       (.I0(m_axi_rdata[0]),
+        .I1(m_axi_rdata[32]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[64]),
+        .O(\\skid_buffer[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[4]_i_1 
+       (.I0(m_axi_rdata[1]),
+        .I1(m_axi_rdata[33]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[65]),
+        .O(\\skid_buffer[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[5]_i_1 
+       (.I0(m_axi_rdata[2]),
+        .I1(m_axi_rdata[34]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[66]),
+        .O(\\skid_buffer[5]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[6]_i_1 
+       (.I0(m_axi_rdata[3]),
+        .I1(m_axi_rdata[35]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[67]),
+        .O(\\skid_buffer[6]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0CAF0CA0)) 
+    \\skid_buffer[7]_i_1 
+       (.I0(m_axi_rdata[68]),
+        .I1(m_axi_rdata[36]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[4]),
+        .O(\\skid_buffer[7]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[8]_i_1 
+       (.I0(m_axi_rdata[5]),
+        .I1(m_axi_rdata[37]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[69]),
+        .O(\\skid_buffer[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[9]_i_1 
+       (.I0(m_axi_rdata[6]),
+        .I1(m_axi_rdata[38]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[70]),
+        .O(\\skid_buffer[9]_i_1_n_0 ));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[10]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[11]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[12]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[13]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[14]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[15]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[16]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[17]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[18]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[19]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[20]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[21]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[22]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[23]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[24]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[25]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[26]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[27]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[28]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[29]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[30]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[31]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[32]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[33]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[34]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[3]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[4]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[5]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[6]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[7]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[8]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[9]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (aclk,
+    aresetn,
+    s_axi_awaddr,
+    s_axi_awprot,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awaddr,
+    m_axi_awprot,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bresp,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_araddr,
+    m_axi_arprot,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rvalid,
+    m_axi_rready);
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLKIF CLK"" *) input aclk;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RSTIF RST"" *) input aresetn;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"" *) input [31:0]s_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"" *) input [2:0]s_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"" *) input [0:0]s_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"" *) output [0:0]s_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WVALID"" *) input [0:0]s_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WREADY"" *) output [0:0]s_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BVALID"" *) output [0:0]s_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BREADY"" *) input [0:0]s_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"" *) input [31:0]s_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"" *) input [2:0]s_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"" *) input [0:0]s_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"" *) output [0:0]s_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RVALID"" *) output [0:0]s_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RREADY"" *) input [0:0]s_axi_rready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]"" *) output [95:0]m_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]"" *) output [8:0]m_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]"" *) output [2:0]m_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]"" *) input [2:0]m_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]"" *) output [95:0]m_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]"" *) output [11:0]m_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]"" *) output [2:0]m_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]"" *) input [2:0]m_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]"" *) input [5:0]m_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]"" *) input [2:0]m_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]"" *) output [2:0]m_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]"" *) output [95:0]m_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]"" *) output [8:0]m_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]"" *) output [2:0]m_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]"" *) input [2:0]m_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]"" *) input [95:0]m_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]"" *) input [5:0]m_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]"" *) input [2:0]m_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]"" *) output [2:0]m_axi_rready;
+
+  wire aclk;
+  wire aresetn;
+  wire [95:0]m_axi_araddr;
+  wire [8:0]m_axi_arprot;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_arvalid;
+  wire [95:0]m_axi_awaddr;
+  wire [8:0]m_axi_awprot;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [95:0]m_axi_wdata;
+  wire [2:0]m_axi_wready;
+  wire [11:0]m_axi_wstrb;
+  wire [2:0]m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+  wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED;
+  wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+  wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+  wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED;
+  wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+  wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+  (* C_AXI_ADDR_WIDTH = ""32"" *) 
+  (* C_AXI_ARUSER_WIDTH = ""1"" *) 
+  (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+  (* C_AXI_BUSER_WIDTH = ""1"" *) 
+  (* C_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_AXI_ID_WIDTH = ""1"" *) 
+  (* C_AXI_PROTOCOL = ""2"" *) 
+  (* C_AXI_RUSER_WIDTH = ""1"" *) 
+  (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+  (* C_AXI_WUSER_WIDTH = ""1"" *) 
+  (* C_CONNECTIVITY_MODE = ""0"" *) 
+  (* C_DEBUG = ""1"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_M_AXI_ADDR_WIDTH = ""96\'b000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000"" *) 
+  (* C_M_AXI_BASE_ADDR = ""192\'b111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+  (* C_M_AXI_READ_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_READ_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_SECURE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* C_M_AXI_WRITE_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_WRITE_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_NUM_ADDR_RANGES = ""1"" *) 
+  (* C_NUM_MASTER_SLOTS = ""3"" *) 
+  (* C_NUM_SLAVE_SLOTS = ""1"" *) 
+  (* C_R_REGISTER = ""1"" *) 
+  (* C_S_AXI_ARB_PRIORITY = ""0"" *) 
+  (* C_S_AXI_BASE_ID = ""0"" *) 
+  (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+  (* C_S_AXI_SINGLE_THREAD = ""1"" *) 
+  (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) 
+  (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+  (* DowngradeIPIdentifiedWarnings = ""yes"" *) 
+  (* P_ADDR_DECODE = ""1"" *) 
+  (* P_AXI3 = ""1"" *) 
+  (* P_AXI4 = ""0"" *) 
+  (* P_AXILITE = ""2"" *) 
+  (* P_AXILITE_SIZE = ""3\'b010"" *) 
+  (* P_FAMILY = ""zynq"" *) 
+  (* P_INCR = ""2\'b01"" *) 
+  (* P_LEN = ""8"" *) 
+  (* P_LOCK = ""1"" *) 
+  (* P_M_AXI_ERR_MODE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_M_AXI_SUPPORTS_READ = ""3\'b111"" *) 
+  (* P_M_AXI_SUPPORTS_WRITE = ""3\'b111"" *) 
+  (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) 
+  (* P_RANGE_CHECK = ""1"" *) 
+  (* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+  (* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar inst
+       (.aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]),
+        .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]),
+        .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]),
+        .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]),
+        .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]),
+        .m_axi_arprot(m_axi_arprot),
+        .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
+        .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]),
+        .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]),
+        .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]),
+        .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]),
+        .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]),
+        .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]),
+        .m_axi_awprot(m_axi_awprot),
+        .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
+        .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]),
+        .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bid({1\'b0,1\'b0,1\'b0}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_buser({1\'b0,1\'b0,1\'b0}),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rid({1\'b0,1\'b0,1\'b0}),
+        .m_axi_rlast({1\'b1,1\'b1,1\'b1}),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_ruser({1\'b0,1\'b0,1\'b0}),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wdata(m_axi_wdata),
+        .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]),
+        .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wstrb(m_axi_wstrb),
+        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst({1\'b0,1\'b0}),
+        .s_axi_arcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arid(1\'b0),
+        .s_axi_arlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arlock(1\'b0),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_aruser(1\'b0),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst({1\'b0,1\'b0}),
+        .s_axi_awcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awid(1\'b0),
+        .s_axi_awlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awlock(1\'b0),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_awuser(1\'b0),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
+        .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wid(1\'b0),
+        .s_axi_wlast(1\'b1),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wuser(1\'b0),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:37:25 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_sim_netlist.v
+// Design      : design_1_xbar_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd
+   (aa_grant_any,
+    m_valid_i,
+    SR,
+    aa_grant_rnw,
+    D,
+    Q,
+    \\m_atarget_hot_reg[2] ,
+    m_ready_d0,
+    s_axi_wready,
+    m_axi_wvalid,
+    \\gen_axilite.s_axi_bvalid_i_reg ,
+    m_axi_awvalid,
+    s_axi_bvalid,
+    m_axi_bready,
+    \\gen_axilite.s_axi_bvalid_i_reg_0 ,
+    \\m_ready_d_reg[1] ,
+    s_ready_i_reg,
+    E,
+    m_axi_arvalid,
+    \\gen_axilite.s_axi_rvalid_i_reg ,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
+    s_axi_awready,
+    s_axi_arready,
+    \\gen_axilite.s_axi_bvalid_i_reg_1 ,
+    \\gen_axilite.s_axi_awready_i_reg ,
+    aclk,
+    aresetn_d,
+    m_ready_d,
+    \\gen_axilite.s_axi_awready_i_reg_0 ,
+    \\gen_axilite.s_axi_awready_i_reg_1 ,
+    \\m_atarget_hot_reg[3] ,
+    s_axi_wvalid,
+    \\gen_axilite.s_axi_bvalid_i_reg_2 ,
+    s_axi_bready,
+    aa_rready,
+    m_ready_d_0,
+    \\gen_axilite.s_axi_rvalid_i_reg_0 ,
+    s_axi_rready,
+    sr_rvalid,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    m_valid_i_reg,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    \\m_ready_d_reg[0] ,
+    s_axi_awvalid,
+    mi_wready,
+    mi_bvalid);
+  output aa_grant_any;
+  output m_valid_i;
+  output [0:0]SR;
+  output aa_grant_rnw;
+  output [3:0]D;
+  output [34:0]Q;
+  output \\m_atarget_hot_reg[2] ;
+  output [2:0]m_ready_d0;
+  output [0:0]s_axi_wready;
+  output [2:0]m_axi_wvalid;
+  output \\gen_axilite.s_axi_bvalid_i_reg ;
+  output [2:0]m_axi_awvalid;
+  output [0:0]s_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  output \\m_ready_d_reg[1] ;
+  output s_ready_i_reg;
+  output [0:0]E;
+  output [2:0]m_axi_arvalid;
+  output \\gen_axilite.s_axi_rvalid_i_reg ;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output \\gen_axilite.s_axi_bvalid_i_reg_1 ;
+  output \\gen_axilite.s_axi_awready_i_reg ;
+  input aclk;
+  input aresetn_d;
+  input [2:0]m_ready_d;
+  input \\gen_axilite.s_axi_awready_i_reg_0 ;
+  input \\gen_axilite.s_axi_awready_i_reg_1 ;
+  input [3:0]\\m_atarget_hot_reg[3] ;
+  input [0:0]s_axi_wvalid;
+  input \\gen_axilite.s_axi_bvalid_i_reg_2 ;
+  input [0:0]s_axi_bready;
+  input aa_rready;
+  input [1:0]m_ready_d_0;
+  input \\gen_axilite.s_axi_rvalid_i_reg_0 ;
+  input [0:0]s_axi_rready;
+  input sr_rvalid;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input m_valid_i_reg;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input \\m_ready_d_reg[0] ;
+  input [0:0]s_axi_awvalid;
+  input [0:0]mi_wready;
+  input [0:0]mi_bvalid;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [34:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg_0 ;
+  wire \\gen_axilite.s_axi_awready_i_reg_1 ;
+  wire \\gen_axilite.s_axi_bvalid_i_i_2_n_0 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_1 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_2 ;
+  wire \\gen_axilite.s_axi_rvalid_i_reg ;
+  wire \\gen_axilite.s_axi_rvalid_i_reg_0 ;
+  wire \\gen_no_arbiter.grant_rnw_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_3_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  wire \\gen_no_arbiter.m_valid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
+  wire \\m_atarget_hot[3]_i_3_n_0 ;
+  wire \\m_atarget_hot[3]_i_4_n_0 ;
+  wire \\m_atarget_hot_reg[2] ;
+  wire [3:0]\\m_atarget_hot_reg[3] ;
+  wire [2:0]m_axi_arvalid;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [2:0]m_axi_wvalid;
+  wire [2:0]m_ready_d;
+  wire [2:0]m_ready_d0;
+  wire [1:0]m_ready_d_0;
+  wire \\m_ready_d_reg[0] ;
+  wire \\m_ready_d_reg[1] ;
+  wire m_valid_i;
+  wire m_valid_i_reg;
+  wire [0:0]mi_bvalid;
+  wire [0:0]mi_wready;
+  wire p_0_in1_in;
+  wire [48:1]s_amesg;
+  wire \\s_arvalid_reg[0]_i_1_n_0 ;
+  wire \\s_arvalid_reg_reg_n_0_[0] ;
+  wire s_awvalid_reg;
+  wire \\s_awvalid_reg[0]_i_1_n_0 ;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [0:0]s_axi_bvalid;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire s_ready_i;
+  wire s_ready_i_reg;
+  wire sr_rvalid;
+
+  LUT5 #(
+    .INIT(32\'hFBFF0400)) 
+    \\gen_axilite.s_axi_awready_i_i_1 
+       (.I0(\\gen_axilite.s_axi_bvalid_i_i_2_n_0 ),
+        .I1(\\m_atarget_hot_reg[3] [3]),
+        .I2(mi_bvalid),
+        .I3(\\gen_axilite.s_axi_bvalid_i_reg ),
+        .I4(mi_wready),
+        .O(\\gen_axilite.s_axi_awready_i_reg ));
+  LUT6 #(
+    .INIT(64\'h0020FF00FF20FF00)) 
+    \\gen_axilite.s_axi_bvalid_i_i_1 
+       (.I0(\\gen_axilite.s_axi_bvalid_i_reg ),
+        .I1(\\gen_axilite.s_axi_bvalid_i_i_2_n_0 ),
+        .I2(mi_wready),
+        .I3(mi_bvalid),
+        .I4(\\m_atarget_hot_reg[3] [3]),
+        .I5(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg_1 ));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT3 #(
+    .INIT(8\'hFB)) 
+    \\gen_axilite.s_axi_bvalid_i_i_2 
+       (.I0(m_ready_d[2]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .O(\\gen_axilite.s_axi_bvalid_i_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT3 #(
+    .INIT(8\'h40)) 
+    \\gen_axilite.s_axi_rvalid_i_i_2 
+       (.I0(m_ready_d_0[1]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .O(\\gen_axilite.s_axi_rvalid_i_reg ));
+  LUT6 #(
+    .INIT(64\'hFFFFFF5300000050)) 
+    \\gen_no_arbiter.grant_rnw_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_arvalid),
+        .I3(aa_grant_any),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\gen_no_arbiter.grant_rnw_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.grant_rnw_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.grant_rnw_i_1_n_0 ),
+        .Q(aa_grant_rnw),
+        .R(SR));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[10]_i_1 
+       (.I0(s_axi_araddr[9]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[9]),
+        .O(s_amesg[10]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[11]_i_1 
+       (.I0(s_axi_araddr[10]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[10]),
+        .O(s_amesg[11]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[12]_i_1 
+       (.I0(s_axi_araddr[11]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[11]),
+        .O(s_amesg[12]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[13]_i_1 
+       (.I0(s_axi_araddr[12]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[12]),
+        .O(s_amesg[13]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[14]_i_1 
+       (.I0(s_axi_araddr[13]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[13]),
+        .O(s_amesg[14]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[15]_i_1 
+       (.I0(s_axi_araddr[14]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[14]),
+        .O(s_amesg[15]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[16]_i_1 
+       (.I0(s_axi_araddr[15]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[15]),
+        .O(s_amesg[16]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[17]_i_1 
+       (.I0(s_axi_araddr[16]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[16]),
+        .O(s_amesg[17]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[18]_i_1 
+       (.I0(s_axi_araddr[17]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[17]),
+        .O(s_amesg[18]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[19]_i_1 
+       (.I0(s_axi_araddr[18]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[18]),
+        .O(s_amesg[19]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[1]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[0]),
+        .O(s_amesg[1]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[20]_i_1 
+       (.I0(s_axi_araddr[19]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[19]),
+        .O(s_amesg[20]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[21]_i_1 
+       (.I0(s_axi_araddr[20]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[20]),
+        .O(s_amesg[21]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[22]_i_1 
+       (.I0(s_axi_araddr[21]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[21]),
+        .O(s_amesg[22]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[23]_i_1 
+       (.I0(s_axi_araddr[22]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[22]),
+        .O(s_amesg[23]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[24]_i_1 
+       (.I0(s_axi_araddr[23]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[23]),
+        .O(s_amesg[24]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[25]_i_1 
+       (.I0(s_axi_araddr[24]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[24]),
+        .O(s_amesg[25]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[26]_i_1 
+       (.I0(s_axi_araddr[25]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[25]),
+        .O(s_amesg[26]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[27]_i_1 
+       (.I0(s_axi_araddr[26]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[26]),
+        .O(s_amesg[27]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[28]_i_1 
+       (.I0(s_axi_araddr[27]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[27]),
+        .O(s_amesg[28]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[29]_i_1 
+       (.I0(s_axi_araddr[28]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[28]),
+        .O(s_amesg[29]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[2]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[1]),
+        .O(s_amesg[2]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[30]_i_1 
+       (.I0(s_axi_araddr[29]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[29]),
+        .O(s_amesg[30]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[31]_i_1 
+       (.I0(s_axi_araddr[30]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[30]),
+        .O(s_amesg[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_1 
+       (.I0(aresetn_d),
+        .O(SR));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_2 
+       (.I0(aa_grant_any),
+        .O(p_0_in1_in));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_3 
+       (.I0(s_axi_araddr[31]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[31]),
+        .O(s_amesg[32]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[3]_i_1 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[2]),
+        .O(s_amesg[3]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[46]_i_1 
+       (.I0(s_axi_arprot[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[0]),
+        .O(s_amesg[46]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[47]_i_1 
+       (.I0(s_axi_arprot[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[1]),
+        .O(s_amesg[47]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[48]_i_1 
+       (.I0(s_axi_arprot[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[2]),
+        .O(s_amesg[48]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[4]_i_1 
+       (.I0(s_axi_araddr[3]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[3]),
+        .O(s_amesg[4]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[5]_i_1 
+       (.I0(s_axi_araddr[4]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[4]),
+        .O(s_amesg[5]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[6]_i_1 
+       (.I0(s_axi_araddr[5]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[5]),
+        .O(s_amesg[6]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[7]_i_1 
+       (.I0(s_axi_araddr[6]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[6]),
+        .O(s_amesg[7]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[8]_i_1 
+       (.I0(s_axi_araddr[7]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[7]),
+        .O(s_amesg[8]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[9]_i_1 
+       (.I0(s_axi_araddr[8]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[8]),
+        .O(s_amesg[9]));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[10] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[10]),
+        .Q(Q[9]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[11] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[11]),
+        .Q(Q[10]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[12] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[12]),
+        .Q(Q[11]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[13] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[13]),
+        .Q(Q[12]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[14] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[14]),
+        .Q(Q[13]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[15] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[15]),
+        .Q(Q[14]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[16] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[16]),
+        .Q(Q[15]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[17] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[17]),
+        .Q(Q[16]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[18] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[18]),
+        .Q(Q[17]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[19] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[19]),
+        .Q(Q[18]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[1] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[1]),
+        .Q(Q[0]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[20] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[20]),
+        .Q(Q[19]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[21] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[21]),
+        .Q(Q[20]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[22] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[22]),
+        .Q(Q[21]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[23] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[23]),
+        .Q(Q[22]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[24] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[24]),
+        .Q(Q[23]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[25] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[25]),
+        .Q(Q[24]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[26] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[26]),
+        .Q(Q[25]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[27] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[27]),
+        .Q(Q[26]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[28] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[28]),
+        .Q(Q[27]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[29] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[29]),
+        .Q(Q[28]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[2] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[2]),
+        .Q(Q[1]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[30] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[30]),
+        .Q(Q[29]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[31] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[31]),
+        .Q(Q[30]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[32] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[32]),
+        .Q(Q[31]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[3] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[3]),
+        .Q(Q[2]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[46] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[46]),
+        .Q(Q[32]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[47] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[47]),
+        .Q(Q[33]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[48] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[48]),
+        .Q(Q[34]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[4] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[4]),
+        .Q(Q[3]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[5] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[5]),
+        .Q(Q[4]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[6] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[6]),
+        .Q(Q[5]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[7] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[7]),
+        .Q(Q[6]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[8] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[8]),
+        .Q(Q[7]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[9] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[9]),
+        .Q(Q[8]),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h8088000080888088)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_1 
+       (.I0(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
+        .I1(aresetn_d),
+        .I2(\\gen_no_arbiter.m_grant_hot_i[0]_i_3_n_0 ),
+        .I3(\\m_ready_d_reg[0] ),
+        .I4(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
+        .I5(\\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT4 #(
+    .INIT(16\'hF0FE)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_2 
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_arvalid),
+        .I2(aa_grant_any),
+        .I3(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'hBFBFAFBF)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_3 
+       (.I0(aa_grant_rnw),
+        .I1(m_ready_d[1]),
+        .I2(m_valid_i),
+        .I3(s_axi_wvalid),
+        .I4(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_3_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT2 #(
+    .INIT(4\'h7)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_4 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT5 #(
+    .INIT(32\'h0000FF80)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_5 
+       (.I0(\\gen_axilite.s_axi_arready_i_reg ),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(m_ready_d_0[1]),
+        .I4(m_valid_i_reg),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ));
+  FDRE \\gen_no_arbiter.m_grant_hot_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
+        .Q(aa_grant_any),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h3AFA3AFA0A0A3AFA)) 
+    \\gen_no_arbiter.m_valid_i_i_1 
+       (.I0(aa_grant_any),
+        .I1(\\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(\\m_ready_d_reg[0] ),
+        .I5(\\gen_no_arbiter.m_grant_hot_i[0]_i_3_n_0 ),
+        .O(\\gen_no_arbiter.m_valid_i_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.m_valid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_valid_i_i_1_n_0 ),
+        .Q(m_valid_i),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT3 #(
+    .INIT(8\'h40)) 
+    \\gen_no_arbiter.s_ready_i[0]_i_1 
+       (.I0(m_valid_i),
+        .I1(aa_grant_any),
+        .I2(aresetn_d),
+        .O(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.s_ready_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
+        .Q(s_ready_i),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00000080)) 
+    \\m_atarget_hot[0]_i_1 
+       (.I0(aa_grant_any),
+        .I1(\\m_atarget_hot_reg[2] ),
+        .I2(Q[21]),
+        .I3(Q[23]),
+        .I4(Q[16]),
+        .O(D[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'h08000000)) 
+    \\m_atarget_hot[1]_i_1 
+       (.I0(\\m_atarget_hot_reg[2] ),
+        .I1(Q[21]),
+        .I2(Q[23]),
+        .I3(Q[16]),
+        .I4(aa_grant_any),
+        .O(D[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h04000000)) 
+    \\m_atarget_hot[2]_i_1 
+       (.I0(Q[16]),
+        .I1(Q[23]),
+        .I2(Q[21]),
+        .I3(\\m_atarget_hot_reg[2] ),
+        .I4(aa_grant_any),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'hF7D70000)) 
+    \\m_atarget_hot[3]_i_1 
+       (.I0(\\m_atarget_hot_reg[2] ),
+        .I1(Q[21]),
+        .I2(Q[23]),
+        .I3(Q[16]),
+        .I4(aa_grant_any),
+        .O(D[3]));
+  LUT5 #(
+    .INIT(32\'h02000000)) 
+    \\m_atarget_hot[3]_i_2 
+       (.I0(\\m_atarget_hot[3]_i_3_n_0 ),
+        .I1(\\m_atarget_hot[3]_i_4_n_0 ),
+        .I2(Q[22]),
+        .I3(Q[24]),
+        .I4(Q[30]),
+        .O(\\m_atarget_hot_reg[2] ));
+  LUT6 #(
+    .INIT(64\'h0000000000000001)) 
+    \\m_atarget_hot[3]_i_3 
+       (.I0(Q[31]),
+        .I1(Q[17]),
+        .I2(Q[18]),
+        .I3(Q[29]),
+        .I4(Q[28]),
+        .I5(Q[27]),
+        .O(\\m_atarget_hot[3]_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\m_atarget_hot[3]_i_4 
+       (.I0(Q[20]),
+        .I1(Q[26]),
+        .I2(Q[25]),
+        .I3(Q[19]),
+        .O(\\m_atarget_hot[3]_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[2]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [2]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[2]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [2]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[2]));
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [0]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[0]));
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [1]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[2]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [2]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_wvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [0]),
+        .I1(m_ready_d[1]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_wvalid),
+        .O(m_axi_wvalid[0]));
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_wvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [1]),
+        .I1(m_ready_d[1]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_wvalid),
+        .O(m_axi_wvalid[1]));
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_wvalid[2]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [2]),
+        .I1(m_ready_d[1]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_wvalid),
+        .O(m_axi_wvalid[2]));
+  LUT5 #(
+    .INIT(32\'h0080FFFF)) 
+    \\m_payload_i[34]_i_1 
+       (.I0(s_axi_rready),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[0]),
+        .I4(sr_rvalid),
+        .O(E));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'hFFFF0400)) 
+    \\m_ready_d[0]_i_2 
+       (.I0(\\gen_axilite.s_axi_bvalid_i_reg_2 ),
+        .I1(s_axi_bready),
+        .I2(aa_grant_rnw),
+        .I3(m_valid_i),
+        .I4(m_ready_d[0]),
+        .O(m_ready_d0[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_ready_d[1]_i_3 
+       (.I0(s_axi_wvalid),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[1]),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_ready_d[1]_i_4 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .O(\\m_ready_d_reg[1] ));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT4 #(
+    .INIT(16\'hBAAA)) 
+    \\m_ready_d[2]_i_2 
+       (.I0(m_ready_d[2]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(\\gen_axilite.s_axi_awready_i_reg_0 ),
+        .O(m_ready_d0[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_ready_d[2]_i_3 
+       (.I0(s_axi_bready),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[0]),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'hFFFF0400)) 
+    \\m_ready_d[2]_i_4 
+       (.I0(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .I1(s_axi_wvalid),
+        .I2(aa_grant_rnw),
+        .I3(m_valid_i),
+        .I4(m_ready_d[1]),
+        .O(m_ready_d0[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h8AAAAAAA)) 
+    m_valid_i_i_2
+       (.I0(aa_rready),
+        .I1(m_ready_d_0[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(\\gen_axilite.s_axi_rvalid_i_reg_0 ),
+        .O(s_ready_i_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'h0040)) 
+    \\s_arvalid_reg[0]_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_arvalid),
+        .I2(aresetn_d),
+        .I3(s_ready_i),
+        .O(\\s_arvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_arvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_arvalid_reg[0]_i_1_n_0 ),
+        .Q(\\s_arvalid_reg_reg_n_0_[0] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h0000000000D00000)) 
+    \\s_awvalid_reg[0]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_awvalid_reg),
+        .I2(s_axi_awvalid),
+        .I3(\\s_arvalid_reg_reg_n_0_[0] ),
+        .I4(aresetn_d),
+        .I5(s_ready_i),
+        .O(\\s_awvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_awvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_awvalid_reg[0]_i_1_n_0 ),
+        .Q(s_awvalid_reg),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_arready[0]_INST_0 
+       (.I0(aa_grant_rnw),
+        .I1(s_ready_i),
+        .O(s_axi_arready));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_awready[0]_INST_0 
+       (.I0(s_ready_i),
+        .I1(aa_grant_rnw),
+        .O(s_axi_awready));
+  LUT5 #(
+    .INIT(32\'h00000400)) 
+    \\s_axi_bvalid[0]_INST_0 
+       (.I0(m_ready_d[0]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(aa_grant_any),
+        .I4(\\gen_axilite.s_axi_bvalid_i_reg_2 ),
+        .O(s_axi_bvalid));
+  LUT5 #(
+    .INIT(32\'h00000400)) 
+    \\s_axi_wready[0]_INST_0 
+       (.I0(m_ready_d[1]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(aa_grant_any),
+        .I4(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .O(s_axi_wready));
+endmodule
+
+(* C_AXI_ADDR_WIDTH = ""32"" *) (* C_AXI_ARUSER_WIDTH = ""1"" *) (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+(* C_AXI_BUSER_WIDTH = ""1"" *) (* C_AXI_DATA_WIDTH = ""32"" *) (* C_AXI_ID_WIDTH = ""1"" *) 
+(* C_AXI_PROTOCOL = ""2"" *) (* C_AXI_RUSER_WIDTH = ""1"" *) (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+(* C_AXI_WUSER_WIDTH = ""1"" *) (* C_CONNECTIVITY_MODE = ""0"" *) (* C_DEBUG = ""1"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_M_AXI_ADDR_WIDTH = ""96\'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"" *) (* C_M_AXI_BASE_ADDR = ""192\'b000000000000000000000000000000000100000110000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+(* C_M_AXI_READ_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_READ_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_SECURE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+(* C_M_AXI_WRITE_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_WRITE_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_NUM_ADDR_RANGES = ""1"" *) 
+(* C_NUM_MASTER_SLOTS = ""3"" *) (* C_NUM_SLAVE_SLOTS = ""1"" *) (* C_R_REGISTER = ""1"" *) 
+(* C_S_AXI_ARB_PRIORITY = ""0"" *) (* C_S_AXI_BASE_ID = ""0"" *) (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+(* C_S_AXI_SINGLE_THREAD = ""1"" *) (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+(* DowngradeIPIdentifiedWarnings = ""yes"" *) (* P_ADDR_DECODE = ""1"" *) (* P_AXI3 = ""1"" *) 
+(* P_AXI4 = ""0"" *) (* P_AXILITE = ""2"" *) (* P_AXILITE_SIZE = ""3\'b010"" *) 
+(* P_FAMILY = ""zynq"" *) (* P_INCR = ""2\'b01"" *) (* P_LEN = ""8"" *) 
+(* P_LOCK = ""1"" *) (* P_M_AXI_ERR_MODE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) (* P_M_AXI_SUPPORTS_READ = ""3\'b111"" *) 
+(* P_M_AXI_SUPPORTS_WRITE = ""3\'b111"" *) (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) (* P_RANGE_CHECK = ""1"" *) 
+(* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+(* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awqos,
+    s_axi_awuser,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wuser,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_buser,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arqos,
+    s_axi_aruser,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_ruser,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awid,
+    m_axi_awaddr,
+    m_axi_awlen,
+    m_axi_awsize,
+    m_axi_awburst,
+    m_axi_awlock,
+    m_axi_awcache,
+    m_axi_awprot,
+    m_axi_awregion,
+    m_axi_awqos,
+    m_axi_awuser,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wid,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wlast,
+    m_axi_wuser,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bid,
+    m_axi_bresp,
+    m_axi_buser,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_arid,
+    m_axi_araddr,
+    m_axi_arlen,
+    m_axi_arsize,
+    m_axi_arburst,
+    m_axi_arlock,
+    m_axi_arcache,
+    m_axi_arprot,
+    m_axi_arregion,
+    m_axi_arqos,
+    m_axi_aruser,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rlast,
+    m_axi_ruser,
+    m_axi_rvalid,
+    m_axi_rready);
+  input aclk;
+  input aresetn;
+  input [0:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [7:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [0:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awqos;
+  input [0:0]s_axi_awuser;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [0:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wlast;
+  input [0:0]s_axi_wuser;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [0:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_buser;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [0:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [7:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [0:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arqos;
+  input [0:0]s_axi_aruser;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rlast;
+  output [0:0]s_axi_ruser;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [2:0]m_axi_awid;
+  output [95:0]m_axi_awaddr;
+  output [23:0]m_axi_awlen;
+  output [8:0]m_axi_awsize;
+  output [5:0]m_axi_awburst;
+  output [2:0]m_axi_awlock;
+  output [11:0]m_axi_awcache;
+  output [8:0]m_axi_awprot;
+  output [11:0]m_axi_awregion;
+  output [11:0]m_axi_awqos;
+  output [2:0]m_axi_awuser;
+  output [2:0]m_axi_awvalid;
+  input [2:0]m_axi_awready;
+  output [2:0]m_axi_wid;
+  output [95:0]m_axi_wdata;
+  output [11:0]m_axi_wstrb;
+  output [2:0]m_axi_wlast;
+  output [2:0]m_axi_wuser;
+  output [2:0]m_axi_wvalid;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bid;
+  input [5:0]m_axi_bresp;
+  input [2:0]m_axi_buser;
+  input [2:0]m_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [2:0]m_axi_arid;
+  output [95:0]m_axi_araddr;
+  output [23:0]m_axi_arlen;
+  output [8:0]m_axi_arsize;
+  output [5:0]m_axi_arburst;
+  output [2:0]m_axi_arlock;
+  output [11:0]m_axi_arcache;
+  output [8:0]m_axi_arprot;
+  output [11:0]m_axi_arregion;
+  output [11:0]m_axi_arqos;
+  output [2:0]m_axi_aruser;
+  output [2:0]m_axi_arvalid;
+  input [2:0]m_axi_arready;
+  input [2:0]m_axi_rid;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rlast;
+  input [2:0]m_axi_ruser;
+  input [2:0]m_axi_rvalid;
+  output [2:0]m_axi_rready;
+
+  wire \\<const0> ;
+  wire aclk;
+  wire aresetn;
+  wire [15:0]\\^m_axi_araddr ;
+  wire [2:0]\\^m_axi_arprot ;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_arvalid;
+  wire [95:80]\\^m_axi_awaddr ;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [2:0]m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+
+  assign m_axi_araddr[95:80] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[79:64] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[63:48] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[31:16] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_arburst[5] = \\<const0> ;
+  assign m_axi_arburst[4] = \\<const0> ;
+  assign m_axi_arburst[3] = \\<const0> ;
+  assign m_axi_arburst[2] = \\<const0> ;
+  assign m_axi_arburst[1] = \\<const0> ;
+  assign m_axi_arburst[0] = \\<const0> ;
+  assign m_axi_arcache[11] = \\<const0> ;
+  assign m_axi_arcache[10] = \\<const0> ;
+  assign m_axi_arcache[9] = \\<const0> ;
+  assign m_axi_arcache[8] = \\<const0> ;
+  assign m_axi_arcache[7] = \\<const0> ;
+  assign m_axi_arcache[6] = \\<const0> ;
+  assign m_axi_arcache[5] = \\<const0> ;
+  assign m_axi_arcache[4] = \\<const0> ;
+  assign m_axi_arcache[3] = \\<const0> ;
+  assign m_axi_arcache[2] = \\<const0> ;
+  assign m_axi_arcache[1] = \\<const0> ;
+  assign m_axi_arcache[0] = \\<const0> ;
+  assign m_axi_arid[2] = \\<const0> ;
+  assign m_axi_arid[1] = \\<const0> ;
+  assign m_axi_arid[0] = \\<const0> ;
+  assign m_axi_arlen[23] = \\<const0> ;
+  assign m_axi_arlen[22] = \\<const0> ;
+  assign m_axi_arlen[21] = \\<const0> ;
+  assign m_axi_arlen[20] = \\<const0> ;
+  assign m_axi_arlen[19] = \\<const0> ;
+  assign m_axi_arlen[18] = \\<const0> ;
+  assign m_axi_arlen[17] = \\<const0> ;
+  assign m_axi_arlen[16] = \\<const0> ;
+  assign m_axi_arlen[15] = \\<const0> ;
+  assign m_axi_arlen[14] = \\<const0> ;
+  assign m_axi_arlen[13] = \\<const0> ;
+  assign m_axi_arlen[12] = \\<const0> ;
+  assign m_axi_arlen[11] = \\<const0> ;
+  assign m_axi_arlen[10] = \\<const0> ;
+  assign m_axi_arlen[9] = \\<const0> ;
+  assign m_axi_arlen[8] = \\<const0> ;
+  assign m_axi_arlen[7] = \\<const0> ;
+  assign m_axi_arlen[6] = \\<const0> ;
+  assign m_axi_arlen[5] = \\<const0> ;
+  assign m_axi_arlen[4] = \\<const0> ;
+  assign m_axi_arlen[3] = \\<const0> ;
+  assign m_axi_arlen[2] = \\<const0> ;
+  assign m_axi_arlen[1] = \\<const0> ;
+  assign m_axi_arlen[0] = \\<const0> ;
+  assign m_axi_arlock[2] = \\<const0> ;
+  assign m_axi_arlock[1] = \\<const0> ;
+  assign m_axi_arlock[0] = \\<const0> ;
+  assign m_axi_arprot[8:6] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_arqos[11] = \\<const0> ;
+  assign m_axi_arqos[10] = \\<const0> ;
+  assign m_axi_arqos[9] = \\<const0> ;
+  assign m_axi_arqos[8] = \\<const0> ;
+  assign m_axi_arqos[7] = \\<const0> ;
+  assign m_axi_arqos[6] = \\<const0> ;
+  assign m_axi_arqos[5] = \\<const0> ;
+  assign m_axi_arqos[4] = \\<const0> ;
+  assign m_axi_arqos[3] = \\<const0> ;
+  assign m_axi_arqos[2] = \\<const0> ;
+  assign m_axi_arqos[1] = \\<const0> ;
+  assign m_axi_arqos[0] = \\<const0> ;
+  assign m_axi_arregion[11] = \\<const0> ;
+  assign m_axi_arregion[10] = \\<const0> ;
+  assign m_axi_arregion[9] = \\<const0> ;
+  assign m_axi_arregion[8] = \\<const0> ;
+  assign m_axi_arregion[7] = \\<const0> ;
+  assign m_axi_arregion[6] = \\<const0> ;
+  assign m_axi_arregion[5] = \\<const0> ;
+  assign m_axi_arregion[4] = \\<const0> ;
+  assign m_axi_arregion[3] = \\<const0> ;
+  assign m_axi_arregion[2] = \\<const0> ;
+  assign m_axi_arregion[1] = \\<const0> ;
+  assign m_axi_arregion[0] = \\<const0> ;
+  assign m_axi_arsize[8] = \\<const0> ;
+  assign m_axi_arsize[7] = \\<const0> ;
+  assign m_axi_arsize[6] = \\<const0> ;
+  assign m_axi_arsize[5] = \\<const0> ;
+  assign m_axi_arsize[4] = \\<const0> ;
+  assign m_axi_arsize[3] = \\<const0> ;
+  assign m_axi_arsize[2] = \\<const0> ;
+  assign m_axi_arsize[1] = \\<const0> ;
+  assign m_axi_arsize[0] = \\<const0> ;
+  assign m_axi_aruser[2] = \\<const0> ;
+  assign m_axi_aruser[1] = \\<const0> ;
+  assign m_axi_aruser[0] = \\<const0> ;
+  assign m_axi_awaddr[95:80] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[79:64] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[63:48] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[31:16] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_awburst[5] = \\<const0> ;
+  assign m_axi_awburst[4] = \\<const0> ;
+  assign m_axi_awburst[3] = \\<const0> ;
+  assign m_axi_awburst[2] = \\<const0> ;
+  assign m_axi_awburst[1] = \\<const0> ;
+  assign m_axi_awburst[0] = \\<const0> ;
+  assign m_axi_awcache[11] = \\<const0> ;
+  assign m_axi_awcache[10] = \\<const0> ;
+  assign m_axi_awcache[9] = \\<const0> ;
+  assign m_axi_awcache[8] = \\<const0> ;
+  assign m_axi_awcache[7] = \\<const0> ;
+  assign m_axi_awcache[6] = \\<const0> ;
+  assign m_axi_awcache[5] = \\<const0> ;
+  assign m_axi_awcache[4] = \\<const0> ;
+  assign m_axi_awcache[3] = \\<const0> ;
+  assign m_axi_awcache[2] = \\<const0> ;
+  assign m_axi_awcache[1] = \\<const0> ;
+  assign m_axi_awcache[0] = \\<const0> ;
+  assign m_axi_awid[2] = \\<const0> ;
+  assign m_axi_awid[1] = \\<const0> ;
+  assign m_axi_awid[0] = \\<const0> ;
+  assign m_axi_awlen[23] = \\<const0> ;
+  assign m_axi_awlen[22] = \\<const0> ;
+  assign m_axi_awlen[21] = \\<const0> ;
+  assign m_axi_awlen[20] = \\<const0> ;
+  assign m_axi_awlen[19] = \\<const0> ;
+  assign m_axi_awlen[18] = \\<const0> ;
+  assign m_axi_awlen[17] = \\<const0> ;
+  assign m_axi_awlen[16] = \\<const0> ;
+  assign m_axi_awlen[15] = \\<const0> ;
+  assign m_axi_awlen[14] = \\<const0> ;
+  assign m_axi_awlen[13] = \\<const0> ;
+  assign m_axi_awlen[12] = \\<const0> ;
+  assign m_axi_awlen[11] = \\<const0> ;
+  assign m_axi_awlen[10] = \\<const0> ;
+  assign m_axi_awlen[9] = \\<const0> ;
+  assign m_axi_awlen[8] = \\<const0> ;
+  assign m_axi_awlen[7] = \\<const0> ;
+  assign m_axi_awlen[6] = \\<const0> ;
+  assign m_axi_awlen[5] = \\<const0> ;
+  assign m_axi_awlen[4] = \\<const0> ;
+  assign m_axi_awlen[3] = \\<const0> ;
+  assign m_axi_awlen[2] = \\<const0> ;
+  assign m_axi_awlen[1] = \\<const0> ;
+  assign m_axi_awlen[0] = \\<const0> ;
+  assign m_axi_awlock[2] = \\<const0> ;
+  assign m_axi_awlock[1] = \\<const0> ;
+  assign m_axi_awlock[0] = \\<const0> ;
+  assign m_axi_awprot[8:6] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_awqos[11] = \\<const0> ;
+  assign m_axi_awqos[10] = \\<const0> ;
+  assign m_axi_awqos[9] = \\<const0> ;
+  assign m_axi_awqos[8] = \\<const0> ;
+  assign m_axi_awqos[7] = \\<const0> ;
+  assign m_axi_awqos[6] = \\<const0> ;
+  assign m_axi_awqos[5] = \\<const0> ;
+  assign m_axi_awqos[4] = \\<const0> ;
+  assign m_axi_awqos[3] = \\<const0> ;
+  assign m_axi_awqos[2] = \\<const0> ;
+  assign m_axi_awqos[1] = \\<const0> ;
+  assign m_axi_awqos[0] = \\<const0> ;
+  assign m_axi_awregion[11] = \\<const0> ;
+  assign m_axi_awregion[10] = \\<const0> ;
+  assign m_axi_awregion[9] = \\<const0> ;
+  assign m_axi_awregion[8] = \\<const0> ;
+  assign m_axi_awregion[7] = \\<const0> ;
+  assign m_axi_awregion[6] = \\<const0> ;
+  assign m_axi_awregion[5] = \\<const0> ;
+  assign m_axi_awregion[4] = \\<const0> ;
+  assign m_axi_awregion[3] = \\<const0> ;
+  assign m_axi_awregion[2] = \\<const0> ;
+  assign m_axi_awregion[1] = \\<const0> ;
+  assign m_axi_awregion[0] = \\<const0> ;
+  assign m_axi_awsize[8] = \\<const0> ;
+  assign m_axi_awsize[7] = \\<const0> ;
+  assign m_axi_awsize[6] = \\<const0> ;
+  assign m_axi_awsize[5] = \\<const0> ;
+  assign m_axi_awsize[4] = \\<const0> ;
+  assign m_axi_awsize[3] = \\<const0> ;
+  assign m_axi_awsize[2] = \\<const0> ;
+  assign m_axi_awsize[1] = \\<const0> ;
+  assign m_axi_awsize[0] = \\<const0> ;
+  assign m_axi_awuser[2] = \\<const0> ;
+  assign m_axi_awuser[1] = \\<const0> ;
+  assign m_axi_awuser[0] = \\<const0> ;
+  assign m_axi_wdata[95:64] = s_axi_wdata;
+  assign m_axi_wdata[63:32] = s_axi_wdata;
+  assign m_axi_wdata[31:0] = s_axi_wdata;
+  assign m_axi_wid[2] = \\<const0> ;
+  assign m_axi_wid[1] = \\<const0> ;
+  assign m_axi_wid[0] = \\<const0> ;
+  assign m_axi_wlast[2] = \\<const0> ;
+  assign m_axi_wlast[1] = \\<const0> ;
+  assign m_axi_wlast[0] = \\<const0> ;
+  assign m_axi_wstrb[11:8] = s_axi_wstrb;
+  assign m_axi_wstrb[7:4] = s_axi_wstrb;
+  assign m_axi_wstrb[3:0] = s_axi_wstrb;
+  assign m_axi_wuser[2] = \\<const0> ;
+  assign m_axi_wuser[1] = \\<const0> ;
+  assign m_axi_wuser[0] = \\<const0> ;
+  assign s_axi_bid[0] = \\<const0> ;
+  assign s_axi_buser[0] = \\<const0> ;
+  assign s_axi_rid[0] = \\<const0> ;
+  assign s_axi_rlast[0] = \\<const0> ;
+  assign s_axi_ruser[0] = \\<const0> ;
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd \\gen_sasd.crossbar_sasd_0 
+       (.Q({\\^m_axi_arprot ,\\^m_axi_awaddr ,\\^m_axi_araddr }),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd
+   (Q,
+    \\s_axi_rdata[31] ,
+    s_axi_wready,
+    m_axi_wvalid,
+    m_axi_awvalid,
+    s_axi_bvalid,
+    m_axi_bready,
+    m_axi_arvalid,
+    s_axi_bresp,
+    s_axi_awready,
+    s_axi_arready,
+    s_axi_rvalid,
+    m_axi_rready,
+    s_axi_rready,
+    aresetn,
+    aclk,
+    s_axi_bready,
+    s_axi_wvalid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rvalid,
+    m_axi_bvalid,
+    m_axi_awready,
+    m_axi_wready,
+    m_axi_arready,
+    m_axi_bresp,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_awvalid);
+  output [34:0]Q;
+  output [33:0]\\s_axi_rdata[31] ;
+  output [0:0]s_axi_wready;
+  output [2:0]m_axi_wvalid;
+  output [2:0]m_axi_awvalid;
+  output [0:0]s_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [2:0]m_axi_arvalid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rvalid;
+  output [2:0]m_axi_rready;
+  input [0:0]s_axi_rready;
+  input aresetn;
+  input aclk;
+  input [0:0]s_axi_bready;
+  input [0:0]s_axi_wvalid;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rvalid;
+  input [2:0]m_axi_bvalid;
+  input [2:0]m_axi_awready;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_arready;
+  input [5:0]m_axi_bresp;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input [0:0]s_axi_awvalid;
+
+  wire [34:0]Q;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire addr_arbiter_inst_n_4;
+  wire addr_arbiter_inst_n_43;
+  wire addr_arbiter_inst_n_5;
+  wire addr_arbiter_inst_n_51;
+  wire addr_arbiter_inst_n_59;
+  wire addr_arbiter_inst_n_6;
+  wire addr_arbiter_inst_n_60;
+  wire addr_arbiter_inst_n_61;
+  wire addr_arbiter_inst_n_66;
+  wire addr_arbiter_inst_n_67;
+  wire addr_arbiter_inst_n_70;
+  wire addr_arbiter_inst_n_71;
+  wire aresetn;
+  wire aresetn_d;
+  wire \\gen_decerr.decerr_slave_inst_n_2 ;
+  wire \\gen_decerr.decerr_slave_inst_n_3 ;
+  wire \\gen_decerr.decerr_slave_inst_n_4 ;
+  wire \\gen_decerr.decerr_slave_inst_n_5 ;
+  wire \\gen_decerr.decerr_slave_inst_n_6 ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc[0]_i_1_n_0 ;
+  wire \\m_atarget_enc[1]_i_1_n_0 ;
+  wire [3:0]m_atarget_hot;
+  wire [0:0]m_atarget_hot0;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_arvalid;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [2:0]m_axi_wvalid;
+  wire [1:0]m_ready_d;
+  wire [2:0]m_ready_d0;
+  wire [2:0]m_ready_d_0;
+  wire m_valid_i;
+  wire [3:3]mi_bvalid;
+  wire [3:3]mi_wready;
+  wire p_1_in;
+  wire reg_slice_r_n_2;
+  wire reset;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire splitter_aw_n_0;
+  wire sr_rvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd addr_arbiter_inst
+       (.D({addr_arbiter_inst_n_4,addr_arbiter_inst_n_5,addr_arbiter_inst_n_6,m_atarget_hot0}),
+        .E(p_1_in),
+        .Q(Q),
+        .SR(reset),
+        .aa_grant_any(aa_grant_any),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_arready_i_reg (\\gen_decerr.decerr_slave_inst_n_6 ),
+        .\\gen_axilite.s_axi_awready_i_reg (addr_arbiter_inst_n_71),
+        .\\gen_axilite.s_axi_awready_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\gen_axilite.s_axi_awready_i_reg_1 (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_51),
+        .\\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_59),
+        .\\gen_axilite.s_axi_bvalid_i_reg_1 (addr_arbiter_inst_n_70),
+        .\\gen_axilite.s_axi_bvalid_i_reg_2 (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\gen_axilite.s_axi_rvalid_i_reg (addr_arbiter_inst_n_66),
+        .\\gen_axilite.s_axi_rvalid_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_2 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (addr_arbiter_inst_n_67),
+        .\\m_atarget_hot_reg[2] (addr_arbiter_inst_n_43),
+        .\\m_atarget_hot_reg[3] (m_atarget_hot),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_wvalid(m_axi_wvalid),
+        .m_ready_d(m_ready_d_0),
+        .m_ready_d0(m_ready_d0),
+        .m_ready_d_0(m_ready_d),
+        .\\m_ready_d_reg[0] (splitter_aw_n_0),
+        .\\m_ready_d_reg[1] (addr_arbiter_inst_n_60),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg(reg_slice_r_n_2),
+        .mi_bvalid(mi_bvalid),
+        .mi_wready(mi_wready),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid),
+        .s_ready_i_reg(addr_arbiter_inst_n_61),
+        .sr_rvalid(sr_rvalid));
+  FDRE #(
+    .INIT(1\'b0)) 
+    aresetn_d_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(aresetn),
+        .Q(aresetn_d),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave \\gen_decerr.decerr_slave_inst 
+       (.Q(m_atarget_enc),
+        .SR(reset),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_awready_i_reg_0 (addr_arbiter_inst_n_70),
+        .\\m_atarget_hot_reg[3] (addr_arbiter_inst_n_71),
+        .\\m_atarget_hot_reg[3]_0 (m_atarget_hot[3]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .\\m_ready_d_reg[1] (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\m_ready_d_reg[1]_0 (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\m_ready_d_reg[1]_1 (\\gen_decerr.decerr_slave_inst_n_6 ),
+        .\\m_ready_d_reg[1]_2 (addr_arbiter_inst_n_66),
+        .\\m_ready_d_reg[2] (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .mi_bvalid(mi_bvalid),
+        .mi_wready(mi_wready),
+        .s_ready_i_reg(\\gen_decerr.decerr_slave_inst_n_2 ));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT4 #(
+    .INIT(16\'hFFD7)) 
+    \\m_atarget_enc[0]_i_1 
+       (.I0(addr_arbiter_inst_n_43),
+        .I1(Q[21]),
+        .I2(Q[23]),
+        .I3(Q[16]),
+        .O(\\m_atarget_enc[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hF7)) 
+    \\m_atarget_enc[1]_i_1 
+       (.I0(addr_arbiter_inst_n_43),
+        .I1(Q[21]),
+        .I2(Q[23]),
+        .O(\\m_atarget_enc[1]_i_1_n_0 ));
+  FDRE \\m_atarget_enc_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_enc[0]_i_1_n_0 ),
+        .Q(m_atarget_enc[0]),
+        .R(reset));
+  FDRE \\m_atarget_enc_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_enc[1]_i_1_n_0 ),
+        .Q(m_atarget_enc[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_atarget_hot0),
+        .Q(m_atarget_hot[0]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_6),
+        .Q(m_atarget_hot[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_5),
+        .Q(m_atarget_hot[2]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_4),
+        .Q(m_atarget_hot[3]),
+        .R(reset));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice reg_slice_r
+       (.E(p_1_in),
+        .Q(m_atarget_enc),
+        .SR(reset),
+        .aa_grant_any(aa_grant_any),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_67),
+        .\\m_atarget_hot_reg[2] (m_atarget_hot[2:0]),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_ready_d(m_ready_d[0]),
+        .\\m_ready_d_reg[1] (reg_slice_r_n_2),
+        .m_valid_i(m_valid_i),
+        .\\s_axi_rdata[31] (\\s_axi_rdata[31] ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_ready_i_reg_0(addr_arbiter_inst_n_61),
+        .sr_rvalid(sr_rvalid));
+  LUT5 #(
+    .INIT(32\'hFCEEFC22)) 
+    \\s_axi_bresp[0]_INST_0 
+       (.I0(m_axi_bresp[0]),
+        .I1(m_atarget_enc[1]),
+        .I2(m_axi_bresp[2]),
+        .I3(m_atarget_enc[0]),
+        .I4(m_axi_bresp[4]),
+        .O(s_axi_bresp[0]));
+  LUT5 #(
+    .INIT(32\'hFCEEFC22)) 
+    \\s_axi_bresp[1]_INST_0 
+       (.I0(m_axi_bresp[1]),
+        .I1(m_atarget_enc[1]),
+        .I2(m_axi_bresp[3]),
+        .I3(m_atarget_enc[0]),
+        .I4(m_axi_bresp[5]),
+        .O(s_axi_bresp[1]));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0 splitter_ar
+       (.aa_grant_rnw(aa_grant_rnw),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_arready_i_reg (\\gen_decerr.decerr_slave_inst_n_6 ),
+        .m_ready_d(m_ready_d),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg(reg_slice_r_n_2));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter splitter_aw
+       (.aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_awready_i_reg (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\gen_axilite.s_axi_awready_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\gen_axilite.s_axi_bvalid_i_reg (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_60),
+        .\\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_59),
+        .\\gen_no_arbiter.grant_rnw_reg_1 (addr_arbiter_inst_n_51),
+        .m_ready_d(m_ready_d_0),
+        .m_ready_d0(m_ready_d0),
+        .\\m_ready_d_reg[1]_0 (splitter_aw_n_0),
+        .s_axi_bready(s_axi_bready));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave
+   (mi_bvalid,
+    mi_wready,
+    s_ready_i_reg,
+    \\m_ready_d_reg[2] ,
+    \\m_ready_d_reg[1] ,
+    \\m_ready_d_reg[1]_0 ,
+    \\m_ready_d_reg[1]_1 ,
+    SR,
+    \\gen_axilite.s_axi_awready_i_reg_0 ,
+    aclk,
+    \\m_atarget_hot_reg[3] ,
+    m_axi_rvalid,
+    Q,
+    m_axi_bvalid,
+    m_axi_awready,
+    m_axi_wready,
+    m_axi_arready,
+    \\m_ready_d_reg[1]_2 ,
+    aa_rready,
+    \\m_atarget_hot_reg[3]_0 ,
+    aresetn_d);
+  output [0:0]mi_bvalid;
+  output [0:0]mi_wready;
+  output s_ready_i_reg;
+  output \\m_ready_d_reg[2] ;
+  output \\m_ready_d_reg[1] ;
+  output \\m_ready_d_reg[1]_0 ;
+  output \\m_ready_d_reg[1]_1 ;
+  input [0:0]SR;
+  input \\gen_axilite.s_axi_awready_i_reg_0 ;
+  input aclk;
+  input \\m_atarget_hot_reg[3] ;
+  input [2:0]m_axi_rvalid;
+  input [1:0]Q;
+  input [2:0]m_axi_bvalid;
+  input [2:0]m_axi_awready;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_arready;
+  input \\m_ready_d_reg[1]_2 ;
+  input aa_rready;
+  input [0:0]\\m_atarget_hot_reg[3]_0 ;
+  input aresetn_d;
+
+  wire [1:0]Q;
+  wire [0:0]SR;
+  wire aa_rready;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_awready_i_reg_0 ;
+  wire \\gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
+  wire \\m_atarget_hot_reg[3] ;
+  wire [0:0]\\m_atarget_hot_reg[3]_0 ;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_bvalid;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire \\m_ready_d_reg[1] ;
+  wire \\m_ready_d_reg[1]_0 ;
+  wire \\m_ready_d_reg[1]_1 ;
+  wire \\m_ready_d_reg[1]_2 ;
+  wire \\m_ready_d_reg[2] ;
+  wire [3:3]mi_arready;
+  wire [0:0]mi_bvalid;
+  wire [3:3]mi_rvalid;
+  wire [0:0]mi_wready;
+  wire s_ready_i_reg;
+
+  LUT5 #(
+    .INIT(32\'hAA2A00AA)) 
+    \\gen_axilite.s_axi_arready_i_i_1 
+       (.I0(aresetn_d),
+        .I1(\\m_ready_d_reg[1]_2 ),
+        .I2(\\m_atarget_hot_reg[3]_0 ),
+        .I3(mi_rvalid),
+        .I4(mi_arready),
+        .O(\\gen_axilite.s_axi_arready_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_arready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_arready_i_i_1_n_0 ),
+        .Q(mi_arready),
+        .R(1\'b0));
+  FDRE \\gen_axilite.s_axi_awready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_hot_reg[3] ),
+        .Q(mi_wready),
+        .R(SR));
+  FDRE \\gen_axilite.s_axi_bvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_awready_i_reg_0 ),
+        .Q(mi_bvalid),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h0F88FF00)) 
+    \\gen_axilite.s_axi_rvalid_i_i_1 
+       (.I0(mi_arready),
+        .I1(\\m_ready_d_reg[1]_2 ),
+        .I2(aa_rready),
+        .I3(mi_rvalid),
+        .I4(\\m_atarget_hot_reg[3]_0 ),
+        .O(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_rvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
+        .Q(mi_rvalid),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'hAACCF0FFAACCF000)) 
+    \\m_ready_d[1]_i_2__0 
+       (.I0(mi_arready),
+        .I1(m_axi_arready[2]),
+        .I2(m_axi_arready[1]),
+        .I3(Q[0]),
+        .I4(Q[1]),
+        .I5(m_axi_arready[0]),
+        .O(\\m_ready_d_reg[1]_1 ));
+  LUT6 #(
+    .INIT(64\'hAACCFFF0AACC00F0)) 
+    \\m_ready_d[2]_i_5 
+       (.I0(mi_wready),
+        .I1(m_axi_awready[2]),
+        .I2(m_axi_awready[0]),
+        .I3(Q[0]),
+        .I4(Q[1]),
+        .I5(m_axi_awready[1]),
+        .O(\\m_ready_d_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hCCFFF0AACC00F0AA)) 
+    m_valid_i_i_3
+       (.I0(m_axi_rvalid[0]),
+        .I1(mi_rvalid),
+        .I2(m_axi_rvalid[1]),
+        .I3(Q[0]),
+        .I4(Q[1]),
+        .I5(m_axi_rvalid[2]),
+        .O(s_ready_i_reg));
+  LUT6 #(
+    .INIT(64\'h0F0055330FFF5533)) 
+    \\s_axi_bvalid[0]_INST_0_i_1 
+       (.I0(m_axi_bvalid[1]),
+        .I1(m_axi_bvalid[0]),
+        .I2(mi_bvalid),
+        .I3(Q[0]),
+        .I4(Q[1]),
+        .I5(m_axi_bvalid[2]),
+        .O(\\m_ready_d_reg[2] ));
+  LUT6 #(
+    .INIT(64\'h3300550F33FF550F)) 
+    \\s_axi_wready[0]_INST_0_i_1 
+       (.I0(m_axi_wready[1]),
+        .I1(mi_wready),
+        .I2(m_axi_wready[0]),
+        .I3(Q[0]),
+        .I4(Q[1]),
+        .I5(m_axi_wready[2]),
+        .O(\\m_ready_d_reg[1]_0 ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter
+   (\\m_ready_d_reg[1]_0 ,
+    m_ready_d,
+    s_axi_bready,
+    \\gen_axilite.s_axi_bvalid_i_reg ,
+    \\gen_axilite.s_axi_awready_i_reg ,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    aresetn_d,
+    m_ready_d0,
+    \\gen_no_arbiter.grant_rnw_reg_0 ,
+    \\gen_no_arbiter.grant_rnw_reg_1 ,
+    \\gen_axilite.s_axi_awready_i_reg_0 ,
+    aclk);
+  output \\m_ready_d_reg[1]_0 ;
+  output [2:0]m_ready_d;
+  input [0:0]s_axi_bready;
+  input \\gen_axilite.s_axi_bvalid_i_reg ;
+  input \\gen_axilite.s_axi_awready_i_reg ;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input aresetn_d;
+  input [2:0]m_ready_d0;
+  input \\gen_no_arbiter.grant_rnw_reg_0 ;
+  input \\gen_no_arbiter.grant_rnw_reg_1 ;
+  input \\gen_axilite.s_axi_awready_i_reg_0 ;
+  input aclk;
+
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_awready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg_0 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg_0 ;
+  wire \\gen_no_arbiter.grant_rnw_reg_1 ;
+  wire [2:0]m_ready_d;
+  wire [2:0]m_ready_d0;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire \\m_ready_d[2]_i_1_n_0 ;
+  wire \\m_ready_d_reg[1]_0 ;
+  wire [0:0]s_axi_bready;
+
+  LUT6 #(
+    .INIT(64\'h20202020A0A020A0)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0[2]),
+        .I2(m_ready_d0[0]),
+        .I3(\\gen_no_arbiter.grant_rnw_reg_1 ),
+        .I4(\\gen_axilite.s_axi_awready_i_reg_0 ),
+        .I5(m_ready_d[1]),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h22220020)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(\\m_ready_d_reg[1]_0 ),
+        .I2(\\gen_no_arbiter.grant_rnw_reg_1 ),
+        .I3(\\gen_axilite.s_axi_awready_i_reg_0 ),
+        .I4(m_ready_d[1]),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAAAEAE0000AE00)) 
+    \\m_ready_d[1]_i_2 
+       (.I0(m_ready_d[0]),
+        .I1(s_axi_bready),
+        .I2(\\gen_axilite.s_axi_bvalid_i_reg ),
+        .I3(\\gen_axilite.s_axi_awready_i_reg ),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(m_ready_d[2]),
+        .O(\\m_ready_d_reg[1]_0 ));
+  LUT6 #(
+    .INIT(64\'h0800080888888888)) 
+    \\m_ready_d[2]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0[2]),
+        .I2(m_ready_d[0]),
+        .I3(\\gen_axilite.s_axi_bvalid_i_reg ),
+        .I4(\\gen_no_arbiter.grant_rnw_reg_0 ),
+        .I5(m_ready_d0[1]),
+        .O(\\m_ready_d[2]_i_1_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg['b'2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[2]_i_1_n_0 ),
+        .Q(m_ready_d[2]),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_crossbar_v2_1_12_splitter"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0
+   (m_ready_d,
+    aresetn_d,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    m_valid_i,
+    aa_grant_rnw,
+    m_valid_i_reg,
+    aclk);
+  output [1:0]m_ready_d;
+  input aresetn_d;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input m_valid_i;
+  input aa_grant_rnw;
+  input m_valid_i_reg;
+  input aclk;
+
+  wire aa_grant_rnw;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire [1:0]m_ready_d;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire m_valid_i;
+  wire m_valid_i_reg;
+
+  LUT6 #(
+    .INIT(64\'h0000000000002AAA)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(m_ready_d[1]),
+        .I5(m_valid_i_reg),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAA800000000000)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(m_ready_d[1]),
+        .I5(m_valid_i_reg),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice
+   (sr_rvalid,
+    aa_rready,
+    \\m_ready_d_reg[1] ,
+    s_axi_rvalid,
+    m_axi_rready,
+    \\s_axi_rdata[31] ,
+    aclk,
+    m_ready_d,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    s_axi_rready,
+    s_ready_i_reg_0,
+    aa_grant_rnw,
+    m_valid_i,
+    m_axi_rdata,
+    Q,
+    m_axi_rresp,
+    aa_grant_any,
+    \\m_atarget_hot_reg[2] ,
+    SR,
+    E);
+  output sr_rvalid;
+  output aa_rready;
+  output \\m_ready_d_reg[1] ;
+  output [0:0]s_axi_rvalid;
+  output [2:0]m_axi_rready;
+  output [33:0]\\s_axi_rdata[31] ;
+  input aclk;
+  input [0:0]m_ready_d;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input [0:0]s_axi_rready;
+  input s_ready_i_reg_0;
+  input aa_grant_rnw;
+  input m_valid_i;
+  input [95:0]m_axi_rdata;
+  input [1:0]Q;
+  input [5:0]m_axi_rresp;
+  input aa_grant_any;
+  input [2:0]\\m_atarget_hot_reg[2] ;
+  input [0:0]SR;
+  input [0:0]E;
+
+  wire [0:0]E;
+  wire [1:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire \\aresetn_d_reg_n_0_[0] ;
+  wire \\aresetn_d_reg_n_0_[1] ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire [2:0]\\m_atarget_hot_reg[2] ;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire \\m_payload_i[10]_i_2_n_0 ;
+  wire \\m_payload_i[11]_i_2_n_0 ;
+  wire \\m_payload_i[12]_i_2_n_0 ;
+  wire \\m_payload_i[13]_i_2_n_0 ;
+  wire \\m_payload_i[14]_i_2_n_0 ;
+  wire \\m_payload_i[15]_i_2_n_0 ;
+  wire \\m_payload_i[16]_i_2_n_0 ;
+  wire \\m_payload_i[17]_i_2_n_0 ;
+  wire \\m_payload_i[18]_i_2_n_0 ;
+  wire \\m_payload_i[19]_i_2_n_0 ;
+  wire \\m_payload_i[1]_i_2_n_0 ;
+  wire \\m_payload_i[20]_i_2_n_0 ;
+  wire \\m_payload_i[21]_i_2_n_0 ;
+  wire \\m_payload_i[22]_i_2_n_0 ;
+  wire \\m_payload_i[23]_i_2_n_0 ;
+  wire \\m_payload_i[24]_i_2_n_0 ;
+  wire \\m_payload_i[25]_i_2_n_0 ;
+  wire \\m_payload_i[26]_i_2_n_0 ;
+  wire \\m_payload_i[27]_i_2_n_0 ;
+  wire \\m_payload_i[28]_i_2_n_0 ;
+  wire \\m_payload_i[29]_i_2_n_0 ;
+  wire \\m_payload_i[2]_i_2_n_0 ;
+  wire \\m_payload_i[30]_i_2_n_0 ;
+  wire \\m_payload_i[31]_i_2_n_0 ;
+  wire \\m_payload_i[32]_i_2_n_0 ;
+  wire \\m_payload_i[33]_i_2_n_0 ;
+  wire \\m_payload_i[34]_i_3_n_0 ;
+  wire \\m_payload_i[3]_i_2_n_0 ;
+  wire \\m_payload_i[4]_i_2_n_0 ;
+  wire \\m_payload_i[5]_i_2_n_0 ;
+  wire \\m_payload_i[6]_i_2_n_0 ;
+  wire \\m_payload_i[7]_i_2_n_0 ;
+  wire \\m_payload_i[8]_i_2_n_0 ;
+  wire \\m_payload_i[9]_i_2_n_0 ;
+  wire \\m_payload_i_reg_n_0_[0] ;
+  wire [0:0]m_ready_d;
+  wire \\m_ready_d_reg[1] ;
+  wire m_valid_i;
+  wire m_valid_i_i_1_n_0;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire s_ready_i_i_1_n_0;
+  wire s_ready_i_reg_0;
+  wire [34:0]skid_buffer;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire sr_rvalid;
+
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(1\'b1),
+        .Q(\\aresetn_d_reg_n_0_[0] ),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\aresetn_d_reg_n_0_[0] ),
+        .Q(\\aresetn_d_reg_n_0_[1] ),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[0]_INST_0 
+       (.I0(aa_rready),
+        .I1(\\m_atarget_hot_reg[2] [0]),
+        .O(m_axi_rready[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[1]_INST_0 
+       (.I0(aa_rready),
+        .I1(\\m_atarget_hot_reg[2] [1]),
+        .O(m_axi_rready[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[2]_INST_0 
+       (.I0(aa_rready),
+        .I1(\\m_atarget_hot_reg[2] [2]),
+        .O(m_axi_rready[2]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[10]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[10] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[7]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[10]_i_2_n_0 ),
+        .O(skid_buffer[10]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[10]_i_2 
+       (.I0(m_axi_rdata[71]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[39]),
+        .O(\\m_payload_i[10]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[11]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[11] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[8]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[11]_i_2_n_0 ),
+        .O(skid_buffer[11]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[11]_i_2 
+       (.I0(m_axi_rdata[72]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[40]),
+        .O(\\m_payload_i[11]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF22E22222)) 
+    \\m_payload_i[12]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[12] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[41]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[12]_i_2_n_0 ),
+        .O(skid_buffer[12]));
+  LUT5 #(
+    .INIT(32\'h23002000)) 
+    \\m_payload_i[12]_i_2 
+       (.I0(m_axi_rdata[73]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[9]),
+        .O(\\m_payload_i[12]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF22E22222)) 
+    \\m_payload_i[13]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[13] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[42]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[13]_i_2_n_0 ),
+        .O(skid_buffer[13]));
+  LUT5 #(
+    .INIT(32\'h23002000)) 
+    \\m_payload_i[13]_i_2 
+       (.I0(m_axi_rdata[74]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[10]),
+        .O(\\m_payload_i[13]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[14]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[14] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[11]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[14]_i_2_n_0 ),
+        .O(skid_buffer[14]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[14]_i_2 
+       (.I0(m_axi_rdata[43]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[75]),
+        .O(\\m_payload_i[14]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[15]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[15] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[12]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[15]_i_2_n_0 ),
+        .O(skid_buffer[15]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[15]_i_2 
+       (.I0(m_axi_rdata[76]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[44]),
+        .O(\\m_payload_i[15]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[16]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[16] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[13]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[16]_i_2_n_0 ),
+        .O(skid_buffer[16]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[16]_i_2 
+       (.I0(m_axi_rdata[77]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[45]),
+        .O(\\m_payload_i[16]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[17]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[17] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[14]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[17]_i_2_n_0 ),
+        .O(skid_buffer[17]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[17]_i_2 
+       (.I0(m_axi_rdata[46]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[78]),
+        .O(\\m_payload_i[17]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[18]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[18] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[15]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[18]_i_2_n_0 ),
+        .O(skid_buffer[18]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[18]_i_2 
+       (.I0(m_axi_rdata[79]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[47]),
+        .O(\\m_payload_i[18]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[19]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[19] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[16]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[19]_i_2_n_0 ),
+        .O(skid_buffer[19]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[19]_i_2 
+       (.I0(m_axi_rdata[80]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[48]),
+        .O(\\m_payload_i[19]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFCFC08F80)) 
+    \\m_payload_i[1]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .I2(aa_rready),
+        .I3(\\skid_buffer_reg_n_0_[1] ),
+        .I4(m_axi_rresp[4]),
+        .I5(\\m_payload_i[1]_i_2_n_0 ),
+        .O(skid_buffer[1]));
+  LUT5 #(
+    .INIT(32\'h0B000800)) 
+    \\m_payload_i[1]_i_2 
+       (.I0(m_axi_rresp[2]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rresp[0]),
+        .O(\\m_payload_i[1]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF22E22222)) 
+    \\m_payload_i[20]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[20] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[49]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[20]_i_2_n_0 ),
+        .O(skid_buffer[20]));
+  LUT5 #(
+    .INIT(32\'h23002000)) 
+    \\m_payload_i[20]_i_2 
+       (.I0(m_axi_rdata[81]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[17]),
+        .O(\\m_payload_i[20]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF22E22222)) 
+    \\m_payload_i[21]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[21] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[50]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[21]_i_2_n_0 ),
+        .O(skid_buffer[21]));
+  LUT5 #(
+    .INIT(32\'h23002000)) 
+    \\m_payload_i[21]_i_2 
+       (.I0(m_axi_rdata[82]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[18]),
+        .O(\\m_payload_i[21]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[22]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[22] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[19]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[22]_i_2_n_0 ),
+        .O(skid_buffer[22]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[22]_i_2 
+       (.I0(m_axi_rdata[51]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[83]),
+        .O(\\m_payload_i[22]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[23]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[23] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[20]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[23]_i_2_n_0 ),
+        .O(skid_buffer[23]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[23]_i_2 
+       (.I0(m_axi_rdata[84]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[52]),
+        .O(\\m_payload_i[23]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[24]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[24] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[21]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[24]_i_2_n_0 ),
+        .O(skid_buffer[24]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[24]_i_2 
+       (.I0(m_axi_rdata[85]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[53]),
+        .O(\\m_payload_i[24]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[25]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[25] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[22]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[25]_i_2_n_0 ),
+        .O(skid_buffer[25]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[25]_i_2 
+       (.I0(m_axi_rdata[54]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[86]),
+        .O(\\m_payload_i[25]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[26]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[26] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[23]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[26]_i_2_n_0 ),
+        .O(skid_buffer[26]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[26]_i_2 
+       (.I0(m_axi_rdata[87]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[55]),
+        .O(\\m_payload_i[26]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[27]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[27] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[24]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[27]_i_2_n_0 ),
+        .O(skid_buffer[27]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[27]_i_2 
+       (.I0(m_axi_rdata[88]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[56]),
+        .O(\\m_payload_i[27]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF22E22222)) 
+    \\m_payload_i[28]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[28] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[57]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[28]_i_2_n_0 ),
+        .O(skid_buffer[28]));
+  LUT5 #(
+    .INIT(32\'h23002000)) 
+    \\m_payload_i[28]_i_2 
+       (.I0(m_axi_rdata[89]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[25]),
+        .O(\\m_payload_i[28]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF22E22222)) 
+    \\m_payload_i[29]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[29] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[58]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[29]_i_2_n_0 ),
+        .O(skid_buffer[29]));
+  LUT5 #(
+    .INIT(32\'h23002000)) 
+    \\m_payload_i[29]_i_2 
+       (.I0(m_axi_rdata[90]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[26]),
+        .O(\\m_payload_i[29]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFAFA08F80)) 
+    \\m_payload_i[2]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .I2(aa_rready),
+        .I3(\\skid_buffer_reg_n_0_[2] ),
+        .I4(m_axi_rresp[3]),
+        .I5(\\m_payload_i[2]_i_2_n_0 ),
+        .O(skid_buffer[2]));
+  LUT5 #(
+    .INIT(32\'h0E000200)) 
+    \\m_payload_i[2]_i_2 
+       (.I0(m_axi_rresp[1]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rresp[5]),
+        .O(\\m_payload_i[2]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[30]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[30] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[27]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[30]_i_2_n_0 ),
+        .O(skid_buffer[30]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[30]_i_2 
+       (.I0(m_axi_rdata[59]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[91]),
+        .O(\\m_payload_i[30]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[31]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[31] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[28]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[31]_i_2_n_0 ),
+        .O(skid_buffer[31]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[31]_i_2 
+       (.I0(m_axi_rdata[92]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[60]),
+        .O(\\m_payload_i[31]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[32]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[32] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[29]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[32]_i_2_n_0 ),
+        .O(skid_buffer[32]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[32]_i_2 
+       (.I0(m_axi_rdata[93]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[61]),
+        .O(\\m_payload_i[32]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[33]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[33] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[30]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[33]_i_2_n_0 ),
+        .O(skid_buffer[33]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[33]_i_2 
+       (.I0(m_axi_rdata[62]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[94]),
+        .O(\\m_payload_i[33]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[34]_i_2 
+       (.I0(\\skid_buffer_reg_n_0_[34] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[31]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[34]_i_3_n_0 ),
+        .O(skid_buffer[34]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[34]_i_3 
+       (.I0(m_axi_rdata[95]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[63]),
+        .O(\\m_payload_i[34]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[3]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[3] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[0]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[3]_i_2_n_0 ),
+        .O(skid_buffer[3]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[3]_i_2 
+       (.I0(m_axi_rdata[64]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[32]),
+        .O(\\m_payload_i[3]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF22E22222)) 
+    \\m_payload_i[4]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[4] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[33]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[4]_i_2_n_0 ),
+        .O(skid_buffer[4]));
+  LUT5 #(
+    .INIT(32\'h23002000)) 
+    \\m_payload_i[4]_i_2 
+       (.I0(m_axi_rdata[65]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[1]),
+        .O(\\m_payload_i[4]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF22E22222)) 
+    \\m_payload_i[5]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[5] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[34]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[5]_i_2_n_0 ),
+        .O(skid_buffer[5]));
+  LUT5 #(
+    .INIT(32\'h23002000)) 
+    \\m_payload_i[5]_i_2 
+       (.I0(m_axi_rdata[66]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[2]),
+        .O(\\m_payload_i[5]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[6]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[6] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[3]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[6]_i_2_n_0 ),
+        .O(skid_buffer[6]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[6]_i_2 
+       (.I0(m_axi_rdata[35]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[67]),
+        .O(\\m_payload_i[6]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[7]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[7] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[4]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[7]_i_2_n_0 ),
+        .O(skid_buffer[7]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[7]_i_2 
+       (.I0(m_axi_rdata[68]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[36]),
+        .O(\\m_payload_i[7]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[8]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[8] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[5]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[8]_i_2_n_0 ),
+        .O(skid_buffer[8]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[8]_i_2 
+       (.I0(m_axi_rdata[69]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[37]),
+        .O(\\m_payload_i[8]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF222222E2)) 
+    \\m_payload_i[9]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[9] ),
+        .I1(aa_rready),
+        .I2(m_axi_rdata[6]),
+        .I3(Q[1]),
+        .I4(Q[0]),
+        .I5(\\m_payload_i[9]_i_2_n_0 ),
+        .O(skid_buffer[9]));
+  LUT5 #(
+    .INIT(32\'h2C002000)) 
+    \\m_payload_i[9]_i_2 
+       (.I0(m_axi_rdata[38]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(aa_rready),
+        .I4(m_axi_rdata[70]),
+        .O(\\m_payload_i[9]_i_2_n_0 ));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[0]),
+        .Q(\\m_payload_i_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[10]),
+        .Q(\\s_axi_rdata[31] [9]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[11]),
+        .Q(\\s_axi_rdata[31] [10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[12]),
+        .Q(\\s_axi_rdata[31] [11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[13]),
+        .Q(\\s_axi_rdata[31] [12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[14]),
+        .Q(\\s_axi_rdata[31] [13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[15]),
+        .Q(\\s_axi_rdata[31] [14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[16]),
+        .Q(\\s_axi_rdata[31] [15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[17]),
+        .Q(\\s_axi_rdata[31] [16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[18]),
+        .Q(\\s_axi_rdata[31] [17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[19]),
+        .Q(\\s_axi_rdata[31] [18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[1]),
+        .Q(\\s_axi_rdata[31] [0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[20]),
+        .Q(\\s_axi_rdata[31] [19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[21]),
+        .Q(\\s_axi_rdata[31] [20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[22]),
+        .Q(\\s_axi_rdata[31] [21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[23]),
+        .Q(\\s_axi_rdata[31] [22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[24]),
+        .Q(\\s_axi_rdata[31] [23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[25]),
+        .Q(\\s_axi_rdata[31] [24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[26]),
+        .Q(\\s_axi_rdata[31] [25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[27]),
+        .Q(\\s_axi_rdata[31] [26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[28]),
+        .Q(\\s_axi_rdata[31] [27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[29]),
+        .Q(\\s_axi_rdata[31] [28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[2]),
+        .Q(\\s_axi_rdata[31] [1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[30]),
+        .Q(\\s_axi_rdata[31] [29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[31]),
+        .Q(\\s_axi_rdata[31] [30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[32]),
+        .Q(\\s_axi_rdata[31] [31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[33]),
+        .Q(\\s_axi_rdata[31] [32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[34]),
+        .Q(\\s_axi_rdata[31] [33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[3]),
+        .Q(\\s_axi_rdata[31] [2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[4]),
+        .Q(\\s_axi_rdata[31] [3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[5]),
+        .Q(\\s_axi_rdata[31] [4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[6]),
+        .Q(\\s_axi_rdata[31] [5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[7]),
+        .Q(\\s_axi_rdata[31] [6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[8]),
+        .Q(\\s_axi_rdata[31] [7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[9]),
+        .Q(\\s_axi_rdata[31] [8]),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h000000007FFFFFFF)) 
+    \\m_ready_d[1]_i_3__0 
+       (.I0(sr_rvalid),
+        .I1(\\m_payload_i_reg_n_0_[0] ),
+        .I2(s_axi_rready),
+        .I3(aa_grant_rnw),
+        .I4(m_valid_i),
+        .I5(m_ready_d),
+        .O(\\m_ready_d_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hA2A2A222A2A2A2A2)) 
+    m_valid_i_i_1
+       (.I0(\\aresetn_d_reg_n_0_[1] ),
+        .I1(s_ready_i_reg_0),
+        .I2(sr_rvalid),
+        .I3(m_ready_d),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(s_axi_rready),
+        .O(m_valid_i_i_1_n_0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i_i_1_n_0),
+        .Q(sr_rvalid),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_rvalid[0]_INST_0 
+       (.I0(sr_rvalid),
+        .I1(aa_grant_any),
+        .O(s_axi_rvalid));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAA222A2222)) 
+    s_ready_i_i_1
+       (.I0(\\aresetn_d_reg_n_0_[0] ),
+        .I1(sr_rvalid),
+        .I2(m_ready_d),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .I4(s_axi_rready),
+        .I5(s_ready_i_reg_0),
+        .O(s_ready_i_i_1_n_0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i_i_1_n_0),
+        .Q(aa_rready),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\skid_buffer[0]_i_1 
+       (.I0(aa_rready),
+        .I1(\\skid_buffer_reg_n_0_[0] ),
+        .O(skid_buffer[0]));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[10]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[11]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[12]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[13]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[14]),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[15]),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[16]),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[17]),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[18]),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[19]),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[20]),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[21]),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[22]),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[23]),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[24]),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[25]),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[26]),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[27]),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[28]),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[29]),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[30]),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[31]),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[32]),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[33]),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[34]),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[3]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[4]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[5]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[6]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[7]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[8]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[9]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (aclk,
+    aresetn,
+    s_axi_awaddr,
+    s_axi_awprot,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awaddr,
+    m_axi_awprot,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bresp,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_araddr,
+    m_axi_arprot,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rvalid,
+    m_axi_rready);
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLKIF CLK"" *) input aclk;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RSTIF RST"" *) input aresetn;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"" *) input [31:0]s_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"" *) input [2:0]s_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"" *) input [0:0]s_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"" *) output [0:0]s_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WVALID"" *) input [0:0]s_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WREADY"" *) output [0:0]s_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BVALID"" *) output [0:0]s_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BREADY"" *) input [0:0]s_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"" *) input [31:0]s_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"" *) input [2:0]s_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"" *) input [0:0]s_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"" *) output [0:0]s_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RVALID"" *) output [0:0]s_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RREADY"" *) input [0:0]s_axi_rready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]"" *) output [95:0]m_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]"" *) output [8:0]m_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]"" *) output [2:0]m_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]"" *) input [2:0]m_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]"" *) output [95:0]m_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]"" *) output [11:0]m_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]"" *) output [2:0]m_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]"" *) input [2:0]m_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]"" *) input [5:0]m_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]"" *) input [2:0]m_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]"" *) output [2:0]m_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]"" *) output [95:0]m_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]"" *) output [8:0]m_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]"" *) output [2:0]m_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]"" *) input [2:0]m_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]"" *) input [95:0]m_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]"" *) input [5:0]m_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]"" *) input [2:0]m_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]"" *) output [2:0]m_axi_rready;
+
+  wire aclk;
+  wire aresetn;
+  wire [95:0]m_axi_araddr;
+  wire [8:0]m_axi_arprot;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_arvalid;
+  wire [95:0]m_axi_awaddr;
+  wire [8:0]m_axi_awprot;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [95:0]m_axi_wdata;
+  wire [2:0]m_axi_wready;
+  wire [11:0]m_axi_wstrb;
+  wire [2:0]m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+  wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED;
+  wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+  wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+  wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED;
+  wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+  wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+  (* C_AXI_ADDR_WIDTH = ""32"" *) 
+  (* C_AXI_ARUSER_WIDTH = ""1"" *) 
+  (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+  (* C_AXI_BUSER_WIDTH = ""1"" *) 
+  (* C_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_AXI_ID_WIDTH = ""1"" *) 
+  (* C_AXI_PROTOCOL = ""2"" *) 
+  (* C_AXI_RUSER_WIDTH = ""1"" *) 
+  (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+  (* C_AXI_WUSER_WIDTH = ""1"" *) 
+  (* C_CONNECTIVITY_MODE = ""0"" *) 
+  (* C_DEBUG = ""1"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_M_AXI_ADDR_WIDTH = ""96\'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"" *) 
+  (* C_M_AXI_BASE_ADDR = ""192\'b000000000000000000000000000000000100000110000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+  (* C_M_AXI_READ_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_READ_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_SECURE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* C_M_AXI_WRITE_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_WRITE_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_NUM_ADDR_RANGES = ""1"" *) 
+  (* C_NUM_MASTER_SLOTS = ""3"" *) 
+  (* C_NUM_SLAVE_SLOTS = ""1"" *) 
+  (* C_R_REGISTER = ""1"" *) 
+  (* C_S_AXI_ARB_PRIORITY = ""0"" *) 
+  (* C_S_AXI_BASE_ID = ""0"" *) 
+  (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+  (* C_S_AXI_SINGLE_THREAD = ""1"" *) 
+  (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) 
+  (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+  (* DowngradeIPIdentifiedWarnings = ""yes"" *) 
+  (* P_ADDR_DECODE = ""1"" *) 
+  (* P_AXI3 = ""1"" *) 
+  (* P_AXI4 = ""0"" *) 
+  (* P_AXILITE = ""2"" *) 
+  (* P_AXILITE_SIZE = ""3\'b010"" *) 
+  (* P_FAMILY = ""zynq"" *) 
+  (* P_INCR = ""2\'b01"" *) 
+  (* P_LEN = ""8"" *) 
+  (* P_LOCK = ""1"" *) 
+  (* P_M_AXI_ERR_MODE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_M_AXI_SUPPORTS_READ = ""3\'b111"" *) 
+  (* P_M_AXI_SUPPORTS_WRITE = ""3\'b111"" *) 
+  (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) 
+  (* P_RANGE_CHECK = ""1"" *) 
+  (* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+  (* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar inst
+       (.aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]),
+        .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]),
+        .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]),
+        .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]),
+        .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]),
+        .m_axi_arprot(m_axi_arprot),
+        .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
+        .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]),
+        .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]),
+        .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]),
+        .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]),
+        .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]),
+        .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]),
+        .m_axi_awprot(m_axi_awprot),
+        .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
+        .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]),
+        .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bid({1\'b0,1\'b0,1\'b0}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_buser({1\'b0,1\'b0,1\'b0}),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rid({1\'b0,1\'b0,1\'b0}),
+        .m_axi_rlast({1\'b1,1\'b1,1\'b1}),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_ruser({1\'b0,1\'b0,1\'b0}),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wdata(m_axi_wdata),
+        .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]),
+        .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wstrb(m_axi_wstrb),
+        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst({1\'b0,1\'b0}),
+        .s_axi_arcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arid(1\'b0),
+        .s_axi_arlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arlock(1\'b0),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_aruser(1\'b0),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst({1\'b0,1\'b0}),
+        .s_axi_awcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awid(1\'b0),
+        .s_axi_awlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awlock(1\'b0),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_awuser(1\'b0),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
+        .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wid(1\'b0),
+        .s_axi_wlast(1\'b1),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wuser(1\'b0),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:44:08 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top design_1_xbar_0 -prefix
+//               design_1_xbar_0_ design_1_xbar_0_sim_netlist.v
+// Design      : design_1_xbar_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd
+   (m_valid_i,
+    SR,
+    aa_grant_rnw,
+    D,
+    any_error,
+    Q,
+    \\m_ready_d_reg[2] ,
+    s_axi_bvalid,
+    m_ready_d0,
+    m_axi_bready,
+    \\gen_axilite.s_axi_bvalid_i_reg ,
+    s_axi_wready,
+    m_axi_wvalid,
+    \\m_ready_d_reg[2]_0 ,
+    \\gen_axilite.s_axi_awready_i_reg ,
+    m_axi_awvalid,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
+    s_ready_i_reg,
+    E,
+    m_axi_arvalid,
+    s_ready_i_reg_0,
+    s_axi_awready,
+    s_axi_arready,
+    s_axi_rvalid,
+    aclk,
+    aresetn_d,
+    m_ready_d,
+    \\gen_axilite.s_axi_awready_i_reg_0 ,
+    \\gen_axilite.s_axi_bvalid_i_reg_0 ,
+    s_axi_bready,
+    \\m_atarget_hot_reg[1] ,
+    \\gen_axilite.s_axi_awready_i_reg_1 ,
+    s_axi_wvalid,
+    m_valid_i_reg,
+    m_ready_d_0,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    aa_rready,
+    \\gen_axilite.s_axi_rvalid_i_reg ,
+    s_axi_rready,
+    sr_rvalid,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    \\m_ready_d_reg[1] ,
+    s_axi_awvalid);
+  output m_valid_i;
+  output [0:0]SR;
+  output aa_grant_rnw;
+  output [2:0]D;
+  output any_error;
+  output [34:0]Q;
+  output \\m_ready_d_reg[2] ;
+  output [0:0]s_axi_bvalid;
+  output [0:0]m_ready_d0;
+  output [1:0]m_axi_bready;
+  output \\gen_axilite.s_axi_bvalid_i_reg ;
+  output [0:0]s_axi_wready;
+  output [1:0]m_axi_wvalid;
+  output \\m_ready_d_reg[2]_0 ;
+  output \\gen_axilite.s_axi_awready_i_reg ;
+  output [1:0]m_axi_awvalid;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  output s_ready_i_reg;
+  output [0:0]E;
+  output [1:0]m_axi_arvalid;
+  output s_ready_i_reg_0;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rvalid;
+  input aclk;
+  input aresetn_d;
+  input [2:0]m_ready_d;
+  input \\gen_axilite.s_axi_awready_i_reg_0 ;
+  input \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  input [0:0]s_axi_bready;
+  input [1:0]\\m_atarget_hot_reg[1] ;
+  input \\gen_axilite.s_axi_awready_i_reg_1 ;
+  input [0:0]s_axi_wvalid;
+  input m_valid_i_reg;
+  input [1:0]m_ready_d_0;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input aa_rready;
+  input \\gen_axilite.s_axi_rvalid_i_reg ;
+  input [0:0]s_axi_rready;
+  input sr_rvalid;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input \\m_ready_d_reg[1] ;
+  input [0:0]s_axi_awvalid;
+
+  wire [2:0]D;
+  wire [0:0]E;
+  wire [34:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire any_error;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg_0 ;
+  wire \\gen_axilite.s_axi_awready_i_reg_1 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  wire \\gen_axilite.s_axi_rvalid_i_reg ;
+  wire \\gen_no_arbiter.grant_rnw_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  wire \\gen_no_arbiter.m_valid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_valid_i_i_2_n_0 ;
+  wire \\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
+  wire \\m_atarget_enc[1]_i_2_n_0 ;
+  wire \\m_atarget_enc[1]_i_3_n_0 ;
+  wire \\m_atarget_enc[1]_i_4_n_0 ;
+  wire [1:0]\\m_atarget_hot_reg[1] ;
+  wire [1:0]m_axi_arvalid;
+  wire [1:0]m_axi_awvalid;
+  wire [1:0]m_axi_bready;
+  wire [1:0]m_axi_wvalid;
+  wire [2:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire [1:0]m_ready_d_0;
+  wire \\m_ready_d_reg[1] ;
+  wire \\m_ready_d_reg[2] ;
+  wire \\m_ready_d_reg[2]_0 ;
+  wire m_valid_i;
+  wire m_valid_i_reg;
+  wire p_0_in1_in;
+  wire [48:1]s_amesg;
+  wire \\s_arvalid_reg[0]_i_1_n_0 ;
+  wire \\s_arvalid_reg_reg_n_0_[0] ;
+  wire s_awvalid_reg;
+  wire \\s_awvalid_reg[0]_i_1_n_0 ;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [0:0]s_axi_bvalid;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire s_ready_i;
+  wire s_ready_i_reg;
+  wire s_ready_i_reg_0;
+  wire sr_rvalid;
+
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT4 #(
+    .INIT(16\'hFBFF)) 
+    \\gen_axilite.s_axi_awready_i_i_2 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d[1]),
+        .I3(s_axi_wvalid),
+        .O(\\gen_axilite.s_axi_awready_i_reg ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\gen_axilite.s_axi_bvalid_i_i_2 
+       (.I0(s_axi_bready),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[0]),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg ));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT2 #(
+    .INIT(4\'h7)) 
+    \\gen_axilite.s_axi_rvalid_i_i_2 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .O(s_ready_i_reg_0));
+  LUT6 #(
+    .INIT(64\'hFFFFFF5300000050)) 
+    \\gen_no_arbiter.grant_rnw_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_arvalid),
+        .I3(aa_grant_any),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\gen_no_arbiter.grant_rnw_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.grant_rnw_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.grant_rnw_i_1_n_0 ),
+        .Q(aa_grant_rnw),
+        .R(SR));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[10]_i_1 
+       (.I0(s_axi_araddr[9]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[9]),
+        .O(s_amesg[10]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[11]_i_1 
+       (.I0(s_axi_araddr[10]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[10]),
+        .O(s_amesg[11]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[12]_i_1 
+       (.I0(s_axi_araddr[11]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[11]),
+        .O(s_amesg[12]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[13]_i_1 
+       (.I0(s_axi_araddr[12]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[12]),
+        .O(s_amesg[13]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[14]_i_1 
+       (.I0(s_axi_araddr[13]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[13]),
+        .O(s_amesg[14]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[15]_i_1 
+       (.I0(s_axi_araddr[14]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[14]),
+        .O(s_amesg[15]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[16]_i_1 
+       (.I0(s_axi_araddr[15]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[15]),
+        .O(s_amesg[16]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[17]_i_1 
+       (.I0(s_axi_araddr[16]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[16]),
+        .O(s_amesg[17]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[18]_i_1 
+       (.I0(s_axi_araddr[17]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[17]),
+        .O(s_amesg[18]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[19]_i_1 
+       (.I0(s_axi_araddr[18]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[18]),
+        .O(s_amesg[19]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[1]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[0]),
+        .O(s_amesg[1]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[20]_i_1 
+       (.I0(s_axi_araddr[19]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[19]),
+        .O(s_amesg[20]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[21]_i_1 
+       (.I0(s_axi_araddr[20]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[20]),
+        .O(s_amesg[21]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[22]_i_1 
+       (.I0(s_axi_araddr[21]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[21]),
+        .O(s_amesg[22]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[23]_i_1 
+       (.I0(s_axi_araddr[22]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[22]),
+        .O(s_amesg[23]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[24]_i_1 
+       (.I0(s_axi_araddr[23]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[23]),
+        .O(s_amesg[24]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[25]_i_1 
+       (.I0(s_axi_araddr[24]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[24]),
+        .O(s_amesg[25]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[26]_i_1 
+       (.I0(s_axi_araddr[25]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[25]),
+        .O(s_amesg[26]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[27]_i_1 
+       (.I0(s_axi_araddr[26]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[26]),
+        .O(s_amesg[27]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[28]_i_1 
+       (.I0(s_axi_araddr[27]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[27]),
+        .O(s_amesg[28]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[29]_i_1 
+       (.I0(s_axi_araddr[28]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[28]),
+        .O(s_amesg[29]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[2]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[1]),
+        .O(s_amesg[2]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[30]_i_1 
+       (.I0(s_axi_araddr[29]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[29]),
+        .O(s_amesg[30]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[31]_i_1 
+       (.I0(s_axi_araddr[30]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[30]),
+        .O(s_amesg[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_1 
+       (.I0(aresetn_d),
+        .O(SR));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_2 
+       (.I0(aa_grant_any),
+        .O(p_0_in1_in));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_3 
+       (.I0(s_axi_araddr[31]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[31]),
+        .O(s_amesg[32]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[3]_i_1 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[2]),
+        .O(s_amesg[3]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[46]_i_1 
+       (.I0(s_axi_arprot[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[0]),
+        .O(s_amesg[46]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[47]_i_1 
+       (.I0(s_axi_arprot[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[1]),
+        .O(s_amesg[47]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[48]_i_1 
+       (.I0(s_axi_arprot[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[2]),
+        .O(s_amesg[48]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[4]_i_1 
+       (.I0(s_axi_araddr[3]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[3]),
+        .O(s_amesg[4]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[5]_i_1 
+       (.I0(s_axi_araddr[4]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[4]),
+        .O(s_amesg[5]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[6]_i_1 
+       (.I0(s_axi_araddr[5]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[5]),
+        .O(s_amesg[6]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[7]_i_1 
+       (.I0(s_axi_araddr[6]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[6]),
+        .O(s_amesg[7]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[8]_i_1 
+       (.I0(s_axi_araddr[7]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[7]),
+        .O(s_amesg[8]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[9]_i_1 
+       (.I0(s_axi_araddr[8]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[8]),
+        .O(s_amesg[9]));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[10] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[10]),
+        .Q(Q[9]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[11] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[11]),
+        .Q(Q[10]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[12] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[12]),
+        .Q(Q[11]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[13] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[13]),
+        .Q(Q[12]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[14] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[14]),
+        .Q(Q[13]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[15] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[15]),
+        .Q(Q[14]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[16] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[16]),
+        .Q(Q[15]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[17] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[17]),
+        .Q(Q[16]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[18] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[18]),
+        .Q(Q[17]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[19] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[19]),
+        .Q(Q[18]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[1] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[1]),
+        .Q(Q[0]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[20] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[20]),
+        .Q(Q[19]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[21] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[21]),
+        .Q(Q[20]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[22] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[22]),
+        .Q(Q[21]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[23] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[23]),
+        .Q(Q[22]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[24] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[24]),
+        .Q(Q[23]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[25] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[25]),
+        .Q(Q[24]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[26] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[26]),
+        .Q(Q[25]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[27] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[27]),
+        .Q(Q[26]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[28] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[28]),
+        .Q(Q[27]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[29] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[29]),
+        .Q(Q[28]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[2] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[2]),
+        .Q(Q[1]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[30] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[30]),
+        .Q(Q[29]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[31] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[31]),
+        .Q(Q[30]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[32] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[32]),
+        .Q(Q[31]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[3] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[3]),
+        .Q(Q[2]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[46] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[46]),
+        .Q(Q[32]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[47] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[47]),
+        .Q(Q[33]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[48] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[48]),
+        .Q(Q[34]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[4] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[4]),
+        .Q(Q[3]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[5] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[5]),
+        .Q(Q[4]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[6] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[6]),
+        .Q(Q[5]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[7] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[7]),
+        .Q(Q[6]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[8] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[8]),
+        .Q(Q[7]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[9] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[9]),
+        .Q(Q[8]),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0000000088888088)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_1 
+       (.I0(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
+        .I1(aresetn_d),
+        .I2(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
+        .I3(m_ready_d0),
+        .I4(\\m_ready_d_reg[1] ),
+        .I5(\\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT4 #(
+    .INIT(16\'hF0FE)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_2 
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_arvalid),
+        .I2(aa_grant_any),
+        .I3(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_3 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h54000000)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_5 
+       (.I0(m_valid_i_reg),
+        .I1(m_ready_d_0[1]),
+        .I2(\\gen_axilite.s_axi_arready_i_reg ),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ));
+  FDRE \\gen_no_arbiter.m_grant_hot_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
+        .Q(aa_grant_any),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h3AFA3A0A3AFA3AFA)) 
+    \\gen_no_arbiter.m_valid_i_i_1 
+       (.I0(aa_grant_any),
+        .I1(\\gen_no_arbiter.m_valid_i_i_2_n_0 ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(\\m_ready_d_reg[1] ),
+        .I5(m_ready_d0),
+        .O(\\gen_no_arbiter.m_valid_i_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h0000FF80)) 
+    \\gen_no_arbiter.m_valid_i_i_2 
+       (.I0(\\gen_axilite.s_axi_arready_i_reg ),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(m_ready_d_0[1]),
+        .I4(m_valid_i_reg),
+        .O(\\gen_no_arbiter.m_valid_i_i_2_n_0 ));
+  FDRE \\gen_no_arbiter.m_valid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_valid_i_i_1_n_0 ),
+        .Q(m_valid_i),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT3 #(
+    .INIT(8\'h40)) 
+    \\gen_no_arbiter.s_ready_i[0]_i_1 
+       (.I0(m_valid_i),
+        .I1(aa_grant_any),
+        .I2(aresetn_d),
+        .O(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.s_ready_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
+        .Q(s_ready_i),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFFFFFEFF)) 
+    \\m_atarget_enc[1]_i_1 
+       (.I0(\\m_atarget_enc[1]_i_2_n_0 ),
+        .I1(\\m_atarget_enc[1]_i_3_n_0 ),
+        .I2(\\m_atarget_enc[1]_i_4_n_0 ),
+        .I3(Q[30]),
+        .I4(Q[23]),
+        .I5(Q[27]),
+        .O(any_error));
+  LUT4 #(
+    .INIT(16\'hFFEF)) 
+    \\m_atarget_enc[1]_i_2 
+       (.I0(Q[25]),
+        .I1(Q[20]),
+        .I2(Q[21]),
+        .I3(Q[29]),
+        .O(\\m_atarget_enc[1]_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFD)) 
+    \\m_atarget_enc[1]_i_3 
+       (.I0(Q[24]),
+        .I1(Q[26]),
+        .I2(Q[19]),
+        .I3(Q[18]),
+        .O(\\m_atarget_enc[1]_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\m_atarget_enc[1]_i_4 
+       (.I0(Q[17]),
+        .I1(Q[31]),
+        .I2(Q[22]),
+        .I3(Q[28]),
+        .O(\\m_atarget_enc[1]_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\m_atarget_hot[0]_i_1 
+       (.I0(Q[16]),
+        .I1(aa_grant_any),
+        .I2(any_error),
+        .O(D[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\m_atarget_hot[1]_i_1 
+       (.I0(Q[16]),
+        .I1(aa_grant_any),
+        .I2(any_error),
+        .O(D[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_atarget_hot[3]_i_1 
+       (.I0(any_error),
+        .I1(aa_grant_any),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[1]));
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[0]));
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[1]));
+  LUT5 #(
+    .INIT(32\'h0080FFFF)) 
+    \\m_payload_i[34]_i_1 
+       (.I0(s_axi_rready),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[0]),
+        .I4(sr_rvalid),
+        .O(E));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'hF4F0F0F0)) 
+    \\m_ready_d[2]_i_2 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d[0]),
+        .I3(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .I4(s_axi_bready),
+        .O(m_ready_d0));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h4555)) 
+    \\m_ready_d[2]_i_3 
+       (.I0(m_ready_d[2]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(\\gen_axilite.s_axi_awready_i_reg_0 ),
+        .O(\\m_ready_d_reg[2] ));
+  LUT5 #(
+    .INIT(32\'h0B0F0F0F)) 
+    \\m_ready_d[2]_i_4 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d[1]),
+        .I3(s_axi_wvalid),
+        .I4(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .O(\\m_ready_d_reg[2]_0 ));
+  LUT5 #(
+    .INIT(32\'h8AAAAAAA)) 
+    m_valid_i_i_2
+       (.I0(aa_rready),
+        .I1(m_ready_d_0[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(\\gen_axilite.s_axi_rvalid_i_reg ),
+        .O(s_ready_i_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT4 #(
+    .INIT(16\'h0040)) 
+    \\s_arvalid_reg[0]_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_arvalid),
+        .I2(aresetn_d),
+        .I3(s_ready_i),
+        .O(\\s_arvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_arvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_arvalid_reg[0]_i_1_n_0 ),
+        .Q(\\s_arvalid_reg_reg_n_0_[0] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h0000000000D00000)) 
+    \\s_awvalid_reg[0]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_awvalid_reg),
+        .I2(s_axi_awvalid),
+        .I3(\\s_arvalid_reg_reg_n_0_[0] ),
+        .I4(aresetn_d),
+        .I5(s_ready_i),
+        .O(\\s_awvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_awvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_awvalid_reg[0]_i_1_n_0 ),
+        .Q(s_awvalid_reg),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_arready[0]_INST_0 
+       (.I0(s_ready_i),
+        .I1(aa_grant_rnw),
+        .O(s_axi_arready));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_awready[0]_INST_0 
+       (.I0(s_ready_i),
+        .I1(aa_grant_rnw),
+        .O(s_axi_awready));
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\s_axi_bvalid[0]_INST_0 
+       (.I0(aa_grant_any),
+        .I1(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .I2(m_ready_d[0]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(s_axi_bvalid));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_rvalid[0]_INST_0 
+       (.I0(aa_grant_any),
+        .I1(sr_rvalid),
+        .O(s_axi_rvalid));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\s_axi_wready[0]_INST_0 
+       (.I0(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .I1(aa_grant_any),
+        .I2(m_ready_d[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(s_axi_wready));
+endmodule
+
+(* C_AXI_ADDR_WIDTH = ""32"" *) (* C_AXI_ARUSER_WIDTH = ""1"" *) (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+(* C_AXI_BUSER_WIDTH = ""1"" *) (* C_AXI_DATA_WIDTH = ""32"" *) (* C_AXI_ID_WIDTH = ""1"" *) 
+(* C_AXI_PROTOCOL = ""2"" *) (* C_AXI_RUSER_WIDTH = ""1"" *) (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+(* C_AXI_WUSER_WIDTH = ""1"" *) (* C_CONNECTIVITY_MODE = ""0"" *) (* C_DEBUG = ""1"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_M_AXI_ADDR_WIDTH = ""96\'b000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000"" *) (* C_M_AXI_BASE_ADDR = ""192\'b111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+(* C_M_AXI_READ_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_READ_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_SECURE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+(* C_M_AXI_WRITE_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_WRITE_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_NUM_ADDR_RANGES = ""1"" *) 
+(* C_NUM_MASTER_SLOTS = ""3"" *) (* C_NUM_SLAVE_SLOTS = ""1"" *) (* C_R_REGISTER = ""1"" *) 
+(* C_S_AXI_ARB_PRIORITY = ""0"" *) (* C_S_AXI_BASE_ID = ""0"" *) (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+(* C_S_AXI_SINGLE_THREAD = ""1"" *) (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+(* DowngradeIPIdentifiedWarnings = ""yes"" *) (* P_ADDR_DECODE = ""1"" *) (* P_AXI3 = ""1"" *) 
+(* P_AXI4 = ""0"" *) (* P_AXILITE = ""2"" *) (* P_AXILITE_SIZE = ""3\'b010"" *) 
+(* P_FAMILY = ""zynq"" *) (* P_INCR = ""2\'b01"" *) (* P_LEN = ""8"" *) 
+(* P_LOCK = ""1"" *) (* P_M_AXI_ERR_MODE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) (* P_M_AXI_SUPPORTS_READ = ""3\'b111"" *) 
+(* P_M_AXI_SUPPORTS_WRITE = ""3\'b111"" *) (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) (* P_RANGE_CHECK = ""1"" *) 
+(* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+(* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+module design_1_xbar_0_axi_crossbar_v2_1_12_axi_crossbar
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awqos,
+    s_axi_awuser,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wuser,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_buser,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arqos,
+    s_axi_aruser,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_ruser,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awid,
+    m_axi_awaddr,
+    m_axi_awlen,
+    m_axi_awsize,
+    m_axi_awburst,
+    m_axi_awlock,
+    m_axi_awcache,
+    m_axi_awprot,
+    m_axi_awregion,
+    m_axi_awqos,
+    m_axi_awuser,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wid,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wlast,
+    m_axi_wuser,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bid,
+    m_axi_bresp,
+    m_axi_buser,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_arid,
+    m_axi_araddr,
+    m_axi_arlen,
+    m_axi_arsize,
+    m_axi_arburst,
+    m_axi_arlock,
+    m_axi_arcache,
+    m_axi_arprot,
+    m_axi_arregion,
+    m_axi_arqos,
+    m_axi_aruser,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rlast,
+    m_axi_ruser,
+    m_axi_rvalid,
+    m_axi_rready);
+  input aclk;
+  input aresetn;
+  input [0:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [7:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [0:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awqos;
+  input [0:0]s_axi_awuser;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [0:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wlast;
+  input [0:0]s_axi_wuser;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [0:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_buser;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [0:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [7:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [0:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arqos;
+  input [0:0]s_axi_aruser;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rlast;
+  output [0:0]s_axi_ruser;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [2:0]m_axi_awid;
+  output [95:0]m_axi_awaddr;
+  output [23:0]m_axi_awlen;
+  output [8:0]m_axi_awsize;
+  output [5:0]m_axi_awburst;
+  output [2:0]m_axi_awlock;
+  output [11:0]m_axi_awcache;
+  output [8:0]m_axi_awprot;
+  output [11:0]m_axi_awregion;
+  output [11:0]m_axi_awqos;
+  output [2:0]m_axi_awuser;
+  output [2:0]m_axi_awvalid;
+  input [2:0]m_axi_awready;
+  output [2:0]m_axi_wid;
+  output [95:0]m_axi_wdata;
+  output [11:0]m_axi_wstrb;
+  output [2:0]m_axi_wlast;
+  output [2:0]m_axi_wuser;
+  output [2:0]m_axi_wvalid;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bid;
+  input [5:0]m_axi_bresp;
+  input [2:0]m_axi_buser;
+  input [2:0]m_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [2:0]m_axi_arid;
+  output [95:0]m_axi_araddr;
+  output [23:0]m_axi_arlen;
+  output [8:0]m_axi_arsize;
+  output [5:0]m_axi_arburst;
+  output [2:0]m_axi_arlock;
+  output [11:0]m_axi_arcache;
+  output [8:0]m_axi_arprot;
+  output [11:0]m_axi_arregion;
+  output [11:0]m_axi_arqos;
+  output [2:0]m_axi_aruser;
+  output [2:0]m_axi_arvalid;
+  input [2:0]m_axi_arready;
+  input [2:0]m_axi_rid;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rlast;
+  input [2:0]m_axi_ruser;
+  input [2:0]m_axi_rvalid;
+  output [2:0]m_axi_rready;
+
+  wire \\<const0> ;
+  wire aclk;
+  wire aresetn;
+  wire [15:0]\\^m_axi_araddr ;
+  wire [2:0]\\^m_axi_arprot ;
+  wire [2:0]m_axi_arready;
+  wire [1:0]\\^m_axi_arvalid ;
+  wire [95:80]\\^m_axi_awaddr ;
+  wire [2:0]m_axi_awready;
+  wire [1:0]\\^m_axi_awvalid ;
+  wire [1:0]\\^m_axi_bready ;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [1:0]\\^m_axi_rready ;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [1:0]\\^m_axi_wvalid ;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+
+  assign m_axi_araddr[95:80] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[79:64] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[63:48] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[31:16] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_arburst[5] = \\<const0> ;
+  assign m_axi_arburst[4] = \\<const0> ;
+  assign m_axi_arburst[3] = \\<const0> ;
+  assign m_axi_arburst[2] = \\<const0> ;
+  assign m_axi_arburst[1] = \\<const0> ;
+  assign m_axi_arburst[0] = \\<const0> ;
+  assign m_axi_arcache[11] = \\<const0> ;
+  assign m_axi_arcache[10] = \\<const0> ;
+  assign m_axi_arcache[9] = \\<const0> ;
+  assign m_axi_arcache[8] = \\<const0> ;
+  assign m_axi_arcache[7] = \\<const0> ;
+  assign m_axi_arcache[6] = \\<const0> ;
+  assign m_axi_arcache[5] = \\<const0> ;
+  assign m_axi_arcache[4] = \\<const0> ;
+  assign m_axi_arcache[3] = \\<const0> ;
+  assign m_axi_arcache[2] = \\<const0> ;
+  assign m_axi_arcache[1] = \\<const0> ;
+  assign m_axi_arcache[0] = \\<const0> ;
+  assign m_axi_arid[2] = \\<const0> ;
+  assign m_axi_arid[1] = \\<const0> ;
+  assign m_axi_arid[0] = \\<const0> ;
+  assign m_axi_arlen[23] = \\<const0> ;
+  assign m_axi_arlen[22] = \\<const0> ;
+  assign m_axi_arlen[21] = \\<const0> ;
+  assign m_axi_arlen[20] = \\<const0> ;
+  assign m_axi_arlen[19] = \\<const0> ;
+  assign m_axi_arlen[18] = \\<const0> ;
+  assign m_axi_arlen[17] = \\<const0> ;
+  assign m_axi_arlen[16] = \\<const0> ;
+  assign m_axi_arlen[15] = \\<const0> ;
+  assign m_axi_arlen[14] = \\<const0> ;
+  assign m_axi_arlen[13] = \\<const0> ;
+  assign m_axi_arlen[12] = \\<const0> ;
+  assign m_axi_arlen[11] = \\<const0> ;
+  assign m_axi_arlen[10] = \\<const0> ;
+  assign m_axi_arlen[9] = \\<const0> ;
+  assign m_axi_arlen[8] = \\<const0> ;
+  assign m_axi_arlen[7] = \\<const0> ;
+  assign m_axi_arlen[6] = \\<const0> ;
+  assign m_axi_arlen[5] = \\<const0> ;
+  assign m_axi_arlen[4] = \\<const0> ;
+  assign m_axi_arlen[3] = \\<const0> ;
+  assign m_axi_arlen[2] = \\<const0> ;
+  assign m_axi_arlen[1] = \\<const0> ;
+  assign m_axi_arlen[0] = \\<const0> ;
+  assign m_axi_arlock[2] = \\<const0> ;
+  assign m_axi_arlock[1] = \\<const0> ;
+  assign m_axi_arlock[0] = \\<const0> ;
+  assign m_axi_arprot[8:6] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_arqos[11] = \\<const0> ;
+  assign m_axi_arqos[10] = \\<const0> ;
+  assign m_axi_arqos[9] = \\<const0> ;
+  assign m_axi_arqos[8] = \\<const0> ;
+  assign m_axi_arqos[7] = \\<const0> ;
+  assign m_axi_arqos[6] = \\<const0> ;
+  assign m_axi_arqos[5] = \\<const0> ;
+  assign m_axi_arqos[4] = \\<const0> ;
+  assign m_axi_arqos[3] = \\<const0> ;
+  assign m_axi_arqos[2] = \\<const0> ;
+  assign m_axi_arqos[1] = \\<const0> ;
+  assign m_axi_arqos[0] = \\<const0> ;
+  assign m_axi_arregion[11] = \\<const0> ;
+  assign m_axi_arregion[10] = \\<const0> ;
+  assign m_axi_arregion[9] = \\<const0> ;
+  assign m_axi_arregion[8] = \\<const0> ;
+  assign m_axi_arregion[7] = \\<const0> ;
+  assign m_axi_arregion[6] = \\<const0> ;
+  assign m_axi_arregion[5] = \\<const0> ;
+  assign m_axi_arregion[4] = \\<const0> ;
+  assign m_axi_arregion[3] = \\<const0> ;
+  assign m_axi_arregion[2] = \\<const0> ;
+  assign m_axi_arregion[1] = \\<const0> ;
+  assign m_axi_arregion[0] = \\<const0> ;
+  assign m_axi_arsize[8] = \\<const0> ;
+  assign m_axi_arsize[7] = \\<const0> ;
+  assign m_axi_arsize[6] = \\<const0> ;
+  assign m_axi_arsize[5] = \\<const0> ;
+  assign m_axi_arsize[4] = \\<const0> ;
+  assign m_axi_arsize[3] = \\<const0> ;
+  assign m_axi_arsize[2] = \\<const0> ;
+  assign m_axi_arsize[1] = \\<const0> ;
+  assign m_axi_arsize[0] = \\<const0> ;
+  assign m_axi_aruser[2] = \\<const0> ;
+  assign m_axi_aruser[1] = \\<const0> ;
+  assign m_axi_aruser[0] = \\<const0> ;
+  assign m_axi_arvalid[2] = \\<const0> ;
+  assign m_axi_arvalid[1:0] = \\^m_axi_arvalid [1:0];
+  assign m_axi_awaddr[95:80] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[79:64] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[63:48] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[31:16] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_awburst[5] = \\<const0> ;
+  assign m_axi_awburst[4] = \\<const0> ;
+  assign m_axi_awburst[3] = \\<const0> ;
+  assign m_axi_awburst[2] = \\<const0> ;
+  assign m_axi_awburst[1] = \\<const0> ;
+  assign m_axi_awburst[0] = \\<const0> ;
+  assign m_axi_awcache[11] = \\<const0> ;
+  assign m_axi_awcache[10] = \\<const0> ;
+  assign m_axi_awcache[9] = \\<const0> ;
+  assign m_axi_awcache[8] = \\<const0> ;
+  assign m_axi_awcache[7] = \\<const0> ;
+  assign m_axi_awcache[6] = \\<const0> ;
+  assign m_axi_awcache[5] = \\<const0> ;
+  assign m_axi_awcache[4] = \\<const0> ;
+  assign m_axi_awcache[3] = \\<const0> ;
+  assign m_axi_awcache[2] = \\<const0> ;
+  assign m_axi_awcache[1] = \\<const0> ;
+  assign m_axi_awcache[0] = \\<const0> ;
+  assign m_axi_awid[2] = \\<const0> ;
+  assign m_axi_awid[1] = \\<const0> ;
+  assign m_axi_awid[0] = \\<const0> ;
+  assign m_axi_awlen[23] = \\<const0> ;
+  assign m_axi_awlen[22] = \\<const0> ;
+  assign m_axi_awlen[21] = \\<const0> ;
+  assign m_axi_awlen[20] = \\<const0> ;
+  assign m_axi_awlen[19] = \\<const0> ;
+  assign m_axi_awlen[18] = \\<const0> ;
+  assign m_axi_awlen[17] = \\<const0> ;
+  assign m_axi_awlen[16] = \\<const0> ;
+  assign m_axi_awlen[15] = \\<const0> ;
+  assign m_axi_awlen[14] = \\<const0> ;
+  assign m_axi_awlen[13] = \\<const0> ;
+  assign m_axi_awlen[12] = \\<const0> ;
+  assign m_axi_awlen[11] = \\<const0> ;
+  assign m_axi_awlen[10] = \\<const0> ;
+  assign m_axi_awlen[9] = \\<const0> ;
+  assign m_axi_awlen[8] = \\<const0> ;
+  assign m_axi_awlen[7] = \\<const0> ;
+  assign m_axi_awlen[6] = \\<const0> ;
+  assign m_axi_awlen[5] = \\<const0> ;
+  assign m_axi_awlen[4] = \\<const0> ;
+  assign m_axi_awlen[3] = \\<const0> ;
+  assign m_axi_awlen[2] = \\<const0> ;
+  assign m_axi_awlen[1] = \\<const0> ;
+  assign m_axi_awlen[0] = \\<const0> ;
+  assign m_axi_awlock[2] = \\<const0> ;
+  assign m_axi_awlock[1] = \\<const0> ;
+  assign m_axi_awlock[0] = \\<const0> ;
+  assign m_axi_awprot[8:6] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_awqos[11] = \\<const0> ;
+  assign m_axi_awqos[10] = \\<const0> ;
+  assign m_axi_awqos[9] = \\<const0> ;
+  assign m_axi_awqos[8] = \\<const0> ;
+  assign m_axi_awqos[7] = \\<const0> ;
+  assign m_axi_awqos[6] = \\<const0> ;
+  assign m_axi_awqos[5] = \\<const0> ;
+  assign m_axi_awqos[4] = \\<const0> ;
+  assign m_axi_awqos[3] = \\<const0> ;
+  assign m_axi_awqos[2] = \\<const0> ;
+  assign m_axi_awqos[1] = \\<const0> ;
+  assign m_axi_awqos[0] = \\<const0> ;
+  assign m_axi_awregion[11] = \\<const0> ;
+  assign m_axi_awregion[10] = \\<const0> ;
+  assign m_axi_awregion[9] = \\<const0> ;
+  assign m_axi_awregion[8] = \\<const0> ;
+  assign m_axi_awregion[7] = \\<const0> ;
+  assign m_axi_awregion[6] = \\<const0> ;
+  assign m_axi_awregion[5] = \\<const0> ;
+  assign m_axi_awregion[4] = \\<const0> ;
+  assign m_axi_awregion[3] = \\<const0> ;
+  assign m_axi_awregion[2] = \\<const0> ;
+  assign m_axi_awregion[1] = \\<const0> ;
+  assign m_axi_awregion[0] = \\<const0> ;
+  assign m_axi_awsize[8] = \\<const0> ;
+  assign m_axi_awsize[7] = \\<const0> ;
+  assign m_axi_awsize[6] = \\<const0> ;
+  assign m_axi_awsize[5] = \\<const0> ;
+  assign m_axi_awsize[4] = \\<const0> ;
+  assign m_axi_awsize[3] = \\<const0> ;
+  assign m_axi_awsize[2] = \\<const0> ;
+  assign m_axi_awsize[1] = \\<const0> ;
+  assign m_axi_awsize[0] = \\<const0> ;
+  assign m_axi_awuser[2] = \\<const0> ;
+  assign m_axi_awuser[1] = \\<const0> ;
+  assign m_axi_awuser[0] = \\<const0> ;
+  assign m_axi_awvalid[2] = \\<const0> ;
+  assign m_axi_awvalid[1:0] = \\^m_axi_awvalid [1:0];
+  assign m_axi_bready[2] = \\<const0> ;
+  assign m_axi_bready[1:0] = \\^m_axi_bready [1:0];
+  assign m_axi_rready[2] = \\<const0> ;
+  assign m_axi_rready[1:0] = \\^m_axi_rready [1:0];
+  assign m_axi_wdata[95:64] = s_axi_wdata;
+  assign m_axi_wdata[63:32] = s_axi_wdata;
+  assign m_axi_wdata[31:0] = s_axi_wdata;
+  assign m_axi_wid[2] = \\<const0> ;
+  assign m_axi_wid[1] = \\<const0> ;
+  assign m_axi_wid[0] = \\<const0> ;
+  assign m_axi_wlast[2] = \\<const0> ;
+  assign m_axi_wlast[1] = \\<const0> ;
+  assign m_axi_wlast[0] = \\<const0> ;
+  assign m_axi_wstrb[11:8] = s_axi_wstrb;
+  assign m_axi_wstrb[7:4] = s_axi_wstrb;
+  assign m_axi_wstrb[3:0] = s_axi_wstrb;
+  assign m_axi_wuser[2] = \\<const0> ;
+  assign m_axi_wuser[1] = \\<const0> ;
+  assign m_axi_wuser[0] = \\<const0> ;
+  assign m_axi_wvalid[2] = \\<const0> ;
+  assign m_axi_wvalid[1:0] = \\^m_axi_wvalid [1:0];
+  assign s_axi_bid[0] = \\<const0> ;
+  assign s_axi_buser[0] = \\<const0> ;
+  assign s_axi_rid[0] = \\<const0> ;
+  assign s_axi_rlast[0] = \\<const0> ;
+  assign s_axi_ruser[0] = \\<const0> ;
+  GND GND
+       (.G(\\<const0> ));
+  design_1_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd \\gen_sasd.crossbar_sasd_0 
+       (.Q({\\^m_axi_arprot ,\\^m_axi_awaddr ,\\^m_axi_araddr }),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(\\^m_axi_arvalid ),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(\\^m_axi_awvalid ),
+        .m_axi_bready(\\^m_axi_bready ),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(\\^m_axi_rready ),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wvalid(\\^m_axi_wvalid ),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module design_1_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd
+   (Q,
+    \\s_axi_rdata[31] ,
+    s_axi_bvalid,
+    m_axi_bready,
+    s_axi_wready,
+    m_axi_wvalid,
+    m_axi_awvalid,
+    m_axi_arvalid,
+    s_axi_awready,
+    s_axi_arready,
+    s_axi_rvalid,
+    m_axi_rready,
+    s_axi_bresp,
+    s_axi_rready,
+    aresetn,
+    aclk,
+    s_axi_wvalid,
+    s_axi_bready,
+    m_axi_arready,
+    m_axi_awready,
+    m_axi_wready,
+    m_axi_bvalid,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    m_axi_rvalid,
+    m_axi_rresp,
+    m_axi_rdata,
+    m_axi_bresp,
+    s_axi_awvalid);
+  output [34:0]Q;
+  output [33:0]\\s_axi_rdata[31] ;
+  output [0:0]s_axi_bvalid;
+  output [1:0]m_axi_bready;
+  output [0:0]s_axi_wready;
+  output [1:0]m_axi_wvalid;
+  output [1:0]m_axi_awvalid;
+  output [1:0]m_axi_arvalid;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rvalid;
+  output [1:0]m_axi_rready;
+  output [1:0]s_axi_bresp;
+  input [0:0]s_axi_rready;
+  input aresetn;
+  input aclk;
+  input [0:0]s_axi_wvalid;
+  input [0:0]s_axi_bready;
+  input [2:0]m_axi_arready;
+  input [2:0]m_axi_awready;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bvalid;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input [2:0]m_axi_rvalid;
+  input [5:0]m_axi_rresp;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_bresp;
+  input [0:0]s_axi_awvalid;
+
+  wire [34:0]Q;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire addr_arbiter_inst_n_3;
+  wire addr_arbiter_inst_n_42;
+  wire addr_arbiter_inst_n_47;
+  wire addr_arbiter_inst_n_51;
+  wire addr_arbiter_inst_n_52;
+  wire addr_arbiter_inst_n_55;
+  wire addr_arbiter_inst_n_56;
+  wire addr_arbiter_inst_n_60;
+  wire any_error;
+  wire aresetn;
+  wire aresetn_d;
+  wire \\gen_decerr.decerr_slave_inst_n_0 ;
+  wire \\gen_decerr.decerr_slave_inst_n_1 ;
+  wire \\gen_decerr.decerr_slave_inst_n_2 ;
+  wire \\gen_decerr.decerr_slave_inst_n_3 ;
+  wire \\gen_decerr.decerr_slave_inst_n_4 ;
+  wire \\gen_decerr.decerr_slave_inst_n_5 ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc[0]_i_1_n_0 ;
+  wire [3:0]m_atarget_hot;
+  wire [1:0]m_atarget_hot0;
+  wire [2:0]m_axi_arready;
+  wire [1:0]m_axi_arvalid;
+  wire [2:0]m_axi_awready;
+  wire [1:0]m_axi_awvalid;
+  wire [1:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [1:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [1:0]m_axi_wvalid;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire [2:0]m_ready_d_0;
+  wire m_valid_i;
+  wire p_1_in;
+  wire reg_slice_r_n_2;
+  wire reset;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire splitter_aw_n_0;
+  wire sr_rvalid;
+
+  design_1_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd addr_arbiter_inst
+       (.D({addr_arbiter_inst_n_3,m_atarget_hot0}),
+        .E(p_1_in),
+        .Q(Q),
+        .SR(reset),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .any_error(any_error),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_arready_i_reg (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\gen_axilite.s_axi_awready_i_reg (addr_arbiter_inst_n_52),
+        .\\gen_axilite.s_axi_awready_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_2 ),
+        .\\gen_axilite.s_axi_awready_i_reg_1 (\\gen_decerr.decerr_slave_inst_n_1 ),
+        .\\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_47),
+        .\\gen_axilite.s_axi_bvalid_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\gen_axilite.s_axi_rvalid_i_reg (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (addr_arbiter_inst_n_55),
+        .\\m_atarget_hot_reg[1] (m_atarget_hot[1:0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_wvalid(m_axi_wvalid),
+        .m_ready_d(m_ready_d_0),
+        .m_ready_d0(m_ready_d0),
+        .m_ready_d_0(m_ready_d),
+        .\\m_ready_d_reg[1] (\\gen_decerr.decerr_slave_inst_n_0 ),
+        .\\m_ready_d_reg[2] (addr_arbiter_inst_n_42),
+        .\\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_51),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg(reg_slice_r_n_2),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid),
+        .s_ready_i_reg(addr_arbiter_inst_n_56),
+        .s_ready_i_reg_0(addr_arbiter_inst_n_60),
+        .sr_rvalid(sr_rvalid));
+  FDRE #(
+    .INIT(1\'b0)) 
+    aresetn_d_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(aresetn),
+        .Q(aresetn_d),
+        .R(1\'b0));
+  design_1_xbar_0_axi_crossbar_v2_1_12_decerr_slave \\gen_decerr.decerr_slave_inst 
+       (.Q(m_atarget_enc),
+        .SR(reset),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_55),
+        .\\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_47),
+        .\\gen_no_arbiter.grant_rnw_reg_1 (addr_arbiter_inst_n_60),
+        .\\gen_no_arbiter.grant_rnw_reg_2 (addr_arbiter_inst_n_52),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0] (\\gen_decerr.decerr_slave_inst_n_0 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (\\gen_decerr.decerr_slave_inst_n_1 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_1 (\\gen_decerr.decerr_slave_inst_n_2 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_2 (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\m_atarget_hot_reg[3] (m_atarget_hot[3]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_ready_d(m_ready_d_0[2:1]),
+        .m_ready_d_0(m_ready_d[1]),
+        .\\m_ready_d_reg[1] (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\m_ready_d_reg[1]_0 (splitter_aw_n_0),
+        .s_axi_wvalid(s_axi_wvalid),
+        .s_ready_i_reg(\\gen_decerr.decerr_slave_inst_n_5 ));
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\m_atarget_enc[0]_i_1 
+       (.I0(Q[16]),
+        .I1(any_error),
+        .O(\\m_atarget_enc[0]_i_1_n_0 ));
+  FDRE \\m_atarget_enc_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_enc[0]_i_1_n_0 ),
+        .Q(m_atarget_enc[0]),
+        .R(reset));
+  FDRE \\m_atarget_enc_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(any_error),
+        .Q(m_atarget_enc[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_atarget_hot0[0]),
+        .Q(m_atarget_hot[0]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_atarget_hot0[1]),
+        .Q(m_atarget_hot[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_3),
+        .Q(m_atarget_hot[3]),
+        .R(reset));
+  design_1_xbar_0_axi_register_slice_v2_1_11_axic_register_slice reg_slice_r
+       (.E(p_1_in),
+        .Q(m_atarget_hot[1:0]),
+        .SR(reset),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_60),
+        .\\m_atarget_enc_reg[1] (m_atarget_enc),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_ready_d(m_ready_d[0]),
+        .\\m_ready_d_reg[1] (reg_slice_r_n_2),
+        .m_valid_i(m_valid_i),
+        .\\s_axi_rdata[31] (\\s_axi_rdata[31] ),
+        .s_axi_rready(s_axi_rready),
+        .s_ready_i_reg_0(addr_arbiter_inst_n_56),
+        .sr_rvalid(sr_rvalid));
+  LUT5 #(
+    .INIT(32\'hFEF2CEC2)) 
+    \\s_axi_bresp[0]_INST_0 
+       (.I0(m_axi_bresp[0]),
+        .I1(m_atarget_enc[1]),
+        .I2(m_atarget_enc[0]),
+        .I3(m_axi_bresp[4]),
+        .I4(m_axi_bresp[2]),
+        .O(s_axi_bresp[0]));
+  LUT5 #(
+    .INIT(32\'hFEF2CEC2)) 
+    \\s_axi_bresp[1]_INST_0 
+       (.I0(m_axi_bresp[1]),
+        .I1(m_atarget_enc[1]),
+        .I2(m_atarget_enc[0]),
+        .I3(m_axi_bresp[5]),
+        .I4(m_axi_bresp[3]),
+        .O(s_axi_bresp[1]));
+  design_1_xbar_0_axi_crossbar_v2_1_12_splitter__parameterized0 splitter_ar
+       (.aa_grant_rnw(aa_grant_rnw),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_arready_i_reg (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .m_ready_d(m_ready_d),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg(reg_slice_r_n_2));
+  design_1_xbar_0_axi_crossbar_v2_1_12_splitter splitter_aw
+       (.Q(m_atarget_hot[3]),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_bvalid_i_reg (splitter_aw_n_0),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_51),
+        .m_ready_d(m_ready_d_0),
+        .m_ready_d0(m_ready_d0),
+        .\\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_42),
+        .m_valid_i(m_valid_i),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module design_1_xbar_0_axi_crossbar_v2_1_12_decerr_slave
+   (\\gen_no_arbiter.m_grant_hot_i_reg[0] ,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ,
+    \\m_ready_d_reg[1] ,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ,
+    s_ready_i_reg,
+    SR,
+    aclk,
+    s_axi_wvalid,
+    m_ready_d,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    m_axi_arready,
+    Q,
+    m_axi_awready,
+    m_axi_wready,
+    m_axi_bvalid,
+    m_axi_rvalid,
+    \\m_atarget_hot_reg[3] ,
+    \\gen_no_arbiter.grant_rnw_reg_0 ,
+    \\m_ready_d_reg[1]_0 ,
+    m_ready_d_0,
+    \\gen_no_arbiter.grant_rnw_reg_1 ,
+    aa_rready,
+    aresetn_d,
+    \\gen_no_arbiter.grant_rnw_reg_2 );
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0] ;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ;
+  output \\m_ready_d_reg[1] ;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ;
+  output s_ready_i_reg;
+  input [0:0]SR;
+  input aclk;
+  input [0:0]s_axi_wvalid;
+  input [1:0]m_ready_d;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input [2:0]m_axi_arready;
+  input [1:0]Q;
+  input [2:0]m_axi_awready;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bvalid;
+  input [2:0]m_axi_rvalid;
+  input [0:0]\\m_atarget_hot_reg[3] ;
+  input \\gen_no_arbiter.grant_rnw_reg_0 ;
+  input \\m_ready_d_reg[1]_0 ;
+  input [0:0]m_ready_d_0;
+  input \\gen_no_arbiter.grant_rnw_reg_1 ;
+  input aa_rready;
+  input aresetn_d;
+  input \\gen_no_arbiter.grant_rnw_reg_2 ;
+
+  wire [1:0]Q;
+  wire [0:0]SR;
+  wire aa_rready;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_awready_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_bvalid_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg_0 ;
+  wire \\gen_no_arbiter.grant_rnw_reg_1 ;
+  wire \\gen_no_arbiter.grant_rnw_reg_2 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0] ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ;
+  wire [0:0]\\m_atarget_hot_reg[3] ;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_bvalid;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d_0;
+  wire \\m_ready_d_reg[1] ;
+  wire \\m_ready_d_reg[1]_0 ;
+  wire [3:3]mi_arready;
+  wire [3:3]mi_bvalid;
+  wire [3:3]mi_rvalid;
+  wire [3:3]mi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire s_ready_i_reg;
+
+  LUT6 #(
+    .INIT(64\'hAAAAA8AA0000AAAA)) 
+    \\gen_axilite.s_axi_arready_i_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_no_arbiter.grant_rnw_reg_1 ),
+        .I2(m_ready_d_0),
+        .I3(\\m_atarget_hot_reg[3] ),
+        .I4(mi_rvalid),
+        .I5(mi_arready),
+        .O(\\gen_axilite.s_axi_arready_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_arready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_arready_i_i_1_n_0 ),
+        .Q(mi_arready),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFEF00000010)) 
+    \\gen_axilite.s_axi_awready_i_i_1 
+       (.I0(mi_bvalid),
+        .I1(\\gen_no_arbiter.grant_rnw_reg_2 ),
+        .I2(\\m_atarget_hot_reg[3] ),
+        .I3(m_ready_d[1]),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(mi_wready),
+        .O(\\gen_axilite.s_axi_awready_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_awready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_awready_i_i_1_n_0 ),
+        .Q(mi_wready),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h77F07700)) 
+    \\gen_axilite.s_axi_bvalid_i_i_1 
+       (.I0(\\m_atarget_hot_reg[3] ),
+        .I1(\\gen_no_arbiter.grant_rnw_reg_0 ),
+        .I2(mi_wready),
+        .I3(mi_bvalid),
+        .I4(\\m_ready_d_reg[1]_0 ),
+        .O(\\gen_axilite.s_axi_bvalid_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_bvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_bvalid_i_i_1_n_0 ),
+        .Q(mi_bvalid),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h00FFFFFF02020000)) 
+    \\gen_axilite.s_axi_rvalid_i_i_1 
+       (.I0(mi_arready),
+        .I1(m_ready_d_0),
+        .I2(\\gen_no_arbiter.grant_rnw_reg_1 ),
+        .I3(aa_rready),
+        .I4(\\m_atarget_hot_reg[3] ),
+        .I5(mi_rvalid),
+        .O(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_rvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
+        .Q(mi_rvalid),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0F0F0707FFFF07FF)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_4 
+       (.I0(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d[0]),
+        .I3(\\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(m_ready_d[1]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\m_ready_d[1]_i_2 
+       (.I0(mi_arready),
+        .I1(m_axi_arready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_arready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_arready[0]),
+        .O(\\m_ready_d_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\m_ready_d[2]_i_5 
+       (.I0(mi_wready),
+        .I1(m_axi_awready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_awready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_awready[0]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    m_valid_i_i_3
+       (.I0(mi_rvalid),
+        .I1(m_axi_rvalid[1]),
+        .I2(Q[0]),
+        .I3(m_axi_rvalid[2]),
+        .I4(Q[1]),
+        .I5(m_axi_rvalid[0]),
+        .O(s_ready_i_reg));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\s_axi_bvalid[0]_INST_0_i_1 
+       (.I0(mi_bvalid),
+        .I1(m_axi_bvalid[1]),
+        .I2(Q[0]),
+        .I3(m_axi_bvalid[2]),
+        .I4(Q[1]),
+        .I5(m_axi_bvalid[0]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_2 ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\s_axi_wready[0]_INST_0_i_1 
+       (.I0(mi_wready),
+        .I1(m_axi_wready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_wready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_wready[0]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
+endmodule
+
+module design_1_xbar_0_axi_crossbar_v2_1_12_splitter
+   (\\gen_axilite.s_axi_bvalid_i_reg ,
+    m_ready_d,
+    s_axi_wvalid,
+    Q,
+    m_valid_i,
+    aa_grant_rnw,
+    aresetn_d,
+    m_ready_d0,
+    \\m_ready_d_reg[2]_0 ,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    aclk);
+  output \\gen_axilite.s_axi_bvalid_i_reg ;
+  output [2:0]m_ready_d;
+  input [0:0]s_axi_wvalid;
+  input [0:0]Q;
+  input m_valid_i;
+  input aa_grant_rnw;
+  input aresetn_d;
+  input [0:0]m_ready_d0;
+  input \\m_ready_d_reg[2]_0 ;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input aclk;
+
+  wire [0:0]Q;
+  wire aa_grant_rnw;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire [2:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire \\m_ready_d[2]_i_1_n_0 ;
+  wire \\m_ready_d_reg[2]_0 ;
+  wire m_valid_i;
+  wire [0:0]s_axi_wvalid;
+
+  LUT6 #(
+    .INIT(64\'h0000000000200000)) 
+    \\gen_axilite.s_axi_bvalid_i_i_3 
+       (.I0(s_axi_wvalid),
+        .I1(m_ready_d[1]),
+        .I2(Q),
+        .I3(m_ready_d[2]),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg ));
+  LUT4 #(
+    .INIT(16\'h8880)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\m_ready_d_reg[2]_0 ),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT4 #(
+    .INIT(16\'h00A2)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\m_ready_d_reg[2]_0 ),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT4 #(
+    .INIT(16\'h0A02)) 
+    \\m_ready_d[2]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\m_ready_d_reg[2]_0 ),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .O(\\m_ready_d[2]_i_1_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[2]_i_1_n_0 ),
+        .Q(m_ready_d[2]),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_crossbar_v2_1_12_splitter"" *) 
+module design_1_xbar_0_axi_crossbar_v2_1_12_splitter__parameterized0
+   (m_ready_d,
+    aresetn_d,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    m_valid_i,
+    aa_grant_rnw,
+    m_valid_i_reg,
+    aclk);
+  output [1:0]m_ready_d;
+  input aresetn_d;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input m_valid_i;
+  input aa_grant_rnw;
+  input m_valid_i_reg;
+  input aclk;
+
+  wire aa_grant_rnw;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire [1:0]m_ready_d;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire m_valid_i;
+  wire m_valid_i_reg;
+
+  LUT6 #(
+    .INIT(64\'h0000000000002AAA)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(m_ready_d[1]),
+        .I5(m_valid_i_reg),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAA800000000000)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(m_ready_d[1]),
+        .I5(m_valid_i_reg),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+endmodule
+
+module design_1_xbar_0_axi_register_slice_v2_1_11_axic_register_slice
+   (sr_rvalid,
+    aa_rready,
+    'b'\\m_ready_d_reg[1] ,
+    m_axi_rready,
+    \\s_axi_rdata[31] ,
+    aclk,
+    m_ready_d,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    s_axi_rready,
+    s_ready_i_reg_0,
+    aa_grant_rnw,
+    m_valid_i,
+    Q,
+    m_axi_rresp,
+    \\m_atarget_enc_reg[1] ,
+    m_axi_rdata,
+    SR,
+    E);
+  output sr_rvalid;
+  output aa_rready;
+  output \\m_ready_d_reg[1] ;
+  output [1:0]m_axi_rready;
+  output [33:0]\\s_axi_rdata[31] ;
+  input aclk;
+  input [0:0]m_ready_d;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input [0:0]s_axi_rready;
+  input s_ready_i_reg_0;
+  input aa_grant_rnw;
+  input m_valid_i;
+  input [1:0]Q;
+  input [5:0]m_axi_rresp;
+  input [1:0]\\m_atarget_enc_reg[1] ;
+  input [95:0]m_axi_rdata;
+  input [0:0]SR;
+  input [0:0]E;
+
+  wire [0:0]E;
+  wire [1:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire \\aresetn_d_reg_n_0_[0] ;
+  wire \\aresetn_d_reg_n_0_[1] ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire [1:0]\\m_atarget_enc_reg[1] ;
+  wire [95:0]m_axi_rdata;
+  wire [1:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire \\m_payload_i[1]_i_2_n_0 ;
+  wire \\m_payload_i[2]_i_2_n_0 ;
+  wire \\m_payload_i_reg_n_0_[0] ;
+  wire [0:0]m_ready_d;
+  wire \\m_ready_d_reg[1] ;
+  wire m_valid_i;
+  wire m_valid_i_i_1_n_0;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire s_ready_i_i_1_n_0;
+  wire s_ready_i_reg_0;
+  wire [34:0]skid_buffer;
+  wire \\skid_buffer[10]_i_1_n_0 ;
+  wire \\skid_buffer[11]_i_1_n_0 ;
+  wire \\skid_buffer[12]_i_1_n_0 ;
+  wire \\skid_buffer[13]_i_1_n_0 ;
+  wire \\skid_buffer[14]_i_1_n_0 ;
+  wire \\skid_buffer[15]_i_1_n_0 ;
+  wire \\skid_buffer[16]_i_1_n_0 ;
+  wire \\skid_buffer[17]_i_1_n_0 ;
+  wire \\skid_buffer[18]_i_1_n_0 ;
+  wire \\skid_buffer[19]_i_1_n_0 ;
+  wire \\skid_buffer[20]_i_1_n_0 ;
+  wire \\skid_buffer[21]_i_1_n_0 ;
+  wire \\skid_buffer[22]_i_1_n_0 ;
+  wire \\skid_buffer[23]_i_1_n_0 ;
+  wire \\skid_buffer[24]_i_1_n_0 ;
+  wire \\skid_buffer[25]_i_1_n_0 ;
+  wire \\skid_buffer[26]_i_1_n_0 ;
+  wire \\skid_buffer[27]_i_1_n_0 ;
+  wire \\skid_buffer[28]_i_1_n_0 ;
+  wire \\skid_buffer[29]_i_1_n_0 ;
+  wire \\skid_buffer[30]_i_1_n_0 ;
+  wire \\skid_buffer[31]_i_1_n_0 ;
+  wire \\skid_buffer[32]_i_1_n_0 ;
+  wire \\skid_buffer[33]_i_1_n_0 ;
+  wire \\skid_buffer[34]_i_1_n_0 ;
+  wire \\skid_buffer[3]_i_1_n_0 ;
+  wire \\skid_buffer[4]_i_1_n_0 ;
+  wire \\skid_buffer[5]_i_1_n_0 ;
+  wire \\skid_buffer[6]_i_1_n_0 ;
+  wire \\skid_buffer[7]_i_1_n_0 ;
+  wire \\skid_buffer[8]_i_1_n_0 ;
+  wire \\skid_buffer[9]_i_1_n_0 ;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire sr_rvalid;
+
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(1\'b1),
+        .Q(\\aresetn_d_reg_n_0_[0] ),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\aresetn_d_reg_n_0_[0] ),
+        .Q(\\aresetn_d_reg_n_0_[1] ),
+        .R(SR));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[0]_INST_0 
+       (.I0(aa_rready),
+        .I1(Q[0]),
+        .O(m_axi_rready[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[1]_INST_0 
+       (.I0(aa_rready),
+        .I1(Q[1]),
+        .O(m_axi_rready[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1 
+       (.I0(\\skid_buffer[10]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(skid_buffer[10]));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1 
+       (.I0(\\skid_buffer[11]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(skid_buffer[11]));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1 
+       (.I0(\\skid_buffer[12]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(skid_buffer[12]));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1 
+       (.I0(\\skid_buffer[13]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(skid_buffer[13]));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1 
+       (.I0(\\skid_buffer[14]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(skid_buffer[14]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1 
+       (.I0(\\skid_buffer[15]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(skid_buffer[15]));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1 
+       (.I0(\\skid_buffer[16]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(skid_buffer[16]));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1 
+       (.I0(\\skid_buffer[17]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(skid_buffer[17]));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1 
+       (.I0(\\skid_buffer[18]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(skid_buffer[18]));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1 
+       (.I0(\\skid_buffer[19]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(skid_buffer[19]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'h0E)) 
+    \\m_payload_i[1]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[1] ),
+        .I1(aa_rready),
+        .I2(\\m_payload_i[1]_i_2_n_0 ),
+        .O(skid_buffer[1]));
+  LUT6 #(
+    .INIT(64\'h0055330F00000000)) 
+    \\m_payload_i[1]_i_2 
+       (.I0(m_axi_rresp[4]),
+        .I1(m_axi_rresp[2]),
+        .I2(m_axi_rresp[0]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(\\m_atarget_enc_reg[1] [1]),
+        .I5(aa_rready),
+        .O(\\m_payload_i[1]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1 
+       (.I0(\\skid_buffer[20]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(skid_buffer[20]));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1 
+       (.I0(\\skid_buffer[21]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(skid_buffer[21]));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1 
+       (.I0(\\skid_buffer[22]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(skid_buffer[22]));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1 
+       (.I0(\\skid_buffer[23]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(skid_buffer[23]));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1 
+       (.I0(\\skid_buffer[24]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(skid_buffer[24]));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1 
+       (.I0(\\skid_buffer[25]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(skid_buffer[25]));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1 
+       (.I0(\\skid_buffer[26]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(skid_buffer[26]));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1 
+       (.I0(\\skid_buffer[27]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(skid_buffer[27]));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1 
+       (.I0(\\skid_buffer[28]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(skid_buffer[28]));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1 
+       (.I0(\\skid_buffer[29]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(skid_buffer[29]));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'h0E)) 
+    \\m_payload_i[2]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[2] ),
+        .I1(aa_rready),
+        .I2(\\m_payload_i[2]_i_2_n_0 ),
+        .O(skid_buffer[2]));
+  LUT6 #(
+    .INIT(64\'h00220A0000220AAA)) 
+    \\m_payload_i[2]_i_2 
+       (.I0(aa_rready),
+        .I1(m_axi_rresp[5]),
+        .I2(m_axi_rresp[3]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(\\m_atarget_enc_reg[1] [1]),
+        .I5(m_axi_rresp[1]),
+        .O(\\m_payload_i[2]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1 
+       (.I0(\\skid_buffer[30]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(skid_buffer[30]));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_1 
+       (.I0(\\skid_buffer[31]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(skid_buffer[31]));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1 
+       (.I0(\\skid_buffer[32]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(skid_buffer[32]));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1 
+       (.I0(\\skid_buffer[33]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(skid_buffer[33]));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_2 
+       (.I0(\\skid_buffer[34]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(skid_buffer[34]));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1 
+       (.I0(\\skid_buffer[3]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(skid_buffer[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1 
+       (.I0(\\skid_buffer[4]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(skid_buffer[4]));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1 
+       (.I0(\\skid_buffer[5]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(skid_buffer[5]));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1 
+       (.I0(\\skid_buffer[6]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(skid_buffer[6]));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1 
+       (.I0(\\skid_buffer[7]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(skid_buffer[7]));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1 
+       (.I0(\\skid_buffer[8]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(skid_buffer[8]));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1 
+       (.I0(\\skid_buffer[9]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(skid_buffer[9]));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[0]),
+        .Q(\\m_payload_i_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[10]),
+        .Q(\\s_axi_rdata[31] [9]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[11]),
+        .Q(\\s_axi_rdata[31] [10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[12]),
+        .Q(\\s_axi_rdata[31] [11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[13]),
+        .Q(\\s_axi_rdata[31] [12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[14]),
+        .Q(\\s_axi_rdata[31] [13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[15]),
+        .Q(\\s_axi_rdata[31] [14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[16]),
+        .Q(\\s_axi_rdata[31] [15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[17]),
+        .Q(\\s_axi_rdata[31] [16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[18]),
+        .Q(\\s_axi_rdata[31] [17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[19]),
+        .Q(\\s_axi_rdata[31] [18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[1]),
+        .Q(\\s_axi_rdata[31] [0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[20]),
+        .Q(\\s_axi_rdata[31] [19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[21]),
+        .Q(\\s_axi_rdata[31] [20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[22]),
+        .Q(\\s_axi_rdata[31] [21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[23]),
+        .Q(\\s_axi_rdata[31] [22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[24]),
+        .Q(\\s_axi_rdata[31] [23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[25]),
+        .Q(\\s_axi_rdata[31] [24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[26]),
+        .Q(\\s_axi_rdata[31] [25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[27]),
+        .Q(\\s_axi_rdata[31] [26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[28]),
+        .Q(\\s_axi_rdata[31] [27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[29]),
+        .Q(\\s_axi_rdata[31] [28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[2]),
+        .Q(\\s_axi_rdata[31] [1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[30]),
+        .Q(\\s_axi_rdata[31] [29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[31]),
+        .Q(\\s_axi_rdata[31] [30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[32]),
+        .Q(\\s_axi_rdata[31] [31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[33]),
+        .Q(\\s_axi_rdata[31] [32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[34]),
+        .Q(\\s_axi_rdata[31] [33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[3]),
+        .Q(\\s_axi_rdata[31] [2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[4]),
+        .Q(\\s_axi_rdata[31] [3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[5]),
+        .Q(\\s_axi_rdata[31] [4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[6]),
+        .Q(\\s_axi_rdata[31] [5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[7]),
+        .Q(\\s_axi_rdata[31] [6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[8]),
+        .Q(\\s_axi_rdata[31] [7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[9]),
+        .Q(\\s_axi_rdata[31] [8]),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h000000007FFFFFFF)) 
+    \\m_ready_d[1]_i_3 
+       (.I0(sr_rvalid),
+        .I1(\\m_payload_i_reg_n_0_[0] ),
+        .I2(s_axi_rready),
+        .I3(aa_grant_rnw),
+        .I4(m_valid_i),
+        .I5(m_ready_d),
+        .O(\\m_ready_d_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hA2A2A222A2A2A2A2)) 
+    m_valid_i_i_1
+       (.I0(\\aresetn_d_reg_n_0_[1] ),
+        .I1(s_ready_i_reg_0),
+        .I2(sr_rvalid),
+        .I3(m_ready_d),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(s_axi_rready),
+        .O(m_valid_i_i_1_n_0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i_i_1_n_0),
+        .Q(sr_rvalid),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAA222A2222)) 
+    s_ready_i_i_1
+       (.I0(\\aresetn_d_reg_n_0_[0] ),
+        .I1(sr_rvalid),
+        .I2(m_ready_d),
+        .I3(\\gen_no_arbiter.grant_rnw_reg ),
+        .I4(s_axi_rready),
+        .I5(s_ready_i_reg_0),
+        .O(s_ready_i_i_1_n_0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i_i_1_n_0),
+        .Q(aa_rready),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\skid_buffer[0]_i_1 
+       (.I0(aa_rready),
+        .I1(\\skid_buffer_reg_n_0_[0] ),
+        .O(skid_buffer[0]));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[10]_i_1 
+       (.I0(m_axi_rdata[7]),
+        .I1(m_axi_rdata[39]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[71]),
+        .O(\\skid_buffer[10]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[11]_i_1 
+       (.I0(m_axi_rdata[8]),
+        .I1(m_axi_rdata[40]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[72]),
+        .O(\\skid_buffer[11]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[12]_i_1 
+       (.I0(m_axi_rdata[9]),
+        .I1(m_axi_rdata[41]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[73]),
+        .O(\\skid_buffer[12]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[13]_i_1 
+       (.I0(m_axi_rdata[10]),
+        .I1(m_axi_rdata[74]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[42]),
+        .O(\\skid_buffer[13]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[14]_i_1 
+       (.I0(m_axi_rdata[11]),
+        .I1(m_axi_rdata[43]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[75]),
+        .O(\\skid_buffer[14]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[15]_i_1 
+       (.I0(m_axi_rdata[12]),
+        .I1(m_axi_rdata[44]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[76]),
+        .O(\\skid_buffer[15]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[16]_i_1 
+       (.I0(m_axi_rdata[13]),
+        .I1(m_axi_rdata[45]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[77]),
+        .O(\\skid_buffer[16]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[17]_i_1 
+       (.I0(m_axi_rdata[14]),
+        .I1(m_axi_rdata[46]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[78]),
+        .O(\\skid_buffer[17]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[18]_i_1 
+       (.I0(m_axi_rdata[15]),
+        .I1(m_axi_rdata[47]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[79]),
+        .O(\\skid_buffer[18]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[19]_i_1 
+       (.I0(m_axi_rdata[16]),
+        .I1(m_axi_rdata[48]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[80]),
+        .O(\\skid_buffer[19]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[20]_i_1 
+       (.I0(m_axi_rdata[17]),
+        .I1(m_axi_rdata[49]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[81]),
+        .O(\\skid_buffer[20]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[21]_i_1 
+       (.I0(m_axi_rdata[18]),
+        .I1(m_axi_rdata[50]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[82]),
+        .O(\\skid_buffer[21]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[22]_i_1 
+       (.I0(m_axi_rdata[19]),
+        .I1(m_axi_rdata[51]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[83]),
+        .O(\\skid_buffer[22]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[23]_i_1 
+       (.I0(m_axi_rdata[20]),
+        .I1(m_axi_rdata[52]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[84]),
+        .O(\\skid_buffer[23]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0CAF0CA0)) 
+    \\skid_buffer[24]_i_1 
+       (.I0(m_axi_rdata[85]),
+        .I1(m_axi_rdata[53]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[21]),
+        .O(\\skid_buffer[24]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[25]_i_1 
+       (.I0(m_axi_rdata[22]),
+        .I1(m_axi_rdata[54]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[86]),
+        .O(\\skid_buffer[25]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[26]_i_1 
+       (.I0(m_axi_rdata[23]),
+        .I1(m_axi_rdata[55]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[87]),
+        .O(\\skid_buffer[26]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[27]_i_1 
+       (.I0(m_axi_rdata[24]),
+        .I1(m_axi_rdata[56]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[88]),
+        .O(\\skid_buffer[27]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[28]_i_1 
+       (.I0(m_axi_rdata[25]),
+        .I1(m_axi_rdata[89]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[57]),
+        .O(\\skid_buffer[28]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[29]_i_1 
+       (.I0(m_axi_rdata[26]),
+        .I1(m_axi_rdata[58]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[90]),
+        .O(\\skid_buffer[29]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[30]_i_1 
+       (.I0(m_axi_rdata[27]),
+        .I1(m_axi_rdata[59]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[91]),
+        .O(\\skid_buffer[30]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[31]_i_1 
+       (.I0(m_axi_rdata[28]),
+        .I1(m_axi_rdata[60]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[92]),
+        .O(\\skid_buffer[31]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[32]_i_1 
+       (.I0(m_axi_rdata[29]),
+        .I1(m_axi_rdata[61]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[93]),
+        .O(\\skid_buffer[32]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[33]_i_1 
+       (.I0(m_axi_rdata[30]),
+        .I1(m_axi_rdata[62]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[94]),
+        .O(\\skid_buffer[33]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[34]_i_1 
+       (.I0(m_axi_rdata[31]),
+        .I1(m_axi_rdata[63]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[95]),
+        .O(\\skid_buffer[34]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[3]_i_1 
+       (.I0(m_axi_rdata[0]),
+        .I1(m_axi_rdata[32]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[64]),
+        .O(\\skid_buffer[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[4]_i_1 
+       (.I0(m_axi_rdata[1]),
+        .I1(m_axi_rdata[33]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[65]),
+        .O(\\skid_buffer[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[5]_i_1 
+       (.I0(m_axi_rdata[2]),
+        .I1(m_axi_rdata[34]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[66]),
+        .O(\\skid_buffer[5]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[6]_i_1 
+       (.I0(m_axi_rdata[3]),
+        .I1(m_axi_rdata[35]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[67]),
+        .O(\\skid_buffer[6]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0CAF0CA0)) 
+    \\skid_buffer[7]_i_1 
+       (.I0(m_axi_rdata[68]),
+        .I1(m_axi_rdata[36]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[4]),
+        .O(\\skid_buffer[7]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[8]_i_1 
+       (.I0(m_axi_rdata[5]),
+        .I1(m_axi_rdata[37]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[69]),
+        .O(\\skid_buffer[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[9]_i_1 
+       (.I0(m_axi_rdata[6]),
+        .I1(m_axi_rdata[38]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[70]),
+        .O(\\skid_buffer[9]_i_1_n_0 ));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[10]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[11]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[12]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[13]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[14]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[15]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[16]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[17]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[18]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[19]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[20]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[21]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[22]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[23]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[24]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[25]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[26]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[27]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[28]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[29]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[30]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[31]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[32]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[33]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[34]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[3]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[4]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[5]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[6]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[7]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[8]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[9]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module design_1_xbar_0
+   (aclk,
+    aresetn,
+    s_axi_awaddr,
+    s_axi_awprot,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awaddr,
+    m_axi_awprot,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bresp,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_araddr,
+    m_axi_arprot,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rvalid,
+    m_axi_rready);
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLKIF CLK"" *) input aclk;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RSTIF RST"" *) input aresetn;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"" *) input [31:0]s_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"" *) input [2:0]s_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"" *) input [0:0]s_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"" *) output [0:0]s_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WVALID"" *) input [0:0]s_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WREADY"" *) output [0:0]s_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BVALID"" *) output [0:0]s_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BREADY"" *) input [0:0]s_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"" *) input [31:0]s_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"" *) input [2:0]s_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"" *) input [0:0]s_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"" *) output [0:0]s_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RVALID"" *) output [0:0]s_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RREADY"" *) input [0:0]s_axi_rready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]"" *) output [95:0]m_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]"" *) output [8:0]m_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]"" *) output [2:0]m_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]"" *) input [2:0]m_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]"" *) output [95:0]m_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]"" *) output [11:0]m_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]"" *) output [2:0]m_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]"" *) input [2:0]m_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]"" *) input [5:0]m_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]"" *) input [2:0]m_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]"" *) output [2:0]m_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]"" *) output [95:0]m_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]"" *) output [8:0]m_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]"" *) output [2:0]m_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]"" *) input [2:0]m_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]"" *) input [95:0]m_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]"" *) input [5:0]m_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]"" *) input [2:0]m_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]"" *) output [2:0]m_axi_rready;
+
+  wire aclk;
+  wire aresetn;
+  wire [95:0]m_axi_araddr;
+  wire [8:0]m_axi_arprot;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_arvalid;
+  wire [95:0]m_axi_awaddr;
+  wire [8:0]m_axi_awprot;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [95:0]m_axi_wdata;
+  wire [2:0]m_axi_wready;
+  wire [11:0]m_axi_wstrb;
+  wire [2:0]m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+  wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED;
+  wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+  wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+  wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED;
+  wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+  wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+  (* C_AXI_ADDR_WIDTH = ""32"" *) 
+  (* C_AXI_ARUSER_WIDTH = ""1"" *) 
+  (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+  (* C_AXI_BUSER_WIDTH = ""1"" *) 
+  (* C_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_AXI_ID_WIDTH = ""1"" *) 
+  (* C_AXI_PROTOCOL = ""2"" *) 
+  (* C_AXI_RUSER_WIDTH = ""1"" *) 
+  (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+  (* C_AXI_WUSER_WIDTH = ""1"" *) 
+  (* C_CONNECTIVITY_MODE = ""0"" *) 
+  (* C_DEBUG = ""1"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_M_AXI_ADDR_WIDTH = ""96\'b000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000"" *) 
+  (* C_M_AXI_BASE_ADDR = ""192\'b111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+  (* C_M_AXI_READ_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_READ_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_SECURE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* C_M_AXI_WRITE_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_WRITE_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_NUM_ADDR_RANGES = ""1"" *) 
+  (* C_NUM_MASTER_SLOTS = ""3"" *) 
+  (* C_NUM_SLAVE_SLOTS = ""1"" *) 
+  (* C_R_REGISTER = ""1"" *) 
+  (* C_S_AXI_ARB_PRIORITY = ""0"" *) 
+  (* C_S_AXI_BASE_ID = ""0"" *) 
+  (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+  (* C_S_AXI_SINGLE_THREAD = ""1"" *) 
+  (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) 
+  (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+  (* DowngradeIPIdentifiedWarnings = ""yes"" *) 
+  (* P_ADDR_DECODE = ""1"" *) 
+  (* P_AXI3 = ""1"" *) 
+  (* P_AXI4 = ""0"" *) 
+  (* P_AXILITE = ""2"" *) 
+  (* P_AXILITE_SIZE = ""3\'b010"" *) 
+  (* P_FAMILY = ""zynq"" *) 
+  (* P_INCR = ""2\'b01"" *) 
+  (* P_LEN = ""8"" *) 
+  (* P_LOCK = ""1"" *) 
+  (* P_M_AXI_ERR_MODE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_M_AXI_SUPPORTS_READ = ""3\'b111"" *) 
+  (* P_M_AXI_SUPPORTS_WRITE = ""3\'b111"" *) 
+  (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) 
+  (* P_RANGE_CHECK = ""1"" *) 
+  (* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+  (* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+  design_1_xbar_0_axi_crossbar_v2_1_12_axi_crossbar inst
+       (.aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]),
+        .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]),
+        .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]),
+        .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]),
+        .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]),
+        .m_axi_arprot(m_axi_arprot),
+        .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
+        .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]),
+        .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]),
+        .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]),
+        .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]),
+        .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]),
+        .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]),
+        .m_axi_awprot(m_axi_awprot),
+        .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
+        .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]),
+        .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bid({1\'b0,1\'b0,1\'b0}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_buser({1\'b0,1\'b0,1\'b0}),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rid({1\'b0,1\'b0,1\'b0}),
+        .m_axi_rlast({1\'b1,1\'b1,1\'b1}),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_ruser({1\'b0,1\'b0,1\'b0}),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wdata(m_axi_wdata),
+        .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]),
+        .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wstrb(m_axi_wstrb),
+        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst({1\'b0,1\'b0}),
+        .s_axi_arcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arid(1\'b0),
+        .s_axi_arlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arlock(1\'b0),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_aruser(1\'b0),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst({1\'b0,1\'b0}),
+        .s_axi_awcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awid(1\'b0),
+        .s_axi_awlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awlock(1\'b0),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_awuser(1\'b0),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
+        .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wid(1\'b0),
+        .s_axi_wlast(1\'b1),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wuser(1\'b0),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:37:11 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_sim_netlist.v
+// Design      : design_1_axi_gpio_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
+   (GPIO2_DBus_i,
+    GPIO_DBus_i,
+    GPIO_xferAck_i,
+    GPIO_intr,
+    GPIO2_intr,
+    Q,
+    \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 ,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_o,
+    gpio2_io_t,
+    Read_Reg2_In,
+    s_axi_aclk,
+    Read_Reg_In,
+    bus2ip_reset,
+    bus2ip_cs,
+    bus2ip_rnw,
+    gpio_io_i,
+    gpio2_io_i,
+    E,
+    s_axi_wdata,
+    bus2ip_rnw_i_reg,
+    bus2ip_rnw_i_reg_0,
+    bus2ip_rnw_i_reg_1);
+  output [3:0]GPIO2_DBus_i;
+  output [3:0]GPIO_DBus_i;
+  output GPIO_xferAck_i;
+  output GPIO_intr;
+  output GPIO2_intr;
+  output [3:0]Q;
+  output [3:0]\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 ;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  output [3:0]gpio2_io_o;
+  output [3:0]gpio2_io_t;
+  input [0:3]Read_Reg2_In;
+  input s_axi_aclk;
+  input [0:3]Read_Reg_In;
+  input bus2ip_reset;
+  input [0:0]bus2ip_cs;
+  input bus2ip_rnw;
+  input [3:0]gpio_io_i;
+  input [3:0]gpio2_io_i;
+  input [0:0]E;
+  input [3:0]s_axi_wdata;
+  input [0:0]bus2ip_rnw_i_reg;
+  input [0:0]bus2ip_rnw_i_reg_0;
+  input [0:0]bus2ip_rnw_i_reg_1;
+
+  wire [3:0]\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 ;
+  wire \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0] ;
+  wire \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[3] ;
+  wire \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[0] ;
+  wire \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[3] ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire GPIO2_intr;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_intr;
+  wire GPIO_xferAck_i;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire [0:0]bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [0:0]bus2ip_rnw_i_reg;
+  wire [0:0]bus2ip_rnw_i_reg_0;
+  wire [0:0]bus2ip_rnw_i_reg_1;
+  wire [0:3]gpio2_data_in_xor;
+  wire [3:0]gpio2_io_i;
+  wire [0:3]gpio2_io_i_d2;
+  wire [3:0]gpio2_io_o;
+  wire [3:0]gpio2_io_t;
+  wire [0:3]gpio_data_in_xor;
+  wire [3:0]gpio_io_i;
+  wire [0:3]gpio_io_i_d2;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire iGPIO_xferAck;
+  wire or_ints;
+  wire or_ints2;
+  wire p_0_in;
+  wire p_0_in2_in;
+  wire p_1_in;
+  wire p_1_in3_in;
+  wire s_axi_aclk;
+  wire [3:0]s_axi_wdata;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \\Dual.INPUT_DOUBLE_REGS4 
+       (.D({gpio_data_in_xor[0],gpio_data_in_xor[1],gpio_data_in_xor[2],gpio_data_in_xor[3]}),
+        .Q(Q),
+        .gpio_io_i(gpio_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \\Dual.INPUT_DOUBLE_REGS5 
+       (.D({gpio2_data_in_xor[0],gpio2_data_in_xor[1],gpio2_data_in_xor[2],gpio2_data_in_xor[3]}),
+        .\\Dual.gpio2_Data_In_reg[0] (\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 ),
+        .gpio2_io_i(gpio2_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3]}));
+  FDRE \\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[0]),
+        .Q(GPIO2_DBus_i[3]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[1]),
+        .Q(GPIO2_DBus_i[2]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[2]),
+        .Q(GPIO2_DBus_i[1]),
+        .R(Read_Reg_Rst));
+  LUT4 #(
+    .INIT(16\'hEFFF)) 
+    \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_1 
+       (.I0(gpio_xferAck_Reg),
+        .I1(GPIO_xferAck_i),
+        .I2(bus2ip_rnw),
+        .I3(bus2ip_cs),
+        .O(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[3]),
+        .Q(GPIO2_DBus_i[0]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[0]),
+        .Q(GPIO_DBus_i[3]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[1]),
+        .Q(GPIO_DBus_i[2]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[2]),
+        .Q(GPIO_DBus_i[1]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[3]),
+        .Q(GPIO_DBus_i[0]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.gen_interrupt_dual.GPIO2_intr_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(or_ints2),
+        .Q(GPIO2_intr),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.GPIO_intr_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(or_ints),
+        .Q(GPIO_intr),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_data_in_xor[0]),
+        .Q(\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0] ),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_data_in_xor[1]),
+        .Q(p_0_in),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_data_in_xor[2]),
+        .Q(p_1_in),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_data_in_xor[3]),
+        .Q(\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[3] ),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[0]),
+        .Q(\\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[0] ),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[1]),
+        .Q(p_0_in2_in),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[2]),
+        .Q(p_1_in3_in),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_data_in_xor[3]),
+        .Q(\\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[3] ),
+        .R(bus2ip_reset));
+  FDRE \\Dual.gpio2_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[0]),
+        .Q(\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 [3]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[1]),
+        .Q(\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 [2]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[2]),
+        .Q(\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 [1]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[3]),
+        .Q(\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 [0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[3]),
+        .Q(gpio2_io_o[3]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[2]),
+        .Q(gpio2_io_o[2]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[1]),
+        .Q(gpio2_io_o[1]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[0]),
+        .Q(gpio2_io_o[0]),
+        .R(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[3]),
+        .Q(gpio2_io_t[3]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[2]),
+        .Q(gpio2_io_t[2]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[1]),
+        .Q(gpio2_io_t[1]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[0]),
+        .Q(gpio2_io_t[0]),
+        .S(bus2ip_reset));
+  FDRE \\Dual.gpio_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[0]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[1]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[2]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[3]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[3]),
+        .Q(gpio_io_o[3]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[2]),
+        .Q(gpio_io_o[2]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[1]),
+        .Q(gpio_io_o[1]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[0]),
+        .Q(gpio_io_o[0]),
+        .R(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[3]),
+        .Q(gpio_io_t[3]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[2]),
+        .Q(gpio_io_t[2]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[1]),
+        .Q(gpio_io_t[1]),
+        .S(bus2ip_reset));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[0]),
+        .Q(gpio_io_t[0]),
+        .S(bus2ip_reset));
+  FDRE gpio_xferAck_Reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_xferAck_i),
+        .Q(gpio_xferAck_Reg),
+        .R(bus2ip_reset));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    iGPIO_xferAck_i_1
+       (.I0(gpio_xferAck_Reg),
+        .I1(bus2ip_cs),
+        .I2(GPIO_xferAck_i),
+        .O(iGPIO_xferAck));
+  FDRE iGPIO_xferAck_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(iGPIO_xferAck),
+        .Q(GPIO_xferAck_i),
+        .R(bus2ip_reset));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    or_reduce
+       (.I0(p_0_in2_in),
+        .I1(p_1_in3_in),
+        .I2(\\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[0] ),
+        .I3(\\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[3] ),
+        .O(or_ints));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\or_reduce_inferred__0/i_ 
+       (.I0(p_0_in),
+        .I1(p_1_in),
+        .I2(\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0] ),
+        .I3(\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[3] ),
+        .O(or_ints2));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
+   (\\ip2bus_data_i_D1_reg[0] ,
+    \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ,
+    ipif_glbl_irpt_enable_reg_reg,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    intr2bus_rdack0,
+    irpt_rdack,
+    irpt_wrack,
+    interrupt_wrce_strb,
+    \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
+    intr_rd_ce_or_reduce,
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
+    intr_wr_ce_or_reduce,
+    ipif_glbl_irpt_enable_reg_reg_0,
+    start2,
+    s_axi_aclk,
+    s_axi_aresetn,
+    Q,
+    is_read,
+    ip2bus_rdack_i_D1,
+    is_write_reg,
+    ip2bus_wrack_i_D1,
+    gpio2_io_t,
+    \\Dual.gpio2_Data_In_reg[0] ,
+    \\bus2ip_addr_i_reg[8] ,
+    bus2ip_rnw_i_reg,
+    bus2ip_reset,
+    GPIO_DBus_i,
+    GPIO2_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    ipif_glbl_irpt_enable_reg,
+    irpt_rdack_d1,
+    irpt_wrack_d1,
+    p_1_in,
+    \\ip_irpt_enable_reg_reg[1] ,
+    \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
+    \\ip_irpt_enable_reg_reg[0] ,
+    ip2Bus_RdAck_intr_reg_hole_d1,
+    ip2Bus_WrAck_intr_reg_hole_d1,
+    s_axi_wdata);
+  output \\ip2bus_data_i_D1_reg[0] ;
+  output \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ;
+  output ipif_glbl_irpt_enable_reg_reg;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [4:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output intr2bus_rdack0;
+  output irpt_rdack;
+  output irpt_wrack;
+  output interrupt_wrce_strb;
+  output \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
+  output \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  output intr_rd_ce_or_reduce;
+  output \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  output intr_wr_ce_or_reduce;
+  output ipif_glbl_irpt_enable_reg_reg_0;
+  input start2;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [3:0]Q;
+  input is_read;
+  input ip2bus_rdack_i_D1;
+  input is_write_reg;
+  input ip2bus_wrack_i_D1;
+  input [3:0]gpio2_io_t;
+  input [3:0]\\Dual.gpio2_Data_In_reg[0] ;
+  input [6:0]\\bus2ip_addr_i_reg[8] ;
+  input bus2ip_rnw_i_reg;
+  input bus2ip_reset;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input ipif_glbl_irpt_enable_reg;
+  input irpt_rdack_d1;
+  input irpt_wrack_d1;
+  input p_1_in;
+  input \\ip_irpt_enable_reg_reg[1] ;
+  input \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
+  input \\ip_irpt_enable_reg_reg[0] ;
+  input ip2Bus_RdAck_intr_reg_hole_d1;
+  input ip2Bus_WrAck_intr_reg_hole_d1;
+  input [0:0]s_axi_wdata;
+
+  wire Bus_RNW_reg_i_1_n_0;
+  wire [4:0]D;
+  wire \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ;
+  wire [3:0]\\Dual.gpio2_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ;
+  wire \\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
+  wire \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
+  wire \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire [6:0]\\bus2ip_addr_i_reg[8] ;
+  wire bus2ip_reset;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack0;
+  wire intr_rd_ce_or_reduce;
+  wire intr_wr_ce_or_reduce;
+  wire ip2Bus_RdAck_intr_reg_hole_d1;
+  wire ip2Bus_WrAck_intr_reg_hole_d1;
+  wire \\ip2bus_data_i_D1[30]_i_2_n_0 ;
+  wire \\ip2bus_data_i_D1[30]_i_3_n_0 ;
+  wire \\ip2bus_data_i_D1[31]_i_2_n_0 ;
+  wire \\ip2bus_data_i_D1_reg[0] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire \\ip_irpt_enable_reg_reg[0] ;
+  wire \\ip_irpt_enable_reg_reg[1] ;
+  wire ipif_glbl_irpt_enable_reg;
+  wire ipif_glbl_irpt_enable_reg_reg;
+  wire ipif_glbl_irpt_enable_reg_reg_0;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire is_read;
+  wire is_write_reg;
+  wire p_10_in;
+  wire p_10_out;
+  wire p_11_in;
+  wire p_11_out;
+  wire p_12_in;
+  wire p_12_out;
+  wire p_13_in;
+  wire p_13_out;
+  wire p_14_in;
+  wire p_14_out;
+  wire p_15_in;
+  wire p_15_out;
+  wire p_16_in;
+  wire p_1_in;
+  wire p_2_in;
+  wire p_3_in;
+  wire p_4_in;
+  wire p_4_out;
+  wire p_5_in;
+  wire p_5_out;
+  wire p_6_out;
+  wire p_7_in;
+  wire p_7_out;
+  wire p_8_in;
+  wire p_8_out;
+  wire p_9_in;
+  wire p_9_out;
+  wire pselect_hit_i_1;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire [0:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire start2;
+
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    Bus_RNW_reg_i_1
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(start2),
+        .I2(ipif_glbl_irpt_enable_reg_reg),
+        .O(Bus_RNW_reg_i_1_n_0));
+  FDRE Bus_RNW_reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_i_1_n_0),
+        .Q(ipif_glbl_irpt_enable_reg_reg),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[28]_i_1 
+       (.I0(gpio2_io_t[3]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[0]));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[29]_i_1 
+       (.I0(gpio2_io_t[2]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[1]));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[30]_i_1 
+       (.I0(gpio2_io_t[1]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[2]));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_2 
+       (.I0(gpio2_io_t[0]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[3]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1 
+       (.I0(gpio_io_t[3]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [6]),
+        .I4(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[0]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1 
+       (.I0(gpio_io_t[2]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [6]),
+        .I4(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[1]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1 
+       (.I0(gpio_io_t[1]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [6]),
+        .I4(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[2]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1 
+       (.I0(gpio_io_t[0]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [6]),
+        .I4(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[3]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00001000)) 
+    \\Dual.gpio2_Data_Out[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(bus2ip_reset),
+        .O(\\Dual.gpio2_Data_Out_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF10000000)) 
+    \\Dual.gpio2_OE[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(bus2ip_reset),
+        .O(E));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00000100)) 
+    \\Dual.gpio_Data_Out[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(bus2ip_reset),
+        .O(\\Dual.gpio_Data_Out_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00040000)) 
+    \\Dual.gpio_OE[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [6]),
+        .I4(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I5(bus2ip_reset),
+        .O(\\Dual.gpio_OE_reg[0] ));
+  LUT6 #(
+    .INIT(64\'h0040000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_9_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_9_out),
+        .Q(p_10_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h4000000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_8_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_8_out),
+        .Q(p_9_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0004000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_7_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_7_out),
+        .Q(p_8_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0400000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_6_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_6_out),
+        .Q(p_7_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0008000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_5_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_5_out),
+        .Q(\\ip2bus_data_i_D1_reg[0] ),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0800000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_4_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_4_out),
+        .Q(p_5_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0008000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ),
+        .Q(p_4_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0800000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(\\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(\\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ),
+        .Q(p_3_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0080000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(\\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(\\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ),
+        .Q(p_2_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT3 #(
+    .INIT(8\'hFD)) 
+    \\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1 
+       (.I0(s_axi_aresetn),
+        .I1(s_axi_arready),
+        .I2(s_axi_wready),
+        .O(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h8000000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_15_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_15_out),
+        .Q(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0001000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(\\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(\\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
+        .Q(p_16_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0100000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_14_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_14_out),
+        .Q(p_15_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0002000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_13_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_13_out),
+        .Q(p_14_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0200000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_12_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_12_out),
+        .Q(p_13_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0004000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_11_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_11_out),
+        .Q(p_12_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0400000000000000)) 
+    \\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [6]),
+        .I5(start2),
+        .O(p_10_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(p_10_out),
+        .Q(p_11_in),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'hEF)) 
+    \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2 
+       (.I0(ipif_glbl_irpt_enable_reg_reg),
+        .I1(irpt_wrack_d1),
+        .I2(p_8_in),
+        .O(\\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT4 #(
+    .INIT(16\'hFE00)) 
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1 
+       (.I0(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
+        .I1(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
+        .I2(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
+        .I3(ipif_glbl_irpt_enable_reg_reg),
+        .O(intr_rd_ce_or_reduce));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'h00FE0000)) 
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1 
+       (.I0(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
+        .I1(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
+        .I2(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
+        .I3(ip2Bus_RdAck_intr_reg_hole_d1),
+        .I4(ipif_glbl_irpt_enable_reg_reg),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT4 #(
+    .INIT(16\'h00FE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1 
+       (.I0(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
+        .I1(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
+        .I2(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
+        .I3(ipif_glbl_irpt_enable_reg_reg),
+        .O(intr_wr_ce_or_reduce));
+  LUT5 #(
+    .INIT(32\'hFFFFFFFE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2 
+       (.I0(p_16_in),
+        .I1(p_2_in),
+        .I2(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
+        .I3(p_14_in),
+        .I4(p_15_in),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3 
+       (.I0(p_12_in),
+        .I1(p_13_in),
+        .I2(p_10_in),
+        .I3(p_11_in),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4 
+       (.I0(p_5_in),
+        .I1(p_7_in),
+        .I2(p_3_in),
+        .I3(p_4_in),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h000000FE)) 
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1 
+       (.I0(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
+        .I1(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
+        .I2(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
+        .I3(ipif_glbl_irpt_enable_reg_reg),
+        .I4(ip2Bus_WrAck_intr_reg_hole_d1),
+        .O(\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ));
+  LUT6 #(
+    .INIT(64\'h0000000000000002)) 
+    \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1 
+       (.I0(start2),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\bus2ip_addr_i_reg[8] [4]),
+        .I3(\\bus2ip_addr_i_reg[8] [5]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .I5(\\bus2ip_addr_i_reg[8] [2]),
+        .O(pselect_hit_i_1));
+  FDRE \\MEM_DECODE_GEN[0].cs_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(start2),
+        .D(pselect_hit_i_1),
+        .Q(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .R(\\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h44444440)) 
+    intr2bus_rdack_i_1
+       (.I0(irpt_rdack_d1),
+        .I1(ipif_glbl_irpt_enable_reg_reg),
+        .I2(p_9_in),
+        .I3(p_8_in),
+        .I4(\\ip2bus_data_i_D1_reg[0] ),
+        .O(intr2bus_rdack0));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h000000FE)) 
+    intr2bus_wrack_i_1
+       (.I0(p_9_in),
+        .I1(p_8_in),
+        .I2(\\ip2bus_data_i_D1_reg[0] ),
+        .I3(ipif_glbl_irpt_enable_reg_reg),
+        .I4(irpt_wrack_d1),
+        .O(interrupt_wrce_strb));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00000080)) 
+    \\ip2bus_data_i_D1[0]_i_1 
+       (.I0(ipif_glbl_irpt_enable_reg),
+        .I1(p_9_in),
+        .I2(ipif_glbl_irpt_enable_reg_reg),
+        .I3(\\ip2bus_data_i_D1_reg[0] ),
+        .I4(p_8_in),
+        .O(D[4]));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[28]_i_1 
+       (.I0(GPIO2_DBus_i[3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[3]),
+        .O(D[3]));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[29]_i_1 
+       (.I0(GPIO2_DBus_i[2]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[2]),
+        .O(D[2]));
+  LUT4 #(
+    .INIT(16\'hFEAE)) 
+    \\ip2bus_data_i_D1[30]_i_1 
+       (.I0(\\ip2bus_data_i_D1[30]_i_2_n_0 ),
+        .I1(GPIO_DBus_i[1]),
+        .I2(\\ip2bus_data_i_D1[30]_i_3_n_0 ),
+        .I3(GPIO2_DBus_i[1]),
+        .O(D[1]));
+  LUT5 #(
+    .INIT(32\'hAA00C000)) 
+    \\ip2bus_data_i_D1[30]_i_2 
+       (.I0(p_1_in),
+        .I1(\\ip2bus_data_i_D1_reg[0] ),
+        .I2(\\ip_irpt_enable_reg_reg[1] ),
+        .I3(ipif_glbl_irpt_enable_reg_reg),
+        .I4(p_8_in),
+        .O(\\ip2bus_data_i_D1[30]_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hEFFF)) 
+    \\ip2bus_data_i_D1[30]_i_3 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .I3(bus2ip_rnw_i_reg),
+        .O(\\ip2bus_data_i_D1[30]_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFEAE)) 
+    \\ip2bus_data_i_D1[31]_i_1 
+       (.I0(\\ip2bus_data_i_D1[31]_i_2_n_0 ),
+        .I1(GPIO_DBus_i[0]),
+        .I2(\\ip2bus_data_i_D1[30]_i_3_n_0 ),
+        .I3(GPIO2_DBus_i[0]),
+        .O(D[0]));
+  LUT5 #(
+    .INIT(32\'hAA00C000)) 
+    \\ip2bus_data_i_D1[31]_i_2 
+       (.I0(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ),
+        .I1(\\ip2bus_data_i_D1_reg[0] ),
+        .I2(\\ip_irpt_enable_reg_reg[0] ),
+        .I3(ipif_glbl_irpt_enable_reg_reg),
+        .I4(p_8_in),
+        .O(\\ip2bus_data_i_D1[31]_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    ipif_glbl_irpt_enable_reg_i_1
+       (.I0(s_axi_wdata),
+        .I1(p_9_in),
+        .I2(ipif_glbl_irpt_enable_reg_reg),
+        .I3(ipif_glbl_irpt_enable_reg),
+        .O(ipif_glbl_irpt_enable_reg_reg_0));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT4 #(
+    .INIT(16\'hFE00)) 
+    irpt_rdack_d1_i_1
+       (.I0(p_9_in),
+        .I1(p_8_in),
+        .I2(\\ip2bus_data_i_D1_reg[0] ),
+        .I3(ipif_glbl_irpt_enable_reg_reg),
+        .O(irpt_rdack));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h00FE)) 
+    irpt_wrack_d1_i_1
+       (.I0(p_9_in),
+        .I1(p_8_in),
+        .I2(\\ip2bus_data_i_D1_reg[0] ),
+        .I3(ipif_glbl_irpt_enable_reg_reg),
+        .O(irpt_wrack));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00020000)) 
+    s_axi_arready_INST_0
+       (.I0(Q[3]),
+        .I1(Q[2]),
+        .I2(Q[1]),
+        .I3(Q[0]),
+        .I4(is_read),
+        .I5(ip2bus_rdack_i_D1),
+        .O(s_axi_arready));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00020000)) 
+    s_axi_wready_INST_0
+       (.I0(Q[3]),
+        .I1(Q[2]),
+        .I2(Q[1]),
+        .I3(Q[0]),
+        .I4(is_write_reg),
+        .I5(ip2bus_wrack_i_D1),
+        .O(s_axi_wready));
+endmodule
+
+(* C_ALL_INPUTS = ""1"" *) (* C_ALL_INPUTS_2 = ""1"" *) (* C_ALL_OUTPUTS = ""0"" *) 
+(* C_ALL_OUTPUTS_2 = ""0"" *) (* C_DOUT_DEFAULT = ""0"" *) (* C_DOUT_DEFAULT_2 = ""0"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_GPIO2_WIDTH = ""4"" *) (* C_GPIO_WIDTH = ""4"" *) 
+(* C_INTERRUPT_PRESENT = ""1"" *) (* C_IS_DUAL = ""1"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* C_TRI_DEFAULT = ""-1"" *) (* C_TRI_DEFAULT_2 = ""-1"" *) 
+(* downgradeipidentifiedwarnings = ""yes"" *) (* ip_group = ""LOGICORE"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_i,
+    gpio2_io_o,
+    gpio2_io_t);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rst"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* sigis = ""INTR_LEVEL_HIGH"" *) output ip2intc_irpt;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  input [3:0]gpio2_io_i;
+  output [3:0]gpio2_io_o;
+  output [3:0]gpio2_io_t;
+
+  wire \\<const0> ;
+  wire AXI_LITE_IPIF_I_n_12;
+  wire AXI_LITE_IPIF_I_n_13;
+  wire AXI_LITE_IPIF_I_n_23;
+  wire AXI_LITE_IPIF_I_n_24;
+  wire AXI_LITE_IPIF_I_n_29;
+  wire AXI_LITE_IPIF_I_n_30;
+  wire AXI_LITE_IPIF_I_n_32;
+  wire AXI_LITE_IPIF_I_n_34;
+  wire [28:31]GPIO2_DBus_i;
+  wire GPIO2_intr;
+  wire [28:31]GPIO_DBus_i;
+  wire GPIO_intr;
+  wire GPIO_xferAck_i;
+  wire \\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1 ;
+  wire \\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_6 ;
+  wire \\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_7 ;
+  wire IP2INTC_Irpt_i;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/p_6_in ;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire [1:1]bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_reset_i_1_n_0;
+  wire bus2ip_rnw;
+  wire [0:3]gpio2_Data_In;
+  wire [3:0]gpio2_io_i;
+  wire [3:0]gpio2_io_o;
+  wire [3:0]gpio2_io_t;
+  wire [0:3]gpio_Data_In;
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack0;
+  wire intr_rd_ce_or_reduce;
+  wire intr_wr_ce_or_reduce;
+  wire ip2Bus_RdAck_intr_reg_hole;
+  wire ip2Bus_RdAck_intr_reg_hole_d1;
+  wire ip2Bus_WrAck_intr_reg_hole;
+  wire ip2Bus_WrAck_intr_reg_hole_d1;
+  wire [28:29]ip2bus_data;
+  wire [30:31]ip2bus_data_i;
+  wire [0:31]ip2bus_data_i_D1;
+  wire ip2bus_rdack_i;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i;
+  wire ip2bus_wrack_i_D1;
+  wire ip2intc_irpt;
+  wire ipif_glbl_irpt_enable_reg;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire [0:0]p_0_out;
+  wire p_1_in;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rst"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [31:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\<const0> ;
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\^s_axi_rdata [31];
+  assign s_axi_rdata[30] = \\<const0> ;
+  assign s_axi_rdata[29] = \\<const0> ;
+  assign s_axi_rdata[28] = \\<const0> ;
+  assign s_axi_rdata[27] = \\<const0> ;
+  assign s_axi_rdata[26] = \\<const0> ;
+  assign s_axi_rdata[25] = \\<const0> ;
+  assign s_axi_rdata[24] = \\<const0> ;
+  assign s_axi_rdata[23] = \\<const0> ;
+  assign s_axi_rdata[22] = \\<const0> ;
+  assign s_axi_rdata[21] = \\<const0> ;
+  assign s_axi_rdata[20] = \\<const0> ;
+  assign s_axi_rdata[19] = \\<const0> ;
+  assign s_axi_rdata[18] = \\<const0> ;
+  assign s_axi_rdata[17] = \\<const0> ;
+  assign s_axi_rdata[16] = \\<const0> ;
+  assign s_axi_rdata[15] = \\<const0> ;
+  assign s_axi_rdata[14] = \\<const0> ;
+  assign s_axi_rdata[13] = \\<const0> ;
+  assign s_axi_rdata[12] = \\<const0> ;
+  assign s_axi_rdata[11] = \\<const0> ;
+  assign s_axi_rdata[10] = \\<const0> ;
+  assign s_axi_rdata[9] = \\<const0> ;
+  assign s_axi_rdata[8] = \\<const0> ;
+  assign s_axi_rdata[7] = \\<const0> ;
+  assign s_axi_rdata[6] = \\<const0> ;
+  assign s_axi_rdata[5] = \\<const0> ;
+  assign s_axi_rdata[4] = \\<const0> ;
+  assign s_axi_rdata[3:0] = \\^s_axi_rdata [3:0];
+  assign s_axi_rresp[1] = \\<const0> ;
+  assign s_axi_rresp[0] = \\<const0> ;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
+       (.Bus_RNW_reg(\\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+        .D({p_0_out,ip2bus_data[28],ip2bus_data[29],ip2bus_data_i[30],ip2bus_data_i[31]}),
+        .\\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_13),
+        .\\Dual.gpio_Data_In_reg[0] ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .\\Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_24),
+        .\\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_23),
+        .E(AXI_LITE_IPIF_I_n_12),
+        .\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1 ),
+        .\\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (AXI_LITE_IPIF_I_n_29),
+        .GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
+        .GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
+        .\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_30),
+        .\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_32),
+        .Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .interrupt_wrce_strb(interrupt_wrce_strb),
+        .intr2bus_rdack0(intr2bus_rdack0),
+        .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
+        .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
+        .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
+        .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
+        .\\ip2bus_data_i_D1_reg[0] ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .\\ip_irpt_enable_reg_reg[0] (\\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_7 ),
+        .\\ip_irpt_enable_reg_reg[1] (\\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_6 ),
+        .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
+        .ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_34),
+        .irpt_rdack(irpt_rdack),
+        .irpt_rdack_d1(irpt_rdack_d1),
+        .irpt_wrack(irpt_wrack),
+        .irpt_wrack_d1(irpt_wrack_d1),
+        .p_1_in(p_1_in),
+        .p_6_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_6_in ),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr[8:2]),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr[8:2]),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata({\\^s_axi_rdata [31],\\^s_axi_rdata [3:0]}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata[31]),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control \\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I 
+       (.Bus_RNW_reg(\\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+        .Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_29),
+        .\\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_34),
+        .\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (\\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1 ),
+        .GPIO2_intr(GPIO2_intr),
+        .GPIO_intr(GPIO_intr),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .IP2INTC_Irpt_i(IP2INTC_Irpt_i),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .interrupt_wrce_strb(interrupt_wrce_strb),
+        .intr2bus_rdack0(intr2bus_rdack0),
+        .ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole),
+        .ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole),
+        .ip2bus_rdack_i(ip2bus_rdack_i),
+        .ip2bus_wrack_i(ip2bus_wrack_i),
+        .\\ip_irpt_enable_reg_reg[0]_0 (\\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_7 ),
+        .\\ip_irpt_enable_reg_reg[1]_0 (\\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_6 ),
+        .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
+        .irpt_rdack(irpt_rdack),
+        .irpt_rdack_d1(irpt_rdack_d1),
+        .irpt_wrack(irpt_wrack),
+        .irpt_wrack_d1(irpt_wrack_d1),
+        .p_1_in(p_1_in),
+        .p_6_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_6_in ),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_wdata(s_axi_wdata[1:0]));
+  FDRE \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(intr_rd_ce_or_reduce),
+        .Q(ip2Bus_RdAck_intr_reg_hole_d1),
+        .R(bus2ip_reset));
+  FDRE \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(AXI_LITE_IPIF_I_n_30),
+        .Q(ip2Bus_RdAck_intr_reg_hole),
+        .R(bus2ip_reset));
+  FDRE \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(intr_wr_ce_or_reduce),
+        .Q(ip2Bus_WrAck_intr_reg_hole_d1),
+        .R(bus2ip_reset));
+  FDRE \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(AXI_LITE_IPIF_I_n_32),
+        .Q(ip2Bus_WrAck_intr_reg_hole),
+        .R(bus2ip_reset));
+  (* sigis = ""INTR_LEVEL_HIGH"" *) 
+  FDRE \\INTR_CTRLR_GEN.ip2intc_irpt_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(IP2INTC_Irpt_i),
+        .Q(ip2intc_irpt),
+        .R(bus2ip_reset));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    bus2ip_reset_i_1
+       (.I0(s_axi_aresetn),
+        .O(bus2ip_reset_i_1_n_0));
+  FDRE bus2ip_reset_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(bus2ip_reset_i_1_n_0),
+        .Q(bus2ip_reset),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
+       (.\\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0 ({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
+        .E(AXI_LITE_IPIF_I_n_24),
+        .GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
+        .GPIO2_intr(GPIO2_intr),
+        .GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
+        .GPIO_intr(GPIO_intr),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_23),
+        .bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_13),
+        .bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_12),
+        .gpio2_io_i(gpio2_io_i),
+        .gpio2_io_o(gpio2_io_o),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_wdata(s_axi_wdata[3:0]));
+  FDRE \\ip2bus_data_i_D1_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out),
+        .Q(ip2bus_data_i_D1[0]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[28]),
+        .Q(ip2bus_data_i_D1[28]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[29]),
+        .Q(ip2bus_data_i_D1[29]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data_i[30]),
+        .Q(ip2bus_data_i_D1[30]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data_i[31]),
+        .Q(ip2bus_data_i_D1[31]),
+        .R(bus2ip_reset));
+  FDRE ip2bus_rdack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_i),
+        .Q(ip2bus_rdack_i_D1),
+        .R(bus2ip_reset));
+  FDRE ip2bus_wrack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_wrack_i),
+        .Q(ip2bus_wrack_i_D1),
+        .R(bus2ip_reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
+   (p_6_in,
+    bus2ip_rnw,
+    bus2ip_cs,
+    Bus_RNW_reg,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    intr2bus_rdack0,
+    irpt_rdack,
+    irpt_wrack,
+    interrupt_wrce_strb,
+    \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
+    intr_rd_ce_or_reduce,
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
+    intr_wr_ce_or_reduce,
+    ipif_glbl_irpt_enable_reg_reg,
+    s_axi_rdata,
+    bus2ip_reset,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_aresetn,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    s_axi_bready,
+    s_axi_rready,
+    s_axi_awaddr,
+    s_axi_araddr,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    gpio2_io_t,
+    Q,
+    GPIO_DBus_i,
+    GPIO2_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    ipif_glbl_irpt_enable_reg,
+    irpt_rdack_d1,
+    irpt_wrack_d1,
+    p_1_in,
+    \\ip_irpt_enable_reg_reg[1] ,
+    \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
+    \\ip_irpt_enable_reg_reg[0] ,
+    ip2Bus_RdAck_intr_reg_hole_d1,
+    ip2Bus_WrAck_intr_reg_hole_d1,
+    s_axi_wdata,
+    \\ip2bus_data_i_D1_reg[0] );
+  output p_6_in;
+  output bus2ip_rnw;
+  output [0:0]bus2ip_cs;
+  output Bus_RNW_reg;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [4:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output intr2bus_rdack0;
+  output irpt_rdack;
+  output irpt_wrack;
+  output interrupt_wrce_strb;
+  output \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
+  output \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  output intr_rd_ce_or_reduce;
+  output \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  output intr_wr_ce_or_reduce;
+  output ipif_glbl_irpt_enable_reg_reg;
+  output [4:0]s_axi_rdata;
+  input bus2ip_reset;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_aresetn;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input s_axi_bready;
+  input s_axi_rready;
+  input [6:0]s_axi_awaddr;
+  input [6:0]s_axi_araddr;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [3:0]gpio2_io_t;
+  input [3:0]Q;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input ipif_glbl_irpt_enable_reg;
+  input irpt_rdack_d1;
+  input irpt_wrack_d1;
+  input p_1_in;
+  input \\ip_irpt_enable_reg_reg[1] ;
+  input \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
+  input \\ip_irpt_enable_reg_reg[0] ;
+  input ip2Bus_RdAck_intr_reg_hole_d1;
+  input ip2Bus_WrAck_intr_reg_hole_d1;
+  input [0:0]s_axi_wdata;
+  input [4:0]\\ip2bus_data_i_D1_reg[0] ;
+
+  wire Bus_RNW_reg;
+  wire [4:0]D;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
+  wire \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire [0:0]bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack0;
+  wire intr_rd_ce_or_reduce;
+  wire intr_wr_ce_or_reduce;
+  wire ip2Bus_RdAck_intr_reg_hole_d1;
+  wire ip2Bus_WrAck_intr_reg_hole_d1;
+  wire [4:0]\\ip2bus_data_i_D1_reg[0] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire \\ip_irpt_enable_reg_reg[0] ;
+  wire \\ip_irpt_enable_reg_reg[1] ;
+  wire ipif_glbl_irpt_enable_reg;
+  wire ipif_glbl_irpt_enable_reg_reg;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire p_1_in;
+  wire p_6_in;
+  wire s_axi_aclk;
+  wire [6:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [6:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [4:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [0:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
+       (.D(D),
+        .\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] (bus2ip_cs),
+        .\\Dual.gpio2_Data_Out_reg[0] (\\Dual.gpio2_Data_Out_reg[0] ),
+        .\\Dual.gpio2_OE_reg[0] (bus2ip_rnw),
+        .\\Dual.gpio_Data_In_reg[0] (\\Dual.gpio_Data_In_reg[0] ),
+        .\\Dual.gpio_Data_Out_reg[0] (\\Dual.gpio_Data_Out_reg[0] ),
+        .\\Dual.gpio_OE_reg[0] (\\Dual.gpio_OE_reg[0] ),
+        .E(E),
+        .\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ),
+        .\\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ),
+        .GPIO2_DBus_i(GPIO2_DBus_i),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
+        .\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
+        .Q(Q),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .bus2ip_reset(bus2ip_reset),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .interrupt_wrce_strb(interrupt_wrce_strb),
+        .intr2bus_rdack0(intr2bus_rdack0),
+        .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
+        .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
+        .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
+        .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
+        .\\ip2bus_data_i_D1_reg[0] (p_6_in),
+        .\\ip2bus_data_i_D1_reg[0]_0 (\\ip2bus_data_i_D1_reg[0] ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .\\ip_irpt_enable_reg_reg[0] (\\ip_irpt_enable_reg_reg[0] ),
+        .\\ip_irpt_enable_reg_reg[1] (\\ip_irpt_enable_reg_reg[1] ),
+        .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
+        .ipif_glbl_irpt_enable_reg_reg(Bus_RNW_reg),
+        .ipif_glbl_irpt_enable_reg_reg_0(ipif_glbl_irpt_enable_reg_reg),
+        .irpt_rdack(irpt_rdack),
+        .irpt_rdack_d1(irpt_rdack_d1),
+        .irpt_wrack(irpt_wrack),
+        .irpt_wrack_d1(irpt_wrack_d1),
+        .p_1_in(p_1_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
+   (D,
+    scndry_vect_out,
+    Q,
+    gpio_io_i,
+    s_axi_aclk);
+  output [3:0]D;
+  output [3:0]scndry_vect_out;
+  input [3:0]Q;
+  input [3:0]gpio_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]D;
+  wire [3:0]Q;
+  wire [3:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[0]_i_1 
+       (.I0(Q[3]),
+        .I1(scndry_vect_out[3]),
+        .O(D[3]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[1]_i_1 
+       (.I0(Q[2]),
+        .I1(scndry_vect_out[2]),
+        .O(D[2]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[2]_i_1 
+       (.I0(Q[1]),
+        .I1(scndry_vect_out[1]),
+        .O(D[1]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[3]_i_1 
+       (.I0(Q[0]),
+        .I1(scndry_vect_out[0]),
+        .O(D[0]));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""cdc_sync"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
+   (D,
+    scndry_vect_out,
+    \\Dual.gpio2_Data_In_reg[0] ,
+    gpio2_io_i,
+    s_axi_aclk);
+  output [3:0]D;
+  output [3:0]scndry_vect_out;
+  input [3:0]\\Dual.gpio2_Data_In_reg[0] ;
+  input [3:0]gpio2_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]D;
+  wire [3:0]\\Dual.gpio2_Data_In_reg[0] ;
+  wire [3:0]gpio2_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[0]_i_1 
+       (.I0(\\Dual.gpio2_Data_In_reg[0] [3]),
+        .I1(scndry_vect_out[3]),
+        .O(D[3]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[1]_i_1 
+       (.I0(\\Dual.gpio2_Data_In_reg[0] [2]),
+        .I1(scndry_vect_out[2]),
+        .O(D[2]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[2]_i_1 
+       (.I0(\\Dual.gpio2_Data_In_reg[0] [1]),
+        .I1(scndry_vect_out[1]),
+        .O(D[1]));
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[3]_i_1 
+       (.I0(\\Dual.gpio2_Data_In_reg[0] [0]),
+        .I1(scndry_vect_out[0]),
+        .O(D[0]));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_gpio_0_0,axi_gpio,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_gpio,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio2_io_i);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWVA'b'LID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"" *) output ip2intc_irpt;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_I"" *) input [3:0]gpio_io_i;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO2 TRI_I"" *) input [3:0]gpio2_io_i;
+
+  wire [3:0]gpio2_io_i;
+  wire [3:0]gpio_io_i;
+  wire ip2intc_irpt;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire [3:0]NLW_U0_gpio2_io_o_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio2_io_t_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio_io_o_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio_io_t_UNCONNECTED;
+
+  (* C_ALL_INPUTS = ""1"" *) 
+  (* C_ALL_INPUTS_2 = ""1"" *) 
+  (* C_ALL_OUTPUTS = ""0"" *) 
+  (* C_ALL_OUTPUTS_2 = ""0"" *) 
+  (* C_DOUT_DEFAULT = ""0"" *) 
+  (* C_DOUT_DEFAULT_2 = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_GPIO2_WIDTH = ""4"" *) 
+  (* C_GPIO_WIDTH = ""4"" *) 
+  (* C_INTERRUPT_PRESENT = ""1"" *) 
+  (* C_IS_DUAL = ""1"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_TRI_DEFAULT = ""-1"" *) 
+  (* C_TRI_DEFAULT_2 = ""-1"" *) 
+  (* downgradeipidentifiedwarnings = ""yes"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
+       (.gpio2_io_i(gpio2_io_i),
+        .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[3:0]),
+        .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[3:0]),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[3:0]),
+        .gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[3:0]),
+        .ip2intc_irpt(ip2intc_irpt),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control
+   (irpt_wrack_d1,
+    \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
+    p_1_in,
+    irpt_rdack_d1,
+    ipif_glbl_irpt_enable_reg,
+    IP2INTC_Irpt_i,
+    \\ip_irpt_enable_reg_reg[1]_0 ,
+    \\ip_irpt_enable_reg_reg[0]_0 ,
+    ip2bus_wrack_i,
+    ip2bus_rdack_i,
+    bus2ip_reset,
+    irpt_wrack,
+    s_axi_aclk,
+    GPIO_intr,
+    GPIO2_intr,
+    interrupt_wrce_strb,
+    irpt_rdack,
+    intr2bus_rdack0,
+    \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ,
+    Bus_RNW_reg_reg,
+    s_axi_wdata,
+    ip2Bus_WrAck_intr_reg_hole,
+    bus2ip_rnw,
+    GPIO_xferAck_i,
+    ip2Bus_RdAck_intr_reg_hole,
+    p_6_in,
+    Bus_RNW_reg);
+  output irpt_wrack_d1;
+  output \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
+  output p_1_in;
+  output irpt_rdack_d1;
+  output ipif_glbl_irpt_enable_reg;
+  output IP2INTC_Irpt_i;
+  output \\ip_irpt_enable_reg_reg[1]_0 ;
+  output \\ip_irpt_enable_reg_reg[0]_0 ;
+  output ip2bus_wrack_i;
+  output ip2bus_rdack_i;
+  input bus2ip_reset;
+  input irpt_wrack;
+  input s_axi_aclk;
+  input GPIO_intr;
+  input GPIO2_intr;
+  input interrupt_wrce_strb;
+  input irpt_rdack;
+  input intr2bus_rdack0;
+  input \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
+  input Bus_RNW_reg_reg;
+  input [1:0]s_axi_wdata;
+  input ip2Bus_WrAck_intr_reg_hole;
+  input bus2ip_rnw;
+  input GPIO_xferAck_i;
+  input ip2Bus_RdAck_intr_reg_hole;
+  input p_6_in;
+  input Bus_RNW_reg;
+
+  wire Bus_RNW_reg;
+  wire Bus_RNW_reg_reg;
+  wire \\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0 ;
+  wire \\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
+  wire \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ;
+  wire \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
+  wire \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 ;
+  wire GPIO2_intr;
+  wire GPIO_intr;
+  wire GPIO_xferAck_i;
+  wire IP2INTC_Irpt_i;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack;
+  wire intr2bus_rdack0;
+  wire intr2bus_wrack;
+  wire ip2Bus_RdAck_intr_reg_hole;
+  wire ip2Bus_WrAck_intr_reg_hole;
+  wire ip2bus_rdack_i;
+  wire ip2bus_wrack_i;
+  wire \\ip_irpt_enable_reg[0]_i_1_n_0 ;
+  wire \\ip_irpt_enable_reg[1]_i_1_n_0 ;
+  wire \\ip_irpt_enable_reg_reg[0]_0 ;
+  wire \\ip_irpt_enable_reg_reg[1]_0 ;
+  wire ipif_glbl_irpt_enable_reg;
+  wire irpt_dly1;
+  wire irpt_dly2;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire p_1_in;
+  wire p_6_in;
+  wire s_axi_aclk;
+  wire [1:0]s_axi_wdata;
+
+  FDSE \\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_intr),
+        .Q(irpt_dly1),
+        .S(bus2ip_reset));
+  FDSE \\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(irpt_dly1),
+        .Q(irpt_dly2),
+        .S(bus2ip_reset));
+  FDSE \\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO2_intr),
+        .Q(\\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0 ),
+        .S(bus2ip_reset));
+  FDSE \\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0 ),
+        .Q(\\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0 ),
+        .S(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'hF44FF4F4)) 
+    \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1 
+       (.I0(irpt_dly2),
+        .I1(irpt_dly1),
+        .I2(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
+        .I3(Bus_RNW_reg_reg),
+        .I4(s_axi_wdata[0]),
+        .O(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ));
+  FDRE \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ),
+        .Q(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'hF44FF4F4)) 
+    \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1 
+       (.I0(\\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0 ),
+        .I1(\\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0 ),
+        .I2(p_1_in),
+        .I3(Bus_RNW_reg_reg),
+        .I4(s_axi_wdata[1]),
+        .O(\\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 ));
+  FDRE \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 ),
+        .Q(p_1_in),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'hF0808080)) 
+    \\INTR_CTRLR_GEN.ip2intc_irpt_i_1 
+       (.I0(\\ip_irpt_enable_reg_reg[1]_0 ),
+        .I1(p_1_in),
+        .I2(ipif_glbl_irpt_enable_reg),
+        .I3(\\ip_irpt_enable_reg_reg[0]_0 ),
+        .I4(\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
+        .O(IP2INTC_Irpt_i));
+  FDRE intr2bus_rdack_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(intr2bus_rdack0),
+        .Q(intr2bus_rdack),
+        .R(bus2ip_reset));
+  FDRE intr2bus_wrack_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(interrupt_wrce_strb),
+        .Q(intr2bus_wrack),
+        .R(bus2ip_reset));
+  LUT4 #(
+    .INIT(16\'hFEEE)) 
+    ip2bus_rdack_i_D1_i_1
+       (.I0(ip2Bus_RdAck_intr_reg_hole),
+        .I1(intr2bus_rdack),
+        .I2(bus2ip_rnw),
+        .I3(GPIO_xferAck_i),
+        .O(ip2bus_rdack_i));
+  LUT4 #(
+    .INIT(16\'hEFEE)) 
+    ip2bus_wrack_i_D1_i_1
+       (.I0(ip2Bus_WrAck_intr_reg_hole),
+        .I1(intr2bus_wrack),
+        .I2(bus2ip_rnw),
+        .I3(GPIO_xferAck_i),
+        .O(ip2bus_wrack_i));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\ip_irpt_enable_reg[0]_i_1 
+       (.I0(s_axi_wdata[0]),
+        .I1(p_6_in),
+        .I2(Bus_RNW_reg),
+        .I3(\\ip_irpt_enable_reg_reg[0]_0 ),
+        .O(\\ip_irpt_enable_reg[0]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\ip_irpt_enable_reg[1]_i_1 
+       (.I0(s_axi_wdata[1]),
+        .I1(p_6_in),
+        .I2(Bus_RNW_reg),
+        .I3(\\ip_irpt_enable_reg_reg[1]_0 ),
+        .O(\\ip_irpt_enable_reg[1]_i_1_n_0 ));
+  FDRE \\ip_irpt_enable_reg_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\ip_irpt_enable_reg[0]_i_1_n_0 ),
+        .Q(\\ip_irpt_enable_reg_reg[0]_0 ),
+        .R(bus2ip_reset));
+  FDRE \\ip_irpt_enable_reg_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\ip_irpt_enable_reg[1]_i_1_n_0 ),
+        .Q(\\ip_irpt_enable_reg_reg[1]_0 ),
+        .R(bus2ip_reset));
+  FDRE ipif_glbl_irpt_enable_reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ),
+        .Q(ipif_glbl_irpt_enable_reg),
+        .R(bus2ip_reset));
+  FDRE irpt_rdack_d1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(irpt_rdack),
+        .Q(irpt_rdack_d1),
+        .R(bus2ip_reset));
+  FDRE irpt_wrack_d1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(irpt_wrack),
+        .Q(irpt_wrack_d1),
+        .R(bus2ip_reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
+   (\\ip2bus_data_i_D1_reg[0] ,
+    \\Dual.gpio2_OE_reg[0] ,
+    \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ,
+    ipif_glbl_irpt_enable_reg_reg,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    intr2bus_rdack0,
+    irpt_rdack,
+    irpt_wrack,
+    interrupt_wrce_strb,
+    \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
+    \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
+    intr_rd_ce_or_reduce,
+    \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
+    intr_wr_ce_or_reduce,
+    ipif_glbl_irpt_enable_reg_reg_0,
+    s_axi_rdata,
+    bus2ip_reset,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_aresetn,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    s_axi_bready,
+    s_axi_rready,
+    s_axi_awaddr,
+    s_axi_araddr,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    gpio2_io_t,
+    Q,
+    GPIO_DBus_i,
+    GPIO2_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    ipif_glbl_irpt_enable_reg,
+    irpt_rdack_d1,
+    irpt_wrack_d1,
+    p_1_in,
+    \\ip_irpt_enable_reg_reg[1] ,
+    \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
+    \\ip_irpt_enable_reg_reg[0] ,
+    ip2Bus_RdAck_intr_reg_hole_d1,
+    ip2Bus_WrAck_intr_reg_hole_d1,
+    s_axi_wdata,
+    \\ip2bus_data_i_D1_reg[0]_0 );
+  output \\ip2bus_data_i_D1_reg[0] ;
+  output \\Dual.gpio2_OE_reg[0] ;
+  output \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ;
+  output ipif_glbl_irpt_enable_reg_reg;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [4:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output intr2bus_rdack0;
+  output irpt_rdack;
+  output irpt_wrack;
+  output interrupt_wrce_strb;
+  output \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
+  output \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  output intr_rd_ce_or_reduce;
+  output \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  output intr_wr_ce_or_reduce;
+  output ipif_glbl_irpt_enable_reg_reg_0;
+  output [4:0]s_axi_rdata;
+  input bus2ip_reset;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_aresetn;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input s_axi_bready;
+  input s_axi_rready;
+  input [6:0]s_axi_awaddr;
+  input [6:0]s_axi_araddr;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [3:0]gpio2_io_t;
+  input [3:0]Q;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input ipif_glbl_irpt_enable_reg;
+  input irpt_rdack_d1;
+  input irpt_wrack_d1;
+  input p_1_in;
+  input \\ip_irpt_enable_reg_reg[1] ;
+  input \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
+  input \\ip_irpt_enable_reg_reg[0] ;
+  input ip2Bus_RdAck_intr_reg_hole_d1;
+  input ip2Bus_WrAck_intr_reg_hole_d1;
+  input [0:0]s_axi_wdata;
+  input [4:0]\\ip2bus_data_i_D1_reg[0]_0 ;
+
+  wire [4:0]D;
+  wire \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire \\Dual.gpio2_OE_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire \\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
+  wire \\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
+  wire \\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire [0:6]bus2ip_addr;
+  wire bus2ip_reset;
+  wire bus2ip_rnw_i06_out;
+  wire clear;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire interrupt_wrce_strb;
+  wire intr2bus_rdack0;
+  wire intr_rd_ce_or_reduce;
+  wire intr_wr_ce_or_reduce;
+  wire ip2Bus_RdAck_intr_reg_hole_d1;
+  wire ip2Bus_WrAck_intr_reg_hole_d1;
+  wire \\ip2bus_data_i_D1_reg[0] ;
+  wire [4:0]\\ip2bus_data_i_D1_reg[0]_0 ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire \\ip_irpt_enable_reg_reg[0] ;
+  wire \\ip_irpt_enable_reg_reg[1] ;
+  wire ipif_glbl_irpt_enable_reg;
+  wire ipif_glbl_irpt_enable_reg_reg;
+  wire ipif_glbl_irpt_enable_reg_reg_0;
+  wire irpt_rdack;
+  wire irpt_rdack_d1;
+  wire irpt_wrack;
+  wire irpt_wrack_d1;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_write;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire [1:0]p_0_out__0;
+  wire p_1_in;
+  wire [8:2]p_1_in__0;
+  wire [3:0]plusOp;
+  wire s_axi_aclk;
+  wire [6:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [6:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [4:0]s_axi_rdata;
+  wire s_axi_rdata_i;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire [0:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire \\state[1]_i_2_n_0 ;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[1]),
+        .I1(state[0]),
+        .O(clear));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(clear));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
+       (.D(D),
+        .\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] (\\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] ),
+        .\\Dual.gpio2_Data_In_reg[0] (Q),
+        .\\Dual.gpio2_Data_Out_reg[0] (\\Dual.gpio2_Data_Out_reg[0] ),
+        .\\Dual.gpio_Data_In_reg[0] (\\Dual.gpio_Data_In_reg[0] ),
+        .\\Dual.gpio_Data_Out_reg[0] (\\Dual.gpio_Data_Out_reg[0] ),
+        .\\Dual.gpio_OE_reg[0] (\\Dual.gpio_OE_reg[0] ),
+        .E(E),
+        .\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ),
+        .\\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ),
+        .GPIO2_DBus_i(GPIO2_DBus_i),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
+        .\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .\\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw_i_reg(\\Dual.gpio2_OE_reg[0] ),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .interrupt_wrce_strb(interrupt_wrce_strb),
+        .intr2bus_rdack0(intr2bus_rdack0),
+        .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
+        .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
+        .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
+        .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
+        .\\ip2bus_data_i_D1_reg[0] (\\ip2bus_data_i_D1_reg[0] ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .\\ip_irpt_enable_reg_reg[0] (\\ip_irpt_enable_reg_reg[0] ),
+        .\\ip_irpt_enable_reg_reg[1] (\\ip_irpt_enable_reg_reg[1] ),
+        .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg),
+        .ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
+        .ipif_glbl_irpt_enable_reg_reg_0(ipif_glbl_irpt_enable_reg_reg_0),
+        .irpt_rdack(irpt_rdack),
+        .irpt_rdack_d1(irpt_rdack_d1),
+        .irpt_wrack(irpt_wrack),
+        .irpt_wrack_d1(irpt_wrack_d1),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .p_1_in(p_1_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .start2(start2));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_awaddr[0]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[0]),
+        .O(p_1_in__0[2]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_awaddr[1]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[1]),
+        .O(p_1_in__0[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[4]_i_1 
+       (.I0(s_axi_awaddr[2]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .O(p_1_in__0[4]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[5]_i_1 
+       (.I0(s_axi_awaddr[3]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[3]),
+        .O(p_1_in__0[5]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[6]_i_1 
+       (.I0(s_axi_awaddr[4]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[4]),
+        .O(p_1_in__0[6]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[7]_i_1 
+       (.I0(s_axi_awaddr[5]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[5]),
+        .O(p_1_in__0[7]));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_awaddr[6]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[6]),
+        .O(p_1_in__0[8]));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[2]),
+        .Q(bus2ip_addr[6]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[3]),
+        .Q(bus2ip_addr[5]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[4]),
+        .Q(bus2ip_addr[4]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[5]),
+        .Q(bus2ip_addr[3]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[6]),
+        .Q(bus2ip_addr[2]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[7]),
+        .Q(bus2ip_addr[1]),
+        .R(bus2ip_reset));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(p_1_in__0[8]),
+        .Q(bus2ip_addr[0]),
+        .R(bus2ip_reset));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT3 #(
+    .INIT(8\'h02)) 
+    bus2ip_rnw_i_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state[0]),
+        .I2(state[1]),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(bus2ip_rnw_i06_out),
+        .Q(\\Dual.gpio2_OE_reg[0] ),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h3FFA000A)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(\\state[1]_i_2_n_0 ),
+        .I2(state[1]),
+        .I3(state[0]),
+        .I4(is_read),
+        .O(is_read_i_1_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(bus2ip_reset));
+  LUT6 #(
+    .INIT(64\'h1000FFFF10000000)) 
+    is_write_i_1
+       (.I0(state[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_axi_wvalid),
+        .I3(s_axi_awvalid),
+        .I4(is_write),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hF88800000000FFFF)) 
+    is_write_i_2
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .I4(state[1]),
+        .I5(state[0]),
+        .O(is_write));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_wready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(bus2ip_reset));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[31]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(s_axi_rdata_i));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_0 [0]),
+        .Q(s_axi_rdata[0]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_0 [1]),
+        .Q(s_axi_rdata[1]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_0 [2]),
+        .Q(s_axi_rdata[2]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_0 [4]),
+        .Q(s_axi_rdata[4]),
+        .R(bus2ip_reset));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[0]_0 [3]),
+        .Q(s_axi_rdata[3]),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_arready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h000000F8)) 
+    start2_i_1
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(state[1]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(bus2ip_reset));
+  LUT5 #(
+    .INIT(32\'h0FFFAACC)) 
+    \\state[0]_i_1 
+       (.I0(s_axi_wready),
+        .I1(s_axi_arvalid),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(p_0_out__0[0]));
+  LUT6 #(
+    .INIT(64\'h2E2E2E2ECCCCFFCC)) 
+    \\state[1]_i_1 
+       (.I0(s_axi_arready),
+        .I1(state[1]),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(\\state[1]_i_3_n_0 ),
+        .I4(s_axi_arvalid),
+        .I5(state[0]),
+        .O(p_0_out__0[1]));
+  LUT4 #(
+    .INIT(16\'hF888)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(\\state[1]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\state[1]_i_3 
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out__0[0]),
+        .Q(state[0]),
+        .R(bus2ip_reset));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out__0[1]),
+        .Q(state[1]),
+        .R(bus2ip_reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:44:08 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top design_1_xbar_0 -prefix
+//               design_1_xbar_0_ design_1_xbar_0_stub.v
+// Design      : design_1_xbar_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *)
+module design_1_xbar_0(aclk, aresetn, s_axi_awaddr, s_axi_awprot, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, 
+  s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr, 
+  m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, 
+  m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, 
+  m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin=""aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]"" */;
+  input aclk;
+  input aresetn;
+  input [31:0]s_axi_awaddr;
+  input [2:0]s_axi_awprot;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [31:0]s_axi_araddr;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [95:0]m_axi_awaddr;
+  output [8:0]m_axi_awprot;
+  output [2:0]m_axi_awvalid;
+  input [2:0]m_axi_awready;
+  output [95:0]m_axi_wdata;
+  output [11:0]m_axi_wstrb;
+  output [2:0]m_axi_wvalid;
+  input [2:0]m_axi_wready;
+  input [5:0]m_axi_bresp;
+  input [2:0]m_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [95:0]m_axi_araddr;
+  output [8:0]m_axi_arprot;
+  output [2:0]m_axi_arvalid;
+  input [2:0]m_axi_arready;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rvalid;
+  output [2:0]m_axi_rready;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:37:11 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_sim_netlist.v
+// Design      : design_1_axi_intc_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
+   (p_15_in,
+    p_17_in,
+    \\mer_int_reg[1] ,
+    D,
+    ip2bus_wrack_prev2,
+    ip2bus_rdack_prev2,
+    Or128_vec2stdlogic19_out,
+    \\mer_int_reg[1]_0 ,
+    \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
+    \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
+    \\mer_int_reg[0] ,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
+    ip2bus_wrack_int_d1_reg,
+    Q,
+    s_axi_aclk,
+    is_write_reg,
+    ip2bus_wrack,
+    s_axi_aresetn,
+    ip2bus_rdack,
+    is_read,
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
+    \\bus2ip_addr_i_reg[8] ,
+    \\IVR_GEN.ivr_reg[0] ,
+    \\REG_GEN[0].ier_reg[0] ,
+    \\bus2ip_addr_i_reg[5] ,
+    \\IVR_GEN.ivr_reg[0]_0 ,
+    ip2bus_wrack_int_d1,
+    ip2bus_rdack_int_d1,
+    s_axi_wdata,
+    p_0_in_0,
+    sie,
+    cie,
+    mer,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ,
+    bus2ip_rnw_i_reg);
+  output p_15_in;
+  output p_17_in;
+  output \\mer_int_reg[1] ;
+  output [2:0]D;
+  output ip2bus_wrack_prev2;
+  output ip2bus_rdack_prev2;
+  output Or128_vec2stdlogic19_out;
+  output \\mer_int_reg[1]_0 ;
+  output \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  output \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  output \\mer_int_reg[0] ;
+  output \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  output ip2bus_wrack_int_d1_reg;
+  input Q;
+  input s_axi_aclk;
+  input is_write_reg;
+  input ip2bus_wrack;
+  input s_axi_aresetn;
+  input ip2bus_rdack;
+  input is_read;
+  input [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  input [6:0]\\bus2ip_addr_i_reg[8] ;
+  input \\IVR_GEN.ivr_reg[0] ;
+  input \\REG_GEN[0].ier_reg[0] ;
+  input \\bus2ip_addr_i_reg[5] ;
+  input \\IVR_GEN.ivr_reg[0]_0 ;
+  input ip2bus_wrack_int_d1;
+  input ip2bus_rdack_int_d1;
+  input [1:0]s_axi_wdata;
+  input p_0_in_0;
+  input sie;
+  input cie;
+  input mer;
+  input \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+  input bus2ip_rnw_i_reg;
+
+  wire Bus_RNW_reg_i_1_n_0;
+  wire \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  wire [2:0]D;
+  wire \\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ;
+  wire \\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0 ;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  wire \\IVR_GEN.ivr_reg[0] ;
+  wire \\IVR_GEN.ivr_reg[0]_0 ;
+  wire Or128_vec2stdlogic19_out;
+  wire Q;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+  wire \\REG_GEN[0].ier_reg[0] ;
+  wire \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  wire \\bus2ip_addr_i_reg[5] ;
+  wire [6:0]\\bus2ip_addr_i_reg[8] ;
+  wire bus2ip_rnw_i_reg;
+  wire cie;
+  wire cs_ce_clr;
+  wire ip2bus_rdack;
+  wire ip2bus_rdack_int_d1;
+  wire ip2bus_rdack_prev2;
+  wire ip2bus_wrack;
+  wire ip2bus_wrack_int_d1;
+  wire ip2bus_wrack_int_d1_i_2_n_0;
+  wire ip2bus_wrack_int_d1_i_3_n_0;
+  wire ip2bus_wrack_int_d1_reg;
+  wire ip2bus_wrack_prev2;
+  wire is_read;
+  wire is_write_reg;
+  wire mer;
+  wire \\mer_int_reg[0] ;
+  wire \\mer_int_reg[1] ;
+  wire \\mer_int_reg[1]_0 ;
+  wire p_0_in_0;
+  wire p_10_in;
+  wire p_11_in;
+  wire p_12_in;
+  wire p_12_out;
+  wire p_13_in;
+  wire p_13_out;
+  wire p_14_in;
+  wire p_15_in;
+  wire p_15_out;
+  wire p_16_in;
+  wire p_17_in;
+  wire p_2_in;
+  wire p_2_out;
+  wire p_3_in;
+  wire p_3_out;
+  wire p_4_in;
+  wire p_4_out;
+  wire p_5_in;
+  wire p_5_out;
+  wire p_6_in;
+  wire p_6_out;
+  wire p_7_in;
+  wire p_7_out;
+  wire p_8_in;
+  wire p_9_in;
+  wire pselect_hit_i_0;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire \\s_axi_rdata_i[0]_i_2_n_0 ;
+  wire \\s_axi_rdata_i[31]_i_3_n_0 ;
+  wire \\s_axi_rdata_i[31]_i_4_n_0 ;
+  wire [1:0]s_axi_wdata;
+  wire sie;
+
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    Bus_RNW_reg_i_1
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(Q),
+        .I2(\\mer_int_reg[1] ),
+        .O(Bus_RNW_reg_i_1_n_0));
+  FDRE Bus_RNW_reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_i_1_n_0),
+        .Q(\\mer_int_reg[1] ),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h02000000)) 
+    \\CIE_GEN.CIE_BIT_GEN[0].cie[0]_i_1 
+       (.I0(s_axi_aresetn),
+        .I1(cie),
+        .I2(\\mer_int_reg[1] ),
+        .I3(p_12_in),
+        .I4(s_axi_wdata[0]),
+        .O(\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h00000010)) 
+    \\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [0]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(\\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ),
+        .Q(p_17_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(p_5_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_5_out),
+        .Q(p_7_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h20000000)) 
+    \\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .O(p_4_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_4_out),
+        .Q(p_6_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h00400000)) 
+    \\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(p_3_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_3_out),
+        .Q(p_5_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h40000000)) 
+    \\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .O(p_2_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_2_out),
+        .Q(p_4_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT5 #(
+    .INIT(32\'h00800000)) 
+    \\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(\\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1_n_0 ),
+        .Q(p_3_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h80000000)) 
+    \\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .O(p_15_out));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'h0002)) 
+    \\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2 
+       (.I0(Q),
+        .I1(\\bus2ip_addr_i_reg[8] [5]),
+        .I2(\\bus2ip_addr_i_reg[8] [4]),
+        .I3(\\bus2ip_addr_i_reg[8] [6]),
+        .O(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_15_out),
+        .Q(p_2_in),
+        .R(cs_ce_clr));
+  LUT6 #(
+    .INIT(64\'hFFCFFFFFFFCFFFEF)) 
+    \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1 
+       (.I0(is_write_reg),
+        .I1(ip2bus_wrack),
+        .I2(s_axi_aresetn),
+        .I3(ip2bus_rdack),
+        .I4(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ),
+        .I5(is_read),
+        .O(cs_ce_clr));
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_2 
+       (.I0(Q),
+        .I1(\\bus2ip_addr_i_reg[8] [6]),
+        .I2(\\bus2ip_addr_i_reg[8] [5]),
+        .O(pselect_hit_i_0));
+  LUT4 #(
+    .INIT(16\'hFFFD)) 
+    \\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
+        .O(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(pselect_hit_i_0),
+        .Q(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT5 #(
+    .INIT(32\'h00000040)) 
+    \\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(\\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ),
+        .Q(p_16_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00001000)) 
+    \\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [0]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(p_13_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_13_out),
+        .Q(p_15_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h00004000)) 
+    \\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(p_12_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_12_out),
+        .Q(p_14_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT5 #(
+    .INIT(32\'h00100000)) 
+    \\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [0]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(\\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
+        .Q(p_13_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'h00400000)) 
+    \\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(\\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ),
+        .Q(p_12_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'h10000000)) 
+    \\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [0]),
+        .I1(\\bus2ip_addr_i_reg[8] [3]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(\\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0 ),
+        .Q(p_11_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT5 #(
+    .INIT(32\'h40000000)) 
+    \\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [3]),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [2]),
+        .O(\\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0 ));
+  FDRE \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(\\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0 ),
+        .Q(p_10_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'h00100000)) 
+    \\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1 
+       (.I0(\\bus2ip_addr_i_reg[8] [1]),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [3]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .O(p_7_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_7_out),
+        .Q(p_9_in),
+        .R(cs_ce_clr));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h02000000)) 
+    \\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1 
+       (.I0(\\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [0]),
+        .I4(\\bus2ip_addr_i_reg[8] [3]),
+        .O(p_6_out));
+  FDRE \\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9] 
+       (.C(s_axi_aclk),
+        .CE(Q),
+        .D(p_6_out),
+        .Q(p_8_in),
+        .R(cs_ce_clr));
+  LUT5 #(
+    .INIT(32\'h00004000)) 
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar[0]_i_1 
+       (.I0(\\mer_int_reg[1] ),
+        .I1(s_axi_wdata[0]),
+        .I2(p_14_in),
+        .I3(s_axi_aresetn),
+        .I4(\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
+        .O(\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ));
+  LUT5 #(
+    .INIT(32\'h00004000)) 
+    \\SIE_GEN.SIE_BIT_GEN[0].sie[0]_i_1 
+       (.I0(\\mer_int_reg[1] ),
+        .I1(p_13_in),
+        .I2(s_axi_wdata[0]),
+        .I3(s_axi_aresetn),
+        .I4(sie),
+        .O(\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ));
+  LUT6 #(
+    .INIT(64\'h00000000FFFB0000)) 
+    ip2bus_rdack_i_1
+       (.I0(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I1(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I2(ip2bus_wrack_int_d1_i_3_n_0),
+        .I3(ip2bus_wrack_int_d1_i_2_n_0),
+        .I4(\\mer_int_reg[1] ),
+        .I5(ip2bus_rdack_int_d1),
+        .O(ip2bus_rdack_prev2));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAAA8AA)) 
+    ip2bus_rdack_int_d1_i_1
+       (.I0(\\mer_int_reg[1] ),
+        .I1(ip2bus_wrack_int_d1_i_2_n_0),
+        .I2(ip2bus_wrack_int_d1_i_3_n_0),
+        .I3(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I4(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .O(Or128_vec2stdlogic19_out));
+  LUT6 #(
+    .INIT(64\'h000000000000FFFB)) 
+    ip2bus_wrack_i_1
+       (.I0(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I1(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I2(ip2bus_wrack_int_d1_i_3_n_0),
+        .I3(ip2bus_wrack_int_d1_i_2_n_0),
+        .I4(\\mer_int_reg[1] ),
+        .I5(ip2bus_wrack_int_d1),
+        .O(ip2bus_wrack_prev2));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT5 #(
+    .INIT(32\'h55555455)) 
+    ip2bus_wrack_int_d1_i_1
+       (.I0(\\mer_int_reg[1] ),
+        .I1(ip2bus_wrack_int_d1_i_2_n_0),
+        .I2(ip2bus_wrack_int_d1_i_3_n_0),
+        .I3(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I4(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .O(ip2bus_wrack_int_d1_reg));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    ip2bus_wrack_int_d1_i_2
+       (.I0(p_4_in),
+        .I1(p_3_in),
+        .I2(p_6_in),
+        .I3(p_2_in),
+        .O(ip2bus_wrack_int_d1_i_2_n_0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFFFFFFFE)) 
+    ip2bus_wrack_int_d1_i_3
+       (.I0(p_12_in),
+        .I1(p_14_in),
+        .I2(p_13_in),
+        .I3(p_7_in),
+        .I4(\\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
+        .I5(p_5_in),
+        .O(ip2bus_wrack_int_d1_i_3_n_0));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\mer_int[0]_i_1 
+       (.I0(s_axi_wdata[0]),
+        .I1(p_10_in),
+        .I2(\\mer_int_reg[1] ),
+        .I3(mer),
+        .O(\\mer_int_reg[0] ));
+  LUT4 #(
+    .INIT(16\'hFF20)) 
+    \\mer_int[1]_i_1 
+       (.I0(s_axi_wdata[1]),
+        .I1(\\mer_int_reg[1] ),
+        .I2(p_10_in),
+        .I3(p_0_in_0),
+        .O(\\mer_int_reg[1]_0 ));
+  LUT6 #(
+    .INIT(64\'h0051515151515151)) 
+    \\s_axi_rdata_i[0]_i_1 
+       (.I0(\\s_axi_rdata_i[31]_i_3_n_0 ),
+        .I1(\\s_axi_rdata_i[0]_i_2_n_0 ),
+        .I2(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I3(\\IVR_GEN.ivr_reg[0] ),
+        .I4(\\REG_GEN[0].ier_reg[0] ),
+        .I5(\\bus2ip_addr_i_reg[5] ),
+        .O(D[0]));
+  LUT3 #(
+    .INIT(8\'h01)) 
+    \\s_axi_rdata_i[0]_i_2 
+       (.I0(p_8_in),
+        .I1(p_11_in),
+        .I2(p_9_in),
+        .O(\\s_axi_rdata_i[0]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0000000055555554)) 
+    \\s_axi_rdata_i[1]_i_1 
+       (.I0(\\s_axi_rdata_i[31]_i_3_n_0 ),
+        .I1(p_9_in),
+        .I2(p_11_in),
+        .I3(p_8_in),
+        .I4(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I5(\\IVR_GEN.ivr_reg[0]_0 ),
+        .O(D[1]));
+  LUT6 #(
+    .INIT(64\'h0000000055555554)) 
+    \\s_axi_rdata_i[31]_i_2 
+       (.I0(\\s_axi_rdata_i[31]_i_3_n_0 ),
+        .I1(p_9_in),
+        .I2(p_11_in),
+        .I3(p_8_in),
+        .I4(\\s_axi_rdata_i[31]_i_4_n_0 ),
+        .I5(\\IVR_GEN.ivr_reg[0] ),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'hFEFF)) 
+    \\s_axi_rdata_i[31]_i_3 
+       (.I0(\\bus2ip_addr_i_reg[8] [5]),
+        .I1(\\bus2ip_addr_i_reg[8] [4]),
+        .I2(\\bus2ip_addr_i_reg[8] [6]),
+        .I3(\\mer_int_reg[1] ),
+        .O(\\s_axi_rdata_i[31]_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\s_axi_rdata_i[31]_i_4 
+       (.I0(p_15_in),
+        .I1(p_17_in),
+        .I2(p_16_in),
+        .I3(p_10_in),
+        .O(\\s_axi_rdata_i[31]_i_4_n_0 ));
+endmodule
+
+(* C_ASYNC_INTR = ""-2"" *) (* C_CASCADE_MASTER = ""0"" *) (* C_DISABLE_SYNCHRONIZERS = ""0"" *) 
+(* C_ENABLE_ASYNC = ""0"" *) (* C_EN_CASCADE_MODE = ""0"" *) (* C_FAMILY = ""zynq"" *) 
+(* C_HAS_CIE = ""1"" *) (* C_HAS_FAST = ""0"" *) (* C_HAS_ILR = ""0"" *) 
+(* C_HAS_IPR = ""1"" *) (* C_HAS_IVR = ""1"" *) (* C_HAS_SIE = ""1"" *) 
+(* C_INSTANCE = ""design_1_axi_intc_0_0"" *) (* C_IRQ_ACTIVE = ""1\'b1"" *) (* C_IRQ_IS_LEVEL = ""1"" *) 
+(* C_IVAR_RESET_VALUE = ""16"" *) (* C_KIND_OF_EDGE = ""-1"" *) (* C_KIND_OF_INTR = ""-2"" *) 
+(* C_KIND_OF_LVL = ""-1"" *) (* C_MB_CLK_NOT_CONNECTED = ""1"" *) (* C_NUM_INTR_INPUTS = ""1"" *) 
+(* C_NUM_SW_INTR = ""0"" *) (* C_NUM_SYNC_FF = ""2"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* hdl = ""VHDL"" *) (* imp_netlist = ""TRUE"" *) 
+(* ip_group = ""LOGICORE"" *) (* iptype = ""PERIPHERAL"" *) (* run_ngcbuild = ""TRUE"" *) 
+(* style = ""HDL"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_intc
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    intr,
+    processor_clk,
+    processor_rst,
+    irq,
+    processor_ack,
+    interrupt_address,
+    irq_in,
+    interrupt_address_in,
+    processor_ack_out);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rstn"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* BUFFER_TYPE = ""none"" *) input [0:0]intr;
+  input processor_clk;
+  input processor_rst;
+  output irq;
+  input [1:0]processor_ack;
+  output [31:0]interrupt_address;
+  input irq_in;
+  input [31:0]interrupt_address_in;
+  output [1:0]processor_ack_out;
+
+  wire \\<const0> ;
+  wire AXI_LITE_IPIF_I_n_12;
+  wire AXI_LITE_IPIF_I_n_13;
+  wire AXI_LITE_IPIF_I_n_14;
+  wire AXI_LITE_IPIF_I_n_15;
+  wire AXI_LITE_IPIF_I_n_16;
+  wire AXI_LITE_IPIF_I_n_17;
+  wire INTC_CORE_I_n_4;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ;
+  wire \\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ;
+  wire Or128_vec2stdlogic19_out;
+  wire cie;
+  wire ier;
+  wire [0:0]intr;
+  wire ip2bus_rdack;
+  wire ip2bus_rdack_int_d1;
+  wire ip2bus_rdack_prev2;
+  wire ip2bus_wrack;
+  wire ip2bus_wrack_int_d1;
+  wire ip2bus_wrack_prev2;
+  wire [0:0]ipr;
+  wire irq;
+  wire isr;
+  wire ivr;
+  wire mer;
+  wire p_0_in;
+  wire p_0_in_0;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rstn"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:1]\\^s_axi_bresp ;
+  wire s_axi_bvalid;
+  wire [30:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire [1:1]\\^s_axi_rresp ;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire sie;
+
+  assign interrupt_address[31] = \\<const0> ;
+  assign interrupt_address[30] = \\<const0> ;
+  assign interrupt_address[29] = \\<const0> ;
+  assign interrupt_address[28] = \\<const0> ;
+  assign interrupt_address[27] = \\<const0> ;
+  assign interrupt_address[26] = \\<const0> ;
+  assign interrupt_address[25] = \\<const0> ;
+  assign interrupt_address[24] = \\<const0> ;
+  assign interrupt_address[23] = \\<const0> ;
+  assign interrupt_address[22] = \\<const0> ;
+  assign interrupt_address[21] = \\<const0> ;
+  assign interrupt_address[20] = \\<const0> ;
+  assign interrupt_address[19] = \\<const0> ;
+  assign interrupt_address[18] = \\<const0> ;
+  assign interrupt_address[17] = \\<const0> ;
+  assign interrupt_address[16] = \\<const0> ;
+  assign interrupt_address[15] = \\<const0> ;
+  assign interrupt_address[14] = \\<const0> ;
+  assign interrupt_address[13] = \\<const0> ;
+  assign interrupt_address[12] = \\<const0> ;
+  assign interrupt_address[11] = \\<const0> ;
+  assign interrupt_address[10] = \\<const0> ;
+  assign interrupt_address[9] = \\<const0> ;
+  assign interrupt_address[8] = \\<const0> ;
+  assign interrupt_address[7] = \\<const0> ;
+  assign interrupt_address[6] = \\<const0> ;
+  assign interrupt_address[5] = \\<const0> ;
+  assign interrupt_address[4] = \\<const0> ;
+  assign interrupt_address[3] = \\<const0> ;
+  assign interrupt_address[2] = \\<const0> ;
+  assign interrupt_address[1] = \\<const0> ;
+  assign interrupt_address[0] = \\<const0> ;
+  assign processor_ack_out[1] = \\<const0> ;
+  assign processor_ack_out[0] = \\<const0> ;
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\^s_axi_bresp [1];
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[30] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[29] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[28] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[27] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[26] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[25] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[24] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[23] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[22] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[21] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[20] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[19] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[18] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[17] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[16] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[15] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[14] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[13] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[12] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[11] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[10] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[9] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[8] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[7] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[6] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[5] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[4] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[3] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[2] = \\^s_axi_rdata [30];
+  assign s_axi_rdata[1:0] = \\^s_axi_rdata [1:0];
+  assign s_axi_rresp[1] = \\^s_axi_rresp [1];
+  assign s_axi_rresp[0] = \\<const0> ;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
+       (.Bus_RNW_reg(\\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+        .\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (AXI_LITE_IPIF_I_n_14),
+        .Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (AXI_LITE_IPIF_I_n_16),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (INTC_CORE_I_n_4),
+        .\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (AXI_LITE_IPIF_I_n_13),
+        .cie(cie),
+        .ier(ier),
+        .ip2bus_rdack(ip2bus_rdack),
+        .ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
+        .ip2bus_rdack_prev2(ip2bus_rdack_prev2),
+        .ip2bus_wrack(ip2bus_wrack),
+        .ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
+        .ip2bus_wrack_int_d1_reg(AXI_LITE_IPIF_I_n_17),
+        .ip2bus_wrack_prev2(ip2bus_wrack_prev2),
+        .ipr(ipr),
+        .isr(isr),
+        .ivr(ivr),
+        .mer(mer),
+        .\\mer_int_reg[0] (AXI_LITE_IPIF_I_n_15),
+        .\\mer_int_reg[1] (AXI_LITE_IPIF_I_n_12),
+        .p_0_in(p_0_in),
+        .p_0_in_0(p_0_in_0),
+        .p_15_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ),
+        .p_17_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr[8:2]),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr[8:2]),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(\\^s_axi_bresp ),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata({\\^s_axi_rdata [30],\\^s_axi_rdata [1:0]}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(\\^s_axi_rresp ),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata[1:0]),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid),
+        .sie(sie));
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_intc_core INTC_CORE_I
+       (.Bus_RNW_reg(\\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
+        .Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_16),
+        .Bus_RNW_reg_reg_0(AXI_LITE_IPIF_I_n_12),
+        .Bus_RNW_reg_reg_1(AXI_LITE_IPIF_I_n_13),
+        .\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 (AXI_LITE_IPIF_I_n_14),
+        .\\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] (AXI_LITE_IPIF_I_n_15),
+        .\\REG_GEN[0].isr_reg[0]_0 (INTC_CORE_I_n_4),
+        .cie(cie),
+        .ier(ier),
+        .intr(intr),
+        .ipr(ipr),
+        .irq(irq),
+        .isr(isr),
+        .ivr(ivr),
+        .mer(mer),
+        .p_0_in(p_0_in),
+        .p_0_in_0(p_0_in_0),
+        .p_15_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ),
+        .p_17_in(\\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_wdata(s_axi_wdata[0]),
+        .sie(sie));
+  FDRE ip2bus_rdack_int_d1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Or128_vec2stdlogic19_out),
+        .Q(ip2bus_rdack_int_d1),
+        .R(p_0_in));
+  FDRE ip2bus_rdack_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_prev2),
+        .Q(ip2bus_rdack),
+        .R(p_0_in));
+  FDRE ip2bus_wrack_int_d1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(AXI_LITE_IPIF_I_n_17),
+        .Q(ip2bus_wrack_int_d1),
+        .R(p_0_in));
+  FDRE ip2bus_wrack_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_wrack_prev2),
+        .Q(ip2bus_wrack),
+        .R(p_0_in));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
+   (p_15_in,
+    p_17_in,
+    s_axi_rresp,
+    Bus_RNW_reg,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_bresp,
+    s_axi_wready,
+    s_axi_arready,
+    ip2bus_wrack_prev2,
+    ip2bus_rdack_prev2,
+    Or128_vec2stdlogic19_out,
+    \\mer_int_reg[1] ,
+    \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
+    \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
+    \\mer_int_reg[0] ,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
+    ip2bus_wrack_int_d1_reg,
+    s_axi_rdata,
+    p_0_in,
+    s_axi_aclk,
+    s_axi_arvalid,
+    ip2bus_wrack,
+    s_axi_aresetn,
+    ip2bus_rdack,
+    s_axi_rready,
+    s_axi_bready,
+    s_axi_wvalid,
+    s_axi_awvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    ier,
+    ipr,
+    ivr,
+    p_0_in_0,
+    mer,
+    isr,
+    ip2bus_wrack_int_d1,
+    ip2bus_rdack_int_d1,
+    s_axi_wstrb,
+    s_axi_wdata,
+    sie,
+    cie,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 );
+  output p_15_in;
+  output p_17_in;
+  output [0:0]s_axi_rresp;
+  output Bus_RNW_reg;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output [0:0]s_axi_bresp;
+  output s_axi_wready;
+  output s_axi_arready;
+  output ip2bus_wrack_prev2;
+  output ip2bus_rdack_prev2;
+  output Or128_vec2stdlogic19_out;
+  output \\mer_int_reg[1] ;
+  output \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  output \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  output \\mer_int_reg[0] ;
+  output \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  output ip2bus_wrack_int_d1_reg;
+  output [2:0]s_axi_rdata;
+  input p_0_in;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input ip2bus_wrack;
+  input s_axi_aresetn;
+  input ip2bus_rdack;
+  input s_axi_rready;
+  input s_axi_bready;
+  input s_axi_wvalid;
+  input s_axi_awvalid;
+  input [6:0]s_axi_araddr;
+  input [6:0]s_axi_awaddr;
+  input ier;
+  input [0:0]ipr;
+  input ivr;
+  input p_0_in_0;
+  input mer;
+  input isr;
+  input ip2bus_wrack_int_d1;
+  input ip2bus_rdack_int_d1;
+  input [3:0]s_axi_wstrb;
+  input [1:0]s_axi_wdata;
+  input sie;
+  input cie;
+  input \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+
+  wire Bus_RNW_reg;
+  wire \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  wire Or128_vec2stdlogic19_out;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+  wire \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  wire cie;
+  wire ier;
+  wire ip2bus_rdack;
+  wire ip2bus_rdack_int_d1;
+  wire ip2bus_rdack_prev2;
+  wire ip2bus_wrack;
+  wire ip2bus_wrack_int_d1;
+  wire ip2bus_wrack_int_d1_reg;
+  wire ip2bus_wrack_prev2;
+  wire [0:0]ipr;
+  wire isr;
+  wire ivr;
+  wire mer;
+  wire \\mer_int_reg[0] ;
+  wire \\mer_int_reg[1] ;
+  wire p_0_in;
+  wire p_0_in_0;
+  wire p_15_in;
+  wire p_17_in;
+  wire s_axi_aclk;
+  wire [6:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [6:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [0:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [2:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [0:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [1:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire sie;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
+       (.\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
+        .Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
+        .\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
+        .cie(cie),
+        .ier(ier),
+        .ip2bus_rdack(ip2bus_rdack),
+        .ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
+        .ip2bus_rdack_prev2(ip2bus_rdack_prev2),
+        .ip2bus_wrack(ip2bus_wrack),
+        .ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
+        .ip2bus_wrack_int_d1_reg(ip2bus_wrack_int_d1_reg),
+        .ip2bus_wrack_prev2(ip2bus_wrack_prev2),
+        .ipr(ipr),
+        .isr(isr),
+        .ivr(ivr),
+        .mer(mer),
+        .\\mer_int_reg[0] (\\mer_int_reg[0] ),
+        .\\mer_int_reg[1] (Bus_RNW_reg),
+        .\\mer_int_reg[1]_0 (\\mer_int_reg[1] ),
+        .p_0_in(p_0_in),
+        .p_0_in_0(p_0_in_0),
+        .p_15_in(p_15_in),
+        .p_17_in(p_17_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid),
+        .sie(sie));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_intc_0_0,axi_intc,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_intc,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    intr,
+    irq);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 s_axi_aclk CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 s_resetn RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi AWVALID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 s_axi RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT"" *) input [0:0]intr;
+  (* x_interface_info = ""xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT"" *) output irq;
+
+  wire [0:0]intr;
+  wire irq;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire [31:0]NLW_U0_interrupt_address_UNCONNECTED;
+  wire [1:0]NLW_U0_processor_ack_out_UNCONNECTED;
+
+  (* C_ASYNC_INTR = ""-2"" *) 
+  (* C_CASCADE_MASTER = ""0"" *) 
+  (* C_DISABLE_SYNCHRONIZERS = ""0"" *) 
+  (* C_ENABLE_ASYNC = ""0"" *) 
+  (* C_EN_CASCADE_MODE = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_HAS_CIE = ""1"" *) 
+  (* C_HAS_FAST = ""0"" *) 
+  (* C_HAS_ILR = ""0"" *) 
+  (* C_HAS_IPR = ""1"" *) 
+  (* C_HAS_IVR = ""1"" *) 
+  (* C_HAS_SIE = ""1"" *) 
+  (* C_INSTANCE = ""design_1_axi_intc_0_0"" *) 
+  (* C_IRQ_ACTIVE = ""1\'b1"" *) 
+  (* C_IRQ_IS_LEVEL = ""1"" *) 
+  (* C_IVAR_RESET_VALUE = ""16"" *) 
+  (* C_KIND_OF_EDGE = ""-1"" *) 
+  (* C_KIND_OF_INTR = ""-2"" *) 
+  (* C_KIND_OF_LVL = ""-1"" *) 
+  (* C_MB_CLK_NOT_CONNECTED = ""1"" *) 
+  (* C_NUM_INTR_INPUTS = ""1"" *) 
+  (* C_NUM_SW_INTR = ""0"" *) 
+  (* C_NUM_SYNC_FF = ""2"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* hdl = ""VHDL"" *) 
+  (* imp_netlist = ""TRUE"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  (* iptype = ""PERIPHERAL"" *) 
+  (* run_ngcbuild = ""TRUE"" *) 
+  (* style = ""HDL"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_intc U0
+       (.interrupt_address(NLW_U0_interrupt_address_UNCONNECTED[31:0]),
+        .interrupt_address_in({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .intr(intr),
+        .irq(irq),
+        .irq_in(1\'b0),
+        .processor_ack({1\'b0,1\'b0}),
+        .processor_ack_out(NLW_U0_processor_ack_out_UNCONNECTED[1:0]),
+        .processor_clk(1\'b0),
+        .processor_rst(1\'b0),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_intc_core
+   (ier,
+    ipr,
+    p_0_in,
+    ivr,
+    \\REG_GEN[0].isr_reg[0]_0 ,
+    p_0_in_0,
+    isr,
+    sie,
+    cie,
+    mer,
+    irq,
+    s_axi_aclk,
+    Bus_RNW_reg_reg,
+    Bus_RNW_reg_reg_0,
+    Bus_RNW_reg_reg_1,
+    \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ,
+    \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ,
+    s_axi_aresetn,
+    s_axi_wdata,
+    p_15_in,
+    Bus_RNW_reg,
+    p_17_in,
+    intr);
+  output ier;
+  output [0:0]ipr;
+  output p_0_in;
+  output ivr;
+  output \\REG_GEN[0].isr_reg[0]_0 ;
+  output p_0_in_0;
+  output isr;
+  output sie;
+  output cie;
+  output mer;
+  output irq;
+  input s_axi_aclk;
+  input Bus_RNW_reg_reg;
+  input Bus_RNW_reg_reg_0;
+  input Bus_RNW_reg_reg_1;
+  input \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
+  input \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
+  input s_axi_aresetn;
+  input [0:0]s_axi_wdata;
+  input p_15_in;
+  input Bus_RNW_reg;
+  input p_17_in;
+  input [0:0]intr;
+
+  wire Bus_RNW_reg;
+  wire Bus_RNW_reg_reg;
+  wire Bus_RNW_reg_reg_0;
+  wire Bus_RNW_reg_reg_1;
+  wire \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
+  wire \\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
+  wire \\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ;
+  wire \\IPR_GEN.ipr[0]_i_1_n_0 ;
+  wire \\IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_i_1_n_0 ;
+  wire \\REG_GEN[0].ier[0]_i_2_n_0 ;
+  wire \\REG_GEN[0].isr[0]_i_1_n_0 ;
+  wire \\REG_GEN[0].isr[0]_i_2_n_0 ;
+  wire \\REG_GEN[0].isr_reg[0]_0 ;
+  wire cie;
+  wire hw_intr;
+  wire ier;
+  wire [0:0]intr;
+  wire [0:0]ipr;
+  wire irq;
+  wire isr;
+  wire ivr;
+  wire mer;
+  wire p_0_in;
+  wire p_0_in_0;
+  wire p_15_in;
+  wire p_17_in;
+  wire p_1_in;
+  wire p_8_out;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire [0:0]s_axi_wdata;
+  wire sie;
+
+  FDRE \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ),
+        .Q(cie),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT4 #(
+    .INIT(16\'h00E0)) 
+    \\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1 
+       (.I0(hw_intr),
+        .I1(intr),
+        .I2(s_axi_aresetn),
+        .I3(\\REG_GEN[0].isr_reg[0]_0 ),
+        .O(\\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ));
+  FDRE \\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ),
+        .Q(hw_intr),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\IPR_GEN.ipr[0]_i_1 
+       (.I0(ier),
+        .I1(isr),
+        .O(\\IPR_GEN.ipr[0]_i_1_n_0 ));
+  FDRE \\IPR_GEN.ipr_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\IPR_GEN.ipr[0]_i_1_n_0 ),
+        .Q(ipr),
+        .R(p_0_in));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT4 #(
+    .INIT(16\'hE000)) 
+    \\IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_i_1 
+       (.I0(irq),
+        .I1(mer),
+        .I2(ipr),
+        .I3(s_axi_aresetn),
+        .O(\\IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_i_1_n_0 ));
+  FDRE \\IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_reg 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_i_1_n_0 ),
+        .Q(irq),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h7)) 
+    \\IVR_GEN.ivr[0]_i_1 
+       (.I0(isr),
+        .I1(ier),
+        .O(p_1_in));
+  FDSE \\IVR_GEN.ivr_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(ivr),
+        .S(p_0_in));
+  FDRE \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_reg),
+        .Q(\\REG_GEN[0].isr_reg[0]_0 ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAA8A0080)) 
+    \\REG_GEN[0].ier[0]_i_1 
+       (.I0(\\REG_GEN[0].ier[0]_i_2_n_0 ),
+        .I1(s_axi_wdata),
+        .I2(p_15_in),
+        .I3(Bus_RNW_reg),
+        .I4(ier),
+        .I5(sie),
+        .O(p_8_out));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\REG_GEN[0].ier[0]_i_2 
+       (.I0(s_axi_aresetn),
+        .I1(cie),
+        .O(\\REG_GEN[0].ier[0]_i_2_n_0 ));
+  FDRE \\REG_GEN[0].ier_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_8_out),
+        .Q(ier),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\REG_GEN[0].isr[0]_i_1 
+       (.I0(\\REG_GEN[0].isr[0]_i_2_n_0 ),
+        .I1(s_axi_aresetn),
+        .I2(\\REG_GEN[0].isr_reg[0]_0 ),
+        .O(\\REG_GEN[0].isr[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAFACAFAFA0ACA0A0)) 
+    \\REG_GEN[0].isr[0]_i_2 
+       (.I0(hw_intr),
+        .I1(s_axi_wdata),
+        .I2(p_0_in_0),
+        .I3(Bus_RNW_reg),
+        .I4(p_17_in),
+        .I5(isr),
+        .O(\\REG_GEN[0].isr[0]_i_2_n_0 ));
+  FDRE \\REG_GEN[0].isr_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\REG_GEN[0].isr[0]_i_1_n_0 ),
+        .Q(isr),
+        .R(1\'b0));
+  FDRE \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_reg_1),
+        .Q(sie),
+        .R(1\'b0));
+  FDRE \\mer_int_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ),
+        .Q(mer),
+        .R(p_0_in));
+  FDRE \\mer_int_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Bus_RNW_reg_reg_0),
+        .Q(p_0_in_0),
+        .R(p_0_in));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    rst_i_1
+       (.I0(s_axi_aresetn),
+        .O(p_0_in));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
+   (p_15_in,
+    p_17_in,
+    s_axi_rresp,
+    \\mer_int_reg[1] ,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_bresp,
+    s_axi_wready,
+    s_axi_arready,
+    ip2bus_wrack_prev2,
+    ip2bus_rdack_prev2,
+    Or128_vec2stdlogic19_out,
+    \\mer_int_reg[1]_0 ,
+    \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
+    \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
+    \\mer_int_reg[0] ,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
+    ip2bus_wrack_int_d1_reg,
+    s_axi_rdata,
+    p_0_in,
+    s_axi_aclk,
+    s_axi_arvalid,
+    ip2bus_wrack,
+    s_axi_aresetn,
+    ip2bus_rdack,
+    s_axi_rready,
+    s_axi_bready,
+    s_axi_wvalid,
+    s_axi_awvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    ier,
+    ipr,
+    ivr,
+    p_0_in_0,
+    mer,
+    isr,
+    ip2bus_wrack_int_d1,
+    ip2bus_rdack_int_d1,
+    s_axi_wstrb,
+    s_axi_wdata,
+    sie,
+    cie,
+    \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 );
+  output p_15_in;
+  output p_17_in;
+  output [0:0]s_axi_rresp;
+  output \\mer_int_reg[1] ;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output [0:0]s_axi_bresp;
+  output s_axi_wready;
+  output s_axi_arready;
+  output ip2bus_wrack_prev2;
+  output ip2bus_rdack_prev2;
+  output Or128_vec2stdlogic19_out;
+  output \\mer_int_reg[1]_0 ;
+  output \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  output \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  output \\mer_int_reg[0] ;
+  output \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  output ip2bus_wrack_int_d1_reg;
+  output [2:0]s_axi_rdata;
+  input p_0_in;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input ip2bus_wrack;
+  input s_axi_aresetn;
+  input ip2bus_rdack;
+  input s_axi_rready;
+  input s_axi_bready;
+  input s_axi_wvalid;
+  input s_axi_awvalid;
+  input [6:0]s_axi_araddr;
+  input [6:0]s_axi_awaddr;
+  input ier;
+  input [0:0]ipr;
+  input ivr;
+  input p_0_in_0;
+  input mer;
+  input isr;
+  input ip2bus_wrack_int_d1;
+  input ip2bus_rdack_int_d1;
+  input [3:0]s_axi_wstrb;
+  input [1:0]s_axi_wdata;
+  input sie;
+  input cie;
+  input \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+
+  wire \\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
+  wire \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire [31:0]IP2Bus_Data;
+  wire Or128_vec2stdlogic19_out;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
+  wire \\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
+  wire \\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
+  wire [8:2]bus2ip_addr;
+  wire \\bus2ip_addr_i[2]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[3]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[4]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[5]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[6]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[7]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_2_n_0 ;
+  wire bus2ip_rnw_i06_out;
+  wire bus2ip_rnw_i_reg_n_0;
+  wire cie;
+  wire ier;
+  wire ip2bus_error;
+  wire ip2bus_rdack;
+  wire ip2bus_rdack_int_d1;
+  wire ip2bus_rdack_prev2;
+  wire ip2bus_wrack;
+  wire ip2bus_wrack_int_d1;
+  wire ip2bus_wrack_int_d1_reg;
+  wire ip2bus_wrack_prev2;
+  wire [0:0]ipr;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_read_i_2_n_0;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire isr;
+  wire ivr;
+  wire mer;
+  wire \\mer_int_reg[0] ;
+  wire \\mer_int_reg[1] ;
+  wire \\mer_int_reg[1]_0 ;
+  wire p_0_in;
+  wire p_0_in_0;
+  wire p_15_in;
+  wire p_17_in;
+  wire [3:0]plusOp;
+  wire rst;
+  wire s_axi_aclk;
+  wire [6:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [6:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [0:0]s_axi_bresp;
+  wire \\s_axi_bresp_i[1]_i_1_n_0 ;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [2:0]s_axi_rdata;
+  wire s_axi_rdata_i;
+  wire \\s_axi_rdata_i[0]_i_3_n_0 ;
+  wire \\s_axi_rdata_i[0]_i_4_n_0 ;
+  wire \\s_axi_rdata_i[1]_i_2_n_0 ;
+  wire \\s_axi_rdata_i[31]_i_5_n_0 ;
+  wire s_axi_rready;
+  wire [0:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire [1:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire sie;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire \\state[0]_i_1_n_0 ;
+  wire \\state[0]_i_2_n_0 ;
+  wire \\state[1]_i_1_n_0 ;
+  wire \\state[1]_i_2_n_0 ;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[1]),
+        .I1(state[0]),
+        .O(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT4 #(
+    .INIT(16\'h6AAA)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(\\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
+       (.\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
+        .D({IP2Bus_Data[31],IP2Bus_Data[1:0]}),
+        .\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .\\IVR_GEN.ivr_reg[0] (\\s_axi_rdata_i[31]_i_5_n_0 ),
+        .\\IVR_GEN.ivr_reg[0]_0 (\\s_axi_rdata_i[1]_i_2_n_0 ),
+        .Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
+        .Q(start2),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ),
+        .\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (\\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
+        .\\REG_GEN[0].ier_reg[0] (\\s_axi_rdata_i[0]_i_3_n_0 ),
+        .\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
+        .\\bus2ip_addr_i_reg[5] (\\s_axi_rdata_i[0]_i_4_n_0 ),
+        .\\bus2ip_addr_i_reg[8] (bus2ip_addr),
+        .bus2ip_rnw_i_reg(bus2ip_rnw_i_reg_n_0),
+        .cie(cie),
+        .ip2bus_rdack(ip2bus_rdack),
+        .ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
+        .ip2bus_rdack_prev2(ip2bus_rdack_prev2),
+        .ip2bus_wrack(ip2bus_wrack),
+        .ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
+        .ip2bus_wrack_int_d1_reg(ip2bus_wrack_int_d1_reg),
+        .ip2bus_wrack_prev2(ip2bus_wrack_prev2),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .mer(mer),
+        .\\mer_int_reg[0] (\\mer_int_reg[0] ),
+        .\\mer_int_reg[1] (\\mer_int_reg[1] ),
+        .\\mer_int_reg[1]_0 (\\mer_int_reg[1]_0 ),
+        .p_0_in_0(p_0_in_0),
+        .p_15_in(p_15_in),
+        .p_17_in(p_17_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_wdata(s_axi_wdata),
+        .sie(sie));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[0]),
+        .O(\\bus2ip_addr_i[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[1]),
+        .O(\\bus2ip_addr_i[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[4]_i_1 
+       (.I0(s_axi_araddr[2]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[2]),
+        .O(\\bus2ip_addr_i[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[5]_i_1 
+       (.I0(s_axi_araddr[3]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[3]),
+        .O(\\bus2ip_addr_i[5]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[6]_i_1 
+       (.I0(s_axi_araddr[4]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[4]),
+        .O(\\bus2ip_addr_i[6]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[7]_i_1 
+       (.I0(s_axi_araddr[5]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[5]),
+        .O(\\bus2ip_addr_i[7]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h000000EA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_awvalid),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(\\bus2ip_addr_i[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFEF0020)) 
+    \\bus2ip_addr_i[8]_i_2 
+       (.I0(s_axi_araddr[6]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(s_axi_awaddr[6]),
+        .O(\\bus2ip_addr_i[8]_i_2_n_0 ));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[2]_i_1_n_0 ),
+        .Q(bus2ip_addr[2]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[3]_i_1_n_0 ),
+        .Q(bus2ip_addr[3]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[4]_i_1_n_0 ),
+        .Q(bus2ip_addr[4]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[5]_i_1_n_0 ),
+        .Q(bus2ip_addr[5]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[6]_i_1_n_0 ),
+        .Q(bus2ip_addr[6]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[7]_i_1_n_0 ),
+        .Q(bus2ip_addr[7]),
+        .R(rst));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[8]_i_2_n_0 ),
+        .Q(bus2ip_addr[8]),
+        .R(rst));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    bus2ip_rnw_i_i_1
+       (.I0(state[1]),
+        .I1(s_axi_arvalid),
+        .I2(state[0]),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(bus2ip_rnw_i06_out),
+        .Q(bus2ip_rnw_i_reg_n_0),
+        .R(rst));
+  LUT4 #(
+    .INIT(16\'h2F20)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state[1]),
+        .I2(is_read_i_2_n_0),
+        .I3(is_read),
+        .O(is_read_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hAA80808055555555)) 
+    is_read_i_2
+       (.I0(state[0]),
+        .I1(s_axi_bready),
+        .I2(s_axi_bvalid),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .I5(state[1]),
+        .O(is_read_i_2_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(rst));
+  LUT6 #(
+    .INIT(64\'h0040FFFF00400000)) 
+    is_write_i_1
+       (.I0(state[1]),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_awvalid),
+        .I3(s_axi_arvalid),
+        .I4(is_read_i_2_n_0),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(rst));
+  FDRE rst_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_in),
+        .Q(rst),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAEAAAAAAAA)) 
+    s_axi_arready_INST_0
+       (.I0(ip2bus_rdack),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I5(is_read),
+        .O(s_axi_arready));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\s_axi_bresp_i[1]_i_1 
+       (.I0(ip2bus_error),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bresp),
+        .O(\\s_axi_bresp_i[1]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_bresp_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\s_axi_bresp_i[1]_i_1_n_0 ),
+        .Q(s_axi_bresp),
+        .R(rst));
+  LUT5 #(
+    .INIT(32\'h5D550C00)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_bready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_wready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(rst));
+  LUT6 #(
+    .INIT(64\'hFFFFFFDDFFFF0FFF)) 
+    \\s_axi_rdata_i[0]_i_3 
+       (.I0(ier),
+        .I1(bus2ip_addr[5]),
+        .I2(ipr),
+        .I3(bus2ip_addr[2]),
+        .I4(bus2ip_addr[4]),
+        .I5(bus2ip_addr[3]),
+        .O(\\s_axi_rdata_i[0]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'hBFFFFEFEBFFFFFFF)) 
+    \\s_axi_rdata_i[0]_i_4 
+       (.I0(bus2ip_addr[5]),
+        .I1(bus2ip_addr[3]),
+        .I2(bus2ip_addr[4]),
+        .I3(mer),
+        .I4(bus2ip_addr[2]),
+        .I5(isr),
+        .O(\\s_axi_rdata_i[0]_i_4_n_0 ));
+  LUT6 #(
+    .INIT(64\'hCDFDFFFFFFFF3F3F)) 
+    \\s_axi_rdata_i[1]_i_2 
+       (.I0(ivr),
+        .I1(bus2ip_addr[5]),
+        .I2(bus2ip_addr[2]),
+        .I3(p_0_in_0),
+        .I4(bus2ip_addr[3]),
+        .I5(bus2ip_addr[4]),
+        .O(\\s_axi_rdata_i[1]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[31]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(s_axi_rdata_i));
+  LUT5 #(
+    .INIT(32\'hFCFFFF7F)) 
+    \\s_axi_rdata_i[31]_i_5 
+       (.I0(ivr),
+        .I1(bus2ip_addr[3]),
+        .I2(bus2ip_addr[4]),
+        .I3(bus2ip_addr[2]),
+        .I4(bus2ip_addr[5]),
+        .O(\\s_axi_rdata_i[31]_i_5_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(IP2Bus_Data[0]),
+        .Q(s_axi_rdata[0]),
+        .R(rst));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(IP2Bus_Data[1]),
+        .Q(s_axi_rdata[1]),
+        .R(rst));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(IP2Bus_Data[31]),
+        .Q(s_axi_rdata[2]),
+        .R(rst));
+  LUT5 #(
+    .INIT(32\'h070F0F0F)) 
+    \\s_axi_rresp_i[1]_i_1 
+       (.I0(s_axi_wstrb[1]),
+        .I1(s_axi_wstrb[2]),
+        .I2(bus2ip_rnw_i_reg_n_0),
+        .I3(s_axi_wstrb[0]),
+        .I4(s_axi_wstrb[3]),
+        .O(ip2bus_error));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rresp_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(ip2bus_error),
+        .Q(s_axi_rresp),
+        .R(rst));
+  LUT5 #(
+    .INIT(32\'h5D550C00)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_rready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_arready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(rst));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAEAAAAAAAA)) 
+    s_axi_wready_INST_0
+       (.I0(ip2bus_wrack),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I5(is_write_reg_n_0),
+        .O(s_axi_wready));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT5 #(
+    .INIT(32\'h00000F08)) 
+    start2_i_1
+       (.I0(s_axi_wvalid),
+        .I1(s_axi_awvalid),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(state[1]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(rst));
+  LUT5 #(
+    .INIT(32\'hF4F4FFF0)) 
+    \\state[0]_i_1 
+       (.I0(state[0]),
+        .I1(s_axi_wready),
+        .I2(\\state[0]_i_2_n_0 ),
+        .I3(s_axi_arvalid),
+        .I4(state[1]),
+        .O(\\state[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h557F7F7F00000000)) 
+    \\state[0]_i_2 
+       (.I0(state[1]),
+        .I1(s_axi_rvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_bvalid),
+        .I4(s_axi_bready),
+        .I5(state[0]),
+        .O(\\state[0]_i_2_n_0 ));
+  LUT5 #(
+    .INIT(32\'h22CFEECF)) 
+    \\state[1]_i_1 
+       (.I0(s_axi_arready),
+        .I1(state[1]),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(state[0]),
+        .I4(\\state[1]_i_3_n_0 ),
+        .O(\\state[1]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT3 #(
+    .INIT(8\'hBF)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_wvalid),
+        .O(\\state[1]_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hF888)) 
+    \\state[1]_i_3 
+       (.I0(s_axi_rvalid),
+        .I1(s_axi_rready),
+        .I2(s_axi_bvalid),
+        .I3(s_axi_bready),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\state[0]_i_1_n_0 ),
+        .Q(state[0]),
+        .R(rst));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\state[1]_i_1_n_0 ),
+        .Q(state[1]),
+        .R(rst));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------'b""
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1'b1;
+\tPRLD_int = 1'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1'b0;
+\tPRLD_int = 1'b0;
+    end
+
+    initial begin
+\tGTS_int = 1'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1'b0;
+    end
+
+endmodule
+`endif
+"
+"// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Response Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   b_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_b_atc #
+  (
+   parameter         C_FAMILY                         = ""rtl"", 
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_BUSER_WIDTH                = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_FIFO_DEPTH_LOG                 = 4
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface
+   input  wire                                  cmd_b_push,
+   input  wire                                  cmd_b_error,
+   input  wire [C_AXI_ID_WIDTH-1:0]             cmd_b_id,
+   output wire                                  cmd_b_ready,
+   output wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr,
+   output reg                                   cmd_b_full,
+   
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_BID,
+   output reg  [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                  S_AXI_BVALID,
+   input  wire                                  S_AXI_BREADY,
+
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_BID,
+   input  wire [2-1:0]                          M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]          M_AXI_BUSER,
+   input  wire                                  M_AXI_BVALID,
+   output wire                                  M_AXI_BREADY,
+   
+   // Trigger detection
+   output reg                                   ERROR_TRIGGER,
+   output reg  [C_AXI_ID_WIDTH-1:0]             ERROR_TRANSACTION_ID
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for packing levels.
+  localparam [2-1:0] C_RESP_OKAY         = 2\'b00;
+  localparam [2-1:0] C_RESP_EXOKAY       = 2\'b01;
+  localparam [2-1:0] C_RESP_SLVERROR     = 2\'b10;
+  localparam [2-1:0] C_RESP_DECERR       = 2\'b11;
+  
+  // Command FIFO settings
+  localparam C_FIFO_WIDTH                = C_AXI_ID_WIDTH + 1;
+  localparam C_FIFO_DEPTH                = 2 ** C_FIFO_DEPTH_LOG;
+    
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Command Queue.
+  reg  [C_FIFO_DEPTH_LOG-1:0]         addr_ptr;
+  reg  [C_FIFO_WIDTH-1:0]             data_srl[C_FIFO_DEPTH-1:0];
+  reg                                 cmd_b_valid;
+  wire                                cmd_b_ready_i;
+  wire                                inject_error;
+  wire [C_AXI_ID_WIDTH-1:0]           current_id;
+  
+  // Search command.
+  wire                                found_match;
+  wire                                use_match;
+  wire                                matching_id;
+  
+  // Manage valid command.
+  wire                                write_valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             updated_valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             next_valid_cmd;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         search_addr_ptr;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         collapsed_addr_ptr;
+  
+  // Pipelined data
+  reg  [C_AXI_ID_WIDTH-1:0]           M_AXI_BID_I;
+  reg  [2-1:0]                        M_AXI_BRESP_I;
+  reg  [C_AXI_BUSER_WIDTH-1:0]        M_AXI_BUSER_I;
+  reg                                 M_AXI_BVALID_I;
+  wire                                M_AXI_BREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command Queue:
+  //
+  // Keep track of depth of Queue to generate full flag.
+  // 
+  // Also generate valid to mark pressence of commands in Queue.
+  // 
+  // Maintain Queue and extract data from currently searched entry.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // SRL FIFO Pointer.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      addr_ptr <= {C_FIFO_DEPTH_LOG{1\'b1}};
+    end else begin
+      if ( cmd_b_push & ~cmd_b_ready_i ) begin
+        // Pushing data increase length/addr.
+        addr_ptr <= addr_ptr + 1;
+      end else if ( cmd_b_ready_i ) begin
+        // Collapse addr when data is popped.
+        addr_ptr <= collapsed_addr_ptr;
+      end
+    end
+  end
+  
+  // FIFO Flags.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_full  <= 1\'b0;
+      cmd_b_valid <= 1\'b0;
+    end else begin
+      if ( cmd_b_push & ~cmd_b_ready_i ) begin
+        cmd_b_full  <= ( addr_ptr == C_FIFO_DEPTH-3 );
+        cmd_b_valid <= 1\'b1;
+      end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
+        cmd_b_full  <= 1\'b0;
+        cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
+      end
+    end
+  end
+  
+  // Infere SRL for storage.
+  always @ (posedge ACLK) begin
+    if ( cmd_b_push ) begin
+      for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
+        data_srl[index+1] <= data_srl[index];
+      end
+      data_srl[0]   <= {cmd_b_error, cmd_b_id};
+    end
+  end
+  
+  // Get current transaction info.
+  assign {inject_error, current_id} = data_srl[search_addr_ptr];
+  
+  // Assign outputs.
+  assign cmd_b_addr = collapsed_addr_ptr;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Search Command Queue:
+  //
+  // Search for matching valid command in queue.
+  // 
+  // A command is found when an valid entry with correct ID is found. The queue
+  // is search from the oldest entry, i.e. from a high value.
+  // When new commands are pushed the search address has to be updated to always 
+  // start the search from the oldest available.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Handle search addr.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      search_addr_ptr <= {C_FIFO_DEPTH_LOG{1\'b1}};
+    end else begin
+      if ( cmd_b_ready_i ) begin
+        // Collapse addr when data is popped.
+        search_addr_ptr <= collapsed_addr_ptr;
+        
+      end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
+        // Skip non valid command.
+        search_addr_ptr <= search_addr_ptr - 1;
+        
+      end else if ( cmd_b_push ) begin
+        search_addr_ptr <= search_addr_ptr + 1;
+        
+      end
+    end
+  end
+  
+  // Check if searched command is valid and match ID (for existing response on MI side).
+  assign matching_id  = ( M_AXI_BID_I == current_id );
+  assign found_match  = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
+  assign use_match    = found_match & S_AXI_BREADY;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Track Used Commands:
+  //
+  // Actions that affect Valid Command:
+  // * When a new command is pushed
+  //   => Shift valid vector one step
+  // * When a command is used
+  //   => Clear corresponding valid bit
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Valid command status is updated when a command is used or a new one is pushed.
+  assign write_valid_cmd  = cmd_b_push | cmd_b_ready_i;
+  
+  // Update the used command valid bit.
+  always @ *
+  begin
+    updated_valid_cmd                   = valid_cmd;
+    updated_valid_cmd[search_addr_ptr]  = ~use_match;
+  end
+  
+  // Shift valid vector when command is pushed.
+  always @ *
+  begin
+    if ( cmd_b_push ) begin
+      next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1\'b1};
+    end else begin
+      next_valid_cmd = updated_valid_cmd;
+    end
+  end
+  
+  // Valid signals for next cycle.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      valid_cmd <= {C_FIFO_WIDTH{1\'b0}};
+    end else if ( write_valid_cmd ) begin
+      valid_cmd <= next_valid_cmd;
+    end
+  end
+  
+  // Detect oldest available command in Queue.
+  always @ *
+  begin
+    // Default to empty.
+    collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1\'b1}};
+    
+    for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
+      if ( next_valid_cmd[index] ) begin
+        collapsed_addr_ptr = index;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Pipe incoming data:
+  // 
+  // The B channel is piped to improve timing and avoid impact in search
+  // mechanism due to late arriving signals.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Clock data.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      M_AXI_BID_I     <= {C_AXI_ID_WIDTH{1\'b0}};
+      M_AXI_BRESP_I   <= 2\'b00;
+      M_AXI_BUSER_I   <= {C_AXI_BUSER_WIDTH{1\'b0}};
+      M_AXI_BVALID_I  <= 1\'b0;
+    end else begin
+      if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
+        M_AXI_BVALID_I  <= 1\'b0;
+      end
+      if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
+        M_AXI_BID_I     <= M_AXI_BID;
+        M_AXI_BRESP_I   <= M_AXI_BRESP;
+        M_AXI_BUSER_I   <= M_AXI_BUSER;
+        M_AXI_BVALID_I  <= 1\'b1;
+      end
+    end
+  end
+  
+  // Generate ready to get new transaction.
+  assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Inject Error:
+  //
+  // BRESP is modified according to command information.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Inject error in response.
+  always @ *
+  begin
+    if ( inject_error ) begin
+      S_AXI_BRESP = C_RESP_SLVERROR;
+    end else begin
+      S_AXI_BRESP = M_AXI_BRESP_I;
+    end
+  end
+  
+  // Handle interrupt generation.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      ERROR_TRIGGER        <= 1\'b0;
+      ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1\'b0}};
+    end else begin
+      if ( inject_error & cmd_b_ready_i ) begin
+        ERROR_TRIGGER        <= 1\'b1;
+        ERROR_TRANSACTION_ID <= M_AXI_BID_I;
+      end else begin
+        ERROR_TRIGGER        <= 1\'b0;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Response is passed forward when a matching entry has been found in queue.
+  // Both ready and valid are set when the command is completed.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign S_AXI_BVALID   = M_AXI_BVALID_I & cmd_b_valid & found_match;
+  
+  // Return ready with push back.
+  assign M_AXI_BREADY_I = cmd_b_valid & use_match;
+  
+  // Command has been handled.
+  assign cmd_b_ready_i  = M_AXI_BVALID_I & cmd_b_valid & use_match;
+  assign cmd_b_ready    = cmd_b_ready_i;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Write Response Propagation:
+  //
+  // All information is simply forwarded on from MI- to SI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign S_AXI_BID    = M_AXI_BID_I;
+  assign S_AXI_BUSER  = M_AXI_BUSER_I;
+  
+  
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:06 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_1_0_sim_netlist.v
+// Design      : design_1_axi_gpio_1_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
+   (D,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    ip2bus_rdack_i,
+    ip2bus_wrack_i_D1_reg,
+    gpio_io_o,
+    gpio_io_t,
+    Q,
+    bus2ip_rnw_i_reg,
+    \\Not_Dual.gpio_Data_In_reg[3]_0 ,
+    s_axi_aclk,
+    \\Not_Dual.gpio_Data_In_reg[2]_0 ,
+    \\Not_Dual.gpio_Data_In_reg[1]_0 ,
+    GPIO_DBus_i,
+    SS,
+    bus2ip_rnw,
+    bus2ip_cs,
+    gpio_io_i,
+    E,
+    \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
+    rst_reg);
+  output [3:0]D;
+  output GPIO_xferAck_i;
+  output gpio_xferAck_Reg;
+  output ip2bus_rdack_i;
+  output ip2bus_wrack_i_D1_reg;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  output [3:0]Q;
+  input bus2ip_rnw_i_reg;
+  input \\Not_Dual.gpio_Data_In_reg[3]_0 ;
+  input s_axi_aclk;
+  input \\Not_Dual.gpio_Data_In_reg[2]_0 ;
+  input \\Not_Dual.gpio_Data_In_reg[1]_0 ;
+  input [0:0]GPIO_DBus_i;
+  input [0:0]SS;
+  input bus2ip_rnw;
+  input bus2ip_cs;
+  input [3:0]gpio_io_i;
+  input [0:0]E;
+  input [3:0]\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  input [0:0]rst_reg;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  wire \\Not_Dual.gpio_Data_In_reg[1]_0 ;
+  wire \\Not_Dual.gpio_Data_In_reg[2]_0 ;
+  wire \\Not_Dual.gpio_Data_In_reg[3]_0 ;
+  wire [3:0]Q;
+  wire [0:0]SS;
+  wire bus2ip_cs;
+  wire bus2ip_rnw;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio_io_i;
+  wire [0:3]gpio_io_i_d2;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire iGPIO_xferAck;
+  wire ip2bus_rdack_i;
+  wire ip2bus_wrack_i_D1_reg;
+  wire [0:0]rst_reg;
+  wire s_axi_aclk;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \\Not_Dual.INPUT_DOUBLE_REGS3 
+       (.gpio_io_i(gpio_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
+  FDRE \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus_i),
+        .Q(D[3]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[1]_0 ),
+        .Q(D[2]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[2]_0 ),
+        .Q(D[1]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[3]_0 ),
+        .Q(D[0]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.gpio_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[0]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[1]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[2]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[3]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
+        .Q(gpio_io_o[3]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
+        .Q(gpio_io_o[2]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
+        .Q(gpio_io_o[1]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
+        .Q(gpio_io_o[0]),
+        .R(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
+        .Q(gpio_io_t[3]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
+        .Q(gpio_io_t[2]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
+        .Q(gpio_io_t[1]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
+        .Q(gpio_io_t[0]),
+        .S(SS));
+  FDRE gpio_xferAck_Reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_xferAck_i),
+        .Q(gpio_xferAck_Reg),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'h02)) 
+    iGPIO_xferAck_i_1
+       (.I0(bus2ip_cs),
+        .I1(gpio_xferAck_Reg),
+        .I2(GPIO_xferAck_i),
+        .O(iGPIO_xferAck));
+  FDRE iGPIO_xferAck_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(iGPIO_xferAck),
+        .Q(GPIO_xferAck_i),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    ip2bus_rdack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_rdack_i));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    ip2bus_wrack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_wrack_i_D1_reg));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
+   (\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_arready,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_aclk,
+    rst_reg,
+    bus2ip_rnw_i_reg,
+    Q,
+    ip2bus_rdack_i_D1,
+    is_read,
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
+    ip2bus_wrack_i_D1,
+    is_write_reg,
+    \\Not_Dual.gpio_Data_In_reg[0] ,
+    gpio_io_t,
+    s_axi_wdata,
+    start2_reg,
+    s_axi_aresetn,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i);
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  input s_axi_aclk;
+  input rst_reg;
+  input bus2ip_rnw_i_reg;
+  input [2:0]Q;
+  input ip2bus_rdack_i_D1;
+  input is_read;
+  input [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  input ip2bus_wrack_i_D1;
+  input is_write_reg;
+  input [3:0]\\Not_Dual.gpio_Data_In_reg[0] ;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input start2_reg;
+  input s_axi_aresetn;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire [3:0]\\Not_Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [2:0]Q;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_write_reg;
+  wire rst_reg;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire start2_reg;
+
+  LUT5 #(
+    .INIT(32\'h000000E0)) 
+    \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1 
+       (.I0(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I1(start2_reg),
+        .I2(s_axi_aresetn),
+        .I3(s_axi_arready),
+        .I4(s_axi_wready),
+        .O(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
+  FDRE \\MEM_DECODE_GEN[0].cs_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
+        .Q(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [3]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[3]),
+        .O(GPIO_DBus_i));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [2]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[2]),
+        .O(\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [1]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[1]),
+        .O(\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ));
+  LUT4 #(
+    .INIT(16\'hFFF7)) 
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I2(gpio_xferAck_Reg),
+        .I3(GPIO_xferAck_i),
+        .O(\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_2 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [0]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[0]),
+        .O(\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAAABAA)) 
+    \\Not_Dual.gpio_Data_Out[0]_i_1 
+       (.I0(rst_reg),
+        .I1(bus2ip_rnw_i_reg),
+        .I2(Q[0]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(Q[2]),
+        .I5(Q[1]),
+        .O(E));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[0]_i_2 
+       (.I0(s_axi_wdata[3]),
+        .I1(s_axi_wdata[7]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[3]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[1]_i_1 
+       (.I0(s_axi_wdata[2]),
+        .I1(s_axi_wdata[6]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[2]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[2]_i_1 
+       (.I0(s_axi_wdata[1]),
+        .I1(s_axi_wdata[5]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[1]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[3]_i_1 
+       (.I0(s_axi_wdata[0]),
+        .I1(s_axi_wdata[4]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[0]));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAABAAAAA)) 
+    \\Not_Dual.gpio_OE[0]_i_1 
+       (.I0(rst_reg),
+        .I1(bus2ip_rnw_i_reg),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[0]),
+        .I5(Q[1]),
+        .O(\\Not_Dual.gpio_OE_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAEAAAA)) 
+    s_axi_arready_INST_0
+       (.I0(ip2bus_rdack_i_D1),
+        .I1(is_read),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
+        .I5(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
+        .O(s_axi_arready));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAEAAAA)) 
+    s_axi_wready_INST_0
+       (.I0(ip2bus_wrack_i_D1),
+        .I1(is_write_reg),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
+        .I5(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
+        .O(s_axi_wready));
+endmodule
+
+(* C_ALL_INPUTS = ""0"" *) (* C_ALL_INPUTS_2 = ""0"" *) (* C_ALL_OUTPUTS = ""0"" *) 
+(* C_ALL_OUTPUTS_2 = ""0"" *) (* C_DOUT_DEFAULT = ""0"" *) (* C_DOUT_DEFAULT_2 = ""0"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_GPIO2_WIDTH = ""32"" *) (* C_GPIO_WIDTH = ""4"" *) 
+(* C_INTERRUPT_PRESENT = ""0"" *) (* C_IS_DUAL = ""0"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* C_TRI_DEFAULT = ""-1"" *) (* C_TRI_DEFAULT_2 = ""-1"" *) 
+(* downgradeipidentifiedwarnings = ""yes"" *) (* ip_group = ""LOGICORE"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_i,
+    gpio2_io_o,
+    gpio2_io_t);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rst"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* sigis = ""INTR_LEVEL_HIGH"" *) output ip2intc_irpt;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  input [31:0]gpio2_io_i;
+  output [31:0]gpio2_io_o;
+  output [31:0]gpio2_io_t;
+
+  wire \\<const0> ;
+  wire \\<const1> ;
+  wire AXI_LITE_IPIF_I_n_10;
+  wire AXI_LITE_IPIF_I_n_11;
+  wire AXI_LITE_IPIF_I_n_12;
+  wire AXI_LITE_IPIF_I_n_17;
+  wire AXI_LITE_IPIF_I_n_6;
+  wire AXI_LITE_IPIF_I_n_7;
+  wire [0:3]DBus_Reg;
+  wire [28:28]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [0:3]gpio_Data_In;
+  wire gpio_core_1_n_7;
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [28:31]ip2bus_data;
+  wire [28:31]ip2bus_data_i_D1;
+  wire ip2bus_rdack_i;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rst"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  assign gpio2_io_o[31] = \\<const0> ;
+  assign gpio2_io_o[30] = \\<const0> ;
+  assign gpio2_io_o[29] = \\<const0> ;
+  assign gpio2_io_o[28] = \\<const0> ;
+  assign gpio2_io_o[27] = \\<const0> ;
+  assign gpio2_io_o[26] = \\<const0> ;
+  assign gpio2_io_o[25] = \\<const0> ;
+  assign gpio2_io_o[24] = \\<const0> ;
+  assign gpio2_io_o[23] = \\<const0> ;
+  assign gpio2_io_o[22] = \\<const0> ;
+  assign gpio2_io_o[21] = \\<const0> ;
+  assign gpio2_io_o[20] = \\<const0> ;
+  assign gpio2_io_o[19] = \\<const0> ;
+  assign gpio2_io_o[18] = \\<const0> ;
+  assign gpio2_io_o[17] = \\<const0> ;
+  assign gpio2_io_o[16] = \\<const0> ;
+  assign gpio2_io_o[15] = \\<const0> ;
+  assign gpio2_io_o[14] = \\<const0> ;
+  assign gpio2_io_o[13] = \\<const0> ;
+  assign gpio2_io_o[12] = \\<const0> ;
+  assign gpio2_io_o[11] = \\<const0> ;
+  assign gpio2_io_o[10] = \\<const0> ;
+  assign gpio2_io_o[9] = \\<const0> ;
+  assign gpio2_io_o[8] = \\<const0> ;
+  assign gpio2_io_o[7] = \\<const0> ;
+  assign gpio2_io_o[6] = \\<const0> ;
+  assign gpio2_io_o[5] = \\<const0> ;
+  assign gpio2_io_o[4] = \\<const0> ;
+  assign gpio2_io_o[3] = \\<const0> ;
+  assign gpio2_io_o[2] = \\<const0> ;
+  assign gpio2_io_o[1] = \\<const0> ;
+  assign gpio2_io_o[0] = \\<const0> ;
+  assign gpio2_io_t[31] = \\<const1> ;
+  assign gpio2_io_t[30] = \\<const1> ;
+  assign gpio2_io_t[29] = \\<const1> ;
+  assign gpio2_io_t[28] = \\<const1> ;
+  assign gpio2_io_t[27] = \\<const1> ;
+  assign gpio2_io_t[26] = \\<const1> ;
+  assign gpio2_io_t[25] = \\<const1> ;
+  assign gpio2_io_t[24] = \\<const1> ;
+  assign gpio2_io_t[23] = \\<const1> ;
+  assign gpio2_io_t[22] = \\<const1> ;
+  assign gpio2_io_t[21] = \\<const1> ;
+  assign gpio2_io_t[20] = \\<const1> ;
+  assign gpio2_io_t[19] = \\<const1> ;
+  assign gpio2_io_t[18] = \\<const1> ;
+  assign gpio2_io_t[17] = \\<const1> ;
+  assign gpio2_io_t[16] = \\<const1> ;
+  assign gpio2_io_t[15] = \\<const1> ;
+  assign gpio2_io_t[14] = \\<const1> ;
+  assign gpio2_io_t[13] = \\<const1> ;
+  assign gpio2_io_t[12] = \\<const1> ;
+  assign gpio2_io_t[11] = \\<const1> ;
+  assign gpio2_io_t[10] = \\<const1> ;
+  assign gpio2_io_t[9] = \\<const1> ;
+  assign gpio2_io_t[8] = \\<const1> ;
+  assign gpio2_io_t[7] = \\<const1> ;
+  assign gpio2_io_t[6] = \\<const1> ;
+  assign gpio2_io_t[5] = \\<const1> ;
+  assign gpio2_io_t[4] = \\<const1> ;
+  assign gpio2_io_t[3] = \\<const1> ;
+  assign gpio2_io_t[2] = \\<const1> ;
+  assign gpio2_io_t[1] = \\<const1> ;
+  assign gpio2_io_t[0] = \\<const1> ;
+  assign ip2intc_irpt = \\<const0> ;
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\<const0> ;
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\<const0> ;
+  assign s_axi_rdata[30] = \\<const0> ;
+  assign s_axi_rdata[29] = \\<const0> ;
+  assign s_axi_rdata[28] = \\<const0> ;
+  assign s_axi_rdata[27] = \\<const0> ;
+  assign s_axi_rdata[26] = \\<const0> ;
+  assign s_axi_rdata[25] = \\<const0> ;
+  assign s_axi_rdata[24] = \\<const0> ;
+  assign s_axi_rdata[23] = \\<const0> ;
+  assign s_axi_rdata[22] = \\<const0> ;
+  assign s_axi_rdata[21] = \\<const0> ;
+  assign s_axi_rdata[20] = \\<const0> ;
+  assign s_axi_rdata[19] = \\<const0> ;
+  assign s_axi_rdata[18] = \\<const0> ;
+  assign s_axi_rdata[17] = \\<const0> ;
+  assign s_axi_rdata[16] = \\<const0> ;
+  assign s_axi_rdata[15] = \\<const0> ;
+  assign s_axi_rdata[14] = \\<const0> ;
+  assign s_axi_rdata[13] = \\<const0> ;
+  assign s_axi_rdata[12] = \\<const0> ;
+  assign s_axi_rdata[11] = \\<const0> ;
+  assign s_axi_rdata[10] = \\<const0> ;
+  assign s_axi_rdata[9] = \\<const0> ;
+  assign s_axi_rdata[8] = \\<const0> ;
+  assign s_axi_rdata[7] = \\<const0> ;
+  assign s_axi_rdata[6] = \\<const0> ;
+  assign s_axi_rdata[5] = \\<const0> ;
+  assign s_axi_rdata[4] = \\<const0> ;
+  assign s_axi_rdata[3:0] = \\^s_axi_rdata [3:0];
+  assign s_axi_rresp[1] = \\<const0> ;
+  assign s_axi_rresp[0] = \\<const0> ;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
+       (.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3]}),
+        .E(AXI_LITE_IPIF_I_n_6),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_17),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_10),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_11),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_12),
+        .\\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] ({ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(\\^s_axi_rdata ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata({s_axi_wdata[31:28],s_axi_wdata[3:0]}),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+  GND GND
+       (.G(\\<const0> ));
+  VCC VCC
+       (.P(\\<const1> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
+       (.D({ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
+        .E(AXI_LITE_IPIF_I_n_6),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3]}),
+        .\\Not_Dual.gpio_Data_In_reg[1]_0 (AXI_LITE_IPIF_I_n_10),
+        .\\Not_Dual.gpio_Data_In_reg[2]_0 (AXI_LITE_IPIF_I_n_11),
+        .\\Not_Dual.gpio_Data_In_reg[3]_0 (AXI_LITE_IPIF_I_n_12),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .SS(bus2ip_reset),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_rnw(bus2ip_rnw),
+        .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_17),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i(ip2bus_rdack_i),
+        .ip2bus_wrack_i_D1_reg(gpio_core_1_n_7),
+        .rst_reg(AXI_LITE_IPIF_I_n_7),
+        .s_axi_aclk(s_axi_aclk));
+  FDRE \\ip2bus_data_i_D1_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[28]),
+        .Q(ip2bus_data_i_D1[28]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[29]),
+        .Q(ip2bus_data_i_D1[29]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[30]),
+        .Q(ip2bus_data_i_D1[30]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[31]),
+        .Q(ip2bus_data_i_D1[31]),
+        .R(bus2ip_reset));
+  FDRE ip2bus_rdack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_i),
+        .Q(ip2bus_rdack_i_D1),
+        .R(bus2ip_reset));
+  FDRE ip2bus_wrack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_core_1_n_7),
+        .Q(ip2bus_wrack_i_D1),
+        .R(bus2ip_reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
+   (bus2ip_reset,
+    bus2ip_rnw,
+    bus2ip_cs,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_aresetn,
+    s_axi_rready,
+    s_axi_bready,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    Q,
+    gpio_io_t,
+    s_axi_wdata,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output bus2ip_reset;
+  output bus2ip_rnw;
+  output bus2ip_cs;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [2:0]s_axi_araddr;
+  input [2:0]s_axi_awaddr;
+  input s_axi_aresetn;
+  input s_axi_rready;
+  input s_axi_bready;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input [3:0]Q;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [3:0]Q;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
+       (.D(D),
+        .E(E),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ),
+        .\\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw),
+        .\\Not_Dual.gpio_OE_reg[0] (\\Not_Dual.gpio_OE_reg[0] ),
+        .Q(Q),
+        .SR(bus2ip_reset),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] (\\ip2bus_data_i_D1_reg[28] ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
+   (scndry_vect_out,
+    gpio_io_i,
+    s_axi_aclk);
+  output [3:0]scndry_vect_out;
+  input [3:0]gpio_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_gpio_1_0,axi_gpio,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_gpio,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_I"" *) input [3:0]gpio_io_i;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_O"" *) output [3:0]gpio_io_o;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_T"" *) output [3:0]gpio_io_t;
+
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire NLW_U0_ip2intc_irpt_UNCONNECTED;
+  wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
+  wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
+
+  (* C_ALL_INPUTS = ""0"" *) 
+  (* C_ALL_INPUTS_2 = ""0"" *) 
+  (* C_ALL_OUTPUTS = ""0"" *) 
+  (* C_ALL_OUTPUTS_2 = ""0"" *) 
+  (* C_DOUT_DEFAULT = ""0"" *) 
+  (* C_DOUT_DEFAULT_2 = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_GPIO2_WIDTH = ""32"" *) 
+  (* C_GPIO_WIDTH = ""4"" *) 
+  (* C_INTERRUPT_PRESENT = ""0"" *) 
+  (* C_IS_DUAL = ""0"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_TRI_DEFAULT = ""-1"" *) 
+  (* C_TRI_DEFAULT_2 = ""-1"" *) 
+  (* downgradeipidentifiedwarnings = ""yes"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
+       (.gpio2_io_i({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
+        .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
+   (SR,
+    \\Not_Dual.gpio_Data_Out_reg[0] ,
+    \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_aresetn,
+    s_axi_rready,
+    s_axi_bready,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    Q,
+    gpio_io_t,
+    s_axi_wdata,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output SR;
+  output \\Not_Dual.gpio_Data_Out_reg[0] ;
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [2:0]s_axi_araddr;
+  input [2:0]s_axi_awaddr;
+  input s_axi_aresetn;
+  input s_axi_rready;
+  input s_axi_bready;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input [3:0]Q;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire \\Not_Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [3:0]Q;
+  wire SR;
+  wire [0:6]bus2ip_addr;
+  wire \\bus2ip_addr_i[2]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[3]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_2_n_0 ;
+  wire bus2ip_rnw_i06_out;
+  wire clear;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_write;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire [1:0]p_0_out;
+  wire p_1_in;
+  wire [3:0]plusOp;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [3:0]s_axi_rdata;
+  wire \\s_axi_rdata_i[3]_i_1_n_0 ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire state1__2;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(clear));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(clear));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
+       (.D(D),
+        .E(E),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ),
+        .\\Not_Dual.gpio_Data_In_reg[0] (Q),
+        .\\Not_Dual.gpio_OE_reg[0] (\\Not_Dual.gpio_OE_reg[0] ),
+        .Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
+        .bus2ip_rnw_i_reg(\\Not_Dual.gpio_Data_Out_reg[0] ),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .rst_reg(SR),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .start2_reg(start2));
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_awaddr[0]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_awaddr[1]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h000000EA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_wvalid),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(\\bus2ip_addr_i[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[8]_i_2 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_awaddr[2]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[8]_i_2_n_0 ));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[2]_i_1_n_0 ),
+        .Q(bus2ip_addr[6]),
+        .R(SR));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[3]_i_1_n_0 ),
+        .Q(bus2ip_addr[5]),
+        .R(SR));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[8]_i_2_n_0 ),
+        .Q(bus2ip_addr[0]),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT3 #(
+    .INIT(8\'h10)) 
+    bus2ip_rnw_i_i_1
+       (.I0(state[0]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(bus2ip_rnw_i06_out),
+        .Q(\\Not_Dual.gpio_Data_Out_reg[0] ),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h3FFA000A)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state1__2),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(is_read),
+        .O(is_read_i_1_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0040FFFF00400000)) 
+    is_write_i_1
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_wvalid),
+        .I3(state[1]),
+        .I4(is_write),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hF88800000000FFFF)) 
+    is_write_i_2
+       (.I0(s_axi_rvalid),
+        .I1(s_axi_rready),
+        .I2(s_axi_bvalid),
+        .I3(s_axi_bready),
+        .I4(state[0]),
+        .I5(state[1]),
+        .O(is_write));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(SR));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    rst_i_1
+       (.I0(s_axi_aresetn),
+        .O(p_1_in));
+  FDRE rst_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(SR),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_wready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(SR));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[3]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(\\s_axi_rdata_i[3]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [0]),
+        .Q(s_axi_rdata[0]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [1]),
+        .Q(s_axi_rdata[1]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [2]),
+        .Q(s_axi_rdata[2]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [3]),
+        .Q(s_axi_rdata[3]),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_arready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h000000F8)) 
+    start2_i_1
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_arvalid),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h77FC44FC)) 
+    \\state[0]_i_1 
+       (.I0(state1__2),
+        .I1(state[0]),
+        .I2(s_axi_arvalid),
+        .I3(state[1]),
+        .I4(s_axi_wready),
+        .O(p_0_out[0]));
+  LUT5 #(
+    .INIT(32\'h5FFC50FC)) 
+    \\state[1]_i_1 
+       (.I0(state1__2),
+        .I1(\\state[1]_i_3_n_0 ),
+        .I2(state[1]),
+        .I3(state[0]),
+        .I4(s_axi_arready),
+        .O(p_0_out[1]));
+  LUT4 #(
+    .INIT(16\'hF888)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(state1__2));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\state[1]_i_3 
+       (.I0(s_axi_wvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_arvalid),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[0]),
+        .Q(state[0]),
+        .R(SR));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[1]),
+        .Q(state[1]),
+        .R(SR));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:35:35 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    SDIO0_WP,
+    UART0_TX,
+    UART0_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    IRQ_F2P,
+    FCLK_CLK0,
+    FCLK_RESET0_N,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_I"" *) input I2C0_SDA_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_O"" *) output I2C0_SDA_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_T"" *) output I2C0_SDA_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_I"" *) input I2C0_SCL_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_O"" *) output I2C0_SCL_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_T"" *) output I2C0_SCL_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *) input SDIO0_WP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 TxD"" *) output UART0_TX;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 RxD"" *) input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *) output [1:0]USB0_PORT_INDCTL;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *) output USB0_VBUS_PWRSELECT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *) input USB0_VBUS_PWRFAULT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *) output M_AXI_GP0_ARVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *) output M_AXI_GP0_AWVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *) output M_AXI_GP0_BREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *) output M_AXI_GP0_RREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *) output M_AXI_GP0_WLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *) output M_AXI_GP0_WVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *) output [11:0]M_AXI_GP0_ARID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *) output [11:0]M_AXI_GP0_AWID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *) output [11:0]M_AXI_GP0_WID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *) output [1:0]M_AXI_GP0_ARBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *) output [1:0]M_AXI_GP0_ARLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *) output [2:0]M_AXI_GP0_ARSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *) output [1:0]M_AXI_GP0_AWBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *) output [1:0]M_AXI_GP0_AWLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *) output [2:0]M_AXI_GP0_AWSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *) output [2:0]M_AXI_GP0_ARPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *) output [2:0]M_AXI_GP0_AWPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *) output [31:0]M_AXI_GP0_ARADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *) output [31:0]M_AXI_GP0_AWADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *) output [31:0]M_AXI_GP0_WDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *) output [3:0]M_AXI_GP0_ARCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *) output [3:0]M_AXI_GP0_ARLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *) output [3:0]M_AXI_GP0_ARQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *) output [3:0]M_AXI_GP0_AWCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *) output [3:0]M_AXI_GP0_AWLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *) output [3:0]M_AXI_GP0_AWQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *) output [3:0]M_AXI_GP0_WSTRB;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *) input M_AXI_GP0_ACLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *) input M_AXI_GP0_ARREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *) input M_AXI_GP0_AWREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *) input M_AXI_GP0_BVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *) input M_AXI_GP0_RLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *) input M_AXI_GP0_RVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *) input M_AXI_GP0_WREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *) input [11:0]M_AXI_GP0_BID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *) input [11:0]M_AXI_GP0_RID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *) input [1:0]M_AXI_GP0_BRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *) input [1:0]M_AXI_GP0_RRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *) input [31:0]M_AXI_GP0_RDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT"" *) input [1:0]IRQ_F2P;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *) output FCLK_CLK0;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *) output FCLK_RESET0_N;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *) inout [53:0]MIO;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *) inout DDR_CAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *) inout DDR_CKE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *) inout DDR_Clk_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *) inout DDR_Clk;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *) inout DDR_CS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *) inout DDR_DRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *) inout DDR_ODT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *) inout DDR_RAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *) inout DDR_WEB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *) inout [2:0]DDR_BankAddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *) inout [14:0]DDR_Addr;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *) inout DDR_VRN;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *) inout DDR_VRP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *) inout [3:0]DDR_DM;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *) inout [31:0]DDR_DQ;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *) inout [3:0]DDR_DQS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *) inout [3:0]DDR_DQS;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *) inout PS_SRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *) inout PS_CLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *) inout PS_PORB;
+
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire FCLK_CLK0;
+  wire FCLK_RESET0_N;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire [1:0]IRQ_F2P;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [2:0]M_AXI_GP0_ARSIZE;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [2:0]M_AXI_GP0_AWSIZE;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_WP;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+  wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+  wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+  wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+  wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+  wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO0_LED_UNCONNECTED;
+  wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO1_LED_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+  wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+  wire NLW_inst_TRACE_CTL_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+  wire NLW_inst_UART0_DTRN_UNCONNECTED;
+  wire NLW_inst_UART0_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_DTRN_UNCONNECTED;
+  wire NLW_inst_UART1_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_TX_UNCONNECTED;
+  wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+  wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+  wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+  wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+  wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+PULLUP pullup_MIO_0
+       (.O(MIO[0]));
+PULLUP pullup_MIO_9
+       (.O(MIO[9]));
+PULLUP pullup_MIO_10
+       (.O(MIO[10]));
+PULLUP pullup_MIO_11
+       (.O(MIO[11]));
+PULLUP pullup_MIO_12
+       (.O(MIO[12]));
+PULLUP pullup_MIO_13
+       (.O(MIO[13]));
+PULLUP pullup_MIO_14
+       (.O(MIO[14]));
+PULLUP pullup_MIO_15
+       (.O(MIO[15]));
+PULLUP pullup_MIO_46
+       (.O(MIO[46]));
+
+  (* C_DM_WIDTH = ""4"" *) 
+  (* C_DQS_WIDTH = ""4"" *) 
+  (* C_DQ_WIDTH = ""32"" *) 
+  (* C_EMIO_GPIO_WIDTH = ""64"" *) 
+  (* C_EN_EMIO_ENET0 = ""0"" *) 
+  (* C_EN_EMIO_ENET1 = ""0"" *) 
+  (* C_EN_EMIO_PJTAG = ""0"" *) 
+  (* C_EN_EMIO_TRACE = ""0"" *) 
+  (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+  (* C_FCLK_CLK1_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK2_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+  (* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+  (* C_INCLUDE_TRACE_BUFFER = ""0"" *) 
+  (* C_IRQ_F2P_MODE = ""DIRECT"" *) 
+  (* C_MIO_PRIMITIVE = ""54"" *) 
+  (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_NUM_F2P_INTR_INPUTS = ""2"" *) 
+  (* C_PACKAGE_NAME = ""clg400"" *) 
+  (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+  (* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+  (* C_S_AXI_GP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP3_ID_WIDTH = ""6"" *) 
+  (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) 
+  (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+  (* C_TRACE_INTERNAL_WIDTH = ""2"" *) 
+  (* C_TRACE_PIPELINE_WIDTH = ""8"" *) 
+  (* C_USE_AXI_NONSECURE = ""0"" *) 
+  (* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) 
+  (* C_USE_M_AXI_GP0 = ""1"" *) 
+  (* C_USE_M_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_ACP = ""0"" *) 
+  (* C_USE_S_AXI_GP0 = ""0"" *) 
+  (* C_USE_S_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP0 = ""0"" *) 
+  (* C_USE_S_AXI_HP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP2 = ""0"" *) 
+  (* C_USE_S_AXI_HP3 = ""0"" *) 
+  (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) 
+  (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+  (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
+       (.CAN0_PHY_RX(1\'b0),
+        .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+        .CAN1_PHY_RX(1\'b0),
+        .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+        .Core0_nFIQ(1\'b0),
+        .Core0_nIRQ(1\'b0),
+        .Core1_nFIQ(1\'b0),
+        .Core1_nIRQ(1\'b0),
+        .DDR_ARB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .DDR_Addr(DDR_Addr),
+        .DDR_BankAddr(DDR_BankAddr),
+        .DDR_CAS_n(DDR_CAS_n),
+        .DDR_CKE(DDR_CKE),
+        .DDR_CS_n(DDR_CS_n),
+        .DDR_Clk(DDR_Clk),
+        .DDR_Clk_n(DDR_Clk_n),
+        .DDR_DM(DDR_DM),
+        .DDR_DQ(DDR_DQ),
+        .DDR_DQS(DDR_DQS),
+        .DDR_DQS_n(DDR_DQS_n),
+        .DDR_DRSTB(DDR_DRSTB),
+        .DDR_ODT(DDR_ODT),
+        .DDR_RAS_n(DDR_RAS_n),
+        .DDR_VRN(DDR_VRN),
+        .DDR_VRP(DDR_VRP),
+        .DDR_WEB(DDR_WEB),
+        .DMA0_ACLK(1\'b0),
+        .DMA0_DAREADY(1\'b0),
+        .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+        .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+        .DMA0_DRLAST(1\'b0),
+        .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+        .DMA0_DRTYPE({1\'b0,1\'b0}),
+        .DMA0_DRVALID(1\'b0),
+        .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+        .DMA1_ACLK(1\'b0),
+        .DMA1_DAREADY(1\'b0),
+        .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+        .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+        .DMA1_DRLAST(1\'b0),
+        .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+        .DMA1_DRTYPE({1\'b0,1\'b0}),
+        .DMA1_DRVALID(1\'b0),
+        .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+        .DMA2_ACLK(1\'b0),
+        .DMA2_DAREADY(1\'b0),
+        .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+        .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+        .DMA2_DRLAST(1\'b0),
+        .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+        .DMA2_DRTYPE({1\'b0,1\'b0}),
+        .DMA2_DRVALID(1\'b0),
+        .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+        .DMA3_ACLK(1\'b0),
+        .DMA3_DAREADY(1\'b0),
+        .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+        .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+        .DMA3_DRLAST(1\'b0),
+        .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+        .DMA3_DRTYPE({1\'b0,1\'b0}),
+        .DMA3_DRVALID(1\'b0),
+        .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+        .ENET0_EXT_INTIN(1\'b0),
+        .ENET0_GMII_COL(1\'b0),
+        .ENET0_GMII_CRS(1\'b0),
+        .ENET0_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET0_GMII_RX_CLK(1\'b0),
+        .ENET0_GMII_RX_DV(1\'b0),
+        .ENET0_GMII_RX_ER(1\'b0),
+        .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET0_GMII_TX_CLK(1\'b0),
+        .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+        .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+        .ENET0_MDIO_I(1\'b0),
+        .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+        .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+        .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+        .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+        .ENET1_EXT_INTIN(1\'b0),
+        .ENET1_GMII_COL(1\'b0),
+        .ENET1_GMII_CRS(1\'b0),
+        .ENET1_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET1_GMII_RX_CLK(1\'b0),
+        .ENET1_GMII_RX_DV(1\'b0),
+        .ENET1_GMII_RX_ER(1\'b0),
+        .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET1_GMII_TX_CLK(1\'b0),
+        .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+        .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+        .ENET1_MDIO_I(1\'b0),
+        .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+        .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+        .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+        .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+        .EVENT_EVENTI(1\'b0),
+        .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+        .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+        .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+        .FCLK_CLK0(FCLK_CLK0),
+        .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+        .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+        .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+        .FCLK_CLKTRIG0_N(1\'b0),
+        .FCLK_CLKTRIG1_N(1\'b0),
+        .FCLK_CLKTRIG2_N(1\'b0),
+        .FCLK_CLKTRIG3_N(1\'b0),
+        .FCLK_RESET0_N(FCLK_RESET0_N),
+        .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+        .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+        .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+        .FPGA_IDLE_N(1\'b0),
+        .FTMD_TRACEIN_ATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_CLK(1\'b0),
+        .FTMD_TRACEIN_DATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_VALID(1\'b0),
+        .FTMT_F2P_DEBUG({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+        .FTMT_F2P_TRIG_0(1\'b0),
+        .FTMT_F2P_TRIG_1(1\'b0),
+        .FTMT_F2P_TRIG_2(1\'b0),
+        .FTMT_F2P_TRIG_3(1\'b0),
+        .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+        .FTMT_P2F_TRIGACK_0(1\'b0),
+        .FTMT_P2F_TRIGACK_1(1\'b0),
+        .FTMT_P2F_TRIGACK_2(1\'b0),
+        .FTMT_P2F_TRIGACK_3(1\'b0),
+        .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+        .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+        .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+        .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+        .GPIO_I({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
+        .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
+        .I2C0_SCL_I(I2C0_SCL_I),
+        .I2C0_SCL_O(I2C0_SCL_O),
+        .I2C0_SCL_T(I2C0_SCL_T),
+        .I2C0_SDA_I(I2C0_SDA_I),
+        .I2C0_SDA_O(I2C0_SDA_O),
+        .I2C0_SDA_T(I2C0_SDA_T),
+        .I2C1_SCL_I(1\'b0),
+        .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+        .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+        .I2C1_SDA_I(1\'b0),
+        .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+        .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+        .IRQ_F2P(IRQ_F2P),
+        .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+        .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+        .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+        .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+        .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+        .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+        .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+        .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+        .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+        .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+        .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+        .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+        .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+        .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+        .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+        .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+        .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+        .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+        .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+        .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+        .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+        .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+        .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+        .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+        .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+        .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+        .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+        .MIO(MIO),
+        .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+        .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+        .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+        .M_AXI_GP1_ACLK(1\'b0),
+        .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+        .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARREADY(1\'b0),
+        .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+        .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWREADY(1\'b0),
+        .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+        .M_AXI_GP1_BID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+        .M_AXI_GP1_BRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_BVALID(1\'b0),
+        .M_AXI_GP1_RDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RLAST(1\'b0),
+        .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+        .M_AXI_GP1_RRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_RVALID(1\'b0),
+        .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+        .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+        .M_AXI_GP1_WREADY(1\'b0),
+        .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+        .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+        .PJTAG_TCK(1\'b0),
+        .PJTAG_TDI(1\'b0),
+        .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+        .PJTAG_TMS(1\'b0),
+        .PS_CLK(PS_CLK),
+        .PS_PORB(PS_PORB),
+        .PS_SRSTB(PS_SRSTB),
+        .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+        .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO0_CDN(1\'b0),
+        .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+        .SDIO0_CLK_FB(1\'b0),
+        .SDIO0_CMD_I(1\'b0),
+        .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+        .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+        .SDIO0_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+        .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+        .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+        .SDIO0_WP(SDIO0_WP),
+        .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+        .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO1_CDN(1\'b0),
+        .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+        .SDIO1_CLK_FB(1\'b0),
+        .SDIO1_CMD_I(1\'b0),
+        .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+        .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+        .SDIO1_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+        .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+        .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+        .SDIO1_WP(1\'b0),
+        .SPI0_MISO_I(1\'b0),
+        .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+        .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+        .SPI0_MOSI_I(1\'b0),
+        .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+        .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+        .SPI0_SCLK_I(1\'b0),
+        .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+        .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+        .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+        .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+        .SPI0_SS_I(1\'b0),
+        .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+        .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+        .SPI1_MISO_I(1\'b0),
+        .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+        .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+        .SPI1_MOSI_I(1\'b0),
+        .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+        .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+        .SPI1_SCLK_I(1\'b0),
+        .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+        .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+        .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+        .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+        .SPI1_SS_I(1\'b0),
+        .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+        .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+        .SRAM_INTIN(1\'b0),
+        .S_AXI_ACP_ACLK(1\'b0),
+        .S_AXI_ACP_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+        .S_AXI_ACP_ARID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+        .S_AXI_ACP_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARVALID(1\'b0),
+        .S_AXI_ACP_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+        .S_AXI_ACP_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWVALID(1\'b0),
+        .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_BREADY(1\'b0),
+        .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+        .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+        .S_AXI_ACP_RREADY(1\'b0),
+        .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+        .S_AXI_ACP_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WLAST(1\'b0),
+        .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+        .S_AXI_ACP_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WVALID(1\'b0),
+        .S_AXI_GP0_ACLK(1\'b0),
+        .S_AXI_GP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+        .S_AXI_GP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+        .S_AXI_GP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARVALID(1\'b0),
+        .S_AXI_GP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+        .S_AXI_GP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWVALID(1\'b0),
+        .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_BREADY(1\'b0),
+        .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+        .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+        .S_AXI_GP0_RREADY(1\'b0),
+        .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+        .S_AXI_GP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WLAST(1\'b0),
+        .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+        .S_AXI_GP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WVALID(1\'b0),
+        .S_AXI_GP1_ACLK(1\'b0),
+        .S_AXI_GP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+        .S_AXI_GP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+        .S_AXI_GP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARVALID(1\'b0),
+        .S_AXI_GP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+        .S_AXI_GP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWVALID(1\'b0),
+        .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_BREADY(1\'b0),
+        .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+        .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+        .S_AXI_GP1_RREADY(1\'b0),
+        .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+        .S_AXI_GP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WLAST(1\'b0),
+        .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+        .S_AXI_GP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WVALID(1\'b0),
+        .S_AXI_HP0_ACLK(1\'b0),
+        .S_AXI_HP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+        .S_AXI_HP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+        .S_AXI_HP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARVALID(1\'b0),
+        .S_AXI_HP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+        .S_AXI_HP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWVALID(1\'b0),
+        .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_BREADY(1\'b0),
+        .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+        .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP0_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+        .S_AXI_HP0_RREADY(1\'b0),
+        .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+        .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WLAST(1\'b0),
+        .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+        .S_AXI_HP0_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WVALID(1\'b0),
+        .S_AXI_HP1_ACLK(1\'b0),
+        .S_AXI_HP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+        .S_AXI_HP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+        .S_AXI_HP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARVALID(1\'b0),
+        .S_AXI_HP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+        .S_AXI_HP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWVALID(1\'b0),
+        .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_BREADY(1\'b0),
+        .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+        .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP1_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+        .S_AXI_HP1_RREADY(1\'b0),
+        .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+        .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WLAST(1\'b0),
+        .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+        .S_AXI_HP1_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WVALID(1\'b0),
+        .S_AXI_HP2_ACLK(1\'b0),
+        .S_AXI_HP2_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+        .S_AXI_HP2_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+        .S_AXI_HP2_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARVALID(1\'b0),
+        .S_AXI_HP2_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+        .S_AXI_HP2_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWVALID(1\'b0),
+        .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_BREADY(1\'b0),
+        .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+        .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP2_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+        .S_AXI_HP2_RREADY(1\'b0),
+        .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+        .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WLAST(1\'b0),
+        .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+        .S_AXI_HP2_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WVALID(1\'b0),
+        .S_AXI_HP3_ACLK(1\'b0),
+        .S_AXI_HP3_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+        .S_AXI_HP3_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+        .S_AXI_HP3_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARVALID(1\'b0),
+        .S_AXI_HP3_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+        .S_AXI_HP3_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWVALID(1\'b0),
+        .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_BREADY(1\'b0),
+        .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+        .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP3_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+        .S_AXI_HP3_RREADY(1\'b0),
+        .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+        .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WLAST(1\'b0),
+        .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3'b'_WREADY_UNCONNECTED),
+        .S_AXI_HP3_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WVALID(1\'b0),
+        .TRACE_CLK(1\'b0),
+        .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+        .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
+        .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+        .TTC0_CLK0_IN(1\'b0),
+        .TTC0_CLK1_IN(1\'b0),
+        .TTC0_CLK2_IN(1\'b0),
+        .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+        .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+        .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+        .TTC1_CLK0_IN(1\'b0),
+        .TTC1_CLK1_IN(1\'b0),
+        .TTC1_CLK2_IN(1\'b0),
+        .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+        .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+        .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+        .UART0_CTSN(1\'b0),
+        .UART0_DCDN(1\'b0),
+        .UART0_DSRN(1\'b0),
+        .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
+        .UART0_RIN(1\'b0),
+        .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
+        .UART0_RX(UART0_RX),
+        .UART0_TX(UART0_TX),
+        .UART1_CTSN(1\'b0),
+        .UART1_DCDN(1\'b0),
+        .UART1_DSRN(1\'b0),
+        .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+        .UART1_RIN(1\'b0),
+        .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+        .UART1_RX(1\'b1),
+        .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+        .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+        .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+        .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+        .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+        .USB1_VBUS_PWRFAULT(1\'b0),
+        .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+        .WDT_CLK_IN(1\'b0),
+        .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = ""4"" *) (* C_DQS_WIDTH = ""4"" *) (* C_DQ_WIDTH = ""32"" *) 
+(* C_EMIO_GPIO_WIDTH = ""64"" *) (* C_EN_EMIO_ENET0 = ""0"" *) (* C_EN_EMIO_ENET1 = ""0"" *) 
+(* C_EN_EMIO_PJTAG = ""0"" *) (* C_EN_EMIO_TRACE = ""0"" *) (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+(* C_FCLK_CLK1_BUF = ""FALSE"" *) (* C_FCLK_CLK2_BUF = ""FALSE"" *) (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+(* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+(* C_INCLUDE_TRACE_BUFFER = ""0"" *) (* C_IRQ_F2P_MODE = ""DIRECT"" *) (* C_MIO_PRIMITIVE = ""54"" *) 
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+(* C_NUM_F2P_INTR_INPUTS = ""2"" *) (* C_PACKAGE_NAME = ""clg400"" *) (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+(* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+(* C_S_AXI_GP0_ID_WIDTH = ""6"" *) (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP0_ID_WIDTH = ""6"" *) (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+(* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP3_ID_WIDTH = ""6"" *) (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+(* C_TRACE_INTERNAL_WIDTH = ""2"" *) (* C_TRACE_PIPELINE_WIDTH = ""8"" *) (* C_USE_AXI_NONSECURE = ""0"" *) 
+(* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) (* C_USE_M_AXI_GP0 = ""1"" *) (* C_USE_M_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_ACP = ""0"" *) (* C_USE_S_AXI_GP0 = ""0"" *) (* C_USE_S_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_HP0 = ""0"" *) (* C_USE_S_AXI_HP1 = ""0"" *) (* C_USE_S_AXI_HP2 = ""0"" *) 
+(* C_USE_S_AXI_HP3 = ""0"" *) (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+(* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
+   (CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TDI,
+    PJTAG_TDO,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    TRACE_CLK_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_PORT_INDCTL,
+    USB1_VBUS_PWRSELECT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARESETN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARESETN,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARESETN,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARESETN,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_ARESETN,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARESETN,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARESETN,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARESETN,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARESETN,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_RSTN,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_RSTN,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_RSTN,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_RSTN,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA3_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DRTYPE,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG_0,
+    FTMT_F2P_TRIGACK_0,
+    FTMT_F2P_TRIG_1,
+    FTMT_F2P_TRIGACK_1,
+    FTMT_F2P_TRIG_2,
+    FTMT_F2P_TRIGACK_2,
+    FTMT_F2P_TRIG_3,
+    FTMT_F2P_TRIGACK_3,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK_0,
+    FTMT_P2F_TRIG_0,
+    FTMT_P2F_TRIGACK_1,
+    FTMT_P2F_TRIG_1,
+    FTMT_P2F_TRIGACK_2,
+    FTMT_P2F_TRIG_2,
+    FTMT_P2F_TRIGACK_3,
+    FTMT_P2F_TRIG_3,
+    FTMT_P2F_DEBUG,
+    FPGA_IDLE_N,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    DDR_ARB,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0]ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input ENET0_EXT_INTIN;
+  input [7:0]ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0]ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input ENET1_EXT_INTIN;
+  input [7:0]ENET1_GMII_RXD;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TDI;
+  output PJTAG_TDO;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0]SDIO0_DATA_I;
+  output [3:0]SDIO0_DATA_O;
+  output [3:0]SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0]SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0]SDIO1_DATA_I;
+  output [3:0]SDIO1_DATA_O;
+  output [3:0]SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0]SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [1:0]TRACE_DATA;
+  output TRACE_CLK_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output [1:0]USB1_PORT_INDCTL;
+  output USB1_VBUS_PWRSELECT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARESETN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARESETN;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [11:0]M_AXI_GP1_ARID;
+  output [11:0]M_AXI_GP1_AWID;
+  output [11:0]M_AXI_GP1_WID;
+  output [1:0]M_AXI_GP1_ARBURST;
+  output [1:0]M_AXI_GP1_ARLOCK;
+  output [2:0]M_AXI_GP1_ARSIZE;
+  output [1:0]M_AXI_GP1_AWBURST;
+  output [1:0]M_AXI_GP1_AWLOCK;
+  output [2:0]M_AXI_GP1_AWSIZE;
+  output [2:0]M_AXI_GP1_ARPROT;
+  output [2:0]M_AXI_GP1_AWPROT;
+  output [31:0]M_AXI_GP1_ARADDR;
+  output [31:0]M_AXI_GP1_AWADDR;
+  output [31:0]M_AXI_GP1_WDATA;
+  output [3:0]M_AXI_GP1_ARCACHE;
+  output [3:0]M_AXI_GP1_ARLEN;
+  output [3:0]M_AXI_GP1_ARQOS;
+  output [3:0]M_AXI_GP1_AWCACHE;
+  output [3:0]M_AXI_GP1_AWLEN;
+  output [3:0]M_AXI_GP1_AWQOS;
+  output [3:0]M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [11:0]M_AXI_GP1_BID;
+  input [11:0]M_AXI_GP1_RID;
+  input [1:0]M_AXI_GP1_BRESP;
+  input [1:0]M_AXI_GP1_RRESP;
+  input [31:0]M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARESETN;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0]S_AXI_GP0_BRESP;
+  output [1:0]S_AXI_GP0_RRESP;
+  output [31:0]S_AXI_GP0_RDATA;
+  output [5:0]S_AXI_GP0_BID;
+  output [5:0]S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0]S_AXI_GP0_ARBURST;
+  input [1:0]S_AXI_GP0_ARLOCK;
+  input [2:0]S_AXI_GP0_ARSIZE;
+  input [1:0]S_AXI_GP0_AWBURST;
+  input [1:0]S_AXI_GP0_AWLOCK;
+  input [2:0]S_AXI_GP0_AWSIZE;
+  input [2:0]S_AXI_GP0_ARPROT;
+  input [2:0]S_AXI_GP0_AWPROT;
+  input [31:0]S_AXI_GP0_ARADDR;
+  input [31:0]S_AXI_GP0_AWADDR;
+  input [31:0]S_AXI_GP0_WDATA;
+  input [3:0]S_AXI_GP0_ARCACHE;
+  input [3:0]S_AXI_GP0_ARLEN;
+  input [3:0]S_AXI_GP0_ARQOS;
+  input [3:0]S_AXI_GP0_AWCACHE;
+  input [3:0]S_AXI_GP0_AWLEN;
+  input [3:0]S_AXI_GP0_AWQOS;
+  input [3:0]S_AXI_GP0_WSTRB;
+  input [5:0]S_AXI_GP0_ARID;
+  input [5:0]S_AXI_GP0_AWID;
+  input [5:0]S_AXI_GP0_WID;
+  output S_AXI_GP1_ARESETN;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0]S_AXI_GP1_BRESP;
+  output [1:0]S_AXI_GP1_RRESP;
+  output [31:0]S_AXI_GP1_RDATA;
+  output [5:0]S_AXI_GP1_BID;
+  output [5:0]S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0]S_AXI_GP1_ARBURST;
+  input [1:0]S_AXI_GP1_ARLOCK;
+  input [2:0]S_AXI_GP1_ARSIZE;
+  input [1:0]S_AXI_GP1_AWBURST;
+  input [1:0]S_AXI_GP1_AWLOCK;
+  input [2:0]S_AXI_GP1_AWSIZE;
+  input [2:0]S_AXI_GP1_ARPROT;
+  input [2:0]S_AXI_GP1_AWPROT;
+  input [31:0]S_AXI_GP1_ARADDR;
+  input [31:0]S_AXI_GP1_AWADDR;
+  input [31:0]S_AXI_GP1_WDATA;
+  input [3:0]S_AXI_GP1_ARCACHE;
+  input [3:0]S_AXI_GP1_ARLEN;
+  input [3:0]S_AXI_GP1_ARQOS;
+  input [3:0]S_AXI_GP1_AWCACHE;
+  input [3:0]S_AXI_GP1_AWLEN;
+  input [3:0]S_AXI_GP1_AWQOS;
+  input [3:0]S_AXI_GP1_WSTRB;
+  input [5:0]S_AXI_GP1_ARID;
+  input [5:0]S_AXI_GP1_AWID;
+  input [5:0]S_AXI_GP1_WID;
+  output S_AXI_ACP_ARESETN;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0]S_AXI_ACP_BRESP;
+  output [1:0]S_AXI_ACP_RRESP;
+  output [2:0]S_AXI_ACP_BID;
+  output [2:0]S_AXI_ACP_RID;
+  output [63:0]S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0]S_AXI_ACP_ARID;
+  input [2:0]S_AXI_ACP_ARPROT;
+  input [2:0]S_AXI_ACP_AWID;
+  input [2:0]S_AXI_ACP_AWPROT;
+  input [2:0]S_AXI_ACP_WID;
+  input [31:0]S_AXI_ACP_ARADDR;
+  input [31:0]S_AXI_ACP_AWADDR;
+  input [3:0]S_AXI_ACP_ARCACHE;
+  input [3:0]S_AXI_ACP_ARLEN;
+  input [3:0]S_AXI_ACP_ARQOS;
+  input [3:0]S_AXI_ACP_AWCACHE;
+  input [3:0]S_AXI_ACP_AWLEN;
+  input [3:0]S_AXI_ACP_AWQOS;
+  input [1:0]S_AXI_ACP_ARBURST;
+  input [1:0]S_AXI_ACP_ARLOCK;
+  input [2:0]S_AXI_ACP_ARSIZE;
+  input [1:0]S_AXI_ACP_AWBURST;
+  input [1:0]S_AXI_ACP_AWLOCK;
+  input [2:0]S_AXI_ACP_AWSIZE;
+  input [4:0]S_AXI_ACP_ARUSER;
+  input [4:0]S_AXI_ACP_AWUSER;
+  input [63:0]S_AXI_ACP_WDATA;
+  input [7:0]S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARESETN;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0]S_AXI_HP0_BRESP;
+  output [1:0]S_AXI_HP0_RRESP;
+  output [5:0]S_AXI_HP0_BID;
+  output [5:0]S_AXI_HP0_RID;
+  output [63:0]S_AXI_HP0_RDATA;
+  output [7:0]S_AXI_HP0_RCOUNT;
+  output [7:0]S_AXI_HP0_WCOUNT;
+  output [2:0]S_AXI_HP0_RACOUNT;
+  output [5:0]S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0]S_AXI_HP0_ARBURST;
+  input [1:0]S_AXI_HP0_ARLOCK;
+  input [2:0]S_AXI_HP0_ARSIZE;
+  input [1:0]S_AXI_HP0_AWBURST;
+  input [1:0]S_AXI_HP0_AWLOCK;
+  input [2:0]S_AXI_HP0_AWSIZE;
+  input [2:0]S_AXI_HP0_ARPROT;
+  input [2:0]S_AXI_HP0_AWPROT;
+  input [31:0]S_AXI_HP0_ARADDR;
+  input [31:0]S_AXI_HP0_AWADDR;
+  input [3:0]S_AXI_HP0_ARCACHE;
+  input [3:0]S_AXI_HP0_ARLEN;
+  input [3:0]S_AXI_HP0_ARQOS;
+  input [3:0]S_AXI_HP0_AWCACHE;
+  input [3:0]S_AXI_HP0_AWLEN;
+  input [3:0]S_AXI_HP0_AWQOS;
+  input [5:0]S_AXI_HP0_ARID;
+  input [5:0]S_AXI_HP0_AWID;
+  input [5:0]S_AXI_HP0_WID;
+  input [63:0]S_AXI_HP0_WDATA;
+  input [7:0]S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARESETN;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0]S_AXI_HP1_BRESP;
+  output [1:0]S_AXI_HP1_RRESP;
+  output [5:0]S_AXI_HP1_BID;
+  output [5:0]S_AXI_HP1_RID;
+  output [63:0]S_AXI_HP1_RDATA;
+  output [7:0]S_AXI_HP1_RCOUNT;
+  output [7:0]S_AXI_HP1_WCOUNT;
+  output [2:0]S_AXI_HP1_RACOUNT;
+  output [5:0]S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0]S_AXI_HP1_ARBURST;
+  input [1:0]S_AXI_HP1_ARLOCK;
+  input [2:0]S_AXI_HP1_ARSIZE;
+  input [1:0]S_AXI_HP1_AWBURST;
+  input [1:0]S_AXI_HP1_AWLOCK;
+  input [2:0]S_AXI_HP1_AWSIZE;
+  input [2:0]S_AXI_HP1_ARPROT;
+  input [2:0]S_AXI_HP1_AWPROT;
+  input [31:0]S_AXI_HP1_ARADDR;
+  input [31:0]S_AXI_HP1_AWADDR;
+  input [3:0]S_AXI_HP1_ARCACHE;
+  input [3:0]S_AXI_HP1_ARLEN;
+  input [3:0]S_AXI_HP1_ARQOS;
+  input [3:0]S_AXI_HP1_AWCACHE;
+  input [3:0]S_AXI_HP1_AWLEN;
+  input [3:0]S_AXI_HP1_AWQOS;
+  input [5:0]S_AXI_HP1_ARID;
+  input [5:0]S_AXI_HP1_AWID;
+  input [5:0]S_AXI_HP1_WID;
+  input [63:0]S_AXI_HP1_WDATA;
+  input [7:0]S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARESETN;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0]S_AXI_HP2_BRESP;
+  output [1:0]S_AXI_HP2_RRESP;
+  output [5:0]S_AXI_HP2_BID;
+  output [5:0]S_AXI_HP2_RID;
+  output [63:0]S_AXI_HP2_RDATA;
+  output [7:0]S_AXI_HP2_RCOUNT;
+  output [7:0]S_AXI_HP2_WCOUNT;
+  output [2:0]S_AXI_HP2_RACOUNT;
+  output [5:0]S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0]S_AXI_HP2_ARBURST;
+  input [1:0]S_AXI_HP2_ARLOCK;
+  input [2:0]S_AXI_HP2_ARSIZE;
+  input [1:0]S_AXI_HP2_AWBURST;
+  input [1:0]S_AXI_HP2_AWLOCK;
+  input [2:0]S_AXI_HP2_AWSIZE;
+  input [2:0]S_AXI_HP2_ARPROT;
+  input [2:0]S_AXI_HP2_AWPROT;
+  input [31:0]S_AXI_HP2_ARADDR;
+  input [31:0]S_AXI_HP2_AWADDR;
+  input [3:0]S_AXI_HP2_ARCACHE;
+  input [3:0]S_AXI_HP2_ARLEN;
+  input [3:0]S_AXI_HP2_ARQOS;
+  input [3:0]S_AXI_HP2_AWCACHE;
+  input [3:0]S_AXI_HP2_AWLEN;
+  input [3:0]S_AXI_HP2_AWQOS;
+  input [5:0]S_AXI_HP2_ARID;
+  input [5:0]S_AXI_HP2_AWID;
+  input [5:0]S_AXI_HP2_WID;
+  input [63:0]S_AXI_HP2_WDATA;
+  input [7:0]S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARESETN;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0]S_AXI_HP3_BRESP;
+  output [1:0]S_AXI_HP3_RRESP;
+  output [5:0]S_AXI_HP3_BID;
+  output [5:0]S_AXI_HP3_RID;
+  output [63:0]S_AXI_HP3_RDATA;
+  output [7:0]S_AXI_HP3_RCOUNT;
+  output [7:0]S_AXI_HP3_WCOUNT;
+  output [2:0]S_AXI_HP3_RACOUNT;
+  output [5:0]S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0]S_AXI_HP3_ARBURST;
+  input [1:0]S_AXI_HP3_ARLOCK;
+  input [2:0]S_AXI_HP3_ARSIZE;
+  input [1:0]S_AXI_HP3_AWBURST;
+  input [1:0]S_AXI_HP3_AWLOCK;
+  input [2:0]S_AXI_HP3_AWSIZE;
+  input [2:0]S_AXI_HP3_ARPROT;
+  input [2:0]S_AXI_HP3_AWPROT;
+  input [31:0]S_AXI_HP3_ARADDR;
+  input [31:0]S_AXI_HP3_AWADDR;
+  input [3:0]S_AXI_HP3_ARCACHE;
+  input [3:0]S_AXI_HP3_ARLEN;
+  input [3:0]S_AXI_HP3_ARQOS;
+  input [3:0]S_AXI_HP3_AWCACHE;
+  input [3:0]S_AXI_HP3_AWLEN;
+  input [3:0]S_AXI_HP3_AWQOS;
+  input [5:0]S_AXI_HP3_ARID;
+  input [5:0]S_AXI_HP3_AWID;
+  input [5:0]S_AXI_HP3_WID;
+  input [63:0]S_AXI_HP3_WDATA;
+  input [7:0]S_AXI_HP3_WSTRB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+  input [1:0]IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output [1:0]DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  output DMA0_RSTN;
+  output [1:0]DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  output DMA1_RSTN;
+  output [1:0]DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  output DMA2_RSTN;
+  output [1:0]DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  output DMA3_RSTN;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input DMA3_DRVALID;
+  input [1:0]DMA0_DRTYPE;
+  input [1:0]DMA1_DRTYPE;
+  input [1:0]DMA2_DRTYPE;
+  input [1:0]DMA3_DRTYPE;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input [31:0]FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0]FTMD_TRACEIN_ATID;
+  input FTMT_F2P_TRIG_0;
+  output FTMT_F2P_TRIGACK_0;
+  input FTMT_F2P_TRIG_1;
+  output FTMT_F2P_TRIGACK_1;
+  input FTMT_F2P_TRIG_2;
+  output FTMT_F2P_TRIGACK_2;
+  input FTMT_F2P_TRIG_3;
+  output FTMT_F2P_TRIGACK_3;
+  input [31:0]FTMT_F2P_DEBUG;
+  input FTMT_P2F_TRIGACK_0;
+  output FTMT_P2F_TRIG_0;
+  input FTMT_P2F_TRIGACK_1;
+  output FTMT_P2F_TRIG_1;
+  input FTMT_P2F_TRIGACK_2;
+  output FTMT_P2F_TRIG_2;
+  input FTMT_P2F_TRIGACK_3;
+  output FTMT_P2F_TRIG_3;
+  output [31:0]FTMT_P2F_DEBUG;
+  input FPGA_IDLE_N;
+  output EVENT_EVENTO;
+  output [1:0]EVENT_STANDBYWFE;
+  output [1:0]EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  input [3:0]DDR_ARB;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+
+  wire \\<const0> ;
+  wire CAN0_PHY_RX;
+  wire CAN0_PHY_TX;
+  wire CAN1_PHY_RX;
+  wire CAN1_PHY_TX;
+  wire Core0_nFIQ;
+  wire Core0_nIRQ;
+  wire Core1_nFIQ;
+  wire Core1_nIRQ;
+  wire [3:0]DDR_ARB;
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire DMA0_ACLK;
+  wire DMA0_DAREADY;
+  wire [1:0]DMA0_DATYPE;
+  wire DMA0_DAVALID;
+  wire DMA0_DRLAST;
+  wire DMA0_DRREADY;
+  wire [1:0]DMA0_DRTYPE;
+  wire DMA0_DRVALID;
+  wire DMA0_RSTN;
+  wire DMA1_ACLK;
+  wire DMA1_DAREADY;
+  wire [1:0]DMA1_DATYPE;
+  wire DMA1_DAVALID;
+  wire DMA1_DRLAST;
+  wire DMA1_DRREADY;
+  wire [1:0]DMA1_DRTYPE;
+  wire DMA1_DRVALID;
+  wire DMA1_RSTN;
+  wire DMA2_ACLK;
+  wire DMA2_DAREADY;
+  wire [1:0]DMA2_DATYPE;
+  wire DMA2_DAVALID;
+  wire DMA2_DRLAST;
+  wire DMA2_DRREADY;
+  wire [1:0]DMA2_DRTYPE;
+  wire DMA2_DRVALID;
+  wire DMA2_RSTN;
+  wire DMA3_ACLK;
+  wire DMA3_DAREADY;
+  wire [1:0]DMA3_DATYPE;
+  wire DMA3_DAVALID;
+  wire DMA3_DRLAST;
+  wire DMA3_DRREADY;
+  wire [1:0]DMA3_DRTYPE;
+  wire DMA3_DRVALID;
+  wire DMA3_RSTN;
+  wire ENET0_EXT_INTIN;
+  wire ENET0_GMII_RX_CLK;
+  wire ENET0_GMII_TX_CLK;
+  wire ENET0_MDIO_I;
+  wire ENET0_MDIO_MDC;
+  wire ENET0_MDIO_O;
+  wire ENET0_MDIO_T;
+  wire ENET0_MDIO_T_n;
+  wire ENET0_PTP_DELAY_REQ_RX;
+  wire ENET0_PTP_DELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_REQ_RX;
+  wire ENET0_PTP_PDELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_RESP_RX;
+  wire ENET0_PTP_PDELAY_RESP_TX;
+  wire ENET0_PTP_SYNC_FRAME_RX;
+  wire ENET0_PTP_SYNC_FRAME_TX;
+  wire ENET0_SOF_RX;
+  wire ENET0_SOF_TX;
+  wire ENET1_EXT_INTIN;
+  wire ENET1_GMII_RX_CLK;
+  wire ENET1_GMII_TX_CLK;
+  wire ENET1_MDIO_I;
+  wire ENET1_MDIO_MDC;
+  wire ENET1_MDIO_O;
+  wire ENET1_MDIO_T;
+  wire ENET1_MDIO_T_n;
+  wire ENET1_PTP_DELAY_REQ_RX;
+  wire ENET1_PTP_DELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_REQ_RX;
+  wire ENET1_PTP_PDELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_RESP_RX;
+  wire ENET1_PTP_PDELAY_RESP_TX;
+  wire ENET1_PTP_SYNC_FRAME_RX;
+  wire ENET1_PTP_SYNC_FRAME_TX;
+  wire ENET1_SOF_RX;
+  wire ENET1_SOF_TX;
+  wire EVENT_EVENTI;
+  wire EVENT_EVENTO;
+  wire [1:0]EVENT_STANDBYWFE;
+  wire [1:0]EVENT_STANDBYWFI;
+  wire FCLK_CLK0;
+  wire FCLK_CLK1;
+  wire FCLK_CLK2;
+  wire FCLK_CLK3;
+  wire [0:0]FCLK_CLK_unbuffered;
+  wire FCLK_RESET0_N;
+  wire FCLK_RESET1_N;
+  wire FCLK_RESET2_N;
+  wire FCLK_RESET3_N;
+  wire FPGA_IDLE_N;
+  wire FTMD_TRACEIN_CLK;
+  wire [31:0]FTMT_F2P_DEBUG;
+  wire FTMT_F2P_TRIGACK_0;
+  wire FTMT_F2P_TRIGACK_1;
+  wire FTMT_F2P_TRIGACK_2;
+  wire FTMT_F2P_TRIGACK_3;
+  wire FTMT_F2P_TRIG_0;
+  wire FTMT_F2P_TRIG_1;
+  wire FTMT_F2P_TRIG_2;
+  wire FTMT_F2P_TRIG_3;
+  wire [31:0]FTMT_P2F_DEBUG;
+  wire FTMT_P2F_TRIGACK_0;
+  wire FTMT_P2F_TRIGACK_1;
+  wire FTMT_P2F_TRIGACK_2;
+  wire FTMT_P2F_TRIGACK_3;
+  wire FTMT_P2F_TRIG_0;
+  wire FTMT_P2F_TRIG_1;
+  wire FTMT_P2F_TRIG_2;
+  wire FTMT_P2F_TRIG_3;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SCL_T_n;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire I2C0_SDA_T_n;
+  wire I2C1_SCL_I;
+  wire I2C1_SCL_O;
+  wire I2C1_SCL_T;
+  wire I2C1_SCL_T_n;
+  wire I2C1_SDA_I;
+  wire I2C1_SDA_O;
+  wire I2C1_SDA_T;
+  wire I2C1_SDA_T_n;
+  wire [1:0]IRQ_F2P;
+  wire IRQ_P2F_CAN0;
+  wire IRQ_P2F_CAN1;
+  wire IRQ_P2F_CTI;
+  wire IRQ_P2F_DMAC0;
+  wire IRQ_P2F_DMAC1;
+  wire IRQ_P2F_DMAC2;
+  wire IRQ_P2F_DMAC3;
+  wire IRQ_P2F_DMAC4;
+  wire IRQ_P2F_DMAC5;
+  wire IRQ_P2F_DMAC6;
+  wire IRQ_P2F_DMAC7;
+  wire IRQ_P2F_DMAC_ABORT;
+  wire IRQ_P2F_ENET0;
+  wire IRQ_P2F_ENET1;
+  wire IRQ_P2F_ENET_WAKE0;
+  wire IRQ_P2F_ENET_WAKE1;
+  wire IRQ_P2F_GPIO;
+  wire IRQ_P2F_I2C0;
+  wire IRQ_P2F_I2C1;
+  wire IRQ_P2F_QSPI;
+  wire IRQ_P2F_SDIO0;
+  wire IRQ_P2F_SDIO1;
+  wire IRQ_P2F_SMC;
+  wire IRQ_P2F_SPI0;
+  wire IRQ_P2F_SPI1;
+  wire IRQ_P2F_UART0;
+  wire IRQ_P2F_UART1;
+  wire IRQ_P2F_USB0;
+  wire IRQ_P2F_USB1;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire M_AXI_GP0_ARESETN;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [1:0]\\^M_AXI_GP0_ARSIZE ;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [1:0]\\^M_AXI_GP0_AWSIZE ;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire M_AXI_GP1_ACLK;
+  wire [31:0]M_AXI_GP1_ARADDR;
+  wire [1:0]M_AXI_GP1_ARBURST;
+  wire [3:0]M_AXI_GP1_ARCACHE;
+  wire M_AXI_GP1_ARESETN;
+  wire [11:0]M_AXI_GP1_ARID;
+  wire [3:0]M_AXI_GP1_ARLEN;
+  wire [1:0]M_AXI_GP1_ARLOCK;
+  wire [2:0]M_AXI_GP1_ARPROT;
+  wire [3:0]M_AXI_GP1_ARQOS;
+  wire M_AXI_GP1_ARREADY;
+  wire [1:0]\\^M_AXI_GP1_ARSIZE ;
+  wire M_AXI_GP1_ARVALID;
+  wire [31:0]M_AXI_GP1_AWADDR;
+  wire [1:0]M_AXI_GP1_AWBURST;
+  wire [3:0]M_AXI_GP1_AWCACHE;
+  wire [11:0]M_AXI_GP1_AWID;
+  wire [3:0]M_AXI_GP1_AWLEN;
+  wire [1:0]M_AXI_GP1_AWLOCK;
+  wire [2:0]M_AXI_GP1_AWPROT;
+  wire [3:0]M_AXI_GP1_AWQOS;
+  wire M_AXI_GP1_AWREADY;
+  wire [1:0]\\^M_AXI_GP1_AWSIZE ;
+  wire M_AXI_GP1_AWVALID;
+  wire [11:0]M_AXI_GP1_BID;
+  wire M_AXI_GP1_BREADY;
+  wire [1:0]M_AXI_GP1_BRESP;
+  wire M_AXI_GP1_BVALID;
+  wire [31:0]M_AXI_GP1_RDATA;
+  wire [11:0]M_AXI_GP1_RID;
+  wire M_AXI_GP1_RLAST;
+  wire M_AXI_GP1_RREADY;
+  wire [1:0]M_AXI_GP1_RRESP;
+  wire M_AXI_GP1_RVALID;
+  wire [31:0]M_AXI_GP1_WDATA;
+  wire [11:0]M_AXI_GP1_WID;
+  wire M_AXI_GP1_WLAST;
+  wire M_AXI_GP1_WREADY;
+  wire [3:0]M_AXI_GP1_WSTRB;
+  wire M_AXI_GP1_WVALID;
+  wire PJTAG_TCK;
+  wire PJTAG_TDI;
+  wire PJTAG_TMS;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_BUSPOW;
+  wire [2:0]SDIO0_BUSVOLT;
+  wire SDIO0_CDN;
+  wire SDIO0_CLK;
+  wire SDIO0_CLK_FB;
+  wire SDIO0_CMD_I;
+  wire SDIO0_CMD_O;
+  wire SDIO0_CMD_T;
+  wire SDIO0_CMD_T_n;
+  wire [3:0]SDIO0_DATA_I;
+  wire [3:0]SDIO0_DATA_O;
+  wire [3:0]SDIO0_DATA_T;
+  wire [3:0]SDIO0_DATA_T_n;
+  wire SDIO0_LED;
+  wire SDIO0_WP;
+  wire SDIO1_BUSPOW;
+  wire [2:0]SDIO1_BUSVOLT;
+  wire SDIO1_CDN;
+  wire SDIO1_CLK;
+  wire SDIO1_CLK_FB;
+  wire SDIO1_CMD_I;
+  wire SDIO1_CMD_O;
+  wire SDIO1_CMD_T;
+  wire SDIO1_CMD_T_n;
+  wire [3:0]SDIO1_DATA_I;
+  wire [3:0]SDIO1_DATA_O;
+  wire [3:0]SDIO1_DATA_T;
+  wire [3:0]SDIO1_DATA_T_n;
+  wire SDIO1_LED;
+  wire SDIO1_WP;
+  wire SPI0_MISO_I;
+  wire SPI0_MISO_O;
+  wire SPI0_MISO_T;
+  wire SPI0_MISO_T_n;
+  wire SPI0_MOSI_I;
+  wire SPI0_MOSI_O;
+  wire SPI0_MOSI_T;
+  wire SPI0_MOSI_T_n;
+  wire SPI0_SCLK_I;
+  wire SPI0_SCLK_O;
+  wire SPI0_SCLK_T;
+  wire SPI0_SCLK_T_n;
+  wire SPI0_SS1_O;
+  wire SPI0_SS2_O;
+  wire SPI0_SS_I;
+  wire SPI0_SS_O;
+  wire SPI0_SS_T;
+  wire SPI0_SS_T_n;
+  wire SPI1_MISO_I;
+  wire SPI1_MISO_O;
+  wire SPI1_MISO_T;
+  wire SPI1_MISO_T_n;
+  wire SPI1_MOSI_I;
+  wire SPI1_MOSI_O;
+  wire SPI1_MOSI_T;
+  wire SPI1_MOSI_T_n;
+  wire SPI1_SCLK_I;
+  wire SPI1_SCLK_O;
+  wire SPI1_SCLK_T;
+  wire SPI1_SCLK_T_n;
+  wire SPI1_SS1_O;
+  wire SPI1_SS2_O;
+  wire SPI1_SS_I;
+  wire SPI1_SS_O;
+  wire SPI1_SS_T;
+  wire SPI1_SS_T_n;
+  wire SRAM_INTIN;
+  wire S_AXI_ACP_ACLK;
+  wire [31:0]S_AXI_ACP_ARADDR;
+  wire [1:0]S_AXI_ACP_ARBURST;
+  wire [3:0]S_AXI_ACP_ARCACHE;
+  wire S_AXI_ACP_ARESETN;
+  wire [2:0]S_AXI_ACP_ARID;
+  wire [3:0]S_AXI_ACP_ARLEN;
+  wire [1:0]S_AXI_ACP_ARLOCK;
+  wire [2:0]S_AXI_ACP_ARPROT;
+  wire [3:0]S_AXI_ACP_ARQOS;
+  wire S_AXI_ACP_ARREADY;
+  wire [2:0]S_AXI_ACP_ARSIZE;
+  wire [4:0]S_AXI_ACP_ARUSER;
+  wire S_AXI_ACP_ARVALID;
+  wire [31:0]S_AXI_ACP_AWADDR;
+  wire [1:0]S_AXI_ACP_AWBURST;
+  wire [3:0]S_AXI_ACP_AWCACHE;
+  wire [2:0]S_AXI_ACP_AWID;
+  wire [3:0]S_AXI_ACP_AWLEN;
+  wire [1:0]S_AXI_ACP_AWLOCK;
+  wire [2:0]S_AXI_ACP_AWPROT;
+  wire [3:0]S_AXI_ACP_AWQOS;
+  wire S_AXI_ACP_AWREADY;
+  wire [2:0]S_AXI_ACP_AWSIZE;
+  wire [4:0]S_AXI_ACP_AWUSER;
+  wire S_AXI_ACP_AWVALID;
+  wire [2:0]S_AXI_ACP_BID;
+  wire S_AXI_ACP_BREADY;
+  wire [1:0]S_AXI_ACP_BRESP;
+  wire S_AXI_ACP_BVALID;
+  wire [63:0]S_AXI_ACP_RDATA;
+  wire [2:0]S_AXI_ACP_RID;
+  wire S_AXI_ACP_RLAST;
+  wire S_AXI_ACP_RREADY;
+  wire [1:0]S_AXI_ACP_RRESP;
+  wire S_AXI_ACP_RVALID;
+  wire [63:0]S_AXI_ACP_WDATA;
+  wire [2:0]S_AXI_ACP_WID;
+  wire S_AXI_ACP_WLAST;
+  wire S_AXI_ACP_WREADY;
+  wire [7:0]S_AXI_ACP_WSTRB;
+  wire S_AXI_ACP_WVALID;
+  wire S_AXI_GP0_ACLK;
+  wire [31:0]S_AXI_GP0_ARADDR;
+  wire [1:0]S_AXI_GP0_ARBURST;
+  wire [3:0]S_AXI_GP0_ARCACHE;
+  wire S_AXI_GP0_ARESETN;
+  wire [5:0]S_AXI_GP0_ARID;
+  wire [3:0]S_AXI_GP0_ARLEN;
+  wire [1:0]S_AXI_GP0_ARLOCK;
+  wire [2:0]S_AXI_GP0_ARPROT;
+  wire [3:0]S_AXI_GP0_ARQOS;
+  wire S_AXI_GP0_ARREADY;
+  wire [2:0]S_AXI_GP0_ARSIZE;
+  wire S_AXI_GP0_ARVALID;
+  wire [31:0]S_AXI_GP0_AWADDR;
+  wire [1:0]S_AXI_GP0_AWBURST;
+  wire [3:0]S_AXI_GP0_AWCACHE;
+  wire [5:0]S_AXI_GP0_AWID;
+  wire [3:0]S_AXI_GP0_AWLEN;
+  wire [1:0]S_AXI_GP0_AWLOCK;
+  wire [2:0]S_AXI_GP0_AWPROT;
+  wire [3:0]S_AXI_GP0_AWQOS;
+  wire S_AXI_GP0_AWREADY;
+  wire [2:0]S_AXI_GP0_AWSIZE;
+  wire S_AXI_GP0_AWVALID;
+  wire [5:0]S_AXI_GP0_BID;
+  wire S_AXI_GP0_BREADY;
+  wire [1:0]S_AXI_GP0_BRESP;
+  wire S_AXI_GP0_BVALID;
+  wire [31:0]S_AXI_GP0_RDATA;
+  wire [5:0]S_AXI_GP0_RID;
+  wire S_AXI_GP0_RLAST;
+  wire S_AXI_GP0_RREADY;
+  wire [1:0]S_AXI_GP0_RRESP;
+  wire S_AXI_GP0_RVALID;
+  wire [31:0]S_AXI_GP0_WDATA;
+  wire [5:0]S_AXI_GP0_WID;
+  wire S_AXI_GP0_WLAST;
+  wire S_AXI_GP0_WREADY;
+  wire [3:0]S_AXI_GP0_WSTRB;
+  wire S_AXI_GP0_WVALID;
+  wire S_AXI_GP1_ACLK;
+  wire [31:0]S_AXI_GP1_ARADDR;
+  wire [1:0]S_AXI_GP1_ARBURST;
+  wire [3:0]S_AXI_GP1_ARCACHE;
+  wire S_AXI_GP1_ARESETN;
+  wire [5:0]S_AXI_GP1_ARID;
+  wire [3:0]S_AXI_GP1_ARLEN;
+  wire [1:0]S_AXI_GP1_ARLOCK;
+  wire [2:0]S_AXI_GP1_ARPROT;
+  wire [3:0]S_AXI_GP1_ARQOS;
+  wire S_AXI_GP1_ARREADY;
+  wire [2:0]S_AXI_GP1_ARSIZE;
+  wire S_AXI_GP1_ARVALID;
+  wire [31:0]S_AXI_GP1_AWADDR;
+  wire [1:0]S_AXI_GP1_AWBURST;
+  wire [3:0]S_AXI_GP1_AWCACHE;
+  wire [5:0]S_AXI_GP1_AWID;
+  wire [3:0]S_AXI_GP1_AWLEN;
+  wire [1:0]S_AXI_GP1_AWLOCK;
+  wire [2:0]S_AXI_GP1_AWPROT;
+  wire [3:0]S_AXI_GP1_AWQOS;
+  wire S_AXI_GP1_AWREADY;
+  wire [2:0]S_AXI_GP1_AWSIZE;
+  wire S_AXI_GP1_AWVALID;
+  wire [5:0]S_AXI_GP1_BID;
+  wire S_AXI_GP1_BREADY;
+  wire [1:0]S_AXI_GP1_BRESP;
+  wire S_AXI_GP1_BVALID;
+  wire [31:0]S_AXI_GP1_RDATA;
+  wire [5:0]S_AXI_GP1_RID;
+  wire S_AXI_GP1_RLAST;
+  wire S_AXI_GP1_RREADY;
+  wire [1:0]S_AXI_GP1_RRESP;
+  wire S_AXI_GP1_RVALID;
+  wire [31:0]S_AXI_GP1_WDATA;
+  wire [5:0]S_AXI_GP1_WID;
+  wire S_AXI_GP1_WLAST;
+  wire S_AXI_GP1_WREADY;
+  wire [3:0]S_AXI_GP1_WSTRB;
+  wire S_AXI_GP1_WVALID;
+  wire S_AXI_HP0_ACLK;
+  wire [31:0]S_AXI_HP0_ARADDR;
+  wire [1:0]S_AXI_HP0_ARBURST;
+  wire [3:0]S_AXI_HP0_ARCACHE;
+  wire S_AXI_HP0_ARESETN;
+  wire [5:0]S_AXI_HP0_ARID;
+  wire [3:0]S_AXI_HP0_ARLEN;
+  wire [1:0]S_AXI_HP0_ARLOCK;
+  wire [2:0]S_AXI_HP0_ARPROT;
+  wire [3:0]S_AXI_HP0_ARQOS;
+  wire S_AXI_HP0_ARREADY;
+  wire [2:0]S_AXI_HP0_ARSIZE;
+  wire S_AXI_HP0_ARVALID;
+  wire [31:0]S_AXI_HP0_AWADDR;
+  wire [1:0]S_AXI_HP0_AWBURST;
+  wire [3:0]S_AXI_HP0_AWCACHE;
+  wire [5:0]S_AXI_HP0_AWID;
+  wire [3:0]S_AXI_HP0_AWLEN;
+  wire [1:0]S_AXI_HP0_AWLOCK;
+  wire [2:0]S_AXI_HP0_AWPROT;
+  wire [3:0]S_AXI_HP0_AWQOS;
+  wire S_AXI_HP0_AWREADY;
+  wire [2:0]S_AXI_HP0_AWSIZE;
+  wire S_AXI_HP0_AWVALID;
+  wire [5:0]S_AXI_HP0_BID;
+  wire S_AXI_HP0_BREADY;
+  wire [1:0]S_AXI_HP0_BRESP;
+  wire S_AXI_HP0_BVALID;
+  wire [2:0]S_AXI_HP0_RACOUNT;
+  wire [7:0]S_AXI_HP0_RCOUNT;
+  wire [63:0]S_AXI_HP0_RDATA;
+  wire S_AXI_HP0_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP0_RID;
+  wire S_AXI_HP0_RLAST;
+  wire S_AXI_HP0_RREADY;
+  wire [1:0]S_AXI_HP0_RRESP;
+  wire S_AXI_HP0_RVALID;
+  wire [5:0]S_AXI_HP0_WACOUNT;
+  wire [7:0]S_AXI_HP0_WCOUNT;
+  wire [63:0]S_AXI_HP0_WDATA;
+  wire [5:0]S_AXI_HP0_WID;
+  wire S_AXI_HP0_WLAST;
+  wire S_AXI_HP0_WREADY;
+  wire S_AXI_HP0_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP0_WSTRB;
+  wire S_AXI_HP0_WVALID;
+  wire S_AXI_HP1_ACLK;
+  wire [31:0]S_AXI_HP1_ARADDR;
+  wire [1:0]S_AXI_HP1_ARBURST;
+  wire [3:0]S_AXI_HP1_ARCACHE;
+  wire S_AXI_HP1_ARESETN;
+  wire [5:0]S_AXI_HP1_ARID;
+  wire [3:0]S_AXI_HP1_ARLEN;
+  wire [1:0]S_AXI_HP1_ARLOCK;
+  wire [2:0]S_AXI_HP1_ARPROT;
+  wire [3:0]S_AXI_HP1_ARQOS;
+  wire S_AXI_HP1_ARREADY;
+  wire [2:0]S_AXI_HP1_ARSIZE;
+  wire S_AXI_HP1_ARVALID;
+  wire [31:0]S_AXI_HP1_AWADDR;
+  wire [1:0]S_AXI_HP1_AWBURST;
+  wire [3:0]S_AXI_HP1_AWCACHE;
+  wire [5:0]S_AXI_HP1_AWID;
+  wire [3:0]S_AXI_HP1_AWLEN;
+  wire [1:0]S_AXI_HP1_AWLOCK;
+  wire [2:0]S_AXI_HP1_AWPROT;
+  wire [3:0]S_AXI_HP1_AWQOS;
+  wire S_AXI_HP1_AWREADY;
+  wire [2:0]S_AXI_HP1_AWSIZE;
+  wire S_AXI_HP1_AWVALID;
+  wire [5:0]S_AXI_HP1_BID;
+  wire S_AXI_HP1_BREADY;
+  wire [1:0]S_AXI_HP1_BRESP;
+  wire S_AXI_HP1_BVALID;
+  wire [2:0]S_AXI_HP1_RACOUNT;
+  wire [7:0]S_AXI_HP1_RCOUNT;
+  wire [63:0]S_AXI_HP1_RDATA;
+  wire S_AXI_HP1_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP1_RID;
+  wire S_AXI_HP1_RLAST;
+  wire S_AXI_HP1_RREADY;
+  wire [1:0]S_AXI_HP1_RRESP;
+  wire S_AXI_HP1_RVALID;
+  wire [5:0]S_AXI_HP1_WACOUNT;
+  wire [7:0]S_AXI_HP1_WCOUNT;
+  wire [63:0]S_AXI_HP1_WDATA;
+  wire [5:0]S_AXI_HP1_WID;
+  wire S_AXI_HP1_WLAST;
+  wire S_AXI_HP1_WREADY;
+  wire S_AXI_HP1_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP1_WSTRB;
+  wire S_AXI_HP1_WVALID;
+  wire S_AXI_HP2_ACLK;
+  wire [31:0]S_AXI_HP2_ARADDR;
+  wire [1:0]S_AXI_HP2_ARBURST;
+  wire [3:0]S_AXI_HP2_ARCACHE;
+  wire S_AXI_HP2_ARESETN;
+  wire [5:0]S_AXI_HP2_ARID;
+  wire [3:0]S_AXI_HP2_ARLEN;
+  wire [1:0]S_AXI_HP2_ARLOCK;
+  wire [2:0]S_AXI_HP2_ARPROT;
+  wire [3:0]S_AXI_HP2_ARQOS;
+  wire S_AXI_HP2_ARREADY;
+  wire [2:0]S_AXI_HP2_ARSIZE;
+  wire S_AXI_HP2_ARVALID;
+  wire [31:0]S_AXI_HP2_AWADDR;
+  wire [1:0]S_AXI_HP2_AWBURST;
+  wire [3:0]S_AXI_HP2_AWCACHE;
+  wire [5:0]S_AXI_HP2_AWID;
+  wire [3:0]S_AXI_HP2_AWLEN;
+  wire [1:0]S_AXI_HP2_AWLOCK;
+  wire [2:0]S_AXI_HP2_AWPROT;
+  wire [3:0]S_AXI_HP2_AWQOS;
+  wire S_AXI_HP2_AWREADY;
+  wire [2:0]S_AXI_HP2_AWSIZE;
+  wire S_AXI_HP2_AWVALID;
+  wire [5:0]S_AXI_HP2_BID;
+  wire S_AXI_HP2_BREADY;
+  wire [1:0]S_AXI_HP2_BRESP;
+  wire S_AXI_HP2_BVALID;
+  wire [2:0]S_AXI_HP2_RACOUNT;
+  wire [7:0]S_AXI_HP2_RCOUNT;
+  wire [63:0]S_AXI_HP2_RDATA;
+  wire S_AXI_HP2_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP2_RID;
+  wire S_AXI_HP2_RLAST;
+  wire S_AXI_HP2_RREADY;
+  wire [1:0]S_AXI_HP2_RRESP;
+  wire S_AXI_HP2_RVALID;
+  wire [5:0]S_AXI_HP2_WACOUNT;
+  wire [7:0]S_AXI_HP2_WCOUNT;
+  wire [63:0]S_AXI_HP2_WDATA;
+  wire [5:0]S_AXI_HP2_WID;
+  wire S_AXI_HP2_WLAST;
+  wire S_AXI_HP2_WREADY;
+  wire S_AXI_HP2_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP2_WSTRB;
+  wire S_AXI_HP2_WVALID;
+  wire S_AXI_HP3_ACLK;
+  wire [31:0]S_AXI_HP3_ARADDR;
+  wire [1:0]S_AXI_HP3_ARBURST;
+  wire [3:0]S_AXI_HP3_ARCACHE;
+  wire S_AXI_HP3_ARESETN;
+  wire [5:0]S_AXI_HP3_ARID;
+  wire [3:0]S_AXI_HP3_ARLEN;
+  wire [1:0]S_AXI_HP3_ARLOCK;
+  wire [2:0]S_AXI_HP3_ARPROT;
+  wire [3:0]S_AXI_HP3_ARQOS;
+  wire S_AXI_HP3_ARREADY;
+  wire [2:0]S_AXI_HP3_ARSIZE;
+  wire S_AXI_HP3_ARVALID;
+  wire [31:0]S_AXI_HP3_AWADDR;
+  wire [1:0]S_AXI_HP3_AWBURST;
+  wire [3:0]S_AXI_HP3_AWCACHE;
+  wire [5:0]S_AXI_HP3_AWID;
+  wire [3:0]S_AXI_HP3_AWLEN;
+  wire [1:0]S_AXI_HP3_AWLOCK;
+  wire [2:0]S_AXI_HP3_AWPROT;
+  wire [3:0]S_AXI_HP3_AWQOS;
+  wire S_AXI_HP3_AWREADY;
+  wire [2:0]S_AXI_HP3_AWSIZE;
+  wire S_AXI_HP3_AWVALID;
+  wire [5:0]S_AXI_HP3_BID;
+  wire S_AXI_HP3_BREADY;
+  wire [1:0]S_AXI_HP3_BRESP;
+  wire S_AXI_HP3_BVALID;
+  wire [2:0]S_AXI_HP3_RACOUNT;
+  wire [7:0]S_AXI_HP3_RCOUNT;
+  wire [63:0]S_AXI_HP3_RDATA;
+  wire S_AXI_HP3_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP3_RID;
+  wire S_AXI_HP3_RLAST;
+  wire S_AXI_HP3_RREADY;
+  wire [1:0]S_AXI_HP3_RRESP;
+  wire S_AXI_HP3_RVALID;
+  wire [5:0]S_AXI_HP3_WACOUNT;
+  wire [7:0]S_AXI_HP3_WCOUNT;
+  wire [63:0]S_AXI_HP3_WDATA;
+  wire [5:0]S_AXI_HP3_WID;
+  wire S_AXI_HP3_WLAST;
+  wire S_AXI_HP3_WREADY;
+  wire S_AXI_HP3_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP3_WSTRB;
+  wire S_AXI_HP3_WVALID;
+  wire TRACE_CLK;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[7] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[7] ;
+  wire TTC0_CLK0_IN;
+  wire TTC0_CLK1_IN;
+  wire TTC0_CLK2_IN;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire TTC1_CLK0_IN;
+  wire TTC1_CLK1_IN;
+  wire TTC1_CLK2_IN;
+  wire TTC1_WAVE0_OUT;
+  wire TTC1_WAVE1_OUT;
+  wire TTC1_WAVE2_OUT;
+  wire UART0_CTSN;
+  wire UART0_DCDN;
+  wire UART0_DSRN;
+  wire UART0_DTRN;
+  wire UART0_RIN;
+  wire UART0_RTSN;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire UART1_CTSN;
+  wire UART1_DCDN;
+  wire UART1_DSRN;
+  wire UART1_DTRN;
+  wire UART1_RIN;
+  wire UART1_RTSN;
+  wire UART1_RX;
+  wire UART1_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire [1:0]USB1_PORT_INDCTL;
+  wire USB1_VBUS_PWRFAULT;
+  wire USB1_VBUS_PWRSELECT;
+  wire WDT_CLK_IN;
+  wire WDT_RST_OUT;
+  wire [14:0]buffered_DDR_Addr;
+  wire [2:0]buffered_DDR_BankAddr;
+  wire buffered_DDR_CAS_n;
+  wire buffered_DDR_CKE;
+  wire buffered_DDR_CS_n;
+  wire buffered_DDR_Clk;
+  wire buffered_DDR_Clk_n;
+  wire [3:0]buffered_DDR_'b'DM;
+  wire [31:0]buffered_DDR_DQ;
+  wire [3:0]buffered_DDR_DQS;
+  wire [3:0]buffered_DDR_DQS_n;
+  wire buffered_DDR_DRSTB;
+  wire buffered_DDR_ODT;
+  wire buffered_DDR_RAS_n;
+  wire buffered_DDR_VRN;
+  wire buffered_DDR_VRP;
+  wire buffered_DDR_WEB;
+  wire [53:0]buffered_MIO;
+  wire buffered_PS_CLK;
+  wire buffered_PS_PORB;
+  wire buffered_PS_SRSTB;
+  wire [63:0]gpio_out_t_n;
+  wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
+  wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+
+  assign ENET0_GMII_TXD[7] = \\<const0> ;
+  assign ENET0_GMII_TXD[6] = \\<const0> ;
+  assign ENET0_GMII_TXD[5] = \\<const0> ;
+  assign ENET0_GMII_TXD[4] = \\<const0> ;
+  assign ENET0_GMII_TXD[3] = \\<const0> ;
+  assign ENET0_GMII_TXD[2] = \\<const0> ;
+  assign ENET0_GMII_TXD[1] = \\<const0> ;
+  assign ENET0_GMII_TXD[0] = \\<const0> ;
+  assign ENET0_GMII_TX_EN = \\<const0> ;
+  assign ENET0_GMII_TX_ER = \\<const0> ;
+  assign ENET1_GMII_TXD[7] = \\<const0> ;
+  assign ENET1_GMII_TXD[6] = \\<const0> ;
+  assign ENET1_GMII_TXD[5] = \\<const0> ;
+  assign ENET1_GMII_TXD[4] = \\<const0> ;
+  assign ENET1_GMII_TXD[3] = \\<const0> ;
+  assign ENET1_GMII_TXD[2] = \\<const0> ;
+  assign ENET1_GMII_TXD[1] = \\<const0> ;
+  assign ENET1_GMII_TXD[0] = \\<const0> ;
+  assign ENET1_GMII_TX_EN = \\<const0> ;
+  assign ENET1_GMII_TX_ER = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[1:0] = \\^M_AXI_GP0_ARSIZE [1:0];
+  assign M_AXI_GP0_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_AWSIZE[1:0] = \\^M_AXI_GP0_AWSIZE [1:0];
+  assign M_AXI_GP1_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_ARSIZE[1:0] = \\^M_AXI_GP1_ARSIZE [1:0];
+  assign M_AXI_GP1_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_AWSIZE[1:0] = \\^M_AXI_GP1_AWSIZE [1:0];
+  assign PJTAG_TDO = \\<const0> ;
+  assign TRACE_CLK_OUT = \\<const0> ;
+  assign TRACE_CTL = \\TRACE_CTL_PIPE[0] ;
+  assign TRACE_DATA[1:0] = \\TRACE_DATA_PIPE[0] ;
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CAS_n_BIBUF
+       (.IO(buffered_DDR_CAS_n),
+        .PAD(DDR_CAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CKE_BIBUF
+       (.IO(buffered_DDR_CKE),
+        .PAD(DDR_CKE));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CS_n_BIBUF
+       (.IO(buffered_DDR_CS_n),
+        .PAD(DDR_CS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_BIBUF
+       (.IO(buffered_DDR_Clk),
+        .PAD(DDR_Clk));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_n_BIBUF
+       (.IO(buffered_DDR_Clk_n),
+        .PAD(DDR_Clk_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_DRSTB_BIBUF
+       (.IO(buffered_DDR_DRSTB),
+        .PAD(DDR_DRSTB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_ODT_BIBUF
+       (.IO(buffered_DDR_ODT),
+        .PAD(DDR_ODT));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_RAS_n_BIBUF
+       (.IO(buffered_DDR_RAS_n),
+        .PAD(DDR_RAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRN_BIBUF
+       (.IO(buffered_DDR_VRN),
+        .PAD(DDR_VRN));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRP_BIBUF
+       (.IO(buffered_DDR_VRP),
+        .PAD(DDR_VRP));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_WEB_BIBUF
+       (.IO(buffered_DDR_WEB),
+        .PAD(DDR_WEB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET0_MDIO_T_INST_0
+       (.I0(ENET0_MDIO_T_n),
+        .O(ENET0_MDIO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET1_MDIO_T_INST_0
+       (.I0(ENET1_MDIO_T_n),
+        .O(ENET1_MDIO_T));
+  GND GND
+       (.G(\\<const0> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[0]_INST_0 
+       (.I0(gpio_out_t_n[0]),
+        .O(GPIO_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[10]_INST_0 
+       (.I0(gpio_out_t_n[10]),
+        .O(GPIO_T[10]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[11]_INST_0 
+       (.I0(gpio_out_t_n[11]),
+        .O(GPIO_T[11]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[12]_INST_0 
+       (.I0(gpio_out_t_n[12]),
+        .O(GPIO_T[12]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[13]_INST_0 
+       (.I0(gpio_out_t_n[13]),
+        .O(GPIO_T[13]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[14]_INST_0 
+       (.I0(gpio_out_t_n[14]),
+        .O(GPIO_T[14]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[15]_INST_0 
+       (.I0(gpio_out_t_n[15]),
+        .O(GPIO_T[15]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[16]_INST_0 
+       (.I0(gpio_out_t_n[16]),
+        .O(GPIO_T[16]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[17]_INST_0 
+       (.I0(gpio_out_t_n[17]),
+        .O(GPIO_T[17]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[18]_INST_0 
+       (.I0(gpio_out_t_n[18]),
+        .O(GPIO_T[18]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[19]_INST_0 
+       (.I0(gpio_out_t_n[19]),
+        .O(GPIO_T[19]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[1]_INST_0 
+       (.I0(gpio_out_t_n[1]),
+        .O(GPIO_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[20]_INST_0 
+       (.I0(gpio_out_t_n[20]),
+        .O(GPIO_T[20]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[21]_INST_0 
+       (.I0(gpio_out_t_n[21]),
+        .O(GPIO_T[21]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[22]_INST_0 
+       (.I0(gpio_out_t_n[22]),
+        .O(GPIO_T[22]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[23]_INST_0 
+       (.I0(gpio_out_t_n[23]),
+        .O(GPIO_T[23]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[24]_INST_0 
+       (.I0(gpio_out_t_n[24]),
+        .O(GPIO_T[24]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[25]_INST_0 
+       (.I0(gpio_out_t_n[25]),
+        .O(GPIO_T[25]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[26]_INST_0 
+       (.I0(gpio_out_t_n[26]),
+        .O(GPIO_T[26]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[27]_INST_0 
+       (.I0(gpio_out_t_n[27]),
+        .O(GPIO_T[27]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[28]_INST_0 
+       (.I0(gpio_out_t_n[28]),
+        .O(GPIO_T[28]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[29]_INST_0 
+       (.I0(gpio_out_t_n[29]),
+        .O(GPIO_T[29]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[2]_INST_0 
+       (.I0(gpio_out_t_n[2]),
+        .O(GPIO_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[30]_INST_0 
+       (.I0(gpio_out_t_n[30]),
+        .O(GPIO_T[30]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[31]_INST_0 
+       (.I0(gpio_out_t_n[31]),
+        .O(GPIO_T[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[32]_INST_0 
+       (.I0(gpio_out_t_n[32]),
+        .O(GPIO_T[32]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[33]_INST_0 
+       (.I0(gpio_out_t_n[33]),
+        .O(GPIO_T[33]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[34]_INST_0 
+       (.I0(gpio_out_t_n[34]),
+        .O(GPIO_T[34]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[35]_INST_0 
+       (.I0(gpio_out_t_n[35]),
+        .O(GPIO_T[35]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[36]_INST_0 
+       (.I0(gpio_out_t_n[36]),
+        .O(GPIO_T[36]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[37]_INST_0 
+       (.I0(gpio_out_t_n[37]),
+        .O(GPIO_T[37]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[38]_INST_0 
+       (.I0(gpio_out_t_n[38]),
+        .O(GPIO_T[38]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[39]_INST_0 
+       (.I0(gpio_out_t_n[39]),
+        .O(GPIO_T[39]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[3]_INST_0 
+       (.I0(gpio_out_t_n[3]),
+        .O(GPIO_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[40]_INST_0 
+       (.I0(gpio_out_t_n[40]),
+        .O(GPIO_T[40]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[41]_INST_0 
+       (.I0(gpio_out_t_n[41]),
+        .O(GPIO_T[41]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[42]_INST_0 
+       (.I0(gpio_out_t_n[42]),
+        .O(GPIO_T[42]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[43]_INST_0 
+       (.I0(gpio_out_t_n[43]),
+        .O(GPIO_T[43]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[44]_INST_0 
+       (.I0(gpio_out_t_n[44]),
+        .O(GPIO_T[44]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[45]_INST_0 
+       (.I0(gpio_out_t_n[45]),
+        .O(GPIO_T[45]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[46]_INST_0 
+       (.I0(gpio_out_t_n[46]),
+        .O(GPIO_T[46]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[47]_INST_0 
+       (.I0(gpio_out_t_n[47]),
+        .O(GPIO_T[47]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[48]_INST_0 
+       (.I0(gpio_out_t_n[48]),
+        .O(GPIO_T[48]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[49]_INST_0 
+       (.I0(gpio_out_t_n[49]),
+        .O(GPIO_T[49]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[4]_INST_0 
+       (.I0(gpio_out_t_n[4]),
+        .O(GPIO_T[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[50]_INST_0 
+       (.I0(gpio_out_t_n[50]),
+        .O(GPIO_T[50]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[51]_INST_0 
+       (.I0(gpio_out_t_n[51]),
+        .O(GPIO_T[51]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[52]_INST_0 
+       (.I0(gpio_out_t_n[52]),
+        .O(GPIO_T[52]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[53]_INST_0 
+       (.I0(gpio_out_t_n[53]),
+        .O(GPIO_T[53]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[54]_INST_0 
+       (.I0(gpio_out_t_n[54]),
+        .O(GPIO_T[54]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[55]_INST_0 
+       (.I0(gpio_out_t_n[55]),
+        .O(GPIO_T[55]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[56]_INST_0 
+       (.I0(gpio_out_t_n[56]),
+        .O(GPIO_T[56]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[57]_INST_0 
+       (.I0(gpio_out_t_n[57]),
+        .O(GPIO_T[57]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[58]_INST_0 
+       (.I0(gpio_out_t_n[58]),
+        .O(GPIO_T[58]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[59]_INST_0 
+       (.I0(gpio_out_t_n[59]),
+        .O(GPIO_T[59]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[5]_INST_0 
+       (.I0(gpio_out_t_n[5]),
+        .O(GPIO_T[5]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[60]_INST_0 
+       (.I0(gpio_out_t_n[60]),
+        .O(GPIO_T[60]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[61]_INST_0 
+       (.I0(gpio_out_t_n[61]),
+        .O(GPIO_T[61]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[62]_INST_0 
+       (.I0(gpio_out_t_n[62]),
+        .O(GPIO_T[62]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[63]_INST_0 
+       (.I0(gpio_out_t_n[63]),
+        .O(GPIO_T[63]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[6]_INST_0 
+       (.I0(gpio_out_t_n[6]),
+        .O(GPIO_T[6]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[7]_INST_0 
+       (.I0(gpio_out_t_n[7]),
+        .O(GPIO_T[7]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[8]_INST_0 
+       (.I0(gpio_out_t_n[8]),
+        .O(GPIO_T[8]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[9]_INST_0 
+       (.I0(gpio_out_t_n[9]),
+        .O(GPIO_T[9]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SCL_T_INST_0
+       (.I0(I2C0_SCL_T_n),
+        .O(I2C0_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SDA_T_INST_0
+       (.I0(I2C0_SDA_T_n),
+        .O(I2C0_SDA_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SCL_T_INST_0
+       (.I0(I2C1_SCL_T_n),
+        .O(I2C1_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SDA_T_INST_0
+       (.I0(I2C1_SDA_T_n),
+        .O(I2C1_SDA_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  PS7 PS7_i
+       (.DDRA(buffered_DDR_Addr),
+        .DDRARB(DDR_ARB),
+        .DDRBA(buffered_DDR_BankAddr),
+        .DDRCASB(buffered_DDR_CAS_n),
+        .DDRCKE(buffered_DDR_CKE),
+        .DDRCKN(buffered_DDR_Clk_n),
+        .DDRCKP(buffered_DDR_Clk),
+        .DDRCSB(buffered_DDR_CS_n),
+        .DDRDM(buffered_DDR_DM),
+        .DDRDQ(buffered_DDR_DQ),
+        .DDRDQSN(buffered_DDR_DQS_n),
+        .DDRDQSP(buffered_DDR_DQS),
+        .DDRDRSTB(buffered_DDR_DRSTB),
+        .DDRODT(buffered_DDR_ODT),
+        .DDRRASB(buffered_DDR_RAS_n),
+        .DDRVRN(buffered_DDR_VRN),
+        .DDRVRP(buffered_DDR_VRP),
+        .DDRWEB(buffered_DDR_WEB),
+        .DMA0ACLK(DMA0_ACLK),
+        .DMA0DAREADY(DMA0_DAREADY),
+        .DMA0DATYPE(DMA0_DATYPE),
+        .DMA0DAVALID(DMA0_DAVALID),
+        .DMA0DRLAST(DMA0_DRLAST),
+        .DMA0DRREADY(DMA0_DRREADY),
+        .DMA0DRTYPE(DMA0_DRTYPE),
+        .DMA0DRVALID(DMA0_DRVALID),
+        .DMA0RSTN(DMA0_RSTN),
+        .DMA1ACLK(DMA1_ACLK),
+        .DMA1DAREADY(DMA1_DAREADY),
+        .DMA1DATYPE(DMA1_DATYPE),
+        .DMA1DAVALID(DMA1_DAVALID),
+        .DMA1DRLAST(DMA1_DRLAST),
+        .DMA1DRREADY(DMA1_DRREADY),
+        .DMA1DRTYPE(DMA1_DRTYPE),
+        .DMA1DRVALID(DMA1_DRVALID),
+        .DMA1RSTN(DMA1_RSTN),
+        .DMA2ACLK(DMA2_ACLK),
+        .DMA2DAREADY(DMA2_DAREADY),
+        .DMA2DATYPE(DMA2_DATYPE),
+        .DMA2DAVALID(DMA2_DAVALID),
+        .DMA2DRLAST(DMA2_DRLAST),
+        .DMA2DRREADY(DMA2_DRREADY),
+        .DMA2DRTYPE(DMA2_DRTYPE),
+        .DMA2DRVALID(DMA2_DRVALID),
+        .DMA2RSTN(DMA2_RSTN),
+        .DMA3ACLK(DMA3_ACLK),
+        .DMA3DAREADY(DMA3_DAREADY),
+        .DMA3DATYPE(DMA3_DATYPE),
+        .DMA3DAVALID(DMA3_DAVALID),
+        .DMA3DRLAST(DMA3_DRLAST),
+        .DMA3DRREADY(DMA3_DRREADY),
+        .DMA3DRTYPE(DMA3_DRTYPE),
+        .DMA3DRVALID(DMA3_DRVALID),
+        .DMA3RSTN(DMA3_RSTN),
+        .EMIOCAN0PHYRX(CAN0_PHY_RX),
+        .EMIOCAN0PHYTX(CAN0_PHY_TX),
+        .EMIOCAN1PHYRX(CAN1_PHY_RX),
+        .EMIOCAN1PHYTX(CAN1_PHY_TX),
+        .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+        .EMIOENET0GMIICOL(1\'b0),
+        .EMIOENET0GMIICRS(1\'b0),
+        .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+        .EMIOENET0GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET0GMIIRXDV(1\'b0),
+        .EMIOENET0GMIIRXER(1\'b0),
+        .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+        .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+        .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+        .EMIOENET0MDIOI(ENET0_MDIO_I),
+        .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+        .EMIOENET0MDIOO(ENET0_MDIO_O),
+        .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+        .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+        .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+        .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+        .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+        .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+        .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+        .EMIOENET0SOFRX(ENET0_SOF_RX),
+        .EMIOENET0SOFTX(ENET0_SOF_TX),
+        .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+        .EMIOENET1GMIICOL(1\'b0),
+        .EMIOENET1GMIICRS(1\'b0),
+        .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+        .EMIOENET1GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET1GMIIRXDV(1\'b0),
+        .EMIOENET1GMIIRXER(1\'b0),
+        .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+        .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+        .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+        .EMIOENET1MDIOI(ENET1_MDIO_I),
+        .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+        .EMIOENET1MDIOO(ENET1_MDIO_O),
+        .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+        .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+        .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+        .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+        .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+        .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+        .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+        .EMIOENET1SOFRX(ENET1_SOF_RX),
+        .EMIOENET1SOFTX(ENET1_SOF_TX),
+        .EMIOGPIOI(GPIO_I),
+        .EMIOGPIOO(GPIO_O),
+        .EMIOGPIOTN(gpio_out_t_n),
+        .EMIOI2C0SCLI(I2C0_SCL_I),
+        .EMIOI2C0SCLO(I2C0_SCL_O),
+        .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+        .EMIOI2C0SDAI(I2C0_SDA_I),
+        .EMIOI2C0SDAO(I2C0_SDA_O),
+        .EMIOI2C0SDATN(I2C0_SDA_T_n),
+        .EMIOI2C1SCLI(I2C1_SCL_I),
+        .EMIOI2C1SCLO(I2C1_SCL_O),
+        .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+        .EMIOI2C1SDAI(I2C1_SDA_I),
+        .EMIOI2C1SDAO(I2C1_SDA_O),
+        .EMIOI2C1SDATN(I2C1_SDA_T_n),
+        .EMIOPJTAGTCK(PJTAG_TCK),
+        .EMIOPJTAGTDI(PJTAG_TDI),
+        .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+        .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+        .EMIOPJTAGTMS(PJTAG_TMS),
+        .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+        .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+        .EMIOSDIO0CDN(SDIO0_CDN),
+        .EMIOSDIO0CLK(SDIO0_CLK),
+        .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+        .EMIOSDIO0CMDI(SDIO0_CMD_I),
+        .EMIOSDIO0CMDO(SDIO0_CMD_O),
+        .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+        .EMIOSDIO0DATAI(SDIO0_DATA_I),
+        .EMIOSDIO0DATAO(SDIO0_DATA_O),
+        .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+        .EMIOSDIO0LED(SDIO0_LED),
+        .EMIOSDIO0WP(SDIO0_WP),
+        .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+        .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+        .EMIOSDIO1CDN(SDIO1_CDN),
+        .EMIOSDIO1CLK(SDIO1_CLK),
+        .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+        .EMIOSDIO1CMDI(SDIO1_CMD_I),
+        .EMIOSDIO1CMDO(SDIO1_CMD_O),
+        .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+        .EMIOSDIO1DATAI(SDIO1_DATA_I),
+        .EMIOSDIO1DATAO(SDIO1_DATA_O),
+        .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+        .EMIOSDIO1LED(SDIO1_LED),
+        .EMIOSDIO1WP(SDIO1_WP),
+        .EMIOSPI0MI(SPI0_MISO_I),
+        .EMIOSPI0MO(SPI0_MOSI_O),
+        .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+        .EMIOSPI0SCLKI(SPI0_SCLK_I),
+        .EMIOSPI0SCLKO(SPI0_SCLK_O),
+        .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+        .EMIOSPI0SI(SPI0_MOSI_I),
+        .EMIOSPI0SO(SPI0_MISO_O),
+        .EMIOSPI0SSIN(SPI0_SS_I),
+        .EMIOSPI0SSNTN(SPI0_SS_T_n),
+        .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+        .EMIOSPI0STN(SPI0_MISO_T_n),
+        .EMIOSPI1MI(SPI1_MISO_I),
+        .EMIOSPI1MO(SPI1_MOSI_O),
+        .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+        .EMIOSPI1SCLKI(SPI1_SCLK_I),
+        .EMIOSPI1SCLKO(SPI1_SCLK_O),
+        .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+        .EMIOSPI1SI(SPI1_MOSI_I),
+        .EMIOSPI1SO(SPI1_MISO_O),
+        .EMIOSPI1SSIN(SPI1_SS_I),
+        .EMIOSPI1SSNTN(SPI1_SS_T_n),
+        .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+        .EMIOSPI1STN(SPI1_MISO_T_n),
+        .EMIOSRAMINTIN(SRAM_INTIN),
+        .EMIOTRACECLK(TRACE_CLK),
+        .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+        .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+        .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+        .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+        .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+        .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+        .EMIOUART0CTSN(UART0_CTSN),
+        .EMIOUART0DCDN(UART0_DCDN),
+        .EMIOUART0DSRN(UART0_DSRN),
+        .EMIOUART0DTRN(UART0_DTRN),
+        .EMIOUART0RIN(UART0_RIN),
+        .EMIOUART0RTSN(UART0_RTSN),
+        .EMIOUART0RX(UART0_RX),
+        .EMIOUART0TX(UART0_TX),
+        .EMIOUART1CTSN(UART1_CTSN),
+        .EMIOUART1DCDN(UART1_DCDN),
+        .EMIOUART1DSRN(UART1_DSRN),
+        .EMIOUART1DTRN(UART1_DTRN),
+        .EMIOUART1RIN(UART1_RIN),
+        .EMIOUART1RTSN(UART1_RTSN),
+        .EMIOUART1RX(UART1_RX),
+        .EMIOUART1TX(UART1_TX),
+        .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+        .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+        .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+        .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+        .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+        .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+        .EMIOWDTCLKI(WDT_CLK_IN),
+        .EMIOWDTRSTO(WDT_RST_OUT),
+        .EVENTEVENTI(EVENT_EVENTI),
+        .EVENTEVENTO(EVENT_EVENTO),
+        .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+        .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+        .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+        .FCLKCLKTRIGN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+        .FPGAIDLEN(FPGA_IDLE_N),
+        .FTMDTRACEINATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+        .FTMDTRACEINDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINVALID(1\'b0),
+        .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+        .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+        .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+        .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+        .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+        .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+        .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,IRQ_F2P}),
+        .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+        .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+        .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+        .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+        .MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
+        .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+        .MAXIGP0ARID(M_AXI_GP0_ARID),
+        .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+        .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+        .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+        .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+        .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+        .MAXIGP0ARSIZE(\\^M_AXI_GP0_ARSIZE ),
+        .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+        .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+        .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+        .MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
+        .MAXIGP0AWID(M_AXI_GP0_AWID),
+        .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+        .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+        .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+        .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+        .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+        .MAXIGP0AWSIZE(\\^M_AXI_GP0_AWSIZE ),
+        .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+        .MAXIGP0BID(M_AXI_GP0_BID),
+        .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+        .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+        .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+        .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+        .MAXIGP0RID(M_AXI_GP0_RID),
+        .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+        .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+        .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+        .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+        .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+        .MAXIGP0WID(M_AXI_GP0_WID),
+        .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+        .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+        .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+        .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+        .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+        .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+        .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+        .MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
+        .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+        .MAXIGP1ARID(M_AXI_GP1_ARID),
+        .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+        .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+        .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+        .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+        .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+        .MAXIGP1ARSIZE(\\^M_AXI_GP1_ARSIZE ),
+        .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+        .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+        .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+        .MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
+        .MAXIGP1AWID(M_AXI_GP1_AWID),
+        .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+        .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+        .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+        .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+        .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+        .MAXIGP1AWSIZE(\\^M_AXI_GP1_AWSIZE ),
+        .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+        .MAXIGP1BID(M_AXI_GP1_BID),
+        .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+        .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+        .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+        .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+        .MAXIGP1RID(M_AXI_GP1_RID),
+        .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+        .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+        .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+        .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+        .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+        .MAXIGP1WID(M_AXI_GP1_WID),
+        .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+        .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+        .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+        .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+        .MIO(buffered_MIO),
+        .PSCLK(buffered_PS_CLK),
+        .PSPORB(buffered_PS_PORB),
+        .PSSRSTB(buffered_PS_SRSTB),
+        .SAXIACPACLK(S_AXI_ACP_ACLK),
+        .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+        .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+        .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+        .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+        .SAXIACPARID(S_AXI_ACP_ARID),
+        .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+        .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+        .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+        .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+        .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+        .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+        .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+        .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+        .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+        .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+        .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+        .SAXIACPAWID(S_AXI_ACP_AWID),
+        .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+        .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+        .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+        .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+        .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+        .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+        .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+        .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+        .SAXIACPBID(S_AXI_ACP_BID),
+        .SAXIACPBREADY(S_AXI_ACP_BREADY),
+        .SAXIACPBRESP(S_AXI_ACP_BRESP),
+        .SAXIACPBVALID(S_AXI_ACP_BVALID),
+        .SAXIACPRDATA(S_AXI_ACP_RDATA),
+        .SAXIACPRID(S_AXI_ACP_RID),
+        .SAXIACPRLAST(S_AXI_ACP_RLAST),
+        .SAXIACPRREADY(S_AXI_ACP_RREADY),
+        .SAXIACPRRESP(S_AXI_ACP_RRESP),
+        .SAXIACPRVALID(S_AXI_ACP_RVALID),
+        .SAXIACPWDATA(S_AXI_ACP_WDATA),
+        .SAXIACPWID(S_AXI_ACP_WID),
+        .SAXIACPWLAST(S_AXI_ACP_WLAST),
+        .SAXIACPWREADY(S_AXI_ACP_WREADY),
+        .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+        .SAXIACPWVALID(S_AXI_ACP_WVALID),
+        .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+        .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+        .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+        .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+        .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+        .SAXIGP0ARID(S_AXI_GP0_ARID),
+        .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+        .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+        .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+        .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+        .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+        .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+        .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+        .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+        .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+        .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+        .SAXIGP0AWID(S_AXI_GP0_AWID),
+        .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+        .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+        .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+        .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+        .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+        .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+        .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+        .SAXIGP0BID(S_AXI_GP0_BID),
+        .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+        .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+        .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+        .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+        .SAXIGP0RID(S_AXI_GP0_RID),
+        .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+        .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+        .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+        .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+        .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+        .SAXIGP0WID(S_AXI_GP0_WID),
+        .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+        .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+        .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+        .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+        .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+        .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+        .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+        .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+        .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+        .SAXIGP1ARID(S_AXI_GP1_ARID),
+        .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+        .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+        .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+        .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+        .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+        .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+        .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+        .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+        .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+        .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+        .SAXIGP1AWID(S_AXI_GP1_AWID),
+        .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+        .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+        .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+        .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+        .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+        .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+        .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+        .SAXIGP1BID(S_AXI_GP1_BID),
+        .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+        .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+        .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+        .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+        .SAXIGP1RID(S_AXI_GP1_RID),
+        .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+        .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+        .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+        .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+        .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+        .SAXIGP1WID(S_AXI_GP1_WID),
+        .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+        .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+        .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+        .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+        .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+        .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+        .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+        .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+        .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+        .SAXIHP0ARID(S_AXI_HP0_ARID),
+        .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+        .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+        .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+        .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+        .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+        .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+        .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+        .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+        .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+        .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+        .SAXIHP0AWID(S_AXI_HP0_AWID),
+        .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+        .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+        .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+        .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+        .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+        .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+        .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+        .SAXIHP0BID(S_AXI_HP0_BID),
+        .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+        .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+        .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+        .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+        .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+        .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+        .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+        .SAXIHP0RID(S_AXI_HP0_RID),
+        .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+        .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+        .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+        .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+        .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+        .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+        .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+        .SAXIHP0WID(S_AXI_HP0_WID),
+        .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+        .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+        .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+        .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+        .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+        .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+        .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+        .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+        .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+        .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+        .SAXIHP1ARID(S_AXI_HP1_ARID),
+        .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+        .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+        .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+        .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+        .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+        .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+        .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+        .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+        .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+        .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+        .SAXIHP1AWID(S_AXI_HP1_AWID),
+        .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+        .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+        .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+        .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+        .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+        .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+        .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+        .SAXIHP1BID(S_AXI_HP1_BID),
+        .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+        .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+        .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+        .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+        .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+        .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+        .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+        .SAXIHP1RID(S_AXI_HP1_RID),
+        .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+        .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+        .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+        .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+        .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+        .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+        .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+        .SAXIHP1WID(S_AXI_HP1_WID),
+        .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+        .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+        .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+        .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+        .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+        .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+        .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+        .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+        .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+        .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+        .SAXIHP2ARID(S_AXI_HP2_ARID),
+        .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+        .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+        .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+        .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+        .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+        .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+        .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+        .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+        .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+        .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+        .SAXIHP2AWID(S_AXI_HP2_AWID),
+        .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+        .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+        .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+        .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+        .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+        .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+        .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+        .SAXIHP2BID(S_AXI_HP2_BID),
+        .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+        .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+        .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+        .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+        .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+        .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+        .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+        .SAXIHP2RID(S_AXI_HP2_RID),
+        .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+        .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+        .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+        .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+        .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+        .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+        .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+        .SAXIHP2WID(S_AXI_HP2_WID),
+        .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+        .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+        .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+        .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+        .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+        .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+        .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+        .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+        .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+        .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+        .SAXIHP3ARID(S_AXI_HP3_ARID),
+        .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+        .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+        .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+        .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+        .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+        .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+        .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+        .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+        .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+        .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+        .SAXIHP3AWID(S_AXI_HP3_AWID),
+        .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+        .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+        .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+        .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+        .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+        .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+        .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+        .SAXIHP3BID(S_AXI_HP3_BID),
+        .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+        .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+        .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+        .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+        .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+        .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+        .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+        .SAXIHP3RID(S_AXI_HP3_RID),
+        .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+        .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+        .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+        .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+        .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+        .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+        .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+        .SAXIHP3WID(S_AXI_HP3_WID),
+        .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+        .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+        .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+        .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+        .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_CLK_BIBUF
+       (.IO(buffered_PS_CLK),
+        .PAD(PS_CLK));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_PORB_BIBUF
+       (.IO(buffered_PS_PORB),
+        .PAD(PS_PORB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_SRSTB_BIBUF
+       (.IO(buffered_PS_SRSTB),
+        .PAD(PS_SRSTB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO0_CMD_T_INST_0
+       (.I0(SDIO0_CMD_T_n),
+        .O(SDIO0_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[0]_INST_0 
+       (.I0(SDIO0_DATA_T_n[0]),
+        .O(SDIO0_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[1]_INST_0 
+       (.I0(SDIO0_DATA_T_n[1]),
+        .O(SDIO0_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[2]_INST_0 
+       (.I0(SDIO0_DATA_T_n[2]),
+        .O(SDIO0_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[3]_INST_0 
+       (.I0(SDIO0_DATA_T_n[3]),
+        .O(SDIO0_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO1_CMD_T_INST_0
+       (.I0(SDIO1_CMD_T_n),
+        .O(SDIO1_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[0]_INST_0 
+       (.I0(SDIO1_DATA_T_n[0]),
+        .O(SDIO1_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[1]_INST_0 
+       (.I0(SDIO1_DATA_T_n[1]),
+        .O(SDIO1_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[2]_INST_0 
+       (.I0(SDIO1_DATA_T_n[2]),
+        .O(SDIO1_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[3]_INST_0 
+       (.I0(SDIO1_DATA_T_n[3]),
+        .O(SDIO1_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MISO_T_INST_0
+       (.I0(SPI0_MISO_T_n),
+        .O(SPI0_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MOSI_T_INST_0
+       (.I0(SPI0_MOSI_T_n),
+        .O(SPI0_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SCLK_T_INST_0
+       (.I0(SPI0_SCLK_T_n),
+        .O(SPI0_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SS_T_INST_0
+       (.I0(SPI0_SS_T_n),
+        .O(SPI0_SS_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MISO_T_INST_0
+       (.I0(SPI1_MISO_T_n),
+        .O(SPI1_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MOSI_T_INST_0
+       (.I0(SPI1_MOSI_T_n),
+        .O(SPI1_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SCLK_T_INST_0
+       (.I0(SPI1_SCLK_T_n),
+        .O(SPI1_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SS_T_INST_0
+       (.I0(SPI1_SS_T_n),
+        .O(SPI1_SS_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BUFG \\buffer_fclk_clk_0.FCLK_CLK_0_BUFG 
+       (.I(FCLK_CLK_unbuffered),
+        .O(FCLK_CLK0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[0].MIO_BIBUF 
+       (.IO(buffered_MIO[0]),
+        .PAD(MIO[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[10].MIO_BIBUF 
+       (.IO(buffered_MIO[10]),
+        .PAD(MIO[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[11].MIO_BIBUF 
+       (.IO(buffered_MIO[11]),
+        .PAD(MIO[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[12].MIO_BIBUF 
+       (.IO(buffered_MIO[12]),
+        .PAD(MIO[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[13].MIO_BIBUF 
+       (.IO(buffered_MIO[13]),
+        .PAD(MIO[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[14].MIO_BIBUF 
+       (.IO(buffered_MIO[14]),
+        .PAD(MIO[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[15].MIO_BIBUF 
+       (.IO(buffered_MIO[15]),
+        .PAD(MIO[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[16].MIO_BIBUF 
+       (.IO(buffered_MIO[16]),
+        .PAD(MIO[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[17].MIO_BIBUF 
+       (.IO(buffered_MIO[17]),
+        .PAD(MIO[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[18].MIO_BIBUF 
+       (.IO(buffered_MIO[18]),
+        .PAD(MIO[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[19].MIO_BIBUF 
+       (.IO(buffered_MIO[19]),
+        .PAD(MIO[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[1].MIO_BIBUF 
+       (.IO(buffered_MIO[1]),
+        .PAD(MIO[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[20].MIO_BIBUF 
+       (.IO(buffered_MIO[20]),
+        .PAD(MIO[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[21].MIO_BIBUF 
+       (.IO(buffered_MIO[21]),
+        .PAD(MIO[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[22].MIO_BIBUF 
+       (.IO(buffered_MIO[22]),
+        .PAD(MIO[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[23].MIO_BIBUF 
+       (.IO(buffered_MIO[23]),
+        .PAD(MIO[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[24].MIO_BIBUF 
+       (.IO(buffered_MIO[24]),
+        .PAD(MIO[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[25].MIO_BIBUF 
+       (.IO(buffered_MIO[25]),
+        .PAD(MIO[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[26].MIO_BIBUF 
+       (.IO(buffered_MIO[26]),
+        .PAD(MIO[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[27].MIO_BIBUF 
+       (.IO(buffered_MIO[27]),
+        .PAD(MIO[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[28].MIO_BIBUF 
+       (.IO(buffered_MIO[28]),
+        .PAD(MIO[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[29].MIO_BIBUF 
+       (.IO(buffered_MIO[29]),
+        .PAD(MIO[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[2].MIO_BIBUF 
+       (.IO(buffered_MIO[2]),
+        .PAD(MIO[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[30].MIO_BIBUF 
+       (.IO(buffered_MIO[30]),
+        .PAD(MIO[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[31].MIO_BIBUF 
+       (.IO(buffered_MIO[31]),
+        .PAD(MIO[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[32].MIO_BIBUF 
+       (.IO(buffered_MIO[32]),
+        .PAD(MIO[32]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[33].MIO_BIBUF 
+       (.IO(buffered_MIO[33]),
+        .PAD(MIO[33]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[34].MIO_BIBUF 
+       (.IO(buffered_MIO[34]),
+        .PAD(MIO[34]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[35].MIO_BIBUF 
+       (.IO(buffered_MIO[35]),
+        .PAD(MIO[35]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[36].MIO_BIBUF 
+       (.IO(buffered_MIO[36]),
+        .PAD(MIO[36]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[37].MIO_BIBUF 
+       (.IO(buffered_MIO[37]),
+        .PAD(MIO[37]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[38].MIO_BIBUF 
+       (.IO(buffered_MIO[38]),
+        .PAD(MIO[38]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[39].MIO_BIBUF 
+       (.IO(buffered_MIO[39]),
+        .PAD(MIO[39]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[3].MIO_BIBUF 
+       (.IO(buffered_MIO[3]),
+        .PAD(MIO[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[40].MIO_BIBUF 
+       (.IO(buffered_MIO[40]),
+        .PAD(MIO[40]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[41].MIO_BIBUF 
+       (.IO(buffered_MIO[41]),
+        .PAD(MIO[41]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[42].MIO_BIBUF 
+       (.IO(buffered_MIO[42]),
+        .PAD(MIO[42]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[43].MIO_BIBUF 
+       (.IO(buffered_MIO[43]),
+        .PAD(MIO[43]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[44].MIO_BIBUF 
+       (.IO(buffered_MIO[44]),
+        .PAD(MIO[44]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[45].MIO_BIBUF 
+       (.IO(buffered_MIO[45]),
+        .PAD(MIO[45]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[46].MIO_BIBUF 
+       (.IO(buffered_MIO[46]),
+        .PAD(MIO[46]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[47].MIO_BIBUF 
+       (.IO(buffered_MIO[47]),
+        .PAD(MIO[47]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[48].MIO_BIBUF 
+       (.IO(buffered_MIO[48]),
+        .PAD(MIO[48]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[49].MIO_BIBUF 
+       (.IO(buffered_MIO[49]),
+        .PAD(MIO[49]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[4].MIO_BIBUF 
+       (.IO(buffered_MIO[4]),
+        .PAD(MIO[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[50].MIO_BIBUF 
+       (.IO(buffered_MIO[50]),
+        .PAD(MIO[50]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[51].MIO_BIBUF 
+       (.IO(buffered_MIO[51]),
+        .PAD(MIO[51]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[52].MIO_BIBUF 
+       (.IO(buffered_MIO[52]),
+        .PAD(MIO[52]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[53].MIO_BIBUF 
+       (.IO(buffered_MIO[53]),
+        .PAD(MIO[53]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[5].MIO_BIBUF 
+       (.IO(buffered_MIO[5]),
+        .PAD(MIO[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[6].MIO_BIBUF 
+       (.IO(buffered_MIO[6]),
+        .PAD(MIO[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[7].MIO_BIBUF 
+       (.IO(buffered_MIO[7]),
+        .PAD(MIO[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[8].MIO_BIBUF 
+       (.IO(buffered_MIO[8]),
+        .PAD(MIO[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[9].MIO_BIBUF 
+       (.IO(buffered_MIO[9]),
+        .PAD(MIO[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[0].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[0]),
+        .PAD(DDR_BankAddr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[1].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[1]),
+        .PAD(DDR_BankAddr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[2].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[2]),
+        .PAD(DDR_BankAddr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[0].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[0]),
+        .PAD(DDR_Addr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[10].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[10]),
+        .PAD(DDR_Addr[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[11].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[11]),
+        .PAD(DDR_Addr[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[12].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[12]),
+        .PAD(DDR_Addr[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[13].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[13]),
+        .PAD(DDR_Addr[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[14].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[14]),
+        .PAD(DDR_Addr[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[1].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[1]),
+        .PAD(DDR_Addr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[2].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[2]),
+        .PAD(DDR_Addr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[3].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[3]),
+        .PAD(DDR_Addr[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[4].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[4]),
+        .PAD(DDR_Addr[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[5].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[5]),
+        .PAD(DDR_Addr[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[6].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[6]),
+        .PAD(DDR_Addr[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[7].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[7]),
+        .PAD(DDR_Addr[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[8].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[8]),
+        .PAD(DDR_Addr[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[9].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[9]),
+        .PAD(DDR_Addr[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[0].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[0]),
+        .PAD(DDR_DM[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[1].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[1]),
+        .PAD(DDR_DM[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[2].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[2]),
+        .PAD(DDR_DM[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[3].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[3]),
+        .PAD(DDR_DM[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[0].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[0]),
+        .PAD(DDR_DQ[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[10].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[10]),
+        .PAD(DDR_DQ[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[11].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[11]),
+        .PAD(DDR_DQ[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[12].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[12]),
+        .PAD(DDR_DQ[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[13].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[13]),
+        .PAD(DDR_DQ[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[14].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[14]),
+        .PAD(DDR_DQ[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[15].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[15]),
+        .PAD(DDR_DQ[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[16].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[16]),
+        .PAD(DDR_DQ[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[17].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[17]),
+        .PAD(DDR_DQ[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[18].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[18]),
+        .PAD(DDR_DQ[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[19].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[19]),
+        .PAD(DDR_DQ[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[1].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[1]),
+        .PAD(DDR_DQ[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[20].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[20]),
+        .PAD(DDR_DQ[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[21].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[21]),
+        .PAD(DDR_DQ[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[22].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[22]),
+        .PAD(DDR_DQ[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[23].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[23]),
+        .PAD(DDR_DQ[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[24].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[24]),
+        .PAD(DDR_DQ[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[25].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[25]),
+        .PAD(DDR_DQ[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[26].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[26]),
+        .PAD(DDR_DQ[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[27].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[27]),
+        .PAD(DDR_DQ[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[28].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[28]),
+        .PAD(DDR_DQ[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[29].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[29]),
+        .PAD(DDR_DQ[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[2].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[2]),
+        .PAD(DDR_DQ[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[30].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[30]),
+        .PAD(DDR_DQ[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[31].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[31]),
+        .PAD(DDR_DQ[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[3].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[3]),
+        .PAD(DDR_DQ[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[4].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[4]),
+        .PAD(DDR_DQ[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[5].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[5]),
+        .PAD(DDR_DQ[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[6].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[6]),
+        .PAD(DDR_DQ[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[7].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[7]),
+        .PAD(DDR_DQ[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[8].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[8]),
+        .PAD(DDR_DQ[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[9].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[9]),
+        .PAD(DDR_DQ[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[0].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[0]),
+        .PAD(DDR_DQS_n[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[1].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[1]),
+        .PAD(DDR_DQS_n[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[2].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[2]),
+        .PAD(DDR_DQS_n[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[3].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[3]),
+        .PAD(DDR_DQS_n[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[0].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[0]),
+        .PAD(DDR_DQS[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[1].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[1]),
+        .PAD(DDR_DQS[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[2].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[2]),
+        .PAD(DDR_DQS[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[3].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[3]),
+        .PAD(DDR_DQS[3]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_0
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[0] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_1
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_10
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_11
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_12
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_13
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_14
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_15
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_16
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_17
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_18
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_19
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_2
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_20
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_21
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_22
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_23
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_3
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[7] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_4
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[6] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_5
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[5] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_6
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[4] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_7
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[3] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_8
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[2] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_9
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:35:10 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_1_0_stub.v
+// Design      : design_1_axi_gpio_1_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_gpio,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:49:15 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    SDIO0_WP,
+    UART0_TX,
+    UART0_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    IRQ_F2P,
+    FCLK_CLK0,
+    FCLK_RESET0_N,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_I"" *) input I2C0_SDA_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_O"" *) output I2C0_SDA_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_T"" *) output I2C0_SDA_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_I"" *) input I2C0_SCL_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_O"" *) output I2C0_SCL_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_T"" *) output I2C0_SCL_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *) input SDIO0_WP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 TxD"" *) output UART0_TX;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 RxD"" *) input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *) output [1:0]USB0_PORT_INDCTL;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *) output USB0_VBUS_PWRSELECT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *) input USB0_VBUS_PWRFAULT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *) output M_AXI_GP0_ARVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *) output M_AXI_GP0_AWVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *) output M_AXI_GP0_BREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *) output M_AXI_GP0_RREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *) output M_AXI_GP0_WLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *) output M_AXI_GP0_WVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *) output [11:0]M_AXI_GP0_ARID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *) output [11:0]M_AXI_GP0_AWID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *) output [11:0]M_AXI_GP0_WID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *) output [1:0]M_AXI_GP0_ARBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *) output [1:0]M_AXI_GP0_ARLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *) output [2:0]M_AXI_GP0_ARSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *) output [1:0]M_AXI_GP0_AWBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *) output [1:0]M_AXI_GP0_AWLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *) output [2:0]M_AXI_GP0_AWSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *) output [2:0]M_AXI_GP0_ARPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *) output [2:0]M_AXI_GP0_AWPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *) output [31:0]M_AXI_GP0_ARADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *) output [31:0]M_AXI_GP0_AWADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *) output [31:0]M_AXI_GP0_WDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *) output [3:0]M_AXI_GP0_ARCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *) output [3:0]M_AXI_GP0_ARLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *) output [3:0]M_AXI_GP0_ARQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *) output [3:0]M_AXI_GP0_AWCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *) output [3:0]M_AXI_GP0_AWLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *) output [3:0]M_AXI_GP0_AWQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *) output [3:0]M_AXI_GP0_WSTRB;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *) input M_AXI_GP0_ACLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *) input M_AXI_GP0_ARREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *) input M_AXI_GP0_AWREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *) input M_AXI_GP0_BVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *) input M_AXI_GP0_RLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *) input M_AXI_GP0_RVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *) input M_AXI_GP0_WREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *) input [11:0]M_AXI_GP0_BID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *) input [11:0]M_AXI_GP0_RID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *) input [1:0]M_AXI_GP0_BRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *) input [1:0]M_AXI_GP0_RRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *) input [31:0]M_AXI_GP0_RDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT"" *) input [0:0]IRQ_F2P;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *) output FCLK_CLK0;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *) output FCLK_RESET0_N;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *) inout [53:0]MIO;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *) inout DDR_CAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *) inout DDR_CKE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *) inout DDR_Clk_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *) inout DDR_Clk;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *) inout DDR_CS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *) inout DDR_DRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *) inout DDR_ODT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *) inout DDR_RAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *) inout DDR_WEB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *) inout [2:0]DDR_BankAddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *) inout [14:0]DDR_Addr;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *) inout DDR_VRN;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *) inout DDR_VRP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *) inout [3:0]DDR_DM;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *) inout [31:0]DDR_DQ;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *) inout [3:0]DDR_DQS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *) inout [3:0]DDR_DQS;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *) inout PS_SRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *) inout PS_CLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *) inout PS_PORB;
+
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire FCLK_CLK0;
+  wire FCLK_RESET0_N;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire [0:0]IRQ_F2P;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [2:0]M_AXI_GP0_ARSIZE;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [2:0]M_AXI_GP0_AWSIZE;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_WP;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+  wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+  wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+  wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+  wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+  wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO0_LED_UNCONNECTED;
+  wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO1_LED_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+  wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+  wire NLW_inst_TRACE_CTL_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+  wire NLW_inst_UART0_DTRN_UNCONNECTED;
+  wire NLW_inst_UART0_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_DTRN_UNCONNECTED;
+  wire NLW_inst_UART1_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_TX_UNCONNECTED;
+  wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+  wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+  wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+  wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+  wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+PULLUP pullup_MIO_0
+       (.O(MIO[0]));
+PULLUP pullup_MIO_9
+       (.O(MIO[9]));
+PULLUP pullup_MIO_10
+       (.O(MIO[10]));
+PULLUP pullup_MIO_11
+       (.O(MIO[11]));
+PULLUP pullup_MIO_12
+       (.O(MIO[12]));
+PULLUP pullup_MIO_13
+       (.O(MIO[13]));
+PULLUP pullup_MIO_14
+       (.O(MIO[14]));
+PULLUP pullup_MIO_15
+       (.O(MIO[15]));
+PULLUP pullup_MIO_46
+       (.O(MIO[46]));
+
+  (* C_DM_WIDTH = ""4"" *) 
+  (* C_DQS_WIDTH = ""4"" *) 
+  (* C_DQ_WIDTH = ""32"" *) 
+  (* C_EMIO_GPIO_WIDTH = ""64"" *) 
+  (* C_EN_EMIO_ENET0 = ""0"" *) 
+  (* C_EN_EMIO_ENET1 = ""0"" *) 
+  (* C_EN_EMIO_PJTAG = ""0"" *) 
+  (* C_EN_EMIO_TRACE = ""0"" *) 
+  (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+  (* C_FCLK_CLK1_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK2_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+  (* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+  (* C_INCLUDE_TRACE_BUFFER = ""0"" *) 
+  (* C_IRQ_F2P_MODE = ""DIRECT"" *) 
+  (* C_MIO_PRIMITIVE = ""54"" *) 
+  (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_NUM_F2P_INTR_INPUTS = ""1"" *) 
+  (* C_PACKAGE_NAME = ""clg400"" *) 
+  (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+  (* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+  (* C_S_AXI_GP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP3_ID_WIDTH = ""6"" *) 
+  (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) 
+  (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+  (* C_TRACE_INTERNAL_WIDTH = ""2"" *) 
+  (* C_TRACE_PIPELINE_WIDTH = ""8"" *) 
+  (* C_USE_AXI_NONSECURE = ""0"" *) 
+  (* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) 
+  (* C_USE_M_AXI_GP0 = ""1"" *) 
+  (* C_USE_M_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_ACP = ""0"" *) 
+  (* C_USE_S_AXI_GP0 = ""0"" *) 
+  (* C_USE_S_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP0 = ""0"" *) 
+  (* C_USE_S_AXI_HP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP2 = ""0"" *) 
+  (* C_USE_S_AXI_HP3 = ""0"" *) 
+  (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) 
+  (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+  (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
+       (.CAN0_PHY_RX(1\'b0),
+        .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+        .CAN1_PHY_RX(1\'b0),
+        .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+        .Core0_nFIQ(1\'b0),
+        .Core0_nIRQ(1\'b0),
+        .Core1_nFIQ(1\'b0),
+        .Core1_nIRQ(1\'b0),
+        .DDR_ARB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .DDR_Addr(DDR_Addr),
+        .DDR_BankAddr(DDR_BankAddr),
+        .DDR_CAS_n(DDR_CAS_n),
+        .DDR_CKE(DDR_CKE),
+        .DDR_CS_n(DDR_CS_n),
+        .DDR_Clk(DDR_Clk),
+        .DDR_Clk_n(DDR_Clk_n),
+        .DDR_DM(DDR_DM),
+        .DDR_DQ(DDR_DQ),
+        .DDR_DQS(DDR_DQS),
+        .DDR_DQS_n(DDR_DQS_n),
+        .DDR_DRSTB(DDR_DRSTB),
+        .DDR_ODT(DDR_ODT),
+        .DDR_RAS_n(DDR_RAS_n),
+        .DDR_VRN(DDR_VRN),
+        .DDR_VRP(DDR_VRP),
+        .DDR_WEB(DDR_WEB),
+        .DMA0_ACLK(1\'b0),
+        .DMA0_DAREADY(1\'b0),
+        .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+        .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+        .DMA0_DRLAST(1\'b0),
+        .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+        .DMA0_DRTYPE({1\'b0,1\'b0}),
+        .DMA0_DRVALID(1\'b0),
+        .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+        .DMA1_ACLK(1\'b0),
+        .DMA1_DAREADY(1\'b0),
+        .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+        .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+        .DMA1_DRLAST(1\'b0),
+        .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+        .DMA1_DRTYPE({1\'b0,1\'b0}),
+        .DMA1_DRVALID(1\'b0),
+        .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+        .DMA2_ACLK(1\'b0),
+        .DMA2_DAREADY(1\'b0),
+        .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+        .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+        .DMA2_DRLAST(1\'b0),
+        .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+        .DMA2_DRTYPE({1\'b0,1\'b0}),
+        .DMA2_DRVALID(1\'b0),
+        .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+        .DMA3_ACLK(1\'b0),
+        .DMA3_DAREADY(1\'b0),
+        .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+        .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+        .DMA3_DRLAST(1\'b0),
+        .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+        .DMA3_DRTYPE({1\'b0,1\'b0}),
+        .DMA3_DRVALID(1\'b0),
+        .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+        .ENET0_EXT_INTIN(1\'b0),
+        .ENET0_GMII_COL(1\'b0),
+        .ENET0_GMII_CRS(1\'b0),
+        .ENET0_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET0_GMII_RX_CLK(1\'b0),
+        .ENET0_GMII_RX_DV(1\'b0),
+        .ENET0_GMII_RX_ER(1\'b0),
+        .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET0_GMII_TX_CLK(1\'b0),
+        .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+        .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+        .ENET0_MDIO_I(1\'b0),
+        .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+        .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+        .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+        .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+        .ENET1_EXT_INTIN(1\'b0),
+        .ENET1_GMII_COL(1\'b0),
+        .ENET1_GMII_CRS(1\'b0),
+        .ENET1_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET1_GMII_RX_CLK(1\'b0),
+        .ENET1_GMII_RX_DV(1\'b0),
+        .ENET1_GMII_RX_ER(1\'b0),
+        .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET1_GMII_TX_CLK(1\'b0),
+        .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+        .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+        .ENET1_MDIO_I(1\'b0),
+        .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+        .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+        .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+        .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+        .EVENT_EVENTI(1\'b0),
+        .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+        .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+        .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+        .FCLK_CLK0(FCLK_CLK0),
+        .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+        .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+        .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+        .FCLK_CLKTRIG0_N(1\'b0),
+        .FCLK_CLKTRIG1_N(1\'b0),
+        .FCLK_CLKTRIG2_N(1\'b0),
+        .FCLK_CLKTRIG3_N(1\'b0),
+        .FCLK_RESET0_N(FCLK_RESET0_N),
+        .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+        .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+        .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+        .FPGA_IDLE_N(1\'b0),
+        .FTMD_TRACEIN_ATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_CLK(1\'b0),
+        .FTMD_TRACEIN_DATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_VALID(1\'b0),
+        .FTMT_F2P_DEBUG({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+        .FTMT_F2P_TRIG_0(1\'b0),
+        .FTMT_F2P_TRIG_1(1\'b0),
+        .FTMT_F2P_TRIG_2(1\'b0),
+        .FTMT_F2P_TRIG_3(1\'b0),
+        .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+        .FTMT_P2F_TRIGACK_0(1\'b0),
+        .FTMT_P2F_TRIGACK_1(1\'b0),
+        .FTMT_P2F_TRIGACK_2(1\'b0),
+        .FTMT_P2F_TRIGACK_3(1\'b0),
+        .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+        .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+        .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+        .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+        .GPIO_I({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
+        .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
+        .I2C0_SCL_I(I2C0_SCL_I),
+        .I2C0_SCL_O(I2C0_SCL_O),
+        .I2C0_SCL_T(I2C0_SCL_T),
+        .I2C0_SDA_I(I2C0_SDA_I),
+        .I2C0_SDA_O(I2C0_SDA_O),
+        .I2C0_SDA_T(I2C0_SDA_T),
+        .I2C1_SCL_I(1\'b0),
+        .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+        .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+        .I2C1_SDA_I(1\'b0),
+        .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+        .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+        .IRQ_F2P(IRQ_F2P),
+        .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+        .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+        .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+        .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+        .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+        .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+        .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+        .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+        .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+        .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+        .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+        .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+        .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+        .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+        .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+        .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+        .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+        .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+        .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+        .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+        .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+        .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+        .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+        .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+        .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+        .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+        .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+        .MIO(MIO),
+        .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+        .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+        .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+        .M_AXI_GP1_ACLK(1\'b0),
+        .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+        .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARREADY(1\'b0),
+        .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+        .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWREADY(1\'b0),
+        .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+        .M_AXI_GP1_BID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+        .M_AXI_GP1_BRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_BVALID(1\'b0),
+        .M_AXI_GP1_RDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RLAST(1\'b0),
+        .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+        .M_AXI_GP1_RRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_RVALID(1\'b0),
+        .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+        .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+        .M_AXI_GP1_WREADY(1\'b0),
+        .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+        .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+        .PJTAG_TCK(1\'b0),
+        .PJTAG_TDI(1\'b0),
+        .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+        .PJTAG_TMS(1\'b0),
+        .PS_CLK(PS_CLK),
+        .PS_PORB(PS_PORB),
+        .PS_SRSTB(PS_SRSTB),
+        .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+        .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO0_CDN(1\'b0),
+        .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+        .SDIO0_CLK_FB(1\'b0),
+        .SDIO0_CMD_I(1\'b0),
+        .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+        .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+        .SDIO0_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+        .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+        .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+        .SDIO0_WP(SDIO0_WP),
+        .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+        .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO1_CDN(1\'b0),
+        .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+        .SDIO1_CLK_FB(1\'b0),
+        .SDIO1_CMD_I(1\'b0),
+        .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+        .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+        .SDIO1_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+        .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+        .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+        .SDIO1_WP(1\'b0),
+        .SPI0_MISO_I(1\'b0),
+        .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+        .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+        .SPI0_MOSI_I(1\'b0),
+        .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+        .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+        .SPI0_SCLK_I(1\'b0),
+        .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+        .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+        .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+        .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+        .SPI0_SS_I(1\'b0),
+        .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+        .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+        .SPI1_MISO_I(1\'b0),
+        .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+        .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+        .SPI1_MOSI_I(1\'b0),
+        .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+        .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+        .SPI1_SCLK_I(1\'b0),
+        .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+        .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+        .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+        .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+        .SPI1_SS_I(1\'b0),
+        .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+        .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+        .SRAM_INTIN(1\'b0),
+        .S_AXI_ACP_ACLK(1\'b0),
+        .S_AXI_ACP_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+        .S_AXI_ACP_ARID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+        .S_AXI_ACP_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARVALID(1\'b0),
+        .S_AXI_ACP_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+        .S_AXI_ACP_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWVALID(1\'b0),
+        .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_BREADY(1\'b0),
+        .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+        .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+        .S_AXI_ACP_RREADY(1\'b0),
+        .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+        .S_AXI_ACP_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WLAST(1\'b0),
+        .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+        .S_AXI_ACP_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WVALID(1\'b0),
+        .S_AXI_GP0_ACLK(1\'b0),
+        .S_AXI_GP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+        .S_AXI_GP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+        .S_AXI_GP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARVALID(1\'b0),
+        .S_AXI_GP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+        .S_AXI_GP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWVALID(1\'b0),
+        .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_BREADY(1\'b0),
+        .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+        .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+        .S_AXI_GP0_RREADY(1\'b0),
+        .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+        .S_AXI_GP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WLAST(1\'b0),
+        .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+        .S_AXI_GP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WVALID(1\'b0),
+        .S_AXI_GP1_ACLK(1\'b0),
+        .S_AXI_GP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+        .S_AXI_GP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+        .S_AXI_GP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARVALID(1\'b0),
+        .S_AXI_GP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+        .S_AXI_GP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWVALID(1\'b0),
+        .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_BREADY(1\'b0),
+        .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+        .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+        .S_AXI_GP1_RREADY(1\'b0),
+        .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+        .S_AXI_GP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WLAST(1\'b0),
+        .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+        .S_AXI_GP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WVALID(1\'b0),
+        .S_AXI_HP0_ACLK(1\'b0),
+        .S_AXI_HP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+        .S_AXI_HP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+        .S_AXI_HP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARVALID(1\'b0),
+        .S_AXI_HP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+        .S_AXI_HP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWVALID(1\'b0),
+        .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_BREADY(1\'b0),
+        .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+        .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP0_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+        .S_AXI_HP0_RREADY(1\'b0),
+        .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+        .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WLAST(1\'b0),
+        .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+        .S_AXI_HP0_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WVALID(1\'b0),
+        .S_AXI_HP1_ACLK(1\'b0),
+        .S_AXI_HP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+        .S_AXI_HP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+        .S_AXI_HP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARVALID(1\'b0),
+        .S_AXI_HP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+        .S_AXI_HP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWVALID(1\'b0),
+        .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_BREADY(1\'b0),
+        .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+        .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP1_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+        .S_AXI_HP1_RREADY(1\'b0),
+        .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+        .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WLAST(1\'b0),
+        .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+        .S_AXI_HP1_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WVALID(1\'b0),
+        .S_AXI_HP2_ACLK(1\'b0),
+        .S_AXI_HP2_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+        .S_AXI_HP2_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+        .S_AXI_HP2_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARVALID(1\'b0),
+        .S_AXI_HP2_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+        .S_AXI_HP2_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWVALID(1\'b0),
+        .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_BREADY(1\'b0),
+        .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+        .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP2_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+        .S_AXI_HP2_RREADY(1\'b0),
+        .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+        .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WLAST(1\'b0),
+        .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+        .S_AXI_HP2_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WVALID(1\'b0),
+        .S_AXI_HP3_ACLK(1\'b0),
+        .S_AXI_HP3_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+        .S_AXI_HP3_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+        .S_AXI_HP3_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARVALID(1\'b0),
+        .S_AXI_HP3_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+        .S_AXI_HP3_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWVALID(1\'b0),
+        .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_BREADY(1\'b0),
+        .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+        .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP3_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+        .S_AXI_HP3_RREADY(1\'b0),
+        .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+        .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_'b'WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WLAST(1\'b0),
+        .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
+        .S_AXI_HP3_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WVALID(1\'b0),
+        .TRACE_CLK(1\'b0),
+        .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+        .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
+        .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+        .TTC0_CLK0_IN(1\'b0),
+        .TTC0_CLK1_IN(1\'b0),
+        .TTC0_CLK2_IN(1\'b0),
+        .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+        .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+        .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+        .TTC1_CLK0_IN(1\'b0),
+        .TTC1_CLK1_IN(1\'b0),
+        .TTC1_CLK2_IN(1\'b0),
+        .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+        .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+        .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+        .UART0_CTSN(1\'b0),
+        .UART0_DCDN(1\'b0),
+        .UART0_DSRN(1\'b0),
+        .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
+        .UART0_RIN(1\'b0),
+        .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
+        .UART0_RX(UART0_RX),
+        .UART0_TX(UART0_TX),
+        .UART1_CTSN(1\'b0),
+        .UART1_DCDN(1\'b0),
+        .UART1_DSRN(1\'b0),
+        .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+        .UART1_RIN(1\'b0),
+        .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+        .UART1_RX(1\'b1),
+        .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+        .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+        .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+        .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+        .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+        .USB1_VBUS_PWRFAULT(1\'b0),
+        .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+        .WDT_CLK_IN(1\'b0),
+        .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = ""4"" *) (* C_DQS_WIDTH = ""4"" *) (* C_DQ_WIDTH = ""32"" *) 
+(* C_EMIO_GPIO_WIDTH = ""64"" *) (* C_EN_EMIO_ENET0 = ""0"" *) (* C_EN_EMIO_ENET1 = ""0"" *) 
+(* C_EN_EMIO_PJTAG = ""0"" *) (* C_EN_EMIO_TRACE = ""0"" *) (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+(* C_FCLK_CLK1_BUF = ""FALSE"" *) (* C_FCLK_CLK2_BUF = ""FALSE"" *) (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+(* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+(* C_INCLUDE_TRACE_BUFFER = ""0"" *) (* C_IRQ_F2P_MODE = ""DIRECT"" *) (* C_MIO_PRIMITIVE = ""54"" *) 
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+(* C_NUM_F2P_INTR_INPUTS = ""1"" *) (* C_PACKAGE_NAME = ""clg400"" *) (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+(* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+(* C_S_AXI_GP0_ID_WIDTH = ""6"" *) (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP0_ID_WIDTH = ""6"" *) (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+(* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP3_ID_WIDTH = ""6"" *) (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+(* C_TRACE_INTERNAL_WIDTH = ""2"" *) (* C_TRACE_PIPELINE_WIDTH = ""8"" *) (* C_USE_AXI_NONSECURE = ""0"" *) 
+(* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) (* C_USE_M_AXI_GP0 = ""1"" *) (* C_USE_M_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_ACP = ""0"" *) (* C_USE_S_AXI_GP0 = ""0"" *) (* C_USE_S_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_HP0 = ""0"" *) (* C_USE_S_AXI_HP1 = ""0"" *) (* C_USE_S_AXI_HP2 = ""0"" *) 
+(* C_USE_S_AXI_HP3 = ""0"" *) (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+(* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
+   (CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TDI,
+    PJTAG_TDO,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    TRACE_CLK_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_PORT_INDCTL,
+    USB1_VBUS_PWRSELECT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARESETN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARESETN,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARESETN,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARESETN,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_ARESETN,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARESETN,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARESETN,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARESETN,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARESETN,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_RSTN,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_RSTN,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_RSTN,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_RSTN,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA3_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DRTYPE,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG_0,
+    FTMT_F2P_TRIGACK_0,
+    FTMT_F2P_TRIG_1,
+    FTMT_F2P_TRIGACK_1,
+    FTMT_F2P_TRIG_2,
+    FTMT_F2P_TRIGACK_2,
+    FTMT_F2P_TRIG_3,
+    FTMT_F2P_TRIGACK_3,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK_0,
+    FTMT_P2F_TRIG_0,
+    FTMT_P2F_TRIGACK_1,
+    FTMT_P2F_TRIG_1,
+    FTMT_P2F_TRIGACK_2,
+    FTMT_P2F_TRIG_2,
+    FTMT_P2F_TRIGACK_3,
+    FTMT_P2F_TRIG_3,
+    FTMT_P2F_DEBUG,
+    FPGA_IDLE_N,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    DDR_ARB,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0]ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input ENET0_EXT_INTIN;
+  input [7:0]ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0]ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input ENET1_EXT_INTIN;
+  input [7:0]ENET1_GMII_RXD;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TDI;
+  output PJTAG_TDO;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0]SDIO0_DATA_I;
+  output [3:0]SDIO0_DATA_O;
+  output [3:0]SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0]SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0]SDIO1_DATA_I;
+  output [3:0]SDIO1_DATA_O;
+  output [3:0]SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0]SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [1:0]TRACE_DATA;
+  output TRACE_CLK_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output [1:0]USB1_PORT_INDCTL;
+  output USB1_VBUS_PWRSELECT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARESETN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARESETN;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [11:0]M_AXI_GP1_ARID;
+  output [11:0]M_AXI_GP1_AWID;
+  output [11:0]M_AXI_GP1_WID;
+  output [1:0]M_AXI_GP1_ARBURST;
+  output [1:0]M_AXI_GP1_ARLOCK;
+  output [2:0]M_AXI_GP1_ARSIZE;
+  output [1:0]M_AXI_GP1_AWBURST;
+  output [1:0]M_AXI_GP1_AWLOCK;
+  output [2:0]M_AXI_GP1_AWSIZE;
+  output [2:0]M_AXI_GP1_ARPROT;
+  output [2:0]M_AXI_GP1_AWPROT;
+  output [31:0]M_AXI_GP1_ARADDR;
+  output [31:0]M_AXI_GP1_AWADDR;
+  output [31:0]M_AXI_GP1_WDATA;
+  output [3:0]M_AXI_GP1_ARCACHE;
+  output [3:0]M_AXI_GP1_ARLEN;
+  output [3:0]M_AXI_GP1_ARQOS;
+  output [3:0]M_AXI_GP1_AWCACHE;
+  output [3:0]M_AXI_GP1_AWLEN;
+  output [3:0]M_AXI_GP1_AWQOS;
+  output [3:0]M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [11:0]M_AXI_GP1_BID;
+  input [11:0]M_AXI_GP1_RID;
+  input [1:0]M_AXI_GP1_BRESP;
+  input [1:0]M_AXI_GP1_RRESP;
+  input [31:0]M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARESETN;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0]S_AXI_GP0_BRESP;
+  output [1:0]S_AXI_GP0_RRESP;
+  output [31:0]S_AXI_GP0_RDATA;
+  output [5:0]S_AXI_GP0_BID;
+  output [5:0]S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0]S_AXI_GP0_ARBURST;
+  input [1:0]S_AXI_GP0_ARLOCK;
+  input [2:0]S_AXI_GP0_ARSIZE;
+  input [1:0]S_AXI_GP0_AWBURST;
+  input [1:0]S_AXI_GP0_AWLOCK;
+  input [2:0]S_AXI_GP0_AWSIZE;
+  input [2:0]S_AXI_GP0_ARPROT;
+  input [2:0]S_AXI_GP0_AWPROT;
+  input [31:0]S_AXI_GP0_ARADDR;
+  input [31:0]S_AXI_GP0_AWADDR;
+  input [31:0]S_AXI_GP0_WDATA;
+  input [3:0]S_AXI_GP0_ARCACHE;
+  input [3:0]S_AXI_GP0_ARLEN;
+  input [3:0]S_AXI_GP0_ARQOS;
+  input [3:0]S_AXI_GP0_AWCACHE;
+  input [3:0]S_AXI_GP0_AWLEN;
+  input [3:0]S_AXI_GP0_AWQOS;
+  input [3:0]S_AXI_GP0_WSTRB;
+  input [5:0]S_AXI_GP0_ARID;
+  input [5:0]S_AXI_GP0_AWID;
+  input [5:0]S_AXI_GP0_WID;
+  output S_AXI_GP1_ARESETN;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0]S_AXI_GP1_BRESP;
+  output [1:0]S_AXI_GP1_RRESP;
+  output [31:0]S_AXI_GP1_RDATA;
+  output [5:0]S_AXI_GP1_BID;
+  output [5:0]S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0]S_AXI_GP1_ARBURST;
+  input [1:0]S_AXI_GP1_ARLOCK;
+  input [2:0]S_AXI_GP1_ARSIZE;
+  input [1:0]S_AXI_GP1_AWBURST;
+  input [1:0]S_AXI_GP1_AWLOCK;
+  input [2:0]S_AXI_GP1_AWSIZE;
+  input [2:0]S_AXI_GP1_ARPROT;
+  input [2:0]S_AXI_GP1_AWPROT;
+  input [31:0]S_AXI_GP1_ARADDR;
+  input [31:0]S_AXI_GP1_AWADDR;
+  input [31:0]S_AXI_GP1_WDATA;
+  input [3:0]S_AXI_GP1_ARCACHE;
+  input [3:0]S_AXI_GP1_ARLEN;
+  input [3:0]S_AXI_GP1_ARQOS;
+  input [3:0]S_AXI_GP1_AWCACHE;
+  input [3:0]S_AXI_GP1_AWLEN;
+  input [3:0]S_AXI_GP1_AWQOS;
+  input [3:0]S_AXI_GP1_WSTRB;
+  input [5:0]S_AXI_GP1_ARID;
+  input [5:0]S_AXI_GP1_AWID;
+  input [5:0]S_AXI_GP1_WID;
+  output S_AXI_ACP_ARESETN;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0]S_AXI_ACP_BRESP;
+  output [1:0]S_AXI_ACP_RRESP;
+  output [2:0]S_AXI_ACP_BID;
+  output [2:0]S_AXI_ACP_RID;
+  output [63:0]S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0]S_AXI_ACP_ARID;
+  input [2:0]S_AXI_ACP_ARPROT;
+  input [2:0]S_AXI_ACP_AWID;
+  input [2:0]S_AXI_ACP_AWPROT;
+  input [2:0]S_AXI_ACP_WID;
+  input [31:0]S_AXI_ACP_ARADDR;
+  input [31:0]S_AXI_ACP_AWADDR;
+  input [3:0]S_AXI_ACP_ARCACHE;
+  input [3:0]S_AXI_ACP_ARLEN;
+  input [3:0]S_AXI_ACP_ARQOS;
+  input [3:0]S_AXI_ACP_AWCACHE;
+  input [3:0]S_AXI_ACP_AWLEN;
+  input [3:0]S_AXI_ACP_AWQOS;
+  input [1:0]S_AXI_ACP_ARBURST;
+  input [1:0]S_AXI_ACP_ARLOCK;
+  input [2:0]S_AXI_ACP_ARSIZE;
+  input [1:0]S_AXI_ACP_AWBURST;
+  input [1:0]S_AXI_ACP_AWLOCK;
+  input [2:0]S_AXI_ACP_AWSIZE;
+  input [4:0]S_AXI_ACP_ARUSER;
+  input [4:0]S_AXI_ACP_AWUSER;
+  input [63:0]S_AXI_ACP_WDATA;
+  input [7:0]S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARESETN;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0]S_AXI_HP0_BRESP;
+  output [1:0]S_AXI_HP0_RRESP;
+  output [5:0]S_AXI_HP0_BID;
+  output [5:0]S_AXI_HP0_RID;
+  output [63:0]S_AXI_HP0_RDATA;
+  output [7:0]S_AXI_HP0_RCOUNT;
+  output [7:0]S_AXI_HP0_WCOUNT;
+  output [2:0]S_AXI_HP0_RACOUNT;
+  output [5:0]S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0]S_AXI_HP0_ARBURST;
+  input [1:0]S_AXI_HP0_ARLOCK;
+  input [2:0]S_AXI_HP0_ARSIZE;
+  input [1:0]S_AXI_HP0_AWBURST;
+  input [1:0]S_AXI_HP0_AWLOCK;
+  input [2:0]S_AXI_HP0_AWSIZE;
+  input [2:0]S_AXI_HP0_ARPROT;
+  input [2:0]S_AXI_HP0_AWPROT;
+  input [31:0]S_AXI_HP0_ARADDR;
+  input [31:0]S_AXI_HP0_AWADDR;
+  input [3:0]S_AXI_HP0_ARCACHE;
+  input [3:0]S_AXI_HP0_ARLEN;
+  input [3:0]S_AXI_HP0_ARQOS;
+  input [3:0]S_AXI_HP0_AWCACHE;
+  input [3:0]S_AXI_HP0_AWLEN;
+  input [3:0]S_AXI_HP0_AWQOS;
+  input [5:0]S_AXI_HP0_ARID;
+  input [5:0]S_AXI_HP0_AWID;
+  input [5:0]S_AXI_HP0_WID;
+  input [63:0]S_AXI_HP0_WDATA;
+  input [7:0]S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARESETN;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0]S_AXI_HP1_BRESP;
+  output [1:0]S_AXI_HP1_RRESP;
+  output [5:0]S_AXI_HP1_BID;
+  output [5:0]S_AXI_HP1_RID;
+  output [63:0]S_AXI_HP1_RDATA;
+  output [7:0]S_AXI_HP1_RCOUNT;
+  output [7:0]S_AXI_HP1_WCOUNT;
+  output [2:0]S_AXI_HP1_RACOUNT;
+  output [5:0]S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0]S_AXI_HP1_ARBURST;
+  input [1:0]S_AXI_HP1_ARLOCK;
+  input [2:0]S_AXI_HP1_ARSIZE;
+  input [1:0]S_AXI_HP1_AWBURST;
+  input [1:0]S_AXI_HP1_AWLOCK;
+  input [2:0]S_AXI_HP1_AWSIZE;
+  input [2:0]S_AXI_HP1_ARPROT;
+  input [2:0]S_AXI_HP1_AWPROT;
+  input [31:0]S_AXI_HP1_ARADDR;
+  input [31:0]S_AXI_HP1_AWADDR;
+  input [3:0]S_AXI_HP1_ARCACHE;
+  input [3:0]S_AXI_HP1_ARLEN;
+  input [3:0]S_AXI_HP1_ARQOS;
+  input [3:0]S_AXI_HP1_AWCACHE;
+  input [3:0]S_AXI_HP1_AWLEN;
+  input [3:0]S_AXI_HP1_AWQOS;
+  input [5:0]S_AXI_HP1_ARID;
+  input [5:0]S_AXI_HP1_AWID;
+  input [5:0]S_AXI_HP1_WID;
+  input [63:0]S_AXI_HP1_WDATA;
+  input [7:0]S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARESETN;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0]S_AXI_HP2_BRESP;
+  output [1:0]S_AXI_HP2_RRESP;
+  output [5:0]S_AXI_HP2_BID;
+  output [5:0]S_AXI_HP2_RID;
+  output [63:0]S_AXI_HP2_RDATA;
+  output [7:0]S_AXI_HP2_RCOUNT;
+  output [7:0]S_AXI_HP2_WCOUNT;
+  output [2:0]S_AXI_HP2_RACOUNT;
+  output [5:0]S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0]S_AXI_HP2_ARBURST;
+  input [1:0]S_AXI_HP2_ARLOCK;
+  input [2:0]S_AXI_HP2_ARSIZE;
+  input [1:0]S_AXI_HP2_AWBURST;
+  input [1:0]S_AXI_HP2_AWLOCK;
+  input [2:0]S_AXI_HP2_AWSIZE;
+  input [2:0]S_AXI_HP2_ARPROT;
+  input [2:0]S_AXI_HP2_AWPROT;
+  input [31:0]S_AXI_HP2_ARADDR;
+  input [31:0]S_AXI_HP2_AWADDR;
+  input [3:0]S_AXI_HP2_ARCACHE;
+  input [3:0]S_AXI_HP2_ARLEN;
+  input [3:0]S_AXI_HP2_ARQOS;
+  input [3:0]S_AXI_HP2_AWCACHE;
+  input [3:0]S_AXI_HP2_AWLEN;
+  input [3:0]S_AXI_HP2_AWQOS;
+  input [5:0]S_AXI_HP2_ARID;
+  input [5:0]S_AXI_HP2_AWID;
+  input [5:0]S_AXI_HP2_WID;
+  input [63:0]S_AXI_HP2_WDATA;
+  input [7:0]S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARESETN;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0]S_AXI_HP3_BRESP;
+  output [1:0]S_AXI_HP3_RRESP;
+  output [5:0]S_AXI_HP3_BID;
+  output [5:0]S_AXI_HP3_RID;
+  output [63:0]S_AXI_HP3_RDATA;
+  output [7:0]S_AXI_HP3_RCOUNT;
+  output [7:0]S_AXI_HP3_WCOUNT;
+  output [2:0]S_AXI_HP3_RACOUNT;
+  output [5:0]S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0]S_AXI_HP3_ARBURST;
+  input [1:0]S_AXI_HP3_ARLOCK;
+  input [2:0]S_AXI_HP3_ARSIZE;
+  input [1:0]S_AXI_HP3_AWBURST;
+  input [1:0]S_AXI_HP3_AWLOCK;
+  input [2:0]S_AXI_HP3_AWSIZE;
+  input [2:0]S_AXI_HP3_ARPROT;
+  input [2:0]S_AXI_HP3_AWPROT;
+  input [31:0]S_AXI_HP3_ARADDR;
+  input [31:0]S_AXI_HP3_AWADDR;
+  input [3:0]S_AXI_HP3_ARCACHE;
+  input [3:0]S_AXI_HP3_ARLEN;
+  input [3:0]S_AXI_HP3_ARQOS;
+  input [3:0]S_AXI_HP3_AWCACHE;
+  input [3:0]S_AXI_HP3_AWLEN;
+  input [3:0]S_AXI_HP3_AWQOS;
+  input [5:0]S_AXI_HP3_ARID;
+  input [5:0]S_AXI_HP3_AWID;
+  input [5:0]S_AXI_HP3_WID;
+  input [63:0]S_AXI_HP3_WDATA;
+  input [7:0]S_AXI_HP3_WSTRB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+  input [0:0]IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output [1:0]DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  output DMA0_RSTN;
+  output [1:0]DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  output DMA1_RSTN;
+  output [1:0]DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  output DMA2_RSTN;
+  output [1:0]DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  output DMA3_RSTN;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input DMA3_DRVALID;
+  input [1:0]DMA0_DRTYPE;
+  input [1:0]DMA1_DRTYPE;
+  input [1:0]DMA2_DRTYPE;
+  input [1:0]DMA3_DRTYPE;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input [31:0]FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0]FTMD_TRACEIN_ATID;
+  input FTMT_F2P_TRIG_0;
+  output FTMT_F2P_TRIGACK_0;
+  input FTMT_F2P_TRIG_1;
+  output FTMT_F2P_TRIGACK_1;
+  input FTMT_F2P_TRIG_2;
+  output FTMT_F2P_TRIGACK_2;
+  input FTMT_F2P_TRIG_3;
+  output FTMT_F2P_TRIGACK_3;
+  input [31:0]FTMT_F2P_DEBUG;
+  input FTMT_P2F_TRIGACK_0;
+  output FTMT_P2F_TRIG_0;
+  input FTMT_P2F_TRIGACK_1;
+  output FTMT_P2F_TRIG_1;
+  input FTMT_P2F_TRIGACK_2;
+  output FTMT_P2F_TRIG_2;
+  input FTMT_P2F_TRIGACK_3;
+  output FTMT_P2F_TRIG_3;
+  output [31:0]FTMT_P2F_DEBUG;
+  input FPGA_IDLE_N;
+  output EVENT_EVENTO;
+  output [1:0]EVENT_STANDBYWFE;
+  output [1:0]EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  input [3:0]DDR_ARB;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+
+  wire \\<const0> ;
+  wire CAN0_PHY_RX;
+  wire CAN0_PHY_TX;
+  wire CAN1_PHY_RX;
+  wire CAN1_PHY_TX;
+  wire Core0_nFIQ;
+  wire Core0_nIRQ;
+  wire Core1_nFIQ;
+  wire Core1_nIRQ;
+  wire [3:0]DDR_ARB;
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire DMA0_ACLK;
+  wire DMA0_DAREADY;
+  wire [1:0]DMA0_DATYPE;
+  wire DMA0_DAVALID;
+  wire DMA0_DRLAST;
+  wire DMA0_DRREADY;
+  wire [1:0]DMA0_DRTYPE;
+  wire DMA0_DRVALID;
+  wire DMA0_RSTN;
+  wire DMA1_ACLK;
+  wire DMA1_DAREADY;
+  wire [1:0]DMA1_DATYPE;
+  wire DMA1_DAVALID;
+  wire DMA1_DRLAST;
+  wire DMA1_DRREADY;
+  wire [1:0]DMA1_DRTYPE;
+  wire DMA1_DRVALID;
+  wire DMA1_RSTN;
+  wire DMA2_ACLK;
+  wire DMA2_DAREADY;
+  wire [1:0]DMA2_DATYPE;
+  wire DMA2_DAVALID;
+  wire DMA2_DRLAST;
+  wire DMA2_DRREADY;
+  wire [1:0]DMA2_DRTYPE;
+  wire DMA2_DRVALID;
+  wire DMA2_RSTN;
+  wire DMA3_ACLK;
+  wire DMA3_DAREADY;
+  wire [1:0]DMA3_DATYPE;
+  wire DMA3_DAVALID;
+  wire DMA3_DRLAST;
+  wire DMA3_DRREADY;
+  wire [1:0]DMA3_DRTYPE;
+  wire DMA3_DRVALID;
+  wire DMA3_RSTN;
+  wire ENET0_EXT_INTIN;
+  wire ENET0_GMII_RX_CLK;
+  wire ENET0_GMII_TX_CLK;
+  wire ENET0_MDIO_I;
+  wire ENET0_MDIO_MDC;
+  wire ENET0_MDIO_O;
+  wire ENET0_MDIO_T;
+  wire ENET0_MDIO_T_n;
+  wire ENET0_PTP_DELAY_REQ_RX;
+  wire ENET0_PTP_DELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_REQ_RX;
+  wire ENET0_PTP_PDELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_RESP_RX;
+  wire ENET0_PTP_PDELAY_RESP_TX;
+  wire ENET0_PTP_SYNC_FRAME_RX;
+  wire ENET0_PTP_SYNC_FRAME_TX;
+  wire ENET0_SOF_RX;
+  wire ENET0_SOF_TX;
+  wire ENET1_EXT_INTIN;
+  wire ENET1_GMII_RX_CLK;
+  wire ENET1_GMII_TX_CLK;
+  wire ENET1_MDIO_I;
+  wire ENET1_MDIO_MDC;
+  wire ENET1_MDIO_O;
+  wire ENET1_MDIO_T;
+  wire ENET1_MDIO_T_n;
+  wire ENET1_PTP_DELAY_REQ_RX;
+  wire ENET1_PTP_DELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_REQ_RX;
+  wire ENET1_PTP_PDELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_RESP_RX;
+  wire ENET1_PTP_PDELAY_RESP_TX;
+  wire ENET1_PTP_SYNC_FRAME_RX;
+  wire ENET1_PTP_SYNC_FRAME_TX;
+  wire ENET1_SOF_RX;
+  wire ENET1_SOF_TX;
+  wire EVENT_EVENTI;
+  wire EVENT_EVENTO;
+  wire [1:0]EVENT_STANDBYWFE;
+  wire [1:0]EVENT_STANDBYWFI;
+  wire FCLK_CLK0;
+  wire FCLK_CLK1;
+  wire FCLK_CLK2;
+  wire FCLK_CLK3;
+  wire [0:0]FCLK_CLK_unbuffered;
+  wire FCLK_RESET0_N;
+  wire FCLK_RESET1_N;
+  wire FCLK_RESET2_N;
+  wire FCLK_RESET3_N;
+  wire FPGA_IDLE_N;
+  wire FTMD_TRACEIN_CLK;
+  wire [31:0]FTMT_F2P_DEBUG;
+  wire FTMT_F2P_TRIGACK_0;
+  wire FTMT_F2P_TRIGACK_1;
+  wire FTMT_F2P_TRIGACK_2;
+  wire FTMT_F2P_TRIGACK_3;
+  wire FTMT_F2P_TRIG_0;
+  wire FTMT_F2P_TRIG_1;
+  wire FTMT_F2P_TRIG_2;
+  wire FTMT_F2P_TRIG_3;
+  wire [31:0]FTMT_P2F_DEBUG;
+  wire FTMT_P2F_TRIGACK_0;
+  wire FTMT_P2F_TRIGACK_1;
+  wire FTMT_P2F_TRIGACK_2;
+  wire FTMT_P2F_TRIGACK_3;
+  wire FTMT_P2F_TRIG_0;
+  wire FTMT_P2F_TRIG_1;
+  wire FTMT_P2F_TRIG_2;
+  wire FTMT_P2F_TRIG_3;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SCL_T_n;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire I2C0_SDA_T_n;
+  wire I2C1_SCL_I;
+  wire I2C1_SCL_O;
+  wire I2C1_SCL_T;
+  wire I2C1_SCL_T_n;
+  wire I2C1_SDA_I;
+  wire I2C1_SDA_O;
+  wire I2C1_SDA_T;
+  wire I2C1_SDA_T_n;
+  wire [0:0]IRQ_F2P;
+  wire IRQ_P2F_CAN0;
+  wire IRQ_P2F_CAN1;
+  wire IRQ_P2F_CTI;
+  wire IRQ_P2F_DMAC0;
+  wire IRQ_P2F_DMAC1;
+  wire IRQ_P2F_DMAC2;
+  wire IRQ_P2F_DMAC3;
+  wire IRQ_P2F_DMAC4;
+  wire IRQ_P2F_DMAC5;
+  wire IRQ_P2F_DMAC6;
+  wire IRQ_P2F_DMAC7;
+  wire IRQ_P2F_DMAC_ABORT;
+  wire IRQ_P2F_ENET0;
+  wire IRQ_P2F_ENET1;
+  wire IRQ_P2F_ENET_WAKE0;
+  wire IRQ_P2F_ENET_WAKE1;
+  wire IRQ_P2F_GPIO;
+  wire IRQ_P2F_I2C0;
+  wire IRQ_P2F_I2C1;
+  wire IRQ_P2F_QSPI;
+  wire IRQ_P2F_SDIO0;
+  wire IRQ_P2F_SDIO1;
+  wire IRQ_P2F_SMC;
+  wire IRQ_P2F_SPI0;
+  wire IRQ_P2F_SPI1;
+  wire IRQ_P2F_UART0;
+  wire IRQ_P2F_UART1;
+  wire IRQ_P2F_USB0;
+  wire IRQ_P2F_USB1;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire M_AXI_GP0_ARESETN;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [1:0]\\^M_AXI_GP0_ARSIZE ;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [1:0]\\^M_AXI_GP0_AWSIZE ;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire M_AXI_GP1_ACLK;
+  wire [31:0]M_AXI_GP1_ARADDR;
+  wire [1:0]M_AXI_GP1_ARBURST;
+  wire [3:0]M_AXI_GP1_ARCACHE;
+  wire M_AXI_GP1_ARESETN;
+  wire [11:0]M_AXI_GP1_ARID;
+  wire [3:0]M_AXI_GP1_ARLEN;
+  wire [1:0]M_AXI_GP1_ARLOCK;
+  wire [2:0]M_AXI_GP1_ARPROT;
+  wire [3:0]M_AXI_GP1_ARQOS;
+  wire M_AXI_GP1_ARREADY;
+  wire [1:0]\\^M_AXI_GP1_ARSIZE ;
+  wire M_AXI_GP1_ARVALID;
+  wire [31:0]M_AXI_GP1_AWADDR;
+  wire [1:0]M_AXI_GP1_AWBURST;
+  wire [3:0]M_AXI_GP1_AWCACHE;
+  wire [11:0]M_AXI_GP1_AWID;
+  wire [3:0]M_AXI_GP1_AWLEN;
+  wire [1:0]M_AXI_GP1_AWLOCK;
+  wire [2:0]M_AXI_GP1_AWPROT;
+  wire [3:0]M_AXI_GP1_AWQOS;
+  wire M_AXI_GP1_AWREADY;
+  wire [1:0]\\^M_AXI_GP1_AWSIZE ;
+  wire M_AXI_GP1_AWVALID;
+  wire [11:0]M_AXI_GP1_BID;
+  wire M_AXI_GP1_BREADY;
+  wire [1:0]M_AXI_GP1_BRESP;
+  wire M_AXI_GP1_BVALID;
+  wire [31:0]M_AXI_GP1_RDATA;
+  wire [11:0]M_AXI_GP1_RID;
+  wire M_AXI_GP1_RLAST;
+  wire M_AXI_GP1_RREADY;
+  wire [1:0]M_AXI_GP1_RRESP;
+  wire M_AXI_GP1_RVALID;
+  wire [31:0]M_AXI_GP1_WDATA;
+  wire [11:0]M_AXI_GP1_WID;
+  wire M_AXI_GP1_WLAST;
+  wire M_AXI_GP1_WREADY;
+  wire [3:0]M_AXI_GP1_WSTRB;
+  wire M_AXI_GP1_WVALID;
+  wire PJTAG_TCK;
+  wire PJTAG_TDI;
+  wire PJTAG_TMS;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_BUSPOW;
+  wire [2:0]SDIO0_BUSVOLT;
+  wire SDIO0_CDN;
+  wire SDIO0_CLK;
+  wire SDIO0_CLK_FB;
+  wire SDIO0_CMD_I;
+  wire SDIO0_CMD_O;
+  wire SDIO0_CMD_T;
+  wire SDIO0_CMD_T_n;
+  wire [3:0]SDIO0_DATA_I;
+  wire [3:0]SDIO0_DATA_O;
+  wire [3:0]SDIO0_DATA_T;
+  wire [3:0]SDIO0_DATA_T_n;
+  wire SDIO0_LED;
+  wire SDIO0_WP;
+  wire SDIO1_BUSPOW;
+  wire [2:0]SDIO1_BUSVOLT;
+  wire SDIO1_CDN;
+  wire SDIO1_CLK;
+  wire SDIO1_CLK_FB;
+  wire SDIO1_CMD_I;
+  wire SDIO1_CMD_O;
+  wire SDIO1_CMD_T;
+  wire SDIO1_CMD_T_n;
+  wire [3:0]SDIO1_DATA_I;
+  wire [3:0]SDIO1_DATA_O;
+  wire [3:0]SDIO1_DATA_T;
+  wire [3:0]SDIO1_DATA_T_n;
+  wire SDIO1_LED;
+  wire SDIO1_WP;
+  wire SPI0_MISO_I;
+  wire SPI0_MISO_O;
+  wire SPI0_MISO_T;
+  wire SPI0_MISO_T_n;
+  wire SPI0_MOSI_I;
+  wire SPI0_MOSI_O;
+  wire SPI0_MOSI_T;
+  wire SPI0_MOSI_T_n;
+  wire SPI0_SCLK_I;
+  wire SPI0_SCLK_O;
+  wire SPI0_SCLK_T;
+  wire SPI0_SCLK_T_n;
+  wire SPI0_SS1_O;
+  wire SPI0_SS2_O;
+  wire SPI0_SS_I;
+  wire SPI0_SS_O;
+  wire SPI0_SS_T;
+  wire SPI0_SS_T_n;
+  wire SPI1_MISO_I;
+  wire SPI1_MISO_O;
+  wire SPI1_MISO_T;
+  wire SPI1_MISO_T_n;
+  wire SPI1_MOSI_I;
+  wire SPI1_MOSI_O;
+  wire SPI1_MOSI_T;
+  wire SPI1_MOSI_T_n;
+  wire SPI1_SCLK_I;
+  wire SPI1_SCLK_O;
+  wire SPI1_SCLK_T;
+  wire SPI1_SCLK_T_n;
+  wire SPI1_SS1_O;
+  wire SPI1_SS2_O;
+  wire SPI1_SS_I;
+  wire SPI1_SS_O;
+  wire SPI1_SS_T;
+  wire SPI1_SS_T_n;
+  wire SRAM_INTIN;
+  wire S_AXI_ACP_ACLK;
+  wire [31:0]S_AXI_ACP_ARADDR;
+  wire [1:0]S_AXI_ACP_ARBURST;
+  wire [3:0]S_AXI_ACP_ARCACHE;
+  wire S_AXI_ACP_ARESETN;
+  wire [2:0]S_AXI_ACP_ARID;
+  wire [3:0]S_AXI_ACP_ARLEN;
+  wire [1:0]S_AXI_ACP_ARLOCK;
+  wire [2:0]S_AXI_ACP_ARPROT;
+  wire [3:0]S_AXI_ACP_ARQOS;
+  wire S_AXI_ACP_ARREADY;
+  wire [2:0]S_AXI_ACP_ARSIZE;
+  wire [4:0]S_AXI_ACP_ARUSER;
+  wire S_AXI_ACP_ARVALID;
+  wire [31:0]S_AXI_ACP_AWADDR;
+  wire [1:0]S_AXI_ACP_AWBURST;
+  wire [3:0]S_AXI_ACP_AWCACHE;
+  wire [2:0]S_AXI_ACP_AWID;
+  wire [3:0]S_AXI_ACP_AWLEN;
+  wire [1:0]S_AXI_ACP_AWLOCK;
+  wire [2:0]S_AXI_ACP_AWPROT;
+  wire [3:0]S_AXI_ACP_AWQOS;
+  wire S_AXI_ACP_AWREADY;
+  wire [2:0]S_AXI_ACP_AWSIZE;
+  wire [4:0]S_AXI_ACP_AWUSER;
+  wire S_AXI_ACP_AWVALID;
+  wire [2:0]S_AXI_ACP_BID;
+  wire S_AXI_ACP_BREADY;
+  wire [1:0]S_AXI_ACP_BRESP;
+  wire S_AXI_ACP_BVALID;
+  wire [63:0]S_AXI_ACP_RDATA;
+  wire [2:0]S_AXI_ACP_RID;
+  wire S_AXI_ACP_RLAST;
+  wire S_AXI_ACP_RREADY;
+  wire [1:0]S_AXI_ACP_RRESP;
+  wire S_AXI_ACP_RVALID;
+  wire [63:0]S_AXI_ACP_WDATA;
+  wire [2:0]S_AXI_ACP_WID;
+  wire S_AXI_ACP_WLAST;
+  wire S_AXI_ACP_WREADY;
+  wire [7:0]S_AXI_ACP_WSTRB;
+  wire S_AXI_ACP_WVALID;
+  wire S_AXI_GP0_ACLK;
+  wire [31:0]S_AXI_GP0_ARADDR;
+  wire [1:0]S_AXI_GP0_ARBURST;
+  wire [3:0]S_AXI_GP0_ARCACHE;
+  wire S_AXI_GP0_ARESETN;
+  wire [5:0]S_AXI_GP0_ARID;
+  wire [3:0]S_AXI_GP0_ARLEN;
+  wire [1:0]S_AXI_GP0_ARLOCK;
+  wire [2:0]S_AXI_GP0_ARPROT;
+  wire [3:0]S_AXI_GP0_ARQOS;
+  wire S_AXI_GP0_ARREADY;
+  wire [2:0]S_AXI_GP0_ARSIZE;
+  wire S_AXI_GP0_ARVALID;
+  wire [31:0]S_AXI_GP0_AWADDR;
+  wire [1:0]S_AXI_GP0_AWBURST;
+  wire [3:0]S_AXI_GP0_AWCACHE;
+  wire [5:0]S_AXI_GP0_AWID;
+  wire [3:0]S_AXI_GP0_AWLEN;
+  wire [1:0]S_AXI_GP0_AWLOCK;
+  wire [2:0]S_AXI_GP0_AWPROT;
+  wire [3:0]S_AXI_GP0_AWQOS;
+  wire S_AXI_GP0_AWREADY;
+  wire [2:0]S_AXI_GP0_AWSIZE;
+  wire S_AXI_GP0_AWVALID;
+  wire [5:0]S_AXI_GP0_BID;
+  wire S_AXI_GP0_BREADY;
+  wire [1:0]S_AXI_GP0_BRESP;
+  wire S_AXI_GP0_BVALID;
+  wire [31:0]S_AXI_GP0_RDATA;
+  wire [5:0]S_AXI_GP0_RID;
+  wire S_AXI_GP0_RLAST;
+  wire S_AXI_GP0_RREADY;
+  wire [1:0]S_AXI_GP0_RRESP;
+  wire S_AXI_GP0_RVALID;
+  wire [31:0]S_AXI_GP0_WDATA;
+  wire [5:0]S_AXI_GP0_WID;
+  wire S_AXI_GP0_WLAST;
+  wire S_AXI_GP0_WREADY;
+  wire [3:0]S_AXI_GP0_WSTRB;
+  wire S_AXI_GP0_WVALID;
+  wire S_AXI_GP1_ACLK;
+  wire [31:0]S_AXI_GP1_ARADDR;
+  wire [1:0]S_AXI_GP1_ARBURST;
+  wire [3:0]S_AXI_GP1_ARCACHE;
+  wire S_AXI_GP1_ARESETN;
+  wire [5:0]S_AXI_GP1_ARID;
+  wire [3:0]S_AXI_GP1_ARLEN;
+  wire [1:0]S_AXI_GP1_ARLOCK;
+  wire [2:0]S_AXI_GP1_ARPROT;
+  wire [3:0]S_AXI_GP1_ARQOS;
+  wire S_AXI_GP1_ARREADY;
+  wire [2:0]S_AXI_GP1_ARSIZE;
+  wire S_AXI_GP1_ARVALID;
+  wire [31:0]S_AXI_GP1_AWADDR;
+  wire [1:0]S_AXI_GP1_AWBURST;
+  wire [3:0]S_AXI_GP1_AWCACHE;
+  wire [5:0]S_AXI_GP1_AWID;
+  wire [3:0]S_AXI_GP1_AWLEN;
+  wire [1:0]S_AXI_GP1_AWLOCK;
+  wire [2:0]S_AXI_GP1_AWPROT;
+  wire [3:0]S_AXI_GP1_AWQOS;
+  wire S_AXI_GP1_AWREADY;
+  wire [2:0]S_AXI_GP1_AWSIZE;
+  wire S_AXI_GP1_AWVALID;
+  wire [5:0]S_AXI_GP1_BID;
+  wire S_AXI_GP1_BREADY;
+  wire [1:0]S_AXI_GP1_BRESP;
+  wire S_AXI_GP1_BVALID;
+  wire [31:0]S_AXI_GP1_RDATA;
+  wire [5:0]S_AXI_GP1_RID;
+  wire S_AXI_GP1_RLAST;
+  wire S_AXI_GP1_RREADY;
+  wire [1:0]S_AXI_GP1_RRESP;
+  wire S_AXI_GP1_RVALID;
+  wire [31:0]S_AXI_GP1_WDATA;
+  wire [5:0]S_AXI_GP1_WID;
+  wire S_AXI_GP1_WLAST;
+  wire S_AXI_GP1_WREADY;
+  wire [3:0]S_AXI_GP1_WSTRB;
+  wire S_AXI_GP1_WVALID;
+  wire S_AXI_HP0_ACLK;
+  wire [31:0]S_AXI_HP0_ARADDR;
+  wire [1:0]S_AXI_HP0_ARBURST;
+  wire [3:0]S_AXI_HP0_ARCACHE;
+  wire S_AXI_HP0_ARESETN;
+  wire [5:0]S_AXI_HP0_ARID;
+  wire [3:0]S_AXI_HP0_ARLEN;
+  wire [1:0]S_AXI_HP0_ARLOCK;
+  wire [2:0]S_AXI_HP0_ARPROT;
+  wire [3:0]S_AXI_HP0_ARQOS;
+  wire S_AXI_HP0_ARREADY;
+  wire [2:0]S_AXI_HP0_ARSIZE;
+  wire S_AXI_HP0_ARVALID;
+  wire [31:0]S_AXI_HP0_AWADDR;
+  wire [1:0]S_AXI_HP0_AWBURST;
+  wire [3:0]S_AXI_HP0_AWCACHE;
+  wire [5:0]S_AXI_HP0_AWID;
+  wire [3:0]S_AXI_HP0_AWLEN;
+  wire [1:0]S_AXI_HP0_AWLOCK;
+  wire [2:0]S_AXI_HP0_AWPROT;
+  wire [3:0]S_AXI_HP0_AWQOS;
+  wire S_AXI_HP0_AWREADY;
+  wire [2:0]S_AXI_HP0_AWSIZE;
+  wire S_AXI_HP0_AWVALID;
+  wire [5:0]S_AXI_HP0_BID;
+  wire S_AXI_HP0_BREADY;
+  wire [1:0]S_AXI_HP0_BRESP;
+  wire S_AXI_HP0_BVALID;
+  wire [2:0]S_AXI_HP0_RACOUNT;
+  wire [7:0]S_AXI_HP0_RCOUNT;
+  wire [63:0]S_AXI_HP0_RDATA;
+  wire S_AXI_HP0_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP0_RID;
+  wire S_AXI_HP0_RLAST;
+  wire S_AXI_HP0_RREADY;
+  wire [1:0]S_AXI_HP0_RRESP;
+  wire S_AXI_HP0_RVALID;
+  wire [5:0]S_AXI_HP0_WACOUNT;
+  wire [7:0]S_AXI_HP0_WCOUNT;
+  wire [63:0]S_AXI_HP0_WDATA;
+  wire [5:0]S_AXI_HP0_WID;
+  wire S_AXI_HP0_WLAST;
+  wire S_AXI_HP0_WREADY;
+  wire S_AXI_HP0_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP0_WSTRB;
+  wire S_AXI_HP0_WVALID;
+  wire S_AXI_HP1_ACLK;
+  wire [31:0]S_AXI_HP1_ARADDR;
+  wire [1:0]S_AXI_HP1_ARBURST;
+  wire [3:0]S_AXI_HP1_ARCACHE;
+  wire S_AXI_HP1_ARESETN;
+  wire [5:0]S_AXI_HP1_ARID;
+  wire [3:0]S_AXI_HP1_ARLEN;
+  wire [1:0]S_AXI_HP1_ARLOCK;
+  wire [2:0]S_AXI_HP1_ARPROT;
+  wire [3:0]S_AXI_HP1_ARQOS;
+  wire S_AXI_HP1_ARREADY;
+  wire [2:0]S_AXI_HP1_ARSIZE;
+  wire S_AXI_HP1_ARVALID;
+  wire [31:0]S_AXI_HP1_AWADDR;
+  wire [1:0]S_AXI_HP1_AWBURST;
+  wire [3:0]S_AXI_HP1_AWCACHE;
+  wire [5:0]S_AXI_HP1_AWID;
+  wire [3:0]S_AXI_HP1_AWLEN;
+  wire [1:0]S_AXI_HP1_AWLOCK;
+  wire [2:0]S_AXI_HP1_AWPROT;
+  wire [3:0]S_AXI_HP1_AWQOS;
+  wire S_AXI_HP1_AWREADY;
+  wire [2:0]S_AXI_HP1_AWSIZE;
+  wire S_AXI_HP1_AWVALID;
+  wire [5:0]S_AXI_HP1_BID;
+  wire S_AXI_HP1_BREADY;
+  wire [1:0]S_AXI_HP1_BRESP;
+  wire S_AXI_HP1_BVALID;
+  wire [2:0]S_AXI_HP1_RACOUNT;
+  wire [7:0]S_AXI_HP1_RCOUNT;
+  wire [63:0]S_AXI_HP1_RDATA;
+  wire S_AXI_HP1_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP1_RID;
+  wire S_AXI_HP1_RLAST;
+  wire S_AXI_HP1_RREADY;
+  wire [1:0]S_AXI_HP1_RRESP;
+  wire S_AXI_HP1_RVALID;
+  wire [5:0]S_AXI_HP1_WACOUNT;
+  wire [7:0]S_AXI_HP1_WCOUNT;
+  wire [63:0]S_AXI_HP1_WDATA;
+  wire [5:0]S_AXI_HP1_WID;
+  wire S_AXI_HP1_WLAST;
+  wire S_AXI_HP1_WREADY;
+  wire S_AXI_HP1_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP1_WSTRB;
+  wire S_AXI_HP1_WVALID;
+  wire S_AXI_HP2_ACLK;
+  wire [31:0]S_AXI_HP2_ARADDR;
+  wire [1:0]S_AXI_HP2_ARBURST;
+  wire [3:0]S_AXI_HP2_ARCACHE;
+  wire S_AXI_HP2_ARESETN;
+  wire [5:0]S_AXI_HP2_ARID;
+  wire [3:0]S_AXI_HP2_ARLEN;
+  wire [1:0]S_AXI_HP2_ARLOCK;
+  wire [2:0]S_AXI_HP2_ARPROT;
+  wire [3:0]S_AXI_HP2_ARQOS;
+  wire S_AXI_HP2_ARREADY;
+  wire [2:0]S_AXI_HP2_ARSIZE;
+  wire S_AXI_HP2_ARVALID;
+  wire [31:0]S_AXI_HP2_AWADDR;
+  wire [1:0]S_AXI_HP2_AWBURST;
+  wire [3:0]S_AXI_HP2_AWCACHE;
+  wire [5:0]S_AXI_HP2_AWID;
+  wire [3:0]S_AXI_HP2_AWLEN;
+  wire [1:0]S_AXI_HP2_AWLOCK;
+  wire [2:0]S_AXI_HP2_AWPROT;
+  wire [3:0]S_AXI_HP2_AWQOS;
+  wire S_AXI_HP2_AWREADY;
+  wire [2:0]S_AXI_HP2_AWSIZE;
+  wire S_AXI_HP2_AWVALID;
+  wire [5:0]S_AXI_HP2_BID;
+  wire S_AXI_HP2_BREADY;
+  wire [1:0]S_AXI_HP2_BRESP;
+  wire S_AXI_HP2_BVALID;
+  wire [2:0]S_AXI_HP2_RACOUNT;
+  wire [7:0]S_AXI_HP2_RCOUNT;
+  wire [63:0]S_AXI_HP2_RDATA;
+  wire S_AXI_HP2_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP2_RID;
+  wire S_AXI_HP2_RLAST;
+  wire S_AXI_HP2_RREADY;
+  wire [1:0]S_AXI_HP2_RRESP;
+  wire S_AXI_HP2_RVALID;
+  wire [5:0]S_AXI_HP2_WACOUNT;
+  wire [7:0]S_AXI_HP2_WCOUNT;
+  wire [63:0]S_AXI_HP2_WDATA;
+  wire [5:0]S_AXI_HP2_WID;
+  wire S_AXI_HP2_WLAST;
+  wire S_AXI_HP2_WREADY;
+  wire S_AXI_HP2_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP2_WSTRB;
+  wire S_AXI_HP2_WVALID;
+  wire S_AXI_HP3_ACLK;
+  wire [31:0]S_AXI_HP3_ARADDR;
+  wire [1:0]S_AXI_HP3_ARBURST;
+  wire [3:0]S_AXI_HP3_ARCACHE;
+  wire S_AXI_HP3_ARESETN;
+  wire [5:0]S_AXI_HP3_ARID;
+  wire [3:0]S_AXI_HP3_ARLEN;
+  wire [1:0]S_AXI_HP3_ARLOCK;
+  wire [2:0]S_AXI_HP3_ARPROT;
+  wire [3:0]S_AXI_HP3_ARQOS;
+  wire S_AXI_HP3_ARREADY;
+  wire [2:0]S_AXI_HP3_ARSIZE;
+  wire S_AXI_HP3_ARVALID;
+  wire [31:0]S_AXI_HP3_AWADDR;
+  wire [1:0]S_AXI_HP3_AWBURST;
+  wire [3:0]S_AXI_HP3_AWCACHE;
+  wire [5:0]S_AXI_HP3_AWID;
+  wire [3:0]S_AXI_HP3_AWLEN;
+  wire [1:0]S_AXI_HP3_AWLOCK;
+  wire [2:0]S_AXI_HP3_AWPROT;
+  wire [3:0]S_AXI_HP3_AWQOS;
+  wire S_AXI_HP3_AWREADY;
+  wire [2:0]S_AXI_HP3_AWSIZE;
+  wire S_AXI_HP3_AWVALID;
+  wire [5:0]S_AXI_HP3_BID;
+  wire S_AXI_HP3_BREADY;
+  wire [1:0]S_AXI_HP3_BRESP;
+  wire S_AXI_HP3_BVALID;
+  wire [2:0]S_AXI_HP3_RACOUNT;
+  wire [7:0]S_AXI_HP3_RCOUNT;
+  wire [63:0]S_AXI_HP3_RDATA;
+  wire S_AXI_HP3_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP3_RID;
+  wire S_AXI_HP3_RLAST;
+  wire S_AXI_HP3_RREADY;
+  wire [1:0]S_AXI_HP3_RRESP;
+  wire S_AXI_HP3_RVALID;
+  wire [5:0]S_AXI_HP3_WACOUNT;
+  wire [7:0]S_AXI_HP3_WCOUNT;
+  wire [63:0]S_AXI_HP3_WDATA;
+  wire [5:0]S_AXI_HP3_WID;
+  wire S_AXI_HP3_WLAST;
+  wire S_AXI_HP3_WREADY;
+  wire S_AXI_HP3_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP3_WSTRB;
+  wire S_AXI_HP3_WVALID;
+  wire TRACE_CLK;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[7] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[7] ;
+  wire TTC0_CLK0_IN;
+  wire TTC0_CLK1_IN;
+  wire TTC0_CLK2_IN;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire TTC1_CLK0_IN;
+  wire TTC1_CLK1_IN;
+  wire TTC1_CLK2_IN;
+  wire TTC1_WAVE0_OUT;
+  wire TTC1_WAVE1_OUT;
+  wire TTC1_WAVE2_OUT;
+  wire UART0_CTSN;
+  wire UART0_DCDN;
+  wire UART0_DSRN;
+  wire UART0_DTRN;
+  wire UART0_RIN;
+  wire UART0_RTSN;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire UART1_CTSN;
+  wire UART1_DCDN;
+  wire UART1_DSRN;
+  wire UART1_DTRN;
+  wire UART1_RIN;
+  wire UART1_RTSN;
+  wire UART1_RX;
+  wire UART1_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire [1:0]USB1_PORT_INDCTL;
+  wire USB1_VBUS_PWRFAULT;
+  wire USB1_VBUS_PWRSELECT;
+  wire WDT_CLK_IN;
+  wire WDT_RST_OUT;
+  wire [14:0]buffered_DDR_Addr;
+  wire [2:0]buffered_DDR_BankAddr;
+  wire buffered_DDR_CAS_n;
+  wire buffered_DDR_CKE;
+  wire buffered_DDR_CS_n;
+  wire buffered_DDR_C'b'lk;
+  wire buffered_DDR_Clk_n;
+  wire [3:0]buffered_DDR_DM;
+  wire [31:0]buffered_DDR_DQ;
+  wire [3:0]buffered_DDR_DQS;
+  wire [3:0]buffered_DDR_DQS_n;
+  wire buffered_DDR_DRSTB;
+  wire buffered_DDR_ODT;
+  wire buffered_DDR_RAS_n;
+  wire buffered_DDR_VRN;
+  wire buffered_DDR_VRP;
+  wire buffered_DDR_WEB;
+  wire [53:0]buffered_MIO;
+  wire buffered_PS_CLK;
+  wire buffered_PS_PORB;
+  wire buffered_PS_SRSTB;
+  wire [63:0]gpio_out_t_n;
+  wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
+  wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+
+  assign ENET0_GMII_TXD[7] = \\<const0> ;
+  assign ENET0_GMII_TXD[6] = \\<const0> ;
+  assign ENET0_GMII_TXD[5] = \\<const0> ;
+  assign ENET0_GMII_TXD[4] = \\<const0> ;
+  assign ENET0_GMII_TXD[3] = \\<const0> ;
+  assign ENET0_GMII_TXD[2] = \\<const0> ;
+  assign ENET0_GMII_TXD[1] = \\<const0> ;
+  assign ENET0_GMII_TXD[0] = \\<const0> ;
+  assign ENET0_GMII_TX_EN = \\<const0> ;
+  assign ENET0_GMII_TX_ER = \\<const0> ;
+  assign ENET1_GMII_TXD[7] = \\<const0> ;
+  assign ENET1_GMII_TXD[6] = \\<const0> ;
+  assign ENET1_GMII_TXD[5] = \\<const0> ;
+  assign ENET1_GMII_TXD[4] = \\<const0> ;
+  assign ENET1_GMII_TXD[3] = \\<const0> ;
+  assign ENET1_GMII_TXD[2] = \\<const0> ;
+  assign ENET1_GMII_TXD[1] = \\<const0> ;
+  assign ENET1_GMII_TXD[0] = \\<const0> ;
+  assign ENET1_GMII_TX_EN = \\<const0> ;
+  assign ENET1_GMII_TX_ER = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[1:0] = \\^M_AXI_GP0_ARSIZE [1:0];
+  assign M_AXI_GP0_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_AWSIZE[1:0] = \\^M_AXI_GP0_AWSIZE [1:0];
+  assign M_AXI_GP1_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_ARSIZE[1:0] = \\^M_AXI_GP1_ARSIZE [1:0];
+  assign M_AXI_GP1_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_AWSIZE[1:0] = \\^M_AXI_GP1_AWSIZE [1:0];
+  assign PJTAG_TDO = \\<const0> ;
+  assign TRACE_CLK_OUT = \\<const0> ;
+  assign TRACE_CTL = \\TRACE_CTL_PIPE[0] ;
+  assign TRACE_DATA[1:0] = \\TRACE_DATA_PIPE[0] ;
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CAS_n_BIBUF
+       (.IO(buffered_DDR_CAS_n),
+        .PAD(DDR_CAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CKE_BIBUF
+       (.IO(buffered_DDR_CKE),
+        .PAD(DDR_CKE));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CS_n_BIBUF
+       (.IO(buffered_DDR_CS_n),
+        .PAD(DDR_CS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_BIBUF
+       (.IO(buffered_DDR_Clk),
+        .PAD(DDR_Clk));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_n_BIBUF
+       (.IO(buffered_DDR_Clk_n),
+        .PAD(DDR_Clk_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_DRSTB_BIBUF
+       (.IO(buffered_DDR_DRSTB),
+        .PAD(DDR_DRSTB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_ODT_BIBUF
+       (.IO(buffered_DDR_ODT),
+        .PAD(DDR_ODT));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_RAS_n_BIBUF
+       (.IO(buffered_DDR_RAS_n),
+        .PAD(DDR_RAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRN_BIBUF
+       (.IO(buffered_DDR_VRN),
+        .PAD(DDR_VRN));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRP_BIBUF
+       (.IO(buffered_DDR_VRP),
+        .PAD(DDR_VRP));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_WEB_BIBUF
+       (.IO(buffered_DDR_WEB),
+        .PAD(DDR_WEB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET0_MDIO_T_INST_0
+       (.I0(ENET0_MDIO_T_n),
+        .O(ENET0_MDIO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET1_MDIO_T_INST_0
+       (.I0(ENET1_MDIO_T_n),
+        .O(ENET1_MDIO_T));
+  GND GND
+       (.G(\\<const0> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[0]_INST_0 
+       (.I0(gpio_out_t_n[0]),
+        .O(GPIO_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[10]_INST_0 
+       (.I0(gpio_out_t_n[10]),
+        .O(GPIO_T[10]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[11]_INST_0 
+       (.I0(gpio_out_t_n[11]),
+        .O(GPIO_T[11]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[12]_INST_0 
+       (.I0(gpio_out_t_n[12]),
+        .O(GPIO_T[12]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[13]_INST_0 
+       (.I0(gpio_out_t_n[13]),
+        .O(GPIO_T[13]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[14]_INST_0 
+       (.I0(gpio_out_t_n[14]),
+        .O(GPIO_T[14]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[15]_INST_0 
+       (.I0(gpio_out_t_n[15]),
+        .O(GPIO_T[15]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[16]_INST_0 
+       (.I0(gpio_out_t_n[16]),
+        .O(GPIO_T[16]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[17]_INST_0 
+       (.I0(gpio_out_t_n[17]),
+        .O(GPIO_T[17]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[18]_INST_0 
+       (.I0(gpio_out_t_n[18]),
+        .O(GPIO_T[18]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[19]_INST_0 
+       (.I0(gpio_out_t_n[19]),
+        .O(GPIO_T[19]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[1]_INST_0 
+       (.I0(gpio_out_t_n[1]),
+        .O(GPIO_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[20]_INST_0 
+       (.I0(gpio_out_t_n[20]),
+        .O(GPIO_T[20]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[21]_INST_0 
+       (.I0(gpio_out_t_n[21]),
+        .O(GPIO_T[21]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[22]_INST_0 
+       (.I0(gpio_out_t_n[22]),
+        .O(GPIO_T[22]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[23]_INST_0 
+       (.I0(gpio_out_t_n[23]),
+        .O(GPIO_T[23]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[24]_INST_0 
+       (.I0(gpio_out_t_n[24]),
+        .O(GPIO_T[24]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[25]_INST_0 
+       (.I0(gpio_out_t_n[25]),
+        .O(GPIO_T[25]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[26]_INST_0 
+       (.I0(gpio_out_t_n[26]),
+        .O(GPIO_T[26]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[27]_INST_0 
+       (.I0(gpio_out_t_n[27]),
+        .O(GPIO_T[27]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[28]_INST_0 
+       (.I0(gpio_out_t_n[28]),
+        .O(GPIO_T[28]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[29]_INST_0 
+       (.I0(gpio_out_t_n[29]),
+        .O(GPIO_T[29]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[2]_INST_0 
+       (.I0(gpio_out_t_n[2]),
+        .O(GPIO_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[30]_INST_0 
+       (.I0(gpio_out_t_n[30]),
+        .O(GPIO_T[30]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[31]_INST_0 
+       (.I0(gpio_out_t_n[31]),
+        .O(GPIO_T[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[32]_INST_0 
+       (.I0(gpio_out_t_n[32]),
+        .O(GPIO_T[32]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[33]_INST_0 
+       (.I0(gpio_out_t_n[33]),
+        .O(GPIO_T[33]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[34]_INST_0 
+       (.I0(gpio_out_t_n[34]),
+        .O(GPIO_T[34]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[35]_INST_0 
+       (.I0(gpio_out_t_n[35]),
+        .O(GPIO_T[35]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[36]_INST_0 
+       (.I0(gpio_out_t_n[36]),
+        .O(GPIO_T[36]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[37]_INST_0 
+       (.I0(gpio_out_t_n[37]),
+        .O(GPIO_T[37]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[38]_INST_0 
+       (.I0(gpio_out_t_n[38]),
+        .O(GPIO_T[38]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[39]_INST_0 
+       (.I0(gpio_out_t_n[39]),
+        .O(GPIO_T[39]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[3]_INST_0 
+       (.I0(gpio_out_t_n[3]),
+        .O(GPIO_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[40]_INST_0 
+       (.I0(gpio_out_t_n[40]),
+        .O(GPIO_T[40]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[41]_INST_0 
+       (.I0(gpio_out_t_n[41]),
+        .O(GPIO_T[41]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[42]_INST_0 
+       (.I0(gpio_out_t_n[42]),
+        .O(GPIO_T[42]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[43]_INST_0 
+       (.I0(gpio_out_t_n[43]),
+        .O(GPIO_T[43]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[44]_INST_0 
+       (.I0(gpio_out_t_n[44]),
+        .O(GPIO_T[44]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[45]_INST_0 
+       (.I0(gpio_out_t_n[45]),
+        .O(GPIO_T[45]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[46]_INST_0 
+       (.I0(gpio_out_t_n[46]),
+        .O(GPIO_T[46]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[47]_INST_0 
+       (.I0(gpio_out_t_n[47]),
+        .O(GPIO_T[47]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[48]_INST_0 
+       (.I0(gpio_out_t_n[48]),
+        .O(GPIO_T[48]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[49]_INST_0 
+       (.I0(gpio_out_t_n[49]),
+        .O(GPIO_T[49]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[4]_INST_0 
+       (.I0(gpio_out_t_n[4]),
+        .O(GPIO_T[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[50]_INST_0 
+       (.I0(gpio_out_t_n[50]),
+        .O(GPIO_T[50]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[51]_INST_0 
+       (.I0(gpio_out_t_n[51]),
+        .O(GPIO_T[51]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[52]_INST_0 
+       (.I0(gpio_out_t_n[52]),
+        .O(GPIO_T[52]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[53]_INST_0 
+       (.I0(gpio_out_t_n[53]),
+        .O(GPIO_T[53]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[54]_INST_0 
+       (.I0(gpio_out_t_n[54]),
+        .O(GPIO_T[54]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[55]_INST_0 
+       (.I0(gpio_out_t_n[55]),
+        .O(GPIO_T[55]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[56]_INST_0 
+       (.I0(gpio_out_t_n[56]),
+        .O(GPIO_T[56]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[57]_INST_0 
+       (.I0(gpio_out_t_n[57]),
+        .O(GPIO_T[57]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[58]_INST_0 
+       (.I0(gpio_out_t_n[58]),
+        .O(GPIO_T[58]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[59]_INST_0 
+       (.I0(gpio_out_t_n[59]),
+        .O(GPIO_T[59]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[5]_INST_0 
+       (.I0(gpio_out_t_n[5]),
+        .O(GPIO_T[5]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[60]_INST_0 
+       (.I0(gpio_out_t_n[60]),
+        .O(GPIO_T[60]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[61]_INST_0 
+       (.I0(gpio_out_t_n[61]),
+        .O(GPIO_T[61]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[62]_INST_0 
+       (.I0(gpio_out_t_n[62]),
+        .O(GPIO_T[62]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[63]_INST_0 
+       (.I0(gpio_out_t_n[63]),
+        .O(GPIO_T[63]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[6]_INST_0 
+       (.I0(gpio_out_t_n[6]),
+        .O(GPIO_T[6]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[7]_INST_0 
+       (.I0(gpio_out_t_n[7]),
+        .O(GPIO_T[7]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[8]_INST_0 
+       (.I0(gpio_out_t_n[8]),
+        .O(GPIO_T[8]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[9]_INST_0 
+       (.I0(gpio_out_t_n[9]),
+        .O(GPIO_T[9]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SCL_T_INST_0
+       (.I0(I2C0_SCL_T_n),
+        .O(I2C0_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SDA_T_INST_0
+       (.I0(I2C0_SDA_T_n),
+        .O(I2C0_SDA_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SCL_T_INST_0
+       (.I0(I2C1_SCL_T_n),
+        .O(I2C1_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SDA_T_INST_0
+       (.I0(I2C1_SDA_T_n),
+        .O(I2C1_SDA_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  PS7 PS7_i
+       (.DDRA(buffered_DDR_Addr),
+        .DDRARB(DDR_ARB),
+        .DDRBA(buffered_DDR_BankAddr),
+        .DDRCASB(buffered_DDR_CAS_n),
+        .DDRCKE(buffered_DDR_CKE),
+        .DDRCKN(buffered_DDR_Clk_n),
+        .DDRCKP(buffered_DDR_Clk),
+        .DDRCSB(buffered_DDR_CS_n),
+        .DDRDM(buffered_DDR_DM),
+        .DDRDQ(buffered_DDR_DQ),
+        .DDRDQSN(buffered_DDR_DQS_n),
+        .DDRDQSP(buffered_DDR_DQS),
+        .DDRDRSTB(buffered_DDR_DRSTB),
+        .DDRODT(buffered_DDR_ODT),
+        .DDRRASB(buffered_DDR_RAS_n),
+        .DDRVRN(buffered_DDR_VRN),
+        .DDRVRP(buffered_DDR_VRP),
+        .DDRWEB(buffered_DDR_WEB),
+        .DMA0ACLK(DMA0_ACLK),
+        .DMA0DAREADY(DMA0_DAREADY),
+        .DMA0DATYPE(DMA0_DATYPE),
+        .DMA0DAVALID(DMA0_DAVALID),
+        .DMA0DRLAST(DMA0_DRLAST),
+        .DMA0DRREADY(DMA0_DRREADY),
+        .DMA0DRTYPE(DMA0_DRTYPE),
+        .DMA0DRVALID(DMA0_DRVALID),
+        .DMA0RSTN(DMA0_RSTN),
+        .DMA1ACLK(DMA1_ACLK),
+        .DMA1DAREADY(DMA1_DAREADY),
+        .DMA1DATYPE(DMA1_DATYPE),
+        .DMA1DAVALID(DMA1_DAVALID),
+        .DMA1DRLAST(DMA1_DRLAST),
+        .DMA1DRREADY(DMA1_DRREADY),
+        .DMA1DRTYPE(DMA1_DRTYPE),
+        .DMA1DRVALID(DMA1_DRVALID),
+        .DMA1RSTN(DMA1_RSTN),
+        .DMA2ACLK(DMA2_ACLK),
+        .DMA2DAREADY(DMA2_DAREADY),
+        .DMA2DATYPE(DMA2_DATYPE),
+        .DMA2DAVALID(DMA2_DAVALID),
+        .DMA2DRLAST(DMA2_DRLAST),
+        .DMA2DRREADY(DMA2_DRREADY),
+        .DMA2DRTYPE(DMA2_DRTYPE),
+        .DMA2DRVALID(DMA2_DRVALID),
+        .DMA2RSTN(DMA2_RSTN),
+        .DMA3ACLK(DMA3_ACLK),
+        .DMA3DAREADY(DMA3_DAREADY),
+        .DMA3DATYPE(DMA3_DATYPE),
+        .DMA3DAVALID(DMA3_DAVALID),
+        .DMA3DRLAST(DMA3_DRLAST),
+        .DMA3DRREADY(DMA3_DRREADY),
+        .DMA3DRTYPE(DMA3_DRTYPE),
+        .DMA3DRVALID(DMA3_DRVALID),
+        .DMA3RSTN(DMA3_RSTN),
+        .EMIOCAN0PHYRX(CAN0_PHY_RX),
+        .EMIOCAN0PHYTX(CAN0_PHY_TX),
+        .EMIOCAN1PHYRX(CAN1_PHY_RX),
+        .EMIOCAN1PHYTX(CAN1_PHY_TX),
+        .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+        .EMIOENET0GMIICOL(1\'b0),
+        .EMIOENET0GMIICRS(1\'b0),
+        .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+        .EMIOENET0GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET0GMIIRXDV(1\'b0),
+        .EMIOENET0GMIIRXER(1\'b0),
+        .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+        .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+        .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+        .EMIOENET0MDIOI(ENET0_MDIO_I),
+        .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+        .EMIOENET0MDIOO(ENET0_MDIO_O),
+        .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+        .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+        .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+        .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+        .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+        .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+        .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+        .EMIOENET0SOFRX(ENET0_SOF_RX),
+        .EMIOENET0SOFTX(ENET0_SOF_TX),
+        .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+        .EMIOENET1GMIICOL(1\'b0),
+        .EMIOENET1GMIICRS(1\'b0),
+        .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+        .EMIOENET1GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET1GMIIRXDV(1\'b0),
+        .EMIOENET1GMIIRXER(1\'b0),
+        .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+        .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+        .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+        .EMIOENET1MDIOI(ENET1_MDIO_I),
+        .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+        .EMIOENET1MDIOO(ENET1_MDIO_O),
+        .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+        .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+        .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+        .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+        .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+        .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+        .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+        .EMIOENET1SOFRX(ENET1_SOF_RX),
+        .EMIOENET1SOFTX(ENET1_SOF_TX),
+        .EMIOGPIOI(GPIO_I),
+        .EMIOGPIOO(GPIO_O),
+        .EMIOGPIOTN(gpio_out_t_n),
+        .EMIOI2C0SCLI(I2C0_SCL_I),
+        .EMIOI2C0SCLO(I2C0_SCL_O),
+        .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+        .EMIOI2C0SDAI(I2C0_SDA_I),
+        .EMIOI2C0SDAO(I2C0_SDA_O),
+        .EMIOI2C0SDATN(I2C0_SDA_T_n),
+        .EMIOI2C1SCLI(I2C1_SCL_I),
+        .EMIOI2C1SCLO(I2C1_SCL_O),
+        .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+        .EMIOI2C1SDAI(I2C1_SDA_I),
+        .EMIOI2C1SDAO(I2C1_SDA_O),
+        .EMIOI2C1SDATN(I2C1_SDA_T_n),
+        .EMIOPJTAGTCK(PJTAG_TCK),
+        .EMIOPJTAGTDI(PJTAG_TDI),
+        .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+        .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+        .EMIOPJTAGTMS(PJTAG_TMS),
+        .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+        .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+        .EMIOSDIO0CDN(SDIO0_CDN),
+        .EMIOSDIO0CLK(SDIO0_CLK),
+        .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+        .EMIOSDIO0CMDI(SDIO0_CMD_I),
+        .EMIOSDIO0CMDO(SDIO0_CMD_O),
+        .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+        .EMIOSDIO0DATAI(SDIO0_DATA_I),
+        .EMIOSDIO0DATAO(SDIO0_DATA_O),
+        .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+        .EMIOSDIO0LED(SDIO0_LED),
+        .EMIOSDIO0WP(SDIO0_WP),
+        .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+        .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+        .EMIOSDIO1CDN(SDIO1_CDN),
+        .EMIOSDIO1CLK(SDIO1_CLK),
+        .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+        .EMIOSDIO1CMDI(SDIO1_CMD_I),
+        .EMIOSDIO1CMDO(SDIO1_CMD_O),
+        .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+        .EMIOSDIO1DATAI(SDIO1_DATA_I),
+        .EMIOSDIO1DATAO(SDIO1_DATA_O),
+        .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+        .EMIOSDIO1LED(SDIO1_LED),
+        .EMIOSDIO1WP(SDIO1_WP),
+        .EMIOSPI0MI(SPI0_MISO_I),
+        .EMIOSPI0MO(SPI0_MOSI_O),
+        .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+        .EMIOSPI0SCLKI(SPI0_SCLK_I),
+        .EMIOSPI0SCLKO(SPI0_SCLK_O),
+        .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+        .EMIOSPI0SI(SPI0_MOSI_I),
+        .EMIOSPI0SO(SPI0_MISO_O),
+        .EMIOSPI0SSIN(SPI0_SS_I),
+        .EMIOSPI0SSNTN(SPI0_SS_T_n),
+        .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+        .EMIOSPI0STN(SPI0_MISO_T_n),
+        .EMIOSPI1MI(SPI1_MISO_I),
+        .EMIOSPI1MO(SPI1_MOSI_O),
+        .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+        .EMIOSPI1SCLKI(SPI1_SCLK_I),
+        .EMIOSPI1SCLKO(SPI1_SCLK_O),
+        .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+        .EMIOSPI1SI(SPI1_MOSI_I),
+        .EMIOSPI1SO(SPI1_MISO_O),
+        .EMIOSPI1SSIN(SPI1_SS_I),
+        .EMIOSPI1SSNTN(SPI1_SS_T_n),
+        .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+        .EMIOSPI1STN(SPI1_MISO_T_n),
+        .EMIOSRAMINTIN(SRAM_INTIN),
+        .EMIOTRACECLK(TRACE_CLK),
+        .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+        .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+        .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+        .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+        .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+        .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+        .EMIOUART0CTSN(UART0_CTSN),
+        .EMIOUART0DCDN(UART0_DCDN),
+        .EMIOUART0DSRN(UART0_DSRN),
+        .EMIOUART0DTRN(UART0_DTRN),
+        .EMIOUART0RIN(UART0_RIN),
+        .EMIOUART0RTSN(UART0_RTSN),
+        .EMIOUART0RX(UART0_RX),
+        .EMIOUART0TX(UART0_TX),
+        .EMIOUART1CTSN(UART1_CTSN),
+        .EMIOUART1DCDN(UART1_DCDN),
+        .EMIOUART1DSRN(UART1_DSRN),
+        .EMIOUART1DTRN(UART1_DTRN),
+        .EMIOUART1RIN(UART1_RIN),
+        .EMIOUART1RTSN(UART1_RTSN),
+        .EMIOUART1RX(UART1_RX),
+        .EMIOUART1TX(UART1_TX),
+        .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+        .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+        .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+        .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+        .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+        .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+        .EMIOWDTCLKI(WDT_CLK_IN),
+        .EMIOWDTRSTO(WDT_RST_OUT),
+        .EVENTEVENTI(EVENT_EVENTI),
+        .EVENTEVENTO(EVENT_EVENTO),
+        .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+        .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+        .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+        .FCLKCLKTRIGN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+        .FPGAIDLEN(FPGA_IDLE_N),
+        .FTMDTRACEINATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+        .FTMDTRACEINDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINVALID(1\'b0),
+        .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+        .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+        .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+        .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+        .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+        .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+        .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,IRQ_F2P}),
+        .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+        .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+        .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+        .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+        .MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
+        .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+        .MAXIGP0ARID(M_AXI_GP0_ARID),
+        .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+        .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+        .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+        .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+        .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+        .MAXIGP0ARSIZE(\\^M_AXI_GP0_ARSIZE ),
+        .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+        .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+        .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+        .MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
+        .MAXIGP0AWID(M_AXI_GP0_AWID),
+        .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+        .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+        .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+        .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+        .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+        .MAXIGP0AWSIZE(\\^M_AXI_GP0_AWSIZE ),
+        .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+        .MAXIGP0BID(M_AXI_GP0_BID),
+        .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+        .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+        .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+        .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+        .MAXIGP0RID(M_AXI_GP0_RID),
+        .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+        .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+        .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+        .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+        .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+        .MAXIGP0WID(M_AXI_GP0_WID),
+        .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+        .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+        .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+        .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+        .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+        .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+        .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+        .MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
+        .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+        .MAXIGP1ARID(M_AXI_GP1_ARID),
+        .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+        .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+        .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+        .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+        .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+        .MAXIGP1ARSIZE(\\^M_AXI_GP1_ARSIZE ),
+        .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+        .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+        .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+        .MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
+        .MAXIGP1AWID(M_AXI_GP1_AWID),
+        .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+        .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+        .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+        .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+        .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+        .MAXIGP1AWSIZE(\\^M_AXI_GP1_AWSIZE ),
+        .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+        .MAXIGP1BID(M_AXI_GP1_BID),
+        .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+        .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+        .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+        .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+        .MAXIGP1RID(M_AXI_GP1_RID),
+        .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+        .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+        .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+        .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+        .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+        .MAXIGP1WID(M_AXI_GP1_WID),
+        .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+        .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+        .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+        .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+        .MIO(buffered_MIO),
+        .PSCLK(buffered_PS_CLK),
+        .PSPORB(buffered_PS_PORB),
+        .PSSRSTB(buffered_PS_SRSTB),
+        .SAXIACPACLK(S_AXI_ACP_ACLK),
+        .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+        .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+        .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+        .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+        .SAXIACPARID(S_AXI_ACP_ARID),
+        .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+        .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+        .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+        .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+        .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+        .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+        .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+        .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+        .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+        .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+        .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+        .SAXIACPAWID(S_AXI_ACP_AWID),
+        .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+        .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+        .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+        .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+        .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+        .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+        .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+        .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+        .SAXIACPBID(S_AXI_ACP_BID),
+        .SAXIACPBREADY(S_AXI_ACP_BREADY),
+        .SAXIACPBRESP(S_AXI_ACP_BRESP),
+        .SAXIACPBVALID(S_AXI_ACP_BVALID),
+        .SAXIACPRDATA(S_AXI_ACP_RDATA),
+        .SAXIACPRID(S_AXI_ACP_RID),
+        .SAXIACPRLAST(S_AXI_ACP_RLAST),
+        .SAXIACPRREADY(S_AXI_ACP_RREADY),
+        .SAXIACPRRESP(S_AXI_ACP_RRESP),
+        .SAXIACPRVALID(S_AXI_ACP_RVALID),
+        .SAXIACPWDATA(S_AXI_ACP_WDATA),
+        .SAXIACPWID(S_AXI_ACP_WID),
+        .SAXIACPWLAST(S_AXI_ACP_WLAST),
+        .SAXIACPWREADY(S_AXI_ACP_WREADY),
+        .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+        .SAXIACPWVALID(S_AXI_ACP_WVALID),
+        .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+        .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+        .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+        .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+        .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+        .SAXIGP0ARID(S_AXI_GP0_ARID),
+        .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+        .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+        .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+        .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+        .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+        .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+        .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+        .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+        .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+        .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+        .SAXIGP0AWID(S_AXI_GP0_AWID),
+        .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+        .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+        .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+        .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+        .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+        .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+        .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+        .SAXIGP0BID(S_AXI_GP0_BID),
+        .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+        .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+        .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+        .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+        .SAXIGP0RID(S_AXI_GP0_RID),
+        .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+        .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+        .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+        .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+        .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+        .SAXIGP0WID(S_AXI_GP0_WID),
+        .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+        .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+        .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+        .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+        .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+        .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+        .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+        .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+        .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+        .SAXIGP1ARID(S_AXI_GP1_ARID),
+        .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+        .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+        .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+        .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+        .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+        .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+        .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+        .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+        .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+        .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+        .SAXIGP1AWID(S_AXI_GP1_AWID),
+        .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+        .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+        .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+        .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+        .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+        .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+        .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+        .SAXIGP1BID(S_AXI_GP1_BID),
+        .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+        .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+        .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+        .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+        .SAXIGP1RID(S_AXI_GP1_RID),
+        .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+        .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+        .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+        .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+        .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+        .SAXIGP1WID(S_AXI_GP1_WID),
+        .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+        .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+        .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+        .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+        .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+        .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+        .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+        .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+        .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+        .SAXIHP0ARID(S_AXI_HP0_ARID),
+        .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+        .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+        .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+        .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+        .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+        .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+        .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+        .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+        .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+        .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+        .SAXIHP0AWID(S_AXI_HP0_AWID),
+        .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+        .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+        .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+        .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+        .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+        .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+        .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+        .SAXIHP0BID(S_AXI_HP0_BID),
+        .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+        .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+        .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+        .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+        .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+        .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+        .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+        .SAXIHP0RID(S_AXI_HP0_RID),
+        .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+        .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+        .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+        .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+        .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+        .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+        .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+        .SAXIHP0WID(S_AXI_HP0_WID),
+        .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+        .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+        .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+        .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+        .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+        .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+        .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+        .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+        .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+        .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+        .SAXIHP1ARID(S_AXI_HP1_ARID),
+        .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+        .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+        .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+        .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+        .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+        .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+        .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+        .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+        .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+        .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+        .SAXIHP1AWID(S_AXI_HP1_AWID),
+        .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+        .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+        .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+        .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+        .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+        .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+        .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+        .SAXIHP1BID(S_AXI_HP1_BID),
+        .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+        .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+        .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+        .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+        .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+        .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+        .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+        .SAXIHP1RID(S_AXI_HP1_RID),
+        .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+        .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+        .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+        .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+        .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+        .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+        .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+        .SAXIHP1WID(S_AXI_HP1_WID),
+        .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+        .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+        .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+        .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+        .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+        .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+        .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+        .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+        .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+        .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+        .SAXIHP2ARID(S_AXI_HP2_ARID),
+        .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+        .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+        .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+        .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+        .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+        .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+        .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+        .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+        .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+        .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+        .SAXIHP2AWID(S_AXI_HP2_AWID),
+        .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+        .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+        .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+        .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+        .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+        .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+        .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+        .SAXIHP2BID(S_AXI_HP2_BID),
+        .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+        .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+        .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+        .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+        .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+        .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+        .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+        .SAXIHP2RID(S_AXI_HP2_RID),
+        .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+        .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+        .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+        .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+        .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+        .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+        .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+        .SAXIHP2WID(S_AXI_HP2_WID),
+        .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+        .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+        .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+        .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+        .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+        .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+        .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+        .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+        .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+        .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+        .SAXIHP3ARID(S_AXI_HP3_ARID),
+        .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+        .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+        .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+        .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+        .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+        .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+        .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+        .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+        .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+        .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+        .SAXIHP3AWID(S_AXI_HP3_AWID),
+        .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+        .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+        .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+        .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+        .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+        .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+        .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+        .SAXIHP3BID(S_AXI_HP3_BID),
+        .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+        .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+        .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+        .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+        .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+        .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+        .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+        .SAXIHP3RID(S_AXI_HP3_RID),
+        .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+        .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+        .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+        .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+        .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+        .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+        .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+        .SAXIHP3WID(S_AXI_HP3_WID),
+        .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+        .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+        .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+        .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+        .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_CLK_BIBUF
+       (.IO(buffered_PS_CLK),
+        .PAD(PS_CLK));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_PORB_BIBUF
+       (.IO(buffered_PS_PORB),
+        .PAD(PS_PORB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_SRSTB_BIBUF
+       (.IO(buffered_PS_SRSTB),
+        .PAD(PS_SRSTB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO0_CMD_T_INST_0
+       (.I0(SDIO0_CMD_T_n),
+        .O(SDIO0_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[0]_INST_0 
+       (.I0(SDIO0_DATA_T_n[0]),
+        .O(SDIO0_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[1]_INST_0 
+       (.I0(SDIO0_DATA_T_n[1]),
+        .O(SDIO0_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[2]_INST_0 
+       (.I0(SDIO0_DATA_T_n[2]),
+        .O(SDIO0_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[3]_INST_0 
+       (.I0(SDIO0_DATA_T_n[3]),
+        .O(SDIO0_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO1_CMD_T_INST_0
+       (.I0(SDIO1_CMD_T_n),
+        .O(SDIO1_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[0]_INST_0 
+       (.I0(SDIO1_DATA_T_n[0]),
+        .O(SDIO1_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[1]_INST_0 
+       (.I0(SDIO1_DATA_T_n[1]),
+        .O(SDIO1_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[2]_INST_0 
+       (.I0(SDIO1_DATA_T_n[2]),
+        .O(SDIO1_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[3]_INST_0 
+       (.I0(SDIO1_DATA_T_n[3]),
+        .O(SDIO1_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MISO_T_INST_0
+       (.I0(SPI0_MISO_T_n),
+        .O(SPI0_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MOSI_T_INST_0
+       (.I0(SPI0_MOSI_T_n),
+        .O(SPI0_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SCLK_T_INST_0
+       (.I0(SPI0_SCLK_T_n),
+        .O(SPI0_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SS_T_INST_0
+       (.I0(SPI0_SS_T_n),
+        .O(SPI0_SS_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MISO_T_INST_0
+       (.I0(SPI1_MISO_T_n),
+        .O(SPI1_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MOSI_T_INST_0
+       (.I0(SPI1_MOSI_T_n),
+        .O(SPI1_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SCLK_T_INST_0
+       (.I0(SPI1_SCLK_T_n),
+        .O(SPI1_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SS_T_INST_0
+       (.I0(SPI1_SS_T_n),
+        .O(SPI1_SS_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BUFG \\buffer_fclk_clk_0.FCLK_CLK_0_BUFG 
+       (.I(FCLK_CLK_unbuffered),
+        .O(FCLK_CLK0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[0].MIO_BIBUF 
+       (.IO(buffered_MIO[0]),
+        .PAD(MIO[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[10].MIO_BIBUF 
+       (.IO(buffered_MIO[10]),
+        .PAD(MIO[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[11].MIO_BIBUF 
+       (.IO(buffered_MIO[11]),
+        .PAD(MIO[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[12].MIO_BIBUF 
+       (.IO(buffered_MIO[12]),
+        .PAD(MIO[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[13].MIO_BIBUF 
+       (.IO(buffered_MIO[13]),
+        .PAD(MIO[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[14].MIO_BIBUF 
+       (.IO(buffered_MIO[14]),
+        .PAD(MIO[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[15].MIO_BIBUF 
+       (.IO(buffered_MIO[15]),
+        .PAD(MIO[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[16].MIO_BIBUF 
+       (.IO(buffered_MIO[16]),
+        .PAD(MIO[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[17].MIO_BIBUF 
+       (.IO(buffered_MIO[17]),
+        .PAD(MIO[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[18].MIO_BIBUF 
+       (.IO(buffered_MIO[18]),
+        .PAD(MIO[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[19].MIO_BIBUF 
+       (.IO(buffered_MIO[19]),
+        .PAD(MIO[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[1].MIO_BIBUF 
+       (.IO(buffered_MIO[1]),
+        .PAD(MIO[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[20].MIO_BIBUF 
+       (.IO(buffered_MIO[20]),
+        .PAD(MIO[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[21].MIO_BIBUF 
+       (.IO(buffered_MIO[21]),
+        .PAD(MIO[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[22].MIO_BIBUF 
+       (.IO(buffered_MIO[22]),
+        .PAD(MIO[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[23].MIO_BIBUF 
+       (.IO(buffered_MIO[23]),
+        .PAD(MIO[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[24].MIO_BIBUF 
+       (.IO(buffered_MIO[24]),
+        .PAD(MIO[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[25].MIO_BIBUF 
+       (.IO(buffered_MIO[25]),
+        .PAD(MIO[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[26].MIO_BIBUF 
+       (.IO(buffered_MIO[26]),
+        .PAD(MIO[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[27].MIO_BIBUF 
+       (.IO(buffered_MIO[27]),
+        .PAD(MIO[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[28].MIO_BIBUF 
+       (.IO(buffered_MIO[28]),
+        .PAD(MIO[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[29].MIO_BIBUF 
+       (.IO(buffered_MIO[29]),
+        .PAD(MIO[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[2].MIO_BIBUF 
+       (.IO(buffered_MIO[2]),
+        .PAD(MIO[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[30].MIO_BIBUF 
+       (.IO(buffered_MIO[30]),
+        .PAD(MIO[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[31].MIO_BIBUF 
+       (.IO(buffered_MIO[31]),
+        .PAD(MIO[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[32].MIO_BIBUF 
+       (.IO(buffered_MIO[32]),
+        .PAD(MIO[32]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[33].MIO_BIBUF 
+       (.IO(buffered_MIO[33]),
+        .PAD(MIO[33]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[34].MIO_BIBUF 
+       (.IO(buffered_MIO[34]),
+        .PAD(MIO[34]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[35].MIO_BIBUF 
+       (.IO(buffered_MIO[35]),
+        .PAD(MIO[35]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[36].MIO_BIBUF 
+       (.IO(buffered_MIO[36]),
+        .PAD(MIO[36]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[37].MIO_BIBUF 
+       (.IO(buffered_MIO[37]),
+        .PAD(MIO[37]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[38].MIO_BIBUF 
+       (.IO(buffered_MIO[38]),
+        .PAD(MIO[38]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[39].MIO_BIBUF 
+       (.IO(buffered_MIO[39]),
+        .PAD(MIO[39]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[3].MIO_BIBUF 
+       (.IO(buffered_MIO[3]),
+        .PAD(MIO[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[40].MIO_BIBUF 
+       (.IO(buffered_MIO[40]),
+        .PAD(MIO[40]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[41].MIO_BIBUF 
+       (.IO(buffered_MIO[41]),
+        .PAD(MIO[41]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[42].MIO_BIBUF 
+       (.IO(buffered_MIO[42]),
+        .PAD(MIO[42]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[43].MIO_BIBUF 
+       (.IO(buffered_MIO[43]),
+        .PAD(MIO[43]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[44].MIO_BIBUF 
+       (.IO(buffered_MIO[44]),
+        .PAD(MIO[44]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[45].MIO_BIBUF 
+       (.IO(buffered_MIO[45]),
+        .PAD(MIO[45]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[46].MIO_BIBUF 
+       (.IO(buffered_MIO[46]),
+        .PAD(MIO[46]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[47].MIO_BIBUF 
+       (.IO(buffered_MIO[47]),
+        .PAD(MIO[47]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[48].MIO_BIBUF 
+       (.IO(buffered_MIO[48]),
+        .PAD(MIO[48]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[49].MIO_BIBUF 
+       (.IO(buffered_MIO[49]),
+        .PAD(MIO[49]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[4].MIO_BIBUF 
+       (.IO(buffered_MIO[4]),
+        .PAD(MIO[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[50].MIO_BIBUF 
+       (.IO(buffered_MIO[50]),
+        .PAD(MIO[50]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[51].MIO_BIBUF 
+       (.IO(buffered_MIO[51]),
+        .PAD(MIO[51]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[52].MIO_BIBUF 
+       (.IO(buffered_MIO[52]),
+        .PAD(MIO[52]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[53].MIO_BIBUF 
+       (.IO(buffered_MIO[53]),
+        .PAD(MIO[53]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[5].MIO_BIBUF 
+       (.IO(buffered_MIO[5]),
+        .PAD(MIO[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[6].MIO_BIBUF 
+       (.IO(buffered_MIO[6]),
+        .PAD(MIO[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[7].MIO_BIBUF 
+       (.IO(buffered_MIO[7]),
+        .PAD(MIO[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[8].MIO_BIBUF 
+       (.IO(buffered_MIO[8]),
+        .PAD(MIO[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[9].MIO_BIBUF 
+       (.IO(buffered_MIO[9]),
+        .PAD(MIO[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[0].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[0]),
+        .PAD(DDR_BankAddr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[1].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[1]),
+        .PAD(DDR_BankAddr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[2].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[2]),
+        .PAD(DDR_BankAddr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[0].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[0]),
+        .PAD(DDR_Addr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[10].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[10]),
+        .PAD(DDR_Addr[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[11].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[11]),
+        .PAD(DDR_Addr[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[12].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[12]),
+        .PAD(DDR_Addr[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[13].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[13]),
+        .PAD(DDR_Addr[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[14].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[14]),
+        .PAD(DDR_Addr[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[1].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[1]),
+        .PAD(DDR_Addr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[2].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[2]),
+        .PAD(DDR_Addr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[3].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[3]),
+        .PAD(DDR_Addr[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[4].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[4]),
+        .PAD(DDR_Addr[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[5].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[5]),
+        .PAD(DDR_Addr[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[6].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[6]),
+        .PAD(DDR_Addr[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[7].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[7]),
+        .PAD(DDR_Addr[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[8].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[8]),
+        .PAD(DDR_Addr[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[9].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[9]),
+        .PAD(DDR_Addr[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[0].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[0]),
+        .PAD(DDR_DM[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[1].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[1]),
+        .PAD(DDR_DM[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[2].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[2]),
+        .PAD(DDR_DM[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[3].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[3]),
+        .PAD(DDR_DM[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[0].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[0]),
+        .PAD(DDR_DQ[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[10].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[10]),
+        .PAD(DDR_DQ[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[11].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[11]),
+        .PAD(DDR_DQ[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[12].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[12]),
+        .PAD(DDR_DQ[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[13].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[13]),
+        .PAD(DDR_DQ[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[14].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[14]),
+        .PAD(DDR_DQ[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[15].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[15]),
+        .PAD(DDR_DQ[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[16].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[16]),
+        .PAD(DDR_DQ[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[17].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[17]),
+        .PAD(DDR_DQ[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[18].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[18]),
+        .PAD(DDR_DQ[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[19].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[19]),
+        .PAD(DDR_DQ[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[1].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[1]),
+        .PAD(DDR_DQ[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[20].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[20]),
+        .PAD(DDR_DQ[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[21].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[21]),
+        .PAD(DDR_DQ[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[22].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[22]),
+        .PAD(DDR_DQ[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[23].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[23]),
+        .PAD(DDR_DQ[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[24].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[24]),
+        .PAD(DDR_DQ[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[25].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[25]),
+        .PAD(DDR_DQ[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[26].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[26]),
+        .PAD(DDR_DQ[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[27].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[27]),
+        .PAD(DDR_DQ[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[28].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[28]),
+        .PAD(DDR_DQ[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[29].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[29]),
+        .PAD(DDR_DQ[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[2].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[2]),
+        .PAD(DDR_DQ[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[30].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[30]),
+        .PAD(DDR_DQ[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[31].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[31]),
+        .PAD(DDR_DQ[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[3].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[3]),
+        .PAD(DDR_DQ[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[4].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[4]),
+        .PAD(DDR_DQ[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[5].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[5]),
+        .PAD(DDR_DQ[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[6].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[6]),
+        .PAD(DDR_DQ[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[7].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[7]),
+        .PAD(DDR_DQ[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[8].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[8]),
+        .PAD(DDR_DQ[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[9].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[9]),
+        .PAD(DDR_DQ[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[0].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[0]),
+        .PAD(DDR_DQS_n[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[1].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[1]),
+        .PAD(DDR_DQS_n[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[2].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[2]),
+        .PAD(DDR_DQS_n[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[3].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[3]),
+        .PAD(DDR_DQS_n[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[0].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[0]),
+        .PAD(DDR_DQS[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[1].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[1]),
+        .PAD(DDR_DQS[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[2].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[2]),
+        .PAD(DDR_DQS[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[3].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[3]),
+        .PAD(DDR_DQS[3]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_0
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[0] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_1
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_10
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_11
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_12
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_13
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_14
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_15
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_16
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_17
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_18
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_19
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_2
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_20
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_21
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_22
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_23
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_3
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[7] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_4
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[6] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_5
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[5] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_6
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[4] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_7
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[3] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_8
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[2] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_9
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_reg_init.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Initialize register default values.
+ *
+ *****************************************************************************/
+
+// Register default value info for chip pele_ps
+// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012
+// 54 modules, 2532 registers.
+
+
+// ************************************************************
+//   Module afi0 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL);
+set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP);
+set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS);
+set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL);
+set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG);
+set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL);
+set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP);
+set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS);
+set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL);
+set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG);
+
+// ************************************************************
+//   Module afi1 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL);
+set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP);
+set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS);
+set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL);
+set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG);
+set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL);
+set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP);
+set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS);
+set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL);
+set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG);
+
+// ************************************************************
+//   Module afi2 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL);
+set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP);
+set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS);
+set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL);
+set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG);
+set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL);
+set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP);
+set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS);
+set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL);
+set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG);
+
+// ************************************************************
+//   Module afi3 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL);
+set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP);
+set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS);
+set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL);
+set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG);
+set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL);
+set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP);
+set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS);
+set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL);
+set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG);
+
+// ************************************************************
+//   Module can0 can
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( can0__SRR, val_can0__SRR);
+set_reset_data( can0__MSR, val_can0__MSR);
+set_reset_data( can0__BRPR, val_can0__BRPR);
+set_reset_data( can0__BTR, val_can0__BTR);
+set_reset_data( can0__ECR, val_can0__ECR);
+set_reset_data( can0__ESR, val_can0__ESR);
+set_reset_data( can0__SR, val_can0__SR);
+set_reset_data( can0__ISR, val_can0__ISR);
+set_reset_data( can0__IER, val_can0__IER);
+set_reset_data( can0__ICR, val_can0__ICR);
+set_reset_data( can0__TCR, val_can0__TCR);
+set_reset_data( can0__WIR, val_can0__WIR);
+set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID);
+set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC);
+set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1);
+set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2);
+set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID);
+set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC);
+set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1);
+set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2);
+set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID);
+set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC);
+set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1);
+set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2);
+set_reset_data( can0__AFR, val_can0__AFR);
+set_reset_data( can0__AFMR1, val_can0__AFMR1);
+set_reset_data( can0__AFIR1, val_can0__AFIR1);
+set_reset_data( can0__AFMR2, val_can0__AFMR2);
+set_reset_data( can0__AFIR2, val_can0__AFIR2);
+set_reset_data( can0__AFMR3, val_can0__AFMR3);
+set_reset_data( can0__AFIR3, val_can0__AFIR3);
+set_reset_data( can0__AFMR4, val_can0__AFMR4);
+set_reset_data( can0__AFIR4, val_can0__AFIR4);
+
+// ************************************************************
+//   Module can1 can
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( can1__SRR, val_can1__SRR);
+set_reset_data( can1__MSR, val_can1__MSR);
+set_reset_data( can1__BRPR, val_can1__BRPR);
+set_reset_data( can1__BTR, val_can1__BTR);
+set_reset_data( can1__ECR, val_can1__ECR);
+set_reset_data( can1__ESR, val_can1__ESR);
+set_reset_data( can1__SR, val_can1__SR);
+set_reset_data( can1__ISR, val_can1__ISR);
+set_reset_data( can1__IER, val_can1__IER);
+set_reset_data( can1__ICR, val_can1__ICR);
+set_reset_data( can1__TCR, val_can1__TCR);
+set_reset_data( can1__WIR, val_can1__WIR);
+set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID);
+set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC);
+set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1);
+set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2);
+set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID);
+set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC);
+set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1);
+set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2);
+set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID);
+set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC);
+set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1);
+set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2);
+set_reset_data( can1__AFR, val_can1__AFR);
+set_reset_data( can1__AFMR1, val_can1__AFMR1);
+set_reset_data( can1__AFIR1, val_can1__AFIR1);
+set_reset_data( can1__AFMR2, val_can1__AFMR2);
+set_reset_data( can1__AFIR2, val_can1__AFIR2);
+set_reset_data( can1__AFMR3, val_can1__AFMR3);
+set_reset_data( can1__AFIR3, val_can1__AFIR3);
+set_reset_data( can1__AFMR4, val_can1__AFMR4);
+set_reset_data( can1__AFIR4, val_can1__AFIR4);
+
+// ************************************************************
+//   Module ddrc ddrc
+//   doc version: 1.25
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl);
+set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg);
+set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg);
+set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg);
+set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg);
+set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0);
+set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1);
+set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2);
+set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3);
+set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4);
+set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param);
+set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg);
+set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg);
+set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr);
+set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ);
+set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank);
+set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col);
+set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row);
+set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg);
+set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg);
+set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt);
+set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg);
+set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib);
+set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold);
+set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1);
+set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2);
+set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3);
+set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4);
+set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5);
+set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6);
+set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01);
+set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ);
+set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg);
+set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg);
+set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c);
+set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d);
+set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing);
+set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2);
+set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing);
+set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET);
+set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET);
+set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub);
+set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET);
+set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET);
+set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable);
+set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0);
+set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1);
+set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2);
+set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3);
+set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0);
+set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1);
+set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2);
+set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3);
+set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0);
+set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1);
+set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2);
+set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3);
+set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0);
+set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1);
+set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2);
+set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3);
+set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0);
+set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1);
+set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2);
+set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3);
+set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0);
+set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1);
+set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2);
+set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3);
+set_reset_data( ddrc__reg_64, val_ddrc__reg_64);
+set_reset_data( ddrc__reg_65, val_ddrc__reg_65);
+set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0);
+set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1);
+set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2);
+set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3);
+set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710);
+set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711);
+set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712);
+set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713);
+set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0);
+set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1);
+set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2);
+set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3);
+set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts);
+set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts);
+set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2);
+set_reset_data( ddrc__axi_id, val_ddrc__axi_id);
+set_reset_data( ddrc__page_mask, val_ddrc__page_mask);
+set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0);
+set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1);
+set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2);
+set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3);
+set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0);
+set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1);
+set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2);
+set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3);
+set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0);
+set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1);
+set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2);
+set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3);
+set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0);
+set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1);
+set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2);
+set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3);
+set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20);
+set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21);
+set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22);
+set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23);
+set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30);
+set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31);
+set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32);
+set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33);
+set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg);
+set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0);
+set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1);
+set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2);
+set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3);
+set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read);
+set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0);
+set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1);
+set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2);
+set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3);
+set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm);
+set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm);
+set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm);
+
+// ************************************************************
+//   Module debug_axim axim
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL);
+set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS);
+set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL);
+set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL);
+set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS);
+set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL);
+set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL);
+set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH);
+set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT);
+set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER);
+set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT);
+set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD);
+set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT);
+set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK);
+set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER);
+set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER);
+set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC);
+set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK);
+set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER);
+set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER);
+set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC);
+set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK);
+set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER);
+set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER);
+set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC);
+set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK);
+set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER);
+set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER);
+set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC);
+set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK);
+set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER);
+set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER);
+set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC);
+set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK);
+set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER);
+set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER);
+set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC);
+set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK);
+set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER);
+set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER);
+set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC);
+set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK);
+set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER);
+set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER);
+set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC);
+set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL);
+set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT);
+set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK);
+set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN);
+set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK);
+set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA);
+set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS);
+set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1);
+set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0);
+set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL);
+set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET);
+set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR);
+set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS);
+set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS);
+set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS);
+set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID);
+set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE);
+set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4);
+set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5);
+set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6);
+set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7);
+set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0);
+set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1);
+set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2);
+set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3);
+set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0);
+set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1);
+set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2);
+set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3);
+
+// ************************************************************
+//   Module debug_cpu_cti0 cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL);
+set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK);
+set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET);
+set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR);
+set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE);
+set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0);
+set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1);
+set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2);
+set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3);
+set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4);
+set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5);
+set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6);
+set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7);
+set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0);
+set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1);
+set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2);
+set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3);
+set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4);
+set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5);
+set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6);
+set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7);
+set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS);
+set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS);
+set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS);
+set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS);
+set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE);
+set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL);
+set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK);
+set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK);
+set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT);
+set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT);
+set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK);
+set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK);
+set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN);
+set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN);
+set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL);
+set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR);
+set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR);
+set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR);
+set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR);
+set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR);
+set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID);
+set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR);
+set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4);
+set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5);
+set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6);
+set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7);
+set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0);
+set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1);
+set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2);
+set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3);
+set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0);
+set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1);
+set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2);
+set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3);
+
+// ************************************************************
+//   Module debug_cpu_cti1 cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL);
+set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK);
+set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET);
+set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR);
+set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE);
+set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0);
+set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1);
+set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2);
+set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3);
+set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4);
+set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5);
+set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6);
+set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7);
+set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0);
+set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1);
+set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2);
+set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3);
+set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4);
+set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5);
+set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6);
+set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7);
+set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS);
+set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS);
+set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS);
+set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS);
+set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE);
+set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL);
+set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK);
+set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK);
+set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT);
+set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT);
+set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK);
+set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK);
+set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN);
+set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN);
+set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL);
+set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR);
+set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR);
+set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR);
+set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR);
+set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR);
+set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID);
+set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR);
+set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4);
+set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5);
+set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6);
+set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7);
+set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0);
+set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1);
+set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2);
+set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3);
+set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0);
+set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1);
+set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2);
+set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3);
+
+// ************************************************************
+//   Module debug_cpu_pmu0 cortexa9_pmu
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5);
+set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5);
+set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET);
+set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR);
+set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET);
+set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR);
+set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR);
+set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC);
+set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR);
+set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR);
+
+// ************************************************************
+//   Module debug_cpu_pmu1 cortexa9_pmu
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5);
+set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5);
+set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET);
+set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR);
+set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET);
+set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR);
+set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR);
+set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC);
+set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR);
+set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR);
+
+// ************************************************************
+//   Module debug_cpu_ptm0 ptm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR);
+set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR);
+set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER);
+set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR);
+set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR);
+set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR);
+set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1);
+set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1);
+set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2);
+set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3);
+set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4);
+set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5);
+set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6);
+set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7);
+set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8);
+set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1);
+set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2);
+set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3);
+set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4);
+set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5);
+set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6);
+set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7);
+set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8);
+set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1);
+set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2);
+set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1);
+set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2);
+set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1);
+set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2);
+set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1);
+set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2);
+set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR);
+set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1);
+set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2);
+set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1);
+set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR);
+set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR);
+set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR);
+set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER);
+set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR);
+set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR);
+set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR);
+set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR);
+set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR);
+set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT);
+set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN);
+set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER);
+set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0);
+set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2);
+set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID);
+set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0);
+set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL);
+set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR);
+set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR);
+set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR);
+set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR);
+set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR);
+set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID);
+set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR);
+set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4);
+set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5);
+set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6);
+set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7);
+set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0);
+set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1);
+set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2);
+set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3);
+set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0);
+set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1);
+set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2);
+set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3);
+
+// ************************************************************
+//   Module debug_cpu_ptm1 ptm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR);
+set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR);
+set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER);
+set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR);
+set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR);
+set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR);
+set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1);
+set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1);
+set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2);
+set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3);
+set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4);
+set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5);
+set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6);
+set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7);
+set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8);
+set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1);
+set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2);
+set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3);
+set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4);
+set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5);
+set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6);
+set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7);
+set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8);
+set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1);
+set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2);
+set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1);
+set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2);
+set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1);
+set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2);
+set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1);
+set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2);
+set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR);
+set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1);
+set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2);
+set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1);
+set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR);
+set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR);
+set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR);
+set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER);
+set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR);
+set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR);
+set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR);
+set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR);
+set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR);
+set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT);
+set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN);
+set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER);
+set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0);
+set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2);
+set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID);
+set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0);
+set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL);
+set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR);
+set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR);
+set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR);
+set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR);
+set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR);
+set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID);
+set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR);
+set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4);
+set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5);
+set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6);
+set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7);
+set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0);
+set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1);
+set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2);
+set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3);
+set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0);
+set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1);
+set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2);
+set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3);
+
+// ************************************************************
+//   Module debug_cti_axim cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL);
+set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK);
+set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET);
+set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR);
+set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE);
+set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0);
+set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1);
+set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2);
+set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3);
+set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4);
+set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5);
+set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6);
+set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7);
+set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0);
+set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1);
+set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2);
+set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3);
+set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4);
+set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5);
+set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6);
+set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7);
+set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS);
+set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS);
+set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS);
+set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS);
+set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE);
+set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL);
+set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK);
+set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK);
+set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT);
+set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT);
+set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK);
+set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK);
+set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN);
+set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN);
+set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL);
+set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR);
+set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR);
+set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR);
+set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR);
+set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR);
+set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID);
+set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR);
+set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4);
+set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5);
+set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6);
+set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7);
+set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0);
+set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1);
+set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2);
+set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3);
+set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0);
+set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1);
+set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2);
+set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3);
+
+// ************************************************************
+//   Module debug_cti_etb_tpiu cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL);
+set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK);
+set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET);
+set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR);
+set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7);
+set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS);
+set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS);
+set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS);
+set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS);
+set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE);
+set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL);
+set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK);
+set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK);
+set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT);
+set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT);
+set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK);
+set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK);
+set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN);
+set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN);
+set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL);
+set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR);
+set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR);
+set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR);
+set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR);
+set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR);
+set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID);
+set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3);
+set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0);
+set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1);
+set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2);
+set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3);
+
+// ************************************************************
+//   Module debug_cti_ftm cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL);
+set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK);
+set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET);
+set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR);
+set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE);
+set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0);
+set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1);
+set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2);
+set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3);
+set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4);
+set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5);
+set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6);
+set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7);
+set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0);
+set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1);
+set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2);
+set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3);
+set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4);
+set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5);
+set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6);
+set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7);
+set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS);
+set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS);
+set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS);
+set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS);
+set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE);
+set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL);
+set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK);
+set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK);
+set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT);
+set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT);
+set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK);
+set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK);
+set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN);
+set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN);
+set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL);
+set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR);
+set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR);
+set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR);
+set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR);
+set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR);
+set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID);
+set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR);
+set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4);
+set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5);
+set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6);
+set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7);
+set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0);
+set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1);
+set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2);
+set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3);
+set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0);
+set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1);
+set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2);
+set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3);
+
+// ************************************************************
+//   Module debug_dap_rom dap
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00);
+set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01);
+set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02);
+set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03);
+set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04);
+set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05);
+set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06);
+set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07);
+set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08);
+set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09);
+set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10);
+set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11);
+set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12);
+set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13);
+set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14);
+set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15);
+set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4);
+set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5);
+set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6);
+set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7);
+set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0);
+set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1);
+set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2);
+set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3);
+set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0);
+set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1);
+set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2);
+set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3);
+
+// ************************************************************
+//   Module debug_etb etb
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_etb__RDP, val_debug_etb__RDP);
+set_reset_data( debug_etb__STS, val_debug_etb__STS);
+set_reset_data( debug_etb__RRD, val_debug_etb__RRD);
+set_reset_data( debug_etb__RRP, val_debug_etb__RRP);
+set_reset_data( debug_etb__RWP, val_debug_etb__RWP);
+set_reset_data( debug_etb__TRG, val_debug_etb__TRG);
+set_reset_data( debug_etb__CTL, val_debug_etb__CTL);
+set_reset_data( debug_etb__RWD, val_debug_etb__RWD);
+set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR);
+set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR);
+set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0);
+set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK);
+set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN);
+set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0);
+set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2);
+set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1);
+set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0);
+set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR);
+set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR);
+set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR);
+set_reset_data( debug_etb__LAR, val_debug_etb__LAR);
+set_reset_data( debug_etb__LSR, val_debug_etb__LSR);
+set_reset_data( debug_etb__ASR, val_debug_etb__ASR);
+set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID);
+set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR);
+set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4);
+set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5);
+set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6);
+set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7);
+set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0);
+set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1);
+set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2);
+set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3);
+set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0);
+set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1);
+set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2);
+set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3);
+
+// ************************************************************
+//   Module debug_ftm ftm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL);
+set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS);
+set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL);
+set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0);
+set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1);
+set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2);
+set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3);
+set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0);
+set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1);
+set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2);
+set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3);
+set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE);
+set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD);
+set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT);
+set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID);
+set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK);
+set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER);
+set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS);
+set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT);
+set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0);
+set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2);
+set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1);
+set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0);
+set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR);
+set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET);
+set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR);
+set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS);
+set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS);
+set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS);
+set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID);
+set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE);
+set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4);
+set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5);
+set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6);
+set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7);
+set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0);
+set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1);
+set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2);
+set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3);
+set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0);
+set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1);
+set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2);
+set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3);
+
+// ************************************************************
+//   Module debug_funnel funnel
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_funnel__Control, val_debug_funnel__Control);
+set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl);
+set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0);
+set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2);
+set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1);
+set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0);
+set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR);
+set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR);
+set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR);
+set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR);
+set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR);
+set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR);
+set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID);
+set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR);
+set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4);
+set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5);
+set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6);
+set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7);
+set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0);
+set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1);
+set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2);
+set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3);
+set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0);
+set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1);
+set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2);
+set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3);
+
+// ************************************************************
+//   Module debug_itm itm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00);
+set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01);
+set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02);
+set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03);
+set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04);
+set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05);
+set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06);
+set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07);
+set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08);
+set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09);
+set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10);
+set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11);
+set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12);
+set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13);
+set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14);
+set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15);
+set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16);
+set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17);
+set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18);
+set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19);
+set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20);
+set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21);
+set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22);
+set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23);
+set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24);
+set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25);
+set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26);
+set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27);
+set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28);
+set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29);
+set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30);
+set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31);
+set_reset_data( debug_itm__TER, val_debug_itm__TER);
+set_reset_data( debug_itm__TTR, val_debug_itm__TTR);
+set_reset_data( debug_itm__CR, val_debug_itm__CR);
+set_reset_data( debug_itm__SCR, val_debug_itm__SCR);
+set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK);
+set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT);
+set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0);
+set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2);
+set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1);
+set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0);
+set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR);
+set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR);
+set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR);
+set_reset_data( debug_itm__LAR, val_debug_itm__LAR);
+set_reset_data( debug_itm__LSR, val_debug_itm__LSR);
+set_reset_data( debug_itm__ASR, val_debug_itm__ASR);
+set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID);
+set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR);
+set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4);
+set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5);
+set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6);
+set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7);
+set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0);
+set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1);
+set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2);
+set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3);
+set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0);
+set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1);
+set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2);
+set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3);
+
+// ************************************************************
+//   Module debug_tpiu tpiu
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize);
+set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize);
+set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode);
+set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount);
+set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult);
+set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest);
+set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest);
+set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount);
+set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR);
+set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR);
+set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount);
+set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn);
+set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut);
+set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK);
+set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN);
+set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0);
+set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2);
+set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1);
+set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0);
+set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR);
+set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR);
+set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR);
+set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR);
+set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR);
+set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR);
+set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID);
+set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR);
+set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4);
+set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5);
+set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6);
+set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7);
+set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0);
+set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1);
+set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2);
+set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3);
+set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0);
+set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1);
+set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2);
+set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3);
+
+// ************************************************************
+//   Module devcfg devcfg
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( devcfg__CTRL, val_devcfg__CTRL);
+set_reset_data( devcfg__LOCK, val_devcfg__LOCK);
+set_reset_data( devcfg__CFG, val_devcfg__CFG);
+set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS);
+set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK);
+set_reset_data( devcfg__STATUS, val_devcfg__STATUS);
+set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR);
+set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR);
+set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN);
+set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN);
+set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW);
+set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR);
+set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID);
+set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK);
+set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL);
+set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG);
+set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS);
+set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK);
+set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS);
+set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO);
+set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO);
+set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL);
+
+// ************************************************************
+//   Module dmac0_ns dmac
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR);
+set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC);
+set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN);
+set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS);
+set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS);
+set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR);
+set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD);
+set_reset_data( dmac0_ns__FSR'b'C, val_dmac0_ns__FSRC);
+set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD);
+set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0);
+set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1);
+set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2);
+set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3);
+set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4);
+set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5);
+set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6);
+set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7);
+set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0);
+set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0);
+set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1);
+set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1);
+set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2);
+set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2);
+set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3);
+set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3);
+set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4);
+set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4);
+set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5);
+set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5);
+set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6);
+set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6);
+set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7);
+set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7);
+set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0);
+set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0);
+set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0);
+set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0);
+set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0);
+set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1);
+set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1);
+set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1);
+set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1);
+set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1);
+set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2);
+set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2);
+set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2);
+set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2);
+set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2);
+set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3);
+set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3);
+set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3);
+set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3);
+set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3);
+set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4);
+set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4);
+set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4);
+set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4);
+set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4);
+set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5);
+set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5);
+set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5);
+set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5);
+set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5);
+set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6);
+set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6);
+set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6);
+set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6);
+set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6);
+set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7);
+set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7);
+set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7);
+set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7);
+set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7);
+set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS);
+set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD);
+set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0);
+set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1);
+set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0);
+set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1);
+set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2);
+set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3);
+set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4);
+set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD);
+set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD);
+set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0);
+set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1);
+set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2);
+set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3);
+set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0);
+set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1);
+set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2);
+set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3);
+
+// ************************************************************
+//   Module dmac0_s dmac
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR);
+set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC);
+set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN);
+set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS);
+set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS);
+set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR);
+set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD);
+set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC);
+set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD);
+set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0);
+set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1);
+set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2);
+set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3);
+set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4);
+set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5);
+set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6);
+set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7);
+set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0);
+set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0);
+set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1);
+set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1);
+set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2);
+set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2);
+set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3);
+set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3);
+set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4);
+set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4);
+set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5);
+set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5);
+set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6);
+set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6);
+set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7);
+set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7);
+set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0);
+set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0);
+set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0);
+set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0);
+set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0);
+set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1);
+set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1);
+set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1);
+set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1);
+set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1);
+set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2);
+set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2);
+set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2);
+set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2);
+set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2);
+set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3);
+set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3);
+set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3);
+set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3);
+set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3);
+set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4);
+set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4);
+set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4);
+set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4);
+set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4);
+set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5);
+set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5);
+set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5);
+set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5);
+set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5);
+set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6);
+set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6);
+set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6);
+set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6);
+set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6);
+set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7);
+set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7);
+set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7);
+set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7);
+set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7);
+set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS);
+set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD);
+set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0);
+set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1);
+set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0);
+set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1);
+set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2);
+set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3);
+set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4);
+set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD);
+set_reset_data( dmac0_s__WD, val_dmac0_s__WD);
+set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0);
+set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1);
+set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2);
+set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3);
+set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0);
+set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1);
+set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2);
+set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3);
+
+// ************************************************************
+//   Module efuse_ctrl efuse_ctrl
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK);
+set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK);
+set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA);
+set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG);
+set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS);
+set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL);
+set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW);
+set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW);
+
+// ************************************************************
+//   Module gem0 GEM
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl);
+set_reset_data( gem0__net_cfg, val_gem0__net_cfg);
+set_reset_data( gem0__net_status, val_gem0__net_status);
+set_reset_data( gem0__user_io, val_gem0__user_io);
+set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg);
+set_reset_data( gem0__tx_status, val_gem0__tx_status);
+set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar);
+set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar);
+set_reset_data( gem0__rx_status, val_gem0__rx_status);
+set_reset_data( gem0__intr_status, val_gem0__intr_status);
+set_reset_data( gem0__intr_en, val_gem0__intr_en);
+set_reset_data( gem0__intr_dis, val_gem0__intr_dis);
+set_reset_data( gem0__intr_mask, val_gem0__intr_mask);
+set_reset_data( gem0__phy_maint, val_gem0__phy_maint);
+set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq);
+set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq);
+set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd);
+set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd);
+set_reset_data( gem0__hash_bot, val_gem0__hash_bot);
+set_reset_data( gem0__hash_top, val_gem0__hash_top);
+set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot);
+set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top);
+set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot);
+set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top);
+set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot);
+set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top);
+set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot);
+set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top);
+set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1);
+set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2);
+set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3);
+set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4);
+set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan);
+set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch);
+set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan);
+set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause);
+set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot);
+set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top);
+set_reset_data( gem0__module_id, val_gem0__module_id);
+set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot);
+set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top);
+set_reset_data( gem0__frames_tx, val_gem0__frames_tx);
+set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx);
+set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx);
+set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx);
+set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx);
+set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx);
+set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx);
+set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx);
+set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx);
+set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx);
+set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx);
+set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs);
+set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames);
+set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames);
+set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns);
+set_reset_data( gem0__late_collisns, val_gem0__late_collisns);
+set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames);
+set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs);
+set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot);
+set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top);
+set_reset_data( gem0__frames_rx, val_gem0__frames_rx);
+set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx);
+set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx);
+set_reset_data( gem0__pause_rx, val_gem0__pause_rx);
+set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx);
+set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx);
+set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx);
+set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx);
+set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx);
+set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx);
+set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx);
+set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx);
+set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx);
+set_reset_data( gem0__jab_rx, val_gem0__jab_rx);
+set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors);
+set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors);
+set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors);
+set_reset_data( gem0__align_errors, val_gem0__align_errors);
+set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors);
+set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors);
+set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors);
+set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors);
+set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors);
+set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s);
+set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns);
+set_reset_data( gem0__timer_s, val_gem0__timer_s);
+set_reset_data( gem0__timer_ns, val_gem0__timer_ns);
+set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust);
+set_reset_data( gem0__timer_incr, val_gem0__timer_incr);
+set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s);
+set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns);
+set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s);
+set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns);
+set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s);
+set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns);
+set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s);
+set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns);
+set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl);
+set_reset_data( gem0__pcs_status, val_gem0__pcs_status);
+set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id);
+set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id);
+set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad);
+set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability);
+set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp);
+set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg);
+set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg);
+set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status);
+set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1);
+set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2);
+set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3);
+set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4);
+set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5);
+set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6);
+set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7);
+set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1);
+set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2);
+set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3);
+set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4);
+set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5);
+set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6);
+set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7);
+set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1);
+set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2);
+set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3);
+set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4);
+set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5);
+set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6);
+set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7);
+set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1);
+set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2);
+set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3);
+set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4);
+set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5);
+set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6);
+set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7);
+set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1);
+set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2);
+set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3);
+set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4);
+set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5);
+set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6);
+set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7);
+set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0);
+set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1);
+set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2);
+set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3);
+set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4);
+set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5);
+set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6);
+set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7);
+set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8);
+set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9);
+set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10);
+set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11);
+set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12);
+set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13);
+set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14);
+set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15);
+set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0);
+set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1);
+set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2);
+set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3);
+set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4);
+set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5);
+set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6);
+set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7);
+set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8);
+set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9);
+set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10);
+set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11);
+set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12);
+set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13);
+set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14);
+set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15);
+set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1);
+set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2);
+set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3);
+set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4);
+set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5);
+set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6);
+set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7);
+set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1);
+set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2);
+set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3);
+set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4);
+set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5);
+set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6);
+set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7);
+set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1);
+set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2);
+set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3);
+set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4);
+set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5);
+set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6);
+set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7);
+
+// ************************************************************
+//   Module gem1 GEM
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl);
+set_reset_data( gem1__net_cfg, val_gem1__net_cfg);
+set_reset_data( gem1__net_status, val_gem1__net_status);
+set_reset_data( gem1__user_io, val_gem1__user_io);
+set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg);
+set_reset_data( gem1__tx_status, val_gem1__tx_status);
+set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar);
+set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar);
+set_reset_data( gem1__rx_status, val_gem1__rx_status);
+set_reset_data( gem1__intr_status, val_gem1__intr_status);
+set_reset_data( gem1__intr_en, val_gem1__intr_en);
+set_reset_data( gem1__intr_dis, val_gem1__intr_dis);
+set_reset_data( gem1__intr_mask, val_gem1__intr_mask);
+set_reset_data( gem1__phy_maint, val_gem1__phy_maint);
+set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq);
+set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq);
+set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd);
+set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd);
+set_reset_data( gem1__hash_bot, val_gem1__hash_bot);
+set_reset_data( gem1__hash_top, val_gem1__hash_top);
+set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot);
+set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top);
+set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot);
+set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top);
+set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot);
+set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top);
+set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot);
+set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top);
+set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1);
+set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2);
+set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3);
+set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4);
+set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan);
+set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch);
+set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan);
+set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause);
+set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot);
+set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top);
+set_reset_data( gem1__module_id, val_gem1__module_id);
+set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot);
+set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top);
+set_reset_data( gem1__frames_tx, val_gem1__frames_tx);
+set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx);
+set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx);
+set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx);
+set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx);
+set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx);
+set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx);
+set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx);
+set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx);
+set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx);
+set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx);
+set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs);
+set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames);
+set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames);
+set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns);
+set_reset_data( gem1__late_collisns, val_gem1__late_collisns);
+set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames);
+set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs);
+set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot);
+set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top);
+set_reset_data( gem1__frames_rx, val_gem1__frames_rx);
+set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx);
+set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx);
+set_reset_data( gem1__pause_rx, val_gem1__pause_rx);
+set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx);
+set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx);
+set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx);
+set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx);
+set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx);
+set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx);
+set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx);
+set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx);
+set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx);
+set_reset_data( gem1__jab_rx, val_gem1__jab_rx);
+set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors);
+set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors);
+set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors);
+set_reset_data( gem1__align_errors, val_gem1__align_errors);
+set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors);
+set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors);
+set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors);
+set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors);
+set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors);
+set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s);
+set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns);
+set_reset_data( gem1__timer_s, val_gem1__timer_s);
+set_reset_data( gem1__timer_ns, val_gem1__timer_ns);
+set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust);
+set_reset_data( gem1__timer_incr, val_gem1__timer_incr);
+set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s);
+set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns);
+set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s);
+set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns);
+set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s);
+set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns);
+set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s);
+set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns);
+set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl);
+set_reset_data( gem1__pcs_status, val_gem1__pcs_status);
+set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id);
+set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id);
+set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad);
+set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability);
+set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp);
+set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg);
+set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg);
+set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status);
+set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1);
+set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2);
+set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3);
+set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4);
+set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5);
+set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6);
+set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7);
+set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1);
+set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2);
+set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3);
+set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4);
+set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5);
+set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6);
+set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7);
+set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1);
+set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2);
+set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3);
+set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4);
+set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5);
+set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6);
+set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7);
+set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1);
+set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2);
+set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3);
+set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4);
+set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5);
+set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6);
+set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7);
+set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1);
+set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2);
+set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3);
+set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4);
+set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5);
+set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6);
+set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7);
+set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0);
+set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1);
+set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2);
+set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3);
+set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4);
+set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5);
+set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6);
+set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7);
+set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8);
+set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9);
+set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10);
+set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11);
+set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12);
+set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13);
+set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14);
+set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15);
+set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0);
+set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1);
+set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2);
+set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3);
+set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4);
+set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5);
+set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6);
+set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7);
+set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8);
+set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9);
+set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10);
+set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11);
+set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12);
+set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13);
+set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14);
+set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15);
+set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1);
+set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2);
+set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3);
+set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4);
+set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5);
+set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6);
+set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7);
+set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1);
+set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2);
+set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3);
+set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4);
+set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5);
+set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6);
+set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7);
+set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1);
+set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2);
+set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3);
+set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4);
+set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5);
+set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6);
+set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7);
+
+// ************************************************************
+//   Module gpio gpio
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW);
+set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW);
+set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW);
+set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW);
+set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW);
+set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW);
+set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW);
+set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW);
+set_reset_data( gpio__DATA_0, val_gpio__DATA_0);
+set_reset_data( gpio__DATA_1, val_gpio__DATA_1);
+set_reset_data( gpio__DATA_2, val_gpio__DATA_2);
+set_reset_data( gpio__DATA_3, val_gpio__DATA_3);
+set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO);
+set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO);
+set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO);
+set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO);
+set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0);
+set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0);
+set_reset_data( gpio__OEN_0, val_gpio__OEN_0);
+set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0);
+set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0);
+set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0);
+set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0);
+set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0);
+set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0);
+set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0);
+set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1);
+set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1);
+set_reset_data( gpio__OEN_1, val_gpio__OEN_1);
+set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1);
+set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1);
+set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1);
+set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1);
+set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1);
+set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1);
+set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1);
+set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2);
+set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2);
+set_reset_data( gpio__OEN_2, val_gpio__OEN_2);
+set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2);
+set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2);
+set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2);
+set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2);
+set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2);
+set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2);
+set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2);
+set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3);
+set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3);
+set_reset_data( gpio__OEN_3, val_gpio__OEN_3);
+set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3);
+set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3);
+set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3);
+set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3);
+set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3);
+set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3);
+set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3);
+
+// ************************************************************
+//   Module gpv_iou_switch gpv_iou_switch
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap);
+set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0);
+set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1);
+set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi);
+set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou);
+set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves);
+set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc);
+set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4);
+set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5);
+set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6);
+set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7);
+set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0);
+set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1);
+set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2);
+set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3);
+set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0);
+set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1);
+set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2);
+set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0);
+set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1);
+set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0);
+set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0);
+set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0);
+set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1);
+set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1);
+set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1);
+set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0);
+set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0);
+set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0);
+set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1);
+set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1);
+set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1);
+set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0);
+set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0);
+set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0);
+set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1);
+set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1);
+set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1);
+set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1);
+set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou);
+
+// ************************************************************
+//   Module gpv_qos301_cpu qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl);
+set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot);
+set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot);
+set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p);
+set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b);
+set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r);
+set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p);
+set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b);
+set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r);
+
+// ************************************************************
+//   Module gpv_qos301_dmac qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl);
+set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot);
+set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot);
+set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p);
+set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b);
+set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r);
+set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p);
+set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b);
+set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r);
+
+// ************************************************************
+//   Module gpv_qos301_iou qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl);
+set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot);
+set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot);
+set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p);
+set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b);
+set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r);
+set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p);
+set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b);
+set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r);
+
+// ************************************************************
+//   Module gpv_trustzone nic301_addr_region_ctrl_registers
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap);
+set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0);
+set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1);
+set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb);
+
+// ************************************************************
+//   Module i2c0 IIC
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0);
+set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0);
+set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0);
+set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0);
+set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0);
+set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0);
+set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0);
+set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0);
+set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0);
+set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0);
+set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0);
+
+// ************************************************************
+//   Module i2c1 IIC
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0);
+set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0);
+set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0);
+set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0);
+set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0);
+set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0);
+set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0);
+set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0);
+set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0);
+set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0);
+set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0);
+
+// ************************************************************
+//   Module l2cache L2Cpl310
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id);
+set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type);
+set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control);
+set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control);
+set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control);
+set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control);
+set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl);
+set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg);
+set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg);
+set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1);
+set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0);
+set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask);
+set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status);
+set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status);
+set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear);
+set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync);
+set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa);
+set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way);
+set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa);
+set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index);
+set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way);
+set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa);
+set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index);
+set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way);
+set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0);
+set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0);
+set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1);
+set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1);
+set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2);
+set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2);
+set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3);
+set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3);
+set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4);
+set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4);
+set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5);
+set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5);
+set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6);
+set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6);
+set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7);
+set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7);
+set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en);
+set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way);
+set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start);
+set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end);
+set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl);
+set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl);
+set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl);
+
+// ************************************************************
+//   Module mpcore mpcore
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER);
+set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER);
+set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register);
+set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State);
+set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register);
+set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register);
+set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC);
+set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register);
+set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR);
+set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR);
+set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR);
+set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR);
+set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR);
+set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR);
+set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR);
+set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR);
+set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR);
+set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0);
+set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1);
+set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register);
+set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register);
+set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0);
+set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1);
+set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register);
+set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register);
+set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register);
+set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register);
+set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register);
+set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register);
+set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register);
+set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register);
+set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register);
+set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register);
+set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register);
+set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR);
+set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR);
+set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR);
+set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0);
+set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1);
+set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2);
+set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0);
+set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1);
+set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2);
+set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0);
+set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1);
+set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2);
+set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0);
+set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1);
+set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2);
+set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0);
+set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1);
+set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2);
+set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0);
+set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1);
+set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2);
+set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0);
+set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1);
+set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2);
+set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3);
+set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4);
+set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5);
+set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6);
+set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7);
+set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8);
+set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9);
+set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10);
+set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11);
+set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12);
+set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13);
+set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14);
+set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15);
+set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16);
+set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17);
+set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18);
+set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19);
+set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20);
+set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21);
+set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22);
+set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23);
+set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0);
+set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1);
+set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2);
+set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3);
+set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4);
+set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5);
+set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6);
+set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7);
+set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8);
+set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9);
+set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10);
+set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11);
+set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12);
+set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13);
+set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14);
+set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15);
+set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16);
+set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17);
+set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18);
+set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19);
+set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20);
+set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21);
+set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22);
+set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23);
+set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0);
+set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1);
+set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2);
+set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3);
+set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4);
+set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5);
+set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status);
+set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0);
+set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1);
+set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR);
+set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4);
+set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5);
+set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6);
+set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7);
+set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0);
+set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1);
+set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2);
+set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3);
+set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0);
+set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1);
+set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2);
+set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3);
+
+// ************************************************************
+//   Module ocm ocm
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL);
+set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS);
+set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS);
+set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL);
+
+// ************************************************************
+//   Module qspi qspi
+//   doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller
+/// Design Specification document
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( qspi__Config_reg, val_qspi__Config_reg);
+set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG);
+set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG);
+set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG);
+set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG);
+set_reset_data( qspi__En_REG, val_qspi__En_REG);
+set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG);
+set_reset_data( qspi__TXD0, val_qspi__TXD0);
+set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG);
+set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG);
+set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG);
+set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG);
+set_reset_data( qspi__GPIO, val_qspi__GPIO);
+set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ);
+set_reset_data( qspi__TXD1, val_qspi__TXD1);
+set_reset_data( qspi__TXD2, val_qspi__TXD2);
+set_reset_data( qspi__TXD3, val_qspi__TXD3);
+set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG);
+set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS);
+set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID);
+
+// ************************************************************
+//   Module sd0 sdio
+//   doc version: 4.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register);
+set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count);
+set_reset_data( sd0__Argument, val_sd0__Argument);
+set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command);
+set_reset_data( sd0__Response0, val_sd0__Response0);
+set_reset_data( sd0__Response1, val_sd0__Response1);
+set_reset_data( sd0__Response2, val_sd0__Response2);
+set_reset_data( sd0__Response3, val_sd0__Response3);
+set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port);
+set_reset_data( sd0__Present_State, val_sd0__Present_State);
+set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control);
+set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset);
+set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status);
+set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable);
+set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable);
+set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status);
+set_reset_data( sd0__Capabilities, val_sd0__Capabilities);
+set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities);
+set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status);
+set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status);
+set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address);
+set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control);
+set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection);
+set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support);
+set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version);
+
+// ************************************************************
+//   Module sd1 sdio
+//   doc version: 4.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register);
+set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count);
+set_reset_data( sd1__Argument, val_sd1__Argument);
+set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command);
+set_reset_data( sd1__Response0, val_sd1__Response0);
+set_reset_data( sd1__Response1, val_sd1__Response1);
+set_reset_data( sd1__Response2, val_sd1__Response2);
+set_reset_data( sd1__Response3, val_sd1__Response3);
+set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port);
+set_reset_data( sd1__Present_State, val_sd1__Present_State);
+set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control);
+set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset);
+set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status);
+set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable);
+set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable);
+set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status);
+set_reset_data( sd1__Capabilities, val_sd1__Capabilities);
+set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities);
+set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status);
+set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status);
+set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address);
+set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control);
+set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection);
+set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support);
+set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version);
+
+// ************************************************************
+//   Module slcr slcr
+//   doc version: 1.3, based on 11/18/2010 SLCR_spec.doc
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( slcr__SCL, val_slcr__SCL);
+set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK);
+set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK);
+set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA);
+set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL);
+set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL);
+set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL);
+set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS);
+set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG);
+set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG);
+set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG);
+set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL);
+set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL);
+set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL);
+set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL);
+set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL);
+set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL);
+set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL);
+set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL);
+set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL);
+set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL);
+set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL);
+set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL);
+set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL);
+set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL);
+set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL);
+set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL);
+set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL);
+set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL);
+set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL);
+set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL);
+set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL);
+set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL);
+set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL);
+set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT);
+set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA);
+set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL);
+set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL);
+set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT);
+set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA);
+set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL);
+set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL);
+set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT);
+set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA);
+set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL);
+set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL);
+set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT);
+set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA);
+set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL);
+set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM);
+set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST'b');
+set_reset_data( slcr__PLL_PREDIVISOR, val_slcr__PLL_PREDIVISOR);
+set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE);
+set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG);
+set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT);
+set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT);
+set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL);
+set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL);
+set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL);
+set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL);
+set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL);
+set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL);
+set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL);
+set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL);
+set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL);
+set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL);
+set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL);
+set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL);
+set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL);
+set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL);
+set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL);
+set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL);
+set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL);
+set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL);
+set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL);
+set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON);
+set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR);
+set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS);
+set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE);
+set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL);
+set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL);
+set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0);
+set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1);
+set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM);
+set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM);
+set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS);
+set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS);
+set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS);
+set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM);
+set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO);
+set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB);
+set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M);
+set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI);
+set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL);
+set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE);
+set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT);
+set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START);
+set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START);
+set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA);
+set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL);
+set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS);
+set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00);
+set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01);
+set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02);
+set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03);
+set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04);
+set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05);
+set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06);
+set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07);
+set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08);
+set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09);
+set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10);
+set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11);
+set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12);
+set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13);
+set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14);
+set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15);
+set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16);
+set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17);
+set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18);
+set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19);
+set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20);
+set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21);
+set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22);
+set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23);
+set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24);
+set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25);
+set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26);
+set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27);
+set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28);
+set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29);
+set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30);
+set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31);
+set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32);
+set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33);
+set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34);
+set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35);
+set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36);
+set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37);
+set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38);
+set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39);
+set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40);
+set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41);
+set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42);
+set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43);
+set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44);
+set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45);
+set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46);
+set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47);
+set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48);
+set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49);
+set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50);
+set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51);
+set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52);
+set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53);
+set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL);
+set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK);
+set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0);
+set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1);
+set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL);
+set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL);
+set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN);
+set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG);
+set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0);
+set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1);
+set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2);
+set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0);
+set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1);
+set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2);
+set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM);
+set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM);
+set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01);
+set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01);
+set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0);
+set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1);
+set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0);
+set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1);
+set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI);
+set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM);
+set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0);
+set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1);
+set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2);
+set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0);
+set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1);
+set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2);
+set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0);
+set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1);
+set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2);
+set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0);
+set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1);
+set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2);
+set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM);
+set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0);
+set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1);
+set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM);
+set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM);
+set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL);
+set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18);
+set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25);
+set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33);
+set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL);
+set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL);
+set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL);
+set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0);
+set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1);
+set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0);
+set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1);
+set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0);
+set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1);
+set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK);
+set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR);
+set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA);
+set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF);
+set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK);
+set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL);
+set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL);
+set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS);
+
+// ************************************************************
+//   Module smcc pl353
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( smcc__memc_status, val_smcc__memc_status);
+set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg);
+set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set);
+set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr);
+set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd);
+set_reset_data( smcc__set_cycles, val_smcc__set_cycles);
+set_reset_data( smcc__set_opmode, val_smcc__set_opmode);
+set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0);
+set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1);
+set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0);
+set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0);
+set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1);
+set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1);
+set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0);
+set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0);
+set_reset_data( smcc__user_status, val_smcc__user_status);
+set_reset_data( smcc__user_config, val_smcc__user_config);
+set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0);
+set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0);
+set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0);
+set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0);
+set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0);
+set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0);
+set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0);
+set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0);
+set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0);
+set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0);
+set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1);
+set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1);
+set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1);
+set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1);
+set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1);
+set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1);
+set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1);
+set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1);
+set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1);
+set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1);
+set_reset_data( smcc__integration_test, val_smcc__integration_test);
+set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0);
+set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1);
+set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2);
+set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3);
+set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0);
+set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1);
+set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2);
+set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3);
+
+// ************************************************************
+//   Module spi0 SPI
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0);
+set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0);
+set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0);
+set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0);
+set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0);
+set_reset_data( spi0__En_reg0, val_spi0__En_reg0);
+set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0);
+set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0);
+set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0);
+set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0);
+set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0);
+set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0);
+set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0);
+
+// ************************************************************
+//   Module spi1 SPI
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0);
+set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0);
+set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0);
+set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0);
+set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0);
+set_reset_data( spi1__En_reg0, val_spi1__En_reg0);
+set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0);
+set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0);
+set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0);
+set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0);
+set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0);
+set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0);
+set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0);
+
+// ************************************************************
+//   Module swdt swdt
+//   doc version: 2.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( swdt__MODE, val_swdt__MODE);
+set_reset_data( swdt__CONTROL, val_swdt__CONTROL);
+set_reset_data( swdt__RESTART, val_swdt__RESTART);
+set_reset_data( swdt__STATUS, val_swdt__STATUS);
+
+// ************************************************************
+//   Module ttc0 ttc
+//   doc version: 2.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1);
+set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2);
+set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3);
+set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1);
+set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2);
+set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3);
+set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1);
+set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2);
+set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3);
+set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1);
+set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2);
+set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3);
+set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1);
+set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2);
+set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3);
+set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1);
+set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2);
+set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3);
+set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1);
+set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2);
+set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3);
+set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1);
+set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2);
+set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3);
+set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1);
+set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2);
+set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3);
+set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1);
+set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2);
+set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3);
+set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1);
+set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2);
+set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3);
+
+// ************************************************************
+//   Module ttc1 ttc
+//   doc version: 2.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1);
+set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2);
+set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3);
+set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1);
+set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2);
+set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3);
+set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1);
+set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2);
+set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3);
+set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1);
+set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2);
+set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3);
+set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1);
+set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2);
+set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3);
+set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1);
+set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2);
+set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3);
+set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1);
+set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2);
+set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3);
+set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1);
+set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2);
+set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3);
+set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1);
+set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2);
+set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3);
+set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1);
+set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2);
+set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3);
+set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1);
+set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2);
+set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3);
+
+// ************************************************************
+//   Module uart0 UART
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0);
+set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0);
+set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0);
+set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0);
+set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0);
+set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0);
+set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0);
+set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0);
+set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0);
+set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0);
+set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0);
+set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0);
+set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0);
+set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0);
+set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0);
+set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0);
+set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0);
+set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0);
+
+// ************************************************************
+//   Module uart1 UART
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0);
+set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0);
+set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0);
+set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0);
+set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0);
+set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0);
+set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0);
+set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0);
+set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0);
+set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0);
+set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0);
+set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0);
+set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0);
+set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0);
+set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0);
+set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0);
+set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0);
+set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0);
+
+// ************************************************************
+//   Module usb0 usb
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( usb0__ID, val_usb0__ID);
+set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL);
+set_reset_data( usb0__HWHOST, val_usb0__HWHOST);
+set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE);
+set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF);
+set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF);
+set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD);
+set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL);
+set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD);
+set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL);
+set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG);
+set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION);
+set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS);
+set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS);
+set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION);
+set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS);
+set_reset_data( usb0__USBCMD, val_usb0__USBCMD);
+set_reset_data( usb0__USBSTS, val_usb0__USBSTS);
+set_reset_data( usb0__USBINTR, val_usb0__USBINTR);
+set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX);
+set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR);
+set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR);
+set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL);
+set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE);
+set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING);
+set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING);
+set_reset_data( usb0__IC_USB, val_usb0__IC_USB);
+set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT);
+set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK);
+set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN);
+set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG);
+set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1);
+set_reset_data( usb0__OTGSC, val_usb0__OTGSC);
+set_reset_data( usb0__USBMODE, val_usb0__USBMODE);
+set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT);
+set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME);
+set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH);
+set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT);
+set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE);
+set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0);
+set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1);
+set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2);
+set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3);
+set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4);
+set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5);
+set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6);
+set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7);
+set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8);
+set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9);
+set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10);
+set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11);
+set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12);
+
+// ************************************************************
+//   Module usb1 usb
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( usb1__ID, val_usb1__ID);
+set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL);
+set_reset_data( usb1__HWHOST, val_usb1__HWHOST);
+set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE);
+set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF);
+set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF);
+set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD);
+set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL);
+set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD);
+set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL);
+set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG);
+set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION);
+set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS);
+set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS);
+set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION);
+set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS);
+set_reset_data( usb1__USBCMD, val_usb1__USBCMD);
+set_reset_data( usb1__USBSTS, val_usb1__USBSTS);
+set_reset_data( usb1__USBINTR, val_usb1__USBINTR);
+set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX);
+set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR);
+set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR);
+set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL);
+set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE);
+set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING);
+set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING);
+set_reset_data( usb1__IC_USB, val_usb1__IC_USB);
+set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT);
+set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK);
+set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN);
+set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG);
+set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1);
+set_reset_data( usb1__OTGSC, val_usb1__OTGSC);
+set_reset_data( usb1__USBMODE, val_usb1__USBMODE);
+set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT);
+set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME);
+set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH);
+set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT);
+set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE);
+set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0);
+set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1);
+set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2);
+set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3);
+set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4);
+set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5);
+set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6);
+set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7);
+set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8);
+set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9);
+set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10);
+set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11);
+set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12);
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:06 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_1_0_stub.v
+// Design      : design_1_axi_gpio_1_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_gpio,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:35:14 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_2_0_stub.v
+// Design      : design_1_axi_gpio_2_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_gpio,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio_io_o, 
+  gpio_io_t)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[7:0],gpio_io_o[7:0],gpio_io_t[7:0]"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output ip2intc_irpt;
+  input [7:0]gpio_io_i;
+  output [7:0]gpio_io_o;
+  output [7:0]gpio_io_t;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:53:58 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top design_1_rst_ps7_0_100M_0 -prefix
+//               design_1_rst_ps7_0_100M_0_ design_1_rst_ps7_0_100M_0_stub.v
+// Design      : design_1_rst_ps7_0_100M_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""proc_sys_reset,Vivado 2016.4"" *)
+module design_1_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in, 
+  mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset, 
+  interconnect_aresetn, peripheral_aresetn)
+/* synthesis syn_black_box black_box_pad_pin=""slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]"" */;
+  input slowest_sync_clk;
+  input ext_reset_in;
+  input aux_reset_in;
+  input mb_debug_sys_rst;
+  input dcm_locked;
+  output mb_reset;
+  output [0:0]bus_struct_reset;
+  output [0:0]peripheral_reset;
+  output [0:0]interconnect_aresetn;
+  output [0:0]peripheral_aresetn;
+endmodule
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_axi_acp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for ACP port
+ *
+ *****************************************************************************/
+
+/* AXI Slave ACP */
+  processing_system7_bfm_v2_0_5_axi_slave #( C_USE_S_AXI_ACP, // enable
+               axi_acp_name, // name
+               axi_acp_data_width, // data width
+               addr_width, /// address width
+               axi_acp_id_width, // ID width
+               C_S_AXI_ACP_BASEADDR, // slave base address
+               C_S_AXI_ACP_HIGHADDR,// slave size
+               axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes 
+               axi_slv_excl_support, // Exclusive access support
+               axi_acp_wr_outstanding,
+               axi_acp_rd_outstanding)
+  S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
+            .S_ACLK   (S_AXI_ACP_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_ACP_AWID),
+            .S_AWADDR  (S_AXI_ACP_AWADDR),
+            .S_AWLEN   (S_AXI_ACP_AWLEN),
+            .S_AWSIZE  (S_AXI_ACP_AWSIZE),
+            .S_AWBURST (S_AXI_ACP_AWBURST),
+            .S_AWLOCK  (S_AXI_ACP_AWLOCK),
+            .S_AWCACHE (S_AXI_ACP_AWCACHE),
+            .S_AWPROT  (S_AXI_ACP_AWPROT),
+            .S_AWVALID (S_AXI_ACP_AWVALID),
+            .S_AWREADY (S_AXI_ACP_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_ACP_WID),
+            .S_WDATA  (S_AXI_ACP_WDATA),
+            .S_WSTRB  (S_AXI_ACP_WSTRB), 
+            .S_WLAST  (S_AXI_ACP_WLAST), 
+            .S_WVALID (S_AXI_ACP_WVALID),
+            .S_WREADY (S_AXI_ACP_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_ACP_BID),
+            .S_BRESP  (S_AXI_ACP_BRESP),
+            .S_BVALID (S_AXI_ACP_BVALID),
+            .S_BREADY (S_AXI_ACP_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_ACP_ARID),
+            .S_ARADDR  (S_AXI_ACP_ARADDR),
+            .S_ARLEN   (S_AXI_ACP_ARLEN),
+            .S_ARSIZE  (S_AXI_ACP_ARSIZE),
+            .S_ARBURST (S_AXI_ACP_ARBURST),
+            .S_ARLOCK  (S_AXI_ACP_ARLOCK),
+            .S_ARCACHE (S_AXI_ACP_ARCACHE),
+            .S_ARPROT  (S_AXI_ACP_ARPROT),
+            .S_ARVALID (S_AXI_ACP_ARVALID),
+            .S_ARREADY (S_AXI_ACP_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_ACP_RID),
+            .S_RDATA  (S_AXI_ACP_RDATA),
+            .S_RRESP  (S_AXI_ACP_RRESP),
+            .S_RLAST  (S_AXI_ACP_RLAST),
+            .S_RVALID (S_AXI_ACP_RVALID),
+            .S_RREADY (S_AXI_ACP_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_ACP_AWQOS),
+            .S_ARQOS  (S_AXI_ACP_ARQOS),            // Side band signals 
+
+            .SW_CLK   (net_sw_clk),
+/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
+            .WR_DATA_ACK_DDR (ddr_wr_ack_port0),
+            .WR_DATA_ACK_OCM (ocm_wr_ack_port0),
+            .WR_DATA  (net_wr_data_acp), 
+            .WR_ADDR  (net_wr_addr_acp), 
+            .WR_BYTES  (net_wr_bytes_acp), 
+            .WR_DATA_VALID_DDR  (ddr_wr_dv_port0), 
+            .WR_DATA_VALID_OCM  (ocm_wr_dv_port0), 
+            .WR_QOS (net_wr_qos_acp),
+
+            .RD_REQ_DDR (ddr_rd_req_port0),
+            .RD_REQ_OCM (ocm_rd_req_port0),
+            .RD_REQ_REG (reg_rd_req_port0),
+            .RD_ADDR (net_rd_addr_acp),
+            .RD_DATA_DDR (ddr_rd_data_port0),
+            .RD_DATA_OCM (ocm_rd_data_port0),
+            .RD_DATA_REG (reg_rd_data_port0),
+            .RD_BYTES (net_rd_bytes_acp),
+            .RD_DATA_VALID_DDR (ddr_rd_dv_port0),
+            .RD_DATA_VALID_OCM (ocm_rd_dv_port0),
+            .RD_DATA_VALID_REG (reg_rd_dv_port0),
+            .RD_QOS (net_rd_qos_acp)
+
+);
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:53:58 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_100M_0_sim_netlist.v
+// Design      : design_1_rst_ps7_0_100M_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
+   (lpf_asr_reg,
+    scndry_out,
+    aux_reset_in,
+    lpf_asr,
+    asr_lpf,
+    p_1_in,
+    p_2_in,
+    slowest_sync_clk);
+  output lpf_asr_reg;
+  output scndry_out;
+  input aux_reset_in;
+  input lpf_asr;
+  input [0:0]asr_lpf;
+  input p_1_in;
+  input p_2_in;
+  input slowest_sync_clk;
+
+  wire asr_d1;
+  wire [0:0]asr_lpf;
+  wire aux_reset_in;
+  wire lpf_asr;
+  wire lpf_asr_reg;
+  wire p_1_in;
+  wire p_2_in;
+  wire s_level_out_d1_cdc_to;
+  wire s_level_out_d2;
+  wire s_level_out_d3;
+  wire scndry_out;
+  wire slowest_sync_clk;
+
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(asr_d1),
+        .Q(s_level_out_d1_cdc_to),
+        .R(1\'b0));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 
+       (.I0(aux_reset_in),
+        .O(asr_d1));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d1_cdc_to),
+        .Q(s_level_out_d2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d2),
+        .Q(s_level_out_d3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d3),
+        .Q(scndry_out),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hEAAAAAA8)) 
+    lpf_asr_i_1
+       (.I0(lpf_asr),
+        .I1(asr_lpf),
+        .I2(scndry_out),
+        .I3(p_1_in),
+        .I4(p_2_in),
+        .O(lpf_asr_reg));
+endmodule
+
+(* ORIG_REF_NAME = ""cdc_sync"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
+   (lpf_exr_reg,
+    scndry_out,
+    lpf_exr,
+    p_3_out,
+    mb_debug_sys_rst,
+    ext_reset_in,
+    slowest_sync_clk);
+  output lpf_exr_reg;
+  output scndry_out;
+  input lpf_exr;
+  input [2:0]p_3_out;
+  input mb_debug_sys_rst;
+  input ext_reset_in;
+  input slowest_sync_clk;
+
+  wire \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
+  wire ext_reset_in;
+  wire lpf_exr;
+  wire lpf_exr_reg;
+  wire mb_debug_sys_rst;
+  wire [2:0]p_3_out;
+  wire s_level_out_d1_cdc_to;
+  wire s_level_out_d2;
+  wire s_level_out_d3;
+  wire scndry_out;
+  wire slowest_sync_clk;
+
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
+        .Q(s_level_out_d1_cdc_to),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 
+       (.I0(mb_debug_sys_rst),
+        .I1(ext_reset_in),
+        .O(\\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d1_cdc_to),
+        .Q(s_level_out_d2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d2),
+        .Q(s_level_out_d3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(s_level_out_d3),
+        .Q(scndry_out),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hEAAAAAA8)) 
+    lpf_exr_i_1
+       (.I0(lpf_exr),
+        .I1(p_3_out[0]),
+        .I2(scndry_out),
+        .I3(p_3_out[1]),
+        .I4(p_3_out[2]),
+        .O(lpf_exr_reg));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_rst_ps7_0_100M_0,proc_sys_reset,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""proc_sys_reset,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (slowest_sync_clk,
+    ext_reset_in,
+    aux_reset_in,
+    mb_debug_sys_rst,
+    dcm_locked,
+    mb_reset,
+    bus_struct_reset,
+    peripheral_reset,
+    interconnect_aresetn,
+    peripheral_aresetn);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 clock CLK"" *) input slowest_sync_clk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 ext_reset RST"" *) input ext_reset_in;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 aux_reset RST"" *) input aux_reset_in;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 dbg_reset RST"" *) input mb_debug_sys_rst;
+  input dcm_locked;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 mb_rst RST"" *) output mb_reset;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 bus_struct_reset RST"" *) output [0:0]bus_struct_reset;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 peripheral_high_rst RST"" *) output [0:0]peripheral_reset;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 interconnect_low_rst RST"" *) output [0:0]interconnect_aresetn;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 peripheral_low_rst RST"" *) output [0:0]peripheral_aresetn;
+
+  wire aux_reset_in;
+  wire [0:0]bus_struct_reset;
+  wire dcm_locked;
+  wire ext_reset_in;
+  wire [0:0]interconnect_aresetn;
+  wire mb_debug_sys_rst;
+  wire mb_reset;
+  wire [0:0]peripheral_aresetn;
+  wire [0:0]peripheral_reset;
+  wire slowest_sync_clk;
+
+  (* C_AUX_RESET_HIGH = ""1\'b0"" *) 
+  (* C_AUX_RST_WIDTH = ""4"" *) 
+  (* C_EXT_RESET_HIGH = ""1\'b0"" *) 
+  (* C_EXT_RST_WIDTH = ""4"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_NUM_BUS_RST = ""1"" *) 
+  (* C_NUM_INTERCONNECT_ARESETN = ""1"" *) 
+  (* C_NUM_PERP_ARESETN = ""1"" *) 
+  (* C_NUM_PERP_RST = ""1"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset U0
+       (.aux_reset_in(aux_reset_in),
+        .bus_struct_reset(bus_struct_reset),
+        .dcm_locked(dcm_locked),
+        .ext_reset_in(ext_reset_in),
+        .interconnect_aresetn(interconnect_aresetn),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .mb_reset(mb_reset),
+        .peripheral_aresetn(peripheral_aresetn),
+        .peripheral_reset(peripheral_reset),
+        .slowest_sync_clk(slowest_sync_clk));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
+   (lpf_int,
+    slowest_sync_clk,
+    dcm_locked,
+    aux_reset_in,
+    mb_debug_sys_rst,
+    ext_reset_in);
+  output lpf_int;
+  input slowest_sync_clk;
+  input dcm_locked;
+  input aux_reset_in;
+  input mb_debug_sys_rst;
+  input ext_reset_in;
+
+  wire \\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
+  wire \\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
+  wire Q;
+  wire [0:0]asr_lpf;
+  wire aux_reset_in;
+  wire dcm_locked;
+  wire ext_reset_in;
+  wire lpf_asr;
+  wire lpf_exr;
+  wire lpf_int;
+  wire lpf_int0__0;
+  wire mb_debug_sys_rst;
+  wire p_1_in;
+  wire p_2_in;
+  wire p_3_in1_in;
+  wire [3:0]p_3_out;
+  wire slowest_sync_clk;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \\ACTIVE_LOW_AUX.ACT_LO_AUX 
+       (.asr_lpf(asr_lpf),
+        .aux_reset_in(aux_reset_in),
+        .lpf_asr(lpf_asr),
+        .lpf_asr_reg(\\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
+        .p_1_in(p_1_in),
+        .p_2_in(p_2_in),
+        .scndry_out(p_3_in1_in),
+        .slowest_sync_clk(slowest_sync_clk));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \\ACTIVE_LOW_EXT.ACT_LO_EXT 
+       (.ext_reset_in(ext_reset_in),
+        .lpf_exr(lpf_exr),
+        .lpf_exr_reg(\\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .p_3_out(p_3_out[2:0]),
+        .scndry_out(p_3_out[3]),
+        .slowest_sync_clk(slowest_sync_clk));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\AUX_LPF[1].asr_lpf_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_in1_in),
+        .Q(p_2_in),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\AUX_LPF[2].asr_lpf_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_2_in),
+        .Q(p_1_in),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\AUX_LPF[3].asr_lpf_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(asr_lpf),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\EXT_LPF[1].exr_lpf_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[3]),
+        .Q(p_3_out[2]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\EXT_LPF[2].exr_lpf_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[2]),
+        .Q(p_3_out[1]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\EXT_LPF[3].exr_lpf_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[1]),
+        .Q(p_3_out[0]),
+        .R(1\'b0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  (* XILINX_LEGACY_PRIM = ""SRL16"" *) 
+  (* srl_name = ""U0/\\EXT_LPF/POR_SRL_I "" *) 
+  SRL16E #(
+    .INIT(16\'hFFFF)) 
+    POR_SRL_I
+       (.A0(1\'b1),
+        .A1(1\'b1),
+        .A2(1\'b1),
+        .A3(1\'b1),
+        .CE(1\'b1),
+        .CLK(slowest_sync_clk),
+        .D(1\'b0),
+        .Q(Q));
+  FDRE #(
+    .INIT(1\'b0)) 
+    lpf_asr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
+        .Q(lpf_asr),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    lpf_exr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
+        .Q(lpf_exr),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hFFEF)) 
+    lpf_int0
+       (.I0(Q),
+        .I1(lpf_asr),
+        .I2(dcm_locked),
+        .I3(lpf_exr),
+        .O(lpf_int0__0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    lpf_int_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(lpf_int0__0),
+        .Q(lpf_int),
+        .R(1\'b0));
+endmodule
+
+(* C_AUX_RESET_HIGH = ""1\'b0"" *) (* C_AUX_RST_WIDTH = ""4"" *) (* C_EXT_RESET_HIGH = ""1\'b0"" *) 
+(* C_EXT_RST_WIDTH = ""4"" *) (* C_FAMILY = ""zynq"" *) (* C_NUM_BUS_RST = ""1"" *) 
+(* C_NUM_INTERCONNECT_ARESETN = ""1"" *) (* C_NUM_PERP_ARESETN = ""1"" *) (* C_NUM_PERP_RST = ""1"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
+   (slowest_sync_clk,
+    ext_reset_in,
+    aux_reset_in,
+    mb_debug_sys_rst,
+    dcm_locked,
+    mb_reset,
+    bus_struct_reset,
+    peripheral_reset,
+    interconnect_aresetn,
+    peripheral_aresetn);
+  input slowest_sync_clk;
+  input ext_reset_in;
+  input aux_reset_in;
+  input mb_debug_sys_rst;
+  input dcm_locked;
+  output mb_reset;
+  (* equivalent_register_removal = ""no"" *) output [0:0]bus_struct_reset;
+  (* equivalent_register_removal = ""no"" *) output [0:0]peripheral_reset;
+  (* equivalent_register_removal = ""no"" *) output [0:0]interconnect_aresetn;
+  (* equivalent_register_removal = ""no"" *) output [0:0]peripheral_aresetn;
+
+  wire Core;
+  wire SEQ_n_3;
+  wire SEQ_n_4;
+  wire aux_reset_in;
+  wire bsr;
+  wire [0:0]bus_struct_reset;
+  wire dcm_locked;
+  wire ext_reset_in;
+  wire [0:0]interconnect_aresetn;
+  wire lpf_int;
+  wire mb_debug_sys_rst;
+  wire mb_reset;
+  wire [0:0]peripheral_aresetn;
+  wire [0:0]peripheral_reset;
+  wire pr;
+  wire slowest_sync_clk;
+
+  (* equivalent_register_removal = ""no"" *) 
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(SEQ_n_3),
+        .Q(interconnect_aresetn),
+        .R(1\'b0));
+  (* equivalent_register_removal = ""no"" *) 
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(SEQ_n_4),
+        .Q(peripheral_aresetn),
+        .R(1\'b0));
+  (* equivalent_register_removal = ""no"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\BSR_OUT_DFF[0].bus_struct_reset_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(bsr),
+        .Q(bus_struct_reset),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf EXT_LPF
+       (.aux_reset_in(aux_reset_in),
+        .dcm_locked(dcm_locked),
+        .ext_reset_in(ext_reset_in),
+        .lpf_int(lpf_int),
+        .mb_debug_sys_rst(mb_debug_sys_rst),
+        .slowest_sync_clk(slowest_sync_clk));
+  (* equivalent_register_removal = ""no"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\PR_OUT_DFF[0].peripheral_reset_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(pr),
+        .Q(peripheral_reset),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr SEQ
+       (.\\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
+        .\\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
+        .Core(Core),
+        .bsr(bsr),
+        .lpf_int(lpf_int),
+        .pr(pr),
+        .slowest_sync_clk(slowest_sync_clk));
+  FDRE #(
+    .INIT(1\'b0)) 
+    mb_reset_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(Core),
+        .Q(mb_reset),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
+   (Core,
+    bsr,
+    pr,
+    \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
+    \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
+    lpf_int,
+    slowest_sync_clk);
+  output Core;
+  output bsr;
+  output pr;
+  output \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
+  output \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
+  input lpf_int;
+  input slowest_sync_clk;
+
+  wire \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
+  wire \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
+  wire Core;
+  wire Core_i_1_n_0;
+  wire bsr;
+  wire \\bsr_dec_reg_n_0_[0] ;
+  wire \\bsr_dec_reg_n_0_[2] ;
+  wire bsr_i_1_n_0;
+  wire \\core_dec[0]_i_1_n_0 ;
+  wire \\core_dec[2]_i_1_n_0 ;
+  wire \\core_dec_reg_n_0_[0] ;
+  wire \\core_dec_reg_n_0_[1] ;
+  wire from_sys_i_1_n_0;
+  wire lpf_int;
+  wire p_0_in;
+  wire [2:0]p_3_out;
+  wire [2:0]p_5_out;
+  wire pr;
+  wire pr_dec0__0;
+  wire \\pr_dec_reg_n_0_[0] ;
+  wire \\pr_dec_reg_n_0_[2] ;
+  wire pr_i_1_n_0;
+  wire seq_clr;
+  wire [5:0]seq_cnt;
+  wire seq_cnt_en;
+  wire slowest_sync_clk;
+
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1 
+       (.I0(bsr),
+        .O(\\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1 
+       (.I0(pr),
+        .O(\\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    Core_i_1
+       (.I0(Core),
+        .I1(p_0_in),
+        .O(Core_i_1_n_0));
+  FDSE #(
+    .INIT(1\'b0)) 
+    Core_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(Core_i_1_n_0),
+        .Q(Core),
+        .S(lpf_int));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n SEQ_COUNTER
+       (.Q(seq_cnt),
+        .seq_clr(seq_clr),
+        .seq_cnt_en(seq_cnt_en),
+        .slowest_sync_clk(slowest_sync_clk));
+  LUT4 #(
+    .INIT(16\'h0804)) 
+    \\bsr_dec[0]_i_1 
+       (.I0(seq_cnt_en),
+        .I1(seq_cnt[3]),
+        .I2(seq_cnt[5]),
+        .I3(seq_cnt[4]),
+        .O(p_5_out[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\bsr_dec[2]_i_1 
+       (.I0(\\core_dec_reg_n_0_[1] ),
+        .I1(\\bsr_dec_reg_n_0_[0] ),
+        .O(p_5_out[2]));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\bsr_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_5_out[0]),
+        .Q(\\bsr_dec_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\bsr_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_5_out[2]),
+        .Q(\\bsr_dec_reg_n_0_[2] ),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    bsr_i_1
+       (.I0(bsr),
+        .I1(\\bsr_dec_reg_n_0_[2] ),
+        .O(bsr_i_1_n_0));
+  FDSE #(
+    .INIT(1\'b0)) 
+    bsr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(bsr_i_1_n_0),
+        .Q(bsr),
+        .S(lpf_int));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h8040)) 
+    \\core_dec[0]_i_1 
+       (.I0(seq_cnt[4]),
+        .I1(seq_cnt[3]),
+        .I2(seq_cnt[5]),
+        .I3(seq_cnt_en),
+        .O(\\core_dec[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\core_dec[2]_i_1 
+       (.I0(\\core_dec_reg_n_0_[1] ),
+        .I1(\\core_dec_reg_n_0_[0] ),
+        .O(\\core_dec[2]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\core_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\core_dec[0]_i_1_n_0 ),
+        .Q(\\core_dec_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\core_dec_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(pr_dec0__0),
+        .Q(\\core_dec_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\core_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(\\core_dec[2]_i_1_n_0 ),
+        .Q(p_0_in),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    from_sys_i_1
+       (.I0(Core),
+        .I1(seq_cnt_en),
+        .O(from_sys_i_1_n_0));
+  FDSE #(
+    .INIT(1\'b0)) 
+    from_sys_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(from_sys_i_1_n_0),
+        .Q(seq_cnt_en),
+        .S(lpf_int));
+  LUT4 #(
+    .INIT(16\'h0210)) 
+    pr_dec0
+       (.I0(seq_cnt[0]),
+        .I1(seq_cnt[1]),
+        .I2(seq_cnt[2]),
+        .I3(seq_cnt_en),
+        .O(pr_dec0__0));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h1080)) 
+    \\pr_dec[0]_i_1 
+       (.I0(seq_cnt_en),
+        .I1(seq_cnt[5]),
+        .I2(seq_cnt[3]),
+        .I3(seq_cnt[4]),
+        .O(p_3_out[0]));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\pr_dec[2]_i_1 
+       (.I0(\\core_dec_reg_n_0_[1] ),
+        .I1(\\pr_dec_reg_n_0_[0] ),
+        .O(p_3_out[2]));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\pr_dec_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[0]),
+        .Q(\\pr_dec_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\pr_dec_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(p_3_out[2]),
+        .Q(\\pr_dec_reg_n_0_[2] ),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    pr_i_1
+       (.I0(pr),
+        .I1(\\pr_dec_reg_n_0_[2] ),
+        .O(pr_i_1_n_0));
+  FDSE #(
+    .INIT(1\'b0)) 
+    pr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(pr_i_1_n_0),
+        .Q(pr),
+        .S(lpf_int));
+  FDRE #(
+    .INIT(1\'b0)) 
+    seq_clr_reg
+       (.C(slowest_sync_clk),
+        .CE(1\'b1),
+        .D(1\'b1),
+        .Q(seq_clr),
+        .R(lpf_int));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
+   (Q,
+    seq_clr,
+    seq_cnt_en,
+    slowest_sync_clk);
+  output [5:0]Q;
+  input seq_clr;
+  input seq_cnt_en;
+  input slowest_sync_clk;
+
+  wire [5:0]Q;
+  wire clear;
+  wire [5:0]q_int0;
+  wire seq_clr;
+  wire seq_cnt_en;
+  wire slowest_sync_clk;
+
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\q_int[0]_i_1 
+       (.I0(Q[0]),
+        .O(q_int0[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\q_int[1]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .O(q_int0[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\q_int[2]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .I2(Q[2]),
+        .O(q_int0[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\q_int[3]_i_1 
+       (.I0(Q[1]),
+        .I1(Q[0]),
+        .I2(Q[2]),
+        .I3(Q[3]),
+        .O(q_int0[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h7FFF8000)) 
+    \\q_int[4]_i_1 
+       (.I0(Q[2]),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(Q[3]),
+        .I4(Q[4]),
+        .O(q_int0[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\q_int[5]_i_1 
+       (.I0(seq_clr),
+        .O(clear));
+  LUT6 #(
+    .INIT(64\'h7FFFFFFF80000000)) 
+    \\q_int[5]_i_2 
+       (.I0(Q[3]),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(Q[2]),
+        .I4(Q[4]),
+        .I5(Q[5]),
+        .O(q_int0[5]));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[0] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[0]),
+        .Q(Q[0]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[1] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[1]),
+        .Q(Q[1]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[2] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[2]),
+        .Q(Q[2]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[3] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[3]),
+        .Q(Q[3]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[4] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[4]),
+        .Q(Q[4]),
+        .R(clear));
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\q_int_reg[5] 
+       (.C(slowest_sync_clk),
+        .CE(seq_cnt_en),
+        .D(q_int0[5]),
+        .Q(Q[5]),
+        .R(clear));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_axi_hp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for AXI HP ports
+ *
+ *****************************************************************************/
+
+/* AXI Slave HP0 */  
+ processing_system7_bfm_v2_0_5_afi_slave #(  C_USE_S_AXI_HP0, // enable
+               axi_hp0_name, // name
+               C_S_AXI_HP0_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP0_BASEADDR, // slave base address
+               C_S_AXI_HP0_HIGHADDR, // slave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+  S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
+            .S_ACLK   (S_AXI_HP0_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP0_AWID),
+            .S_AWADDR  (S_AXI_HP0_AWADDR),
+            .S_AWLEN   (S_AXI_HP0_AWLEN),
+            .S_AWSIZE  (S_AXI_HP0_AWSIZE),
+            .S_AWBURST (S_AXI_HP0_AWBURST),
+            .S_AWLOCK  (S_AXI_HP0_AWLOCK),
+            .S_AWCACHE (S_AXI_HP0_AWCACHE),
+            .S_AWPROT  (S_AXI_HP0_AWPROT),
+            .S_AWVALID (S_AXI_HP0_AWVALID),
+            .S_AWREADY (S_AXI_HP0_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP0_WID),
+            .S_WDATA  (S_AXI_HP0_WDATA),
+            .S_WSTRB  (S_AXI_HP0_WSTRB), 
+            .S_WLAST  (S_AXI_HP0_WLAST), 
+            .S_WVALID (S_AXI_HP0_WVALID),
+            .S_WREADY (S_AXI_HP0_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP0_BID),
+            .S_BRESP  (S_AXI_HP0_BRESP),
+            .S_BVALID (S_AXI_HP0_BVALID),
+            .S_BREADY (S_AXI_HP0_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP0_ARID),
+            .S_ARADDR  (S_AXI_HP0_ARADDR),
+            .S_ARLEN   (S_AXI_HP0_ARLEN),
+            .S_ARSIZE  (S_AXI_HP0_ARSIZE),
+            .S_ARBURST (S_AXI_HP0_ARBURST),
+            .S_ARLOCK  (S_AXI_HP0_ARLOCK),
+            .S_ARCACHE (S_AXI_HP0_ARCACHE),
+            .S_ARPROT  (S_AXI_HP0_ARPROT),
+            .S_ARVALID (S_AXI_HP0_ARVALID),
+            .S_ARREADY (S_AXI_HP0_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP0_RID),
+            .S_RDATA  (S_AXI_HP0_RDATA),
+            .S_RRESP  (S_AXI_HP0_RRESP),
+            .S_RLAST  (S_AXI_HP0_RLAST),
+            .S_RVALID (S_AXI_HP0_RVALID),
+            .S_RREADY (S_AXI_HP0_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP0_AWQOS), 
+            .S_ARQOS  (S_AXI_HP0_ARQOS), 
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP0_RCOUNT),
+            .S_WCOUNT (S_AXI_HP0_WCOUNT),
+            .S_RACOUNT (S_AXI_HP0_RACOUNT),
+            .S_WACOUNT (S_AXI_HP0_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
+            .WR_DATA  (net_wr_data_hp0), 
+            .WR_ADDR  (net_wr_addr_hp0), 
+            .WR_BYTES (net_wr_bytes_hp0), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp0), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp0), 
+            .WR_QOS (net_wr_qos_hp0),
+            .RD_REQ_DDR (net_rd_req_ddr_hp0),
+            .RD_REQ_OCM (net_rd_req_ocm_hp0),
+            .RD_ADDR (net_rd_addr_hp0),
+            .RD_DATA_DDR (net_rd_data_ddr_hp0),
+            .RD_DATA_OCM (net_rd_data_ocm_hp0),
+            .RD_BYTES (net_rd_bytes_hp0),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
+            .RD_QOS (net_rd_qos_hp0)
+ );
+
+/* AXI Slave HP1 */  
+ processing_system7_bfm_v2_0_5_afi_slave #( C_USE_S_AXI_HP1, // enable
+               axi_hp1_name, // name
+               C_S_AXI_HP1_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP1_BASEADDR, // slave base address
+               C_S_AXI_HP1_HIGHADDR, // Slave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
+            .S_ACLK   (S_AXI_HP1_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP1_AWID),
+            .S_AWADDR  (S_AXI_HP1_AWADDR),
+            .S_AWLEN   (S_AXI_HP1_AWLEN),
+            .S_AWSIZE  (S_AXI_HP1_AWSIZE),
+            .S_AWBURST (S_AXI_HP1_AWBURST),
+            .S_AWLOCK  (S_AXI_HP1_AWLOCK),
+            .S_AWCACHE (S_AXI_HP1_AWCACHE),
+            .S_AWPROT  (S_AXI_HP1_AWPROT),
+            .S_AWVALID (S_AXI_HP1_AWVALID),
+            .S_AWREADY (S_AXI_HP1_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP1_WID),
+            .S_WDATA  (S_AXI_HP1_WDATA),
+            .S_WSTRB  (S_AXI_HP1_WSTRB), 
+            .S_WLAST  (S_AXI_HP1_WLAST), 
+            .S_WVALID (S_AXI_HP1_WVALID),
+            .S_WREADY (S_AXI_HP1_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP1_BID),
+            .S_BRESP  (S_AXI_HP1_BRESP),
+            .S_BVALID (S_AXI_HP1_BVALID),
+            .S_BREADY (S_AXI_HP1_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP1_ARID),
+            .S_ARADDR  (S_AXI_HP1_ARADDR),
+            .S_ARLEN   (S_AXI_HP1_ARLEN),
+            .S_ARSIZE  (S_AXI_HP1_ARSIZE),
+            .S_ARBURST (S_AXI_HP1_ARBURST),
+            .S_ARLOCK  (S_AXI_HP1_ARLOCK),
+            .S_ARCACHE (S_AXI_HP1_ARCACHE),
+            .S_ARPROT  (S_AXI_HP1_ARPROT),
+            .S_ARVALID (S_AXI_HP1_ARVALID),
+            .S_ARREADY (S_AXI_HP1_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP1_RID),
+            .S_RDATA  (S_AXI_HP1_RDATA),
+            .S_RRESP  (S_AXI_HP1_RRESP),
+            .S_RLAST  (S_AXI_HP1_RLAST),
+            .S_RVALID (S_AXI_HP1_RVALID),
+            .S_RREADY (S_AXI_HP1_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP1_AWQOS), 
+            .S_ARQOS  (S_AXI_HP1_ARQOS), 
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP1_RCOUNT),
+            .S_WCOUNT (S_AXI_HP1_WCOUNT),
+            .S_RACOUNT (S_AXI_HP1_RACOUNT),
+            .S_WACOUNT (S_AXI_HP1_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
+            .WR_DATA  (net_wr_data_hp1), 
+            .WR_ADDR  (net_wr_addr_hp1), 
+            .WR_BYTES (net_wr_bytes_hp1), 
+            .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1), 
+            .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1), 
+            .WR_QOS (net_wr_qos_hp1),
+            .RD_REQ_DDR (net_rd_req_ddr_hp1),
+            .RD_REQ_OCM (net_rd_req_ocm_hp1),
+            .RD_ADDR (net_rd_addr_hp1),
+            .RD_DATA_DDR (net_rd_data_ddr_hp1),
+            .RD_DATA_OCM (net_rd_data_ocm_hp1),
+            .RD_BYTES (net_rd_bytes_hp1),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
+            .RD_QOS (net_rd_qos_hp1)
+
+  );
+
+/* AXI Slave HP2 */  
+ processing_system7_bfm_v2_0_5_afi_slave #( C_USE_S_AXI_HP2, // enable
+               axi_hp2_name, // name
+               C_S_AXI_HP2_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP2_BASEADDR, // slave base address
+               C_S_AXI_HP2_HIGHADDR, // SLave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
+            .S_ACLK    (S_AXI_HP2_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP2_AWID),
+            .S_AWADDR  (S_AXI_HP2_AWADDR),
+            .S_AWLEN   (S_AXI_HP2_AWLEN),
+            .S_AWSIZE  (S_AXI_HP2_AWSIZE),
+            .S_AWBURST (S_AXI_HP2_AWBURST),
+            .S_AWLOCK  (S_AXI_HP2_AWLOCK),
+            .S_AWCACHE (S_AXI_HP2_AWCACHE),
+            .S_AWPROT  (S_AXI_HP2_AWPROT),
+            .S_AWVALID (S_AXI_HP2_AWVALID),
+            .S_AWREADY (S_AXI_HP2_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP2_WID),
+            .S_WDATA  (S_AXI_HP2_WDATA),
+            .S_WSTRB  (S_AXI_HP2_WSTRB), 
+            .S_WLAST  (S_AXI_HP2_WLAST), 
+            .S_WVALID (S_AXI_HP2_WVALID),
+            .S_WREADY (S_AXI_HP2_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP2_BID),
+            .S_BRESP  (S_AXI_HP2_BRESP),
+            .S_BVALID (S_AXI_HP2_BVALID),
+            .S_BREADY (S_AXI_HP2_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP2_ARID),
+            .S_ARADDR  (S_AXI_HP2_ARADDR),
+            .S_ARLEN   (S_AXI_HP2_ARLEN),
+            .S_ARSIZE  (S_AXI_HP2_ARSIZE),
+            .S_ARBURST (S_AXI_HP2_ARBURST),
+            .S_ARLOCK  (S_AXI_HP2_ARLOCK),
+            .S_ARCACHE (S_AXI_HP2_ARCACHE),
+            .S_ARPROT  (S_AXI_HP2_ARPROT),
+            .S_ARVALID (S_AXI_HP2_ARVALID),
+            .S_ARREADY (S_AXI_HP2_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP2_RID),
+            .S_RDATA  (S_AXI_HP2_RDATA),
+            .S_RRESP  (S_AXI_HP2_RRESP),
+            .S_RLAST  (S_AXI_HP2_RLAST),
+            .S_RVALID (S_AXI_HP2_RVALID),
+            .S_RREADY (S_AXI_HP2_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP2_AWQOS), 
+            .S_ARQOS  (S_AXI_HP2_ARQOS), 
+             // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP2_RCOUNT),
+            .S_WCOUNT (S_AXI_HP2_WCOUNT),
+            .S_RACOUNT (S_AXI_HP2_RACOUNT),
+            .S_WACOUNT (S_AXI_HP2_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
+            .WR_DATA  (net_wr_data_hp2), 
+            .WR_ADDR  (net_wr_addr_hp2), 
+            .WR_BYTES (net_wr_bytes_hp2), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp2), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp2), 
+            .WR_QOS (net_wr_qos_hp2),
+            .RD_REQ_DDR (net_rd_req_ddr_hp2),
+            .RD_REQ_OCM (net_rd_req_ocm_hp2),
+            .RD_ADDR (net_rd_addr_hp2),
+            .RD_DATA_DDR (net_rd_data_ddr_hp2),
+            .RD_DATA_OCM (net_rd_data_ocm_hp2),
+            .RD_BYTES (net_rd_bytes_hp2),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
+            .RD_QOS (net_rd_qos_hp2)
+
+ );
+
+/* AXI Slave HP3 */  
+ processing_system7_bfm_v2_0_5_afi_slave #( C_USE_S_AXI_HP3, // enable
+               axi_hp3_name, // name
+               C_S_AXI_HP3_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP3_BASEADDR, // slave base address
+               C_S_AXI_HP3_HIGHADDR, // SLave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
+            .S_ACLK   (S_AXI_HP3_ACLK),
+            // Write ADDRESS CHANNEL
+            .S_AWID    (S_AXI_HP3_AWID),
+            .S_AWADDR  (S_AXI_HP3_AWADDR),
+            .S_AWLEN   (S_AXI_HP3_AWLEN),
+            .S_AWSIZE  (S_AXI_HP3_AWSIZE),
+            .S_AWBURST (S_AXI_HP3_AWBURST),
+            .S_AWLOCK  (S_AXI_HP3_AWLOCK),
+            .S_AWCACHE (S_AXI_HP3_AWCACHE),
+            .S_AWPROT  (S_AXI_HP3_AWPROT),
+            .S_AWVALID (S_AXI_HP3_AWVALID),
+            .S_AWREADY (S_AXI_HP3_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP3_WID),
+            .S_WDATA  (S_AXI_HP3_WDATA),
+            .S_WSTRB  (S_AXI_HP3_WSTRB), 
+            .S_WLAST  (S_AXI_HP3_WLAST), 
+            .S_WVALID (S_AXI_HP3_WVALID),
+            .S_WREADY (S_AXI_HP3_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP3_BID),
+            .S_BRESP  (S_AXI_HP3_BRESP),
+            .S_BVALID (S_AXI_HP3_BVALID),
+            .S_BREADY (S_AXI_HP3_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP3_ARID),
+            .S_ARADDR  (S_AXI_HP3_ARADDR),
+            .S_ARLEN   (S_AXI_HP3_ARLEN),
+            .S_ARSIZE  (S_AXI_HP3_ARSIZE),
+            .S_ARBURST (S_AXI_HP3_ARBURST),
+            .S_ARLOCK  (S_AXI_HP3_ARLOCK),
+            .S_ARCACHE (S_AXI_HP3_ARCACHE),
+            .S_ARPROT  (S_AXI_HP3_ARPROT),
+            .S_ARVALID (S_AXI_HP3_ARVALID),
+            .S_ARREADY (S_AXI_HP3_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP3_RID),
+            .S_RDATA  (S_AXI_HP3_RDATA),
+            .S_RRESP  (S_AXI_HP3_RRESP),
+            .S_RLAST  (S_AXI_HP3_RLAST),
+            .S_RVALID (S_AXI_HP3_RVALID),
+            .S_RREADY (S_AXI_HP3_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP3_AWQOS), 
+            .S_ARQOS  (S_AXI_HP3_ARQOS),
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP3_RCOUNT),
+            .S_WCOUNT (S_AXI_HP3_WCOUNT),
+            .S_RACOUNT (S_AXI_HP3_RACOUNT),
+            .S_WACOUNT (S_AXI_HP3_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
+            .WR_DATA  (net_wr_data_hp3), 
+            .WR_ADDR  (net_wr_addr_hp3), 
+            .WR_BYTES (net_wr_bytes_hp3), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp3), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp3), 
+            .WR_QOS (net_wr_qos_hp3),
+            .RD_REQ_DDR (net_rd_req_ddr_hp3),
+            .RD_REQ_OCM (net_rd_req_ocm_hp3),
+            .RD_ADDR (net_rd_addr_hp3),
+            .RD_DATA_DDR (net_rd_data_ddr_hp3),
+            .RD_DATA_OCM (net_rd_data_ocm_hp3),
+            .RD_BYTES (net_rd_bytes_hp3),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
+            .RD_QOS (net_rd_qos_hp3)
+ );
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:57:55 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top design_1_auto_pc_0 -prefix
+//               design_1_auto_pc_0_ design_1_auto_pc_0_sim_netlist.v
+// Design      : design_1_auto_pc_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* C_AXI_ADDR_WIDTH = ""32"" *) (* C_AXI_ARUSER_WIDTH = ""1"" *) (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+(* C_AXI_BUSER_WIDTH = ""1"" *) (* C_AXI_DATA_WIDTH = ""32"" *) (* C_AXI_ID_WIDTH = ""12"" *) 
+(* C_AXI_RUSER_WIDTH = ""1"" *) (* C_AXI_SUPPORTS_READ = ""1"" *) (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+(* C_AXI_SUPPORTS_WRITE = ""1"" *) (* C_AXI_WUSER_WIDTH = ""1"" *) (* C_FAMILY = ""zynq"" *) 
+(* C_IGNORE_ID = ""0"" *) (* C_M_AXI_PROTOCOL = ""2"" *) (* C_S_AXI_PROTOCOL = ""1"" *) 
+(* C_TRANSLATION_MODE = ""2"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* P_AXI3 = ""1"" *) 
+(* P_AXI4 = ""0"" *) (* P_AXILITE = ""2"" *) (* P_AXILITE_SIZE = ""3\'b010"" *) 
+(* P_CONVERSION = ""2"" *) (* P_DECERR = ""2\'b11"" *) (* P_INCR = ""2\'b01"" *) 
+(* P_PROTECTION = ""1"" *) (* P_SLVERR = ""2\'b10"" *) 
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awregion,
+    s_axi_awqos,
+    s_axi_awuser,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wuser,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_buser,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arregion,
+    s_axi_arqos,
+    s_axi_aruser,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_ruser,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awid,
+    m_axi_awaddr,
+    m_axi_awlen,
+    m_axi_awsize,
+    m_axi_awburst,
+    m_axi_awlock,
+    m_axi_awcache,
+    m_axi_awprot,
+    m_axi_awregion,
+    m_axi_awqos,
+    m_axi_awuser,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wid,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wlast,
+    m_axi_wuser,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bid,
+    m_axi_bresp,
+    m_axi_buser,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_arid,
+    m_axi_araddr,
+    m_axi_arlen,
+    m_axi_arsize,
+    m_axi_arburst,
+    m_axi_arlock,
+    m_axi_arcache,
+    m_axi_arprot,
+    m_axi_arregion,
+    m_axi_arqos,
+    m_axi_aruser,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rlast,
+    m_axi_ruser,
+    m_axi_rvalid,
+    m_axi_rready);
+  input aclk;
+  input aresetn;
+  input [11:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [3:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awregion;
+  input [3:0]s_axi_awqos;
+  input [0:0]s_axi_awuser;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [11:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wlast;
+  input [0:0]s_axi_wuser;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [11:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_buser;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [11:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [3:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arregion;
+  input [3:0]s_axi_arqos;
+  input [0:0]s_axi_aruser;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [11:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rlast;
+  output [0:0]s_axi_ruser;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output [11:0]m_axi_awid;
+  output [31:0]m_axi_awaddr;
+  output [7:0]m_axi_awlen;
+  output [2:0]m_axi_awsize;
+  output [1:0]m_axi_awburst;
+  output [0:0]m_axi_awlock;
+  output [3:0]m_axi_awcache;
+  output [2:0]m_axi_awprot;
+  output [3:0]m_axi_awregion;
+  output [3:0]m_axi_awqos;
+  output [0:0]m_axi_awuser;
+  output m_axi_awvalid;
+  input m_axi_awready;
+  output [11:0]m_axi_wid;
+  output [31:0]m_axi_wdata;
+  output [3:0]m_axi_wstrb;
+  output m_axi_wlast;
+  output [0:0]m_axi_wuser;
+  output m_axi_wvalid;
+  input m_axi_wready;
+  input [11:0]m_axi_bid;
+  input [1:0]m_axi_bresp;
+  input [0:0]m_axi_buser;
+  input m_axi_bvalid;
+  output m_axi_bready;
+  output [11:0]m_axi_arid;
+  output [31:0]m_axi_araddr;
+  output [7:0]m_axi_arlen;
+  output [2:0]m_axi_arsize;
+  output [1:0]m_axi_arburst;
+  output [0:0]m_axi_arlock;
+  output [3:0]m_axi_arcache;
+  output [2:0]m_axi_arprot;
+  output [3:0]m_axi_arregion;
+  output [3:0]m_axi_arqos;
+  output [0:0]m_axi_aruser;
+  output m_axi_arvalid;
+  input m_axi_arready;
+  input [11:0]m_axi_rid;
+  input [31:0]m_axi_rdata;
+  input [1:0]m_axi_rresp;
+  input m_axi_rlast;
+  input [0:0]m_axi_ruser;
+  input m_axi_rvalid;
+  output m_axi_rready;
+
+  wire \\<const0> ;
+  wire \\<const1> ;
+  wire aclk;
+  wire aresetn;
+  wire [31:0]m_axi_araddr;
+  wire [2:0]m_axi_arprot;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire [31:0]m_axi_awaddr;
+  wire [2:0]m_axi_awprot;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire m_axi_bready;
+  wire [1:0]m_axi_bresp;
+  wire m_axi_bvalid;
+  wire [31:0]m_axi_rdata;
+  wire m_axi_rready;
+  wire [1:0]m_axi_rresp;
+  wire m_axi_rvalid;
+  wire m_axi_wready;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [2:0]s_axi_arprot;
+  wire s_axi_arready;
+  wire [2:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [2:0]s_axi_awprot;
+  wire s_axi_awready;
+  wire [2:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire [11:0]s_axi_bid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [11:0]s_axi_rid;
+  wire s_axi_rlast;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+
+  assign m_axi_arburst[1] = \\<const0> ;
+  assign m_axi_arburst[0] = \\<const1> ;
+  assign m_axi_arcache[3] = \\<const0> ;
+  assign m_axi_arcache[2] = \\<const0> ;
+  assign m_axi_arcache[1] = \\<const0> ;
+  assign m_axi_arcache[0] = \\<const0> ;
+  assign m_axi_arid[11] = \\<const0> ;
+  assign m_axi_arid[10] = \\<const0> ;
+  assign m_axi_arid[9] = \\<const0> ;
+  assign m_axi_arid[8] = \\<const0> ;
+  assign m_axi_arid[7] = \\<const0> ;
+  assign m_axi_arid[6] = \\<const0> ;
+  assign m_axi_arid[5] = \\<const0> ;
+  assign m_axi_arid[4] = \\<const0> ;
+  assign m_axi_arid[3] = \\<const0> ;
+  assign m_axi_arid[2] = \\<const0> ;
+  assign m_axi_arid[1] = \\<const0> ;
+  assign m_axi_arid[0] = \\<const0> ;
+  assign m_axi_arlen[7] = \\<const0> ;
+  assign m_axi_arlen[6] = \\<const0> ;
+  assign m_axi_arlen[5] = \\<const0> ;
+  assign m_axi_arlen[4] = \\<const0> ;
+  assign m_axi_arlen[3] = \\<const0> ;
+  assign m_axi_arlen[2] = \\<const0> ;
+  assign m_axi_arlen[1] = \\<const0> ;
+  assign m_axi_arlen[0] = \\<const0> ;
+  assign m_axi_arlock[0] = \\<const0> ;
+  assign m_axi_arqos[3] = \\<const0> ;
+  assign m_axi_arqos[2] = \\<const0> ;
+  assign m_axi_arqos[1] = \\<const0> ;
+  assign m_axi_arqos[0] = \\<const0> ;
+  assign m_axi_arregion[3] = \\<const0> ;
+  assign m_axi_arregion[2] = \\<const0> ;
+  assign m_axi_arregion[1] = \\<const0> ;
+  assign m_axi_arregion[0] = \\<const0> ;
+  assign m_axi_arsize[2] = \\<const0> ;
+  assign m_axi_arsize[1] = \\<const1> ;
+  assign m_axi_arsize[0] = \\<const0> ;
+  assign m_axi_aruser[0] = \\<const0> ;
+  assign m_axi_awburst[1] = \\<const0> ;
+  assign m_axi_awburst[0] = \\<const1> ;
+  assign m_axi_awcache[3] = \\<const0> ;
+  assign m_axi_awcache[2] = \\<const0> ;
+  assign m_axi_awcache[1] = \\<const0> ;
+  assign m_axi_awcache[0] = \\<const0> ;
+  assign m_axi_awid[11] = \\<const0> ;
+  assign m_axi_awid[10] = \\<const0> ;
+  assign m_axi_awid[9] = \\<const0> ;
+  assign m_axi_awid[8] = \\<const0> ;
+  assign m_axi_awid[7] = \\<const0> ;
+  assign m_axi_awid[6] = \\<const0> ;
+  assign m_axi_awid[5] = \\<const0> ;
+  assign m_axi_awid[4] = \\<const0> ;
+  assign m_axi_awid[3] = \\<const0> ;
+  assign m_axi_awid[2] = \\<const0> ;
+  assign m_axi_awid[1] = \\<const0> ;
+  assign m_axi_awid[0] = \\<const0> ;
+  assign m_axi_awlen[7] = \\<const0> ;
+  assign m_axi_awlen[6] = \\<const0> ;
+  assign m_axi_awlen[5] = \\<const0> ;
+  assign m_axi_awlen[4] = \\<const0> ;
+  assign m_axi_awlen[3] = \\<const0> ;
+  assign m_axi_awlen[2] = \\<const0> ;
+  assign m_axi_awlen[1] = \\<const0> ;
+  assign m_axi_awlen[0] = \\<const0> ;
+  assign m_axi_awlock[0] = \\<const0> ;
+  assign m_axi_awqos[3] = \\<const0> ;
+  assign m_axi_awqos[2] = \\<const0> ;
+  assign m_axi_awqos[1] = \\<const0> ;
+  assign m_axi_awqos[0] = \\<const0> ;
+  assign m_axi_awregion[3] = \\<const0> ;
+  assign m_axi_awregion[2] = \\<const0> ;
+  assign m_axi_awregion[1] = \\<const0> ;
+  assign m_axi_awregion[0] = \\<const0> ;
+  assign m_axi_awsize[2] = \\<const0> ;
+  assign m_axi_awsize[1] = \\<const1> ;
+  assign m_axi_awsize[0] = \\<const0> ;
+  assign m_axi_awuser[0] = \\<const0> ;
+  assign m_axi_wdata[31:0] = s_axi_wdata;
+  assign m_axi_wid[11] = \\<const0> ;
+  assign m_axi_wid[10] = \\<const0> ;
+  assign m_axi_wid[9] = \\<const0> ;
+  assign m_axi_wid[8] = \\<const0> ;
+  assign m_axi_wid[7] = \\<const0> ;
+  assign m_axi_wid[6] = \\<const0> ;
+  assign m_axi_wid[5] = \\<const0> ;
+  assign m_axi_wid[4] = \\<const0> ;
+  assign m_axi_wid[3] = \\<const0> ;
+  assign m_axi_wid[2] = \\<const0> ;
+  assign m_axi_wid[1] = \\<const0> ;
+  assign m_axi_wid[0] = \\<const0> ;
+  assign m_axi_wlast = \\<const1> ;
+  assign m_axi_wstrb[3:0] = s_axi_wstrb;
+  assign m_axi_wuser[0] = \\<const0> ;
+  assign m_axi_wvalid = s_axi_wvalid;
+  assign s_axi_buser[0] = \\<const0> ;
+  assign s_axi_ruser[0] = \\<const0> ;
+  assign s_axi_wready = m_axi_wready;
+  GND GND
+       (.G(\\<const0> ));
+  VCC VCC
+       (.P(\\<const1> ));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s \\gen_axilite.gen_b2s_conv.axilite_b2s 
+       (.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .in({m_axi_rresp,m_axi_rdata}),
+        .m_axi_araddr(m_axi_araddr[11:0]),
+        .\\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr[11:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rvalid(m_axi_rvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize(s_axi_arsize[1:0]),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize(s_axi_awsize[1:0]),
+        .s_axi_awvalid(s_axi_awvalid),
+        .\\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s
+   (s_axi_rvalid,
+    s_axi_awready,
+    Q,
+    s_axi_arready,
+    \\m_axi_arprot[2] ,
+    s_axi_bvalid,
+    \\s_axi_bid[11] ,
+    \\s_axi_rid[11] ,
+    m_axi_awvalid,
+    m_axi_bready,
+    m_axi_arvalid,
+    m_axi_rready,
+    m_axi_awaddr,
+    m_axi_araddr,
+    m_axi_arready,
+    s_axi_rready,
+    aclk,
+    in,
+    s_axi_awid,
+    s_axi_awlen,
+    s_axi_awburst,
+    s_axi_awsize,
+    s_axi_awprot,
+    s_axi_awaddr,
+    m_axi_bresp,
+    s_axi_arid,
+    s_axi_arlen,
+    s_axi_arburst,
+    s_axi_arsize,
+    s_axi_arprot,
+    s_axi_araddr,
+    m_axi_awready,
+    s_axi_awvalid,
+    m_axi_bvalid,
+    m_axi_rvalid,
+    s_axi_bready,
+    s_axi_arvalid,
+    aresetn);
+  output s_axi_rvalid;
+  output s_axi_awready;
+  output [22:0]Q;
+  output s_axi_arready;
+  output [22:0]\\m_axi_arprot[2] ;
+  output s_axi_bvalid;
+  output [13:0]\\s_axi_bid[11] ;
+  output [46:0]\\s_axi_rid[11] ;
+  output m_axi_awvalid;
+  output m_axi_bready;
+  output m_axi_arvalid;
+  output m_axi_rready;
+  output [11:0]m_axi_awaddr;
+  output [11:0]m_axi_araddr;
+  input m_axi_arready;
+  input s_axi_rready;
+  input aclk;
+  input [33:0]in;
+  input [11:0]s_axi_awid;
+  input [3:0]s_axi_awlen;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awsize;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_awaddr;
+  input [1:0]m_axi_bresp;
+  input [11:0]s_axi_arid;
+  input [3:0]s_axi_arlen;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arsize;
+  input [2:0]s_axi_arprot;
+  input [31:0]s_axi_araddr;
+  input m_axi_awready;
+  input s_axi_awvalid;
+  input m_axi_bvalid;
+  input m_axi_rvalid;
+  input s_axi_bready;
+  input s_axi_arvalid;
+  input aresetn;
+
+  wire [11:4]C;
+  wire [22:0]Q;
+  wire \\RD.ar_channel_0_n_14 ;
+  wire \\RD.ar_channel_0_n_15 ;
+  wire \\RD.ar_channel_0_n_44 ;
+  wire \\RD.ar_channel_0_n_45 ;
+  wire \\RD.ar_channel_0_n_46 ;
+  wire \\RD.ar_channel_0_n_47 ;
+  wire \\RD.ar_channel_0_n_5 ;
+  wire \\RD.r_channel_0_n_0 ;
+  wire \\RD.r_channel_0_n_1 ;
+  wire SI_REG_n_10;
+  wire SI_REG_n_132;
+  wire SI_REG_n_133;
+  wire SI_REG_n_134;
+  wire SI_REG_n_135;
+  wire SI_REG_n_136;
+  wire SI_REG_n_137;
+  wire SI_REG_n_138;
+  wire SI_REG_n_139;
+  wire SI_REG_n_140;
+  wire SI_REG_n_141;
+  wire SI_REG_n_142;
+  wire SI_REG_n_143;
+  wire SI_REG_n_144;
+  wire SI_REG_n_145;
+  wire SI_REG_n_146;
+  wire SI_REG_n_147;
+  wire SI_REG_n_148;
+  wire SI_REG_n_149;
+  wire SI_REG_n_154;
+  wire SI_REG_n_155;
+  wire SI_REG_n_157;
+  wire SI_REG_n_160;
+  wire SI_REG_n_164;
+  wire SI_REG_n_165;
+  wire SI_REG_n_166;
+  wire SI_REG_n_167;
+  wire SI_REG_n_168;
+  wire SI_REG_n_169;
+  wire SI_REG_n_170;
+  wire SI_REG_n_171;
+  wire SI_REG_n_172;
+  wire SI_REG_n_173;
+  wire SI_REG_n_174;
+  wire SI_REG_n_175;
+  wire SI_REG_n_176;
+  wire SI_REG_n_177;
+  wire SI_REG_n_178;
+  wire SI_REG_n_179;
+  wire SI_REG_n_180;
+  wire SI_REG_n_181;
+  wire SI_REG_n_182;
+  wire SI_REG_n_183;
+  wire SI_REG_n_184;
+  wire \\WR.aw_channel_0_n_47 ;
+  wire \\WR.aw_channel_0_n_48 ;
+  wire \\WR.aw_channel_0_n_49 ;
+  wire \\WR.aw_channel_0_n_50 ;
+  wire \\WR.aw_channel_0_n_7 ;
+  wire \\WR.b_channel_0_n_1 ;
+  wire \\WR.b_channel_0_n_2 ;
+  wire \\WR.b_channel_0_n_3 ;
+  wire aclk;
+  wire \\ar_pipe/m_valid_i0 ;
+  wire \\ar_pipe/p_1_in ;
+  wire areset_d1;
+  wire areset_d1_i_1_n_0;
+  wire aresetn;
+  wire [1:0]\\aw_cmd_fsm_0/state ;
+  wire \\aw_pipe/p_1_in ;
+  wire [11:0]b_awid;
+  wire [3:0]b_awlen;
+  wire b_push;
+  wire [3:0]\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ;
+  wire [3:0]\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ;
+  wire \\cmd_translator_0/incr_cmd_0/sel_first ;
+  wire \\cmd_translator_0/incr_cmd_0/sel_first_4 ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
+  wire [3:1]\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ;
+  wire [2:1]\\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
+  wire [2:0]\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ;
+  wire [33:0]in;
+  wire [11:0]m_axi_araddr;
+  wire [22:0]\\m_axi_arprot[2] ;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire [11:0]m_axi_awaddr;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire m_axi_bready;
+  wire [1:0]m_axi_bresp;
+  wire m_axi_bvalid;
+  wire m_axi_rready;
+  wire m_axi_rvalid;
+  wire r_push;
+  wire r_rlast;
+  wire [11:0]s_arid;
+  wire [11:0]s_arid_r;
+  wire [11:0]s_awid;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [2:0]s_axi_arprot;
+  wire s_axi_arready;
+  wire [1:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [2:0]s_axi_awprot;
+  wire s_axi_awready;
+  wire [1:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire [13:0]\\s_axi_bid[11] ;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [46:0]\\s_axi_rid[11] ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire shandshake;
+  wire [11:0]si_rs_araddr;
+  wire [1:1]si_rs_arburst;
+  wire [3:0]si_rs_arlen;
+  wire [1:0]si_rs_arsize;
+  wire si_rs_arvalid;
+  wire [11:0]si_rs_awaddr;
+  wire [1:1]si_rs_awburst;
+  wire [3:0]si_rs_awlen;
+  wire [1:0]si_rs_awsize;
+  wire si_rs_awvalid;
+  wire [11:0]si_rs_bid;
+  wire si_rs_bready;
+  wire [1:0]si_rs_bresp;
+  wire si_rs_bvalid;
+  wire [31:0]si_rs_rdata;
+  wire [11:0]si_rs_rid;
+  wire si_rs_rlast;
+  wire si_rs_rready;
+  wire [1:0]si_rs_rresp;
+  wire [3:0]wrap_cnt;
+
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel \\RD.ar_channel_0 
+       (.CO(SI_REG_n_145),
+        .D(\\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
+        .E(\\ar_pipe/p_1_in ),
+        .O({SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149}),
+        .Q(\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
+        .S({\\RD.ar_channel_0_n_44 ,\\RD.ar_channel_0_n_45 ,\\RD.ar_channel_0_n_46 ,\\RD.ar_channel_0_n_47 }),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\axaddr_incr_reg[3] (\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
+        .axaddr_offset(\\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
+        .\\axaddr_offset_r_reg[3] (\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
+        .\\axaddr_offset_r_reg[3]_0 (SI_REG_n_160),
+        .\\cnt_read_reg[1]_rep__0 (\\RD.r_channel_0_n_1 ),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .\\m_payload_i_reg[0] (\\RD.ar_channel_0_n_14 ),
+        .\\m_payload_i_reg[0]_0 (\\RD.ar_channel_0_n_15 ),
+        .\\m_payload_i_reg[11] ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
+        .\\m_payload_i_reg[35] (SI_REG_n_164),
+        .\\m_payload_i_reg[35]_0 (SI_REG_n_165),
+        .\\m_payload_i_reg[38] (SI_REG_n_184),
+        .\\m_payload_i_reg[3] (SI_REG_n_175),
+        .\\m_payload_i_reg[3]_0 ({SI_REG_n_137,SI_REG_n_138,SI_REG_n_139,SI_REG_n_140}),
+        .\\m_payload_i_reg[44] (SI_REG_n_166),
+        .\\m_payload_i_reg[47] (SI_REG_n_167),
+        .\\m_payload_i_reg[47]_0 (\\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
+        .\\m_payload_i_reg[61] ({s_arid,si_rs_arlen,si_rs_arburst,si_rs_arsize,si_rs_araddr}),
+        .\\m_payload_i_reg[6] ({SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174}),
+        .m_valid_i0(\\ar_pipe/m_valid_i0 ),
+        .\\r_arid_r_reg[11] (s_arid_r),
+        .r_push(r_push),
+        .r_rlast(r_rlast),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_ready_i_reg(s_axi_arready),
+        .sel_first(\\cmd_translator_0/incr_cmd_0/sel_first ),
+        .si_rs_arvalid(si_rs_arvalid),
+        .\\wrap_boundary_axaddr_r_reg[11] (\\RD.ar_channel_0_n_5 ),
+        .\\wrap_second_len_r_reg[0] (SI_REG_n_157));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel \\RD.r_channel_0 
+       (.D(s_arid_r),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .in(in),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_valid_i_reg(\\RD.r_channel_0_n_0 ),
+        .out({si_rs_rresp,si_rs_rdata}),
+        .r_push(r_push),
+        .r_rlast(r_rlast),
+        .si_rs_rready(si_rs_rready),
+        .\\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
+        .\\state_reg[1]_rep (\\RD.r_channel_0_n_1 ));
+  design_1_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice SI_REG
+       (.CO(SI_REG_n_132),
+        .D({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}),
+        .E(\\aw_pipe/p_1_in ),
+        .O({SI_REG_n_133,SI_REG_n_134,SI_REG_n_135,SI_REG_n_136}),
+        .Q({s_awid,si_rs_awlen,si_rs_awburst,si_rs_awsize,Q,si_rs_awaddr}),
+        .S({\\WR.aw_channel_0_n_47 ,\\WR.aw_channel_0_n_48 ,\\WR.aw_channel_0_n_49 ,\\WR.aw_channel_0_n_50 }),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .axaddr_incr_reg(\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
+        .\\axaddr_incr_reg[11] (C),
+        .\\axaddr_incr_reg[11]_0 ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
+        .\\axaddr_incr_reg[3] ({SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149}),
+        .\\axaddr_incr_reg[3]_0 (\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
+        .\\axaddr_incr_reg[7] ({SI_REG_n_137,SI_REG_n_138,SI_REG_n_139,SI_REG_n_140}),
+        .\\axaddr_incr_reg[7]_0 (SI_REG_n_145),
+        .axaddr_offset(\\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
+        .axaddr_offset_0(\\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
+        .\\axaddr_offset_r_reg[0] (SI_REG_n_175),
+        .\\axaddr_offset_r_reg[1] (SI_REG_n_164),
+        .\\axaddr_offset_r_reg[3] (\\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
+        .\\axaddr_offset_r_reg[3]_0 (\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
+        .\\axaddr_offset_r_reg[3]_1 (\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
+        .\\axlen_cnt_reg[3] (SI_REG_n_154),
+        .\\axlen_cnt_reg[3]_0 (SI_REG_n_167),
+        .b_push(b_push),
+        .\\cnt_read_reg[3]_rep__2 (\\RD.r_channel_0_n_0 ),
+        .\\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
+        .\\m_axi_araddr[10] (SI_REG_n_184),
+        .\\m_axi_awaddr[10] (SI_REG_n_183),
+        .\\m_payload_i_reg[3] ({\\RD.ar_channel_0_n_44 ,\\RD.ar_channel_0_n_45 ,\\RD.ar_channel_0_n_46 ,\\RD.ar_channel_0_n_47 }),
+        .m_valid_i0(\\ar_pipe/m_valid_i0 ),
+        .next_pending_r_reg(SI_REG_n_155),
+        .next_pending_r_reg_0(SI_REG_n_166),
+        .out(si_rs_bid),
+        .r_push_r_reg({si_rs_rid,si_rs_rlast}),
+        .\\s_arid_r_reg[11] ({s_arid,si_rs_arlen,si_rs_arburst,si_rs_arsize,\\m_axi_arprot[2] ,si_rs_araddr}),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize(s_axi_arsize),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize(s_axi_awsize),
+        .s_axi_awvalid(s_axi_awvalid),
+        .\\s_axi_bid[11] (\\s_axi_bid[11] ),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rid[11] (\\s_axi_rid[11] ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .\\s_bresp_acc_reg[1] (si_rs_bresp),
+        .sel_first(\\cmd_translator_0/incr_cmd_0/sel_first_4 ),
+        .sel_first_1(\\cmd_translator_0/incr_cmd_0/sel_first ),
+        .shandshake(shandshake),
+        .si_rs_arvalid(si_rs_arvalid),
+        .si_rs_awvalid(si_rs_awvalid),
+        .si_rs_bready(si_rs_bready),
+        .si_rs_bvalid(si_rs_bvalid),
+        .si_rs_rready(si_rs_rready),
+        .\\state_reg[0]_rep (\\RD.ar_channel_0_n_15 ),
+        .\\state_reg[1] (\\WR.aw_channel_0_n_7 ),
+        .\\state_reg[1]_0 (\\aw_cmd_fsm_0/state ),
+        .\\state_reg[1]_rep (\\RD.ar_channel_0_n_5 ),
+        .\\state_reg[1]_rep_0 (\\RD.ar_channel_0_n_14 ),
+        .\\state_reg[1]_rep_1 (\\ar_pipe/p_1_in ),
+        .\\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174}),
+        .\\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
+        .\\wrap_cnt_r_reg[2] (SI_REG_n_157),
+        .\\wrap_cnt_r_reg[2]_0 (SI_REG_n_160),
+        .wrap_second_len(\\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
+        .\\wrap_second_len_r_reg[2] (\\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
+        .\\wrap_second_len_r_reg[2]_0 (\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
+        .\\wrap_second_len_r_reg[3] (SI_REG_n_165),
+        .\\wrap_second_len_r_reg[3]_0 (\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel \\WR.aw_channel_0 
+       (.CO(SI_REG_n_132),
+        .D(\\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
+        .E(\\aw_pipe/p_1_in ),
+        .O({SI_REG_n_133,SI_REG_n_134,SI_REG_n_135,SI_REG_n_136}),
+        .Q(\\aw_cmd_fsm_0/state ),
+        .S({\\WR.aw_channel_0_n_47 ,\\WR.aw_channel_0_n_48 ,\\WR.aw_channel_0_n_49 ,\\WR.aw_channel_0_n_50 }),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\axaddr_incr_reg[3] (\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
+        .\\axaddr_offset_r_reg[3] (\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
+        .b_push(b_push),
+        .\\cnt_read_reg[0]_rep__0 (\\WR.b_channel_0_n_1 ),
+        .\\cnt_read_reg[1]_rep__0 (\\WR.b_channel_0_n_3 ),
+        .\\cnt_read_reg[1]_rep__0_0 (\\WR.b_channel_0_n_2 ),
+        .in({b_awid,b_awlen}),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .\\m_payload_i_reg[11] (C),
+        .\\m_payload_i_reg[38] (SI_REG_n_183),
+        .\\m_payload_i_reg[46] (SI_REG_n_155),
+        .\\m_payload_i_reg[47] (SI_REG_n_154),
+        .\\m_payload_i_reg[61] ({s_awid,si_rs_awlen,si_rs_awburst,si_rs_awsize,si_rs_awaddr}),
+        .\\m_payload_i_reg[6] ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
+        .sel_first(\\cmd_translator_0/incr_cmd_0/sel_first_4 ),
+        .si_rs_awvalid(si_rs_awvalid),
+        .\\wrap_boundary_axaddr_r_reg[0] (\\WR.aw_channel_0_n_7 ),
+        .\\wrap_second_len_r_reg[3] (\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ),
+        .\\wrap_second_len_r_reg[3]_0 (\\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
+        .\\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel \\WR.b_channel_0 
+       (.aclk(aclk),
+        .areset_d1(areset_d1),
+        .b_push(b_push),
+        .\\cnt_read_reg[0]_rep__0 (\\WR.b_channel_0_n_1 ),
+        .\\cnt_read_reg[1]_rep__0 (\\WR.b_channel_0_n_2 ),
+        .in({b_awid,b_awlen}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .out(si_rs_bid),
+        .shandshake(shandshake),
+        .si_rs_bready(si_rs_bready),
+        .si_rs_bvalid(si_rs_bvalid),
+        .\\skid_buffer_reg[1] (si_rs_bresp),
+        .\\state_reg[0] (\\WR.b_channel_0_n_3 ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    areset_d1_i_1
+       (.I0(aresetn),
+        .O(areset_d1_i_1_n_0));
+  FDRE areset_d1_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(areset_d1_i_1_n_0),
+        .Q(areset_d1),
+        .R(1\'b0));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel
+   (\\axaddr_incr_reg[3] ,
+    sel_first,
+    \\wrap_boundary_axaddr_r_reg[11] ,
+    Q,
+    axaddr_offset,
+    \\axaddr_offset_r_reg[3] ,
+    r_push,
+    \\m_payload_i_reg[0] ,
+    \\m_payload_i_reg[0]_0 ,
+    m_axi_arvalid,
+    r_rlast,
+    m_valid_i0,
+    E,
+    m_axi_araddr,
+    \\r_arid_r_reg[11] ,
+    S,
+    aclk,
+    O,
+    \\m_payload_i_reg[47] ,
+    m_axi_arready,
+    si_rs_arvalid,
+    \\axaddr_offset_r_reg[3]_0 ,
+    \\m_payload_i_reg[61] ,
+    CO,
+    \\cnt_read_reg[1]_rep__0 ,
+    D,
+    \\m_payload_i_reg[35] ,
+    \\m_payload_i_reg[47]_0 ,
+    \\m_payload_i_reg[35]_0 ,
+    \\m_payload_i_reg[3] ,
+    \\m_payload_i_reg[44] ,
+    areset_d1,
+    \\m_payload_i_reg[3]_0 ,
+    \\m_payload_i_reg[11] ,
+    s_axi_arvalid,
+    s_ready_i_reg,
+    \\m_payload_i_reg[38] ,
+    \\wrap_second_len_r_reg[0] ,
+    \\m_payload_i_reg[6] );
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output sel_first;
+  output \\wrap_boundary_axaddr_r_reg[11] ;
+  output [2:0]Q;
+  output [0:0]axaddr_offset;
+  output [2:0]\\axaddr_offset_r_reg[3] ;
+  output r_push;
+  output \\m_payload_i_reg[0] ;
+  output \\m_payload_i_reg[0]_0 ;
+  output m_axi_arvalid;
+  output r_rlast;
+  output m_valid_i0;
+  output [0:0]E;
+  output [11:0]m_axi_araddr;
+  output [11:0]\\r_arid_r_reg[11] ;
+  output [3:0]S;
+  input aclk;
+  input [3:0]O;
+  input \\m_payload_i_reg[47] ;
+  input m_axi_arready;
+  input si_rs_arvalid;
+  input \\axaddr_offset_r_reg[3]_0 ;
+  input [30:0]\\m_payload_i_reg[61] ;
+  input [0:0]CO;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input [1:0]D;
+  input \\m_payload_i_reg[35] ;
+  input [2:0]\\m_payload_i_reg[47]_0 ;
+  input \\m_payload_i_reg[35]_0 ;
+  input \\m_payload_i_reg[3] ;
+  input \\m_payload_i_reg[44] ;
+  input areset_d1;
+  input [3:0]\\m_payload_i_reg[3]_0 ;
+  input [3:0]\\m_payload_i_reg[11] ;
+  input s_axi_arvalid;
+  input s_ready_i_reg;
+  input \\m_payload_i_reg[38] ;
+  input [0:0]\\wrap_second_len_r_reg[0] ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [0:0]CO;
+  wire [1:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [2:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire ar_cmd_fsm_0_n_0;
+  wire ar_cmd_fsm_0_n_10;
+  wire ar_cmd_fsm_0_n_13;
+  wire ar_cmd_fsm_0_n_17;
+  wire ar_cmd_fsm_0_n_18;
+  wire ar_cmd_fsm_0_n_22;
+  wire ar_cmd_fsm_0_n_23;
+  wire ar_cmd_fsm_0_n_3;
+  wire ar_cmd_fsm_0_n_4;
+  wire ar_cmd_fsm_0_n_6;
+  wire areset_d1;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [0:0]axaddr_offset;
+  wire [2:0]\\axaddr_offset_r_reg[3] ;
+  wire \\axaddr_offset_r_reg[3]_0 ;
+  wire cmd_translator_0_n_1;
+  wire cmd_translator_0_n_10;
+  wire cmd_translator_0_n_11;
+  wire cmd_translator_0_n_13;
+  wire cmd_translator_0_n_2;
+  wire cmd_translator_0_n_8;
+  wire cmd_translator_0_n_9;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire incr_next_pending;
+  wire [11:0]m_axi_araddr;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire \\m_payload_i_reg[0] ;
+  wire \\m_payload_i_reg[0]_0 ;
+  wire [3:0]\\m_payload_i_reg[11] ;
+  wire \\m_payload_i_reg[35] ;
+  wire \\m_payload_i_reg[35]_0 ;
+  wire \\m_payload_i_reg[38] ;
+  wire \\m_payload_i_reg[3] ;
+  wire [3:0]\\m_payload_i_reg[3]_0 ;
+  wire \\m_payload_i_reg[44] ;
+  wire \\m_payload_i_reg[47] ;
+  wire [2:0]\\m_payload_i_reg[47]_0 ;
+  wire [30:0]\\m_payload_i_reg[61] ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire m_valid_i0;
+  wire [11:0]\\r_arid_r_reg[11] ;
+  wire r_push;
+  wire r_rlast;
+  wire s_axi_arvalid;
+  wire s_ready_i_reg;
+  wire sel_first;
+  wire sel_first_i;
+  wire si_rs_arvalid;
+  wire [1:0]state;
+  wire \\wrap_boundary_axaddr_r_reg[11] ;
+  wire [0:0]\\wrap_cmd_0/axaddr_offset_r ;
+  wire [3:0]\\wrap_cmd_0/wrap_second_len ;
+  wire [3:3]\\wrap_cmd_0/wrap_second_len_r ;
+  wire wrap_next_pending;
+  wire [0:0]\\wrap_second_len_r_reg[0] ;
+
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm ar_cmd_fsm_0
+       (.D({ar_cmd_fsm_0_n_3,ar_cmd_fsm_0_n_4}),
+        .E(\\wrap_boundary_axaddr_r_reg[11] ),
+        .Q(state),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\axaddr_incr_reg[11] (ar_cmd_fsm_0_n_18),
+        .\\axaddr_offset_r_reg[0] (axaddr_offset),
+        .\\axaddr_offset_r_reg[0]_0 (\\wrap_cmd_0/axaddr_offset_r ),
+        .\\axaddr_offset_r_reg[3] (\\axaddr_offset_r_reg[3]_0 ),
+        .\\axlen_cnt_reg[0] (ar_cmd_fsm_0_n_6),
+        .\\axlen_cnt_reg[0]_0 (cmd_translator_0_n_9),
+        .\\axlen_cnt_reg[3] (ar_cmd_fsm_0_n_17),
+        .\\axlen_cnt_reg[6] (cmd_translator_0_n_10),
+        .\\axlen_cnt_reg[7] (ar_cmd_fsm_0_n_0),
+        .\\cnt_read_reg[1]_rep__0 (\\cnt_read_reg[1]_rep__0 ),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .\\m_payload_i_reg[0] (\\m_payload_i_reg[0] ),
+        .\\m_payload_i_reg[0]_0 (\\m_payload_i_reg[0]_0 ),
+        .\\m_payload_i_reg[0]_1 (E),
+        .\\m_payload_i_reg[35] (\\m_payload_i_reg[35] ),
+        .\\m_payload_i_reg[35]_0 (\\m_payload_i_reg[35]_0 ),
+        .\\m_payload_i_reg[3] (\\m_payload_i_reg[3] ),
+        .\\m_payload_i_reg[44] (\\m_payload_i_reg[61] [15:14]),
+        .\\m_payload_i_reg[44]_0 (\\m_payload_i_reg[44] ),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47]_0 [2:1]),
+        .m_valid_i0(m_valid_i0),
+        .next_pending_r_reg(cmd_translator_0_n_1),
+        .r_push_r_reg(r_push),
+        .s_axburst_eq0_reg(ar_cmd_fsm_0_n_10),
+        .s_axburst_eq1_reg(ar_cmd_fsm_0_n_13),
+        .s_axburst_eq1_reg_0(cmd_translator_0_n_13),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_ready_i_reg(s_ready_i_reg),
+        .sel_first_i(sel_first_i),
+        .sel_first_reg(ar_cmd_fsm_0_n_22),
+        .sel_first_reg_0(ar_cmd_fsm_0_n_23),
+        .sel_first_reg_1(cmd_translator_0_n_2),
+        .sel_first_reg_2(sel_first),
+        .sel_first_reg_3(cmd_translator_0_n_8),
+        .si_rs_arvalid(si_rs_arvalid),
+        .\\state_reg[0]_0 (cmd_translator_0_n_11),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[2] (D),
+        .\\wrap_second_len_r_reg[3] ({\\wrap_cmd_0/wrap_second_len [3],\\wrap_cmd_0/wrap_second_len [0]}),
+        .\\wrap_second_len_r_reg[3]_0 ({\\wrap_cmd_0/wrap_second_len_r ,Q[0]}));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1 cmd_translator_0
+       (.CO(CO),
+        .D(ar_cmd_fsm_0_n_6),
+        .E(\\wrap_boundary_axaddr_r_reg[11] ),
+        .O(O),
+        .Q(cmd_translator_0_n_9),
+        .S(S),
+        .aclk(aclk),
+        .\\axaddr_incr_reg[11] (sel_first),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_offset_r_reg[3] ({\\axaddr_offset_r_reg[3] ,\\wrap_cmd_0/axaddr_offset_r }),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3]_0 ),
+        .\\axlen_cnt_reg[1] (cmd_translator_0_n_10),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arready(m_axi_arready),
+        .\\m_payload_i_reg[11] (\\m_payload_i_reg[11] ),
+        .\\m_payload_i_reg[35] (\\m_payload_i_reg[35] ),
+        .\\m_payload_i_reg[38] (\\m_payload_i_reg[38] ),
+        .\\m_payload_i_reg[39] (ar_cmd_fsm_0_n_10),
+        .\\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_13),
+        .\\m_payload_i_reg[3] (\\m_payload_i_reg[3]_0 ),
+        .\\m_payload_i_reg[44] (\\m_payload_i_reg[44] ),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47] ),
+        .\\m_payload_i_reg[47]_0 (\\m_payload_i_reg[61] [18:0]),
+        .\\m_payload_i_reg[47]_1 ({\\m_payload_i_reg[47]_0 ,axaddr_offset}),
+        .\\m_payload_i_reg[6] (\\m_payload_i_reg[6] ),
+        .m_valid_i_reg(ar_cmd_fsm_0_n_17),
+        .next_pending_r_reg(cmd_translator_0_n_1),
+        .next_pending_r_reg_0(cmd_translator_0_n_11),
+        .r_rlast(r_rlast),
+        .sel_first_i(sel_first_i),
+        .sel_first_reg_0(cmd_translator_0_n_2),
+        .sel_first_reg_1(cmd_translator_0_n_8),
+        .sel_first_reg_2(ar_cmd_fsm_0_n_18),
+        .sel_first_reg_3(ar_cmd_fsm_0_n_22),
+        .sel_first_reg_4(ar_cmd_fsm_0_n_23),
+        .si_rs_arvalid(si_rs_arvalid),
+        .\\state_reg[0]_rep (cmd_translator_0_n_13),
+        .\\state_reg[1] (state),
+        .\\state_reg[1]_0 (ar_cmd_fsm_0_n_0),
+        .\\state_reg[1]_rep (r_push),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[3] ({\\wrap_cmd_0/wrap_second_len_r ,Q}),
+        .\\wrap_second_len_r_reg[3]_0 ({\\wrap_cmd_0/wrap_second_len [3],D,\\wrap_cmd_0/wrap_second_len [0]}),
+        .\\wrap_second_len_r_reg[3]_1 ({ar_cmd_fsm_0_n_3,\\wrap_second_len_r_reg[0] ,ar_cmd_fsm_0_n_4}));
+  FDRE \\s_arid_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [19]),
+        .Q(\\r_arid_r_reg[11] [0]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[10] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [29]),
+        .Q(\\r_arid_r_reg[11] [10]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[11] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [30]),
+        .Q(\\r_arid_r_reg[11] [11]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [20]),
+        .Q(\\r_arid_r_reg[11] [1]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [21]),
+        .Q(\\r_arid_r_reg[11] [2]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [22]),
+        .Q(\\r_arid_r_reg[11] [3]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [23]),
+        .Q(\\r_arid_r_reg[11] [4]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[5] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [24]),
+        .Q(\\r_arid_r_reg[11] [5]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[6] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [25]),
+        .Q(\\r_arid_r_reg[11] [6]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[7] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [26]),
+        .Q(\\r_arid_r_reg[11] [7]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[8] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [27]),
+        .Q(\\r_arid_r_reg[11] [8]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[9] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [28]),
+        .Q(\\r_arid_r_reg[11] [9]),
+        .R(1\'b0));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel
+   (\\axaddr_incr_reg[3] ,
+    sel_first,
+    Q,
+    \\wrap_boundary_axaddr_r_reg[0] ,
+    E,
+    b_push,
+    m_axi_awvalid,
+    m_axi_awaddr,
+    \\axaddr_offset_r_reg[3] ,
+    \\wrap_second_len_r_reg[3] ,
+    in,
+    S,
+    aclk,
+    O,
+    si_rs_awvalid,
+    \\m_payload_i_reg[47] ,
+    \\m_payload_i_reg[61] ,
+    CO,
+    \\m_payload_i_reg[46] ,
+    areset_d1,
+    \\cnt_read_reg[1]_rep__0 ,
+    m_axi_awready,
+    \\cnt_read_reg[1]_rep__0_0 ,
+    \\cnt_read_reg[0]_rep__0 ,
+    \\m_payload_i_reg[11] ,
+    \\m_payload_i_reg[38] ,
+    D,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\wrap_second_len_r_reg[3]_1 ,
+    \\m_payload_i_reg[6] );
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output sel_first;
+  output [1:0]Q;
+  output \\wrap_boundary_axaddr_r_reg[0] ;
+  output [0:0]E;
+  output b_push;
+  output m_axi_awvalid;
+  output [11:0]m_axi_awaddr;
+  output [3:0]\\axaddr_offset_r_reg[3] ;
+  output [3:0]\\wrap_second_len_r_reg[3] ;
+  output [15:0]in;
+  output [3:0]S;
+  input aclk;
+  input [3:0]O;
+  input si_rs_awvalid;
+  input \\m_payload_i_reg[47] ;
+  input [30:0]\\m_payload_i_reg[61] ;
+  input [0:0]CO;
+  input \\m_payload_i_reg[46] ;
+  input areset_d1;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input m_axi_awready;
+  input \\cnt_read_reg[1]_rep__0_0 ;
+  input \\cnt_read_reg[0]_rep__0 ;
+  input [7:0]\\m_payload_i_reg[11] ;
+  input \\m_payload_i_reg[38] ;
+  input [3:0]D;
+  input [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [0:0]CO;
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [1:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire areset_d1;
+  wire aw_cmd_fsm_0_n_0;
+  wire aw_cmd_fsm_0_n_10;
+  wire aw_cmd_fsm_0_n_14;
+  wire aw_cmd_fsm_0_n_15;
+  wire aw_cmd_fsm_0_n_3;
+  wire aw_cmd_fsm_0_n_5;
+  wire aw_cmd_fsm_0_n_6;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3] ;
+  wire b_push;
+  wire cmd_translator_0_n_0;
+  wire cmd_translator_0_n_1;
+  wire cmd_translator_0_n_10;
+  wire cmd_translator_0_n_11;
+  wire cmd_translator_0_n_2;
+  wire cmd_translator_0_n_9;
+  wire \\cnt_read_reg[0]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0_0 ;
+  wire [15:0]in;
+  wire incr_next_pending;
+  wire [11:0]m_axi_awaddr;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire [7:0]\\m_payload_i_reg[11] ;
+  wire \\m_payload_i_reg[38] ;
+  wire \\m_payload_i_reg[46] ;
+  wire \\m_payload_i_reg[47] ;
+  wire [30:0]\\m_payload_i_reg[61] ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire sel_first;
+  wire sel_first__0;
+  wire sel_first_i;
+  wire si_rs_awvalid;
+  wire \\wrap_boundary_axaddr_r_reg[0] ;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3] ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_1 ;
+
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm aw_cmd_fsm_0
+       (.E(aw_cmd_fsm_0_n_0),
+        .Q(Q),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\axlen_cnt_reg[3] (cmd_translator_0_n_11),
+        .\\axlen_cnt_reg[7] (aw_cmd_fsm_0_n_5),
+        .\\axlen_cnt_reg[7]_0 (cmd_translator_0_n_9),
+        .b_push(b_push),
+        .\\cnt_read_reg[0]_rep__0 (\\cnt_read_reg[0]_rep__0 ),
+        .\\cnt_read_reg[1]_rep__0 (\\cnt_read_reg[1]_rep__0 ),
+        .\\cnt_read_reg[1]_rep__0_0 (\\cnt_read_reg[1]_rep__0_0 ),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .\\m_payload_i_reg[0] (E),
+        .\\m_payload_i_reg[39] (\\m_payload_i_reg[61] [14]),
+        .\\m_payload_i_reg[46] (\\m_payload_i_reg[46] ),
+        .next_pending_r_reg(cmd_translator_0_n_0),
+        .next_pending_r_reg_0(cmd_translator_0_n_1),
+        .s_axburst_eq0_reg(aw_cmd_fsm_0_n_6),
+        .s_axburst_eq1_reg(aw_cmd_fsm_0_n_10),
+        .s_axburst_eq1_reg_0(cmd_translator_0_n_10),
+        .sel_first__0(sel_first__0),
+        .sel_first_i(sel_first_i),
+        .sel_first_reg(aw_cmd_fsm_0_n_3),
+        .sel_first_reg_0(aw_cmd_fsm_0_n_14),
+        .sel_first_reg_1(aw_cmd_fsm_0_n_15),
+        .sel_first_reg_2(cmd_translator_0_n_2),
+        .sel_first_reg_3(sel_first),
+        .si_rs_awvalid(si_rs_awvalid),
+        .\\wrap_boundary_axaddr_r_reg[0] (\\wrap_boundary_axaddr_r_reg[0] ),
+        .wrap_next_pending(wrap_next_pending));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator cmd_translator_0
+       (.CO(CO),
+        .D(D),
+        .E(\\wrap_boundary_axaddr_r_reg[0] ),
+        .O(O),
+        .Q(Q),
+        .S(S),
+        .aclk(aclk),
+        .\\axaddr_incr_reg[11] (sel_first),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_offset_r_reg[3] (\\axaddr_offset_r_reg[3] ),
+        .\\axlen_cnt_reg[0] (cmd_translator_0_n_9),
+        .\\cnt_read_reg[1]_rep__0 (aw_cmd_fsm_0_n_3),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_awaddr(m_axi_awaddr),
+        .\\m_payload_i_reg[11] (\\m_payload_i_reg[11] ),
+        .\\m_payload_i_reg[38] (\\m_payload_i_reg[38] ),
+        .\\m_payload_i_reg[39] (aw_cmd_fsm_0_n_6),
+        .\\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_10),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47] ),
+        .\\m_payload_i_reg[47]_0 (\\m_payload_i_reg[61] [18:0]),
+        .\\m_payload_i_reg[6] (\\m_payload_i_reg[6] ),
+        .next_pending_r_reg(cmd_translator_0_n_0),
+        .next_pending_r_reg_0(cmd_translator_0_n_1),
+        .next_pending_r_reg_1(cmd_translator_0_n_11),
+        .sel_first__0(sel_first__0),
+        .sel_first_i(sel_first_i),
+        .sel_first_reg_0(cmd_translator_0_n_2),
+        .sel_first_reg_1(aw_cmd_fsm_0_n_14),
+        .sel_first_reg_2(aw_cmd_fsm_0_n_15),
+        .si_rs_awvalid(si_rs_awvalid),
+        .\\state_reg[0] (cmd_translator_0_n_10),
+        .\\state_reg[0]_0 (aw_cmd_fsm_0_n_0),
+        .\\state_reg[0]_1 (aw_cmd_fsm_0_n_5),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[3] (\\wrap_second_len_r_reg[3] ),
+        .\\wrap_second_len_r_reg[3]_0 (\\wrap_second_len_r_reg[3]_0 ),
+        .\\wrap_second_len_r_reg[3]_1 (\\wrap_second_len_r_reg[3]_1 ));
+  FDRE \\s_awid_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [19]),
+        .Q(in[4]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[10] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [29]),
+        .Q(in[14]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[11] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [30]),
+        .Q(in[15]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [20]),
+        .Q(in[5]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [21]),
+        .Q(in[6]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [22]),
+        .Q(in[7]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [23]),
+        .Q(in[8]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[5] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [24]),
+        .Q(in[9]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[6] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [25]),
+        .Q(in[10]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[7] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [26]),
+        .Q(in[11]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[8] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [27]),
+        .Q(in[12]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[9] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [28]),
+        .Q(in[13]),
+        .R(1\'b0));
+  FDRE \\s_awlen_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [15]),
+        .Q(in[0]),
+        .R(1\'b0));
+  FDRE \\s_awlen_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [16]),
+        .Q(in[1]),
+        .R(1\'b0));
+  FDRE \\s_awlen_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [17]),
+        .Q(in[2]),
+        .R(1\'b0));
+  FDRE \\s_awlen_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [18]),
+        .Q(in[3]),
+        .R(1\'b0));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel
+   (si_rs_bvalid,
+    \\cnt_read_reg[0]_rep__0 ,
+    \\cnt_read_reg[1]_rep__0 ,
+    \\state_reg[0] ,
+    m_axi_bready,
+    out,
+    \\skid_buffer_reg[1] ,
+    shandshake,
+    aclk,
+    b_push,
+    m_axi_bvalid,
+    areset_d1,
+    si_rs_bready,
+    in,
+    m_axi_bresp);
+  output si_rs_bvalid;
+  output \\cnt_read_reg[0]_rep__0 ;
+  output \\cnt_read_reg[1]_rep__0 ;
+  output \\state_reg[0] ;
+  output m_axi_bready;
+  output [11:0]out;
+  output [1:0]\\skid_buffer_reg[1] ;
+  input shandshake;
+  input aclk;
+  input b_push;
+  input m_axi_bvalid;
+  input areset_d1;
+  input si_rs_bready;
+  input [15:0]in;
+  input [1:0]m_axi_bresp;
+
+  wire aclk;
+  wire areset_d1;
+  wire b_push;
+  wire bid_fifo_0_n_5;
+  wire \\bresp_cnt[7]_i_3_n_0 ;
+  wire [7:0]bresp_cnt_reg__0;
+  wire bresp_push;
+  wire [1:0]cnt_read;
+  wire \\cnt_read_reg[0]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire [15:0]in;
+  wire m_axi_bready;
+  wire [1:0]m_axi_bresp;
+  wire m_axi_bvalid;
+  wire mhandshake;
+  wire mhandshake_r;
+  wire [11:0]out;
+  wire [7:0]p_0_in;
+  wire s_bresp_acc0;
+  wire \\s_bresp_acc[0]_i_1_n_0 ;
+  wire \\s_bresp_acc[1]_i_1_n_0 ;
+  wire \\s_bresp_acc_reg_n_0_[0] ;
+  wire \\s_bresp_acc_reg_n_0_[1] ;
+  wire shandshake;
+  wire shandshake_r;
+  wire si_rs_bready;
+  wire si_rs_bvalid;
+  wire [1:0]\\skid_buffer_reg[1] ;
+  wire \\state_reg[0] ;
+
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo bid_fifo_0
+       (.Q(bresp_cnt_reg__0),
+        .SR(s_bresp_acc0),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .b_push(b_push),
+        .bresp_push(bresp_push),
+        .bvalid_i_reg(bid_fifo_0_n_5),
+        .\\cnt_read_reg[0]_rep__0_0 (\\cnt_read_reg[0]_rep__0 ),
+        .\\cnt_read_reg[1]_0 (cnt_read),
+        .\\cnt_read_reg[1]_rep__0_0 (\\cnt_read_reg[1]_rep__0 ),
+        .in(in),
+        .mhandshake_r(mhandshake_r),
+        .out(out),
+        .shandshake_r(shandshake_r),
+        .si_rs_bready(si_rs_bready),
+        .si_rs_bvalid(si_rs_bvalid),
+        .\\state_reg[0] (\\state_reg[0] ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\bresp_cnt[0]_i_1 
+       (.I0(bresp_cnt_reg__0[0]),
+        .O(p_0_in[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair117"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\bresp_cnt[1]_i_1 
+       (.I0(bresp_cnt_reg__0[0]),
+        .I1(bresp_cnt_reg__0[1]),
+        .O(p_0_in[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair117"" *) 
+  LUT3 #(
+    .INIT(8\'h6A)) 
+    \\bresp_cnt[2]_i_1 
+       (.I0(bresp_cnt_reg__0[2]),
+        .I1(bresp_cnt_reg__0[1]),
+        .I2(bresp_cnt_reg__0[0]),
+        .O(p_0_in[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair115"" *) 
+  LUT4 #(
+    .INIT(16\'h6AAA)) 
+    \\bresp_cnt[3]_i_1 
+       (.I0(bresp_cnt_reg__0[3]),
+        .I1(bresp_cnt_reg__0[0]),
+        .I2(bresp_cnt_reg__0[1]),
+        .I3(bresp_cnt_reg__0[2]),
+        .O(p_0_in[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair115"" *) 
+  LUT5 #(
+    .INIT(32\'h6AAAAAAA)) 
+    \\bresp_cnt[4]_i_1 
+       (.I0(bresp_cnt_reg__0[4]),
+        .I1(bresp_cnt_reg__0[2]),
+        .I2(bresp_cnt_reg__0[1]),
+        .I3(bresp_cnt_reg__0[0]),
+        .I4(bresp_cnt_reg__0[3]),
+        .O(p_0_in[4]));
+  LUT6 #(
+    .INIT(64\'h6AAAAAAAAAAAAAAA)) 
+    \\bresp_cnt[5]_i_1 
+       (.I0(bresp_cnt_reg__0[5]),
+        .I1(bresp_cnt_reg__0[3]),
+        .I2(bresp_cnt_reg__0[0]),
+        .I3(bresp_cnt_reg__0[1]),
+        .I4(bresp_cnt_reg__0[2]),
+        .I5(bresp_cnt_reg__0[4]),
+        .O(p_0_in[5]));
+  (* SOFT_HLUTNM = ""soft_lutpair116"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\bresp_cnt[6]_i_1 
+       (.I0(bresp_cnt_reg__0[6]),
+        .I1(\\bresp_cnt[7]_i_3_n_0 ),
+        .O(p_0_in[6]));
+  (* SOFT_HLUTNM = ""soft_lutpair116"" *) 
+  LUT3 #(
+    .INIT(8\'h6A)) 
+    \\bresp_cnt[7]_i_2 
+       (.I0(bresp_cnt_reg__0[7]),
+        .I1(\\bresp_cnt[7]_i_3_n_0 ),
+        .I2(bresp_cnt_reg__0[6]),
+        .O(p_0_in[7]));
+  LUT6 #(
+    .INIT(64\'h8000000000000000)) 
+    \\bresp_cnt[7]_i_3 
+       (.I0(bresp_cnt_reg__0[5]),
+        .I1(bresp_cnt_reg__0[3]),
+        .I2(bresp_cnt_reg__0[0]),
+        .I3(bresp_cnt_reg__0[1]),
+        .I4(bresp_cnt_reg__0[2]),
+        .I5(bresp_cnt_reg__0[4]),
+        .O(\\bresp_cnt[7]_i_3_n_0 ));
+  FDRE \\bresp_cnt_reg[0] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[0]),
+        .Q(bresp_cnt_reg__0[0]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[1] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[1]),
+        .Q(bresp_cnt_reg__0[1]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[2] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[2]),
+        .Q(bresp_cnt_reg__0[2]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[3] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[3]),
+        .Q(bresp_cnt_reg__0[3]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[4] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[4]),
+        .Q(bresp_cnt_reg__0[4]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[5] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[5]),
+        .Q(bresp_cnt_reg__0[5]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[6] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[6]),
+        .Q(bresp_cnt_reg__0[6]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[7] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[7]),
+        .Q(bresp_cnt_reg__0[7]),
+        .R(s_bresp_acc0));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0 bresp_fifo_0
+       (.Q(cnt_read),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .bresp_push(bresp_push),
+        .in({\\s_bresp_acc_reg_n_0_[1] ,\\s_bresp_acc_reg_n_0_[0] }),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bvalid(m_axi_bvalid),
+        .mhandshake(mhandshake),
+        .mhandshake_r(mhandshake_r),
+        .shandshake_r(shandshake_r),
+        .\\skid_buffer_reg[1] (\\skid_buffer_reg[1] ));
+  FDRE bvalid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(bid_fifo_0_n_5),
+        .Q(si_rs_bvalid),
+        .R(1\'b0));
+  FDRE mhandshake_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(mhandshake),
+        .Q(mhandshake_r),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h00000000EACECCCC)) 
+    \\s_bresp_acc[0]_i_1 
+       (.I0(m_axi_bresp[0]),
+        .I1(\\s_bresp_acc_reg_n_0_[0] ),
+        .I2(\\s_bresp_acc_reg_n_0_[1] ),
+        .I3(m_axi_bresp[1]),
+        .I4(mhandshake),
+        .I5(s_bresp_acc0),
+        .O(\\s_bresp_acc[0]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h00EA)) 
+    \\s_bresp_acc[1]_i_1 
+       (.I0(\\s_bresp_acc_reg_n_0_[1] ),
+        .I1(m_axi_bresp[1]),
+        .I2(mhandshake),
+        .I3(s_bresp_acc0),
+        .O(\\s_bresp_acc[1]_i_1_n_0 ));
+  FDRE \\s_bresp_acc_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_bresp_acc[0]_i_1_n_0 ),
+        .Q(\\s_bresp_acc_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\s_bresp_acc_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_bresp_acc[1]_i_1_n_0 ),
+        .Q(\\s_bresp_acc_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE shandshake_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(shandshake),
+        .Q(shandshake_r),
+        .R(1\'b0));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator
+   (next_pending_r_reg,
+    next_pending_r_reg_0,
+    sel_first_reg_0,
+    \\axaddr_incr_reg[3] ,
+    \\axaddr_incr_reg[11] ,
+    sel_first__0,
+    \\axlen_cnt_reg[0] ,
+    \\state_reg[0] ,
+    next_pending_r_reg_1,
+    m_axi_awaddr,
+    \\axaddr_offset_r_reg[3] ,
+    \\wrap_second_len_r_reg[3] ,
+    S,
+    incr_next_pending,
+    aclk,
+    wrap_next_pending,
+    sel_first_i,
+    \\m_payload_i_reg[39] ,
+    \\m_payload_i_reg[39]_0 ,
+    O,
+    sel_first_reg_1,
+    sel_first_reg_2,
+    \\m_payload_i_reg[47] ,
+    Q,
+    si_rs_awvalid,
+    \\m_payload_i_reg[47]_0 ,
+    E,
+    CO,
+    \\cnt_read_reg[1]_rep__0 ,
+    \\m_payload_i_reg[11] ,
+    \\m_payload_i_reg[38] ,
+    \\state_reg[0]_0 ,
+    \\state_reg[0]_1 ,
+    D,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\wrap_second_len_r_reg[3]_1 ,
+    \\m_payload_i_reg[6] );
+  output next_pending_r_reg;
+  output next_pending_r_reg_0;
+  output sel_first_reg_0;
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output \\axaddr_incr_reg[11] ;
+  output sel_first__0;
+  output \\axlen_cnt_reg[0] ;
+  output \\state_reg[0] ;
+  output next_pending_r_reg_1;
+  output [11:0]m_axi_awaddr;
+  output [3:0]\\axaddr_offset_r_reg[3] ;
+  output [3:0]\\wrap_second_len_r_reg[3] ;
+  output [3:0]S;
+  input incr_next_pending;
+  input aclk;
+  input wrap_next_pending;
+  input sel_first_i;
+  input \\m_payload_i_reg[39] ;
+  input \\m_payload_i_reg[39]_0 ;
+  input [3:0]O;
+  input sel_first_reg_1;
+  input sel_first_reg_2;
+  input \\m_payload_i_reg[47] ;
+  input [1:0]Q;
+  input si_rs_awvalid;
+  input [18:0]\\m_payload_i_reg[47]_0 ;
+  input [0:0]E;
+  input [0:0]CO;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input [7:0]\\m_payload_i_reg[11] ;
+  input \\m_payload_i_reg[38] ;
+  input [0:0]\\state_reg[0]_0 ;
+  input \\state_reg[0]_1 ;
+  input [3:0]D;
+  input [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [0:0]CO;
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [1:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire [11:4]axaddr_incr_reg;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire axaddr_incr_reg_11__s_net_1;
+  wire [3:0]\\axaddr_offset_r_reg[3] ;
+  wire \\axlen_cnt_reg[0] ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire incr_next_pending;
+  wire [11:0]m_axi_awaddr;
+  wire [7:0]\\m_payload_i_reg[11] ;
+  wire \\m_payload_i_reg[38] ;
+  wire \\m_payload_i_reg[39] ;
+  wire \\m_payload_i_reg[39]_0 ;
+  wire \\m_payload_i_reg[47] ;
+  wire [18:0]\\m_payload_i_reg[47]_0 ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire next_pending_r_reg;
+  wire next_pending_r_reg_0;
+  wire next_pending_r_reg_1;
+  wire s_axburst_eq0;
+  wire s_axburst_eq1;
+  wire sel_first__0;
+  wire sel_first_i;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire sel_first_reg_2;
+  wire si_rs_awvalid;
+  wire \\state_reg[0] ;
+  wire [0:0]\\state_reg[0]_0 ;
+  wire \\state_reg[0]_1 ;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3] ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_1 ;
+
+  assign \\axaddr_incr_reg[11]  = axaddr_incr_reg_11__s_net_1;
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd incr_cmd_0
+       (.CO(CO),
+        .E(E),
+        .O(O),
+        .Q(Q),
+        .S(S),
+        .aclk(aclk),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
+        .\\axaddr_incr_reg[3]_0 (\\axaddr_incr_reg[3] ),
+        .\\axlen_cnt_reg[0]_0 (\\axlen_cnt_reg[0] ),
+        .\\cnt_read_reg[1]_rep__0 (\\cnt_read_reg[1]_rep__0 ),
+        .incr_next_pending(incr_next_pending),
+        .\\m_payload_i_reg[11] (\\m_payload_i_reg[11] ),
+        .\\m_payload_i_reg[46] ({\\m_payload_i_reg[47]_0 [17:15],\\m_payload_i_reg[47]_0 [13:12],\\m_payload_i_reg[47]_0 [3:0]}),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47] ),
+        .next_pending_r_reg_0(next_pending_r_reg),
+        .sel_first_reg_0(sel_first_reg_1),
+        .si_rs_awvalid(si_rs_awvalid),
+        .\\state_reg[0] (\\state_reg[0]_0 ),
+        .\\state_reg[0]_0 (\\state_reg[0]_1 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\memory_reg[3][0]_srl4_i_2 
+       (.I0(s_axburst_eq1),
+        .I1(\\m_payload_i_reg[47]_0 [14]),
+        .I2(s_axburst_eq0),
+        .O(\\state_reg[0] ));
+  FDRE s_axburst_eq0_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[39] ),
+        .Q(s_axburst_eq0),
+        .R(1\'b0));
+  FDRE s_axburst_eq1_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[39]_0 ),
+        .Q(s_axburst_eq1),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_i),
+        .Q(sel_first_reg_0),
+        .R(1\'b0));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd wrap_cmd_0
+       (.D(D),
+        .E(E),
+        .aclk(aclk),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3] ),
+        .\\cnt_read_reg[1]_rep__0 (\\cnt_read_reg[1]_rep__0 ),
+        .m_axi_awaddr(m_axi_awaddr),
+        .\\m_payload_i_reg[38] (\\m_payload_i_reg[38] ),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47]_0 ),
+        .\\m_payload_i_reg[6] (\\m_payload_i_reg[6] ),
+        .next_pending_r_reg_0(next_pending_r_reg_0),
+        .next_pending_r_reg_1(next_pending_r_reg_1),
+        .sel_first_reg_0(sel_first__0),
+        .sel_first_reg_1(sel_first_reg_2),
+        .\\state_reg[0] (\\state_reg[0]_0 ),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[3]_0 (\\wrap_second_len_r_reg[3] ),
+        .\\wrap_second_len_r_reg[3]_1 (\\wrap_second_len_r_reg[3]_0 ),
+        .\\wrap_second_len_r_reg[3]_2 (\\wrap_second_len_r_reg[3]_1 ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_cmd_translator"" *) 
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1
+   (incr_next_pending,
+    next_pending_r_reg,
+    sel_first_reg_0,
+    \\axaddr_incr_reg[3] ,
+    \\axaddr_incr_reg[11] ,
+    sel_first_reg_1,
+    Q,
+    \\axlen_cnt_reg[1] ,
+    next_pending_r_reg_0,
+    r_rlast,
+    \\state_reg[0]_rep ,
+    m_axi_araddr,
+    \\wrap_second_len_r_reg[3] ,
+    \\axaddr_offset_r_reg[3] ,
+    S,
+    aclk,
+    wrap_next_pending,
+    sel_first_i,
+    \\m_payload_i_reg[39] ,
+    \\m_payload_i_reg[39]_0 ,
+    sel_first_reg_2,
+    O,
+    sel_first_reg_3'b',
+    sel_first_reg_4,
+    \\m_payload_i_reg[47] ,
+    E,
+    \\m_payload_i_reg[47]_0 ,
+    \\state_reg[1] ,
+    si_rs_arvalid,
+    CO,
+    \\state_reg[1]_rep ,
+    \\m_payload_i_reg[44] ,
+    \\m_payload_i_reg[3] ,
+    \\m_payload_i_reg[11] ,
+    \\m_payload_i_reg[38] ,
+    \\axaddr_offset_r_reg[3]_0 ,
+    \\m_payload_i_reg[35] ,
+    m_valid_i_reg,
+    D,
+    \\state_reg[1]_0 ,
+    \\m_payload_i_reg[47]_1 ,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\wrap_second_len_r_reg[3]_1 ,
+    \\m_payload_i_reg[6] ,
+    m_axi_arready);
+  output incr_next_pending;
+  output next_pending_r_reg;
+  output sel_first_reg_0;
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output \\axaddr_incr_reg[11] ;
+  output sel_first_reg_1;
+  output [0:0]Q;
+  output \\axlen_cnt_reg[1] ;
+  output next_pending_r_reg_0;
+  output r_rlast;
+  output \\state_reg[0]_rep ;
+  output [11:0]m_axi_araddr;
+  output [3:0]\\wrap_second_len_r_reg[3] ;
+  output [3:0]\\axaddr_offset_r_reg[3] ;
+  output [3:0]S;
+  input aclk;
+  input wrap_next_pending;
+  input sel_first_i;
+  input \\m_payload_i_reg[39] ;
+  input \\m_payload_i_reg[39]_0 ;
+  input sel_first_reg_2;
+  input [3:0]O;
+  input sel_first_reg_3;
+  input sel_first_reg_4;
+  input \\m_payload_i_reg[47] ;
+  input [0:0]E;
+  input [18:0]\\m_payload_i_reg[47]_0 ;
+  input [1:0]\\state_reg[1] ;
+  input si_rs_arvalid;
+  input [0:0]CO;
+  input \\state_reg[1]_rep ;
+  input \\m_payload_i_reg[44] ;
+  input [3:0]\\m_payload_i_reg[3] ;
+  input [3:0]\\m_payload_i_reg[11] ;
+  input \\m_payload_i_reg[38] ;
+  input \\axaddr_offset_r_reg[3]_0 ;
+  input \\m_payload_i_reg[35] ;
+  input [0:0]m_valid_i_reg;
+  input [0:0]D;
+  input \\state_reg[1]_0 ;
+  input [3:0]\\m_payload_i_reg[47]_1 ;
+  input [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input [2:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+  input m_axi_arready;
+
+  wire [0:0]CO;
+  wire [0:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [0:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire [11:4]axaddr_incr_reg;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire axaddr_incr_reg_11__s_net_1;
+  wire [3:0]\\axaddr_offset_r_reg[3] ;
+  wire \\axaddr_offset_r_reg[3]_0 ;
+  wire \\axlen_cnt_reg[1] ;
+  wire incr_next_pending;
+  wire [11:0]m_axi_araddr;
+  wire m_axi_arready;
+  wire [3:0]\\m_payload_i_reg[11] ;
+  wire \\m_payload_i_reg[35] ;
+  wire \\m_payload_i_reg[38] ;
+  wire \\m_payload_i_reg[39] ;
+  wire \\m_payload_i_reg[39]_0 ;
+  wire [3:0]\\m_payload_i_reg[3] ;
+  wire \\m_payload_i_reg[44] ;
+  wire \\m_payload_i_reg[47] ;
+  wire [18:0]\\m_payload_i_reg[47]_0 ;
+  wire [3:0]\\m_payload_i_reg[47]_1 ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire [0:0]m_valid_i_reg;
+  wire next_pending_r_reg;
+  wire next_pending_r_reg_0;
+  wire r_rlast;
+  wire s_axburst_eq0;
+  wire s_axburst_eq1;
+  wire sel_first_i;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire sel_first_reg_2;
+  wire sel_first_reg_3;
+  wire sel_first_reg_4;
+  wire si_rs_arvalid;
+  wire \\state_reg[0]_rep ;
+  wire [1:0]\\state_reg[1] ;
+  wire \\state_reg[1]_0 ;
+  wire \\state_reg[1]_rep ;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3] ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [2:0]\\wrap_second_len_r_reg[3]_1 ;
+
+  assign \\axaddr_incr_reg[11]  = axaddr_incr_reg_11__s_net_1;
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2 incr_cmd_0
+       (.CO(CO),
+        .D(D),
+        .E(E),
+        .O(O),
+        .Q(Q),
+        .S(S),
+        .aclk(aclk),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
+        .\\axaddr_incr_reg[3]_0 (\\axaddr_incr_reg[3] ),
+        .\\axlen_cnt_reg[1]_0 (\\axlen_cnt_reg[1] ),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_arready(m_axi_arready),
+        .\\m_payload_i_reg[11] (\\m_payload_i_reg[11] ),
+        .\\m_payload_i_reg[3] (\\m_payload_i_reg[3] ),
+        .\\m_payload_i_reg[44] (\\m_payload_i_reg[44] ),
+        .\\m_payload_i_reg[46] ({\\m_payload_i_reg[47]_0 [17:16],\\m_payload_i_reg[47]_0 [13:12],\\m_payload_i_reg[47]_0 [3:0]}),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47] ),
+        .m_valid_i_reg(m_valid_i_reg),
+        .sel_first_reg_0(sel_first_reg_2),
+        .sel_first_reg_1(sel_first_reg_3),
+        .\\state_reg[1] (\\state_reg[1]_0 ),
+        .\\state_reg[1]_0 (\\state_reg[1] ),
+        .\\state_reg[1]_rep (\\state_reg[1]_rep ));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT3 #(
+    .INIT(8\'h1D)) 
+    r_rlast_r_i_1
+       (.I0(s_axburst_eq0),
+        .I1(\\m_payload_i_reg[47]_0 [14]),
+        .I2(s_axburst_eq1),
+        .O(r_rlast));
+  FDRE s_axburst_eq0_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[39] ),
+        .Q(s_axburst_eq0),
+        .R(1\'b0));
+  FDRE s_axburst_eq1_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[39]_0 ),
+        .Q(s_axburst_eq1),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_i),
+        .Q(sel_first_reg_0),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\state[1]_i_2 
+       (.I0(s_axburst_eq1),
+        .I1(\\m_payload_i_reg[47]_0 [14]),
+        .I2(s_axburst_eq0),
+        .O(\\state_reg[0]_rep ));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3 wrap_cmd_0
+       (.E(E),
+        .aclk(aclk),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3] ),
+        .\\axaddr_offset_r_reg[3]_1 (\\axaddr_offset_r_reg[3]_0 ),
+        .m_axi_araddr(m_axi_araddr),
+        .\\m_payload_i_reg[35] (\\m_payload_i_reg[35] ),
+        .\\m_payload_i_reg[38] (\\m_payload_i_reg[38] ),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47]_0 ),
+        .\\m_payload_i_reg[47]_0 (\\m_payload_i_reg[47]_1 ),
+        .\\m_payload_i_reg[6] (\\m_payload_i_reg[6] ),
+        .m_valid_i_reg(m_valid_i_reg),
+        .next_pending_r_reg_0(next_pending_r_reg),
+        .next_pending_r_reg_1(next_pending_r_reg_0),
+        .sel_first_reg_0(sel_first_reg_1),
+        .sel_first_reg_1(sel_first_reg_4),
+        .si_rs_arvalid(si_rs_arvalid),
+        .\\state_reg[1] (\\state_reg[1] ),
+        .\\state_reg[1]_rep (\\state_reg[1]_rep ),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[3]_0 (\\wrap_second_len_r_reg[3] ),
+        .\\wrap_second_len_r_reg[3]_1 (\\wrap_second_len_r_reg[3]_0 ),
+        .\\wrap_second_len_r_reg[3]_2 (\\wrap_second_len_r_reg[3]_1 ));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd
+   (next_pending_r_reg_0,
+    \\axaddr_incr_reg[3]_0 ,
+    axaddr_incr_reg,
+    \\axaddr_incr_reg[11]_0 ,
+    \\axlen_cnt_reg[0]_0 ,
+    S,
+    incr_next_pending,
+    aclk,
+    O,
+    sel_first_reg_0,
+    \\m_payload_i_reg[47] ,
+    Q,
+    si_rs_awvalid,
+    \\m_payload_i_reg[46] ,
+    E,
+    CO,
+    \\cnt_read_reg[1]_rep__0 ,
+    \\m_payload_i_reg[11] ,
+    \\state_reg[0] ,
+    \\state_reg[0]_0 );
+  output next_pending_r_reg_0;
+  output [3:0]\\axaddr_incr_reg[3]_0 ;
+  output [7:0]axaddr_incr_reg;
+  output \\axaddr_incr_reg[11]_0 ;
+  output \\axlen_cnt_reg[0]_0 ;
+  output [3:0]S;
+  input incr_next_pending;
+  input aclk;
+  input [3:0]O;
+  input sel_first_reg_0;
+  input \\m_payload_i_reg[47] ;
+  input [1:0]Q;
+  input si_rs_awvalid;
+  input [8:0]\\m_payload_i_reg[46] ;
+  input [0:0]E;
+  input [0:0]CO;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input [7:0]\\m_payload_i_reg[11] ;
+  input [0:0]\\state_reg[0] ;
+  input \\state_reg[0]_0 ;
+
+  wire [0:0]CO;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [1:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire \\axaddr_incr[0]_i_1_n_0 ;
+  wire \\axaddr_incr[4]_i_2_n_0 ;
+  wire \\axaddr_incr[4]_i_3_n_0 ;
+  wire \\axaddr_incr[4]_i_4_n_0 ;
+  wire \\axaddr_incr[4]_i_5_n_0 ;
+  wire \\axaddr_incr[8]_i_2_n_0 ;
+  wire \\axaddr_incr[8]_i_3_n_0 ;
+  wire \\axaddr_incr[8]_i_4_n_0 ;
+  wire \\axaddr_incr[8]_i_5_n_0 ;
+  wire [7:0]axaddr_incr_reg;
+  wire \\axaddr_incr_reg[11]_0 ;
+  wire [3:0]\\axaddr_incr_reg[3]_0 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_0 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_1 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_2 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_3 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_4 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_5 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_6 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_7 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_1 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_2 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_3 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_4 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_5 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_6 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_7 ;
+  wire \\axlen_cnt[0]_i_1__1_n_0 ;
+  wire \\axlen_cnt[3]_i_2_n_0 ;
+  wire \\axlen_cnt[4]_i_1_n_0 ;
+  wire \\axlen_cnt[5]_i_1_n_0 ;
+  wire \\axlen_cnt[6]_i_1_n_0 ;
+  wire \\axlen_cnt[7]_i_2_n_0 ;
+  wire \\axlen_cnt[7]_i_3_n_0 ;
+  wire \\axlen_cnt_reg[0]_0 ;
+  wire \\axlen_cnt_reg_n_0_[0] ;
+  wire \\axlen_cnt_reg_n_0_[1] ;
+  wire \\axlen_cnt_reg_n_0_[2] ;
+  wire \\axlen_cnt_reg_n_0_[3] ;
+  wire \\axlen_cnt_reg_n_0_[4] ;
+  wire \\axlen_cnt_reg_n_0_[5] ;
+  wire \\axlen_cnt_reg_n_0_[6] ;
+  wire \\axlen_cnt_reg_n_0_[7] ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire incr_next_pending;
+  wire [7:0]\\m_payload_i_reg[11] ;
+  wire [8:0]\\m_payload_i_reg[46] ;
+  wire \\m_payload_i_reg[47] ;
+  wire next_pending_r_i_5_n_0;
+  wire next_pending_r_reg_0;
+  wire [2:1]p_1_in;
+  wire sel_first_reg_0;
+  wire si_rs_awvalid;
+  wire [0:0]\\state_reg[0] ;
+  wire \\state_reg[0]_0 ;
+  wire [3:3]\\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED ;
+
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\axaddr_incr[0]_i_1 
+       (.I0(\\axaddr_incr_reg[11]_0 ),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .O(\\axaddr_incr[0]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h9AAA)) 
+    \\axaddr_incr[0]_i_15 
+       (.I0(\\m_payload_i_reg[46] [3]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(\\m_payload_i_reg[46] [4]),
+        .I3(\\m_payload_i_reg[46] [5]),
+        .O(S[3]));
+  LUT4 #(
+    .INIT(16\'h0A9A)) 
+    \\axaddr_incr[0]_i_16 
+       (.I0(\\m_payload_i_reg[46] [2]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(\\m_payload_i_reg[46] [5]),
+        .I3(\\m_payload_i_reg[46] [4]),
+        .O(S[2]));
+  LUT4 #(
+    .INIT(16\'h009A)) 
+    \\axaddr_incr[0]_i_17 
+       (.I0(\\m_payload_i_reg[46] [1]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(\\m_payload_i_reg[46] [4]),
+        .I3(\\m_payload_i_reg[46] [5]),
+        .O(S[1]));
+  LUT4 #(
+    .INIT(16\'h0009)) 
+    \\axaddr_incr[0]_i_18 
+       (.I0(\\m_payload_i_reg[46] [0]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(\\m_payload_i_reg[46] [4]),
+        .I3(\\m_payload_i_reg[46] [5]),
+        .O(S[0]));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_2 
+       (.I0(\\m_payload_i_reg[11] [3]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[3]),
+        .O(\\axaddr_incr[4]_i_2_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_3 
+       (.I0(\\m_payload_i_reg[11] [2]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[2]),
+        .O(\\axaddr_incr[4]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_4 
+       (.I0(\\m_payload_i_reg[11] [1]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[1]),
+        .O(\\axaddr_incr[4]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_5 
+       (.I0(\\m_payload_i_reg[11] [0]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[0]),
+        .O(\\axaddr_incr[4]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_2 
+       (.I0(\\m_payload_i_reg[11] [7]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[7]),
+        .O(\\axaddr_incr[8]_i_2_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_3 
+       (.I0(\\m_payload_i_reg[11] [6]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[6]),
+        .O(\\axaddr_incr[8]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_4 
+       (.I0(\\m_payload_i_reg[11] [5]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[5]),
+        .O(\\axaddr_incr[8]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_5 
+       (.I0(\\m_payload_i_reg[11] [4]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[4]),
+        .O(\\axaddr_incr[8]_i_5_n_0 ));
+  FDRE \\axaddr_incr_reg[0] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(O[0]),
+        .Q(\\axaddr_incr_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[10] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[8]_i_1_n_5 ),
+        .Q(axaddr_incr_reg[6]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[11] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[8]_i_1_n_4 ),
+        .Q(axaddr_incr_reg[7]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[1] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(O[1]),
+        .Q(\\axaddr_incr_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[2] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(O[2]),
+        .Q(\\axaddr_incr_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[3] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(O[3]),
+        .Q(\\axaddr_incr_reg[3]_0 [3]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[4] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[4]_i_1_n_7 ),
+        .Q(axaddr_incr_reg[0]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_incr_reg[4]_i_1 
+       (.CI(CO),
+        .CO({\\axaddr_incr_reg[4]_i_1_n_0 ,\\axaddr_incr_reg[4]_i_1_n_1 ,\\axaddr_incr_reg[4]_i_1_n_2 ,\\axaddr_incr_reg[4]_i_1_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_incr_reg[4]_i_1_n_4 ,\\axaddr_incr_reg[4]_i_1_n_5 ,\\axaddr_incr_reg[4]_i_1_n_6 ,\\axaddr_incr_reg[4]_i_1_n_7 }),
+        .S({\\axaddr_incr[4]_i_2_n_0 ,\\axaddr_incr[4]_i_3_n_0 ,\\axaddr_incr[4]_i_4_n_0 ,\\axaddr_incr[4]_i_5_n_0 }));
+  FDRE \\axaddr_incr_reg[5] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[4]_i_1_n_6 ),
+        .Q(axaddr_incr_reg[1]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[6] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[4]_i_1_n_5 ),
+        .Q(axaddr_incr_reg[2]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[7] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[4]_i_1_n_4 ),
+        .Q(axaddr_incr_reg[3]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[8] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[8]_i_1_n_7 ),
+        .Q(axaddr_incr_reg[4]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_incr_reg[8]_i_1 
+       (.CI(\\axaddr_incr_reg[4]_i_1_n_0 ),
+        .CO({\\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED [3],\\axaddr_incr_reg[8]_i_1_n_1 ,\\axaddr_incr_reg[8]_i_1_n_2 ,\\axaddr_incr_reg[8]_i_1_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_incr_reg[8]_i_1_n_4 ,\\axaddr_incr_reg[8]_i_1_n_5 ,\\axaddr_incr_reg[8]_i_1_n_6 ,\\axaddr_incr_reg[8]_i_1_n_7 }),
+        .S({\\axaddr_incr[8]_i_2_n_0 ,\\axaddr_incr[8]_i_3_n_0 ,\\axaddr_incr[8]_i_4_n_0 ,\\axaddr_incr[8]_i_5_n_0 }));
+  FDRE \\axaddr_incr_reg[9] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[8]_i_1_n_6 ),
+        .Q(axaddr_incr_reg[5]),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h44444F4444444444)) 
+    \\axlen_cnt[0]_i_1__1 
+       (.I0(\\axlen_cnt_reg_n_0_[0] ),
+        .I1(\\axlen_cnt_reg[0]_0 ),
+        .I2(Q[1]),
+        .I3(si_rs_awvalid),
+        .I4(Q[0]),
+        .I5(\\m_payload_i_reg[46] [6]),
+        .O(\\axlen_cnt[0]_i_1__1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hF88F8888)) 
+    \\axlen_cnt[1]_i_1 
+       (.I0(E),
+        .I1(\\m_payload_i_reg[46] [7]),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(\\axlen_cnt_reg[0]_0 ),
+        .O(p_1_in[1]));
+  LUT6 #(
+    .INIT(64\'hF8F8F88F88888888)) 
+    \\axlen_cnt[2]_i_1 
+       (.I0(E),
+        .I1(\\m_payload_i_reg[46] [8]),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(\\axlen_cnt_reg_n_0_[1] ),
+        .I5(\\axlen_cnt_reg[0]_0 ),
+        .O(p_1_in[2]));
+  LUT6 #(
+    .INIT(64\'hAAA90000FFFFFFFF)) 
+    \\axlen_cnt[3]_i_2 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(\\axlen_cnt_reg[0]_0 ),
+        .I5(\\m_payload_i_reg[47] ),
+        .O(\\axlen_cnt[3]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair107"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAAAAA9)) 
+    \\axlen_cnt[4]_i_1 
+       (.I0(\\axlen_cnt_reg_n_0_[4] ),
+        .I1(\\axlen_cnt_reg_n_0_[3] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .O(\\axlen_cnt[4]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAAAAA9)) 
+    \\axlen_cnt[5]_i_1 
+       (.I0(\\axlen_cnt_reg_n_0_[5] ),
+        .I1(\\axlen_cnt_reg_n_0_[0] ),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(\\axlen_cnt_reg_n_0_[4] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[5]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair108"" *) 
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axlen_cnt[6]_i_1 
+       (.I0(\\axlen_cnt_reg_n_0_[6] ),
+        .I1(\\axlen_cnt_reg_n_0_[5] ),
+        .I2(\\axlen_cnt[7]_i_3_n_0 ),
+        .O(\\axlen_cnt[6]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair108"" *) 
+  LUT4 #(
+    .INIT(16\'hA9AA)) 
+    \\axlen_cnt[7]_i_2 
+       (.I0(\\axlen_cnt_reg_n_0_[7] ),
+        .I1(\\axlen_cnt_reg_n_0_[5] ),
+        .I2(\\axlen_cnt_reg_n_0_[6] ),
+        .I3(\\axlen_cnt[7]_i_3_n_0 ),
+        .O(\\axlen_cnt[7]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair107"" *) 
+  LUT5 #(
+    .INIT(32\'h00000001)) 
+    \\axlen_cnt[7]_i_3 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[4] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[2] ),
+        .I4(\\axlen_cnt_reg_n_0_[0] ),
+        .O(\\axlen_cnt[7]_i_3_n_0 ));
+  FDRE \\axlen_cnt_reg[0] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[0]_i_1__1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[1] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(p_1_in[1]),
+        .Q(\\axlen_cnt_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[2] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(p_1_in[2]),
+        .Q(\\axlen_cnt_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[3] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[3]_i_2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[4] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[4]_i_1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[4] ),
+        .R(\\state_reg[0]_0 ));
+  FDRE \\axlen_cnt_reg[5] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[5]_i_1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[5] ),
+        .R(\\state_reg[0]_0 ));
+  FDRE \\axlen_cnt_reg[6] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[6]_i_1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[6] ),
+        .R(\\state_reg[0]_0 ));
+  FDRE \\axlen_cnt_reg[7] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[7]_i_2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[7] ),
+        .R(\\state_reg[0]_0 ));
+  LUT5 #(
+    .INIT(32\'h55545555)) 
+    next_pending_r_i_4__0
+       (.I0(E),
+        .I1(\\axlen_cnt_reg_n_0_[7] ),
+        .I2(\\axlen_cnt_reg_n_0_[6] ),
+        .I3(\\axlen_cnt_reg_n_0_[5] ),
+        .I4(next_pending_r_i_5_n_0),
+        .O(\\axlen_cnt_reg[0]_0 ));
+  LUT4 #(
+    .INIT(16\'h0001)) 
+    next_pending_r_i_5
+       (.I0(\\axlen_cnt_reg_n_0_[2] ),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(\\axlen_cnt_reg_n_0_[4] ),
+        .I3(\\axlen_cnt_reg_n_0_[3] ),
+        .O(next_pending_r_i_5_n_0));
+  FDRE next_pending_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(incr_next_pending),
+        .Q(next_pending_r_reg_0),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_reg_0),
+        .Q(\\axaddr_incr_reg[11]_0 ),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_incr_cmd"" *) 
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2
+   (incr_next_pending,
+    \\axaddr_incr_reg[3]_0 ,
+    axaddr_incr_reg,
+    \\axaddr_incr_reg[11]_0 ,
+    Q,
+    \\axlen_cnt_reg[1]_0 ,
+    S,
+    aclk,
+    sel_first_reg_0,
+    O,
+    sel_first_reg_1,
+    \\m_payload_i_reg[47] ,
+    E,
+    CO,
+    \\m_payload_i_reg[46] ,
+    \\state_reg[1]_rep ,
+    \\m_payload_i_reg[44] ,
+    \\m_payload_i_reg[3] ,
+    \\m_payload_i_reg[11] ,
+    m_valid_i_reg,
+    D,
+    \\state_reg[1] ,
+    m_axi_arready,
+    \\state_reg[1]_0 );
+  output incr_next_pending;
+  output [3:0]\\axaddr_incr_reg[3]_0 ;
+  output [7:0]axaddr_incr_reg;
+  output \\axaddr_incr_reg[11]_0 ;
+  output [0:0]Q;
+  output \\axlen_cnt_reg[1]_0 ;
+  output [3:0]S;
+  input aclk;
+  input sel_first_reg_0;
+  input [3:0]O;
+  input sel_first_reg_1;
+  input \\m_payload_i_reg[47] ;
+  input [0:0]E;
+  input [0:0]CO;
+  input [7:0]\\m_payload_i_reg[46] ;
+  input \\state_reg[1]_rep ;
+  input \\m_payload_i_reg[44] ;
+  input [3:0]\\m_payload_i_reg[3] ;
+  input [3:0]\\m_payload_i_reg[11] ;
+  input [0:0]m_valid_i_reg;
+  input [0:0]D;
+  input \\state_reg[1] ;
+  input m_axi_arready;
+  input [1:0]\\state_reg[1]_0 ;
+
+  wire [0:0]CO;
+  wire [0:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [0:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire \\axaddr_incr[4]_i_2__0_n_0 ;
+  wire \\axaddr_incr[4]_i_3__0_n_0 ;
+  wire \\axaddr_incr[4]_i_4__0_n_0 ;
+  wire \\axaddr_incr[4]_i_5__0_n_0 ;
+  wire \\axaddr_incr[8]_i_2__0_n_0 ;
+  wire \\axaddr_incr[8]_i_3__0_n_0 ;
+  wire \\axaddr_incr[8]_i_4__0_n_0 ;
+  wire \\axaddr_incr[8]_i_5__0_n_0 ;
+  wire [7:0]axaddr_incr_reg;
+  wire \\axaddr_incr_reg[11]_0 ;
+  wire [3:0]\\axaddr_incr_reg[3]_0 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_0 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_1 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_2 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_3 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_4 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_5 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_6 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_7 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_1 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_2 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_3 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_4 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_5 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_6 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_7 ;
+  wire \\axlen_cnt[1]_i_1__1_n_0 ;
+  wire \\axlen_cnt[2]_i_1__1_n_0 ;
+  wire \\axlen_cnt[3]_i_2__0_n_0 ;
+  wire \\axlen_cnt[4]_i_1__0_n_0 ;
+  wire \\axlen_cnt[5]_i_1__0_n_0 ;
+  wire \\axlen_cnt[6]_i_1__0_n_0 ;
+  wire \\axlen_cnt[7]_i_2__0_n_0 ;
+  wire \\axlen_cnt[7]_i_3__0_n_0 ;
+  wire \\axlen_cnt_reg[1]_0 ;
+  wire \\axlen_cnt_reg_n_0_[1] ;
+  wire \\axlen_cnt_reg_n_0_[2] ;
+  wire \\axlen_cnt_reg_n_0_[3] ;
+  wire \\axlen_cnt_reg_n_0_[4] ;
+  wire \\axlen_cnt_reg_n_0_[5] ;
+  wire \\axlen_cnt_reg_n_0_[6] ;
+  wire \\axlen_cnt_reg_n_0_[7] ;
+  wire incr_next_pending;
+  wire m_axi_arready;
+  wire [3:0]\\m_payload_i_reg[11] ;
+  wire [3:0]\\m_payload_i_reg[3] ;
+  wire \\m_payload_i_reg[44] ;
+  wire [7:0]\\m_payload_i_reg[46] ;
+  wire \\m_payload_i_reg[47] ;
+  wire [0:0]m_valid_i_reg;
+  wire next_pending_r_i_2__1_n_0;
+  wire next_pending_r_i_4_n_0;
+  wire next_pending_r_reg_n_0;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire \\state_reg[1] ;
+  wire [1:0]\\state_reg[1]_0 ;
+  wire \\state_reg[1]_rep ;
+  wire [3:3]\\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED ;
+
+  LUT6 #(
+    .INIT(64\'hAAAA6AAAAAAAAAAA)) 
+    \\axaddr_incr[0]_i_15 
+       (.I0(\\m_payload_i_reg[46] [3]),
+        .I1(\\m_payload_i_reg[46] [4]),
+        .I2(\\m_payload_i_reg[46] [5]),
+        .I3(m_axi_arready),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\state_reg[1]_0 [0]),
+        .O(S[3]));
+  LUT6 #(
+    .INIT(64\'h2A2A262A2A2A2A2A)) 
+    \\axaddr_incr[0]_i_16 
+       (.I0(\\m_payload_i_reg[46] [2]),
+        .I1(\\m_payload_i_reg[46] [5]),
+        .I2(\\m_payload_i_reg[46] [4]),
+        .I3(m_axi_arready),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\state_reg[1]_0 [0]),
+        .O(S[2]));
+  LUT6 #(
+    .INIT(64\'h0A0A060A0A0A0A0A)) 
+    \\axaddr_incr[0]_i_17 
+       (.I0(\\m_payload_i_reg[46] [1]),
+        .I1(\\m_payload_i_reg[46] [4]),
+        .I2(\\m_payload_i_reg[46] [5]),
+        .I3(m_axi_arready),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\state_reg[1]_0 [0]),
+        .O(S[1]));
+  LUT6 #(
+    .INIT(64\'h0202010202020202)) 
+    \\axaddr_incr[0]_i_18 
+       (.I0(\\m_payload_i_reg[46] [0]),
+        .I1(\\m_payload_i_reg[46] [4]),
+        .I2(\\m_payload_i_reg[46] [5]),
+        .I3(m_axi_arready),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\state_reg[1]_0 [0]),
+        .O(S[0]));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_2__0 
+       (.I0(\\m_payload_i_reg[3] [3]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[3]),
+        .O(\\axaddr_incr[4]_i_2__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_3__0 
+       (.I0(\\m_payload_i_reg[3] [2]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[2]),
+        .O(\\axaddr_incr[4]_i_3__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_4__0 
+       (.I0(\\m_payload_i_reg[3] [1]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[1]),
+        .O(\\axaddr_incr[4]_i_4__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_5__0 
+       (.I0(\\m_payload_i_reg[3] [0]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[0]),
+        .O(\\axaddr_incr[4]_i_5__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_2__0 
+       (.I0(\\m_payload_i_reg[11] [3]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[7]),
+        .O(\\axaddr_incr[8]_i_2__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_3__0 
+       (.I0(\\m_payload_i_reg[11] [2]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[6]),
+        .O(\\axaddr_incr[8]_i_3__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_4__0 
+       (.I0(\\m_payload_i_reg[11] [1]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[5]),
+        .O(\\axaddr_incr[8]_i_4__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_5__0 
+       (.I0(\\m_payload_i_reg[11] [0]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[4]),
+        .O(\\axaddr_incr[8]_i_5__0_n_0 ));
+  FDRE \\axaddr_incr_reg[0] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(O[0]),
+        .Q(\\axaddr_incr_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[10] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[8]_i_1__0_n_5 ),
+        .Q(axaddr_incr_reg[6]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[11] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[8]_i_1__0_n_4 ),
+        .Q(axaddr_incr_reg[7]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[1] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(O[1]),
+        .Q(\\axaddr_incr_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[2] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(O[2]),
+        .Q(\\axaddr_incr_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[3] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(O[3]),
+        .Q(\\axaddr_incr_reg[3]_0 [3]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[4] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[4]_i_1__0_n_7 ),
+        .Q(axaddr_incr_reg[0]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_incr_reg[4]_i_1__0 
+       (.CI(CO),
+        .CO({\\axaddr_incr_reg[4]_i_1__0_n_0 ,\\axaddr_incr_reg[4]_i_1__0_n_1 ,\\axaddr_incr_reg[4]_i_1__0_n_2 ,\\axaddr_incr_reg[4]_i_1__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_incr_reg[4]_i_1__0_n_4 ,\\axaddr_incr_reg[4]_i_1__0_n_5 ,\\axaddr_incr_reg[4]_i_1__0_n_6 ,\\axaddr_incr_reg[4]_i_1__0_n_7 }),
+        .S({\\axaddr_incr[4]_i_2__0_n_0 ,\\axaddr_incr[4]_i_3__0_n_0 ,\\axaddr_incr[4]_i_4__0_n_0 ,\\axaddr_incr[4]_i_5__0_n_0 }));
+  FDRE \\axaddr_incr_reg[5] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[4]_i_1__0_n_6 ),
+        .Q(axaddr_incr_reg[1]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[6] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[4]_i_1__0_n_5 ),
+        .Q(axaddr_incr_reg[2]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[7] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[4]_i_1__0_n_4 ),
+        .Q(axaddr_incr_reg[3]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[8] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[8]_i_1__0_n_7 ),
+        .Q(axaddr_incr_reg[4]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_incr_reg[8]_i_1__0 
+       (.CI(\\axaddr_incr_reg[4]_i_1__0_n_0 ),
+        .CO({\\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED [3],\\axaddr_incr_reg[8]_i_1__0_n_1 ,\\axaddr_incr_reg[8]_i_1__0_n_2 ,\\axaddr_incr_reg[8]_i_1__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_incr_reg[8]_i_1__0_n_4 ,\\axaddr_incr_reg[8]_i_1__0_n_5 ,\\axaddr_incr_reg[8]_i_1__0_n_6 ,\\axaddr_incr_reg[8]_i_1__0_n_7 }),
+        .S({\\axaddr_incr[8]_i_2__0_n_0 ,\\axaddr_incr[8]_i_3__0_n_0 ,\\axaddr_incr[8]_i_4__0_n_0 ,\\axaddr_incr[8]_i_5__0_n_0 }));
+  FDRE \\axaddr_incr_reg[9] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[8]_i_1__0_n_6 ),
+        .Q(axaddr_incr_reg[5]),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hF88F8888)) 
+    \\axlen_cnt[1]_i_1__1 
+       (.I0(E),
+        .I1(\\m_payload_i_reg[46] [6]),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(Q),
+        .I4(\\axlen_cnt_reg[1]_0 ),
+        .O(\\axlen_cnt[1]_i_1__1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hF8F8F88F88888888)) 
+    \\axlen_cnt[2]_i_1__1 
+       (.I0(E),
+        .I1(\\m_payload_i_reg[46] [7]),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(Q),
+        .I4(\\axlen_cnt_reg_n_0_[1] ),
+        .I5(\\axlen_cnt_reg[1]_0 ),
+        .O(\\axlen_cnt[2]_i_1__1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAA90000FFFFFFFF)) 
+    \\axlen_cnt[3]_i_2__0 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(Q),
+        .I4(\\axlen_cnt_reg[1]_0 ),
+        .I5(\\m_payload_i_reg[47] ),
+        .O(\\axlen_cnt[3]_i_2__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT5 #(
+    .INIT(32\'h55545555)) 
+    \\axlen_cnt[3]_i_3__0 
+       (.I0(E),
+        .I1(\\axlen_cnt_reg_n_0_[6] ),
+        .I2(\\axlen_cnt_reg_n_0_[5] ),
+        .I3(\\axlen_cnt_reg_n_0_[7] ),
+        .I4(next_pending_r_i_4_n_0),
+        .O(\\axlen_cnt_reg[1]_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAAAAA9)) 
+    \\axlen_cnt[4]_i_1__0 
+       (.I0(\\axlen_cnt_reg_n_0_[4] ),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(Q),
+        .I3(\\axlen_cnt_reg_n_0_[2] ),
+        .I4(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[4]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAAAAA9)) 
+    \\axlen_cnt[5]_i_1__0 
+       (.I0(\\axlen_cnt_reg_n_0_[5] ),
+        .I1(Q),
+        .I2(\\axlen_cnt_reg_n_0_[3] ),
+        .I3(\\axlen_cnt_reg_n_0_[2] ),
+        .I4(\\axlen_cnt_reg_n_0_[4] ),
+        .I5(\\axlen_cnt_reg_n_0_[1] ),
+        .O(\\axlen_cnt[5]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT3 #(
+    .INIT(8\'hA6)) 
+    \\axlen_cnt[6]_i_1__0 
+       (.I0(\\axlen_cnt_reg_n_0_[6] ),
+        .I1(\\axlen_cnt[7]_i_3__0_n_0 ),
+        .I2(\\axlen_cnt_reg_n_0_[5] ),
+        .O(\\axlen_cnt[6]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT4 #(
+    .INIT(16\'hA9AA)) 
+    \\axlen_cnt[7]_i_2__0 
+       (.I0(\\axlen_cnt_reg_n_0_[7] ),
+        .I1(\\axlen_cnt_reg_n_0_[5] ),
+        .I2(\\axlen_cnt_reg_n_0_[6] ),
+        .I3(\\axlen_cnt[7]_i_3__0_n_0 ),
+        .O(\\axlen_cnt[7]_i_2__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'h00000001)) 
+    \\axlen_cnt[7]_i_3__0 
+       (.I0(\\axlen_cnt_reg_n_0_[1] ),
+        .I1(\\axlen_cnt_reg_n_0_[4] ),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\axlen_cnt_reg_n_0_[3] ),
+        .I4(Q),
+        .O(\\axlen_cnt[7]_i_3__0_n_0 ));
+  FDRE \\axlen_cnt_reg[0] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(D),
+        .Q(Q),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[1] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[1]_i_1__1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[2] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[2]_i_1__1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[3] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[3]_i_2__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[4] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[4]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[4] ),
+        .R(\\state_reg[1] ));
+  FDRE \\axlen_cnt_reg[5] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[5]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[5] ),
+        .R(\\state_reg[1] ));
+  FDRE \\axlen_cnt_reg[6] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[6]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[6] ),
+        .R(\\state_reg[1] ));
+  FDRE \\axlen_cnt_reg[7] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[7]_i_2__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[7] ),
+        .R(\\state_reg[1] ));
+  LUT5 #(
+    .INIT(32\'hFFFF505C)) 
+    next_pending_r_i_1__2
+       (.I0(next_pending_r_i_2__1_n_0),
+        .I1(next_pending_r_reg_n_0),
+        .I2(\\state_reg[1]_rep ),
+        .I3(E),
+        .I4(\\m_payload_i_reg[44] ),
+        .O(incr_next_pending));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT4 #(
+    .INIT(16\'h0002)) 
+    next_pending_r_i_2__1
+       (.I0(next_pending_r_i_4_n_0),
+        .I1(\\axlen_cnt_reg_n_0_[7] ),
+        .I2(\\axlen_cnt_reg_n_0_[5] ),
+        .I3(\\axlen_cnt_reg_n_0_[6] ),
+        .O(next_pending_r_i_2__1_n_0));
+  LUT4 #(
+    .INIT(16\'h0001)) 
+    next_pending_r_i_4
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[4] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .O(next_pending_r_i_4_n_0));
+  FDRE next_pending_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(incr_next_pending),
+        .Q(next_pending_r_reg_n_0),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_reg_1),
+        .Q(\\axaddr_incr_reg[11]_0 ),
+        .R(1\'b0));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel
+   (m_valid_i_reg,
+    \\state_reg[1]_rep ,
+    m_axi_rready,
+    out,
+    \\skid_buffer_reg[46] ,
+    r_push,
+    aclk,
+    r_rlast,
+    si_rs_rready,
+    m_axi_rvalid,
+    in,
+    areset_d1,
+    D);
+  output m_valid_i_reg;
+  output \\state_reg[1]_rep ;
+  output m_axi_rready;
+  output [33:0]out;
+  output [12:0]\\skid_buffer_reg[46] ;
+  input r_push;
+  input aclk;
+  input r_rlast;
+  input si_rs_rready;
+  input m_axi_rvalid;
+  input [33:0]in;
+  input areset_d1;
+  input [11:0]D;
+
+  wire [11:0]D;
+  wire aclk;
+  wire areset_d1;
+  wire [33:0]in;
+  wire m_axi_rready;
+  wire m_axi_rvalid;
+  wire m_valid_i_reg;
+  wire [33:0]out;
+  wire r_push;
+  wire r_push_r;
+  wire r_rlast;
+  wire rd_data_fifo_0_n_0;
+  wire rd_data_fifo_0_n_3;
+  wire si_rs_rready;
+  wire [12:0]\\skid_buffer_reg[46] ;
+  wire \\state_reg[1]_rep ;
+  wire [12:0]trans_in;
+  wire transaction_fifo_0_n_1;
+
+  FDRE \\r_arid_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[0]),
+        .Q(trans_in[1]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[10] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[10]),
+        .Q(trans_in[11]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[11] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[11]),
+        .Q(trans_in[12]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[1]),
+        .Q(trans_in[2]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[2]),
+        .Q(trans_in[3]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[3]),
+        .Q(trans_in[4]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[4]),
+        .Q(trans_in[5]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[5] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[5]),
+        .Q(trans_in[6]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[6] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[6]),
+        .Q(trans_in[7]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[7] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[7]),
+        .Q(trans_in[8]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[8] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[8]),
+        .Q(trans_in[9]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[9] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[9]),
+        .Q(trans_in[10]),
+        .R(1\'b0));
+  FDRE r_push_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(r_push),
+        .Q(r_push_r),
+        .R(1\'b0));
+  FDRE r_rlast_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(r_rlast),
+        .Q(trans_in[0]),
+        .R(1\'b0));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1 rd_data_fifo_0
+       (.aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\cnt_read_reg[1]_rep__3_0 (rd_data_fifo_0_n_0),
+        .\\cnt_read_reg[2]_rep__0_0 (transaction_fifo_0_n_1),
+        .in(in),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_valid_i_reg(m_valid_i_reg),
+        .out(out),
+        .si_rs_rready(si_rs_rready),
+        .\\state_reg[1]_rep (rd_data_fifo_0_n_3));
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2 transaction_fifo_0
+       (.aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\cnt_read_reg[0]_rep__3 (rd_data_fifo_0_n_3),
+        .\\cnt_read_reg[3]_rep__2 (m_valid_i_reg),
+        .in(trans_in),
+        .m_valid_i_reg(transaction_fifo_0_n_1),
+        .r_push_r(r_push_r),
+        .s_ready_i_reg(rd_data_fifo_0_n_0),
+        .si_rs_rready(si_rs_rready),
+        .\\skid_buffer_reg[46] (\\skid_buffer_reg[46] ),
+        .\\state_reg[1]_rep (\\state_reg[1]_rep ));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm
+   (\\axlen_cnt_reg[7] ,
+    Q,
+    D,
+    \\axaddr_offset_r_reg[0] ,
+    \\axlen_cnt_reg[0] ,
+    \\wrap_second_len_r_reg[3] ,
+    E,
+    s_axburst_eq0_reg,
+    wrap_next_pending,
+    sel_first_i,
+    s_axburst_eq1_reg,
+    r_push_r_reg,
+    \\m_payload_i_reg[0] ,
+    \\m_payload_i_reg[0]_0 ,
+    \\axlen_cnt_reg[3] ,
+    \\axaddr_incr_reg[11] ,
+    m_axi_arvalid,
+    m_valid_i0,
+    \\m_payload_i_reg[0]_1 ,
+    sel_first_reg,
+    sel_first_reg_0,
+    m_axi_arready,
+    si_rs_arvalid,
+    \\axlen_cnt_reg[6] ,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\axaddr_offset_r_reg[3] ,
+    \\cnt_read_reg[1]_rep__0 ,
+    s_axburst_eq1_reg_0,
+    \\m_payload_i_reg[44] ,
+    \\axlen_cnt_reg[0]_0 ,
+    \\wrap_second_len_r_reg[2] ,
+    \\m_payload_i_reg[35] ,
+    \\m_payload_i_reg[47] ,
+    \\m_payload_i_reg[35]_0 ,
+    \\axaddr_offset_r_reg[0]_0 ,
+    \\m_payload_i_reg[3] ,
+    incr_next_pending,
+    \\m_payload_i_reg[44]_0 ,
+    \\state_reg[0]_0 ,
+    next_pending_r_reg,
+    areset_d1,
+    sel_first_reg_1,
+    sel_first_reg_2,
+    s_axi_arvalid,
+    s_ready_i_reg,
+    sel_first_reg_3,
+    aclk);
+  output \\axlen_cnt_reg[7] ;
+  output [1:0]Q;
+  output [1:0]D;
+  output [0:0]\\axaddr_offset_r_reg[0] ;
+  output [0:0]\\axlen_cnt_reg[0] ;
+  output [1:0]\\wrap_second_len_r_reg[3] ;
+  output [0:0]E;
+  output s_axburst_eq0_reg;
+  output wrap_next_pending;
+  output sel_first_i;
+  output s_axburst_eq1_reg;
+  output r_push_r_reg;
+  output \\m_payload_i_reg[0] ;
+  output \\m_payload_i_reg[0]_0 ;
+  output [0:0]\\axlen_cnt_reg[3] ;
+  output \\axaddr_incr_reg[11] ;
+  output m_axi_arvalid;
+  output m_valid_i0;
+  output [0:0]\\m_payload_i_reg[0]_1 ;
+  output sel_first_reg;
+  output sel_first_reg_0;
+  input m_axi_arready;
+  input si_rs_arvalid;
+  input \\axlen_cnt_reg[6] ;
+  input [1:0]\\wrap_second_len_r_reg[3]_0 ;
+  input \\axaddr_offset_r_reg[3] ;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input s_axburst_eq1_reg_0;
+  input [1:0]\\m_payload_i_reg[44] ;
+  input [0:0]\\axlen_cnt_reg[0]_0 ;
+  input [1:0]\\wrap_second_len_r_reg[2] ;
+  input \\m_payload_i_reg[35] ;
+  input [1:0]\\m_payload_i_reg[47] ;
+  input \\m_payload_i_reg[35]_0 ;
+  input [0:0]\\axaddr_offset_r_reg[0]_0 ;
+  input \\m_payload_i_reg[3] ;
+  input incr_next_pending;
+  input \\m_payload_i_reg[44]_0 ;
+  input \\state_reg[0]_0 ;
+  input next_pending_r_reg;
+  input areset_d1;
+  input sel_first_reg_1;
+  input sel_first_reg_2;
+  input s_axi_arvalid;
+  input s_ready_i_reg;
+  input sel_first_reg_3;
+  input aclk;
+
+  wire [1:0]D;
+  wire [0:0]E;
+  wire [1:0]Q;
+  wire aclk;
+  wire areset_d1;
+  wire \\axaddr_incr_reg[11] ;
+  wire [0:0]\\axaddr_offset_r_reg[0] ;
+  wire [0:0]\\axaddr_offset_r_reg[0]_0 ;
+  wire \\axaddr_offset_r_reg[3] ;
+  wire [0:0]\\axlen_cnt_reg[0] ;
+  wire [0:0]\\axlen_cnt_reg[0]_0 ;
+  wire [0:0]\\axlen_cnt_reg[3] ;
+  wire \\axlen_cnt_reg[6] ;
+  wire \\axlen_cnt_reg[7] ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire incr_next_pending;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire \\m_payload_i_reg[0] ;
+  wire \\m_payload_i_reg[0]_0 ;
+  wire [0:0]\\m_payload_i_reg[0]_1 ;
+  wire \\m_payload_i_reg[35] ;
+  wire \\m_payload_i_reg[35]_0 ;
+  wire \\m_payload_i_reg[3] ;
+  wire [1:0]\\m_payload_i_reg[44] ;
+  wire \\m_payload_i_reg[44]_0 ;
+  wire [1:0]\\m_payload_i_reg[47] ;
+  wire m_valid_i0;
+  wire next_pending_r_reg;
+  wire [1:0]next_state;
+  wire r_push_r_reg;
+  wire s_axburst_eq0_reg;
+  wire s_axburst_eq1_reg;
+  wire s_axburst_eq1_reg_0;
+  wire s_axi_arvalid;
+  wire s_ready_i_reg;
+  wire sel_first_i;
+  wire sel_first_reg;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire sel_first_reg_2;
+  wire sel_first_reg_3;
+  wire si_rs_arvalid;
+  wire \\state_reg[0]_0 ;
+  wire \\wrap_cnt_r[3]_i_2__0_n_0 ;
+  wire wrap_next_pending;
+  wire [1:0]\\wrap_second_len_r_reg[2] ;
+  wire [1:0]\\wrap_second_len_r_reg[3] ;
+  wire [1:0]\\wrap_second_len_r_reg[3]_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'hAEAA)) 
+    \\axaddr_incr[0]_i_1__0 
+       (.I0(sel_first_reg_2),
+        .I1(\\m_payload_i_reg[0]_0 ),
+        .I2(\\m_payload_i_reg[0] ),
+        .I3(m_axi_arready),
+        .O(\\axaddr_incr_reg[11] ));
+  LUT6 #(
+    .INIT(64\'hAAAAACAAAAAAA0AA)) 
+    \\axaddr_offset_r[0]_i_1__0 
+       (.I0(\\axaddr_offset_r_reg[0]_0 ),
+        .I1(\\m_payload_i_reg[44] [1]),
+        .I2(Q[0]),
+        .I3(si_rs_arvalid),
+        .I4(Q[1]),
+        .I5(\\m_payload_i_reg[3] ),
+        .O(\\axaddr_offset_r_reg[0] ));
+  LUT6 #(
+    .INIT(64\'h0400FFFF04000400)) 
+    \\axlen_cnt[0]_i_1 
+       (.I0(Q[1]),
+        .I1(si_rs_arvalid),
+        .I2(Q[0]),
+        .I3(\\m_payload_i_reg[44] [1]),
+        .I4(\\axlen_cnt_reg[0]_0 ),
+        .I5(\\axlen_cnt_reg[6] ),
+        .O(\\axlen_cnt_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h0E02)) 
+    \\axlen_cnt[3]_i_1 
+       (.I0(si_rs_arvalid),
+        .I1(\\m_payload_i_reg[0]_0 ),
+        .I2(\\m_payload_i_reg[0] ),
+        .I3(m_axi_arready),
+        .O(\\axlen_cnt_reg[3] ));
+  LUT5 #(
+    .INIT(32\'h00002320)) 
+    \\axlen_cnt[7]_i_1 
+       (.I0(m_axi_arready),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(si_rs_arvalid),
+        .I4(\\axlen_cnt_reg[6] ),
+        .O(\\axlen_cnt_reg[7] ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    m_axi_arvalid_INST_0
+       (.I0(\\m_payload_i_reg[0]_0 ),
+        .I1(\\m_payload_i_reg[0] ),
+        .O(m_axi_arvalid));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'h8F)) 
+    \\m_payload_i[31]_i_1__0 
+       (.I0(\\m_payload_i_reg[0] ),
+        .I1(\\m_payload_i_reg[0]_0 ),
+        .I2(si_rs_arvalid),
+        .O(\\m_payload_i_reg[0]_1 ));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'hFF70FFFF)) 
+    m_valid_i_i_1__1
+       (.I0(\\m_payload_i_reg[0] ),
+        .I1(\\m_payload_i_reg[0]_0 ),
+        .I2(si_rs_arvalid),
+        .I3(s_axi_arvalid),
+        .I4(s_ready_i_reg),
+        .O(m_valid_i0));
+  LUT5 #(
+    .INIT(32\'hFFABEEAA)) 
+    next_pending_r_i_1__1
+       (.I0(\\m_payload_i_reg[44]_0 ),
+        .I1(r_push_r_reg),
+        .I2(E),
+        .I3(\\state_reg[0]_0 ),
+        .I4(next_pending_r_reg),
+        .O(wrap_next_pending));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h20)) 
+    r_push_r_i_1
+       (.I0(m_axi_arready),
+        .I1(\\m_payload_i_reg[0] ),
+        .I2(\\m_payload_i_reg[0]_0 ),
+        .O(r_push_r_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    s_axburst_eq0_i_1__0
+       (.I0(wrap_next_pending),
+        .I1(\\m_payload_i_reg[44] [0]),
+        .I2(sel_first_i),
+        .I3(incr_next_pending),
+        .O(s_axburst_eq0_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT4 #(
+    .INIT(16\'hABA8)) 
+    s_axburst_eq1_i_1__0
+       (.I0(wrap_next_pending),
+        .I1(\\m_payload_i_reg[44] [0]),
+        .I2(sel_first_i),
+        .I3(incr_next_pending),
+        .O(s_axburst_eq1_reg));
+  LUT6 #(
+    .INIT(64\'hFFCFFFFFCCCCCCEE)) 
+    sel_first_i_1__0
+       (.I0(si_rs_arvalid),
+        .I1(areset_d1),
+        .I2(m_axi_arready),
+        .I3(\\m_payload_i_reg[0] ),
+        .I4(\\m_payload_i_reg[0]_0 ),
+        .I5(sel_first_reg_1),
+        .O(sel_first_i));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFC4C4CFCC)) 
+    sel_first_i_1__3
+       (.I0(m_axi_arready),
+        .I1(sel_first_reg_2),
+        .I2(Q[1]),
+        .I3(si_rs_arvalid),
+        .I4(Q[0]),
+        .I5(areset_d1),
+        .O(sel_first_reg));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFC4C4CFCC)) 
+    sel_first_i_1__4
+       (.I0(m_axi_arready),
+        .I1(sel_first_reg_3),
+        .I2(Q[1]),
+        .I3(si_rs_arvalid),
+        .I4(Q[0]),
+        .I5(areset_d1),
+        .O(sel_first_reg_0));
+  LUT6 #(
+    .INIT(64\'h000033333FFF2222)) 
+    \\state[0]_i_1__0 
+       (.I0(si_rs_arvalid),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(s_axburst_eq1_reg_0),
+        .I3(m_axi_arready),
+        .I4(Q[0]),
+        .I5(Q[1]),
+        .O(next_state[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h0FC00040)) 
+    \\state[1]_i_1__0 
+       (.I0(s_axburst_eq1_reg_0),
+        .I1(m_axi_arready),
+        .I2(\\m_payload_i_reg[0]_0 ),
+        .I3(\\m_payload_i_reg[0] ),
+        .I4(\\cnt_read_reg[1]_rep__0 ),
+        .O(next_state[1]));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""state_reg[0]"" *) 
+  FDRE \\state_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[0]),
+        .Q(Q[0]),
+        .R(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""state_reg[0]"" *) 
+  FDRE \\state_reg[0]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[0]),
+        .Q(\\m_payload_i_reg[0]_0 ),
+        .R(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""state_reg[1]"" *) 
+  FDRE \\state_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[1]),
+        .Q(Q[1]),
+        .R(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""state_reg[1]"" *) 
+  FDRE \\state_reg[1]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[1]),
+        .Q(\\m_payload_i_reg[0] ),
+        .R(areset_d1));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\wrap_boundary_axaddr_r[11]_i_1 
+       (.I0(\\m_payload_i_reg[0] ),
+        .I1(si_rs_arvalid),
+        .I2(\\m_payload_i_reg[0]_0 ),
+        .O(E));
+  LUT6 #(
+    .INIT(64\'h5575AA8A5545AA8A)) 
+    \\wrap_cnt_r[0]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[3]_0 [0]),
+        .I1(Q[0]),
+        .I2(si_rs_arvalid),
+        .I3(Q[1]),
+        .I4(\\axaddr_offset_r_reg[3] ),
+        .I5(\\axaddr_offset_r_reg[0] ),
+        .O(D[0]));
+  LUT4 #(
+    .INIT(16\'hA6AA)) 
+    \\wrap_cnt_r[3]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[3] [1]),
+        .I1(\\wrap_second_len_r_reg[2] [0]),
+        .I2(\\wrap_cnt_r[3]_i_2__0_n_0 ),
+        .I3(\\wrap_second_len_r_reg[2] [1]),
+        .O(D[1]));
+  LUT6 #(
+    .INIT(64\'hDD11DD11DD11DDF1)) 
+    \\wrap_cnt_r[3]_i_2__0 
+       (.I0(\\wrap_second_len_r_reg[3]_0 [0]),
+        .I1(E),
+        .I2(\\m_payload_i_reg[35] ),
+        .I3(\\axaddr_offset_r_reg[0] ),
+        .I4(\\m_payload_i_reg[47] [0]),
+        .I5(\\m_payload_i_reg[47] [1]),
+        .O(\\wrap_cnt_r[3]_i_2__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAA8AAA8AAABAAA8A)) 
+    \\wrap_second_len_r[0]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[3]_0 [0]),
+        .I1(Q[0]),
+        .I2(si_rs_arvalid),
+        .I3(Q[1]),
+        .I4(\\axaddr_offset_r_reg[3] ),
+        .I5(\\axaddr_offset_r_reg[0] ),
+        .O(\\wrap_second_len_r_reg[3] [0]));
+  LUT6 #(
+    .INIT(64\'hFFFFF4FF44444444)) 
+    \\wrap_second_len_r[3]_i_1__0 
+       (.I0(E),
+        .I1(\\wrap_second_len_r_reg[3]_0 [1]),
+        .I2(\\axaddr_offset_r_reg[0] ),
+        .I3(\\m_payload_i_reg[35] ),
+        .I4(\\m_payload_i_reg[47] [0]),
+        .I5(\\m_payload_i_reg[35]_0 ),
+        .O(\\wrap_second_len_r_reg[3] [1]));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo
+   (\\cnt_read_reg[0]_rep__0_0 ,
+    \\cnt_read_reg[1]_rep__0_0 ,
+    \\state_reg[0] ,
+    SR,
+    bresp_push,
+    bvalid_i_reg,
+    out,
+    b_push,
+    shandshake_r,
+    areset_d1,
+    Q,
+    mhandshake_r,
+    si_rs_bready,
+    si_rs_bvalid,
+    \\cnt_read_reg[1]_0 ,
+    in,
+    aclk);
+  output \\cnt_read_reg[0]_rep__0_0 ;
+  output \\cnt_read_reg[1]_rep__0_0 ;
+  output \\state_reg[0] ;
+  output [0:0]SR;
+  output bresp_push;
+  output bvalid_i_reg;
+  output [11:0]out;
+  input b_push;
+  input shandshake_r;
+  input areset_d1;
+  input [7:0]Q;
+  input mhandshake_r;
+  input si_rs_bready;
+  input si_rs_bvalid;
+  input [1:0]\\cnt_read_reg[1]_0 ;
+  input [15:0]in;
+  input aclk;
+
+  wire [7:0]Q;
+  wire [0:0]SR;
+  wire aclk;
+  wire areset_d1;
+  wire b_push;
+  wire bresp_push;
+  wire bvalid_i_i_2_n_0;
+  wire bvalid_i_reg;
+  wire [1:1]cnt_read;
+  wire \\cnt_read[0]_i_1_n_0 ;
+  wire [1:0]cnt_read_0;
+  wire \\cnt_read_reg[0]_rep__0_0 ;
+  wire \\cnt_read_reg[0]_rep_n_0 ;
+  wire [1:0]\\cnt_read_reg[1]_0 ;
+  wire \\cnt_read_reg[1]_rep__0_0 ;
+  wire \\cnt_read_reg[1]_rep_n_0 ;
+  wire [15:0]in;
+  wire \\memory_reg[3][0]_srl4_i_2__0_n_0 ;
+  wire \\memory_reg[3][0]_srl4_i_3_n_0 ;
+  wire \\memory_reg[3][0]_srl4_i_4_n_0 ;
+  wire \\memory_reg[3][0]_srl4_n_0 ;
+  wire \\memory_reg[3][1]_srl4_n_0 ;
+  wire \\memory_reg[3][2]_srl4_n_0 ;
+  wire \\memory_reg[3][3]_srl4_n_0 ;
+  wire mhandshake_r;
+  wire [11:0]out;
+  wire shandshake_r;
+  wire si_rs_bready;
+  wire si_rs_bvalid;
+  wire \\state_reg[0] ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair112"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\bresp_cnt[7]_i_1 
+       (.I0(areset_d1),
+        .I1(bresp_push),
+        .O(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair112"" *) 
+  LUT4 #(
+    .INIT(16\'h002A)) 
+    bvalid_i_i_1
+       (.I0(bvalid_i_i_2_n_0),
+        .I1(si_rs_bready),
+        .I2(si_rs_bvalid),
+        .I3(areset_d1),
+        .O(bvalid_i_reg));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00070707)) 
+    bvalid_i_i_2
+       (.I0(\\cnt_read_reg[0]_rep__0_0 ),
+        .I1(\\cnt_read_reg[1]_rep__0_0 ),
+        .I2(shandshake_r),
+        .I3(\\cnt_read_reg[1]_0 [1]),
+        .I4(\\cnt_read_reg[1]_0 [0]),
+        .I5(si_rs_bvalid),
+        .O(bvalid_i_i_2_n_0));
+  (* SOFT_HLUTNM = ""soft_lutpair111"" *) 
+  LUT3 #(
+    .INIT(8\'h96)) 
+    \\cnt_read[0]_i_1 
+       (.I0(\\cnt_read_reg[0]_rep__0_0 ),
+        .I1(b_push),
+        .I2(shandshake_r),
+        .O(\\cnt_read[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair111"" *) 
+  LUT4 #(
+    .INIT(16\'hE718)) 
+    \\cnt_read[1]_i_1 
+       (.I0(\\cnt_read_reg[0]_rep__0_0 ),
+        .I1(b_push),
+        .I2(shandshake_r),
+        .I3(\\cnt_read_reg[1]_rep__0_0 ),
+        .O(cnt_read));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1_n_0 ),
+        .Q(cnt_read_0[0]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__0_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(cnt_read),
+        .Q(cnt_read_0[1]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(cnt_read),
+        .Q(\\cnt_read_reg[1]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(cnt_read),
+        .Q(\\cnt_read_reg[1]_rep__0_0 ),
+        .S(areset_d1));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][0]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[0]),
+        .Q(\\memory_reg[3][0]_srl4_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0000000000000082)) 
+    \\memory_reg[3][0]_srl4_i_1__0 
+       (.I0(\\memory_reg[3][0]_srl4_i_2__0_n_0 ),
+        .I1(\\memory_reg[3][1]_srl4_n_0 ),
+        .I2(Q[1]),
+        .I3(Q[7]),
+        .I4(\\memory_reg[3][0]_srl4_i_3_n_0 ),
+        .I5(\\memory_reg[3][0]_srl4_i_4_n_0 ),
+        .O(bresp_push));
+  LUT5 #(
+    .INIT(32\'h04000004)) 
+    \\memory_reg[3][0]_srl4_i_2__0 
+       (.I0(Q[5]),
+        .I1(mhandshake_r),
+        .I2(Q[4]),
+        .I3(\\memory_reg[3][3]_srl4_n_0 ),
+        .I4(Q[3]),
+        .O(\\memory_reg[3][0]_srl4_i_2__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair110"" *) 
+  LUT5 #(
+    .INIT(32\'hFFAEAEAE)) 
+    \\memory_reg[3][0]_srl4_i_3 
+       (.I0(Q[6]),
+        .I1(\\memory_reg[3][0]_srl4_n_0 ),
+        .I2(Q[0]),
+        .I3(\\cnt_read_reg[1]_rep__0_0 ),
+        .I4(\\cnt_read_reg[0]_rep__0_0 ),
+        .O(\\memory_reg[3][0]_srl4_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'h2FF2)) 
+    \\memory_reg[3][0]_srl4_i_4 
+       (.I0(Q[0]),
+        .I1(\\memory_reg[3][0]_srl4_n_0 ),
+        .I2(\\memory_reg[3][2]_srl4_n_0 ),
+        .I3(Q[2]),
+        .O(\\memory_reg[3][0]_srl4_i_4_n_0 ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][10]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[6]),
+        .Q(out[2]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][11]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[7]),
+        .Q(out[3]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][12]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[8]),
+        .Q(out[4]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][13]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[9]),
+        .Q(out[5]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][14]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[10]),
+        .Q(out[6]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][15]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[11]),
+        .Q(out[7]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][16]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[12]),
+        .Q(out[8]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][17]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[13]),
+        .Q(out[9]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][18]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[14]),
+        .Q(out[10]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][19]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[15]),
+        .Q(out[11]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][1]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[1]),
+        .Q(\\memory_reg[3][1]_srl4_n_0 ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][2]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[2]),
+        .Q(\\memory_reg[3][2]_srl4_n_0 ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][3]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[3]),
+        .Q(\\memory_reg[3][3]_srl4_n_0 ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][8]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[4]),
+        .Q(out[0]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][9]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[5]),
+        .Q(out[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair110"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\state[0]_i_2 
+       (.I0(\\cnt_read_reg[1]_rep__0_0 ),
+        .I1(\\cnt_read_reg[0]_rep__0_0 ),
+        .O(\\state_reg[0] ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_simple_fifo"" *) 
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0
+   (Q,
+    mhandshake,
+    m_axi_bready,
+    \\skid_buffer_reg[1] ,
+    bresp_push,
+    shandshake_r,
+    m_axi_bvalid,
+    mhandshake_r,
+    in,
+    aclk,
+    areset_d1);
+  output [1:0]Q;
+  output mhandshake;
+  output m_axi_bready;
+  output [1:0]\\skid_buffer_reg[1] ;
+  input bresp_push;
+  input shandshake_r;
+  input m_axi_bvalid;
+  input mhandshake_r;
+  input [1:0]in;
+  input aclk;
+  input areset_d1;
+
+  wire [1:0]Q;
+  wire aclk;
+  wire areset_d1;
+  wire bresp_push;
+  wire \\cnt_read[0]_i_1__0_n_0 ;
+  wire \\cnt_read[1]_i_1__0_n_0 ;
+  wire [1:0]in;
+  wire m_axi_bready;
+  wire m_axi_bvalid;
+  wire mhandshake;
+  wire mhandshake_r;
+  wire shandshake_r;
+  wire [1:0]\\skid_buffer_reg[1] ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair114"" *) 
+  LUT3 #(
+    .INIT(8\'h96)) 
+    \\cnt_read[0]_i_1__0 
+       (.I0(Q[0]),
+        .I1(bresp_push),
+        .I2(shandshake_r),
+        .O(\\cnt_read[0]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair114"" *) 
+  LUT4 #(
+    .INIT(16\'hE718)) 
+    \\cnt_read[1]_i_1__0 
+       (.I0(Q[0]),
+        .I1(bresp_push),
+        .I2(shandshake_r),
+        .I3(Q[1]),
+        .O(\\cnt_read[1]_i_1__0_n_0 ));
+  (* KEEP = ""yes"" *) 
+  FDSE \\cnt_read_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__0_n_0 ),
+        .Q(Q[0]),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  FDSE \\cnt_read_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__0_n_0 ),
+        .Q(Q[1]),
+        .S(areset_d1));
+  (* SOFT_HLUTNM = ""soft_lutpair113"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    m_axi_bready_INST_0
+       (.I0(Q[1]),
+        .I1(Q[0]),
+        .I2(mhandshake_r),
+        .O(m_axi_bready));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][0]_srl4 
+       (.A0(Q[0]),
+        .A1(Q[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(bresp_push),
+        .CLK(aclk),
+        .D(in[0]),
+        .Q(\\skid_buffer_reg[1] [0]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][1]_srl4 
+       (.A0(Q[0]),
+        .A1(Q[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(bresp_push),
+        .CLK(aclk),
+        .D(in[1]),
+        .Q(\\skid_buffer_reg[1] [1]));
+  (* SOFT_HLUTNM = ""soft_lutpair113"" *) 
+  LUT4 #(
+    .INIT(16\'h2000)) 
+    mhandshake_r_i_1
+       (.I0(m_axi_bvalid),
+        .I1(mhandshake_r),
+        .I2(Q[0]),
+        .I3(Q[1]),
+        .O(mhandshake));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_simple_fifo"" *) 
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1
+   (\\cnt_read_reg[1]_rep__3_0 ,
+    m_valid_i_reg,
+    m_axi_rready,
+    \\state_reg[1]_rep ,
+    out,
+    si_rs_rready,
+    m_axi_rvalid,
+    \\cnt_read_reg[2]_rep__0_0 ,
+    in,
+    aclk,
+    areset_d1);
+  output \\cnt_read_reg[1]_rep__3_0 ;
+  output m_valid_i_reg;
+  output m_axi_rready;
+  output \\state_reg[1]_rep ;
+  output [33:0]out;
+  input si_rs_rready;
+  input m_axi_rvalid;
+  input \\cnt_read_reg[2]_rep__0_0 ;
+  input [33:0]in;
+  input aclk;
+  input areset_d1;
+
+  wire aclk;
+  wire areset_d1;
+  wire [4:0]cnt_read;
+  wire \\cnt_read[0]_i_1__1_n_0 ;
+  wire \\cnt_read[1]_i_1__1_n_0 ;
+  wire \\cnt_read[2]_i_1_n_0 ;
+  wire \\cnt_read[3]_i_1_n_0 ;
+  wire \\cnt_read[3]_i_2_n_0 ;
+  wire \\cnt_read[4]_i_1_n_0 ;
+  wire \\cnt_read[4]_i_2_n_0 ;
+  wire \\cnt_read[4]_i_3_n_0 ;
+  wire \\cnt_read_reg[0]_rep__0_n_0 ;
+  wire \\cnt_read_reg[0]_rep__1_n_0 ;
+  wire \\cnt_read_reg[0]_rep__2_n_0 ;
+  wire \\cnt_read_reg[0]_rep__3_n_0 ;
+  wire \\cnt_read_reg[0]_rep_n_0 ;
+  wire \\cnt_read_reg[1]_rep__0_n_0 ;
+  wire \\cnt_read_reg[1]_rep__1_n_0 ;
+  wire \\cnt_read_reg[1]_rep__2_n_0 ;
+  wire \\cnt_read_reg[1]_rep__3_0 ;
+  wire \\cnt_read_reg[1]_rep__3_n_0 ;
+  wire \\cnt_read_reg[1]_rep_n_0 ;
+  wire \\cnt_read_reg[2]_rep__0_0 ;
+  wire \\cnt_read_reg[2]_rep__0_n_0 ;
+  wire \\cnt_read_reg[2]_rep__1_n_0 ;
+  wire \\cnt_read_reg[2]_rep__2_n_0 ;
+  wire \\cnt_read_reg[2]_rep_n_0 ;
+  wire \\cnt_read_reg[3]_rep__0_n_0 ;
+  wire \\cnt_read_reg[3]_rep__1_n_0 ;
+  wire \\cnt_read_reg[3]_rep__2_n_0 ;
+  wire \\cnt_read_reg[3]_rep_n_0 ;
+  wire \\cnt_read_reg[4]_rep__0_n_0 ;
+  wire \\cnt_read_reg[4]_rep__1_n_0 ;
+  wire \\cnt_read_reg[4]_rep__2_n_0 ;
+  wire \\cnt_read_reg[4]_rep_n_0 ;
+  wire [33:0]in;
+  wire m_axi_rready;
+  wire m_axi_rvalid;
+  wire m_valid_i_reg;
+  wire [33:0]out;
+  wire si_rs_rready;
+  wire \\state_reg[1]_rep ;
+  wire wr_en0;
+  wire \\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
+
+  LUT3 #(
+    .INIT(8\'h96)) 
+    \\cnt_read[0]_i_1__1 
+       (.I0(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[1]_rep__3_0 ),
+        .I2(\\cnt_read[3]_i_2_n_0 ),
+        .O(\\cnt_read[0]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'hE718)) 
+    \\cnt_read[1]_i_1__1 
+       (.I0(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[1]_rep__3_0 ),
+        .I2(\\cnt_read[3]_i_2_n_0 ),
+        .I3(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .O(\\cnt_read[1]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT5 #(
+    .INIT(32\'hFE7F0180)) 
+    \\cnt_read[2]_i_1 
+       (.I0(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_0 ),
+        .I3(\\cnt_read[3]_i_2_n_0 ),
+        .I4(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .O(\\cnt_read[2]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hDFFFFFFB20000004)) 
+    \\cnt_read[3]_i_1 
+       (.I0(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .I1(\\cnt_read[3]_i_2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_0 ),
+        .I3(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I4(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I5(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .O(\\cnt_read[3]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h08808880FFFFFFFF)) 
+    \\cnt_read[3]_i_2 
+       (.I0(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I3(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I4(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I5(m_axi_rvalid),
+        .O(\\cnt_read[3]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\cnt_read[3]_i_3 
+       (.I0(m_valid_i_reg),
+        .I1(si_rs_rready),
+        .O(\\cnt_read_reg[1]_rep__3_0 ));
+  LUT5 #(
+    .INIT(32\'h9AA69AAA)) 
+    \\cnt_read[4]_i_1 
+       (.I0(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .I1(\\cnt_read[4]_i_2_n_0 ),
+        .I2(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I3(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I4(\\cnt_read[4]_i_3_n_0 ),
+        .O(\\cnt_read[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFFF7F77)) 
+    \\cnt_read[4]_i_2 
+       (.I0(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I1(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I2(m_valid_i_reg),
+        .I3(si_rs_rready),
+        .I4(\\cnt_read[3]_i_2_n_0 ),
+        .O(\\cnt_read[4]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT5 #(
+    .INIT(32\'h00000400)) 
+    \\cnt_read[4]_i_3 
+       (.I0(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I1(si_rs_rready),
+        .I2(m_valid_i_reg),
+        .I3(\\cnt_read[3]_i_2_n_0 ),
+        .I4(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .O(\\cnt_read[4]_i_3_n_0 ));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(cnt_read[0]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__3 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(cnt_read[1]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__3 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(cnt_read[2]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(cnt_read[3]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(cnt_read[4]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .S(areset_d1));
+  LUT5 #(
+    .INIT(32\'hF77F777F)) 
+    m_axi_rready_INST_0
+       (.I0(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .I3(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I4(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .O(m_axi_rready));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF80000000)) 
+    m_valid_i_i_2
+       (.I0(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I3(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I4(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I5(\\cnt_read_reg[2]_rep__0_0 ),
+        .O(m_valid_i_reg));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][0]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[0]),
+        .Q(out[0]),
+        .Q31(\\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
+  LUT6 #(
+    .INIT(64\'h800AAAAAAAAAAAAA)) 
+    \\memory_reg[31][0]_srl32_i_1 
+       (.I0(m_axi_rvalid),
+        .I1(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I2(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I3(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I4(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I5(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .O(wr_en0));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][10]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[10]),
+        .Q(out[10]),
+        .Q31(\\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][11]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[11]),
+        .Q(out[11]),
+        .Q31(\\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][12]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[12]),
+        .Q(out[12]),
+        .Q31(\\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][13]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[13]),
+        .Q(out[13]),
+        .Q31(\\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][14]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[14]),
+        .Q(out[14]),
+        .Q31(\\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][15]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[15]),
+        .Q(out[15]),
+        .Q31(\\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][16]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[16]),
+        .Q(out[16]),
+        .Q31(\\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][17]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[17]),
+        .Q(out[17]),
+        .Q31(\\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][18]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[18]),
+        .Q(out[18]),
+        .Q31(\\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][19]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[19]),
+        .Q(out[19]),
+        .Q31(\\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][1]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[1]),
+        .Q(out[1]),
+        .Q31(\\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][20]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[20]),
+        .Q(out[20]),
+        .Q31(\\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][21]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[21]),
+        .Q(out[21]),
+        .Q31(\\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][22]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[22]),
+        .Q(out[22]),
+        .Q31(\\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][23]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[23]),
+        .Q(out[23]),
+        .Q31(\\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][24]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[24]),
+        .Q(out[24]),
+        .Q31(\\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][25]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[25]),
+        .Q(out[25]),
+        .Q31(\\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][26]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[26]),
+        .Q(out[26]),
+        .Q31(\\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][27]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[27]),
+        .Q(out[27]),
+        .Q31(\\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][28]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[28]),
+        .Q(out[28]),
+        .Q31(\\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][29]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[29]),
+        .Q(out[29]),
+        .Q31(\\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][2]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[2]),
+        .Q(out[2]),
+        .Q31(\\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][30]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[30]),
+        .Q(out[30]),
+        .Q31(\\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][31]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[31]),
+        .Q(out[31]),
+        .Q31(\\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][32]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[32]),
+        .Q(out[32]),
+        .Q31(\\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][33]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[33]),
+        .Q(out[33]),
+        .Q31(\\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][3]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[3]),
+        .Q(out[3]),
+        .Q31(\\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][4]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[4]),
+        .Q(out[4]),
+        .Q31(\\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][5]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[5]),
+        .Q(out[5]),
+        .Q31(\\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][6]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[6]),
+        .Q(out[6]),
+        .Q31(\\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][7]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[7]),
+        .Q(out[7]),
+        .Q31(\\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][8]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[8]),
+        .Q(out[8]),
+        .Q31(\\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][9]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[9]),
+        .Q(out[9]),
+        .Q31(\\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
+  LUT5 #(
+    .INIT(32\'h7C000000)) 
+    \\state[1]_i_4 
+       (.I0(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I1(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I3(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I4(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .O(\\state_reg[1]_rep ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_simple_fifo"" *) 
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2
+   (\\state_reg[1]_rep ,
+    m_valid_i_reg,
+    \\skid_buffer_reg[46] ,
+    s_ready_i_reg,
+    r_push_r,
+    si_rs_rready,
+    \\cnt_read_reg[3]_rep__2 ,
+    \\cnt_read_reg[0]_rep__3 ,
+    i'b'n,
+    aclk,
+    areset_d1);
+  output \\state_reg[1]_rep ;
+  output m_valid_i_reg;
+  output [12:0]\\skid_buffer_reg[46] ;
+  input s_ready_i_reg;
+  input r_push_r;
+  input si_rs_rready;
+  input \\cnt_read_reg[3]_rep__2 ;
+  input \\cnt_read_reg[0]_rep__3 ;
+  input [12:0]in;
+  input aclk;
+  input areset_d1;
+
+  wire aclk;
+  wire areset_d1;
+  wire [4:0]cnt_read;
+  wire \\cnt_read[0]_i_1__2_n_0 ;
+  wire \\cnt_read[1]_i_1__2_n_0 ;
+  wire \\cnt_read[2]_i_1__0_n_0 ;
+  wire \\cnt_read[3]_i_1__0_n_0 ;
+  wire \\cnt_read[4]_i_1__0_n_0 ;
+  wire \\cnt_read[4]_i_2__0_n_0 ;
+  wire \\cnt_read[4]_i_3__0_n_0 ;
+  wire \\cnt_read_reg[0]_rep__0_n_0 ;
+  wire \\cnt_read_reg[0]_rep__1_n_0 ;
+  wire \\cnt_read_reg[0]_rep__3 ;
+  wire \\cnt_read_reg[0]_rep_n_0 ;
+  wire \\cnt_read_reg[1]_rep__0_n_0 ;
+  wire \\cnt_read_reg[1]_rep_n_0 ;
+  wire \\cnt_read_reg[2]_rep__0_n_0 ;
+  wire \\cnt_read_reg[2]_rep_n_0 ;
+  wire \\cnt_read_reg[3]_rep__0_n_0 ;
+  wire \\cnt_read_reg[3]_rep__2 ;
+  wire \\cnt_read_reg[3]_rep_n_0 ;
+  wire \\cnt_read_reg[4]_rep__0_n_0 ;
+  wire \\cnt_read_reg[4]_rep_n_0 ;
+  wire [12:0]in;
+  wire m_valid_i_reg;
+  wire r_push_r;
+  wire s_ready_i_reg;
+  wire si_rs_rready;
+  wire [12:0]\\skid_buffer_reg[46] ;
+  wire \\state_reg[1]_rep ;
+  wire \\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT3 #(
+    .INIT(8\'h69)) 
+    \\cnt_read[0]_i_1__2 
+       (.I0(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .I1(s_ready_i_reg),
+        .I2(r_push_r),
+        .O(\\cnt_read[0]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT4 #(
+    .INIT(16\'h7E81)) 
+    \\cnt_read[1]_i_1__2 
+       (.I0(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .I1(r_push_r),
+        .I2(s_ready_i_reg),
+        .I3(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .O(\\cnt_read[1]_i_1__2_n_0 ));
+  LUT5 #(
+    .INIT(32\'h7FFE8001)) 
+    \\cnt_read[2]_i_1__0 
+       (.I0(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I1(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .I2(r_push_r),
+        .I3(s_ready_i_reg),
+        .I4(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .O(\\cnt_read[2]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'h7FFFFFFE80000001)) 
+    \\cnt_read[3]_i_1__0 
+       (.I0(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I1(s_ready_i_reg),
+        .I2(r_push_r),
+        .I3(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .I4(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .I5(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .O(\\cnt_read[3]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'h9AA69AAA)) 
+    \\cnt_read[4]_i_1__0 
+       (.I0(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .I1(\\cnt_read[4]_i_2__0_n_0 ),
+        .I2(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .I3(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .I4(\\cnt_read[4]_i_3__0_n_0 ),
+        .O(\\cnt_read[4]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'h5DFFFFFF)) 
+    \\cnt_read[4]_i_2__0 
+       (.I0(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I1(si_rs_rready),
+        .I2(\\cnt_read_reg[3]_rep__2 ),
+        .I3(r_push_r),
+        .I4(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .O(\\cnt_read[4]_i_2__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'h00000010)) 
+    \\cnt_read[4]_i_3__0 
+       (.I0(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .I1(r_push_r),
+        .I2(si_rs_rready),
+        .I3(\\cnt_read_reg[3]_rep__2 ),
+        .I4(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .O(\\cnt_read[4]_i_3__0_n_0 ));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__2_n_0 ),
+        .Q(cnt_read[0]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__2_n_0 ),
+        .Q(cnt_read[1]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1__0_n_0 ),
+        .Q(cnt_read[2]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1__0_n_0 ),
+        .Q(cnt_read[3]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1__0_n_0 ),
+        .Q(cnt_read[4]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .S(areset_d1));
+  LUT5 #(
+    .INIT(32\'h80000000)) 
+    m_valid_i_i_3
+       (.I0(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .I1(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I3(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .I4(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .O(m_valid_i_reg));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][0]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[0]),
+        .Q(\\skid_buffer_reg[46] [0]),
+        .Q31(\\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][10]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[10]),
+        .Q(\\skid_buffer_reg[46] [10]),
+        .Q31(\\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][11]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[11]),
+        .Q(\\skid_buffer_reg[46] [11]),
+        .Q31(\\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][12]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[12]),
+        .Q(\\skid_buffer_reg[46] [12]),
+        .Q31(\\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][1]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[1]),
+        .Q(\\skid_buffer_reg[46] [1]),
+        .Q31(\\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][2]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[2]),
+        .Q(\\skid_buffer_reg[46] [2]),
+        .Q31(\\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][3]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[3]),
+        .Q(\\skid_buffer_reg[46] [3]),
+        .Q31(\\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][4]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[4]),
+        .Q(\\skid_buffer_reg[46] [4]),
+        .Q31(\\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][5]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[5]),
+        .Q(\\skid_buffer_reg[46] [5]),
+        .Q31(\\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][6]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[6]),
+        .Q(\\skid_buffer_reg[46] [6]),
+        .Q31(\\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][7]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[7]),
+        .Q(\\skid_buffer_reg[46] [7]),
+        .Q31(\\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][8]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[8]),
+        .Q(\\skid_buffer_reg[46] [8]),
+        .Q31(\\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][9]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[9]),
+        .Q(\\skid_buffer_reg[46] [9]),
+        .Q31(\\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
+  LUT6 #(
+    .INIT(64\'hBFEEAAAAAAAAAAAA)) 
+    \\state[1]_i_3 
+       (.I0(\\cnt_read_reg[0]_rep__3 ),
+        .I1(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I2(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .I3(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .I4(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .I5(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .O(\\state_reg[1]_rep ));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm
+   (E,
+    Q,
+    sel_first_reg,
+    \\wrap_boundary_axaddr_r_reg[0] ,
+    \\axlen_cnt_reg[7] ,
+    s_axburst_eq0_reg,
+    wrap_next_pending,
+    sel_first_i,
+    incr_next_pending,
+    s_axburst_eq1_reg,
+    \\m_payload_i_reg[0] ,
+    b_push,
+    m_axi_awvalid,
+    sel_first_reg_0,
+    sel_first_reg_1,
+    si_rs_awvalid,
+    \\axlen_cnt_reg[7]_0 ,
+    \\m_payload_i_reg[39] ,
+    \\m_payload_i_reg[46] ,
+    next_pending_r_reg,
+    next_pending_r_reg_0,
+    \\axlen_cnt_reg[3] ,
+    areset_d1,
+    sel_first_reg_2,
+    \\cnt_read_reg[1]_rep__0 ,
+    s_axburst_eq1_reg_0,
+    m_axi_awready,
+    \\cnt_read_reg[1]_rep__0_0 ,
+    \\cnt_read_reg[0]_rep__0 ,
+    sel_first_reg_3,
+    sel_first__0,
+    aclk);
+  output [0:0]E;
+  output [1:0]Q;
+  output sel_first_reg;
+  output [0:0]\\wrap_boundary_axaddr_r_reg[0] ;
+  output \\axlen_cnt_reg[7] ;
+  output s_axburst_eq0_reg;
+  output wrap_next_pending;
+  output sel_first_i;
+  output incr_next_pending;
+  output s_axburst_eq1_reg;
+  output [0:0]\\m_payload_i_reg[0] ;
+  output b_push;
+  output m_axi_awvalid;
+  output sel_first_reg_0;
+  output sel_first_reg_1;
+  input si_rs_awvalid;
+  input \\axlen_cnt_reg[7]_0 ;
+  input [0:0]\\m_payload_i_reg[39] ;
+  input \\m_payload_i_reg[46] ;
+  input next_pending_r_reg;
+  input next_pending_r_reg_0;
+  input \\axlen_cnt_reg[3] ;
+  input areset_d1;
+  input sel_first_reg_2;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input s_axburst_eq1_reg_0;
+  input m_axi_awready;
+  input \\cnt_read_reg[1]_rep__0_0 ;
+  input \\cnt_read_reg[0]_rep__0 ;
+  input sel_first_reg_3;
+  input sel_first__0;
+  input aclk;
+
+  wire [0:0]E;
+  wire [1:0]Q;
+  wire aclk;
+  wire areset_d1;
+  wire \\axlen_cnt_reg[3] ;
+  wire \\axlen_cnt_reg[7] ;
+  wire \\axlen_cnt_reg[7]_0 ;
+  wire b_push;
+  wire \\cnt_read_reg[0]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0_0 ;
+  wire incr_next_pending;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire [0:0]\\m_payload_i_reg[0] ;
+  wire [0:0]\\m_payload_i_reg[39] ;
+  wire \\m_payload_i_reg[46] ;
+  wire next_pending_r_reg;
+  wire next_pending_r_reg_0;
+  wire [1:0]next_state;
+  wire s_axburst_eq0_reg;
+  wire s_axburst_eq1_reg;
+  wire s_axburst_eq1_reg_0;
+  wire sel_first__0;
+  wire sel_first_i;
+  wire sel_first_reg;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire sel_first_reg_2;
+  wire sel_first_reg_3;
+  wire si_rs_awvalid;
+  wire [0:0]\\wrap_boundary_axaddr_r_reg[0] ;
+  wire wrap_next_pending;
+
+  (* SOFT_HLUTNM = ""soft_lutpair104"" *) 
+  LUT4 #(
+    .INIT(16\'h04FF)) 
+    \\axlen_cnt[3]_i_1__0 
+       (.I0(Q[0]),
+        .I1(si_rs_awvalid),
+        .I2(Q[1]),
+        .I3(sel_first_reg),
+        .O(E));
+  (* SOFT_HLUTNM = ""soft_lutpair104"" *) 
+  LUT5 #(
+    .INIT(32\'h000004FF)) 
+    \\axlen_cnt[7]_i_1__0 
+       (.I0(Q[0]),
+        .I1(si_rs_awvalid),
+        .I2(Q[1]),
+        .I3(sel_first_reg),
+        .I4(\\axlen_cnt_reg[7]_0 ),
+        .O(\\axlen_cnt_reg[7] ));
+  (* SOFT_HLUTNM = ""soft_lutpair106"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    m_axi_awvalid_INST_0
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .O(m_axi_awvalid));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_payload_i[31]_i_1 
+       (.I0(b_push),
+        .I1(si_rs_awvalid),
+        .O(\\m_payload_i_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hA000A0A0A800A8A8)) 
+    \\memory_reg[3][0]_srl4_i_1 
+       (.I0(Q[0]),
+        .I1(m_axi_awready),
+        .I2(Q[1]),
+        .I3(\\cnt_read_reg[0]_rep__0 ),
+        .I4(\\cnt_read_reg[1]_rep__0_0 ),
+        .I5(s_axburst_eq1_reg_0),
+        .O(b_push));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    next_pending_r_i_1
+       (.I0(\\m_payload_i_reg[46] ),
+        .I1(\\wrap_boundary_axaddr_r_reg[0] ),
+        .I2(next_pending_r_reg),
+        .I3(sel_first_reg),
+        .I4(\\axlen_cnt_reg[7]_0 ),
+        .O(incr_next_pending));
+  LUT5 #(
+    .INIT(32\'hB888B8BB)) 
+    next_pending_r_i_1__0
+       (.I0(\\m_payload_i_reg[46] ),
+        .I1(\\wrap_boundary_axaddr_r_reg[0] ),
+        .I2(next_pending_r_reg_0),
+        .I3(sel_first_reg),
+        .I4(\\axlen_cnt_reg[3] ),
+        .O(wrap_next_pending));
+  LUT6 #(
+    .INIT(64\'h0CAE0CFF00FF00FF)) 
+    next_pending_r_i_3
+       (.I0(s_axburst_eq1_reg_0),
+        .I1(\\cnt_read_reg[1]_rep__0_0 ),
+        .I2(\\cnt_read_reg[0]_rep__0 ),
+        .I3(Q[1]),
+        .I4(m_axi_awready),
+        .I5(Q[0]),
+        .O(sel_first_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair105"" *) 
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    s_axburst_eq0_i_1
+       (.I0(wrap_next_pending),
+        .I1(\\m_payload_i_reg[39] ),
+        .I2(sel_first_i),
+        .I3(incr_next_pending),
+        .O(s_axburst_eq0_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair105"" *) 
+  LUT4 #(
+    .INIT(16\'hABA8)) 
+    s_axburst_eq1_i_1
+       (.I0(wrap_next_pending),
+        .I1(\\m_payload_i_reg[39] ),
+        .I2(sel_first_i),
+        .I3(incr_next_pending),
+        .O(s_axburst_eq1_reg));
+  LUT6 #(
+    .INIT(64\'hFFFFFF04FF04FF04)) 
+    sel_first_i_1
+       (.I0(Q[1]),
+        .I1(si_rs_awvalid),
+        .I2(Q[0]),
+        .I3(areset_d1),
+        .I4(sel_first_reg),
+        .I5(sel_first_reg_2),
+        .O(sel_first_i));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF88888F88)) 
+    sel_first_i_1__1
+       (.I0(sel_first_reg),
+        .I1(sel_first_reg_3),
+        .I2(Q[1]),
+        .I3(si_rs_awvalid),
+        .I4(Q[0]),
+        .I5(areset_d1),
+        .O(sel_first_reg_0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF88888F88)) 
+    sel_first_i_1__2
+       (.I0(sel_first_reg),
+        .I1(sel_first__0),
+        .I2(Q[1]),
+        .I3(si_rs_awvalid),
+        .I4(Q[0]),
+        .I5(areset_d1),
+        .O(sel_first_reg_1));
+  LUT6 #(
+    .INIT(64\'hF232FE32FE3EFE3E)) 
+    \\state[0]_i_1 
+       (.I0(si_rs_awvalid),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(\\cnt_read_reg[1]_rep__0 ),
+        .I4(s_axburst_eq1_reg_0),
+        .I5(m_axi_awready),
+        .O(next_state[0]));
+  LUT6 #(
+    .INIT(64\'h20E0202000E00000)) 
+    \\state[1]_i_1 
+       (.I0(m_axi_awready),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(\\cnt_read_reg[0]_rep__0 ),
+        .I4(\\cnt_read_reg[1]_rep__0_0 ),
+        .I5(s_axburst_eq1_reg_0),
+        .O(next_state[1]));
+  (* KEEP = ""yes"" *) 
+  FDRE \\state_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[0]),
+        .Q(Q[0]),
+        .R(areset_d1));
+  (* KEEP = ""yes"" *) 
+  FDRE \\state_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[1]),
+        .Q(Q[1]),
+        .R(areset_d1));
+  (* SOFT_HLUTNM = ""soft_lutpair106"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\wrap_boundary_axaddr_r[11]_i_1__0 
+       (.I0(Q[1]),
+        .I1(si_rs_awvalid),
+        .I2(Q[0]),
+        .O(\\wrap_boundary_axaddr_r_reg[0] ));
+endmodule
+
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd
+   (next_pending_r_reg_0,
+    sel_first_reg_0,
+    next_pending_r_reg_1,
+    m_axi_awaddr,
+    \\axaddr_offset_r_reg[3]_0 ,
+    \\wrap_second_len_r_reg[3]_0 ,
+    wrap_next_pending,
+    aclk,
+    sel_first_reg_1,
+    E,
+    \\m_payload_i_reg[47] ,
+    \\cnt_read_reg[1]_rep__0 ,
+    axaddr_incr_reg,
+    \\m_payload_i_reg[38] ,
+    \\axaddr_incr_reg[3] ,
+    D,
+    \\wrap_second_len_r_reg[3]_1 ,
+    \\state_reg[0] ,
+    \\wrap_second_len_r_reg[3]_2 ,
+    \\m_payload_i_reg[6] );
+  output next_pending_r_reg_0;
+  output sel_first_reg_0;
+  output next_pending_r_reg_1;
+  output [11:0]m_axi_awaddr;
+  output [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  output [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input wrap_next_pending;
+  input aclk;
+  input sel_first_reg_1;
+  input [0:0]E;
+  input [18:0]\\m_payload_i_reg[47] ;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input [7:0]axaddr_incr_reg;
+  input \\m_payload_i_reg[38] ;
+  input [3:0]\\axaddr_incr_reg[3] ;
+  input [3:0]D;
+  input [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [0:0]\\state_reg[0] ;
+  input [3:0]\\wrap_second_len_r_reg[3]_2 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire aclk;
+  wire [7:0]axaddr_incr_reg;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire [11:0]axaddr_wrap;
+  wire [11:0]axaddr_wrap0;
+  wire \\axaddr_wrap[0]_i_1_n_0 ;
+  wire \\axaddr_wrap[10]_i_1_n_0 ;
+  wire \\axaddr_wrap[11]_i_1_n_0 ;
+  wire \\axaddr_wrap[11]_i_3_n_0 ;
+  wire \\axaddr_wrap[11]_i_4_n_0 ;
+  wire \\axaddr_wrap[11]_i_5_n_0 ;
+  wire \\axaddr_wrap[11]_i_6_n_0 ;
+  wire \\axaddr_wrap[11]_i_7_n_0 ;
+  wire \\axaddr_wrap[11]_i_8_n_0 ;
+  wire \\axaddr_wrap[1]_i_1_n_0 ;
+  wire \\axaddr_wrap[2]_i_1_n_0 ;
+  wire \\axaddr_wrap[3]_i_1_n_0 ;
+  wire \\axaddr_wrap[3]_i_3_n_0 ;
+  wire \\axaddr_wrap[3]_i_4_n_0 ;
+  wire \\axaddr_wrap[3]_i_5_n_0 ;
+  wire \\axaddr_wrap[3]_i_6_n_0 ;
+  wire \\axaddr_wrap[4]_i_1_n_0 ;
+  wire \\axaddr_wrap[5]_i_1_n_0 ;
+  wire \\axaddr_wrap[6]_i_1_n_0 ;
+  wire \\axaddr_wrap[7]_i_1_n_0 ;
+  wire \\axaddr_wrap[7]_i_3_n_0 ;
+  wire \\axaddr_wrap[7]_i_4_n_0 ;
+  wire \\axaddr_wrap[7]_i_5_n_0 ;
+  wire \\axaddr_wrap[7]_i_6_n_0 ;
+  wire \\axaddr_wrap[8]_i_1_n_0 ;
+  wire \\axaddr_wrap[9]_i_1_n_0 ;
+  wire \\axaddr_wrap_reg[11]_i_2_n_1 ;
+  wire \\axaddr_wrap_reg[11]_i_2_n_2 ;
+  wire \\axaddr_wrap_reg[11]_i_2_n_3 ;
+  wire \\axaddr_wrap_reg[3]_i_2_n_0 ;
+  wire \\axaddr_wrap_reg[3]_i_2_n_1 ;
+  wire \\axaddr_wrap_reg[3]_i_2_n_2 ;
+  wire \\axaddr_wrap_reg[3]_i_2_n_3 ;
+  wire \\axaddr_wrap_reg[7]_i_2_n_0 ;
+  wire \\axaddr_wrap_reg[7]_i_2_n_1 ;
+  wire \\axaddr_wrap_reg[7]_i_2_n_2 ;
+  wire \\axaddr_wrap_reg[7]_i_2_n_3 ;
+  wire \\axlen_cnt[0]_i_1__2_n_0 ;
+  wire \\axlen_cnt[1]_i_1__0_n_0 ;
+  wire \\axlen_cnt[2]_i_1__0_n_0 ;
+  wire \\axlen_cnt[3]_i_1__1_n_0 ;
+  wire \\axlen_cnt_reg_n_0_[0] ;
+  wire \\axlen_cnt_reg_n_0_[1] ;
+  wire \\axlen_cnt_reg_n_0_[2] ;
+  wire \\axlen_cnt_reg_n_0_[3] ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire [11:0]m_axi_awaddr;
+  wire \\m_payload_i_reg[38] ;
+  wire [18:0]\\m_payload_i_reg[47] ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire next_pending_r_reg_0;
+  wire next_pending_r_reg_1;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire [0:0]\\state_reg[0] ;
+  wire [11:0]wrap_boundary_axaddr_r;
+  wire [3:0]wrap_cnt_r;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_2 ;
+  wire [3:3]\\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED ;
+
+  FDRE \\axaddr_offset_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[0]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[1]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[2]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[3]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [3]),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[0]_i_1 
+       (.I0(\\m_payload_i_reg[47] [0]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[0]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[0]),
+        .O(\\axaddr_wrap[0]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[10]_i_1 
+       (.I0(\\m_payload_i_reg[47] [10]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[10]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[10]),
+        .O(\\axaddr_wrap[10]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[11]_i_1 
+       (.I0(\\m_payload_i_reg[47] [11]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[11]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[11]),
+        .O(\\axaddr_wrap[11]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair109"" *) 
+  LUT3 #(
+    .INIT(8\'hBE)) 
+    \\axaddr_wrap[11]_i_3 
+       (.I0(\\axaddr_wrap[11]_i_8_n_0 ),
+        .I1(wrap_cnt_r[3]),
+        .I2(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axaddr_wrap[11]_i_3_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_4 
+       (.I0(axaddr_wrap[11]),
+        .O(\\axaddr_wrap[11]_i_4_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_5 
+       (.I0(axaddr_wrap[10]),
+        .O(\\axaddr_wrap[11]_i_5_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_6 
+       (.I0(axaddr_wrap[9]),
+        .O(\\axaddr_wrap[11]_i_6_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_7 
+       (.I0(axaddr_wrap[8]),
+        .O(\\axaddr_wrap[11]_i_7_n_0 ));
+  LUT6 #(
+    .INIT(64\'h6FF6FFFFFFFF6FF6)) 
+    \\axaddr_wrap[11]_i_8 
+       (.I0(wrap_cnt_r[2]),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(wrap_cnt_r[1]),
+        .I4(\\axlen_cnt_reg_n_0_[0] ),
+        .I5(wrap_cnt_r[0]),
+        .O(\\axaddr_wrap[11]_i_8_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[1]_i_1 
+       (.I0(\\m_payload_i_reg[47] [1]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[1]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[1]),
+        .O(\\axaddr_wrap[1]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[2]_i_1 
+       (.I0(\\m_payload_i_reg[47] [2]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[2]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[2]),
+        .O(\\axaddr_wrap[2]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[3]_i_1 
+       (.I0(\\m_payload_i_reg[47] [3]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[3]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[3]),
+        .O(\\axaddr_wrap[3]_i_1_n_0 ));
+  LUT3 #(
+    .INIT(8\'h6A)) 
+    \\axaddr_wrap[3]_i_3 
+       (.I0(axaddr_wrap[3]),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axaddr_wrap[3]_i_4 
+       (.I0(axaddr_wrap[2]),
+        .I1(\\m_payload_i_reg[47] [12]),
+        .I2(\\m_payload_i_reg[47] [13]),
+        .O(\\axaddr_wrap[3]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axaddr_wrap[3]_i_5 
+       (.I0(axaddr_wrap[1]),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8\'hA9)) 
+    \\axaddr_wrap[3]_i_6 
+       (.I0(axaddr_wrap[0]),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_6_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[4]_i_1 
+       (.I0(\\m_payload_i_reg[47] [4]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[4]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[4]),
+        .O(\\axaddr_wrap[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[5]_i_1 
+       (.I0(\\m_payload_i_reg[47] [5]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[5]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[5]),
+        .O(\\axaddr_wrap[5]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[6]_i_1 
+       (.I0(\\m_payload_i_reg[47] [6]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[6]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[6]),
+        .O(\\axaddr_wrap[6]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[7]_i_1 
+       (.I0(\\m_payload_i_reg[47] [7]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[7]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[7]),
+        .O(\\axaddr_wrap[7]_i_1_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_3 
+       (.I0(axaddr_wrap[7]),
+        .O(\\axaddr_wrap[7]_i_3_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_4 
+       (.I0(axaddr_wrap[6]),
+        .O(\\axaddr_wrap[7]_i_4_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_5 
+       (.I0(axaddr_wrap[5]),
+        .O(\\axaddr_wrap[7]_i_5_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_6 
+       (.I0(axaddr_wrap[4]),
+        .O(\\axaddr_wrap[7]_i_6_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[8]_i_1 
+       (.I0(\\m_payload_i_reg[47] [8]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[8]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[8]),
+        .O(\\axaddr_wrap[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[9]_i_1 
+       (.I0(\\m_payload_i_reg[47] [9]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[9]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[9]),
+        .O(\\axaddr_wrap[9]_i_1_n_0 ));
+  FDRE \\axaddr_wrap_reg[0] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[0]_i_1_n_0 ),
+        .Q(axaddr_wrap[0]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[10] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[10]_i_1_n_0 ),
+        .Q(axaddr_wrap[10]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[11] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[11]_i_1_n_0 ),
+        .Q(axaddr_wrap[11]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[11]_i_2 
+       (.CI(\\axaddr_wrap_reg[7]_i_2_n_0 ),
+        .CO({\\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED [3],\\axaddr_wrap_reg[11]_i_2_n_1 ,\\axaddr_wrap_reg[11]_i_2_n_2 ,\\axaddr_wrap_reg[11]_i_2_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(axaddr_wrap0[11:8]),
+        .S({\\axaddr_wrap[11]_i_4_n_0 ,\\axaddr_wrap[11]_i_5_n_0 ,\\axaddr_wrap[11]_i_6_n_0 ,\\axaddr_wrap[11]_i_7_n_0 }));
+  FDRE \\axaddr_wrap_reg[1] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[1]_i_1_n_0 ),
+        .Q(axaddr_wrap[1]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[2] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[2]_i_1_n_0 ),
+        .Q(axaddr_wrap[2]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[3] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[3]_i_1_n_0 ),
+        .Q(axaddr_wrap[3]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[3]_i_2 
+       (.CI(1\'b0),
+        .CO({\\axaddr_wrap_reg[3]_i_2_n_0 ,\\axaddr_wrap_reg[3]_i_2_n_1 ,\\axaddr_wrap_reg[3]_i_2_n_2 ,\\axaddr_wrap_reg[3]_i_2_n_3 }),
+        .CYINIT(1\'b0),
+        .DI(axaddr_wrap[3:0]),
+        .O(axaddr_wrap0[3:0]),
+        .S({\\axaddr_wrap[3]_i_3_n_0 ,\\axaddr_wrap[3]_i_4_n_0 ,\\axaddr_wrap[3]_i_5_n_0 ,\\axaddr_wrap[3]_i_6_n_0 }));
+  FDRE \\axaddr_wrap_reg[4] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[4]_i_1_n_0 ),
+        .Q(axaddr_wrap[4]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[5] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[5]_i_1_n_0 ),
+        .Q(axaddr_wrap[5]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[6] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[6]_i_1_n_0 ),
+        .Q(axaddr_wrap[6]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[7] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[7]_i_1_n_0 ),
+        .Q(axaddr_wrap[7]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[7]_i_2 
+       (.CI(\\axaddr_wrap_reg[3]_i_2_n_0 ),
+        .CO({\\axaddr_wrap_reg[7]_i_2_n_0 ,\\axaddr_wrap_reg[7]_i_2_n_1 ,\\axaddr_wrap_reg[7]_i_2_n_2 ,\\axaddr_wrap_reg[7]_i_2_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(axaddr_wrap0[7:4]),
+        .S({\\axaddr_wrap[7]_i_3_n_0 ,\\axaddr_wrap[7]_i_4_n_0 ,\\axaddr_wrap[7]_i_5_n_0 ,\\axaddr_wrap[7]_i_6_n_0 }));
+  FDRE \\axaddr_wrap_reg[8] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[8]_i_1_n_0 ),
+        .Q(axaddr_wrap[8]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[9] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[9]_i_1_n_0 ),
+        .Q(axaddr_wrap[9]),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hFFFF555400005554)) 
+    \\axlen_cnt[0]_i_1__2 
+       (.I0(\\axlen_cnt_reg_n_0_[0] ),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\axlen_cnt_reg_n_0_[3] ),
+        .I4(E),
+        .I5(\\m_payload_i_reg[47] [15]),
+        .O(\\axlen_cnt[0]_i_1__2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAC3AAC3AAC3AAC0)) 
+    \\axlen_cnt[1]_i_1__0 
+       (.I0(\\m_payload_i_reg[47] [16]),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(E),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[1]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAACCC3AAAACCC0)) 
+    \\axlen_cnt[2]_i_1__0 
+       (.I0(\\m_payload_i_reg[47] [17]),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(E),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[2]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFAAA80000AAA8)) 
+    \\axlen_cnt[3]_i_1__1 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(E),
+        .I5(\\m_payload_i_reg[47] [18]),
+        .O(\\axlen_cnt[3]_i_1__1_n_0 ));
+  FDRE \\axlen_cnt_reg[0] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[0]_i_1__2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[1] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[1]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[2] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[2]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[3] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[3]_i_1__1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[3] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[0]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[0]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [0]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [0]),
+        .O(m_axi_awaddr[0]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[10]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[10]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[6]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [10]),
+        .O(m_axi_awaddr[10]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[11]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[11]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[7]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [11]),
+        .O(m_axi_awaddr[11]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[1]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[1]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [1]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [1]),
+        .O(m_axi_awaddr[1]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[2]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[2]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [2]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [2]),
+        .O(m_axi_awaddr[2]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[3]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[3]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [3]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [3]),
+        .O(m_axi_awaddr[3]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[4]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[4]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[0]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [4]),
+        .O(m_axi_awaddr[4]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[5]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[5]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[1]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [5]),
+        .O(m_axi_awaddr[5]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[6]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[6]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[2]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [6]),
+        .O(m_axi_awaddr[6]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[7]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[7]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[3]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [7]),
+        .O(m_axi_awaddr[7]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[8]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[8]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[4]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [8]),
+        .O(m_axi_awaddr[8]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[9]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[9]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[5]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [9]),
+        .O(m_axi_awaddr[9]));
+  (* SOFT_HLUTNM = ""soft_lutpair109"" *) 
+  LUT3 #(
+    .INIT(8\'h01)) 
+    next_pending_r_i_2__0
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .O(next_pending_r_reg_1));
+  FDRE next_pending_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(wrap_next_pending),
+        .Q(next_pending_r_reg_0),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_reg_1),
+        .Q(sel_first_reg_0),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [0]),
+        .Q(wrap_boundary_axaddr_r[0]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [10]),
+        .Q(wrap_boundary_axaddr_r[10]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [11]),
+        .Q(wrap_boundary_axaddr_r[11]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [1]),
+        .Q(wrap_boundary_axaddr_r[1]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [2]),
+        .Q(wrap_boundary_axaddr_r[2]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [3]),
+        .Q(wrap_boundary_axaddr_r[3]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [4]),
+        .Q(wrap_boundary_axaddr_r[4]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [5]),
+        .Q(wrap_boundary_axaddr_r[5]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [6]),
+        .Q(wrap_boundary_axaddr_r[6]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [7]),
+        .Q(wrap_boundary_axaddr_r[7]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [8]),
+        .Q(wrap_boundary_axaddr_r[8]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [9]),
+        .Q(wrap_boundary_axaddr_r[9]),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [0]),
+        .Q(wrap_cnt_r[0]),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [1]),
+        .Q(wrap_cnt_r[1]),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [2]),
+        .Q(wrap_cnt_r[2]),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [3]),
+        .Q(wrap_cnt_r[3]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [0]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [1]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [2]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [3]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [3]),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_wrap_cmd"" *) 
+module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3
+   (next_pending_r_reg_0,
+    sel_first_reg_0,
+    next_pending_r_reg_1,
+    m_axi_araddr,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\axaddr_offset_r_reg[3]_0 ,
+    wrap_next_pending,
+    aclk,
+    sel_first_reg_1,
+    E,
+    \\m_payload_i_reg[47] ,
+    \\state_reg[1] ,
+    si_rs_arvalid,
+    \\state_reg[1]_rep ,
+    axaddr_incr_reg,
+    \\m_payload_i_reg[38] ,
+    \\axaddr_incr_reg[3] ,
+    \\axaddr_offset_r_reg[3]_1 ,
+    \\m_payload_i_reg[35] ,
+    \\m_payload_i_reg[47]_0 ,
+    \\wrap_second_len_r_reg[3]_1 ,
+    m_valid_i_reg,
+    \\wrap_second_len_r_reg[3]_2 ,
+    \\m_payload_i_reg[6] );
+  output next_pending_r_reg_0;
+  output sel_first_reg_0;
+  output next_pending_r_reg_1;
+  output [11:0]m_axi_araddr;
+  output [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  output [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  input wrap_next_pending;
+  input aclk;
+  input sel_first_reg_1;
+  input [0:0]E;
+  input [18:0]\\m_payload_i_reg[47] ;
+  input [1:0]\\state_reg[1] ;
+  input si_rs_arvalid;
+  input \\state_reg[1]_rep ;
+  input [7:0]axaddr_incr_reg;
+  input \\m_payload_i_reg[38] ;
+  input [3:0]\\axaddr_incr_reg[3] ;
+  input \\axaddr_offset_r_reg[3]_1 ;
+  input \\m_payload_i_reg[35] ;
+  input [3:0]\\m_payload_i_reg[47]_0 ;
+  input [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [0:0]m_valid_i_reg;
+  input [2:0]\\wrap_second_len_r_reg[3]_2 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [0:0]E;
+  wire aclk;
+  wire [7:0]axaddr_incr_reg;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire \\axaddr_offset_r_reg[3]_1 ;
+  wire \\axaddr_wrap[0]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[10]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_3__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_4__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_5__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_6__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_7__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_8__0_n_0 ;
+  wire \\axaddr_wrap[1]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[2]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[3]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[3]_i_3_n_0 ;
+  wire \\axaddr_wrap[3]_i_4_n_0 ;
+  wire \\axaddr_wrap[3]_i_5_n_0 ;
+  wire \\axaddr_wrap[3]_i_6_n_0 ;
+  wire \\axaddr_wrap[4]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[5]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[6]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_3__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_4__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_5__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_6__0_n_0 ;
+  wire \\axaddr_wrap[8]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[9]_i_1__0_n_0 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_1 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_2 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_3 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_4 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_5 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_6 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_7 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_0 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_1 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_2 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_3 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_4 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_5 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_6 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_7 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_0 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_1 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_2 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_3 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_4 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_5 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_6 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_7 ;
+  wire \\axaddr_wrap_reg_n_0_[0] ;
+  wire \\axaddr_wrap_reg_n_0_[10] ;
+  wire \\axaddr_wrap_reg_n_0_[11] ;
+  wire \\axaddr_wrap_reg_n_0_[1] ;
+  wire \\axaddr_wrap_reg_n_0_[2] ;
+  wire \\axaddr_wrap_reg_n_0_[3] ;
+  wire \\axaddr_wrap_reg_n_0_[4] ;
+  wire \\axaddr_wrap_reg_n_0_[5] ;
+  wire \\axaddr_wrap_reg_n_0_[6] ;
+  wire \\axaddr_wrap_reg_n_0_[7] ;
+  wire \\axaddr_wrap_reg_n_0_[8] ;
+  wire \\axaddr_wrap_reg_n_0_[9] ;
+  wire \\axlen_cnt[0]_i_1__0_n_0 ;
+  wire \\axlen_cnt[1]_i_1__2_n_0 ;
+  wire \\axlen_cnt[2]_i_1__2_n_0 ;
+  wire \\axlen_cnt[3]_i_1__2_n_0 ;
+  wire \\axlen_cnt_reg_n_0_[0] ;
+  wire \\axlen_cnt_reg_n_0_[1] ;
+  wire \\axlen_cnt_reg_n_0_[2] ;
+  wire \\axlen_cnt_reg_n_0_[3] ;
+  wire [11:0]m_axi_araddr;
+  wire \\m_payload_i_reg[35] ;
+  wire \\m_payload_i_reg[38] ;
+  wire [18:0]\\m_payload_i_reg[47] ;
+  wire [3:0]\\m_payload_i_reg[47]_0 ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire [0:0]m_valid_i_reg;
+  wire next_pending_r_reg_0;
+  wire next_pending_r_reg_1;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire si_rs_arvalid;
+  wire [1:0]\\state_reg[1] ;
+  wire \\state_reg[1]_rep ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[0] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[10] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[11] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[1] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[2] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[3] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[4] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[5] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[6] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[7] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[8] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[9] ;
+  wire \\wrap_cnt_r[1]_i_1_n_0 ;
+  wire \\wrap_cnt_r_reg_n_0_[0] ;
+  wire \\wrap_cnt_r_reg_n_0_[1] ;
+  wire \\wrap_cnt_r_reg_n_0_[2] ;
+  wire \\wrap_cnt_r_reg_n_0_[3] ;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  wire [2:0]\\wrap_second_len_r_reg[3]_2 ;
+  wire [3:3]\\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED ;
+
+  FDRE \\axaddr_offset_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[47]_0 [0]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[47]_0 [1]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[47]_0 [2]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[47]_0 [3]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [3]),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[0]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[3]_i_2__0_n_7 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[0] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [0]),
+        .O(\\axaddr_wrap[0]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[10]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[11]_i_2__0_n_5 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[10] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [10]),
+        .O(\\axaddr_wrap[10]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[11]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[11]_i_2__0_n_4 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[11] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [11]),
+        .O(\\axaddr_wrap[11]_i_1__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hF6)) 
+    \\axaddr_wrap[11]_i_3__0 
+       (.I0(\\wrap_cnt_r_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[3] ),
+        .I2(\\axaddr_wrap[11]_i_8__0_n_0 ),
+        .O(\\axaddr_wrap[11]_i_3__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_4__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[11] ),
+        .O(\\axaddr_wrap[11]_i_4__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_5__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[10] ),
+        .O(\\axaddr_wrap[11]_i_5__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_6__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[9] ),
+        .O(\\axaddr_wrap[11]_i_6__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_7__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[8] ),
+        .O(\\axaddr_wrap[11]_i_7__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'h6FF6FFFFFFFF6FF6)) 
+    \\axaddr_wrap[11]_i_8__0 
+       (.I0(\\wrap_cnt_r_reg_n_0_[0] ),
+        .I1(\\axlen_cnt_reg_n_0_[0] ),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\wrap_cnt_r_reg_n_0_[2] ),
+        .I4(\\axlen_cnt_reg_n_0_[1] ),
+        .I5(\\wrap_cnt_r_reg_n_0_[1] ),
+        .O(\\axaddr_wrap[11]_i_8__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[1]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[3]_i_2__0_n_6 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[1] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [1]),
+        .O(\\axaddr_wrap[1]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[2]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[3]_i_2__0_n_5 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[2] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [2]),
+        .O(\\axaddr_wrap[2]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[3]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[3]_i_2__0_n_4 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[3] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [3]),
+        .O(\\axaddr_wrap[3]_i_1__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h6A)) 
+    \\axaddr_wrap[3]_i_3 
+       (.I0(\\axaddr_wrap_reg_n_0_[3] ),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axaddr_wrap[3]_i_4 
+       (.I0(\\axaddr_wrap_reg_n_0_[2] ),
+        .I1(\\m_payload_i_reg[47] [12]),
+        .I2(\\m_payload_i_reg[47] [13]),
+        .O(\\axaddr_wrap[3]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axaddr_wrap[3]_i_5 
+       (.I0(\\axaddr_wrap_reg_n_0_[1] ),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8\'hA9)) 
+    \\axaddr_wrap[3]_i_6 
+       (.I0(\\axaddr_wrap_reg_n_0_[0] ),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_6_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[4]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[7]_i_2__0_n_7 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[4] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [4]),
+        .O(\\axaddr_wrap[4]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[5]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[7]_i_2__0_n_6 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[5] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [5]),
+        .O(\\axaddr_wrap[5]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[6]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[7]_i_2__0_n_5 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[6] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [6]),
+        .O(\\axaddr_wrap[6]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[7]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[7]_i_2__0_n_4 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[7] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [7]),
+        .O(\\axaddr_wrap[7]_i_1__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_3__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[7] ),
+        .O(\\axaddr_wrap[7]_i_3__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_4__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[6] ),
+        .O(\\axaddr_wrap[7]_i_4__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_5__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[5] ),
+        .O(\\axaddr_wrap[7]_i_5__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_6__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[4] ),
+        .O(\\axaddr_wrap[7]_i_6__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[8]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[11]_i_2__0_n_7 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[8] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [8]),
+        .O(\\axaddr_wrap[8]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[9]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[11]_i_2__0_n_6 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[9] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [9]),
+        .O(\\axaddr_wrap[9]_i_1__0_n_0 ));
+  FDRE \\axaddr_wrap_reg[0] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[0]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[10] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[10]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[11] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[11]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[11] ),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[11]_i_2__0 
+       (.CI(\\axaddr_wrap_reg[7]_i_2__0_n_0 ),
+        .CO({\\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED [3],\\axaddr_wrap_reg[11]_i_2__0_n_1 ,\\axaddr_wrap_reg[11]_i_2__0_n_2 ,\\axaddr_wrap_reg[11]_i_2__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_wrap_reg[11]_i_2__0_n_4 ,\\axaddr_wrap_reg[11]_i_2__0_n_5 ,\\axaddr_wrap_reg[11]_i_2__0_n_6 ,\\axaddr_wrap_reg[11]_i_2__0_n_7 }),
+        .S({\\axaddr_wrap[11]_i_4__0_n_0 ,\\axaddr_wrap[11]_i_5__0_n_0 ,\\axaddr_wrap[11]_i_6__0_n_0 ,\\axaddr_wrap[11]_i_7__0_n_0 }));
+  FDRE \\axaddr_wrap_reg[1] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[1]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[2] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[2]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[3] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[3]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[3] ),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[3]_i_2__0 
+       (.CI(1\'b0),
+        .CO({\\axaddr_wrap_reg[3]_i_2__0_n_0 ,\\axaddr_wrap_reg[3]_i_2__0_n_1 ,\\axaddr_wrap_reg[3]_i_2__0_n_2 ,\\axaddr_wrap_reg[3]_i_2__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({\\axaddr_wrap_reg_n_0_[3] ,\\axaddr_wrap_reg_n_0_[2] ,\\axaddr_wrap_reg_n_0_[1] ,\\axaddr_wrap_reg_n_0_[0] }),
+        .O({\\axaddr_wrap_reg[3]_i_2__0_n_4 ,\\axaddr_wrap_reg[3]_i_2__0_n_5 ,\\axaddr_wrap_reg[3]_i_2__0_n_6 ,\\axaddr_wrap_reg[3]_i_2__0_n_7 }),
+        .S({\\axaddr_wrap[3]_i_3_n_0 ,\\axaddr_wrap[3]_i_4_n_0 ,\\axaddr_wrap[3]_i_5_n_0 ,\\axaddr_wrap[3]_i_6_n_0 }));
+  FDRE \\axaddr_wrap_reg[4] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[4]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[5] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[5]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[6] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[6]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[7] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[7]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[7] ),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[7]_i_2__0 
+       (.CI(\\axaddr_wrap_reg[3]_i_2__0_n_0 ),
+        .CO({\\axaddr_wrap_reg[7]_i_2__0_n_0 ,\\axaddr_wrap_reg[7]_i_2__0_n_1 ,\\axaddr_wrap_reg[7]_i_2__0_n_2 ,\\axaddr_wrap_reg[7]_i_2__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_wrap_reg[7]_i_2__0_n_4 ,\\axaddr_wrap_reg[7]_i_2__0_n_5 ,\\axaddr_wrap_reg[7]_i_2__0_n_6 ,\\axaddr_wrap_reg[7]_i_2__0_n_7 }),
+        .S({\\axaddr_wrap[7]_i_3__0_n_0 ,\\axaddr_wrap[7]_i_4__0_n_0 ,\\axaddr_wrap[7]_i_5__0_n_0 ,\\axaddr_wrap[7]_i_6__0_n_0 }));
+  FDRE \\axaddr_wrap_reg[8] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[8]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[9] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[9]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[9] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hA3A3A3A3A3A3A3A0)) 
+    \\axlen_cnt[0]_i_1__0 
+       (.I0(\\m_payload_i_reg[47] [15]),
+        .I1(\\axlen_cnt_reg_n_0_[0] ),
+        .I2(E),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[0]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAC3AAC3AAC3AAC0)) 
+    \\axlen_cnt[1]_i_1__2 
+       (.I0(\\m_payload_i_reg[47] [16]),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(E),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[1]_i_1__2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAACCC3AAAACCC0)) 
+    \\axlen_cnt[2]_i_1__2 
+       (.I0(\\m_payload_i_reg[47] [17]),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(E),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[2]_i_1__2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFAAA80000AAA8)) 
+    \\axlen_cnt[3]_i_1__2 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(E),
+        .I5(\\m_payload_i_reg[47] [18]),
+        .O(\\axlen_cnt[3]_i_1__2_n_0 ));
+  FDRE \\axlen_cnt_reg[0] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[0]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[1] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[1]_i_1__2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[2] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[2]_i_1__2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[3] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[3]_i_1__2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[3] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[0]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[0] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [0]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [0]),
+        .O(m_axi_araddr[0]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[10]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[10] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[6]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [10]),
+        .O(m_axi_araddr[10]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[11]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[11] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[7]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [11]),
+        .O(m_axi_araddr[11]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[1]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[1] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [1]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [1]),
+        .O(m_axi_araddr[1]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[2]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[2] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [2]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [2]),
+        .O(m_axi_araddr[2]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[3]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[3] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [3]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [3]),
+        .O(m_axi_araddr[3]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[4]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[4] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[0]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [4]),
+        .O(m_axi_araddr[4]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[5]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[5] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[1]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [5]),
+        .O(m_axi_araddr[5]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[6]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[6] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[2]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [6]),
+        .O(m_axi_araddr[6]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[7]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[7] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[3]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [7]),
+        .O(m_axi_araddr[7]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[8]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[8] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[4]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [8]),
+        .O(m_axi_araddr[8]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[9]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[9] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[5]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [9]),
+        .O(m_axi_araddr[9]));
+  LUT6 #(
+    .INIT(64\'hFBFBFBFBFBFBFB00)) 
+    next_pending_r_i_2__2
+       (.I0(\\state_reg[1] [0]),
+        .I1(si_rs_arvalid),
+        .I2(\\state_reg[1] [1]),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(next_pending_r_reg_1));
+  FDRE next_pending_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(wrap_next_pending),
+        .Q(next_pending_r_reg_0),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_reg_1),
+        .Q(sel_first_reg_0),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [0]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [10]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [11]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [1]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [2]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [3]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [4]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [5]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [6]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [7]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [8]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [9]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[9] ),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h13D320E0)) 
+    \\wrap_cnt_r[1]_i_1 
+       (.I0(\\wrap_second_len_r_reg[3]_0 [0]),
+        .I1(E),
+        .I2(\\axaddr_offset_r_reg[3]_1 ),
+        .I3(\\m_payload_i_reg[35] ),
+        .I4(\\wrap_second_len_r_reg[3]_0 [1]),
+        .O(\\wrap_cnt_r[1]_i_1_n_0 ));
+  FDRE \\wrap_cnt_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [0]),
+        .Q(\\wrap_cnt_r_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_cnt_r[1]_i_1_n_0 ),
+        .Q(\\wrap_cnt_r_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [1]),
+        .Q(\\wrap_cnt_r_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [2]),
+        .Q(\\wrap_cnt_r_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [0]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [1]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [2]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [3]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [3]),
+        .R(1\'b0));
+endmodule
+
+module design_1_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice
+   (s_axi_awready,
+    s_axi_arready,
+    si_rs_awvalid,
+    s_axi_bvalid,
+    si_rs_bready,
+    si_rs_arvalid,
+    s_axi_rvalid,
+    si_rs_rready,
+    D,
+    wrap_second_len,
+    Q,
+    \\s_arid_r_reg[11] ,
+    \\axaddr_incr_reg[11] ,
+    CO,
+    O,
+    \\axaddr_incr_reg[7] ,
+    \\axaddr_incr_reg[11]_0 ,
+    \\axaddr_incr_reg[7]_0 ,
+    \\axaddr_incr_reg[3] ,
+    axaddr_offset,
+    \\axlen_cnt_reg[3] ,
+    next_pending_r_reg,
+    shandshake,
+    \\wrap_cnt_r_reg[2] ,
+    \\wrap_second_len_r_reg[2] ,
+    \\wrap_cnt_r_reg[2]_0 ,
+    \\axaddr_offset_r_reg[3] ,
+    \\axaddr_offset_r_reg[1] ,
+    \\wrap_second_len_r_reg[3] ,
+    next_pending_r_reg_0,
+    \\axlen_cnt_reg[3]_0 ,
+    \\wrap_boundary_axaddr_r_reg[6] ,
+    \\axaddr_offset_r_reg[0] ,
+    \\wrap_boundary_axaddr_r_reg[6]_0 ,
+    \\m_axi_awaddr[10] ,
+    \\m_axi_araddr[10] ,
+    \\s_axi_bid[11] ,
+    \\s_axi_rid[11] ,
+    aclk,
+    m_valid_i0,
+    aresetn,
+    \\cnt_read_reg[3]_rep__2 ,
+    s_axi_rready,
+    S,
+    \\m_payload_i_reg[3] ,
+    \\state_reg[1] ,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\state_reg[1]_0 ,
+    \\axaddr_offset_r_reg[3]_0 ,
+    s_axi_awvalid,
+    b_push,
+    si_rs_bvalid,
+    \\wrap_second_len_r_reg[2]_0 ,
+    \\state_reg[1]_rep ,
+    axaddr_offset_0,
+    \\axaddr_offset_r_reg[3]_1 ,
+    \\state_reg[1]_rep_0 ,
+    \\state_reg[0]_rep ,
+    sel_first,
+    sel_first_1,
+    s_axi_bready,
+    s_axi_arvalid,
+    s_axi_awid,
+    s_axi_awlen,
+    s_axi_awburst,
+    s_axi_awsize,
+    s_axi_awprot,
+    s_axi_awaddr,
+    s_axi_arid,
+    s_axi_arlen,
+    s_axi_arburst,
+    s_axi_arsize,
+    s_axi_arprot,
+    s_axi_araddr,
+    out,
+    \\s_bresp_acc_reg[1] ,
+    r_push_r_reg,
+    \\cnt_read_reg[4] ,
+    axaddr_incr_reg,
+    \\axaddr_incr_reg[3]_0 ,
+    E,
+    \\state_reg[1]_rep_1 );
+  output s_axi_awready;
+  output s_axi_arready;
+  output si_rs_awvalid;
+  output s_axi_bvalid;
+  output si_rs_bready;
+  output si_rs_arvalid;
+  output s_axi_rvalid;
+  output si_rs_rready;
+  output [3:0]D;
+  output [3:0]wrap_second_len;
+  output [53:0]Q;
+  output [53:0]\\s_arid_r_reg[11] ;
+  output [7:0]\\axaddr_incr_reg[11] ;
+  output [0:0]CO;
+  output [3:0]O;
+  output [3:0]\\axaddr_incr_reg[7] ;
+  output [3:0]\\axaddr_incr_reg[11]_0 ;
+  output [0:0]\\axaddr_incr_reg[7]_0 ;
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output [3:0]axaddr_offset;
+  output \\axlen_cnt_reg[3] ;
+  output next_pending_r_reg;
+  output shandshake;
+  output [0:0]\\wrap_cnt_r_reg[2] ;
+  output [1:0]\\wrap_second_len_r_reg[2] ;
+  output \\wrap_cnt_r_reg[2]_0 ;
+  output [2:0]\\axaddr_offset_r_reg[3] ;
+  output \\axaddr_offset_r_reg[1] ;
+  output \\wrap_second_len_r_reg[3] ;
+  output next_pending_r_reg_0;
+  output \\axlen_cnt_reg[3]_0 ;
+  output [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  output \\axaddr_offset_r_reg[0] ;
+  output [6:0]\\wrap_boundary_axaddr_r_reg[6]_0 ;
+  output \\m_axi_awaddr[10] ;
+  output \\m_axi_araddr[10] ;
+  output [13:0]\\s_axi_bid[11] ;
+  output [46:0]\\s_axi_rid[11] ;
+  input aclk;
+  input m_valid_i0;
+  input aresetn;
+  input \\cnt_read_reg[3]_rep__2 ;
+  input s_axi_rready;
+  input [3:0]S;
+  input [3:0]\\m_payload_i_reg[3] ;
+  input \\state_reg[1] ;
+  input [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input [1:0]\\state_reg[1]_0 ;
+  input [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  input s_axi_awvalid;
+  input b_push;
+  input si_rs_bvalid;
+  input [2:0]\\wrap_second_len_r_reg[2]_0 ;
+  input \\state_reg[1]_rep ;
+  input [0:0]axaddr_offset_0;
+  input [2:0]\\axaddr_offset_r_reg[3]_1 ;
+  input \\state_reg[1]_rep_0 ;
+  input \\state_reg[0]_rep ;
+  input sel_first;
+  input sel_first_1;
+  input s_axi_bready;
+  input s_axi_arvalid;
+  input [11:0]s_axi_awid;
+  input [3:0]s_axi_awlen;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awsize;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_awaddr;
+  input [11:0]s_axi_arid;
+  input [3:0]s_axi_arlen;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arsize;
+  input [2:0]s_axi_arprot;
+  input [31:0]s_axi_araddr;
+  input [11:0]out;
+  input [1:0]\\s_bresp_acc_reg[1] ;
+  input [12:0]r_push_r_reg;
+  input [33:0]\\cnt_read_reg[4] ;
+  input [3:0]axaddr_incr_reg;
+  input [3:0]\\axaddr_incr_reg[3]_0 ;
+  input [0:0]E;
+  input [0:0]\\state_reg[1]_rep_1 ;
+
+  wire [0:0]CO;
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [53:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire ar_pipe_n_2;
+  wire aresetn;
+  wire aw_pipe_n_1;
+  wire aw_pipe_n_92;
+  wire [3:0]axaddr_incr_reg;
+  wire [7:0]\\axaddr_incr_reg[11] ;
+  wire [3:0]\\axaddr_incr_reg[11]_0 ;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_incr_reg[3]_0 ;
+  wire [3:0]\\axaddr_incr_reg[7] ;
+  wire [0:0]\\axaddr_incr_reg[7]_0 ;
+  wire [3:0]axaddr_offset;
+  wire [0:0]axaddr_offset_0;
+  wire \\axaddr_offset_r_reg[0] ;
+  wire \\axaddr_offset_r_reg[1] ;
+  wire [2:0]\\axaddr_offset_r_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire [2:0]\\axaddr_offset_r_reg[3]_1 ;
+  wire \\axlen_cnt_reg[3] ;
+  wire \\axlen_cnt_reg[3]_0 ;
+  wire b_push;
+  wire \\cnt_read_reg[3]_rep__2 ;
+  wire [33:0]\\cnt_read_reg[4] ;
+  wire \\m_axi_araddr[10] ;
+  wire \\m_axi_awaddr[10] ;
+  wire [3:0]\\m_payload_i_reg[3] ;
+  wire m_valid_i0;
+  wire next_pending_r_reg;
+  wire next_pending_r_reg_0;
+  wire [11:0]out;
+  wire [12:0]r_push_r_reg;
+  wire [53:0]\\s_arid_r_reg[11] ;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [2:0]s_axi_arprot;
+  wire s_axi_arready;
+  wire [1:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [2:0]s_axi_awprot;
+  wire s_axi_awready;
+  wire [1:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire [13:0]\\s_axi_bid[11] ;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [46:0]\\s_axi_rid[11] ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [1:0]\\s_bresp_acc_reg[1] ;
+  wire sel_first;
+  wire sel_first_1;
+  wire shandshake;
+  wire si_rs_arvalid;
+  wire si_rs_awvalid;
+  wire si_rs_bready;
+  wire si_rs_bvalid;
+  wire si_rs_rready;
+  wire \\state_reg[0]_rep ;
+  wire \\state_reg[1] ;
+  wire [1:0]\\state_reg[1]_0 ;
+  wire \\state_reg[1]_rep ;
+  wire \\state_reg[1]_rep_0 ;
+  wire [0:0]\\state_reg[1]_rep_1 ;
+  wire [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  wire [6:0]\\wrap_boundary_axaddr_r_reg[6]_0 ;
+  wire [0:0]\\wrap_cnt_r_reg[2] ;
+  wire \\wrap_cnt_r_reg[2]_0 ;
+  wire [3:0]wrap_second_len;
+  wire [1:0]\\wrap_second_len_r_reg[2] ;
+  wire [2:0]\\wrap_second_len_r_reg[2]_0 ;
+  wire \\wrap_second_len_r_reg[3] ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+
+  design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice ar_pipe
+       (.Q(\\s_arid_r_reg[11] ),
+        .aclk(aclk),
+        .\\aresetn_d_reg[0] (aw_pipe_n_1),
+        .\\aresetn_d_reg[0]_0 (aw_pipe_n_92),
+        .\\axaddr_incr_reg[11] (\\axaddr_incr_reg[11]_0 ),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_incr_reg[3]_0 (\\axaddr_incr_reg[3]_0 ),
+        .\\axaddr_incr_reg[7] (\\axaddr_incr_reg[7] ),
+        .\\axaddr_incr_reg[7]_0 (\\axaddr_incr_reg[7]_0 ),
+        .axaddr_offset_0(axaddr_offset_0),
+        .\\axaddr_offset_r_reg[0] (\\axaddr_offset_r_reg[0] ),
+        .\\axaddr_offset_r_reg[1] (\\axaddr_offset_r_reg[1] ),
+        .\\axaddr_offset_r_reg[2] (\\axaddr_offset_r_reg[3] [1]),
+        .\\axaddr_offset_r_reg[3] ({\\axaddr_offset_r_reg[3] [2],\\axaddr_offset_r_reg[3] [0]}),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3]_1 ),
+        .\\axlen_cnt_reg[3] (\\axlen_cnt_reg[3]_0 ),
+        .\\m_axi_araddr[10] (\\m_axi_araddr[10] ),
+        .\\m_payload_i_reg[3]_0 (\\m_payload_i_reg[3] ),
+        .m_valid_i0(m_valid_i0),
+        .m_valid_i_reg_0(ar_pipe_n_2),
+        .next_pending_r_reg(next_pending_r_reg_0),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize(s_axi_arsize),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_ready_i_reg_0(si_rs_arvalid),
+        .sel_first_1(sel_first_1),
+        .\\state_reg[0]_rep (\\state_reg[0]_rep ),
+        .\\state_reg[1]_rep (\\state_reg[1]_rep ),
+        .\\state_reg[1]_rep_0 (\\state_reg[1]_rep_0 ),
+        .\\state_reg[1]_rep_1 (\\state_reg[1]_rep_1 ),
+        .\\wrap_boundary_axaddr_r_reg[6] (\\wrap_boundary_axaddr_r_reg[6] ),
+        .\\wrap_cnt_r_reg[2] (\\wrap_cnt_r_reg[2] ),
+        .\\wrap_cnt_r_reg[2]_0 (\\wrap_cnt_r_reg[2]_0 ),
+        .\\wrap_second_len_r_reg[2] (\\wrap_second_len_r_reg[2] ),
+        .\\wrap_second_len_r_reg[2]_0 (\\wrap_second_len_r_reg[2]_0 ),
+        .\\wrap_second_len_r_reg[3] (\\wrap_second_len_r_reg[3] ));
+  design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0 aw_pipe
+       (.CO(CO),
+        .D(D),
+        .E(E),
+        .O(O),
+        .Q(Q),
+        .S(S),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .\\aresetn_d_reg[1]_inv (aw_pipe_n_92),
+        .\\aresetn_d_reg[1]_inv_0 (ar_pipe_n_2),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[11] (\\axaddr_incr_reg[11] ),
+        .axaddr_offset({axaddr_offset[2],axaddr_offset[0]}),
+        .\\axaddr_offset_r_reg[1] (axaddr_offset[1]),
+        .\\axaddr_offset_r_reg[3] (axaddr_offset[3]),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3]_0 ),
+        .\\axlen_cnt_reg[3] (\\axlen_cnt_reg[3] ),
+        .b_push(b_push),
+        .\\m_axi_awaddr[10] (\\m_axi_awaddr[10] ),
+        .m_valid_i_reg_0(si_rs_awvalid),
+        .next_pending_r_reg(next_pending_r_reg),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize(s_axi_awsize),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_ready_i_reg_0(aw_pipe_n_1),
+        .sel_first(sel_first),
+        .\\state_reg[1] (\\state_reg[1] ),
+        .\\state_reg[1]_0 (\\state_reg[1]_0 ),
+        .\\wrap_boundary_axaddr_r_reg[6] (\\wrap_boundary_axaddr_r_reg[6]_0 ),
+        .wrap_second_len({wrap_second_len[3:2],wrap_second_len[0]}),
+        .\\wrap_second_len_r_reg[1] (wrap_second_len[1]),
+        .\\wrap_second_len_r_reg[3] (\\wrap_second_len_r_reg[3]_0 ));
+  design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1 b_pipe
+       (.aclk(aclk),
+        .\\aresetn_d_reg[0] (aw_pipe_n_1),
+        .\\aresetn_d_reg[1]_inv (ar_pipe_n_2),
+        .out(out),
+        .\\s_axi_bid[11] (\\s_axi_bid[11] ),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_bresp_acc_reg[1] (\\s_bresp_acc_reg[1] ),
+        .shandshake(shandshake),
+        .si_rs_bvalid(si_rs_bvalid),
+        .\\skid_buffer_reg[0]_0 (si_rs_bready));
+  design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2 r_pipe
+       (.aclk(aclk),
+        .\\aresetn_d_reg[0] (aw_pipe_n_1),
+        .\\aresetn_d_reg[1]_inv (ar_pipe_n_2),
+        .\\cnt_read_reg[3]_rep__2 (\\cnt_read_reg[3]_rep__2 ),
+        .\\cnt_read_reg[4] (\\cnt_read_reg[4] ),
+        .r_push_r_reg(r_push_r_reg),
+        .\\s_axi_rid[11] (\\s_axi_rid[11] ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .\\skid_buffer_reg[0]_0 (si_rs_rready));
+endmodule
+
+module design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice
+   (s_axi_arready,
+    s_ready_i_reg_0,
+    m_valid_i_reg_0,
+    Q,
+    \\axaddr_incr_reg[7] ,
+    \\axaddr_incr_reg[11] ,
+    \\axaddr_incr_reg[7]_0 ,
+    \\axaddr_incr_reg[3] ,
+    \\wrap_cnt_r_reg[2] ,
+    \\wrap_second_len_r_reg[2] ,
+    \\wrap_cnt_r_reg[2]_0 ,
+    \\axaddr_offset_r_reg[2] ,
+    \\axaddr_offset_r_reg[3] ,
+    \\axaddr_offset_r_reg[1] ,
+    \\wrap_second_len_r_reg[3] ,
+    next_pending_r_reg,
+    \\axlen_cnt_reg[3] ,
+    \\wrap_boundary_axaddr_r_reg[6] ,
+    \\axaddr_offset_r_reg[0] ,
+    \\m_axi_araddr[10] ,
+    \\aresetn_d_reg[0] ,
+    aclk,
+    m_valid_i0,
+    \\aresetn_d_reg[0]_0 ,
+    \\m_payload_i_reg[3]_0 ,
+    \\wrap_second_len_r_reg[2]_0 ,
+    \\state_reg[1]_rep ,
+    axaddr_offset_0,
+    \\axaddr_offset_r_reg[3]_0 ,
+    \\state_reg[1]_rep_0 ,
+    \\state_reg[0]_rep ,
+    sel_first_1,
+    s_axi_arvalid,
+    s_axi_arid,
+    s_axi_arlen,
+    s_axi_arburst,
+    s_axi_arsize,
+    s_axi_arprot,
+    s_axi_araddr,
+    \\axaddr_incr_reg[3]_0 ,
+    \\state_reg[1]_rep_1 );
+  output s_axi_arready;
+  output s_ready_i_reg_0;
+  output m_valid_i_reg_0;
+  output [53:0]Q;
+  output [3:0]\\axaddr_incr_reg[7] ;
+  output [3:0]\\axaddr_incr_reg[11] ;
+  output [0:0]\\axaddr_incr_reg[7]_0 ;
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output [0:0]\\wrap_cnt_r_reg[2] ;
+  output [1:0]\\wrap_second_len_r_reg[2] ;
+  output \\wrap_cnt_r_reg[2]_0 ;
+  output \\axaddr_offset_r_reg[2] ;
+  output [1:0]\\axaddr_offset_r_reg[3] ;
+  output \\axaddr_offset_r_reg[1] ;
+  output \\wrap_second_len_r_reg[3] ;
+  output next_pending_r_reg;
+  output \\axlen_cnt_reg[3] ;
+  output [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  output \\axaddr_offset_r_reg[0] ;
+  output \\m_axi_araddr[10] ;
+  input \\aresetn_d_reg[0] ;
+  input aclk;
+  input m_valid_i0;
+  input \\aresetn_d_reg[0]_0 ;
+  input [3:0]\\m_payload_i_reg[3]_0 ;
+  input [2:0]\\wrap_second_len_r_reg[2]_0 ;
+  input \\state_reg[1]_rep ;
+  input [0:0]axaddr_offset_0;
+  input [2:0]\\axaddr_offset_r_reg[3]_0 ;
+  input \\state_reg[1]_rep_0 ;
+  input \\state_reg[0]_rep ;
+  input sel_first_1;
+  input s_axi_arvalid;
+  input [11:0]s_axi_arid;
+  input [3:0]s_axi_arlen;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arsize;
+  input [2:0]s_axi_arprot;
+  input [31:0]s_axi_araddr;
+  input [3:0]\\axaddr_incr_reg[3]_0 ;
+  input [0:0]\\state_reg[1]_rep_1 ;
+
+  wire [53:0]Q;
+  wire aclk;
+  wire \\aresetn_d_reg[0] ;
+  wire \\aresetn_d_reg[0]_0 ;
+  wire \\axaddr_incr[0]_i_10__0_n_0 ;
+  wire \\axaddr_incr[0]_i_12__0_n_0 ;
+  wire \\axaddr_incr[0]_i_13__0_n_0 ;
+  wire \\axaddr_incr[0]_i_14__0_n_0 ;
+  wire \\axaddr_incr[0]_i_3__0_n_0 ;
+  wire \\axaddr_incr[0]_i_4__0_n_0 ;
+  wire \\axaddr_incr[0]_i_5__0_n_0 ;
+  wire \\axaddr_incr[0]_i_6__0_n_0 ;
+  wire \\axaddr_incr[0]_i_7__0_n_0 ;
+  wire \\axaddr_incr[0]_i_8__0_n_0 ;
+  wire \\axaddr_incr[0]_i_9__0_n_0 ;
+  wire \\axaddr_incr[4]_i_10__0_n_0 ;
+  wire \\axaddr_incr[4]_i_7__0_n_0 ;
+  wire \\axaddr_incr[4]_i_8__0_n_0 ;
+  wire \\axaddr_incr[4]_i_9__0_n_0 ;
+  wire \\axaddr_incr[8]_i_10__0_n_0 ;
+  wire \\axaddr_incr[8]_i_7__0_n_0 ;
+  wire \\axaddr_incr[8]_i_8__0_n_0 ;
+  wire \\axaddr_incr[8]_i_9__0_n_0 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_0 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_1 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_2 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_3 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_4 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_5 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_6 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_7 ;
+  wire \\axaddr_incr_reg[0]_i_2__0_n_1 ;
+  wire \\axaddr_incr_reg[0]_i_2__0_n_2 ;
+  wire \\axaddr_incr_reg[0]_i_2__0_n_3 ;
+  wire [3:0]\\axaddr_incr_reg[11] ;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_incr_reg[3]_0 ;
+  wire \\axaddr_incr_reg[4]_i_6__0_n_0 ;
+  wire \\axaddr_incr_reg[4]_i_6__0_n_1 ;
+  wire \\axaddr_incr_reg[4]_i_6__0_n_2 ;
+  wire \\axaddr_incr_reg[4]_i_6__0_n_3 ;
+  wire [3:0]\\axaddr_incr_reg[7] ;
+  wire [0:0]\\axaddr_incr_reg[7]_0 ;
+  wire \\axaddr_incr_reg[8]_i_6__0_n_1 ;
+  wire \\axaddr_incr_reg[8]_i_6__0_n_2 ;
+  wire \\axaddr_incr_reg[8]_i_6__0_n_3 ;
+  wire [0:0]axaddr_offset_0;
+  wire \\axaddr_offset_r[1]_i_3_n_0 ;
+  wire \\axaddr_offset_r[2]_i_2__0_n_0 ;
+  wire \\axaddr_offset_r[2]_i_3__0_n_0 ;
+  wire \\axaddr_offset_r[3]_i_2__0_n_0 ;
+  wire \\axaddr_offset_r_reg[0] ;
+  wire \\axaddr_offset_r_reg[1] ;
+  wire \\axaddr_offset_r_reg[2] ;
+  wire [1:0]\\axaddr_offset_r_reg[3] ;
+  wire [2:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire \\axlen_cnt_reg[3] ;
+  wire \\m_axi_araddr[10] ;
+  wire \\m_payload_i[0]_i_1__0_n_0 ;
+  wire \\m_payload_i[10]_i_1__0_n_0 ;
+  wire \\m_payload_i[11]_i_1__0_n_0 ;
+  wire \\m_payload_i[12]_i_1__0_n_0 ;
+  wire \\m_payload_i[13]_i_1__1_n_0 ;
+  wire \\m_payload_i[14]_i_1__0_n_0 ;
+  wire \\m_payload_i[15]_i_1__0_n_0 ;
+  wire \\m_payload_i[16]_i_1__0_n_0 ;
+  wire \\m_payload_i[17]_i_1__0_n_0 ;
+  wire \\m_payload_i[18]_i_1__0_n_0 ;
+  wire \\m_payload_i[19]_i_1__0_n_0 ;
+  wire \\m_payload_i[1]_i_1__0_n_0 ;
+  wire \\m_payload_i[20]_i_1__0_n_0 ;
+  wire \\m_payload_i[21]_i_1__0_n_0 ;
+  wire \\m_payload_i[22]_i_1__0_n_0 ;
+  wire \\m_payload_i[23]_i_1__0_n_0 ;
+  wire \\m_payload_i[24]_i_1__0_n_0 ;
+  wire \\m_payload_i[25]_i_1__0_n_0 ;
+  wire \\m_payload_i[26]_i_1__0_n_0 ;
+  wire \\m_payload_i[27]_i_1__0_n_0 ;
+  wire \\m_payload_i[28]_i_1__0_n_0 ;
+  wire \\m_payload_i[29]_i_1__0_n_0 ;
+  wire \\m_payload_i[2]_i_1__0_n_0 ;
+  wire \\m_payload_i[30]_i_1__0_n_0 ;
+  wire \\m_payload_i[31]_i_2__0_n_0 ;
+  wire \\m_payload_i[32]_i_1__0_n_0 ;
+  wire \\m_payload_i[33]_i_1__0_n_0 ;
+  wire \\m_payload_i[34]_i_1__0_n_0 ;
+  wire \\m_payload_i[35]_i_1__0_n_0 ;
+  wire \\m_payload_i[36]_i_1__0_n_0 ;
+  wire \\m_payload_i[38]_i_1__0_n_0 ;
+  wire \\m_payload_i[39]_i_1__0_n_0 ;
+  wire \\m_payload_i[3]_i_1__0_n_0 ;
+  wire \\m_payload_i[44]_i_1__0_n_0 ;
+  wire \\m_payload_i[45]_i_1__0_n_0 ;
+  wire \\m_payload_i[46]_i_1__1_n_0 ;
+  wire \\m_payload_i[47]_i_1__0_n_0 ;
+  wire \\m_payload_i[4]_i_1__0_n_0 ;
+  wire \\m_payload_i[50]_i_1__0_n_0 ;
+  wire \\m_payload_i[51]_i_1__0_n_0 ;
+  wire \\m_payload_i[52]_i_1__0_n_0 ;
+  wire \\m_payload_i[53]_i_1__0_n_0 ;
+  wire \\m_payload_i[54]_i_1__0_n_0 ;
+  wire \\m_payload_i[55]_i_1__0_n_0 ;
+  wire \\m_payload_i[56]_i_1__0_n_0 ;
+  wire \\m_payload_i[57]_i_1__0_n_0 ;
+  wire \\m_payload_i[58]_i_1__0_n_0 ;
+  wire \\m_payload_i[59]_i_1__0_n_0 ;
+  wire \\m_payload_i[5]_i_1__0_n_0 ;
+  wire \\m_payload_i[60]_i_1__0_n_0 ;
+  wire \\m_payload_i[61]_i_1__0_n_0 ;
+  wire \\m_payload_i[6]_i_1__0_n_0 ;
+  wire \\m_payload_i[7]_i_1__0_n_0 ;
+  wire \\m_payload_i[8]_i_1__0_n_0 ;
+  wire \\m_payload_i[9]_i_1__0_n_0 ;
+  wire [3:0]\\m_payload_i_reg[3]_0 ;
+  wire \\m_payload_i_reg_n_0_[38] ;
+  wire m_valid_i0;
+  wire m_valid_i_reg_0;
+  wire next_pending_r_reg;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [2:0]s_axi_arprot;
+  wire s_axi_arready;
+  wire [1:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire s_ready_i0;
+  wire s_ready_i_reg_0;
+  wire sel_first_1;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[35] ;
+  wire \\skid_buffer_reg_n_0_[36] ;
+  wire \\skid_buffer_reg_n_0_[38] ;
+  wire \\skid_buffer_reg_n_0_[39] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[44] ;
+  wire \\skid_buffer_reg_n_0_[45] ;
+  wire \\skid_buffer_reg_n_0_[46] ;
+  wire \\skid_buffer_reg_n_0_[47] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[50] ;
+  wire \\skid_buffer_reg_n_0_[51] ;
+  wire \\skid_buffer_reg_n_0_[52] ;
+  wire \\skid_buffer_reg_n_0_[53] ;
+  wire \\skid_buffer_reg_n_0_[5'b'4] ;
+  wire \\skid_buffer_reg_n_0_[55] ;
+  wire \\skid_buffer_reg_n_0_[56] ;
+  wire \\skid_buffer_reg_n_0_[57] ;
+  wire \\skid_buffer_reg_n_0_[58] ;
+  wire \\skid_buffer_reg_n_0_[59] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[60] ;
+  wire \\skid_buffer_reg_n_0_[61] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire \\state_reg[0]_rep ;
+  wire \\state_reg[1]_rep ;
+  wire \\state_reg[1]_rep_0 ;
+  wire [0:0]\\state_reg[1]_rep_1 ;
+  wire \\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
+  wire [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  wire [0:0]\\wrap_cnt_r_reg[2] ;
+  wire \\wrap_cnt_r_reg[2]_0 ;
+  wire [1:0]\\wrap_second_len_r_reg[2] ;
+  wire [2:0]\\wrap_second_len_r_reg[2]_0 ;
+  wire \\wrap_second_len_r_reg[3] ;
+  wire [3:3]\\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED ;
+
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\aresetn_d_reg[1]_inv 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\aresetn_d_reg[0]_0 ),
+        .Q(m_valid_i_reg_0),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hFFE100E1)) 
+    \\axaddr_incr[0]_i_10__0 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(\\axaddr_incr_reg[3]_0 [0]),
+        .I3(sel_first_1),
+        .I4(\\axaddr_incr_reg[0]_i_11__0_n_7 ),
+        .O(\\axaddr_incr[0]_i_10__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h2A)) 
+    \\axaddr_incr[0]_i_12__0 
+       (.I0(Q[2]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .O(\\axaddr_incr[0]_i_12__0_n_0 ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\axaddr_incr[0]_i_13__0 
+       (.I0(Q[1]),
+        .I1(Q[36]),
+        .O(\\axaddr_incr[0]_i_13__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h02)) 
+    \\axaddr_incr[0]_i_14__0 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .O(\\axaddr_incr[0]_i_14__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\axaddr_incr[0]_i_3__0 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first_1),
+        .O(\\axaddr_incr[0]_i_3__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\axaddr_incr[0]_i_4__0 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(sel_first_1),
+        .O(\\axaddr_incr[0]_i_4__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\axaddr_incr[0]_i_5__0 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first_1),
+        .O(\\axaddr_incr[0]_i_5__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h01)) 
+    \\axaddr_incr[0]_i_6__0 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first_1),
+        .O(\\axaddr_incr[0]_i_6__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFF780078)) 
+    \\axaddr_incr[0]_i_7__0 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(\\axaddr_incr_reg[3]_0 [3]),
+        .I3(sel_first_1),
+        .I4(\\axaddr_incr_reg[0]_i_11__0_n_4 ),
+        .O(\\axaddr_incr[0]_i_7__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFD200D2)) 
+    \\axaddr_incr[0]_i_8__0 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(\\axaddr_incr_reg[3]_0 [2]),
+        .I3(sel_first_1),
+        .I4(\\axaddr_incr_reg[0]_i_11__0_n_5 ),
+        .O(\\axaddr_incr[0]_i_8__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFD200D2)) 
+    \\axaddr_incr[0]_i_9__0 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(\\axaddr_incr_reg[3]_0 [1]),
+        .I3(sel_first_1),
+        .I4(\\axaddr_incr_reg[0]_i_11__0_n_6 ),
+        .O(\\axaddr_incr[0]_i_9__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_10__0 
+       (.I0(Q[4]),
+        .O(\\axaddr_incr[4]_i_10__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_7__0 
+       (.I0(Q[7]),
+        .O(\\axaddr_incr[4]_i_7__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_8__0 
+       (.I0(Q[6]),
+        .O(\\axaddr_incr[4]_i_8__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_9__0 
+       (.I0(Q[5]),
+        .O(\\axaddr_incr[4]_i_9__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_10__0 
+       (.I0(Q[8]),
+        .O(\\axaddr_incr[8]_i_10__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_7__0 
+       (.I0(Q[11]),
+        .O(\\axaddr_incr[8]_i_7__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_8__0 
+       (.I0(Q[10]),
+        .O(\\axaddr_incr[8]_i_8__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_9__0 
+       (.I0(Q[9]),
+        .O(\\axaddr_incr[8]_i_9__0_n_0 ));
+  CARRY4 \\axaddr_incr_reg[0]_i_11__0 
+       (.CI(1\'b0),
+        .CO({\\axaddr_incr_reg[0]_i_11__0_n_0 ,\\axaddr_incr_reg[0]_i_11__0_n_1 ,\\axaddr_incr_reg[0]_i_11__0_n_2 ,\\axaddr_incr_reg[0]_i_11__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({Q[3],\\axaddr_incr[0]_i_12__0_n_0 ,\\axaddr_incr[0]_i_13__0_n_0 ,\\axaddr_incr[0]_i_14__0_n_0 }),
+        .O({\\axaddr_incr_reg[0]_i_11__0_n_4 ,\\axaddr_incr_reg[0]_i_11__0_n_5 ,\\axaddr_incr_reg[0]_i_11__0_n_6 ,\\axaddr_incr_reg[0]_i_11__0_n_7 }),
+        .S(\\m_payload_i_reg[3]_0 ));
+  CARRY4 \\axaddr_incr_reg[0]_i_2__0 
+       (.CI(1\'b0),
+        .CO({\\axaddr_incr_reg[7]_0 ,\\axaddr_incr_reg[0]_i_2__0_n_1 ,\\axaddr_incr_reg[0]_i_2__0_n_2 ,\\axaddr_incr_reg[0]_i_2__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({\\axaddr_incr[0]_i_3__0_n_0 ,\\axaddr_incr[0]_i_4__0_n_0 ,\\axaddr_incr[0]_i_5__0_n_0 ,\\axaddr_incr[0]_i_6__0_n_0 }),
+        .O(\\axaddr_incr_reg[3] ),
+        .S({\\axaddr_incr[0]_i_7__0_n_0 ,\\axaddr_incr[0]_i_8__0_n_0 ,\\axaddr_incr[0]_i_9__0_n_0 ,\\axaddr_incr[0]_i_10__0_n_0 }));
+  CARRY4 \\axaddr_incr_reg[4]_i_6__0 
+       (.CI(\\axaddr_incr_reg[0]_i_11__0_n_0 ),
+        .CO({\\axaddr_incr_reg[4]_i_6__0_n_0 ,\\axaddr_incr_reg[4]_i_6__0_n_1 ,\\axaddr_incr_reg[4]_i_6__0_n_2 ,\\axaddr_incr_reg[4]_i_6__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(\\axaddr_incr_reg[7] ),
+        .S({\\axaddr_incr[4]_i_7__0_n_0 ,\\axaddr_incr[4]_i_8__0_n_0 ,\\axaddr_incr[4]_i_9__0_n_0 ,\\axaddr_incr[4]_i_10__0_n_0 }));
+  CARRY4 \\axaddr_incr_reg[8]_i_6__0 
+       (.CI(\\axaddr_incr_reg[4]_i_6__0_n_0 ),
+        .CO({\\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED [3],\\axaddr_incr_reg[8]_i_6__0_n_1 ,\\axaddr_incr_reg[8]_i_6__0_n_2 ,\\axaddr_incr_reg[8]_i_6__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(\\axaddr_incr_reg[11] ),
+        .S({\\axaddr_incr[8]_i_7__0_n_0 ,\\axaddr_incr[8]_i_8__0_n_0 ,\\axaddr_incr[8]_i_9__0_n_0 ,\\axaddr_incr[8]_i_10__0_n_0 }));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[0]_i_2__0 
+       (.I0(Q[3]),
+        .I1(Q[1]),
+        .I2(Q[35]),
+        .I3(Q[2]),
+        .I4(Q[36]),
+        .I5(Q[0]),
+        .O(\\axaddr_offset_r_reg[0] ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\axaddr_offset_r[1]_i_1__0 
+       (.I0(\\axaddr_offset_r_reg[1] ),
+        .O(\\axaddr_offset_r_reg[3] [0]));
+  LUT6 #(
+    .INIT(64\'h1FDF00001FDFFFFF)) 
+    \\axaddr_offset_r[1]_i_2 
+       (.I0(\\axaddr_offset_r[1]_i_3_n_0 ),
+        .I1(Q[35]),
+        .I2(Q[39]),
+        .I3(\\axaddr_offset_r[2]_i_3__0_n_0 ),
+        .I4(\\state_reg[1]_rep ),
+        .I5(\\axaddr_offset_r_reg[3]_0 [0]),
+        .O(\\axaddr_offset_r_reg[1] ));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[1]_i_3 
+       (.I0(Q[3]),
+        .I1(Q[36]),
+        .I2(Q[1]),
+        .O(\\axaddr_offset_r[1]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAC00FFFFAC000000)) 
+    \\axaddr_offset_r[2]_i_1__0 
+       (.I0(\\axaddr_offset_r[2]_i_2__0_n_0 ),
+        .I1(\\axaddr_offset_r[2]_i_3__0_n_0 ),
+        .I2(Q[35]),
+        .I3(Q[40]),
+        .I4(\\state_reg[1]_rep ),
+        .I5(\\axaddr_offset_r_reg[3]_0 [1]),
+        .O(\\axaddr_offset_r_reg[2] ));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[2]_i_2__0 
+       (.I0(Q[5]),
+        .I1(Q[36]),
+        .I2(Q[3]),
+        .O(\\axaddr_offset_r[2]_i_2__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[2]_i_3__0 
+       (.I0(Q[4]),
+        .I1(Q[36]),
+        .I2(Q[2]),
+        .O(\\axaddr_offset_r[2]_i_3__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFF8FF00000800)) 
+    \\axaddr_offset_r[3]_i_1__0 
+       (.I0(Q[41]),
+        .I1(\\axaddr_offset_r[3]_i_2__0_n_0 ),
+        .I2(\\state_reg[1]_rep_0 ),
+        .I3(s_ready_i_reg_0),
+        .I4(\\state_reg[0]_rep ),
+        .I5(\\axaddr_offset_r_reg[3]_0 [2]),
+        .O(\\axaddr_offset_r_reg[3] [1]));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[3]_i_2__0 
+       (.I0(Q[6]),
+        .I1(Q[4]),
+        .I2(Q[35]),
+        .I3(Q[5]),
+        .I4(Q[36]),
+        .I5(Q[3]),
+        .O(\\axaddr_offset_r[3]_i_2__0_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\axlen_cnt[3]_i_4 
+       (.I0(Q[41]),
+        .I1(\\state_reg[0]_rep ),
+        .I2(s_ready_i_reg_0),
+        .I3(\\state_reg[1]_rep_0 ),
+        .O(\\axlen_cnt_reg[3] ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\m_axi_araddr[11]_INST_0_i_1 
+       (.I0(\\m_payload_i_reg_n_0_[38] ),
+        .I1(sel_first_1),
+        .O(\\m_axi_araddr[10] ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[0]_i_1__0 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[0] ),
+        .O(\\m_payload_i[0]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair36"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1__0 
+       (.I0(s_axi_araddr[10]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(\\m_payload_i[10]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair35"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1__0 
+       (.I0(s_axi_araddr[11]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(\\m_payload_i[11]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair33"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1__0 
+       (.I0(s_axi_araddr[12]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(\\m_payload_i[12]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair35"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1__1 
+       (.I0(s_axi_araddr[13]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(\\m_payload_i[13]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair34"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1__0 
+       (.I0(s_axi_araddr[14]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(\\m_payload_i[14]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair34"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1__0 
+       (.I0(s_axi_araddr[15]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(\\m_payload_i[15]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair33"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1__0 
+       (.I0(s_axi_araddr[16]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(\\m_payload_i[16]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair32"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1__0 
+       (.I0(s_axi_araddr[17]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(\\m_payload_i[17]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1__0 
+       (.I0(s_axi_araddr[18]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(\\m_payload_i[18]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair32"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1__0 
+       (.I0(s_axi_araddr[19]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(\\m_payload_i[19]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair40"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[1]_i_1__0 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[1] ),
+        .O(\\m_payload_i[1]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair31"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1__0 
+       (.I0(s_axi_araddr[20]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(\\m_payload_i[20]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair31"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1__0 
+       (.I0(s_axi_araddr[21]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(\\m_payload_i[21]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1__0 
+       (.I0(s_axi_araddr[22]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(\\m_payload_i[22]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1__0 
+       (.I0(s_axi_araddr[23]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(\\m_payload_i[23]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1__0 
+       (.I0(s_axi_araddr[24]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(\\m_payload_i[24]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1__0 
+       (.I0(s_axi_araddr[25]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(\\m_payload_i[25]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1__0 
+       (.I0(s_axi_araddr[26]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(\\m_payload_i[26]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1__0 
+       (.I0(s_axi_araddr[27]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(\\m_payload_i[27]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1__0 
+       (.I0(s_axi_araddr[28]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(\\m_payload_i[28]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1__0 
+       (.I0(s_axi_araddr[29]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(\\m_payload_i[29]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair40"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[2]_i_1__0 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[2] ),
+        .O(\\m_payload_i[2]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1__0 
+       (.I0(s_axi_araddr[30]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(\\m_payload_i[30]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_2__0 
+       (.I0(s_axi_araddr[31]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(\\m_payload_i[31]_i_2__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1__0 
+       (.I0(s_axi_arprot[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(\\m_payload_i[32]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1__0 
+       (.I0(s_axi_arprot[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(\\m_payload_i[33]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_1__0 
+       (.I0(s_axi_arprot[2]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(\\m_payload_i[34]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[35]_i_1__0 
+       (.I0(s_axi_arsize[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[35] ),
+        .O(\\m_payload_i[35]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[36]_i_1__0 
+       (.I0(s_axi_arsize[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[36] ),
+        .O(\\m_payload_i[36]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[38]_i_1__0 
+       (.I0(s_axi_arburst[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[38] ),
+        .O(\\m_payload_i[38]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[39]_i_1__0 
+       (.I0(s_axi_arburst[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[39] ),
+        .O(\\m_payload_i[39]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair39"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1__0 
+       (.I0(s_axi_araddr[3]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(\\m_payload_i[3]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[44]_i_1__0 
+       (.I0(s_axi_arlen[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[44] ),
+        .O(\\m_payload_i[44]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[45]_i_1__0 
+       (.I0(s_axi_arlen[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[45] ),
+        .O(\\m_payload_i[45]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[46]_i_1__1 
+       (.I0(s_axi_arlen[2]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[46] ),
+        .O(\\m_payload_i[46]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[47]_i_1__0 
+       (.I0(s_axi_arlen[3]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[47] ),
+        .O(\\m_payload_i[47]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair39"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1__0 
+       (.I0(s_axi_araddr[4]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(\\m_payload_i[4]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[50]_i_1__0 
+       (.I0(s_axi_arid[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[50] ),
+        .O(\\m_payload_i[50]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[51]_i_1__0 
+       (.I0(s_axi_arid[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[51] ),
+        .O(\\m_payload_i[51]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[52]_i_1__0 
+       (.I0(s_axi_arid[2]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[52] ),
+        .O(\\m_payload_i[52]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[53]_i_1__0 
+       (.I0(s_axi_arid[3]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[53] ),
+        .O(\\m_payload_i[53]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[54]_i_1__0 
+       (.I0(s_axi_arid[4]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[54] ),
+        .O(\\m_payload_i[54]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[55]_i_1__0 
+       (.I0(s_axi_arid[5]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[55] ),
+        .O(\\m_payload_i[55]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[56]_i_1__0 
+       (.I0(s_axi_arid[6]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[56] ),
+        .O(\\m_payload_i[56]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[57]_i_1__0 
+       (.I0(s_axi_arid[7]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[57] ),
+        .O(\\m_payload_i[57]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[58]_i_1__0 
+       (.I0(s_axi_arid[8]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[58] ),
+        .O(\\m_payload_i[58]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[59]_i_1__0 
+       (.I0(s_axi_arid[9]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[59] ),
+        .O(\\m_payload_i[59]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair38"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1__0 
+       (.I0(s_axi_araddr[5]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(\\m_payload_i[5]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[60]_i_1__0 
+       (.I0(s_axi_arid[10]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[60] ),
+        .O(\\m_payload_i[60]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[61]_i_1__0 
+       (.I0(s_axi_arid[11]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[61] ),
+        .O(\\m_payload_i[61]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair38"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1__0 
+       (.I0(s_axi_araddr[6]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(\\m_payload_i[6]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair37"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1__0 
+       (.I0(s_axi_araddr[7]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(\\m_payload_i[7]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair36"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1__0 
+       (.I0(s_axi_araddr[8]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(\\m_payload_i[8]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair37"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1__0 
+       (.I0(s_axi_araddr[9]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(\\m_payload_i[9]_i_1__0_n_0 ));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[0]_i_1__0_n_0 ),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[10]_i_1__0_n_0 ),
+        .Q(Q[10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[11]_i_1__0_n_0 ),
+        .Q(Q[11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[12]_i_1__0_n_0 ),
+        .Q(Q[12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[13]_i_1__1_n_0 ),
+        .Q(Q[13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[14]_i_1__0_n_0 ),
+        .Q(Q[14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[15]_i_1__0_n_0 ),
+        .Q(Q[15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[16]_i_1__0_n_0 ),
+        .Q(Q[16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[17]_i_1__0_n_0 ),
+        .Q(Q[17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[18]_i_1__0_n_0 ),
+        .Q(Q[18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[19]_i_1__0_n_0 ),
+        .Q(Q[19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[1]_i_1__0_n_0 ),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[20]_i_1__0_n_0 ),
+        .Q(Q[20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[21]_i_1__0_n_0 ),
+        .Q(Q[21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[22]_i_1__0_n_0 ),
+        .Q(Q[22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[23]_i_1__0_n_0 ),
+        .Q(Q[23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[24]_i_1__0_n_0 ),
+        .Q(Q[24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[25]_i_1__0_n_0 ),
+        .Q(Q[25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[26]_i_1__0_n_0 ),
+        .Q(Q[26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[27]_i_1__0_n_0 ),
+        .Q(Q[27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[28]_i_1__0_n_0 ),
+        .Q(Q[28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[29]_i_1__0_n_0 ),
+        .Q(Q[29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[2]_i_1__0_n_0 ),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[30]_i_1__0_n_0 ),
+        .Q(Q[30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[31]_i_2__0_n_0 ),
+        .Q(Q[31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[32]_i_1__0_n_0 ),
+        .Q(Q[32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[33]_i_1__0_n_0 ),
+        .Q(Q[33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[34]_i_1__0_n_0 ),
+        .Q(Q[34]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[35] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[35]_i_1__0_n_0 ),
+        .Q(Q[35]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[36] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[36]_i_1__0_n_0 ),
+        .Q(Q[36]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[38] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[38]_i_1__0_n_0 ),
+        .Q(\\m_payload_i_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[39] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[39]_i_1__0_n_0 ),
+        .Q(Q[37]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[3]_i_1__0_n_0 ),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[44] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[44]_i_1__0_n_0 ),
+        .Q(Q[38]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[45] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[45]_i_1__0_n_0 ),
+        .Q(Q[39]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[46] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[46]_i_1__1_n_0 ),
+        .Q(Q[40]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[47] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[47]_i_1__0_n_0 ),
+        .Q(Q[41]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[4]_i_1__0_n_0 ),
+        .Q(Q[4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[50] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[50]_i_1__0_n_0 ),
+        .Q(Q[42]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[51] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[51]_i_1__0_n_0 ),
+        .Q(Q[43]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[52] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[52]_i_1__0_n_0 ),
+        .Q(Q[44]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[53] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[53]_i_1__0_n_0 ),
+        .Q(Q[45]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[54] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[54]_i_1__0_n_0 ),
+        .Q(Q[46]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[55] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[55]_i_1__0_n_0 ),
+        .Q(Q[47]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[56] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[56]_i_1__0_n_0 ),
+        .Q(Q[48]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[57] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[57]_i_1__0_n_0 ),
+        .Q(Q[49]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[58] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[58]_i_1__0_n_0 ),
+        .Q(Q[50]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[59] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[59]_i_1__0_n_0 ),
+        .Q(Q[51]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[5]_i_1__0_n_0 ),
+        .Q(Q[5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[60] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[60]_i_1__0_n_0 ),
+        .Q(Q[52]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[61] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[61]_i_1__0_n_0 ),
+        .Q(Q[53]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[6]_i_1__0_n_0 ),
+        .Q(Q[6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[7]_i_1__0_n_0 ),
+        .Q(Q[7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[8]_i_1__0_n_0 ),
+        .Q(Q[8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[9]_i_1__0_n_0 ),
+        .Q(Q[9]),
+        .R(1\'b0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i0),
+        .Q(s_ready_i_reg_0),
+        .R(m_valid_i_reg_0));
+  LUT5 #(
+    .INIT(32\'hAAAAAAA8)) 
+    next_pending_r_i_3__0
+       (.I0(\\state_reg[1]_rep ),
+        .I1(Q[38]),
+        .I2(Q[41]),
+        .I3(Q[39]),
+        .I4(Q[40]),
+        .O(next_pending_r_reg));
+  LUT5 #(
+    .INIT(32\'hF444FFFF)) 
+    s_ready_i_i_1__0
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_arready),
+        .I2(\\state_reg[1]_rep_0 ),
+        .I3(\\state_reg[0]_rep ),
+        .I4(s_ready_i_reg_0),
+        .O(s_ready_i0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i0),
+        .Q(s_axi_arready),
+        .R(\\aresetn_d_reg[0] ));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[10]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[11]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[12]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[13]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[14]),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[15]),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[16]),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[17]),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[18]),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[19]),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[20]),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[21]),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[22]),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[23]),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[24]),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[25]),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[26]),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[27]),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[28]),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[29]),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[30]),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[31]),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arprot[0]),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arprot[1]),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arprot[2]),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[35] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arsize[0]),
+        .Q(\\skid_buffer_reg_n_0_[35] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[36] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arsize[1]),
+        .Q(\\skid_buffer_reg_n_0_[36] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[38] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arburst[0]),
+        .Q(\\skid_buffer_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[39] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arburst[1]),
+        .Q(\\skid_buffer_reg_n_0_[39] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[3]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[44] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arlen[0]),
+        .Q(\\skid_buffer_reg_n_0_[44] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[45] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arlen[1]),
+        .Q(\\skid_buffer_reg_n_0_[45] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[46] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arlen[2]),
+        .Q(\\skid_buffer_reg_n_0_[46] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[47] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arlen[3]),
+        .Q(\\skid_buffer_reg_n_0_[47] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[4]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[50] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[0]),
+        .Q(\\skid_buffer_reg_n_0_[50] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[51] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[1]),
+        .Q(\\skid_buffer_reg_n_0_[51] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[52] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[2]),
+        .Q(\\skid_buffer_reg_n_0_[52] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[53] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[3]),
+        .Q(\\skid_buffer_reg_n_0_[53] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[54] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[4]),
+        .Q(\\skid_buffer_reg_n_0_[54] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[55] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[5]),
+        .Q(\\skid_buffer_reg_n_0_[55] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[56] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[6]),
+        .Q(\\skid_buffer_reg_n_0_[56] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[57] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[7]),
+        .Q(\\skid_buffer_reg_n_0_[57] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[58] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[8]),
+        .Q(\\skid_buffer_reg_n_0_[58] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[59] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[9]),
+        .Q(\\skid_buffer_reg_n_0_[59] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[5]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[60] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[10]),
+        .Q(\\skid_buffer_reg_n_0_[60] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[61] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[11]),
+        .Q(\\skid_buffer_reg_n_0_[61] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[6]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[7]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[8]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[9]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hAA8A)) 
+    \\wrap_boundary_axaddr_r[0]_i_1__0 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[38]),
+        .I3(Q[35]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [0]));
+  LUT5 #(
+    .INIT(32\'h8A888AAA)) 
+    \\wrap_boundary_axaddr_r[1]_i_1__0 
+       (.I0(Q[1]),
+        .I1(Q[36]),
+        .I2(Q[38]),
+        .I3(Q[35]),
+        .I4(Q[39]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [1]));
+  LUT6 #(
+    .INIT(64\'h8888082AAAAA082A)) 
+    \\wrap_boundary_axaddr_r[2]_i_1 
+       (.I0(Q[2]),
+        .I1(Q[35]),
+        .I2(Q[39]),
+        .I3(Q[40]),
+        .I4(Q[36]),
+        .I5(Q[38]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [2]));
+  LUT6 #(
+    .INIT(64\'h020202A2A2A202A2)) 
+    \\wrap_boundary_axaddr_r[3]_i_1__0 
+       (.I0(Q[3]),
+        .I1(\\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
+        .I2(Q[36]),
+        .I3(Q[39]),
+        .I4(Q[35]),
+        .I5(Q[38]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [3]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\wrap_boundary_axaddr_r[3]_i_2__0 
+       (.I0(Q[40]),
+        .I1(Q[35]),
+        .I2(Q[41]),
+        .O(\\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'h002AA02A0A2AAA2A)) 
+    \\wrap_boundary_axaddr_r[4]_i_1 
+       (.I0(Q[4]),
+        .I1(Q[41]),
+        .I2(Q[35]),
+        .I3(Q[36]),
+        .I4(Q[39]),
+        .I5(Q[40]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [4]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT5 #(
+    .INIT(32\'h2A222AAA)) 
+    \\wrap_boundary_axaddr_r[5]_i_1__0 
+       (.I0(Q[5]),
+        .I1(Q[36]),
+        .I2(Q[40]),
+        .I3(Q[35]),
+        .I4(Q[41]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [5]));
+  LUT4 #(
+    .INIT(16\'h2AAA)) 
+    \\wrap_boundary_axaddr_r[6]_i_1__0 
+       (.I0(Q[6]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .I3(Q[41]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [6]));
+  LUT6 #(
+    .INIT(64\'hA656AAAAAAAAAAAA)) 
+    \\wrap_cnt_r[2]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[2] [1]),
+        .I1(\\wrap_second_len_r_reg[2]_0 [0]),
+        .I2(\\state_reg[1]_rep ),
+        .I3(axaddr_offset_0),
+        .I4(\\wrap_cnt_r_reg[2]_0 ),
+        .I5(\\wrap_second_len_r_reg[2] [0]),
+        .O(\\wrap_cnt_r_reg[2] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFBAFFFFFFFF)) 
+    \\wrap_second_len_r[0]_i_2__0 
+       (.I0(\\wrap_second_len_r_reg[3] ),
+        .I1(\\state_reg[1]_rep ),
+        .I2(\\axaddr_offset_r_reg[3]_0 [2]),
+        .I3(\\axaddr_offset_r_reg[2] ),
+        .I4(axaddr_offset_0),
+        .I5(\\axaddr_offset_r_reg[1] ),
+        .O(\\wrap_cnt_r_reg[2]_0 ));
+  LUT6 #(
+    .INIT(64\'h0EF0FFFF0EF00000)) 
+    \\wrap_second_len_r[1]_i_1__0 
+       (.I0(\\axaddr_offset_r_reg[2] ),
+        .I1(\\axaddr_offset_r_reg[3] [1]),
+        .I2(axaddr_offset_0),
+        .I3(\\axaddr_offset_r_reg[1] ),
+        .I4(\\state_reg[1]_rep ),
+        .I5(\\wrap_second_len_r_reg[2]_0 [1]),
+        .O(\\wrap_second_len_r_reg[2] [0]));
+  LUT6 #(
+    .INIT(64\'hD2D0FFFFD2D00000)) 
+    \\wrap_second_len_r[2]_i_1__0 
+       (.I0(\\axaddr_offset_r_reg[1] ),
+        .I1(axaddr_offset_0),
+        .I2(\\axaddr_offset_r_reg[2] ),
+        .I3(\\axaddr_offset_r_reg[3] [1]),
+        .I4(\\state_reg[1]_rep ),
+        .I5(\\wrap_second_len_r_reg[2]_0 [2]),
+        .O(\\wrap_second_len_r_reg[2] [1]));
+  LUT6 #(
+    .INIT(64\'h00000000EEE222E2)) 
+    \\wrap_second_len_r[3]_i_2__0 
+       (.I0(\\axaddr_offset_r[2]_i_2__0_n_0 ),
+        .I1(Q[35]),
+        .I2(Q[4]),
+        .I3(Q[36]),
+        .I4(Q[6]),
+        .I5(\\axlen_cnt_reg[3] ),
+        .O(\\wrap_second_len_r_reg[3] ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_register_slice_v2_1_11_axic_register_slice"" *) 
+module design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0
+   (s_axi_awready,
+    s_ready_i_reg_0,
+    m_valid_i_reg_0,
+    D,
+    \\wrap_second_len_r_reg[1] ,
+    Q,
+    \\axaddr_incr_reg[11] ,
+    CO,
+    O,
+    wrap_second_len,
+    \\axaddr_offset_r_reg[1] ,
+    \\axaddr_offset_r_reg[3] ,
+    axaddr_offset,
+    \\axlen_cnt_reg[3] ,
+    next_pending_r_reg,
+    \\wrap_boundary_axaddr_r_reg[6] ,
+    \\m_axi_awaddr[10] ,
+    \\aresetn_d_reg[1]_inv ,
+    aclk,
+    \\aresetn_d_reg[1]_inv_0 ,
+    aresetn,
+    S,
+    \\state_reg[1] ,
+    \\wrap_second_len_r_reg[3] ,
+    \\state_reg[1]_0 ,
+    \\axaddr_offset_r_reg[3]_0 ,
+    s_axi_awvalid,
+    b_push,
+    sel_first,
+    s_axi_awid,
+    s_axi_awlen,
+    s_axi_awburst,
+    s_axi_awsize,
+    s_axi_awprot,
+    s_axi_awaddr,
+    axaddr_incr_reg,
+    E);
+  output s_axi_awready;
+  output s_ready_i_reg_0;
+  output m_valid_i_reg_0;
+  output [3:0]D;
+  output \\wrap_second_len_r_reg[1] ;
+  output [53:0]Q;
+  output [7:0]\\axaddr_incr_reg[11] ;
+  output [0:0]CO;
+  output [3:0]O;
+  output [2:0]wrap_second_len;
+  output \\axaddr_offset_r_reg[1] ;
+  output \\axaddr_offset_r_reg[3] ;
+  output [1:0]axaddr_offset;
+  output \\axlen_cnt_reg[3] ;
+  output next_pending_r_reg;
+  output [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  output \\m_axi_awaddr[10] ;
+  output \\aresetn_d_reg[1]_inv ;
+  input aclk;
+  input \\aresetn_d_reg[1]_inv_0 ;
+  input aresetn;
+  input [3:0]S;
+  input \\state_reg[1] ;
+  input [3:0]\\wrap_second_len_r_reg[3] ;
+  input [1:0]\\state_reg[1]_0 ;
+  input [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  input s_axi_awvalid;
+  input b_push;
+  input sel_first;
+  input [11:0]s_axi_awid;
+  input [3:0]s_axi_awlen;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awsize;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_awaddr;
+  input [3:0]axaddr_incr_reg;
+  input [0:0]E;
+
+  wire [3:0]C;
+  wire [0:0]CO;
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [53:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire aresetn;
+  wire \\aresetn_d_reg[1]_inv ;
+  wire \\aresetn_d_reg[1]_inv_0 ;
+  wire \\aresetn_d_reg_n_0_[0] ;
+  wire \\axaddr_incr[0]_i_10_n_0 ;
+  wire \\axaddr_incr[0]_i_12_n_0 ;
+  wire \\axaddr_incr[0]_i_13_n_0 ;
+  wire \\axaddr_incr[0]_i_14_n_0 ;
+  wire \\axaddr_incr[0]_i_3_n_0 ;
+  wire \\axaddr_incr[0]_i_4_n_0 ;
+  wire \\axaddr_incr[0]_i_5_n_0 ;
+  wire \\axaddr_incr[0]_i_6_n_0 ;
+  wire \\axaddr_incr[0]_i_7_n_0 ;
+  wire \\axaddr_incr[0]_i_8_n_0 ;
+  wire \\axaddr_incr[0]_i_9_n_0 ;
+  wire \\axaddr_incr[4]_i_10_n_0 ;
+  wire \\axaddr_incr[4]_i_7_n_0 ;
+  wire \\axaddr_incr[4]_i_8_n_0 ;
+  wire \\axaddr_incr[4]_i_9_n_0 ;
+  wire \\axaddr_incr[8]_i_10_n_0 ;
+  wire \\axaddr_incr[8]_i_7_n_0 ;
+  wire \\axaddr_incr[8]_i_8_n_0 ;
+  wire \\axaddr_incr[8]_i_9_n_0 ;
+  wire [3:0]axaddr_incr_reg;
+  wire \\axaddr_incr_reg[0]_i_11_n_0 ;
+  wire \\axaddr_incr_reg[0]_i_11_n_1 ;
+  wire \\axaddr_incr_reg[0]_i_11_n_2 ;
+  wire \\axaddr_incr_reg[0]_i_11_n_3 ;
+  wire \\axaddr_incr_reg[0]_i_2_n_1 ;
+  wire \\axaddr_incr_reg[0]_i_2_n_2 ;
+  wire \\axaddr_incr_reg[0]_i_2_n_3 ;
+  wire [7:0]\\axaddr_incr_reg[11] ;
+  wire \\axaddr_incr_reg[4]_i_6_n_0 ;
+  wire \\axaddr_incr_reg[4]_i_6_n_1 ;
+  wire \\axaddr_incr_reg[4]_i_6_n_2 ;
+  wire \\axaddr_incr_reg[4]_i_6_n_3 ;
+  wire \\axaddr_incr_reg[8]_i_6_n_1 ;
+  wire \\axaddr_incr_reg[8]_i_6_n_2 ;
+  wire \\axaddr_incr_reg[8]_i_6_n_3 ;
+  wire [1:0]axaddr_offset;
+  wire \\axaddr_offset_r[0]_i_2_n_0 ;
+  wire \\axaddr_offset_r[0]_i_3_n_0 ;
+  wire \\axaddr_offset_r[1]_i_2__0_n_0 ;
+  wire \\axaddr_offset_r[2]_i_2_n_0 ;
+  wire \\axaddr_offset_r[2]_i_3_n_0 ;
+  wire \\axaddr_offset_r[2]_i_4_n_0 ;
+  wire \\axaddr_offset_r[3]_i_2_n_0 ;
+  wire \\axaddr_offset_r_reg[1] ;
+  wire \\axaddr_offset_r_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire \\axlen_cnt_reg[3] ;
+  wire b_push;
+  wire \\m_axi_awaddr[10] ;
+  wire \\m_payload_i_reg_n_0_[38] ;
+  wire m_valid_i0;
+  wire m_valid_i_reg_0;
+  wire next_pending_r_reg;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [2:0]s_axi_awprot;
+  wire s_axi_awready;
+  wire [1:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire s_ready_i0;
+  wire s_ready_i_reg_0;
+  wire sel_first;
+  wire [61:0]skid_buffer;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[35] ;
+  wire \\skid_buffer_reg_n_0_[36] ;
+  wire \\skid_buffer_reg_n_0_[38] ;
+  wire \\skid_buffer_reg_n_0_[39] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[44] ;
+  wire \\skid_buffer_reg_n_0_[45] ;
+  wire \\skid_buffer_reg_n_0_[46] ;
+  wire \\skid_buffer_reg_n_0_[47] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[50] ;
+  wire \\skid_buffer_reg_n_0_[51] ;
+  wire \\skid_buffer_reg_n_0_[52] ;
+  wire \\skid_buffer_reg_n_0_[53] ;
+  wire \\skid_buffer_reg_n_0_[54] ;
+  wire \\skid_buffer_reg_n_0_[55] ;
+  wire \\skid_buffer_reg_n_0_[56] ;
+  wire \\skid_buffer_reg_n_0_[57] ;
+  wire \\skid_buffer_reg_n_0_[58] ;
+  wire \\skid_buffer_reg_n_0_[59] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[60] ;
+  wire \\skid_buffer_reg_n_0_[61] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire \\state_reg[1] ;
+  wire [1:0]\\state_reg[1]_0 ;
+  wire \\wrap_boundary_axaddr_r[3]_i_2_n_0 ;
+  wire [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  wire \\wrap_cnt_r[3]_i_2_n_0 ;
+  wire \\wrap_cnt_r[3]_i_3_n_0 ;
+  wire [2:0]wrap_second_len;
+  wire \\wrap_second_len_r[0]_i_2_n_0 ;
+  wire \\wrap_second_len_r[0]_i_3_n_0 ;
+  wire \\wrap_second_len_r[0]_i_4_n_0 ;
+  wire \\wrap_second_len_r[0]_i_5_n_0 ;
+  wire \\wrap_second_len_r[3]_i_2_n_0 ;
+  wire \\wrap_second_len_r_reg[1] ;
+  wire [3:0]\\wrap_second_len_r_reg[3] ;
+  wire [3:3]\\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED ;
+
+  LUT2 #(
+    .INIT(4\'h7)) 
+    \\aresetn_d[1]_inv_i_1 
+       (.I0(\\aresetn_d_reg_n_0_[0] ),
+        .I1(aresetn),
+        .O(\\aresetn_d_reg[1]_inv ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(aresetn),
+        .Q(\\aresetn_d_reg_n_0_[0] ),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hFFE100E1)) 
+    \\axaddr_incr[0]_i_10 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(axaddr_incr_reg[0]),
+        .I3(sel_first),
+        .I4(C[0]),
+        .O(\\axaddr_incr[0]_i_10_n_0 ));
+  LUT3 #(
+    .INIT(8\'h2A)) 
+    \\axaddr_incr[0]_i_12 
+       (.I0(Q[2]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .O(\\axaddr_incr[0]_i_12_n_0 ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\axaddr_incr[0]_i_13 
+       (.I0(Q[1]),
+        .I1(Q[36]),
+        .O(\\axaddr_incr[0]_i_13_n_0 ));
+  LUT3 #(
+    .INIT(8\'h02)) 
+    \\axaddr_incr[0]_i_14 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .O(\\axaddr_incr[0]_i_14_n_0 ));
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\axaddr_incr[0]_i_3 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first),
+        .O(\\axaddr_incr[0]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\axaddr_incr[0]_i_4 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(sel_first),
+        .O(\\axaddr_incr[0]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\axaddr_incr[0]_i_5 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first),
+        .O(\\axaddr_incr[0]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8\'h01)) 
+    \\axaddr_incr[0]_i_6 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first),
+        .O(\\axaddr_incr[0]_i_6_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFF780078)) 
+    \\axaddr_incr[0]_i_7 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(axaddr_incr_reg[3]),
+        .I3(sel_first),
+        .I4(C[3]),
+        .O(\\axaddr_incr[0]_i_7_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFD200D2)) 
+    \\axaddr_incr[0]_i_8 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(axaddr_incr_reg[2]),
+        .I3(sel_first),
+        .I4(C[2]),
+        .O(\\axaddr_incr[0]_i_8_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFD200D2)) 
+    \\axaddr_incr[0]_i_9 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(axaddr_incr_reg[1]),
+        .I3(sel_first),
+        .I4(C[1]),
+        .O(\\axaddr_incr[0]_i_9_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_10 
+       (.I0(Q[4]),
+        .O(\\axaddr_incr[4]_i_10_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_7 
+       (.I0(Q[7]),
+        .O(\\axaddr_incr[4]_i_7_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_8 
+       (.I0(Q[6]),
+        .O(\\axaddr_incr[4]_i_8_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_9 
+       (.I0(Q[5]),
+        .O(\\axaddr_incr[4]_i_9_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_10 
+       (.I0(Q[8]),
+        .O(\\axaddr_incr[8]_i_10_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_7 
+       (.I0(Q[11]),
+        .O(\\axaddr_incr[8]_i_7_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_8 
+       (.I0(Q[10]),
+        .O(\\axaddr_incr[8]_i_8_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_9 
+       (.I0(Q[9]),
+        .O(\\axaddr_incr[8]_i_9_n_0 ));
+  CARRY4 \\axaddr_incr_reg[0]_i_11 
+       (.CI(1\'b0),
+        .CO({\\axaddr_incr_reg[0]_i_11_n_0 ,\\axaddr_incr_reg[0]_i_11_n_1 ,\\axaddr_incr_reg[0]_i_11_n_2 ,\\axaddr_incr_reg[0]_i_11_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({Q[3],\\axaddr_incr[0]_i_12_n_0 ,\\axaddr_incr[0]_i_13_n_0 ,\\axaddr_incr[0]_i_14_n_0 }),
+        .O(C),
+        .S(S));
+  CARRY4 \\axaddr_incr_reg[0]_i_2 
+       (.CI(1\'b0),
+        .CO({CO,\\axaddr_incr_reg[0]_i_2_n_1 ,\\axaddr_incr_reg[0]_i_2_n_2 ,\\axaddr_incr_reg[0]_i_2_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({\\axaddr_incr[0]_i_3_n_0 ,\\axaddr_incr[0]_i_4_n_0 ,\\axaddr_incr[0]_i_5_n_0 ,\\axaddr_incr[0]_i_6_n_0 }),
+        .O(O),
+        .S({\\axaddr_incr[0]_i_7_n_0 ,\\axaddr_incr[0]_i_8_n_0 ,\\axaddr_incr[0]_i_9_n_0 ,\\axaddr_incr[0]_i_10_n_0 }));
+  CARRY4 \\axaddr_incr_reg[4]_i_6 
+       (.CI(\\axaddr_incr_reg[0]_i_11_n_0 ),
+        .CO({\\axaddr_incr_reg[4]_i_6_n_0 ,\\axaddr_incr_reg[4]_i_6_n_1 ,\\axaddr_incr_reg[4]_i_6_n_2 ,\\axaddr_incr_reg[4]_i_6_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(\\axaddr_incr_reg[11] [3:0]),
+        .S({\\axaddr_incr[4]_i_7_n_0 ,\\axaddr_incr[4]_i_8_n_0 ,\\axaddr_incr[4]_i_9_n_0 ,\\axaddr_incr[4]_i_10_n_0 }));
+  CARRY4 \\axaddr_incr_reg[8]_i_6 
+       (.CI(\\axaddr_incr_reg[4]_i_6_n_0 ),
+        .CO({\\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED [3],\\axaddr_incr_reg[8]_i_6_n_1 ,\\axaddr_incr_reg[8]_i_6_n_2 ,\\axaddr_incr_reg[8]_i_6_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(\\axaddr_incr_reg[11] [7:4]),
+        .S({\\axaddr_incr[8]_i_7_n_0 ,\\axaddr_incr[8]_i_8_n_0 ,\\axaddr_incr[8]_i_9_n_0 ,\\axaddr_incr[8]_i_10_n_0 }));
+  (* SOFT_HLUTNM = ""soft_lutpair41"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\axaddr_offset_r[0]_i_1 
+       (.I0(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .O(axaddr_offset[0]));
+  LUT6 #(
+    .INIT(64\'h00000700FFFFF7FF)) 
+    \\axaddr_offset_r[0]_i_2 
+       (.I0(Q[38]),
+        .I1(\\axaddr_offset_r[0]_i_3_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\axaddr_offset_r_reg[3]_0 [0]),
+        .O(\\axaddr_offset_r[0]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[0]_i_3 
+       (.I0(Q[3]),
+        .I1(Q[1]),
+        .I2(Q[35]),
+        .I3(Q[2]),
+        .I4(Q[36]),
+        .I5(Q[0]),
+        .O(\\axaddr_offset_r[0]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFF8FF00000800)) 
+    \\axaddr_offset_r[1]_i_1 
+       (.I0(Q[39]),
+        .I1(\\axaddr_offset_r[1]_i_2__0_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\axaddr_offset_r_reg[3]_0 [1]),
+        .O(\\axaddr_offset_r_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[1]_i_2__0 
+       (.I0(Q[4]),
+        .I1(Q[2]),
+        .I2(Q[35]),
+        .I3(Q[3]),
+        .I4(Q[36]),
+        .I5(Q[1]),
+        .O(\\axaddr_offset_r[1]_i_2__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\axaddr_offset_r[2]_i_1 
+       (.I0(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .O(axaddr_offset[1]));
+  LUT6 #(
+    .INIT(64\'h03FFF3FF55555555)) 
+    \\axaddr_offset_r[2]_i_2 
+       (.I0(\\axaddr_offset_r_reg[3]_0 [2]),
+        .I1(\\axaddr_offset_r[2]_i_3_n_0 ),
+        .I2(Q[35]),
+        .I3(Q[40]),
+        .I4(\\axaddr_offset_r[2]_i_4_n_0 ),
+        .I5(\\state_reg[1] ),
+        .O(\\axaddr_offset_r[2]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair45"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[2]_i_3 
+       (.I0(Q[4]),
+        .I1(Q[36]),
+        .I2(Q[2]),
+        .O(\\axaddr_offset_r[2]_i_3_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair45"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[2]_i_4 
+       (.I0(Q[5]),
+        .I1(Q[36]),
+        .I2(Q[3]),
+        .O(\\axaddr_offset_r[2]_i_4_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFF8FF00000800)) 
+    \\axaddr_offset_r[3]_i_1 
+       (.I0(Q[41]),
+        .I1(\\axaddr_offset_r[3]_i_2_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\axaddr_offset_r_reg[3]_0 [3]),
+        .O(\\axaddr_offset_r_reg[3] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[3]_i_2 
+       (.I0(Q[6]),
+        .I1(Q[4]),
+        .I2(Q[35]),
+        .I3(Q[5]),
+        .I4(Q[36]),
+        .I5(Q[3]),
+        .O(\\axaddr_offset_r[3]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair44"" *) 
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\axlen_cnt[3]_i_3 
+       (.I0(Q[41]),
+        .I1(\\state_reg[1]_0 [0]),
+        .I2(m_valid_i_reg_0),
+        .I3(\\state_reg[1]_0 [1]),
+        .O(\\axlen_cnt_reg[3] ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\m_axi_awaddr[11]_INST_0_i_1 
+       (.I0(\\m_payload_i_reg_n_0_[38] ),
+        .I1(sel_first),
+        .O(\\m_axi_awaddr[10] ));
+  (* SOFT_HLUTNM = ""soft_lutpair47"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[0]_i_1 
+       (.I0(s_axi_awaddr[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[0] ),
+        .O(skid_buffer[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair69"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1 
+       (.I0(s_axi_awaddr[10]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(skid_buffer[10]));
+  (* SOFT_HLUTNM = ""soft_lutpair69"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1 
+       (.I0(s_axi_awaddr[11]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(skid_buffer[11]));
+  (* SOFT_HLUTNM = ""soft_lutpair68"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1 
+       (.I0(s_axi_awaddr[12]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(skid_buffer[12]));
+  (* SOFT_HLUTNM = ""soft_lutpair68"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1__0 
+       (.I0(s_axi_awaddr[13]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(skid_buffer[13]));
+  (* SOFT_HLUTNM = ""soft_lutpair67"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1 
+       (.I0(s_axi_awaddr[14]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(skid_buffer[14]));
+  (* SOFT_HLUTNM = ""soft_lutpair67"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1 
+       (.I0(s_axi_awaddr[15]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(skid_buffer[15]));
+  (* SOFT_HLUTNM = ""soft_lutpair66"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1 
+       (.I0(s_axi_awaddr[16]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(skid_buffer[16]));
+  (* SOFT_HLUTNM = ""soft_lutpair66"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1 
+       (.I0(s_axi_awaddr[17]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(skid_buffer[17]));
+  (* SOFT_HLUTNM = ""soft_lutpair65"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1 
+       (.I0(s_axi_awaddr[18]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(skid_buffer[18]));
+  (* SOFT_HLUTNM = ""soft_lutpair65"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1 
+       (.I0(s_axi_awaddr[19]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(skid_buffer[19]));
+  (* SOFT_HLUTNM = ""soft_lutpair46"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[1]_i_1 
+       (.I0(s_axi_awaddr[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[1] ),
+        .O(skid_buffer[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair64"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1 
+       (.I0(s_axi_awaddr[20]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(skid_buffer[20]));
+  (* SOFT_HLUTNM = ""soft_lutpair64"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1 
+       (.I0(s_axi_awaddr[21]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(skid_buffer[21]));
+  (* SOFT_HLUTNM = ""soft_lutpair63"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1 
+       (.I0(s_axi_awaddr[22]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(skid_buffer[22]));
+  (* SOFT_HLUTNM = ""soft_lutpair63"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1 
+       (.I0(s_axi_awaddr[23]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(skid_buffer[23]));
+  (* SOFT_HLUTNM = ""soft_lutpair62"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1 
+       (.I0(s_axi_awaddr[24]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(skid_buffer[24]));
+  (* SOFT_HLUTNM = ""soft_lutpair62"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1 
+       (.I0(s_axi_awaddr[25]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(skid_buffer[25]));
+  (* SOFT_HLUTNM = ""soft_lutpair61"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1 
+       (.I0(s_axi_awaddr[26]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(skid_buffer[26]));
+  (* SOFT_HLUTNM = ""soft_lutpair61"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1 
+       (.I0(s_axi_awaddr[27]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(skid_buffer[27]));
+  (* SOFT_HLUTNM = ""soft_lutpair60"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1 
+       (.I0(s_axi_awaddr[28]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(skid_buffer[28]));
+  (* SOFT_HLUTNM = ""soft_lutpair60"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1 
+       (.I0(s_axi_awaddr[29]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(skid_buffer[29]));
+  (* SOFT_HLUTNM = ""soft_lutpair52"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[2]_i_1 
+       (.I0(s_axi_awaddr[2]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[2] ),
+        .O(skid_buffer[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair59"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1 
+       (.I0(s_axi_awaddr[30]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(skid_buffer[30]));
+  (* SOFT_HLUTNM = ""soft_lutpair59"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_2 
+       (.I0(s_axi_awaddr[31]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(skid_buffer[31]));
+  (* SOFT_HLUTNM = ""soft_lutpair58"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1 
+       (.I0(s_axi_awprot[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(skid_buffer[32]));
+  (* SOFT_HLUTNM = ""soft_lutpair58"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1 
+       (.I0(s_axi_awprot[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(skid_buffer[33]));
+  (* SOFT_HLUTNM = ""soft_lutpair57"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_1 
+       (.I0(s_axi_awprot[2]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(skid_buffer[34]));
+  (* SOFT_HLUTNM = ""soft_lutpair57"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[35]_i_1 
+       (.I0(s_axi_awsize[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[35] ),
+        .O(skid_buffer[35]));
+  (* SOFT_HLUTNM = ""soft_lutpair56"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[36]_i_1 
+       (.I0(s_axi_awsize[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[36] ),
+        .O(skid_buffer[36]));
+  (* SOFT_HLUTNM = ""soft_lutpair56"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[38]_i_1 
+       (.I0(s_axi_awburst[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[38] ),
+        .O(skid_buffer[38]));
+  (* SOFT_HLUTNM = ""soft_lutpair55"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[39]_i_1 
+       (.I0(s_axi_awburst[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[39] ),
+        .O(skid_buffer[39]));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1 
+       (.I0(s_axi_awaddr[3]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(skid_buffer[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair55"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[44]_i_1 
+       (.I0(s_axi_awlen[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[44] ),
+        .O(skid_buffer[44]));
+  (* SOFT_HLUTNM = ""soft_lutpair54"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[45]_i_1 
+       (.I0(s_axi_awlen[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[45] ),
+        .O(skid_buffer[45]));
+  (* SOFT_HLUTNM = ""soft_lutpair54"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[46]_i_1__0 
+       (.I0(s_axi_awlen[2]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[46] ),
+        .O(skid_buffer[46]));
+  (* SOFT_HLUTNM = ""soft_lutpair53"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[47]_i_1 
+       (.I0(s_axi_awlen[3]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[47] ),
+        .O(skid_buffer[47]));
+  (* SOFT_HLUTNM = ""soft_lutpair72"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1 
+       (.I0(s_axi_awaddr[4]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(skid_buffer[4]));
+  (* SOFT_HLUTNM = ""soft_lutpair53"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[50]_i_1 
+       (.I0(s_axi_awid[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[50] ),
+        .O(skid_buffer[50]));
+  (* SOFT_HLUTNM = ""soft_lutpair52"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[51]_i_1 
+       (.I0(s_axi_awid[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[51] ),
+        .O(skid_buffer[51]));
+  (* SOFT_HLUTNM = ""soft_lutpair48"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[52]_i_1 
+       (.I0(s_axi_awid[2]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[52] ),
+        .O(skid_buffer[52]));
+  (* SOFT_HLUTNM = ""soft_lutpair51"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[53]_i_1 
+       (.I0(s_axi_awid[3]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[53] ),
+        .O(skid_buffer[53]));
+  (* SOFT_HLUTNM = ""soft_lutpair51"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[54]_i_1 
+       (.I0(s_axi_awid[4]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[54] ),
+        .O(skid_buffer[54]));
+  (* SOFT_HLUTNM = ""soft_lutpair50"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[55]_i_1 
+       (.I0(s_axi_awid[5]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[55] ),
+        .O(skid_buffer[55]));
+  (* SOFT_HLUTNM = ""soft_lutpair50"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[56]_i_1 
+       (.I0(s_axi_awid[6]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[56] ),
+        .O(skid_buffer[56]));
+  (* SOFT_HLUTNM = ""soft_lutpair49"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[57]_i_1 
+       (.I0(s_axi_awid[7]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[57] ),
+        .O(skid_buffer[57]));
+  (* SOFT_HLUTNM = ""soft_lutpair49"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[58]_i_1 
+       (.I0(s_axi_awid[8]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[58] ),
+        .O(skid_buffer[58]));
+  (* SOFT_HLUTNM = ""soft_lutpair48"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[59]_i_1 
+       (.I0(s_axi_awid[9]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[59] ),
+        .O(skid_buffer[59]));
+  (* SOFT_HLUTNM = ""soft_lutpair72"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1 
+       (.I0(s_axi_awaddr[5]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(skid_buffer[5]));
+  (* SOFT_HLUTNM = ""soft_lutpair47"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[60]_i_1 
+       (.I0(s_axi_awid[10]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[60] ),
+        .O(skid_buffer[60]));
+  (* SOFT_HLUTNM = ""soft_lutpair46"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[61]_i_1 
+       (.I0(s_axi_awid[11]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[61] ),
+        .O(skid_buffer[61]));
+  (* SOFT_HLUTNM = ""soft_lutpair71"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1 
+       (.I0(s_axi_awaddr[6]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(skid_buffer[6]));
+  (* SOFT_HLUTNM = ""soft_lutpair71"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1 
+       (.I0(s_axi_awaddr[7]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(skid_buffer[7]));
+  (* SOFT_HLUTNM = ""soft_lutpair70"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1 
+       (.I0(s_axi_awaddr[8]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(skid_buffer[8]));
+  (* SOFT_HLUTNM = ""soft_lutpair70"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1 
+       (.I0(s_axi_awaddr[9]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(skid_buffer[9]));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[0]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[10]),
+        .Q(Q[10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[11]),
+        .Q(Q[11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[12]),
+        .Q(Q[12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[13]),
+        .Q(Q[13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[14]),
+        .Q(Q[14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[15]),
+        .Q(Q[15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[16]),
+        .Q(Q[16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[17]),
+        .Q(Q[17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[18]),
+        .Q(Q[18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[19]),
+        .Q(Q[19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[1]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[20]),
+        .Q(Q[20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[21]),
+        .Q(Q[21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[22]),
+        .Q(Q[22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[23]),
+        .Q(Q[23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[24]),
+        .Q(Q[24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[25]),
+        .Q(Q[25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[26]),
+        .Q(Q[26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[27]),
+        .Q(Q[27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[28]),
+        .Q(Q[28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[29]),
+        .Q(Q[29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[2]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[30]),
+        .Q(Q[30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[31]),
+        .Q(Q[31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[32]),
+        .Q(Q[32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[33]),
+        .Q(Q[33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[34]),
+        .Q(Q[34]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[35] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[35]),
+        .Q(Q[35]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[36] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[36]),
+        .Q(Q[36]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[38] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[38]),
+        .Q(\\m_payload_i_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[39] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[39]),
+        .Q(Q[37]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[3]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[44] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[44]),
+        .Q(Q[38]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[45] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[45]),
+        .Q(Q[39]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[46] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[46]),
+        .Q(Q[40]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[47] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[47]),
+        .Q(Q[41]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[4]),
+        .Q(Q[4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[50] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[50]),
+        .Q(Q[42]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[51] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[51]),
+        .Q(Q[43]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[52] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[52]),
+        .Q(Q[44]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[53] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[53]),
+        .Q(Q[45]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[54] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[54]),
+        .Q(Q[46]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[55] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[55]),
+        .Q(Q[47]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[56] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[56]),
+        .Q(Q[48]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[57] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[57]),
+        .Q(Q[49]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[58] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[58]),
+        .Q(Q[50]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[59] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[59]),
+        .Q(Q[51]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[5]),
+        .Q(Q[5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[60] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[60]),
+        .Q(Q[52]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[61] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[61]),
+        .Q(Q[53]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[6]),
+        .Q(Q[6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[7]),
+        .Q(Q[7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[8]),
+        .Q(Q[8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[9]),
+        .Q(Q[9]),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hF4FF)) 
+    m_valid_i_i_1
+       (.I0(b_push),
+        .I1(m_valid_i_reg_0),
+        .I2(s_axi_awvalid),
+        .I3(s_axi_awready),
+        .O(m_valid_i0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i0),
+        .Q(m_valid_i_reg_0),
+        .R(\\aresetn_d_reg[1]_inv_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    next_pending_r_i_2
+       (.I0(Q[40]),
+        .I1(Q[39]),
+        .I2(Q[41]),
+        .I3(Q[38]),
+        .O(next_pending_r_reg));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    s_ready_i_i_1__1
+       (.I0(\\aresetn_d_reg_n_0_[0] ),
+        .O(s_ready_i_reg_0));
+  LUT4 #(
+    .INIT(16\'hF4FF)) 
+    s_ready_i_i_2
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_awready),
+        .I2(b_push),
+        .I3(m_valid_i_reg_0),
+        .O(s_ready_i0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i0),
+        .Q(s_axi_awready),
+        .R(s_ready_i_reg_0));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[10]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[11]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[12]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[13]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[14]),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[15]),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[16]),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[17]),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[18]),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[19]),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[20]),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[21]),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[22]),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[23]),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[24]),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[25]),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[26]),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[27]),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[28]),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[29]),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[30]),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[31]),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awprot[0]),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awprot[1]),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awprot[2]),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[35] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awsize[0]),
+        .Q(\\skid_buffer_reg_n_0_[35] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[36] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awsize[1]),
+        .Q(\\skid_buffer_reg_n_0_[36] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[38] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awburst[0]),
+        .Q(\\skid_buffer_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[39] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awburst[1]),
+        .Q(\\skid_buffer_reg_n_0_[39] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[3]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[44] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awlen[0]),
+        .Q(\\skid_buffer_reg_n_0_[44] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[45] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awlen[1]),
+        .Q(\\skid_buffer_reg_n_0_[45] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[46] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awlen[2]),
+        .Q(\\skid_buffer_reg_n_0_[46] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[47] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awlen[3]),
+        .Q(\\skid_buffer_reg_n_0_[47] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[4]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[50] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[0]),
+        .Q(\\skid_buffer_reg_n_0_[50] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[51] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[1]),
+        .Q(\\skid_buffer_reg_n_0_[51] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[52] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[2]),
+        .Q(\\skid_buffer_reg_n_0_[52] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[53] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[3]),
+        .Q(\\skid_buffer_reg_n_0_[53] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[54] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[4]),
+        .Q(\\skid_buffer_reg_n_0_[54] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[55] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[5]),
+        .Q(\\skid_buffer_reg_n_0_[55] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[56] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[6]),
+        .Q(\\skid_buffer_reg_n_0_[56] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[57] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[7]),
+        .Q(\\skid_buffer_reg_n_0_[57] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[58] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[8]),
+        .Q(\\skid_buffer_reg_n_0_[58] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[59] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[9]),
+        .Q(\\skid_buffer_reg_n_0_[59] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[5]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[60] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[10]),
+        .Q(\\skid_buffer_reg_n_0_[60] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[61] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[11]),
+        .Q(\\skid_buffer_reg_n_0_[61] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[6]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[7]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[8]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[9]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hAA8A)) 
+    \\wrap_boundary_axaddr_r[0]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[38]),
+        .I3(Q[35]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [0]));
+  LUT5 #(
+    .INIT(32\'h8A888AAA)) 
+    \\wrap_boundary_axaddr_r[1]_i_1 
+       (.I0(Q[1]),
+        .I1(Q[36]),
+        .I2(Q[38]),
+        .I3(Q[35]),
+        .I4(Q[39]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [1]));
+  LUT6 #(
+    .INIT(64\'hA0A002A2AAAA02A2)) 
+    \\wrap_boundary_axaddr_r[2]_i_1__0 
+       (.I0(Q[2]),
+        .I1(Q[40]),
+        .I2(Q[35]),
+        .I3(Q[39]),
+        .I4(Q[36]),
+        .I5(Q[38]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [2]));
+  LUT6 #(
+    .INIT(64\'h020202A2A2A202A2)) 
+    \\wrap_boundary_axaddr_r[3]_i_1 
+       (.I0(Q[3]),
+        .I1(\\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
+        .I2(Q[36]),
+        .I3(Q[39]),
+        .I4(Q[35]),
+        .I5(Q[38]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [3]));
+  (* SOFT_HLUTNM = ""soft_lutpair42"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\wrap_boundary_axaddr_r[3]_i_2 
+       (.I0(Q[40]),
+        .I1(Q[35]),
+        .I2(Q[41]),
+        .O(\\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'h002A0A2AA02AAA2A)) 
+    \\wrap_boundary_axaddr_r[4]_i_1__0 
+       (.I0(Q[4]),
+        .I1(Q[41]),
+        .I2(Q[35]),
+        .I3(Q[36]),
+        .I4(Q[40]),
+        .I5(Q[39]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [4]));
+  (* SOFT_HLUTNM = ""soft_lutpair42"" *) 
+  LUT5 #(
+    .INIT(32\'h2A222AAA)) 
+    \\wrap_boundary_axaddr_r[5]_i_1 
+       (.I0(Q[5]),
+        .I1(Q[36]),
+        .I2(Q[40]),
+        .I3(Q[35]),
+        .I4(Q[41]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [5]));
+  LUT4 #(
+    .INIT(16\'h2AAA)) 
+    \\wrap_boundary_axaddr_r[6]_i_1 
+       (.I0(Q[6]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .I3(Q[41]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [6]));
+  LUT6 #(
+    .INIT(64\'hDDDDD8DDAAAAA8AA)) 
+    \\wrap_cnt_r[0]_i_1 
+       (.I0(\\wrap_'b'second_len_r[0]_i_2_n_0 ),
+        .I1(\\wrap_second_len_r[0]_i_3_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\wrap_second_len_r_reg[3] [0]),
+        .O(D[0]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\wrap_cnt_r[1]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[1] ),
+        .I1(\\wrap_cnt_r[3]_i_2_n_0 ),
+        .O(D[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair43"" *) 
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\wrap_cnt_r[2]_i_1 
+       (.I0(wrap_second_len[1]),
+        .I1(\\wrap_cnt_r[3]_i_2_n_0 ),
+        .I2(\\wrap_second_len_r_reg[1] ),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair43"" *) 
+  LUT4 #(
+    .INIT(16\'hA6AA)) 
+    \\wrap_cnt_r[3]_i_1 
+       (.I0(wrap_second_len[2]),
+        .I1(\\wrap_second_len_r_reg[1] ),
+        .I2(\\wrap_cnt_r[3]_i_2_n_0 ),
+        .I3(wrap_second_len[1]),
+        .O(D[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair41"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAABAAA)) 
+    \\wrap_cnt_r[3]_i_2 
+       (.I0(\\wrap_cnt_r[3]_i_3_n_0 ),
+        .I1(\\axaddr_offset_r_reg[1] ),
+        .I2(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I3(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .I4(\\axaddr_offset_r_reg[3] ),
+        .O(\\wrap_cnt_r[3]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'h00000800FFFFF8FF)) 
+    \\wrap_cnt_r[3]_i_3 
+       (.I0(Q[38]),
+        .I1(\\axaddr_offset_r[0]_i_3_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\wrap_second_len_r_reg[3] [0]),
+        .O(\\wrap_cnt_r[3]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'h00000000CCCCCACC)) 
+    \\wrap_second_len_r[0]_i_1 
+       (.I0(\\wrap_second_len_r[0]_i_2_n_0 ),
+        .I1(\\wrap_second_len_r_reg[3] [0]),
+        .I2(\\state_reg[1]_0 [0]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\wrap_second_len_r[0]_i_3_n_0 ),
+        .O(wrap_second_len[0]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFF2FFFFFF)) 
+    \\wrap_second_len_r[0]_i_2 
+       (.I0(\\axaddr_offset_r_reg[3]_0 [3]),
+        .I1(\\state_reg[1] ),
+        .I2(\\wrap_second_len_r[3]_i_2_n_0 ),
+        .I3(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .I4(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I5(\\axaddr_offset_r_reg[1] ),
+        .O(\\wrap_second_len_r[0]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'h00000000FFE200E2)) 
+    \\wrap_second_len_r[0]_i_3 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[2]),
+        .I3(Q[35]),
+        .I4(\\wrap_second_len_r[0]_i_4_n_0 ),
+        .I5(\\wrap_second_len_r[0]_i_5_n_0 ),
+        .O(\\wrap_second_len_r[0]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\wrap_second_len_r[0]_i_4 
+       (.I0(Q[3]),
+        .I1(Q[36]),
+        .I2(Q[1]),
+        .O(\\wrap_second_len_r[0]_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair44"" *) 
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\wrap_second_len_r[0]_i_5 
+       (.I0(Q[38]),
+        .I1(\\state_reg[1]_0 [0]),
+        .I2(m_valid_i_reg_0),
+        .I3(\\state_reg[1]_0 [1]),
+        .O(\\wrap_second_len_r[0]_i_5_n_0 ));
+  LUT6 #(
+    .INIT(64\'h2EE22E222EE22EE2)) 
+    \\wrap_second_len_r[1]_i_1 
+       (.I0(\\wrap_second_len_r_reg[3] [1]),
+        .I1(\\state_reg[1] ),
+        .I2(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I3(\\axaddr_offset_r_reg[1] ),
+        .I4(\\axaddr_offset_r_reg[3] ),
+        .I5(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .O(\\wrap_second_len_r_reg[1] ));
+  LUT6 #(
+    .INIT(64\'h08F3FFFF08F30000)) 
+    \\wrap_second_len_r[2]_i_1 
+       (.I0(\\axaddr_offset_r_reg[3] ),
+        .I1(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I2(\\axaddr_offset_r_reg[1] ),
+        .I3(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .I4(\\state_reg[1] ),
+        .I5(\\wrap_second_len_r_reg[3] [2]),
+        .O(wrap_second_len[1]));
+  LUT6 #(
+    .INIT(64\'hBF00FFFFBF00BF00)) 
+    \\wrap_second_len_r[3]_i_1 
+       (.I0(\\axaddr_offset_r_reg[1] ),
+        .I1(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I2(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .I3(\\wrap_second_len_r[3]_i_2_n_0 ),
+        .I4(\\state_reg[1] ),
+        .I5(\\wrap_second_len_r_reg[3] [3]),
+        .O(wrap_second_len[2]));
+  LUT6 #(
+    .INIT(64\'h00000000EEE222E2)) 
+    \\wrap_second_len_r[3]_i_2 
+       (.I0(\\axaddr_offset_r[2]_i_4_n_0 ),
+        .I1(Q[35]),
+        .I2(Q[4]),
+        .I3(Q[36]),
+        .I4(Q[6]),
+        .I5(\\axlen_cnt_reg[3] ),
+        .O(\\wrap_second_len_r[3]_i_2_n_0 ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_register_slice_v2_1_11_axic_register_slice"" *) 
+module design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1
+   (s_axi_bvalid,
+    \\skid_buffer_reg[0]_0 ,
+    shandshake,
+    \\s_axi_bid[11] ,
+    \\aresetn_d_reg[1]_inv ,
+    aclk,
+    \\aresetn_d_reg[0] ,
+    si_rs_bvalid,
+    s_axi_bready,
+    out,
+    \\s_bresp_acc_reg[1] );
+  output s_axi_bvalid;
+  output \\skid_buffer_reg[0]_0 ;
+  output shandshake;
+  output [13:0]\\s_axi_bid[11] ;
+  input \\aresetn_d_reg[1]_inv ;
+  input aclk;
+  input \\aresetn_d_reg[0] ;
+  input si_rs_bvalid;
+  input s_axi_bready;
+  input [11:0]out;
+  input [1:0]\\s_bresp_acc_reg[1] ;
+
+  wire aclk;
+  wire \\aresetn_d_reg[0] ;
+  wire \\aresetn_d_reg[1]_inv ;
+  wire \\m_payload_i[0]_i_1__1_n_0 ;
+  wire \\m_payload_i[10]_i_1__1_n_0 ;
+  wire \\m_payload_i[11]_i_1__1_n_0 ;
+  wire \\m_payload_i[12]_i_1__1_n_0 ;
+  wire \\m_payload_i[13]_i_2_n_0 ;
+  wire \\m_payload_i[1]_i_1__1_n_0 ;
+  wire \\m_payload_i[2]_i_1__1_n_0 ;
+  wire \\m_payload_i[3]_i_1__1_n_0 ;
+  wire \\m_payload_i[4]_i_1__1_n_0 ;
+  wire \\m_payload_i[5]_i_1__1_n_0 ;
+  wire \\m_payload_i[6]_i_1__1_n_0 ;
+  wire \\m_payload_i[7]_i_1__1_n_0 ;
+  wire \\m_payload_i[8]_i_1__1_n_0 ;
+  wire \\m_payload_i[9]_i_1__1_n_0 ;
+  wire m_valid_i0;
+  wire [11:0]out;
+  wire p_1_in;
+  wire [13:0]\\s_axi_bid[11] ;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [1:0]\\s_bresp_acc_reg[1] ;
+  wire s_ready_i0;
+  wire shandshake;
+  wire si_rs_bvalid;
+  wire \\skid_buffer_reg[0]_0 ;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair80"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[0]_i_1__1 
+       (.I0(\\s_bresp_acc_reg[1] [0]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[0] ),
+        .O(\\m_payload_i[0]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair75"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1__1 
+       (.I0(out[8]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(\\m_payload_i[10]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair74"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1__1 
+       (.I0(out[9]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(\\m_payload_i[11]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair75"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1__1 
+       (.I0(out[10]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(\\m_payload_i[12]_i_1__1_n_0 ));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_payload_i[13]_i_1 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .O(p_1_in));
+  (* SOFT_HLUTNM = ""soft_lutpair74"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_2 
+       (.I0(out[11]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(\\m_payload_i[13]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair80"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[1]_i_1__1 
+       (.I0(\\s_bresp_acc_reg[1] [1]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[1] ),
+        .O(\\m_payload_i[1]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair79"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[2]_i_1__1 
+       (.I0(out[0]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[2] ),
+        .O(\\m_payload_i[2]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair79"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1__1 
+       (.I0(out[1]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(\\m_payload_i[3]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair78"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1__1 
+       (.I0(out[2]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(\\m_payload_i[4]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair78"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1__1 
+       (.I0(out[3]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(\\m_payload_i[5]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair77"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1__1 
+       (.I0(out[4]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(\\m_payload_i[6]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair77"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1__1 
+       (.I0(out[5]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(\\m_payload_i[7]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair76"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1__1 
+       (.I0(out[6]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(\\m_payload_i[8]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair76"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1__1 
+       (.I0(out[7]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(\\m_payload_i[9]_i_1__1_n_0 ));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[0]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[10]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[11]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[12]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[13]_i_2_n_0 ),
+        .Q(\\s_axi_bid[11] [13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[1]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[2]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[3]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[4]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[5]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[6]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[7]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[8]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[9]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [9]),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hF4FF)) 
+    m_valid_i_i_1__0
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(si_rs_bvalid),
+        .I3(\\skid_buffer_reg[0]_0 ),
+        .O(m_valid_i0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i0),
+        .Q(s_axi_bvalid),
+        .R(\\aresetn_d_reg[1]_inv ));
+  (* SOFT_HLUTNM = ""soft_lutpair73"" *) 
+  LUT4 #(
+    .INIT(16\'hF4FF)) 
+    s_ready_i_i_1
+       (.I0(si_rs_bvalid),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(s_axi_bready),
+        .I3(s_axi_bvalid),
+        .O(s_ready_i0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i0),
+        .Q(\\skid_buffer_reg[0]_0 ),
+        .R(\\aresetn_d_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair73"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    shandshake_r_i_1
+       (.I0(\\skid_buffer_reg[0]_0 ),
+        .I1(si_rs_bvalid),
+        .O(shandshake));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\s_bresp_acc_reg[1] [0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[8]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[9]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[10]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[11]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\s_bresp_acc_reg[1] [1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[0]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[1]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[2]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[3]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[4]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[5]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[6]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[7]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_register_slice_v2_1_11_axic_register_slice"" *) 
+module design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2
+   (s_axi_rvalid,
+    \\skid_buffer_reg[0]_0 ,
+    \\s_axi_rid[11] ,
+    \\aresetn_d_reg[1]_inv ,
+    aclk,
+    \\aresetn_d_reg[0] ,
+    \\cnt_read_reg[3]_rep__2 ,
+    s_axi_rready,
+    r_push_r_reg,
+    \\cnt_read_reg[4] );
+  output s_axi_rvalid;
+  output \\skid_buffer_reg[0]_0 ;
+  output [46:0]\\s_axi_rid[11] ;
+  input \\aresetn_d_reg[1]_inv ;
+  input aclk;
+  input \\aresetn_d_reg[0] ;
+  input \\cnt_read_reg[3]_rep__2 ;
+  input s_axi_rready;
+  input [12:0]r_push_r_reg;
+  input [33:0]\\cnt_read_reg[4] ;
+
+  wire aclk;
+  wire \\aresetn_d_reg[0] ;
+  wire \\aresetn_d_reg[1]_inv ;
+  wire \\cnt_read_reg[3]_rep__2 ;
+  wire [33:0]\\cnt_read_reg[4] ;
+  wire \\m_payload_i[0]_i_1__2_n_0 ;
+  wire \\m_payload_i[10]_i_1__2_n_0 ;
+  wire \\m_payload_i[11]_i_1__2_n_0 ;
+  wire \\m_payload_i[12]_i_1__2_n_0 ;
+  wire \\m_payload_i[13]_i_1__2_n_0 ;
+  wire \\m_payload_i[14]_i_1__1_n_0 ;
+  wire \\m_payload_i[15]_i_1__1_n_0 ;
+  wire \\m_payload_i[16]_i_1__1_n_0 ;
+  wire \\m_payload_i[17]_i_1__1_n_0 ;
+  wire \\m_payload_i[18]_i_1__1_n_0 ;
+  wire \\m_payload_i[19]_i_1__1_n_0 ;
+  wire \\m_payload_i[1]_i_1__2_n_0 ;
+  wire \\m_payload_i[20]_i_1__1_n_0 ;
+  wire \\m_payload_i[21]_i_1__1_n_0 ;
+  wire \\m_payload_i[22]_i_1__1_n_0 ;
+  wire \\m_payload_i[23]_i_1__1_n_0 ;
+  wire \\m_payload_i[24]_i_1__1_n_0 ;
+  wire \\m_payload_i[25]_i_1__1_n_0 ;
+  wire \\m_payload_i[26]_i_1__1_n_0 ;
+  wire \\m_payload_i[27]_i_1__1_n_0 ;
+  wire \\m_payload_i[28]_i_1__1_n_0 ;
+  wire \\m_payload_i[29]_i_1__1_n_0 ;
+  wire \\m_payload_i[2]_i_1__2_n_0 ;
+  wire \\m_payload_i[30]_i_1__1_n_0 ;
+  wire \\m_payload_i[31]_i_1__1_n_0 ;
+  wire \\m_payload_i[32]_i_1__1_n_0 ;
+  wire \\m_payload_i[33]_i_1__1_n_0 ;
+  wire \\m_payload_i[34]_i_1__1_n_0 ;
+  wire \\m_payload_i[35]_i_1__1_n_0 ;
+  wire \\m_payload_i[36]_i_1__1_n_0 ;
+  wire \\m_payload_i[37]_i_1_n_0 ;
+  wire \\m_payload_i[38]_i_1__1_n_0 ;
+  wire \\m_payload_i[39]_i_1__1_n_0 ;
+  wire \\m_payload_i[3]_i_1__2_n_0 ;
+  wire \\m_payload_i[40]_i_1_n_0 ;
+  wire \\m_payload_i[41]_i_1_n_0 ;
+  wire \\m_payload_i[42]_i_1_n_0 ;
+  wire \\m_payload_i[43]_i_1_n_0 ;
+  wire \\m_payload_i[44]_i_1__1_n_0 ;
+  wire \\m_payload_i[45]_i_1__1_n_0 ;
+  wire \\m_payload_i[46]_i_2_n_0 ;
+  wire \\m_payload_i[4]_i_1__2_n_0 ;
+  wire \\m_payload_i[5]_i_1__2_n_0 ;
+  wire \\m_payload_i[6]_i_1__2_n_0 ;
+  wire \\m_payload_i[7]_i_1__2_n_0 ;
+  wire \\m_payload_i[8]_i_1__2_n_0 ;
+  wire \\m_payload_i[9]_i_1__2_n_0 ;
+  wire m_valid_i_i_1__2_n_0;
+  wire p_1_in;
+  wire [12:0]r_push_r_reg;
+  wire [46:0]\\s_axi_rid[11] ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_ready_i_i_1__2_n_0;
+  wire \\skid_buffer_reg[0]_0 ;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[35] ;
+  wire \\skid_buffer_reg_n_0_[36] ;
+  wire \\skid_buffer_reg_n_0_[37] ;
+  wire \\skid_buffer_reg_n_0_[38] ;
+  wire \\skid_buffer_reg_n_0_[39] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[40] ;
+  wire \\skid_buffer_reg_n_0_[41] ;
+  wire \\skid_buffer_reg_n_0_[42] ;
+  wire \\skid_buffer_reg_n_0_[43] ;
+  wire \\skid_buffer_reg_n_0_[44] ;
+  wire \\skid_buffer_reg_n_0_[45] ;
+  wire \\skid_buffer_reg_n_0_[46] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[0]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [0]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[0] ),
+        .O(\\m_payload_i[0]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair99"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [10]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(\\m_payload_i[10]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair98"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [11]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(\\m_payload_i[11]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair98"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [12]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(\\m_payload_i[12]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair97"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [13]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(\\m_payload_i[13]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair97"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [14]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(\\m_payload_i[14]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair96"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [15]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(\\m_payload_i[15]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair96"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [16]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(\\m_payload_i[16]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair95"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [17]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(\\m_payload_i[17]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair95"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [18]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(\\m_payload_i[18]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair94"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [19]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(\\m_payload_i[19]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair103"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[1]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [1]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[1] ),
+        .O(\\m_payload_i[1]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair94"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [20]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(\\m_payload_i[20]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair93"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [21]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(\\m_payload_i[21]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair93"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [22]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(\\m_payload_i[22]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair92"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [23]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(\\m_payload_i[23]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair92"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [24]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(\\m_payload_i[24]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair91"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [25]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(\\m_payload_i[25]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair91"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [26]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(\\m_payload_i[26]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair90"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [27]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(\\m_payload_i[27]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair90"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [28]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(\\m_payload_i[28]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair89"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [29]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(\\m_payload_i[29]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair103"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[2]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [2]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[2] ),
+        .O(\\m_payload_i[2]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair89"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [30]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(\\m_payload_i[30]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair88"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [31]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(\\m_payload_i[31]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair88"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [32]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(\\m_payload_i[32]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair87"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [33]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(\\m_payload_i[33]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair87"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_1__1 
+       (.I0(r_push_r_reg[0]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(\\m_payload_i[34]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair86"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[35]_i_1__1 
+       (.I0(r_push_r_reg[1]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[35] ),
+        .O(\\m_payload_i[35]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair86"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[36]_i_1__1 
+       (.I0(r_push_r_reg[2]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[36] ),
+        .O(\\m_payload_i[36]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair85"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[37]_i_1 
+       (.I0(r_push_r_reg[3]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[37] ),
+        .O(\\m_payload_i[37]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair85"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[38]_i_1__1 
+       (.I0(r_push_r_reg[4]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[38] ),
+        .O(\\m_payload_i[38]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair84"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[39]_i_1__1 
+       (.I0(r_push_r_reg[5]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[39] ),
+        .O(\\m_payload_i[39]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair102"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [3]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(\\m_payload_i[3]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair84"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[40]_i_1 
+       (.I0(r_push_r_reg[6]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[40] ),
+        .O(\\m_payload_i[40]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair83"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[41]_i_1 
+       (.I0(r_push_r_reg[7]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[41] ),
+        .O(\\m_payload_i[41]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair83"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[42]_i_1 
+       (.I0(r_push_r_reg[8]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[42] ),
+        .O(\\m_payload_i[42]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair82"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[43]_i_1 
+       (.I0(r_push_r_reg[9]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[43] ),
+        .O(\\m_payload_i[43]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair81"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[44]_i_1__1 
+       (.I0(r_push_r_reg[10]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[44] ),
+        .O(\\m_payload_i[44]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair82"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[45]_i_1__1 
+       (.I0(r_push_r_reg[11]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[45] ),
+        .O(\\m_payload_i[45]_i_1__1_n_0 ));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_payload_i[46]_i_1 
+       (.I0(s_axi_rready),
+        .I1(s_axi_rvalid),
+        .O(p_1_in));
+  (* SOFT_HLUTNM = ""soft_lutpair81"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[46]_i_2 
+       (.I0(r_push_r_reg[12]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[46] ),
+        .O(\\m_payload_i[46]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair102"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [4]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(\\m_payload_i[4]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair101"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [5]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(\\m_payload_i[5]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair101"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [6]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(\\m_payload_i[6]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair100"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [7]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(\\m_payload_i[7]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair100"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [8]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(\\m_payload_i[8]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair99"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [9]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(\\m_payload_i[9]_i_1__2_n_0 ));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[0]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[10]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[11]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[12]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[13]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[14]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[15]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[16]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[17]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[18]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[19]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[1]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[20]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[21]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[22]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[23]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[24]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[25]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[26]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[27]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[28]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[29]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[2]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[30]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[31]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[32]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[33]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[34]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [34]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[35] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[35]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [35]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[36] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[36]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [36]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[37] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[37]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [37]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[38] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[38]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [38]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[39] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[39]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [39]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[3]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[40] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[40]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [40]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[41] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[41]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [41]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[42] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[42]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [42]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[43] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[43]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [43]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[44] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[44]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [44]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[45] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[45]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [45]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[46] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[46]_i_2_n_0 ),
+        .Q(\\s_axi_rid[11] [46]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[4]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[5]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[6]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[7]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[8]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[9]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [9]),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'h4FFF)) 
+    m_valid_i_i_1__2
+       (.I0(s_axi_rready),
+        .I1(s_axi_rvalid),
+        .I2(\\skid_buffer_reg[0]_0 ),
+        .I3(\\cnt_read_reg[3]_rep__2 ),
+        .O(m_valid_i_i_1__2_n_0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i_i_1__2_n_0),
+        .Q(s_axi_rvalid),
+        .R(\\aresetn_d_reg[1]_inv ));
+  LUT4 #(
+    .INIT(16\'hF8FF)) 
+    s_ready_i_i_1__2
+       (.I0(\\skid_buffer_reg[0]_0 ),
+        .I1(\\cnt_read_reg[3]_rep__2 ),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(s_ready_i_i_1__2_n_0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i_i_1__2_n_0),
+        .Q(\\skid_buffer_reg[0]_0 ),
+        .R(\\aresetn_d_reg[0] ));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [10]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [11]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [12]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [13]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [14]),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [15]),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [16]),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [17]),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [18]),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [19]),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [20]),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [21]),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [22]),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [23]),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [24]),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [25]),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [26]),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [27]),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [28]),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [29]),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [30]),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [31]),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [32]),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [33]),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[0]),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[35] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[1]),
+        .Q(\\skid_buffer_reg_n_0_[35] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[36] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[2]),
+        .Q(\\skid_buffer_reg_n_0_[36] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[37] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[3]),
+        .Q(\\skid_buffer_reg_n_0_[37] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[38] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[4]),
+        .Q(\\skid_buffer_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[39] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[5]),
+        .Q(\\skid_buffer_reg_n_0_[39] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [3]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[40] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[6]),
+        .Q(\\skid_buffer_reg_n_0_[40] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[41] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[7]),
+        .Q(\\skid_buffer_reg_n_0_[41] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[42] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[8]),
+        .Q(\\skid_buffer_reg_n_0_[42] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[43] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[9]),
+        .Q(\\skid_buffer_reg_n_0_[43] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[44] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[10]),
+        .Q(\\skid_buffer_reg_n_0_[44] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[45] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[11]),
+        .Q(\\skid_buffer_reg_n_0_[45] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[46] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[12]),
+        .Q(\\skid_buffer_reg_n_0_[46] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [4]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [5]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [6]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [7]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [8]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [9]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module design_1_auto_pc_0
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awqos,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arqos,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awaddr,
+    m_axi_awprot,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bresp,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_araddr,
+    m_axi_arprot,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rvalid,
+    m_axi_rready);
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLK CLK"" *) input aclk;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RST RST"" *) input aresetn;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWID"" *) input [11:0]s_axi_awid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [31:0]s_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWLEN"" *) input [3:0]s_axi_awlen;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"" *) input [2:0]s_axi_awsize;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWBURST"" *) input [1:0]s_axi_awburst;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"" *) input [1:0]s_axi_awlock;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"" *) input [3:0]s_axi_awcache;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWPROT"" *) input [2:0]s_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWQOS"" *) input [3:0]s_axi_awqos;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *) input s_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WID"" *) input [11:0]s_axi_wid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WLAST"" *) input s_axi_wlast;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BID"" *) output [11:0]s_axi_bid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARID"" *) input [11:0]s_axi_arid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [31:0]s_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARLEN"" *) input [3:0]s_axi_arlen;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"" *) input [2:0]s_axi_arsize;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARBURST"" *) input [1:0]s_axi_arburst;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"" *) input [1:0]s_axi_arlock;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"" *) input [3:0]s_axi_arcache;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARPROT"" *) input [2:0]s_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARQOS"" *) input [3:0]s_axi_arqos;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RID"" *) output [11:0]s_axi_rid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RLAST"" *) output s_axi_rlast;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWADDR"" *) output [31:0]m_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWPROT"" *) output [2:0]m_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWVALID"" *) output m_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWREADY"" *) input m_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WDATA"" *) output [31:0]m_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WSTRB"" *) output [3:0]m_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WVALID"" *) output m_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WREADY"" *) input m_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BRESP"" *) input [1:0]m_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BVALID"" *) input m_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BREADY"" *) output m_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARADDR"" *) output [31:0]m_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARPROT"" *) output [2:0]m_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARVALID"" *) output m_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARREADY"" *) input m_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RDATA"" *) input [31:0]m_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RRESP"" *) input [1:0]m_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RVALID"" *) input m_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RREADY"" *) output m_axi_rready;
+
+  wire aclk;
+  wire aresetn;
+  wire [31:0]m_axi_araddr;
+  wire [2:0]m_axi_arprot;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire [31:0]m_axi_awaddr;
+  wire [2:0]m_axi_awprot;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire m_axi_bready;
+  wire [1:0]m_axi_bresp;
+  wire m_axi_bvalid;
+  wire [31:0]m_axi_rdata;
+  wire m_axi_rready;
+  wire [1:0]m_axi_rresp;
+  wire m_axi_rvalid;
+  wire [31:0]m_axi_wdata;
+  wire m_axi_wready;
+  wire [3:0]m_axi_wstrb;
+  wire m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [3:0]s_axi_arcache;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [1:0]s_axi_arlock;
+  wire [2:0]s_axi_arprot;
+  wire [3:0]s_axi_arqos;
+  wire s_axi_arready;
+  wire [2:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [3:0]s_axi_awcache;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [1:0]s_axi_awlock;
+  wire [2:0]s_axi_awprot;
+  wire [3:0]s_axi_awqos;
+  wire s_axi_awready;
+  wire [2:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire [11:0]s_axi_bid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [11:0]s_axi_rid;
+  wire s_axi_rlast;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [11:0]s_axi_wid;
+  wire s_axi_wlast;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire NLW_inst_m_axi_wlast_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+  (* C_AXI_ADDR_WIDTH = ""32"" *) 
+  (* C_AXI_ARUSER_WIDTH = ""1"" *) 
+  (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+  (* C_AXI_BUSER_WIDTH = ""1"" *) 
+  (* C_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_AXI_ID_WIDTH = ""12"" *) 
+  (* C_AXI_RUSER_WIDTH = ""1"" *) 
+  (* C_AXI_SUPPORTS_READ = ""1"" *) 
+  (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+  (* C_AXI_SUPPORTS_WRITE = ""1"" *) 
+  (* C_AXI_WUSER_WIDTH = ""1"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_IGNORE_ID = ""0"" *) 
+  (* C_M_AXI_PROTOCOL = ""2"" *) 
+  (* C_S_AXI_PROTOCOL = ""1"" *) 
+  (* C_TRANSLATION_MODE = ""2"" *) 
+  (* DowngradeIPIdentifiedWarnings = ""yes"" *) 
+  (* P_AXI3 = ""1"" *) 
+  (* P_AXI4 = ""0"" *) 
+  (* P_AXILITE = ""2"" *) 
+  (* P_AXILITE_SIZE = ""3\'b010"" *) 
+  (* P_CONVERSION = ""2"" *) 
+  (* P_DECERR = ""2\'b11"" *) 
+  (* P_INCR = ""2\'b01"" *) 
+  (* P_PROTECTION = ""1"" *) 
+  (* P_SLVERR = ""2\'b10"" *) 
+  design_1_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter inst
+       (.aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
+        .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
+        .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
+        .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
+        .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
+        .m_axi_arprot(m_axi_arprot),
+        .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
+        .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
+        .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
+        .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
+        .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
+        .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
+        .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
+        .m_axi_awprot(m_axi_awprot),
+        .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
+        .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
+        .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bid({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_buser(1\'b0),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rid({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .m_axi_rlast(1\'b1),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_ruser(1\'b0),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wdata(m_axi_wdata),
+        .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
+        .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wstrb(m_axi_wstrb),
+        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arcache(s_axi_arcache),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arlock(s_axi_arlock),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arqos(s_axi_arqos),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arregion({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arsize(s_axi_arsize),
+        .s_axi_aruser(1\'b0),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awcache(s_axi_awcache),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awlock(s_axi_awlock),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awqos(s_axi_awqos),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awregion({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awsize(s_axi_awsize),
+        .s_axi_awuser(1\'b0),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bid(s_axi_bid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rid(s_axi_rid),
+        .s_axi_rlast(s_axi_rlast),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wid(s_axi_wid),
+        .s_axi_wlast(s_axi_wlast),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wuser(1\'b0),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:56:44 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_sim_netlist.v
+// Design      : design_1_xbar_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd
+   (aa_grant_any,
+    m_valid_i,
+    SR,
+    aa_grant_rnw,
+    D,
+    any_error,
+    Q,
+    \\m_ready_d_reg[2] ,
+    s_axi_bvalid,
+    m_axi_bready,
+    \\gen_axilite.s_axi_bvalid_i_reg ,
+    \\m_ready_d_reg[2]_0 ,
+    s_axi_wready,
+    m_axi_wvalid,
+    \\m_ready_d_reg[1] ,
+    m_axi_awvalid,
+    \\m_ready_d_reg[2]_1 ,
+    m_axi_arvalid,
+    m_valid_i_reg,
+    E,
+    \\m_ready_d_reg[1]_0 ,
+    \\m_ready_d_reg[0] ,
+    s_axi_awready,
+    s_axi_arready,
+    aclk,
+    aresetn_d,
+    \\m_atarget_enc_reg[0] ,
+    m_ready_d0,
+    \\m_ready_d_reg[1]_1 ,
+    \\m_ready_d_reg[2]_2 ,
+    m_atarget_enc,
+    mi_wready,
+    m_axi_awready,
+    \\gen_axilite.s_axi_bvalid_i_reg_0 ,
+    \\m_atarget_hot_reg[1] ,
+    m_ready_d,
+    s_axi_bready,
+    \\gen_axilite.s_axi_awready_i_reg ,
+    s_axi_wvalid,
+    m_ready_d_0,
+    mi_rvalid,
+    s_axi_rready,
+    sr_rvalid,
+    mi_arready,
+    m_axi_arready,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_awvalid);
+  output aa_grant_any;
+  output m_valid_i;
+  output [0:0]SR;
+  output aa_grant_rnw;
+  output [2:0]D;
+  output any_error;
+  output [34:0]Q;
+  output \\m_ready_d_reg[2] ;
+  output [0:0]s_axi_bvalid;
+  output [1:0]m_axi_bready;
+  output \\gen_axilite.s_axi_bvalid_i_reg ;
+  output \\m_ready_d_reg[2]_0 ;
+  output [0:0]s_axi_wready;
+  output [1:0]m_axi_wvalid;
+  output \\m_ready_d_reg[1] ;
+  output [1:0]m_axi_awvalid;
+  output \\m_ready_d_reg[2]_1 ;
+  output [1:0]m_axi_arvalid;
+  output m_valid_i_reg;
+  output [0:0]E;
+  output \\m_ready_d_reg[1]_0 ;
+  output \\m_ready_d_reg[0] ;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  input aclk;
+  input aresetn_d;
+  input \\m_atarget_enc_reg[0] ;
+  input [0:0]m_ready_d0;
+  input \\m_ready_d_reg[1]_1 ;
+  input \\m_ready_d_reg[2]_2 ;
+  input [1:0]m_atarget_enc;
+  input [0:0]mi_wready;
+  input [0:0]m_axi_awready;
+  input \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  input [1:0]\\m_atarget_hot_reg[1] ;
+  input [2:0]m_ready_d;
+  input [0:0]s_axi_bready;
+  input \\gen_axilite.s_axi_awready_i_reg ;
+  input [0:0]s_axi_wvalid;
+  input [1:0]m_ready_d_0;
+  input [0:0]mi_rvalid;
+  input [0:0]s_axi_rready;
+  input sr_rvalid;
+  input [0:0]mi_arready;
+  input [0:0]m_axi_arready;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input [0:0]s_axi_awvalid;
+
+  wire [2:0]D;
+  wire [0:0]E;
+  wire [34:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aclk;
+  wire any_error;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_awready_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  wire \\gen_no_arbiter.grant_rnw_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
+  wire \\gen_no_arbiter.m_valid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc[1]_i_2_n_0 ;
+  wire \\m_atarget_enc[1]_i_3_n_0 ;
+  wire \\m_atarget_enc[1]_i_4_n_0 ;
+  wire \\m_atarget_enc_reg[0] ;
+  wire [1:0]\\m_atarget_hot_reg[1] ;
+  wire [0:0]m_axi_arready;
+  wire [1:0]m_axi_arvalid;
+  wire [0:0]m_axi_awready;
+  wire [1:0]m_axi_awvalid;
+  wire [1:0]m_axi_bready;
+  wire [1:0]m_axi_wvalid;
+  wire [2:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire [1:0]m_ready_d_0;
+  wire \\m_ready_d_reg[0] ;
+  wire \\m_ready_d_reg[1] ;
+  wire \\m_ready_d_reg[1]_0 ;
+  wire \\m_ready_d_reg[1]_1 ;
+  wire \\m_ready_d_reg[2] ;
+  wire \\m_ready_d_reg[2]_0 ;
+  wire \\m_ready_d_reg[2]_1 ;
+  wire \\m_ready_d_reg[2]_2 ;
+  wire m_valid_i;
+  wire m_valid_i_reg;
+  wire [0:0]mi_arready;
+  wire [0:0]mi_rvalid;
+  wire [0:0]mi_wready;
+  wire p_0_in1_in;
+  wire [48:1]s_amesg;
+  wire \\s_arvalid_reg[0]_i_1_n_0 ;
+  wire \\s_arvalid_reg_reg_n_0_[0] ;
+  wire s_awvalid_reg;
+  wire \\s_awvalid_reg[0]_i_1_n_0 ;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [0:0]s_axi_bvalid;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire s_ready_i;
+  wire sr_rvalid;
+
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\gen_axilite.s_axi_bvalid_i_i_2 
+       (.I0(s_axi_bready),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[0]),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg ));
+  LUT6 #(
+    .INIT(64\'hFFFFFF4700000044)) 
+    \\gen_no_arbiter.grant_rnw_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_arvalid),
+        .I2(s_axi_awvalid),
+        .I3(aa_grant_any),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\gen_no_arbiter.grant_rnw_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.grant_rnw_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.grant_rnw_i_1_n_0 ),
+        .Q(aa_grant_rnw),
+        .R(SR));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[10]_i_1 
+       (.I0(s_axi_araddr[9]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[9]),
+        .O(s_amesg[10]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[11]_i_1 
+       (.I0(s_axi_araddr[10]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[10]),
+        .O(s_amesg[11]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[12]_i_1 
+       (.I0(s_axi_araddr[11]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[11]),
+        .O(s_amesg[12]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[13]_i_1 
+       (.I0(s_axi_araddr[12]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[12]),
+        .O(s_amesg[13]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[14]_i_1 
+       (.I0(s_axi_araddr[13]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[13]),
+        .O(s_amesg[14]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[15]_i_1 
+       (.I0(s_axi_araddr[14]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[14]),
+        .O(s_amesg[15]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[16]_i_1 
+       (.I0(s_axi_araddr[15]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[15]),
+        .O(s_amesg[16]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[17]_i_1 
+       (.I0(s_axi_araddr[16]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[16]),
+        .O(s_amesg[17]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[18]_i_1 
+       (.I0(s_axi_araddr[17]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[17]),
+        .O(s_amesg[18]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[19]_i_1 
+       (.I0(s_axi_araddr[18]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[18]),
+        .O(s_amesg[19]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[1]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[0]),
+        .O(s_amesg[1]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[20]_i_1 
+       (.I0(s_axi_araddr[19]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[19]),
+        .O(s_amesg[20]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[21]_i_1 
+       (.I0(s_axi_araddr[20]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[20]),
+        .O(s_amesg[21]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[22]_i_1 
+       (.I0(s_axi_araddr[21]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[21]),
+        .O(s_amesg[22]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[23]_i_1 
+       (.I0(s_axi_araddr[22]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[22]),
+        .O(s_amesg[23]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[24]_i_1 
+       (.I0(s_axi_araddr[23]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[23]),
+        .O(s_amesg[24]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[25]_i_1 
+       (.I0(s_axi_araddr[24]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[24]),
+        .O(s_amesg[25]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[26]_i_1 
+       (.I0(s_axi_araddr[25]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[25]),
+        .O(s_amesg[26]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[27]_i_1 
+       (.I0(s_axi_araddr[26]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[26]),
+        .O(s_amesg[27]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[28]_i_1 
+       (.I0(s_axi_araddr[27]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[27]),
+        .O(s_amesg[28]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[29]_i_1 
+       (.I0(s_axi_araddr[28]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[28]),
+        .O(s_amesg[29]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[2]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[1]),
+        .O(s_amesg[2]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[30]_i_1 
+       (.I0(s_axi_araddr[29]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[29]),
+        .O(s_amesg[30]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[31]_i_1 
+       (.I0(s_axi_araddr[30]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[30]),
+        .O(s_amesg[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_1 
+       (.I0(aresetn_d),
+        .O(SR));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_2 
+       (.I0(aa_grant_any),
+        .O(p_0_in1_in));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_3 
+       (.I0(s_axi_araddr[31]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[31]),
+        .O(s_amesg[32]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[3]_i_1 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[2]),
+        .O(s_amesg[3]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[46]_i_1 
+       (.I0(s_axi_arprot[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[0]),
+        .O(s_amesg[46]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[47]_i_1 
+       (.I0(s_axi_arprot[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[1]),
+        .O(s_amesg[47]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[48]_i_1 
+       (.I0(s_axi_arprot[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[2]),
+        .O(s_amesg[48]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[4]_i_1 
+       (.I0(s_axi_araddr[3]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[3]),
+        .O(s_amesg[4]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[5]_i_1 
+       (.I0(s_axi_araddr[4]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[4]),
+        .O(s_amesg[5]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[6]_i_1 
+       (.I0(s_axi_araddr[5]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[5]),
+        .O(s_amesg[6]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[7]_i_1 
+       (.I0(s_axi_araddr[6]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[6]),
+        .O(s_amesg[7]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[8]_i_1 
+       (.I0(s_axi_araddr[7]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[7]),
+        .O(s_amesg[8]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[9]_i_1 
+       (.I0(s_axi_araddr[8]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[8]),
+        .O(s_amesg[9]));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[10] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[10]),
+        .Q(Q[9]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[11] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[11]),
+        .Q(Q[10]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[12] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[12]),
+        .Q(Q[11]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[13] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[13]),
+        .Q(Q[12]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[14] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[14]),
+        .Q(Q[13]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[15] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[15]),
+        .Q(Q[14]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[16] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[16]),
+        .Q(Q[15]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[17] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[17]),
+        .Q(Q[16]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[18] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[18]),
+        .Q(Q[17]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[19] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[19]),
+        .Q(Q[18]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[1] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[1]),
+        .Q(Q[0]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[20] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[20]),
+        .Q(Q[19]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[21] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[21]),
+        .Q(Q[20]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[22] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[22]),
+        .Q(Q[21]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[23] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[23]),
+        .Q(Q[22]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[24] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[24]),
+        .Q(Q[23]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[25] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[25]),
+        .Q(Q[24]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[26] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[26]),
+        .Q(Q[25]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[27] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[27]),
+        .Q(Q[26]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[28] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[28]),
+        .Q(Q[27]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[29] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[29]),
+        .Q(Q[28]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[2] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[2]),
+        .Q(Q[1]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[30] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[30]),
+        .Q(Q[29]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[31] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[31]),
+        .Q(Q[30]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[32] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[32]),
+        .Q(Q[31]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[3] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[3]),
+        .Q(Q[2]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[46] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[46]),
+        .Q(Q[32]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[47] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[47]),
+        .Q(Q[33]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[48] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[48]),
+        .Q(Q[34]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[4] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[4]),
+        .Q(Q[3]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[5] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[5]),
+        .Q(Q[4]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[6] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[6]),
+        .Q(Q[5]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[7] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[7]),
+        .Q(Q[6]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[8] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[8]),
+        .Q(Q[7]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[9] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[9]),
+        .Q(Q[8]),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h00000000DDDC0000)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_1 
+       (.I0(m_valid_i),
+        .I1(aa_grant_any),
+        .I2(s_axi_awvalid),
+        .I3(s_axi_arvalid),
+        .I4(aresetn_d),
+        .I5(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h808080808080B080)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_2 
+       (.I0(\\m_atarget_enc_reg[0] ),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d0),
+        .I4(\\m_ready_d_reg[1]_1 ),
+        .I5(\\m_ready_d_reg[2]_2 ),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
+  FDRE \\gen_no_arbiter.m_grant_hot_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
+        .Q(aa_grant_any),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT3 #(
+    .INIT(8\'h74)) 
+    \\gen_no_arbiter.m_valid_i_i_1 
+       (.I0(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
+        .I1(m_valid_i),
+        .I2(aa_grant_any),
+        .O(\\gen_no_arbiter.m_valid_i_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.m_valid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_valid_i_i_1_n_0 ),
+        .Q(m_valid_i),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT3 #(
+    .INIT(8\'h40)) 
+    \\gen_no_arbiter.s_ready_i[0]_i_1 
+       (.I0(m_valid_i),
+        .I1(aa_grant_any),
+        .I2(aresetn_d),
+        .O(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.s_ready_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
+        .Q(s_ready_i),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFFFFFFFE)) 
+    \\m_atarget_enc[1]_i_1 
+       (.I0(\\m_atarget_enc[1]_i_2_n_0 ),
+        .I1(\\m_atarget_enc[1]_i_3_n_0 ),
+        .I2(\\m_atarget_enc[1]_i_4_n_0 ),
+        .I3(Q[18]),
+        .I4(Q[25]),
+        .I5(Q[17]),
+        .O(any_error));
+  LUT4 #(
+    .INIT(16\'hFFEF)) 
+    \\m_atarget_enc[1]_i_2 
+       (.I0(Q[22]),
+        .I1(Q[29]),
+        .I2(Q[24]),
+        .I3(Q[27]),
+        .O(\\m_atarget_enc[1]_i_2_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\m_atarget_enc[1]_i_3 
+       (.I0(Q[21]),
+        .I1(Q[26]),
+        .I2(Q[30]),
+        .I3(Q[19]),
+        .O(\\m_atarget_enc[1]_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    \\m_atarget_enc[1]_i_4 
+       (.I0(Q[28]),
+        .I1(Q[23]),
+        .I2(Q[20]),
+        .I3(Q[31]),
+        .O(\\m_atarget_enc[1]_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\m_atarget_hot[0]_i_1 
+       (.I0(any_error),
+        .I1(aa_grant_any),
+        .I2(Q[16]),
+        .O(D[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT3 #(
+    .INIT(8\'h40)) 
+    \\m_atarget_hot[1]_i_1 
+       (.I0(any_error),
+        .I1(Q[16]),
+        .I2(aa_grant_any),
+        .O(D[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_atarget_hot[2]_i_1 
+       (.I0(any_error),
+        .I1(aa_grant_any),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(m_ready_d_0[1]),
+        .O(m_axi_arvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d[2]),
+        .O(m_axi_awvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h00200000)) 
+    \\m_axi_bready[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(m_ready_d[0]),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(s_axi_bready),
+        .O(m_axi_bready[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [0]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[1] [1]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h4000FFFF)) 
+    \\m_payload_i[34]_i_1 
+       (.I0(m_ready_d_0[0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(s_axi_rready),
+        .I4(sr_rvalid),
+        .O(E));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h7)) 
+    \\m_ready_d[0]_i_2 
+       (.I0(m_valid_i),
+        .I1(aa_grant_rnw),
+        .O(\\m_ready_d_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hC4F4FFFFFFFFFFFF)) 
+    \\m_ready_d[1]_i_4 
+       (.I0(mi_arready),
+        .I1(m_atarget_enc[1]),
+        .I2(m_atarget_enc[0]),
+        .I3(m_axi_arready),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\m_ready_d_reg[1]_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_ready_d[2]_i_6 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .O(\\m_ready_d_reg[2]_1 ));
+  LUT6 #(
+    .INIT(64\'hFFFFA2F2FFFFFFFF)) 
+    \\m_ready_d[2]_i_7 
+       (.I0(m_atarget_enc[1]),
+        .I1(mi_wready),
+        .I2(m_atarget_enc[0]),
+        .I3(m_axi_awready),
+        .I4(aa_grant_rnw),
+        .I5(m_valid_i),
+        .O(\\m_ready_d_reg[2] ));
+  LUT5 #(
+    .INIT(32\'h0000D000)) 
+    m_valid_i_i_3
+       (.I0(m_atarget_enc[1]),
+        .I1(mi_rvalid),
+        .I2(m_valid_i),
+        .I3(aa_grant_rnw),
+        .I4(m_ready_d_0[0]),
+        .O(m_valid_i_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT4 #(
+    .INIT(16\'h0040)) 
+    \\s_arvalid_reg[0]_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_arvalid),
+        .I2(aresetn_d),
+        .I3(s_ready_i),
+        .O(\\s_arvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_arvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_arvalid_reg[0]_i_1_n_0 ),
+        .Q(\\s_arvalid_reg_reg_n_0_[0] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h0000000000D00000)) 
+    \\s_awvalid_reg[0]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_awvalid_reg),
+        .I2(s_axi_awvalid),
+        .I3(\\s_arvalid_reg_reg_n_0_[0] ),
+        .I4(aresetn_d),
+        .I5(s_ready_i),
+        .O(\\s_awvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_awvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_awvalid_reg[0]_i_1_n_0 ),
+        .Q(s_awvalid_reg),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_arready[0]_INST_0 
+       (.I0(aa_grant_rnw),
+        .I1(s_ready_i),
+        .O(s_axi_arready));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_awready[0]_INST_0 
+       (.I0(s_ready_i),
+        .I1(aa_grant_rnw),
+        .O(s_axi_awready));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_bvalid[0]_INST_0 
+       (.I0(aa_grant_any),
+        .I1(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .O(s_axi_bvalid));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'hFB)) 
+    \\s_axi_bvalid[0]_INST_0_i_2 
+       (.I0(m_ready_d[0]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .O(\\m_ready_d_reg[2]_0 ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_wready[0]_INST_0 
+       (.I0(aa_grant_any),
+        .I1(\\gen_axilite.s_axi_awready_i_reg ),
+        .O(s_axi_wready));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT3 #(
+    .INIT(8\'hFB)) 
+    \\s_axi_wready[0]_INST_0_i_2 
+       (.I0(m_ready_d[1]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .O(\\m_ready_d_reg[1] ));
+endmodule
+
+(* C_AXI_ADDR_WIDTH = ""32"" *) (* C_AXI_ARUSER_WIDTH = ""1"" *) (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+(* C_AXI_BUSER_WIDTH = ""1"" *) (* C_AXI_DATA_WIDTH = ""32"" *) (* C_AXI_ID_WIDTH = ""1"" *) 
+(* C_AXI_PROTOCOL = ""2"" *) (* C_AXI_RUSER_WIDTH = ""1"" *) (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+(* C_AXI_WUSER_WIDTH = ""1"" *) (* C_CONNECTIVITY_MODE = ""0"" *) (* C_DEBUG = ""1"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_M_AXI_ADDR_WIDTH = ""64\'b0000000000000000000000000001000000000000000000000000000000010000"" *) (* C_M_AXI_BASE_ADDR = ""128\'b00000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+(* C_M_AXI_READ_CONNECTIVITY = ""64\'b1111111111111111111111111111111111111111111111111111111111111111"" *) (* C_M_AXI_READ_ISSUING = ""64\'b0000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_SECURE = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+(* C_M_AXI_WRITE_CONNECTIVITY = ""64\'b1111111111111111111111111111111111111111111111111111111111111111"" *) (* C_M_AXI_WRITE_ISSUING = ""64\'b0000000000000000000000000000000100000000000000000000000000000001"" *) (* C_NUM_ADDR_RANGES = ""1"" *) 
+(* C_NUM_MASTER_SLOTS = ""2"" *) (* C_NUM_SLAVE_SLOTS = ""1"" *) (* C_R_REGISTER = ""1"" *) 
+(* C_S_AXI_ARB_PRIORITY = ""0"" *) (* C_S_AXI_BASE_ID = ""0"" *) (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+(* C_S_AXI_SINGLE_THREAD = ""1"" *) (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+(* DowngradeIPIdentifiedWarnings = ""yes"" *) (* P_ADDR_DECODE = ""1"" *) (* P_AXI3 = ""1"" *) 
+(* P_AXI4 = ""0"" *) (* P_AXILITE = ""2"" *) (* P_AXILITE_SIZE = ""3\'b010"" *) 
+(* P_FAMILY = ""zynq"" *) (* P_INCR = ""2\'b01"" *) (* P_LEN = ""8"" *) 
+(* P_LOCK = ""1"" *) (* P_M_AXI_ERR_MODE = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_M_AXI_SUPPORTS_READ = ""2\'b11"" *) 
+(* P_M_AXI_SUPPORTS_WRITE = ""2\'b11"" *) (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) (* P_RANGE_CHECK = ""1"" *) 
+(* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+(* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awqos,
+    s_axi_awuser,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wuser,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_buser,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arqos,
+    s_axi_aruser,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_ruser,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awid,
+    m_axi_awaddr,
+    m_axi_awlen,
+    m_axi_awsize,
+    m_axi_awburst,
+    m_axi_awlock,
+    m_axi_awcache,
+    m_axi_awprot,
+    m_axi_awregion,
+    m_axi_awqos,
+    m_axi_awuser,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wid,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wlast,
+    m_axi_wuser,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bid,
+    m_axi_bresp,
+    m_axi_buser,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_arid,
+    m_axi_araddr,
+    m_axi_arlen,
+    m_axi_arsize,
+    m_axi_arburst,
+    m_axi_arlock,
+    m_axi_arcache,
+    m_axi_arprot,
+    m_axi_arregion,
+    m_axi_arqos,
+    m_axi_aruser,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rlast,
+    m_axi_ruser,
+    m_axi_rvalid,
+    m_axi_rready);
+  input aclk;
+  input aresetn;
+  input [0:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [7:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [0:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awqos;
+  input [0:0]s_axi_awuser;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [0:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wlast;
+  input [0:0]s_axi_wuser;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [0:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_buser;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [0:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [7:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [0:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arqos;
+  input [0:0]s_axi_aruser;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rlast;
+  output [0:0]s_axi_ruser;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [1:0]m_axi_awid;
+  output [63:0]m_axi_awaddr;
+  output [15:0]m_axi_awlen;
+  output [5:0]m_axi_awsize;
+  output [3:0]m_axi_awburst;
+  output [1:0]m_axi_awlock;
+  output [7:0]m_axi_awcache;
+  output [5:0]m_axi_awprot;
+  output [7:0]m_axi_awregion;
+  output [7:0]m_axi_awqos;
+  output [1:0]m_axi_awuser;
+  output [1:0]m_axi_awvalid;
+  input [1:0]m_axi_awready;
+  output [1:0]m_axi_wid;
+  output [63:0]m_axi_wdata;
+  output [7:0]m_axi_wstrb;
+  output [1:0]m_axi_wlast;
+  output [1:0]m_axi_wuser;
+  output [1:0]m_axi_wvalid;
+  input [1:0]m_axi_wready;
+  input [1:0]m_axi_bid;
+  input [3:0]m_axi_bresp;
+  input [1:0]m_axi_buser;
+  input [1:0]m_axi_bvalid;
+  output [1:0]m_axi_bready;
+  output [1:0]m_axi_arid;
+  output [63:0]m_axi_araddr;
+  output [15:0]m_axi_arlen;
+  output [5:0]m_axi_arsize;
+  output [3:0]m_axi_arburst;
+  output [1:0]m_axi_arlock;
+  output [7:0]m_axi_arcache;
+  output [5:0]m_axi_arprot;
+  output [7:0]m_axi_arregion;
+  output [7:0]m_axi_arqos;
+  output [1:0]m_axi_aruser;
+  output [1:0]m_axi_arvalid;
+  input [1:0]m_axi_arready;
+  input [1:0]m_axi_rid;
+  input [63:0]m_axi_rdata;
+  input [3:0]m_axi_rresp;
+  input [1:0]m_axi_rlast;
+  input [1:0]m_axi_ruser;
+  input [1:0]m_axi_rvalid;
+  output [1:0]m_axi_rready;
+
+  wire \\<const0> ;
+  wire aclk;
+  wire aresetn;
+  wire [15:0]\\^m_axi_araddr ;
+  wire [2:0]\\^m_axi_arprot ;
+  wire [1:0]m_axi_arready;
+  wire [1:0]m_axi_arvalid;
+  wire [63:48]\\^m_axi_awaddr ;
+  wire [1:0]m_axi_awready;
+  wire [1:0]m_axi_awvalid;
+  wire [1:0]m_axi_bready;
+  wire [3:0]m_axi_bresp;
+  wire [1:0]m_axi_bvalid;
+  wire [63:0]m_axi_rdata;
+  wire [1:0]m_axi_rready;
+  wire [3:0]m_axi_rresp;
+  wire [1:0]m_axi_rvalid;
+  wire [1:0]m_axi_wready;
+  wire [1:0]m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+
+  assign m_axi_araddr[63:48] = \\^m_axi_awaddr [63:48];
+  assign m_axi_araddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[31:16] = \\^m_axi_awaddr [63:48];
+  assign m_axi_araddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_arburst[3] = \\<const0> ;
+  assign m_axi_arburst[2] = \\<const0> ;
+  assign m_axi_arburst[1] = \\<const0> ;
+  assign m_axi_arburst[0] = \\<const0> ;
+  assign m_axi_arcache[7] = \\<const0> ;
+  assign m_axi_arcache[6] = \\<const0> ;
+  assign m_axi_arcache[5] = \\<const0> ;
+  assign m_axi_arcache[4] = \\<const0> ;
+  assign m_axi_arcache[3] = \\<const0> ;
+  assign m_axi_arcache[2] = \\<const0> ;
+  assign m_axi_arcache[1] = \\<const0> ;
+  assign m_axi_arcache[0] = \\<const0> ;
+  assign m_axi_arid[1] = \\<const0> ;
+  assign m_axi_arid[0] = \\<const0> ;
+  assign m_axi_arlen[15] = \\<const0> ;
+  assign m_axi_arlen[14] = \\<const0> ;
+  assign m_axi_arlen[13] = \\<const0> ;
+  assign m_axi_arlen[12] = \\<const0> ;
+  assign m_axi_arlen[11] = \\<const0> ;
+  assign m_axi_arlen[10] = \\<const0> ;
+  assign m_axi_arlen[9] = \\<const0> ;
+  assign m_axi_arlen[8] = \\<const0> ;
+  assign m_axi_arlen[7] = \\<const0> ;
+  assign m_axi_arlen[6] = \\<const0> ;
+  assign m_axi_arlen[5] = \\<const0> ;
+  assign m_axi_arlen[4] = \\<const0> ;
+  assign m_axi_arlen[3] = \\<const0> ;
+  assign m_axi_arlen[2] = \\<const0> ;
+  assign m_axi_arlen[1] = \\<const0> ;
+  assign m_axi_arlen[0] = \\<const0> ;
+  assign m_axi_arlock[1] = \\<const0> ;
+  assign m_axi_arlock[0] = \\<const0> ;
+  assign m_axi_arprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_arqos[7] = \\<const0> ;
+  assign m_axi_arqos[6] = \\<const0> ;
+  assign m_axi_arqos[5] = \\<const0> ;
+  assign m_axi_arqos[4] = \\<const0> ;
+  assign m_axi_arqos[3] = \\<const0> ;
+  assign m_axi_arqos[2] = \\<const0> ;
+  assign m_axi_arqos[1] = \\<const0> ;
+  assign m_axi_arqos[0] = \\<const0> ;
+  assign m_axi_arregion[7] = \\<const0> ;
+  assign m_axi_arregion[6] = \\<const0> ;
+  assign m_axi_arregion[5] = \\<const0> ;
+  assign m_axi_arregion[4] = \\<const0> ;
+  assign m_axi_arregion[3] = \\<const0> ;
+  assign m_axi_arregion[2] = \\<const0> ;
+  assign m_axi_arregion[1] = \\<const0> ;
+  assign m_axi_arregion[0] = \\<const0> ;
+  assign m_axi_arsize[5] = \\<const0> ;
+  assign m_axi_arsize[4] = \\<const0> ;
+  assign m_axi_arsize[3] = \\<const0> ;
+  assign m_axi_arsize[2] = \\<const0> ;
+  assign m_axi_arsize[1] = \\<const0> ;
+  assign m_axi_arsize[0] = \\<const0> ;
+  assign m_axi_aruser[1] = \\<const0> ;
+  assign m_axi_aruser[0] = \\<const0> ;
+  assign m_axi_awaddr[63:48] = \\^m_axi_awaddr [63:48];
+  assign m_axi_awaddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[31:16] = \\^m_axi_awaddr [63:48];
+  assign m_axi_awaddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_awburst[3] = \\<const0> ;
+  assign m_axi_awburst[2] = \\<const0> ;
+  assign m_axi_awburst[1] = \\<const0> ;
+  assign m_axi_awburst[0] = \\<const0> ;
+  assign m_axi_awcache[7] = \\<const0> ;
+  assign m_axi_awcache[6] = \\<const0> ;
+  assign m_axi_awcache[5] = \\<const0> ;
+  assign m_axi_awcache[4] = \\<const0> ;
+  assign m_axi_awcache[3] = \\<const0> ;
+  assign m_axi_awcache[2] = \\<const0> ;
+  assign m_axi_awcache[1] = \\<const0> ;
+  assign m_axi_awcache[0] = \\<const0> ;
+  assign m_axi_awid[1] = \\<const0> ;
+  assign m_axi_awid[0] = \\<const0> ;
+  assign m_axi_awlen[15] = \\<const0> ;
+  assign m_axi_awlen[14] = \\<const0> ;
+  assign m_axi_awlen[13] = \\<const0> ;
+  assign m_axi_awlen[12] = \\<const0> ;
+  assign m_axi_awlen[11] = \\<const0> ;
+  assign m_axi_awlen[10] = \\<const0> ;
+  assign m_axi_awlen[9] = \\<const0> ;
+  assign m_axi_awlen[8] = \\<const0> ;
+  assign m_axi_awlen[7] = \\<const0> ;
+  assign m_axi_awlen[6] = \\<const0> ;
+  assign m_axi_awlen[5] = \\<const0> ;
+  assign m_axi_awlen[4] = \\<const0> ;
+  assign m_axi_awlen[3] = \\<const0> ;
+  assign m_axi_awlen[2] = \\<const0> ;
+  assign m_axi_awlen[1] = \\<const0> ;
+  assign m_axi_awlen[0] = \\<const0> ;
+  assign m_axi_awlock[1] = \\<const0> ;
+  assign m_axi_awlock[0] = \\<const0> ;
+  assign m_axi_awprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_awqos[7] = \\<const0> ;
+  assign m_axi_awqos[6] = \\<const0> ;
+  assign m_axi_awqos[5] = \\<const0> ;
+  assign m_axi_awqos[4] = \\<const0> ;
+  assign m_axi_awqos[3] = \\<const0> ;
+  assign m_axi_awqos[2] = \\<const0> ;
+  assign m_axi_awqos[1] = \\<const0> ;
+  assign m_axi_awqos[0] = \\<const0> ;
+  assign m_axi_awregion[7] = \\<const0> ;
+  assign m_axi_awregion[6] = \\<const0> ;
+  assign m_axi_awregion[5] = \\<const0> ;
+  assign m_axi_awregion[4] = \\<const0> ;
+  assign m_axi_awregion[3] = \\<const0> ;
+  assign m_axi_awregion[2] = \\<const0> ;
+  assign m_axi_awregion[1] = \\<const0> ;
+  assign m_axi_awregion[0] = \\<const0> ;
+  assign m_axi_awsize[5] = \\<const0> ;
+  assign m_axi_awsize[4] = \\<const0> ;
+  assign m_axi_awsize[3] = \\<const0> ;
+  assign m_axi_awsize[2] = \\<const0> ;
+  assign m_axi_awsize[1] = \\<const0> ;
+  assign m_axi_awsize[0] = \\<const0> ;
+  assign m_axi_awuser[1] = \\<const0> ;
+  assign m_axi_awuser[0] = \\<const0> ;
+  assign m_axi_wdata[63:32] = s_axi_wdata;
+  assign m_axi_wdata[31:0] = s_axi_wdata;
+  assign m_axi_wid[1] = \\<const0> ;
+  assign m_axi_wid[0] = \\<const0> ;
+  assign m_axi_wlast[1] = \\<const0> ;
+  assign m_axi_wlast[0] = \\<const0> ;
+  assign m_axi_wstrb[7:4] = s_axi_wstrb;
+  assign m_axi_wstrb[3:0] = s_axi_wstrb;
+  assign m_axi_wuser[1] = \\<const0> ;
+  assign m_axi_wuser[0] = \\<const0> ;
+  assign s_axi_bid[0] = \\<const0> ;
+  assign s_axi_buser[0] = \\<const0> ;
+  assign s_axi_rid[0] = \\<const0> ;
+  assign s_axi_rlast[0] = \\<const0> ;
+  assign s_axi_ruser[0] = \\<const0> ;
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd \\gen_sasd.crossbar_sasd_0 
+       (.Q({\\^m_axi_arprot ,\\^m_axi_awaddr ,\\^m_axi_araddr }),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd
+   (Q,
+    \\s_axi_rdata[31] ,
+    s_axi_bvalid,
+    m_axi_bready,
+    s_axi_wready,
+    m_axi_wvalid,
+    m_axi_awvalid,
+    m_axi_arvalid,
+    s_axi_bresp,
+    s_axi_awready,
+    s_axi_arready,
+    s_axi_rvalid,
+    m_axi_rready,
+    m_axi_arready,
+    aresetn,
+    aclk,
+    s_axi_bready,
+    s_axi_wvalid,
+    s_axi_rready,
+    m_axi_awready,
+    m_axi_bvalid,
+    m_axi_wready,
+    m_axi_rvalid,
+    m_axi_bresp,
+    m_axi_rresp,
+    m_axi_rdata,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_awvalid);
+  output [34:0]Q;
+  output [33:0]\\s_axi_rdata[31] ;
+  output [0:0]s_axi_bvalid;
+  output [1:0]m_axi_bready;
+  output [0:0]s_axi_wready;
+  output [1:0]m_axi_wvalid;
+  output [1:0]m_axi_awvalid;
+  output [1:0]m_axi_arvalid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rvalid;
+  output [1:0]m_axi_rready;
+  input [1:0]m_axi_arready;
+  input aresetn;
+  input aclk;
+  input [0:0]s_axi_bready;
+  input [0:0]s_axi_wvalid;
+  input [0:0]s_axi_rready;
+  input [1:0]m_axi_awready;
+  input [1:0]m_axi_bvalid;
+  input [1:0]m_axi_wready;
+  input [1:0]m_axi_rvalid;
+  input [3:0]m_axi_bresp;
+  input [3:0]m_axi_rresp;
+  input [63:0]m_axi_rdata;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input [0:0]s_axi_awvalid;
+
+  wire [34:0]Q;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire addr_arbiter_inst_n_4;
+  wire addr_arbiter_inst_n_43;
+  wire addr_arbiter_inst_n_47;
+  wire addr_arbiter_inst_n_48;
+  wire addr_arbiter_inst_n_5;
+  wire addr_arbiter_inst_n_52;
+  wire addr_arbiter_inst_n_55;
+  wire addr_arbiter_inst_n_58;
+  wire addr_arbiter_inst_n_60;
+  wire addr_arbiter_inst_n_61;
+  wire any_error;
+  wire aresetn;
+  wire aresetn_d;
+  wire \\gen_decerr.decerr_slave_inst_n_3 ;
+  wire \\gen_decerr.decerr_slave_inst_n_4 ;
+  wire \\gen_decerr.decerr_slave_inst_n_5 ;
+  wire \\gen_decerr.decerr_slave_inst_n_7 ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc[0]_i_1_n_0 ;
+  wire [2:0]m_atarget_hot;
+  wire [0:0]m_atarget_hot0;
+  wire [1:0]m_axi_arready;
+  wire [1:0]m_axi_arvalid;
+  wire [1:0]m_axi_awready;
+  wire [1:0]m_axi_awvalid;
+  wire [1:0]m_axi_bready;
+  wire [3:0]m_axi_bresp;
+  wire [1:0]m_axi_bvalid;
+  wire [63:0]m_axi_rdata;
+  wire [1:0]m_axi_rready;
+  wire [3:0]m_axi_rresp;
+  wire [1:0]m_axi_rvalid;
+  wire [1:0]m_axi_wready;
+  wire [1:0]m_axi_wvalid;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire [0:0]m_ready_d0_0;
+  wire [2:0]m_ready_d_1;
+  wire m_valid_i;
+  wire [2:2]mi_arready;
+  wire [2:2]mi_rvalid;
+  wire [2:2]mi_wready;
+  wire p_1_in;
+  wire reg_slice_r_n_2;
+  wire reg_slice_r_n_3;
+  wire reg_slice_r_n_39;
+  wire reset;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire splitter_aw_n_0;
+  wire splitter_aw_n_4;
+  wire splitter_aw_n_5;
+  wire sr_rvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd addr_arbiter_inst
+       (.D({addr_arbiter_inst_n_4,addr_arbiter_inst_n_5,m_atarget_hot0}),
+        .E(p_1_in),
+        .Q(Q),
+        .SR(reset),
+        .aa_grant_any(aa_grant_any),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aclk(aclk),
+        .any_error(any_error),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_awready_i_reg (\\gen_decerr.decerr_slave_inst_n_7 ),
+        .\\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_47),
+        .\\gen_axilite.s_axi_bvalid_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .m_atarget_enc(m_atarget_enc),
+        .\\m_atarget_enc_reg[0] (reg_slice_r_n_3),
+        .\\m_atarget_hot_reg[1] (m_atarget_hot[1:0]),
+        .m_axi_arready(m_axi_arready[1]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awready(m_axi_awready[1]),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_wvalid(m_axi_wvalid),
+        .m_ready_d(m_ready_d_1),
+        .m_ready_d0(m_ready_d0),
+        .m_ready_d_0(m_ready_d),
+        .\\m_ready_d_reg[0] (addr_arbiter_inst_n_61),
+        .\\m_ready_d_reg[1] (addr_arbiter_inst_n_52),
+        .\\m_ready_d_reg[1]_0 (addr_arbiter_inst_n_60),
+        .\\m_ready_d_reg[1]_1 (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\m_ready_d_reg[2] (addr_arbiter_inst_n_43),
+        .\\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_48),
+        .\\m_ready_d_reg[2]_1 (addr_arbiter_inst_n_55),
+        .\\m_ready_d_reg[2]_2 (splitter_aw_n_0),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg(addr_arbiter_inst_n_58),
+        .mi_arready(mi_arready),
+        .mi_rvalid(mi_rvalid),
+        .mi_wready(mi_wready),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid),
+        .sr_rvalid(sr_rvalid));
+  FDRE #(
+    .INIT(1\'b0)) 
+    aresetn_d_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(aresetn),
+        .Q(aresetn_d),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave \\gen_decerr.decerr_slave_inst 
+       (.Q(m_atarget_hot[2]),
+        .SR(reset),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_55),
+        .\\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_47),
+        .\\gen_no_arbiter.m_valid_i_reg (addr_arbiter_inst_n_61),
+        .m_atarget_enc(m_atarget_enc),
+        .\\m_atarget_enc_reg[0] (splitter_aw_n_5),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_ready_d(m_ready_d_1[1:0]),
+        .m_ready_d0(m_ready_d0),
+        .m_ready_d_0(m_ready_d[1]),
+        .\\m_ready_d_reg[0] (addr_arbiter_inst_n_48),
+        .\\m_ready_d_reg[1] (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\m_ready_d_reg[1]_0 (\\gen_decerr.decerr_slave_inst_n_7 ),
+        .\\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_52),
+        .\\m_ready_d_reg[1]_2 (splitter_aw_n_4),
+        .\\m_ready_d_reg[2] (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\m_ready_d_reg[2]_0 (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\m_ready_d_reg[2]_1 (splitter_aw_n_0),
+        .mi_arready(mi_arready),
+        .mi_rvalid(mi_rvalid),
+        .mi_wready(mi_wready),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_wvalid(s_axi_wvalid));
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\m_atarget_enc[0]_i_1 
+       (.I0(Q[16]),
+        .I1(aresetn_d),
+        .I2(any_error),
+        .O(\\m_atarget_enc[0]_i_1_n_0 ));
+  FDRE \\m_atarget_enc_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_enc[0]_i_1_n_0 ),
+        .Q(m_atarget_enc[0]),
+        .R(1\'b0));
+  FDRE \\m_atarget_enc_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(any_error),
+        .Q(m_atarget_enc[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_atarget_hot0),
+        .Q(m_atarget_hot[0]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_5),
+        .Q(m_atarget_hot[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_4),
+        .Q(m_atarget_hot[2]),
+        .R(reset));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice reg_slice_r
+       (.E(p_1_in),
+        .Q({\\s_axi_rdata[31] ,reg_slice_r_n_39}),
+        .SR(reset),
+        .aa_grant_any(aa_grant_any),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_arready_i_reg (addr_arbiter_inst_n_60),
+        .m_atarget_enc(m_atarget_enc),
+        .\\m_atarget_enc_reg[1] (addr_arbiter_inst_n_58),
+        .\\m_atarget_hot_reg[1] (m_atarget_hot[1:0]),
+        .m_axi_arready(m_axi_arready[0]),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_ready_d(m_ready_d),
+        .m_ready_d0(m_ready_d0_0),
+        .\\m_ready_d_reg[0] (reg_slice_r_n_2),
+        .\\m_ready_d_reg[0]_0 (reg_slice_r_n_3),
+        .m_valid_i(m_valid_i),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .sr_rvalid(sr_rvalid));
+  LUT4 #(
+    .INIT(16\'h0CFA)) 
+    \\s_axi_bresp[0]_INST_0 
+       (.I0(m_axi_bresp[0]),
+        .I1(m_axi_bresp[2]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_atarget_enc[0]),
+        .O(s_axi_bresp[0]));
+  LUT4 #(
+    .INIT(16\'h0CFA)) 
+    \\s_axi_bresp[1]_INST_0 
+       (.I0(m_axi_bresp[1]),
+        .I1(m_axi_bresp[3]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_atarget_enc[0]),
+        .O(s_axi_bresp[1]));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0 splitter_ar
+       (.Q(reg_slice_r_n_39),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .aresetn_d_reg(reg_slice_r_n_2),
+        .\\gen_axilite.s_axi_arready_i_reg (addr_arbiter_inst_n_60),
+        .\\gen_no_arbiter.m_valid_i_reg (addr_arbiter_inst_n_61),
+        .m_atarget_enc(m_atarget_enc),
+        .m_axi_arready(m_axi_arready[0]),
+        .m_ready_d(m_ready_d),
+        .m_ready_d0(m_ready_d0_0),
+        .s_axi_rready(s_axi_rready),
+        .sr_rvalid(sr_rvalid));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter splitter_aw
+       (.Q(m_atarget_hot[2]),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_awready_i_reg (\\gen_decerr.decerr_slave_inst_n_7 ),
+        .\\gen_axilite.s_axi_bvalid_i_reg (splitter_aw_n_4),
+        .\\gen_axilite.s_axi_bvalid_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .m_atarget_enc(m_atarget_enc),
+        .\\m_atarget_enc_reg[1] (addr_arbiter_inst_n_43),
+        .m_axi_awready(m_axi_awready[0]),
+        .m_ready_d(m_ready_d_1),
+        .\\m_ready_d_reg[0]_0 (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\m_ready_d_reg[1]_0 (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\m_ready_d_reg[2]_0 (splitter_aw_n_0),
+        .\\m_ready_d_reg[2]_1 (splitter_aw_n_5),
+        .m_valid_i(m_valid_i),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave
+   (mi_wready,
+    mi_rvalid,
+    mi_arready,
+    \\m_ready_d_reg[1] ,
+    \\m_ready_d_reg[2] ,
+    \\m_ready_d_reg[2]_0 ,
+    m_ready_d0,
+    \\m_ready_d_reg[1]_0 ,
+    SR,
+    aclk,
+    s_axi_bready,
+    m_ready_d,
+    \\m_ready_d_reg[2]_1 ,
+    m_axi_bvalid,
+    \\m_atarget_enc_reg[0] ,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    m_atarget_enc,
+    \\m_ready_d_reg[0] ,
+    m_axi_wready,
+    s_axi_wvalid,
+    \\m_ready_d_reg[1]_1 ,
+    Q,
+    \\gen_no_arbiter.grant_rnw_reg_0 ,
+    \\m_ready_d_reg[1]_2 ,
+    m_ready_d_0,
+    \\gen_no_arbiter.m_valid_i_reg ,
+    aa_rready,
+    aresetn_d);
+  output [0:0]mi_wready;
+  output [0:0]mi_rvalid;
+  output [0:0]mi_arready;
+  output \\m_ready_d_reg[1] ;
+  output \\m_ready_d_reg[2] ;
+  output \\m_ready_d_reg[2]_0 ;
+  output [0:0]m_ready_d0;
+  output \\m_ready_d_reg[1]_0 ;
+  input [0:0]SR;
+  input aclk;
+  input [0:0]s_axi_bready;
+  input [1:0]m_ready_d;
+  input \\m_ready_d_reg[2]_1 ;
+  input [1:0]m_axi_bvalid;
+  input \\m_atarget_enc_reg[0] ;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input [1:0]m_atarget_enc;
+  input \\m_ready_d_reg[0] ;
+  input [1:0]m_axi_wready;
+  input [0:0]s_axi_wvalid;
+  input \\m_ready_d_reg[1]_1 ;
+  input [0:0]Q;
+  input \\gen_no_arbiter.grant_rnw_reg_0 ;
+  input \\m_ready_d_reg[1]_2 ;
+  input [0:0]m_ready_d_0;
+  input \\gen_no_arbiter.m_valid_i_reg ;
+  input aa_rready;
+  input aresetn_d;
+
+  wire [0:0]Q;
+  wire [0:0]SR;
+  wire aa_rready;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_awready_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_bvalid_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_4_n_0 ;
+  wire \\gen_no_arbiter.m_valid_i_reg ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc_reg[0] ;
+  wire [1:0]m_axi_bvalid;
+  wire [1:0]m_axi_wready;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire \\m_ready_d[2]_i_4_n_0 ;
+  wire [0:0]m_ready_d_0;
+  wire \\m_ready_d_reg[0] ;
+  wire \\m_ready_d_reg[1] ;
+  wire \\m_ready_d_reg[1]_0 ;
+  wire \\m_ready_d_reg[1]_1 ;
+  wire \\m_ready_d_reg[1]_2 ;
+  wire \\m_ready_d_reg[2] ;
+  wire \\m_ready_d_reg[2]_0 ;
+  wire \\m_ready_d_reg[2]_1 ;
+  wire [0:0]mi_arready;
+  wire [2:2]mi_bvalid;
+  wire [0:0]mi_rvalid;
+  wire [0:0]mi_wready;
+  wire [0:0]s_axi_bready;
+  wire [0:0]s_axi_wvalid;
+
+  LUT6 #(
+    .INIT(64\'hAAAAA8AA0000AAAA)) 
+    \\gen_axilite.s_axi_arready_i_i_1 
+       (.I0(aresetn_d),
+        .I1(\\gen_no_arbiter.m_valid_i_reg ),
+        .I2(m_ready_d_0),
+        .I3(Q),
+        .I4(mi_rvalid),
+        .I5(mi_arready),
+        .O(\\gen_axilite.s_axi_arready_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_arready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_arready_i_i_1_n_0 ),
+        .Q(mi_arready),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT3 #(
+    .INIT(8\'hE1)) 
+    \\gen_axilite.s_axi_awready_i_i_1 
+       (.I0(\\m_ready_d_reg[1]_2 ),
+        .I1(mi_bvalid),
+        .I2(mi_wready),
+        .O(\\gen_axilite.s_axi_awready_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_awready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_awready_i_i_1_n_0 ),
+        .Q(mi_wready),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT5 #(
+    .INIT(32\'h77770F00)) 
+    \\gen_axilite.s_axi_bvalid_i_i_1 
+       (.I0(Q),
+        .I1(\\gen_no_arbiter.grant_rnw_reg_0 ),
+        .I2(\\m_ready_d_reg[1]_2 ),
+        .I3(mi_wready),
+        .I4(mi_bvalid),
+        .O(\\gen_axilite.s_axi_bvalid_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_bvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_bvalid_i_i_1_n_0 ),
+        .Q(mi_bvalid),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h00FF0202FFFF0000)) 
+    \\gen_axilite.s_axi_rvalid_i_i_1 
+       (.I0(mi_arready),
+        .I1(m_ready_d_0),
+        .I2(\\gen_no_arbiter.m_valid_i_reg ),
+        .I3(aa_rready),
+        .I4(mi_rvalid),
+        .I5(Q),
+        .O(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_rvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
+        .Q(mi_rvalid),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'hFF00FF54FF00FF00)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_3 
+       (.I0(\\gen_no_arbiter.m_grant_hot_i[0]_i_4_n_0 ),
+        .I1(m_axi_bvalid[0]),
+        .I2(\\m_atarget_enc_reg[0] ),
+        .I3(m_ready_d[0]),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(s_axi_bready),
+        .O(m_ready_d0));
+  LUT4 #(
+    .INIT(16\'hDD0C)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_4 
+       (.I0(m_axi_bvalid[1]),
+        .I1(m_atarget_enc[1]),
+        .I2(mi_bvalid),
+        .I3(m_atarget_enc[0]),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_4_n_0 ));
+  LUT5 #(
+    .INIT(32\'h000000F2)) 
+    \\m_ready_d[1]_i_2 
+       (.I0(s_axi_bready),
+        .I1(\\m_ready_d_reg[2] ),
+        .I2(m_ready_d[0]),
+        .I3(\\m_ready_d_reg[2]_0 ),
+        .I4(\\m_ready_d_reg[2]_1 ),
+        .O(\\m_ready_d_reg[1] ));
+  LUT6 #(
+    .INIT(64\'h00FF00AB00FF00FF)) 
+    \\m_ready_d[2]_i_2 
+       (.I0(\\m_ready_d[2]_i_4_n_0 ),
+        .I1(m_axi_wready[0]),
+        .I2(\\m_atarget_enc_reg[0] ),
+        .I3(m_ready_d[1]),
+        .I4(\\gen_no_arbiter.grant_rnw_reg ),
+        .I5(s_axi_wvalid),
+        .O(\\m_ready_d_reg[2]_0 ));
+  LUT4 #(
+    .INIT(16\'hAF22)) 
+    \\m_ready_d[2]_i_4 
+       (.I0(m_atarget_enc[1]),
+        .I1(mi_wready),
+        .I2(m_axi_wready[1]),
+        .I3(m_atarget_enc[0]),
+        .O(\\m_ready_d[2]_i_4_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFF33550F)) 
+    \\s_axi_bvalid[0]_INST_0_i_1 
+       (.I0(mi_bvalid),
+        .I1(m_axi_bvalid[1]),
+        .I2(m_axi_bvalid[0]),
+        .I3(m_atarget_enc[1]),
+        .I4(m_atarget_enc[0]),
+        .I5(\\m_ready_d_reg[0] ),
+        .O(\\m_ready_d_reg[2] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFF55330F)) 
+    \\s_axi_wready[0]_INST_0_i_1 
+       (.I0(m_axi_wready[1]),
+        .I1(mi_wready),
+        .I2(m_axi_wready[0]),
+        .I3(m_atarget_enc[1]),
+        .I4(m_atarget_enc[0]),
+        .I5(\\m_ready_d_reg[1]_1 ),
+        .O(\\m_ready_d_reg[1]_0 ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter
+   (\\m_ready_d_reg[2]_0 ,
+    m_ready_d,
+    \\gen_axilite.s_axi_bvalid_i_reg ,
+    \\m_ready_d_reg[2]_1 ,
+    \\m_atarget_enc_reg[1] ,
+    m_axi_awready,
+    m_atarget_enc,
+    s_axi_wvalid,
+    Q,
+    m_valid_i,
+    aa_grant_rnw,
+    aresetn_d,
+    s_axi_bready,
+    \\gen_axilite.s_axi_bvalid_i_reg_0 ,
+    \\m_ready_d_reg[1]_0 ,
+    \\gen_axilite.s_axi_awready_i_reg ,
+    \\m_ready_d_reg[0]_0 ,
+    aclk);
+  output \\m_ready_d_reg[2]_0 ;
+  output [2:0]m_ready_d;
+  output \\gen_axilite.s_axi_bvalid_i_reg ;
+  output \\m_ready_d_reg[2]_1 ;
+  input \\m_atarget_enc_reg[1] ;
+  input [0:0]m_axi_awready;
+  input [1:0]m_atarget_enc;
+  input [0:0]s_axi_wvalid;
+  input [0:0]Q;
+  input m_valid_i;
+  input aa_grant_rnw;
+  input aresetn_d;
+  input [0:0]s_axi_bready;
+  input \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  input \\m_ready_d_reg[1]_0 ;
+  input \\gen_axilite.s_axi_awready_i_reg ;
+  input \\m_ready_d_reg[0]_0 ;
+  input aclk;
+
+  wire [0:0]Q;
+  wire aa_grant_rnw;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_awready_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc_reg[1] ;
+  wire [0:0]m_axi_awready;
+  wire [2:0]m_ready_d;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire \\m_ready_d[2]_i_1_n_0 ;
+  wire \\m_ready_d_reg[0]_0 ;
+  wire \\m_ready_d_reg[1]_0 ;
+  wire \\m_ready_d_reg[2]_0 ;
+  wire \\m_ready_d_reg[2]_1 ;
+  wire m_valid_i;
+  wire [0:0]s_axi_bready;
+  wire [0:0]s_axi_wvalid;
+
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFFDFFFFF)) 
+    \\gen_axilite.s_axi_bvalid_i_i_3 
+       (.I0(s_axi_wvalid),
+        .I1(m_ready_d[1]),
+        .I2(Q),
+        .I3(m_ready_d[2]),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg ));
+  LUT5 #(
+    .INIT(32\'h0000F200)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(s_axi_bready),
+        .I1(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .I2(m_ready_d[0]),
+        .I3(aresetn_d),
+        .I4(\\m_ready_d_reg[0]_0 ),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0000BA00)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(m_ready_d[1]),
+        .I1(\\gen_axilite.s_axi_awready_i_reg ),
+        .I2(s_axi_wvalid),
+        .I3(aresetn_d),
+        .I4(\\m_ready_d_reg[0]_0 ),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h00000000AAAA00A2)) 
+    \\m_ready_d[2]_i_1 
+       (.I0(aresetn_d),
+        .I1(s_axi_bready),
+        .I2(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .I3(m_ready_d[0]),
+        .I4(\\m_ready_d_reg[1]_0 ),
+        .I5(\\m_ready_d_reg[2]_0 ),
+        .O(\\m_ready_d[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT5 #(
+    .INIT(32\'h44444445)) 
+    \\m_ready_d[2]_i_3 
+       (.I0(m_ready_d[2]),
+        .I1(\\m_atarget_enc_reg[1] ),
+        .I2(m_axi_awready),
+        .I3(m_atarget_enc[1]),
+        .I4(m_atarget_enc[0]),
+        .O(\\m_ready_d_reg[2]_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\m_ready_d[2]_i_5 
+       (.I0(m_atarget_enc[0]),
+        .I1(m_atarget_enc[1]),
+        .O(\\m_ready_d_reg[2]_1 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[2]_i_1_n_0 ),
+        .Q(m_ready_d[2]),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_crossbar_v2_1_12_splitter"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0
+   (m_ready_d,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    m_axi_arready,
+    m_atarget_enc,
+    aresetn_d,
+    m_ready_d0,
+    \\gen_no_arbiter.m_valid_i_reg ,
+    s_axi_rready,
+    sr_rvalid,
+    Q,
+    aresetn_d_reg,
+    aclk);
+  output [1:0]m_ready_d;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input [0:0]m_axi_arready;
+  input [1:0]m_atarget_enc;
+  input aresetn_d;
+  input [0:0]m_ready_d0;
+  input \\gen_no_arbiter.m_valid_i_reg ;
+  input [0:0]s_axi_rready;
+  input sr_rvalid;
+  input [0:0]Q;
+  input aresetn_d_reg;
+  input aclk;
+
+  wire [0:0]Q;
+  wire aclk;
+  wire aresetn_d;
+  wire aresetn_d_reg;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire \\gen_no_arbiter.m_valid_i_reg ;
+  wire [1:0]m_atarget_enc;
+  wire [0:0]m_axi_arready;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_3_n_0 ;
+  wire [0:0]s_axi_rready;
+  wire sr_rvalid;
+
+  LUT6 #(
+    .INIT(64\'h00000000BAAAAAAA)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(m_ready_d[0]),
+        .I1(\\gen_no_arbiter.m_valid_i_reg ),
+        .I2(s_axi_rready),
+        .I3(sr_rvalid),
+        .I4(Q),
+        .I5(aresetn_d_reg),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  LUT3 #(
+    .INIT(8\'h02)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\m_ready_d[1]_i_3_n_0 ),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h44444445)) 
+    \\m_ready_d[1]_i_3 
+       (.I0(m_ready_d[1]),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(m_axi_arready),
+        .I3(m_atarget_enc[1]),
+        .I4(m_atarget_enc[0]),
+        .O(\\m_ready_d[1]_i_3_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice
+   (sr_rvalid,
+    aa_rready,
+    \\m_ready_d_reg[0] ,
+    \\m_ready_d_reg[0]_0 ,
+    m_ready_d0,
+    'b'Q,
+    s_axi_rvalid,
+    m_axi_rready,
+    aclk,
+    E,
+    aresetn_d,
+    m_axi_rvalid,
+    m_atarget_enc,
+    \\m_atarget_enc_reg[1] ,
+    m_axi_arready,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    m_ready_d,
+    s_axi_rready,
+    m_valid_i,
+    aa_grant_rnw,
+    m_axi_rresp,
+    m_axi_rdata,
+    aa_grant_any,
+    \\m_atarget_hot_reg[1] ,
+    SR);
+  output sr_rvalid;
+  output aa_rready;
+  output \\m_ready_d_reg[0] ;
+  output \\m_ready_d_reg[0]_0 ;
+  output [0:0]m_ready_d0;
+  output [34:0]Q;
+  output [0:0]s_axi_rvalid;
+  output [1:0]m_axi_rready;
+  input aclk;
+  input [0:0]E;
+  input aresetn_d;
+  input [1:0]m_axi_rvalid;
+  input [1:0]m_atarget_enc;
+  input \\m_atarget_enc_reg[1] ;
+  input [0:0]m_axi_arready;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input [1:0]m_ready_d;
+  input [0:0]s_axi_rready;
+  input m_valid_i;
+  input aa_grant_rnw;
+  input [3:0]m_axi_rresp;
+  input [63:0]m_axi_rdata;
+  input aa_grant_any;
+  input [1:0]\\m_atarget_hot_reg[1] ;
+  input [0:0]SR;
+
+  wire [0:0]E;
+  wire [34:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire aresetn_d;
+  wire \\aresetn_d_reg_n_0_[0] ;
+  wire \\aresetn_d_reg_n_0_[1] ;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc_reg[1] ;
+  wire [1:0]\\m_atarget_hot_reg[1] ;
+  wire [0:0]m_axi_arready;
+  wire [63:0]m_axi_rdata;
+  wire [1:0]m_axi_rready;
+  wire [3:0]m_axi_rresp;
+  wire [1:0]m_axi_rvalid;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire \\m_ready_d_reg[0] ;
+  wire \\m_ready_d_reg[0]_0 ;
+  wire m_valid_i;
+  wire m_valid_i_i_1_n_0;
+  wire m_valid_i_i_2_n_0;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire s_ready_i_i_1_n_0;
+  wire [34:0]skid_buffer;
+  wire \\skid_buffer[10]_i_1_n_0 ;
+  wire \\skid_buffer[11]_i_1_n_0 ;
+  wire \\skid_buffer[12]_i_1_n_0 ;
+  wire \\skid_buffer[13]_i_1_n_0 ;
+  wire \\skid_buffer[14]_i_1_n_0 ;
+  wire \\skid_buffer[15]_i_1_n_0 ;
+  wire \\skid_buffer[16]_i_1_n_0 ;
+  wire \\skid_buffer[17]_i_1_n_0 ;
+  wire \\skid_buffer[18]_i_1_n_0 ;
+  wire \\skid_buffer[19]_i_1_n_0 ;
+  wire \\skid_buffer[20]_i_1_n_0 ;
+  wire \\skid_buffer[21]_i_1_n_0 ;
+  wire \\skid_buffer[22]_i_1_n_0 ;
+  wire \\skid_buffer[23]_i_1_n_0 ;
+  wire \\skid_buffer[24]_i_1_n_0 ;
+  wire \\skid_buffer[25]_i_1_n_0 ;
+  wire \\skid_buffer[26]_i_1_n_0 ;
+  wire \\skid_buffer[27]_i_1_n_0 ;
+  wire \\skid_buffer[28]_i_1_n_0 ;
+  wire \\skid_buffer[29]_i_1_n_0 ;
+  wire \\skid_buffer[30]_i_1_n_0 ;
+  wire \\skid_buffer[31]_i_1_n_0 ;
+  wire \\skid_buffer[32]_i_1_n_0 ;
+  wire \\skid_buffer[33]_i_1_n_0 ;
+  wire \\skid_buffer[34]_i_1_n_0 ;
+  wire \\skid_buffer[3]_i_1_n_0 ;
+  wire \\skid_buffer[4]_i_1_n_0 ;
+  wire \\skid_buffer[5]_i_1_n_0 ;
+  wire \\skid_buffer[6]_i_1_n_0 ;
+  wire \\skid_buffer[7]_i_1_n_0 ;
+  wire \\skid_buffer[8]_i_1_n_0 ;
+  wire \\skid_buffer[9]_i_1_n_0 ;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire sr_rvalid;
+
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(1\'b1),
+        .Q(\\aresetn_d_reg_n_0_[0] ),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\aresetn_d_reg_n_0_[0] ),
+        .Q(\\aresetn_d_reg_n_0_[1] ),
+        .R(SR));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[0]_INST_0 
+       (.I0(aa_rready),
+        .I1(\\m_atarget_hot_reg[1] [0]),
+        .O(m_axi_rready[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[1]_INST_0 
+       (.I0(aa_rready),
+        .I1(\\m_atarget_hot_reg[1] [1]),
+        .O(m_axi_rready[1]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[10]_i_1 
+       (.I0(m_axi_rdata[39]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[7]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[10] ),
+        .O(skid_buffer[10]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[11]_i_1 
+       (.I0(m_axi_rdata[40]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[8]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[11] ),
+        .O(skid_buffer[11]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[12]_i_1 
+       (.I0(m_axi_rdata[41]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[9]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[12] ),
+        .O(skid_buffer[12]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[13]_i_1 
+       (.I0(m_axi_rdata[42]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[10]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[13] ),
+        .O(skid_buffer[13]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[14]_i_1 
+       (.I0(m_axi_rdata[43]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[11]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[14] ),
+        .O(skid_buffer[14]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[15]_i_1 
+       (.I0(m_axi_rdata[44]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[12]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[15] ),
+        .O(skid_buffer[15]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[16]_i_1 
+       (.I0(m_axi_rdata[45]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[13]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[16] ),
+        .O(skid_buffer[16]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[17]_i_1 
+       (.I0(m_axi_rdata[46]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[14]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[17] ),
+        .O(skid_buffer[17]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[18]_i_1 
+       (.I0(m_axi_rdata[47]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[15]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[18] ),
+        .O(skid_buffer[18]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[19]_i_1 
+       (.I0(m_axi_rdata[48]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[16]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[19] ),
+        .O(skid_buffer[19]));
+  LUT6 #(
+    .INIT(64\'h3300FCFCAAAAAAAA)) 
+    \\m_payload_i[1]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[1] ),
+        .I1(m_atarget_enc[1]),
+        .I2(m_axi_rresp[0]),
+        .I3(m_axi_rresp[2]),
+        .I4(m_atarget_enc[0]),
+        .I5(aa_rready),
+        .O(skid_buffer[1]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[20]_i_1 
+       (.I0(m_axi_rdata[49]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[17]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[20] ),
+        .O(skid_buffer[20]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[21]_i_1 
+       (.I0(m_axi_rdata[50]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[18]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[21] ),
+        .O(skid_buffer[21]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[22]_i_1 
+       (.I0(m_axi_rdata[51]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[19]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[22] ),
+        .O(skid_buffer[22]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[23]_i_1 
+       (.I0(m_axi_rdata[52]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[20]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[23] ),
+        .O(skid_buffer[23]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[24]_i_1 
+       (.I0(m_axi_rdata[53]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[21]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[24] ),
+        .O(skid_buffer[24]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[25]_i_1 
+       (.I0(m_axi_rdata[54]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[22]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[25] ),
+        .O(skid_buffer[25]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[26]_i_1 
+       (.I0(m_axi_rdata[55]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[23]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[26] ),
+        .O(skid_buffer[26]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[27]_i_1 
+       (.I0(m_axi_rdata[56]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[24]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[27] ),
+        .O(skid_buffer[27]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[28]_i_1 
+       (.I0(m_axi_rdata[57]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[25]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[28] ),
+        .O(skid_buffer[28]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[29]_i_1 
+       (.I0(m_axi_rdata[58]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[26]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[29] ),
+        .O(skid_buffer[29]));
+  LUT6 #(
+    .INIT(64\'h0FCFAAAA0FC0AAAA)) 
+    \\m_payload_i[2]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[2] ),
+        .I1(m_axi_rresp[3]),
+        .I2(m_atarget_enc[0]),
+        .I3(m_atarget_enc[1]),
+        .I4(aa_rready),
+        .I5(m_axi_rresp[1]),
+        .O(skid_buffer[2]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[30]_i_1 
+       (.I0(m_axi_rdata[59]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[27]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[30] ),
+        .O(skid_buffer[30]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[31]_i_1 
+       (.I0(m_axi_rdata[60]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[28]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[31] ),
+        .O(skid_buffer[31]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[32]_i_1 
+       (.I0(m_axi_rdata[61]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[29]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[32] ),
+        .O(skid_buffer[32]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[33]_i_1 
+       (.I0(m_axi_rdata[62]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[30]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[33] ),
+        .O(skid_buffer[33]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[34]_i_2 
+       (.I0(m_axi_rdata[63]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[31]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[34] ),
+        .O(skid_buffer[34]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[3]_i_1 
+       (.I0(m_axi_rdata[32]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[0]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[3] ),
+        .O(skid_buffer[3]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[4]_i_1 
+       (.I0(m_axi_rdata[33]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[1]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[4] ),
+        .O(skid_buffer[4]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[5]_i_1 
+       (.I0(m_axi_rdata[34]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[2]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[5] ),
+        .O(skid_buffer[5]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[6]_i_1 
+       (.I0(m_axi_rdata[35]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[3]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[6] ),
+        .O(skid_buffer[6]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[7]_i_1 
+       (.I0(m_axi_rdata[36]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[4]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[7] ),
+        .O(skid_buffer[7]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[8]_i_1 
+       (.I0(m_axi_rdata[37]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[5]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[8] ),
+        .O(skid_buffer[8]));
+  LUT6 #(
+    .INIT(64\'h0B08FFFF0B080000)) 
+    \\m_payload_i[9]_i_1 
+       (.I0(m_axi_rdata[38]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[6]),
+        .I4(aa_rready),
+        .I5(\\skid_buffer_reg_n_0_[9] ),
+        .O(skid_buffer[9]));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[0]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[10]),
+        .Q(Q[10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[11]),
+        .Q(Q[11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[12]),
+        .Q(Q[12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[13]),
+        .Q(Q[13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[14]),
+        .Q(Q[14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[15]),
+        .Q(Q[15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[16]),
+        .Q(Q[16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[17]),
+        .Q(Q[17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[18]),
+        .Q(Q[18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[19]),
+        .Q(Q[19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[1]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[20]),
+        .Q(Q[20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[21]),
+        .Q(Q[21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[22]),
+        .Q(Q[22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[23]),
+        .Q(Q[23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[24]),
+        .Q(Q[24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[25]),
+        .Q(Q[25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[26]),
+        .Q(Q[26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[27]),
+        .Q(Q[27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[28]),
+        .Q(Q[28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[29]),
+        .Q(Q[29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[2]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[30]),
+        .Q(Q[30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[31]),
+        .Q(Q[31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[32]),
+        .Q(Q[32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[33]),
+        .Q(Q[33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[34]),
+        .Q(Q[34]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[3]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[4]),
+        .Q(Q[4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[5]),
+        .Q(Q[5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[6]),
+        .Q(Q[6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[7]),
+        .Q(Q[7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[8]),
+        .Q(Q[8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[9]),
+        .Q(Q[9]),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_ready_d[0]_i_3 
+       (.I0(\\m_ready_d_reg[0]_0 ),
+        .I1(aresetn_d),
+        .O(\\m_ready_d_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAA0000AAA8)) 
+    \\m_ready_d[0]_i_4 
+       (.I0(m_ready_d0),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_arready),
+        .I4(\\gen_axilite.s_axi_arready_i_reg ),
+        .I5(m_ready_d[1]),
+        .O(\\m_ready_d_reg[0]_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF80000000)) 
+    \\m_ready_d[1]_i_2__0 
+       (.I0(Q[0]),
+        .I1(sr_rvalid),
+        .I2(s_axi_rready),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .I5(m_ready_d[0]),
+        .O(m_ready_d0));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'h2A)) 
+    m_valid_i_i_1
+       (.I0(\\aresetn_d_reg_n_0_[1] ),
+        .I1(E),
+        .I2(m_valid_i_i_2_n_0),
+        .O(m_valid_i_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hA020A02AAAAAAAAA)) 
+    m_valid_i_i_2
+       (.I0(aa_rready),
+        .I1(m_axi_rvalid[1]),
+        .I2(m_atarget_enc[0]),
+        .I3(m_atarget_enc[1]),
+        .I4(m_axi_rvalid[0]),
+        .I5(\\m_atarget_enc_reg[1] ),
+        .O(m_valid_i_i_2_n_0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i_i_1_n_0),
+        .Q(sr_rvalid),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_rvalid[0]_INST_0 
+       (.I0(sr_rvalid),
+        .I1(aa_grant_any),
+        .O(s_axi_rvalid));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'hA8)) 
+    s_ready_i_i_1
+       (.I0(\\aresetn_d_reg_n_0_[0] ),
+        .I1(E),
+        .I2(m_valid_i_i_2_n_0),
+        .O(s_ready_i_i_1_n_0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i_i_1_n_0),
+        .Q(aa_rready),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT4 #(
+    .INIT(16\'h7F70)) 
+    \\skid_buffer[0]_i_1 
+       (.I0(m_atarget_enc[0]),
+        .I1(m_atarget_enc[1]),
+        .I2(aa_rready),
+        .I3(\\skid_buffer_reg_n_0_[0] ),
+        .O(skid_buffer[0]));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[10]_i_1 
+       (.I0(m_axi_rdata[39]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[7]),
+        .O(\\skid_buffer[10]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[11]_i_1 
+       (.I0(m_axi_rdata[40]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[8]),
+        .O(\\skid_buffer[11]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[12]_i_1 
+       (.I0(m_axi_rdata[41]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[9]),
+        .O(\\skid_buffer[12]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[13]_i_1 
+       (.I0(m_axi_rdata[42]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[10]),
+        .O(\\skid_buffer[13]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[14]_i_1 
+       (.I0(m_axi_rdata[43]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[11]),
+        .O(\\skid_buffer[14]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[15]_i_1 
+       (.I0(m_axi_rdata[44]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[12]),
+        .O(\\skid_buffer[15]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[16]_i_1 
+       (.I0(m_axi_rdata[45]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[13]),
+        .O(\\skid_buffer[16]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[17]_i_1 
+       (.I0(m_axi_rdata[46]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[14]),
+        .O(\\skid_buffer[17]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[18]_i_1 
+       (.I0(m_axi_rdata[47]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[15]),
+        .O(\\skid_buffer[18]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[19]_i_1 
+       (.I0(m_axi_rdata[48]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[16]),
+        .O(\\skid_buffer[19]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[20]_i_1 
+       (.I0(m_axi_rdata[49]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[17]),
+        .O(\\skid_buffer[20]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[21]_i_1 
+       (.I0(m_axi_rdata[50]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[18]),
+        .O(\\skid_buffer[21]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[22]_i_1 
+       (.I0(m_axi_rdata[51]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[19]),
+        .O(\\skid_buffer[22]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[23]_i_1 
+       (.I0(m_axi_rdata[52]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[20]),
+        .O(\\skid_buffer[23]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[24]_i_1 
+       (.I0(m_axi_rdata[53]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[21]),
+        .O(\\skid_buffer[24]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[25]_i_1 
+       (.I0(m_axi_rdata[54]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[22]),
+        .O(\\skid_buffer[25]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[26]_i_1 
+       (.I0(m_axi_rdata[55]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[23]),
+        .O(\\skid_buffer[26]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[27]_i_1 
+       (.I0(m_axi_rdata[56]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[24]),
+        .O(\\skid_buffer[27]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[28]_i_1 
+       (.I0(m_axi_rdata[57]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[25]),
+        .O(\\skid_buffer[28]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[29]_i_1 
+       (.I0(m_axi_rdata[58]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[26]),
+        .O(\\skid_buffer[29]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[30]_i_1 
+       (.I0(m_axi_rdata[59]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[27]),
+        .O(\\skid_buffer[30]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[31]_i_1 
+       (.I0(m_axi_rdata[60]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[28]),
+        .O(\\skid_buffer[31]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[32]_i_1 
+       (.I0(m_axi_rdata[61]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[29]),
+        .O(\\skid_buffer[32]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[33]_i_1 
+       (.I0(m_axi_rdata[62]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[30]),
+        .O(\\skid_buffer[33]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[34]_i_1 
+       (.I0(m_axi_rdata[63]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[31]),
+        .O(\\skid_buffer[34]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[3]_i_1 
+       (.I0(m_axi_rdata[32]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[0]),
+        .O(\\skid_buffer[3]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[4]_i_1 
+       (.I0(m_axi_rdata[33]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[1]),
+        .O(\\skid_buffer[4]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[5]_i_1 
+       (.I0(m_axi_rdata[34]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[2]),
+        .O(\\skid_buffer[5]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[6]_i_1 
+       (.I0(m_axi_rdata[35]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[3]),
+        .O(\\skid_buffer[6]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[7]_i_1 
+       (.I0(m_axi_rdata[36]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[4]),
+        .O(\\skid_buffer[7]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[8]_i_1 
+       (.I0(m_axi_rdata[37]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[5]),
+        .O(\\skid_buffer[8]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h0B08)) 
+    \\skid_buffer[9]_i_1 
+       (.I0(m_axi_rdata[38]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_rdata[6]),
+        .O(\\skid_buffer[9]_i_1_n_0 ));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[10]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[11]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[12]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[13]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[14]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[15]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[16]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[17]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[18]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[19]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[20]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[21]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[22]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[23]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[24]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[25]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[26]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[27]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[28]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[29]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[30]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[31]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[32]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[33]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[34]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[3]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[4]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[5]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[6]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[7]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[8]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[9]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (aclk,
+    aresetn,
+    s_axi_awaddr,
+    s_axi_awprot,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awaddr,
+    m_axi_awprot,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bresp,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_araddr,
+    m_axi_arprot,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rvalid,
+    m_axi_rready);
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLKIF CLK"" *) input aclk;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RSTIF RST"" *) input aresetn;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"" *) input [31:0]s_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"" *) input [2:0]s_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"" *) input [0:0]s_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"" *) output [0:0]s_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WVALID"" *) input [0:0]s_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WREADY"" *) output [0:0]s_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BVALID"" *) output [0:0]s_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BREADY"" *) input [0:0]s_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"" *) input [31:0]s_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"" *) input [2:0]s_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"" *) input [0:0]s_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"" *) output [0:0]s_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RVALID"" *) output [0:0]s_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RREADY"" *) input [0:0]s_axi_rready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]"" *) output [63:0]m_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]"" *) output [5:0]m_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]"" *) output [1:0]m_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]"" *) input [1:0]m_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]"" *) output [63:0]m_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]"" *) output [7:0]m_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]"" *) output [1:0]m_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]"" *) input [1:0]m_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]"" *) input [3:0]m_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]"" *) input [1:0]m_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]"" *) output [1:0]m_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]"" *) output [63:0]m_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]"" *) output [5:0]m_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]"" *) output [1:0]m_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]"" *) input [1:0]m_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]"" *) input [63:0]m_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]"" *) input [3:0]m_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]"" *) input [1:0]m_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]"" *) output [1:0]m_axi_rready;
+
+  wire aclk;
+  wire aresetn;
+  wire [63:0]m_axi_araddr;
+  wire [5:0]m_axi_arprot;
+  wire [1:0]m_axi_arready;
+  wire [1:0]m_axi_arvalid;
+  wire [63:0]m_axi_awaddr;
+  wire [5:0]m_axi_awprot;
+  wire [1:0]m_axi_awready;
+  wire [1:0]m_axi_awvalid;
+  wire [1:0]m_axi_bready;
+  wire [3:0]m_axi_bresp;
+  wire [1:0]m_axi_bvalid;
+  wire [63:0]m_axi_rdata;
+  wire [1:0]m_axi_rready;
+  wire [3:0]m_axi_rresp;
+  wire [1:0]m_axi_rvalid;
+  wire [63:0]m_axi_wdata;
+  wire [1:0]m_axi_wready;
+  wire [7:0]m_axi_wstrb;
+  wire [1:0]m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+  wire [3:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_arid_UNCONNECTED;
+  wire [15:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+  wire [5:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_awid_UNCONNECTED;
+  wire [15:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+  wire [5:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_wid_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_wlast_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+  (* C_AXI_ADDR_WIDTH = ""32"" *) 
+  (* C_AXI_ARUSER_WIDTH = ""1"" *) 
+  (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+  (* C_AXI_BUSER_WIDTH = ""1"" *) 
+  (* C_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_AXI_ID_WIDTH = ""1"" *) 
+  (* C_AXI_PROTOCOL = ""2"" *) 
+  (* C_AXI_RUSER_WIDTH = ""1"" *) 
+  (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+  (* C_AXI_WUSER_WIDTH = ""1"" *) 
+  (* C_CONNECTIVITY_MODE = ""0"" *) 
+  (* C_DEBUG = ""1"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_M_AXI_ADDR_WIDTH = ""64\'b0000000000000000000000000001000000000000000000000000000000010000"" *) 
+  (* C_M_AXI_BASE_ADDR = ""128\'b00000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+  (* C_M_AXI_READ_CONNECTIVITY = ""64\'b1111111111111111111111111111111111111111111111111111111111111111"" *) 
+  (* C_M_AXI_READ_ISSUING = ""64\'b0000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_SECURE = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* C_M_AXI_WRITE_CONNECTIVITY = ""64\'b1111111111111111111111111111111111111111111111111111111111111111"" *) 
+  (* C_M_AXI_WRITE_ISSUING = ""64\'b0000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_NUM_ADDR_RANGES = ""1"" *) 
+  (* C_NUM_MASTER_SLOTS = ""2"" *) 
+  (* C_NUM_SLAVE_SLOTS = ""1"" *) 
+  (* C_R_REGISTER = ""1"" *) 
+  (* C_S_AXI_ARB_PRIORITY = ""0"" *) 
+  (* C_S_AXI_BASE_ID = ""0"" *) 
+  (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+  (* C_S_AXI_SINGLE_THREAD = ""1"" *) 
+  (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) 
+  (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+  (* DowngradeIPIdentifiedWarnings = ""yes"" *) 
+  (* P_ADDR_DECODE = ""1"" *) 
+  (* P_AXI3 = ""1"" *) 
+  (* P_AXI4 = ""0"" *) 
+  (* P_AXILITE = ""2"" *) 
+  (* P_AXILITE_SIZE = ""3\'b010"" *) 
+  (* P_FAMILY = ""zynq"" *) 
+  (* P_INCR = ""2\'b01"" *) 
+  (* P_LEN = ""8"" *) 
+  (* P_LOCK = ""1"" *) 
+  (* P_M_AXI_ERR_MODE = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_M_AXI_SUPPORTS_READ = ""2\'b11"" *) 
+  (* P_M_AXI_SUPPORTS_WRITE = ""2\'b11"" *) 
+  (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) 
+  (* P_RANGE_CHECK = ""1"" *) 
+  (* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+  (* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar inst
+       (.aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[3:0]),
+        .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[7:0]),
+        .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[1:0]),
+        .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[15:0]),
+        .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[1:0]),
+        .m_axi_arprot(m_axi_arprot),
+        .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[7:0]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[7:0]),
+        .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[5:0]),
+        .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[1:0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[3:0]),
+        .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[7:0]),
+        .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[1:0]),
+        .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[15:0]),
+        .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[1:0]),
+        .m_axi_awprot(m_axi_awprot),
+        .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[7:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[7:0]),
+        .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[5:0]),
+        .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[1:0]),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bid({1\'b0,1\'b0}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_buser({1\'b0,1\'b0}),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rid({1\'b0,1\'b0}),
+        .m_axi_rlast({1\'b1,1\'b1}),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_ruser({1\'b0,1\'b0}),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wdata(m_axi_wdata),
+        .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[1:0]),
+        .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[1:0]),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wstrb(m_axi_wstrb),
+        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[1:0]),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst({1\'b0,1\'b0}),
+        .s_axi_arcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arid(1\'b0),
+        .s_axi_arlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arlock(1\'b0),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_aruser(1\'b0),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst({1\'b0,1\'b0}),
+        .s_axi_awcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awid(1\'b0),
+        .s_axi_awlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awlock(1\'b0),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_awuser(1\'b0),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
+        .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wid(1\'b0),
+        .s_axi_wlast(1\'b1),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wuser(1\'b0),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+//Date        : Tue Feb 14 01:36:24 2017
+//Host        : TheMosass-PC running 64-bit major release  (build 9200)
+//Command     : generate_target design_1_wrapper.bd
+//Design      : design_1_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+   (DDR_addr,
+    DDR_ba,
+    DDR_cas_n,
+    DDR_ck_n,
+    DDR_ck_p,
+    DDR_cke,
+    DDR_cs_n,
+    DDR_dm,
+    DDR_dq,
+    DDR_dqs_n,
+    DDR_dqs_p,
+    DDR_odt,
+    DDR_ras_n,
+    DDR_reset_n,
+    DDR_we_n,
+    FIXED_IO_ddr_vrn,
+    FIXED_IO_ddr_vrp,
+    FIXED_IO_mio,
+    FIXED_IO_ps_clk,
+    FIXED_IO_ps_porb,
+    FIXED_IO_ps_srstb,
+    btns_4bits_tri_i,
+    leds_4bits_tri_io,
+    sws_4bits_tri_i);
+  inout [14:0]DDR_addr;
+  inout [2:0]DDR_ba;
+  inout DDR_cas_n;
+  inout DDR_ck_n;
+  inout DDR_ck_p;
+  inout DDR_cke;
+  inout DDR_cs_n;
+  inout [3:0]DDR_dm;
+  inout [31:0]DDR_dq;
+  inout [3:0]DDR_dqs_n;
+  inout [3:0]DDR_dqs_p;
+  inout DDR_odt;
+  inout DDR_ras_n;
+  inout DDR_reset_n;
+  inout DDR_we_n;
+  inout FIXED_IO_ddr_vrn;
+  inout FIXED_IO_ddr_vrp;
+  inout [53:0]FIXED_IO_mio;
+  inout FIXED_IO_ps_clk;
+  inout FIXED_IO_ps_porb;
+  inout FIXED_IO_ps_srstb;
+  input [3:0]btns_4bits_tri_i;
+  inout [3:0]leds_4bits_tri_io;
+  input [3:0]sws_4bits_tri_i;
+
+  wire [14:0]DDR_addr;
+  wire [2:0]DDR_ba;
+  wire DDR_cas_n;
+  wire DDR_ck_n;
+  wire DDR_ck_p;
+  wire DDR_cke;
+  wire DDR_cs_n;
+  wire [3:0]DDR_dm;
+  wire [31:0]DDR_dq;
+  wire [3:0]DDR_dqs_n;
+  wire [3:0]DDR_dqs_p;
+  wire DDR_odt;
+  wire DDR_ras_n;
+  wire DDR_reset_n;
+  wire DDR_we_n;
+  wire FIXED_IO_ddr_vrn;
+  wire FIXED_IO_ddr_vrp;
+  wire [53:0]FIXED_IO_mio;
+  wire FIXED_IO_ps_clk;
+  wire FIXED_IO_ps_porb;
+  wire FIXED_IO_ps_srstb;
+  wire [3:0]btns_4bits_tri_i;
+  wire [0:0]leds_4bits_tri_i_0;
+  wire [1:1]leds_4bits_tri_i_1;
+  wire [2:2]leds_4bits_tri_i_2;
+  wire [3:3]leds_4bits_tri_i_3;
+  wire [0:0]leds_4bits_tri_io_0;
+  wire [1:1]leds_4bits_tri_io_1;
+  wire [2:2]leds_4bits_tri_io_2;
+  wire [3:3]leds_4bits_tri_io_3;
+  wire [0:0]leds_4bits_tri_o_0;
+  wire [1:1]leds_4bits_tri_o_1;
+  wire [2:2]leds_4bits_tri_o_2;
+  wire [3:3]leds_4bits_tri_o_3;
+  wire [0:0]leds_4bits_tri_t_0;
+  wire [1:1]leds_4bits_tri_t_1;
+  wire [2:2]leds_4bits_tri_t_2;
+  wire [3:3]leds_4bits_tri_t_3;
+  wire [3:0]sws_4bits_tri_i;
+
+  design_1 design_1_i
+       (.DDR_addr(DDR_addr),
+        .DDR_ba(DDR_ba),
+        .DDR_cas_n(DDR_cas_n),
+        .DDR_ck_n(DDR_ck_n),
+        .DDR_ck_p(DDR_ck_p),
+        .DDR_cke(DDR_cke),
+        .DDR_cs_n(DDR_cs_n),
+        .DDR_dm(DDR_dm),
+        .DDR_dq(DDR_dq),
+        .DDR_dqs_n(DDR_dqs_n),
+        .DDR_dqs_p(DDR_dqs_p),
+        .DDR_odt(DDR_odt),
+        .DDR_ras_n(DDR_ras_n),
+        .DDR_reset_n(DDR_reset_n),
+        .DDR_we_n(DDR_we_n),
+        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
+        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
+        .FIXED_IO_mio(FIXED_IO_mio),
+        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
+        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
+        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
+        .btns_4bits_tri_i(btns_4bits_tri_i),
+        .leds_4bits_tri_i({leds_4bits_tri_i_3,leds_4bits_tri_i_2,leds_4bits_tri_i_1,leds_4bits_tri_i_0}),
+        .leds_4bits_tri_o({leds_4bits_tri_o_3,leds_4bits_tri_o_2,leds_4bits_tri_o_1,leds_4bits_tri_o_0}),
+        .leds_4bits_tri_t({leds_4bits_tri_t_3,leds_4bits_tri_t_2,leds_4bits_tri_t_1,leds_4bits_tri_t_0}),
+        .sws_4bits_tri_i(sws_4bits_tri_i));
+  IOBUF leds_4bits_tri_iobuf_0
+       (.I(leds_4bits_tri_o_0),
+        .IO(leds_4bits_tri_io[0]),
+        .O(leds_4bits_tri_i_0),
+        .T(leds_4bits_tri_t_0));
+  IOBUF leds_4bits_tri_iobuf_1
+       (.I(leds_4bits_tri_o_1),
+        .IO(leds_4bits_tri_io[1]),
+        .O(leds_4bits_tri_i_1),
+        .T(leds_4bits_tri_t_1));
+  IOBUF leds_4bits_tri_iobuf_2
+       (.I(leds_4bits_tri_o_2),
+        .IO(leds_4bits_tri_io[2]),
+        .O(leds_4bits_tri_i_2),
+        .T(leds_4bits_tri_t_2));
+  IOBUF leds_4bits_tri_iobuf_3
+       (.I(leds_4bits_tri_o_3),
+        .IO(leds_4bits_tri_io[3]),
+        .O(leds_4bits_tri_i_3),
+        .T(leds_4bits_tri_t_3));
+endmodule
+"
+"// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Address AXI3 Slave Converter
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   a_axi3_conv
+//     axic_fifo
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_a_axi3_conv #
+  (
+   parameter C_FAMILY                            = ""none"",
+   parameter integer C_AXI_ID_WIDTH              = 1,
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_DATA_WIDTH            = 32,
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
+   parameter integer C_AXI_AUSER_WIDTH           = 1,
+   parameter integer C_AXI_CHANNEL                    = 0,
+                       // 0 = AXI AW Channel.
+                       // 1 = AXI AR Channel.
+   parameter integer C_SUPPORT_SPLITTING              = 1,
+                       // Implement transaction splitting logic.
+                       // Disabled whan all connected masters are AXI3 and have same or narrower data width.
+   parameter integer C_SUPPORT_BURSTS                 = 1,
+                       // Disabled when all connected masters are AxiLite,
+                       //   allowing logic to be simplified.
+   parameter integer C_SINGLE_THREAD                  = 1
+                       // 0 = Ignore ID when propagating transactions (assume all responses are in order).
+                       // 1 = Enforce single-threading (one ID at a time) when any outstanding or 
+                       //     requested transaction requires splitting.
+                       //     While no split is ongoing any new non-split transaction will pass immediately regardless
+                       //     off ID.
+                       //     A split transaction will stall if there are multiple ID (non-split) transactions
+                       //     ongoing, once it has been forwarded only transactions with the same ID is allowed
+                       //     (split or not) until all ongoing split transactios has been completed.
+   )
+  (
+   // System Signals
+   input wire ACLK,
+   input wire ARESET,
+
+   // Command Interface (W/R)
+   output wire                              cmd_valid,
+   output wire                              cmd_split,
+   output wire [C_AXI_ID_WIDTH-1:0]         cmd_id,
+   output wire [4-1:0]                      cmd_length,
+   input  wire                              cmd_ready,
+   
+   // Command Interface (B)
+   output wire                              cmd_b_valid,
+   output wire                              cmd_b_split,
+   output wire [4-1:0]                      cmd_b_repeat,
+   input  wire                              cmd_b_ready,
+   
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_AID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_AADDR,
+   input  wire [8-1:0]                  S_AXI_ALEN,
+   input  wire [3-1:0]                  S_AXI_ASIZE,
+   input  wire [2-1:0]                  S_AXI_ABURST,
+   input  wire [1-1:0]                  S_AXI_ALOCK,
+   input  wire [4-1:0]                  S_AXI_ACACHE,
+   input  wire [3-1:0]                  S_AXI_APROT,
+   input  wire [4-1:0]                  S_AXI_AQOS,
+   input  wire [C_AXI_AUSER_WIDTH-1:0]  S_AXI_AUSER,
+   input  wire                          S_AXI_AVALID,
+   output wire                          S_AXI_AREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_AID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_AADDR,
+   output wire [4-1:0]                  M_AXI_ALEN,
+   output wire [3-1:0]                  M_AXI_ASIZE,
+   output wire [2-1:0]                  M_AXI_ABURST,
+   output wire [2-1:0]                  M_AXI_ALOCK,
+   output wire [4-1:0]                  M_AXI_ACACHE,
+   output wire [3-1:0]                  M_AXI_APROT,
+   output wire [4-1:0]                  M_AXI_AQOS,
+   output wire [C_AXI_AUSER_WIDTH-1:0]  M_AXI_AUSER,
+   output wire                          M_AXI_AVALID,
+   input  wire                          M_AXI_AREADY
+   );
+
+   
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for burst types.
+  localparam [2-1:0] C_FIX_BURST         = 2\'b00;
+  localparam [2-1:0] C_INCR_BURST        = 2\'b01;
+  localparam [2-1:0] C_WRAP_BURST        = 2\'b10;
+  
+  // Depth for command FIFO.
+  localparam integer C_FIFO_DEPTH_LOG    = 5;
+  
+  // Constants used to generate size mask.
+  localparam [C_AXI_ADDR_WIDTH+8-1:0] C_SIZE_MASK = {{C_AXI_ADDR_WIDTH{1\'b1}}, 8\'b0000_0000};
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Access decoding related signals.
+  wire                                access_is_incr;
+  wire [4-1:0]                        num_transactions;
+  wire                                incr_need_to_split;
+  reg  [C_AXI_ADDR_WIDTH-1:0]         next_mi_addr;
+  reg                                 split_ongoing;
+  reg  [4-1:0]                        pushed_commands;
+  reg  [16-1:0]                       addr_step;
+  reg  [16-1:0]                       first_step;
+  wire [8-1:0]                        first_beats;
+  reg  [C_AXI_ADDR_WIDTH-1:0]         size_mask;
+  
+  // Access decoding related signals for internal pipestage.
+  reg                                 access_is_incr_q;
+  reg                                 incr_need_to_split_q;
+  wire                                need_to_split_q;
+  reg  [4-1:0]                        num_transactions_q;
+  reg  [16-1:0]                       addr_step_q;
+  reg  [16-1:0]                       first_step_q;
+  reg  [C_AXI_ADDR_WIDTH-1:0]         size_mask_q;
+  
+  // Command buffer help signals.
+  reg  [C_FIFO_DEPTH_LOG:0]           cmd_depth;
+  reg                                 cmd_empty;
+  reg  [C_AXI_ID_WIDTH-1:0]           queue_id;
+  wire                                id_match;
+  wire                                cmd_id_check;
+  wire                                s_ready;
+  wire                                cmd_full;
+  wire                                allow_this_cmd;
+  wire                                allow_new_cmd;
+  wire                                cmd_push;
+  reg                                 cmd_push_block;
+  reg  [C_FIFO_DEPTH_LOG:0]           cmd_b_depth;
+  reg                                 cmd_b_empty;
+  wire                                cmd_b_full;
+  wire                                cmd_b_push;
+  reg                                 cmd_b_push_block;
+  wire                                pushed_new_cmd;
+  wire                                last_incr_split;
+  wire                                last_split;
+  wire                                first_split;
+  wire                                no_cmd;
+  wire                                allow_split_cmd;
+  wire                                almost_empty;
+  wire                                no_b_cmd;
+  wire                                allow_non_split_cmd;
+  wire                                almost_b_empty;
+  reg                                 multiple_id_non_split;
+  reg                                 split_in_progress;
+  
+  // Internal Command Interface signals (W/R).
+  wire                                cmd_split_i;
+  wire [C_AXI_ID_WIDTH-1:0]           cmd_id_i;
+  reg  [4-1:0]                        cmd_length_i;
+  
+  // Internal Command Interface signals (B).
+  wire                                cmd_b_split_i;
+  wire [4-1:0]                        cmd_b_repeat_i;
+  
+  // Throttling help signals.
+  wire                                mi_stalling;
+  reg                                 command_ongoing;
+   
+  // Internal SI-side signals.
+  reg  [C_AXI_ID_WIDTH-1:0]           S_AXI_AID_Q;
+  reg  [C_AXI_ADDR_WIDTH-1:0]         S_AXI_AADDR_Q;
+  reg  [8-1:0]                        S_AXI_ALEN_Q;
+  reg  [3-1:0]                        S_AXI_ASIZE_Q;
+  reg  [2-1:0]                        S_AXI_ABURST_Q;
+  reg  [2-1:0]                        S_AXI_ALOCK_Q;
+  reg  [4-1:0]                        S_AXI_ACACHE_Q;
+  reg  [3-1:0]                        S_AXI_APROT_Q;
+  reg  [4-1:0]                        S_AXI_AQOS_Q;
+  reg  [C_AXI_AUSER_WIDTH-1:0]        S_AXI_AUSER_Q;
+  reg                                 S_AXI_AREADY_I;
+  
+  // Internal MI-side signals.
+  wire [C_AXI_ID_WIDTH-1:0]           M_AXI_AID_I;
+  reg  [C_AXI_ADDR_WIDTH-1:0]         M_AXI_AADDR_I;
+  reg  [8-1:0]                        M_AXI_ALEN_I;
+  wire [3-1:0]                        M_AXI_ASIZE_I;
+  wire [2-1:0]                        M_AXI_ABURST_I;
+  reg  [2-1:0]                        M_AXI_ALOCK_I;
+  wire [4-1:0]                        M_AXI_ACACHE_I;
+  wire [3-1:0]                        M_AXI_APROT_I;
+  wire [4-1:0]                        M_AXI_AQOS_I;
+  wire [C_AXI_AUSER_WIDTH-1:0]        M_AXI_AUSER_I;
+  wire                                M_AXI_AVALID_I;
+  wire                                M_AXI_AREADY_I;
+  
+  reg [1:0] areset_d; // Reset delay register
+  always @(posedge ACLK) begin
+    areset_d <= {areset_d[0], ARESET};
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Capture SI-Side signals.
+  //
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Register SI-Side signals.
+  always @ (posedge ACLK) begin
+    if ( ARESET ) begin
+      S_AXI_AID_Q     <= {C_AXI_ID_WIDTH{1\'b0}};
+      S_AXI_AADDR_Q   <= {C_AXI_ADDR_WIDTH{1\'b0}};
+      S_AXI_ALEN_Q    <= 8\'b0;
+      S_AXI_ASIZE_Q   <= 3\'b0;
+      S_AXI_ABURST_Q  <= 2\'b0;
+      S_AXI_ALOCK_Q   <= 2\'b0;
+      S_AXI_ACACHE_Q  <= 4\'b0;
+      S_AXI_APROT_Q   <= 3\'b0;
+      S_AXI_AQOS_Q    <= 4\'b0;
+      S_AXI_AUSER_Q   <= {C_AXI_AUSER_WIDTH{1\'b0}};
+    end else begin
+      if ( S_AXI_AREADY_I ) begin
+        S_AXI_AID_Q     <= S_AXI_AID;
+        S_AXI_AADDR_Q   <= S_AXI_AADDR;
+        S_AXI_ALEN_Q    <= S_AXI_ALEN;
+        S_AXI_ASIZE_Q   <= S_AXI_ASIZE;
+        S_AXI_ABURST_Q  <= S_AXI_ABURST;
+        S_AXI_ALOCK_Q   <= S_AXI_ALOCK;
+        S_AXI_ACACHE_Q  <= S_AXI_ACACHE;
+        S_AXI_APROT_Q   <= S_AXI_APROT;
+        S_AXI_AQOS_Q    <= S_AXI_AQOS;
+        S_AXI_AUSER_Q   <= S_AXI_AUSER;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Decode the Incoming Transaction.
+  // 
+  // Extract transaction type and the number of splits that may be needed.
+  // 
+  // Calculate the step size so that the address for each part of a split can
+  // can be calculated. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction burst type.
+  assign access_is_incr   = ( S_AXI_ABURST == C_INCR_BURST );
+  
+  // Get number of transactions for split INCR.
+  assign num_transactions = S_AXI_ALEN[4 +: 4];
+  assign first_beats = {3\'b0, S_AXI_ALEN[0 +: 4]} + 7\'b01;
+  
+  // Generate address increment of first split transaction.
+  always @ *
+  begin
+    case (S_AXI_ASIZE)
+      3\'b000: first_step = first_beats << 0;
+      3\'b001: first_step = first_beats << 1;
+      3\'b010: first_step = first_beats << 2;
+      3\'b011: first_step = first_beats << 3;
+      3\'b100: first_step = first_beats << 4;
+      3\'b101: first_step = first_beats << 5;
+      3\'b110: first_step = first_beats << 6;
+      3\'b111: first_step = first_beats << 7;
+    endcase
+  end
+  
+  // Generate address increment for remaining split transactions.
+  always @ *
+  begin
+    case (S_AXI_ASIZE)
+      3\'b000: addr_step = 16\'h0010;
+      3\'b001: addr_step = 16\'h0020;
+      3\'b010: addr_step = 16\'h0040;
+      3\'b011: addr_step = 16\'h0080;
+      3\'b100: addr_step = 16\'h0100;
+      3\'b101: addr_step = 16\'h0200;
+      3\'b110: addr_step = 16\'h0400;
+      3\'b111: addr_step = 16\'h0800;
+    endcase
+  end
+  
+  // Generate address mask bits to remove split transaction unalignment.
+  always @ *
+  begin
+    case (S_AXI_ASIZE)
+      3\'b000: size_mask = C_SIZE_MASK[8 +: C_AXI_ADDR_WIDTH];
+      3\'b001: size_mask = C_SIZE_MASK[7 +: C_AXI_ADDR_WIDTH];
+      3\'b010: size_mask = C_SIZE_MASK[6 +: C_AXI_ADDR_WIDTH];
+      3\'b011: size_mask = C_SIZE_MASK[5 +: C_AXI_ADDR_WIDTH];
+      3\'b100: size_mask = C_SIZE_MASK[4 +: C_AXI_ADDR_WIDTH];
+      3\'b101: size_mask = C_SIZE_MASK[3 +: C_AXI_ADDR_WIDTH];
+      3\'b110: size_mask = C_SIZE_MASK[2 +: C_AXI_ADDR_WIDTH];
+      3\'b111: size_mask = C_SIZE_MASK[1 +: C_AXI_ADDR_WIDTH];
+    endcase
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transfer SI-Side signals to internal Pipeline Stage.
+  //
+  /////////////////////////////////////////////////////////////////////////////
+  
+  always @ (posedge ACLK) begin
+    if ( ARESET ) begin
+      access_is_incr_q      <= 1\'b0;
+      incr_need_to_split_q  <= 1\'b0;
+      num_transactions_q    <= 4\'b0;
+      addr_step_q           <= 16\'b0;
+      first_step_q           <= 16\'b0;
+      size_mask_q           <= {C_AXI_ADDR_WIDTH{1\'b0}};
+    end else begin
+      if ( S_AXI_AREADY_I ) begin
+        access_is_incr_q      <= access_is_incr;
+        incr_need_to_split_q  <= incr_need_to_split;
+        num_transactions_q    <= num_transactions;
+        addr_step_q           <= addr_step;
+        first_step_q          <= first_step;
+        size_mask_q           <= size_mask;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Generate Command Information.
+  // 
+  // Detect if current transation needs to be split, and keep track of all
+  // the generated split transactions.
+  // 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detect when INCR must be split.
+  assign incr_need_to_split = access_is_incr & ( num_transactions != 0 ) &
+                              ( C_SUPPORT_SPLITTING == 1 ) &
+                              ( C_SUPPORT_BURSTS == 1 );
+  
+  // Detect when a command has to be split.
+  assign need_to_split_q    = incr_need_to_split_q;
+  
+  // Handle progress of split transactions.
+  always @ (posedge ACLK) begin
+    if ( ARESET ) begin
+      split_ongoing     <= 1\'b0;
+    end else begin
+      if ( pushed_new_cmd ) begin
+        split_ongoing     <= need_to_split_q & ~last_split;
+      end
+    end
+  end
+  
+  // Keep track of number of transactions generated.
+  always @ (posedge ACLK) begin
+    if ( ARESET ) begin
+      pushed_commands <= 4\'b0;
+    end else begin
+      if ( S_AXI_AREADY_I ) begin
+        pushed_commands <= 4\'b0;
+      end else if ( pushed_new_cmd ) begin
+        pushed_commands <= pushed_commands + 4\'b1;
+      end
+    end
+  end
+  
+  // Detect last part of a command, split or not.
+  assign last_incr_split    = access_is_incr_q & ( num_transactions_q   == pushed_commands );
+  assign last_split         = last_incr_split | ~access_is_incr_q | 
+                              ( C_SUPPORT_SPLITTING == 0 ) |
+                              ( C_SUPPORT_BURSTS == 0 );
+  assign first_split = (pushed_commands == 4\'b0);
+  
+  // Calculate base for next address.
+  always @ (posedge ACLK) begin
+    if ( ARESET ) begin
+      next_mi_addr  = {C_AXI_ADDR_WIDTH{1\'b0}};
+    end else if ( pushed_new_cmd ) begin
+      next_mi_addr  = M_AXI_AADDR_I + (first_split ? first_step_q : addr_step_q);
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Translating Transaction.
+  // 
+  // Set Split transaction information on all part except last for a transaction 
+  // that needs splitting.
+  // The B Channel will only get one command for a Split transaction and in 
+  // the Split bflag will be set in that case.
+  // 
+  // The AWID is extracted and applied to all commands generated for the current 
+  // incomming SI-Side transaction.
+  // 
+  // The address is increased for each part of a Split transaction, the amount
+  // depends on the siSIZE for the transaction.
+  // 
+  // The length has to be changed for Split transactions. All part except tha 
+  // last one will have 0xF, the last one uses the 4 lsb bits from the SI-side
+  // transaction as length.
+  // 
+  // Non-Split has untouched address and length information.
+  // 
+  // Exclusive access are diasabled for a Split transaction because it is not 
+  // possible to guarantee concistency between all the parts.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Assign Split signals.
+  assign cmd_split_i        = need_to_split_q & ~last_split;
+  assign cmd_b_split_i      = need_to_split_q & ~last_split;
+  
+  // Copy AW ID to W.
+  assign cmd_id_i           = S_AXI_AID_Q;
+  
+  // Set B Responses to merge.
+  assign cmd_b_repeat_i     = num_transactions_q;
+  
+  // Select new size or remaining size.
+  always @ *
+  begin
+    if ( split_ongoing & access_is_incr_q ) begin
+      M_AXI_AADDR_I = next_mi_addr & size_mask_q;
+    end else begin
+      M_AXI_AADDR_I = S_AXI_AADDR_Q;
+    end
+  end
+  
+  // Generate the base length for each transaction.
+  always @ *
+  begin
+    if ( first_split | ~need_to_split_q ) begin
+      M_AXI_ALEN_I = S_AXI_ALEN_Q[0 +: 4];
+      cmd_length_i = S_AXI_ALEN_Q[0 +: 4];
+    end else begin
+      M_AXI_ALEN_I = 4\'hF;
+      cmd_length_i = 4\'hF;
+    end
+  end
+  
+  // Kill Exclusive for Split transactions.
+  always @ *
+  begin
+    if ( need_to_split_q ) begin
+      M_AXI_ALOCK_I = 2\'b00;
+    end else begin
+      M_AXI_ALOCK_I = {1\'b0, S_AXI_ALOCK_Q};
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Forward the command to the MI-side interface.
+  // 
+  // It is determined that this is an allowed command/access when there is 
+  // room in the command queue (and it passes ID and Split checks as required).
+  //
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Move SI-side transaction to internal pipe stage.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      command_ongoing <= 1\'b0;
+      S_AXI_AREADY_I <= 1\'b0;
+    end else begin
+      if (areset_d == 2\'b10) begin
+        S_AXI_AREADY_I <= 1\'b1;
+      end else begin
+        if ( S_AXI_AVALID & S_AXI_AREADY_I ) begin
+          command_ongoing <= 1\'b1;
+          S_AXI_AREADY_I <= 1\'b0;
+        end else if ( pushed_new_cmd & last_split ) begin
+          command_ongoing <= 1\'b0;
+          S_AXI_AREADY_I <= 1\'b1;
+        end 
+      end
+    end
+  end
+  
+  // Generate ready signal.
+  assign S_AXI_AREADY   = S_AXI_AREADY_I;
+  
+  // Only allowed to forward translated command when command queue is ok with it.
+  assign M_AXI_AVALID_I = allow_new_cmd & command_ongoing;
+  
+  // Detect when MI-side is stalling.
+  assign mi_stalling    = M_AXI_AVALID_I & ~M_AXI_AREADY_I;
+                          
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Simple transfer of paramters that doesn\'t need to be adjusted.
+  // 
+  // ID     - Transaction still recognized with the same ID.
+  // CACHE  - No need to change the chache features. Even if the modyfiable
+  //          bit is overridden (forcefully) there is no need to let downstream
+  //          component beleive it is ok to modify it further.
+  // PROT   - Security level of access is not changed when upsizing.
+  // QOS    - Quality of Service is static 0.
+  // USER   - User bits remains the same.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  assign M_AXI_AID_I      = S_AXI_AID_Q;
+  assign M_AXI_ASIZE_I    = S_AXI_ASIZE_Q;
+  assign M_AXI_ABURST_I   = S_AXI_ABURST_Q;
+  assign M_AXI_ACACHE_I   = S_AXI_ACACHE_Q;
+  assign M_AXI_APROT_I    = S_AXI_APROT_Q;
+  assign M_AXI_AQOS_I     = S_AXI_AQOS_Q;
+  assign M_AXI_AUSER_I    = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER_Q : {C_AXI_AUSER_WIDTH{1\'b0}};
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Control command queue to W/R channel.
+  //
+  // Commands can be pushed into the Cmd FIFO even if MI-side is stalling.
+  // A flag is set if MI-side is stalling when Command is pushed to the 
+  // Cmd FIFO. This will prevent multiple push of the same Command as well as
+  // keeping the MI-side Valid signal if the Allow Cmd requirement has been 
+  // updated to disable furter Commands (I.e. it is made sure that the SI-side 
+  // Command has been forwarded to both Cmd FIFO and MI-side).
+  // 
+  // It is allowed to continue pushing new commands as long as
+  // * There is room in the queue(s)
+  // * The ID is the same as previously queued. Since data is not reordered
+  //   for the same ID it is always OK to let them proceed.
+  //   Or, if no split transaction is ongoing any ID can be allowed.
+  //
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Keep track of current ID in queue.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      queue_id              <= {C_AXI_ID_WIDTH{1\'b0}};
+      multiple_id_non_split <= 1\'b0;
+      split_in_progress     <= 1\'b0;
+    end else begin
+      if ( cmd_push ) begin
+        // Store ID (it will be matching ID or a ""new beginning"").
+        queue_id              <= S_AXI_AID_Q;
+      end
+      
+      if ( no_cmd & no_b_cmd ) begin
+        multiple_id_non_split <= 1\'b0;
+      end else if ( cmd_push & allow_non_split_cmd & ~id_match ) begin
+        multiple_id_non_split <= 1\'b1;
+      end
+      
+      if ( no_cmd & no_b_cmd ) begin
+        split_in_progress     <= 1\'b0;
+      end else if ( cmd_push & allow_split_cmd ) begin
+        split_in_progress     <= 1\'b1;
+      end
+    end
+  end
+  
+  // Determine if the command FIFOs are empty.
+  assign no_cmd               = almost_empty   & cmd_ready   | cmd_empty;
+  assign no_b_cmd             = almost_b_empty & cmd_b_ready | cmd_b_empty;
+  
+  // Check ID to make sure this command is allowed.
+  assign id_match             = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID_Q);
+  assign cmd_id_check         = (cmd_empty & cmd_b_empty) | ( id_match & (~cmd_empty | ~cmd_b_empty) );
+  
+  // Command type affects possibility to push immediately or wait.
+  assign allow_split_cmd      = need_to_split_q & cmd_id_check & ~multiple_id_non_split;
+  assign allow_non_split_cmd  = ~need_to_split_q & (cmd_id_check | ~split_in_progress);
+  assign allow_this_cmd       = allow_split_cmd | allow_non_split_cmd | ( C_SINGLE_THREAD == 0 );
+  
+  // Check if it is allowed to push more commands.
+  assign allow_new_cmd        = (~cmd_full & ~cmd_b_full & allow_this_cmd) | 
+                                cmd_push_block;
+  
+  // Push new command when allowed and MI-side is able to receive the command.
+  assign cmd_push             = M_AXI_AVALID_I & ~cmd_push_block;
+  assign cmd_b_push           = M_AXI_AVALID_I & ~cmd_b_push_block & (C_AXI_CHANNEL == 0);
+  
+  // Block furter push until command has been forwarded to MI-side.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_push_block <= 1\'b0;
+    end else begin
+      if ( pushed_new_cmd ) begin
+        cmd_push_block <= 1\'b0;
+      end else if ( cmd_push & mi_stalling ) begin
+        cmd_push_block <= 1\'b1;
+      end 
+    end
+  end
+  
+  // Block furter push until command has been forwarded to MI-side.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_push_block <= 1\'b0;
+    end else begin
+      if ( S_AXI_AREADY_I ) begin
+        cmd_b_push_block <= 1\'b0;
+      end else if ( cmd_b_push ) begin
+        cmd_b_push_block <= 1\'b1;
+      end 
+    end
+  end
+  
+  // Acknowledge command when we can push it into queue (and forward it).
+  assign pushed_new_cmd = M_AXI_AVALID_I & M_AXI_AREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command Queue (W/R):
+  // 
+  // Instantiate a FIFO as the queue and adjust the control signals.
+  // 
+  // The features from Command FIFO can be reduced depending on configuration:
+  // Read Channel only need the split information.
+  // Write Channel always require ID information. When bursts are supported 
+  // Split and Length information is also used.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Instantiated queue.
+  generate
+    if ( C_AXI_CHANNEL == 1 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_R_CHANNEL
+      axi_data_fifo_v2_1_10_axic_fifo #
+      (
+       .C_FAMILY(C_FAMILY),
+       .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
+       .C_FIFO_WIDTH(1),
+       .C_FIFO_TYPE(""lut"")
+       ) 
+       cmd_queue
+      (
+       .ACLK(ACLK),
+       .ARESET(ARESET),
+       .S_MESG({cmd_split_i}),
+       .S_VALID(cmd_push),
+       .S_READY(s_ready),
+       .M_MESG({cmd_split}),
+       .M_VALID(cmd_valid),
+       .M_READY(cmd_ready)
+       );
+       
+       assign cmd_id            = {C_AXI_ID_WIDTH{1\'b0}};
+       assign cmd_length        = 4\'b0;
+       
+    end else if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS
+      axi_data_fifo_v2_1_10_axic_fifo #
+      (
+       .C_FAMILY(C_FAMILY),
+       .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
+       .C_FIFO_WIDTH(C_AXI_ID_WIDTH+4),
+       .C_FIFO_TYPE(""lut"")
+       ) 
+       cmd_queue
+      (
+       .ACLK(ACLK),
+       .ARESET(ARESET),
+       .S_MESG({cmd_id_i, cmd_length_i}),
+       .S_VALID(cmd_push),
+       .S_READY(s_ready),
+       .M_MESG({cmd_id, cmd_length}),
+       .M_VALID(cmd_valid),
+       .M_READY(cmd_ready)
+       );
+       
+       assign cmd_split         = 1\'b0;
+       
+    end else begin : NO_BURSTS
+      axi_data_fifo_v2_1_10_axic_fifo #
+      (
+       .C_FAMILY(C_FAMILY),
+       .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
+       .C_FIFO_WIDTH(C_AXI_ID_WIDTH),
+       .C_FIFO_TYPE(""lut"")
+       ) 
+       cmd_queue
+      (
+       .ACLK(ACLK),
+       .ARESET(ARESET),
+       .S_MESG({cmd_id_i}),
+       .S_VALID(cmd_push),
+       .S_READY(s_ready),
+       .M_MESG({cmd_id}),
+       .M_VALID(cmd_valid),
+       .M_READY(cmd_ready)
+       );
+       
+       assign cmd_split         = 1\'b0;
+       assign cmd_length        = 4\'b0;
+       
+    end
+  endgenerate
+
+  // Queue is concidered full when not ready.
+  assign cmd_full   = ~s_ready;
+  
+  // Queue is empty when no data at output port.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_empty <= 1\'b1;
+      cmd_depth <= {C_FIFO_DEPTH_LOG+1{1\'b0}};
+    end else begin
+      if ( cmd_push & ~cmd_ready ) begin
+        // Push only => Increase depth.
+        cmd_depth <= cmd_depth + 1\'b1;
+        cmd_empty <= 1\'b0;
+      end else if ( ~cmd_push & cmd_ready ) begin
+        // Pop only => Decrease depth.
+        cmd_depth <= cmd_depth - 1\'b1;
+        cmd_empty <= almost_empty;
+      end
+    end
+  end
+  
+  assign almost_empty = ( cmd_depth == 1 );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command Queue (B):
+  // 
+  // Add command queue for B channel only when it is AW channel and both burst
+  // and splitting is supported.
+  //
+  // When turned off the command appears always empty.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Instantiated queue.
+  generate
+    if ( C_AXI_CHANNEL == 0 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_B_CHANNEL
+      
+      wire                                cmd_b_valid_i;
+      wire                                s_b_ready;
+      
+      axi_data_fifo_v2_1_10_axic_fifo #
+      (
+       .C_FAMILY(C_FAMILY),
+       .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
+       .C_FIFO_WIDTH(1+4),
+       .C_FIFO_TYPE(""lut"")
+       ) 
+       cmd_b_queue
+      (
+       .ACLK(ACLK),
+       .ARESET(ARESET),
+       .S_MESG({cmd_b_split_i, cmd_b_repeat_i}),
+       .S_VALID(cmd_b_push),
+       .S_READY(s_b_ready),
+       .M_MESG({cmd_b_split, cmd_b_repeat}),
+       .M_VALID(cmd_b_valid_i),
+       .M_READY(cmd_b_ready)
+       );
+    
+      // Queue is concidered full when not ready.
+      assign cmd_b_full   = ~s_b_ready;
+      
+      // Queue is empty when no data at output port.
+      always @ (posedge ACLK) begin
+        if (ARESET) begin
+          cmd_b_empty <= 1\'b1;
+          cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1\'b0}};
+        end else begin
+          if ( cmd_b_push & ~cmd_b_ready ) begin
+            // Push only => Increase depth.
+            cmd_b_depth <= cmd_b_depth + 1\'b1;
+            cmd_b_empty <= 1\'b0;
+          end else if ( ~cmd_b_push & cmd_b_ready ) begin
+            // Pop only => Decrease depth.
+            cmd_b_depth <= cmd_b_depth - 1\'b1;
+            cmd_b_empty <= ( cmd_b_depth == 1 );
+          end
+        end
+      end
+  
+      assign almost_b_empty = ( cmd_b_depth == 1 );
+      
+      // Assign external signal.
+      assign cmd_b_valid  = cmd_b_valid_i;
+      
+    end else begin : NO_B_CHANNEL
+      
+      // Assign external command signals.
+      assign cmd_b_valid    = 1\'b0;
+      assign cmd_b_split    = 1\'b0;
+      assign cmd_b_repeat   = 4\'b0;
+   
+      // Assign internal command FIFO signals.
+      assign cmd_b_full     = 1\'b0;
+      assign almost_b_empty = 1\'b0;
+      always @ (posedge ACLK) begin
+        if (ARESET) begin
+          cmd_b_empty <= 1\'b1;
+          cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1\'b0}};
+        end else begin
+          // Constant FF due to ModelSim behavior.
+          cmd_b_empty <= 1\'b1;
+          cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1\'b0}};
+        end
+      end
+      
+    end
+  endgenerate
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // MI-side output handling
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  assign M_AXI_AID      = M_AXI_AID_I;
+  assign M_AXI_AADDR    = M_AXI_AADDR_I;
+  assign M_AXI_ALEN     = M_AXI_ALEN_I;
+  assign M_AXI_ASIZE    = M_AXI_ASIZE_I;
+  assign M_AXI_ABURST   = M_AXI_ABURST_I;
+  assign M_AXI_ALOCK    = M_AXI_ALOCK_I;
+  assign M_AXI_ACACHE   = M_AXI_ACACHE_I;
+  assign M_AXI_APROT    = M_AXI_APROT_I;
+  assign M_AXI_AQOS     = M_AXI_AQOS_I;
+  assign M_AXI_AUSER    = M_AXI_AUSER_I;
+  assign M_AXI_AVALID   = M_AXI_AVALID_I;
+  assign M_AXI_AREADY_I = M_AXI_AREADY;
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same'b'.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: AXI3 Slave Converter
+// This module instantiates Address, Write Data and Read Data AXI3 Converter 
+// modules, each one taking care of the channel specific tasks.
+// The Address AXI3 converter can handle both AR and AW channels.
+// The Write Respons Channel is reused from the Down-Sizer.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//    axi3_conv
+//      a_axi3_conv
+//        axic_fifo
+//      w_axi3_conv
+//      b_downsizer
+//      r_axi3_conv
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_axi3_conv #
+  (
+   parameter C_FAMILY                            = ""none"",
+   parameter integer C_AXI_ID_WIDTH              = 1,
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_DATA_WIDTH            = 32,
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
+   parameter integer C_AXI_AWUSER_WIDTH          = 1,
+   parameter integer C_AXI_ARUSER_WIDTH          = 1,
+   parameter integer C_AXI_WUSER_WIDTH           = 1,
+   parameter integer C_AXI_RUSER_WIDTH           = 1,
+   parameter integer C_AXI_BUSER_WIDTH           = 1,
+   parameter integer C_AXI_SUPPORTS_WRITE             = 1,
+   parameter integer C_AXI_SUPPORTS_READ              = 1,
+   parameter integer C_SUPPORT_SPLITTING              = 1,
+                       // Implement transaction splitting logic.
+                       // Disabled whan all connected masters are AXI3 and have same or narrower data width.
+   parameter integer C_SUPPORT_BURSTS                 = 1,
+                       // Disabled when all connected masters are AxiLite,
+                       //   allowing logic to be simplified.
+   parameter integer C_SINGLE_THREAD                  = 1
+                       // 0 = Ignore ID when propagating transactions (assume all responses are in order).
+                       // 1 = Enforce single-threading (one ID at a time) when any outstanding or 
+                       //     requested transaction requires splitting.
+                       //     While no split is ongoing any new non-split transaction will pass immediately regardless
+                       //     off ID.
+                       //     A split transaction will stall if there are multiple ID (non-split) transactions
+                       //     ongoing, once it has been forwarded only transactions with the same ID is allowed
+                       //     (split or not) until all ongoing split transactios has been completed.
+   )
+  (
+   // System Signals
+   input wire ACLK,
+   input wire ARESETN,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_AWADDR,
+   input  wire [8-1:0]                  S_AXI_AWLEN,
+   input  wire [3-1:0]                  S_AXI_AWSIZE,
+   input  wire [2-1:0]                  S_AXI_AWBURST,
+   input  wire [1-1:0]                  S_AXI_AWLOCK,
+   input  wire [4-1:0]                  S_AXI_AWCACHE,
+   input  wire [3-1:0]                  S_AXI_AWPROT,
+   input  wire [4-1:0]                  S_AXI_AWQOS,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
+   input  wire                          S_AXI_AWVALID,
+   output wire                          S_AXI_AWREADY,
+
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_DATA_WIDTH-1:0]   S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
+   input  wire                          S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]  S_AXI_WUSER,
+   input  wire                          S_AXI_WVALID,
+   output wire                          S_AXI_WREADY,
+
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID,
+   output wire [2-1:0]                 S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
+   output wire                         S_AXI_BVALID,
+   input  wire                         S_AXI_BREADY,
+
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_ARID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_ARADDR,
+   input  wire [8-1:0]                  S_AXI_ARLEN,
+   input  wire [3-1:0]                  S_AXI_ARSIZE,
+   input  wire [2-1:0]                  S_AXI_ARBURST,
+   input  wire [1-1:0]                  S_AXI_ARLOCK,
+   input  wire [4-1:0]                  S_AXI_ARCACHE,
+   input  wire [3-1:0]                  S_AXI_ARPROT,
+   input  wire [4-1:0]                  S_AXI_ARQOS,
+   input  wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
+   input  wire                          S_AXI_ARVALID,
+   output wire                          S_AXI_ARREADY,
+
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID,
+   output wire [C_AXI_DATA_WIDTH-1:0]  S_AXI_RDATA,
+   output wire [2-1:0]                 S_AXI_RRESP,
+   output wire                         S_AXI_RLAST,
+   output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
+   output wire                         S_AXI_RVALID,
+   input  wire                         S_AXI_RREADY,
+   
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_AWADDR,
+   output wire [4-1:0]                  M_AXI_AWLEN,
+   output wire [3-1:0]                  M_AXI_AWSIZE,
+   output wire [2-1:0]                  M_AXI_AWBURST,
+   output wire [2-1:0]                  M_AXI_AWLOCK,
+   output wire [4-1:0]                  M_AXI_AWCACHE,
+   output wire [3-1:0]                  M_AXI_AWPROT,
+   output wire [4-1:0]                  M_AXI_AWQOS,
+   output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
+   output wire                          M_AXI_AWVALID,
+   input  wire                          M_AXI_AWREADY,
+   
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]   M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
+   output wire                          M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]  M_AXI_WUSER,
+   output wire                          M_AXI_WVALID,
+   input  wire                          M_AXI_WREADY,
+   
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]    M_AXI_BID,
+   input  wire [2-1:0]                 M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
+   input  wire                         M_AXI_BVALID,
+   output wire                         M_AXI_BREADY,
+   
+   // Master Interface Read Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_ARID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_ARADDR,
+   output wire [4-1:0]                  M_AXI_ARLEN,
+   output wire [3-1:0]                  M_AXI_ARSIZE,
+   output wire [2-1:0]                  M_AXI_ARBURST,
+   output wire [2-1:0]                  M_AXI_ARLOCK,
+   output wire [4-1:0]                  M_AXI_ARCACHE,
+   output wire [3-1:0]                  M_AXI_ARPROT,
+   output wire [4-1:0]                  M_AXI_ARQOS,
+   output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
+   output wire                          M_AXI_ARVALID,
+   input  wire                          M_AXI_ARREADY,
+   
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]    M_AXI_RID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]  M_AXI_RDATA,
+   input  wire [2-1:0]                 M_AXI_RRESP,
+   input  wire                         M_AXI_RLAST,
+   input  wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
+   input  wire                         M_AXI_RVALID,
+   output wire                         M_AXI_RREADY
+   );
+
+   
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Write Channels (AW/W/B)
+  /////////////////////////////////////////////////////////////////////////////
+  generate
+    if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
+    
+      // Write Channel Signals for Commands Queue Interface.
+      wire                              wr_cmd_valid;
+      wire [C_AXI_ID_WIDTH-1:0]         wr_cmd_id;
+      wire [4-1:0]                      wr_cmd_length;
+      wire                              wr_cmd_ready;
+      
+      wire                              wr_cmd_b_valid;
+      wire                              wr_cmd_b_split;
+      wire [4-1:0]                      wr_cmd_b_repeat;
+      wire                              wr_cmd_b_ready;
+      
+      // Write Address Channel.
+      axi_protocol_converter_v2_1_11_a_axi3_conv #
+      (
+       .C_FAMILY                    (C_FAMILY),
+       .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+       .C_AXI_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
+       .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
+       .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
+       .C_AXI_AUSER_WIDTH           (C_AXI_AWUSER_WIDTH),
+       .C_AXI_CHANNEL               (0),
+       .C_SUPPORT_SPLITTING         (C_SUPPORT_SPLITTING),
+       .C_SUPPORT_BURSTS            (C_SUPPORT_BURSTS),
+       .C_SINGLE_THREAD             (C_SINGLE_THREAD)
+        ) write_addr_inst
+       (
+        // Global Signals
+        .ARESET                     (~ARESETN),
+        .ACLK                       (ACLK),
+    
+        // Command Interface (W)
+        .cmd_valid                  (wr_cmd_valid),
+        .cmd_split                  (),
+        .cmd_id                     (wr_cmd_id),
+        .cmd_length                 (wr_cmd_length),
+        .cmd_ready                  (wr_cmd_ready),
+       
+        // Command Interface (B)
+        .cmd_b_valid                (wr_cmd_b_valid),
+        .cmd_b_split                (wr_cmd_b_split),
+        .cmd_b_repeat               (wr_cmd_b_repeat),
+        .cmd_b_ready                (wr_cmd_b_ready),
+       
+        // Slave Interface Write Address Ports
+        .S_AXI_AID                  (S_AXI_AWID),
+        .S_AXI_AADDR                (S_AXI_AWADDR),
+        .S_AXI_ALEN                 (S_AXI_AWLEN),
+        .S_AXI_ASIZE                (S_AXI_AWSIZE),
+        .S_AXI_ABURST               (S_AXI_AWBURST),
+        .S_AXI_ALOCK                (S_AXI_AWLOCK),
+        .S_AXI_ACACHE               (S_AXI_AWCACHE),
+        .S_AXI_APROT                (S_AXI_AWPROT),
+        .S_AXI_AQOS                 (S_AXI_AWQOS),
+        .S_AXI_AUSER                (S_AXI_AWUSER),
+        .S_AXI_AVALID               (S_AXI_AWVALID),
+        .S_AXI_AREADY               (S_AXI_AWREADY),
+        
+        // Master Interface Write Address Port
+        .M_AXI_AID                  (M_AXI_AWID),
+        .M_AXI_AADDR                (M_AXI_AWADDR),
+        .M_AXI_ALEN                 (M_AXI_AWLEN),
+        .M_AXI_ASIZE                (M_AXI_AWSIZE),
+        .M_AXI_ABURST               (M_AXI_AWBURST),
+        .M_AXI_ALOCK                (M_AXI_AWLOCK),
+        .M_AXI_ACACHE               (M_AXI_AWCACHE),
+        .M_AXI_APROT                (M_AXI_AWPROT),
+        .M_AXI_AQOS                 (M_AXI_AWQOS),
+        .M_AXI_AUSER                (M_AXI_AWUSER),
+        .M_AXI_AVALID               (M_AXI_AWVALID),
+        .M_AXI_AREADY               (M_AXI_AWREADY)
+       );
+       
+      // Write Data Channel.
+      axi_protocol_converter_v2_1_11_w_axi3_conv #
+      (
+       .C_FAMILY                    (C_FAMILY),
+       .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+       .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
+       .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
+       .C_AXI_WUSER_WIDTH           (C_AXI_WUSER_WIDTH),
+       .C_SUPPORT_SPLITTING         (C_SUPPORT_SPLITTING),
+       .C_SUPPORT_BURSTS            (C_SUPPORT_BURSTS)
+        ) write_data_inst
+       (
+        // Global Signals
+        .ARESET                     (~ARESETN),
+        .ACLK                       (ACLK),
+    
+        // Command Interface
+        .cmd_valid                  (wr_cmd_valid),
+        .cmd_id                     (wr_cmd_id),
+        .cmd_length                 (wr_cmd_length),
+        .cmd_ready                  (wr_cmd_ready),
+       
+        // Slave Interface Write Data Ports
+        .S_AXI_WDATA                (S_AXI_WDATA),
+        .S_AXI_WSTRB                (S_AXI_WSTRB),
+        .S_AXI_WLAST                (S_AXI_WLAST),
+        .S_AXI_WUSER                (S_AXI_WUSER),
+        .S_AXI_WVALID               (S_AXI_WVALID),
+        .S_AXI_WREADY               (S_AXI_WREADY),
+        
+        // Master Interface Write Data Ports
+        .M_AXI_WID                  (M_AXI_WID),
+        .M_AXI_WDATA                (M_AXI_WDATA),
+        .M_AXI_WSTRB                (M_AXI_WSTRB),
+        .M_AXI_WLAST                (M_AXI_WLAST),
+        .M_AXI_WUSER                (M_AXI_WUSER),
+        .M_AXI_WVALID               (M_AXI_WVALID),
+        .M_AXI_WREADY               (M_AXI_WREADY)
+       );
+      
+      if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_W
+      
+        // Write Data Response Channel.
+        axi_protocol_converter_v2_1_11_b_downsizer #
+        (
+         .C_FAMILY                    (C_FAMILY),
+         .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+         .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
+         .C_AXI_BUSER_WIDTH           (C_AXI_BUSER_WIDTH)
+          ) write_resp_inst
+         (
+          // Global Signals
+          .ARESET                     (~ARESETN),
+          .ACLK                       (ACLK),
+      
+          // Command Interface
+          .cmd_valid                  (wr_cmd_b_valid),
+          .cmd_split                  (wr_cmd_b_split),
+          .cmd_repeat                 (wr_cmd_b_repeat),
+          .cmd_ready                  (wr_cmd_b_ready),
+          
+          // Slave Interface Write Response Ports
+          .S_AXI_BID                  (S_AXI_BID),
+          .S_AXI_BRESP                (S_AXI_BRESP),
+          .S_AXI_BUSER                (S_AXI_BUSER),
+          .S_AXI_BVALID               (S_AXI_BVALID),
+          .S_AXI_BREADY               (S_AXI_BREADY),
+          
+          // Master Interface Write Response Ports
+          .M_AXI_BID                  (M_AXI_BID),
+          .M_AXI_BRESP                (M_AXI_BRESP),
+          .M_AXI_BUSER                (M_AXI_BUSER),
+          .M_AXI_BVALID               (M_AXI_BVALID),
+          .M_AXI_BREADY               (M_AXI_BREADY)
+         );
+        
+      end else begin : NO_SPLIT_W
+      
+        // MI -> SI Interface Write Response Ports
+        assign S_AXI_BID      = M_AXI_BID;
+        assign S_AXI_BRESP    = M_AXI_BRESP;
+        assign S_AXI_BUSER    = M_AXI_BUSER;
+        assign S_AXI_BVALID   = M_AXI_BVALID;
+        assign M_AXI_BREADY   = S_AXI_BREADY;
+        
+      end
+      
+    end else begin : NO_WRITE
+    
+      // Slave Interface Write Address Ports
+      assign S_AXI_AWREADY = 1\'b0;
+      // Slave Interface Write Data Ports
+      assign S_AXI_WREADY  = 1\'b0;
+      // Slave Interface Write Response Ports
+      assign S_AXI_BID     = {C_AXI_ID_WIDTH{1\'b0}};
+      assign S_AXI_BRESP   = 2\'b0;
+      assign S_AXI_BUSER   = {C_AXI_BUSER_WIDTH{1\'b0}};
+      assign S_AXI_BVALID  = 1\'b0;
+      
+      // Master Interface Write Address Port
+      assign M_AXI_AWID    = {C_AXI_ID_WIDTH{1\'b0}};
+      assign M_AXI_AWADDR  = {C_AXI_ADDR_WIDTH{1\'b0}};
+      assign M_AXI_AWLEN   = 4\'b0;
+      assign M_AXI_AWSIZE  = 3\'b0;
+      assign M_AXI_AWBURST = 2\'b0;
+      assign M_AXI_AWLOCK  = 2\'b0;
+      assign M_AXI_AWCACHE = 4\'b0;
+      assign M_AXI_AWPROT  = 3\'b0;
+      assign M_AXI_AWQOS   = 4\'b0;
+      assign M_AXI_AWUSER  = {C_AXI_AWUSER_WIDTH{1\'b0}};
+      assign M_AXI_AWVALID = 1\'b0;
+      // Master Interface Write Data Ports
+      assign M_AXI_WDATA   = {C_AXI_DATA_WIDTH{1\'b0}};
+      assign M_AXI_WSTRB   = {C_AXI_DATA_WIDTH/8{1\'b0}};
+      assign M_AXI_WLAST   = 1\'b0;
+      assign M_AXI_WUSER   = {C_AXI_WUSER_WIDTH{1\'b0}};
+      assign M_AXI_WVALID  = 1\'b0;
+      // Master Interface Write Response Ports
+      assign M_AXI_BREADY  = 1\'b0;
+      
+    end
+  endgenerate
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Read Channels (AR/R)
+  /////////////////////////////////////////////////////////////////////////////
+  generate
+    if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
+    
+      // Write Response channel.
+      if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_R
+      
+        // Read Channel Signals for Commands Queue Interface.
+        wire                              rd_cmd_valid;
+        wire                              rd_cmd_split;
+        wire                              rd_cmd_ready;
+        
+        // Write Address Channel.
+        axi_protocol_converter_v2_1_11_a_axi3_conv #
+        (
+         .C_FAMILY                    (C_FAMILY),
+         .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+         .C_AXI_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
+         .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
+         .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
+         .C_AXI_AUSER_WIDTH           (C_AXI_ARUSER_WIDTH),
+         .C_AXI_CHANNEL               (1),
+         .C_SUPPORT_SPLITTING         (C_SUPPORT_SPLITTING),
+         .C_SUPPORT_BURSTS            (C_SUPPORT_BURSTS),
+         .C_SINGLE_THREAD             (C_SINGLE_THREAD)
+          ) read_addr_inst
+         (
+          // Global Signals
+          .ARESET                     (~ARESETN),
+          .ACLK                       (ACLK),
+      
+          // Command Interface (R)
+          .cmd_valid                  (rd_cmd_valid),
+          .cmd_split                  (rd_cmd_split),
+          .cmd_id                     (),
+          .cmd_length                 (),
+          .cmd_ready                  (rd_cmd_ready),
+         
+          // Command Interface (B)
+          .cmd_b_valid                (),
+          .cmd_b_split                (),
+          .cmd_b_repeat               (),
+          .cmd_b_ready                (1\'b0),
+         
+          // Slave Interface Write Address Ports
+          .S_AXI_AID                  (S_AXI_ARID),
+          .S_AXI_AADDR                (S_AXI_ARADDR),
+          .S_AXI_ALEN                 (S_AXI_ARLEN),
+          .S_AXI_ASIZE                (S_AXI_ARSIZE),
+          .S_AXI_ABURST               (S_AXI_ARBURST),
+          .S_AXI_ALOCK                (S_AXI_ARLOCK),
+          .S_AXI_ACACHE               (S_AXI_ARCACHE),
+          .S_AXI_APROT                (S_AXI_ARPROT),
+          .S_AXI_AQOS                 (S_AXI_ARQOS),
+          .S_AXI_AUSER                (S_AXI_ARUSER),
+          .S_AXI_AVALID               (S_AXI_ARVALID),
+          .S_AXI_AREADY               (S_AXI_ARREADY),
+          
+          // Master Interface Write Address Port
+          .M_AXI_AID                  (M_AXI_ARID),
+          .M_AXI_AADDR                (M_AXI_ARADDR),
+          .M_AXI_ALEN                 (M_AXI_ARLEN),
+          .M_AXI_ASIZE                (M_AXI_ARSIZE),
+          .M_AXI_ABURST               (M_AXI_ARBURST),
+          .M_AXI_ALOCK                (M_AXI_ARLOCK),
+          .M_AXI_ACACHE               (M_AXI_ARCACHE),
+          .M_AXI_APROT                (M_AXI_ARPROT),
+          .M_AXI_AQOS                 (M_AXI_ARQOS),
+          .M_AXI_AUSER                (M_AXI_ARUSER),
+          .M_AXI_AVALID               (M_AXI_ARVALID),
+          .M_AXI_AREADY               (M_AXI_ARREADY)
+         );
+         
+        // Read Data Channel.
+        axi_protocol_converter_v2_1_11_r_axi3_conv #
+        (
+         .C_FAMILY                    (C_FAMILY),
+         .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+         .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
+         .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
+         .C_AXI_RUSER_WIDTH           (C_AXI_RUSER_WIDTH),
+         .C_SUPPORT_SPLITTING         (C_SUPPORT_SPLITTING),
+         .C_SUPPORT_BURSTS            (C_SUPPORT_BURSTS)
+          ) read_data_inst
+         (
+          // Global Signals
+          .ARESET                     (~ARESETN),
+          .ACLK                       (ACLK),
+      
+          // Command Interface
+          .cmd_valid                  (rd_cmd_valid),
+          .cmd_split                  (rd_cmd_split),
+          .cmd_ready                  (rd_cmd_ready),
+         
+          // Slave Interface Read Data Ports
+          .S_AXI_RID                  (S_AXI_RID),
+          .S_AXI_RDATA                (S_AXI_RDATA),
+          .S_AXI_RRESP                (S_AXI_RRESP),
+          .S_AXI_RLAST                (S_AXI_RLAST),
+          .S_AXI_RUSER                (S_AXI_RUSER),
+          .S_AXI_RVALID               (S_AXI_RVALID),
+          .S_AXI_RREADY               (S_AXI_RREADY),
+          
+          // Master Interface Read Data Ports
+          .M_AXI_RID                  (M_AXI_RID),
+          .M_AXI_RDATA                (M_AXI_RDATA),
+          .M_AXI_RRESP                (M_AXI_RRESP),
+          .M_AXI_RLAST                (M_AXI_RLAST),
+          .M_AXI_RUSER                (M_AXI_RUSER),
+          .M_AXI_RVALID               (M_AXI_RVALID),
+          .M_AXI_RREADY               (M_AXI_RREADY)
+         );
+       
+      end else begin : NO_SPLIT_R
+      
+        // SI -> MI Interface Write Address Port
+        assign M_AXI_ARID     = S_AXI_ARID;
+        assign M_AXI_ARADDR   = S_AXI_ARADDR;
+        assign M_AXI_ARLEN    = S_AXI_ARLEN;
+        assign M_AXI_ARSIZE   = S_AXI_ARSIZE;
+        assign M_AXI_ARBURST  = S_AXI_ARBURST;
+        assign M_AXI_ARLOCK   = S_AXI_ARLOCK;
+        assign M_AXI_ARCACHE  = S_AXI_ARCACHE;
+        assign M_AXI_ARPROT   = S_AXI_ARPROT;
+        assign M_AXI_ARQOS    = S_AXI_ARQOS;
+        assign M_AXI_ARUSER   = S_AXI_ARUSER;
+        assign M_AXI_ARVALID  = S_AXI_ARVALID;
+        assign S_AXI_ARREADY  = M_AXI_ARREADY;
+        
+        // MI -> SI Interface Read Data Ports
+        assign S_AXI_RID      = M_AXI_RID;
+        assign S_AXI_RDATA    = M_AXI_RDATA;
+        assign S_AXI_RRESP    = M_AXI_RRESP;
+        assign S_AXI_RLAST    = M_AXI_RLAST;
+        assign S_AXI_RUSER    = M_AXI_RUSER;
+        assign S_AXI_RVALID   = M_AXI_RVALID;
+        assign M_AXI_RREADY   = S_AXI_RREADY;
+        
+      end
+      
+    end else begin : NO_READ
+    
+      // Slave Interface Read Address Ports
+      assign S_AXI_ARREADY = 1\'b0;
+      // Slave Interface Read Data Ports
+      assign S_AXI_RID     = {C_AXI_ID_WIDTH{1\'b0}};
+      assign S_AXI_RDATA   = {C_AXI_DATA_WIDTH{1\'b0}};
+      assign S_AXI_RRESP   = 2\'b0;
+      assign S_AXI_RLAST   = 1\'b0;
+      assign S_AXI_RUSER   = {C_AXI_RUSER_WIDTH{1\'b0}};
+      assign S_AXI_RVALID  = 1\'b0;
+      
+      // Master Interface Read Address Port
+      assign M_AXI_ARID    = {C_AXI_ID_WIDTH{1\'b0}};
+      assign M_AXI_ARADDR  = {C_AXI_ADDR_WIDTH{1\'b0}};
+      assign M_AXI_ARLEN   = 4\'b0;
+      assign M_AXI_ARSIZE  = 3\'b0;
+      assign M_AXI_ARBURST = 2\'b0;
+      assign M_AXI_ARLOCK  = 2\'b0;
+      assign M_AXI_ARCACHE = 4\'b0;
+      assign M_AXI_ARPROT  = 3\'b0;
+      assign M_AXI_ARQOS   = 4\'b0;
+      assign M_AXI_ARUSER  = {C_AXI_ARUSER_WIDTH{1\'b0}};
+      assign M_AXI_ARVALID = 1\'b0;
+      // Master Interface Read Data Ports
+      assign M_AXI_RREADY  = 1\'b0;
+      
+    end
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: AxiLite Slave Conversion
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axilite_conv
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_axilite_conv #
+  (
+   parameter         C_FAMILY                    = ""virtex6"",
+   parameter integer C_AXI_ID_WIDTH              = 1,
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_DATA_WIDTH            = 32,
+   parameter integer C_AXI_SUPPORTS_WRITE        = 1,
+   parameter integer C_AXI_SUPPORTS_READ         = 1,
+   parameter integer C_AXI_RUSER_WIDTH                = 1,
+   parameter integer C_AXI_BUSER_WIDTH                = 1
+   )
+  (
+   // System Signals
+   input  wire                          ACLK,
+   input  wire                          ARESETN,
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_AWADDR,
+   input  wire [3-1:0]                  S_AXI_AWPROT,
+   input  wire                          S_AXI_AWVALID,
+   output wire                          S_AXI_AWREADY,
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_DATA_WIDTH-1:0]   S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
+   input  wire                          S_AXI_WVALID,
+   output wire                          S_AXI_WREADY,
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     S_AXI_BID,
+   output wire [2-1:0]                  S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]  S_AXI_BUSER,    // Constant =0
+   output wire                          S_AXI_BVALID,
+   input  wire                          S_AXI_BREADY,
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_ARID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_ARADDR,
+   input  wire [3-1:0]                  S_AXI_ARPROT,
+   input  wire                          S_AXI_ARVALID,
+   output wire                          S_AXI_ARREADY,
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     S_AXI_RID,
+   output wire [C_AXI_DATA_WIDTH-1:0]   S_AXI_RDATA,
+   output wire [2-1:0]                  S_AXI_RRESP,
+   output wire                          S_AXI_RLAST,    // Constant =1
+   output wire [C_AXI_RUSER_WIDTH-1:0]  S_AXI_RUSER,    // Constant =0
+   output wire                          S_AXI_RVALID,
+   input  wire                          S_AXI_RREADY,
+   
+   // Master Interface Write Address Port
+   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_AWADDR,
+   output wire [3-1:0]                  M_AXI_AWPROT,
+   output wire                          M_AXI_AWVALID,
+   input  wire                          M_AXI_AWREADY,
+   // Master Interface Write Data Ports
+   output wire [C_AXI_DATA_WIDTH-1:0]   M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
+   output wire                          M_AXI_WVALID,
+   input  wire                          M_AXI_WREADY,
+   // Master Interface Write Response Ports
+   input  wire [2-1:0]                  M_AXI_BRESP,
+   input  wire                          M_AXI_BVALID,
+   output wire                          M_AXI_BREADY,
+   // Master Interface Read Address Port
+   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_ARADDR,
+   output wire [3-1:0]                  M_AXI_ARPROT,
+   output wire                          M_AXI_ARVALID,
+   input  wire                          M_AXI_ARREADY,
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_DATA_WIDTH-1:0]   M_AXI_RDATA,
+   input  wire [2-1:0]                  M_AXI_RRESP,
+   input  wire                          M_AXI_RVALID,
+   output wire                          M_AXI_RREADY
+  );
+
+  wire s_awvalid_i;
+  wire s_arvalid_i;
+  wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
+
+  // Arbiter
+  reg read_active;
+  reg write_active;
+  reg busy;
+
+  wire read_req;
+  wire write_req;
+  wire read_complete;
+  wire write_complete;
+  
+  reg [1:0] areset_d; // Reset delay register
+  always @(posedge ACLK) begin
+    areset_d <= {areset_d[0], ~ARESETN};
+  end
+  
+  assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
+  assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
+
+  assign read_req  = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
+  assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
+
+  assign read_complete  = M_AXI_RVALID & S_AXI_RREADY;
+  assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
+
+  always @(posedge ACLK) begin : arbiter_read_ff
+    if (|areset_d)
+      read_active <= 1\'b0;
+    else if (read_complete)
+      read_active <= 1\'b0;
+    else if (read_req)
+      read_active <= 1\'b1;
+  end
+
+  always @(posedge ACLK) begin : arbiter_write_ff
+    if (|areset_d)
+      write_active <= 1\'b0;
+    else if (write_complete)
+      write_active <= 1\'b0;
+    else if (write_req)
+      write_active <= 1\'b1;
+  end
+
+  always @(posedge ACLK) begin : arbiter_busy_ff
+    if (|areset_d)
+      busy <= 1\'b0;
+    else if (read_complete | write_complete)
+      busy <= 1\'b0;
+    else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
+      busy <= 1\'b1;
+  end
+
+  assign M_AXI_ARVALID = read_req;
+  assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
+
+  assign M_AXI_AWVALID = write_req;
+  assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
+
+  assign M_AXI_RREADY  = S_AXI_RREADY & read_active;
+  assign S_AXI_RVALID  = M_AXI_RVALID & read_active;
+
+  assign M_AXI_BREADY  = S_AXI_BREADY & write_active;
+  assign S_AXI_BVALID  = M_AXI_BVALID & write_active;
+
+  // Address multiplexer
+  assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
+
+  // Id multiplexer and flip-flop
+  reg [C_AXI_ID_WIDTH-1:0] s_axid;
+
+  always @(posedge ACLK) begin : axid
+    if      (read_req)  s_axid <= S_AXI_ARID;
+    else if (write_req) s_axid <= S_AXI_AWID;
+  end
+
+  assign S_AXI_BID = s_axid;
+  assign S_AXI_RID = s_axid;
+
+  assign M_AXI_AWADDR = m_axaddr;
+  assign M_AXI_ARADDR = m_axaddr;
+
+
+  // Feed-through signals
+  assign S_AXI_WREADY   = M_AXI_WREADY & ~|areset_d;
+  assign S_AXI_BRESP    = M_AXI_BRESP;
+  assign S_AXI_RDATA    = M_AXI_RDATA;
+  assign S_AXI_RRESP    = M_AXI_RRESP;
+  assign S_AXI_RLAST    = 1\'b1;
+  assign S_AXI_BUSER    = {C_AXI_BUSER_WIDTH{1\'b0}};
+  assign S_AXI_RUSER    = {C_AXI_RUSER_WIDTH{1\'b0}};
+
+  assign M_AXI_AWPROT   = S_AXI_AWPROT;
+  assign M_AXI_WVALID   = S_AXI_WVALID & ~|areset_d;
+  assign M_AXI_WDATA    = S_AXI_WDATA;
+  assign M_AXI_WSTRB    = S_AXI_WSTRB;
+  assign M_AXI_ARPROT   = S_AXI_ARPROT;
+
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Read Data Response AXI3 Slave Converter
+// Forwards and re-assembles split transactions.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   r_axi3_conv
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_r_axi3_conv #
+  (
+   parameter C_FAMILY                            = ""none"",
+   parameter integer C_AXI_ID_WIDTH              = 1,
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_DATA_WIDTH            = 32,
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
+   parameter integer C_AXI_RUSER_WIDTH           = 1,
+   parameter integer C_SUPPORT_SPLITTING              = 1,
+                       // Implement transaction splitting logic.
+                       // Disabled whan all connected masters are AXI3 and have same or narrower data width.
+   parameter integer C_SUPPORT_BURSTS                 = 1
+                       // Disabled when all connected masters are AxiLite,
+                       //   allowing logic to be simplified.
+   )
+  (
+   // System Signals
+   input wire ACLK,
+   input wire ARESET,
+
+   // Command Interface
+   input  wire                              cmd_valid,
+   input  wire                              cmd_split,
+   output wire                              cmd_ready,
+   
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID,
+   output wire [C_AXI_DATA_WIDTH-1:0]  S_AXI_RDATA,
+   output wire [2-1:0]                 S_AXI_RRESP,
+   output wire                         S_AXI_RLAST,
+   output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
+   output wire                         S_AXI_RVALID,
+   input  wire                         S_AXI_RREADY,
+   
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]    M_AXI_RID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]  M_AXI_RDATA,
+   input  wire [2-1:0]                 M_AXI_RRESP,
+   input  wire                         M_AXI_RLAST,
+   input  wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
+   input  wire                         M_AXI_RVALID,
+   output wire                         M_AXI_RREADY
+   );
+
+   
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for packing levels.
+  localparam [2-1:0] C_RESP_OKAY        = 2\'b00;
+  localparam [2-1:0] C_RESP_EXOKAY      = 2\'b01;
+  localparam [2-1:0] C_RESP_SLVERROR    = 2\'b10;
+  localparam [2-1:0] C_RESP_DECERR      = 2\'b11;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Throttling help signals.
+  wire                            cmd_ready_i;
+  wire                            pop_si_data;
+  wire                            si_stalling;
+  
+  // Internal MI-side control signals.
+  wire                            M_AXI_RREADY_I;
+   
+  // Internal signals for SI-side.
+  wire [C_AXI_ID_WIDTH-1:0]       S_AXI_RID_I;
+  wire [C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA_I;
+  wire [2-1:0]                    S_AXI_RRESP_I;
+  wire                            S_AXI_RLAST_I;
+  wire [C_AXI_RUSER_WIDTH-1:0]    S_AXI_RUSER_I;
+  wire                            S_AXI_RVALID_I;
+  wire                            S_AXI_RREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle interface handshaking:
+  //
+  // Forward data from MI-Side to SI-Side while a command is available. When
+  // the transaction has completed the command is popped from the Command FIFO.
+  // 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Pop word from SI-side.
+  assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
+  assign M_AXI_RREADY   = M_AXI_RREADY_I;
+  
+  // Indicate when there is data available @ SI-side.
+  assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
+  
+  // Get SI-side data.
+  assign pop_si_data    = S_AXI_RVALID_I & S_AXI_RREADY_I;
+  
+  // Signal that the command is done (so that it can be poped from command queue).
+  assign cmd_ready_i    = cmd_valid & pop_si_data & M_AXI_RLAST;
+  assign cmd_ready      = cmd_ready_i;
+  
+  // Detect when MI-side is stalling.
+  assign si_stalling    = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Simple AXI signal forwarding:
+  // 
+  // USER, ID, DATA and RRESP passes through untouched.
+  // 
+  // LAST has to be filtered to remove any intermediate LAST (due to split 
+  // trasactions). LAST is only removed for the first parts of a split 
+  // transaction. When splitting is unsupported is the LAST filtering completely
+  // completely removed.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Calculate last, i.e. mask from split transactions.
+  assign S_AXI_RLAST_I  = M_AXI_RLAST & 
+                          ( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
+  
+  // Data is passed through.
+  assign S_AXI_RID_I    = M_AXI_RID;
+  assign S_AXI_RUSER_I  = M_AXI_RUSER;
+  assign S_AXI_RDATA_I  = M_AXI_RDATA;
+  assign S_AXI_RRESP_I  = M_AXI_RRESP;
+      
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // SI-side output handling
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+// TODO: registered?  
+  assign S_AXI_RREADY_I = S_AXI_RREADY;
+  assign S_AXI_RVALID   = S_AXI_RVALID_I;
+  assign S_AXI_RID      = S_AXI_RID_I;
+  assign S_AXI_RDATA    = S_AXI_RDATA_I;
+  assign S_AXI_RRESP    = S_AXI_RRESP_I;
+  assign S_AXI_RLAST    = S_AXI_RLAST_I;
+  assign S_AXI_RUSER    = S_AXI_RUSER_I;
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Data AXI3 Slave Converter
+// Forward and split transactions as required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   w_axi3_conv
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_w_axi3_conv #
+  (
+   parameter C_FAMILY                            = ""none"",
+   parameter integer C_AXI_ID_WIDTH              = 1,
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_DATA_WIDTH            = 32,
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
+   parameter integer C_AXI_WUSER_WIDTH           = 1,
+   parameter integer C_SUPPORT_SPLITTING              = 1,
+                       // Implement transaction splitting logic.
+                       // Disabled whan all connected masters are AXI3 and have same or narrower data width.
+   parameter integer C_SUPPORT_BURSTS                 = 1
+                       // Disabled when all connected masters are AxiLite,
+                       //   allowing logic to be simplified.
+   )
+  (
+   // System Signals
+   input wire ACLK,
+   input wire ARESET,
+
+   // Command Interface
+   input  wire                              cmd_valid,
+   input  wire [C_AXI_ID_WIDTH-1:0]         cmd_id,
+   input  wire [4-1:0]                      cmd_length,
+   output wire                              cmd_ready,
+   
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_DATA_WIDTH-1:0]   S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
+   input  wire                          S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]  S_AXI_WUSER,
+   input  wire                          S_AXI_WVALID,
+   output wire                          S_AXI_WREADY,
+   
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]   M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
+   output wire                          M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]  M_AXI_WUSER,
+   output wire                          M_AXI_WVALID,
+   input  wire                          M_AXI_WREADY
+   );
+
+   
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+
+  // Burst length handling.
+  reg                             first_mi_word;
+  reg  [8-1:0]                    length_counter_1;
+  reg  [8-1:0]                    length_counter;
+  wire [8-1:0]                    next_length_counter;
+  wire                            last_beat;
+  wire                            last_word;
+  
+  // Throttling help signals.
+  wire                            cmd_ready_i;
+  wire                            pop_mi_data;
+  wire                            mi_stalling;
+  
+  // Internal SI side control signals.
+  wire                            S_AXI_WREADY_I;
+  
+  // Internal signals for MI-side.
+  wire [C_AXI_ID_WIDTH-1:0]       M_AXI_WID_I;
+  wire [C_AXI_DATA_WIDTH-1:0]     M_AXI_WDATA_I;
+  wire [C_AXI_DATA_WIDTH/8-1:0]   M_AXI_WSTRB_I;
+  wire                            M_AXI_WLAST_I;
+  wire [C_AXI_WUSER_WIDTH-1:0]    M_AXI_WUSER_I;
+  wire                            M_AXI_WVALID_I;
+  wire                            M_AXI_WREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle interface handshaking:
+  // 
+  // Forward data from SI-Side to MI-Side while a command is available. When
+  // the transaction has completed the command is popped from the Command FIFO.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+                          
+  // Pop word from SI-side.
+  assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
+  assign S_AXI_WREADY   = S_AXI_WREADY_I;
+  
+  // Indicate when there is data available @ MI-side.
+  assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
+  
+  // Get MI-side data.
+  assign pop_mi_data    = M_AXI_WVALID_I & M_AXI_WREADY_I;
+  
+  // Signal that the command is done (so that it can be poped from command queue).
+  assign cmd_ready_i    = cmd_valid & pop_mi_data & last_word;
+  assign cmd_ready      = cmd_ready_i;
+  
+  // Detect when MI-side is stalling.
+  assign mi_stalling    = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Keep track of data forwarding:
+  // 
+  // On the first cycle of the transaction is the length taken from the Command
+  // FIFO. The length is decreased until 0 is reached which indicates last data 
+  // word.
+  //
+  // If bursts are unsupported will all data words be the last word, each one
+  // from a separate transaction.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Select command length or counted length.
+  always @ *
+  begin
+    if ( first_mi_word )
+      length_counter = cmd_length;
+    else
+      length_counter = length_counter_1;
+  end
+  
+  // Calculate next length counter value.
+  assign next_length_counter = length_counter - 1\'b1;
+  
+  // Keep track of burst length.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      first_mi_word    <= 1\'b1;
+      length_counter_1 <= 4\'b0;
+    end else begin
+      if ( pop_mi_data ) begin
+        if ( M_AXI_WLAST_I ) begin
+          first_mi_word    <= 1\'b1;
+        end else begin
+          first_mi_word    <= 1\'b0;
+        end
+      
+        length_counter_1 <= next_length_counter;
+      end
+    end
+  end
+  
+  // Detect last beat in a burst.
+  assign last_beat = ( length_counter == 4\'b0 );
+  
+  // Determine if this last word that shall be extracted from this SI-side word.
+  assign last_word = ( last_beat ) |
+                     ( C_SUPPORT_BURSTS == 0 );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Select the SI-side word to write.
+  // 
+  // Most information can be reused directly (DATA, STRB, ID and USER).
+  // ID is taken from the Command FIFO.
+  //
+  // Split transactions needs to insert new LAST transactions. So to simplify
+  // is the LAST signal always generated.
+  //
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // ID and USER is copied from the SI word to all MI word transactions.
+  assign M_AXI_WUSER_I  = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1\'b0}};
+  
+  // Data has to be multiplexed.
+  assign M_AXI_WDATA_I  = S_AXI_WDATA;
+  assign M_AXI_WSTRB_I  = S_AXI_WSTRB;
+  
+  // ID is taken directly from the command queue.
+  assign M_AXI_WID_I    = cmd_id;
+  
+  // Handle last flag, i.e. set for MI-side last word.
+  assign M_AXI_WLAST_I  = last_word;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // MI-side output handling
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+// TODO: registered?
+  assign M_AXI_WID      = M_AXI_WID_I;
+  assign M_AXI_WDATA    = M_AXI_WDATA_I;
+  assign M_AXI_WSTRB    = M_AXI_WSTRB_I;
+  assign M_AXI_WLAST    = M_AXI_WLAST_I;
+  assign M_AXI_WUSER    = M_AXI_WUSER_I;
+  assign M_AXI_WVALID   = M_AXI_WVALID_I;
+  assign M_AXI_WREADY_I = M_AXI_WREADY;
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Data Response Down-Sizer
+// Collect MI-side responses and set the SI-side response to the most critical
+// level (in descending order):
+//    DECERR, SLVERROR and OKAY.
+// EXOKAY cannot occur for split transactions. 
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   wr_upsizer
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b_downsizer #
+  (
+   parameter         C_FAMILY                         = ""none"", 
+                       // FPGA Family. Current version: virtex6 or spartan6.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of converter.
+                       // Range: >= 1.
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,
+                       // 1 = Propagate all USER signals, 0 = Don\xef\xbf\xbdt propagate.
+   parameter integer C_AXI_BUSER_WIDTH                = 1
+                       // Width of BUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                                    ARESET,
+   input  wire                                                    ACLK,
+
+   // Command Interface
+   input  wire                              cmd_valid,
+   input  wire                              cmd_split,
+   input  wire [4-1:0]                      cmd_repeat,
+   output wire                              cmd_ready,
+   
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]           S_AXI_BID,
+   output wire [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                                    S_AXI_BVALID,
+   input  wire                                                    S_AXI_BREADY,
+
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]          M_AXI_BID,
+   input  wire [2-1:0]                         M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,
+   input  wire                                                   M_AXI_BVALID,
+   output wire                                                   M_AXI_BREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for packing levels.
+  localparam [2-1:0] C_RESP_OKAY        = 2\'b00;
+  localparam [2-1:0] C_RESP_EXOKAY      = 2\'b01;
+  localparam [2-1:0] C_RESP_SLVERROR    = 2\'b10;
+  localparam [2-1:0] C_RESP_DECERR      = 2\'b11;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Throttling help signals.
+  wire                            cmd_ready_i;
+  wire                            pop_mi_data;
+  wire                            mi_stalling;
+  
+  // Repeat handling related.
+  reg  [4-1:0]                    repeat_cnt_pre;
+  reg  [4-1:0]                    repeat_cnt;
+  wire [4-1:0]                    next_repeat_cnt;
+  reg                             first_mi_word;
+  wire                            last_word;
+  
+  // Ongoing split transaction.
+  wire                            load_bresp;
+  wire                            need_to_update_bresp;
+  reg  [2-1:0]                    S_AXI_BRESP_ACC;
+  
+  // Internal signals for MI-side.
+  wire                            M_AXI_BREADY_I;
+  
+  // Internal signals for SI-side.
+  wire [C_AXI_ID_WIDTH-1:0]       S_AXI_BID_I;
+  reg  [2-1:0]                    S_AXI_BRESP_I;
+  wire [C_AXI_BUSER_WIDTH-1:0]    S_AXI_BUSER_I;
+  wire                            S_AXI_BVALID_I;
+  wire                            S_AXI_BREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle interface handshaking:
+  // 
+  // The MI-side BRESP is popped when at once for split transactions, except 
+  // for the last cycle that behaves like a ""normal"" transaction.
+  // A ""normal"" BRESP is popped once the SI-side is able to use it,
+  // 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Pop word from MI-side.
+  assign M_AXI_BREADY_I = M_AXI_BVALID & ~mi_stalling;
+  assign M_AXI_BREADY   = M_AXI_BREADY_I;
+  
+  // Indicate when there is a BRESP available @ SI-side.
+  assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
+  
+  // Get MI-side data.
+  assign pop_mi_data    = M_AXI_BVALID & M_AXI_BREADY_I;
+  
+  // Signal that the command is done (so that it can be poped from command queue).
+  assign cmd_ready_i    = cmd_valid & pop_mi_data & last_word;
+  assign cmd_ready      = cmd_ready_i;
+  
+  // Detect when MI-side is stalling.
+  assign mi_stalling    = (~S_AXI_BREADY_I & last_word);
+                          
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle the accumulation of BRESP.
+  // 
+  // Forward the accumulated or MI-side BRESP value depending on state:
+  //  * MI-side BRESP is forwarded untouched when it is a non split cycle.
+  //    (MI-side BRESP value is also used when updating the accumulated for
+  //     the last access during a split access).
+  //  * The accumulated BRESP is for a split transaction.
+  // 
+  // The accumulated BRESP register is updated for each MI-side response that 
+  // is used.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Force load accumulated BRESPs to first value
+  assign load_bresp           = (cmd_split & first_mi_word);
+  
+  // Update if more critical.
+  assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
+  
+  // Select accumultated or direct depending on setting.
+  always @ *
+  begin
+    if ( cmd_split ) begin
+      if ( load_bresp || need_to_update_bresp ) begin
+        S_AXI_BRESP_I = M_AXI_BRESP;
+      end else begin
+        S_AXI_BRESP_I = S_AXI_BRESP_ACC;
+      end
+    end else begin
+      S_AXI_BRESP_I = M_AXI_BRESP;
+    end
+  end
+  
+  // Accumulate MI-side BRESP.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      S_AXI_BRESP_ACC <= C_RESP_OKAY;
+    end else begin
+      if ( pop_mi_data ) begin
+        S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Keep track of BRESP repeat counter.
+  //
+  // Last BRESP word is either:
+  //  * The first and only word when not merging.
+  //  * The last value when merging.
+  // 
+  // The internal counter is taken from the external command interface during
+  // the first response when merging. The counter is updated each time a
+  // BRESP is popped from the MI-side interface.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Determine last BRESP cycle.
+  assign last_word  = ( ( repeat_cnt == 4\'b0 ) & ~first_mi_word ) | 
+                      ~cmd_split;
+  
+  // Select command reapeat or counted repeat value.
+  always @ *
+  begin
+    if ( first_mi_word ) begin
+      repeat_cnt_pre  =  cmd_repeat;
+    end else begin
+      repeat_cnt_pre  =  repeat_cnt;
+    end
+  end
+  
+  // Calculate next repeat counter value.
+  assign next_repeat_cnt  = repeat_cnt_pre - 1\'b1;
+  
+  // Keep track of the repeat count.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      repeat_cnt    <= 4\'b0;
+      first_mi_word <= 1\'b1;
+    end else begin
+      if ( pop_mi_data ) begin
+        repeat_cnt    <= next_repeat_cnt;
+        first_mi_word <= last_word;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // BID Handling
+  /////////////////////////////////////////////////////////////////////////////
+  
+  assign S_AXI_BID_I  = M_AXI_BID;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // USER Data bits
+  // 
+  // The last USER bits are simply taken from the last BRESP that is merged.
+  // Ground USER bits when unused.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Select USER bits.
+  assign S_AXI_BUSER_I = {C_AXI_BUSER_WIDTH{1\'b0}};
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // SI-side output handling
+  /////////////////////////////////////////////////////////////////////////////
+// TODO: registered?  
+  assign S_AXI_BID      = S_AXI_BID_I;
+  assign S_AXI_BRESP    = S_AXI_BRESP_I;
+  assign S_AXI_BUSER    = S_AXI_BUSER_I;
+  assign S_AXI_BVALID   = S_AXI_BVALID_I;
+  assign S_AXI_BREADY_I = S_AXI_BREADY;
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: decerr_slave.v
+//
+// Description: 
+//   Phantom slave interface used to complete W, R and B channel transfers when an
+//   erroneous transaction is trapped in the crossbar.
+//--------------------------------------------------------------------------
+//
+// Structure:
+//    decerr_slave
+//    
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_decerr_slave #
+  (
+   parameter integer C_AXI_ID_WIDTH           = 1,
+   parameter integer C_AXI_DATA_WIDTH         = 32,
+   parameter integer C_AXI_BUSER_WIDTH        = 1,
+   parameter integer C_AXI_RUSER_WIDTH        = 1,
+   parameter integer C_AXI_PROTOCOL           = 0,
+   parameter integer C_RESP                   = 2\'b11'b',
+   parameter integer C_IGNORE_ID              = 0
+   )
+  (
+   input   wire                                         ACLK,
+   input   wire                                         ARESETN,
+   input   wire [(C_AXI_ID_WIDTH-1):0]                  S_AXI_AWID,
+   input   wire                                         S_AXI_AWVALID,
+   output  wire                                         S_AXI_AWREADY,
+   input   wire                                         S_AXI_WLAST,
+   input   wire                                         S_AXI_WVALID,
+   output  wire                                         S_AXI_WREADY,
+   output  wire [(C_AXI_ID_WIDTH-1):0]                  S_AXI_BID,
+   output  wire [1:0]                                   S_AXI_BRESP,
+   output  wire [C_AXI_BUSER_WIDTH-1:0]                 S_AXI_BUSER,
+   output  wire                                         S_AXI_BVALID,
+   input   wire                                         S_AXI_BREADY,
+   input   wire [(C_AXI_ID_WIDTH-1):0]                  S_AXI_ARID,
+   input   wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]   S_AXI_ARLEN,
+   input   wire                                         S_AXI_ARVALID,
+   output  wire                                         S_AXI_ARREADY,
+   output  wire [(C_AXI_ID_WIDTH-1):0]                  S_AXI_RID,
+   output  wire [(C_AXI_DATA_WIDTH-1):0]                S_AXI_RDATA,
+   output  wire [1:0]                                   S_AXI_RRESP,
+   output  wire [C_AXI_RUSER_WIDTH-1:0]                 S_AXI_RUSER,
+   output  wire                                         S_AXI_RLAST,
+   output  wire                                         S_AXI_RVALID,
+   input   wire                                         S_AXI_RREADY
+   );
+   
+  reg s_axi_awready_i;
+  reg s_axi_wready_i;
+  reg s_axi_bvalid_i;
+  reg s_axi_arready_i;
+  reg s_axi_rvalid_i;
+  
+  localparam P_WRITE_IDLE = 2\'b00;
+  localparam P_WRITE_DATA = 2\'b01;
+  localparam P_WRITE_RESP = 2\'b10;
+  localparam P_READ_IDLE  = 2\'b00;
+  localparam P_READ_START = 2\'b01;
+  localparam P_READ_DATA  = 2\'b10;
+  localparam integer  P_AXI4 = 0;
+  localparam integer  P_AXI3 = 1;
+  localparam integer  P_AXILITE = 2;
+   
+  assign S_AXI_BRESP = C_RESP;
+  assign S_AXI_RRESP = C_RESP;
+  assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1\'b0}};
+  assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1\'b0}};
+  assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1\'b0}};
+  assign S_AXI_AWREADY = s_axi_awready_i;
+  assign S_AXI_WREADY = s_axi_wready_i;
+  assign S_AXI_BVALID = s_axi_bvalid_i;
+  assign S_AXI_ARREADY = s_axi_arready_i;
+  assign S_AXI_RVALID = s_axi_rvalid_i;
+  
+  generate
+  if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
+    
+    reg s_axi_rvalid_en;
+    assign S_AXI_RLAST = 1\'b1;
+    assign S_AXI_BID = 0;
+    assign S_AXI_RID = 0;
+    
+    always @(posedge ACLK) begin
+      if (~ARESETN) begin
+        s_axi_awready_i <= 1\'b0;
+        s_axi_wready_i <= 1\'b0;
+        s_axi_bvalid_i <= 1\'b0;
+      end else begin
+        if (s_axi_bvalid_i) begin
+          if (S_AXI_BREADY) begin
+            s_axi_bvalid_i <= 1\'b0;
+            s_axi_awready_i <= 1\'b1;
+          end
+        end else if (S_AXI_WVALID & s_axi_wready_i) begin
+            s_axi_wready_i <= 1\'b0;
+            s_axi_bvalid_i <= 1\'b1;
+        end else if (S_AXI_AWVALID & s_axi_awready_i) begin
+          s_axi_awready_i <= 1\'b0;
+          s_axi_wready_i <= 1\'b1;
+        end else begin
+          s_axi_awready_i <= 1\'b1;
+        end
+      end
+    end
+           
+    always @(posedge ACLK) begin
+      if (~ARESETN) begin
+        s_axi_arready_i <= 1\'b0;
+        s_axi_rvalid_i <= 1\'b0;
+        s_axi_rvalid_en <= 1\'b0;
+      end else begin
+        if (s_axi_rvalid_i) begin
+          if (S_AXI_RREADY) begin
+            s_axi_rvalid_i <= 1\'b0;
+            s_axi_arready_i <= 1\'b1;
+          end
+        end else if (s_axi_rvalid_en) begin
+          s_axi_rvalid_en <= 1\'b0;
+          s_axi_rvalid_i <= 1\'b1;
+        end else if (S_AXI_ARVALID & s_axi_arready_i) begin
+          s_axi_arready_i <= 1\'b0;
+          s_axi_rvalid_en <= 1\'b1;
+        end else begin
+          s_axi_arready_i <= 1\'b1;
+        end
+      end
+    end
+        
+  end else begin : gen_axi
+  
+    reg s_axi_rlast_i;
+    reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
+    reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
+    reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
+    reg [1:0] write_cs;
+    reg [1:0] read_cs;
+  
+    assign S_AXI_RLAST = s_axi_rlast_i;
+    assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
+    assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
+  
+    always @(posedge ACLK) begin
+      if (~ARESETN) begin
+        write_cs <= P_WRITE_IDLE;
+        s_axi_awready_i <= 1\'b0;
+        s_axi_wready_i <= 1\'b0;
+        s_axi_bvalid_i <= 1\'b0;
+        s_axi_bid_i <= 0;
+      end else begin
+        case (write_cs) 
+          P_WRITE_IDLE: 
+            begin
+              if (S_AXI_AWVALID & s_axi_awready_i) begin
+                s_axi_awready_i <= 1\'b0;
+                if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
+                s_axi_wready_i <= 1\'b1;
+                write_cs <= P_WRITE_DATA;
+              end else begin
+                s_axi_awready_i <= 1\'b1;
+              end
+            end
+          P_WRITE_DATA:
+            begin
+              if (S_AXI_WVALID & S_AXI_WLAST) begin
+                s_axi_wready_i <= 1\'b0;
+                s_axi_bvalid_i <= 1\'b1;
+                write_cs <= P_WRITE_RESP;
+              end
+            end
+          P_WRITE_RESP:
+            begin
+              if (S_AXI_BREADY) begin
+                s_axi_bvalid_i <= 1\'b0;
+                s_axi_awready_i <= 1\'b1;
+                write_cs <= P_WRITE_IDLE;
+              end
+            end
+        endcase
+      end
+    end
+  
+    always @(posedge ACLK) begin
+      if (~ARESETN) begin
+        read_cs <= P_READ_IDLE;
+        s_axi_arready_i <= 1\'b0;
+        s_axi_rvalid_i <= 1\'b0;
+        s_axi_rlast_i <= 1\'b0;
+        s_axi_rid_i <= 0;
+        read_cnt <= 0;
+      end else begin
+        case (read_cs) 
+          P_READ_IDLE: 
+            begin
+              if (S_AXI_ARVALID & s_axi_arready_i) begin
+                s_axi_arready_i <= 1\'b0;
+                if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
+                read_cnt <= S_AXI_ARLEN;
+                s_axi_rlast_i <= (S_AXI_ARLEN == 0);
+                read_cs <= P_READ_START;
+              end else begin
+                s_axi_arready_i <= 1\'b1;
+              end
+            end
+          P_READ_START:
+            begin
+              s_axi_rvalid_i <= 1\'b1;
+              read_cs <= P_READ_DATA;
+            end
+          P_READ_DATA:
+            begin
+              if (S_AXI_RREADY) begin
+                if (read_cnt == 0) begin
+                  s_axi_rvalid_i <= 1\'b0;
+                  s_axi_rlast_i <= 1\'b0;
+                  s_axi_arready_i <= 1\'b1;
+                  read_cs <= P_READ_IDLE;
+                end else begin
+                  if (read_cnt == 1) begin
+                    s_axi_rlast_i <= 1\'b1;
+                  end
+                  read_cnt <= read_cnt - 1;
+                end
+              end
+            end
+        endcase
+      end
+    end
+  
+  end  
+  endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+//-----------------------------------------------
+// This is the simplest form of inferring the
+// simple/SRL(16/32)CE in a Xilinx FPGA.
+//-----------------------------------------------
+`timescale 1ns / 100ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_simple_fifo #
+(
+  parameter C_WIDTH  = 8,
+  parameter C_AWIDTH = 4,
+  parameter C_DEPTH  = 16
+)
+(
+  input  wire               clk,       // Main System Clock  (Sync FIFO)
+  input  wire               rst,       // FIFO Counter Reset (Clk
+  input  wire               wr_en,     // FIFO Write Enable  (Clk)
+  input  wire               rd_en,     // FIFO Read Enable   (Clk)
+  input  wire [C_WIDTH-1:0] din,       // FIFO Data Input    (Clk)
+  output wire [C_WIDTH-1:0] dout,      // FIFO Data Output   (Clk)
+  output wire               a_full,
+  output wire               full,      // FIFO FULL Status   (Clk)
+  output wire               a_empty,
+  output wire               empty      // FIFO EMPTY Status  (Clk)
+);
+
+///////////////////////////////////////
+// FIFO Local Parameters
+///////////////////////////////////////
+localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
+localparam [C_AWIDTH-1:0] C_EMPTY_PRE =  (0);
+localparam [C_AWIDTH-1:0] C_FULL  = C_EMPTY-1;
+localparam [C_AWIDTH-1:0] C_FULL_PRE  = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
+ 
+///////////////////////////////////////
+// FIFO Internal Signals
+///////////////////////////////////////
+reg [C_WIDTH-1:0]  memory [C_DEPTH-1:0];
+reg [C_AWIDTH-1:0] cnt_read;
+  // synthesis attribute MAX_FANOUT of cnt_read is 10; 
+
+///////////////////////////////////////
+// Main simple FIFO Array
+///////////////////////////////////////
+always @(posedge clk) begin : BLKSRL
+integer i;
+  if (wr_en) begin
+    for (i = 0; i < C_DEPTH-1; i = i + 1) begin
+      memory[i+1] <= memory[i];
+    end
+    memory[0] <= din;
+  end
+end
+
+///////////////////////////////////////
+// Read Index Counter
+// Up/Down Counter
+//  *** Notice that there is no ***
+//  *** OVERRUN protection.     ***
+///////////////////////////////////////
+always @(posedge clk) begin
+  if (rst) cnt_read <= C_EMPTY;
+  else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1\'b1;
+  else if (!wr_en &  rd_en) cnt_read <= cnt_read - 1\'b1;
+end
+
+///////////////////////////////////////
+// Status Flags / Outputs
+// These could be registered, but would
+// increase logic in order to pre-decode
+// FULL/EMPTY status.
+///////////////////////////////////////
+assign full  = (cnt_read == C_FULL);
+assign empty = (cnt_read == C_EMPTY);
+assign a_full  = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
+assign a_empty = (cnt_read == C_EMPTY_PRE);
+
+assign dout  = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
+
+endmodule // axi_protocol_converter_v2_1_11_b2s_simple_fifo
+
+`default_nettype wire
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axi_protocol_converter_v2_1_11_b2s_wrap_cmd.v
+//
+///////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_wrap_cmd #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+                    // Width of AxADDR
+                    // Range: 32.
+  parameter integer C_AXI_ADDR_WIDTH            = 32
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations     
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                                 clk           , 
+  input  wire                                 reset         , 
+  input  wire [C_AXI_ADDR_WIDTH-1:0]          axaddr        , 
+  input  wire [7:0]                           axlen         , 
+  input  wire [2:0]                           axsize        , 
+  // axhandshake = axvalid & axready
+  input  wire                                 axhandshake   , 
+  output wire [C_AXI_ADDR_WIDTH-1:0]          cmd_byte_addr , 
+
+  // Connections to/from fsm module
+  // signal to increment to the next mc transaction 
+  input  wire                                 next          , 
+  // signal to the fsm there is another transaction required
+  output reg                                  next_pending 
+
+);
+////////////////////////////////////////////////////////////////////////////////
+// Wire and register declarations
+////////////////////////////////////////////////////////////////////////////////
+reg                         sel_first;
+wire [11:0]                 axaddr_i;
+wire [3:0]                  axlen_i;
+reg  [11:0]                 wrap_boundary_axaddr;
+reg  [3:0]                  axaddr_offset;
+reg  [3:0]                  wrap_second_len;
+reg  [11:0]                 wrap_boundary_axaddr_r;
+reg  [3:0]                  axaddr_offset_r;
+reg  [3:0]                  wrap_second_len_r;
+reg  [4:0]                  axlen_cnt;
+reg  [4:0]                  wrap_cnt_r;
+wire [4:0]                  wrap_cnt;
+reg  [11:0]                 axaddr_wrap;
+reg                         next_pending_r;
+
+localparam    L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+generate
+  if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
+    assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_wrap[11:0]};
+  end else begin : ADDR_4K
+    assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_wrap[11:0];
+  end
+endgenerate
+
+assign axaddr_i = axaddr[11:0];
+assign axlen_i = axlen[3:0];
+
+// Mask bits based on transaction length to get wrap boundary low address
+// Offset used to calculate the length of each transaction
+always @( * ) begin
+  if(axhandshake) begin
+    wrap_boundary_axaddr = axaddr_i & ~(axlen_i << axsize[1:0]);
+    axaddr_offset = axaddr_i[axsize[1:0] +: 4] & axlen_i;
+  end else begin
+    wrap_boundary_axaddr = wrap_boundary_axaddr_r;
+    axaddr_offset = axaddr_offset_r; 
+  end
+end
+
+//    case (axsize[1:0])
+//      2\'b00   : axaddr_offset = axaddr_i[4:0] & axlen_i;
+//      2\'b01   : axaddr_offset = axaddr_i[5:1] & axlen_i;
+//      2\'b10   : axaddr_offset = axaddr_i[6:2] & axlen_i;
+//      2\'b11   : axaddr_offset = axaddr_i[7:3] & axlen_i;
+//      default : axaddr_offset = axaddr_i[7:3] & axlen_i;
+//    endcase
+
+// The first and the second command from the wrap transaction could
+// be of odd length or even length with address offset. This will be 
+// an issue with BL8, extra transactions have to be issued.
+// Rounding up the length to account for extra transactions. 
+always @( * ) begin
+  if(axhandshake) begin
+    wrap_second_len = (axaddr_offset >0) ? axaddr_offset - 1 : 0;
+  end else begin
+    wrap_second_len = wrap_second_len_r;
+  end
+end
+
+// registering to be used in the combo logic. 
+always @(posedge clk) begin
+  wrap_boundary_axaddr_r <= wrap_boundary_axaddr;
+  axaddr_offset_r <= axaddr_offset;
+  wrap_second_len_r <= wrap_second_len;
+end
+   
+// determining if extra data is required for even offsets
+
+// wrap_cnt used to switch the address for first and second transaction.
+assign wrap_cnt = {1\'b0, wrap_second_len + {3\'b000, (|axaddr_offset)}}; 
+
+always @(posedge clk)
+  wrap_cnt_r <= wrap_cnt;
+
+always @(posedge clk) begin
+  if (axhandshake) begin
+    axaddr_wrap <= axaddr[11:0];
+  end if(next)begin
+    if(axlen_cnt == wrap_cnt_r) begin
+      axaddr_wrap <= wrap_boundary_axaddr_r;
+    end else begin
+      axaddr_wrap <= axaddr_wrap + (1 << axsize[1:0]);
+    end
+  end
+end 
+
+
+
+// Even numbber of transactions with offset, inc len by 2 for BL8
+always @(posedge clk) begin
+  if (axhandshake)begin
+    axlen_cnt <= axlen_i;
+    next_pending_r <= axlen_i >= 1;
+  end else if (next) begin
+    if (axlen_cnt > 1) begin
+      axlen_cnt <= axlen_cnt - 1;
+      next_pending_r <= (axlen_cnt - 1) >= 1;
+    end else begin
+      axlen_cnt <= 5\'d0;
+      next_pending_r <= 1\'b0;
+    end
+  end  
+end  
+
+always @( * ) begin
+  if (axhandshake)begin
+    next_pending = axlen_i >= 1;
+  end else if (next) begin
+    if (axlen_cnt > 1) begin
+      next_pending = (axlen_cnt - 1) >= 1;
+    end else begin
+      next_pending = 1\'b0;
+    end
+  end else begin
+    next_pending = next_pending_r;
+  end 
+end  
+
+// last and ignore signals to data channel. These signals are used for
+// BL8 to ignore and insert data for even len transactions with offset
+// and odd len transactions
+// For odd len transactions with no offset the last read is ignored and
+// last write is masked
+// For odd len transactions with offset the first read is ignored and
+// first write is masked
+// For even len transactions with offset the last & first read is ignored and
+// last& first  write is masked
+// For even len transactions no ingnores or masks. 
+
+
+// Indicates if we are on the first transaction of a mc translation with more
+// than 1 transaction.
+always @(posedge clk) begin
+  if (reset | axhandshake) begin
+    sel_first <= 1\'b1;
+  end else if (next) begin
+    sel_first <= 1\'b0;
+  end
+end
+
+endmodule
+`default_nettype wire
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axi_protocol_converter_v2_1_11_b2s_incr_cmd.v
+//
+///////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_incr_cmd #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+                    // Width of AxADDR
+                    // Range: 32.
+  parameter integer C_AXI_ADDR_WIDTH            = 32
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                                 clk           ,
+  input  wire                                 reset         ,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]          axaddr        ,
+  input  wire [7:0]                           axlen         ,
+  input  wire [2:0]                           axsize        ,
+  // axhandshake = axvalid & axready
+  input  wire                                 axhandshake   ,
+  output wire [C_AXI_ADDR_WIDTH-1:0]          cmd_byte_addr ,
+  // Connections to/from fsm module
+  // signal to increment to the next mc transaction
+  input  wire                                 next          ,
+  // signal to the fsm there is another transaction required
+  output reg                                  next_pending
+
+);
+////////////////////////////////////////////////////////////////////////////////
+// Wire and register declarations
+////////////////////////////////////////////////////////////////////////////////
+reg                           sel_first;
+reg  [11:0]                   axaddr_incr;
+reg  [8:0]                    axlen_cnt;
+reg                           next_pending_r;
+wire [3:0]                    axsize_shift;
+wire [11:0]                   axsize_mask;
+
+localparam    L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// calculate cmd_byte_addr
+generate
+  if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
+    assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_incr[11:0]};
+  end else begin : ADDR_4K
+    assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_incr[11:0];
+  end
+endgenerate
+
+assign axsize_shift = (1 << axsize[1:0]);
+assign axsize_mask  = ~(axsize_shift - 1\'b1);
+
+// Incremented version of axaddr
+always @(posedge clk) begin
+  if (sel_first) begin
+    if(~next) begin
+      axaddr_incr <= axaddr[11:0] & axsize_mask;
+    end else begin
+      axaddr_incr <= (axaddr[11:0] & axsize_mask) + axsize_shift;
+    end
+  end else if (next) begin
+    axaddr_incr <= axaddr_incr + axsize_shift;
+  end
+end
+
+always @(posedge clk) begin
+  if (axhandshake)begin
+     axlen_cnt <= axlen;
+     next_pending_r <= (axlen >= 1);
+  end else if (next) begin
+    if (axlen_cnt > 1) begin
+      axlen_cnt <= axlen_cnt - 1;
+      next_pending_r <= ((axlen_cnt - 1) >= 1);
+    end else begin
+      axlen_cnt <= 9\'d0;
+      next_pending_r <= 1\'b0;
+    end
+  end
+end
+
+always @( * ) begin
+  if (axhandshake)begin
+     next_pending = (axlen >= 1);
+  end else if (next) begin
+    if (axlen_cnt > 1) begin
+      next_pending = ((axlen_cnt - 1) >= 1);
+    end else begin
+      next_pending = 1\'b0;
+    end
+  end else begin
+    next_pending = next_pending_r;
+  end
+end
+
+// last and ignore signals to data channel. These signals are used for
+// BL8 to ignore and insert data for even len transactions with offset
+// and odd len transactions
+// For odd len transactions with no offset the last read is ignored and
+// last write is masked
+// For odd len transactions with offset the first read is ignored and
+// first write is masked
+// For even len transactions with offset the last & first read is ignored and
+// last& first  write is masked
+// For even len transactions no ingnores or masks.
+
+// Indicates if we are on the first transaction of a mc translation with more
+// than 1 transaction.
+always @(posedge clk) begin
+  if (reset | axhandshake) begin
+    sel_first <= 1\'b1;
+  end else if (next) begin
+    sel_first <= 1\'b0;
+  end
+end
+
+endmodule
+`default_nettype wire
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm.v
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                                 clk           ,
+  input  wire                                 reset         ,
+  output wire                                 s_awready       ,
+  input  wire                                 s_awvalid       ,
+  output wire                                 m_awvalid        ,
+  input  wire                                 m_awready      ,
+  // signal to increment to the next mc transaction
+  output wire                                 next          ,
+  // signal to the fsm there is another transaction required
+  input  wire                                 next_pending  ,
+  // Write Data portion has completed or Read FIFO has a slot available (not
+  // full)
+  output wire                                 b_push        ,
+  input  wire                                 b_full        ,
+  output wire                                 a_push
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+// States
+localparam SM_IDLE                = 2\'b00;
+localparam SM_CMD_EN              = 2\'b01;
+localparam SM_CMD_ACCEPTED        = 2\'b10;
+localparam SM_DONE_WAIT           = 2\'b11;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg [1:0]       state;
+// synthesis attribute MAX_FANOUT of state is 20;
+reg [1:0]       next_state;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+///////////////////////////////////////////////////////////////////////////////
+
+
+always @(posedge clk) begin
+  if (reset) begin
+    state <= SM_IDLE;
+  end else begin
+    state <= next_state;
+  end
+end
+
+// Next state transitions.
+always @( * )
+begin
+  next_state = state;
+  case (state)
+    SM_IDLE:
+      if (s_awvalid) begin
+        next_state = SM_CMD_EN;
+      end else
+        next_state = state;
+
+    SM_CMD_EN:
+      if (m_awready & next_pending)
+        next_state = SM_CMD_ACCEPTED;
+      else if (m_awready & ~next_pending & b_full)
+        next_state = SM_DONE_WAIT;
+      else if (m_awready & ~next_pending & ~b_full)
+        next_state = SM_IDLE;
+      else
+        next_state = state;
+
+    SM_CMD_ACCEPTED:
+      next_state = SM_CMD_EN;
+
+    SM_DONE_WAIT:
+      if (!b_full)
+        next_state = SM_IDLE;
+      else
+        next_state = state;
+
+      default:
+        next_state = SM_IDLE;
+  endcase
+end
+
+// Assign outputs based on current state.
+
+assign m_awvalid  = (state == SM_CMD_EN);
+
+assign next    = ((state == SM_CMD_ACCEPTED)
+                 | (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ;
+
+assign a_push  = (state == SM_IDLE);
+assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
+assign b_push  = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
+
+endmodule
+`default_nettype wire
+
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm.v
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                                 clk           ,
+  input  wire                                 reset         ,
+  output wire                                 s_arready       ,
+  input  wire                                 s_arvalid       ,
+  input  wire [7:0]                           s_arlen         ,
+  output wire                                 m_arvalid        ,
+  input  wire                                 m_arready      ,
+  // signal to increment to the next mc transaction
+  output wire                                 next          ,
+  // signal to the fsm there is another transaction required
+  input  wire                                 next_pending  ,
+  // Write Data portion has completed or Read FIFO has a slot available (not
+  // full)
+  input  wire                                 data_ready    ,
+  // status signal for w_channel when command is written.
+  output wire                                 a_push        ,
+  output wire                                 r_push
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+// States
+localparam SM_IDLE                = 2\'b00;
+localparam SM_CMD_EN              = 2\'b01;
+localparam SM_CMD_ACCEPTED        = 2\'b10;
+localparam SM_DONE                = 2\'b11;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg [1:0]       state;
+// synthesis attribute MAX_FANOUT of state is 20;
+reg [1:0]       state_r1;
+reg [1:0]       next_state;
+reg [7:0]       s_arlen_r;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+///////////////////////////////////////////////////////////////////////////////
+
+
+// register for timing
+always @(posedge clk) begin
+  if (reset) begin
+    state <= SM_IDLE;
+    state_r1 <= SM_IDLE;
+    s_arlen_r  <= 0;
+  end else begin
+    state <= next_state;
+    state_r1 <= state;
+    s_arlen_r  <= s_arlen;
+  end
+end
+
+// Next state transitions.
+always @( * ) begin
+  next_state = state;
+  case (state)
+    SM_IDLE:
+      if (s_arvalid & data_ready) begin
+        next_state = SM_CMD_EN;
+      end else begin
+        next_state = state;
+      end
+    SM_CMD_EN:
+    ///////////////////////////////////////////////////////////////////
+    // Drive m_arvalid downstream in this state
+      ///////////////////////////////////////////////////////////////////
+      //If there is no fifo space
+      if (~data_ready & m_arready & next_pending) begin
+        ///////////////////////////////////////////////////////////////////
+        //There is more to do, wait until data space is available drop valid
+        next_state = SM_CMD_ACCEPTED;
+      end else if (m_arready & ~next_pending)begin
+         next_state = SM_DONE;
+      end else if (m_arready & next_pending) begin
+        next_state = SM_CMD_EN;
+      end else begin
+        next_state = state;
+      end
+
+    SM_CMD_ACCEPTED:
+      if (data_ready) begin
+        next_state = SM_CMD_EN;
+      end else begin
+        next_state = state;
+      end
+
+    SM_DONE:
+        next_state = SM_IDLE;
+
+      default:
+        next_state = SM_IDLE;
+  endcase
+end
+
+// Assign outputs based on current state.
+
+assign m_arvalid  = (state == SM_CMD_EN);
+assign next    = m_arready && (state == SM_CMD_EN);
+assign         r_push  = next;
+assign a_push  = (state == SM_IDLE);
+assign s_arready = ((state == SM_CMD_EN) || (state == SM_DONE))  && (next_state == SM_IDLE);
+
+endmodule
+`default_nettype wire
+
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axi_protocol_converter_v2_1_11_b2s_cmd_translator.v
+//
+// Description: 
+// INCR and WRAP burst modes are decoded in parallel and then the output is
+// chosen based on the AxBURST value.  FIXED burst mode is not supported and
+// is mapped to the INCR command instead.  
+//
+// Specifications:
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_cmd_translator #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+                    // Width of AxADDR
+                    // Range: 32.
+  parameter integer C_AXI_ADDR_WIDTH            = 32
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations     
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                                 clk           , 
+  input  wire                                 reset         , 
+  input  wire [C_AXI_ADDR_WIDTH-1:0]          s_axaddr        , 
+  input  wire [7:0]                           s_axlen         , 
+  input  wire [2:0]                           s_axsize        , 
+  input  wire [1:0]                           s_axburst       , 
+  input  wire                                 s_axhandshake   , 
+  output wire [C_AXI_ADDR_WIDTH-1:0]          m_axaddr , 
+  output wire                                 incr_burst    , 
+
+  // Connections to/from fsm module
+  // signal to increment to the next mc transaction 
+  input  wire                                 next          , 
+  // signal to the fsm there is another transaction required
+  output wire                                 next_pending
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+// AXBURST decodes
+localparam P_AXBURST_FIXED = 2\'b00;
+localparam P_AXBURST_INCR  = 2\'b01;
+localparam P_AXBURST_WRAP  = 2\'b10;
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire [C_AXI_ADDR_WIDTH-1:0]     incr_cmd_byte_addr;
+wire                            incr_next_pending;
+wire [C_AXI_ADDR_WIDTH-1:0]     wrap_cmd_byte_addr;
+wire                            wrap_next_pending;
+reg                             sel_first;
+reg                             s_axburst_eq1;
+reg                             s_axburst_eq0;
+reg                             sel_first_i;   
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// INCR and WRAP translations are calcuated in independently, select the one
+// for our transactions
+// right shift by the UI width to the DRAM width ratio 
+ 
+assign m_axaddr         = (s_axburst == P_AXBURST_FIXED) ?  s_axaddr : 
+                          (s_axburst == P_AXBURST_INCR)  ?  incr_cmd_byte_addr : 
+                                                            wrap_cmd_byte_addr;
+assign incr_burst       = (s_axburst[1]) ? 1\'b0 : 1\'b1;
+
+// Indicates if we are on the first transaction of a mc translation with more
+// than 1 transaction.
+always @(posedge clk) begin
+  if (reset | s_axhandshake) begin
+    sel_first <= 1\'b1;
+  end else if (next) begin
+    sel_first <= 1\'b0;
+  end
+end
+
+always @( * ) begin
+  if (reset | s_axhandshake) begin
+    sel_first_i = 1\'b1;
+  end else if (next) begin
+    sel_first_i = 1\'b0;
+  end else begin
+    sel_first_i = sel_first;
+  end
+end
+
+assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
+
+always @(posedge clk) begin
+  if (sel_first_i || s_axburst[1]) begin
+    s_axburst_eq1 <= wrap_next_pending;
+  end else begin
+    s_axburst_eq1 <= incr_next_pending;
+  end
+  if (sel_first_i || !s_axburst[1]) begin
+    s_axburst_eq0 <= incr_next_pending;
+  end else begin
+    s_axburst_eq0 <= wrap_next_pending;
+  end
+end
+
+axi_protocol_converter_v2_1_11_b2s_incr_cmd #(
+  .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
+)
+incr_cmd_0
+(
+  .clk           ( clk                ) ,
+  .reset         ( reset              ) ,
+  .axaddr        ( s_axaddr           ) ,
+  .axlen         ( s_axlen            ) ,
+  .axsize        ( s_axsize           ) ,
+  .axhandshake   ( s_axhandshake      ) ,
+  .cmd_byte_addr ( incr_cmd_byte_addr ) ,
+  .next          ( next               ) ,
+  .next_pending  ( incr_next_pending  ) 
+);
+
+axi_protocol_converter_v2_1_11_b2s_wrap_cmd #(
+  .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
+)
+wrap_cmd_0
+(
+  .clk           ( clk                ) ,
+  .reset         ( reset              ) ,
+  .axaddr        ( s_axaddr           ) ,
+  .axlen         ( s_axlen            ) ,
+  .axsize        ( s_axsize           ) ,
+  .axhandshake   ( s_axhandshake      ) ,
+  .cmd_byte_addr ( wrap_cmd_byte_addr ) ,
+  .next          ( next               ) ,
+  .next_pending  ( wrap_next_pending  ) 
+);
+
+endmodule
+`default_nettype wire
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axi_protocol_converter_v2_1_11_b2s_b_channel.v
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_b_channel #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+                    // Width of ID signals.
+                    // Range: >= 1.
+  parameter integer C_ID_WIDTH                = 4
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                                 clk,
+  input  wire                                 reset,
+
+  // AXI signals
+  output wire [C_ID_WIDTH-1:0]                s_bid,
+  output wire [1:0]                           s_bresp,
+  output wire                                 s_bvalid,
+  input  wire                                 s_bready,
+
+  input  wire [1:0]                           m_bresp,
+  input  wire                                 m_bvalid,
+  output wire                                 m_bready,
+
+
+  // Signals to/from the axi_protocol_converter_v2_1_11_b2s_aw_channel modules
+  input  wire                                 b_push,
+  input  wire [C_ID_WIDTH-1:0]                b_awid,
+  input  wire [7:0]                           b_awlen,
+  input  wire                                 b_resp_rdy,
+  output wire                                 b_full
+
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+// AXI protocol responses:
+localparam [1:0] LP_RESP_OKAY        = 2\'b00;
+localparam [1:0] LP_RESP_EXOKAY      = 2\'b01;
+localparam [1:0] LP_RESP_SLVERROR    = 2\'b10;
+localparam [1:0] LP_RESP_DECERR      = 2\'b11;
+
+// FIFO settings
+localparam P_WIDTH  = C_ID_WIDTH + 8;
+localparam P_DEPTH  = 4;
+localparam P_AWIDTH = 2;
+
+localparam P_RWIDTH  = 2;
+localparam P_RDEPTH  = 4;
+localparam P_RAWIDTH = 2;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wire and register declarations
+////////////////////////////////////////////////////////////////////////////////
+reg                     bvalid_i;
+wire [C_ID_WIDTH-1:0]   bid_i;
+wire                    shandshake;
+reg                     shandshake_r;
+wire                    mhandshake;
+reg                     mhandshake_r;
+
+wire                    b_empty;
+wire                    bresp_full;
+wire                    bresp_empty;
+wire [7:0]              b_awlen_i;
+reg  [7:0]              bresp_cnt;
+
+reg  [1:0]              s_bresp_acc;
+wire [1:0]              s_bresp_acc_r;
+reg  [1:0]              s_bresp_i;
+wire                    need_to_update_bresp;
+wire                    bresp_push;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// assign AXI outputs
+assign s_bid      = bid_i;
+assign s_bresp    = s_bresp_acc_r;
+assign s_bvalid   = bvalid_i;
+assign shandshake = s_bvalid & s_bready;
+assign mhandshake = m_bvalid & m_bready;
+
+always @(posedge clk) begin
+  if (reset | shandshake) begin
+    bvalid_i <= 1\'b0;
+  end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
+    bvalid_i <= 1\'b1;
+  end
+end
+
+always @(posedge clk) begin
+  shandshake_r <= shandshake;
+  mhandshake_r <= mhandshake;
+end
+
+axi_protocol_converter_v2_1_11_b2s_simple_fifo #(
+  .C_WIDTH                  (P_WIDTH),
+  .C_AWIDTH                 (P_AWIDTH),
+  .C_DEPTH                  (P_DEPTH)
+)
+bid_fifo_0
+(
+  .clk     ( clk          ) ,
+  .rst     ( reset        ) ,
+  .wr_en   ( b_push       ) ,
+  .rd_en   ( shandshake_r ) ,
+  .din     ( {b_awid, b_awlen} ) ,
+  .dout    ( {bid_i, b_awlen_i}) ,
+  .a_full  (              ) ,
+  .full    ( b_full       ) ,
+  .a_empty (              ) ,
+  .empty   ( b_empty        )
+);
+
+assign m_bready = ~mhandshake_r & bresp_empty;
+
+/////////////////////////////////////////////////////////////////////////////
+// Update if more critical.
+assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
+
+// Select accumultated or direct depending on setting.
+always @( * ) begin
+  if ( need_to_update_bresp ) begin
+    s_bresp_i = m_bresp;
+  end else begin
+    s_bresp_i = s_bresp_acc;
+  end
+end
+
+/////////////////////////////////////////////////////////////////////////////
+// Accumulate MI-side BRESP.
+always @ (posedge clk) begin
+  if (reset | bresp_push ) begin
+    s_bresp_acc <= LP_RESP_OKAY;
+  end else if ( mhandshake ) begin
+    s_bresp_acc <= s_bresp_i;
+  end
+end
+
+assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
+
+always @ (posedge clk) begin
+  if (reset | bresp_push ) begin
+    bresp_cnt <= 8\'h00;
+  end else if ( mhandshake_r ) begin
+    bresp_cnt <= bresp_cnt + 1\'b1;
+  end
+end
+
+axi_protocol_converter_v2_1_11_b2s_simple_fifo #(
+  .C_WIDTH                  (P_RWIDTH),
+  .C_AWIDTH                 (P_RAWIDTH),
+  .C_DEPTH                  (P_RDEPTH)
+)
+bresp_fifo_0
+(
+  .clk     ( clk          ) ,
+  .rst     ( reset        ) ,
+  .wr_en   ( bresp_push   ) ,
+  .rd_en   ( shandshake_r ) ,
+  .din     ( s_bresp_acc  ) ,
+  .dout    ( s_bresp_acc_r) ,
+  .a_full  (              ) ,
+  .full    ( bresp_full   ) ,
+  .a_empty (              ) ,
+  .empty   ( bresp_empty  )
+);
+
+
+endmodule
+
+`default_nettype wire
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axi_protocol_converter_v2_1_11_b2s_r_channel.v
+//
+// Description:
+// Read data channel module to buffer read data from MC, ignore
+// extra data in case of BL8 and send the data to AXI.
+// The MC will send out the read data as it is ready and it has to be
+// accepted. The read data FIFO in the axi_protocol_converter_v2_1_11_b2s_r_channel module will buffer
+// the data before being sent to AXI. The address channel module will
+// send the transaction information for every command that is sent to the
+// MC. The transaction information will be buffered in a transaction FIFO.
+// Based on the transaction FIFO information data will be ignored in
+// BL8 mode and the last signal to the AXI will be asserted.
+
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_r_channel #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+                    // Width of ID signals.
+                    // Range: >= 1.
+  parameter integer C_ID_WIDTH                = 4,
+                    // Width of AXI xDATA and MCB xx_data
+                    // Range: 32, 64, 128.
+  parameter integer C_DATA_WIDTH              = 32
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                                 clk              ,
+  input  wire                                 reset            ,
+
+  output wire  [C_ID_WIDTH-1:0]               s_rid              ,
+  output wire  [C_DATA_WIDTH-1:0]             s_rdata            ,
+  output wire [1:0]                           s_rresp            ,
+  output wire                                 s_rlast            ,
+  output wire                                 s_rvalid           ,
+  input  wire                                 s_rready           ,
+
+  input  wire [C_DATA_WIDTH-1:0]              m_rdata   ,
+  input  wire [1:0]                           m_rresp   ,
+  input  wire                                 m_rvalid  ,
+  output wire                                 m_rready  ,
+
+  // Connections to/from axi_protocol_converter_v2_1_11_b2s_ar_channel module
+  input  wire                                 r_push           ,
+  output wire                                 r_full           ,
+  // length not needed. Can be removed.
+  input  wire [C_ID_WIDTH-1:0]                r_arid           ,
+  input  wire                                 r_rlast
+
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam P_WIDTH = 1+C_ID_WIDTH;
+localparam P_DEPTH = 32;
+localparam P_AWIDTH = 5;
+localparam P_D_WIDTH = C_DATA_WIDTH + 2;
+// rd data FIFO depth varies based on burst length.
+// For Bl8 it is two times the size of transaction FIFO.
+// Only in 2:1 mode BL8 transactions will happen which results in
+// two beats of read data per read transaction.
+localparam P_D_DEPTH  = 32;
+localparam P_D_AWIDTH = 5;
+
+////////////////////////////////////////////////////////////////////////////////
+// Wire and register declarations
+////////////////////////////////////////////////////////////////////////////////
+
+wire [C_ID_WIDTH+1-1:0]    trans_in;
+wire [C_ID_WIDTH+1-1:0]    trans_out;
+wire                       tr_empty;
+
+wire                       rhandshake;
+wire                       r_valid_i;
+wire [P_D_WIDTH-1:0]       rd_data_fifo_in;
+wire [P_D_WIDTH-1:0]       rd_data_fifo_out;
+wire                       rd_en;
+wire                       rd_full;
+wire                       rd_empty;
+wire                       rd_a_full;
+wire                       fifo_a_full;
+
+reg [C_ID_WIDTH-1:0]       r_arid_r;
+reg                        r_rlast_r;
+reg                        r_push_r;
+
+wire                       fifo_full;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+assign s_rresp  = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
+assign s_rid    = trans_out[1+:C_ID_WIDTH];
+assign s_rdata  = rd_data_fifo_out[C_DATA_WIDTH-1:0];
+assign s_rlast  = trans_out[0];
+assign s_rvalid = ~rd_empty & ~tr_empty;
+
+
+// assign MCB outputs
+assign rd_en      = rhandshake & (~rd_empty);
+
+assign rhandshake =(s_rvalid & s_rready);
+
+// register for timing
+
+always @(posedge clk) begin
+  r_arid_r <= r_arid;
+  r_rlast_r <= r_rlast;
+  r_push_r <= r_push;
+end
+
+assign trans_in[0]  = r_rlast_r;
+assign trans_in[1+:C_ID_WIDTH]  = r_arid_r;
+
+
+// rd data fifo
+axi_protocol_converter_v2_1_11_b2s_simple_fifo #(
+  .C_WIDTH                (P_D_WIDTH),
+  .C_AWIDTH               (P_D_AWIDTH),
+  .C_DEPTH                (P_D_DEPTH)
+)
+rd_data_fifo_0
+(
+  .clk     ( clk              ) ,
+  .rst     ( reset            ) ,
+  .wr_en   ( m_rvalid & m_rready ) ,
+  .rd_en   ( rd_en            ) ,
+  .din     ( rd_data_fifo_in  ) ,
+  .dout    ( rd_data_fifo_out ) ,
+  .a_full  ( rd_a_full        ) ,
+  .full    ( rd_full          ) ,
+  .a_empty (                  ) ,
+  .empty   ( rd_empty         )
+);
+
+assign rd_data_fifo_in = {m_rresp, m_rdata};
+
+axi_protocol_converter_v2_1_11_b2s_simple_fifo #(
+  .C_WIDTH                  (P_WIDTH),
+  .C_AWIDTH                 (P_AWIDTH),
+  .C_DEPTH                  (P_DEPTH)
+)
+transaction_fifo_0
+(
+  .clk     ( clk         ) ,
+  .rst     ( reset       ) ,
+  .wr_en   ( r_push_r    ) ,
+  .rd_en   ( rd_en       ) ,
+  .din     ( trans_in    ) ,
+  .dout    ( trans_out   ) ,
+  .a_full  ( fifo_a_full ) ,
+  .full    (             ) ,
+  .a_empty (             ) ,
+  .empty   ( tr_empty    )
+);
+
+assign fifo_full = fifo_a_full | rd_a_full ;
+assign r_full = fifo_full ;
+assign m_rready = ~rd_a_full;
+
+endmodule
+`default_nettype wire
+
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_aw_channel #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+                    // Width of ID signals.
+                    // Range: >= 1.
+  parameter integer C_ID_WIDTH          = 4,
+                    // Width of AxADDR
+                    // Range: 32.
+  parameter integer C_AXI_ADDR_WIDTH    = 32
+
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // AXI Slave Interface
+  // Slave Interface System Signals
+  input  wire                                 clk             ,
+  input  wire                                 reset           ,
+
+  // Slave Interface Write Address Ports
+  input  wire [C_ID_WIDTH-1:0]                s_awid            ,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]          s_awaddr          ,
+  input  wire [7:0]                           s_awlen           ,
+  input  wire [2:0]                           s_awsize          ,
+  input  wire [1:0]                           s_awburst         ,
+  input  wire                                 s_awvalid         ,
+  output wire                                 s_awready         ,
+
+  output wire                                 m_awvalid         ,
+  output wire [C_AXI_ADDR_WIDTH-1:0]          m_awaddr          ,
+  input  wire                                 m_awready         ,
+
+  // Connections to/from axi_protocol_converter_v2_1_11_b2s_b_channel module
+  output wire                                 b_push           ,
+  output wire [C_ID_WIDTH-1:0]                b_awid           ,
+  output wire [7:0]                           b_awlen          ,
+  input  wire                                 b_full
+
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+wire                        next         ;
+wire                        next_pending ;
+wire                        a_push;
+wire                        incr_burst;
+reg  [C_ID_WIDTH-1:0]       s_awid_r;
+reg  [7:0]                  s_awlen_r;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// Translate the AXI transaction to the MC transaction(s)
+axi_protocol_converter_v2_1_11_b2s_cmd_translator #
+(
+  .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
+)
+cmd_translator_0
+(
+  .clk           ( clk                   ) ,
+  .reset         ( reset                 ) ,
+  .s_axaddr      ( s_awaddr              ) ,
+  .s_axlen       ( s_awlen               ) ,
+  .s_axsize      ( s_awsize              ) ,
+  .s_axburst     ( s_awburst             ) ,
+  .s_axhandshake ( s_awvalid & a_push    ) ,
+  .m_axaddr      ( m_awaddr              ) ,
+  .incr_burst    ( incr_burst            ) ,
+  .next          ( next                  ) ,
+  .next_pending  ( next_pending          )
+);
+
+
+axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm aw_cmd_fsm_0
+(
+  .clk          ( clk            ) ,
+  .reset        ( reset          ) ,
+  .s_awready    ( s_awready      ) ,
+  .s_awvalid    ( s_awvalid      ) ,
+  .m_awvalid    ( m_awvalid      ) ,
+  .m_awready    ( m_awready      ) ,
+  .next         ( next           ) ,
+  .next_pending ( next_pending   ) ,
+  .b_push       ( b_push         ) ,
+  .b_full       ( b_full         ) ,
+  .a_push       ( a_push         )
+);
+
+assign b_awid = s_awid_r;
+assign b_awlen = s_awlen_r;
+
+always @(posedge clk) begin
+  s_awid_r <= s_awid ;
+  s_awlen_r <= s_awlen ;
+end
+
+endmodule
+
+`default_nettype wire
+
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s_ar_channel #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+                    // Width of ID signals.
+                    // Range: >= 1.
+  parameter integer C_ID_WIDTH          = 4,
+                    // Width of AxADDR
+                    // Range: 32.
+  parameter integer C_AXI_ADDR_WIDTH    = 32
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // AXI Slave Interface
+  // Slave Interface System Signals
+  input  wire                                 clk             ,
+  input  wire                                 reset           ,
+
+  // Slave Interface Read Address Ports
+  input  wire [C_ID_WIDTH-1:0]                s_arid            ,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]          s_araddr          ,
+  input  wire [7:0]                           s_arlen           ,
+  input  wire [2:0]                           s_arsize          ,
+  input  wire [1:0]                           s_arburst         ,
+  input  wire                                 s_arvalid         ,
+  output wire                                 s_arready         ,
+
+  output wire                                 m_arvalid         ,
+  output wire [C_AXI_ADDR_WIDTH-1:0]          m_araddr          ,
+  input  wire                                 m_arready         ,
+
+  // Connections to/from axi_protocol_converter_v2_1_11_b2s_r_channel module
+  output wire [C_ID_WIDTH-1:0]                r_arid            ,
+  output wire                                 r_push            ,
+  output wire                                 r_rlast           ,
+  input  wire                                 r_full
+
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire                        next      ;
+wire                        next_pending ;
+wire                        a_push;
+wire                        incr_burst;
+reg [C_ID_WIDTH-1:0]        s_arid_r;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+
+// Translate the AXI transaction to the MC transaction(s)
+axi_protocol_converter_v2_1_11_b2s_cmd_translator #
+(
+  .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
+)
+cmd_translator_0
+(
+  .clk           ( clk                   ) ,
+  .reset         ( reset                 ) ,
+  .s_axaddr      ( s_araddr              ) ,
+  .s_axlen       ( s_arlen               ) ,
+  .s_axsize      ( s_arsize              ) ,
+  .s_axburst     ( s_arburst             ) ,
+  .s_axhandshake ( s_arvalid & a_push    ) ,
+  .incr_burst    ( incr_burst            ) ,
+  .m_axaddr      ( m_araddr              ) ,
+  .next          ( next                  ) ,
+  .next_pending  ( next_pending          )
+);
+
+axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm ar_cmd_fsm_0
+(
+  .clk          ( clk            ) ,
+  .reset        ( reset          ) ,
+  .s_arready    ( s_arready      ) ,
+  .s_arvalid    ( s_arvalid      ) ,
+  .s_arlen      ( s_arlen        ) ,
+  .m_arvalid    ( m_arvalid      ) ,
+  .m_arready    ( m_arready      ) ,
+  .next         ( next           ) ,
+  .next_pending ( next_pending   ) ,
+  .data_ready   ( ~r_full        ) ,
+  .a_push       ( a_push         ) ,
+  .r_push       ( r_push         )
+);
+
+// these signals can be moved out of this block to the top level.
+assign r_arid  = s_arid_r;
+assign r_rlast = ~next_pending;
+
+always @(posedge clk) begin
+  s_arid_r <= s_arid ;
+end
+
+endmodule
+
+`default_nettype wire
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// File name: axi_protocol_converter_v2_1_11_b2s.v
+//
+// Description:
+// To handle AXI4 transactions to external memory on Virtex-6 architectures
+// requires a bridge to convert the AXI4 transactions to the memory
+// controller(MC) user interface.  The MC user interface has bidirectional
+// data path and supports data width of 256/128/64/32 bits.
+// The bridge is designed to allow AXI4 IP masters to communicate with
+// the MC user interface.
+//
+//
+// Specifications:
+// AXI4 Slave Side:
+// Configurable data width of 32, 64, 128, 256
+// Read acceptance depth is:
+// Write acceptance depth is:
+//
+// Structure:
+// axi_protocol_converter_v2_1_11_b2s
+//   WRITE_BUNDLE
+//     aw_channel_0
+//       cmd_translator_0
+//       rd_cmd_fsm_0
+//     w_channel_0
+//     b_channel_0
+//   READ_BUNDLE
+//     ar_channel_0
+//       cmd_translator_0
+//       rd_cmd_fsm_0
+//     r_channel_0
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_b2s #(
+  parameter C_S_AXI_PROTOCOL                      = 0,
+                    // Width of all master and slave ID signals.
+                    // Range: >= 1.
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 30,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_WRITE          = 1,
+  parameter integer C_AXI_SUPPORTS_READ           = 1
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // AXI Slave Interface
+  // Slave Interface System Signals
+  input  wire                               aclk              ,
+  input  wire                               aresetn           ,
+  // Slave Interface Write Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]          s_axi_awid        ,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr      ,
+  input  wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,
+  input  wire [2:0]                         s_axi_awsize      ,
+  input  wire [1:0]                         s_axi_awburst     ,
+  input  wire [2:0]                         s_axi_awprot      ,
+  input  wire                               s_axi_awvalid     ,
+  output wire                               s_axi_awready     ,
+  // Slave Interface Write Data Ports
+  input  wire [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata       ,
+  input  wire [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb       ,
+  input  wire                               s_axi_wlast       ,
+  input  wire                               s_axi_wvalid      ,
+  output wire                               s_axi_wready      ,
+  // Slave Interface Write Response Ports
+  output wire [C_AXI_ID_WIDTH-1:0]          s_axi_bid         ,
+  output wire [1:0]                         s_axi_bresp       ,
+  output wire                               s_axi_bvalid      ,
+  input  wire                               s_axi_bready      ,
+  // Slave Interface Read Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]          s_axi_arid        ,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr      ,
+  input  wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,
+  input  wire [2:0]                         s_axi_arsize      ,
+  input  wire [1:0]                         s_axi_arburst     ,
+  input  wire [2:0]                         s_axi_arprot      ,
+  input  wire                               s_axi_arvalid     ,
+  output wire                               s_axi_arready     ,
+  // Slave Interface Read Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]          s_axi_rid         ,
+  output wire [C_AXI_DATA_WIDTH-1:0]        s_axi_rdata       ,
+  output wire [1:0]                         s_axi_rresp       ,
+  output wire                               s_axi_rlast       ,
+  output wire                               s_axi_rvalid      ,
+  input  wire                               s_axi_rready      ,
+
+  // Slave Interface Write Address Ports
+  output wire [C_AXI_ADDR_WIDTH-1:0]        m_axi_awaddr      ,
+  output wire [2:0]                         m_axi_awprot      ,
+  output wire                               m_axi_awvalid     ,
+  input  wire                               m_axi_awready     ,
+  // Slave Interface Write Data Ports
+  output wire [C_AXI_DATA_WIDTH-1:0]        m_axi_wdata       ,
+  output wire [C_AXI_DATA_WIDTH/8-1:0]      m_axi_wstrb       ,
+  output wire                               m_axi_wvalid      ,
+  input  wire                               m_axi_wready      ,
+  // Slave Interface Write Response Ports
+  input  wire [1:0]                         m_axi_bresp       ,
+  input  wire                               m_axi_bvalid      ,
+  output wire                               m_axi_bready      ,
+  // Slave Interface Read Address Ports
+  output wire [C_AXI_ADDR_WIDTH-1:0]        m_axi_araddr      ,
+  output wire [2:0]                         m_axi_arprot      ,
+  output wire                               m_axi_arvalid     ,
+  input  wire                               m_axi_arready     ,
+  // Slave Interface Read Data Ports
+  input  wire [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata       ,
+  input  wire [1:0]                         m_axi_rresp       ,
+  input  wire                               m_axi_rvalid      ,
+  output wire                               m_axi_rready
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+reg                            areset_d1;
+
+always @(posedge aclk)
+  areset_d1 <= ~aresetn;
+
+
+// AW/W/B'b' channel internal communication
+wire                                b_push;
+wire [C_AXI_ID_WIDTH-1:0]           b_awid;
+wire [7:0]                          b_awlen;
+wire                                b_full;
+
+wire [C_AXI_ID_WIDTH-1:0]                   si_rs_awid;
+wire [C_AXI_ADDR_WIDTH-1:0]                 si_rs_awaddr;
+wire [8-1:0]                                si_rs_awlen;
+wire [3-1:0]                                si_rs_awsize;
+wire [2-1:0]                                si_rs_awburst;
+wire [3-1:0]                                si_rs_awprot;
+wire                                        si_rs_awvalid;
+wire                                        si_rs_awready;
+wire [C_AXI_DATA_WIDTH-1:0]                 si_rs_wdata;
+wire [C_AXI_DATA_WIDTH/8-1:0]               si_rs_wstrb;
+wire                                        si_rs_wlast;
+wire                                        si_rs_wvalid;
+wire                                        si_rs_wready;
+wire [C_AXI_ID_WIDTH-1:0]                   si_rs_bid;
+wire [2-1:0]                                si_rs_bresp;
+wire                                        si_rs_bvalid;
+wire                                        si_rs_bready;
+wire [C_AXI_ID_WIDTH-1:0]                   si_rs_arid;
+wire [C_AXI_ADDR_WIDTH-1:0]                 si_rs_araddr;
+wire [8-1:0]                                si_rs_arlen;
+wire [3-1:0]                                si_rs_arsize;
+wire [2-1:0]                                si_rs_arburst;
+wire [3-1:0]                                si_rs_arprot;
+wire                                        si_rs_arvalid;
+wire                                        si_rs_arready;
+wire [C_AXI_ID_WIDTH-1:0]                   si_rs_rid;
+wire [C_AXI_DATA_WIDTH-1:0]                 si_rs_rdata;
+wire [2-1:0]                                si_rs_rresp;
+wire                                        si_rs_rlast;
+wire                                        si_rs_rvalid;
+wire                                        si_rs_rready;
+
+wire [C_AXI_ADDR_WIDTH-1:0]                 rs_mi_awaddr;
+wire                                        rs_mi_awvalid;
+wire                                        rs_mi_awready;
+wire [C_AXI_DATA_WIDTH-1:0]                 rs_mi_wdata;
+wire [C_AXI_DATA_WIDTH/8-1:0]               rs_mi_wstrb;
+wire                                        rs_mi_wvalid;
+wire                                        rs_mi_wready;
+wire [2-1:0]                                rs_mi_bresp;
+wire                                        rs_mi_bvalid;
+wire                                        rs_mi_bready;
+wire [C_AXI_ADDR_WIDTH-1:0]                 rs_mi_araddr;
+wire                                        rs_mi_arvalid;
+wire                                        rs_mi_arready;
+wire [C_AXI_DATA_WIDTH-1:0]                 rs_mi_rdata;
+wire [2-1:0]                                rs_mi_rresp;
+wire                                        rs_mi_rvalid;
+wire                                        rs_mi_rready;
+
+
+axi_register_slice_v2_1_11_axi_register_slice #(
+  .C_AXI_PROTOCOL              ( C_S_AXI_PROTOCOL            ) ,
+  .C_AXI_ID_WIDTH              ( C_AXI_ID_WIDTH              ) ,
+  .C_AXI_ADDR_WIDTH            ( C_AXI_ADDR_WIDTH            ) ,
+  .C_AXI_DATA_WIDTH            ( C_AXI_DATA_WIDTH            ) ,
+  .C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
+  .C_AXI_AWUSER_WIDTH          ( 1 ) ,
+  .C_AXI_ARUSER_WIDTH          ( 1 ) ,
+  .C_AXI_WUSER_WIDTH           ( 1 ) ,
+  .C_AXI_RUSER_WIDTH           ( 1 ) ,
+  .C_AXI_BUSER_WIDTH           ( 1 ) ,
+  .C_REG_CONFIG_AW             ( 1 ) ,
+  .C_REG_CONFIG_AR             ( 1 ) ,
+  .C_REG_CONFIG_W              ( 0 ) ,
+  .C_REG_CONFIG_R              ( 1 ) ,
+  .C_REG_CONFIG_B              ( 1 )
+) SI_REG (
+  .aresetn                    ( aresetn     ) ,
+  .aclk                       ( aclk          ) ,
+  .s_axi_awid                 ( s_axi_awid    ) ,
+  .s_axi_awaddr               ( s_axi_awaddr  ) ,
+  .s_axi_awlen                ( s_axi_awlen   ) ,
+  .s_axi_awsize               ( s_axi_awsize  ) ,
+  .s_axi_awburst              ( s_axi_awburst ) ,
+  .s_axi_awlock               ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1\'b0}}  ) ,
+  .s_axi_awcache              ( 4\'h0 ) ,
+  .s_axi_awprot               ( s_axi_awprot  ) ,
+  .s_axi_awqos                ( 4\'h0 ) ,
+  .s_axi_awuser               ( 1\'b0  ) ,
+  .s_axi_awvalid              ( s_axi_awvalid ) ,
+  .s_axi_awready              ( s_axi_awready ) ,
+  .s_axi_awregion             ( 4\'h0 ) ,
+  .s_axi_wid                  ( {C_AXI_ID_WIDTH{1\'b0}} ) ,
+  .s_axi_wdata                ( s_axi_wdata   ) ,
+  .s_axi_wstrb                ( s_axi_wstrb   ) ,
+  .s_axi_wlast                ( s_axi_wlast   ) ,
+  .s_axi_wuser                ( 1\'b0  ) ,
+  .s_axi_wvalid               ( s_axi_wvalid  ) ,
+  .s_axi_wready               ( s_axi_wready  ) ,
+  .s_axi_bid                  ( s_axi_bid     ) ,
+  .s_axi_bresp                ( s_axi_bresp   ) ,
+  .s_axi_buser                ( ) ,
+  .s_axi_bvalid               ( s_axi_bvalid  ) ,
+  .s_axi_bready               ( s_axi_bready  ) ,
+  .s_axi_arid                 ( s_axi_arid    ) ,
+  .s_axi_araddr               ( s_axi_araddr  ) ,
+  .s_axi_arlen                ( s_axi_arlen   ) ,
+  .s_axi_arsize               ( s_axi_arsize  ) ,
+  .s_axi_arburst              ( s_axi_arburst ) ,
+  .s_axi_arlock               ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1\'b0}}  ) ,
+  .s_axi_arcache              ( 4\'h0 ) ,
+  .s_axi_arprot               ( s_axi_arprot  ) ,
+  .s_axi_arqos                ( 4\'h0 ) ,
+  .s_axi_aruser               ( 1\'b0  ) ,
+  .s_axi_arvalid              ( s_axi_arvalid ) ,
+  .s_axi_arready              ( s_axi_arready ) ,
+  .s_axi_arregion             ( 4\'h0 ) ,
+  .s_axi_rid                  ( s_axi_rid     ) ,
+  .s_axi_rdata                ( s_axi_rdata   ) ,
+  .s_axi_rresp                ( s_axi_rresp   ) ,
+  .s_axi_rlast                ( s_axi_rlast   ) ,
+  .s_axi_ruser                ( ) ,
+  .s_axi_rvalid               ( s_axi_rvalid  ) ,
+  .s_axi_rready               ( s_axi_rready  ) ,
+  .m_axi_awid                 ( si_rs_awid    ) ,
+  .m_axi_awaddr               ( si_rs_awaddr  ) ,
+  .m_axi_awlen                ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
+  .m_axi_awsize               ( si_rs_awsize  ) ,
+  .m_axi_awburst              ( si_rs_awburst ) ,
+  .m_axi_awlock               ( ) ,
+  .m_axi_awcache              ( ) ,
+  .m_axi_awprot               ( si_rs_awprot  ) ,
+  .m_axi_awqos                ( ) ,
+  .m_axi_awuser               ( ) ,
+  .m_axi_awvalid              ( si_rs_awvalid ) ,
+  .m_axi_awready              ( si_rs_awready ) ,
+  .m_axi_awregion             ( ) ,
+  .m_axi_wid                  ( ) ,
+  .m_axi_wdata                ( si_rs_wdata   ) ,
+  .m_axi_wstrb                ( si_rs_wstrb   ) ,
+  .m_axi_wlast                ( si_rs_wlast   ) ,
+  .m_axi_wuser                ( ) ,
+  .m_axi_wvalid               ( si_rs_wvalid  ) ,
+  .m_axi_wready               ( si_rs_wready  ) ,
+  .m_axi_bid                  ( si_rs_bid     ) ,
+  .m_axi_bresp                ( si_rs_bresp   ) ,
+  .m_axi_buser                ( 1\'b0 ) ,
+  .m_axi_bvalid               ( si_rs_bvalid  ) ,
+  .m_axi_bready               ( si_rs_bready  ) ,
+  .m_axi_arid                 ( si_rs_arid    ) ,
+  .m_axi_araddr               ( si_rs_araddr  ) ,
+  .m_axi_arlen                ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
+  .m_axi_arsize               ( si_rs_arsize  ) ,
+  .m_axi_arburst              ( si_rs_arburst ) ,
+  .m_axi_arlock               ( ) ,
+  .m_axi_arcache              ( ) ,
+  .m_axi_arprot               ( si_rs_arprot  ) ,
+  .m_axi_arqos                ( ) ,
+  .m_axi_aruser               ( ) ,
+  .m_axi_arvalid              ( si_rs_arvalid ) ,
+  .m_axi_arready              ( si_rs_arready ) ,
+  .m_axi_arregion             ( ) ,
+  .m_axi_rid                  ( si_rs_rid     ) ,
+  .m_axi_rdata                ( si_rs_rdata   ) ,
+  .m_axi_rresp                ( si_rs_rresp   ) ,
+  .m_axi_rlast                ( si_rs_rlast   ) ,
+  .m_axi_ruser                ( 1\'b0 ) ,
+  .m_axi_rvalid               ( si_rs_rvalid  ) ,
+  .m_axi_rready               ( si_rs_rready  )
+);
+
+generate
+  if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
+    axi_protocol_converter_v2_1_11_b2s_aw_channel #
+    (
+      .C_ID_WIDTH                       ( C_AXI_ID_WIDTH   ),
+      .C_AXI_ADDR_WIDTH                 ( C_AXI_ADDR_WIDTH )
+    )
+    aw_channel_0
+    (
+      .clk                              ( aclk              ) ,
+      .reset                            ( areset_d1         ) ,
+      .s_awid                           ( si_rs_awid        ) ,
+      .s_awaddr                         ( si_rs_awaddr      ) ,
+      .s_awlen                          ( (C_S_AXI_PROTOCOL == 1) ? {4\'h0,si_rs_awlen[3:0]} : si_rs_awlen),
+      .s_awsize                         ( si_rs_awsize      ) ,
+      .s_awburst                        ( si_rs_awburst     ) ,
+      .s_awvalid                        ( si_rs_awvalid     ) ,
+      .s_awready                        ( si_rs_awready     ) ,
+      .m_awvalid                        ( rs_mi_awvalid     ) ,
+      .m_awaddr                         ( rs_mi_awaddr      ) ,
+      .m_awready                        ( rs_mi_awready     ) ,
+      .b_push                           ( b_push            ) ,
+      .b_awid                           ( b_awid            ) ,
+      .b_awlen                          ( b_awlen           ) ,
+      .b_full                           ( b_full            )
+    );
+
+    axi_protocol_converter_v2_1_11_b2s_b_channel #
+    (
+      .C_ID_WIDTH                       ( C_AXI_ID_WIDTH   )
+    )
+    b_channel_0
+    (
+      .clk                              ( aclk            ) ,
+      .reset                            ( areset_d1       ) ,
+      .s_bid                            ( si_rs_bid       ) ,
+      .s_bresp                          ( si_rs_bresp     ) ,
+      .s_bvalid                         ( si_rs_bvalid    ) ,
+      .s_bready                         ( si_rs_bready    ) ,
+      .m_bready                         ( rs_mi_bready    ) ,
+      .m_bvalid                         ( rs_mi_bvalid    ) ,
+      .m_bresp                          ( rs_mi_bresp     ) ,
+      .b_push                           ( b_push          ) ,
+      .b_awid                           ( b_awid          ) ,
+      .b_awlen                          ( b_awlen         ) ,
+      .b_full                           ( b_full          ) ,
+      .b_resp_rdy                       ( si_rs_awready   )
+    );
+    
+    assign rs_mi_wdata        = si_rs_wdata;
+    assign rs_mi_wstrb        = si_rs_wstrb;
+    assign rs_mi_wvalid       = si_rs_wvalid;
+    assign si_rs_wready       = rs_mi_wready;
+
+  end else begin : NO_WR
+    assign rs_mi_awaddr       = {C_AXI_ADDR_WIDTH{1\'b0}};
+    assign rs_mi_awvalid      = 1\'b0;
+    assign si_rs_awready      = 1\'b0;
+
+    assign rs_mi_wdata        = {C_AXI_DATA_WIDTH{1\'b0}};
+    assign rs_mi_wstrb        = {C_AXI_DATA_WIDTH/8{1\'b0}};
+    assign rs_mi_wvalid       = 1\'b0;
+    assign si_rs_wready       = 1\'b0;
+
+    assign rs_mi_bready    = 1\'b0;
+    assign si_rs_bvalid       = 1\'b0;
+    assign si_rs_bresp        = 2\'b00;
+    assign si_rs_bid          = {C_AXI_ID_WIDTH{1\'b0}};
+  end
+endgenerate
+
+
+// AR/R channel communication
+wire                                r_push        ;
+wire [C_AXI_ID_WIDTH-1:0]           r_arid        ;
+wire                                r_rlast       ;
+wire                                r_full        ;
+
+generate
+  if (C_AXI_SUPPORTS_READ == 1) begin : RD
+    axi_protocol_converter_v2_1_11_b2s_ar_channel #
+    (
+      .C_ID_WIDTH                       ( C_AXI_ID_WIDTH   ),
+      .C_AXI_ADDR_WIDTH                 ( C_AXI_ADDR_WIDTH )
+    
+    )
+    ar_channel_0
+    (
+      .clk                              ( aclk              ) ,
+      .reset                            ( areset_d1         ) ,
+      .s_arid                           ( si_rs_arid        ) ,
+      .s_araddr                         ( si_rs_araddr      ) ,
+      .s_arlen                          ( (C_S_AXI_PROTOCOL == 1) ? {4\'h0,si_rs_arlen[3:0]} : si_rs_arlen),
+      .s_arsize                         ( si_rs_arsize      ) ,
+      .s_arburst                        ( si_rs_arburst     ) ,
+      .s_arvalid                        ( si_rs_arvalid     ) ,
+      .s_arready                        ( si_rs_arready     ) ,
+      .m_arvalid                        ( rs_mi_arvalid     ) ,
+      .m_araddr                         ( rs_mi_araddr      ) ,
+      .m_arready                        ( rs_mi_arready     ) ,
+      .r_push                           ( r_push            ) ,
+      .r_arid                           ( r_arid            ) ,
+      .r_rlast                          ( r_rlast           ) ,
+      .r_full                           ( r_full            )
+    );
+    
+    axi_protocol_converter_v2_1_11_b2s_r_channel #
+    (
+      .C_ID_WIDTH                       ( C_AXI_ID_WIDTH   ),
+      .C_DATA_WIDTH                     ( C_AXI_DATA_WIDTH )
+    )
+    r_channel_0
+    (
+      .clk                              ( aclk            ) ,
+      .reset                            ( areset_d1       ) ,
+      .s_rid                            ( si_rs_rid       ) ,
+      .s_rdata                          ( si_rs_rdata     ) ,
+      .s_rresp                          ( si_rs_rresp     ) ,
+      .s_rlast                          ( si_rs_rlast     ) ,
+      .s_rvalid                         ( si_rs_rvalid    ) ,
+      .s_rready                         ( si_rs_rready    ) ,
+      .m_rvalid                         ( rs_mi_rvalid    ) ,
+      .m_rready                         ( rs_mi_rready    ) ,
+      .m_rdata                          ( rs_mi_rdata     ) ,
+      .m_rresp                          ( rs_mi_rresp     ) ,
+      .r_push                           ( r_push          ) ,
+      .r_full                           ( r_full          ) ,
+      .r_arid                           ( r_arid          ) ,
+      .r_rlast                          ( r_rlast         )
+    );
+  end else begin : NO_RD
+    assign rs_mi_araddr       = {C_AXI_ADDR_WIDTH{1\'b0}};
+    assign rs_mi_arvalid      = 1\'b0;
+    assign si_rs_arready      = 1\'b0;
+    assign si_rs_rlast        = 1\'b1;
+
+    assign si_rs_rdata        = {C_AXI_DATA_WIDTH{1\'b0}};
+    assign si_rs_rvalid       = 1\'b0;
+    assign si_rs_rresp        = 2\'b00;
+    assign si_rs_rid          = {C_AXI_ID_WIDTH{1\'b0}};
+    assign rs_mi_rready       = 1\'b0;
+  end
+endgenerate
+
+axi_register_slice_v2_1_11_axi_register_slice #(
+  .C_AXI_PROTOCOL              ( 2 ) ,
+  .C_AXI_ID_WIDTH              ( 1 ) ,
+  .C_AXI_ADDR_WIDTH            ( C_AXI_ADDR_WIDTH            ) ,
+  .C_AXI_DATA_WIDTH            ( C_AXI_DATA_WIDTH            ) ,
+  .C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
+  .C_AXI_AWUSER_WIDTH          ( 1 ) ,
+  .C_AXI_ARUSER_WIDTH          ( 1 ) ,
+  .C_AXI_WUSER_WIDTH           ( 1 ) ,
+  .C_AXI_RUSER_WIDTH           ( 1 ) ,
+  .C_AXI_BUSER_WIDTH           ( 1 ) ,
+  .C_REG_CONFIG_AW             ( 0 ) ,
+  .C_REG_CONFIG_AR             ( 0 ) ,
+  .C_REG_CONFIG_W              ( 0 ) ,
+  .C_REG_CONFIG_R              ( 0 ) ,
+  .C_REG_CONFIG_B              ( 0 )
+) MI_REG (
+  .aresetn                    ( aresetn       ) ,
+  .aclk                       ( aclk          ) ,
+  .s_axi_awid                 ( 1\'b0          ) ,
+  .s_axi_awaddr               ( rs_mi_awaddr  ) ,
+  .s_axi_awlen                ( 8\'h00         ) ,
+  .s_axi_awsize               ( 3\'b000        ) ,
+  .s_axi_awburst              ( 2\'b01         ) ,
+  .s_axi_awlock               ( 1\'b0          ) ,
+  .s_axi_awcache              ( 4\'h0          ) ,
+  .s_axi_awprot               ( si_rs_awprot  ) ,
+  .s_axi_awqos                ( 4\'h0          ) ,
+  .s_axi_awuser               ( 1\'b0          ) ,
+  .s_axi_awvalid              ( rs_mi_awvalid ) ,
+  .s_axi_awready              ( rs_mi_awready ) ,
+  .s_axi_awregion             ( 4\'h0          ) ,
+  .s_axi_wid                  ( 1\'b0          ) ,
+  .s_axi_wdata                ( rs_mi_wdata   ) ,
+  .s_axi_wstrb                ( rs_mi_wstrb   ) ,
+  .s_axi_wlast                ( 1\'b1          ) ,
+  .s_axi_wuser                ( 1\'b0          ) ,
+  .s_axi_wvalid               ( rs_mi_wvalid  ) ,
+  .s_axi_wready               ( rs_mi_wready  ) ,
+  .s_axi_bid                  (               ) ,
+  .s_axi_bresp                ( rs_mi_bresp   ) ,
+  .s_axi_buser                (               ) ,
+  .s_axi_bvalid               ( rs_mi_bvalid  ) ,
+  .s_axi_bready               ( rs_mi_bready  ) ,
+  .s_axi_arid                 ( 1\'b0          ) ,
+  .s_axi_araddr               ( rs_mi_araddr  ) ,
+  .s_axi_arlen                ( 8\'h00         ) ,
+  .s_axi_arsize               ( 3\'b000        ) ,
+  .s_axi_arburst              ( 2\'b01         ) ,
+  .s_axi_arlock               ( 1\'b0          ) ,
+  .s_axi_arcache              ( 4\'h0          ) ,
+  .s_axi_arprot               ( si_rs_arprot  ) ,
+  .s_axi_arqos                ( 4\'h0          ) ,
+  .s_axi_aruser               ( 1\'b0          ) ,
+  .s_axi_arvalid              ( rs_mi_arvalid ) ,
+  .s_axi_arready              ( rs_mi_arready ) ,
+  .s_axi_arregion             ( 4\'h0          ) ,
+  .s_axi_rid                  (               ) ,
+  .s_axi_rdata                ( rs_mi_rdata   ) ,
+  .s_axi_rresp                ( rs_mi_rresp   ) ,
+  .s_axi_rlast                (               ) ,
+  .s_axi_ruser                (               ) ,
+  .s_axi_rvalid               ( rs_mi_rvalid  ) ,
+  .s_axi_rready               ( rs_mi_rready  ) ,
+  .m_axi_awid                 (               ) ,
+  .m_axi_awaddr               ( m_axi_awaddr  ) ,
+  .m_axi_awlen                (               ) ,
+  .m_axi_awsize               (               ) ,
+  .m_axi_awburst              (               ) ,
+  .m_axi_awlock               (               ) ,
+  .m_axi_awcache              (               ) ,
+  .m_axi_awprot               ( m_axi_awprot  ) ,
+  .m_axi_awqos                (               ) ,
+  .m_axi_awuser               (               ) ,
+  .m_axi_awvalid              ( m_axi_awvalid ) ,
+  .m_axi_awready              ( m_axi_awready ) ,
+  .m_axi_awregion             (               ) ,
+  .m_axi_wid                  (               ) ,
+  .m_axi_wdata                ( m_axi_wdata   ) ,
+  .m_axi_wstrb                ( m_axi_wstrb   ) ,
+  .m_axi_wlast                (               ) ,
+  .m_axi_wuser                (               ) ,
+  .m_axi_wvalid               ( m_axi_wvalid  ) ,
+  .m_axi_wready               ( m_axi_wready  ) ,
+  .m_axi_bid                  ( 1\'b0          ) ,
+  .m_axi_bresp                ( m_axi_bresp   ) ,
+  .m_axi_buser                ( 1\'b0          ) ,
+  .m_axi_bvalid               ( m_axi_bvalid  ) ,
+  .m_axi_bready               ( m_axi_bready  ) ,
+  .m_axi_arid                 (               ) ,
+  .m_axi_araddr               ( m_axi_araddr  ) ,
+  .m_axi_arlen                (               ) ,
+  .m_axi_arsize               (               ) ,
+  .m_axi_arburst              (               ) ,
+  .m_axi_arlock               (               ) ,
+  .m_axi_arcache              (               ) ,
+  .m_axi_arprot               ( m_axi_arprot  ) ,
+  .m_axi_arqos                (               ) ,
+  .m_axi_aruser               (               ) ,
+  .m_axi_arvalid              ( m_axi_arvalid ) ,
+  .m_axi_arready              ( m_axi_arready ) ,
+  .m_axi_arregion             (               ) ,
+  .m_axi_rid                  ( 1\'b0          ) ,
+  .m_axi_rdata                ( m_axi_rdata   ) ,
+  .m_axi_rresp                ( m_axi_rresp   ) ,
+  .m_axi_rlast                ( 1\'b1          ) ,
+  .m_axi_ruser                ( 1\'b0          ) ,
+  .m_axi_rvalid               ( m_axi_rvalid  ) ,
+  .m_axi_rready               ( m_axi_rready  )
+);
+
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2012 -2013 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
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+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: axi_protocol_converter.v
+//
+// Description: 
+//   This module is a bank of AXI4-Lite and AXI3 protocol converters for a vectored AXI interface.
+//   The interface of this module consists of a vectored slave and master interface
+//     which are each concatenations of upper-level AXI pathways,
+//     plus various vectored parameters.
+//   This module instantiates a set of individual protocol converter modules.
+//
+//-----------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_protocol_converter_v2_1_11_axi_protocol_converter #(
+  parameter         C_FAMILY                    = ""virtex6"",
+  parameter integer C_M_AXI_PROTOCOL            = 0, 
+  parameter integer C_S_AXI_PROTOCOL            = 0, 
+  parameter integer C_IGNORE_ID                = 0,
+                     // 0 = RID/BID are stored by axilite_conv.
+                     // 1 = RID/BID have already been stored in an upstream device, like SASD crossbar.
+  parameter integer C_AXI_ID_WIDTH              = 4,
+  parameter integer C_AXI_ADDR_WIDTH            = 32,
+  parameter integer C_AXI_DATA_WIDTH            = 32,
+  parameter integer C_AXI_SUPPORTS_WRITE        = 1,
+  parameter integer C_AXI_SUPPORTS_READ         = 1,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
+                     // 1 = Propagate all USER signals, 0 = Don\x92t propagate.
+  parameter integer C_AXI_AWUSER_WIDTH          = 1,
+  parameter integer C_AXI_ARUSER_WIDTH          = 1,
+  parameter integer C_AXI_WUSER_WIDTH           = 1,
+  parameter integer C_AXI_RUSER_WIDTH           = 1,
+  parameter integer C_AXI_BUSER_WIDTH           = 1,
+  parameter integer C_TRANSLATION_MODE                  = 1
+                     // 0 (Unprotected) = Disable all error checking; master is well-behaved.
+                     // 1 (Protection) = Detect SI transaction violations, but perform no splitting.
+                     //     AXI4 -> AXI3 must be <= 16 beats; AXI4/3 -> AXI4LITE must be single.
+                     // 2 (Conversion) = Include transaction splitting logic
+) (
+  // Global Signals
+   input wire aclk,
+   input wire aresetn,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,
+   input  wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,
+   input  wire [3-1:0]                  s_axi_awsize,
+   input  wire [2-1:0]                  s_axi_awburst,
+   input  wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,
+   input  wire [4-1:0]                  s_axi_awcache,
+   input  wire [3-1:0]                  s_axi_awprot,
+   input  wire [4-1:0]                  s_axi_awregion,
+   input  wire [4-1:0]                  s_axi_awqos,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
+   input  wire                          s_axi_awvalid,
+   output wire                          s_axi_awready,
+
+   // Slave Interface Write Data Ports
+   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,
+   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
+   input  wire                          s_axi_wlast,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,
+   input  wire                          s_axi_wvalid,
+   output wire                          s_axi_wready,
+
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,
+   output wire [2-1:0]                 s_axi_bresp,
+   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
+   output wire                         s_axi_bvalid,
+   input  wire                         s_axi_bready,
+
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,
+   input  wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,
+   input  wire [3-1:0]                  s_axi_arsize,
+   input  wire [2-1:0]                  s_axi_arburst,
+   input  wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,
+   input  wire [4-1:0]                  s_axi_arcache,
+   input  wire [3-1:0]                  s_axi_arprot,
+   input  wire [4-1:0]                  s_axi_arregion,
+   input  wire [4-1:0]                  s_axi_arqos,
+   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
+   input  wire                          s_axi_arvalid,
+   output wire                          s_axi_arready,
+
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,
+   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,
+   output wire [2-1:0]                 s_axi_rresp,
+   output wire                         s_axi_rlast,
+   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
+   output wire                         s_axi_rvalid,
+   input  wire                         s_axi_rready,
+   
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,
+   output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,
+   output wire [3-1:0]                  m_axi_awsize,
+   output wire [2-1:0]                  m_axi_awburst,
+   output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,
+   output wire [4-1:0]                  m_axi_awcache,
+   output wire [3-1:0]                  m_axi_awprot,
+   output wire [4-1:0]                  m_axi_awregion,
+   output wire [4-1:0]                  m_axi_awqos,
+   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
+   output wire                          m_axi_awvalid,
+   input  wire                          m_axi_awready,
+   
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,
+   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,
+   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
+   output wire                          m_axi_wlast,
+   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,
+   output wire                          m_axi_wvalid,
+   input  wire                          m_axi_wready,
+   
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,
+   input  wire [2-1:0]                 m_axi_bresp,
+   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
+   input  wire                         m_axi_bvalid,
+   output wire                         m_axi_bready,
+   
+   // Master Interface Read Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,
+   output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,
+   output wire [3-1:0]                  m_axi_arsize,
+   output wire [2-1:0]                  m_axi_arburst,
+   output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,
+   output wire [4-1:0]                  m_axi_arcache,
+   output wire [3-1:0]                  m_axi_arprot,
+   output wire [4-1:0]                  m_axi_arregion,
+   output wire [4-1:0]                  m_axi_arqos,
+   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
+   output wire                          m_axi_arvalid,
+   input  wire                          m_axi_arready,
+   
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,
+   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,
+   input  wire [2-1:0]                 m_axi_rresp,
+   input  wire                         m_axi_rlast,
+   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
+   input  wire                         m_axi_rvalid,
+   output wire                         m_axi_rready
+);
+
+localparam P_AXI4 = 32\'h0;
+localparam P_AXI3 = 32\'h1;
+localparam P_AXILITE = 32\'h2;
+localparam P_AXILITE_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3\'b010 : 3\'b011;
+localparam P_INCR = 2\'b01;
+localparam P_DECERR = 2\'b11;
+localparam P_SLVERR = 2\'b10;
+localparam integer P_PROTECTION = 1;
+localparam integer P_CONVERSION = 2;
+
+wire                          s_awvalid_i;
+wire                          s_arvalid_i;
+wire                          s_wvalid_i ;
+wire                          s_bready_i ;
+wire                          s_rready_i ;
+wire                          s_awready_i; 
+wire                          s_wready_i;
+wire                          s_bvalid_i;
+wire [C_AXI_ID_WIDTH-1:0]     s_bid_i;
+wire [1:0]                    s_bresp_i;
+wire [C_AXI_BUSER_WIDTH-1:0]  s_buser_i;
+wire                          s_arready_i; 
+wire                          s_rvalid_i;
+wire [C_AXI_ID_WIDTH-1:0]     s_rid_i;
+wire [1:0]                    s_rresp_i;
+wire [C_AXI_RUSER_WIDTH-1:0]  s_ruser_i;
+wire [C_AXI_DATA_WIDTH-1:0]   s_rdata_i;
+wire                          s_rlast_i;
+
+generate
+  if ((C_M_AXI_PROTOCOL == P_AXILITE)  || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite
+    assign m_axi_awid         = 0;
+    assign m_axi_awlen        = 0;
+    assign m_axi_awsize       = P_AXILITE_SIZE;
+    assign m_axi_awburst      = P_INCR;
+    assign m_axi_awlock       = 0;
+    assign m_axi_awcache      = 0;
+    assign m_axi_awregion     = 0;
+    assign m_axi_awqos        = 0;
+    assign m_axi_awuser       = 0;
+    assign m_axi_wid          = 0;
+    assign m_axi_wlast        = 1\'b1;
+    assign m_axi_wuser        = 0;
+    assign m_axi_arid         = 0;
+    assign m_axi_arlen        = 0;
+    assign m_axi_arsize       = P_AXILITE_SIZE;
+    assign m_axi_arburst      = P_INCR;
+    assign m_axi_arlock       = 0;
+    assign m_axi_arcache      = 0;
+    assign m_axi_arregion     = 0;
+    assign m_axi_arqos        = 0;
+    assign m_axi_aruser       = 0;
+    
+    if (((C_IGNORE_ID == 1) && (C_TRANSLATION_MODE != P_CONVERSION)) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite_passthru
+      assign m_axi_awaddr       = s_axi_awaddr;
+      assign m_axi_awprot       = s_axi_awprot;
+      assign m_axi_awvalid      = s_awvalid_i;
+      assign s_awready_i        = m_axi_awready;
+      assign m_axi_wdata        = s_axi_wdata;
+      assign m_axi_wstrb        = s_axi_wstrb;
+      assign m_axi_wvalid       = s_wvalid_i;
+      assign s_wready_i         = m_axi_wready;
+      assign s_bid_i            = 0;
+      assign s_bresp_i          = m_axi_bresp;
+      assign s_buser_i          = 0;
+      assign s_bvalid_i         = m_axi_bvalid;
+      assign m_axi_bready       = s_bready_i;
+      assign m_axi_araddr       = s_axi_araddr;
+      assign m_axi_arprot       = s_axi_arprot;
+      assign m_axi_arvalid      = s_arvalid_i;
+      assign s_arready_i        = m_axi_arready;
+      assign s_rid_i            = 0;
+      assign s_rdata_i          = m_axi_rdata;
+      assign s_rresp_i          = m_axi_rresp;
+      assign s_rlast_i          = 1\'b1;
+      assign s_ruser_i          = 0;
+      assign s_rvalid_i         = m_axi_rvalid;
+      assign m_axi_rready       = s_rready_i;
+      
+    end else if (C_TRANSLATION_MODE == P_CONVERSION) begin : gen_b2s_conv
+      assign s_buser_i = {C_AXI_BUSER_WIDTH{1\'b0}};
+      assign s_ruser_i = {C_AXI_RUSER_WIDTH{1\'b0}};
+
+      axi_protocol_converter_v2_1_11_b2s #(
+        .C_S_AXI_PROTOCOL                 (C_S_AXI_PROTOCOL),
+        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
+        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
+        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
+        .C_AXI_SUPPORTS_WRITE             (C_AXI_SUPPORTS_WRITE),
+        .C_AXI_SUPPORTS_READ              (C_AXI_SUPPORTS_READ)
+      ) axilite_b2s (
+        .aresetn                          (aresetn),
+        .aclk                             (aclk),
+        .s_axi_awid                       (s_axi_awid),
+        .s_axi_awaddr                     (s_axi_awaddr),
+        .s_axi_awlen                      (s_axi_awlen),
+        .s_axi_awsize                     (s_axi_awsize),
+        .s_axi_awburst                    (s_axi_awburst),
+        .s_axi_awprot                     (s_axi_awprot),
+        .s_axi_awvalid                    (s_awvalid_i),
+        .s_axi_awready                    (s_awready_i),
+        .s_axi_wdata                      (s_axi_wdata),
+        .s_axi_wstrb                      (s_axi_wstrb),
+        .s_axi_wlast                      (s_axi_wlast),
+        .s_axi_wvalid                     (s_wvalid_i),
+        .s_axi_wready                     (s_wready_i),
+        .s_axi_bid                        (s_bid_i),
+        .s_axi_bresp                      (s_bresp_i),
+        .s_axi_bvalid                     (s_bvalid_i),
+        .s_axi_bready                     (s_bready_i),
+        .s_axi_arid                       (s_axi_arid),
+        .s_axi_araddr                     (s_axi_araddr),
+        .s_axi_arlen                      (s_axi_arlen),
+        .s_axi_arsize                     (s_axi_arsize),
+        .s_axi_arburst                    (s_axi_arburst),
+        .s_axi_arprot                     (s_axi_arprot),
+        .s_axi_arvalid                    (s_arvalid_i),
+        .s_axi_arready                    (s_arready_i),
+        .s_axi_rid                        (s_rid_i),
+        .s_axi_rdata                      (s_rdata_i),
+        .s_axi_rresp                      (s_rresp_i),
+        .s_axi_rlast                      (s_rlast_i),
+        .s_axi_rvalid                     (s_rvalid_i),
+        .s_axi_rready                     (s_rready_i),
+        .m_axi_awaddr                     (m_axi_awaddr),
+        .m_axi_awprot                     (m_axi_awprot),
+        .m_axi_awvalid                    (m_axi_awvalid),
+        .m_axi_awready                    (m_axi_awready),
+        .m_axi_wdata                      (m_axi_wdata),
+        .m_axi_wstrb                      (m_axi_wstrb),
+        .m_axi_wvalid                     (m_axi_wvalid),
+        .m_axi_wready                     (m_axi_wready),
+        .m_axi_bresp                      (m_axi_bresp),
+        .m_axi_bvalid                     (m_axi_bvalid),
+        .m_axi_bready                     (m_axi_bready),
+        .m_axi_araddr                     (m_axi_araddr),
+        .m_axi_arprot                     (m_axi_arprot),
+        .m_axi_arvalid                    (m_axi_arvalid),
+        .m_axi_arready                    (m_axi_arready),
+        .m_axi_rdata                      (m_axi_rdata),
+        .m_axi_rresp                      (m_axi_rresp),
+        .m_axi_rvalid                     (m_axi_rvalid),
+        .m_axi_rready                     (m_axi_rready)
+      );
+    end else begin : gen_axilite_conv
+      axi_protocol_converter_v2_1_11_axilite_conv #(
+        .C_FAMILY                         (C_FAMILY),
+        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
+        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
+        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
+        .C_AXI_SUPPORTS_WRITE             (C_AXI_SUPPORTS_WRITE),
+        .C_AXI_SUPPORTS_READ              (C_AXI_SUPPORTS_READ),
+        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
+        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH)
+      ) axilite_conv_inst (
+        .ARESETN                          (aresetn),
+        .ACLK                             (aclk),
+        .S_AXI_AWID                       (s_axi_awid),
+        .S_AXI_AWADDR                     (s_axi_awaddr),
+        .S_AXI_AWPROT                     (s_axi_awprot),
+        .S_AXI_AWVALID                    (s_awvalid_i),
+        .S_AXI_AWREADY                    (s_awready_i),
+        .S_AXI_WDATA                      (s_axi_wdata),
+        .S_AXI_WSTRB                      (s_axi_wstrb),
+        .S_AXI_WVALID                     (s_wvalid_i),
+        .S_AXI_WREADY                     (s_wready_i),
+        .S_AXI_BID                        (s_bid_i),
+        .S_AXI_BRESP                      (s_bresp_i),
+        .S_AXI_BUSER                      (s_buser_i),
+        .S_AXI_BVALID                     (s_bvalid_i),
+        .S_AXI_BREADY                     (s_bready_i),
+        .S_AXI_ARID                       (s_axi_arid),
+        .S_AXI_ARADDR                     (s_axi_araddr),
+        .S_AXI_ARPROT                     (s_axi_arprot),
+        .S_AXI_ARVALID                    (s_arvalid_i),
+        .S_AXI_ARREADY                    (s_arready_i),
+        .S_AXI_RID                        (s_rid_i),
+        .S_AXI_RDATA                      (s_rdata_i),
+        .S_AXI_RRESP                      (s_rresp_i),
+        .S_AXI_RLAST                      (s_rlast_i),
+        .S_AXI_RUSER                      (s_ruser_i),
+        .S_AXI_RVALID                     (s_rvalid_i),
+        .S_AXI_RREADY                     (s_rready_i),
+        .M_AXI_AWADDR                     (m_axi_awaddr),
+        .M_AXI_AWPROT                     (m_axi_awprot),
+        .M_AXI_AWVALID                    (m_axi_awvalid),
+        .M_AXI_AWREADY                    (m_axi_awready),
+        .M_AXI_WDATA                      (m_axi_wdata),
+        .M_AXI_WSTRB                      (m_axi_wstrb),
+        .M_AXI_WVALID                     (m_axi_wvalid),
+        .M_AXI_WREADY                     (m_axi_wready),
+        .M_AXI_BRESP                      (m_axi_bresp),
+        .M_AXI_BVALID                     (m_axi_bvalid),
+        .M_AXI_BREADY                     (m_axi_bready),
+        .M_AXI_ARADDR                     (m_axi_araddr),
+        .M_AXI_ARPROT                     (m_axi_arprot),
+        .M_AXI_ARVALID                    (m_axi_arvalid),
+        .M_AXI_ARREADY                    (m_axi_arready),
+        .M_AXI_RDATA                      (m_axi_rdata),
+        .M_AXI_RRESP                      (m_axi_rresp),
+        .M_AXI_RVALID                     (m_axi_rvalid),
+        .M_AXI_RREADY                     (m_axi_rready)
+      );
+    end
+  end else if ((C_M_AXI_PROTOCOL == P_AXI3) && (C_S_AXI_PROTOCOL == P_AXI4)) begin : gen_axi4_axi3
+    axi_protocol_converter_v2_1_11_axi3_conv #(
+      .C_FAMILY                         (C_FAMILY),
+      .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
+      .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
+      .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
+      .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),
+      .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),
+      .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),
+      .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),
+      .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
+      .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),
+      .C_AXI_SUPPORTS_WRITE             (C_AXI_SUPPORTS_WRITE),
+      .C_AXI_SUPPORTS_READ              (C_AXI_SUPPORTS_READ),
+      .C_SUPPORT_SPLITTING              ((C_TRANSLATION_MODE == P_CONVERSION) ? 1 : 0)
+    ) axi3_conv_inst (
+      .ARESETN                          (aresetn),
+      .ACLK                             (aclk),
+      .S_AXI_AWID                       (s_axi_awid),
+      .S_AXI_AWADDR                     (s_axi_awaddr),
+      .S_AXI_AWLEN                      (s_axi_awlen),
+      .S_AXI_AWSIZE                     (s_axi_awsize),
+      .S_AXI_AWBURST                    (s_axi_awburst),
+      .S_AXI_AWLOCK                     (s_axi_awlock),
+      .S_AXI_AWCACHE                    (s_axi_awcache),
+      .S_AXI_AWPROT                     (s_axi_awprot),
+      .S_AXI_AWQOS                      (s_axi_awqos),
+      .S_AXI_AWUSER                     (s_axi_awuser),
+      .S_AXI_AWVALID                    (s_awvalid_i),
+      .S_AXI_AWREADY                    (s_awready_i),
+      .S_AXI_WDATA                      (s_axi_wdata),
+      .S_AXI_WSTRB                      (s_axi_wstrb),
+      .S_AXI_WLAST                      (s_axi_wlast),
+      .S_AXI_WUSER                      (s_axi_wuser),
+      .S_AXI_WVALID                     (s_wvalid_i),
+      .S_AXI_WREADY                     (s_wready_i),
+      .S_AXI_BID                        (s_bid_i),
+      .S_AXI_BRESP                      (s_bresp_i),
+      .S_AXI_BUSER                      (s_buser_i),
+      .S_AXI_BVALID                     (s_bvalid_i),
+      .S_AXI_BREADY                     (s_bready_i),
+      .S_AXI_ARID                       (s_axi_arid),
+      .S_AXI_ARADDR                     (s_axi_araddr),
+      .S_AXI_ARLEN                      (s_axi_arlen),
+      .S_AXI_ARSIZE                     (s_axi_arsize),
+      .S_AXI_ARBURST                    (s_axi_arburst),
+      .S_AXI_ARLOCK                     (s_axi_arlock),
+      .S_AXI_ARCACHE                    (s_axi_arcache),
+      .S_AXI_ARPROT                     (s_axi_arprot),
+      .S_AXI_ARQOS                      (s_axi_arqos),
+      .S_AXI_ARUSER                     (s_axi_aruser),
+      .S_AXI_ARVALID                    (s_arvalid_i),
+      .S_AXI_ARREADY                    (s_arready_i),
+      .S_AXI_RID                        (s_rid_i),
+      .S_AXI_RDATA                      (s_rdata_i),
+      .S_AXI_RRESP                      (s_rresp_i),
+      .S_AXI_RLAST                      (s_rlast_i),
+      .S_AXI_RUSER                      (s_ruser_i),
+      .S_AXI_RVALID                     (s_rvalid_i),
+      .S_AXI_RREADY                     (s_rready_i),
+      .M_AXI_AWID                       (m_axi_awid),
+      .M_AXI_AWADDR                     (m_axi_awaddr),
+      .M_AXI_AWLEN                      (m_axi_awlen),
+      .M_AXI_AWSIZE                     (m_axi_awsize),
+      .M_AXI_AWBURST                    (m_axi_awburst),
+      .M_AXI_AWLOCK                     (m_axi_awlock),
+      .M_AXI_AWCACHE                    (m_axi_awcache),
+      .M_AXI_AWPROT                     (m_axi_awprot),
+      .M_AXI_AWQOS                      (m_axi_awqos),
+      .M_AXI_AWUSER                     (m_axi_awuser),
+      .M_AXI_AWVALID                    (m_axi_awvalid),
+      .M_AXI_AWREADY                    (m_axi_awready),
+      .M_AXI_WID                        (m_axi_wid),
+      .M_AXI_WDATA                      (m_axi_wdata),
+      .M_AXI_WSTRB                      (m_axi_wstrb),
+      .M_AXI_WLAST                      (m_axi_wlast),
+      .M_AXI_WUSER                      (m_axi_wuser),
+      .M_AXI_WVALID                     (m_axi_wvalid),
+      .M_AXI_WREADY                     (m_axi_wready),
+      .M_AXI_BID                        (m_axi_bid),
+      .M_AXI_BRESP                      (m_axi_bresp),
+      .M_AXI_BUSER                      (m_axi_buser),
+      .M_AXI_BVALID                     (m_axi_bvalid),
+      .M_AXI_BREADY                     (m_axi_bready),
+      .M_AXI_ARID                       (m_axi_arid),
+      .M_AXI_ARADDR                     (m_axi_araddr),
+      .M_AXI_ARLEN                      (m_axi_arlen),
+      .M_AXI_ARSIZE                     (m_axi_arsize),
+      .M_AXI_ARBURST                    (m_axi_arburst),
+      .M_AXI_ARLOCK                     (m_axi_arlock),
+      .M_AXI_ARCACHE                    (m_axi_arcache),
+      .M_AXI_ARPROT                     (m_axi_arprot),
+      .M_AXI_ARQOS                      (m_axi_arqos),
+      .M_AXI_ARUSER                     (m_axi_aruser),
+      .M_AXI_ARVALID                    (m_axi_arvalid),
+      .M_AXI_ARREADY                    (m_axi_arready),
+      .M_AXI_RID                        (m_axi_rid),
+      .M_AXI_RDATA                      (m_axi_rdata),
+      .M_AXI_RRESP                      (m_axi_rresp),
+      .M_AXI_RLAST                      (m_axi_rlast),
+      .M_AXI_RUSER                      (m_axi_ruser),
+      .M_AXI_RVALID                     (m_axi_rvalid),
+      .M_AXI_RREADY                     (m_axi_rready)
+    );
+    assign m_axi_awregion     = 0;
+    assign m_axi_arregion     = 0;
+    
+  end else if ((C_S_AXI_PROTOCOL == P_AXI3) && (C_M_AXI_PROTOCOL == P_AXI4)) begin : gen_axi3_axi4
+    assign m_axi_awid                = s_axi_awid;
+    assign m_axi_awaddr              = s_axi_awaddr;
+    assign m_axi_awlen               = {4\'h0, s_axi_awlen[3:0]};
+    assign m_axi_awsize              = s_axi_awsize;
+    assign m_axi_awburst             = s_axi_awburst;
+    assign m_axi_awlock              = s_axi_awlock[0];
+    assign m_axi_awcache             = s_axi_awcache;
+    assign m_axi_awprot              = s_axi_awprot;
+    assign m_axi_awregion            = 4\'h0;
+    assign m_axi_awqos               = s_axi_awqos;
+    assign m_axi_awuser              = s_axi_awuser;
+    assign m_axi_awvalid             = s_awvalid_i;
+    assign s_awready_i               = m_axi_awready;
+    assign m_axi_wid                 = {C_AXI_ID_WIDTH{1\'b0}} ;
+    assign m_axi_wdata               = s_axi_wdata;
+    assign m_axi_wstrb               = s_axi_wstrb;
+    assign m_axi_wlast               = s_axi_wlast;
+    assign m_axi_wuser               = s_axi_wuser;
+    assign m_axi_wvalid              = s_wvalid_i;
+    assign s_wready_i                = m_axi_wready;
+    assign s_bid_i                   = m_axi_bid;
+    assign s_bresp_i                 = m_axi_bresp;
+    assign s_buser_i                 = m_axi_buser;
+    assign s_bvalid_i                = m_axi_bvalid;
+    assign m_axi_bready              = s_bready_i;
+    assign m_axi_arid                = s_axi_arid;
+    assign m_axi_araddr              = s_axi_araddr;
+    assign m_axi_arlen               = {4\'h0, s_axi_arlen[3:0]};
+    assign m_axi_arsize              = s_axi_arsize;
+    assign m_axi_arburst             = s_axi_arburst;
+    assign m_axi_arlock              = s_axi_arlock[0];
+    assign m_axi_arcache             = s_axi_arcache;
+    assign m_axi_arprot              = s_axi_arprot;
+    assign m_axi_arregion            = 4\'h0;
+    assign m_axi_arqos               = s_axi_arqos;
+    assign m_axi_aruser              = s_axi_aruser;
+    assign m_axi_arvalid             = s_arvalid_i;
+    assign s_arready_i               = m_axi_arready;
+    assign s_rid_i                   = m_axi_rid;
+    assign s_rdata_i                 = m_axi_rdata;
+    assign s_rresp_i                 = m_axi_rresp;
+    assign s_rlast_i                 = m_axi_rlast;
+    assign s_ruser_i                 = m_axi_ruser;
+    assign s_rvalid_i                = m_axi_rvalid;
+    assign m_axi_rready              = s_rready_i;
+    
+  end else begin :gen_no_conv
+    assign m_axi_awid                = s_axi_awid;
+    assign m_axi_awaddr              = s_axi_awaddr;
+    assign m_axi_awlen               = s_axi_awlen;
+    assign m_axi_awsize              = s_axi_awsize;
+    assign m_axi_awburst             = s_axi_awburst;
+    assign m_axi_awlock              = s_axi_awlock;
+    assign m_axi_awcache             = s_axi_awcache;
+    assign m_axi_awprot              = s_axi_awprot;
+    assign m_axi_awregion            = s_axi_awregion;
+    assign m_axi_awqos               = s_axi_awqos;
+    assign m_axi_awuser              = s_axi_awuser;
+    assign m_axi_awvalid             = s_awvalid_i;
+    assign s_awready_i               = m_axi_awready;
+    assign m_axi_wid                 = s_axi_wid;
+    assign m_axi_wdata               = s_axi_wdata;
+    assign m_axi_wstrb               = s_axi_wstrb;
+    assign m_axi_wlast               = s_axi_wlast;
+    assign m_axi_wuser               = s_axi_wuser;
+    assign m_axi_wvalid              = s_wvalid_i;
+    assign s_wready_i                = m_axi_wready;
+    assign s_bid_i                   = m_axi_bid;
+    assign s_bresp_i                 = m_axi_bresp;
+    assign s_buser_i                 = m_axi_buser;
+    assign s_bvalid_i                = m_axi_bvalid;
+    assign m_axi_bready              = s_bready_i;
+    assign m_axi_arid                = s_axi_arid;
+    assign m_axi_araddr              = s_axi_araddr;
+    assign m_axi_arlen               = s_axi_arlen;
+    assign m_axi_arsize              = s_axi_arsize;
+    assign m_axi_arburst             = s_axi_arburst;
+    assign m_axi_arlock              = s_axi_arlock;
+    assign m_axi_arcache             = s_axi_arcache;
+    assign m_axi_arprot              = s_axi_arprot;
+    assign m_axi_arregion            = s_axi_arregion;
+    assign m_axi_arqos               = s_axi_arqos;
+    assign m_axi_aruser              = s_axi_aruser;
+    assign m_axi_arvalid             = s_arvalid_i;
+    assign s_arready_i               = m_axi_arready;
+    assign s_rid_i                   = m_axi_rid;
+    assign s_rdata_i                 = m_axi_rdata;
+    assign s_rresp_i                 = m_axi_rresp;
+    assign s_rlast_i                 = m_axi_rlast;
+    assign s_ruser_i                 = m_axi_ruser;
+    assign s_rvalid_i                = m_axi_rvalid;
+    assign m_axi_rready              = s_rready_i;
+  end
+  
+    if ((C_TRANSLATION_MODE == P_PROTECTION) && 
+        (((C_S_AXI_PROTOCOL != P_AXILITE) && (C_M_AXI_PROTOCOL == P_AXILITE)) ||
+        ((C_S_AXI_PROTOCOL == P_AXI4) && (C_M_AXI_PROTOCOL == P_AXI3)))) begin : gen_err_detect
+
+      wire                           e_awvalid;
+      reg                            e_awvalid_r;
+      wire                           e_arvalid;
+      reg                            e_arvalid_r;
+      wire                           e_wvalid;
+      wire                           e_bvalid;
+      wire                           e_rvalid;
+      reg                            e_awready;
+      reg                            e_arready;
+      wire                           e_wready;
+      reg  [C_AXI_ID_WIDTH-1:0]      e_awid;
+      reg  [C_AXI_ID_WIDTH-1:0]      e_arid;
+      reg  [8-1:0]                   e_arlen;
+      wire [C_AXI_ID_WIDTH-1:0]      e_bid;
+      wire [C_AXI_ID_WIDTH-1:0]      e_rid;
+      wire                           e_rlast;
+      wire                           w_err;
+      wire                           r_err;
+      wire                           busy_aw;
+      wire                           busy_w;
+      wire                           busy_ar;
+      wire                           aw_push;
+      wire                           aw_pop;
+      wire                           w_pop;
+      wire                           ar_push;
+      wire                           ar_pop;
+      reg                            s_awvalid_pending;
+      reg                            s_awvalid_en;
+      reg                            s_arvalid_en;
+      reg                            s_awready_en;
+      reg                            s_arready_en;
+      reg  [4:0]                     aw_cnt;
+      reg  [4:0]                     ar_cnt;
+      reg  [4:0]                     w_cnt;
+      reg                            w_borrow;
+      reg                            err_busy_w;
+      reg                            err_busy_r;
+
+      assign w_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_awlen != 0) : ((s_axi_awlen>>4) != 0);
+      assign r_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_arlen != 0) : ((s_axi_arlen>>4) != 0);
+      assign s_awvalid_i = s_axi_awvalid & s_awvalid_en & ~w_err;
+      assign e_awvalid   = e_awvalid_r & ~busy_aw & ~busy_w;
+      assign s_arvalid_i = s_axi_arvalid & s_arvalid_en & ~r_err;
+      assign e_arvalid   = e_arvalid_r & ~busy_ar ;
+      assign s_wvalid_i = s_axi_wvalid & (busy_w | (s_awvalid_pending & ~w_borrow));
+      assign e_wvalid   = s_axi_wvalid & err_busy_w;
+      assign s_bready_i = s_axi_bready & busy_aw;
+      assign s_rready_i = s_axi_rready & busy_ar;
+      assign s_axi_awready = (s_awready_i & s_awready_en) | e_awready; 
+      assign s_axi_wready = (s_wready_i & (busy_w | (s_awvalid_pending & ~w_borrow))) | e_wready;
+      assign s_axi_bvalid = (s_bvalid_i & busy_aw) | e_bvalid;
+      assign s_axi_bid = err_busy_w ? e_bid : s_bid_i;
+      assign s_axi_bresp = err_busy_w ? P_SLVERR : s_bresp_i;
+      assign s_axi_buser = err_busy_w ? {C_AXI_BUSER_WIDTH{1\'b0}} : s_buser_i;
+      assign s_axi_arready = (s_arready_i & s_arready_en) | e_arready; 
+      assign s_axi_rvalid = (s_rvalid_i & busy_ar) | e_rvalid;
+      assign s_axi_rid = err_busy_r ? e_rid : s_rid_i;
+      assign s_axi_rresp = err_busy_r ? P_SLVERR : s_rresp_i;
+      assign s_axi_ruser = err_busy_r ? {C_AXI_RUSER_WIDTH{1\'b0}} : s_ruser_i;
+      assign s_axi_rdata = err_busy_r ? {C_AXI_DATA_WIDTH{1\'b0}} : s_rdata_i;
+      assign s_axi_rlast = err_busy_r ? e_rlast : s_rlast_i;
+      assign busy_aw = (aw_cnt != 0);
+      assign busy_w  = (w_cnt != 0);
+      assign busy_ar = (ar_cnt != 0);
+      assign aw_push = s_awvalid_i & s_awready_i & s_awready_en;
+      assign aw_pop  = s_bvalid_i & s_bready_i;
+      assign w_pop   = s_wvalid_i & s_wready_i & s_axi_wlast;
+      assign ar_push = s_arvalid_i & s_arready_i & s_arready_en;
+      assign ar_pop  = s_rvalid_i & s_rready_i & s_rlast_i;
+      
+      always @(posedge aclk) begin
+        if (~aresetn) begin
+          s_awvalid_en <= 1\'b0;
+          s_arvalid_en <= 1\'b0;
+          s_awready_en <= 1\'b0;
+          s_arready_en <= 1\'b0;
+          e_awvalid_r <= 1\'b0;
+          e_arvalid_r <= 1\'b0;
+          e_awready <= 1\'b0;
+          e_arready <= 1\'b0;
+          aw_cnt <= 0;
+          w_cnt <= 0;
+          ar_cnt <= 0;
+          err_busy_w <= 1\'b0;
+          err_busy_r <= 1\'b0;
+          w_borrow <= 1\'b0;
+          s_awvalid_pending <= 1\'b0;
+        end else begin
+          e_awready <= 1\'b0;  // One-cycle pulse
+          if (e_bvalid & s_axi_bready) begin
+            s_awvalid_en <= 1\'b1;
+            s_awready_en <= 1\'b1;
+            err_busy_w <= 1\'b0;
+          end else if (e_awvalid) begin
+            e_awvalid_r <= 1\'b0;
+            err_busy_w <= 1\'b1;
+          end else if (s_axi_awvalid & w_err & ~e_awvalid_r & ~err_busy_w) begin
+            e_awvalid_r <= 1\'b1;
+            e_awready <= ~(s_awready_i & s_awvalid_en);  // 1-cycle pulse if awready not already asserted
+            s_awvalid_en <= 1\'b0;
+            s_awready_en <= 1\'b0;
+          end else if ((&aw_cnt) | (&w_cnt) | aw_push) begin
+            s_awvalid_en <= 1\'b0;
+            s_awready_en <= 1\'b0;
+          end else if (~err_busy_w & ~e_awvalid_r & ~(s_axi_awvalid & w_err)) begin
+            s_awvalid_en <= 1\'b1;
+            s_awready_en <= 1\'b1;
+          end
+          
+          if (aw_push & ~aw_pop) begin
+            aw_cnt <= aw_cnt + 1;
+          end else if (~aw_push & aw_pop & (|aw_cnt)) begin
+            aw_cnt <= aw_cnt - 1;
+          end
+          if (aw_push) begin
+            if (~w_pop & ~w_borrow) begin
+              w_cnt <= w_cnt + 1;
+            end
+            w_borrow <= 1\'b0;
+          end else if (~aw_push & w_pop) begin
+            if (|w_cnt) begin
+              w_cnt <= w_cnt - 1;
+            end else begin
+              w_borrow <= 1\'b1;
+            end
+          end
+          s_awvalid_pending <= s_awvalid_i & ~s_awready_i;
+          
+          e_arready <= 1\'b0;  // One-cycle pulse
+          if (e_rvalid & s_axi_rready & e_rlast) begin
+            s_arvalid_en <= 1\'b1;
+            s_arready_en <= 1\'b1;
+            err_busy_r <= 1\'b0;
+          end else if (e_arvalid) begin
+            e_arvalid_r <= 1\'b0;
+            err_busy_r <= 1\'b1;
+          end else if (s_axi_arvalid & r_err & ~e_arvalid_r & ~err_busy_r) begin
+            e_arvalid_r <= 1\'b1;
+            e_arready <= ~(s_arready_i & s_arvalid_en);  // 1-cycle pulse if arready not already asserted
+            s_arvalid_en <= 1\'b0;
+            s_arready_en <= 1\'b0;
+          end else if ((&ar_cnt) | ar_push) begin
+            s_arvalid_en <= 1\'b0;
+            s_arready_en <= 1\'b0;
+          end else if (~err_busy_r & ~e_arvalid_r & ~(s_axi_arvalid & r_err)) begin
+            s_arvalid_en <= 1\'b1;
+            s_arready_en <= 1\'b1;
+          end
+          
+          if (ar_push & ~ar_pop) begin
+            ar_cnt <= ar_cnt + 1;
+          end else if (~ar_push & ar_pop & (|ar_cnt)) begin
+            ar_cnt <= ar_cnt - 1;
+          end
+        end
+      end
+      
+      always @(posedge aclk) begin
+        if (s_axi_awvalid & ~err_busy_w & ~e_awvalid_r ) begin
+          e_awid <= s_axi_awid;
+        end
+        if (s_axi_arvalid & ~err_busy_r & ~e_arvalid_r ) begin
+          e_arid <= s_axi_arid;
+          e_arlen <= s_axi_arlen;
+        end
+      end
+      
+      axi_protocol_converter_v2_1_11_decerr_slave #
+        (
+         .C_AXI_ID_WIDTH                 'b'(C_AXI_ID_WIDTH),
+         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),
+         .C_AXI_RUSER_WIDTH              (C_AXI_RUSER_WIDTH),
+         .C_AXI_BUSER_WIDTH              (C_AXI_BUSER_WIDTH),
+         .C_AXI_PROTOCOL                 (C_S_AXI_PROTOCOL),
+         .C_RESP                         (P_SLVERR),
+         .C_IGNORE_ID                    (C_IGNORE_ID)
+        )
+        decerr_slave_inst
+          (
+           .ACLK (aclk),
+           .ARESETN (aresetn),
+           .S_AXI_AWID (e_awid),
+           .S_AXI_AWVALID (e_awvalid),
+           .S_AXI_AWREADY (),
+           .S_AXI_WLAST (s_axi_wlast),
+           .S_AXI_WVALID (e_wvalid),
+           .S_AXI_WREADY (e_wready),
+           .S_AXI_BID (e_bid),
+           .S_AXI_BRESP (),
+           .S_AXI_BUSER (),
+           .S_AXI_BVALID (e_bvalid),
+           .S_AXI_BREADY (s_axi_bready),
+           .S_AXI_ARID (e_arid),
+           .S_AXI_ARLEN (e_arlen),
+           .S_AXI_ARVALID (e_arvalid),
+           .S_AXI_ARREADY (),
+           .S_AXI_RID (e_rid),
+           .S_AXI_RDATA (),
+           .S_AXI_RRESP (),
+           .S_AXI_RUSER (),
+           .S_AXI_RLAST (e_rlast),
+           .S_AXI_RVALID (e_rvalid),
+           .S_AXI_RREADY (s_axi_rready)
+         );
+    end else begin : gen_no_err_detect
+      assign s_awvalid_i = s_axi_awvalid;
+      assign s_arvalid_i = s_axi_arvalid;
+      assign s_wvalid_i = s_axi_wvalid;
+      assign s_bready_i = s_axi_bready;
+      assign s_rready_i = s_axi_rready;
+      assign s_axi_awready = s_awready_i; 
+      assign s_axi_wready = s_wready_i;
+      assign s_axi_bvalid = s_bvalid_i;
+      assign s_axi_bid = s_bid_i;
+      assign s_axi_bresp = s_bresp_i;
+      assign s_axi_buser = s_buser_i;
+      assign s_axi_arready = s_arready_i; 
+      assign s_axi_rvalid = s_rvalid_i;
+      assign s_axi_rid = s_rid_i;
+      assign s_axi_rresp = s_rresp_i;
+      assign s_axi_ruser = s_ruser_i;
+      assign s_axi_rdata = s_rdata_i;
+      assign s_axi_rlast = s_rlast_i;
+    end  // gen_err_detect
+endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_local_params.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Parameters used in Zynq BFM
+ *
+ *****************************************************************************/
+
+/* local */ 
+parameter m_axi_gp0_baseaddr = 32\'h4000_0000;
+parameter m_axi_gp1_baseaddr = 32\'h8000_0000;
+parameter m_axi_gp0_highaddr = 32\'h7FFF_FFFF;
+parameter m_axi_gp1_highaddr = 32\'hBFFF_FFFF;
+
+parameter addr_width = 32;   // maximum address width
+parameter data_width = 32;   // maximum data width.
+parameter max_chars  = 128;  // max characters for file name
+parameter mem_width  = data_width/8; /// memory width in bytes
+parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
+parameter int_width  = 32; //integre width
+
+/* for internal read/write APIs used for data transfers */
+parameter max_burst_len   = 16;  /// maximum brst length on axi 
+parameter max_data_width  = 64; // maximum data width for internal AXI bursts 
+parameter max_burst_bits  = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts 
+parameter max_burst_bytes = (max_burst_bits)/8;                // maximum data bytes in each transfer 
+parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts 
+
+parameter max_registers   = 32;
+parameter max_regs_width  = clogb2(max_registers);
+
+parameter REG_MEM = 2\'b00, DDR_MEM = 2\'b01, OCM_MEM = 2\'b10, INVALID_MEM_TYPE = 2\'b11; 
+
+/* Interrupt bits supported */
+parameter irq_width = 16;
+
+/* GP Master0 & Master1 address decode */
+parameter GP_M0 = 2\'b01;
+parameter GP_M1 = 2\'b10;
+
+parameter ALL_RANDOM= 2\'b00;
+parameter ALL_ZEROS = 2\'b01;
+parameter ALL_ONES  = 2\'b10;
+
+parameter ddr_start_addr = 32\'h0008_0000;
+parameter ddr_end_addr   = 32\'h3FFF_FFFF;
+
+parameter ocm_start_addr = 32\'h0000_0000;
+parameter ocm_end_addr   = 32\'h0003_FFFF;
+parameter high_ocm_start_addr = 32\'hFFFC_0000;
+parameter high_ocm_end_addr   = 32\'hFFFF_FFFF;
+parameter ocm_low_addr   = 32\'hFFFF_0000;
+
+parameter reg_start_addr = 32\'hE000_0000;
+parameter reg_end_addr   = 32\'hF8F0_2F80;
+
+
+/* for Master port APIs and AXI protocol related signal widths*/
+parameter axi_burst_len  = 16;
+parameter axi_len_width  = clogb2(axi_burst_len);
+parameter axi_size_width = 3;
+parameter axi_brst_type_width = 2;
+parameter axi_lock_width = 2;
+parameter axi_cache_width = 4;
+parameter axi_prot_width = 3;
+parameter axi_rsp_width = 2;
+parameter axi_mgp_data_width = 32;
+parameter axi_mgp_id_width   = 12;
+parameter axi_mgp_outstanding = 8;
+parameter axi_mgp_wr_id = 12\'hC00;
+parameter axi_mgp_rd_id = 12\'hC0C;
+parameter axi_mgp0_name  = ""M_AXI_GP0"";
+parameter axi_mgp1_name  = ""M_AXI_GP1"";
+parameter axi_qos_width  = 4;
+parameter max_transfer_bytes = 128; // For Master APIs.
+parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
+
+
+/* for GP slave ports*/
+parameter axi_sgp_data_width = 32;
+parameter axi_sgp_id_width   = 6;
+parameter axi_sgp_rd_outstanding = 8;
+parameter axi_sgp_wr_outstanding = 8;
+parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
+parameter axi_sgp0_name  = ""S_AXI_GP0"";
+parameter axi_sgp1_name  = ""S_AXI_GP1"";
+
+/* for ACP slave ports*/
+parameter axi_acp_data_width = 64;
+parameter axi_acp_id_width   = 3;
+parameter axi_acp_rd_outstanding = 7;
+parameter axi_acp_wr_outstanding = 3;
+parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
+parameter axi_acp_name  = ""S_AXI_ACP"";
+
+/* for HP slave ports*/
+parameter axi_hp_id_width   = 6;
+parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
+parameter axi_hp0_name  = ""S_AXI_HP0"";
+parameter axi_hp1_name  = ""S_AXI_HP1"";
+parameter axi_hp2_name  = ""S_AXI_HP2"";
+parameter axi_hp3_name  = ""S_AXI_HP3"";
+
+
+parameter axi_slv_excl_support = 0; // For Slave  ports EXCL access is not supported
+parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
+
+/* AXI transfer types */
+parameter AXI_FIXED = 2\'b00;
+parameter AXI_INCR  = 2\'b01;
+parameter AXI_WRAP  = 2\'b10;
+
+/* Exclusive Access */
+parameter AXI_NRML  = 2\'b00;
+parameter AXI_EXCL  = 2\'b01;
+parameter AXI_LOCK  = 2\'b10;
+
+/* AXI Response types */
+parameter AXI_OK = 2\'b00;
+parameter AXI_EXCL_OK  = 2\'b01;
+parameter AXI_SLV_ERR  = 2\'b10;
+parameter AXI_DEC_ERR  = 2\'b11;
+
+function automatic integer clogb2;
+  input [31:0] value;
+  begin
+      value = value - 1;
+      for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
+          value = value >> 1;
+      end
+  end
+endfunction
+
+/* needed only for AFI modules  and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
+  /* WR FIFO data */
+  parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
+  parameter wr_bytes_lsb = 0;
+  parameter wr_bytes_msb = max_burst_bytes_width;
+  parameter wr_addr_lsb  = wr_bytes_msb + 1;
+  parameter wr_addr_msb  = wr_addr_lsb + addr_width-1;
+  parameter wr_data_lsb  = wr_addr_msb + 1;
+  parameter wr_data_msb  = wr_data_lsb + max_burst_bits-1;
+  parameter wr_qos_lsb   = wr_data_msb + 1;
+  parameter wr_qos_msb   = wr_qos_lsb + axi_qos_width-1;
+ 
+  /* WR AFI FIFO data */ 
+    /* ID -  1071:1066
+     Resp - 1065:1064
+     data - 1063:40   
+     address - 39:8
+     valid_bytes - 7:0
+    */
+  parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
+  parameter wr_afi_bytes_lsb = 0;
+  parameter wr_afi_bytes_msb = max_burst_bytes_width;
+  parameter wr_afi_addr_lsb  = wr_afi_bytes_msb + 1;
+  parameter wr_afi_addr_msb  = wr_afi_addr_lsb + addr_width-1;
+  parameter wr_afi_data_lsb  = wr_afi_addr_msb + 1;
+  parameter wr_afi_data_msb  = wr_afi_data_lsb + max_burst_bits-1; 
+  parameter wr_afi_rsp_lsb   = wr_afi_data_msb + 1; 
+  parameter wr_afi_rsp_msb   = wr_afi_rsp_lsb + axi_rsp_width-1; 
+  parameter wr_afi_id_lsb    = wr_afi_rsp_msb + 1; 
+  parameter wr_afi_id_msb    = wr_afi_id_lsb + axi_hp_id_width-1; 
+  parameter wr_afi_ln_lsb    = wr_afi_id_msb + 1;
+  parameter wr_afi_ln_msb    = wr_afi_ln_lsb + axi_len_width-1;
+  parameter wr_afi_qos_lsb   = wr_afi_ln_msb + 1;
+  parameter wr_afi_qos_msb   = wr_afi_qos_lsb + axi_qos_width-1;
+
+
+  parameter afi_fifo_size    = 1024; /// AFI FIFO is stored as 1024-bytes 
+  parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
+  parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
+
+/* for interconnect fifo models */
+  parameter intr_max_outstanding = 8;
+  parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
+  parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width +  axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
+  parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
+
+  //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
+  parameter rd_afi_bytes_lsb = 0;
+  parameter rd_afi_bytes_msb = max_burst_bytes_width;
+  parameter rd_afi_rsp_lsb   = rd_afi_bytes_msb + 1; 
+  parameter rd_afi_rsp_msb   = rd_afi_rsp_lsb + axi_rsp_width-1; 
+  parameter rd_afi_id_lsb    = rd_afi_rsp_msb + 1; 
+  parameter rd_afi_id_msb    = rd_afi_id_lsb + axi_hp_id_width-1; 
+  parameter rd_afi_ln_lsb    = rd_afi_id_msb + 1;
+  parameter rd_afi_ln_msb    = rd_afi_ln_lsb + axi_len_width-1;
+  parameter rd_afi_brst_lsb  = rd_afi_ln_msb + 1;
+  parameter rd_afi_brst_msb  = rd_afi_brst_lsb + axi_brst_type_width-1;
+  parameter rd_afi_siz_lsb   = rd_afi_brst_msb + 1;
+  parameter rd_afi_siz_msb   = rd_afi_siz_lsb + axi_size_width-1;
+  parameter rd_afi_addr_lsb  = rd_afi_siz_msb + 1;
+  parameter rd_afi_addr_msb  = rd_afi_addr_lsb + addr_width-1;
+  parameter rd_afi_data_lsb  = rd_afi_addr_msb + 1;
+  parameter rd_afi_data_msb  = rd_afi_data_lsb + max_burst_bits-1; 
+
+
+/* Latency types */
+ parameter BEST_CASE  = 0;
+ parameter AVG_CASE   = 1;
+ parameter WORST_CASE = 2;
+ parameter RANDOM_CASE  = 3;
+
+/* Latency Parameters ACP  */
+  parameter acp_wr_min   =  21;
+  parameter acp_wr_avg   =  16;
+  parameter acp_wr_max   =  27;
+  parameter acp_rd_min   =  34;
+  parameter acp_rd_avg   =  125;
+  parameter acp_rd_max   =  130; 
+
+/* Latency Parameters GP  */
+  parameter gp_wr_min   =  21;
+  parameter gp_wr_avg   =  16;
+  parameter gp_wr_max   =  46;
+  parameter gp_rd_min   =  38;
+  parameter gp_rd_avg   =  125;
+  parameter gp_rd_max   =  130; 
+
+/* Latency Parameters HP  */
+  parameter afi_wr_min  =  37;
+  parameter afi_wr_avg  =  41;
+  parameter afi_wr_max  =  42;
+  parameter afi_rd_min  =  41;
+  parameter afi_rd_avg  =  221;
+  parameter afi_rd_max  =  229; 
+
+/* ID VALID and INVALID */
+  parameter secure_access_enabled = 0;
+  parameter id_invalid = 0;
+  parameter id_valid = 1;
+
+/* Display */
+  parameter DISP_INFO = ""*ZYNQ_BFM_INFO"";
+  parameter DISP_WARN = ""*ZYNQ_BFM_WARNING"";
+  parameter DISP_ERR  = ""*ZYNQ_BFM_ERROR"";
+  parameter DISP_INT_INFO = ""ZYNQ_BFM_INT_INFO"";
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:35:10 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_1_0_sim_netlist.v
+// Design      : design_1_axi_gpio_1_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
+   (D,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    ip2bus_rdack_i,
+    ip2bus_wrack_i_D1_reg,
+    gpio_io_o,
+    gpio_io_t,
+    Q,
+    bus2ip_rnw_i_reg,
+    \\Not_Dual.gpio_Data_In_reg[3]_0 ,
+    s_axi_aclk,
+    \\Not_Dual.gpio_Data_In_reg[2]_0 ,
+    \\Not_Dual.gpio_Data_In_reg[1]_0 ,
+    GPIO_DBus_i,
+    SS,
+    bus2ip_rnw,
+    bus2ip_cs,
+    gpio_io_i,
+    E,
+    \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
+    rst_reg);
+  output [3:0]D;
+  output GPIO_xferAck_i;
+  output gpio_xferAck_Reg;
+  output ip2bus_rdack_i;
+  output ip2bus_wrack_i_D1_reg;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  output [3:0]Q;
+  input bus2ip_rnw_i_reg;
+  input \\Not_Dual.gpio_Data_In_reg[3]_0 ;
+  input s_axi_aclk;
+  input \\Not_Dual.gpio_Data_In_reg[2]_0 ;
+  input \\Not_Dual.gpio_Data_In_reg[1]_0 ;
+  input [0:0]GPIO_DBus_i;
+  input [0:0]SS;
+  input bus2ip_rnw;
+  input bus2ip_cs;
+  input [3:0]gpio_io_i;
+  input [0:0]E;
+  input [3:0]\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  input [0:0]rst_reg;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  wire \\Not_Dual.gpio_Data_In_reg[1]_0 ;
+  wire \\Not_Dual.gpio_Data_In_reg[2]_0 ;
+  wire \\Not_Dual.gpio_Data_In_reg[3]_0 ;
+  wire [3:0]Q;
+  wire [0:0]SS;
+  wire bus2ip_cs;
+  wire bus2ip_rnw;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio_io_i;
+  wire [0:3]gpio_io_i_d2;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire iGPIO_xferAck;
+  wire ip2bus_rdack_i;
+  wire ip2bus_wrack_i_D1_reg;
+  wire [0:0]rst_reg;
+  wire s_axi_aclk;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \\Not_Dual.INPUT_DOUBLE_REGS3 
+       (.gpio_io_i(gpio_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
+  FDRE \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus_i),
+        .Q(D[3]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[1]_0 ),
+        .Q(D[2]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[2]_0 ),
+        .Q(D[1]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[3]_0 ),
+        .Q(D[0]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.gpio_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[0]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[1]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[2]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[3]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
+        .Q(gpio_io_o[3]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
+        .Q(gpio_io_o[2]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
+        .Q(gpio_io_o[1]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
+        .Q(gpio_io_o[0]),
+        .R(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
+        .Q(gpio_io_t[3]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
+        .Q(gpio_io_t[2]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
+        .Q(gpio_io_t[1]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
+        .Q(gpio_io_t[0]),
+        .S(SS));
+  FDRE gpio_xferAck_Reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_xferAck_i),
+        .Q(gpio_xferAck_Reg),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'h02)) 
+    iGPIO_xferAck_i_1
+       (.I0(bus2ip_cs),
+        .I1(gpio_xferAck_Reg),
+        .I2(GPIO_xferAck_i),
+        .O(iGPIO_xferAck));
+  FDRE iGPIO_xferAck_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(iGPIO_xferAck),
+        .Q(GPIO_xferAck_i),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    ip2bus_rdack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_rdack_i));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    ip2bus_wrack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_wrack_i_D1_reg));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
+   (\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_arready,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_aclk,
+    rst_reg,
+    bus2ip_rnw_i_reg,
+    Q,
+    ip2bus_rdack_i_D1,
+    is_read,
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
+    ip2bus_wrack_i_D1,
+    is_write_reg,
+    \\Not_Dual.gpio_Data_In_reg[0] ,
+    gpio_io_t,
+    s_axi_wdata,
+    start2_reg,
+    s_axi_aresetn,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i);
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  input s_axi_aclk;
+  input rst_reg;
+  input bus2ip_rnw_i_reg;
+  input [2:0]Q;
+  input ip2bus_rdack_i_D1;
+  input is_read;
+  input [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  input ip2bus_wrack_i_D1;
+  input is_write_reg;
+  input [3:0]\\Not_Dual.gpio_Data_In_reg[0] ;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input start2_reg;
+  input s_axi_aresetn;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire [3:0]\\Not_Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [2:0]Q;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_write_reg;
+  wire rst_reg;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire start2_reg;
+
+  LUT5 #(
+    .INIT(32\'h000000E0)) 
+    \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1 
+       (.I0(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I1(start2_reg),
+        .I2(s_axi_aresetn),
+        .I3(s_axi_arready),
+        .I4(s_axi_wready),
+        .O(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
+  FDRE \\MEM_DECODE_GEN[0].cs_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
+        .Q(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [3]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[3]),
+        .O(GPIO_DBus_i));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [2]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[2]),
+        .O(\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [1]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[1]),
+        .O(\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ));
+  LUT4 #(
+    .INIT(16\'hFFF7)) 
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I2(gpio_xferAck_Reg),
+        .I3(GPIO_xferAck_i),
+        .O(\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_2 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [0]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[0]),
+        .O(\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAAABAA)) 
+    \\Not_Dual.gpio_Data_Out[0]_i_1 
+       (.I0(rst_reg),
+        .I1(bus2ip_rnw_i_reg),
+        .I2(Q[0]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(Q[2]),
+        .I5(Q[1]),
+        .O(E));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[0]_i_2 
+       (.I0(s_axi_wdata[3]),
+        .I1(s_axi_wdata[7]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[3]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[1]_i_1 
+       (.I0(s_axi_wdata[2]),
+        .I1(s_axi_wdata[6]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[2]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[2]_i_1 
+       (.I0(s_axi_wdata[1]),
+        .I1(s_axi_wdata[5]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[1]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[3]_i_1 
+       (.I0(s_axi_wdata[0]),
+        .I1(s_axi_wdata[4]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[0]));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAABAAAAA)) 
+    \\Not_Dual.gpio_OE[0]_i_1 
+       (.I0(rst_reg),
+        .I1(bus2ip_rnw_i_reg),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[0]),
+        .I5(Q[1]),
+        .O(\\Not_Dual.gpio_OE_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAEAAAA)) 
+    s_axi_arready_INST_0
+       (.I0(ip2bus_rdack_i_D1),
+        .I1(is_read),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
+        .I5(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
+        .O(s_axi_arready));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAEAAAA)) 
+    s_axi_wready_INST_0
+       (.I0(ip2bus_wrack_i_D1),
+        .I1(is_write_reg),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
+        .I5(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
+        .O(s_axi_wready));
+endmodule
+
+(* C_ALL_INPUTS = ""0"" *) (* C_ALL_INPUTS_2 = ""0"" *) (* C_ALL_OUTPUTS = ""0"" *) 
+(* C_ALL_OUTPUTS_2 = ""0"" *) (* C_DOUT_DEFAULT = ""0"" *) (* C_DOUT_DEFAULT_2 = ""0"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_GPIO2_WIDTH = ""32"" *) (* C_GPIO_WIDTH = ""4"" *) 
+(* C_INTERRUPT_PRESENT = ""0"" *) (* C_IS_DUAL = ""0"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* C_TRI_DEFAULT = ""-1"" *) (* C_TRI_DEFAULT_2 = ""-1"" *) 
+(* downgradeipidentifiedwarnings = ""yes"" *) (* ip_group = ""LOGICORE"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_i,
+    gpio2_io_o,
+    gpio2_io_t);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rst"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* sigis = ""INTR_LEVEL_HIGH"" *) output ip2intc_irpt;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  input [31:0]gpio2_io_i;
+  output [31:0]gpio2_io_o;
+  output [31:0]gpio2_io_t;
+
+  wire \\<const0> ;
+  wire \\<const1> ;
+  wire AXI_LITE_IPIF_I_n_10;
+  wire AXI_LITE_IPIF_I_n_11;
+  wire AXI_LITE_IPIF_I_n_12;
+  wire AXI_LITE_IPIF_I_n_17;
+  wire AXI_LITE_IPIF_I_n_6;
+  wire AXI_LITE_IPIF_I_n_7;
+  wire [0:3]DBus_Reg;
+  wire [28:28]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [0:3]gpio_Data_In;
+  wire gpio_core_1_n_7;
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [28:31]ip2bus_data;
+  wire [28:31]ip2bus_data_i_D1;
+  wire ip2bus_rdack_i;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rst"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  assign gpio2_io_o[31] = \\<const0> ;
+  assign gpio2_io_o[30] = \\<const0> ;
+  assign gpio2_io_o[29] = \\<const0> ;
+  assign gpio2_io_o[28] = \\<const0> ;
+  assign gpio2_io_o[27] = \\<const0> ;
+  assign gpio2_io_o[26] = \\<const0> ;
+  assign gpio2_io_o[25] = \\<const0> ;
+  assign gpio2_io_o[24] = \\<const0> ;
+  assign gpio2_io_o[23] = \\<const0> ;
+  assign gpio2_io_o[22] = \\<const0> ;
+  assign gpio2_io_o[21] = \\<const0> ;
+  assign gpio2_io_o[20] = \\<const0> ;
+  assign gpio2_io_o[19] = \\<const0> ;
+  assign gpio2_io_o[18] = \\<const0> ;
+  assign gpio2_io_o[17] = \\<const0> ;
+  assign gpio2_io_o[16] = \\<const0> ;
+  assign gpio2_io_o[15] = \\<const0> ;
+  assign gpio2_io_o[14] = \\<const0> ;
+  assign gpio2_io_o[13] = \\<const0> ;
+  assign gpio2_io_o[12] = \\<const0> ;
+  assign gpio2_io_o[11] = \\<const0> ;
+  assign gpio2_io_o[10] = \\<const0> ;
+  assign gpio2_io_o[9] = \\<const0> ;
+  assign gpio2_io_o[8] = \\<const0> ;
+  assign gpio2_io_o[7] = \\<const0> ;
+  assign gpio2_io_o[6] = \\<const0> ;
+  assign gpio2_io_o[5] = \\<const0> ;
+  assign gpio2_io_o[4] = \\<const0> ;
+  assign gpio2_io_o[3] = \\<const0> ;
+  assign gpio2_io_o[2] = \\<const0> ;
+  assign gpio2_io_o[1] = \\<const0> ;
+  assign gpio2_io_o[0] = \\<const0> ;
+  assign gpio2_io_t[31] = \\<const1> ;
+  assign gpio2_io_t[30] = \\<const1> ;
+  assign gpio2_io_t[29] = \\<const1> ;
+  assign gpio2_io_t[28] = \\<const1> ;
+  assign gpio2_io_t[27] = \\<const1> ;
+  assign gpio2_io_t[26] = \\<const1> ;
+  assign gpio2_io_t[25] = \\<const1> ;
+  assign gpio2_io_t[24] = \\<const1> ;
+  assign gpio2_io_t[23] = \\<const1> ;
+  assign gpio2_io_t[22] = \\<const1> ;
+  assign gpio2_io_t[21] = \\<const1> ;
+  assign gpio2_io_t[20] = \\<const1> ;
+  assign gpio2_io_t[19] = \\<const1> ;
+  assign gpio2_io_t[18] = \\<const1> ;
+  assign gpio2_io_t[17] = \\<const1> ;
+  assign gpio2_io_t[16] = \\<const1> ;
+  assign gpio2_io_t[15] = \\<const1> ;
+  assign gpio2_io_t[14] = \\<const1> ;
+  assign gpio2_io_t[13] = \\<const1> ;
+  assign gpio2_io_t[12] = \\<const1> ;
+  assign gpio2_io_t[11] = \\<const1> ;
+  assign gpio2_io_t[10] = \\<const1> ;
+  assign gpio2_io_t[9] = \\<const1> ;
+  assign gpio2_io_t[8] = \\<const1> ;
+  assign gpio2_io_t[7] = \\<const1> ;
+  assign gpio2_io_t[6] = \\<const1> ;
+  assign gpio2_io_t[5] = \\<const1> ;
+  assign gpio2_io_t[4] = \\<const1> ;
+  assign gpio2_io_t[3] = \\<const1> ;
+  assign gpio2_io_t[2] = \\<const1> ;
+  assign gpio2_io_t[1] = \\<const1> ;
+  assign gpio2_io_t[0] = \\<const1> ;
+  assign ip2intc_irpt = \\<const0> ;
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\<const0> ;
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\<const0> ;
+  assign s_axi_rdata[30] = \\<const0> ;
+  assign s_axi_rdata[29] = \\<const0> ;
+  assign s_axi_rdata[28] = \\<const0> ;
+  assign s_axi_rdata[27] = \\<const0> ;
+  assign s_axi_rdata[26] = \\<const0> ;
+  assign s_axi_rdata[25] = \\<const0> ;
+  assign s_axi_rdata[24] = \\<const0> ;
+  assign s_axi_rdata[23] = \\<const0> ;
+  assign s_axi_rdata[22] = \\<const0> ;
+  assign s_axi_rdata[21] = \\<const0> ;
+  assign s_axi_rdata[20] = \\<const0> ;
+  assign s_axi_rdata[19] = \\<const0> ;
+  assign s_axi_rdata[18] = \\<const0> ;
+  assign s_axi_rdata[17] = \\<const0> ;
+  assign s_axi_rdata[16] = \\<const0> ;
+  assign s_axi_rdata[15] = \\<const0> ;
+  assign s_axi_rdata[14] = \\<const0> ;
+  assign s_axi_rdata[13] = \\<const0> ;
+  assign s_axi_rdata[12] = \\<const0> ;
+  assign s_axi_rdata[11] = \\<const0> ;
+  assign s_axi_rdata[10] = \\<const0> ;
+  assign s_axi_rdata[9] = \\<const0> ;
+  assign s_axi_rdata[8] = \\<const0> ;
+  assign s_axi_rdata[7] = \\<const0> ;
+  assign s_axi_rdata[6] = \\<const0> ;
+  assign s_axi_rdata[5] = \\<const0> ;
+  assign s_axi_rdata[4] = \\<const0> ;
+  assign s_axi_rdata[3:0] = \\^s_axi_rdata [3:0];
+  assign s_axi_rresp[1] = \\<const0> ;
+  assign s_axi_rresp[0] = \\<const0> ;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
+       (.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3]}),
+        .E(AXI_LITE_IPIF_I_n_6),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_17),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_10),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_11),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_12),
+        .\\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] ({ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(\\^s_axi_rdata ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata({s_axi_wdata[31:28],s_axi_wdata[3:0]}),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+  GND GND
+       (.G(\\<const0> ));
+  VCC VCC
+       (.P(\\<const1> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
+       (.D({ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
+        .E(AXI_LITE_IPIF_I_n_6),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3]}),
+        .\\Not_Dual.gpio_Data_In_reg[1]_0 (AXI_LITE_IPIF_I_n_10),
+        .\\Not_Dual.gpio_Data_In_reg[2]_0 (AXI_LITE_IPIF_I_n_11),
+        .\\Not_Dual.gpio_Data_In_reg[3]_0 (AXI_LITE_IPIF_I_n_12),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .SS(bus2ip_reset),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_rnw(bus2ip_rnw),
+        .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_17),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i(ip2bus_rdack_i),
+        .ip2bus_wrack_i_D1_reg(gpio_core_1_n_7),
+        .rst_reg(AXI_LITE_IPIF_I_n_7),
+        .s_axi_aclk(s_axi_aclk));
+  FDRE \\ip2bus_data_i_D1_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[28]),
+        .Q(ip2bus_data_i_D1[28]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[29]),
+        .Q(ip2bus_data_i_D1[29]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[30]),
+        .Q(ip2bus_data_i_D1[30]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[31]),
+        .Q(ip2bus_data_i_D1[31]),
+        .R(bus2ip_reset));
+  FDRE ip2bus_rdack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_i),
+        .Q(ip2bus_rdack_i_D1),
+        .R(bus2ip_reset));
+  FDRE ip2bus_wrack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_core_1_n_7),
+        .Q(ip2bus_wrack_i_D1),
+        .R(bus2ip_reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
+   (bus2ip_reset,
+    bus2ip_rnw,
+    bus2ip_cs,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_aresetn,
+    s_axi_rready,
+    s_axi_bready,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    Q,
+    gpio_io_t,
+    s_axi_wdata,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output bus2ip_reset;
+  output bus2ip_rnw;
+  output bus2ip_cs;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [2:0]s_axi_araddr;
+  input [2:0]s_axi_awaddr;
+  input s_axi_aresetn;
+  input s_axi_rready;
+  input s_axi_bready;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input [3:0]Q;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [3:0]Q;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
+       (.D(D),
+        .E(E),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ),
+        .\\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw),
+        .\\Not_Dual.gpio_OE_reg[0] (\\Not_Dual.gpio_OE_reg[0] ),
+        .Q(Q),
+        .SR(bus2ip_reset),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] (\\ip2bus_data_i_D1_reg[28] ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
+   (scndry_vect_out,
+    gpio_io_i,
+    s_axi_aclk);
+  output [3:0]scndry_vect_out;
+  input [3:0]gpio_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_gpio_1_0,axi_gpio,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_gpio,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_I"" *) input [3:0]gpio_io_i;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_O"" *) output [3:0]gpio_io_o;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_T"" *) output [3:0]gpio_io_t;
+
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire NLW_U0_ip2intc_irpt_UNCONNECTED;
+  wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
+  wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
+
+  (* C_ALL_INPUTS = ""0"" *) 
+  (* C_ALL_INPUTS_2 = ""0"" *) 
+  (* C_ALL_OUTPUTS = ""0"" *) 
+  (* C_ALL_OUTPUTS_2 = ""0"" *) 
+  (* C_DOUT_DEFAULT = ""0"" *) 
+  (* C_DOUT_DEFAULT_2 = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_GPIO2_WIDTH = ""32"" *) 
+  (* C_GPIO_WIDTH = ""4"" *) 
+  (* C_INTERRUPT_PRESENT = ""0"" *) 
+  (* C_IS_DUAL = ""0"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_TRI_DEFAULT = ""-1"" *) 
+  (* C_TRI_DEFAULT_2 = ""-1"" *) 
+  (* downgradeipidentifiedwarnings = ""yes"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
+       (.gpio2_io_i({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
+        .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
+   (SR,
+    \\Not_Dual.gpio_Data_Out_reg[0] ,
+    \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_aresetn,
+    s_axi_rready,
+    s_axi_bready,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    Q,
+    gpio_io_t,
+    s_axi_wdata,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output SR;
+  output \\Not_Dual.gpio_Data_Out_reg[0] ;
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [2:0]s_axi_araddr;
+  input [2:0]s_axi_awaddr;
+  input s_axi_aresetn;
+  input s_axi_rready;
+  input s_axi_bready;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input [3:0]Q;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire \\Not_Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [3:0]Q;
+  wire SR;
+  wire [0:6]bus2ip_addr;
+  wire \\bus2ip_addr_i[2]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[3]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_2_n_0 ;
+  wire bus2ip_rnw_i06_out;
+  wire clear;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_write;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire [1:0]p_0_out;
+  wire p_1_in;
+  wire [3:0]plusOp;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [3:0]s_axi_rdata;
+  wire \\s_axi_rdata_i[3]_i_1_n_0 ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire state1__2;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(clear));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(clear));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
+       (.D(D),
+        .E(E),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ),
+        .\\Not_Dual.gpio_Data_In_reg[0] (Q),
+        .\\Not_Dual.gpio_OE_reg[0] (\\Not_Dual.gpio_OE_reg[0] ),
+        .Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
+        .bus2ip_rnw_i_reg(\\Not_Dual.gpio_Data_Out_reg[0] ),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .rst_reg(SR),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .start2_reg(start2));
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_awaddr[0]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_awaddr[1]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h000000EA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_wvalid),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(\\bus2ip_addr_i[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[8]_i_2 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_awaddr[2]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[8]_i_2_n_0 ));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[2]_i_1_n_0 ),
+        .Q(bus2ip_addr[6]),
+        .R(SR));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[3]_i_1_n_0 ),
+        .Q(bus2ip_addr[5]),
+        .R(SR));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[8]_i_2_n_0 ),
+        .Q(bus2ip_addr[0]),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT3 #(
+    .INIT(8\'h10)) 
+    bus2ip_rnw_i_i_1
+       (.I0(state[0]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(bus2ip_rnw_i06_out),
+        .Q(\\Not_Dual.gpio_Data_Out_reg[0] ),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h3FFA000A)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state1__2),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(is_read),
+        .O(is_read_i_1_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0040FFFF00400000)) 
+    is_write_i_1
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_wvalid),
+        .I3(state[1]),
+        .I4(is_write),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hF88800000000FFFF)) 
+    is_write_i_2
+       (.I0(s_axi_rvalid),
+        .I1(s_axi_rready),
+        .I2(s_axi_bvalid),
+        .I3(s_axi_bready),
+        .I4(state[0]),
+        .I5(state[1]),
+        .O(is_write));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(SR));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    rst_i_1
+       (.I0(s_axi_aresetn),
+        .O(p_1_in));
+  FDRE rst_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(SR),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_wready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(SR));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[3]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(\\s_axi_rdata_i[3]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [0]),
+        .Q(s_axi_rdata[0]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [1]),
+        .Q(s_axi_rdata[1]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [2]),
+        .Q(s_axi_rdata[2]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [3]),
+        .Q(s_axi_rdata[3]),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_arready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h000000F8)) 
+    start2_i_1
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_arvalid),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h77FC44FC)) 
+    \\state[0]_i_1 
+       (.I0(state1__2),
+        .I1(state[0]),
+        .I2(s_axi_arvalid),
+        .I3(state[1]),
+        .I4(s_axi_wready),
+        .O(p_0_out[0]));
+  LUT5 #(
+    .INIT(32\'h5FFC50FC)) 
+    \\state[1]_i_1 
+       (.I0(state1__2),
+        .I1(\\state[1]_i_3_n_0 ),
+        .I2(state[1]),
+        .I3(state[0]),
+        .I4(s_axi_arready),
+        .O(p_0_out[1]));
+  LUT4 #(
+    .INIT(16\'hF888)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(state1__2));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\state[1]_i_3 
+       (.I0(s_axi_wvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_arvalid),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[0]),
+        .Q(state[0]),
+        .R(SR));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[1]),
+        .Q(state[1]),
+        .R(SR));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Wed Feb 01 18:22:40 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    SDIO0_WP,
+    UART0_TX,
+    UART0_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    FCLK_CLK0,
+    FCLK_RESET0_N,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_I"" *) input I2C0_SDA_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_O"" *) output I2C0_SDA_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_T"" *) output I2C0_SDA_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_I"" *) input I2C0_SCL_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_O"" *) output I2C0_SCL_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_T"" *) output I2C0_SCL_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *) input SDIO0_WP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 TxD"" *) output UART0_TX;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 RxD"" *) input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *) output [1:0]USB0_PORT_INDCTL;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *) output USB0_VBUS_PWRSELECT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *) input USB0_VBUS_PWRFAULT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *) output M_AXI_GP0_ARVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *) output M_AXI_GP0_AWVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *) output M_AXI_GP0_BREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *) output M_AXI_GP0_RREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *) output M_AXI_GP0_WLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *) output M_AXI_GP0_WVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *) output [11:0]M_AXI_GP0_ARID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *) output [11:0]M_AXI_GP0_AWID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *) output [11:0]M_AXI_GP0_WID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *) output [1:0]M_AXI_GP0_ARBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *) output [1:0]M_AXI_GP0_ARLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *) output [2:0]M_AXI_GP0_ARSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *) output [1:0]M_AXI_GP0_AWBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *) output [1:0]M_AXI_GP0_AWLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *) output [2:0]M_AXI_GP0_AWSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *) output [2:0]M_AXI_GP0_ARPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *) output [2:0]M_AXI_GP0_AWPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *) output [31:0]M_AXI_GP0_ARADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *) output [31:0]M_AXI_GP0_AWADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *) output [31:0]M_AXI_GP0_WDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *) output [3:0]M_AXI_GP0_ARCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *) output [3:0]M_AXI_GP0_ARLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *) output [3:0]M_AXI_GP0_ARQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *) output [3:0]M_AXI_GP0_AWCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *) output [3:0]M_AXI_GP0_AWLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *) output [3:0]M_AXI_GP0_AWQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *) output [3:0]M_AXI_GP0_WSTRB;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *) input M_AXI_GP0_ACLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *) input M_AXI_GP0_ARREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *) input M_AXI_GP0_AWREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *) input M_AXI_GP0_BVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *) input M_AXI_GP0_RLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *) input M_AXI_GP0_RVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *) input M_AXI_GP0_WREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *) input [11:0]M_AXI_GP0_BID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *) input [11:0]M_AXI_GP0_RID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *) input [1:0]M_AXI_GP0_BRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *) input [1:0]M_AXI_GP0_RRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *) input [31:0]M_AXI_GP0_RDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *) output FCLK_CLK0;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *) output FCLK_RESET0_N;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *) inout [53:0]MIO;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *) inout DDR_CAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *) inout DDR_CKE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *) inout DDR_Clk_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *) inout DDR_Clk;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *) inout DDR_CS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *) inout DDR_DRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *) inout DDR_ODT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *) inout DDR_RAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *) inout DDR_WEB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *) inout [2:0]DDR_BankAddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *) inout [14:0]DDR_Addr;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *) inout DDR_VRN;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *) inout DDR_VRP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *) inout [3:0]DDR_DM;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *) inout [31:0]DDR_DQ;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *) inout [3:0]DDR_DQS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *) inout [3:0]DDR_DQS;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *) inout PS_SRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *) inout PS_CLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *) inout PS_PORB;
+
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire FCLK_CLK0;
+  wire FCLK_RESET0_N;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [2:0]M_AXI_GP0_ARSIZE;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [2:0]M_AXI_GP0_AWSIZE;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_WP;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+  wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+  wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+  wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+  wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+  wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO0_LED_UNCONNECTED;
+  wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO1_LED_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+  wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+  wire NLW_inst_TRACE_CTL_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+  wire NLW_inst_UART0_DTRN_UNCONNECTED;
+  wire NLW_inst_UART0_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_DTRN_UNCONNECTED;
+  wire NLW_inst_UART1_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_TX_UNCONNECTED;
+  wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+  wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+  wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+  wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+  wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+PULLUP pullup_MIO_0
+       (.O(MIO[0]));
+PULLUP pullup_MIO_9
+       (.O(MIO[9]));
+PULLUP pullup_MIO_10
+       (.O(MIO[10]));
+PULLUP pullup_MIO_11
+       (.O(MIO[11]));
+PULLUP pullup_MIO_12
+       (.O(MIO[12]));
+PULLUP pullup_MIO_13
+       (.O(MIO[13]));
+PULLUP pullup_MIO_14
+       (.O(MIO[14]));
+PULLUP pullup_MIO_15
+       (.O(MIO[15]));
+PULLUP pullup_MIO_46
+       (.O(MIO[46]));
+
+  (* C_DM_WIDTH = ""4"" *) 
+  (* C_DQS_WIDTH = ""4"" *) 
+  (* C_DQ_WIDTH = ""32"" *) 
+  (* C_EMIO_GPIO_WIDTH = ""64"" *) 
+  (* C_EN_EMIO_ENET0 = ""0"" *) 
+  (* C_EN_EMIO_ENET1 = ""0"" *) 
+  (* C_EN_EMIO_PJTAG = ""0"" *) 
+  (* C_EN_EMIO_TRACE = ""0"" *) 
+  (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+  (* C_FCLK_CLK1_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK2_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+  (* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+  (* C_INCLUDE_TRACE_BUFFER = ""0"" *) 
+  (* C_IRQ_F2P_MODE = ""DIRECT"" *) 
+  (* C_MIO_PRIMITIVE = ""54"" *) 
+  (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_NUM_F2P_INTR_INPUTS = ""1"" *) 
+  (* C_PACKAGE_NAME = ""clg400"" *) 
+  (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+  (* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+  (* C_S_AXI_GP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP3_ID_WIDTH = ""6"" *) 
+  (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) 
+  (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+  (* C_TRACE_INTERNAL_WIDTH = ""2"" *) 
+  (* C_TRACE_PIPELINE_WIDTH = ""8"" *) 
+  (* C_USE_AXI_NONSECURE = ""0"" *) 
+  (* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) 
+  (* C_USE_M_AXI_GP0 = ""1"" *) 
+  (* C_USE_M_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_ACP = ""0"" *) 
+  (* C_USE_S_AXI_GP0 = ""0"" *) 
+  (* C_USE_S_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP0 = ""0"" *) 
+  (* C_USE_S_AXI_HP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP2 = ""0"" *) 
+  (* C_USE_S_AXI_HP3 = ""0"" *) 
+  (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) 
+  (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+  (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
+       (.CAN0_PHY_RX(1\'b0),
+        .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+        .CAN1_PHY_RX(1\'b0),
+        .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+        .Core0_nFIQ(1\'b0),
+        .Core0_nIRQ(1\'b0),
+        .Core1_nFIQ(1\'b0),
+        .Core1_nIRQ(1\'b0),
+        .DDR_ARB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .DDR_Addr(DDR_Addr),
+        .DDR_BankAddr(DDR_BankAddr),
+        .DDR_CAS_n(DDR_CAS_n),
+        .DDR_CKE(DDR_CKE),
+        .DDR_CS_n(DDR_CS_n),
+        .DDR_Clk(DDR_Clk),
+        .DDR_Clk_n(DDR_Clk_n),
+        .DDR_DM(DDR_DM),
+        .DDR_DQ(DDR_DQ),
+        .DDR_DQS(DDR_DQS),
+        .DDR_DQS_n(DDR_DQS_n),
+        .DDR_DRSTB(DDR_DRSTB),
+        .DDR_ODT(DDR_ODT),
+        .DDR_RAS_n(DDR_RAS_n),
+        .DDR_VRN(DDR_VRN),
+        .DDR_VRP(DDR_VRP),
+        .DDR_WEB(DDR_WEB),
+        .DMA0_ACLK(1\'b0),
+        .DMA0_DAREADY(1\'b0),
+        .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+        .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+        .DMA0_DRLAST(1\'b0),
+        .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+        .DMA0_DRTYPE({1\'b0,1\'b0}),
+        .DMA0_DRVALID(1\'b0),
+        .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+        .DMA1_ACLK(1\'b0),
+        .DMA1_DAREADY(1\'b0),
+        .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+        .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+        .DMA1_DRLAST(1\'b0),
+        .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+        .DMA1_DRTYPE({1\'b0,1\'b0}),
+        .DMA1_DRVALID(1\'b0),
+        .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+        .DMA2_ACLK(1\'b0),
+        .DMA2_DAREADY(1\'b0),
+        .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+        .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+        .DMA2_DRLAST(1\'b0),
+        .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+        .DMA2_DRTYPE({1\'b0,1\'b0}),
+        .DMA2_DRVALID(1\'b0),
+        .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+        .DMA3_ACLK(1\'b0),
+        .DMA3_DAREADY(1\'b0),
+        .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+        .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+        .DMA3_DRLAST(1\'b0),
+        .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+        .DMA3_DRTYPE({1\'b0,1\'b0}),
+        .DMA3_DRVALID(1\'b0),
+        .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+        .ENET0_EXT_INTIN(1\'b0),
+        .ENET0_GMII_COL(1\'b0),
+        .ENET0_GMII_CRS(1\'b0),
+        .ENET0_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET0_GMII_RX_CLK(1\'b0),
+        .ENET0_GMII_RX_DV(1\'b0),
+        .ENET0_GMII_RX_ER(1\'b0),
+        .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET0_GMII_TX_CLK(1\'b0),
+        .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+        .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+        .ENET0_MDIO_I(1\'b0),
+        .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+        .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+        .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+        .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+        .ENET1_EXT_INTIN(1\'b0),
+        .ENET1_GMII_COL(1\'b0),
+        .ENET1_GMII_CRS(1\'b0),
+        .ENET1_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET1_GMII_RX_CLK(1\'b0),
+        .ENET1_GMII_RX_DV(1\'b0),
+        .ENET1_GMII_RX_ER(1\'b0),
+        .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET1_GMII_TX_CLK(1\'b0),
+        .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+        .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+        .ENET1_MDIO_I(1\'b0),
+        .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+        .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+        .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+        .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+        .EVENT_EVENTI(1\'b0),
+        .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+        .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+        .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+        .FCLK_CLK0(FCLK_CLK0),
+        .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+        .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+        .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+        .FCLK_CLKTRIG0_N(1\'b0),
+        .FCLK_CLKTRIG1_N(1\'b0),
+        .FCLK_CLKTRIG2_N(1\'b0),
+        .FCLK_CLKTRIG3_N(1\'b0),
+        .FCLK_RESET0_N(FCLK_RESET0_N),
+        .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+        .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+        .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+        .FPGA_IDLE_N(1\'b0),
+        .FTMD_TRACEIN_ATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_CLK(1\'b0),
+        .FTMD_TRACEIN_DATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_VALID(1\'b0),
+        .FTMT_F2P_DEBUG({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+        .FTMT_F2P_TRIG_0(1\'b0),
+        .FTMT_F2P_TRIG_1(1\'b0),
+        .FTMT_F2P_TRIG_2(1\'b0),
+        .FTMT_F2P_TRIG_3(1\'b0),
+        .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+        .FTMT_P2F_TRIGACK_0(1\'b0),
+        .FTMT_P2F_TRIGACK_1(1\'b0),
+        .FTMT_P2F_TRIGACK_2(1\'b0),
+        .FTMT_P2F_TRIGACK_3(1\'b0),
+        .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+        .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+        .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+        .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+        .GPIO_I({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
+        .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
+        .I2C0_SCL_I(I2C0_SCL_I),
+        .I2C0_SCL_O(I2C0_SCL_O),
+        .I2C0_SCL_T(I2C0_SCL_T),
+        .I2C0_SDA_I(I2C0_SDA_I),
+        .I2C0_SDA_O(I2C0_SDA_O),
+        .I2C0_SDA_T(I2C0_SDA_T),
+        .I2C1_SCL_I(1\'b0),
+        .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+        .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+        .I2C1_SDA_I(1\'b0),
+        .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+        .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+        .IRQ_F2P(1\'b0),
+        .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+        .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+        .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+        .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+        .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+        .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+        .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+        .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+        .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+        .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+        .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+        .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+        .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+        .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+        .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+        .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+        .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+        .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+        .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+        .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+        .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+        .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+        .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+        .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+        .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+        .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+        .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+        .MIO(MIO),
+        .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+        .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+        .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+        .M_AXI_GP1_ACLK(1\'b0),
+        .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+        .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARREADY(1\'b0),
+        .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+        .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWREADY(1\'b0),
+        .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+        .M_AXI_GP1_BID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+        .M_AXI_GP1_BRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_BVALID(1\'b0),
+        .M_AXI_GP1_RDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RLAST(1\'b0),
+        .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+        .M_AXI_GP1_RRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_RVALID(1\'b0),
+        .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+        .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+        .M_AXI_GP1_WREADY(1\'b0),
+        .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+        .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+        .PJTAG_TCK(1\'b0),
+        .PJTAG_TDI(1\'b0),
+        .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+        .PJTAG_TMS(1\'b0),
+        .PS_CLK(PS_CLK),
+        .PS_PORB(PS_PORB),
+        .PS_SRSTB(PS_SRSTB),
+        .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+        .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO0_CDN(1\'b0),
+        .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+        .SDIO0_CLK_FB(1\'b0),
+        .SDIO0_CMD_I(1\'b0),
+        .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+        .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+        .SDIO0_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+        .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+        .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+        .SDIO0_WP(SDIO0_WP),
+        .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+        .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO1_CDN(1\'b0),
+        .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+        .SDIO1_CLK_FB(1\'b0),
+        .SDIO1_CMD_I(1\'b0),
+        .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+        .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+        .SDIO1_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+        .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+        .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+        .SDIO1_WP(1\'b0),
+        .SPI0_MISO_I(1\'b0),
+        .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+        .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+        .SPI0_MOSI_I(1\'b0),
+        .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+        .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+        .SPI0_SCLK_I(1\'b0),
+        .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+        .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+        .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+        .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+        .SPI0_SS_I(1\'b0),
+        .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+        .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+        .SPI1_MISO_I(1\'b0),
+        .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+        .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+        .SPI1_MOSI_I(1\'b0),
+        .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+        .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+        .SPI1_SCLK_I(1\'b0),
+        .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+        .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+        .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+        .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+        .SPI1_SS_I(1\'b0),
+        .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+        .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+        .SRAM_INTIN(1\'b0),
+        .S_AXI_ACP_ACLK(1\'b0),
+        .S_AXI_ACP_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+        .S_AXI_ACP_ARID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+        .S_AXI_ACP_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARVALID(1\'b0),
+        .S_AXI_ACP_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+        .S_AXI_ACP_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWVALID(1\'b0),
+        .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_BREADY(1\'b0),
+        .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+        .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+        .S_AXI_ACP_RREADY(1\'b0),
+        .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+        .S_AXI_ACP_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WLAST(1\'b0),
+        .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+        .S_AXI_ACP_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WVALID(1\'b0),
+        .S_AXI_GP0_ACLK(1\'b0),
+        .S_AXI_GP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+        .S_AXI_GP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+        .S_AXI_GP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARVALID(1\'b0),
+        .S_AXI_GP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+        .S_AXI_GP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWVALID(1\'b0),
+        .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_BREADY(1\'b0),
+        .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+        .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+        .S_AXI_GP0_RREADY(1\'b0),
+        .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+        .S_AXI_GP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WLAST(1\'b0),
+        .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+        .S_AXI_GP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WVALID(1\'b0),
+        .S_AXI_GP1_ACLK(1\'b0),
+        .S_AXI_GP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+        .S_AXI_GP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+        .S_AXI_GP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARVALID(1\'b0),
+        .S_AXI_GP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+        .S_AXI_GP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWVALID(1\'b0),
+        .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_BREADY(1\'b0),
+        .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+        .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+        .S_AXI_GP1_RREADY(1\'b0),
+        .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+        .S_AXI_GP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WLAST(1\'b0),
+        .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+        .S_AXI_GP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WVALID(1\'b0),
+        .S_AXI_HP0_ACLK(1\'b0),
+        .S_AXI_HP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+        .S_AXI_HP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+        .S_AXI_HP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARVALID(1\'b0),
+        .S_AXI_HP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+        .S_AXI_HP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWVALID(1\'b0),
+        .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_BREADY(1\'b0),
+        .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+        .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP0_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+        .S_AXI_HP0_RREADY(1\'b0),
+        .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+        .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WLAST(1\'b0),
+        .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+        .S_AXI_HP0_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WVALID(1\'b0),
+        .S_AXI_HP1_ACLK(1\'b0),
+        .S_AXI_HP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+        .S_AXI_HP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+        .S_AXI_HP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARVALID(1\'b0),
+        .S_AXI_HP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+        .S_AXI_HP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWVALID(1\'b0),
+        .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_BREADY(1\'b0),
+        .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+        .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP1_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+        .S_AXI_HP1_RREADY(1\'b0),
+        .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+        .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WLAST(1\'b0),
+        .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+        .S_AXI_HP1_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WVALID(1\'b0),
+        .S_AXI_HP2_ACLK(1\'b0),
+        .S_AXI_HP2_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+        .S_AXI_HP2_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+        .S_AXI_HP2_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARVALID(1\'b0),
+        .S_AXI_HP2_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+        .S_AXI_HP2_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWVALID(1\'b0),
+        .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_BREADY(1\'b0),
+        .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+        .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP2_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+        .S_AXI_HP2_RREADY(1\'b0),
+        .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+        .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WLAST(1\'b0),
+        .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+        .S_AXI_HP2_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WVALID(1\'b0),
+        .S_AXI_HP3_ACLK(1\'b0),
+        .S_AXI_HP3_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+        .S_AXI_HP3_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+        .S_AXI_HP3_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARVALID(1\'b0),
+        .S_AXI_HP3_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+        .S_AXI_HP3_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWVALID(1\'b0),
+        .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_BREADY(1\'b0),
+        .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+        .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP3_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+        .S_AXI_HP3_RREADY(1\'b0),
+        .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+        .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WLAST(1\'b0),
+        .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
+        .S_AXI_HP3_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WVALID(1\'b0),
+        .TRACE_CLK(1\'b0),
+        .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+        .TRACE_CTL'b'(NLW_inst_TRACE_CTL_UNCONNECTED),
+        .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+        .TTC0_CLK0_IN(1\'b0),
+        .TTC0_CLK1_IN(1\'b0),
+        .TTC0_CLK2_IN(1\'b0),
+        .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+        .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+        .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+        .TTC1_CLK0_IN(1\'b0),
+        .TTC1_CLK1_IN(1\'b0),
+        .TTC1_CLK2_IN(1\'b0),
+        .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+        .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+        .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+        .UART0_CTSN(1\'b0),
+        .UART0_DCDN(1\'b0),
+        .UART0_DSRN(1\'b0),
+        .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
+        .UART0_RIN(1\'b0),
+        .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
+        .UART0_RX(UART0_RX),
+        .UART0_TX(UART0_TX),
+        .UART1_CTSN(1\'b0),
+        .UART1_DCDN(1\'b0),
+        .UART1_DSRN(1\'b0),
+        .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+        .UART1_RIN(1\'b0),
+        .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+        .UART1_RX(1\'b1),
+        .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+        .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+        .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+        .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+        .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+        .USB1_VBUS_PWRFAULT(1\'b0),
+        .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+        .WDT_CLK_IN(1\'b0),
+        .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = ""4"" *) (* C_DQS_WIDTH = ""4"" *) (* C_DQ_WIDTH = ""32"" *) 
+(* C_EMIO_GPIO_WIDTH = ""64"" *) (* C_EN_EMIO_ENET0 = ""0"" *) (* C_EN_EMIO_ENET1 = ""0"" *) 
+(* C_EN_EMIO_PJTAG = ""0"" *) (* C_EN_EMIO_TRACE = ""0"" *) (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+(* C_FCLK_CLK1_BUF = ""FALSE"" *) (* C_FCLK_CLK2_BUF = ""FALSE"" *) (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+(* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+(* C_INCLUDE_TRACE_BUFFER = ""0"" *) (* C_IRQ_F2P_MODE = ""DIRECT"" *) (* C_MIO_PRIMITIVE = ""54"" *) 
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+(* C_NUM_F2P_INTR_INPUTS = ""1"" *) (* C_PACKAGE_NAME = ""clg400"" *) (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+(* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+(* C_S_AXI_GP0_ID_WIDTH = ""6"" *) (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP0_ID_WIDTH = ""6"" *) (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+(* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP3_ID_WIDTH = ""6"" *) (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+(* C_TRACE_INTERNAL_WIDTH = ""2"" *) (* C_TRACE_PIPELINE_WIDTH = ""8"" *) (* C_USE_AXI_NONSECURE = ""0"" *) 
+(* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) (* C_USE_M_AXI_GP0 = ""1"" *) (* C_USE_M_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_ACP = ""0"" *) (* C_USE_S_AXI_GP0 = ""0"" *) (* C_USE_S_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_HP0 = ""0"" *) (* C_USE_S_AXI_HP1 = ""0"" *) (* C_USE_S_AXI_HP2 = ""0"" *) 
+(* C_USE_S_AXI_HP3 = ""0"" *) (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+(* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
+   (CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TDI,
+    PJTAG_TDO,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    TRACE_CLK_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_PORT_INDCTL,
+    USB1_VBUS_PWRSELECT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARESETN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARESETN,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARESETN,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARESETN,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_ARESETN,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARESETN,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARESETN,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARESETN,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARESETN,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_RSTN,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_RSTN,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_RSTN,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_RSTN,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA3_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DRTYPE,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG_0,
+    FTMT_F2P_TRIGACK_0,
+    FTMT_F2P_TRIG_1,
+    FTMT_F2P_TRIGACK_1,
+    FTMT_F2P_TRIG_2,
+    FTMT_F2P_TRIGACK_2,
+    FTMT_F2P_TRIG_3,
+    FTMT_F2P_TRIGACK_3,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK_0,
+    FTMT_P2F_TRIG_0,
+    FTMT_P2F_TRIGACK_1,
+    FTMT_P2F_TRIG_1,
+    FTMT_P2F_TRIGACK_2,
+    FTMT_P2F_TRIG_2,
+    FTMT_P2F_TRIGACK_3,
+    FTMT_P2F_TRIG_3,
+    FTMT_P2F_DEBUG,
+    FPGA_IDLE_N,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    DDR_ARB,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0]ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input ENET0_EXT_INTIN;
+  input [7:0]ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0]ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input ENET1_EXT_INTIN;
+  input [7:0]ENET1_GMII_RXD;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TDI;
+  output PJTAG_TDO;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0]SDIO0_DATA_I;
+  output [3:0]SDIO0_DATA_O;
+  output [3:0]SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0]SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0]SDIO1_DATA_I;
+  output [3:0]SDIO1_DATA_O;
+  output [3:0]SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0]SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [1:0]TRACE_DATA;
+  output TRACE_CLK_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output [1:0]USB1_PORT_INDCTL;
+  output USB1_VBUS_PWRSELECT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARESETN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARESETN;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [11:0]M_AXI_GP1_ARID;
+  output [11:0]M_AXI_GP1_AWID;
+  output [11:0]M_AXI_GP1_WID;
+  output [1:0]M_AXI_GP1_ARBURST;
+  output [1:0]M_AXI_GP1_ARLOCK;
+  output [2:0]M_AXI_GP1_ARSIZE;
+  output [1:0]M_AXI_GP1_AWBURST;
+  output [1:0]M_AXI_GP1_AWLOCK;
+  output [2:0]M_AXI_GP1_AWSIZE;
+  output [2:0]M_AXI_GP1_ARPROT;
+  output [2:0]M_AXI_GP1_AWPROT;
+  output [31:0]M_AXI_GP1_ARADDR;
+  output [31:0]M_AXI_GP1_AWADDR;
+  output [31:0]M_AXI_GP1_WDATA;
+  output [3:0]M_AXI_GP1_ARCACHE;
+  output [3:0]M_AXI_GP1_ARLEN;
+  output [3:0]M_AXI_GP1_ARQOS;
+  output [3:0]M_AXI_GP1_AWCACHE;
+  output [3:0]M_AXI_GP1_AWLEN;
+  output [3:0]M_AXI_GP1_AWQOS;
+  output [3:0]M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [11:0]M_AXI_GP1_BID;
+  input [11:0]M_AXI_GP1_RID;
+  input [1:0]M_AXI_GP1_BRESP;
+  input [1:0]M_AXI_GP1_RRESP;
+  input [31:0]M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARESETN;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0]S_AXI_GP0_BRESP;
+  output [1:0]S_AXI_GP0_RRESP;
+  output [31:0]S_AXI_GP0_RDATA;
+  output [5:0]S_AXI_GP0_BID;
+  output [5:0]S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0]S_AXI_GP0_ARBURST;
+  input [1:0]S_AXI_GP0_ARLOCK;
+  input [2:0]S_AXI_GP0_ARSIZE;
+  input [1:0]S_AXI_GP0_AWBURST;
+  input [1:0]S_AXI_GP0_AWLOCK;
+  input [2:0]S_AXI_GP0_AWSIZE;
+  input [2:0]S_AXI_GP0_ARPROT;
+  input [2:0]S_AXI_GP0_AWPROT;
+  input [31:0]S_AXI_GP0_ARADDR;
+  input [31:0]S_AXI_GP0_AWADDR;
+  input [31:0]S_AXI_GP0_WDATA;
+  input [3:0]S_AXI_GP0_ARCACHE;
+  input [3:0]S_AXI_GP0_ARLEN;
+  input [3:0]S_AXI_GP0_ARQOS;
+  input [3:0]S_AXI_GP0_AWCACHE;
+  input [3:0]S_AXI_GP0_AWLEN;
+  input [3:0]S_AXI_GP0_AWQOS;
+  input [3:0]S_AXI_GP0_WSTRB;
+  input [5:0]S_AXI_GP0_ARID;
+  input [5:0]S_AXI_GP0_AWID;
+  input [5:0]S_AXI_GP0_WID;
+  output S_AXI_GP1_ARESETN;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0]S_AXI_GP1_BRESP;
+  output [1:0]S_AXI_GP1_RRESP;
+  output [31:0]S_AXI_GP1_RDATA;
+  output [5:0]S_AXI_GP1_BID;
+  output [5:0]S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0]S_AXI_GP1_ARBURST;
+  input [1:0]S_AXI_GP1_ARLOCK;
+  input [2:0]S_AXI_GP1_ARSIZE;
+  input [1:0]S_AXI_GP1_AWBURST;
+  input [1:0]S_AXI_GP1_AWLOCK;
+  input [2:0]S_AXI_GP1_AWSIZE;
+  input [2:0]S_AXI_GP1_ARPROT;
+  input [2:0]S_AXI_GP1_AWPROT;
+  input [31:0]S_AXI_GP1_ARADDR;
+  input [31:0]S_AXI_GP1_AWADDR;
+  input [31:0]S_AXI_GP1_WDATA;
+  input [3:0]S_AXI_GP1_ARCACHE;
+  input [3:0]S_AXI_GP1_ARLEN;
+  input [3:0]S_AXI_GP1_ARQOS;
+  input [3:0]S_AXI_GP1_AWCACHE;
+  input [3:0]S_AXI_GP1_AWLEN;
+  input [3:0]S_AXI_GP1_AWQOS;
+  input [3:0]S_AXI_GP1_WSTRB;
+  input [5:0]S_AXI_GP1_ARID;
+  input [5:0]S_AXI_GP1_AWID;
+  input [5:0]S_AXI_GP1_WID;
+  output S_AXI_ACP_ARESETN;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0]S_AXI_ACP_BRESP;
+  output [1:0]S_AXI_ACP_RRESP;
+  output [2:0]S_AXI_ACP_BID;
+  output [2:0]S_AXI_ACP_RID;
+  output [63:0]S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0]S_AXI_ACP_ARID;
+  input [2:0]S_AXI_ACP_ARPROT;
+  input [2:0]S_AXI_ACP_AWID;
+  input [2:0]S_AXI_ACP_AWPROT;
+  input [2:0]S_AXI_ACP_WID;
+  input [31:0]S_AXI_ACP_ARADDR;
+  input [31:0]S_AXI_ACP_AWADDR;
+  input [3:0]S_AXI_ACP_ARCACHE;
+  input [3:0]S_AXI_ACP_ARLEN;
+  input [3:0]S_AXI_ACP_ARQOS;
+  input [3:0]S_AXI_ACP_AWCACHE;
+  input [3:0]S_AXI_ACP_AWLEN;
+  input [3:0]S_AXI_ACP_AWQOS;
+  input [1:0]S_AXI_ACP_ARBURST;
+  input [1:0]S_AXI_ACP_ARLOCK;
+  input [2:0]S_AXI_ACP_ARSIZE;
+  input [1:0]S_AXI_ACP_AWBURST;
+  input [1:0]S_AXI_ACP_AWLOCK;
+  input [2:0]S_AXI_ACP_AWSIZE;
+  input [4:0]S_AXI_ACP_ARUSER;
+  input [4:0]S_AXI_ACP_AWUSER;
+  input [63:0]S_AXI_ACP_WDATA;
+  input [7:0]S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARESETN;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0]S_AXI_HP0_BRESP;
+  output [1:0]S_AXI_HP0_RRESP;
+  output [5:0]S_AXI_HP0_BID;
+  output [5:0]S_AXI_HP0_RID;
+  output [63:0]S_AXI_HP0_RDATA;
+  output [7:0]S_AXI_HP0_RCOUNT;
+  output [7:0]S_AXI_HP0_WCOUNT;
+  output [2:0]S_AXI_HP0_RACOUNT;
+  output [5:0]S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0]S_AXI_HP0_ARBURST;
+  input [1:0]S_AXI_HP0_ARLOCK;
+  input [2:0]S_AXI_HP0_ARSIZE;
+  input [1:0]S_AXI_HP0_AWBURST;
+  input [1:0]S_AXI_HP0_AWLOCK;
+  input [2:0]S_AXI_HP0_AWSIZE;
+  input [2:0]S_AXI_HP0_ARPROT;
+  input [2:0]S_AXI_HP0_AWPROT;
+  input [31:0]S_AXI_HP0_ARADDR;
+  input [31:0]S_AXI_HP0_AWADDR;
+  input [3:0]S_AXI_HP0_ARCACHE;
+  input [3:0]S_AXI_HP0_ARLEN;
+  input [3:0]S_AXI_HP0_ARQOS;
+  input [3:0]S_AXI_HP0_AWCACHE;
+  input [3:0]S_AXI_HP0_AWLEN;
+  input [3:0]S_AXI_HP0_AWQOS;
+  input [5:0]S_AXI_HP0_ARID;
+  input [5:0]S_AXI_HP0_AWID;
+  input [5:0]S_AXI_HP0_WID;
+  input [63:0]S_AXI_HP0_WDATA;
+  input [7:0]S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARESETN;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0]S_AXI_HP1_BRESP;
+  output [1:0]S_AXI_HP1_RRESP;
+  output [5:0]S_AXI_HP1_BID;
+  output [5:0]S_AXI_HP1_RID;
+  output [63:0]S_AXI_HP1_RDATA;
+  output [7:0]S_AXI_HP1_RCOUNT;
+  output [7:0]S_AXI_HP1_WCOUNT;
+  output [2:0]S_AXI_HP1_RACOUNT;
+  output [5:0]S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0]S_AXI_HP1_ARBURST;
+  input [1:0]S_AXI_HP1_ARLOCK;
+  input [2:0]S_AXI_HP1_ARSIZE;
+  input [1:0]S_AXI_HP1_AWBURST;
+  input [1:0]S_AXI_HP1_AWLOCK;
+  input [2:0]S_AXI_HP1_AWSIZE;
+  input [2:0]S_AXI_HP1_ARPROT;
+  input [2:0]S_AXI_HP1_AWPROT;
+  input [31:0]S_AXI_HP1_ARADDR;
+  input [31:0]S_AXI_HP1_AWADDR;
+  input [3:0]S_AXI_HP1_ARCACHE;
+  input [3:0]S_AXI_HP1_ARLEN;
+  input [3:0]S_AXI_HP1_ARQOS;
+  input [3:0]S_AXI_HP1_AWCACHE;
+  input [3:0]S_AXI_HP1_AWLEN;
+  input [3:0]S_AXI_HP1_AWQOS;
+  input [5:0]S_AXI_HP1_ARID;
+  input [5:0]S_AXI_HP1_AWID;
+  input [5:0]S_AXI_HP1_WID;
+  input [63:0]S_AXI_HP1_WDATA;
+  input [7:0]S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARESETN;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0]S_AXI_HP2_BRESP;
+  output [1:0]S_AXI_HP2_RRESP;
+  output [5:0]S_AXI_HP2_BID;
+  output [5:0]S_AXI_HP2_RID;
+  output [63:0]S_AXI_HP2_RDATA;
+  output [7:0]S_AXI_HP2_RCOUNT;
+  output [7:0]S_AXI_HP2_WCOUNT;
+  output [2:0]S_AXI_HP2_RACOUNT;
+  output [5:0]S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0]S_AXI_HP2_ARBURST;
+  input [1:0]S_AXI_HP2_ARLOCK;
+  input [2:0]S_AXI_HP2_ARSIZE;
+  input [1:0]S_AXI_HP2_AWBURST;
+  input [1:0]S_AXI_HP2_AWLOCK;
+  input [2:0]S_AXI_HP2_AWSIZE;
+  input [2:0]S_AXI_HP2_ARPROT;
+  input [2:0]S_AXI_HP2_AWPROT;
+  input [31:0]S_AXI_HP2_ARADDR;
+  input [31:0]S_AXI_HP2_AWADDR;
+  input [3:0]S_AXI_HP2_ARCACHE;
+  input [3:0]S_AXI_HP2_ARLEN;
+  input [3:0]S_AXI_HP2_ARQOS;
+  input [3:0]S_AXI_HP2_AWCACHE;
+  input [3:0]S_AXI_HP2_AWLEN;
+  input [3:0]S_AXI_HP2_AWQOS;
+  input [5:0]S_AXI_HP2_ARID;
+  input [5:0]S_AXI_HP2_AWID;
+  input [5:0]S_AXI_HP2_WID;
+  input [63:0]S_AXI_HP2_WDATA;
+  input [7:0]S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARESETN;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0]S_AXI_HP3_BRESP;
+  output [1:0]S_AXI_HP3_RRESP;
+  output [5:0]S_AXI_HP3_BID;
+  output [5:0]S_AXI_HP3_RID;
+  output [63:0]S_AXI_HP3_RDATA;
+  output [7:0]S_AXI_HP3_RCOUNT;
+  output [7:0]S_AXI_HP3_WCOUNT;
+  output [2:0]S_AXI_HP3_RACOUNT;
+  output [5:0]S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0]S_AXI_HP3_ARBURST;
+  input [1:0]S_AXI_HP3_ARLOCK;
+  input [2:0]S_AXI_HP3_ARSIZE;
+  input [1:0]S_AXI_HP3_AWBURST;
+  input [1:0]S_AXI_HP3_AWLOCK;
+  input [2:0]S_AXI_HP3_AWSIZE;
+  input [2:0]S_AXI_HP3_ARPROT;
+  input [2:0]S_AXI_HP3_AWPROT;
+  input [31:0]S_AXI_HP3_ARADDR;
+  input [31:0]S_AXI_HP3_AWADDR;
+  input [3:0]S_AXI_HP3_ARCACHE;
+  input [3:0]S_AXI_HP3_ARLEN;
+  input [3:0]S_AXI_HP3_ARQOS;
+  input [3:0]S_AXI_HP3_AWCACHE;
+  input [3:0]S_AXI_HP3_AWLEN;
+  input [3:0]S_AXI_HP3_AWQOS;
+  input [5:0]S_AXI_HP3_ARID;
+  input [5:0]S_AXI_HP3_AWID;
+  input [5:0]S_AXI_HP3_WID;
+  input [63:0]S_AXI_HP3_WDATA;
+  input [7:0]S_AXI_HP3_WSTRB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+  input [0:0]IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output [1:0]DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  output DMA0_RSTN;
+  output [1:0]DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  output DMA1_RSTN;
+  output [1:0]DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  output DMA2_RSTN;
+  output [1:0]DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  output DMA3_RSTN;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input DMA3_DRVALID;
+  input [1:0]DMA0_DRTYPE;
+  input [1:0]DMA1_DRTYPE;
+  input [1:0]DMA2_DRTYPE;
+  input [1:0]DMA3_DRTYPE;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input [31:0]FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0]FTMD_TRACEIN_ATID;
+  input FTMT_F2P_TRIG_0;
+  output FTMT_F2P_TRIGACK_0;
+  input FTMT_F2P_TRIG_1;
+  output FTMT_F2P_TRIGACK_1;
+  input FTMT_F2P_TRIG_2;
+  output FTMT_F2P_TRIGACK_2;
+  input FTMT_F2P_TRIG_3;
+  output FTMT_F2P_TRIGACK_3;
+  input [31:0]FTMT_F2P_DEBUG;
+  input FTMT_P2F_TRIGACK_0;
+  output FTMT_P2F_TRIG_0;
+  input FTMT_P2F_TRIGACK_1;
+  output FTMT_P2F_TRIG_1;
+  input FTMT_P2F_TRIGACK_2;
+  output FTMT_P2F_TRIG_2;
+  input FTMT_P2F_TRIGACK_3;
+  output FTMT_P2F_TRIG_3;
+  output [31:0]FTMT_P2F_DEBUG;
+  input FPGA_IDLE_N;
+  output EVENT_EVENTO;
+  output [1:0]EVENT_STANDBYWFE;
+  output [1:0]EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  input [3:0]DDR_ARB;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+
+  wire \\<const0> ;
+  wire CAN0_PHY_RX;
+  wire CAN0_PHY_TX;
+  wire CAN1_PHY_RX;
+  wire CAN1_PHY_TX;
+  wire Core0_nFIQ;
+  wire Core0_nIRQ;
+  wire Core1_nFIQ;
+  wire Core1_nIRQ;
+  wire [3:0]DDR_ARB;
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire DMA0_ACLK;
+  wire DMA0_DAREADY;
+  wire [1:0]DMA0_DATYPE;
+  wire DMA0_DAVALID;
+  wire DMA0_DRLAST;
+  wire DMA0_DRREADY;
+  wire [1:0]DMA0_DRTYPE;
+  wire DMA0_DRVALID;
+  wire DMA0_RSTN;
+  wire DMA1_ACLK;
+  wire DMA1_DAREADY;
+  wire [1:0]DMA1_DATYPE;
+  wire DMA1_DAVALID;
+  wire DMA1_DRLAST;
+  wire DMA1_DRREADY;
+  wire [1:0]DMA1_DRTYPE;
+  wire DMA1_DRVALID;
+  wire DMA1_RSTN;
+  wire DMA2_ACLK;
+  wire DMA2_DAREADY;
+  wire [1:0]DMA2_DATYPE;
+  wire DMA2_DAVALID;
+  wire DMA2_DRLAST;
+  wire DMA2_DRREADY;
+  wire [1:0]DMA2_DRTYPE;
+  wire DMA2_DRVALID;
+  wire DMA2_RSTN;
+  wire DMA3_ACLK;
+  wire DMA3_DAREADY;
+  wire [1:0]DMA3_DATYPE;
+  wire DMA3_DAVALID;
+  wire DMA3_DRLAST;
+  wire DMA3_DRREADY;
+  wire [1:0]DMA3_DRTYPE;
+  wire DMA3_DRVALID;
+  wire DMA3_RSTN;
+  wire ENET0_EXT_INTIN;
+  wire ENET0_GMII_RX_CLK;
+  wire ENET0_GMII_TX_CLK;
+  wire ENET0_MDIO_I;
+  wire ENET0_MDIO_MDC;
+  wire ENET0_MDIO_O;
+  wire ENET0_MDIO_T;
+  wire ENET0_MDIO_T_n;
+  wire ENET0_PTP_DELAY_REQ_RX;
+  wire ENET0_PTP_DELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_REQ_RX;
+  wire ENET0_PTP_PDELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_RESP_RX;
+  wire ENET0_PTP_PDELAY_RESP_TX;
+  wire ENET0_PTP_SYNC_FRAME_RX;
+  wire ENET0_PTP_SYNC_FRAME_TX;
+  wire ENET0_SOF_RX;
+  wire ENET0_SOF_TX;
+  wire ENET1_EXT_INTIN;
+  wire ENET1_GMII_RX_CLK;
+  wire ENET1_GMII_TX_CLK;
+  wire ENET1_MDIO_I;
+  wire ENET1_MDIO_MDC;
+  wire ENET1_MDIO_O;
+  wire ENET1_MDIO_T;
+  wire ENET1_MDIO_T_n;
+  wire ENET1_PTP_DELAY_REQ_RX;
+  wire ENET1_PTP_DELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_REQ_RX;
+  wire ENET1_PTP_PDELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_RESP_RX;
+  wire ENET1_PTP_PDELAY_RESP_TX;
+  wire ENET1_PTP_SYNC_FRAME_RX;
+  wire ENET1_PTP_SYNC_FRAME_TX;
+  wire ENET1_SOF_RX;
+  wire ENET1_SOF_TX;
+  wire EVENT_EVENTI;
+  wire EVENT_EVENTO;
+  wire [1:0]EVENT_STANDBYWFE;
+  wire [1:0]EVENT_STANDBYWFI;
+  wire FCLK_CLK0;
+  wire FCLK_CLK1;
+  wire FCLK_CLK2;
+  wire FCLK_CLK3;
+  wire [0:0]FCLK_CLK_unbuffered;
+  wire FCLK_RESET0_N;
+  wire FCLK_RESET1_N;
+  wire FCLK_RESET2_N;
+  wire FCLK_RESET3_N;
+  wire FPGA_IDLE_N;
+  wire FTMD_TRACEIN_CLK;
+  wire [31:0]FTMT_F2P_DEBUG;
+  wire FTMT_F2P_TRIGACK_0;
+  wire FTMT_F2P_TRIGACK_1;
+  wire FTMT_F2P_TRIGACK_2;
+  wire FTMT_F2P_TRIGACK_3;
+  wire FTMT_F2P_TRIG_0;
+  wire FTMT_F2P_TRIG_1;
+  wire FTMT_F2P_TRIG_2;
+  wire FTMT_F2P_TRIG_3;
+  wire [31:0]FTMT_P2F_DEBUG;
+  wire FTMT_P2F_TRIGACK_0;
+  wire FTMT_P2F_TRIGACK_1;
+  wire FTMT_P2F_TRIGACK_2;
+  wire FTMT_P2F_TRIGACK_3;
+  wire FTMT_P2F_TRIG_0;
+  wire FTMT_P2F_TRIG_1;
+  wire FTMT_P2F_TRIG_2;
+  wire FTMT_P2F_TRIG_3;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SCL_T_n;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire I2C0_SDA_T_n;
+  wire I2C1_SCL_I;
+  wire I2C1_SCL_O;
+  wire I2C1_SCL_T;
+  wire I2C1_SCL_T_n;
+  wire I2C1_SDA_I;
+  wire I2C1_SDA_O;
+  wire I2C1_SDA_T;
+  wire I2C1_SDA_T_n;
+  wire [0:0]IRQ_F2P;
+  wire IRQ_P2F_CAN0;
+  wire IRQ_P2F_CAN1;
+  wire IRQ_P2F_CTI;
+  wire IRQ_P2F_DMAC0;
+  wire IRQ_P2F_DMAC1;
+  wire IRQ_P2F_DMAC2;
+  wire IRQ_P2F_DMAC3;
+  wire IRQ_P2F_DMAC4;
+  wire IRQ_P2F_DMAC5;
+  wire IRQ_P2F_DMAC6;
+  wire IRQ_P2F_DMAC7;
+  wire IRQ_P2F_DMAC_ABORT;
+  wire IRQ_P2F_ENET0;
+  wire IRQ_P2F_ENET1;
+  wire IRQ_P2F_ENET_WAKE0;
+  wire IRQ_P2F_ENET_WAKE1;
+  wire IRQ_P2F_GPIO;
+  wire IRQ_P2F_I2C0;
+  wire IRQ_P2F_I2C1;
+  wire IRQ_P2F_QSPI;
+  wire IRQ_P2F_SDIO0;
+  wire IRQ_P2F_SDIO1;
+  wire IRQ_P2F_SMC;
+  wire IRQ_P2F_SPI0;
+  wire IRQ_P2F_SPI1;
+  wire IRQ_P2F_UART0;
+  wire IRQ_P2F_UART1;
+  wire IRQ_P2F_USB0;
+  wire IRQ_P2F_USB1;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire M_AXI_GP0_ARESETN;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [1:0]\\^M_AXI_GP0_ARSIZE ;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [1:0]\\^M_AXI_GP0_AWSIZE ;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire M_AXI_GP1_ACLK;
+  wire [31:0]M_AXI_GP1_ARADDR;
+  wire [1:0]M_AXI_GP1_ARBURST;
+  wire [3:0]M_AXI_GP1_ARCACHE;
+  wire M_AXI_GP1_ARESETN;
+  wire [11:0]M_AXI_GP1_ARID;
+  wire [3:0]M_AXI_GP1_ARLEN;
+  wire [1:0]M_AXI_GP1_ARLOCK;
+  wire [2:0]M_AXI_GP1_ARPROT;
+  wire [3:0]M_AXI_GP1_ARQOS;
+  wire M_AXI_GP1_ARREADY;
+  wire [1:0]\\^M_AXI_GP1_ARSIZE ;
+  wire M_AXI_GP1_ARVALID;
+  wire [31:0]M_AXI_GP1_AWADDR;
+  wire [1:0]M_AXI_GP1_AWBURST;
+  wire [3:0]M_AXI_GP1_AWCACHE;
+  wire [11:0]M_AXI_GP1_AWID;
+  wire [3:0]M_AXI_GP1_AWLEN;
+  wire [1:0]M_AXI_GP1_AWLOCK;
+  wire [2:0]M_AXI_GP1_AWPROT;
+  wire [3:0]M_AXI_GP1_AWQOS;
+  wire M_AXI_GP1_AWREADY;
+  wire [1:0]\\^M_AXI_GP1_AWSIZE ;
+  wire M_AXI_GP1_AWVALID;
+  wire [11:0]M_AXI_GP1_BID;
+  wire M_AXI_GP1_BREADY;
+  wire [1:0]M_AXI_GP1_BRESP;
+  wire M_AXI_GP1_BVALID;
+  wire [31:0]M_AXI_GP1_RDATA;
+  wire [11:0]M_AXI_GP1_RID;
+  wire M_AXI_GP1_RLAST;
+  wire M_AXI_GP1_RREADY;
+  wire [1:0]M_AXI_GP1_RRESP;
+  wire M_AXI_GP1_RVALID;
+  wire [31:0]M_AXI_GP1_WDATA;
+  wire [11:0]M_AXI_GP1_WID;
+  wire M_AXI_GP1_WLAST;
+  wire M_AXI_GP1_WREADY;
+  wire [3:0]M_AXI_GP1_WSTRB;
+  wire M_AXI_GP1_WVALID;
+  wire PJTAG_TCK;
+  wire PJTAG_TDI;
+  wire PJTAG_TMS;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_BUSPOW;
+  wire [2:0]SDIO0_BUSVOLT;
+  wire SDIO0_CDN;
+  wire SDIO0_CLK;
+  wire SDIO0_CLK_FB;
+  wire SDIO0_CMD_I;
+  wire SDIO0_CMD_O;
+  wire SDIO0_CMD_T;
+  wire SDIO0_CMD_T_n;
+  wire [3:0]SDIO0_DATA_I;
+  wire [3:0]SDIO0_DATA_O;
+  wire [3:0]SDIO0_DATA_T;
+  wire [3:0]SDIO0_DATA_T_n;
+  wire SDIO0_LED;
+  wire SDIO0_WP;
+  wire SDIO1_BUSPOW;
+  wire [2:0]SDIO1_BUSVOLT;
+  wire SDIO1_CDN;
+  wire SDIO1_CLK;
+  wire SDIO1_CLK_FB;
+  wire SDIO1_CMD_I;
+  wire SDIO1_CMD_O;
+  wire SDIO1_CMD_T;
+  wire SDIO1_CMD_T_n;
+  wire [3:0]SDIO1_DATA_I;
+  wire [3:0]SDIO1_DATA_O;
+  wire [3:0]SDIO1_DATA_T;
+  wire [3:0]SDIO1_DATA_T_n;
+  wire SDIO1_LED;
+  wire SDIO1_WP;
+  wire SPI0_MISO_I;
+  wire SPI0_MISO_O;
+  wire SPI0_MISO_T;
+  wire SPI0_MISO_T_n;
+  wire SPI0_MOSI_I;
+  wire SPI0_MOSI_O;
+  wire SPI0_MOSI_T;
+  wire SPI0_MOSI_T_n;
+  wire SPI0_SCLK_I;
+  wire SPI0_SCLK_O;
+  wire SPI0_SCLK_T;
+  wire SPI0_SCLK_T_n;
+  wire SPI0_SS1_O;
+  wire SPI0_SS2_O;
+  wire SPI0_SS_I;
+  wire SPI0_SS_O;
+  wire SPI0_SS_T;
+  wire SPI0_SS_T_n;
+  wire SPI1_MISO_I;
+  wire SPI1_MISO_O;
+  wire SPI1_MISO_T;
+  wire SPI1_MISO_T_n;
+  wire SPI1_MOSI_I;
+  wire SPI1_MOSI_O;
+  wire SPI1_MOSI_T;
+  wire SPI1_MOSI_T_n;
+  wire SPI1_SCLK_I;
+  wire SPI1_SCLK_O;
+  wire SPI1_SCLK_T;
+  wire SPI1_SCLK_T_n;
+  wire SPI1_SS1_O;
+  wire SPI1_SS2_O;
+  wire SPI1_SS_I;
+  wire SPI1_SS_O;
+  wire SPI1_SS_T;
+  wire SPI1_SS_T_n;
+  wire SRAM_INTIN;
+  wire S_AXI_ACP_ACLK;
+  wire [31:0]S_AXI_ACP_ARADDR;
+  wire [1:0]S_AXI_ACP_ARBURST;
+  wire [3:0]S_AXI_ACP_ARCACHE;
+  wire S_AXI_ACP_ARESETN;
+  wire [2:0]S_AXI_ACP_ARID;
+  wire [3:0]S_AXI_ACP_ARLEN;
+  wire [1:0]S_AXI_ACP_ARLOCK;
+  wire [2:0]S_AXI_ACP_ARPROT;
+  wire [3:0]S_AXI_ACP_ARQOS;
+  wire S_AXI_ACP_ARREADY;
+  wire [2:0]S_AXI_ACP_ARSIZE;
+  wire [4:0]S_AXI_ACP_ARUSER;
+  wire S_AXI_ACP_ARVALID;
+  wire [31:0]S_AXI_ACP_AWADDR;
+  wire [1:0]S_AXI_ACP_AWBURST;
+  wire [3:0]S_AXI_ACP_AWCACHE;
+  wire [2:0]S_AXI_ACP_AWID;
+  wire [3:0]S_AXI_ACP_AWLEN;
+  wire [1:0]S_AXI_ACP_AWLOCK;
+  wire [2:0]S_AXI_ACP_AWPROT;
+  wire [3:0]S_AXI_ACP_AWQOS;
+  wire S_AXI_ACP_AWREADY;
+  wire [2:0]S_AXI_ACP_AWSIZE;
+  wire [4:0]S_AXI_ACP_AWUSER;
+  wire S_AXI_ACP_AWVALID;
+  wire [2:0]S_AXI_ACP_BID;
+  wire S_AXI_ACP_BREADY;
+  wire [1:0]S_AXI_ACP_BRESP;
+  wire S_AXI_ACP_BVALID;
+  wire [63:0]S_AXI_ACP_RDATA;
+  wire [2:0]S_AXI_ACP_RID;
+  wire S_AXI_ACP_RLAST;
+  wire S_AXI_ACP_RREADY;
+  wire [1:0]S_AXI_ACP_RRESP;
+  wire S_AXI_ACP_RVALID;
+  wire [63:0]S_AXI_ACP_WDATA;
+  wire [2:0]S_AXI_ACP_WID;
+  wire S_AXI_ACP_WLAST;
+  wire S_AXI_ACP_WREADY;
+  wire [7:0]S_AXI_ACP_WSTRB;
+  wire S_AXI_ACP_WVALID;
+  wire S_AXI_GP0_ACLK;
+  wire [31:0]S_AXI_GP0_ARADDR;
+  wire [1:0]S_AXI_GP0_ARBURST;
+  wire [3:0]S_AXI_GP0_ARCACHE;
+  wire S_AXI_GP0_ARESETN;
+  wire [5:0]S_AXI_GP0_ARID;
+  wire [3:0]S_AXI_GP0_ARLEN;
+  wire [1:0]S_AXI_GP0_ARLOCK;
+  wire [2:0]S_AXI_GP0_ARPROT;
+  wire [3:0]S_AXI_GP0_ARQOS;
+  wire S_AXI_GP0_ARREADY;
+  wire [2:0]S_AXI_GP0_ARSIZE;
+  wire S_AXI_GP0_ARVALID;
+  wire [31:0]S_AXI_GP0_AWADDR;
+  wire [1:0]S_AXI_GP0_AWBURST;
+  wire [3:0]S_AXI_GP0_AWCACHE;
+  wire [5:0]S_AXI_GP0_AWID;
+  wire [3:0]S_AXI_GP0_AWLEN;
+  wire [1:0]S_AXI_GP0_AWLOCK;
+  wire [2:0]S_AXI_GP0_AWPROT;
+  wire [3:0]S_AXI_GP0_AWQOS;
+  wire S_AXI_GP0_AWREADY;
+  wire [2:0]S_AXI_GP0_AWSIZE;
+  wire S_AXI_GP0_AWVALID;
+  wire [5:0]S_AXI_GP0_BID;
+  wire S_AXI_GP0_BREADY;
+  wire [1:0]S_AXI_GP0_BRESP;
+  wire S_AXI_GP0_BVALID;
+  wire [31:0]S_AXI_GP0_RDATA;
+  wire [5:0]S_AXI_GP0_RID;
+  wire S_AXI_GP0_RLAST;
+  wire S_AXI_GP0_RREADY;
+  wire [1:0]S_AXI_GP0_RRESP;
+  wire S_AXI_GP0_RVALID;
+  wire [31:0]S_AXI_GP0_WDATA;
+  wire [5:0]S_AXI_GP0_WID;
+  wire S_AXI_GP0_WLAST;
+  wire S_AXI_GP0_WREADY;
+  wire [3:0]S_AXI_GP0_WSTRB;
+  wire S_AXI_GP0_WVALID;
+  wire S_AXI_GP1_ACLK;
+  wire [31:0]S_AXI_GP1_ARADDR;
+  wire [1:0]S_AXI_GP1_ARBURST;
+  wire [3:0]S_AXI_GP1_ARCACHE;
+  wire S_AXI_GP1_ARESETN;
+  wire [5:0]S_AXI_GP1_ARID;
+  wire [3:0]S_AXI_GP1_ARLEN;
+  wire [1:0]S_AXI_GP1_ARLOCK;
+  wire [2:0]S_AXI_GP1_ARPROT;
+  wire [3:0]S_AXI_GP1_ARQOS;
+  wire S_AXI_GP1_ARREADY;
+  wire [2:0]S_AXI_GP1_ARSIZE;
+  wire S_AXI_GP1_ARVALID;
+  wire [31:0]S_AXI_GP1_AWADDR;
+  wire [1:0]S_AXI_GP1_AWBURST;
+  wire [3:0]S_AXI_GP1_AWCACHE;
+  wire [5:0]S_AXI_GP1_AWID;
+  wire [3:0]S_AXI_GP1_AWLEN;
+  wire [1:0]S_AXI_GP1_AWLOCK;
+  wire [2:0]S_AXI_GP1_AWPROT;
+  wire [3:0]S_AXI_GP1_AWQOS;
+  wire S_AXI_GP1_AWREADY;
+  wire [2:0]S_AXI_GP1_AWSIZE;
+  wire S_AXI_GP1_AWVALID;
+  wire [5:0]S_AXI_GP1_BID;
+  wire S_AXI_GP1_BREADY;
+  wire [1:0]S_AXI_GP1_BRESP;
+  wire S_AXI_GP1_BVALID;
+  wire [31:0]S_AXI_GP1_RDATA;
+  wire [5:0]S_AXI_GP1_RID;
+  wire S_AXI_GP1_RLAST;
+  wire S_AXI_GP1_RREADY;
+  wire [1:0]S_AXI_GP1_RRESP;
+  wire S_AXI_GP1_RVALID;
+  wire [31:0]S_AXI_GP1_WDATA;
+  wire [5:0]S_AXI_GP1_WID;
+  wire S_AXI_GP1_WLAST;
+  wire S_AXI_GP1_WREADY;
+  wire [3:0]S_AXI_GP1_WSTRB;
+  wire S_AXI_GP1_WVALID;
+  wire S_AXI_HP0_ACLK;
+  wire [31:0]S_AXI_HP0_ARADDR;
+  wire [1:0]S_AXI_HP0_ARBURST;
+  wire [3:0]S_AXI_HP0_ARCACHE;
+  wire S_AXI_HP0_ARESETN;
+  wire [5:0]S_AXI_HP0_ARID;
+  wire [3:0]S_AXI_HP0_ARLEN;
+  wire [1:0]S_AXI_HP0_ARLOCK;
+  wire [2:0]S_AXI_HP0_ARPROT;
+  wire [3:0]S_AXI_HP0_ARQOS;
+  wire S_AXI_HP0_ARREADY;
+  wire [2:0]S_AXI_HP0_ARSIZE;
+  wire S_AXI_HP0_ARVALID;
+  wire [31:0]S_AXI_HP0_AWADDR;
+  wire [1:0]S_AXI_HP0_AWBURST;
+  wire [3:0]S_AXI_HP0_AWCACHE;
+  wire [5:0]S_AXI_HP0_AWID;
+  wire [3:0]S_AXI_HP0_AWLEN;
+  wire [1:0]S_AXI_HP0_AWLOCK;
+  wire [2:0]S_AXI_HP0_AWPROT;
+  wire [3:0]S_AXI_HP0_AWQOS;
+  wire S_AXI_HP0_AWREADY;
+  wire [2:0]S_AXI_HP0_AWSIZE;
+  wire S_AXI_HP0_AWVALID;
+  wire [5:0]S_AXI_HP0_BID;
+  wire S_AXI_HP0_BREADY;
+  wire [1:0]S_AXI_HP0_BRESP;
+  wire S_AXI_HP0_BVALID;
+  wire [2:0]S_AXI_HP0_RACOUNT;
+  wire [7:0]S_AXI_HP0_RCOUNT;
+  wire [63:0]S_AXI_HP0_RDATA;
+  wire S_AXI_HP0_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP0_RID;
+  wire S_AXI_HP0_RLAST;
+  wire S_AXI_HP0_RREADY;
+  wire [1:0]S_AXI_HP0_RRESP;
+  wire S_AXI_HP0_RVALID;
+  wire [5:0]S_AXI_HP0_WACOUNT;
+  wire [7:0]S_AXI_HP0_WCOUNT;
+  wire [63:0]S_AXI_HP0_WDATA;
+  wire [5:0]S_AXI_HP0_WID;
+  wire S_AXI_HP0_WLAST;
+  wire S_AXI_HP0_WREADY;
+  wire S_AXI_HP0_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP0_WSTRB;
+  wire S_AXI_HP0_WVALID;
+  wire S_AXI_HP1_ACLK;
+  wire [31:0]S_AXI_HP1_ARADDR;
+  wire [1:0]S_AXI_HP1_ARBURST;
+  wire [3:0]S_AXI_HP1_ARCACHE;
+  wire S_AXI_HP1_ARESETN;
+  wire [5:0]S_AXI_HP1_ARID;
+  wire [3:0]S_AXI_HP1_ARLEN;
+  wire [1:0]S_AXI_HP1_ARLOCK;
+  wire [2:0]S_AXI_HP1_ARPROT;
+  wire [3:0]S_AXI_HP1_ARQOS;
+  wire S_AXI_HP1_ARREADY;
+  wire [2:0]S_AXI_HP1_ARSIZE;
+  wire S_AXI_HP1_ARVALID;
+  wire [31:0]S_AXI_HP1_AWADDR;
+  wire [1:0]S_AXI_HP1_AWBURST;
+  wire [3:0]S_AXI_HP1_AWCACHE;
+  wire [5:0]S_AXI_HP1_AWID;
+  wire [3:0]S_AXI_HP1_AWLEN;
+  wire [1:0]S_AXI_HP1_AWLOCK;
+  wire [2:0]S_AXI_HP1_AWPROT;
+  wire [3:0]S_AXI_HP1_AWQOS;
+  wire S_AXI_HP1_AWREADY;
+  wire [2:0]S_AXI_HP1_AWSIZE;
+  wire S_AXI_HP1_AWVALID;
+  wire [5:0]S_AXI_HP1_BID;
+  wire S_AXI_HP1_BREADY;
+  wire [1:0]S_AXI_HP1_BRESP;
+  wire S_AXI_HP1_BVALID;
+  wire [2:0]S_AXI_HP1_RACOUNT;
+  wire [7:0]S_AXI_HP1_RCOUNT;
+  wire [63:0]S_AXI_HP1_RDATA;
+  wire S_AXI_HP1_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP1_RID;
+  wire S_AXI_HP1_RLAST;
+  wire S_AXI_HP1_RREADY;
+  wire [1:0]S_AXI_HP1_RRESP;
+  wire S_AXI_HP1_RVALID;
+  wire [5:0]S_AXI_HP1_WACOUNT;
+  wire [7:0]S_AXI_HP1_WCOUNT;
+  wire [63:0]S_AXI_HP1_WDATA;
+  wire [5:0]S_AXI_HP1_WID;
+  wire S_AXI_HP1_WLAST;
+  wire S_AXI_HP1_WREADY;
+  wire S_AXI_HP1_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP1_WSTRB;
+  wire S_AXI_HP1_WVALID;
+  wire S_AXI_HP2_ACLK;
+  wire [31:0]S_AXI_HP2_ARADDR;
+  wire [1:0]S_AXI_HP2_ARBURST;
+  wire [3:0]S_AXI_HP2_ARCACHE;
+  wire S_AXI_HP2_ARESETN;
+  wire [5:0]S_AXI_HP2_ARID;
+  wire [3:0]S_AXI_HP2_ARLEN;
+  wire [1:0]S_AXI_HP2_ARLOCK;
+  wire [2:0]S_AXI_HP2_ARPROT;
+  wire [3:0]S_AXI_HP2_ARQOS;
+  wire S_AXI_HP2_ARREADY;
+  wire [2:0]S_AXI_HP2_ARSIZE;
+  wire S_AXI_HP2_ARVALID;
+  wire [31:0]S_AXI_HP2_AWADDR;
+  wire [1:0]S_AXI_HP2_AWBURST;
+  wire [3:0]S_AXI_HP2_AWCACHE;
+  wire [5:0]S_AXI_HP2_AWID;
+  wire [3:0]S_AXI_HP2_AWLEN;
+  wire [1:0]S_AXI_HP2_AWLOCK;
+  wire [2:0]S_AXI_HP2_AWPROT;
+  wire [3:0]S_AXI_HP2_AWQOS;
+  wire S_AXI_HP2_AWREADY;
+  wire [2:0]S_AXI_HP2_AWSIZE;
+  wire S_AXI_HP2_AWVALID;
+  wire [5:0]S_AXI_HP2_BID;
+  wire S_AXI_HP2_BREADY;
+  wire [1:0]S_AXI_HP2_BRESP;
+  wire S_AXI_HP2_BVALID;
+  wire [2:0]S_AXI_HP2_RACOUNT;
+  wire [7:0]S_AXI_HP2_RCOUNT;
+  wire [63:0]S_AXI_HP2_RDATA;
+  wire S_AXI_HP2_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP2_RID;
+  wire S_AXI_HP2_RLAST;
+  wire S_AXI_HP2_RREADY;
+  wire [1:0]S_AXI_HP2_RRESP;
+  wire S_AXI_HP2_RVALID;
+  wire [5:0]S_AXI_HP2_WACOUNT;
+  wire [7:0]S_AXI_HP2_WCOUNT;
+  wire [63:0]S_AXI_HP2_WDATA;
+  wire [5:0]S_AXI_HP2_WID;
+  wire S_AXI_HP2_WLAST;
+  wire S_AXI_HP2_WREADY;
+  wire S_AXI_HP2_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP2_WSTRB;
+  wire S_AXI_HP2_WVALID;
+  wire S_AXI_HP3_ACLK;
+  wire [31:0]S_AXI_HP3_ARADDR;
+  wire [1:0]S_AXI_HP3_ARBURST;
+  wire [3:0]S_AXI_HP3_ARCACHE;
+  wire S_AXI_HP3_ARESETN;
+  wire [5:0]S_AXI_HP3_ARID;
+  wire [3:0]S_AXI_HP3_ARLEN;
+  wire [1:0]S_AXI_HP3_ARLOCK;
+  wire [2:0]S_AXI_HP3_ARPROT;
+  wire [3:0]S_AXI_HP3_ARQOS;
+  wire S_AXI_HP3_ARREADY;
+  wire [2:0]S_AXI_HP3_ARSIZE;
+  wire S_AXI_HP3_ARVALID;
+  wire [31:0]S_AXI_HP3_AWADDR;
+  wire [1:0]S_AXI_HP3_AWBURST;
+  wire [3:0]S_AXI_HP3_AWCACHE;
+  wire [5:0]S_AXI_HP3_AWID;
+  wire [3:0]S_AXI_HP3_AWLEN;
+  wire [1:0]S_AXI_HP3_AWLOCK;
+  wire [2:0]S_AXI_HP3_AWPROT;
+  wire [3:0]S_AXI_HP3_AWQOS;
+  wire S_AXI_HP3_AWREADY;
+  wire [2:0]S_AXI_HP3_AWSIZE;
+  wire S_AXI_HP3_AWVALID;
+  wire [5:0]S_AXI_HP3_BID;
+  wire S_AXI_HP3_BREADY;
+  wire [1:0]S_AXI_HP3_BRESP;
+  wire S_AXI_HP3_BVALID;
+  wire [2:0]S_AXI_HP3_RACOUNT;
+  wire [7:0]S_AXI_HP3_RCOUNT;
+  wire [63:0]S_AXI_HP3_RDATA;
+  wire S_AXI_HP3_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP3_RID;
+  wire S_AXI_HP3_RLAST;
+  wire S_AXI_HP3_RREADY;
+  wire [1:0]S_AXI_HP3_RRESP;
+  wire S_AXI_HP3_RVALID;
+  wire [5:0]S_AXI_HP3_WACOUNT;
+  wire [7:0]S_AXI_HP3_WCOUNT;
+  wire [63:0]S_AXI_HP3_WDATA;
+  wire [5:0]S_AXI_HP3_WID;
+  wire S_AXI_HP3_WLAST;
+  wire S_AXI_HP3_WREADY;
+  wire S_AXI_HP3_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP3_WSTRB;
+  wire S_AXI_HP3_WVALID;
+  wire TRACE_CLK;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[7] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[7] ;
+  wire TTC0_CLK0_IN;
+  wire TTC0_CLK1_IN;
+  wire TTC0_CLK2_IN;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire TTC1_CLK0_IN;
+  wire TTC1_CLK1_IN;
+  wire TTC1_CLK2_IN;
+  wire TTC1_WAVE0_OUT;
+  wire TTC1_WAVE1_OUT;
+  wire TTC1_WAVE2_OUT;
+  wire UART0_CTSN;
+  wire UART0_DCDN;
+  wire UART0_DSRN;
+  wire UART0_DTRN;
+  wire UART0_RIN;
+  wire UART0_RTSN;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire UART1_CTSN;
+  wire UART1_DCDN;
+  wire UART1_DSRN;
+  wire UART1_DTRN;
+  wire UART1_RIN;
+  wire UART1_RTSN;
+  wire UART1_RX;
+  wire UART1_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire [1:0]USB1_PORT_INDCTL;
+  wire USB1_VBUS_PWRFAULT;
+  wire USB1_VBUS_PWRSELECT;
+  wire WDT_CLK_IN;
+  wire WDT_RST_OUT;
+  wire [14:0]buffered_DDR_Addr;
+  wire [2:0]buffered_DDR_BankAddr;
+  wire buffered_DDR_CAS_n;
+  wire buffered_DDR_CKE;
+  wire buffered_DDR_CS_n;
+  wire buffered_DDR_Clk;
+  wire buffered_DDR_Clk_n;
+  wire [3:0]buffered_DDR_DM;
+  wire [31:0]buffered_DDR_DQ;
+  wire [3:0]buffered_DDR_DQS;
+  wire [3:0]buffered_DDR_DQS_n;
+  wire buffered_DDR_DRSTB;
+  wire buffered_DDR_ODT;
+  wire buffered_DDR_RAS_n;
+  wire buffered_DDR_VRN;
+  wire buffered_DDR_VRP'b';
+  wire buffered_DDR_WEB;
+  wire [53:0]buffered_MIO;
+  wire buffered_PS_CLK;
+  wire buffered_PS_PORB;
+  wire buffered_PS_SRSTB;
+  wire [63:0]gpio_out_t_n;
+  wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
+  wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+
+  assign ENET0_GMII_TXD[7] = \\<const0> ;
+  assign ENET0_GMII_TXD[6] = \\<const0> ;
+  assign ENET0_GMII_TXD[5] = \\<const0> ;
+  assign ENET0_GMII_TXD[4] = \\<const0> ;
+  assign ENET0_GMII_TXD[3] = \\<const0> ;
+  assign ENET0_GMII_TXD[2] = \\<const0> ;
+  assign ENET0_GMII_TXD[1] = \\<const0> ;
+  assign ENET0_GMII_TXD[0] = \\<const0> ;
+  assign ENET0_GMII_TX_EN = \\<const0> ;
+  assign ENET0_GMII_TX_ER = \\<const0> ;
+  assign ENET1_GMII_TXD[7] = \\<const0> ;
+  assign ENET1_GMII_TXD[6] = \\<const0> ;
+  assign ENET1_GMII_TXD[5] = \\<const0> ;
+  assign ENET1_GMII_TXD[4] = \\<const0> ;
+  assign ENET1_GMII_TXD[3] = \\<const0> ;
+  assign ENET1_GMII_TXD[2] = \\<const0> ;
+  assign ENET1_GMII_TXD[1] = \\<const0> ;
+  assign ENET1_GMII_TXD[0] = \\<const0> ;
+  assign ENET1_GMII_TX_EN = \\<const0> ;
+  assign ENET1_GMII_TX_ER = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[1:0] = \\^M_AXI_GP0_ARSIZE [1:0];
+  assign M_AXI_GP0_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_AWSIZE[1:0] = \\^M_AXI_GP0_AWSIZE [1:0];
+  assign M_AXI_GP1_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_ARSIZE[1:0] = \\^M_AXI_GP1_ARSIZE [1:0];
+  assign M_AXI_GP1_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_AWSIZE[1:0] = \\^M_AXI_GP1_AWSIZE [1:0];
+  assign PJTAG_TDO = \\<const0> ;
+  assign TRACE_CLK_OUT = \\<const0> ;
+  assign TRACE_CTL = \\TRACE_CTL_PIPE[0] ;
+  assign TRACE_DATA[1:0] = \\TRACE_DATA_PIPE[0] ;
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CAS_n_BIBUF
+       (.IO(buffered_DDR_CAS_n),
+        .PAD(DDR_CAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CKE_BIBUF
+       (.IO(buffered_DDR_CKE),
+        .PAD(DDR_CKE));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CS_n_BIBUF
+       (.IO(buffered_DDR_CS_n),
+        .PAD(DDR_CS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_BIBUF
+       (.IO(buffered_DDR_Clk),
+        .PAD(DDR_Clk));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_n_BIBUF
+       (.IO(buffered_DDR_Clk_n),
+        .PAD(DDR_Clk_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_DRSTB_BIBUF
+       (.IO(buffered_DDR_DRSTB),
+        .PAD(DDR_DRSTB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_ODT_BIBUF
+       (.IO(buffered_DDR_ODT),
+        .PAD(DDR_ODT));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_RAS_n_BIBUF
+       (.IO(buffered_DDR_RAS_n),
+        .PAD(DDR_RAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRN_BIBUF
+       (.IO(buffered_DDR_VRN),
+        .PAD(DDR_VRN));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRP_BIBUF
+       (.IO(buffered_DDR_VRP),
+        .PAD(DDR_VRP));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_WEB_BIBUF
+       (.IO(buffered_DDR_WEB),
+        .PAD(DDR_WEB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET0_MDIO_T_INST_0
+       (.I0(ENET0_MDIO_T_n),
+        .O(ENET0_MDIO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET1_MDIO_T_INST_0
+       (.I0(ENET1_MDIO_T_n),
+        .O(ENET1_MDIO_T));
+  GND GND
+       (.G(\\<const0> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[0]_INST_0 
+       (.I0(gpio_out_t_n[0]),
+        .O(GPIO_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[10]_INST_0 
+       (.I0(gpio_out_t_n[10]),
+        .O(GPIO_T[10]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[11]_INST_0 
+       (.I0(gpio_out_t_n[11]),
+        .O(GPIO_T[11]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[12]_INST_0 
+       (.I0(gpio_out_t_n[12]),
+        .O(GPIO_T[12]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[13]_INST_0 
+       (.I0(gpio_out_t_n[13]),
+        .O(GPIO_T[13]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[14]_INST_0 
+       (.I0(gpio_out_t_n[14]),
+        .O(GPIO_T[14]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[15]_INST_0 
+       (.I0(gpio_out_t_n[15]),
+        .O(GPIO_T[15]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[16]_INST_0 
+       (.I0(gpio_out_t_n[16]),
+        .O(GPIO_T[16]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[17]_INST_0 
+       (.I0(gpio_out_t_n[17]),
+        .O(GPIO_T[17]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[18]_INST_0 
+       (.I0(gpio_out_t_n[18]),
+        .O(GPIO_T[18]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[19]_INST_0 
+       (.I0(gpio_out_t_n[19]),
+        .O(GPIO_T[19]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[1]_INST_0 
+       (.I0(gpio_out_t_n[1]),
+        .O(GPIO_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[20]_INST_0 
+       (.I0(gpio_out_t_n[20]),
+        .O(GPIO_T[20]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[21]_INST_0 
+       (.I0(gpio_out_t_n[21]),
+        .O(GPIO_T[21]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[22]_INST_0 
+       (.I0(gpio_out_t_n[22]),
+        .O(GPIO_T[22]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[23]_INST_0 
+       (.I0(gpio_out_t_n[23]),
+        .O(GPIO_T[23]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[24]_INST_0 
+       (.I0(gpio_out_t_n[24]),
+        .O(GPIO_T[24]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[25]_INST_0 
+       (.I0(gpio_out_t_n[25]),
+        .O(GPIO_T[25]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[26]_INST_0 
+       (.I0(gpio_out_t_n[26]),
+        .O(GPIO_T[26]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[27]_INST_0 
+       (.I0(gpio_out_t_n[27]),
+        .O(GPIO_T[27]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[28]_INST_0 
+       (.I0(gpio_out_t_n[28]),
+        .O(GPIO_T[28]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[29]_INST_0 
+       (.I0(gpio_out_t_n[29]),
+        .O(GPIO_T[29]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[2]_INST_0 
+       (.I0(gpio_out_t_n[2]),
+        .O(GPIO_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[30]_INST_0 
+       (.I0(gpio_out_t_n[30]),
+        .O(GPIO_T[30]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[31]_INST_0 
+       (.I0(gpio_out_t_n[31]),
+        .O(GPIO_T[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[32]_INST_0 
+       (.I0(gpio_out_t_n[32]),
+        .O(GPIO_T[32]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[33]_INST_0 
+       (.I0(gpio_out_t_n[33]),
+        .O(GPIO_T[33]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[34]_INST_0 
+       (.I0(gpio_out_t_n[34]),
+        .O(GPIO_T[34]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[35]_INST_0 
+       (.I0(gpio_out_t_n[35]),
+        .O(GPIO_T[35]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[36]_INST_0 
+       (.I0(gpio_out_t_n[36]),
+        .O(GPIO_T[36]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[37]_INST_0 
+       (.I0(gpio_out_t_n[37]),
+        .O(GPIO_T[37]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[38]_INST_0 
+       (.I0(gpio_out_t_n[38]),
+        .O(GPIO_T[38]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[39]_INST_0 
+       (.I0(gpio_out_t_n[39]),
+        .O(GPIO_T[39]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[3]_INST_0 
+       (.I0(gpio_out_t_n[3]),
+        .O(GPIO_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[40]_INST_0 
+       (.I0(gpio_out_t_n[40]),
+        .O(GPIO_T[40]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[41]_INST_0 
+       (.I0(gpio_out_t_n[41]),
+        .O(GPIO_T[41]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[42]_INST_0 
+       (.I0(gpio_out_t_n[42]),
+        .O(GPIO_T[42]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[43]_INST_0 
+       (.I0(gpio_out_t_n[43]),
+        .O(GPIO_T[43]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[44]_INST_0 
+       (.I0(gpio_out_t_n[44]),
+        .O(GPIO_T[44]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[45]_INST_0 
+       (.I0(gpio_out_t_n[45]),
+        .O(GPIO_T[45]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[46]_INST_0 
+       (.I0(gpio_out_t_n[46]),
+        .O(GPIO_T[46]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[47]_INST_0 
+       (.I0(gpio_out_t_n[47]),
+        .O(GPIO_T[47]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[48]_INST_0 
+       (.I0(gpio_out_t_n[48]),
+        .O(GPIO_T[48]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[49]_INST_0 
+       (.I0(gpio_out_t_n[49]),
+        .O(GPIO_T[49]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[4]_INST_0 
+       (.I0(gpio_out_t_n[4]),
+        .O(GPIO_T[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[50]_INST_0 
+       (.I0(gpio_out_t_n[50]),
+        .O(GPIO_T[50]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[51]_INST_0 
+       (.I0(gpio_out_t_n[51]),
+        .O(GPIO_T[51]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[52]_INST_0 
+       (.I0(gpio_out_t_n[52]),
+        .O(GPIO_T[52]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[53]_INST_0 
+       (.I0(gpio_out_t_n[53]),
+        .O(GPIO_T[53]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[54]_INST_0 
+       (.I0(gpio_out_t_n[54]),
+        .O(GPIO_T[54]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[55]_INST_0 
+       (.I0(gpio_out_t_n[55]),
+        .O(GPIO_T[55]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[56]_INST_0 
+       (.I0(gpio_out_t_n[56]),
+        .O(GPIO_T[56]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[57]_INST_0 
+       (.I0(gpio_out_t_n[57]),
+        .O(GPIO_T[57]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[58]_INST_0 
+       (.I0(gpio_out_t_n[58]),
+        .O(GPIO_T[58]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[59]_INST_0 
+       (.I0(gpio_out_t_n[59]),
+        .O(GPIO_T[59]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[5]_INST_0 
+       (.I0(gpio_out_t_n[5]),
+        .O(GPIO_T[5]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[60]_INST_0 
+       (.I0(gpio_out_t_n[60]),
+        .O(GPIO_T[60]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[61]_INST_0 
+       (.I0(gpio_out_t_n[61]),
+        .O(GPIO_T[61]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[62]_INST_0 
+       (.I0(gpio_out_t_n[62]),
+        .O(GPIO_T[62]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[63]_INST_0 
+       (.I0(gpio_out_t_n[63]),
+        .O(GPIO_T[63]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[6]_INST_0 
+       (.I0(gpio_out_t_n[6]),
+        .O(GPIO_T[6]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[7]_INST_0 
+       (.I0(gpio_out_t_n[7]),
+        .O(GPIO_T[7]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[8]_INST_0 
+       (.I0(gpio_out_t_n[8]),
+        .O(GPIO_T[8]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[9]_INST_0 
+       (.I0(gpio_out_t_n[9]),
+        .O(GPIO_T[9]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SCL_T_INST_0
+       (.I0(I2C0_SCL_T_n),
+        .O(I2C0_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SDA_T_INST_0
+       (.I0(I2C0_SDA_T_n),
+        .O(I2C0_SDA_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SCL_T_INST_0
+       (.I0(I2C1_SCL_T_n),
+        .O(I2C1_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SDA_T_INST_0
+       (.I0(I2C1_SDA_T_n),
+        .O(I2C1_SDA_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  PS7 PS7_i
+       (.DDRA(buffered_DDR_Addr),
+        .DDRARB(DDR_ARB),
+        .DDRBA(buffered_DDR_BankAddr),
+        .DDRCASB(buffered_DDR_CAS_n),
+        .DDRCKE(buffered_DDR_CKE),
+        .DDRCKN(buffered_DDR_Clk_n),
+        .DDRCKP(buffered_DDR_Clk),
+        .DDRCSB(buffered_DDR_CS_n),
+        .DDRDM(buffered_DDR_DM),
+        .DDRDQ(buffered_DDR_DQ),
+        .DDRDQSN(buffered_DDR_DQS_n),
+        .DDRDQSP(buffered_DDR_DQS),
+        .DDRDRSTB(buffered_DDR_DRSTB),
+        .DDRODT(buffered_DDR_ODT),
+        .DDRRASB(buffered_DDR_RAS_n),
+        .DDRVRN(buffered_DDR_VRN),
+        .DDRVRP(buffered_DDR_VRP),
+        .DDRWEB(buffered_DDR_WEB),
+        .DMA0ACLK(DMA0_ACLK),
+        .DMA0DAREADY(DMA0_DAREADY),
+        .DMA0DATYPE(DMA0_DATYPE),
+        .DMA0DAVALID(DMA0_DAVALID),
+        .DMA0DRLAST(DMA0_DRLAST),
+        .DMA0DRREADY(DMA0_DRREADY),
+        .DMA0DRTYPE(DMA0_DRTYPE),
+        .DMA0DRVALID(DMA0_DRVALID),
+        .DMA0RSTN(DMA0_RSTN),
+        .DMA1ACLK(DMA1_ACLK),
+        .DMA1DAREADY(DMA1_DAREADY),
+        .DMA1DATYPE(DMA1_DATYPE),
+        .DMA1DAVALID(DMA1_DAVALID),
+        .DMA1DRLAST(DMA1_DRLAST),
+        .DMA1DRREADY(DMA1_DRREADY),
+        .DMA1DRTYPE(DMA1_DRTYPE),
+        .DMA1DRVALID(DMA1_DRVALID),
+        .DMA1RSTN(DMA1_RSTN),
+        .DMA2ACLK(DMA2_ACLK),
+        .DMA2DAREADY(DMA2_DAREADY),
+        .DMA2DATYPE(DMA2_DATYPE),
+        .DMA2DAVALID(DMA2_DAVALID),
+        .DMA2DRLAST(DMA2_DRLAST),
+        .DMA2DRREADY(DMA2_DRREADY),
+        .DMA2DRTYPE(DMA2_DRTYPE),
+        .DMA2DRVALID(DMA2_DRVALID),
+        .DMA2RSTN(DMA2_RSTN),
+        .DMA3ACLK(DMA3_ACLK),
+        .DMA3DAREADY(DMA3_DAREADY),
+        .DMA3DATYPE(DMA3_DATYPE),
+        .DMA3DAVALID(DMA3_DAVALID),
+        .DMA3DRLAST(DMA3_DRLAST),
+        .DMA3DRREADY(DMA3_DRREADY),
+        .DMA3DRTYPE(DMA3_DRTYPE),
+        .DMA3DRVALID(DMA3_DRVALID),
+        .DMA3RSTN(DMA3_RSTN),
+        .EMIOCAN0PHYRX(CAN0_PHY_RX),
+        .EMIOCAN0PHYTX(CAN0_PHY_TX),
+        .EMIOCAN1PHYRX(CAN1_PHY_RX),
+        .EMIOCAN1PHYTX(CAN1_PHY_TX),
+        .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+        .EMIOENET0GMIICOL(1\'b0),
+        .EMIOENET0GMIICRS(1\'b0),
+        .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+        .EMIOENET0GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET0GMIIRXDV(1\'b0),
+        .EMIOENET0GMIIRXER(1\'b0),
+        .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+        .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+        .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+        .EMIOENET0MDIOI(ENET0_MDIO_I),
+        .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+        .EMIOENET0MDIOO(ENET0_MDIO_O),
+        .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+        .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+        .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+        .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+        .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+        .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+        .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+        .EMIOENET0SOFRX(ENET0_SOF_RX),
+        .EMIOENET0SOFTX(ENET0_SOF_TX),
+        .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+        .EMIOENET1GMIICOL(1\'b0),
+        .EMIOENET1GMIICRS(1\'b0),
+        .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+        .EMIOENET1GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET1GMIIRXDV(1\'b0),
+        .EMIOENET1GMIIRXER(1\'b0),
+        .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+        .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+        .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+        .EMIOENET1MDIOI(ENET1_MDIO_I),
+        .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+        .EMIOENET1MDIOO(ENET1_MDIO_O),
+        .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+        .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+        .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+        .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+        .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+        .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+        .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+        .EMIOENET1SOFRX(ENET1_SOF_RX),
+        .EMIOENET1SOFTX(ENET1_SOF_TX),
+        .EMIOGPIOI(GPIO_I),
+        .EMIOGPIOO(GPIO_O),
+        .EMIOGPIOTN(gpio_out_t_n),
+        .EMIOI2C0SCLI(I2C0_SCL_I),
+        .EMIOI2C0SCLO(I2C0_SCL_O),
+        .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+        .EMIOI2C0SDAI(I2C0_SDA_I),
+        .EMIOI2C0SDAO(I2C0_SDA_O),
+        .EMIOI2C0SDATN(I2C0_SDA_T_n),
+        .EMIOI2C1SCLI(I2C1_SCL_I),
+        .EMIOI2C1SCLO(I2C1_SCL_O),
+        .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+        .EMIOI2C1SDAI(I2C1_SDA_I),
+        .EMIOI2C1SDAO(I2C1_SDA_O),
+        .EMIOI2C1SDATN(I2C1_SDA_T_n),
+        .EMIOPJTAGTCK(PJTAG_TCK),
+        .EMIOPJTAGTDI(PJTAG_TDI),
+        .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+        .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+        .EMIOPJTAGTMS(PJTAG_TMS),
+        .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+        .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+        .EMIOSDIO0CDN(SDIO0_CDN),
+        .EMIOSDIO0CLK(SDIO0_CLK),
+        .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+        .EMIOSDIO0CMDI(SDIO0_CMD_I),
+        .EMIOSDIO0CMDO(SDIO0_CMD_O),
+        .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+        .EMIOSDIO0DATAI(SDIO0_DATA_I),
+        .EMIOSDIO0DATAO(SDIO0_DATA_O),
+        .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+        .EMIOSDIO0LED(SDIO0_LED),
+        .EMIOSDIO0WP(SDIO0_WP),
+        .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+        .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+        .EMIOSDIO1CDN(SDIO1_CDN),
+        .EMIOSDIO1CLK(SDIO1_CLK),
+        .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+        .EMIOSDIO1CMDI(SDIO1_CMD_I),
+        .EMIOSDIO1CMDO(SDIO1_CMD_O),
+        .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+        .EMIOSDIO1DATAI(SDIO1_DATA_I),
+        .EMIOSDIO1DATAO(SDIO1_DATA_O),
+        .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+        .EMIOSDIO1LED(SDIO1_LED),
+        .EMIOSDIO1WP(SDIO1_WP),
+        .EMIOSPI0MI(SPI0_MISO_I),
+        .EMIOSPI0MO(SPI0_MOSI_O),
+        .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+        .EMIOSPI0SCLKI(SPI0_SCLK_I),
+        .EMIOSPI0SCLKO(SPI0_SCLK_O),
+        .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+        .EMIOSPI0SI(SPI0_MOSI_I),
+        .EMIOSPI0SO(SPI0_MISO_O),
+        .EMIOSPI0SSIN(SPI0_SS_I),
+        .EMIOSPI0SSNTN(SPI0_SS_T_n),
+        .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+        .EMIOSPI0STN(SPI0_MISO_T_n),
+        .EMIOSPI1MI(SPI1_MISO_I),
+        .EMIOSPI1MO(SPI1_MOSI_O),
+        .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+        .EMIOSPI1SCLKI(SPI1_SCLK_I),
+        .EMIOSPI1SCLKO(SPI1_SCLK_O),
+        .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+        .EMIOSPI1SI(SPI1_MOSI_I),
+        .EMIOSPI1SO(SPI1_MISO_O),
+        .EMIOSPI1SSIN(SPI1_SS_I),
+        .EMIOSPI1SSNTN(SPI1_SS_T_n),
+        .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+        .EMIOSPI1STN(SPI1_MISO_T_n),
+        .EMIOSRAMINTIN(SRAM_INTIN),
+        .EMIOTRACECLK(TRACE_CLK),
+        .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+        .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+        .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+        .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+        .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+        .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+        .EMIOUART0CTSN(UART0_CTSN),
+        .EMIOUART0DCDN(UART0_DCDN),
+        .EMIOUART0DSRN(UART0_DSRN),
+        .EMIOUART0DTRN(UART0_DTRN),
+        .EMIOUART0RIN(UART0_RIN),
+        .EMIOUART0RTSN(UART0_RTSN),
+        .EMIOUART0RX(UART0_RX),
+        .EMIOUART0TX(UART0_TX),
+        .EMIOUART1CTSN(UART1_CTSN),
+        .EMIOUART1DCDN(UART1_DCDN),
+        .EMIOUART1DSRN(UART1_DSRN),
+        .EMIOUART1DTRN(UART1_DTRN),
+        .EMIOUART1RIN(UART1_RIN),
+        .EMIOUART1RTSN(UART1_RTSN),
+        .EMIOUART1RX(UART1_RX),
+        .EMIOUART1TX(UART1_TX),
+        .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+        .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+        .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+        .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+        .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+        .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+        .EMIOWDTCLKI(WDT_CLK_IN),
+        .EMIOWDTRSTO(WDT_RST_OUT),
+        .EVENTEVENTI(EVENT_EVENTI),
+        .EVENTEVENTO(EVENT_EVENTO),
+        .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+        .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+        .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+        .FCLKCLKTRIGN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+        .FPGAIDLEN(FPGA_IDLE_N),
+        .FTMDTRACEINATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+        .FTMDTRACEINDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINVALID(1\'b0),
+        .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+        .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+        .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+        .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+        .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+        .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+        .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,IRQ_F2P}),
+        .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+        .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+        .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+        .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+        .MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
+        .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+        .MAXIGP0ARID(M_AXI_GP0_ARID),
+        .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+        .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+        .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+        .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+        .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+        .MAXIGP0ARSIZE(\\^M_AXI_GP0_ARSIZE ),
+        .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+        .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+        .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+        .MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
+        .MAXIGP0AWID(M_AXI_GP0_AWID),
+        .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+        .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+        .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+        .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+        .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+        .MAXIGP0AWSIZE(\\^M_AXI_GP0_AWSIZE ),
+        .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+        .MAXIGP0BID(M_AXI_GP0_BID),
+        .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+        .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+        .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+        .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+        .MAXIGP0RID(M_AXI_GP0_RID),
+        .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+        .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+        .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+        .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+        .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+        .MAXIGP0WID(M_AXI_GP0_WID),
+        .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+        .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+        .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+        .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+        .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+        .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+        .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+        .MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
+        .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+        .MAXIGP1ARID(M_AXI_GP1_ARID),
+        .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+        .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+        .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+        .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+        .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+        .MAXIGP1ARSIZE(\\^M_AXI_GP1_ARSIZE ),
+        .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+        .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+        .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+        .MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
+        .MAXIGP1AWID(M_AXI_GP1_AWID),
+        .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+        .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+        .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+        .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+        .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+        .MAXIGP1AWSIZE(\\^M_AXI_GP1_AWSIZE ),
+        .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+        .MAXIGP1BID(M_AXI_GP1_BID),
+        .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+        .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+        .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+        .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+        .MAXIGP1RID(M_AXI_GP1_RID),
+        .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+        .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+        .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+        .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+        .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+        .MAXIGP1WID(M_AXI_GP1_WID),
+        .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+        .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+        .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+        .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+        .MIO(buffered_MIO),
+        .PSCLK(buffered_PS_CLK),
+        .PSPORB(buffered_PS_PORB),
+        .PSSRSTB(buffered_PS_SRSTB),
+        .SAXIACPACLK(S_AXI_ACP_ACLK),
+        .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+        .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+        .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+        .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+        .SAXIACPARID(S_AXI_ACP_ARID),
+        .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+        .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+        .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+        .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+        .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+        .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+        .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+        .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+        .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+        .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+        .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+        .SAXIACPAWID(S_AXI_ACP_AWID),
+        .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+        .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+        .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+        .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+        .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+        .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+        .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+        .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+        .SAXIACPBID(S_AXI_ACP_BID),
+        .SAXIACPBREADY(S_AXI_ACP_BREADY),
+        .SAXIACPBRESP(S_AXI_ACP_BRESP),
+        .SAXIACPBVALID(S_AXI_ACP_BVALID),
+        .SAXIACPRDATA(S_AXI_ACP_RDATA),
+        .SAXIACPRID(S_AXI_ACP_RID),
+        .SAXIACPRLAST(S_AXI_ACP_RLAST),
+        .SAXIACPRREADY(S_AXI_ACP_RREADY),
+        .SAXIACPRRESP(S_AXI_ACP_RRESP),
+        .SAXIACPRVALID(S_AXI_ACP_RVALID),
+        .SAXIACPWDATA(S_AXI_ACP_WDATA),
+        .SAXIACPWID(S_AXI_ACP_WID),
+        .SAXIACPWLAST(S_AXI_ACP_WLAST),
+        .SAXIACPWREADY(S_AXI_ACP_WREADY),
+        .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+        .SAXIACPWVALID(S_AXI_ACP_WVALID),
+        .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+        .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+        .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+        .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+        .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+        .SAXIGP0ARID(S_AXI_GP0_ARID),
+        .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+        .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+        .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+        .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+        .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+        .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+        .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+        .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+        .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+        .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+        .SAXIGP0AWID(S_AXI_GP0_AWID),
+        .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+        .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+        .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+        .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+        .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+        .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+        .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+        .SAXIGP0BID(S_AXI_GP0_BID),
+        .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+        .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+        .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+        .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+        .SAXIGP0RID(S_AXI_GP0_RID),
+        .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+        .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+        .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+        .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+        .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+        .SAXIGP0WID(S_AXI_GP0_WID),
+        .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+        .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+        .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+        .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+        .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+        .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+        .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+        .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+        .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+        .SAXIGP1ARID(S_AXI_GP1_ARID),
+        .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+        .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+        .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+        .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+        .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+        .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+        .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+        .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+        .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+        .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+        .SAXIGP1AWID(S_AXI_GP1_AWID),
+        .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+        .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+        .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+        .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+        .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+        .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+        .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+        .SAXIGP1BID(S_AXI_GP1_BID),
+        .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+        .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+        .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+        .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+        .SAXIGP1RID(S_AXI_GP1_RID),
+        .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+        .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+        .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+        .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+        .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+        .SAXIGP1WID(S_AXI_GP1_WID),
+        .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+        .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+        .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+        .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+        .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+        .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+        .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+        .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+        .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+        .SAXIHP0ARID(S_AXI_HP0_ARID),
+        .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+        .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+        .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+        .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+        .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+        .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+        .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+        .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+        .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+        .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+        .SAXIHP0AWID(S_AXI_HP0_AWID),
+        .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+        .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+        .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+        .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+        .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+        .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+        .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+        .SAXIHP0BID(S_AXI_HP0_BID),
+        .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+        .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+        .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+        .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+        .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+        .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+        .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+        .SAXIHP0RID(S_AXI_HP0_RID),
+        .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+        .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+        .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+        .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+        .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+        .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+        .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+        .SAXIHP0WID(S_AXI_HP0_WID),
+        .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+        .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+        .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+        .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+        .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+        .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+        .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+        .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+        .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+        .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+        .SAXIHP1ARID(S_AXI_HP1_ARID),
+        .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+        .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+        .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+        .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+        .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+        .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+        .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+        .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+        .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+        .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+        .SAXIHP1AWID(S_AXI_HP1_AWID),
+        .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+        .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+        .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+        .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+        .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+        .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+        .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+        .SAXIHP1BID(S_AXI_HP1_BID),
+        .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+        .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+        .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+        .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+        .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+        .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+        .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+        .SAXIHP1RID(S_AXI_HP1_RID),
+        .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+        .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+        .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+        .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+        .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+        .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+        .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+        .SAXIHP1WID(S_AXI_HP1_WID),
+        .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+        .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+        .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+        .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+        .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+        .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+        .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+        .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+        .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+        .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+        .SAXIHP2ARID(S_AXI_HP2_ARID),
+        .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+        .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+        .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+        .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+        .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+        .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+        .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+        .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+        .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+        .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+        .SAXIHP2AWID(S_AXI_HP2_AWID),
+        .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+        .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+        .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+        .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+        .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+        .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+        .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+        .SAXIHP2BID(S_AXI_HP2_BID),
+        .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+        .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+        .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+        .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+        .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+        .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+        .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+        .SAXIHP2RID(S_AXI_HP2_RID),
+        .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+        .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+        .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+        .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+        .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+        .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+        .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+        .SAXIHP2WID(S_AXI_HP2_WID),
+        .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+        .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+        .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+        .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+        .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+        .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+        .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+        .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+        .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+        .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+        .SAXIHP3ARID(S_AXI_HP3_ARID),
+        .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+        .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+        .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+        .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+        .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+        .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+        .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+        .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+        .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+        .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+        .SAXIHP3AWID(S_AXI_HP3_AWID),
+        .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+        .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+        .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+        .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+        .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+        .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+        .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+        .SAXIHP3BID(S_AXI_HP3_BID),
+        .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+        .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+        .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+        .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+        .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+        .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+        .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+        .SAXIHP3RID(S_AXI_HP3_RID),
+        .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+        .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+        .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+        .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+        .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+        .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+        .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+        .SAXIHP3WID(S_AXI_HP3_WID),
+        .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+        .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+        .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+        .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+        .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_CLK_BIBUF
+       (.IO(buffered_PS_CLK),
+        .PAD(PS_CLK));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_PORB_BIBUF
+       (.IO(buffered_PS_PORB),
+        .PAD(PS_PORB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_SRSTB_BIBUF
+       (.IO(buffered_PS_SRSTB),
+        .PAD(PS_SRSTB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO0_CMD_T_INST_0
+       (.I0(SDIO0_CMD_T_n),
+        .O(SDIO0_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[0]_INST_0 
+       (.I0(SDIO0_DATA_T_n[0]),
+        .O(SDIO0_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[1]_INST_0 
+       (.I0(SDIO0_DATA_T_n[1]),
+        .O(SDIO0_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[2]_INST_0 
+       (.I0(SDIO0_DATA_T_n[2]),
+        .O(SDIO0_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[3]_INST_0 
+       (.I0(SDIO0_DATA_T_n[3]),
+        .O(SDIO0_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO1_CMD_T_INST_0
+       (.I0(SDIO1_CMD_T_n),
+        .O(SDIO1_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[0]_INST_0 
+       (.I0(SDIO1_DATA_T_n[0]),
+        .O(SDIO1_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[1]_INST_0 
+       (.I0(SDIO1_DATA_T_n[1]),
+        .O(SDIO1_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[2]_INST_0 
+       (.I0(SDIO1_DATA_T_n[2]),
+        .O(SDIO1_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[3]_INST_0 
+       (.I0(SDIO1_DATA_T_n[3]),
+        .O(SDIO1_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MISO_T_INST_0
+       (.I0(SPI0_MISO_T_n),
+        .O(SPI0_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MOSI_T_INST_0
+       (.I0(SPI0_MOSI_T_n),
+        .O(SPI0_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SCLK_T_INST_0
+       (.I0(SPI0_SCLK_T_n),
+        .O(SPI0_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SS_T_INST_0
+       (.I0(SPI0_SS_T_n),
+        .O(SPI0_SS_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MISO_T_INST_0
+       (.I0(SPI1_MISO_T_n),
+        .O(SPI1_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MOSI_T_INST_0
+       (.I0(SPI1_MOSI_T_n),
+        .O(SPI1_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SCLK_T_INST_0
+       (.I0(SPI1_SCLK_T_n),
+        .O(SPI1_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SS_T_INST_0
+       (.I0(SPI1_SS_T_n),
+        .O(SPI1_SS_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BUFG \\buffer_fclk_clk_0.FCLK_CLK_0_BUFG 
+       (.I(FCLK_CLK_unbuffered),
+        .O(FCLK_CLK0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[0].MIO_BIBUF 
+       (.IO(buffered_MIO[0]),
+        .PAD(MIO[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[10].MIO_BIBUF 
+       (.IO(buffered_MIO[10]),
+        .PAD(MIO[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[11].MIO_BIBUF 
+       (.IO(buffered_MIO[11]),
+        .PAD(MIO[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[12].MIO_BIBUF 
+       (.IO(buffered_MIO[12]),
+        .PAD(MIO[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[13].MIO_BIBUF 
+       (.IO(buffered_MIO[13]),
+        .PAD(MIO[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[14].MIO_BIBUF 
+       (.IO(buffered_MIO[14]),
+        .PAD(MIO[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[15].MIO_BIBUF 
+       (.IO(buffered_MIO[15]),
+        .PAD(MIO[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[16].MIO_BIBUF 
+       (.IO(buffered_MIO[16]),
+        .PAD(MIO[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[17].MIO_BIBUF 
+       (.IO(buffered_MIO[17]),
+        .PAD(MIO[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[18].MIO_BIBUF 
+       (.IO(buffered_MIO[18]),
+        .PAD(MIO[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[19].MIO_BIBUF 
+       (.IO(buffered_MIO[19]),
+        .PAD(MIO[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[1].MIO_BIBUF 
+       (.IO(buffered_MIO[1]),
+        .PAD(MIO[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[20].MIO_BIBUF 
+       (.IO(buffered_MIO[20]),
+        .PAD(MIO[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[21].MIO_BIBUF 
+       (.IO(buffered_MIO[21]),
+        .PAD(MIO[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[22].MIO_BIBUF 
+       (.IO(buffered_MIO[22]),
+        .PAD(MIO[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[23].MIO_BIBUF 
+       (.IO(buffered_MIO[23]),
+        .PAD(MIO[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[24].MIO_BIBUF 
+       (.IO(buffered_MIO[24]),
+        .PAD(MIO[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[25].MIO_BIBUF 
+       (.IO(buffered_MIO[25]),
+        .PAD(MIO[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[26].MIO_BIBUF 
+       (.IO(buffered_MIO[26]),
+        .PAD(MIO[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[27].MIO_BIBUF 
+       (.IO(buffered_MIO[27]),
+        .PAD(MIO[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[28].MIO_BIBUF 
+       (.IO(buffered_MIO[28]),
+        .PAD(MIO[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[29].MIO_BIBUF 
+       (.IO(buffered_MIO[29]),
+        .PAD(MIO[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[2].MIO_BIBUF 
+       (.IO(buffered_MIO[2]),
+        .PAD(MIO[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[30].MIO_BIBUF 
+       (.IO(buffered_MIO[30]),
+        .PAD(MIO[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[31].MIO_BIBUF 
+       (.IO(buffered_MIO[31]),
+        .PAD(MIO[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[32].MIO_BIBUF 
+       (.IO(buffered_MIO[32]),
+        .PAD(MIO[32]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[33].MIO_BIBUF 
+       (.IO(buffered_MIO[33]),
+        .PAD(MIO[33]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[34].MIO_BIBUF 
+       (.IO(buffered_MIO[34]),
+        .PAD(MIO[34]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[35].MIO_BIBUF 
+       (.IO(buffered_MIO[35]),
+        .PAD(MIO[35]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[36].MIO_BIBUF 
+       (.IO(buffered_MIO[36]),
+        .PAD(MIO[36]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[37].MIO_BIBUF 
+       (.IO(buffered_MIO[37]),
+        .PAD(MIO[37]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[38].MIO_BIBUF 
+       (.IO(buffered_MIO[38]),
+        .PAD(MIO[38]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[39].MIO_BIBUF 
+       (.IO(buffered_MIO[39]),
+        .PAD(MIO[39]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[3].MIO_BIBUF 
+       (.IO(buffered_MIO[3]),
+        .PAD(MIO[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[40].MIO_BIBUF 
+       (.IO(buffered_MIO[40]),
+        .PAD(MIO[40]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[41].MIO_BIBUF 
+       (.IO(buffered_MIO[41]),
+        .PAD(MIO[41]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[42].MIO_BIBUF 
+       (.IO(buffered_MIO[42]),
+        .PAD(MIO[42]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[43].MIO_BIBUF 
+       (.IO(buffered_MIO[43]),
+        .PAD(MIO[43]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[44].MIO_BIBUF 
+       (.IO(buffered_MIO[44]),
+        .PAD(MIO[44]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[45].MIO_BIBUF 
+       (.IO(buffered_MIO[45]),
+        .PAD(MIO[45]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[46].MIO_BIBUF 
+       (.IO(buffered_MIO[46]),
+        .PAD(MIO[46]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[47].MIO_BIBUF 
+       (.IO(buffered_MIO[47]),
+        .PAD(MIO[47]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[48].MIO_BIBUF 
+       (.IO(buffered_MIO[48]),
+        .PAD(MIO[48]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[49].MIO_BIBUF 
+       (.IO(buffered_MIO[49]),
+        .PAD(MIO[49]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[4].MIO_BIBUF 
+       (.IO(buffered_MIO[4]),
+        .PAD(MIO[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[50].MIO_BIBUF 
+       (.IO(buffered_MIO[50]),
+        .PAD(MIO[50]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[51].MIO_BIBUF 
+       (.IO(buffered_MIO[51]),
+        .PAD(MIO[51]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[52].MIO_BIBUF 
+       (.IO(buffered_MIO[52]),
+        .PAD(MIO[52]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[53].MIO_BIBUF 
+       (.IO(buffered_MIO[53]),
+        .PAD(MIO[53]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[5].MIO_BIBUF 
+       (.IO(buffered_MIO[5]),
+        .PAD(MIO[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[6].MIO_BIBUF 
+       (.IO(buffered_MIO[6]),
+        .PAD(MIO[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[7].MIO_BIBUF 
+       (.IO(buffered_MIO[7]),
+        .PAD(MIO[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[8].MIO_BIBUF 
+       (.IO(buffered_MIO[8]),
+        .PAD(MIO[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[9].MIO_BIBUF 
+       (.IO(buffered_MIO[9]),
+        .PAD(MIO[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[0].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[0]),
+        .PAD(DDR_BankAddr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[1].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[1]),
+        .PAD(DDR_BankAddr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[2].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[2]),
+        .PAD(DDR_BankAddr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[0].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[0]),
+        .PAD(DDR_Addr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[10].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[10]),
+        .PAD(DDR_Addr[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[11].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[11]),
+        .PAD(DDR_Addr[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[12].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[12]),
+        .PAD(DDR_Addr[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[13].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[13]),
+        .PAD(DDR_Addr[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[14].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[14]),
+        .PAD(DDR_Addr[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[1].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[1]),
+        .PAD(DDR_Addr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[2].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[2]),
+        .PAD(DDR_Addr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[3].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[3]),
+        .PAD(DDR_Addr[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[4].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[4]),
+        .PAD(DDR_Addr[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[5].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[5]),
+        .PAD(DDR_Addr[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[6].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[6]),
+        .PAD(DDR_Addr[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[7].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[7]),
+        .PAD(DDR_Addr[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[8].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[8]),
+        .PAD(DDR_Addr[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[9].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[9]),
+        .PAD(DDR_Addr[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[0].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[0]),
+        .PAD(DDR_DM[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[1].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[1]),
+        .PAD(DDR_DM[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[2].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[2]),
+        .PAD(DDR_DM[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[3].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[3]),
+        .PAD(DDR_DM[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[0].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[0]),
+        .PAD(DDR_DQ[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[10].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[10]),
+        .PAD(DDR_DQ[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[11].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[11]),
+        .PAD(DDR_DQ[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[12].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[12]),
+        .PAD(DDR_DQ[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[13].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[13]),
+        .PAD(DDR_DQ[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[14].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[14]),
+        .PAD(DDR_DQ[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[15].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[15]),
+        .PAD(DDR_DQ[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[16].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[16]),
+        .PAD(DDR_DQ[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[17].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[17]),
+        .PAD(DDR_DQ[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[18].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[18]),
+        .PAD(DDR_DQ[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[19].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[19]),
+        .PAD(DDR_DQ[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[1].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[1]),
+        .PAD(DDR_DQ[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[20].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[20]),
+        .PAD(DDR_DQ[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[21].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[21]),
+        .PAD(DDR_DQ[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[22].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[22]),
+        .PAD(DDR_DQ[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[23].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[23]),
+        .PAD(DDR_DQ[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[24].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[24]),
+        .PAD(DDR_DQ[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[25].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[25]),
+        .PAD(DDR_DQ[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[26].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[26]),
+        .PAD(DDR_DQ[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[27].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[27]),
+        .PAD(DDR_DQ[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[28].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[28]),
+        .PAD(DDR_DQ[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[29].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[29]),
+        .PAD(DDR_DQ[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[2].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[2]),
+        .PAD(DDR_DQ[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[30].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[30]),
+        .PAD(DDR_DQ[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[31].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[31]),
+        .PAD(DDR_DQ[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[3].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[3]),
+        .PAD(DDR_DQ[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[4].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[4]),
+        .PAD(DDR_DQ[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[5].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[5]),
+        .PAD(DDR_DQ[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[6].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[6]),
+        .PAD(DDR_DQ[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[7].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[7]),
+        .PAD(DDR_DQ[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[8].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[8]),
+        .PAD(DDR_DQ[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[9].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[9]),
+        .PAD(DDR_DQ[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[0].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[0]),
+        .PAD(DDR_DQS_n[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[1].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[1]),
+        .PAD(DDR_DQS_n[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[2].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[2]),
+        .PAD(DDR_DQS_n[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[3].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[3]),
+        .PAD(DDR_DQS_n[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[0].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[0]),
+        .PAD(DDR_DQS[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[1].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[1]),
+        .PAD(DDR_DQS[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[2].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[2]),
+        .PAD(DDR_DQS[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[3].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[3]),
+        .PAD(DDR_DQS[3]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_0
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[0] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_1
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_10
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_11
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_12
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_13
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_14
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_15
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_16
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_17
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_18
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_19
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_2
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_20
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_21
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_22
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_23
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_3
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[7] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_4
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[6] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_5
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[5] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_6
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[4] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_7
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[3] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_8
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[2] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_9
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, ""Critical
+// Applications""). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
+// IP Revision: 12
+
+(* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *)
+(* CHECK_LICENSE_TYPE = ""design_1_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}"" *)
+(* CORE_GENERATION_INFO = ""design_1_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=3,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0xffffffffffffffff00000000412100000000000041200000,C_M_AXI_ADDR_WIDTH=0x000000000000001000000010,C_S_AXI_BASE_ID=0x000\\
+00000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x000000010000000100000001,C_M_AXI_READ_ISSUING=0x000000010000000100000001,C_S_\\
+AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x000000000000000000000000,C_CONNECTIVITY_MODE=0}"" *)
+(* DowngradeIPIdentifiedWarnings = ""yes"" *)
+module design_1_xbar_0 (
+  aclk,
+  aresetn,
+  s_axi_awaddr,
+  s_axi_awprot,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arprot,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLKIF CLK"" *)
+input wire aclk;
+(* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RSTIF RST"" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"" *)
+input wire [0 : 0] s_axi_awvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"" *)
+output wire [0 : 0] s_axi_awready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WDATA"" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WVALID"" *)
+input wire [0 : 0] s_axi_wvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WREADY"" *)
+output wire [0 : 0] s_axi_wready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BRESP"" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BVALID"" *)
+output wire [0 : 0] s_axi_bvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BREADY"" *)
+input wire [0 : 0] s_axi_bready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"" *)
+input wire [0 : 0] s_axi_arvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"" *)
+output wire [0 : 0] s_axi_arready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RDATA"" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RRESP"" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RVALID"" *)
+output wire [0 : 0] s_axi_rvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RREADY"" *)
+input wire [0 : 0] s_axi_rready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]"" *)
+output wire [95 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]"" *)
+output wire [8 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_awvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_awready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]"" *)
+output wire [95 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]"" *)
+output wire [11 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_wvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_wready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]"" *)
+input wire [5 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_bvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_bready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]"" *)
+output wire [95 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]"" *)
+output wire [8 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_arvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_arready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]"" *)
+input wire [95 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]"" *)
+input wire [5 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_rvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_rready;
+
+  axi_crossbar_v2_1_12_axi_crossbar #(
+    .C_FAMILY(""zynq""),
+    .C_NUM_SLAVE_SLOTS(1),
+    .C_NUM_MASTER_SLOTS(3),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_PROTOCOL(2),
+    .C_NUM_ADDR_RANGES(1),
+    .C_M_AXI_BASE_ADDR(192\'Hffffffffffffffff00000000412100000000000041200000),
+    .C_M_AXI_ADDR_WIDTH(96\'H000000000000001000000010),
+    .C_S_AXI_BASE_ID(32\'H00000000),
+    .C_S_AXI_THREAD_ID_WIDTH(32\'H00000000),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_M_AXI_WRITE_CONNECTIVITY(96\'H000000010000000100000001),
+    .C_M_AXI_READ_CONNECTIVITY(96\'H000000010000000100000001),
+    .C_R_REGISTER(1),
+    .C_S_AXI_SINGLE_THREAD(32\'H00000001),
+    .C_S_AXI_WRITE_ACCEPTANCE(32\'H00000001),
+    .C_S_AXI_READ_ACCEPTANCE(32\'H00000001),
+    .C_M_AXI_WRITE_ISSUING(96\'H000000010000000100000001),
+    .C_M_AXI_READ_ISSUING(96\'H000000010000000100000001),
+    .C_S_AXI_ARB_PRIORITY(32\'H00000000),
+    .C_M_AXI_SECURE(96\'H000000000000000000000000),
+    .C_CONNECTIVITY_MODE(0)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(1\'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(8\'H00),
+    .s_axi_awsize(3\'H0),
+    .s_axi_awburst(2\'H0),
+    .s_axi_awlock(1\'H0),
+    .s_axi_awcache(4\'H0),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(4\'H0),
+    .s_axi_awuser(1\'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1\'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(1\'H1),
+    .s_axi_wuser(1\'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1\'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(8\'H00),
+    .s_axi_arsize(3\'H0),
+    .s_axi_arburst(2\'H0),
+    .s_axi_arlock(1\'H0),
+    .s_axi_arcache(4\'H0),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(4\'H0),
+    .s_axi_aruser(1\'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(3\'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(3\'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(3\'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(3\'H7),
+    .m_axi_ruser(3\'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_axi_gp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for AXI GP ports
+ *
+ *****************************************************************************/
+
+    /* IDs for Masters 
+       // l2m1 (CPU000)
+       12'b11_000_000_00_00    
+       12'b11_010_000_00_00     
+       12'b11_011_000_00_00   
+       12'b11_100_000_00_00   
+       12'b11_101_000_00_00   
+       12'b11_110_000_00_00     
+       12'b11_111_000_00_00     
+       // l2m1 (CPU001)
+       12'b11_000_001_00_00    
+       12'b11_010_001_00_00     
+       12'b11_011_001_00_00    
+       12'b11_100_001_00_00    
+       12'b11_101_001_00_00    
+       12'b11_110_001_00_00     
+       12'b11_111_001_00_00    
+   */
+ 
+/* AXI -Master GP0 */
+  processing_system7_bfm_v2_0_5_axi_master #(C_USE_M_AXI_GP0, // enable
+               axi_mgp0_name,// name
+               axi_mgp_data_width, /// Data Width
+               addr_width, /// Address width
+               axi_mgp_id_width,  //// ID Width
+               axi_mgp_outstanding,  //// Outstanding transactions
+               axi_mst_excl_support, // EXCL Access Support
+               axi_mgp_wr_id, //WR_ID
+               axi_mgp_rd_id) //RD_ID
+  M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
+            .M_ACLK   (M_AXI_GP0_ACLK),
+            // Write Address Channel
+            .M_AWID    (M_AXI_GP0_AWID_FULL),
+            .M_AWADDR  (M_AXI_GP0_AWADDR),
+            .M_AWLEN   (M_AXI_GP0_AWLEN),
+            .M_AWSIZE  (M_AXI_GP0_AWSIZE),
+            .M_AWBURST (M_AXI_GP0_AWBURST),
+            .M_AWLOCK  (M_AXI_GP0_AWLOCK),
+            .M_AWCACHE (M_AXI_GP0_AWCACHE),
+            .M_AWPROT  (M_AXI_GP0_AWPROT),
+            .M_AWVALID (M_AXI_GP0_AWVALID),
+            .M_AWREADY (M_AXI_GP0_AWREADY),
+            // Write Data Channel Signals.
+            .M_WID    (M_AXI_GP0_WID_FULL),
+            .M_WDATA  (M_AXI_GP0_WDATA),
+            .M_WSTRB  (M_AXI_GP0_WSTRB), 
+            .M_WLAST  (M_AXI_GP0_WLAST), 
+            .M_WVALID (M_AXI_GP0_WVALID),
+            .M_WREADY (M_AXI_GP0_WREADY),
+            // Write Response Channel Signals.
+            .M_BID    (M_AXI_GP0_BID_FULL),
+            .M_BRESP  (M_AXI_GP0_BRESP),
+            .M_BVALID (M_AXI_GP0_BVALID),
+            .M_BREADY (M_AXI_GP0_BREADY),
+            // Read Address Channel Signals.
+            .M_ARID    (M_AXI_GP0_ARID_FULL),
+            .M_ARADDR  (M_AXI_GP0_ARADDR),
+            .M_ARLEN   (M_AXI_GP0_ARLEN),
+            .M_ARSIZE  (M_AXI_GP0_ARSIZE),
+            .M_ARBURST (M_AXI_GP0_ARBURST),
+            .M_ARLOCK  (M_AXI_GP0_ARLOCK),
+            .M_ARCACHE (M_AXI_GP0_ARCACHE),
+            .M_ARPROT  (M_AXI_GP0_ARPROT),
+            .M_ARVALID (M_AXI_GP0_ARVALID),
+            .M_ARREADY (M_AXI_GP0_ARREADY),
+            // Read Data Channel Signals.
+            .M_RID    (M_AXI_GP0_RID_FULL),
+            .M_RDATA  (M_AXI_GP0_RDATA),
+            .M_RRESP  (M_AXI_GP0_RRESP),
+            .M_RLAST  (M_AXI_GP0_RLAST),
+            .M_RVALID (M_AXI_GP0_RVALID),
+            .M_RREADY (M_AXI_GP0_RREADY),
+            // Side band signals 
+            .M_AWQOS  (M_AXI_GP0_AWQOS),
+            .M_ARQOS  (M_AXI_GP0_ARQOS)
+            ); 
+ 
+ /* AXI Master GP1 */
+  processing_system7_bfm_v2_0_5_axi_master #(C_USE_M_AXI_GP1, // enable
+               axi_mgp1_name,// name
+               axi_mgp_data_width, /// Data Width
+               addr_width, /// Address width
+               axi_mgp_id_width,  //// ID Width
+               axi_mgp_outstanding,  //// Outstanding transactions
+               axi_mst_excl_support, // EXCL Access Support
+               axi_mgp_wr_id, //WR_ID
+               axi_mgp_rd_id) //RD_ID
+  M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
+            .M_ACLK   (M_AXI_GP1_ACLK),
+            // Write Address Channel
+            .M_AWID    (M_AXI_GP1_AWID_FULL),
+            .M_AWADDR  (M_AXI_GP1_AWADDR),
+            .M_AWLEN   (M_AXI_GP1_AWLEN),
+            .M_AWSIZE  (M_AXI_GP1_AWSIZE),
+            .M_AWBURST (M_AXI_GP1_AWBURST),
+            .M_AWLOCK  (M_AXI_GP1_AWLOCK),
+            .M_AWCACHE (M_AXI_GP1_AWCACHE),
+            .M_AWPROT  (M_AXI_GP1_AWPROT),
+            .M_AWVALID (M_AXI_GP1_AWVALID),
+            .M_AWREADY (M_AXI_GP1_AWREADY),
+            // Write Data Channel Signals.
+            .M_WID    (M_AXI_GP1_WID_FULL),
+            .M_WDATA  (M_AXI_GP1_WDATA),
+            .M_WSTRB  (M_AXI_GP1_WSTRB), 
+            .M_WLAST  (M_AXI_GP1_WLAST), 
+            .M_WVALID (M_AXI_GP1_WVALID),
+            .M_WREADY (M_AXI_GP1_WREADY),
+            // Write Response Channel Signals.
+            .M_BID    (M_AXI_GP1_BID_FULL),
+            .M_BRESP  (M_AXI_GP1_BRESP),
+            .M_BVALID (M_AXI_GP1_BVALID),
+            .M_BREADY (M_AXI_GP1_BREADY),
+            // Read Address Channel Signals.
+            .M_ARID    (M_AXI_GP1_ARID_FULL),
+            .M_ARADDR  (M_AXI_GP1_ARADDR),
+            .M_ARLEN   (M_AXI_GP1_ARLEN),
+            .M_ARSIZE  (M_AXI_GP1_ARSIZE),
+            .M_ARBURST (M_AXI_GP1_ARBURST),
+            .M_ARLOCK  (M_AXI_GP1_ARLOCK),
+            .M_ARCACHE (M_AXI_GP1_ARCACHE),
+            .M_ARPROT  (M_AXI_GP1_ARPROT),
+            .M_ARVALID (M_AXI_GP1_ARVALID),
+            .M_ARREADY (M_AXI_GP1_ARREADY),
+            // Read Data Channel Signals.
+            .M_RID    (M_AXI_GP1_RID_FULL),
+            .M_RDATA  (M_AXI_GP1_RDATA),
+            .M_RRESP  (M_AXI_GP1_RRESP),
+            .M_RLAST  (M_AXI_GP1_RLAST),
+            .M_RVALID (M_AXI_GP1_RVALID),
+            .M_RREADY (M_AXI_GP1_RREADY),
+            // Side band signals 
+            .M_AWQOS  (M_AXI_GP1_AWQOS),
+            .M_ARQOS  (M_AXI_GP1_ARQOS)
+           );
+
+/* AXI Slave GP0 */
+  processing_system7_bfm_v2_0_5_axi_slave #(C_USE_S_AXI_GP0, /// enable
+              axi_sgp0_name, //name
+              axi_sgp_data_width, /// data width
+              addr_width, /// address width
+              axi_sgp_id_width,  /// ID width
+              C_S_AXI_GP0_BASEADDR,//// base address
+              C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr) 
+              axi_sgp_outstanding, // outstanding transactions
+              axi_slv_excl_support, // exclusive access not supported
+              axi_sgp_wr_outstanding,
+              axi_sgp_rd_outstanding)
+  S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
+            .S_ACLK   (S_AXI_GP0_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_GP0_AWID),
+            .S_AWADDR  (S_AXI_GP0_AWADDR),
+            .S_AWLEN   (S_AXI_GP0_AWLEN),
+            .S_AWSIZE  (S_AXI_GP0_AWSIZE),
+            .S_AWBURST (S_AXI_GP0_AWBURST),
+            .S_AWLOCK  (S_AXI_GP0_AWLOCK),
+            .S_AWCACHE (S_AXI_GP0_AWCACHE),
+            .S_AWPROT  (S_AXI_GP0_AWPROT),
+            .S_AWVALID (S_AXI_GP0_AWVALID),
+            .S_AWREADY (S_AXI_GP0_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_GP0_WID),
+            .S_WDATA  (S_AXI_GP0_WDATA),
+            .S_WSTRB  (S_AXI_GP0_WSTRB), 
+            .S_WLAST  (S_AXI_GP0_WLAST), 
+            .S_WVALID (S_AXI_GP0_WVALID),
+            .S_WREADY (S_AXI_GP0_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_GP0_BID),
+            .S_BRESP  (S_AXI_GP0_BRESP),
+            .S_BVALID (S_AXI_GP0_BVALID),
+            .S_BREADY (S_AXI_GP0_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_GP0_ARID),
+            .S_ARADDR  (S_AXI_GP0_ARADDR),
+            .S_ARLEN   (S_AXI_GP0_ARLEN),
+            .S_ARSIZE  (S_AXI_GP0_ARSIZE),
+            .S_ARBURST (S_AXI_GP0_ARBURST),
+            .S_ARLOCK  (S_AXI_GP0_ARLOCK),
+            .S_ARCACHE (S_AXI_GP0_ARCACHE),
+            .S_ARPROT  (S_AXI_GP0_ARPROT),
+            .S_ARVALID (S_AXI_GP0_ARVALID),
+            .S_ARREADY (S_AXI_GP0_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_GP0_RID),
+            .S_RDATA  (S_AXI_GP0_RDATA),
+            .S_RRESP  (S_AXI_GP0_RRESP),
+            .S_RLAST  (S_AXI_GP0_RLAST),
+            .S_RVALID (S_AXI_GP0_RVALID),
+            .S_RREADY (S_AXI_GP0_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_GP0_AWQOS),
+            .S_ARQOS  (S_AXI_GP0_ARQOS),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
+            .WR_DATA  (net_wr_data_gp0), 
+            .WR_ADDR  (net_wr_addr_gp0), 
+            .WR_BYTES  (net_wr_bytes_gp0), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_gp0), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_gp0), 
+            .WR_QOS (net_wr_qos_gp0),
+            .RD_REQ_DDR (net_rd_req_ddr_gp0),
+            .RD_REQ_OCM (net_rd_req_ocm_gp0),
+            .RD_REQ_REG (net_rd_req_reg_gp0),
+            .RD_ADDR (net_rd_addr_gp0),
+            .RD_DATA_DDR (net_rd_data_ddr_gp0),
+            .RD_DATA_OCM (net_rd_data_ocm_gp0),
+            .RD_DATA_REG (net_rd_data_reg_gp0),
+            .RD_BYTES (net_rd_bytes_gp0),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
+            .RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
+            .RD_QOS (net_rd_qos_gp0)
+
+);
+
+/* AXI Slave GP1 */
+  processing_system7_bfm_v2_0_5_axi_slave #(C_USE_S_AXI_GP1, /// enable
+              axi_sgp1_name, //name
+              axi_sgp_data_width, /// data width
+              addr_width, /// address width
+              axi_sgp_id_width,  /// ID width
+              C_S_AXI_GP1_BASEADDR,//// base address
+              C_S_AXI_GP1_HIGHADDR,/// HIGh_addr 
+              axi_sgp_outstanding, // outstanding transactions
+              axi_slv_excl_support, // exclusive access
+              axi_sgp_wr_outstanding,
+              axi_sgp_rd_outstanding)
+  S_AXI_GP1(.S_RESETN  (net_axi_gp1_rstn),
+            .S_ACLK    (S_AXI_GP1_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_GP1_AWID),
+            .S_AWADDR  (S_AXI_GP1_AWADDR),
+            .S_AWLEN   (S_AXI_GP1_AWLEN),
+            .S_AWSIZE  (S_AXI_GP1_AWSIZE),
+            .S_AWBURST (S_AXI_GP1_AWBURST),
+            .S_AWLOCK  (S_AXI_GP1_AWLOCK),
+            .S_AWCACHE (S_AXI_GP1_AWCACHE),
+            .S_AWPROT  (S_AXI_GP1_AWPROT),
+            .S_AWVALID (S_AXI_GP1_AWVALID),
+            .S_AWREADY (S_AXI_GP1_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_GP1_WID),
+            .S_WDATA  (S_AXI_GP1_WDATA),
+            .S_WSTRB  (S_AXI_GP1_WSTRB), 
+            .S_WLAST  (S_AXI_GP1_WLAST), 
+            .S_WVALID (S_AXI_GP1_WVALID),
+            .S_WREADY (S_AXI_GP1_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_GP1_BID),
+            .S_BRESP  (S_AXI_GP1_BRESP),
+            .S_BVALID (S_AXI_GP1_BVALID),
+            .S_BREADY (S_AXI_GP1_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_GP1_ARID),
+            .S_ARADDR  (S_AXI_GP1_ARADDR),
+            .S_ARLEN   (S_AXI_GP1_ARLEN),
+            .S_ARSIZE  (S_AXI_GP1_ARSIZE),
+            .S_ARBURST (S_AXI_GP1_ARBURST),
+            .S_ARLOCK  (S_AXI_GP1_ARLOCK),
+            .S_ARCACHE (S_AXI_GP1_ARCACHE),
+            .S_ARPROT  (S_AXI_GP1_ARPROT),
+            .S_ARVALID (S_AXI_GP1_ARVALID),
+            .S_ARREADY (S_AXI_GP1_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_GP1_RID),
+            .S_RDATA  (S_AXI_GP1_RDATA),
+            .S_RRESP  (S_AXI_GP1_RRESP),
+            .S_RLAST  (S_AXI_GP1_RLAST),
+            .S_RVALID (S_AXI_GP1_RVALID),
+            .S_RREADY (S_AXI_GP1_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_GP1_AWQOS),
+            .S_ARQOS  (S_AXI_GP1_ARQOS),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
+            .WR_DATA  (net_wr_data_gp1), 
+            .WR_ADDR  (net_wr_addr_gp1), 
+            .WR_BYTES  (net_wr_bytes_gp1), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_gp1), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_gp1), 
+            .WR_QOS (net_wr_qos_gp1),
+            .RD_REQ_OCM (net_rd_req_ocm_gp1),
+            .RD_REQ_DDR (net_rd_req_ddr_gp1),
+            .RD_REQ_REG (net_rd_req_reg_gp1),
+            .RD_ADDR (net_rd_addr_gp1),
+            .RD_DATA_DDR (net_rd_data_ddr_gp1),
+            .RD_DATA_OCM (net_rd_data_ocm_gp1),
+            .RD_DATA_REG (net_rd_data_reg_gp1),
+            .RD_BYTES (net_rd_bytes_gp1),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
+            .RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
+            .RD_QOS (net_rd_qos_gp1)
+
+);
+"
+"//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+//Date        : Tue Feb 14 01:36:24 2017
+//Host        : TheMosass-PC running 64-bit major release  (build 9200)
+//Command     : generate_target design_1.bd
+//Design      : design_1
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CORE_GENERATION_INFO = ""design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=11,numReposBlks=6,numNonXlnxBlks=0,numHierBlks=5,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=4,da_board_cnt=10,synth_mode=OOC_per_IP}"" *) (* HW_HANDOFF = ""design_1.hwdef"" *) 
+module design_1
+   (DDR_addr,
+    DDR_ba,
+    DDR_cas_n,
+    DDR_ck_n,
+    DDR_ck_p,
+    DDR_cke,
+    DDR_cs_n,
+    DDR_dm,
+    DDR_dq,
+    DDR_dqs_n,
+    DDR_dqs_p,
+    DDR_odt,
+    DDR_ras_n,
+    DDR_reset_n,
+    DDR_we_n,
+    FIXED_IO_ddr_vrn,
+    FIXED_IO_ddr_vrp,
+    FIXED_IO_mio,
+    FIXED_IO_ps_clk,
+    FIXED_IO_ps_porb,
+    FIXED_IO_ps_srstb,
+    btns_4bits_tri_i,
+    leds_4bits_tri_i,
+    leds_4bits_tri_o,
+    leds_4bits_tri_t,
+    sws_4bits_tri_i);
+  inout [14:0]DDR_addr;
+  inout [2:0]DDR_ba;
+  inout DDR_cas_n;
+  inout DDR_ck_n;
+  inout DDR_ck_p;
+  inout DDR_cke;
+  inout DDR_cs_n;
+  inout [3:0]DDR_dm;
+  inout [31:0]DDR_dq;
+  inout [3:0]DDR_dqs_n;
+  inout [3:0]DDR_dqs_p;
+  inout DDR_odt;
+  inout DDR_ras_n;
+  inout DDR_reset_n;
+  inout DDR_we_n;
+  inout FIXED_IO_ddr_vrn;
+  inout FIXED_IO_ddr_vrp;
+  inout [53:0]FIXED_IO_mio;
+  inout FIXED_IO_ps_clk;
+  inout FIXED_IO_ps_porb;
+  inout FIXED_IO_ps_srstb;
+  input [3:0]btns_4bits_tri_i;
+  input [3:0]leds_4bits_tri_i;
+  output [3:0]leds_4bits_tri_o;
+  output [3:0]leds_4bits_tri_t;
+  input [3:0]sws_4bits_tri_i;
+
+  wire [3:0]axi_gpio_0_GPIO2_TRI_I;
+  wire [3:0]axi_gpio_0_GPIO_TRI_I;
+  wire [3:0]axi_gpio_1_GPIO_TRI_I;
+  wire [3:0]axi_gpio_1_GPIO_TRI_O;
+  wire [3:0]axi_gpio_1_GPIO_TRI_T;
+  wire [14:0]processing_system7_0_DDR_ADDR;
+  wire [2:0]processing_system7_0_DDR_BA;
+  wire processing_system7_0_DDR_CAS_N;
+  wire processing_system7_0_DDR_CKE;
+  wire processing_system7_0_DDR_CK_N;
+  wire processing_system7_0_DDR_CK_P;
+  wire processing_system7_0_DDR_CS_N;
+  wire [3:0]processing_system7_0_DDR_DM;
+  wire [31:0]processing_system7_0_DDR_DQ;
+  wire [3:0]processing_system7_0_DDR_DQS_N;
+  wire [3:0]processing_system7_0_DDR_DQS_P;
+  wire processing_system7_0_DDR_ODT;
+  wire processing_system7_0_DDR_RAS_N;
+  wire processing_system7_0_DDR_RESET_N;
+  wire processing_system7_0_DDR_WE_N;
+  wire processing_system7_0_FCLK_CLK0;
+  wire processing_system7_0_FCLK_RESET0_N;
+  wire processing_system7_0_FIXED_IO_DDR_VRN;
+  wire processing_system7_0_FIXED_IO_DDR_VRP;
+  wire [53:0]processing_system7_0_FIXED_IO_MIO;
+  wire processing_system7_0_FIXED_IO_PS_CLK;
+  wire processing_system7_0_FIXED_IO_PS_PORB;
+  wire processing_system7_0_FIXED_IO_PS_SRSTB;
+  wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
+  wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
+  wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
+  wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
+  wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
+  wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
+  wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
+  wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
+  wire processing_system7_0_M_AXI_GP0_ARREADY;
+  wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
+  wire processing_system7_0_M_AXI_GP0_ARVALID;
+  wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
+  wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
+  wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
+  wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
+  wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
+  wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
+  wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
+  wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
+  wire processing_system7_0_M_AXI_GP0_AWREADY;
+  wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
+  wire processing_system7_0_M_AXI_GP0_AWVALID;
+  wire [11:0]processing_system7_0_M_AXI_GP0_BID;
+  wire processing_system7_0_M_AXI_GP0_BREADY;
+  wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
+  wire processing_system7_0_M_AXI_GP0_BVALID;
+  wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
+  wire [11:0]processing_system7_0_M_AXI_GP0_RID;
+  wire processing_system7_0_M_AXI_GP0_RLAST;
+  wire processing_system7_0_M_AXI_GP0_RREADY;
+  wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
+  wire processing_system7_0_M_AXI_GP0_RVALID;
+  wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
+  wire [11:0]processing_system7_0_M_AXI_GP0_WID;
+  wire processing_system7_0_M_AXI_GP0_WLAST;
+  wire processing_system7_0_M_AXI_GP0_WREADY;
+  wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
+  wire processing_system7_0_M_AXI_GP0_WVALID;
+  wire [31:0]ps7_0_axi_periph_M00_AXI_ARADDR;
+  wire ps7_0_axi_periph_M00_AXI_ARREADY;
+  wire [0:0]ps7_0_axi_periph_M00_AXI_ARVALID;
+  wire [31:0]ps7_0_axi_periph_M00_AXI_AWADDR;
+  wire ps7_0_axi_periph_M00_AXI_AWREADY;
+  wire [0:0]ps7_0_axi_periph_M00_AXI_AWVALID;
+  wire [0:0]ps7_0_axi_periph_M00_AXI_BREADY;
+  wire [1:0]ps7_0_axi_periph_M00_AXI_BRESP;
+  wire ps7_0_axi_periph_M00_AXI_BVALID;
+  wire [31:0]ps7_0_axi_periph_M00_AXI_RDATA;
+  wire [0:0]ps7_0_axi_periph_M00_AXI_RREADY;
+  wire [1:0]ps7_0_axi_periph_M00_AXI_RRESP;
+  wire ps7_0_axi_periph_M00_AXI_RVALID;
+  wire [31:0]ps7_0_axi_periph_M00_AXI_WDATA;
+  wire ps7_0_axi_periph_M00_AXI_WREADY;
+  wire [3:0]ps7_0_axi_periph_M00_AXI_WSTRB;
+  wire [0:0]ps7_0_axi_periph_M00_AXI_WVALID;
+  wire [31:0]ps7_0_axi_periph_M01_AXI_ARADDR;
+  wire ps7_0_axi_periph_M01_AXI_ARREADY;
+  wire [0:0]ps7_0_axi_periph_M01_AXI_ARVALID;
+  wire [31:0]ps7_0_axi_periph_M01_AXI_AWADDR;
+  wire ps7_0_axi_periph_M01_AXI_AWREADY;
+  wire [0:0]ps7_0_axi_periph_M01_AXI_AWVALID;
+  wire [0:0]ps7_0_axi_periph_M01_AXI_BREADY;
+  wire [1:0]ps7_0_axi_periph_M01_AXI_BRESP;
+  wire ps7_0_axi_periph_M01_AXI_BVALID;
+  wire [31:0]ps7_0_axi_periph_M01_AXI_RDATA;
+  wire [0:0]ps7_0_axi_periph_M01_AXI_RREADY;
+  wire [1:0]ps7_0_axi_periph_M01_AXI_RRESP;
+  wire ps7_0_axi_periph_M01_AXI_RVALID;
+  wire [31:0]ps7_0_axi_periph_M01_AXI_WDATA;
+  wire ps7_0_axi_periph_M01_AXI_WREADY;
+  wire [3:0]ps7_0_axi_periph_M01_AXI_WSTRB;
+  wire [0:0]ps7_0_axi_periph_M01_AXI_WVALID;
+  wire [0:0]rst_ps7_0_100M_interconnect_aresetn;
+  wire [0:0]rst_ps7_0_100M_peripheral_aresetn;
+
+  assign axi_gpio_0_GPIO2_TRI_I = sws_4bits_tri_i[3:0];
+  assign axi_gpio_0_GPIO_TRI_I = btns_4bits_tri_i[3:0];
+  assign axi_gpio_1_GPIO_TRI_I = leds_4bits_tri_i[3:0];
+  assign leds_4bits_tri_o[3:0] = axi_gpio_1_GPIO_TRI_O;
+  assign leds_4bits_tri_t[3:0] = axi_gpio_1_GPIO_TRI_T;
+  design_1_axi_gpio_0_0 axi_gpio_0
+       (.gpio2_io_i(axi_gpio_0_GPIO2_TRI_I),
+        .gpio_io_i(axi_gpio_0_GPIO_TRI_I),
+        .s_axi_aclk(processing_system7_0_FCLK_CLK0),
+        .s_axi_araddr(ps7_0_axi_periph_M00_AXI_ARADDR[8:0]),
+        .s_axi_aresetn(rst_ps7_0_100M_peripheral_aresetn),
+        .s_axi_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
+        .s_axi_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
+        .s_axi_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR[8:0]),
+        .s_axi_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
+        .s_axi_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
+        .s_axi_bready(ps7_0_axi_periph_M00_AXI_BREADY),
+        .s_axi_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
+        .s_axi_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
+        .s_axi_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
+        .s_axi_rready(ps7_0_axi_periph_M00_AXI_RREADY),
+        .s_axi_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
+        .s_axi_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
+        .s_axi_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
+        .s_axi_wready(ps7_0_axi_periph_M00_AXI_WREADY),
+        .s_axi_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
+        .s_axi_wvalid(ps7_0_axi_periph_M00_AXI_WVALID));
+  design_1_axi_gpio_1_0 axi_gpio_1
+       (.gpio_io_i(axi_gpio_1_GPIO_TRI_I),
+        .gpio_io_o(axi_gpio_1_GPIO_TRI_O),
+        .gpio_io_t(axi_gpio_1_GPIO_TRI_T),
+        .s_axi_aclk(processing_system7_0_FCLK_CLK0),
+        .s_axi_araddr(ps7_0_axi_periph_M01_AXI_ARADDR[8:0]),
+        .s_axi_aresetn(rst_ps7_0_100M_peripheral_aresetn),
+        .s_axi_arready(ps7_0_axi_periph_M01_AXI_ARREADY),
+        .s_axi_arvalid(ps7_0_axi_periph_M01_AXI_ARVALID),
+        .s_axi_awaddr(ps7_0_axi_periph_M01_AXI_AWADDR[8:0]),
+        .s_axi_awready(ps7_0_axi_periph_M01_AXI_AWREADY),
+        .s_axi_awvalid(ps7_0_axi_periph_M01_AXI_AWVALID),
+        .s_axi_bready(ps7_0_axi_periph_M01_AXI_BREADY),
+        .s_axi_bresp(ps7_0_axi_periph_M01_AXI_BRESP),
+        .s_axi_bvalid(ps7_0_axi_periph_M01_AXI_BVALID),
+        .s_axi_rdata(ps7_0_axi_periph_M01_AXI_RDATA),
+        .s_axi_rready(ps7_0_axi_periph_M01_AXI_RREADY),
+        .s_axi_rresp(ps7_0_axi_periph_M01_AXI_RRESP),
+        .s_axi_rvalid(ps7_0_axi_periph_M01_AXI_RVALID),
+        .s_axi_wdata(ps7_0_axi_periph_M01_AXI_WDATA),
+        .s_axi_wready(ps7_0_axi_periph_M01_AXI_WREADY),
+        .s_axi_wstrb(ps7_0_axi_periph_M01_AXI_WSTRB),
+        .s_axi_wvalid(ps7_0_axi_periph_M01_AXI_WVALID));
+  design_1_processing_system7_0_0 processing_system7_0
+       (.DDR_Addr(DDR_addr[14:0]),
+        .DDR_BankAddr(DDR_ba[2:0]),
+        .DDR_CAS_n(DDR_cas_n),
+        .DDR_CKE(DDR_cke),
+        .DDR_CS_n(DDR_cs_n),
+        .DDR_Clk(DDR_ck_p),
+        .DDR_Clk_n(DDR_ck_n),
+        .DDR_DM(DDR_dm[3:0]),
+        .DDR_DQ(DDR_dq[31:0]),
+        .DDR_DQS(DDR_dqs_p[3:0]),
+        .DDR_DQS_n(DDR_dqs_n[3:0]),
+        .DDR_DRSTB(DDR_reset_n),
+        .DDR_ODT(DDR_odt),
+        .DDR_RAS_n(DDR_ras_n),
+        .DDR_VRN(FIXED_IO_ddr_vrn),
+        .DDR_VRP(FIXED_IO_ddr_vrp),
+        .DDR_WEB(DDR_we_n),
+        .FCLK_CLK0(processing_system7_0_FCLK_CLK0),
+        .FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
+        .GPIO_I({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .MIO(FIXED_IO_mio[53:0]),
+        .M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
+        .M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
+        .PS_CLK(FIXED_IO_ps_clk),
+        .PS_PORB(FIXED_IO_ps_porb),
+        .PS_SRSTB(FIXED_IO_ps_srstb),
+        .SDIO0_WP(1\'b0),
+        .USB0_VBUS_PWRFAULT(1\'b0));
+  design_1_ps7_0_axi_periph_0 ps7_0_axi_periph
+       (.ACLK(processing_system7_0_FCLK_CLK0),
+        .ARESETN(rst_ps7_0_100M_interconnect_aresetn),
+        .M00_ACLK(processing_system7_0_FCLK_CLK0),
+        .M00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
+        .M00_AXI_araddr(ps7_0_axi_periph_M00_AXI_ARADDR),
+        .M00_AXI_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
+        .M00_AXI_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
+        .M00_AXI_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR),
+        .M00_AXI_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
+        .M00_AXI_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
+        .M00_AXI_bready(ps7_0_axi_periph_M00_AXI_BREADY),
+        .M00_AXI_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
+        .M00_AXI_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
+        .M00_AXI_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
+        .M00_AXI_rready(ps7_0_axi_periph_M00_AXI_RREADY),
+        .M00_AXI_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
+        .M00_AXI_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
+        .M00_AXI_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
+        .M00_AXI_wready(ps7_0_axi_periph_M00_AXI_WREADY),
+        .M00_AXI_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
+        .M00_AXI_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
+        .M01_ACLK(processing_system7_0_FCLK_CLK0),
+        .M01_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
+        .M01_AXI_araddr(ps7_0_axi_periph_M01_AXI_ARADDR),
+        .M01_AXI_arready(ps7_0_axi_periph_M01_AXI_ARREADY),
+        .M01_AXI_arvalid(ps7_0_axi_periph_M01_AXI_ARVALID),
+        .M01_AXI_awaddr(ps7_0_axi_periph_M01_AXI_AWADDR),
+        .M01_AXI_awready(ps7_0_axi_periph_M01_AXI_AWREADY),
+        .M01_AXI_awvalid(ps7_0_axi_periph_M01_AXI_AWVALID),
+        .M01_AXI_bready(ps7_0_axi_periph_M01_AXI_BREADY),
+        .M01_AXI_bresp(ps7_0_axi_periph_M01_AXI_BRESP),
+        .M01_AXI_bvalid(ps7_0_axi_periph_M01_AXI_BVALID),
+        .M01_AXI_rdata(ps7_0_axi_periph_M01_AXI_RDATA),
+        .M01_AXI_rready(ps7_0_axi_periph_M01_AXI_RREADY),
+        .M01_AXI_rresp(ps7_0_axi_periph_M01_AXI_RRESP),
+        .M01_AXI_rvalid(ps7_0_axi_periph_M01_AXI_RVALID),
+        .M01_AXI_wdata(ps7_0_axi_periph_M01_AXI_WDATA),
+        .M01_AXI_wready(ps7_0_axi_periph_M01_AXI_WREADY),
+        .M01_AXI_wstrb(ps7_0_axi_periph_M01_AXI_WSTRB),
+        .M01_AXI_wvalid(ps7_0_axi_periph_M01_AXI_WVALID),
+        .M02_ACLK(processing_system7_0_FCLK_CLK0),
+        .M02_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
+        .M02_AXI_arready(1\'b0),
+        .M02_AXI_awready(1\'b0),
+        .M02_AXI_bresp({1\'b0,1\'b0}),
+        .M02_AXI_bvalid(1\'b0),
+        .M02_AXI_rdata({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M02_AXI_rresp({1\'b0,1\'b0}),
+        .M02_AXI_rvalid(1\'b0),
+        .M02_AXI_wready(1\'b0),
+        .S00_ACLK(processing_system7_0_FCLK_CLK0),
+        .S00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
+        .S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
+        .S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
+        .S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
+        .S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
+        .S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
+        .S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
+        .S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
+        .S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
+        .S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
+        .S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
+        .S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
+        .S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
+        .S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
+        .S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
+        .S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
+        .S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
+        .S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
+        .S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
+        .S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
+        .S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
+        .S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
+        .S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
+        .S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
+        .S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
+        .S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
+        .S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
+        .S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
+        .S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
+        .S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
+        .S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
+        .S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
+        .S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
+        .S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
+        .S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
+        .S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
+        .S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
+        .S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
+        .S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
+  design_1_rst_ps7_0_100M_0 rst_ps7_0_100M
+       (.aux_reset_in(1\'b1),
+        .dcm_locked(1\'b1),
+        .ext_reset_in(processing_system7_0_FCLK_RESET0_N),
+        .interconnect_aresetn(rst_ps7_0_100M_interconnect_aresetn),
+        .mb_debug_sys_rst(1\'b0),
+        .peripheral_aresetn(rst_ps7_0_100M_peripheral_aresetn),
+        .slowest_sync_clk(processing_system7_0_FCLK_CLK0));
+endmodule
+
+module design_1_ps7_0_axi_periph_0
+   (ACLK,
+    ARESETN,
+    M00_ACLK,
+    M00_ARESETN,
+    M00_AXI_araddr,
+    M00_AXI_arready,
+    M00_AXI_arvalid,
+    M00_AXI_awaddr,
+    M00_AXI_awready,
+    M00_AXI_awvalid,
+    M00_AXI_bready,
+    M00_AXI_bresp,
+    M00_AXI_bvalid,
+    M00_AXI_rdata,
+    M00_AXI_rready,
+    M00_AXI_rresp,
+    M00_AXI_rvalid,
+    M00_AXI_wdata,
+    M00_AXI_wready,
+    M00_AXI_wstrb,
+    M00_AXI_wvalid,
+    M01_ACLK,
+    M01_ARESETN,
+    M01_AXI_araddr,
+    M01_AXI_arready,
+    M01_AXI_arvalid,
+    M01_AXI_awaddr,
+    M01_AXI_awready,
+    M01_AXI_awvalid,
+    M01_AXI_bready,
+    M01_AXI_bresp,
+    M01_AXI_bvalid,
+    M01_AXI_rdata,
+    M01_AXI_rready,
+    M01_AXI_rresp,
+    M01_AXI_rvalid,
+    M01_AXI_wdata,
+    M01_AXI_wready,
+    M01_AXI_wstrb,
+    M01_AXI_wvalid,
+    M02_ACLK,
+    M02_ARESETN,
+    M02_AXI_araddr,
+    M02_AXI_arready,
+    M02_AXI_arvalid,
+    M02_AXI_awaddr,
+    M02_AXI_awready,
+    M02_AXI_awvalid,
+    M02_AXI_bready,
+    M02_AXI_bresp,
+    M02_AXI_bvalid,
+    M02_AXI_rdata,
+    M02_AXI_rready,
+    M02_AXI_rresp,
+    M02_AXI_rvalid,
+    M02_AXI_wdata,
+    M02_AXI_wready,
+    M02_AXI_wstrb,
+    M02_AXI_wvalid,
+    S00_ACLK,
+    S00_ARESETN,
+    S00_AXI_araddr,
+    S00_AXI_arburst,
+    S00_AXI_arcache,
+    S00_AXI_arid,
+    S00_AXI_arlen,
+    S00_AXI_arlock,
+    S00_AXI_arprot,
+    S00_AXI_arqos,
+    S00_AXI_arready,
+    S00_AXI_arsize,
+    S00_AXI_arvalid,
+    S00_AXI_awaddr,
+    S00_AXI_awburst,
+    S00_AXI_awcache,
+    S00_AXI_awid,
+    S00_AXI_awlen,
+    S00_AXI_awlock,
+    S00_AXI_awprot,
+    S00_AXI_awqos,
+    S00_AXI_awready,
+    S00_AXI_awsize,
+    S00_AXI_awvalid,
+    S00_AXI_bid,
+    S00_AXI_bready,
+    S00_AXI_bresp,
+    S00_AXI_bvalid,
+    S00_AXI_rdata,
+    S00_AXI_rid,
+    S00_AXI_rlast,
+    S00_AXI_rready,
+    S00_AXI_rresp,
+    S00_AXI_rvalid,
+    S00_AXI_wdata,
+    S00_AXI_wid,
+    S00_AXI_wlast,
+    S00_AXI_wready,
+    S00_AXI_wstrb,
+    S00_AXI_wvalid);
+  input ACLK;
+  input ARESETN;
+  input M00_ACLK;
+  input M00_ARESETN;
+  output [31:0]M00_AXI_araddr;
+  input [0:0]M00_AXI_arready;
+  output [0:0]M00_AXI_arvalid;
+  output [31:0]M00_AXI_awaddr;
+  input [0:0]M00_AXI_awready;
+  output [0:0]M00_AXI_awvalid;
+  output [0:0]M00_AXI_bready;
+  input [1:0]M00_AXI_bresp;
+  input [0:0]M00_AXI_bvalid;
+  input [31:0]M00_AXI_rdata;
+  output [0:0]M00_AXI_rready;
+  input [1:0]M00_AXI_rresp;
+  input [0:0]M00_AXI_rvalid;
+  output [31:0]M00_AXI_wdata;
+  input [0:0]M00_AXI_wready;
+  output [3:0]M00_AXI_wstrb;
+  output [0:0]M00_AXI_wvalid;
+  input M01_ACLK;
+  input M01_ARESETN;
+  output [31:0]M01_AXI_araddr;
+  input [0:0]M01_AXI_arready;
+  output [0:0]M01_AXI_arvalid;
+  output [31:0]M01_AXI_awaddr;
+  input [0:0]M01_AXI_awready;
+  output [0:0]M01_AXI_awvalid;
+  output [0:0]M01_AXI_bready;
+  input [1:0]M01_AXI_bresp;
+  input [0:0]M01_AXI_bvalid;
+  input [31:0]M01_AXI_rdata;
+  output [0:0]M01_AXI_rready;
+  input [1:0]M01_AXI_rresp;
+  input [0:0]M01_AXI_rvalid;
+  output [31:0]M01_AXI_wdata;
+  input [0:0]M01_AXI_wready;
+  output [3:0]M01_AXI_wstrb;
+  output [0:0]M01_AXI_wvalid;
+  input M02_ACLK;
+  input M02_ARESETN;
+  output [31:0]M02_AXI_araddr;
+  input M02_AXI_arready;
+  output M02_AXI_arvalid;
+  output [31:0]M02_AXI_awaddr;
+  input M02_AXI_awready;
+  output M02_AXI_awvalid;
+  output M02_AXI_bready;
+  input [1:0]M02_AXI_bresp;
+  input M02_AXI_bvalid;
+  input [31:0]M02_AXI_rdata;
+  output M02_AXI_rready;
+  input [1:0]M02_AXI_rresp;
+  input M02_AXI_rvalid;
+  output [31:0]M02_AXI_wdata;
+  input M02_AXI_wready;
+  output [3:0]M02_AXI_wstrb;
+  output M02_AXI_wvalid;
+  input S00_ACLK;
+  input S00_ARESETN;
+  input [31:0]S00_AXI_araddr;
+  input [1:0]S00_AXI_arburst;
+  input [3:0]S00_AXI_arcache;
+  input [11:0]S00_AXI_arid;
+  input [3:0]S00_AXI_arlen;
+  input [1:0]S00_AXI_arlock;
+  input [2:0]S00_AXI_arprot;
+  input [3:0]S00_AXI_arqos;
+  output S00_AXI_arready;
+  input [2:0]S00_AXI_arsize;
+  input S00_AXI_arvalid;
+  input [31:0]S00_AXI_awaddr;
+  input [1:0]S00_AXI_awburst;
+  input [3:0]S00_AXI_awcache;
+  input [11:0]S00_AXI_awid;
+  input [3:0]S00_AXI_awlen;
+  input [1:0]S00_AXI_awlock;
+  input [2:0]S00_AXI_awprot;
+  input [3:0]S00_AXI_awqos;
+  output S00_AXI_awready;
+  input [2:0]S00_AXI_awsize;
+  input S00_AXI_awvalid;
+  output [11:0]S00_AXI_bid;
+  input S00_AXI_bready;
+  output [1:0]S00_AXI_bresp;
+  output S00_AXI_bvalid;
+  output [31:0]S00_AXI_rdata;
+  output [11:0]S00_AXI_rid;
+  output S00_AXI_rlast;
+  input S00_AXI_rready;
+  output [1:0]S00_AXI_rresp;
+  output S00_AXI_rvalid;
+  input [31:0]S00_AXI_wdata;
+  input [11:0]S00_AXI_wid;
+  input S00_AXI_wlast;
+  output S00_AXI_wready;
+  input [3:0]S00_AXI_wstrb;
+  input S00_AXI_wvalid;
+
+  wire M00_ACLK_1;
+  wire M00_ARESETN_1;
+  wire M01_ACLK_1;
+  wire M01_ARESETN_1;
+  wire M02_ACLK_1;
+  wire M02_ARESETN_1;
+  wire S00_ACLK_1;
+  wire S00_ARESETN_1;
+  wire [31:0]m00_couplers_to_ps7_0_axi_periph_ARADDR;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_ARREADY;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_ARVALID;
+  wire [31:0]m00_couplers_to_ps7_0_axi_periph_AWADDR;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_AWREADY;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_AWVALID;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_BREADY;
+  wire [1:0]m00_couplers_to_ps7_0_axi_periph_BRESP;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_BVALID;
+  wire [31:0]m00_couplers_to_ps7_0_axi_periph_RDATA;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_RREADY;
+  wire [1:0]m00_couplers_to_ps7_0_axi_periph_RRESP;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_RVALID;
+  wire [31:0]m00_couplers_to_ps7_0_axi_periph_WDATA;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_WREADY;
+  wire [3:0]m00_couplers_to_ps7_0_axi_periph_WSTRB;
+  wire [0:0]m00_couplers_to_ps7_0_axi_periph_WVALID;
+  wire [31:0]m01_couplers_to_ps7_0_axi_periph_ARADDR;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_ARREADY;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_ARVALID;
+  wire [31:0]m01_couplers_to_ps7_0_axi_periph_AWADDR;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_AWREADY;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_AWVALID;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_BREADY;
+  wire [1:0]m01_couplers_to_ps7_0_axi_periph_BRESP;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_BVALID;
+  wire [31:0]m01_couplers_to_ps7_0_axi_periph_RDATA;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_RREADY;
+  wire [1:0]m01_couplers_to_ps7_0_axi_periph_RRESP;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_RVALID;
+  wire [31:0]m01_couplers_to_ps7_0_axi_periph_WDATA;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_WREADY;
+  wire [3:0]m01_couplers_to_ps7_0_axi_periph_WSTRB;
+  wire [0:0]m01_couplers_to_ps7_0_axi_periph_WVALID;
+  wire m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  wire m02_couplers_to_ps7_0_axi_periph_ARREADY;
+  wire m02_couplers_to_ps7_0_axi_periph_ARVALID;
+  wire m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  wire m02_couplers_to_ps7_0_axi_periph_AWREADY;
+  wire m02_couplers_to_ps7_0_axi_periph_AWVALID;
+  wire m02_couplers_to_ps7_0_axi_periph_BREADY;
+  wire [1:0]m02_couplers_to_ps7_0_axi_periph_BRESP;
+  wire m02_couplers_to_ps7_0_axi_periph_BVALID;
+  wire [31:0]m02_couplers_to_ps7_0_axi_periph_RDATA;
+  wire m02_couplers_to_ps7_0_axi_periph_RREADY;
+  wire [1:0]m02_couplers_to_ps7_0_axi_periph_RRESP;
+  wire m02_couplers_to_ps7_0_axi_periph_RVALID;
+  wire m02_couplers_to_ps7_0_axi_periph_WDATA;
+  wire m02_couplers_to_ps7_0_axi_periph_WREADY;
+  wire m02_couplers_to_ps7_0_axi_periph_WSTRB;
+  wire m02_couplers_to_ps7_0_axi_periph_WVALID;
+  wire ps7_0_axi_periph_ACLK_net;
+  wire ps7_0_axi_periph_ARESETN_net;
+  wire [31:0]ps7_0_axi_periph_to_s00_couplers_ARADDR;
+  wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARBURST;
+  wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARCACHE;
+  wire [11:0]ps7_0_axi_periph_to_s00_couplers_ARID;
+  wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARLEN;
+  wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARLOCK;
+  wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARPROT;
+  wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARQOS;
+  wire ps7_0_axi_periph_to_s00_couplers_ARREADY;
+  wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARSIZE;
+  wire ps7_0_axi_periph_to_s00_couplers_ARVALID;
+  wire [31:0]ps7_0_axi_periph_to_s00_couplers_AWADDR;
+  wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWBURST;
+  wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWCACHE;
+  wire [11:0]ps7_0_axi_periph_to_s00_couplers_AWID;
+  wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWLEN;
+  wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWLOCK;
+  wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWPROT;
+  wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWQOS;
+  wire ps7_0_axi_periph_to_s00_couplers_AWREADY;
+  wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWSIZE;
+  wire ps7_0_axi_periph_to_s00_couplers_AWVALID;
+  wire [11:0]ps7_0_axi_periph_to_s00_couplers_BID;
+  wire ps7_0_axi_periph_to_s00_couplers_BREADY;
+  wire [1:0]ps7_0_axi_periph_to_s00_couplers_BRESP;
+  wire ps7_0_axi_periph_to_s00_couplers_BVALID;
+  wire [31:0]ps7_0_axi_periph_to_s00_couplers_RDATA;
+  wire [11:0]ps7_0_axi_periph_to_s00_couplers_RID;
+  wire ps7_0_axi_periph_to_s00_couplers_RLAST;
+  wire ps7_0_axi_periph_to_s00_couplers_RREADY;
+  wire [1:0]ps7_0_axi_periph_to_s00_couplers_RRESP;
+  wire ps7_0_axi_periph_to_s00_couplers_RVALID;
+  wire [31:0]ps7_0_axi_periph_to_s00_couplers_WDATA;
+  wire [11:0]ps7_0_axi_periph_to_s00_couplers_WID;
+  wire ps7_0_axi_periph_to_s00_couplers_WLAST;
+  wire ps7_0_axi_periph_to_s00_couplers_WREADY;
+  wire [3:0]ps7_0_axi_periph_to_s00_couplers_WSTRB;
+  wire ps7_0_axi_periph_to_s00_couplers_WVALID;
+  wire [31:0]s00_couplers_to_xbar_ARADDR;
+  wire [2:0]s00_couplers_to_xbar_ARPROT;
+  wire [0:0]s00_couplers_to_xbar_ARREADY;
+  wire s00_couplers_to_xbar_ARVALID;
+  wire [31:0]s00_couplers_to_xbar_AWADDR;
+  wire [2:0]s00_couplers_to_xbar_AWPROT;
+  wire [0:0]s00_couplers_to_xbar_AWREADY;
+  wire s00_couplers_to_xbar_AWVALID;
+  wire s00_couplers_to_xbar_BREADY;
+  wire [1:0]s00_couplers_to_xbar_BRESP;
+  wire [0:0]s00_couplers_to_xbar_BVALID;
+  wire [31:0]s00_couplers_to_xbar_RDATA;
+  wire s00_couplers_to_xbar_RREADY;
+  wire [1:0]s00_couplers_to_xbar_RRESP;
+  wire [0:0]s00_couplers_to_xbar_RVALID;
+  wire [31:0]s00_couplers_to_xbar_WDATA;
+  wire [0:0]s00_couplers_to_xbar_WREADY;
+  wire [3:0]s00_couplers_to_xbar_WSTRB;
+  wire s00_couplers_to_xbar_WVALID;
+  wire [31:0]xbar_to_m00_couplers_ARADDR;
+  wire [0:0]xbar_to_m00_couplers_ARREADY;
+  wire [0:0]xbar_to_m00_couplers_ARVALID;
+  wire [31:0]xbar_to_m00_couplers_AWADDR;
+  wire [0:0]xbar_to_m00_couplers_AWREADY;
+  wire [0:0]xbar_to_m00_couplers_AWVALID;
+  wire [0:0]xbar_to_m00_couplers_BREADY;
+  wire [1:0]xbar_to_m00_couplers_BRESP;
+  wire [0:0]xbar_to_m00_couplers_BVALID;
+  wire [31:0]xbar_to_m00_couplers_RDATA;
+  wire [0:0]xbar_to_m00_couplers_RREADY;
+  wire [1:0]xbar_to_m00_couplers_RRESP;
+  wire [0:0]xbar_to_m00_couplers_RVALID;
+  wire [31:0]xbar_to_m00_couplers_WDATA;
+  wire [0:0]xbar_to_m00_couplers_WREADY;
+  wire [3:0]xbar_to_m00_couplers_WSTRB;
+  wire [0:0]xbar_to_m00_couplers_WVALID;
+  wire [63:32]xbar_to_m01_couplers_ARADDR;
+  wire [0:0]xbar_to_m01_couplers_ARREADY;
+  wire [1:1]xbar_to_m01_couplers_ARVALID;
+  wire [63:32]xbar_to_m01_couplers_AWADDR;
+  wire [0:0]xbar_to_m01_couplers_AWREADY;
+  wire [1:1]xbar_to_m01_couplers_AWVALID;
+  wire [1:1]xbar_to_m01_couplers_BREADY;
+  wire [1:0]xbar_to_m01_couplers_BRESP;
+  wire [0:0]xbar_to_m01_couplers_BVALID;
+  wire [31:0]xbar_to_m01_couplers_RDATA;
+  wire [1:1]xbar_to_m01_couplers_RREADY;
+  wire [1:0]xbar_to_m01_couplers_RRESP;
+  wire [0:0]xbar_to_m01_couplers_RVALID;
+  wire [63:32]xbar_to_m01_couplers_WDATA;
+  wire [0:0]xbar_to_m01_couplers_WREADY;
+  wire [7:4]xbar_to_m01_couplers_WSTRB;
+  wire [1:1]xbar_to_m01_couplers_WVALID;
+  wire [95:64]xbar_to_m02_couplers_ARADDR;
+  wire xbar_to_m02_couplers_ARREADY;
+  wire [2:2]xbar_to_m02_couplers_ARVALID;
+  wire [95:64]xbar_to_m02_couplers_AWADDR;
+  wire xbar_to_m02_couplers_AWREADY;
+  wire [2:2]xbar_to_m02_couplers_AWVALID;
+  wire [2:2]xbar_to_m02_couplers_BREADY;
+  wire xbar_to_m02_couplers_BRESP;
+  wire xbar_to_m02_couplers_BVALID;
+  wire xbar_to_m02_couplers_RDATA;
+  wire [2:2]xbar_to_m02_couplers_RREADY;
+  wire xbar_to_m02_couplers_RRESP;
+  wire xbar_to_m02_couplers_RVALID;
+  wire [95:64]xbar_to_m02_couplers_WDATA;
+  wire xbar_to_m02_couplers_WREADY;
+  wire [11:8]xbar_to_m02_couplers_WSTRB;
+  wire [2:2]xbar_to_m02_couplers_WVALID;
+
+  assign M00_ACLK_1 = M00_ACLK;
+  assign M00_ARESETN_1 = M00_ARESETN;
+  assign M00_AXI_araddr[31:0] = m00_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M00_AXI_arvalid[0] = m00_couplers_to_ps7_0_axi_periph_ARVALID;
+  assign M00_AXI_awaddr[31:0] = m00_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M00_AXI_awvalid[0] = m00_couplers_to_ps7_0_axi_periph_AWVALID;
+  assign M00_AXI_bready[0] = m00_couplers_to_ps7_0_axi_periph_BREADY;
+  assign M00_AXI_rready[0] = m00_couplers_to_ps7_0_axi_periph_RREADY;
+  assign M00_AXI_wdata[31:0] = m00_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M00_AXI_wstrb[3:0] = m00_couplers_to_ps7_0_axi_periph_WSTRB;
+  assign M00_AXI_wvalid[0] = m00_couplers_to_ps7_0_axi_periph_WVALID;
+  assign M01_ACLK_1 = M01_ACLK;
+  assign M01_ARESETN_1 = M01_ARESETN;
+  assign M01_AXI_araddr[31:0] = m01_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M01_AXI_arvalid[0] = m01_couplers_to_ps7_0_axi_periph_ARVALID;
+  assign M01_AXI_awaddr[31:0] = m01_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M01_AXI_awvalid[0] = m01_couplers_to_ps7_0_axi_periph_AWVALID;
+  assign M01_AXI_bready[0] = m01_couplers_to_ps7_0_axi_periph_BREADY;
+  assign M01_AXI_rready[0] = m01_couplers_to_ps7_0_axi_periph_RREADY;
+  assign M01_AXI_wdata[31:0] = m01_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M01_AXI_wstrb[3:0] = m01_couplers_to_ps7_0_axi_periph_WSTRB;
+  assign M01_AXI_wvalid[0] = m01_couplers_to_ps7_0_axi_periph_WVALID;
+  assign M02_ACLK_1 = M02_ACLK;
+  assign M02_ARESETN_1 = M02_ARESETN;
+  assign M02_AXI_araddr[31] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[30] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[29] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[28] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[27] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[26] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[25] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[24] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[23] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[22] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[21] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[20] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[19] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[18] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[17] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[16] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[15] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[14] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[13] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[12] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[11] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[10] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[9] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[8] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[7] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[6] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[5] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[4] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[3] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[2] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[1] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_araddr[0] = m02_couplers_to_ps7_0_axi_periph_ARADDR;
+  assign M02_AXI_arvalid = m02_couplers_to_ps7_0_axi_periph_ARVALID;
+  assign M02_AXI_awaddr[31] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[30] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[29] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[28] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[27] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[26] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[25] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[24] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[23] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[22] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[21] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[20] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[19] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[18] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[17] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[16] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[15] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[14] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[13] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[12] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[11] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[10] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[9] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[8] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[7] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[6] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[5] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[4] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[3] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[2] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[1] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awaddr[0] = m02_couplers_to_ps7_0_axi_periph_AWADDR;
+  assign M02_AXI_awvalid = m02_couplers_to_ps7_0_axi_periph_AWVALID;
+  assign M02_AXI_bready = m02_couplers_to_ps7_0_axi_periph_BREADY;
+  assign M02_AXI_rready = m02_couplers_to_ps7_0_axi_periph_RREADY;
+  assign M02_AXI_wdata[31] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[30] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[29] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[28] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[27] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[26] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[25] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[24] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[23] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[22] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[21] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[20] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[19] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[18] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[17] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[16] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[15] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[14] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[13] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[12] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[11] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[10] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[9] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[8] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[7] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[6] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[5] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[4] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[3] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[2] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[1] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wdata[0] = m02_couplers_to_ps7_0_axi_periph_WDATA;
+  assign M02_AXI_wstrb[3] = m02_couplers_to_ps7_0_axi_periph_WSTRB;
+  assign M02_AXI_wstrb[2] = m02_couplers_to_ps7_0_axi_periph_WSTRB;
+  assign M02_AXI_wstrb[1] = m02_couplers_to_ps7_0_axi_periph_WSTRB;
+  assign M02_AXI_wstrb[0] = m02_couplers_to_ps7_0_axi_periph_WSTRB;
+  assign M02_AXI_wvalid = m02_couplers_to_ps7_0_axi_periph_WVALID;
+  assign S00_ACLK_1 = S00_ACLK;
+  assign S00_ARESETN_1 = S00_ARESETN;
+  assign S00_AXI_arready = ps7_0_axi_periph_to_s00_couplers_ARREADY;
+  assign S00_AXI_awready = ps7_0_axi_periph_to_s00_couplers_AWREADY;
+  assign S00_AXI_bid[11:0] = ps7_0_axi_periph_to_s00_couplers_BID;
+  assign S00_AXI_bresp[1:0] = ps7_0_axi_periph_to_s00_couplers_BRESP;
+  assign S00_AXI_bvalid = ps7_0_axi_periph_to_s00_couplers_BVALID;
+  assign S00_AXI_rdata[31:0] = ps7_0_axi_periph_to_s00_couplers_RDATA;
+  assign S00_AXI_rid[11:0] = ps7_0_axi_periph_to_s00_couplers_RID;
+  assign S00_AXI_rlast = ps7_0_axi_periph_to_s00_couplers_RLAST;
+  assign S00_AXI_rresp[1:0] = ps7_0_axi_periph_to_s00_couplers_RRESP;
+  assign S00_AXI_rvalid = ps7_0_axi_periph_to_s00_couplers_RVALID;
+  assign S00_AXI_wready = ps7_0_axi_periph_to_s00_couplers_WREADY;
+  assign m00_couplers_to_ps7_0_axi_periph_ARREADY = M00_AXI_arready[0];
+  assign m00_couplers_to_ps7_0_axi_periph_AWREADY = M00_AXI_awready[0];
+  assign m00_couplers_to_ps7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
+  assign m00_couplers_to_ps7_0_axi_periph_BVALID = M00_AXI_bvalid[0];
+  assign m00_couplers_to_ps7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
+  assign m00_couplers_to_ps7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
+  assign m00_couplers_to_ps7_0_axi_periph_RVALID = M00_AXI_rvalid[0];
+  assign m00_couplers_to_ps7_0_axi_periph_WREADY = M00_AXI_wready[0];
+  assign m01_couplers_to_ps7_0_axi_periph_ARREADY = M01_AXI_arready[0];
+  assign m01_couplers_to_ps7_0_axi_periph_AWREADY = M01_AXI_awready[0];
+  assign m01_couplers_to_ps7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
+  assign m01_couplers_to_ps7_0_axi_periph_BVALID = M01_AXI_bvalid[0];
+  assign m01_couplers_to_ps7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
+  assign m01_couplers_to_ps7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
+  assign m01_couplers_to_ps7_0_axi_periph_RVALID = M01_AXI_rvalid[0];
+  assign m01_couplers_to_ps7_0_axi_periph_WREADY = M01_AXI_wready[0];
+  assign m02_couplers_to_ps7_0_axi_periph_ARREADY = M02_AXI_arready;
+  assign m02_couplers_to_ps7_0_axi_periph_AWREADY = M02_AXI_awready;
+  assign m02_couplers_to_ps7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
+  assign m02_couplers_to_ps7_0_axi_periph_BVALID = M02_AXI_bvalid;
+  assign m02_couplers_to_ps7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
+  assign m02_couplers_to_ps7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
+  assign m02_couplers_to_ps7_0_axi_periph_RVALID = M02_AXI_rvalid;
+  assign m02_couplers_to_ps7_0_axi_periph_WREADY = M02_AXI_wready;
+  assign ps7_0_axi_periph_ACLK_net = ACLK;
+  assign ps7_0_axi_periph_ARESETN_net = ARESETN;
+  assign ps7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
+  assign ps7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
+  assign ps7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
+  assign ps7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
+  assign ps7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
+  assign ps7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
+  assign ps7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
+  assign ps7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
+  assign ps7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
+  assign ps7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
+  assign ps7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
+  m00_couplers_imp_15SPJYW m00_couplers
+       (.M_ACLK(M00_ACLK_1),
+        .M_ARESETN(M00_ARESETN_1),
+        .M_AXI_araddr(m00_couplers_to_ps7_0_axi_periph_ARADDR),
+        .M_AXI_arready(m00_couplers_to_ps7_0_axi_periph_ARREADY),
+        .M_AXI_arvalid(m00_couplers_to_ps7_0_axi_periph_ARVALID),
+        .M_AXI_awaddr(m00_couplers_to_ps7_0_axi_periph_AWADDR),
+        .M_AXI_awready(m00_couplers_to_ps7_0_axi_periph_AWREADY),
+        .M_AXI_awvalid(m00_couplers_to_ps7_0_axi_periph_AWVALID),
+        .M_AXI_bready(m00_couplers_to_ps7_0_axi_periph_BREADY),
+        .M_AXI_bresp(m00_couplers_to_ps7_0_axi_periph_BRESP),
+        .M_AXI_bvalid(m00_couplers_to_ps7_0_axi_periph_BVALID),
+        .M_AXI_rdata(m00_couplers_to_ps7_0_axi_periph_RDATA),
+        .M_AXI_rready(m00_couplers_to_ps7_0_axi_periph_RREADY),
+        .M_AXI_rresp(m00_couplers_to_ps7_0_axi_periph_RRESP),
+        .M_AXI_rvalid(m00_couplers_to_ps7_0_axi_periph_RVALID),
+        .M_AXI_wdata(m00_couplers_to_ps7_0_axi_periph_WDATA),
+        .M_AXI_wready(m00_couplers_to_ps7_0_axi_periph_WREADY),
+        .M_AXI_wstrb(m00_couplers_to_ps7_0_axi_periph_WSTRB),
+        .M_AXI_wvalid(m00_couplers_to_ps7_0_axi_periph_WVALID),
+        .S_ACLK(ps7_0_axi_periph_ACLK_net),
+        .S_ARESETN(ps7_0_axi_periph_ARESETN_net),
+        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
+        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),
+        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
+        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
+        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),
+        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
+        .S_AXI_bready(xbar_to_m00_couplers_BREADY),
+        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),
+        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
+        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),
+        .S_AXI_rready(xbar_to_m00_couplers_RREADY),
+        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),
+        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
+        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),
+        .S_AXI_wready(xbar_to_m00_couplers_WREADY),
+        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
+        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
+  m01_couplers_imp_XU9C55 m01_couplers
+       (.M_ACLK(M01_ACLK_1),
+        .M_ARESETN(M01_ARESETN_1),
+        .M_AXI_araddr(m01_couplers_to_ps7_0_axi_periph_ARADDR),
+        .M_AXI_arready(m01_couplers_to_ps7_0_axi_periph_ARREADY),
+        .M_AXI_arvalid(m01_couplers_to_ps7_0_axi_periph_ARVALID),
+        .M_AXI_awaddr(m01_couplers_to_ps7_0_axi_periph_AWADDR),
+        .M_AXI_awready(m01_couplers_to_ps7_0_axi_periph_AWREADY),
+        .M_AXI_awvalid(m01_couplers_to_ps7_0_axi_periph_AWVALID),
+        .M_AXI_bready(m01_couplers_to_ps7_0_axi_periph_BREADY),
+        .M_AXI_bresp(m01_couplers_to_ps7_0_axi_periph_BRESP),
+        .M_AXI_bvalid(m01_couplers_to_ps7_0_axi_periph_BVALID),
+        .M_AXI_rdata(m01_couplers_to_ps7_0_axi_periph_RDATA),
+        .M_AXI_rready(m01_couplers_to_ps7_0_axi_periph_RREADY),
+        .M_AXI_rresp(m01_couplers_to_ps7_0_axi_periph_RRESP),
+        .M_AXI_rvalid(m01_couplers_to_ps7_0_axi_periph_RVALID),
+        .M_AXI_wdata(m01_couplers_to_ps7_0_axi_periph_WDATA),
+        .M_AXI_wready(m01_couplers_to_ps7_0_axi_periph_WREADY),
+        .M_AXI_wstrb(m01_couplers_to_ps7_0_axi_periph_WSTRB),
+        .M_AXI_wvalid(m01_couplers_to_ps7_0_axi_periph_WVALID),
+        .S_ACLK(ps7_0_axi_periph_ACLK_net),
+        .S_ARESETN(ps7_0_axi_periph_ARESETN_net),
+        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
+        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),
+        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
+        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
+        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),
+        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
+        .S_AXI_bready(xbar_to_m01_couplers_BREADY),
+        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),
+        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
+        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),
+        .S_AXI_rready(xbar_to_m01_couplers_RREADY),
+        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),
+        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
+        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),
+        .S_AXI_wready(xbar_to_m01_couplers_WREADY),
+        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
+        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
+  m02_couplers_imp_14WQB4R m02_couplers
+       (.M_ACLK(M02_ACLK_1),
+        .M_ARESETN(M02_ARESETN_1),
+        .M_AXI_araddr(m02_couplers_to_ps7_0_axi_periph_ARADDR),
+        .M_AXI_arready(m02_couplers_to_ps7_0_axi_periph_ARREADY),
+        .M_AXI_arvalid(m02_couplers_to_ps7_0_axi_periph_ARVALID),
+        .M_AXI_awaddr(m02_couplers_to_ps7_0_axi_periph_AWADDR),
+        .M_AXI_awready(m02_couplers_to_ps7_0_axi_periph_AWREADY),
+        .M_AXI_awvalid(m02_couplers_to_ps7_0_axi_periph_AWVALID),
+        .M_AXI_bready(m02_couplers_to_ps7_0_axi_periph_BREADY),
+        .M_AXI_bresp(m02_couplers_to_ps7_0_axi_periph_BRESP[0]),
+        .M_AXI_bvalid(m02_couplers_to_ps7_0_axi_periph_BVALID),
+        .M_AXI_rdata(m02_couplers_to_ps7_0_axi_periph_RDATA[0]),
+        .M_AXI_rready(m02_couplers_to_ps7_0_axi_periph_RREADY),
+        .M_AXI_rresp(m02_couplers_to_ps7_0_axi_periph_RRESP[0]),
+        .M_AXI_rvalid(m02_couplers_to_ps7_0_axi_periph_RVALID),
+        .M_AXI_wdata(m02_couplers_to_ps7_0_axi_periph_WDATA),
+        .M_AXI_wready(m02_couplers_to_ps7_0_axi_periph_WREADY),
+        .M_AXI_wstrb(m02_couplers_to_ps7_0_axi_periph_WSTRB),
+        .M_AXI_wvalid(m02_couplers_to_ps7_0_axi_periph_WVALID),
+        .S_ACLK(ps7_0_axi_periph_ACLK_net),
+        .S_ARESETN(ps7_0_axi_periph_ARESETN_net),
+        .S_AXI_araddr(xbar_to_m02_couplers_ARADDR[64]),
+        .S_AXI_arready(xbar_to_m02_couplers_ARREADY),
+        .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
+        .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[64]),
+        .S_AXI_awready(xbar_to_m02_couplers_AWREADY),
+        .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
+        .S_AXI_bready(xbar_to_m02_couplers_BREADY),
+        .S_AXI_bresp(xbar_to_m02_couplers_BRESP),
+        .S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
+        .S_AXI_rdata(xbar_to_m02_couplers_RDATA),
+        .S_AXI_rready(xbar_to_m02_couplers_RREADY),
+        .S_AXI_rresp(xbar_to_m02_couplers_RRESP),
+        .S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
+        .S_AXI_wdata(xbar_to_m02_couplers_WDATA[64]),
+        .S_AXI_wready(xbar_to_m02_couplers_WREADY),
+        .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB[8]),
+        .S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
+  s00_couplers_imp_UYSKKA s00_couplers
+       (.M_ACLK(ps7_0_axi_periph_ACLK_net),
+        .M_ARESETN(ps7_0_axi_periph_ARESETN_net),
+        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
+        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
+        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),
+        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
+        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
+        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
+        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),
+        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
+        .M_AXI_bready(s00_couplers_to_xbar_BREADY),
+        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),
+        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
+        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),
+        .M_AXI_rready(s00_couplers_to_xbar_RREADY),
+        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),
+        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
+        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),
+        .M_AXI_wready(s00_couplers_to_xbar_WREADY),
+        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
+        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
+        .S_ACLK(S00_ACLK_1),
+        .S_ARESETN(S00_ARESETN_1),
+        .S_AXI_araddr(ps7_0_axi_periph_to_s00_couplers_ARADDR),
+        .S_AXI_arburst(ps7_0_axi_periph_to_s00_couplers_ARBURST),
+        .S_AXI_arcache(ps7_0_axi_periph_to_s00_couplers_ARCACHE),
+        .S_AXI_arid(ps7_0_axi_periph_to_s00_couplers_ARID),
+        .S_AXI_arlen(ps7_0_axi_periph_to_s00_couplers_ARLEN),
+        .S_AXI_arlock(ps7_0_axi_periph_to_s00_couplers_ARLOCK),
+        .S_AXI_arprot(ps7_0_axi_periph_to_s00_couplers_ARPROT),
+        .S_AXI_arqos(ps7_0_axi_periph_to_s00_couplers_ARQOS),
+        .S_AXI_arready(ps7_0_axi_periph_to_s00_couplers_ARREADY),
+        .S_AXI_arsize(ps7_0_axi_periph_to_s00_couplers_ARSIZE),
+        .S_AXI_arvalid(ps7_0_axi_periph_to_s00_couplers_ARVALID),
+        .S_AXI_awaddr(ps7_0_axi_periph_to_s00_couplers_AWADDR),
+        .S_AXI_awburst(ps7_0_axi_periph_to_s00_couplers_AWBURST),
+        .S_AXI_awcache(ps7_0_axi_periph_to_s00_couplers_AWCACHE),
+        .S_AXI_awid(ps7_0_axi_periph_to_s00_couplers_AWID),
+        .S_AXI_awlen(ps7_0_axi_periph_to_s00_couplers_AWLEN),
+        .S_AXI_awlock(ps7_0_axi_periph_to_s00_couplers_AWLOCK),
+        .S_AXI_awprot(ps7_0_axi_periph_to_s00_couplers_AWPROT),
+        .S_AXI_awqos(ps7_0_axi_periph_to_s00_couplers_AWQOS),
+        .S_AXI_awready(ps7_0_axi_periph_to_s00_couplers_AWREADY),
+        .S_AXI_awsize(ps7_0_axi_periph_to_s00_couplers_AWSIZE),
+        .S_AXI_awvalid(ps7_0_axi_periph_to_s00_couplers_AWVALID),
+        .S_AXI_bid(ps7_0_axi_periph_to_s00_couplers_BID),
+        .S_AXI_bready(ps7_0_axi_periph_to_s00_couplers_BREADY),
+        .S_AXI_bresp(ps7_0_axi_periph_to_s00_couplers_BRESP),
+        .S_AXI_bvalid(ps7_0_axi_periph_to_s00_couplers_BVALID),
+        .S_AXI_rdata(ps7_0_axi_periph_to_s00_couplers_RDATA),
+        .S_AXI_rid(ps7_0_axi_periph_to_s00_couplers_RID),
+        .S_AXI_rlast(ps7_0_axi_periph_to_s00_couplers_RLAST),
+        .S_AXI_rready(ps7_0_axi_periph_to_s00_couplers_RREADY),
+        .S_AXI_rresp(ps7_0_axi_periph_to_s00_couplers_RRESP),
+        .S_AXI_rvalid(ps7_0_axi_periph_to_s00_couplers_RVALID),
+        .S_AXI_wdata(ps7_0_axi_periph_to_s00_couplers_WDATA),
+        .S_AXI_wid(ps7_0_axi_periph_to_s00_couplers_WID),
+        .S_AXI_wlast(ps7_0_axi_periph_to_s00_couplers_WLAST),
+        .S_AXI_wready(ps7_0_axi_periph_to_s00_couplers_WREADY),
+        .S_AXI_wstrb(ps7_0_axi_periph_to_s00_couplers_WSTRB),
+        .S_AXI_wvalid(ps7_0_axi_periph_to_s00_couplers_WVALID));
+  design_1_xbar_0 xbar
+       (.aclk(ps7_0_axi_periph_ACLK_net),
+        .aresetn(ps7_0_axi_periph_ARESETN_net),
+        .m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
+        .m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
+        .m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
+        .m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
+        .m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
+        .m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
+        .m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
+        .m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
+        .m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
+        .m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
+        .m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
+        .m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
+        .m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
+        .m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
+        .m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
+        .m_axi_wstrb({xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
+        .m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
+        .s_axi_araddr(s00_couplers_to_xbar_ARADDR),
+        .s_axi_arprot(s00_couplers_to_xbar_ARPROT),
+        .s_axi_arready(s00_couplers_to_xbar_ARREADY),
+        .s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
+        .s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
+        .s_axi_awprot(s00_couplers_to_xbar_AWPROT),
+        .s_axi_awready(s00_couplers_to_xbar_AWREADY),
+        .s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
+        .s_axi_bready(s00_couplers_to_xbar_BREADY),
+        .s_axi_bresp(s00_couplers_to_xbar_BRESP),
+        .s_axi_bvalid(s00_couplers_to_xbar_BVALID),
+        .s_axi_rdata(s00_couplers_to_xbar_RDATA),
+        .s_axi_rready(s00_couplers_to_xbar_RREADY),
+        .s_axi_rresp(s00_couplers_to_xbar_RRESP),
+        .s_axi_rvalid(s00_couplers_to_xbar_RVALID),
+        .s_axi_wdata(s00_couplers_to_xbar_WDATA),
+        .s_axi_wready(s00_couplers_to_xbar_WREADY),
+        .s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
+        .s_axi_wvalid(s00_couplers_to_xbar_WVALID));
+endmodule
+
+module m00_couplers_imp_15SPJYW
+   (M_ACLK,
+    M_ARESETN,
+    M_AXI_araddr,
+    M_AXI_arready,
+    M_AXI_arvalid,
+    M_AXI_awaddr,
+    M_AXI_awready,
+    M_AXI_awvalid,
+    M_AXI_bready,
+    M_AXI_bresp,
+    M_AXI_bvalid,
+    M_AXI_rdata,
+    M_AXI_rready,
+    M_AXI_rresp,
+    M_AXI_rvalid,
+    M_AXI_wdata,
+    M_AXI_wready,
+    M_AXI_wstrb,
+    M_AXI_wvalid,
+    S_ACLK,
+    S_ARESETN,
+    S_AXI_araddr,
+    S_AXI_arready,
+    S_AXI_arvalid,
+    S_AXI_awaddr,
+    S_AXI_awready,
+    S_AXI_awvalid,
+    S_AXI_bready,
+    S_AXI_bresp,
+    S_AXI_bvalid,
+    S_AXI_rdata,
+    S_AXI_rready,
+    S_AXI_rresp,
+    S_AXI_rvalid,
+    S_AXI_wdata,
+    S_AXI_wready,
+    S_AXI_wstrb,
+    S_AXI_wvalid);
+  input M_ACLK;
+  input M_ARESETN;
+  output [31:0]M_AXI_araddr;
+  input [0:0]M_AXI_arready;
+  output [0:0]M_AXI_arvalid;
+  output [31:0]M_AXI_awaddr;
+  input [0:0]M_AXI_awready;
+  output [0:0]M_AXI_awvalid;
+  output [0:0]M_AXI_bready;
+  input [1:0]M_AXI_bresp;
+  input [0:0]M_AXI_bvalid;
+  input [31:0]M_AXI_rdata;
+  output [0:0]M_AXI_rready;
+  input [1:0]M_AXI_rresp;
+  input [0:0]M_AXI_rvalid;
+  output [31:0]M_AXI_wdata;
+  input [0:0]M_AXI_wready;
+  output [3:0]M_AXI_wstrb;
+  output [0:0]M_AXI_wvalid;
+  input S_ACLK;
+  input S_ARESETN;
+  input [31:0]S_AXI_araddr;
+  output [0:0]S_AXI_arready;
+  input [0:0]S_AXI_arvalid;
+  input [31:0]S_AXI_awaddr;
+  output [0:0]S_AXI_awready;
+  input [0:0]S_AXI_awvalid;
+  input [0:0]S_AXI_bready;
+  output [1:0]S_AXI_bresp;
+  output [0:0]S_AXI_bvalid;
+  output [31:0]S_AXI_rdata;
+  input [0:0]S_AXI_rready;
+  output [1:0]S_AXI_rresp;
+  output [0:0]S_AXI_rvalid;
+  input [31:0]S_AXI_wdata;
+  output [0:0]S_AXI_wready;
+  input [3:0]S_AXI_wstrb;
+  input [0:0]S_AXI_wvalid;
+
+  wire [31:0]m00_couplers_to_m00_couplers_ARADDR;
+  wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
+  wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
+  wire [31:0]m00_couplers_to_m00_couplers_AWADDR;
+  wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
+  wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
+  wire [0:0]m00_couplers_to_m00_couplers_BREADY;
+  wire [1:0]m00_couplers_to_m00_couplers_BRESP;
+  wire [0:0]m00_couplers_to_m00_couplers_BVALID;
+  wire [31:0]m00_couplers_to_m00_couplers_RDATA;
+  wire [0:0]m00_couplers_to_m00_couplers_RREADY;
+  wire [1:0]m00_couplers_to_m00_couplers_RRESP;
+  wire [0:0]m00_couplers_to_m00_couplers_RVALID;
+  wire [31:0]m00_couplers_to_m00_couplers_WDATA;
+  wire [0:0]m00_couplers_to_m00_couplers_WREADY;
+  wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
+  wire [0:0]m00_couplers_to_m00_couplers_WVALID;
+
+  assign M_AXI_araddr[31:0] = m00_couplers_to_m00_couplers_ARADDR;
+  assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
+  assign M_AXI_awaddr[31:0] = m00_couplers_to_m00_couplers_AWADDR;
+  assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
+  assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
+  assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
+  assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
+  assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
+  assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
+  assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
+  assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
+  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
+  assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
+  assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
+  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
+  assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
+  assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
+  assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[31:0];
+  assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
+  assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
+  assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[31:0];
+  assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
+  assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
+  assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
+  assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
+  assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
+  assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
+  assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
+  assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
+  assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
+  assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
+  assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
+  assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
+  assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
+endmodule
+
+module m01_couplers_imp_XU9C55
+   (M_ACLK,
+    M_ARESETN,
+    M_AXI_araddr,
+    M_AXI_arready,
+    M_AXI_arvalid,
+    M_AXI_awaddr,
+    M_AXI_awready,
+    M_AXI_awvalid,
+    M_AXI_bready,
+    M_AXI_bresp,
+    M_AXI_bvalid,
+    M_AXI_rdata,
+    M_AXI_rready,
+    M_AXI_rresp,
+    M_AXI_rvalid,
+    M_AXI_wdata,
+    M_AXI_wready,
+    M_AXI_wstrb,
+    M_AXI_wvalid,
+    S_ACLK,
+    S_ARESETN,
+    S_AXI_araddr,
+    S_AXI_arready,
+    S_AXI_arvalid,
+    S_AXI_awaddr,
+    S_AXI_awready,
+    S_AXI_awvalid,
+    S_AXI_bready,
+    S_AXI_bresp,
+    S_AXI_bvalid,
+    S_AXI_rdata,
+    S_AXI_rready,
+    S_AXI_rresp,
+    S_AXI_rvalid,
+    S_AXI_wdata,
+    S_AXI_wready,
+    S_AXI_wstrb,
+    S_AXI_wvalid);
+  input M_ACLK;
+  input M_ARESETN;
+  output [31:0]M_AXI_araddr;
+  input [0:0]M_AXI_arready;
+  output [0:0]M_AXI_arvalid;
+  output [31:0]M_AXI_awaddr;
+  input [0:0]M_AXI_awready;
+  output [0:0]M_AXI_awvalid;
+  output [0:0]M_AXI_bready;
+  input [1:0]M_AXI_bresp;
+  input [0:0]M_AXI_bvalid;
+  input [31:0]M_AXI_rdata;
+  output [0:0]M_AXI_rready;
+  input [1:0]M_AXI_rresp;
+  input [0:0]M_AXI_rvalid;
+  output [31:0]M_AXI_wdata;
+  input [0:0]M_AXI_wready;
+  output [3:0]M_AXI_wstrb;
+  output [0:0]M_AXI_wvalid;
+  input S_ACLK;
+  input S_ARESETN;
+  input [31:0]S_AXI_araddr;
+  output [0:0]S_AXI_arready;
+  input [0:0]S_AXI_arvalid;
+  input [31:0]S_AXI_awaddr;
+  output [0:0]S_AXI_awready;
+  input [0:0]S_AXI_awvalid;
+  input [0:0]S_AXI_bready;
+  output [1:0]S_AXI_bresp;
+  output [0:0]S_AXI_bvalid;
+  output [31:0]S_AXI_rdata;
+  input [0:0]S_AXI_rready;
+  output [1:0]S_AXI_rresp;
+  output [0:0]S_AXI_rvalid;
+  input [31:0]S_AXI_wdata;
+  output [0:0]S_AXI_wready;
+  input [3:0]S_AXI_wstrb;
+  input [0:0]S_AXI_wvalid;
+
+  wire [31:0]m01_couplers_to_m01_couplers_ARADDR;
+  wire [0:0]m01_couplers_to_m01_couplers_ARREADY;
+  wire [0:0]m01_couplers_to_m01_couplers_ARVALID;
+  wire [31:0]m01_couplers_to_m01_couplers_AWADDR;
+  wire [0:0]m01_couplers_to_m01_couplers_AWREADY;
+  wire [0:0]m01_couplers_to_m01_couplers_AWVALID;
+  wire [0:0]m01_couplers_to_m01_couplers_BREADY;
+  wire [1:0]m01_couplers_to_m01_couplers_BRESP;
+  wire [0:0]m01_couplers_to_m01_couplers_BVALID;
+  wire [31:0]m01_couplers_to_m01_couplers_RDATA;
+  wire [0:0]m01_couplers_to_m01_couplers_RREADY;
+  wire [1:0]m01_couplers_to_m01_couplers_RRESP;
+  wire [0:0]m01_couplers_to_m01_couplers_RVALID;
+  wire [31:0]m01_couplers_to_m01_couplers_WDATA;
+  wire [0:0]m01_couplers_to_m01_couplers_WREADY;
+  wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
+  wire [0:0]m01_couplers_to_m01_couplers_WVALID;
+
+  assign M_AXI_araddr[31:0] = m01_couplers_to_m01_couplers_ARADDR;
+  assign M_AXI_arvalid[0] = m01_couplers_to_m01_couplers_ARVALID;
+  assign M_AXI_awaddr[31:0] = m01_couplers_to_m01_couplers_AWADDR;
+  assign M_AXI_awvalid[0] = m01_couplers_to_m01_couplers_AWVALID;
+  assign M_AXI_bready[0] = m01_couplers_to_m01_couplers_BREADY;
+  assign M_AXI_rready[0] = m01_couplers_to_m01_couplers_RREADY;
+  assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
+  assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
+  assign M_AXI_wvalid[0] = m01_couplers_to_m01_couplers_WVALID;
+  assign S_AXI_arready[0] = m01_couplers_to_m01_couplers_ARREADY;
+  assign S_AXI_awready[0] = m01_couplers_to_m01_couplers_AWREADY;
+  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
+  assign S_AXI_bvalid[0] = m01_couplers_to_m01_couplers_BVALID;
+  assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
+  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
+  assign S_AXI_rvalid[0] = m01_couplers_to_m01_couplers_RVALID;
+  assign S_AXI_wready[0] = m01_couplers_to_m01_couplers_WREADY;
+  assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[31:0];
+  assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready[0];
+  assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid[0];
+  assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[31:0];
+  assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready[0];
+  assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid[0];
+  assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready[0];
+  assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
+  assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid[0];
+  assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
+  assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready[0];
+  assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
+  assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid[0];
+  assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
+  assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready[0];
+  assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
+  assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid[0];
+endmodule
+
+module m02_couplers_imp_14WQB4R
+   (M_ACLK,
+    M_ARESETN,
+    M_AXI_araddr,
+    M_AXI_arready,
+    M_AXI_arvalid,
+    M_AXI_awaddr,
+    M_AXI_awready,
+    M_AXI_awvalid,
+    M_AXI_bready,
+    M_AXI_bresp,
+    M_AXI_bvalid,
+    M_AXI_rdata,
+    M_AXI_rready,
+    M_AXI_rresp,
+    M_AXI_rvalid,
+    M_AXI_wdata,
+    M_AXI_wready,
+    M_AXI_wstrb,
+    M_AXI_wvalid,
+    S_ACLK,
+    S_ARESETN,
+    S_AXI_araddr,
+    S_AXI_arready,
+    S_AXI_arvalid,
+    S_AXI_awaddr,
+    S_AXI_awready,
+    S_AXI_awvalid,
+    S_AXI_bready,
+    S_AXI_bresp,
+    S_AXI_bvalid,
+    S_AXI_rdata,
+    S_AXI_rready,
+    S_AXI_rresp,
+    S_AXI_rvalid,
+    S_AXI_wdata,
+    S_AXI_wready,
+    S_AXI_wstrb,
+    S_AXI_wvalid);
+  input M_ACLK;
+  input M_ARESETN;
+  output M_AXI_araddr;
+  input M_AXI_arready;
+  output M_AXI_arvalid;
+  output M_AXI_awaddr;
+  input M_AXI_awready;
+  output M_AXI_awvalid;
+  output M_AXI_bready;
+  input M_AXI_bresp;
+  input M_AXI_bvalid;
+  input M_AXI_rdata;
+  output M_AXI_rready;
+  input M_AXI_rresp;
+  input M_AXI_rvalid;
+  output M_AXI_wdata;
+  input M_AXI_wready;
+  output M_AXI_wstrb;
+  output M_AXI_wvalid;
+  input S_ACLK;
+  input S_ARESETN;
+  input S_AXI_araddr;
+  output S_AXI_arready;
+  input S_AXI_arvalid;
+  input S_AXI_awaddr;
+  output S_AXI_awready;
+  input S_AXI_awvalid;
+  input S_AXI_bready;
+  output S_AXI_bresp;
+  output S_AXI_bvalid;
+  output S_AXI_rdata;
+  input S_AXI_rready;
+  output S_AXI_rresp;
+  output S_AXI_rvalid;
+  input S_AXI_wdata;
+  output S_AXI_wready;
+  input S_AXI_wstrb;
+  input S_AXI_wvalid;
+
+  wire m02_couplers_to_m02_couplers_ARADDR;
+  wire m02_couplers_to_m02_couplers_ARREADY;
+  wire m02_couplers_to_m02_couplers_ARVALID;
+  wire m02_couplers_to_m02_couplers_AWADDR;
+  wire m02_couplers_to_m02_couplers_AWREADY;
+  wire m02_couplers_to_m02_couplers_AWVALID;
+  wire m02_couplers_to_m02_couplers_BREADY;
+  wire m02_couplers_to_m02_couplers_BRESP;
+  wire m02_couplers_to_m02_couplers_BVALID;
+  wire m02_couplers_to_m02_couplers_RDATA;
+  wire m02_couplers_to_m02_couplers_RREADY;
+  wire m02_couplers_to_m02_couplers_RRESP;
+  wire m02_couplers_to_m02_couplers_RVALID;
+  wire m02_couplers_to_m02_couplers_WDATA;
+  wire m02_couplers_to_m02_couplers_WREADY;
+  wire m02_couplers_to_m02_couplers_WSTRB;
+  wire m02_couplers_to_m02_couplers_WVALID;
+
+  assign M_AXI_araddr = m02_couplers_to_m02_couplers_ARADDR;
+  assign M_AXI_arvalid = m02_couplers_to_m02_couplers_ARVALID;
+  assign M_AXI_awaddr = m02_couplers_to_m02_couplers_AWADDR;
+  assign M_AXI_awvalid = m02_couplers_to_m02_couplers_AWVALID;
+  assign M_AXI_bready = m02_couplers_to_m02_couplers_BREADY;
+  assign M_AXI_rready = m02_couplers_to_m02_couplers_RREADY;
+  assign M_AXI_wdata = m02_couplers_to_m02_couplers_WDATA;
+  assign M_AXI_wstrb = m02_couplers_to_m02_couplers_WSTRB;
+  assign M_AXI_wvalid = m02_couplers_to_m02_couplers_WVALID;
+  assign S_AXI_arready = m02_couplers_to_m02_couplers_ARREADY;
+  assign S_AXI_awready = m02_couplers_to_m02_couplers_AWREADY;
+  assign S_AXI_bresp = m02_couplers_to_m02_couplers_BRESP;
+  assign S_AXI_bvalid = m02_couplers_to_m02_couplers_BVALID;
+  assign S_AXI_rdata = m02_couplers_to_m02_couplers_RDATA;
+  assign S_AXI_rresp = m02_couplers_to_m02_couplers_RRESP;
+  assign S_AXI_rvalid = m02_couplers_to_m02_couplers_RVALID;
+  assign S_AXI_wready = m02_couplers_to_m02_couplers_WREADY;
+  assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr;
+  assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready;
+  assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid;
+  assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr;
+  assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready;
+  assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid;
+  assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready;
+  assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp;
+  assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid;
+  assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata;
+  assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready;
+  assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp;
+  assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid;
+  assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata;
+  assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready;
+  assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb;
+  assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid;
+endmodule
+
+module s00_couplers_imp_UYSKKA
+   (M_ACLK,
+    M_ARESETN,
+    M_AXI_araddr,
+    M_AXI_arprot,
+    M_AXI_arready,
+    M_AXI_arvalid,
+    M_AXI_awaddr,
+    M_AXI_awprot,
+    M_AXI_awready,
+    M_AXI_awvalid,
+    M_AXI_bready,
+    M_AXI_bresp,
+    M_AXI_bvalid,
+    M_AXI_rdata,
+    M_AXI_rready,
+    M_AXI_rresp,
+    M_AXI_rvalid,
+    M_AXI_wdata,
+    M_AXI_wready,
+    M_AXI_wstrb,
+    M_AXI_wvalid,
+    S_ACLK,
+    S_ARESETN,
+    S_AXI_araddr,
+    S_AXI_arburst,
+    S_AXI_arcache,
+    S_AXI_arid,
+    S_AXI_arlen,
+    S_AXI_arlock,
+    S_AXI_arprot,
+    S_AXI_arqos,
+    S_AXI_arready,
+    S_AXI_arsize,
+    S_AXI_arvalid,
+    S_AXI_awaddr,
+    S_AXI_awburst,
+    S_AXI_awcache,
+    S_AXI_awid,
+    S_AXI_awlen,
+    S_AXI_awlock,
+    S_AXI_awprot,
+    S_AXI_awqos,
+    S_AXI_awready,
+    S_AXI_awsize,
+    S_AXI_awvalid,
+    S_AXI_bid,
+    S_AXI_bready,
+    S_AXI_bresp,
+    S_AXI_bvalid,
+    S_AXI_rdata,
+    S_AXI_rid,
+    S_AXI_rlast,
+    S_AXI_rready,
+    S_AXI_rresp,
+    S_AXI_rvalid,
+    S_AXI_wdata,
+    S_AXI_wid,
+    S_AXI_wlast,
+    S_AXI_wready,
+    S_AXI_wstrb,
+    S_AXI_wvalid);
+  input M_ACLK;
+  input M_ARESETN;
+  output [31:0]M_AXI_araddr;
+  output [2:0]M_AXI_arprot;
+  input M_AXI_arready;
+  output M_AXI_arvalid;
+  output [31:0]M_AXI_awaddr;
+  output [2:0]M_AXI_awprot;
+  input M_AXI_awready;
+  output M_AXI_awvalid;
+  output M_AXI_bready;
+  input [1:0]M_AXI_bresp;
+  input M_AXI_bvalid;
+  input [31:0]M_AXI_rdata;
+  output M_AXI_rready;
+  input [1:0]M_AXI_rresp;
+  input M_AXI_rvalid;
+  output [31:0]M_AXI_wdata;
+  input M_AXI_wready;
+  output [3:0]M_AXI_wstrb;
+  output M_AXI_wvalid;
+  input S_ACLK;
+  input S_ARESETN;
+  input [31:0]S_AXI_araddr;
+  input [1:0]S_AXI_arburst;
+  input [3:0]S_AXI_arcache;
+  input [11:0]S_AXI_arid;
+  input [3:0]S_AXI_arlen;
+  input [1:0]S_AXI_arlock;
+  input [2:0]S_AXI_arprot;
+  input [3:0]S_AXI_arqos;
+  output S_AXI_arready;
+  input [2:0]S_AXI_arsize;
+  input S_AXI_arvalid;
+  input [31:0]S_AXI_awaddr;
+  input [1:0]S_AXI_aw'b'burst;
+  input [3:0]S_AXI_awcache;
+  input [11:0]S_AXI_awid;
+  input [3:0]S_AXI_awlen;
+  input [1:0]S_AXI_awlock;
+  input [2:0]S_AXI_awprot;
+  input [3:0]S_AXI_awqos;
+  output S_AXI_awready;
+  input [2:0]S_AXI_awsize;
+  input S_AXI_awvalid;
+  output [11:0]S_AXI_bid;
+  input S_AXI_bready;
+  output [1:0]S_AXI_bresp;
+  output S_AXI_bvalid;
+  output [31:0]S_AXI_rdata;
+  output [11:0]S_AXI_rid;
+  output S_AXI_rlast;
+  input S_AXI_rready;
+  output [1:0]S_AXI_rresp;
+  output S_AXI_rvalid;
+  input [31:0]S_AXI_wdata;
+  input [11:0]S_AXI_wid;
+  input S_AXI_wlast;
+  output S_AXI_wready;
+  input [3:0]S_AXI_wstrb;
+  input S_AXI_wvalid;
+
+  wire S_ACLK_1;
+  wire S_ARESETN_1;
+  wire [31:0]auto_pc_to_s00_couplers_ARADDR;
+  wire [2:0]auto_pc_to_s00_couplers_ARPROT;
+  wire auto_pc_to_s00_couplers_ARREADY;
+  wire auto_pc_to_s00_couplers_ARVALID;
+  wire [31:0]auto_pc_to_s00_couplers_AWADDR;
+  wire [2:0]auto_pc_to_s00_couplers_AWPROT;
+  wire auto_pc_to_s00_couplers_AWREADY;
+  wire auto_pc_to_s00_couplers_AWVALID;
+  wire auto_pc_to_s00_couplers_BREADY;
+  wire [1:0]auto_pc_to_s00_couplers_BRESP;
+  wire auto_pc_to_s00_couplers_BVALID;
+  wire [31:0]auto_pc_to_s00_couplers_RDATA;
+  wire auto_pc_to_s00_couplers_RREADY;
+  wire [1:0]auto_pc_to_s00_couplers_RRESP;
+  wire auto_pc_to_s00_couplers_RVALID;
+  wire [31:0]auto_pc_to_s00_couplers_WDATA;
+  wire auto_pc_to_s00_couplers_WREADY;
+  wire [3:0]auto_pc_to_s00_couplers_WSTRB;
+  wire auto_pc_to_s00_couplers_WVALID;
+  wire [31:0]s00_couplers_to_auto_pc_ARADDR;
+  wire [1:0]s00_couplers_to_auto_pc_ARBURST;
+  wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
+  wire [11:0]s00_couplers_to_auto_pc_ARID;
+  wire [3:0]s00_couplers_to_auto_pc_ARLEN;
+  wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
+  wire [2:0]s00_couplers_to_auto_pc_ARPROT;
+  wire [3:0]s00_couplers_to_auto_pc_ARQOS;
+  wire s00_couplers_to_auto_pc_ARREADY;
+  wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
+  wire s00_couplers_to_auto_pc_ARVALID;
+  wire [31:0]s00_couplers_to_auto_pc_AWADDR;
+  wire [1:0]s00_couplers_to_auto_pc_AWBURST;
+  wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
+  wire [11:0]s00_couplers_to_auto_pc_AWID;
+  wire [3:0]s00_couplers_to_auto_pc_AWLEN;
+  wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
+  wire [2:0]s00_couplers_to_auto_pc_AWPROT;
+  wire [3:0]s00_couplers_to_auto_pc_AWQOS;
+  wire s00_couplers_to_auto_pc_AWREADY;
+  wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
+  wire s00_couplers_to_auto_pc_AWVALID;
+  wire [11:0]s00_couplers_to_auto_pc_BID;
+  wire s00_couplers_to_auto_pc_BREADY;
+  wire [1:0]s00_couplers_to_auto_pc_BRESP;
+  wire s00_couplers_to_auto_pc_BVALID;
+  wire [31:0]s00_couplers_to_auto_pc_RDATA;
+  wire [11:0]s00_couplers_to_auto_pc_RID;
+  wire s00_couplers_to_auto_pc_RLAST;
+  wire s00_couplers_to_auto_pc_RREADY;
+  wire [1:0]s00_couplers_to_auto_pc_RRESP;
+  wire s00_couplers_to_auto_pc_RVALID;
+  wire [31:0]s00_couplers_to_auto_pc_WDATA;
+  wire [11:0]s00_couplers_to_auto_pc_WID;
+  wire s00_couplers_to_auto_pc_WLAST;
+  wire s00_couplers_to_auto_pc_WREADY;
+  wire [3:0]s00_couplers_to_auto_pc_WSTRB;
+  wire s00_couplers_to_auto_pc_WVALID;
+
+  assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
+  assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
+  assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
+  assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
+  assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
+  assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
+  assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
+  assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
+  assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
+  assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
+  assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
+  assign S_ACLK_1 = S_ACLK;
+  assign S_ARESETN_1 = S_ARESETN;
+  assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
+  assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
+  assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
+  assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
+  assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
+  assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
+  assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
+  assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
+  assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
+  assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
+  assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
+  assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
+  assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
+  assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
+  assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
+  assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
+  assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
+  assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
+  assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
+  assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
+  assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
+  assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
+  assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
+  assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
+  assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
+  assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
+  assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
+  assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
+  assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
+  assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
+  assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
+  assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
+  assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
+  assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
+  assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
+  assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
+  assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
+  assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
+  assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
+  assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
+  assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
+  assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
+  assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
+  assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
+  assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
+  assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
+  design_1_auto_pc_0 auto_pc
+       (.aclk(S_ACLK_1),
+        .aresetn(S_ARESETN_1),
+        .m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
+        .m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
+        .m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
+        .m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
+        .m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
+        .m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
+        .m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
+        .m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
+        .m_axi_bready(auto_pc_to_s00_couplers_BREADY),
+        .m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
+        .m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
+        .m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
+        .m_axi_rready(auto_pc_to_s00_couplers_RREADY),
+        .m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
+        .m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
+        .m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
+        .m_axi_wready(auto_pc_to_s00_couplers_WREADY),
+        .m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
+        .m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
+        .s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
+        .s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
+        .s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
+        .s_axi_arid(s00_couplers_to_auto_pc_ARID),
+        .s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
+        .s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
+        .s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
+        .s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
+        .s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
+        .s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
+        .s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
+        .s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
+        .s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
+        .s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
+        .s_axi_awid(s00_couplers_to_auto_pc_AWID),
+        .s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
+        .s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
+        .s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
+        .s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
+        .s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
+        .s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
+        .s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
+        .s_axi_bid(s00_couplers_to_auto_pc_BID),
+        .s_axi_bready(s00_couplers_to_auto_pc_BREADY),
+        .s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
+        .s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
+        .s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
+        .s_axi_rid(s00_couplers_to_auto_pc_RID),
+        .s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
+        .s_axi_rready(s00_couplers_to_auto_pc_RREADY),
+        .s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
+        .s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
+        .s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
+        .s_axi_wid(s00_couplers_to_auto_pc_WID),
+        .s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
+        .s_axi_wready(s00_couplers_to_auto_pc_WREADY),
+        .s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
+        .s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:44:08 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
+// Design      : design_1_xbar_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, 
+  s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr, 
+  m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, 
+  m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, 
+  m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin=""aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]"" */;
+  input aclk;
+  input aresetn;
+  input [31:0]s_axi_awaddr;
+  input [2:0]s_axi_awprot;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [31:0]s_axi_araddr;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [95:0]m_axi_awaddr;
+  output [8:0]m_axi_awprot;
+  output [2:0]m_axi_awvalid;
+  input [2:0]m_axi_awready;
+  output [95:0]m_axi_wdata;
+  output [11:0]m_axi_wstrb;
+  output [2:0]m_axi_wvalid;
+  input [2:0]m_axi_wready;
+  input [5:0]m_axi_bresp;
+  input [2:0]m_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [95:0]m_axi_araddr;
+  output [8:0]m_axi_arprot;
+  output [2:0]m_axi_arvalid;
+  input [2:0]m_axi_arready;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rvalid;
+  output [2:0]m_axi_rready;
+endmodule
+"
+" 
+//-----------------------------------------------------------------------------
+// processing_system7
+// processor sub system wrapper
+//-----------------------------------------------------------------------------
+//
+// ************************************************************************
+// ** DISCLAIMER OF LIABILITY                                            **
+// **                                                                    **
+// ** This file contains proprietary and confidential information of     **
+// ** Xilinx, Inc. (""Xilinx""), that is distributed under a license       **
+// ** from Xilinx, and may be used, copied and/or diSCLosed only         **
+// ** pursuant to the terms of a valid license agreement with Xilinx.    **
+// **                                                                    **
+// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION              **
+// ** (""MATERIALS"") ""AS IS"" WITHOUT WARRANTY OF ANY KIND, EITHER         **
+// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT                **
+// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,          **
+// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx      **
+// ** does not warrant that functions included in the Materials will     **
+// ** meet the requirements of Licensee, or that the operation of the    **
+// ** Materials will be uninterrupted or error-free, or that defects     **
+// ** in the Materials will be corrected. Furthermore, Xilinx does       **
+// ** not warrant or make any representations regarding use, or the      **
+// ** results of the use, of the Materials in terms of correctness,      **
+// ** accuracy, reliability or otherwise.                                **
+// **                                                                    **
+// ** Xilinx products are not designed or intended to be fail-safe,      **
+// ** or for use in any application requiring fail-safe performance,     **
+// ** such as life-support or safety devices or systems, Class III       **
+// ** medical devices, nuclear facilities, applications related to       **
+// ** the deployment of airbags, or any other applications that could    **
+// ** lead to death, personal injury or severe property or               **
+// ** environmental damage (individually and collectively, ""critical     **
+// ** applications""). Customer assumes the sole risk and liability       **
+// ** of any use of Xilinx products in critical applications,            **
+// ** subject only to applicable laws and regulations governing          **
+// ** limitations on product liability.                                  **
+// **                                                                    **
+// ** Copyright 2010 Xilinx, Inc.                                        **
+// ** All rights reserved.                                               **
+// **                                                                    **
+// ** This disclaimer and copyright notice must be retained as part      **
+// ** of this file at all times.                                         **
+// ************************************************************************
+//
+//-----------------------------------------------------------------------------
+// Filename:      processing_system7_v5_5_processing_system7.v
+// Version:       v1.00.a
+// Description:   This is the wrapper file for PSS. 
+//-----------------------------------------------------------------------------
+// Structure:   This section shows the hierarchical structure of 
+//              pss_wrapper.
+//
+//              --processing_system7_v5_5_processing_system7.v
+//                    --PS7.v - Unisim component
+//-----------------------------------------------------------------------------
+// Author:      SD
+//
+// History:
+//
+//  SD      09/20/11      -- First version
+// ~~~~~~
+// Created the first version v2.00.a
+// ^^^^^^
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  SR     11/25/11       -- v3.00.a version
+// ~~~~~~~
+// Key changes are
+// 1. Changed all clock, reset and clktrig ports to be individual
+// signals instead of vectors. This is required for modeling of tools.
+// 2. Interrupts are now defined as individual signals as well.
+// 3. Added Clk buffer logic for FCLK_CLK
+// 4. Includes the ACP related changes done
+//
+// TODO:
+// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
+//    number of interrupt ports connected for IRQ_F2P.
+// 
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  KP     12/07/11       -- v3.00.a version
+// ~~~~~~~
+// Key changes are
+//  C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     12/09/11       -- v3.00.a version
+// ~~~~~~~
+// Key changes are
+//  C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated 
+//  to STRING and fix for CR 640523
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     12/13/11       -- v3.00.a version
+// ~~~~~~~
+// Key changes are
+// Updated IRQ_F2P logic to address CR 641523.
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     02/01/12       -- v3.01.a version
+// ~~~~~~~
+// Key changes are
+// Updated SDIO logic to address CR 636210.
+//         |
+//         Added C_PS7_SI_REV parameter to track SI Rev
+// Removed compress/decompress logic to address CR 642527.
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     02/27/12       -- v3.01.a version
+// ~~~~~~~
+// Key changes are
+// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual 
+// ports as fix for CR 646379
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     03/05/12       -- v3.01.a version
+// ~~~~~~~
+// Key changes are
+// Added/updated compress/decompress logic to address 648393
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     03/14/12       -- v4.00.a version
+// ~~~~~~~
+// Unused parameters deleted CR 651120
+// Addressed CR 651751
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     04/17/12       -- v4.01.a version
+// ~~~~~~~
+// Added FTM trace buffer functionality
+// Added support for ACP AxUSER ports local update
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  VR     05/18/12       -- v4.01.a version
+// ~~~~~~~
+// Fixed CR#659157
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  VR     07/25/12       -- v4.01.a version
+// ~~~~~~~
+// Changed S_AXI_HP{1,2}_WACOUNT port\'s width to 6 from 8 to match unisim model
+// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  VR     11/06/12       -- v5.00 version
+// ~~~~~~~
+// CR #682573
+// Added BIBUF to fixed IO ports and IBUF to fixed input ports
+//------------------------------------------------------------------------------
+(*POWER= ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *)
+(* CORE_GENERATION_INFO = ""processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.034, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.03, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.082, PCW_UIPARAM_DDR_BOARD_DELAY0=0.176, PCW_UIPARAM_DDR_BOARD_DELAY1=0.159, PCW_UIPARAM_DDR_BOARD_DELAY2=0.162, PCW_UIPARAM_DDR_BOARD_DELAY3=0.187, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\\
+, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50.000000, PCW_APU_PERIPHERAL_FREQMHZ=650, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\\
+, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\\
+, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=MIO 14 .. 15, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0\\
+, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=MIO 10 .. 11, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=64, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL\\
+, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1\\
+, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }"" *)  
+(* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *)  
+
+module processing_system7_v5_5_processing_system7
+
+#(
+  parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
+  parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
+  parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
+  parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
+  parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12, 
+  parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
+  parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1, 
+  parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
+  parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
+  parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
+  parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
+  parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
+  parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
+  parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
+  parameter integer C_NUM_F2P_INTR_INPUTS = 1,
+  parameter         C_FCLK_CLK0_BUF = ""TRUE"",
+  parameter         C_FCLK_CLK1_BUF = ""TRUE"",
+  parameter         C_FCLK_CLK2_BUF = ""TRUE"",
+  parameter         C_FCLK_CLK3_BUF = ""TRUE"",
+  parameter integer C_EMIO_GPIO_WIDTH = 64,
+  parameter integer C_INCLUDE_TRACE_BUFFER = 0,
+  parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
+  parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
+  parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
+  parameter integer C_TRACE_PIPELINE_WIDTH = 8,
+  parameter         C_PS7_SI_REV = ""PRODUCTION"",
+  parameter integer C_EN_EMIO_ENET0 = 0,
+  parameter integer C_EN_EMIO_ENET1 = 0,
+  parameter integer C_EN_EMIO_TRACE = 0,
+  parameter integer C_DQ_WIDTH = 32,
+  parameter integer C_DQS_WIDTH = 4,
+  parameter integer C_DM_WIDTH = 4,
+  parameter integer C_MIO_PRIMITIVE = 54,
+  parameter\t    C_PACKAGE_NAME = ""clg484"",
+  parameter C_IRQ_F2P_MODE = ""DIRECT"",
+  parameter C_TRACE_INTERNAL_WIDTH = 32,
+  parameter integer C_EN_EMIO_PJTAG = 0,
+  
+  // Enable and disable AFI Secure transaction 
+  parameter C_USE_AXI_NONSECURE = 0,
+  
+  //parameters for HP enable ports 
+  parameter C_USE_S_AXI_HP0 = 0,
+  parameter C_USE_S_AXI_HP1 = 0,
+  parameter C_USE_S_AXI_HP2 = 0,
+  parameter C_USE_S_AXI_HP3 = 0,
+  
+  //parameters for GP and ACP enable ports */
+  parameter C_USE_M_AXI_GP0 = 0,
+  parameter C_USE_M_AXI_GP1 = 0,
+  parameter C_USE_S_AXI_GP0 = 0,
+  parameter C_USE_S_AXI_GP1 = 0,
+  parameter C_USE_S_AXI_ACP = 0,
+  parameter C_GP0_EN_MODIFIABLE_TXN=0,
+  parameter C_GP1_EN_MODIFIABLE_TXN=0
+   
+)
+(
+  //FMIO =========================================
+  
+  //FMIO CAN0
+  output          CAN0_PHY_TX,
+  input           CAN0_PHY_RX,
+
+  //FMIO CAN1
+  output          CAN1_PHY_TX,  
+  input           CAN1_PHY_RX,
+  
+  //FMIO ENET0
+  output  reg     ENET0_GMII_TX_EN = \'b0,
+  output  reg     ENET0_GMII_TX_ER = \'b0,
+  output          ENET0_MDIO_MDC,
+  output          ENET0_MDIO_O,
+  output          ENET0_MDIO_T,
+  output          ENET0_PTP_DELAY_REQ_RX,
+  output          ENET0_PTP_DELAY_REQ_TX,
+  output          ENET0_PTP_PDELAY_REQ_RX,
+  output          ENET0_PTP_PDELAY_REQ_TX,
+  output          ENET0_PTP_PDELAY_RESP_RX,
+  output          ENET0_PTP_PDELAY_RESP_TX,
+  output          ENET0_PTP_SYNC_FRAME_RX,
+  output          ENET0_PTP_SYNC_FRAME_TX,
+  output          ENET0_SOF_RX,
+  output          ENET0_SOF_TX,
+  
+  
+  output  reg [7:0]    ENET0_GMII_TXD,  
+
+  
+  input           ENET0_GMII_COL,
+  input           ENET0_GMII_CRS,
+  input           ENET0_GMII_RX_CLK,
+  input           ENET0_GMII_RX_DV,
+  input           ENET0_GMII_RX_ER,
+  input           ENET0_GMII_TX_CLK,
+  input           ENET0_MDIO_I,
+  input           ENET0_EXT_INTIN,
+  input [7:0]     ENET0_GMII_RXD,  
+
+  //FMIO ENET1
+  output   reg    ENET1_GMII_TX_EN = \'b0,
+  output   reg    ENET1_GMII_TX_ER = \'b0,
+  output          ENET1_MDIO_MDC,
+  output          ENET1_MDIO_O,
+  output          ENET1_MDIO_T,
+  output          ENET1_PTP_DELAY_REQ_RX,
+  output          ENET1_PTP_DELAY_REQ_TX,
+  output          ENET1_PTP_PDELAY_REQ_RX,
+  output          ENET1_PTP_PDELAY_REQ_TX,
+  output          ENET1_PTP_PDELAY_RESP_RX,
+  output          ENET1_PTP_PDELAY_RESP_TX,
+  output          ENET1_PTP_SYNC_FRAME_RX,
+  output          ENET1_PTP_SYNC_FRAME_TX,
+  output          ENET1_SOF_RX,
+  output          ENET1_SOF_TX,
+  output reg [7:0]    ENET1_GMII_TXD,  
+
+  input          ENET1_GMII_COL,
+  input          ENET1_GMII_CRS,
+  input          ENET1_GMII_RX_CLK,
+  input          ENET1_GMII_RX_DV,
+  input          ENET1_GMII_RX_ER,
+  input          ENET1_GMII_TX_CLK,
+  input          ENET1_MDIO_I,
+  input          ENET1_EXT_INTIN,  
+  input [7:0]    ENET1_GMII_RXD,
+  
+  //FMIO GPIO
+  input    [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
+  output   [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
+  output   [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,  
+  
+  //FMIO I2C0
+  input           I2C0_SDA_I,
+  output          I2C0_SDA_O,
+  output          I2C0_SDA_T,
+  input           I2C0_SCL_I,
+  output          I2C0_SCL_O,
+  output          I2C0_SCL_T,
+
+  //FMIO I2C1
+  input           I2C1_SDA_I,
+  output          I2C1_SDA_O,
+  output          I2C1_SDA_T,
+  input           I2C1_SCL_I,
+  output          I2C1_SCL_O,
+  output          I2C1_SCL_T,
+  
+  //FMIO PJTAG
+  input           PJTAG_TCK,
+  input           PJTAG_TMS,
+  input           PJTAG_TDI,
+  output          PJTAG_TDO,
+
+  
+  //FMIO SDIO0
+  output          SDIO0_CLK,
+  input           SDIO0_CLK_FB,
+  output          SDIO0_CMD_O,
+  input           SDIO0_CMD_I,
+  output          SDIO0_CMD_T,
+  input     [3:0] SDIO0_DATA_I,
+  output    [3:0] SDIO0_DATA_O,
+  output    [3:0] SDIO0_DATA_T,
+  output          SDIO0_LED,
+  input           SDIO0_CDN,
+  input           SDIO0_WP,  
+  output          SDIO0_BUSPOW,
+  output    [2:0] SDIO0_BUSVOLT,
+
+  //FMIO SDIO1
+  output          SDIO1_CLK,
+  input           SDIO1_CLK_FB,
+  output          SDIO1_CMD_O,
+  input           SDIO1_CMD_I,
+  output          SDIO1_CMD_T,
+  input     [3:0] SDIO1_DATA_I,
+  output    [3:0] SDIO1_DATA_O,
+  output    [3:0] SDIO1_DATA_T,  
+  output          SDIO1_LED,
+  input           SDIO1_CDN,  
+  input           SDIO1_WP,
+  output          SDIO1_BUSPOW,  
+  output    [2:0] SDIO1_BUSVOLT,
+
+  //FMIO SPI0
+  input           SPI0_SCLK_I,
+  output          SPI0_SCLK_O,
+  output          SPI0_SCLK_T,
+  input           SPI0_MOSI_I,
+  output          SPI0_MOSI_O,
+  output          SPI0_MOSI_T,
+  input           SPI0_MISO_I,
+  output          SPI0_MISO_O,
+  output          SPI0_MISO_T,
+  input           SPI0_SS_I,
+  output          SPI0_SS_O,
+  output          SPI0_SS1_O,
+  output          SPI0_SS2_O,
+  output          SPI0_SS_T,
+
+  //FMIO SPI1
+  input           SPI1_SCLK_I,
+  output          SPI1_SCLK_O,
+  output          SPI1_SCLK_T,
+  input           SPI1_MOSI_I,
+  output          SPI1_MOSI_O,
+  output          SPI1_MOSI_T,
+  input           SPI1_MISO_I,
+  output          SPI1_MISO_O,
+  output          SPI1_MISO_T,
+  input           SPI1_SS_I,
+  output          SPI1_SS_O,
+  output          SPI1_SS1_O,
+  output          SPI1_SS2_O,  
+  output          SPI1_SS_T,
+
+  //FMIO UART0
+  output          UART0_DTRN,
+  output          UART0_RTSN,  
+  output          UART0_TX,
+  input           UART0_CTSN,
+  input           UART0_DCDN,
+  input           UART0_DSRN,
+  input           UART0_RIN,  
+  input           UART0_RX,
+
+  //FMIO UART1
+  output          UART1_DTRN,
+  output          UART1_RTSN,  
+  output          UART1_TX,
+  input           UART1_CTSN,
+  input           UART1_DCDN,
+  input           UART1_DSRN,
+  input           UART1_RIN,  
+  input           UART1_RX,
+
+  //FMIO TTC0
+  output    \t\tTTC0_WAVE0_OUT,
+  output    \t\tTTC0_WAVE1_OUT,
+  output    \t\tTTC0_WAVE2_OUT,
+  input     \t\tTTC0_CLK0_IN,
+  input     \t\tTTC0_CLK1_IN,
+  input     \t\tTTC0_CLK2_IN,
+
+  //FMIO TTC1
+  output    \t\tTTC1_WAVE0_OUT,
+  output    \t\tTTC1_WAVE1_OUT,
+  output    \t\tTTC1_WAVE2_OUT,
+  input     \t\tTTC1_CLK0_IN,
+  input     \t\tTTC1_CLK1_IN,
+  input     \t\tTTC1_CLK2_IN,
+
+  //WDT
+  input           WDT_CLK_IN,
+  output          WDT_RST_OUT,
+
+  //FTPORT
+  input           TRACE_CLK,
+  output          TRACE_CTL,
+  output   [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
+  output   reg\t\t  TRACE_CLK_OUT,
+  
+  // USB
+  output   [1:0]  USB0_PORT_INDCTL,
+  output          USB0_VBUS_PWRSELECT,
+  input           USB0_VBUS_PWRFAULT,
+
+  output   [1:0]  USB1_PORT_INDCTL,
+  output          USB1_VBUS_PWRSELECT,
+  input           USB1_VBUS_PWRFAULT,
+  
+  input           SRAM_INTIN,
+
+  //AIO ===================================================
+
+  //M_AXI_GP0
+  
+  // -- Output
+  
+  output M_AXI_GP0_ARESETN,
+  output M_AXI_GP0_ARVALID,
+  output M_AXI_GP0_AWVALID,
+  output M_AXI_GP0_BREADY,
+  output M_AXI_GP0_RREADY,
+  output M_AXI_GP0_WLAST,
+  output M_AXI_GP0_WVALID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
+  output [1:0] M_AXI_GP0_ARBURST,
+  output [1:0] M_AXI_GP0_ARLOCK,
+  output [2:0] M_AXI_GP0_ARSIZE,
+  output [1:0] M_AXI_GP0_AWBURST,
+  output [1:0] M_AXI_GP0_AWLOCK,
+  output [2:0] M_AXI_GP0_AWSIZE,
+  output [2:0] M_AXI_GP0_ARPROT,
+  output [2:0] M_AXI_GP0_AWPROT,
+  output [31:0] M_AXI_GP0_ARADDR,
+  output [31:0] M_AXI_GP0_AWADDR,
+  output [31:0] M_AXI_GP0_WDATA,
+  output [3:0] M_AXI_GP0_ARCACHE,
+  output [3:0] M_AXI_GP0_ARLEN,
+  output [3:0] M_AXI_GP0_ARQOS,
+  output [3:0] M_AXI_GP0_AWCACHE,
+  output [3:0] M_AXI_GP0_AWLEN,
+  output [3:0] M_AXI_GP0_AWQOS,
+  output [3:0] M_AXI_GP0_WSTRB, 
+  
+  // -- Input  
+  
+  input M_AXI_GP0_ACLK,
+  input M_AXI_GP0_ARREADY,
+  input M_AXI_GP0_AWREADY,
+  input M_AXI_GP0_BVALID,
+  input M_AXI_GP0_RLAST,
+  input M_AXI_GP0_RVALID,
+  input M_AXI_GP0_WREADY,
+  input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
+  input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
+  input [1:0] M_AXI_GP0_BRESP,
+  input [1:0] M_AXI_GP0_RRESP,
+  input [31:0] M_AXI_GP0_RDATA,  
+
+
+  //M_AXI_GP1
+  
+  // -- Output
+
+  output M_AXI_GP1_ARESETN,
+  output M_AXI_GP1_ARVALID,
+  output M_AXI_GP1_AWVALID,
+  output M_AXI_GP1_BREADY,
+  output M_AXI_GP1_RREADY,
+  output M_AXI_GP1_WLAST,
+  output M_AXI_GP1_WVALID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
+  output [1:0] M_AXI_GP1_ARBURST,
+  output [1:0] M_AXI_GP1_ARLOCK,
+  output [2:0] M_AXI_GP1_ARSIZE,
+  output [1:0] M_AXI_GP1_AWBURST,
+  output [1:0] M_AXI_GP1_AWLOCK,
+  output [2:0] M_AXI_GP1_AWSIZE,
+  output [2:0] M_AXI_GP1_ARPROT,
+  output [2:0] M_AXI_GP1_AWPROT,
+  output [31:0] M_AXI_GP1_ARADDR,
+  output [31:0] M_AXI_GP1_AWADDR,
+  output [31:0] M_AXI_GP1_WDATA,
+  output [3:0] M_AXI_GP1_ARCACHE,
+  output [3:0] M_AXI_GP1_ARLEN,
+  output [3:0] M_AXI_GP1_ARQOS,
+  output [3:0] M_AXI_GP1_AWCACHE,
+  output [3:0] M_AXI_GP1_AWLEN,
+  output [3:0] M_AXI_GP1_AWQOS,
+  output [3:0] M_AXI_GP1_WSTRB,
+  
+  // -- Input
+  
+  input M_AXI_GP1_ACLK,
+  input M_AXI_GP1_ARREADY,
+  input M_AXI_GP1_AWREADY,
+  input M_AXI_GP1_BVALID,
+  input M_AXI_GP1_RLAST,
+  input M_AXI_GP1_RVALID,
+  input M_AXI_GP1_WREADY,  
+  input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
+  input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
+  input [1:0] M_AXI_GP1_BRESP,
+  input [1:0] M_AXI_GP1_RRESP,
+  input [31:0] M_AXI_GP1_RDATA,  
+  
+
+  // S_AXI_GP0
+  
+  // -- Output
+  
+  output S_AXI_GP0_ARESETN,
+  output S_AXI_GP0_ARREADY,
+  output S_AXI_GP0_AWREADY,
+  output S_AXI_GP0_BVALID,
+  output S_AXI_GP0_RLAST,
+  output S_AXI_GP0_RVALID,
+  output S_AXI_GP0_WREADY,  
+  output [1:0] S_AXI_GP0_BRESP,
+  output [1:0] S_AXI_GP0_RRESP,
+  output [31:0] S_AXI_GP0_RDATA,
+  output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
+  output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
+  
+  // -- Input
+  input S_AXI_GP0_ACLK,
+  input S_AXI_GP0_ARVALID,
+  input S_AXI_GP0_AWVALID,
+  input S_AXI_GP0_BREADY,
+  input S_AXI_GP0_RREADY,
+  input S_AXI_GP0_WLAST,
+  input S_AXI_GP0_WVALID,
+  input [1:0] S_AXI_GP0_ARBURST,
+  input [1:0] S_AXI_GP0_ARLOCK,
+  input [2:0] S_AXI_GP0_ARSIZE,
+  input [1:0] S_AXI_GP0_AWBURST,
+  input [1:0] S_AXI_GP0_AWLOCK,
+  input [2:0] S_AXI_GP0_AWSIZE,
+  input [2:0] S_AXI_GP0_ARPROT,
+  input [2:0] S_AXI_GP0_AWPROT,
+  input [31:0] S_AXI_GP0_ARADDR,
+  input [31:0] S_AXI_GP0_AWADDR,
+  input [31:0] S_AXI_GP0_WDATA,
+  input [3:0] S_AXI_GP0_ARCACHE,
+  input [3:0] S_AXI_GP0_ARLEN,
+  input [3:0] S_AXI_GP0_ARQOS,
+  input [3:0] S_AXI_GP0_AWCACHE,
+  input [3:0] S_AXI_GP0_AWLEN,
+  input [3:0] S_AXI_GP0_AWQOS,
+  input [3:0] S_AXI_GP0_WSTRB,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,  
+
+  // S_AXI_GP1
+  
+  // -- Output  
+  output S_AXI_GP1_ARESETN,
+  output S_AXI_GP1_ARREADY,
+  output S_AXI_GP1_AWREADY,
+  output S_AXI_GP1_BVALID,
+  output S_AXI_GP1_RLAST,
+  output S_AXI_GP1_RVALID,
+  output S_AXI_GP1_WREADY,  
+  output [1:0] S_AXI_GP1_BRESP,
+  output [1:0] S_AXI_GP1_RRESP,
+  output [31:0] S_AXI_GP1_RDATA,
+  output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
+  output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
+  
+  // -- Input
+  input S_AXI_GP1_ACLK,
+  input S_AXI_GP1_ARVALID,
+  input S_AXI_GP1_AWVALID,
+  input S_AXI_GP1_BREADY,
+  input S_AXI_GP1_RREADY,
+  input S_AXI_GP1_WLAST,
+  input S_AXI_GP1_WVALID,
+  input [1:0] S_AXI_GP1_ARBURST,
+  input [1:0] S_AXI_GP1_ARLOCK,
+  input [2:0] S_AXI_GP1_ARSIZE,
+  input [1:0] S_AXI_GP1_AWBURST,
+  input [1:0] S_AXI_GP1_AWLOCK,
+  input [2:0] S_AXI_GP1_AWSIZE,
+  input [2:0] S_AXI_GP1_ARPROT,
+  input [2:0] S_AXI_GP1_AWPROT,
+  input [31:0] S_AXI_GP1_ARADDR,
+  input [31:0] S_AXI_GP1_AWADDR,
+  input [31:0] S_AXI_GP1_WDATA,
+  input [3:0] S_AXI_GP1_ARCACHE,
+  input [3:0] S_AXI_GP1_ARLEN,
+  input [3:0] S_AXI_GP1_ARQOS,
+  input [3:0] S_AXI_GP1_AWCACHE,
+  input [3:0] S_AXI_GP1_AWLEN,
+  input [3:0] S_AXI_GP1_AWQOS,
+  input [3:0] S_AXI_GP1_WSTRB,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,  
+
+  //S_AXI_ACP
+  
+  // -- Output  
+  
+  output S_AXI_ACP_ARESETN,
+  output S_AXI_ACP_ARREADY,
+  output S_AXI_ACP_AWREADY,
+  output S_AXI_ACP_BVALID,
+  output S_AXI_ACP_RLAST,
+  output S_AXI_ACP_RVALID,
+  output S_AXI_ACP_WREADY,  
+  output [1:0] S_AXI_ACP_BRESP,
+  output [1:0] S_AXI_ACP_RRESP,
+  output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
+  output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
+  output [63:0] S_AXI_ACP_RDATA,
+  
+  // -- Input
+  
+  input S_AXI_ACP_ACLK,
+  input S_AXI_ACP_ARVALID,
+  input S_AXI_ACP_AWVALID,
+  input S_AXI_ACP_BREADY,
+  input S_AXI_ACP_RREADY,
+  input S_AXI_ACP_WLAST,
+  input S_AXI_ACP_WVALID,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
+  input [2:0] S_AXI_ACP_ARPROT,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
+  input [2:0] S_AXI_ACP_AWPROT,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
+  input [31:0] S_AXI_ACP_ARADDR,
+  input [31:0] S_AXI_ACP_AWADDR,
+  input [3:0] S_AXI_ACP_ARCACHE,
+  input [3:0] S_AXI_ACP_ARLEN,
+  input [3:0] S_AXI_ACP_ARQOS,
+  input [3:0] S_AXI_ACP_AWCACHE,
+  input [3:0] S_AXI_ACP_AWLEN,
+  input [3:0] S_AXI_ACP_AWQOS,  
+  input [1:0] S_AXI_ACP_ARBURST,
+  input [1:0] S_AXI_ACP_ARLOCK,
+  input [2:0] S_AXI_ACP_ARSIZE,
+  input [1:0] S_AXI_ACP_AWBURST,
+  input [1:0] S_AXI_ACP_AWLOCK,
+  input [2:0] S_AXI_ACP_AWSIZE,
+  input [4:0] S_AXI_ACP_ARUSER,
+  input [4:0] S_AXI_ACP_AWUSER,
+  input [63:0] S_AXI_ACP_WDATA,
+  input [7:0] S_AXI_ACP_WSTRB,  
+  
+  // S_AXI_HP_0
+  
+  // -- Output
+  output S_AXI_HP0_ARESETN,
+  output S_AXI_HP0_ARREADY,
+  output S_AXI_HP0_AWREADY,
+  output S_AXI_HP0_BVALID,
+  output S_AXI_HP0_RLAST,
+  output S_AXI_HP0_RVALID,
+  output S_AXI_HP0_WREADY,  
+  output [1:0] S_AXI_HP0_BRESP,
+  output [1:0] S_AXI_HP0_RRESP,
+  output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
+  output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
+  output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
+  output [7:0] S_AXI_HP0_RCOUNT,
+  output [7:0] S_AXI_HP0_WCOUNT,
+  output [2:0] S_AXI_HP0_RACOUNT,
+  output [5:0] S_AXI_HP0_WACOUNT,
+  
+  // -- Input  
+  input S_AXI_HP0_ACLK,
+  input S_AXI_HP0_ARVALID,
+  input S_AXI_HP0_AWVALID,
+  input S_AXI_HP0_BREADY,
+  input S_AXI_HP0_RDISSUECAP1_EN,
+  input S_AXI_HP0_RREADY,
+  input S_AXI_HP0_WLAST,
+  input S_AXI_HP0_WRISSUECAP1_EN,
+  input S_AXI_HP0_WVALID,
+  input [1:0] S_AXI_HP0_ARBURST,
+  input [1:0] S_AXI_HP0_ARLOCK,
+  input [2:0] S_AXI_HP0_ARSIZE,
+  input [1:0] S_AXI_HP0_AWBURST,
+  input [1:0] S_AXI_HP0_AWLOCK,
+  input [2:0] S_AXI_HP0_AWSIZE,
+  input [2:0] S_AXI_HP0_ARPROT,
+  input [2:0] S_AXI_HP0_AWPROT,
+  input [31:0] S_AXI_HP0_ARADDR,
+  input [31:0] S_AXI_HP0_AWADDR,
+  input [3:0] S_AXI_HP0_ARCACHE,
+  input [3:0] S_AXI_HP0_ARLEN,
+  input [3:0] S_AXI_HP0_ARQOS,
+  input [3:0] S_AXI_HP0_AWCACHE,
+  input [3:0] S_AXI_HP0_AWLEN,
+  input [3:0] S_AXI_HP0_AWQOS,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
+  input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
+  input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,  
+
+  // S_AXI_HP1
+  // -- Output
+  output S_AXI_HP1_ARESETN,
+  output S_AXI_HP1_ARREADY,
+  output S_AXI_HP1_AWREADY,
+  output S_AXI_HP1_BVALID,
+  output S_AXI_HP1_RLAST,
+  output S_AXI_HP1_RVALID,
+  output S_AXI_HP1_WREADY,  
+  output [1:0] S_AXI_HP1_BRESP,
+  output [1:0] S_AXI_HP1_RRESP,
+  output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
+  output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
+  output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
+  output [7:0] S_AXI_HP1_RCOUNT,
+  output [7:0] S_AXI_HP1_WCOUNT,
+  output [2:0] S_AXI_HP1_RACOUNT,
+  output [5:0] S_AXI_HP1_WACOUNT,
+  
+  
+  // -- Input  
+  input S_AXI_HP1_ACLK,
+  input S_AXI_HP1_ARVALID,
+  input S_AXI_HP1_AWVALID,
+  input S_AXI_HP1_BREADY,
+  input S_AXI_HP1_RDISSUECAP1_EN,
+  input S_AXI_HP1_RREADY,
+  input S_AXI_HP1_WLAST,
+  input S_AXI_HP1_WRISSUECAP1_EN,
+  input S_AXI_HP1_WVALID,
+  input [1:0] S_AXI_HP1_ARBURST,
+  input [1:0] S_AXI_HP1_ARLOCK,
+  input [2:0] S_AXI_HP1_ARSIZE,
+  input [1:0] S_AXI_HP1_AWBURST,
+  input [1:0] S_AXI_HP1_AWLOCK,
+  input [2:0] S_AXI_HP1_AWSIZE,
+  input [2:0] S_AXI_HP1_ARPROT,
+  input [2:0] S_AXI_HP1_AWPROT,
+  input [31:0] S_AXI_HP1_ARADDR,
+  input [31:0] S_AXI_HP1_AWADDR,
+  input [3:0] S_AXI_HP1_ARCACHE,
+  input [3:0] S_AXI_HP1_ARLEN,
+  input [3:0] S_AXI_HP1_ARQOS,
+  input [3:0] S_AXI_HP1_AWCACHE,
+  input [3:0] S_AXI_HP1_AWLEN,
+  input [3:0] S_AXI_HP1_AWQOS,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
+  input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
+  input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,  
+
+  // S_AXI_HP2
+  // -- Output
+  output S_AXI_HP2_ARESETN,
+  output S_AXI_HP2_ARREADY,
+  output S_AXI_HP2_AWREADY,
+  output S_AXI_HP2_BVALID,
+  output S_AXI_HP2_RLAST,
+  output S_AXI_HP2_RVALID,
+  output S_AXI_HP2_WREADY,  
+  output [1:0] S_AXI_HP2_BRESP,
+  output [1:0] S_AXI_HP2_RRESP,
+  output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
+  output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
+  output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
+  output [7:0] S_AXI_HP2_RCOUNT,
+  output [7:0] S_AXI_HP2_WCOUNT,
+  output [2:0] S_AXI_HP2_RACOUNT,
+  output [5:0] S_AXI_HP2_WACOUNT,
+  
+  
+  // -- Input  
+  input S_AXI_HP2_ACLK,
+  input S_AXI_HP2_ARVALID,
+  input S_AXI_HP2_AWVALID,
+  input S_AXI_HP2_BREADY,
+  input S_AXI_HP2_RDISSUECAP1_EN,
+  input S_AXI_HP2_RREADY,
+  input S_AXI_HP2_WLAST,
+  input S_AXI_HP2_WRISSUECAP1_EN,
+  input S_AXI_HP2_WVALID,
+  input [1:0] S_AXI_HP2_ARBURST,
+  input [1:0] S_AXI_HP2_ARLOCK,
+  input [2:0] S_AXI_HP2_ARSIZE,
+  input [1:0] S_AXI_HP2_AWBURST,
+  input [1:0] S_AXI_HP2_AWLOCK,
+  input [2:0] S_AXI_HP2_AWSIZE,
+  input [2:0] S_AXI_HP2_ARPROT,
+  input [2:0] S_AXI_HP2_AWPROT,
+  input [31:0] S_AXI_HP2_ARADDR,
+  input [31:0] S_AXI_HP2_AWADDR,
+  input [3:0] S_AXI_HP2_ARCACHE,
+  input [3:0] S_AXI_HP2_ARLEN,
+  input [3:0] S_AXI_HP2_ARQOS,
+  input [3:0] S_AXI_HP2_AWCACHE,
+  input [3:0] S_AXI_HP2_AWLEN,
+  input [3:0] S_AXI_HP2_AWQOS,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
+  input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
+  input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,  
+
+  // S_AXI_HP_3
+  
+  // -- Output
+  output S_AXI_HP3_ARESETN,
+  output S_AXI_HP3_ARREADY,
+  output S_AXI_HP3_AWREADY,
+  output S_AXI_HP3_BVALID,
+  output S_AXI_HP3_RLAST,
+  output S_AXI_HP3_RVALID,
+  output S_AXI_HP3_WREADY,  
+  output [1:0] S_AXI_HP3_BRESP,
+  output [1:0] S_AXI_HP3_RRESP,
+  output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
+  output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
+  output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
+  output [7:0] S_AXI_HP3_RCOUNT,
+  output [7:0] S_AXI_HP3_WCOUNT,
+  output [2:0] S_AXI_HP3_RACOUNT,
+  output [5:0] S_AXI_HP3_WACOUNT,
+  
+  
+  // -- Input  
+  input S_AXI_HP3_ACLK,
+  input S_AXI_HP3_ARVALID,
+  input S_AXI_HP3_AWVALID,
+  input S_AXI_HP3_BREADY,
+  input S_AXI_HP3_RDISSUECAP1_EN,
+  input S_AXI_HP3_RREADY,
+  input S_AXI_HP3_WLAST,
+  input S_AXI_HP3_WRISSUECAP1_EN,
+  input S_AXI_HP3_WVALID,
+  input [1:0] S_AXI_HP3_ARBURST,
+  input [1:0] S_AXI_HP3_ARLOCK,
+  input [2:0] S_AXI_HP3_ARSIZE,
+  input [1:0] S_AXI_HP3_AWBURST,
+  input [1:0] S_AXI_HP3_AWLOCK,
+  input [2:0] S_AXI_HP3_AWSIZE,
+  input [2:0] S_AXI_HP3_ARPROT,
+  input [2:0] S_AXI_HP3_AWPROT,
+  input [31:0] S_AXI_HP3_ARADDR,
+  input [31:0] S_AXI_HP3_AWADDR,
+  input [3:0] S_AXI_HP3_ARCACHE,
+  input [3:0] S_AXI_HP3_ARLEN,
+  input [3:0] S_AXI_HP3_ARQOS,
+  input [3:0] S_AXI_HP3_AWCACHE,
+  input [3:0] S_AXI_HP3_AWLEN,
+  input [3:0] S_AXI_HP3_AWQOS,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
+  input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
+  input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,  
+  
+  //FIO ========================================
+
+  //IRQ
+  //output [28:0] IRQ_P2F,
+  output IRQ_P2F_DMAC_ABORT ,
+  output IRQ_P2F_DMAC0,
+  output IRQ_P2F_DMAC1,
+  output IRQ_P2F_DMAC2,
+  output IRQ_P2F_DMAC3,
+  output IRQ_P2F_DMAC4,
+  output IRQ_P2F_DMAC5,
+  output IRQ_P2F_DMAC6,
+  output IRQ_P2F_DMAC7,
+  output IRQ_P2F_SMC,
+  output IRQ_P2F_QSPI,
+  output IRQ_P2F_CTI,
+  output IRQ_P2F_GPIO,
+  output IRQ_P2F_USB0,
+  output IRQ_P2F_ENET0,
+  output IRQ_P2F_ENET_WAKE0,
+  output IRQ_P2F_SDIO0,
+  output IRQ_P2F_I2C0,
+  output IRQ_P2F_SPI0,
+  output IRQ_P2F_UART0,
+  output IRQ_P2F_CAN0,
+  output IRQ_P2F_USB1,
+  output IRQ_P2F_ENET1,
+  output IRQ_P2F_ENET_WAKE1,
+  output IRQ_P2F_SDIO1,
+  output IRQ_P2F_I2C1,
+  output IRQ_P2F_SPI1,
+  output IRQ_P2F_UART1,
+  output IRQ_P2F_CAN1,
+  input  [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
+  input         Core0_nFIQ,
+  input         Core0_nIRQ,
+  input         Core1_nFIQ,
+  input         Core1_nIRQ,
+
+  //DMA
+
+  output [1:0] DMA0_DATYPE,  
+  output DMA0_DAVALID,
+  output DMA0_DRREADY,
+  output DMA0_RSTN,  
+  output [1:0] DMA1_DATYPE,  
+  output DMA1_DAVALID,
+  output DMA1_DRREADY,
+  output DMA1_RSTN,  
+  output [1:0] DMA2_DATYPE,  
+  output DMA2_DAVALID,
+  output DMA2_DRREADY,
+  output DMA2_RSTN,  
+  output [1:0] DMA3_DATYPE,    
+  output DMA3_DAVALID,
+  output DMA3_DRREADY,
+  output DMA3_RSTN,  
+  input DMA0_ACLK,
+  input DMA0_DAREADY,
+  input DMA0_DRLAST,
+  input DMA0_DRVALID,
+  input DMA1_ACLK,
+  input DMA1_DAREADY,
+  input DMA1_DRLAST,
+  input DMA1_DRVALID,
+  input DMA2_ACLK,
+  input DMA2_DAREADY,
+  input DMA2_DRLAST,
+  input DMA2_DRVALID,
+  input DMA3_ACLK,
+  input DMA3_DAREADY,
+  input DMA3_DRLAST,
+  input DMA3_DRVALID,  
+  input [1:0] DMA0_DRTYPE,
+  input [1:0] DMA1_DRTYPE,
+  input [1:0] DMA2_DRTYPE,
+  input [1:0] DMA3_DRTYPE,
+  
+  //FCLK
+  output    FCLK_CLK3,
+  output    FCLK_CLK2,
+  output    FCLK_CLK1,
+  output    FCLK_CLK0,
+ 
+  input     FCLK_CLKTRIG3_N,
+  input     FCLK_CLKTRIG2_N,
+  input     FCLK_CLKTRIG1_N,
+  input     FCLK_CLKTRIG0_N,
+ 
+  output    FCLK_RESET3_N,
+  output    FCLK_RESET2_N,
+  output    FCLK_RESET1_N,
+  output    FCLK_RESET0_N,
+
+  //FTMD
+  input    [31:0] FTMD_TRACEIN_DATA,
+  input           FTMD_TRACEIN_VALID,
+  input           FTMD_TRACEIN_CLK,
+  input    [3:0]  FTMD_TRACEIN_ATID,
+
+  //FTMT
+  input     FTMT_F2P_TRIG_0,
+  output    FTMT_F2P_TRIGACK_0,
+  input     FTMT_F2P_TRIG_1,
+  output    FTMT_F2P_TRIGACK_1,
+  input     FTMT_F2P_TRIG_2,
+  output    FTMT_F2P_TRIGACK_2,
+  input     FTMT_F2P_TRIG_3,
+  output    FTMT_F2P_TRIGACK_3'b',
+  input     [31:0] FTMT_F2P_DEBUG,  
+  input     FTMT_P2F_TRIGACK_0,
+  output    FTMT_P2F_TRIG_0,
+  input     FTMT_P2F_TRIGACK_1,
+  output    FTMT_P2F_TRIG_1,
+  input     FTMT_P2F_TRIGACK_2,
+  output    FTMT_P2F_TRIG_2,
+  input     FTMT_P2F_TRIGACK_3,
+  output    FTMT_P2F_TRIG_3,
+  output    [31:0] FTMT_P2F_DEBUG,
+
+  //FIDLE
+  input           FPGA_IDLE_N,
+  
+  //EVENT
+
+  output EVENT_EVENTO,
+  output [1:0] EVENT_STANDBYWFE,
+  output [1:0] EVENT_STANDBYWFI,  
+  input EVENT_EVENTI,   
+  
+
+  //DARB
+  input     [3:0] DDR_ARB,
+  inout     [C_MIO_PRIMITIVE - 1:0] MIO,  
+  
+  //DDR
+  inout         DDR_CAS_n,       // CASB
+  inout         DDR_CKE,         // CKE
+  inout         DDR_Clk_n,       // CKN
+  inout         DDR_Clk,         // CKP
+  inout         DDR_CS_n,        // CSB 
+  inout         DDR_DRSTB,       // DDR_DRSTB  
+  inout         DDR_ODT,         // ODT
+  inout         DDR_RAS_n,       // RASB
+  inout         DDR_WEB,
+  inout  [2:0]  DDR_BankAddr,    // BA  
+  inout  [14:0] DDR_Addr,        // A
+  
+  inout          DDR_VRN,
+  inout          DDR_VRP,
+  inout   [C_DM_WIDTH - 1:0]  DDR_DM,          // DM  
+  inout   [C_DQ_WIDTH - 1:0] DDR_DQ,          // DQ
+  inout   [C_DQS_WIDTH -1:0]  DDR_DQS_n,       // DQSN
+  inout   [C_DQS_WIDTH - 1:0]  DDR_DQS,         // DQSP
+  
+  inout          PS_SRSTB,        // SRSTB    
+  inout          PS_CLK,          // CLK
+  inout          PS_PORB         // PORB 
+
+
+);
+
+wire [11:0]  M_AXI_GP0_AWID_FULL;
+wire [11:0]  M_AXI_GP0_WID_FULL;
+wire [11:0]  M_AXI_GP0_ARID_FULL;
+
+wire [11:0]  M_AXI_GP0_BID_FULL;
+wire [11:0]  M_AXI_GP0_RID_FULL;
+
+wire [11:0]  M_AXI_GP1_AWID_FULL;
+wire [11:0]  M_AXI_GP1_WID_FULL;
+wire [11:0]  M_AXI_GP1_ARID_FULL;
+
+wire [11:0]  M_AXI_GP1_BID_FULL;
+wire [11:0]  M_AXI_GP1_RID_FULL;
+
+wire [3:0] M_AXI_GP0_ARCACHE_t;
+wire [3:0] M_AXI_GP1_ARCACHE_t;
+wire [3:0] M_AXI_GP0_AWCACHE_t;
+wire [3:0] M_AXI_GP1_AWCACHE_t;
+
+
+// Wires for connecting to the PS7
+wire    ENET0_GMII_TX_EN_i;
+wire    ENET0_GMII_TX_ER_i;
+reg          ENET0_GMII_COL_i;
+reg          ENET0_GMII_CRS_i;
+reg          ENET0_GMII_RX_DV_i;
+reg          ENET0_GMII_RX_ER_i;
+reg [7:0]    ENET0_GMII_RXD_i;
+wire [7:0]   ENET0_GMII_TXD_i;
+
+wire         ENET1_GMII_TX_EN_i;
+wire         ENET1_GMII_TX_ER_i;
+reg          ENET1_GMII_COL_i;
+reg          ENET1_GMII_CRS_i;
+reg          ENET1_GMII_RX_DV_i;
+reg          ENET1_GMII_RX_ER_i;
+reg [7:0]   ENET1_GMII_RXD_i;
+wire [7:0]   ENET1_GMII_TXD_i;
+
+reg    [31:0] FTMD_TRACEIN_DATA_notracebuf;
+reg           FTMD_TRACEIN_VALID_notracebuf;
+reg    [3:0]  FTMD_TRACEIN_ATID_notracebuf;
+
+wire    [31:0] FTMD_TRACEIN_DATA_i;
+wire           FTMD_TRACEIN_VALID_i;
+wire    [3:0]  FTMD_TRACEIN_ATID_i;
+
+wire    [31:0] FTMD_TRACEIN_DATA_tracebuf;
+wire           FTMD_TRACEIN_VALID_tracebuf;
+wire    [3:0]  FTMD_TRACEIN_ATID_tracebuf;
+
+wire [5:0]    S_AXI_GP0_BID_out;
+wire [5:0]    S_AXI_GP0_RID_out;
+wire [5:0]    S_AXI_GP0_ARID_in;
+wire [5:0]    S_AXI_GP0_AWID_in;
+wire [5:0]    S_AXI_GP0_WID_in;
+
+wire [5:0]    S_AXI_GP1_BID_out;
+wire [5:0]    S_AXI_GP1_RID_out;
+wire [5:0]    S_AXI_GP1_ARID_in;
+wire [5:0]    S_AXI_GP1_AWID_in;
+wire [5:0]    S_AXI_GP1_WID_in;
+
+wire [5:0]    S_AXI_HP0_BID_out;
+wire [5:0]    S_AXI_HP0_RID_out;
+wire [5:0]    S_AXI_HP0_ARID_in;
+wire [5:0]    S_AXI_HP0_AWID_in;
+wire [5:0]    S_AXI_HP0_WID_in;
+
+wire [5:0]    S_AXI_HP1_BID_out;
+wire [5:0]    S_AXI_HP1_RID_out;
+wire [5:0]    S_AXI_HP1_ARID_in;
+wire [5:0]    S_AXI_HP1_AWID_in;
+wire [5:0]    S_AXI_HP1_WID_in;
+
+wire [5:0]    S_AXI_HP2_BID_out;
+wire [5:0]    S_AXI_HP2_RID_out;
+wire [5:0]    S_AXI_HP2_ARID_in;
+wire [5:0]    S_AXI_HP2_AWID_in;
+wire [5:0]    S_AXI_HP2_WID_in;
+
+wire [5:0]    S_AXI_HP3_BID_out;
+wire [5:0]    S_AXI_HP3_RID_out;
+wire [5:0]    S_AXI_HP3_ARID_in;
+wire [5:0]    S_AXI_HP3_AWID_in;
+wire [5:0]    S_AXI_HP3_WID_in;
+
+wire [2:0]    S_AXI_ACP_BID_out;
+wire [2:0]    S_AXI_ACP_RID_out;
+wire [2:0]    S_AXI_ACP_ARID_in;
+wire [2:0]    S_AXI_ACP_AWID_in;
+wire [2:0]    S_AXI_ACP_WID_in;  
+
+wire [63:0]   S_AXI_HP0_WDATA_in;
+wire [7:0]    S_AXI_HP0_WSTRB_in;
+wire [63:0]   S_AXI_HP0_RDATA_out;
+
+wire [63:0]   S_AXI_HP1_WDATA_in;
+wire [7:0]    S_AXI_HP1_WSTRB_in;
+wire [63:0]   S_AXI_HP1_RDATA_out;
+
+wire [63:0]   S_AXI_HP2_WDATA_in;
+wire [7:0]    S_AXI_HP2_WSTRB_in;
+wire [63:0]   S_AXI_HP2_RDATA_out;
+
+wire [63:0]   S_AXI_HP3_WDATA_in;
+wire [7:0]    S_AXI_HP3_WSTRB_in;
+wire [63:0]   S_AXI_HP3_RDATA_out;
+ 
+wire [1:0]    M_AXI_GP0_ARSIZE_i;
+wire [1:0]    M_AXI_GP0_AWSIZE_i;
+
+wire [1:0]    M_AXI_GP1_ARSIZE_i;
+wire [1:0]    M_AXI_GP1_AWSIZE_i;
+
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPBID_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPRID_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPARID_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPAWID_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPWID_W;  
+
+
+wire SAXIACPARREADY_W;
+wire SAXIACPAWREADY_W;
+wire SAXIACPBVALID_W;
+wire SAXIACPRLAST_W;
+wire SAXIACPRVALID_W;
+wire SAXIACPWREADY_W;  
+wire [1:0] SAXIACPBRESP_W;
+wire [1:0] SAXIACPRRESP_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
+wire [63:0] SAXIACPRDATA_W;
+  
+wire S_AXI_ATC_ARVALID;
+wire S_AXI_ATC_AWVALID;
+wire S_AXI_ATC_BREADY;
+wire S_AXI_ATC_RREADY;
+wire S_AXI_ATC_WLAST;
+wire S_AXI_ATC_WVALID;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
+wire [2:0] S_AXI_ATC_ARPROT;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
+wire [2:0] S_AXI_ATC_AWPROT;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
+wire [31:0] S_AXI_ATC_ARADDR;
+wire [31:0] S_AXI_ATC_AWADDR;
+wire [3:0] S_AXI_ATC_ARCACHE;
+wire [3:0] S_AXI_ATC_ARLEN;
+wire [3:0] S_AXI_ATC_ARQOS;
+wire [3:0] S_AXI_ATC_AWCACHE;
+wire [3:0] S_AXI_ATC_AWLEN;
+wire [3:0] S_AXI_ATC_AWQOS;  
+wire [1:0] S_AXI_ATC_ARBURST;
+wire [1:0] S_AXI_ATC_ARLOCK;
+wire [2:0] S_AXI_ATC_ARSIZE;
+wire [1:0] S_AXI_ATC_AWBURST;
+wire [1:0] S_AXI_ATC_AWLOCK;
+wire [2:0] S_AXI_ATC_AWSIZE;
+wire [4:0] S_AXI_ATC_ARUSER;
+wire [4:0] S_AXI_ATC_AWUSER;
+wire [63:0] S_AXI_ATC_WDATA;
+wire [7:0] S_AXI_ATC_WSTRB;  
+
+
+wire SAXIACPARVALID_W;
+wire SAXIACPAWVALID_W;
+wire SAXIACPBREADY_W;
+wire SAXIACPRREADY_W;
+wire SAXIACPWLAST_W;
+wire SAXIACPWVALID_W;
+wire [2:0] SAXIACPARPROT_W;
+wire [2:0] SAXIACPAWPROT_W;
+wire [31:0] SAXIACPARADDR_W;
+wire [31:0] SAXIACPAWADDR_W;
+wire [3:0] SAXIACPARCACHE_W;
+wire [3:0] SAXIACPARLEN_W;
+wire [3:0] SAXIACPARQOS_W;
+wire [3:0] SAXIACPAWCACHE_W;
+wire [3:0] SAXIACPAWLEN_W;
+wire [3:0] SAXIACPAWQOS_W;  
+wire [1:0] SAXIACPARBURST_W;
+wire [1:0] SAXIACPARLOCK_W;
+wire [2:0] SAXIACPARSIZE_W;
+wire [1:0] SAXIACPAWBURST_W;
+wire [1:0] SAXIACPAWLOCK_W;
+wire [2:0] SAXIACPAWSIZE_W;
+wire [4:0] SAXIACPARUSER_W;
+wire [4:0] SAXIACPAWUSER_W;
+wire [63:0] SAXIACPWDATA_W;
+wire [7:0] SAXIACPWSTRB_W;
+
+// AxUSER signal update
+wire [4:0] param_aruser;
+wire [4:0] param_awuser;
+
+// Added to address CR 651751
+wire [3:0]   fclk_clktrig_gnd = 4\'h0;
+
+
+wire [19:0]   irq_f2p_i;
+wire [15:0]   irq_f2p_null = 16\'h0000;
+
+// EMIO I2C0
+wire          I2C0_SDA_T_n;
+wire          I2C0_SCL_T_n;
+// EMIO I2C1
+wire          I2C1_SDA_T_n;
+wire          I2C1_SCL_T_n;
+// EMIO SPI0
+wire          SPI0_SCLK_T_n;
+wire          SPI0_MOSI_T_n;
+wire          SPI0_MISO_T_n;
+wire          SPI0_SS_T_n;
+// EMIO SPI1
+wire          SPI1_SCLK_T_n;
+wire          SPI1_MOSI_T_n;
+wire          SPI1_MISO_T_n;
+wire          SPI1_SS_T_n;
+
+// EMIO GEM0
+wire          ENET0_MDIO_T_n;
+
+// EMIO GEM1
+wire          ENET1_MDIO_T_n;
+
+// EMIO GPIO
+wire  [(C_EMIO_GPIO_WIDTH-1):0]        GPIO_T_n;
+
+wire [63:0]   gpio_out_t_n;
+wire [63:0]   gpio_out;
+wire [63:0]   gpio_in63_0;
+
+//For Clock buffering
+wire    [3:0] FCLK_CLK_unbuffered;
+wire    [3:0] FCLK_CLK_buffered;
+wire   \t\t  FCLK_CLK0_temp;
+
+// EMIO PJTAG
+wire          PJTAG_TDO_O;
+wire          PJTAG_TDO_T;
+wire          PJTAG_TDO_T_n;
+
+// EMIO SDIO0
+wire          SDIO0_CMD_T_n;
+wire [3:0]    SDIO0_DATA_T_n;
+
+// EMIO SDIO1
+wire          SDIO1_CMD_T_n;
+wire [3:0]    SDIO1_DATA_T_n;
+
+// buffered IO
+wire  [C_MIO_PRIMITIVE - 1:0]  buffered_MIO;
+wire  buffered_DDR_WEB;
+wire  buffered_DDR_CAS_n;
+wire  buffered_DDR_CKE;
+wire  buffered_DDR_Clk_n;
+wire  buffered_DDR_Clk;
+wire  buffered_DDR_CS_n; 
+wire  buffered_DDR_DRSTB;  
+wire  buffered_DDR_ODT;
+wire  buffered_DDR_RAS_n;
+wire  [2:0]  buffered_DDR_BankAddr; 
+wire  [14:0]  buffered_DDR_Addr;
+  
+wire  buffered_DDR_VRN;
+wire  buffered_DDR_VRP;
+wire  [C_DM_WIDTH - 1:0]  buffered_DDR_DM;  
+wire  [C_DQ_WIDTH - 1:0]  buffered_DDR_DQ;
+wire  [C_DQS_WIDTH -1:0]  buffered_DDR_DQS_n;
+wire  [C_DQS_WIDTH - 1:0]  buffered_DDR_DQS;
+  
+wire  buffered_PS_SRSTB; 
+wire  buffered_PS_CLK;
+wire  buffered_PS_PORB;
+
+wire S_AXI_HP0_ACLK_temp;
+wire S_AXI_HP1_ACLK_temp;
+wire S_AXI_HP2_ACLK_temp;
+wire S_AXI_HP3_ACLK_temp;
+wire M_AXI_GP0_ACLK_temp;
+wire M_AXI_GP1_ACLK_temp;
+wire S_AXI_GP0_ACLK_temp;
+wire S_AXI_GP1_ACLK_temp;
+wire S_AXI_ACP_ACLK_temp;
+
+wire [31:0] TRACE_DATA_i;
+wire TRACE_CTL_i;
+(* keep = ""true"" *) reg   TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
+(* keep = ""true"" *) reg   [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
+
+// fixed CR #665394
+integer j;
+generate
+  if (C_EN_EMIO_TRACE == 1) begin 
+    always @(posedge TRACE_CLK) 
+    begin
+\t  TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
+\t  TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
+\t  for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
+\t\tTRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
+\t\tTRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
+      end
+\t  TRACE_CLK_OUT  <= ~TRACE_CLK_OUT;
+\tend
+  end\t
+else
+begin
+always @*
+begin
+TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1\'b0;
+  TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1\'b0; 
+  for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
+  TRACE_CTL_PIPE[j-1] <= 1\'b0;
+\t\tTRACE_DATA_PIPE[j-1] <= 1\'b0;
+\t\tend
+  TRACE_CLK_OUT  <= 1\'b0; 
+  end
+end
+endgenerate
+
+assign TRACE_CTL = TRACE_CTL_PIPE[0];
+
+assign TRACE_DATA = TRACE_DATA_PIPE[0];
+
+//irq_p2f
+
+// Updated IRQ_F2P logic to address CR 641523
+generate 
+  if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
+    assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
+  end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
+    assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
+  end else begin : irq_f2p_select
+\tif (C_IRQ_F2P_MODE == ""DIRECT"") begin
+    assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
+\t\t\t\tirq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
+\t\t\t\tIRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
+\tend else begin
+\tassign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
+\t\t\t\tIRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
+\t\t\t\tirq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
+\tend
+  end
+endgenerate
+
+assign M_AXI_GP0_ARSIZE[2:0] = {1\'b0, M_AXI_GP0_ARSIZE_i[1:0]};
+assign M_AXI_GP0_AWSIZE[2:0] = {1\'b0, M_AXI_GP0_AWSIZE_i[1:0]};
+assign M_AXI_GP1_ARSIZE[2:0] = {1\'b0, M_AXI_GP1_ARSIZE_i[1:0]};
+assign M_AXI_GP1_AWSIZE[2:0] = {1\'b0, M_AXI_GP1_AWSIZE_i[1:0]};
+
+
+
+// Compress Function
+
+   
+// Modified as per CR 631955   
+//function [11:0] uncompress_id; 
+//   input [5:0] id; 
+//      begin 
+//         case (id[5:0]) 
+//            // dmac0 
+//            6\'d1 : uncompress_id = 12\'b010000_1000_00 ; 
+//            6\'d2 : uncompress_id = 12\'b010000_0000_00 ; 
+//            6\'d3 : uncompress_id = 12\'b010000_0001_00 ; 
+//            6\'d4 : uncompress_id = 12\'b010000_0010_00 ; 
+//            6\'d5 : uncompress_id = 12\'b010000_0011_00 ; 
+//            6\'d6 : uncompress_id = 12\'b010000_0100_00 ; 
+//            6\'d7 : uncompress_id = 12\'b010000_0101_00 ; 
+//            6\'d8 : uncompress_id = 12\'b010000_0110_00 ; 
+//            6\'d9 : uncompress_id = 12\'b010000_0111_00 ; 
+//            // ioum 
+//            6\'d10 : uncompress_id = 12\'b0100000_000_01 ; 
+//            6\'d11 : uncompress_id = 12\'b0100000_001_01 ; 
+//            6\'d12 : uncompress_id = 12\'b0100000_010_01 ; 
+//            6\'d13 : uncompress_id = 12\'b0100000_011_01 ; 
+//            6\'d14 : uncompress_id = 12\'b0100000_100_01 ; 
+//            6\'d15 : uncompress_id = 12\'b0100000_101_01 ; 
+//            // devci 
+//            6\'d16 : uncompress_id = 12\'b1000_0000_0000 ; 
+//            // dap 
+//            6\'d17 : uncompress_id = 12\'b1000_0000_0001 ; 
+//            // l2m1 (CPU000) 
+//            6\'d18 : uncompress_id = 12\'b11_000_000_00_00 ; 
+//            6\'d19 : uncompress_id = 12\'b11_010_000_00_00 ; 
+//            6\'d20 : uncompress_id = 12\'b11_011_000_00_00 ; 
+//            6\'d21 : uncompress_id = 12\'b11_100_000_00_00 ; 
+//            6\'d22 : uncompress_id = 12\'b11_101_000_00_00 ; 
+//            6\'d23 : uncompress_id = 12\'b11_110_000_00_00 ; 
+//            6\'d24 : uncompress_id = 12\'b11_111_000_00_00 ; 
+//            // l2m1 (CPU001) 
+//            6\'d25 : uncompress_id = 12\'b11_000_001_00_00 ; 
+//            6\'d26 : uncompress_id = 12\'b11_010_001_00_00 ; 
+//            6\'d27 : uncompress_id = 12\'b11_011_001_00_00 ; 
+//            6\'d28 : uncompress_id = 12\'b11_100_001_00_00 ; 
+//            6\'d29 : uncompress_id = 12\'b11_101_001_00_00 ; 
+//            6\'d30 : uncompress_id = 12\'b11_110_001_00_00 ; 
+//            6\'d31 : uncompress_id = 12\'b11_111_001_00_00 ; 
+//            // l2m1 (L2CC) 
+//            6\'d32 : uncompress_id = 12\'b11_000_00101_00 ; 
+//            6\'d33 : uncompress_id = 12\'b11_000_01001_00 ; 
+//            6\'d34 : uncompress_id = 12\'b11_000_01101_00 ; 
+//            6\'d35 : uncompress_id = 12\'b11_000_10011_00 ; 
+//            6\'d36 : uncompress_id = 12\'b11_000_10111_00 ; 
+//            6\'d37 : uncompress_id = 12\'b11_000_11011_00 ; 
+//            6\'d38 : uncompress_id = 12\'b11_000_11111_00 ; 
+//            6\'d39 : uncompress_id = 12\'b11_000_00011_00 ; 
+//            6\'d40 : uncompress_id = 12\'b11_000_00111_00 ; 
+//            6\'d41 : uncompress_id = 12\'b11_000_01011_00 ; 
+//            6\'d42 : uncompress_id = 12\'b11_000_01111_00 ; 
+//            6\'d43 : uncompress_id = 12\'b11_000_00001_00 ; 
+//            // l2m1 (ACP) 
+//            6\'d44 : uncompress_id = 12\'b11_000_10000_00 ; 
+//            6\'d45 : uncompress_id = 12\'b11_001_10000_00 ; 
+//            6\'d46 : uncompress_id = 12\'b11_010_10000_00 ; 
+//            6\'d47 : uncompress_id = 12\'b11_011_10000_00 ; 
+//            6\'d48 : uncompress_id = 12\'b11_100_10000_00 ; 
+//            6\'d49 : uncompress_id = 12\'b11_101_10000_00 ; 
+//            6\'d50 : uncompress_id = 12\'b11_110_10000_00 ; 
+//            6\'d51 : uncompress_id = 12\'b11_111_10000_00 ; 
+//         default : uncompress_id = ~0; 
+//      endcase 
+//   end 
+//endfunction 
+// 
+//function [5:0] compress_id; 
+//   input [11:0] id; 
+//      begin 
+//         case (id[11:0]) 
+//         // dmac0 
+//            12\'b010000_1000_00 : compress_id = \'d1 ; 
+//            12\'b010000_0000_00 : compress_id = \'d2 ; 
+//            12\'b010000_0001_00 : compress_id = \'d3 ; 
+//            12\'b010000_0010_00 : compress_id = \'d4 ; 
+//            12\'b010000_0011_00 : compress_id = \'d5 ; 
+//            12\'b010000_0100_00 : compress_id = \'d6 ; 
+//            12\'b010000_0101_00 : compress_id = \'d7 ; 
+//            12\'b010000_0110_00 : compress_id = \'d8 ; 
+//            12\'b010000_0111_00 : compress_id = \'d9 ; 
+//            // ioum 
+//            12\'b0100000_000_01 : compress_id = \'d10 ; 
+//            12\'b0100000_001_01 : compress_id = \'d11 ; 
+//            12\'b0100000_010_01 : compress_id = \'d12 ; 
+//            12\'b0100000_011_01 : compress_id = \'d13 ; 
+//            12\'b0100000_100_01 : compress_id = \'d14 ; 
+//            12\'b0100000_101_01 : compress_id = \'d15 ; 
+//            // devci 
+//            12\'b1000_0000_0000 : compress_id = \'d16 ; 
+//            // dap 
+//            12\'b1000_0000_0001 : compress_id = \'d17 ; 
+//            // l2m1 (CPU000) 
+//            12\'b11_000_000_00_00 : compress_id = \'d18 ; 
+//            12\'b11_010_000_00_00 : compress_id = \'d19 ; 
+//            12\'b11_011_000_00_00 : compress_id = \'d20 ; 
+//            12\'b11_100_000_00_00 : compress_id = \'d21 ; 
+//            12\'b11_101_000_00_00 : compress_id = \'d22 ; 
+//            12\'b11_110_000_00_00 : compress_id = \'d23 ; 
+//            12\'b11_111_000_00_00 : compress_id = \'d24 ; 
+//            // l2m1 (CPU001) 
+//            12\'b11_000_001_00_00 : compress_id = \'d25 ; 
+//            12\'b11_010_001_00_00 : compress_id = \'d26 ; 
+//            12\'b11_011_001_00_00 : compress_id = \'d27 ; 
+//            12\'b11_100_001_00_00 : compress_id = \'d28 ; 
+//            12\'b11_101_001_00_00 : compress_id = \'d29 ; 
+//            12\'b11_110_001_00_00 : compress_id = \'d30 ; 
+//            12\'b11_111_001_00_00 : compress_id = \'d31 ; 
+//            // l2m1 (L2CC) 
+//            12\'b11_000_00101_00 : compress_id = \'d32 ; 
+//            12\'b11_000_01001_00 : compress_id = \'d33 ; 
+//            12\'b11_000_01101_00 : compress_id = \'d34 ; 
+//            12\'b11_000_10011_00 : compress_id = \'d35 ; 
+//            12\'b11_000_10111_00 : compress_id = \'d36 ; 
+//            12\'b11_000_11011_00 : compress_id = \'d37 ; 
+//            12\'b11_000_11111_00 : compress_id = \'d38 ; 
+//            12\'b11_000_00011_00 : compress_id = \'d39 ; 
+//            12\'b11_000_00111_00 : compress_id = \'d40 ; 
+//            12\'b11_000_01011_00 : compress_id = \'d41 ; 
+//            12\'b11_000_01111_00 : compress_id = \'d42 ; 
+//            12\'b11_000_00001_00 : compress_id = \'d43 ; 
+//            // l2m1 (ACP) 
+//            12\'b11_000_10000_00 : compress_id = \'d44 ; 
+//            12\'b11_001_10000_00 : compress_id = \'d45 ; 
+//            12\'b11_010_10000_00 : compress_id = \'d46 ; 
+//            12\'b11_011_10000_00 : compress_id = \'d47 ; 
+//            12\'b11_100_10000_00 : compress_id = \'d48 ; 
+//            12\'b11_101_10000_00 : compress_id = \'d49 ; 
+//            12\'b11_110_10000_00 : compress_id = \'d50 ; 
+//            12\'b11_111_10000_00 : compress_id = \'d51 ; 
+//         default: compress_id = ~0; 
+//      endcase 
+//   end 
+//endfunction 
+
+// Modified as per CR 648393
+
+\tfunction [5:0] compress_id; 
+\t\tinput [11:0] id; 
+\t\t\tbegin 
+\t\t\t\tcompress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]); 
+\t\t\t\tcompress_id[1] = id[8] | id[5] | (~id[11] & id[3]); 
+\t\t\t\tcompress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]); 
+\t\t\t\tcompress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]); 
+\t\t\t\tcompress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]); 
+\t\t\t\tcompress_id[5] = id[11] & id[10] & ~id[3]; 
+\t\t\tend 
+\tendfunction 
+
+\tfunction [11:0] uncompress_id; 
+\t\tinput [5:0] id; 
+\t\t\tbegin 
+\t\t\t\tcase (id[5:0]) 
+\t\t\t\t\t// dmac0 
+\t\t\t\t\t6\'b000_010 : uncompress_id = 12\'b010000_1000_00 ; 
+\t\t\t\t\t6\'b001_000 : uncompress_id = 12\'b010000_0000_00 ; 
+\t\t\t\t\t6\'b001_001 : uncompress_id = 12\'b010000_0001_00 ; 
+\t\t\t\t\t6\'b001_010 : uncompress_id = 12\'b010000_0010_00 ; 
+\t\t\t\t\t6\'b001_011 : uncompress_id = 12\'b010000_0011_00 ; 
+\t\t\t\t\t6\'b001_100 : uncompress_id = 12\'b010000_0100_00 ; 
+\t\t\t\t\t6\'b001_101 : uncompress_id = 12\'b010000_0101_00 ; 
+\t\t\t\t\t6\'b001_110 : uncompress_id = 12\'b010000_0110_00 ; 
+\t\t\t\t\t6\'b001_111 : uncompress_id = 12\'b010000_0111_00 ; 
+\t\t\t\t\t// ioum 
+\t\t\t\t\t6\'b010_000 : uncompress_id = 12\'b0100000_000_01 ; 
+\t\t\t\t\t6\'b010_001 : uncompress_id = 12\'b0100000_001_01 ; 
+\t\t\t\t\t6\'b010_010 : uncompress_id = 12\'b0100000_010_01 ; 
+\t\t\t\t\t6\'b010_011 : uncompress_id = 12\'b0100000_011_01 ; 
+\t\t\t\t\t6\'b010_100 : uncompress_id = 12\'b0100000_100_01 ; 
+\t\t\t\t\t6\'b010_101 : uncompress_id = 12\'b0100000_101_01 ; 
+\t\t\t\t\t// devci 
+\t\t\t\t\t6\'b000_000 : uncompress_id = 12\'b1000_0000_0000 ; 
+\t\t\t\t\t// dap 
+\t\t\t\t\t6\'b000_001 : uncompress_id = 12\'b1000_0000_0001 ; 
+\t\t\t\t\t// l2m1 (CPU000) 
+\t\t\t\t\t6\'b110_000 : uncompress_id = 12\'b11_000_000_00_00 ; 
+\t\t\t\t\t6\'b110_010 : uncompress_id = 12\'b11_010_000_00_00 ; 
+\t\t\t\t\t6\'b110_011 : uncompress_id = 12\'b11_011_000_00_00 ; 
+\t\t\t\t\t6\'b110_100 : uncompress_id = 12\'b11_100_000_00_00 ; 
+\t\t\t\t\t6\'b110_101 : uncompress_id = 12\'b11_101_000_00_00 ; 
+\t\t\t\t\t6\'b110_110 : uncompress_id = 12\'b11_110_000_00_00 ; 
+\t\t\t\t\t6\'b110_111 : uncompress_id = 12\'b11_111_000_00_00 ; 
+\t\t\t\t\t// l2m1 (CPU001) 
+\t\t\t\t\t6\'b111_000 : uncompress_id = 12\'b11_000_001_00_00 ; 
+\t\t\t\t\t6\'b111_010 : uncompress_id = 12\'b11_010_001_00_00 ; 
+\t\t\t\t\t6\'b111_011 : uncompress_id = 12\'b11_011_001_00_00 ; 
+\t\t\t\t\t6\'b111_100 : uncompress_id = 12\'b11_100_001_00_00 ; 
+\t\t\t\t\t6\'b111_101 : uncompress_id = 12\'b11_101_001_00_00 ; 
+\t\t\t\t\t6\'b111_110 : uncompress_id = 12\'b11_110_001_00_00 ; 
+\t\t\t\t\t6\'b111_111 : uncompress_id = 12\'b11_111_001_00_00 ; 
+\t\t\t\t\t// l2m1 (L2CC) 
+\t\t\t\t\t6\'b101_001 : uncompress_id = 12\'b11_000_00101_00 ; 
+\t\t\t\t\t6\'b101_010 : uncompress_id = 12\'b11_000_01001_00 ; 
+\t\t\t\t\t6\'b101_011 : uncompress_id = 12\'b11_000_01101_00 ; 
+\t\t\t\t\t6\'b011_100 : uncompress_id = 12\'b11_000_10011_00 ; 
+\t\t\t\t\t6\'b011_101 : uncompress_id = 12\'b11_000_10111_00 ; 
+\t\t\t\t\t6\'b011_110 : uncompress_id = 12\'b11_000_11011_00 ; 
+\t\t\t\t\t6\'b011_111 : uncompress_id = 12\'b11_000_11111_00 ; 
+\t\t\t\t\t6\'b011_000 : uncompress_id = 12\'b11_000_00011_00 ; 
+\t\t\t\t\t6\'b011_001 : uncompress_id = 12\'b11_000_00111_00 ; 
+\t\t\t\t\t6\'b011_010 : uncompress_id = 12\'b11_000_01011_00 ; 
+\t\t\t\t\t6\'b011_011 : uncompress_id = 12\'b11_000_01111_00 ; 
+\t\t\t\t\t6\'b101_000 : uncompress_id = 12\'b11_000_00001_00 ; 
+\t\t\t\t\t// l2m1 (ACP) 
+\t\t\t\t\t6\'b100_000 : uncompress_id = 12\'b11_000_10000_00 ; 
+\t\t\t\t\t6\'b100_001 : uncompress_id = 12\'b11_001_10000_00 ; 
+\t\t\t\t\t6\'b100_010 : uncompress_id = 12\'b11_010_10000_00 ; 
+\t\t\t\t\t6\'b100_011 : uncompress_id = 12\'b11_011_10000_00 ; 
+\t\t\t\t\t6\'b100_100 : uncompress_id = 12\'b11_100_10000_00 ; 
+\t\t\t\t\t6\'b100_101 : uncompress_id = 12\'b11_101_10000_00 ; 
+\t\t\t\t\t6\'b100_110 : uncompress_id = 12\'b11_110_10000_00 ; 
+\t\t\t\t\t6\'b100_111 : uncompress_id = 12\'b11_111_10000_00 ; 
+\t\t\t\t\tdefault : uncompress_id = 12\'hx ; 
+\t\t\t\tendcase 
+\t\t\tend 
+\tendfunction
+
+   
+// Static Remap logic Enablement and Disablement for C_M_AXI0 port
+        
+        assign M_AXI_GP0_AWID        = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
+        assign M_AXI_GP0_WID         = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL)  : M_AXI_GP0_WID_FULL;   
+        assign M_AXI_GP0_ARID        = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;      
+        assign M_AXI_GP0_BID_FULL    = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID)     : M_AXI_GP0_BID;
+        assign M_AXI_GP0_RID_FULL    = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID)     : M_AXI_GP0_RID;      
+
+  // Static Remap logic Enablement and Disablement for C_M_AXI1 port   
+
+        assign M_AXI_GP1_AWID        = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
+        assign M_AXI_GP1_WID         = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL)  : M_AXI_GP1_WID_FULL;   
+        assign M_AXI_GP1_ARID        = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;      
+        assign M_AXI_GP1_BID_FULL    = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID)     : M_AXI_GP1_BID;
+        assign M_AXI_GP1_RID_FULL    = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID)     : M_AXI_GP1_RID;      
+
+
+//// Compress_id and uncompress_id has been removed to address CR 642527
+//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
+//        assign M_AXI_GP0_AWID        =  M_AXI_GP0_AWID_FULL;
+//        assign M_AXI_GP0_WID         =  M_AXI_GP0_WID_FULL;   
+//        assign M_AXI_GP0_ARID        =  M_AXI_GP0_ARID_FULL;      
+//        assign M_AXI_GP0_BID_FULL    =  M_AXI_GP0_BID;
+//        assign M_AXI_GP0_RID_FULL    =  M_AXI_GP0_RID;      
+//
+//        assign M_AXI_GP1_AWID        =  M_AXI_GP1_AWID_FULL;
+//        assign M_AXI_GP1_WID         =  M_AXI_GP1_WID_FULL;   
+//        assign M_AXI_GP1_ARID        =  M_AXI_GP1_ARID_FULL;      
+//        assign M_AXI_GP1_BID_FULL    =  M_AXI_GP1_BID;
+//        assign M_AXI_GP1_RID_FULL    =  M_AXI_GP1_RID;      
+\t\t\t\t\t\t  
+  
+// Pipeline Stage for ENET0
+\t
+generate
+  if (C_EN_EMIO_ENET0 == 1) begin
+  always @(posedge ENET0_GMII_TX_CLK)
+  begin
+      ENET0_GMII_TXD    <= ENET0_GMII_TXD_i;
+      ENET0_GMII_TX_EN  <= ENET0_GMII_TX_EN_i; //1\'b0; //ENET0_GMII_TX_EN_i;
+\t  ENET0_GMII_TX_ER  <= ENET0_GMII_TX_ER_i; //1\'b0;//ENET0_GMII_TX_ER_i;
+      ENET0_GMII_COL_i  <= ENET0_GMII_COL;
+      ENET0_GMII_CRS_i  <= ENET0_GMII_CRS;
+    end
+\tend
+\telse
+\talways@*
+\t begin
+\t  ENET0_GMII_TXD    <= \'b0;//ENET0_GMII_TXD_i;
+      ENET0_GMII_TX_EN  <= \'b0;//ENET0_GMII_TX_EN_i; //1\'b0; //ENET0_GMII_TX_EN_i;
+\t  ENET0_GMII_TX_ER  <= \'b0;//ENET0_GMII_TX_ER_i; //1\'b0;//ENET0_GMII_TX_ER_i;
+\t  ENET0_GMII_COL_i <= \'b0;
+\t  ENET0_GMII_CRS_i <= \'b0;
+\t end  
+endgenerate
+  
+generate
+  if (C_EN_EMIO_ENET0 == 1) begin 
+    always @(posedge ENET0_GMII_RX_CLK) 
+    begin
+      ENET0_GMII_RXD_i    <= ENET0_GMII_RXD;
+      ENET0_GMII_RX_DV_i  <= ENET0_GMII_RX_DV;
+      ENET0_GMII_RX_ER_i  <= ENET0_GMII_RX_ER;
+    end
+  end
+\telse
+\tbegin
+\talways @*
+\tbegin
+\tENET0_GMII_RXD_i    <= 0;
+   ENET0_GMII_RX_DV_i  <= 0;
+    ENET0_GMII_RX_ER_i  <= 0;
+\tend
+\tend
+endgenerate
+
+// Pipeline Stage for ENET1
+\t
+generate
+  if (C_EN_EMIO_ENET1 == 1) begin 
+    always @(posedge ENET1_GMII_TX_CLK) 
+    begin
+      ENET1_GMII_TXD    <= ENET1_GMII_TXD_i;
+      ENET1_GMII_TX_EN  <= ENET1_GMII_TX_EN_i;
+      ENET1_GMII_TX_ER  <= ENET1_GMII_TX_ER_i;
+      ENET1_GMII_COL_i  <= ENET1_GMII_COL;
+      ENET1_GMII_CRS_i  <= ENET1_GMII_CRS;
+    end
+  end
+  else
+  begin
+  always@*
+\t begin
+\t  ENET1_GMII_TXD    <= \'b0;//ENET0_GMII_TXD_i;
+      ENET1_GMII_TX_EN  <= \'b0;//ENET0_GMII_TX_EN_i; //1\'b0; //ENET0_GMII_TX_EN_i;
+\t  ENET1_GMII_TX_ER  <= \'b0;//ENET0_GMII_TX_ER_i; //1\'b0;//ENET0_GMII_TX_ER_i;
+\t  ENET1_GMII_COL_i <= 0;
+\t  ENET1_GMII_CRS_i <= 0;
+\t end  
+  end
+endgenerate
+   
+generate\t
+  if (C_EN_EMIO_ENET1 == 1) begin 
+    always @(posedge ENET1_GMII_RX_CLK) 
+    begin
+      ENET1_GMII_RXD_i    <= ENET1_GMII_RXD;
+      ENET1_GMII_RX_DV_i  <= ENET1_GMII_RX_DV;
+      ENET1_GMII_RX_ER_i  <= ENET1_GMII_RX_ER;
+    end
+  end\t
+else
+\tbegin
+\talways @*
+\tbegin
+\tENET1_GMII_RXD_i    <= \'b0;
+   ENET1_GMII_RX_DV_i  <= \'b0;
+  ENET1_GMII_RX_ER_i  <= \'b0;
+\tend
+\tend  
+endgenerate   
+   
+// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
+
+generate
+  if (C_EN_EMIO_TRACE == 1)  begin
+    if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
+        
+      // Pipeline Stage for Traceport ATID
+      always @(posedge FTMD_TRACEIN_CLK) 
+      begin
+       \tFTMD_TRACEIN_DATA_notracebuf    <= FTMD_TRACEIN_DATA;
+        FTMD_TRACEIN_VALID_notracebuf   <= FTMD_TRACEIN_VALID;
+\tFTMD_TRACEIN_ATID_notracebuf    <= FTMD_TRACEIN_ATID;
+      end
+
+      assign FTMD_TRACEIN_DATA_i   = FTMD_TRACEIN_DATA_notracebuf;
+      assign FTMD_TRACEIN_VALID_i  = FTMD_TRACEIN_VALID_notracebuf;
+      assign FTMD_TRACEIN_ATID_i   = FTMD_TRACEIN_ATID_notracebuf;
+
+    end else begin : gen_trace_buffer
+    
+      processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
+      .USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
+      .C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
+       )
+      trace_buffer_i (
+        .TRACE_CLK(FTMD_TRACEIN_CLK), 
+        .RST(~FCLK_RESET0_N), 
+        .TRACE_VALID_IN(FTMD_TRACEIN_VALID), 
+        .TRACE_DATA_IN(FTMD_TRACEIN_DATA), 
+        .TRACE_ATID_IN(FTMD_TRACEIN_ATID), 
+        .TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf), 
+        .TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf), 
+        .TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
+      );
+
+      assign FTMD_TRACEIN_DATA_i   = FTMD_TRACEIN_DATA_tracebuf;
+      assign FTMD_TRACEIN_VALID_i  = FTMD_TRACEIN_VALID_tracebuf;
+      assign FTMD_TRACEIN_ATID_i   = FTMD_TRACEIN_ATID_tracebuf;
+ 
+    end
+  end
+  else
+  begin
+  assign FTMD_TRACEIN_DATA_i   = 1\'b0;
+      assign FTMD_TRACEIN_VALID_i  = 1\'b0;
+      assign FTMD_TRACEIN_ATID_i   = 1\'b0;
+\t  end
+endgenerate
+  
+   
+   // ID Width Control on AXI Slave ports
+   // S_AXI_GP0
+   
+     function [5:0] id_in_gp0;
+       input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
+     begin
+        case (C_S_AXI_GP0_ID_WIDTH)
+              1:  id_in_gp0  = {5\'b0, axi_id_gp0_in};
+              2:  id_in_gp0  = {4\'b0, axi_id_gp0_in};
+              3:  id_in_gp0  = {3\'b0, axi_id_gp0_in};
+              4:  id_in_gp0  = {2\'b0, axi_id_gp0_in};
+              5:  id_in_gp0  = {1\'b0, axi_id_gp0_in};
+              6:  id_in_gp0  = axi_id_gp0_in;    
+              default : id_in_gp0 =  axi_id_gp0_in;
+        endcase
+     end
+     endfunction
+
+    assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
+    assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
+    assign S_AXI_GP0_WID_in  = id_in_gp0(S_AXI_GP0_WID);
+
+     function [5:0] id_out_gp0;
+       input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
+     begin
+        case (C_S_AXI_GP0_ID_WIDTH)
+              1:  id_out_gp0  = axi_id_gp0_out[0];
+              2:  id_out_gp0  = axi_id_gp0_out[1:0];
+              3:  id_out_gp0  = axi_id_gp0_out[2:0];
+              4:  id_out_gp0  = axi_id_gp0_out[3:0];
+              5:  id_out_gp0  = axi_id_gp0_out[4:0];
+              6:  id_out_gp0  = axi_id_gp0_out;    
+              default : id_out_gp0 =  axi_id_gp0_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_GP0_BID     = id_out_gp0(S_AXI_GP0_BID_out);
+    assign S_AXI_GP0_RID     = id_out_gp0(S_AXI_GP0_RID_out);    
+   
+   // S_AXI_GP1
+   
+     function [5:0] id_in_gp1;
+       input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
+     begin
+        case (C_S_AXI_GP1_ID_WIDTH)
+              1:  id_in_gp1  = {5\'b0, axi_id_gp1_in};
+              2:  id_in_gp1  = {4\'b0, axi_id_gp1_in};
+              3:  id_in_gp1  = {3\'b0, axi_id_gp1_in};
+              4:  id_in_gp1  = {2\'b0, axi_id_gp1_in};
+              5:  id_in_gp1  = {1\'b0, axi_id_gp1_in};
+              6:  id_in_gp1  = axi_id_gp1_in;    
+              default : id_in_gp1 =  axi_id_gp1_in;
+        endcase
+     end
+     endfunction
+
+    assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
+    assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
+    assign S_AXI_GP1_WID_in  = id_in_gp1(S_AXI_GP1_WID);
+
+     function [5:0] id_out_gp1;
+       input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
+     begin
+        case (C_S_AXI_GP1_ID_WIDTH)
+              1:  id_out_gp1  = axi_id_gp1_out[0];
+              2:  id_out_gp1  = axi_id_gp1_out[1:0];
+              3:  id_out_gp1  = axi_id_gp1_out[2:0];
+              4:  id_out_gp1  = axi_id_gp1_out[3:0];
+              5:  id_out_gp1  = axi_id_gp1_out[4:0];
+              6:  id_out_gp1  = axi_id_gp1_out;    
+              default : id_out_gp1 =  axi_id_gp1_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_GP1_BID     = id_out_gp1(S_AXI_GP1_BID_out);
+    assign S_AXI_GP1_RID     = id_out_gp1(S_AXI_GP1_RID_out);    
+    
+// S_AXI_HP0    
+    
+     function [5:0] id_in_hp0;
+       input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
+     begin
+        case (C_S_AXI_HP0_ID_WIDTH)
+              1:  id_in_hp0  = {5\'b0, axi_id_hp0_in};
+              2:  id_in_hp0  = {4\'b0, axi_id_hp0_in};
+              3:  id_in_hp0  = {3\'b0, axi_id_hp0_in};
+              4:  id_in_hp0  = {2\'b0, axi_id_hp0_in};
+              5:  id_in_hp0  = {1\'b0, axi_id_hp0_in};
+              6:  id_in_hp0  = axi_id_hp0_in;    
+              default : id_in_hp0 =  axi_id_hp0_in;
+        endcase
+     end
+     endfunction
+
+    assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
+    assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
+    assign S_AXI_HP0_WID_in  = id_in_hp0(S_AXI_HP0_WID);
+
+     function [5:0] id_out_hp0;
+       input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
+     begin
+        case (C_S_AXI_HP0_ID_WIDTH)
+              1:  id_out_hp0  = axi_id_hp0_out[0];
+              2:  id_out_hp0  = axi_id_hp0_out[1:0];
+              3:  id_out_hp0  = axi_id_hp0_out[2:0];
+              4:  id_out_hp0  = axi_id_hp0_out[3:0];
+              5:  id_out_hp0  = axi_id_hp0_out[4:0];
+              6:  id_out_hp0  = axi_id_hp0_out;    
+              default : id_out_hp0 =  axi_id_hp0_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_HP0_BID     = id_out_hp0(S_AXI_HP0_BID_out);
+    assign S_AXI_HP0_RID     = id_out_hp0(S_AXI_HP0_RID_out);  
+    
+    assign S_AXI_HP0_WDATA_in        = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32\'b0,S_AXI_HP0_WDATA};
+    assign S_AXI_HP0_WSTRB_in        = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4\'b0,S_AXI_HP0_WSTRB};       
+    assign S_AXI_HP0_RDATA           = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
+    
+// S_AXI_HP1    
+
+     function [5:0] id_in_hp1;
+       input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
+     begin
+        case (C_S_AXI_HP1_ID_WIDTH)
+              1:  id_in_hp1  = {5\'b0, axi_id_hp1_in};
+              2:  id_in_hp1  = {4\'b0, axi_id_hp1_in};
+              3:  id_in_hp1  = {3\'b0, axi_id_hp1_in};
+              4:  id_in_hp1  = {2\'b0, axi_id_hp1_in};
+              5:  id_in_hp1  = {1\'b0, axi_id_hp1_in};
+              6:  id_in_hp1  = axi_id_hp1_in;    
+              default : id_in_hp1 =  axi_id_hp1_in;
+        endcase
+     end
+     endfunction
+     
+     
+
+    assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
+    assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
+    assign S_AXI_HP1_WID_in  = id_in_hp1(S_AXI_HP1_WID);
+
+     function [5:0] id_out_hp1;
+       input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
+     begin
+        case (C_S_AXI_HP1_ID_WIDTH)
+              1:  id_out_hp1  = axi_id_hp1_out[0];
+              2:  id_out_hp1  = axi_id_hp1_out[1:0];
+              3:  id_out_hp1  = axi_id_hp1_out[2:0];
+              4:  id_out_hp1  = axi_id_hp1_out[3:0];
+              5:  id_out_hp1  = axi_id_hp1_out[4:0];
+              6:  id_out_hp1  = axi_id_hp1_out;    
+              default : id_out_hp1 =  axi_id_hp1_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_HP1_BID     = id_out_hp1(S_AXI_HP1_BID_out);
+    assign S_AXI_HP1_RID     = id_out_hp1(S_AXI_HP1_RID_out); 
+    
+    assign S_AXI_HP1_WDATA_in        = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32\'b0,S_AXI_HP1_WDATA};
+    assign S_AXI_HP1_WSTRB_in        = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4\'b0,S_AXI_HP1_WSTRB};       
+    assign S_AXI_HP1_RDATA           = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
+    
+    
+// S_AXI_HP2    
+
+     function [5:0] id_in_hp2;
+       input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
+     begin
+        case (C_S_AXI_HP2_ID_WIDTH)
+              1:  id_in_hp2  = {5\'b0, axi_id_hp2_in};
+              2:  id_in_hp2  = {4\'b0, axi_id_hp2_in};
+              3:  id_in_hp2  = {3\'b0, axi_id_hp2_in};
+              4:  id_in_hp2  = {2\'b0, axi_id_hp2_in};
+              5:  id_in_hp2  = {1\'b0, axi_id_hp2_in};
+              6:  id_in_hp2  = axi_id_hp2_in;    
+              default : id_in_hp2 =  axi_id_hp2_in;
+        endcase
+     end
+     endfunction
+     
+    assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
+    assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
+    assign S_AXI_HP2_WID_in  = id_in_hp2(S_AXI_HP2_WID);
+ 
+
+     function [5:0] id_out_hp2;
+       input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
+     begin
+        case (C_S_AXI_HP2_ID_WIDTH)
+              1:  id_out_hp2  = axi_id_hp2_out[0];
+              2:  id_out_hp2  = axi_id_hp2_out[1:0];
+              3:  id_out_hp2  = axi_id_hp2_out[2:0];
+              4:  id_out_hp2  = axi_id_hp2_out[3:0];
+              5:  id_out_hp2  = axi_id_hp2_out[4:0];
+              6:  id_out_hp2  = axi_id_hp2_out;    
+              default : id_out_hp2 =  axi_id_hp2_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_HP2_BID     = id_out_hp2(S_AXI_HP2_BID_out);
+    assign S_AXI_HP2_RID     = id_out_hp2(S_AXI_HP2_RID_out);  
+    
+    assign S_AXI_HP2_WDATA_in        = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32\'b0,S_AXI_HP2_WDATA};
+    assign S_AXI_HP2_WSTRB_in        = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4\'b0,S_AXI_HP2_WSTRB};       
+    assign S_AXI_HP2_RDATA           = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
+    
+    
+// S_AXI_HP3    
+
+     function [5:0] id_in_hp3;
+       input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
+     begin
+        case (C_S_AXI_HP3_ID_WIDTH)
+              1:  id_in_hp3  = {5\'b0, axi_id_hp3_in};
+              2:  id_in_hp3  = {4\'b0, axi_id_hp3_in};
+              3:  id_in_hp3  = {3\'b0, axi_id_hp3_in};
+              4:  id_in_hp3  = {2\'b0, axi_id_hp3_in};
+              5:  id_in_hp3  = {1\'b0, axi_id_hp3_in};
+              6:  id_in_hp3  = axi_id_hp3_in;    
+              default : id_in_hp3 =  axi_id_hp3_in;
+        endcase
+     end
+     endfunction
+     
+    assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
+    assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
+    assign S_AXI_HP3_WID_in  = id_in_hp3(S_AXI_HP3_WID);
+     
+
+
+     function [5:0] id_out_hp3;
+       input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
+     begin
+        case (C_S_AXI_HP3_ID_WIDTH)
+              1:  id_out_hp3  = axi_id_hp3_out[0];
+              2:  id_out_hp3  = axi_id_hp3_out[1:0];
+              3:  id_out_hp3  = axi_id_hp3_out[2:0];
+              4:  id_out_hp3  = axi_id_hp3_out[3:0];
+              5:  id_out_hp3  = axi_id_hp3_out[4:0];
+              6:  id_out_hp3  = axi_id_hp3_out;    
+              default : id_out_hp3 =  axi_id_hp3_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_HP3_BID     = id_out_hp3(S_AXI_HP3_BID_out);
+    assign S_AXI_HP3_RID     = id_out_hp3(S_AXI_HP3_RID_out); 
+    
+    assign S_AXI_HP3_WDATA_in        = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32\'b0,S_AXI_HP3_WDATA};
+    assign S_AXI_HP3_WSTRB_in        = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4\'b0,S_AXI_HP3_WSTRB};       
+    assign S_AXI_HP3_RDATA           = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
+    
+    
+// S_AXI_ACP    
+
+     function [2:0] id_in_acp;
+       input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
+     begin
+        case (C_S_AXI_ACP_ID_WIDTH)
+              1:  id_in_acp  = {2\'b0, axi_id_acp_in};
+              2:  id_in_acp  = {1\'b0, axi_id_acp_in};
+              3:  id_in_acp  = axi_id_acp_in;
+              default : id_in_acp =  axi_id_acp_in;
+        endcase
+     end
+     endfunction
+
+    assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
+    assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
+    assign S_AXI_ACP_WID_in  = id_in_acp(SAXIACPWID_W);
+
+     function [2:0] id_out_acp;
+       input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
+     begin
+        case (C_S_AXI_ACP_ID_WIDTH)
+              1:  id_out_acp  = axi_id_acp_out[0];
+              2:  id_out_acp  = axi_id_acp_out[1:0];
+              3:  id_out_acp  = axi_id_acp_out;
+              default : id_out_acp =  axi_id_acp_out;              
+        endcase
+     end
+     endfunction
+    
+    assign SAXIACPBID_W     = id_out_acp(S_AXI_ACP_BID_out);
+    assign SAXIACPRID_W     = id_out_acp(S_AXI_ACP_RID_out);  
+    
+// FMIO Tristate Inversion logic 
+
+//FMIO I2C0
+assign        I2C0_SDA_T  = ~ I2C0_SDA_T_n;
+assign        I2C0_SCL_T  = ~ I2C0_SCL_T_n;
+//FMIO I2C1                     
+assign        I2C1_SDA_T  = ~ I2C1_SDA_T_n;
+assign        I2C1_SCL_T  = ~ I2C1_SCL_T_n;
+//FMIO SPI0             
+assign        SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
+assign        SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
+assign        SPI0_MISO_T = ~ SPI0_MISO_T_n;
+assign        SPI0_SS_T   = ~ SPI0_SS_T_n;
+//FMIO SPI1             
+assign        SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
+assign        SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
+assign        SPI1_MISO_T = ~ SPI1_MISO_T_n;
+assign        SPI1_SS_T   = ~ SPI1_SS_T_n;
+
+
+
+// EMIO GEM0 MDIO
+assign        ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
+    
+// EMIO GEM1 MDIO
+assign        ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
+
+// EMIO GPIO
+assign        GPIO_T = ~ GPIO_T_n;
+
+// EMIO GPIO Width Control 
+
+  function [63:0] gpio_width_adjust_in;
+    input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
+  begin
+     case (C_EMIO_GPIO_WIDTH)
+           1:  gpio_width_adjust_in   = {63\'b0, gpio_in};
+           2:  gpio_width_adjust_in   = {62\'b0, gpio_in};
+           3:  gpio_width_adjust_in   = {61\'b0, gpio_in};
+           4:  gpio_width_adjust_in   = {60\'b0, gpio_in};
+           5:  gpio_width_adjust_in   = {59\'b0, gpio_in};
+           6:  gpio_width_adjust_in   = {58\'b0, gpio_in};
+           7:  gpio_width_adjust_in   = {57\'b0, gpio_in};
+           8:  gpio_width_adjust_in   = {56\'b0, gpio_in};
+           9:  gpio_width_adjust_in   = {55\'b0, gpio_in};
+           10:  gpio_width_adjust_in  = {54\'b0, gpio_in};
+           11:  gpio_width_adjust_in  = {53\'b0, gpio_in};
+           12:  gpio_width_adjust_in  = {52\'b0, gpio_in};
+           13:  gpio_width_adjust_in  = {51\'b0, gpio_in};
+           14:  gpio_width_adjust_in  = {50\'b0, gpio_in};
+           15:  gpio_width_adjust_in  = {49\'b0, gpio_in};
+           16:  gpio_width_adjust_in  = {48\'b0, gpio_in};
+           17:  gpio_width_adjust_in  = {47\'b0, gpio_in};
+           18:  gpio_width_adjust_in  = {46\'b0, gpio_in};
+           19:  gpio_width_adjust_in  = {45\'b0, gpio_in};
+           20:  gpio_width_adjust_in  = {44\'b0, gpio_in};
+           21:  gpio_width_adjust_in  = {43\'b0, gpio_in};
+           22:  gpio_width_adjust_in  = {42\'b0, gpio_in};
+           23:  gpio_width_adjust_in  = {41\'b0, gpio_in};
+           24:  gpio_width_adjust_in  = {40\'b0, gpio_in};
+           25:  gpio_width_adjust_in  = {39\'b0, gpio_in};
+           26:  gpio_width_adjust_in  = {38\'b0, gpio_in};
+           27:  gpio_width_adjust_in  = {37\'b0, gpio_in};
+           28:  gpio_width_adjust_in  = {36\'b0, gpio_in};
+           29:  gpio_width_adjust_in  = {35\'b0, gpio_in};
+           30:  gpio_width_adjust_in  = {34\'b0, gpio_in};
+           31:  gpio_width_adjust_in  = {33\'b0, gpio_in};
+           32:  gpio_width_adjust_in  = {32\'b0, gpio_in};
+           33:  gpio_width_adjust_in  = {31\'b0, gpio_in};
+           34:  gpio_width_adjust_in  = {30\'b0, gpio_in};
+           35:  gpio_width_adjust_in  = {29\'b0, gpio_in};
+           36:  gpio_width_adjust_in  = {28\'b0, gpio_in};
+           37:  gpio_width_adjust_in  = {27\'b0, gpio_in};
+           38:  gpio_width_adjust_in  = {26\'b0, gpio_in};
+           39:  gpio_width_adjust_in  = {25\'b0, gpio_in};
+           40:  gpio_width_adjust_in  = {24\'b0, gpio_in};
+           41:  gpio_width_adjust_in  = {23\'b0, gpio_in};
+           42:  gpio_width_adjust_in  = {22\'b0, gpio_in};
+           43:  gpio_width_adjust_in  = {21\'b0, gpio_in};
+           44:  gpio_width_adjust_in  = {20\'b0, gpio_in};
+           45:  gpio_width_adjust_in  = {19\'b0, gpio_in};
+           46:  gpio_width_adjust_in  = {18\'b0, gpio_in};
+           47:  gpio_width_adjust_in  = {17\'b0, gpio_in};
+           48:  gpio_width_adjust_in  = {16\'b0, gpio_in};
+           49:  gpio_width_adjust_in  = {15\'b0, gpio_in};
+           50:  gpio_width_adjust_in  = {14\'b0, gpio_in};
+           51:  gpio_width_adjust_in  = {13\'b0, gpio_in};
+           52:  gpio_width_adjust_in  = {12\'b0, gpio_in};
+           53:  gpio_width_adjust_in  = {11\'b0, gpio_in};
+           54:  gpio_width_adjust_in  = {10\'b0, gpio_in};
+           55:  gpio_width_adjust_in  = {9\'b0, gpio_in};
+           56:  gpio_width_adjust_in  = {8\'b0, gpio_in};
+           57:  gpio_width_adjust_in  = {7\'b0, gpio_in};
+           58:  gpio_width_adjust_in  = {6\'b0, gpio_in};
+           59:  gpio_width_adjust_in  = {5\'b0, gpio_in};
+           60:  gpio_width_adjust_in  = {4\'b0, gpio_in};
+           61:  gpio_width_adjust_in  = {3\'b0, gpio_in};
+           62:  gpio_width_adjust_in  = {2\'b0, gpio_in};
+           63:  gpio_width_adjust_in  = {1\'b0, gpio_in};
+           64:  gpio_width_adjust_in  = gpio_in;    
+           default : gpio_width_adjust_in =  gpio_in;
+     endcase
+  end
+  endfunction
+
+ assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
+
+
+  function [63:0] gpio_width_adjust_out;
+    input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
+  begin
+     case (C_EMIO_GPIO_WIDTH)
+           1:  gpio_width_adjust_out    = gpio_o[0];
+           2:  gpio_width_adjust_out    = gpio_o[1:0];
+           3:  gpio_width_adjust_out    = gpio_o[2:0];
+           4:  gpio_width_adjust_out    = gpio_o[3:0];
+           5:  gpio_width_adjust_out    = gpio_o[4:0];
+           6:  gpio_width_adjust_out    = gpio_o[5:0];
+           7:  gpio_width_adjust_out    = gpio_o[6:0];
+           8:  gpio_width_adjust_out    = gpio_o[7:0];
+           9:  gpio_width_adjust_out    = gpio_o[8:0];
+           10: gpio_width_adjust_out    = gpio_o[9:0];
+           11: gpio_width_adjust_out    = gpio_o[10:0];
+           12: gpio_width_adjust_out    = gpio_o[11:0];
+           13: gpio_width_adjust_out    = gpio_o[12:0];
+           14: gpio_width_adjust_out    = gpio_o[13:0];
+           15: gpio_width_adjust_out    = gpio_o[14:0];
+           16: gpio_width_adjust_out    = gpio_o[15:0];
+           17: gpio_width_adjust_out    = gpio_o[16:0];
+           18: gpio_width_adjust_out    = gpio_o[17:0];
+           19: gpio_width_adjust_out    = gpio_o[18:0];
+           20: gpio_width_adjust_out    = gpio_o[19:0];
+           21: gpio_width_adjust_out    = gpio_o[20:0];
+           22: gpio_width_adjust_out    = gpio_o[21:0];
+           23: gpio_width_adjust_out    = gpio_o[22:0];
+           24: gpio_width_adjust_out    = gpio_o[23:0];
+           25: gpio_width_adjust_out    = gpio_o[24:0];
+           26: gpio_width_adjust_out    = gpio_o[25:0];
+           27: gpio_width_adjust_out    = gpio_o[26:0];
+           28: gpio_width_adjust_out    = gpio_o[27:0];
+           29: gpio_width_adjust_out    = gpio_o[28:0];
+           30: gpio_width_adjust_out    = gpio_o[29:0];
+           31: gpio_width_adjust_out    = gpio_o[30:0];
+           32: gpio_width_adjust_out    = gpio_o[31:0];
+           33: gpio_width_adjust_out    = gpio_o[32:0];
+           34: gpio_width_adjust_out    = gpio_o[33:0];
+           35: gpio_width_adjust_out    = gpio_o[34:0];
+           36: gpio_width_adjust_out    = gpio_o[35:0];
+           37: gpio_width_adjust_out    = gpio_o[36:0];
+           38: gpio_width_adjust_out    = gpio_o[37:0];
+           39: gpio_width_adjust_out    = gpio_o[38:0];
+           40: gpio_width_adjust_out    = gpio_o[39:0];
+           41: gpio_width_adjust_out    = gpio_o[40:0];
+           42: gpio_width_adjust_out    = gpio_o[41:0];
+           43: gpio_width_adjust_out    = gpio_o[42:0];
+           44: gpio_width_adjust_out    = gpio_o[43:0];
+           45: gpio_width_adjust_out    = gpio_o[44:0];
+           46: gpio_width_adjust_out    = gpio_o[45:0];
+           47: gpio_width_adjust_out    = gpio_o[46:0];
+           48: gpio_width_adjust_out    = gpio_o[47:0];
+           49: gpio_width_adjust_out    = gpio_o[48:0];
+           50: gpio_width_adjust_out    = gpio_o[49:0];
+           51: gpio_width_adjust_out    = gpio_o[50:0];
+           52: gpio_width_adjust_out    = gpio_o[51:0];
+           53: gpio_width_adjust_out    = gpio_o[52:0];
+           54: gpio_width_adjust_out    = gpio_o[53:0];
+           55: gpio_width_adjust_out    = gpio_o[54:0];
+           56: gpio_width_adjust_out    = gpio_o[55:0];
+           57: gpio_width_adjust_out    = gpio_o[56:0];
+           58: gpio_width_adjust_out    = gpio_o[57:0];
+           59: gpio_width_adjust_out    = gpio_o[58:0];
+           60: gpio_width_adjust_out    = gpio_o[59:0];
+           61: gpio_width_adjust_out    = gpio_o[60:0];
+           62: gpio_width_adjust_out    = gpio_o[61:0];
+           63: gpio_width_adjust_out    = gpio_o[62:0];
+           64: gpio_width_adjust_out    = gpio_o;    
+           default : gpio_width_adjust_out =  gpio_o;
+     endcase
+  end
+  endfunction
+
+ assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0]   = gpio_width_adjust_out(gpio_out);
+ assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
+
+// Adding OBUFT to JTAG out port
+generate
+  if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
+\tOBUFT jtag_obuft_inst (
+\t.O(PJTAG_TDO),
+\t.I(PJTAG_TDO_O),
+\t.T(PJTAG_TDO_T)  
+\t);
+  end
+  else
+  begin
+  assign PJTAG_TDO = 1\'b0;
+  end
+endgenerate
+// -------
+// EMIO PJTAG
+assign        PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
+
+// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of  Silicon,
+// FOR Other SI REV, inversion is required
+ 
+assign        SDIO0_CMD_T       =   (C_PS7_SI_REV == ""1.0"") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
+assign        SDIO0_DATA_T[3:0] =   (C_PS7_SI_REV == ""1.0"") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
+
+// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of  Silicon,
+// FOR Other SI REV, inversion is required
+assign        SDIO1_CMD_T       =  (C_PS7_SI_REV == ""1.0"") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
+assign        SDIO1_DATA_T[3:0] =  (C_PS7_SI_REV == ""1.0"") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
+
+// FCLK_CLK optional clock buffers
+
+generate
+   if (C_FCLK_CLK0_BUF == ""TRUE"" | C_FCLK_CLK0_BUF == ""true"") begin : buffer_fclk_clk_0
+     BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
+   end
+   if (C_FCLK_CLK1_BUF == ""TRUE"" | C_FCLK_CLK1_BUF == ""true"") begin : buffer_fclk_clk_1
+     BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
+   end
+   if (C_FCLK_CLK2_BUF == ""TRUE"" | C_FCLK_CLK2_BUF == ""true"") begin : buffer_fclk_clk_2
+     BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
+   end
+   if (C_FCLK_CLK3_BUF == ""TRUE"" | C_FCLK_CLK3_BUF == ""true"") begin : buffer_fclk_clk_3
+     BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
+   end
+endgenerate 
+
+assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == ""TRUE"" | C_FCLK_CLK0_BUF == ""true"") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
+assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == ""TRUE"" | C_FCLK_CLK1_BUF == ""true"") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
+assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == ""TRUE"" | C_FCLK_CLK2_BUF == ""true"") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
+assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == ""TRUE"" | C_FCLK_CLK3_BUF == ""true"") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
+
+assign FCLK_CLK0 = FCLK_CLK0_temp;
+
+// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
+
+BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
+BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
+BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
+BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
+BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
+BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
+BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
+BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
+BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
+BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
+BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
+BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
+BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
+BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
+
+genvar i;
+generate
+\tfor (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
+\t\tBIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
+\tend
+endgenerate
+
+generate
+\tfor (i=0; i < 3; i=i+1) begin
+\t\tBIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
+\tend
+endgenerate
+
+generate
+\tfor (i=0; i < 15; i=i+1) begin
+\t\tBIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
+\tend
+endgenerate
+
+generate
+\tfor (i=0; i < C_DM_WIDTH; i=i+1) begin
+\t\tBIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
+\tend
+endgenerate
+
+generate
+\tfor (i=0; i < C_DQ_WIDTH; i=i+1) begin
+\t\tBIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
+\tend
+endgenerate
+
+generate
+\tfor (i=0; i < C_DQS_WIDTH; i=i+1) begin
+\t\tBIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
+\tend
+endgenerate
+
+generate
+\tfor (i=0; i < C_DQS_WIDTH; i=i+1) begin
+\t\tBIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
+\tend
+endgenerate
+
+// Connect FCLK in case of disable the AXI port for non Secure Transaction
+//Start
+
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin 
+   assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+  assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin 
+\tassign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+\tassign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin 
+\tassign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+\tassign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin 
+\tassign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+\tassign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
+  end
+endgenerate
+
+//Start
+
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin 
+\tassign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+\tassign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;  
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin 
+\tassign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+\tassign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;    
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin 
+\tassign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+\tassign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;    
+    end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin 
+\tassign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+\tassign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;      
+   end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin 
+\tassign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+\tassign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;        
+  end
+endgenerate
+
+assign M_AXI_GP0_ARCACHE='b'(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1\'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
+assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1\'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
+assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1\'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
+assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1\'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
+
+
+//END
+//====================
+//PSS TOP             
+//====================
+generate 
+if (C_PACKAGE_NAME == ""clg225"" ) begin
+\twire [21:0] dummy;
+\tPS7 PS7_i (
+\t  .DMA0DATYPE\t\t   (DMA0_DATYPE ),
+\t  .DMA0DAVALID\t\t   (DMA0_DAVALID),
+\t  .DMA0DRREADY\t\t   (DMA0_DRREADY),  
+\t  .DMA0RSTN\t\t   (DMA0_RSTN   ),  
+\t  .DMA1DATYPE\t\t   (DMA1_DATYPE ),
+\t  .DMA1DAVALID\t\t   (DMA1_DAVALID),
+\t  .DMA1DRREADY\t\t   (DMA1_DRREADY),
+\t  .DMA1RSTN\t\t   (DMA1_RSTN   ),
+\t  .DMA2DATYPE\t\t   (DMA2_DATYPE ),
+\t  .DMA2DAVALID\t\t   (DMA2_DAVALID),
+\t  .DMA2DRREADY\t\t   (DMA2_DRREADY),
+\t  .DMA2RSTN\t\t   (DMA2_RSTN   ),
+\t  .DMA3DATYPE\t\t   (DMA3_DATYPE ),
+\t  .DMA3DAVALID\t\t   (DMA3_DAVALID),
+\t  .DMA3DRREADY\t\t   (DMA3_DRREADY),
+\t  .DMA3RSTN\t\t   (DMA3_RSTN   ),  
+\t  .EMIOCAN0PHYTX\t   (CAN0_PHY_TX ),
+\t  .EMIOCAN1PHYTX\t   (CAN1_PHY_TX ),  
+\t  .EMIOENET0GMIITXD\t  (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
+\t  .EMIOENET0GMIITXEN\t(ENET0_GMII_TX_EN_i), //   (ENET0_GMII_TX_EN_i),
+\t  .EMIOENET0GMIITXER\t(ENET0_GMII_TX_ER_i), //   (ENET0_GMII_TX_ER_i),
+\t  .EMIOENET0MDIOMDC\t   (ENET0_MDIO_MDC),
+\t  .EMIOENET0MDIOO\t   (ENET0_MDIO_O  ),
+\t  .EMIOENET0MDIOTN\t   (ENET0_MDIO_T_n  ),
+\t  .EMIOENET0PTPDELAYREQRX  (ENET0_PTP_DELAY_REQ_RX),
+\t  .EMIOENET0PTPDELAYREQTX  (ENET0_PTP_DELAY_REQ_TX),
+\t  .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
+\t  .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
+\t  .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+\t  .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+\t  .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
+\t  .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
+\t  .EMIOENET0SOFRX          (ENET0_SOF_RX),
+\t  .EMIOENET0SOFTX          (ENET0_SOF_TX),   
+\t  .EMIOENET1GMIITXD\t   (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
+\t  .EMIOENET1GMIITXEN\t(ENET1_GMII_TX_EN_i), //  (ENET1_GMII_TX_EN_i),
+\t  .EMIOENET1GMIITXER\t(ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
+\t  .EMIOENET1MDIOMDC\t   (ENET1_MDIO_MDC),
+\t  .EMIOENET1MDIOO\t   (ENET1_MDIO_O),
+\t  .EMIOENET1MDIOTN\t   (ENET1_MDIO_T_n),
+\t  .EMIOENET1PTPDELAYREQRX  (ENET1_PTP_DELAY_REQ_RX),
+\t  .EMIOENET1PTPDELAYREQTX  (ENET1_PTP_DELAY_REQ_TX),
+\t  .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
+\t  .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
+\t  .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+\t  .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+\t  .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
+\t  .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
+\t  .EMIOENET1SOFRX          (ENET1_SOF_RX),
+\t  .EMIOENET1SOFTX          (ENET1_SOF_TX),  
+\t  .EMIOGPIOO\t           (gpio_out),
+\t  .EMIOGPIOTN\t           (gpio_out_t_n),
+\t  .EMIOI2C0SCLO            (I2C0_SCL_O),
+\t  .EMIOI2C0SCLTN           (I2C0_SCL_T_n),
+\t  .EMIOI2C0SDAO\t           (I2C0_SDA_O),
+\t  .EMIOI2C0SDATN\t   (I2C0_SDA_T_n),
+\t  .EMIOI2C1SCLO\t           (I2C1_SCL_O),
+\t  .EMIOI2C1SCLTN           (I2C1_SCL_T_n),
+\t  .EMIOI2C1SDAO\t           (I2C1_SDA_O),
+\t  .EMIOI2C1SDATN\t   (I2C1_SDA_T_n),
+\t  .EMIOPJTAGTDO  \t   (PJTAG_TDO_O),
+\t  .EMIOPJTAGTDTN\t   (PJTAG_TDO_T_n),
+\t  .EMIOSDIO0BUSPOW         (SDIO0_BUSPOW),
+\t  .EMIOSDIO0CLK\t\t   (SDIO0_CLK   ),
+\t  .EMIOSDIO0CMDO\t   (SDIO0_CMD_O ),
+\t  .EMIOSDIO0CMDTN\t   (SDIO0_CMD_T_n ),
+\t  .EMIOSDIO0DATAO\t   (SDIO0_DATA_O),
+\t  .EMIOSDIO0DATATN\t   (SDIO0_DATA_T_n),
+\t  .EMIOSDIO0LED            (SDIO0_LED),
+\t  .EMIOSDIO1BUSPOW         (SDIO1_BUSPOW),  
+\t  .EMIOSDIO1CLK            (SDIO1_CLK   ),
+\t  .EMIOSDIO1CMDO           (SDIO1_CMD_O ),
+\t  .EMIOSDIO1CMDTN          (SDIO1_CMD_T_n ),
+\t  .EMIOSDIO1DATAO          (SDIO1_DATA_O),
+\t  .EMIOSDIO1DATATN         (SDIO1_DATA_T_n),
+\t  .EMIOSDIO1LED            (SDIO1_LED),  
+\t  .EMIOSPI0MO\t\t   (SPI0_MOSI_O),
+\t  .EMIOSPI0MOTN\t           (SPI0_MOSI_T_n),
+\t  .EMIOSPI0SCLKO\t   (SPI0_SCLK_O),
+\t  .EMIOSPI0SCLKTN\t   (SPI0_SCLK_T_n),
+\t  .EMIOSPI0SO\t\t   (SPI0_MISO_O),
+\t  .EMIOSPI0STN\t           (SPI0_MISO_T_n),
+\t  .EMIOSPI0SSON\t           ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+\t  .EMIOSPI0SSNTN\t   (SPI0_SS_T_n),
+\t  .EMIOSPI1MO\t\t   (SPI1_MOSI_O),
+\t  .EMIOSPI1MOTN\t           (SPI1_MOSI_T_n),
+\t  .EMIOSPI1SCLKO\t   (SPI1_SCLK_O),
+\t  .EMIOSPI1SCLKTN\t   (SPI1_SCLK_T_n),
+\t  .EMIOSPI1SO\t\t   (SPI1_MISO_O),
+\t  .EMIOSPI1STN\t           (SPI1_MISO_T_n),
+\t  .EMIOSPI1SSON\t           ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+\t  .EMIOSPI1SSNTN\t   (SPI1_SS_T_n),
+\t  .EMIOTRACECTL\t\t   (TRACE_CTL_i),
+\t  .EMIOTRACEDATA\t   (TRACE_DATA_i),
+\t  .EMIOTTC0WAVEO\t   ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+\t  .EMIOTTC1WAVEO\t   ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+\t  .EMIOUART0DTRN\t   (UART0_DTRN),
+\t  .EMIOUART0RTSN\t   (UART0_RTSN),
+\t  .EMIOUART0TX\t\t   (UART0_TX  ),
+\t  .EMIOUART1DTRN\t   (UART1_DTRN),
+\t  .EMIOUART1RTSN\t   (UART1_RTSN),
+\t  .EMIOUART1TX\t\t   (UART1_TX  ),
+\t  .EMIOUSB0PORTINDCTL      (USB0_PORT_INDCTL),  
+\t  .EMIOUSB0VBUSPWRSELECT   (USB0_VBUS_PWRSELECT),
+\t  .EMIOUSB1PORTINDCTL      (USB1_PORT_INDCTL),
+\t  .EMIOUSB1VBUSPWRSELECT   (USB1_VBUS_PWRSELECT),  
+\t  .EMIOWDTRSTO    \t   (WDT_RST_OUT),
+\t  .EVENTEVENTO             (EVENT_EVENTO),
+\t  .EVENTSTANDBYWFE         (EVENT_STANDBYWFE),
+\t  .EVENTSTANDBYWFI         (EVENT_STANDBYWFI),  
+\t  .FCLKCLK\t\t   (FCLK_CLK_unbuffered),
+\t  .FCLKRESETN\t\t   ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),  
+\t  .EMIOSDIO0BUSVOLT        (SDIO0_BUSVOLT), 
+\t  .EMIOSDIO1BUSVOLT        (SDIO1_BUSVOLT),  
+\t  .FTMTF2PTRIGACK\t   ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+\t  .FTMTP2FDEBUG\t\t   (FTMT_P2F_DEBUG  ),
+\t  .FTMTP2FTRIG\t\t   ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+\t  .IRQP2F\t\t   ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),    
+\t  .MAXIGP0ARADDR\t   (M_AXI_GP0_ARADDR),
+\t  .MAXIGP0ARBURST\t   (M_AXI_GP0_ARBURST),
+\t  .MAXIGP0ARCACHE\t   (M_AXI_GP0_ARCACHE_t),
+\t  .MAXIGP0ARESETN\t   (M_AXI_GP0_ARESETN),
+\t  .MAXIGP0ARID\t           (M_AXI_GP0_ARID_FULL   ),
+\t  .MAXIGP0ARLEN\t           (M_AXI_GP0_ARLEN  ),
+\t  .MAXIGP0ARLOCK\t   (M_AXI_GP0_ARLOCK ),
+\t  .MAXIGP0ARPROT\t   (M_AXI_GP0_ARPROT ),
+\t  .MAXIGP0ARQOS\t           (M_AXI_GP0_ARQOS  ),
+\t  .MAXIGP0ARSIZE\t   (M_AXI_GP0_ARSIZE_i ),
+\t  .MAXIGP0ARVALID\t   (M_AXI_GP0_ARVALID),
+\t  .MAXIGP0AWADDR\t   (M_AXI_GP0_AWADDR ),
+\t  .MAXIGP0AWBURST\t   (M_AXI_GP0_AWBURST),
+\t  .MAXIGP0AWCACHE\t   (M_AXI_GP0_AWCACHE_t),
+\t  .MAXIGP0AWID\t           (M_AXI_GP0_AWID_FULL   ),
+\t  .MAXIGP0AWLEN\t           (M_AXI_GP0_AWLEN  ),
+\t  .MAXIGP0AWLOCK\t   (M_AXI_GP0_AWLOCK ),
+\t  .MAXIGP0AWPROT\t   (M_AXI_GP0_AWPROT ),
+\t  .MAXIGP0AWQOS\t           (M_AXI_GP0_AWQOS  ),
+\t  .MAXIGP0AWSIZE\t   (M_AXI_GP0_AWSIZE_i ),
+\t  .MAXIGP0AWVALID\t   (M_AXI_GP0_AWVALID),
+\t  .MAXIGP0BREADY\t   (M_AXI_GP0_BREADY ),
+\t  .MAXIGP0RREADY\t   (M_AXI_GP0_RREADY ),
+\t  .MAXIGP0WDATA\t           (M_AXI_GP0_WDATA  ),
+\t  .MAXIGP0WID\t           (M_AXI_GP0_WID_FULL    ),
+\t  .MAXIGP0WLAST\t           (M_AXI_GP0_WLAST  ),
+\t  .MAXIGP0WSTRB\t           (M_AXI_GP0_WSTRB  ),
+\t  .MAXIGP0WVALID\t   (M_AXI_GP0_WVALID ),
+\t  .MAXIGP1ARADDR\t   (M_AXI_GP1_ARADDR ),
+\t  .MAXIGP1ARBURST\t   (M_AXI_GP1_ARBURST),
+\t  .MAXIGP1ARCACHE\t   (M_AXI_GP1_ARCACHE_t),
+\t  .MAXIGP1ARESETN\t   (M_AXI_GP1_ARESETN),
+\t  .MAXIGP1ARID\t           (M_AXI_GP1_ARID_FULL   ),
+\t  .MAXIGP1ARLEN\t           (M_AXI_GP1_ARLEN  ),
+\t  .MAXIGP1ARLOCK\t   (M_AXI_GP1_ARLOCK ),
+\t  .MAXIGP1ARPROT\t   (M_AXI_GP1_ARPROT ),
+\t  .MAXIGP1ARQOS\t           (M_AXI_GP1_ARQOS  ),
+\t  .MAXIGP1ARSIZE\t   (M_AXI_GP1_ARSIZE_i ),
+\t  .MAXIGP1ARVALID\t   (M_AXI_GP1_ARVALID),
+\t  .MAXIGP1AWADDR\t   (M_AXI_GP1_AWADDR ),
+\t  .MAXIGP1AWBURST\t   (M_AXI_GP1_AWBURST),
+\t  .MAXIGP1AWCACHE\t   (M_AXI_GP1_AWCACHE_t),
+\t  .MAXIGP1AWID\t           (M_AXI_GP1_AWID_FULL   ),
+\t  .MAXIGP1AWLEN\t           (M_AXI_GP1_AWLEN  ),
+\t  .MAXIGP1AWLOCK\t   (M_AXI_GP1_AWLOCK ),
+\t  .MAXIGP1AWPROT\t   (M_AXI_GP1_AWPROT ),
+\t  .MAXIGP1AWQOS\t           (M_AXI_GP1_AWQOS  ),
+\t  .MAXIGP1AWSIZE\t   (M_AXI_GP1_AWSIZE_i ),
+\t  .MAXIGP1AWVALID\t   (M_AXI_GP1_AWVALID),
+\t  .MAXIGP1BREADY\t   (M_AXI_GP1_BREADY ),
+\t  .MAXIGP1RREADY\t   (M_AXI_GP1_RREADY ),
+\t  .MAXIGP1WDATA\t           (M_AXI_GP1_WDATA  ),
+\t  .MAXIGP1WID\t           (M_AXI_GP1_WID_FULL    ),
+\t  .MAXIGP1WLAST\t           (M_AXI_GP1_WLAST  ),
+\t  .MAXIGP1WSTRB\t           (M_AXI_GP1_WSTRB  ),
+\t  .MAXIGP1WVALID\t   (M_AXI_GP1_WVALID ),
+\t  .SAXIACPARESETN\t   (S_AXI_ACP_ARESETN),
+\t  .SAXIACPARREADY\t   (SAXIACPARREADY_W),
+\t  .SAXIACPAWREADY\t   (SAXIACPAWREADY_W),
+\t  .SAXIACPBID\t           (S_AXI_ACP_BID_out    ),
+\t  .SAXIACPBRESP\t           (SAXIACPBRESP_W  ),
+\t  .SAXIACPBVALID\t   (SAXIACPBVALID_W ),
+\t  .SAXIACPRDATA\t           (SAXIACPRDATA_W  ),
+\t  .SAXIACPRID\t           (S_AXI_ACP_RID_out),
+\t  .SAXIACPRLAST\t           (SAXIACPRLAST_W  ),
+\t  .SAXIACPRRESP\t           (SAXIACPRRESP_W  ),
+\t  .SAXIACPRVALID\t   (SAXIACPRVALID_W ),
+\t  .SAXIACPWREADY\t   (SAXIACPWREADY_W ),
+\t  .SAXIGP0ARESETN\t   (S_AXI_GP0_ARESETN),
+\t  .SAXIGP0ARREADY\t   (S_AXI_GP0_ARREADY),
+\t  .SAXIGP0AWREADY\t   (S_AXI_GP0_AWREADY),
+\t  .SAXIGP0BID\t           (S_AXI_GP0_BID_out),
+\t  .SAXIGP0BRESP\t           (S_AXI_GP0_BRESP  ),
+\t  .SAXIGP0BVALID\t   (S_AXI_GP0_BVALID ),
+\t  .SAXIGP0RDATA\t           (S_AXI_GP0_RDATA  ),
+\t  .SAXIGP0RID\t           (S_AXI_GP0_RID_out ),
+\t  .SAXIGP0RLAST\t           (S_AXI_GP0_RLAST  ),
+\t  .SAXIGP0RRESP\t           (S_AXI_GP0_RRESP  ),
+\t  .SAXIGP0RVALID\t   (S_AXI_GP0_RVALID ),
+\t  .SAXIGP0WREADY\t   (S_AXI_GP0_WREADY ),
+\t  .SAXIGP1ARESETN\t   (S_AXI_GP1_ARESETN),
+\t  .SAXIGP1ARREADY\t   (S_AXI_GP1_ARREADY),
+\t  .SAXIGP1AWREADY\t   (S_AXI_GP1_AWREADY),
+\t  .SAXIGP1BID\t           (S_AXI_GP1_BID_out    ),
+\t  .SAXIGP1BRESP\t           (S_AXI_GP1_BRESP  ),
+\t  .SAXIGP1BVALID\t   (S_AXI_GP1_BVALID ),
+\t  .SAXIGP1RDATA\t           (S_AXI_GP1_RDATA  ),
+\t  .SAXIGP1RID\t           (S_AXI_GP1_RID_out    ),
+\t  .SAXIGP1RLAST\t           (S_AXI_GP1_RLAST  ),
+\t  .SAXIGP1RRESP\t           (S_AXI_GP1_RRESP  ),
+\t  .SAXIGP1RVALID\t   (S_AXI_GP1_RVALID ),
+\t  .SAXIGP1WREADY\t   (S_AXI_GP1_WREADY ),
+\t  .SAXIHP0ARESETN\t   (S_AXI_HP0_ARESETN),
+\t  .SAXIHP0ARREADY\t   (S_AXI_HP0_ARREADY),
+\t  .SAXIHP0AWREADY\t   (S_AXI_HP0_AWREADY),
+\t  .SAXIHP0BID\t           (S_AXI_HP0_BID_out    ),
+\t  .SAXIHP0BRESP\t           (S_AXI_HP0_BRESP  ),
+\t  .SAXIHP0BVALID\t   (S_AXI_HP0_BVALID ),
+\t  .SAXIHP0RACOUNT          (S_AXI_HP0_RACOUNT),
+\t  .SAXIHP0RCOUNT\t   (S_AXI_HP0_RCOUNT),
+\t  .SAXIHP0RDATA\t           (S_AXI_HP0_RDATA_out),
+\t  .SAXIHP0RID\t           (S_AXI_HP0_RID_out ),
+\t  .SAXIHP0RLAST\t           (S_AXI_HP0_RLAST),
+\t  .SAXIHP0RRESP\t           (S_AXI_HP0_RRESP),
+\t  .SAXIHP0RVALID\t   (S_AXI_HP0_RVALID),
+\t  .SAXIHP0WCOUNT\t   (S_AXI_HP0_WCOUNT),
+\t  .SAXIHP0WACOUNT          (S_AXI_HP0_WACOUNT),  
+\t  .SAXIHP0WREADY\t   (S_AXI_HP0_WREADY),
+\t  .SAXIHP1ARESETN\t   (S_AXI_HP1_ARESETN),
+\t  .SAXIHP1ARREADY\t   (S_AXI_HP1_ARREADY),
+\t  .SAXIHP1AWREADY\t   (S_AXI_HP1_AWREADY),
+\t  .SAXIHP1BID\t           (S_AXI_HP1_BID_out    ),
+\t  .SAXIHP1BRESP\t           (S_AXI_HP1_BRESP  ),
+\t  .SAXIHP1BVALID\t   (S_AXI_HP1_BVALID ),
+\t  .SAXIHP1RACOUNT\t   (S_AXI_HP1_RACOUNT ),  
+\t  .SAXIHP1RCOUNT\t   (S_AXI_HP1_RCOUNT ),
+\t  .SAXIHP1RDATA\t           (S_AXI_HP1_RDATA_out),
+\t  .SAXIHP1RID\t           (S_AXI_HP1_RID_out    ),
+\t  .SAXIHP1RLAST\t           (S_AXI_HP1_RLAST  ),
+\t  .SAXIHP1RRESP\t           (S_AXI_HP1_RRESP  ),
+\t  .SAXIHP1RVALID\t   (S_AXI_HP1_RVALID),
+\t  .SAXIHP1WACOUNT\t   (S_AXI_HP1_WACOUNT),  
+\t  .SAXIHP1WCOUNT\t   (S_AXI_HP1_WCOUNT),
+\t  .SAXIHP1WREADY\t   (S_AXI_HP1_WREADY),
+\t  .SAXIHP2ARESETN\t   (S_AXI_HP2_ARESETN),
+\t  .SAXIHP2ARREADY\t   (S_AXI_HP2_ARREADY),
+\t  .SAXIHP2AWREADY\t   (S_AXI_HP2_AWREADY),
+\t  .SAXIHP2BID\t           (S_AXI_HP2_BID_out ),
+\t  .SAXIHP2BRESP\t           (S_AXI_HP2_BRESP),
+\t  .SAXIHP2BVALID\t   (S_AXI_HP2_BVALID),
+\t  .SAXIHP2RACOUNT\t   (S_AXI_HP2_RACOUNT),  
+\t  .SAXIHP2RCOUNT\t   (S_AXI_HP2_RCOUNT),
+\t  .SAXIHP2RDATA\t           (S_AXI_HP2_RDATA_out),
+\t  .SAXIHP2RID\t           (S_AXI_HP2_RID_out ),
+\t  .SAXIHP2RLAST\t           (S_AXI_HP2_RLAST),
+\t  .SAXIHP2RRESP\t           (S_AXI_HP2_RRESP),
+\t  .SAXIHP2RVALID\t   (S_AXI_HP2_RVALID),
+\t  .SAXIHP2WACOUNT\t   (S_AXI_HP2_WACOUNT),  
+\t  .SAXIHP2WCOUNT\t   (S_AXI_HP2_WCOUNT),
+\t  .SAXIHP2WREADY\t   (S_AXI_HP2_WREADY),
+\t  .SAXIHP3ARESETN\t   (S_AXI_HP3_ARESETN),
+\t  .SAXIHP3ARREADY\t   (S_AXI_HP3_ARREADY),
+\t  .SAXIHP3AWREADY\t   (S_AXI_HP3_AWREADY),
+\t  .SAXIHP3BID\t           (S_AXI_HP3_BID_out),
+\t  .SAXIHP3BRESP\t           (S_AXI_HP3_BRESP),
+\t  .SAXIHP3BVALID\t   (S_AXI_HP3_BVALID),
+\t  .SAXIHP3RACOUNT\t   (S_AXI_HP3_RACOUNT),    
+\t  .SAXIHP3RCOUNT\t   (S_AXI_HP3_RCOUNT),
+\t  .SAXIHP3RDATA\t           (S_AXI_HP3_RDATA_out),
+\t  .SAXIHP3RID\t           (S_AXI_HP3_RID_out),
+\t  .SAXIHP3RLAST\t           (S_AXI_HP3_RLAST),
+\t  .SAXIHP3RRESP\t           (S_AXI_HP3_RRESP),
+\t  .SAXIHP3RVALID\t   (S_AXI_HP3_RVALID),
+\t  .SAXIHP3WCOUNT\t   (S_AXI_HP3_WCOUNT),
+\t  .SAXIHP3WACOUNT\t   (S_AXI_HP3_WACOUNT),    
+\t  .SAXIHP3WREADY\t   (S_AXI_HP3_WREADY), 
+\t  .DDRARB                  (DDR_ARB), 
+\t  .DMA0ACLK\t\t   (DMA0_ACLK   ),
+\t  .DMA0DAREADY\t\t   (DMA0_DAREADY),
+\t  .DMA0DRLAST\t\t   (DMA0_DRLAST ),
+\t  .DMA0DRTYPE              (DMA0_DRTYPE),
+\t  .DMA0DRVALID\t\t   (DMA0_DRVALID),
+\t  .DMA1ACLK\t\t   (DMA1_ACLK   ),
+\t  .DMA1DAREADY\t\t   (DMA1_DAREADY),
+\t  .DMA1DRLAST\t\t   (DMA1_DRLAST ),
+\t  .DMA1DRTYPE              (DMA1_DRTYPE),  
+\t  .DMA1DRVALID\t\t   (DMA1_DRVALID),
+\t  .DMA2ACLK\t\t   (DMA2_ACLK   ),
+\t  .DMA2DAREADY\t\t   (DMA2_DAREADY),
+\t  .DMA2DRLAST\t\t   (DMA2_DRLAST ),
+\t  .DMA2DRTYPE              (DMA2_DRTYPE),    
+\t  .DMA2DRVALID\t\t   (DMA2_DRVALID),
+\t  .DMA3ACLK\t\t   (DMA3_ACLK   ),
+\t  .DMA3DAREADY\t\t   (DMA3_DAREADY),
+\t  .DMA3DRLAST\t\t   (DMA3_DRLAST ),
+\t  .DMA3DRTYPE              (DMA3_DRTYPE),      
+\t  .DMA3DRVALID\t\t   (DMA3_DRVALID),
+\t  .EMIOCAN0PHYRX\t   (CAN0_PHY_RX),  
+\t  .EMIOCAN1PHYRX\t   (CAN1_PHY_RX),
+\t  .EMIOENET0EXTINTIN       (ENET0_EXT_INTIN),  
+\t  .EMIOENET0GMIICOL        (ENET0_GMII_COL_i),
+\t  .EMIOENET0GMIICRS        (ENET0_GMII_CRS_i),
+\t  .EMIOENET0GMIIRXCLK      (ENET0_GMII_RX_CLK),
+\t  .EMIOENET0GMIIRXD        (ENET0_GMII_RXD_i),
+\t  .EMIOENET0GMIIRXDV       (ENET0_GMII_RX_DV_i),
+\t  .EMIOENET0GMIIRXER       (ENET0_GMII_RX_ER_i),
+\t  .EMIOENET0GMIITXCLK      (ENET0_GMII_TX_CLK),
+\t  .EMIOENET0MDIOI          (ENET0_MDIO_I),
+\t  .EMIOENET1EXTINTIN       (ENET1_EXT_INTIN),    
+\t  .EMIOENET1GMIICOL        (ENET1_GMII_COL_i),
+\t  .EMIOENET1GMIICRS        (ENET1_GMII_CRS_i),
+\t  .EMIOENET1GMIIRXCLK      (ENET1_GMII_RX_CLK),
+\t  .EMIOENET1GMIIRXD        (ENET1_GMII_RXD_i),
+\t  .EMIOENET1GMIIRXDV       (ENET1_GMII_RX_DV_i),
+\t  .EMIOENET1GMIIRXER       (ENET1_GMII_RX_ER_i),
+\t  .EMIOENET1GMIITXCLK      (ENET1_GMII_TX_CLK),
+\t  .EMIOENET1MDIOI          (ENET1_MDIO_I),  
+\t  .EMIOGPIOI\t           (gpio_in63_0  ),
+\t  .EMIOI2C0SCLI\t           (I2C0_SCL_I),
+\t  .EMIOI2C0SDAI\t           (I2C0_SDA_I),
+\t  .EMIOI2C1SCLI\t           (I2C1_SCL_I),
+\t  .EMIOI2C1SDAI\t           (I2C1_SDA_I),
+\t  .EMIOPJTAGTCK\t\t   (PJTAG_TCK),
+\t  .EMIOPJTAGTDI\t\t   (PJTAG_TDI),
+\t  .EMIOPJTAGTMS\t\t   (PJTAG_TMS),
+\t  .EMIOSDIO0CDN            (SDIO0_CDN),
+\t  .EMIOSDIO0CLKFB\t   (SDIO0_CLK_FB  ),
+\t  .EMIOSDIO0CMDI\t   (SDIO0_CMD_I   ),
+\t  .EMIOSDIO0DATAI\t   (SDIO0_DATA_I  ),
+\t  .EMIOSDIO0WP             (SDIO0_WP),
+\t  .EMIOSDIO1CDN            (SDIO1_CDN),  
+\t  .EMIOSDIO1CLKFB\t   (SDIO1_CLK_FB  ),
+\t  .EMIOSDIO1CMDI\t   (SDIO1_CMD_I   ),
+\t  .EMIOSDIO1DATAI\t   (SDIO1_DATA_I  ),
+\t  .EMIOSDIO1WP             (SDIO1_WP),
+\t  .EMIOSPI0MI\t\t   (SPI0_MISO_I),
+\t  .EMIOSPI0SCLKI\t   (SPI0_SCLK_I),
+\t  .EMIOSPI0SI\t\t   (SPI0_MOSI_I),
+\t  .EMIOSPI0SSIN \t   (SPI0_SS_I),
+\t  .EMIOSPI1MI\t\t   (SPI1_MISO_I),
+\t  .EMIOSPI1SCLKI\t   (SPI1_SCLK_I),
+\t  .EMIOSPI1SI\t\t   (SPI1_MOSI_I),
+\t  .EMIOSPI1SSIN\t           (SPI1_SS_I),
+\t  .EMIOSRAMINTIN           (SRAM_INTIN),  
+\t  .EMIOTRACECLK\t\t   (TRACE_CLK),
+\t  .EMIOTTC0CLKI\t           ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
+\t  .EMIOTTC1CLKI\t           ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
+\t  .EMIOUART0CTSN\t   (UART0_CTSN),
+\t  .EMIOUART0DCDN\t   (UART0_DCDN),
+\t  .EMIOUART0DSRN\t   (UART0_DSRN),
+\t  .EMIOUART0RIN\t\t   (UART0_RIN ),
+\t  .EMIOUART0RX\t\t   (UART0_RX  ),
+\t  .EMIOUART1CTSN\t   (UART1_CTSN),
+\t  .EMIOUART1DCDN\t   (UART1_DCDN),
+\t  .EMIOUART1DSRN\t   (UART1_DSRN),
+\t  .EMIOUART1RIN\t\t   (UART1_RIN ),
+\t  .EMIOUART1RX\t\t   (UART1_RX  ),
+\t  .EMIOUSB0VBUSPWRFAULT    (USB0_VBUS_PWRFAULT),
+\t  .EMIOUSB1VBUSPWRFAULT    (USB1_VBUS_PWRFAULT),  
+\t  .EMIOWDTCLKI\t\t   (WDT_CLK_IN),  
+\t  .EVENTEVENTI             (EVENT_EVENTI),
+\t  .FCLKCLKTRIGN\t\t   (fclk_clktrig_gnd),
+\t  .FPGAIDLEN\t\t   (FPGA_IDLE_N),  
+\t  .FTMDTRACEINATID\t   (FTMD_TRACEIN_ATID_i),  
+\t  .FTMDTRACEINCLOCK\t   (FTMD_TRACEIN_CLK),
+\t  .FTMDTRACEINDATA\t   (FTMD_TRACEIN_DATA_i),
+\t  .FTMDTRACEINVALID\t   (FTMD_TRACEIN_VALID_i),
+\t  .FTMTF2PDEBUG\t\t   (FTMT_F2P_DEBUG  ),
+\t  .FTMTF2PTRIG\t\t   ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+\t  .FTMTP2FTRIGACK\t   ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),  
+\t  .IRQF2P\t\t   (irq_f2p_i),  
+\t  .MAXIGP0ACLK\t           (M_AXI_GP0_ACLK_temp),
+\t  .MAXIGP0ARREADY\t   (M_AXI_GP0_ARREADY),
+\t  .MAXIGP0AWREADY\t   (M_AXI_GP0_AWREADY),
+\t  .MAXIGP0BID\t           (M_AXI_GP0_BID_FULL    ),
+\t  .MAXIGP0BRESP\t           (M_AXI_GP0_BRESP  ),
+\t  .MAXIGP0BVALID\t   (M_AXI_GP0_BVALID ),
+\t  .MAXIGP0RDATA\t           (M_AXI_GP0_RDATA  ),
+\t  .MAXIGP0RID\t           (M_AXI_GP0_RID_FULL    ),
+\t  .MAXIGP0RLAST\t           (M_AXI_GP0_RLAST  ),
+\t  .MAXIGP0RRESP\t           (M_AXI_GP0_RRESP  ),
+\t  .MAXIGP0RVALID\t   (M_AXI_GP0_RVALID ),
+\t  .MAXIGP0WREADY\t   (M_AXI_GP0_WREADY ),
+\t  .MAXIGP1ACLK\t           (M_AXI_GP1_ACLK_temp   ),
+\t  .MAXIGP1ARREADY\t   (M_AXI_GP1_ARREADY),
+\t  .MAXIGP1AWREADY\t   (M_AXI_GP1_AWREADY),
+\t  .MAXIGP1BID\t           (M_AXI_GP1_BID_FULL ),
+\t  .MAXIGP1BRESP\t           (M_AXI_GP1_BRESP  ),
+\t  .MAXIGP1BVALID\t   (M_AXI_GP1_BVALID ),
+\t  .MAXIGP1RDATA\t           (M_AXI_GP1_RDATA  ),
+\t  .MAXIGP1RID\t           (M_AXI_GP1_RID_FULL    ),
+\t  .MAXIGP1RLAST\t           (M_AXI_GP1_RLAST  ),
+\t  .MAXIGP1RRESP\t           (M_AXI_GP1_RRESP  ),
+\t  .MAXIGP1RVALID\t   (M_AXI_GP1_RVALID ),
+\t  .MAXIGP1WREADY\t   (M_AXI_GP1_WREADY ),  
+\t  .SAXIACPACLK\t           (S_AXI_ACP_ACLK_temp   ),
+\t  .SAXIACPARADDR\t   (SAXIACPARADDR_W ),
+\t  .SAXIACPARBURST\t   (SAXIACPARBURST_W),
+\t  .SAXIACPARCACHE\t   (SAXIACPARCACHE_W),
+\t  .SAXIACPARID\t           (S_AXI_ACP_ARID_in   ),
+\t  .SAXIACPARLEN\t           (SAXIACPARLEN_W  ),
+\t  .SAXIACPARLOCK\t   (SAXIACPARLOCK_W ),
+\t  .SAXIACPARPROT\t   (SAXIACPARPROT_W ),
+\t  .SAXIACPARQOS\t           (S_AXI_ACP_ARQOS  ),
+\t  .SAXIACPARSIZE\t   (SAXIACPARSIZE_W[1:0] ),
+\t  .SAXIACPARUSER\t   (SAXIACPARUSER_W ),
+\t  .SAXIACPARVALID\t   (SAXIACPARVALID_W),
+\t  .SAXIACPAWADDR\t   (SAXIACPAWADDR_W ),
+\t  .SAXIACPAWBURST\t   (SAXIACPAWBURST_W),
+\t  .SAXIACPAWCACHE\t   (SAXIACPAWCACHE_W),
+\t  .SAXIACPAWID\t           (S_AXI_ACP_AWID_in   ),
+\t  .SAXIACPAWLEN\t           (SAXIACPAWLEN_W  ),
+\t  .SAXIACPAWLOCK\t   (SAXIACPAWLOCK_W ),
+\t  .SAXIACPAWPROT\t   (SAXIACPAWPROT_W ),
+\t  .SAXIACPAWQOS\t           (S_AXI_ACP_AWQOS  ),
+\t  .SAXIACPAWSIZE\t   (SAXIACPAWSIZE_W[1:0] ),
+\t  .SAXIACPAWUSER\t   (SAXIACPAWUSER_W ),
+\t  .SAXIACPAWVALID\t   (SAXIACPAWVALID_W),
+\t  .SAXIACPBREADY\t   (SAXIACPBREADY_W ),
+\t  .SAXIACPRREADY\t   (SAXIACPRREADY_W ),
+\t  .SAXIACPWDATA\t           (SAXIACPWDATA_W  ),
+\t  .SAXIACPWID\t           (S_AXI_ACP_WID_in    ),
+\t  .SAXIACPWLAST\t           (SAXIACPWLAST_W  ),
+\t  .SAXIACPWSTRB\t           (SAXIACPWSTRB_W  ),
+\t  .SAXIACPWVALID\t   (SAXIACPWVALID_W ),
+\t  .SAXIGP0ACLK             (S_AXI_GP0_ACLK_temp   ),
+\t  .SAXIGP0ARADDR           (S_AXI_GP0_ARADDR ),
+\t  .SAXIGP0ARBURST          (S_AXI_GP0_ARBURST),
+\t  .SAXIGP0ARCACHE          (S_AXI_GP0_ARCACHE),
+\t  .SAXIGP0ARID             (S_AXI_GP0_ARID_in   ),
+\t  .SAXIGP0ARLEN            (S_AXI_GP0_ARLEN  ),
+\t  .SAXIGP0ARLOCK           (S_AXI_GP0_ARLOCK ),
+\t  .SAXIGP0ARPROT           (S_AXI_GP0_ARPROT ),
+\t  .SAXIGP0ARQOS            (S_AXI_GP0_ARQOS  ),
+\t  .SAXIGP0ARSIZE           (S_AXI_GP0_ARSIZE[1:0] ),
+\t  .SAXIGP0ARVALID          (S_AXI_GP0_ARVALID),
+\t  .SAXIGP0AWADDR           (S_AXI_GP0_AWADDR ),
+\t  .SAXIGP0AWBURST          (S_AXI_GP0_AWBURST),
+\t  .SAXIGP0AWCACHE          (S_AXI_GP0_AWCACHE),
+\t  .SAXIGP0AWID             (S_AXI_GP0_AWID_in   ),
+\t  .SAXIGP0AWLEN            (S_AXI_GP0_AWLEN  ),
+\t  .SAXIGP0AWLOCK           (S_AXI_GP0_AWLOCK ),
+\t  .SAXIGP0AWPROT           (S_AXI_GP0_AWPROT ),
+\t  .SAXIGP0AWQOS            (S_AXI_GP0_AWQOS  ),
+\t  .SAXIGP0AWSIZE           (S_AXI_GP0_AWSIZE[1:0] ),
+\t  .SAXIGP0AWVALID          (S_AXI_GP0_AWVALID),
+\t  .SAXIGP0BREADY           (S_AXI_GP0_BREADY ),
+\t  .SAXIGP0RREADY           (S_AXI_GP0_RREADY ),
+\t  .SAXIGP0WDATA            (S_AXI_GP0_WDATA  ),
+\t  .SAXIGP0WID              (S_AXI_GP0_WID_in ),
+\t  .SAXIGP0WLAST            (S_AXI_GP0_WLAST  ),
+\t  .SAXIGP0WSTRB            (S_AXI_GP0_WSTRB  ),
+\t  .SAXIGP0WVALID           (S_AXI_GP0_WVALID ),
+\t  .SAXIGP1ACLK\t           (S_AXI_GP1_ACLK_temp   ),
+\t  .SAXIGP1ARADDR\t   (S_AXI_GP1_ARADDR ),
+\t  .SAXIGP1ARBURST\t   (S_AXI_GP1_ARBURST),
+\t  .SAXIGP1ARCACHE\t   (S_AXI_GP1_ARCACHE),
+\t  .SAXIGP1ARID\t           (S_AXI_GP1_ARID_in   ),
+\t  .SAXIGP1ARLEN\t           (S_AXI_GP1_ARLEN  ),
+\t  .SAXIGP1ARLOCK\t   (S_AXI_GP1_ARLOCK ),
+\t  .SAXIGP1ARPROT\t   (S_AXI_GP1_ARPROT ),
+\t  .SAXIGP1ARQOS\t           (S_AXI_GP1_ARQOS  ),
+\t  .SAXIGP1ARSIZE\t   (S_AXI_GP1_ARSIZE[1:0] ),
+\t  .SAXIGP1ARVALID\t   (S_AXI_GP1_ARVALID),
+\t  .SAXIGP1AWADDR\t   (S_AXI_GP1_AWADDR ),
+\t  .SAXIGP1AWBURST\t   (S_AXI_GP1_AWBURST),
+\t  .SAXIGP1AWCACHE\t   (S_AXI_GP1_AWCACHE),
+\t  .SAXIGP1AWID\t           (S_AXI_GP1_AWID_in   ),
+\t  .SAXIGP1AWLEN\t           (S_AXI_GP1_AWLEN  ),
+\t  .SAXIGP1AWLOCK\t   (S_AXI_GP1_AWLOCK ),
+\t  .SAXIGP1AWPROT\t   (S_AXI_GP1_AWPROT ),
+\t  .SAXIGP1AWQOS\t           (S_AXI_GP1_AWQOS  ),
+\t  .SAXIGP1AWSIZE\t   (S_AXI_GP1_AWSIZE[1:0] ),
+\t  .SAXIGP1AWVALID\t   (S_AXI_GP1_AWVALID),
+\t  .SAXIGP1BREADY\t   (S_AXI_GP1_BREADY ),
+\t  .SAXIGP1RREADY\t   (S_AXI_GP1_RREADY ),
+\t  .SAXIGP1WDATA\t           (S_AXI_GP1_WDATA  ),
+\t  .SAXIGP1WID\t           (S_AXI_GP1_WID_in    ),
+\t  .SAXIGP1WLAST\t           (S_AXI_GP1_WLAST  ),
+\t  .SAXIGP1WSTRB\t           (S_AXI_GP1_WSTRB  ),
+\t  .SAXIGP1WVALID\t   (S_AXI_GP1_WVALID ),  
+\t  .SAXIHP0ACLK             (S_AXI_HP0_ACLK_temp   ),
+\t  .SAXIHP0ARADDR           (S_AXI_HP0_ARADDR),
+\t  .SAXIHP0ARBURST          (S_AXI_HP0_ARBURST),
+\t  .SAXIHP0ARCACHE          (S_AXI_HP0_ARCACHE),
+\t  .SAXIHP0ARID             (S_AXI_HP0_ARID_in),
+\t  .SAXIHP0ARLEN            (S_AXI_HP0_ARLEN),
+\t  .SAXIHP0ARLOCK           (S_AXI_HP0_ARLOCK),
+\t  .SAXIHP0ARPROT           (S_AXI_HP0_ARPROT),
+\t  .SAXIHP0ARQOS            (S_AXI_HP0_ARQOS),
+\t  .SAXIHP0ARSIZE           (S_AXI_HP0_ARSIZE[1:0]),
+\t  .SAXIHP0ARVALID          (S_AXI_HP0_ARVALID),
+\t  .SAXIHP0AWADDR           (S_AXI_HP0_AWADDR),
+\t  .SAXIHP0AWBURST          (S_AXI_HP0_AWBURST),
+\t  .SAXIHP0AWCACHE          (S_AXI_HP0_AWCACHE),
+\t  .SAXIHP0AWID             (S_AXI_HP0_AWID_in),
+\t  .SAXIHP0AWLEN            (S_AXI_HP0_AWLEN),
+\t  .SAXIHP0AWLOCK           (S_AXI_HP0_AWLOCK),
+\t  .SAXIHP0AWPROT           (S_AXI_HP0_AWPROT),
+\t  .SAXIHP0AWQOS            (S_AXI_HP0_AWQOS),
+\t  .SAXIHP0AWSIZE           (S_AXI_HP0_AWSIZE[1:0]),
+\t  .SAXIHP0AWVALID          (S_AXI_HP0_AWVALID),
+\t  .SAXIHP0BREADY           (S_AXI_HP0_BREADY),
+\t  .SAXIHP0RDISSUECAP1EN    (S_AXI_HP0_RDISSUECAP1_EN),
+\t  .SAXIHP0RREADY           (S_AXI_HP0_RREADY),
+\t  .SAXIHP0WDATA            (S_AXI_HP0_WDATA_in),
+\t  .SAXIHP0WID              (S_AXI_HP0_WID_in),
+\t  .SAXIHP0WLAST            (S_AXI_HP0_WLAST),
+\t  .SAXIHP0WRISSUECAP1EN    (S_AXI_HP0_WRISSUECAP1_EN),
+\t  .SAXIHP0WSTRB            (S_AXI_HP0_WSTRB_in),
+\t  .SAXIHP0WVALID           (S_AXI_HP0_WVALID),
+\t  .SAXIHP1ACLK             (S_AXI_HP1_ACLK_temp),
+\t  .SAXIHP1ARADDR           (S_AXI_HP1_ARADDR),
+\t  .SAXIHP1ARBURST          (S_AXI_HP1_ARBURST),
+\t  .SAXIHP1ARCACHE          (S_AXI_HP1_ARCACHE),
+\t  .SAXIHP1ARID             (S_AXI_HP1_ARID_in),
+\t  .SAXIHP1ARLEN            (S_AXI_HP1_ARLEN),
+\t  .SAXIHP1ARLOCK           (S_AXI_HP1_ARLOCK),
+\t  .SAXIHP1ARPROT           (S_AXI_HP1_ARPROT),
+\t  .SAXIHP1ARQOS            (S_AXI_HP1_ARQOS),
+\t  .SAXIHP1ARSIZE           (S_AXI_HP1_ARSIZE[1:0]),
+\t  .SAXIHP1ARVALID          (S_AXI_HP1_ARVALID),
+\t  .SAXIHP1AWADDR           (S_AXI_HP1_AWADDR),
+\t  .SAXIHP1AWBURST          (S_AXI_HP1_AWBURST),
+\t  .SAXIHP1AWCACHE          (S_AXI_HP1_AWCACHE),
+\t  .SAXIHP1AWID             (S_AXI_HP1_AWID_in),
+\t  .SAXIHP1AWLEN            (S_AXI_HP1_AWLEN),
+\t  .SAXIHP1AWLOCK           (S_AXI_HP1_AWLOCK),
+\t  .SAXIHP1AWPROT           (S_AXI_HP1_AWPROT),
+\t  .SAXIHP1AWQOS            (S_AXI_HP1_AWQOS),
+\t  .SAXIHP1AWSIZE           (S_AXI_HP1_AWSIZE[1:0]),
+\t  .SAXIHP1AWVALID          (S_AXI_HP1_AWVALID),
+\t  .SAXIHP1BREADY           (S_AXI_HP1_BREADY),
+\t  .SAXIHP1RDISSUECAP1EN    (S_AXI_HP1_RDISSUECAP1_EN),
+\t  .SAXIHP1RREADY           (S_AXI_HP1_RREADY),
+\t  .SAXIHP1WDATA            (S_AXI_HP1_WDATA_in),
+\t  .SAXIHP1WID              (S_AXI_HP1_WID_in),
+\t  .SAXIHP1WLAST            (S_AXI_HP1_WLAST),
+\t  .SAXIHP1WRISSUECAP1EN    (S_AXI_HP1_WRISSUECAP1_EN),
+\t  .SAXIHP1WSTRB            (S_AXI_HP1_WSTRB_in),
+\t  .SAXIHP1WVALID           (S_AXI_HP1_WVALID),
+\t  .SAXIHP2ACLK             (S_AXI_HP2_ACLK_temp),
+\t  .SAXIHP2ARADDR           (S_AXI_HP2_ARADDR),
+\t  .SAXIHP2ARBURST          (S_AXI_HP2_ARBURST),
+\t  .SAXIHP2ARCACHE          (S_AXI_HP2_ARCACHE),
+\t  .SAXIHP2ARID             (S_AXI_HP2_ARID_in),
+\t  .SAXIHP2ARLEN            (S_AXI_HP2_ARLEN),
+\t  .SAXIHP2ARLOCK           (S_AXI_HP2_ARLOCK),
+\t  .SAXIHP2ARPROT           (S_AXI_HP2_ARPROT),
+\t  .SAXIHP2ARQOS            (S_AXI_HP2_ARQOS),
+\t  .SAXIHP2ARSIZE           (S_AXI_HP2_ARSIZE[1:0]),
+\t  .SAXIHP2ARVALID          (S_AXI_HP2_ARVALID),
+\t  .SAXIHP2AWADDR           (S_AXI_HP2_AWADDR),
+\t  .SAXIHP2AWBURST          (S_AXI_HP2_AWBURST),
+\t  .SAXIHP2AWCACHE          (S_AXI_HP2_AWCACHE),
+\t  .SAXIHP2AWID             (S_AXI_HP2_AWID_in),
+\t  .SAXIHP2AWLEN            (S_AXI_HP2_AWLEN),
+\t  .SAXIHP2AWLOCK           (S_AXI_HP2_AWLOCK),
+\t  .SAXIHP2AWPROT           (S_AXI_HP2_AWPROT),
+\t  .SAXIHP2AWQOS            (S_AXI_HP2_AWQOS),
+\t  .SAXIHP2AWSIZE           (S_AXI_HP2_AWSIZE[1:0]),
+\t  .SAXIHP2AWVALID          (S_AXI_HP2_AWVALID),
+\t  .SAXIHP2BREADY           (S_AXI_HP2_BREADY),
+\t  .SAXIHP2RDISSUECAP1EN    (S_AXI_HP2_RDISSUECAP1_EN),
+\t  .SAXIHP2RREADY           (S_AXI_HP2_RREADY),
+\t  .SAXIHP2WDATA            (S_AXI_HP2_WDATA_in),
+\t  .SAXIHP2WID              (S_AXI_HP2_WID_in),
+\t  .SAXIHP2WLAST            (S_AXI_HP2_WLAST),
+\t  .SAXIHP2WRISSUECAP1EN    (S_AXI_HP2_WRISSUECAP1_EN),
+\t  .SAXIHP2WSTRB            (S_AXI_HP2_WSTRB_in),
+\t  .SAXIHP2WVALID           (S_AXI_HP2_WVALID),  
+\t  .SAXIHP3ACLK             (S_AXI_HP3_ACLK_temp),
+\t  .SAXIHP3ARADDR           (S_AXI_HP3_ARADDR ),
+\t  .SAXIHP3ARBURST          (S_AXI_HP3_ARBURST),
+\t  .SAXIHP3ARCACHE          (S_AXI_HP3_ARCACHE),
+\t  .SAXIHP3ARID             (S_AXI_HP3_ARID_in   ),
+\t  .SAXIHP3ARLEN            (S_AXI_HP3_ARLEN),
+\t  .SAXIHP3ARLOCK           (S_AXI_HP3_ARLOCK),
+\t  .SAXIHP3ARPROT           (S_AXI_HP3_ARPROT),
+\t  .SAXIHP3ARQOS            (S_AXI_HP3_ARQOS),
+\t  .SAXIHP3ARSIZE           (S_AXI_HP3_ARSIZE[1:0]),
+\t  .SAXIHP3ARVALID          (S_AXI_HP3_ARVALID),
+\t  .SAXIHP3AWADDR           (S_AXI_HP3_AWADDR),
+\t  .SAXIHP3AWBURST          (S_AXI_HP3_AWBURST),
+\t  .SAXIHP3AWCACHE          (S_AXI_HP3_AWCACHE),
+\t  .SAXIHP3AWID             (S_AXI_HP3_AWID_in),
+\t  .SAXIHP3AWLEN            (S_AXI_HP3_AWLEN),
+\t  .SAXIHP3AWLOCK           (S_AXI_HP3_AWLOCK),
+\t  .SAXIHP3AWPROT           (S_AXI_HP3_AWPROT),
+\t  .SAXIHP3AWQOS            (S_AXI_HP3_AWQOS),
+\t  .SAXIHP3AWSIZE           (S_AXI_HP3_AWSIZE[1:0]),
+\t  .SAXIHP3AWVALID          (S_AXI_HP3_AWVALID),
+\t  .SAXIHP3BREADY           (S_AXI_HP3_BREADY),
+\t  .SAXIHP3RDISSUECAP1EN    (S_AXI_HP3_RDISSUECAP1_EN),
+\t  .SAXIHP3RREADY           (S_AXI_HP3_RREADY),
+\t  .SAXIHP3WDATA            (S_AXI_HP3_WDATA_in),
+\t  .SAXIHP3WID              (S_AXI_HP3_WID_in),
+\t  .SAXIHP3WLAST            (S_AXI_HP3_WLAST),
+\t  .SAXIHP3WRISSUECAP1EN    (S_AXI_HP3_WRISSUECAP1_EN),
+\t  .SAXIHP3WSTRB            (S_AXI_HP3_WSTRB_in),
+\t  .SAXIHP3WVALID           (S_AXI_HP3_WVALID),
+\t  .DDRA\t\t           (buffered_DDR_Addr),
+\t  .DDRBA\t\t   (buffered_DDR_BankAddr),
+\t  .DDRCASB\t\t   (buffered_DDR_CAS_n),
+\t  .DDRCKE\t\t   (buffered_DDR_CKE),
+\t  .DDRCKN\t\t   (buffered_DDR_Clk_n),
+\t  .DDRCKP\t\t   (buffered_DDR_Clk),
+\t  .DDRCSB\t\t   (buffered_DDR_CS_n),
+\t  .DDRDM\t\t   (buffered_DDR_DM),
+\t  .DDRDQ\t\t   (buffered_DDR_DQ),
+\t  .DDRDQSN\t\t   (buffered_DDR_DQS_n),
+\t  .DDRDQSP\t\t   (buffered_DDR_DQS),
+\t  .DDRDRSTB                (buffered_DDR_DRSTB),
+\t  .DDRODT\t\t   (buffered_DDR_ODT),  
+\t  .DDRRASB\t\t   (buffered_DDR_RAS_n),
+\t  .DDRVRN          (buffered_DDR_VRN),
+\t  .DDRVRP          (buffered_DDR_VRP),
+\t  .DDRWEB          (buffered_DDR_WEB),
+\t  .MIO\t\t\t   ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
+\t  .PSCLK\t\t   (buffered_PS_CLK),  
+\t  .PSPORB\t\t   (buffered_PS_PORB),  
+\t  .PSSRSTB\t\t   (buffered_PS_SRSTB)  
+  
+
+);
+ end
+ else begin
+\tPS7 PS7_i (
+\t  .DMA0DATYPE\t\t   (DMA0_DATYPE ),
+\t  .DMA0DAVALID\t\t   (DMA0_DAVALID),
+\t  .DMA0DRREADY\t\t   (DMA0_DRREADY),  
+\t  .DMA0RSTN\t\t   (DMA0_RSTN   ),  
+\t  .DMA1DATYPE\t\t   (DMA1_DATYPE ),
+\t  .DMA1DAVALID\t\t   (DMA1_DAVALID),
+\t  .DMA1DRREADY\t\t   (DMA1_DRREADY),
+\t  .DMA1RSTN\t\t   (DMA1_RSTN   ),
+\t  .DMA2DATYPE\t\t   (DMA2_DATYPE ),
+\t  .DMA2DAVALID\t\t   (DMA2_DAVALID),
+\t  .DMA2DRREADY\t\t   (DMA2_DRREADY),
+\t  .DMA2RSTN\t\t   (DMA2_RSTN   ),
+\t  .DMA3DATYPE\t\t   (DMA3_DATYPE ),
+\t  .DMA3DAVALID\t\t   (DMA3_DAVALID),
+\t  .DMA3DRREADY\t\t   (DMA3_DRREADY),
+\t  .DMA3RSTN\t\t   (DMA3_RSTN   ),  
+\t  .EMIOCAN0PHYTX\t   (CAN0_PHY_TX ),
+\t  .EMIOCAN1PHYTX\t   (CAN1_PHY_TX ),  
+\t  .EMIOENET0GMIITXD\t  (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
+\t  .EMIOENET0GMIITXEN\t(ENET0_GMII_TX_EN_i), //  (ENET0_GMII_TX_EN_i),
+\t  .EMIOENET0GMIITXER   (ENET0_GMII_TX_ER_i), //\t (ENET0_GMII_TX_ER_i),
+\t  .EMIOENET0MDIOMDC\t   (ENET0_MDIO_MDC),
+\t  .EMIOENET0MDIOO\t   (ENET0_MDIO_O  ),
+\t  .EMIOENET0MDIOTN\t   (ENET0_MDIO_T_n  ),
+\t  .EMIOENET0PTPDELAYREQRX  (ENET0_PTP_DELAY_REQ_RX),
+\t  .EMIOENET0PTPDELAYREQTX  (ENET0_PTP_DELAY_REQ_TX),
+\t  .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
+\t  .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
+\t  .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+\t  .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+\t  .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
+\t  .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
+\t  .EMIOENET0SOFRX          (ENET0_SOF_RX),
+\t  .EMIOENET0SOFTX          (ENET0_SOF_TX),   
+\t  .EMIOENET1GMIITXD\t (ENET1_GMII_TXD_i), //  (ENET1_GMII_TXD_i),
+\t  .EMIOENET1GMIITXEN\t(ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
+\t  .EMIOENET1GMIITXER\t(ENET1_GMII_TX_ER_i), //  (ENET1_GMII_TX_ER_i),
+\t  .EMIOENET1MDIOMDC\t   (ENET1_MDIO_MDC),
+\t  .EMIOENET1MDIOO\t   (ENET1_MDIO_O  ),
+\t  .EMIOENET1MDIOTN\t   (ENET1_MDIO_T_n),
+\t  .EMIOENET1PTPDELAYREQRX  (ENET1_PTP_DELAY_REQ_RX),
+\t  .EMIOENET1PTPDELAYREQTX  (ENET1_PTP_DELAY_REQ_TX),
+\t  .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
+\t  .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
+\t  .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+\t  .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+\t  .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
+\t  .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
+\t  .EMIOENET1SOFRX          (ENET1_SOF_RX),
+\t  .EMIOENET1SOFTX          (ENET1_SOF_TX),  
+\t  .EMIOGPIOO\t           (gpio_out),
+\t  .EMIOGPIOTN\t           (gpio_out_t_n),
+\t  .EMIOI2C0SCLO            (I2C0_SCL_O),
+\t  .EMIOI2C0SCLTN           (I2C0_SCL_T_n),
+\t  .EMIOI2C0SDAO\t           (I2C0_SDA_O),
+\t  .EMIOI2C0SDATN\t   (I2C0_SDA_T_n),
+\t  .EMIOI2C1SCLO\t           (I2C1_SCL_O),
+\t  .EMIOI2C1SCLTN           (I2C1_SCL_T_n),
+\t  .EMIOI2C1SDAO\t           (I2C1_SDA_O),
+\t  .EMIOI2C1SDATN\t   (I2C1_SDA_T_n),
+\t  .EMIOPJTAGTDO  \t   (PJTAG_TDO_O),
+\t  .EMIOPJTAGTDTN\t   (PJTAG_TDO_T_n),
+\t  .EMIOSDIO0BUSPOW         (SDIO0_BUSPOW),
+\t  .EMIOSDIO0CLK\t\t   (SDIO0_CLK   ),
+\t  .EMIOSDIO0CMDO\t   (SDIO0_CMD_O ),
+\t  .EMIOSDIO0CMDTN\t   (SDIO0_CMD_T_n ),
+\t  .EMIOSDIO0DATAO\t   (SDIO0_DATA_O),
+\t  .EMIOSDIO0DATATN\t   (SDIO0_DATA_T_n),
+\t  .EMIOSDIO0LED            (SDIO0_LED),
+\t  .EMIOSDIO1BUSPOW         (SDIO1_BUSPOW),  
+\t  .EMIOSDIO1CLK            (SDIO1_CLK   ),
+\t  .EMIOSDIO1CMDO           (SDIO1_CMD_O ),
+\t  .EMIOSDIO1CMDTN          (SDIO1_CMD_T_n ),
+\t  .EMIOSDIO1DATAO          (SDIO1_DATA_O),
+\t  .EMIOSDIO1DATATN         (SDIO1_DATA_T_n),
+\t  .EMIOSDIO1LED            (SDIO1_LED),  
+\t  .EMIOSPI0MO\t\t   (SPI0_MOSI_O),
+\t  .EMIOSPI0MOTN\t           (SPI0_MOSI_T_n),
+\t  .EMIOSPI0SCLKO\t   (SPI0_SCLK_O),
+\t  .EMIOSPI0SCLKTN\t   (SPI0_SCLK_T_n),
+\t  .EMIOSPI0SO\t\t   (SPI0_MISO_O),
+\t  .EMIOSPI0STN\t           (SPI0_MISO_T_n),
+\t  .EMIOSPI0SSON\t           ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+\t  .EMIOSPI0SSNTN\t   (SPI0_SS_T_n),
+\t  .EMIOSPI1MO\t\t   (SPI1_MOSI_O),
+\t  .EMIOSPI1MOTN\t           (SPI1_MOSI_T_n),
+\t  .EMIOSPI1SCLKO\t   (SPI1_SCLK_O),
+\t  .EMIOSPI1SCLKTN\t   (SPI1_SCLK_T_n),
+\t  .EMIOSPI1SO\t\t   (SPI1_MISO_O),
+\t  .EMIOSPI1STN\t           (SPI1_MISO_T_n),
+\t  .EMIOSPI1SSON\t           ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+\t  .EMIOSPI1SSNTN\t   (SPI1_SS_T_n),
+\t  .EMIOTRACECTL\t\t   (TRACE_CTL_i),
+\t  .EMIOTRACEDATA\t   (TRACE_DATA_i),
+\t  .EMIOTTC0WAVEO\t   ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+\t  .EMIOTTC1WAVEO\t   ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+\t  .EMIOUART0DTRN\t   (UART0_DTRN),
+\t  .EMIOUART0RTSN\t   (UART0_RTSN),
+\t  .EMIOUART0TX\t\t   (UART0_TX  ),
+\t  .EMIOUART1DTRN\t   (UART1_DTRN),
+\t  .EMIOUART1RTSN\t   (UART1_RTSN),
+\t  .EMIOUART1TX\t\t   (UART1_TX  ),
+\t  .EMIOUSB0PORTINDCTL      (USB0_PORT_INDCTL),  
+\t  .EMIOUSB0VBUSPWRSELECT   (USB0_VBUS_PWRSELECT),
+\t  .EMIOUSB1PORTINDCTL      (USB1_PORT_INDCTL),
+\t  .EMIOUSB1VBUSPWRSELECT   (USB1_VBUS_PWRSELECT),  
+\t  .EMIOWDTRSTO    \t   (WDT_RST_OUT),
+\t  .EVENTEVENTO             (EVENT_EVENTO),
+\t  .EVENTSTANDBYWFE         (EVENT_STANDBYWFE),
+\t  .EVENTSTANDBYWFI         (EVENT_STANDBYWFI),  
+\t  .FCLKCLK\t\t   (FCLK_CLK_unbuffered),
+\t  .FCLKRESETN\t\t   ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),  
+\t  .EMIOSDIO0BUSVOLT        (SDIO0_BUSVOLT), 
+\t  .EMIOSDIO1BUSVOLT        (SDIO1_BUSVOLT),  
+\t  .FTMTF2PTRIGACK\t   ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+\t  .FTMTP2FDEBUG\t\t   (FTMT_P2F_DEBUG  ),
+\t  .FTMTP2FTRIG\t\t   ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+\t  .IRQP2F\t\t   ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),    
+\t  .MAXIGP0ARADDR\t   (M_AXI_GP0_ARADDR),
+\t  .MAXIGP0ARBURST\t   (M_AXI_GP0_ARBURST),
+\t  .MAXIGP0ARCACHE\t   (M_AXI_GP0_ARCACHE_t),
+\t  .MAXIGP0ARESETN\t   (M_AXI_GP0_ARESETN),
+\t  .MAXIGP0ARID\t           (M_AXI_GP0_ARID_FULL   ),
+\t  .MAXIGP0ARLEN\t           (M_AXI_GP0_ARLEN  ),
+\t  .MAXIGP0ARLOCK\t   (M_AXI_GP0_ARLOCK ),
+\t  .MAXIGP0ARPROT\t   (M_AXI_GP0_ARPROT ),
+\t  .MAXIGP0ARQOS\t           (M_AXI_GP0_ARQOS  ),
+\t  .MAXIGP0ARSIZE\t   (M_AXI_GP0_ARSIZE_i ),
+\t  .MAXIGP0ARVALID\t   (M_AXI_GP0_ARVALID),
+\t  .MAXIGP0AWADDR\t   (M_AXI_GP0_AWADDR ),
+\t  .MAXIGP0AWBURST\t   (M_AXI_GP0_AWBURST),
+\t  .MAXIGP0AWCACHE\t   (M_AXI_GP0_AWCACHE_t),
+\t  .MAXIGP0AWID\t           (M_AXI_GP0_AWID_FULL   ),
+\t  .MAXIGP0AWLEN\t           (M_AXI_GP0_AWLEN  ),
+\t  .MAXIGP0AWLOCK\t   (M_AXI_GP0_AWLOCK ),
+\t  .MAXIGP0AWPROT\t   (M_AXI_GP0_AWPROT ),
+\t  .MAXIGP0AWQOS\t           (M_AXI_GP0_AWQOS  ),
+\t  .MAXIGP0AWSIZE\t   (M_AXI_GP0_AWSIZE_i ),
+\t  .MAXIGP0AWVALID\t   (M_AXI_GP0_AWVALID),
+\t  .MAXIGP0BREADY\t   (M_AXI_GP0_BREADY ),
+\t  .MAXIGP0RREADY\t   (M_AXI_GP0_RREADY ),
+\t  .MAXIGP0WDATA\t           (M_AXI_GP0_WDATA  ),
+\t  .MAXIGP0WID\t           (M_AXI_GP0_WID_FULL    ),
+\t  .MAXIGP0WLAST\t           (M_AXI_GP0_WLAST  ),
+\t  .MAXIGP0WSTRB\t           (M_AXI_GP0_WSTRB  ),
+\t  .MAXIGP0WVALID\t   (M_AXI_GP0_WVALID ),
+\t  .MAXIGP1ARADDR\t   (M_AXI_GP1_ARADDR ),
+\t  .MAXIGP1ARBURST\t   (M_AXI_GP1_ARBURST),
+\t  .MAXIGP1ARCACHE\t   (M_AXI_GP1_ARCACHE_t),
+\t  .MAXIGP1ARESETN\t   (M_AXI_GP1_ARESETN),
+\t  .MAXIGP1ARID\t           (M_AXI_GP1_ARID_FULL   ),
+\t  .MAXIGP1ARLEN\t           (M_AXI_GP1_ARLEN  ),
+\t  .MAXIGP1ARLOCK\t   (M_AXI_GP1_ARLOCK ),
+\t  .MAXIGP1ARPROT\t   (M_AXI_GP1_ARPROT ),
+\t  .MAXIGP1ARQOS\t           (M_AXI_GP1_ARQOS  ),
+\t  .MAXIGP1ARSIZE\t   (M_AXI_GP1_ARSIZE_i ),
+\t  .MAXIGP1ARVALID\t   (M_AXI_GP1_ARVALID),
+\t  .MAXIGP1AWADDR\t   (M_AXI_GP1_AWADDR ),
+\t  .MAXIGP1AWBURST\t   (M_AXI_GP1_AWBURST),
+\t  .MAXIGP1AWCACHE\t   (M_AXI_GP1_AWCACHE_t),
+\t  .MAXIGP1AWID\t           (M_AXI_GP1_AWID_FULL   ),
+\t  .MAXIGP1AWLEN\t           (M_AXI_GP1_AWLEN  ),
+\t  .MAXIGP1AWLOCK\t   (M_AXI_GP1_AWLOCK ),
+\t  .MAXIGP1AWPROT\t   (M_AXI_GP1_AWPROT ),
+\t  .MAXIGP1AWQOS\t           (M_AXI_GP1_AWQOS  ),
+\t  .MAXIGP1AWSIZE\t   (M_AXI_GP1_AWSIZE_i ),
+\t  .MAXIGP1AWVALID\t   (M_AXI_GP1_AWVALID),
+\t  .MAXIGP1BREADY\t   (M_AXI_GP1_BREADY ),
+\t  .MAXIGP1RREADY\t   (M_AXI_GP1_RREADY ),
+\t  .MAXIGP1WDATA\t           (M_AXI_GP1_WDATA  ),
+\t  .MAXIGP1WID\t           (M_AXI_GP1_WID_FULL    ),
+\t  .MAXIGP1WLAST\t           (M_AXI_GP1_WLAST  ),
+\t  .MAXIGP1WSTRB\t           (M_AXI_GP1_WSTRB  ),
+\t  .MAXIGP1WVALID\t   (M_AXI_GP1_WVALID ),
+\t  .SAXIACPARESETN\t   (S_AXI_ACP_ARESETN),
+\t  .SAXIACPARREADY\t   (SAXIACPARREADY_W),
+\t  .SAXIACPAWREADY\t   (SAXIACPAWREADY_W),
+\t  .SAXIACPBID\t           (S_AXI_ACP_BID_out    ),
+\t  .SAXIACPBRESP\t           (SAXIACPBRESP_W  ),
+\t  .SAXIACPBVALID\t   (SAXIACPBVALID_W ),
+\t  .SAXIACPRDATA\t           (SAXIACPRDATA_W  ),
+\t  .SAXIACPRID\t           (S_AXI_ACP_RID_out),
+\t  .SAXIACPRLAST\t           (SAXIACPRLAST_W  ),
+\t  .SAXIACPRRESP\t           (SAXIACPRRESP_W  ),
+\t  .SAXIACPRVALID\t   (SAXIACPRVALID_W ),
+\t  .SAXIACPWREADY\t   (SAXIACPWREADY_W ),
+\t  .SAXIGP0ARESETN\t   (S_AXI_GP0_ARESETN),
+\t  .SAXIGP0ARREADY\t   (S_AXI_GP0_ARREADY),
+\t  .SAXIGP0AWREADY\t   (S_AXI_GP0_AWREADY),
+\t  .SAXIGP0BID\t           (S_AXI_GP0_BID_out),
+\t  .SAXIGP0BRESP\t           (S_AXI_GP0_BRESP  ),
+\t  .SAXIGP0BVALID\t   (S_AXI_GP0_BVALID ),
+\t  .SAXIGP0RDATA\t           (S_AXI_GP0_RDATA  ),
+\t  .SAXIGP0RID\t           (S_AXI_GP0_RID_out ),
+\t  .SAXIGP0RLAST\t           (S_AXI_GP0_RLAST  ),
+\t  .SAXIGP0RRESP\t           (S_AXI_GP0_RRESP  ),
+\t  .SAXIGP0RVALID\t   (S_AXI_GP0_RVALID ),
+\t  .SAXIGP0WREADY\t   (S_AXI_GP0_WREADY ),
+\t  .SAXIGP1ARESETN\t   (S_AXI_GP1_ARESETN),
+\t  .SAXIGP1ARREADY\t   (S_AXI_GP1_ARREADY),
+\t  .SAXIGP1AWREADY\t   (S_AXI_GP1_AWREADY),
+\t  .SAXIGP1BID\t           (S_AXI_GP1_BID_out    ),
+\t  .SAXIGP1BRESP\t           (S_AXI_GP1_BRESP  ),
+\t  .SAXIGP1BVALID\t   (S_AXI_GP1_BVALID ),
+\t  .SAXIGP1RDATA\t           (S_AXI_GP1_RDATA  ),
+\t  .SAXIGP1RID\t           (S_AXI_GP1_RID_out    ),
+\t  .SAXIGP1RLAST\t           (S_AXI_GP1_RLAST  ),
+\t  .SAXIGP1RRESP\t           (S_AXI_GP1_RRESP  ),
+\t  .SAXIGP1RVALID\t   (S_AXI_GP1_RVALID ),
+\t  .SAXIGP1WREADY\t   (S_AXI_GP1_WREADY ),
+\t  .SAXIHP0ARESETN\t   (S_AXI_HP0_ARESETN),
+\t  .SAXIHP0ARREADY\t   (S_AXI_HP0_ARREADY),
+\t  .SAXIHP0AWREADY\t   (S_AXI_HP0_AWREADY),
+\t  .SAXIHP0BID\t           (S_AXI_HP0_BID_out    ),
+\t  .SAXIHP0BRESP\t           (S_AXI_HP0_BRESP  ),
+\t  .SAXIHP0BVALID\t   (S_AXI_HP0_BVALID ),
+\t  .SAXIHP0RACOUNT          (S_AXI_HP0_RACOUNT),
+\t  .SAXIHP0RCOUNT\t   (S_AXI_HP0_RCOUNT),
+\t  .SAXIHP0RDATA\t           (S_AXI_HP0_RDATA_out),
+\t  .SAXIHP0RID\t           (S_AXI_HP0_RID_out ),
+\t  .SAXIHP0RLAST\t           (S_AXI_HP0_RLAST),
+\t  .SAXIHP0RRESP\t           (S_AXI_HP0_RRESP),
+\t  .SAXIHP0RVALID\t   (S_AXI_HP0_RVALID),
+\t  .SAXIHP0WCOUNT\t   (S_AXI_HP0_WCOUNT),
+\t  .SAXIHP0WACOUNT          (S_AXI_HP0_WACOUNT),  
+\t  .SAXIHP0WREADY\t   (S_AXI_HP0_WREADY),
+\t  .SAXIHP1ARESETN\t   (S_AXI_HP1_ARESETN),
+\t  .SAXIHP1ARREADY\t   (S_AXI_HP1_ARREADY),
+\t  .SAXIHP1AWREADY\t   (S_AXI_HP1_AWREADY),
+\t  .SAXIHP1BID\t           (S_AXI_HP1_BID_out    ),
+\t  .SAXIHP1BRESP\t           (S_AXI_HP1_BRESP  ),
+\t  .SAXIHP1BVALID\t   (S_AXI_HP1_BVALID ),
+\t  .SAXIHP1RACOUNT\t   (S_AXI_HP1_RACOUNT ),  
+\t  .SAXIHP1RCOUNT\t   (S_AXI_HP1_RCOUNT ),
+\t  .SAXIHP1RDATA\t           (S_AXI_HP1_RDATA_out),
+\t  .SAXIHP1RID\t           (S_AXI_HP1_RID_out    ),
+\t  .SAXIHP1RLAST\t           (S_AXI_HP1_RLAST  ),
+\t  .SAXIHP1RRESP\t           (S_AXI_HP1_RRESP  ),
+\t  .SAXIHP1RVALID\t   (S_AXI_HP1_RVALID),
+\t  .SAXIHP1WACOUNT\t   (S_AXI_HP1_WACOUNT),  
+\t  .SAXIHP1WCOUNT\t   (S_AXI_HP1_WCOUNT),
+\t  .SAXIHP1WREADY\t   (S_AXI_HP1_WREADY),
+\t  .SAXIHP2ARESETN\t   (S_AXI_HP2_ARESETN),
+\t  .SAXIHP2ARREADY\t   (S_AXI_HP2_ARREADY),
+\t  .SAXIHP2AWREADY\t   (S_AXI_HP2_AWREADY),
+\t  .SAXIHP2BID\t           (S_AXI_HP2_BID_out ),
+\t  .SAXIHP2BRESP\t           (S_AXI_HP2_BRESP),
+\t  .SAXIHP2BVALID\t   (S_AXI_HP2_BVALID),
+\t  .SAXIHP2RACOUNT\t   (S_AXI_HP2_RACOUNT),  
+\t  .SAXIHP2RCOUNT\t   (S_AXI_HP2_RCOUNT),
+\t  .SAXIHP2RDATA\t           (S_AXI_HP2_RDATA_out),
+\t  .SAXIHP2RID\t           (S_AXI_HP2_RID_out ),
+\t  .SAXIHP2RLAST\t           (S_AXI_HP2_RLAST),
+\t  .SAXIHP2RRESP\t           (S_AXI_HP2_RRESP),
+\t  .SAXIHP2RVALID\t   (S_AXI_HP2_RVALID),
+\t  .SAXIHP2WACOUNT\t   (S_AXI_HP2_WACOUNT),  
+\t  .SAXIHP2WCOUNT\t   (S_AXI_HP2_WCOUNT),
+\t  .SAXIHP2WREADY\t   (S_AXI_HP2_WREADY),
+\t  .SAXIHP3ARESETN\t   (S_AXI_HP3_ARESETN),
+\t  .SAXIHP3ARREADY\t   (S_AXI_HP3_ARREADY),
+\t  .SAXIHP3AWREADY\t   (S_AXI_HP3_AWREADY),
+\t  .SAXIHP3BID\t           (S_AXI_HP3_BID_out),
+\t  .SAXIHP3BRESP\t           (S_AXI_HP3_BRESP),
+\t  .SAXIHP3BVALID\t   (S_AXI_HP3_BVALID),
+\t  .SAXIHP3RACOUNT\t   (S_AXI_HP3_RACOUNT),    
+\t  .SAXIHP3RCOUNT\t   (S_AXI_HP3_RCOUNT),
+\t  .SAXIHP3RDATA\t           (S_AXI_HP3_RDATA_out),
+\t  .SAXIHP3RID\t           (S_AXI_HP3_RID_out),
+\t  .SAXIHP3RLAST\t           (S_AXI_HP3_RLAST),
+\t  .SAXIHP3RRESP\t           (S_AXI_HP3_RRESP),
+\t  .SAXIHP3RVALID\t   (S_AXI_HP3_RVALID),
+\t  .SAXIHP3WCOUNT\t   (S_AXI_HP3_WCOUNT),
+\t  .SAXIHP3WACOUNT\t   (S_AXI_HP3_WACOUNT),    
+\t  .SAXIHP3WREADY\t   (S_AXI_HP3_WREADY), 
+\t  .DDRARB                  (DDR_ARB), 
+\t  .DMA0ACLK\t\t   (DMA0_ACLK   ),
+\t  .DMA0DAREADY\t\t   (DMA0_DAREADY),
+\t  .DMA0DRLAST\t\t   (DMA0_DRLAST ),
+\t  .DMA0DRTYPE              (DMA0_DRTYPE),
+\t  .DMA0DRVALID\t\t   (DMA0_DRVALID),
+\t  .DMA1ACLK\t\t   (DMA1_ACLK   ),
+\t  .DMA1DAREADY\t\t   (DMA1_DAREADY),
+\t  .DMA1DRLAST\t\t   (DMA1_DRLAST ),
+\t  .DMA1DRTYPE              (DMA1_DRTYPE),  
+\t  .DMA1DRVALID\t\t   (DMA1_DRVALID),
+\t  .DMA2ACLK\t\t   (DMA2_ACLK   ),
+\t  .DMA2DAREADY\t\t   (DMA2_DAREADY),
+\t  .DMA2DRLAST\t\t   (DMA2_DRLAST ),
+\t  .DMA2DRTYPE              (DMA2_DRTYPE),    
+\t  .DMA2DRVALID\t\t   (DMA2_DRVALID),
+\t  .DMA3ACLK\t\t   (DMA3_ACLK   ),
+\t  .DMA3DAREADY\t\t   (DMA3_DAREADY),
+\t  .DMA3DRLAST\t\t   (DMA3_DRLAST ),
+\t  .DMA3DRTYPE              (DMA3_DRTYPE),      
+\t  .DMA3DRVALID\t\t   (DMA3_DRVALID),
+\t  .EMIOCAN0PHYRX\t   (CAN0_PHY_RX),  
+\t  .EMIOCAN1PHYRX\t   (CAN1_PHY_RX),
+\t  .EMIOENET0EXTINTIN       (ENET0_EXT_INTIN),  
+\t  .EMIOENET0GMIICOL        (ENET0_GMII_COL_i),
+\t  .EMIOENET0GMIICRS        (ENET0_GMII_CRS_i),
+\t  .EMIOENET0GMIIRXCLK      (ENET0_GMII_RX_CLK),
+\t  .EMIOENET0GMIIRXD        (ENET0_GMII_RXD_i),
+\t  .EMIOENET0GMIIRXDV       (ENET0_GMII_RX_DV_i),
+\t  .EMIOENET0GMIIRXER       (ENET0_GMII_RX_ER_i),
+\t  .EMIOENET0GMIITXCLK      (ENET0_GMII_TX_CLK),
+\t  .EMIOENET0MDIOI          (ENET0_MDIO_I),
+\t  .EMIOENET1EXTINTIN       (ENET1_EXT_INTIN),    
+\t  .EMIOENET1GMIICOL        (ENET1_GMII_COL_i),
+\t  .EMIOENET1GMIICRS        (ENET1_GMII_CRS_i),
+\t  .EMIOENET1GMIIRXCLK      (ENET1_GMII_RX_CLK),
+\t  .EMIOENET1GMIIRXD        (ENET1_GMII_RXD_i),
+\t  .EMIOENET1GMIIRXDV       (ENET1_GMII_RX_DV_i),
+\t  .EMIOENET1GMIIRXER       (ENET1_GMII_RX_ER_i),
+\t  .EMIOENET1GMIITXCLK      (ENET1_GMII_TX_CLK),
+\t  .EMIOENET1MDIOI          (ENET1_MDIO_I),  
+\t  .EMIOGPIOI\t           (gpio_in63_0  ),
+\t  .EMIOI2C0SCLI\t           (I2C0_SCL_I),
+\t  .EMIOI2C0SDAI\t           (I2C0_SDA_I),
+\t  .EMIOI2C1SCLI\t           (I2C1_SCL_I),
+\t  .EMIOI2C1SDAI\t           (I2C1_SDA_I),
+\t  .EMIOPJTAGTCK\t\t   (PJTAG_TCK),
+\t  .EMIOPJTAGTDI\t\t   (PJTAG_TDI),
+\t  .EMIOPJTAGTMS\t\t   (PJTAG_TMS),
+\t  .EMIOSDIO0CDN            (SDIO0_CDN),
+\t  .EMIOSDIO0CLKFB\t   (SDIO0_CLK_FB  ),
+\t  .EMIOSDIO0CMDI\t   (SDIO0_CMD_I   ),
+\t  .EMIOSDIO0DATAI\t   (SDIO0_DATA_I  ),
+\t  .EMIOSDIO0WP             (SDIO0_WP),
+\t  .EMIOSDIO1CDN            (SDIO1_CDN),  
+\t  .EMIOSDIO1CLKFB\t   (SDIO1_CLK_FB  ),
+\t  .EMIOSDIO1CMDI\t   (SDIO1_CMD_I   ),
+\t  .EMIOSDIO1DATAI\t   (SDIO1_DATA_I  ),
+\t  .EMIOSDIO1WP             (SDIO1_WP),
+\t  .EMIOSPI0MI\t\t   (SPI0_MISO_I),
+\t  .EMIOSPI0SCLKI\t   (SPI0_SCLK_I),
+\t  .EMIOSPI0SI\t\t   (SPI0_MOSI_I),
+\t  .EMIOSPI0SSIN \t   (SPI0_SS_I),
+\t  .EMIOSPI1MI\t\t   (SPI1_MISO_I),
+\t  .EMIOSPI1SCLKI\t   (SPI1_SCLK_I),
+\t  .EMIOSPI1SI\t\t   (SPI1_MOSI_I),
+\t  .EMIOSPI1SSIN\t           (SPI1_SS_I),
+\t  .EMIOSRAMINTIN           (SRAM_INTIN),  
+\t  .EMIOTRACECLK\t\t   (TRACE_CLK),
+\t  .EMIOTTC0CLKI\t           ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
+\t  .EMIOTTC1CLKI\t           ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
+\t  .EMIOUART0CTSN\t   (UART0_CTSN),
+\t  .EMIOUART0DCDN\t   (UART0_DCDN),
+\t  .EMIOUART0DSRN\t   (UART0_DSRN),
+\t  .EMIOUART0RIN\t\t   (UART0_RIN ),
+\t  .EMIOUART0RX\t\t   (UART0_RX  ),
+\t  .EMIOUART1CTSN\t   (UART1_CTSN),
+\t  .EMIOUART1DCDN\t   (UART1_DCDN),
+\t  .EMIOUART1DSRN\t   (UART1_DSRN),
+\t  .EMIOUART1RIN\t\t   (UART1_RIN ),
+\t  .EMIOUART1RX\t\t   (UART1_RX  ),
+\t  .EMIOUSB0VBUSPWRFAULT    (USB0_VBUS_PWRFAULT),
+\t  .EMIOUSB1VBUSPWRFAULT    (USB1_VBUS_PWRFAULT),  
+\t  .EMIOWDTCLKI\t\t   (WDT_CLK_IN),  
+\t  .EVENTEVENTI             (EVENT_EVENTI),
+\t  .FCLKCLKTRIGN\t\t   (fclk_clktrig_gnd),
+\t  .FPGAIDLEN\t\t   (FPGA_IDLE_N),  
+\t  .FTMDTRACEINATID\t   (FTMD_TRACEIN_ATID_i),  
+\t  .FTMDTRACEINCLOCK\t   (FTMD_TRACEIN_CLK),
+\t  .FTMDTRACEINDATA\t   (FTMD_TRACEIN_DATA_i),
+\t  .FTMDTRACEINVALID\t   (FTMD_TRACEIN_VALID_i),
+\t  .FTMTF2PDEBUG\t\t   (FTMT_F2P_DEBUG  ),
+\t  .FTMTF2PTRIG\t\t   ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+\t  .FTMTP2FTRIGACK\t   ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),  
+\t  .IRQF2P\t\t   (irq_f2p_i),  
+\t  .MAXIGP0ACLK\t           (M_AXI_GP0_ACLK_temp),
+\t  .MAXIGP0ARREADY\t   (M_AXI_GP0_ARREADY),
+\t  .MAXIGP0AWREADY\t   (M_AXI_GP0_AWREADY),
+\t  .MAXIGP0BID\t           (M_AXI_GP0_BID_FULL    ),
+\t  .MAXIGP0BRESP\t           (M_AXI_GP0_BRESP  ),
+\t  .MAXIGP0BVALID\t   (M_AXI_GP0_BVALID ),
+\t  .MAXIGP0RDATA\t           (M_AXI_GP0_RDATA  ),
+\t  .MAXIGP0RID\t           (M_AXI_GP0_RID_FULL    ),
+\t  .MAXIGP0RLAST\t           (M_AXI_GP0_RLAST  ),
+\t  .MAXIGP0RRESP\t           (M_AXI_GP0_RRESP  ),
+\t  .MAXIGP0RVALID\t   (M_AXI_GP0_RVALID ),
+\t  .MAXIGP0WREADY\t   (M_AXI_GP0_WREADY ),
+\t  .MAXIGP1ACLK\t           (M_AXI_GP1_ACLK_temp ),
+\t  .MAXIGP1ARREADY\t   (M_AXI_GP1_ARREADY),
+\t  .MAXIGP1AWREADY\t   (M_AXI_GP1_AWREADY),
+\t  .MAXIGP1BID\t           (M_AXI_GP1_BID_FULL ),
+\t  .MAXIGP1BRESP\t           (M_AXI_GP1_BRESP  ),
+\t  .MAXIGP1BVALID\t   (M_AXI_GP1_BVALID ),
+\t  .MAXIGP1RDATA\t           (M_AXI_GP1_RDATA  ),
+\t  .MAXIGP1RID\t           (M_AXI_GP1_RID_FULL    ),
+\t  .MAXIGP1RLAST\t           (M_AXI_GP1_RLAST  ),
+\t  .MAXIGP1RRESP\t           (M_AXI_GP1_RRESP  ),
+\t  .MAXIGP1RVALID\t   (M_AXI_GP1_RVALID ),
+\t  .MAXIGP1WREADY\t   (M_AXI_GP1_WREADY ),  
+\t  .SAXIACPACLK\t           (S_AXI_ACP_ACLK_temp),
+\t  .SAXIACPARADDR\t   (SAXIACPARADDR_W ),
+\t  .SAXIACPARBURST\t   (SAXIACPARBURST_W),
+\t  .SAXIACPARCACHE\t   (SAXIACPARCACHE_W),
+\t  .SAXIACPARID\t           (S_AXI_ACP_ARID_in   ),
+\t  .SAXIACPARLEN\t           (SAXIACPARLEN_W  ),
+\t  .SAXIACPARLOCK\t   (SAXIACPARLOCK_W ),
+\t  .SAXIACPARPROT\t   (SAXIACPARPROT_W ),
+\t  .SAXIACPARQOS\t           (S_AXI_ACP_ARQOS  ),
+\t  .SAXIACPARSIZE\t   (SAXIACPARSIZE_W[1:0] ),
+\t  .SAXIACPARUSER\t   (SAXIACPARUSER_W ),
+\t  .SAXIACPARVALID\t   (SAXIACPARVALID_W),
+\t  .SAXIACPAWADDR\t   (SAXIACPAWADDR_W ),
+\t  .SAXIACPAWBURST\t   (SAXIACPAWBURST_W),
+\t  .SAXIACPAWCACHE\t   (SAXIACPAWCACHE_W),
+\t  .SAXIACPAWID\t           (S_AXI_ACP_AWID_in   ),
+\t  .SAXIACPAWLEN\t           (SAXIACPAWLEN_W  ),
+\t  .SAXIACPAWLOCK\t   (SAXIACPAWLOCK_W ),
+\t  .SAXIACPAWPROT\t   (SAXIACPAWPROT_W ),
+\t  .SAXIACPAWQOS\t           (S_AXI_ACP_AWQOS  ),
+\t  .SAXIACPAWSIZE\t   (SAXIACPAWSIZE_W[1:0] ),
+\t  .SAXIACPAWUSER\t   (SAXIACPAWUSER_W ),
+\t  .SAXIACPAWVALID\t   (SAXIACPAWVALID_W),
+\t  .SAXIACPBREADY\t   (SAXIACPBREADY_W ),
+\t  .SAXIACPRREADY\t   (SAXIACPRREADY_W ),
+\t  .SAXIACPWDATA\t           (SAXIACPWDATA_W  ),
+\t  .SAXIACPWID\t           (S_AXI_ACP_WID_in    ),
+\t  .SAXIACPWLAST\t           (SAXIACPWLAST_W  ),
+\t  .SAXIACPWSTRB\t           (SAXIACPWSTRB_W  ),
+\t  .SAXIACPWVALID\t   (SAXIACPWVALID_W ),
+\t  .SAXIGP0ACLK             (S_AXI_GP0_ACLK_temp   ),
+\t  .SAXIGP0ARADDR           (S_AXI_GP0_ARADDR ),
+\t  .SAXIGP0ARBURST          (S_AXI_GP0_ARBURST),
+\t  .SAXIGP0ARCACHE          (S_AXI_GP0_ARCACHE),
+\t  .SAXIGP0ARID             (S_AXI_GP0_ARID_in   ),
+\t  .SAXIGP0ARLEN            (S_AXI_GP0_ARLEN  ),
+\t  .SAXIGP0ARLOCK           (S_AXI_GP0_ARLOCK ),
+\t  .SAXIGP0ARPROT           (S_AXI_GP0_ARPROT ),
+\t  .SAXIGP0ARQOS            (S_AXI_GP0_ARQOS  ),
+\t  .SAXIGP0ARSIZE           (S_AXI_GP0_ARSIZE[1:0] ),
+\t  .SAXIGP0ARVALID          (S_AXI_GP0_ARVALID),
+\t  .SAXIGP0AWADDR           (S_AXI_GP0_AWADDR ),
+\t  .SAXIGP0AWBURST          (S_AXI_GP0_AWBURST),
+\t  .SAXIGP0AWCACHE          (S_AXI_GP0_AWCACHE),
+\t  .SAXIGP0AWID             (S_AXI_GP0_AWID_in   ),
+\t  .SAXIGP0AWLEN            (S_AXI_GP0_AWLEN  ),
+\t  .SAXIGP0AWLOCK           (S_AXI_GP0_AWLOCK ),
+\t  .SAXIGP0AWPROT           (S_AXI_GP0_AWPROT ),
+\t  .SAXIGP0AWQOS            (S_AXI_GP0_AWQOS  ),
+\t  .SAXIGP0AWSIZE           (S_AXI_GP0_AWSIZE[1:0] ),
+\t  .SAXIGP0AWVALID          (S_AXI_GP0_AWVALID),
+\t  .SAXIGP0BREADY           (S_AXI_GP0_BREADY ),
+\t  .SAXIGP0RREADY           (S_AXI_GP0_RREADY ),
+\t  .SAXIGP0WDATA            (S_AXI_GP0_WDATA  ),
+\t  .SAXIGP0WID              (S_AXI_GP0_WID_in ),
+\t  .SAXIGP0WLAST            (S_AXI_GP0_WLAST  ),
+\t  .SAXIGP0WSTRB            (S_AXI_GP0_WSTRB  ),
+\t  .SAXIGP0WVALID           (S_AXI_GP0_WVALID ),
+\t  .SAXIGP1ACLK\t           (S_AXI_GP1_ACLK_temp   ),
+\t  .SAXIGP1ARADDR\t   (S_AXI_GP1_ARADDR ),
+\t  .SAXIGP1ARBURST\t   (S_AXI_GP1_ARBURST),
+\t  .SAXIGP1ARCACHE\t   (S_AXI_GP1_ARCACHE),
+\t  .SAXIGP1ARID\t           (S_AXI_GP1_ARID_in   ),
+\t  .SAXIGP1ARLEN\t           (S_AXI_GP1_ARLEN  ),
+\t  .SAXIGP1ARLOCK\t   (S_AXI_GP1_ARLOCK ),
+\t  .SAXIGP1ARPROT\t   (S_AXI_GP1_ARPROT ),
+\t  .SAXIGP1ARQOS\t           (S_AXI_GP1_ARQOS  ),
+\t  .SAXIGP1ARSIZE\t   (S_AXI_GP1_ARSIZE[1:0] ),
+\t  .SAXIGP1ARVALID\t   (S_AXI_GP1_ARVALID),
+\t  .SAXIGP1AWADDR\t   (S_AXI_GP1_AWADDR ),
+\t  .SAXIGP1AWBURST\t   (S_AXI_GP1_AWBURST),
+\t  .SAXIGP1AWCACHE\t   (S_AXI_GP1_AWCACHE),
+\t  .SAXIGP1AWID\t           (S_AXI_GP1_AWID_in   ),
+\t  .SAXIGP1AWLEN\t           (S_AXI_GP1_AWLEN  ),
+\t  .SAXIGP1AWLOCK\t   (S_AXI_GP1_AWLOCK ),
+\t  .SAXIGP1AWPROT\t   (S_AXI_GP1_AWPROT ),
+\t  .SAXIGP1AWQOS\t           (S_AXI_GP1_AWQOS  ),
+\t  .SAXIGP1AWSIZE\t   (S_AXI_GP1_AWSIZE[1:0] ),
+\t  .SAXIGP1AWVALID\t   (S_AXI_GP1_AWVALID),
+\t  .SAXIGP1BREADY\t   (S_AXI_GP1_BREADY ),
+\t  .SAXIGP1RREADY\t   (S_AXI_GP1_RREADY ),
+\t  .SAXIGP1WDATA\t           (S_AXI_GP1_WDATA  ),
+\t  .SAXIGP1WID\t           (S_AXI_GP1_WID_in    ),
+\t  .SAXIGP1WLAST\t           (S_AXI_GP1_WLAST  ),
+\t  .SAXIGP1WSTRB\t           (S_AXI_GP1_WSTRB  ),
+\t  .SAXIGP1WVALID\t   (S_AXI_GP1_WVALID ),  
+\t  .SAXIHP0ACLK             (S_AXI_HP0_ACLK_temp   ),
+\t  .SAXIHP0ARADDR           (S_AXI_HP0_ARADDR),
+\t  .SAXIHP0ARBURST          (S_AXI_HP0_ARBURST),
+\t  .SAXIHP0ARCACHE          (S_AXI_HP0_ARCACHE),
+\t  .SAXIHP0ARID             (S_AXI_HP0_ARID_in),
+\t  .SAXIHP0ARLEN            (S_AXI_HP0_ARLEN),
+\t  .SAXIHP0ARLOCK           (S_AXI_HP0_ARLOCK),
+\t  .SAXIHP0ARPROT           (S_AXI_HP0_ARPROT),
+\t  .SAXIHP0ARQOS            (S_AXI_HP0_ARQOS),
+\t  .SAXIHP0ARSIZE           (S_AXI_HP0_ARSIZE[1:0]),
+\t  .SAXIHP0ARVALID          (S_AXI_HP0_ARVALID),
+\t  .SAXIHP0AWADDR           (S_AXI_HP0_AWADDR),
+\t  .SAXIHP0AWBURST          (S_AXI_HP0_AWBURST),
+\t  .SAXIHP0AWCACHE          (S_AXI_HP0_AWCACHE),
+\t  .SAXIHP0AWID             (S_AXI_HP0_AWID_in),
+\t  .SAXIHP0AWLEN            (S_AXI_HP0_AWLEN),
+\t  .SAXIHP0AWLOCK           (S_AXI_HP0_AWLOCK),
+\t  .SAXIHP0AWPROT           (S_AXI_HP0_AWPROT),
+\t  .SAXIHP0AWQOS            (S_AXI_HP0_AWQOS),
+\t  .SAXIHP0AWSIZE           (S_AXI_HP0_AWSIZE[1:0]),
+\t  .SAXIHP0AWVALID          (S_AXI_HP0_AWVALID),
+\t  .SAXIHP0BREADY           (S_AXI_HP0_BREADY),
+\t  .SAXIHP0RDISSUECAP1EN    (S_AXI_HP0_RDISSUECAP1_EN),
+\t  .SAXIHP0RREADY           (S_AXI_HP0_RREADY),
+\t  .SAXIHP0WDATA            (S_AXI_HP0_WDATA_in),
+\t  .SAXIHP0WID              (S_AXI_HP0_WID_in),
+\t  .SAXIHP0WLAST            (S_AXI_HP0_WLAST),
+\t  .SAXIHP0WRISSUECAP1EN    (S_AXI_HP0_WRISSUECAP1_EN),
+\t  .SAXIHP0WSTRB            (S_AXI_HP0_WSTRB_in),
+\t  .SAXIHP0WVALID           (S_AXI_HP0_WVALID),
+\t  .SAXIHP1ACLK             (S_AXI_HP1_ACLK_temp),
+\t  .SAXIHP1ARADDR           (S_AXI_HP1_ARADDR),
+\t  .SAXIHP1ARBURST          (S_AXI_HP1_ARBURST),
+\t  .SAXIHP1ARCACHE          (S_AXI_HP1_ARCACHE),
+\t  .SAXIHP1ARID             (S_AXI_HP1_ARID_in),
+\t  .SAXIHP1ARLEN            (S_AXI_HP1_ARLEN),
+\t  .SAXIHP1ARLOCK           (S_AXI_HP1_ARLOCK),
+\t  .SAXIHP1ARPROT           (S_AXI_HP1_ARPROT),
+\t  .SAXIHP1ARQOS            (S_AXI_HP1_ARQOS),
+\t  .SAXIHP1ARSIZE           (S_AXI_HP1_ARSIZE[1:0]),
+\t  .SAXIHP1ARVALID          (S_AXI_HP1_ARVALID),
+\t  .SAXIHP1AWADDR           (S_AXI_HP1_AWADDR),
+\t  .SAXIHP1AWBURST          (S_AXI_HP1_AWBURST),
+\t  .SAXIHP1AWCACHE          (S_AXI_HP1_AWCACHE),
+\t  .SAXIHP1AWID             (S_AXI_HP1_AWID_in),
+\t  .SAXIHP1AWLEN            (S_AXI_HP1_AWLEN),
+\t  .SAXIHP1AWLOCK           (S_AXI_HP1_AWLOCK),
+\t  .SAXIHP1AWPROT           (S_AXI_HP1_AWPROT),
+\t  .SAXIHP1AWQOS            (S_AXI_HP1_AWQOS),
+\t  .SAXIHP1AWSIZE           (S_AXI_HP1_AWSIZE[1:0]),
+\t  .SAXIHP1AWVALID          (S_AXI_HP1_AWVALID),
+\t  .SAXIHP1BREADY           (S_AXI_HP1_BREADY),
+\t  .SAXIHP1RDISSUECAP1EN    (S_AXI_HP1_RDISSUECAP1_EN),
+\t  .SAXIHP1RREADY           (S_AXI_HP1_RREADY),
+\t  .SAXIHP1WDATA            (S_AXI_HP1_WDATA_in),
+\t  .SAXIHP1WID              (S_AXI_HP1_WID_in),
+\t  .SAXIHP1WLAST            (S_AXI_HP1_WLAST),
+\t  .SAXIHP1WRISSUECAP1EN    (S_AXI_HP1_WRISSUECAP1_EN),
+\t  .SAXIHP1WSTRB            (S_AXI_HP1_WSTRB_in),
+\t  .SAXIHP1WVALID           (S_AXI_HP1_WVALID),
+\t  .SAXIHP2ACLK             (S_AXI_HP2_ACLK_temp),
+\t  .SAXIHP2ARADDR           (S_AXI_HP2_ARADDR),
+\t  .SAXIHP2ARBURST          (S_AXI_HP2_ARBURST),
+\t  .SAXIHP2ARCACHE          (S_AXI_HP2_ARCACHE),
+\t  .SAXIHP2ARID             (S_AXI_HP2_ARID_in),
+\t  .SAXIHP2ARLEN            (S_AXI_HP2_ARLEN),
+\t  .SAXIHP2ARLOCK           (S_AXI_HP2_ARLOCK),
+\t  .SAXIHP2ARPROT           (S_AXI_HP2_ARPROT),
+\t  .SAXIHP2ARQOS            (S_AXI_HP2_ARQOS),
+\t  .SAXIHP2ARSIZE           (S_AXI_HP2_ARSIZE[1:0]),
+\t  .SAXIHP2ARVALID          (S_AXI_HP2_ARVALID),
+\t  .SAXIHP2AWADDR           (S_AXI_HP2_AWADDR),
+\t  .SAXIHP2AWBURST          (S_AXI_HP2_AWBURST),
+\t  .SAXIHP2AWCACHE          (S_AXI_HP2_AWCACHE),
+\t  .SAXIHP2AWID             (S_AXI_HP2_AWID_in),
+\t  .SAXIHP2AWLEN            (S_AXI_HP2_AWLEN),
+\t  .SAXIHP2AWLOCK           (S_AXI_HP2_AWLOCK),
+\t  .SAXIHP2AWPROT           (S_AXI_HP2_AWPROT),
+\t  .SAXIHP2AWQOS            (S_AXI_HP2_AWQOS),
+\t  .SAXIHP2AWSIZE           (S_AXI_HP2_AWSIZE[1:0]),
+\t  .SAXIHP2AWVALID          (S_AXI_HP2_AWVALID),
+\t  .SAXIHP2BREADY           (S_AXI_HP2_BREADY),
+\t  .SAXIHP2RDISSUECAP1EN    (S_AXI_HP2_RDISSUECAP1_EN),
+\t  .SAXIHP2RREADY           (S_AXI_HP2_RREADY),
+\t  .SAXIHP2WDATA            (S_AXI_HP2_WDATA_in),
+\t  .SAXIHP2WID              (S_AXI_HP2_WID_in),
+\t  .SAXIHP2WLAST            (S_AXI_HP2_WLAST),
+\t  .SAXIHP2WRISSUECAP1EN    (S_AXI_HP2_WRISSUECAP1_EN),
+\t  .SAXIHP2WSTRB            (S_AXI_HP2_WSTRB_in),
+\t  .SAXIHP2WVALID           (S_AXI_HP2_WVALID),  
+\t  .SAXIHP3ACLK             (S_AXI_HP3_ACLK_temp),
+\t  .SAXIHP3ARADDR           (S_AXI_HP3_ARADDR ),
+\t  .SAXIHP3ARBURST          (S_AXI_HP3_ARBURST),
+\t  .SAXIHP3ARCACHE          (S_AXI_HP3_ARCACHE),
+\t  .SAXIHP3ARID             (S_AXI_HP3_ARID_in   ),
+\t  .SAXIHP3ARLEN            (S_AXI_HP3_ARLEN),
+\t  .SAXIHP3ARLOCK           (S_AXI_HP3_ARLOCK),
+\t  .SAXIHP3ARPROT           (S_AXI_HP3_ARPROT),
+\t  .SAXIHP3ARQOS            (S_AXI_HP3_ARQOS),
+\t  .SAXIHP3ARSIZE           (S_AXI_HP3_ARSIZE[1:0]),
+\t  .SAXIHP3ARVALID          (S_AXI_HP3_ARVALID),
+\t  .SAXIHP3AWADDR           (S_AXI_HP3_AWADDR),
+\t  .SAXIHP3AWBURST          (S_AXI_HP3_AWBURST),
+\t  .SAXIHP3AWCACHE          (S_AXI_HP3_AWCACHE),
+\t  .SAXIHP3AWID             (S_AXI_HP3_AWID_in),
+\t  .SAXIHP3AWLEN            (S_AXI_HP3_AWLEN),
+\t  .SAXIHP3AWLOCK           (S_AXI_HP3_AWLOCK),
+\t  .SAXIHP3AWPROT           (S_AXI_HP3_AWPROT),
+\t  .SAXIHP3AWQOS            (S_AXI_HP3_AWQOS),
+\t  .SAXIHP3AWSIZE           (S_AXI_HP3_AWSIZE[1:0]),
+\t  .SAXIHP3AWVALID          (S_AXI_HP3_AWVALID),
+\t  .SAXIHP3BREADY           (S_AXI_HP3_BREADY),
+\t  .SAXIHP3RDISSUECAP1EN    (S_AXI_HP3_RDISSUECAP1_EN),
+\t  .SAXIHP3RREADY           (S_AXI_HP3_RREADY),
+\t  .SAXIHP3WDATA            (S_AXI_HP3_WDATA_in),
+\t  .SAXIHP3WID              (S_AXI_HP3_WID_in),
+\t  .SAXIHP3WLAST            (S_AXI_HP3_WLAST),
+\t  .SAXIHP3WRISSUECAP1EN    (S_AXI_HP3_WRISSUECAP1_EN),
+\t  .SAXIHP3WSTRB            (S_AXI_HP3_WSTRB_in),
+\t  .SAXIHP3WVALID           (S_AXI_HP3_WVALID),
+\t  .DDRA\t\t           (buffered_DDR_Addr),
+\t  .DDRBA\t\t   (buffered_DDR_BankAddr),
+\t  .DDRCASB\t\t   (buffered_DDR_CAS_n),
+\t  .DDRCKE\t\t   (buffered_DDR_CKE),
+\t  .DDRCKN\t\t   (buffered_DDR_Clk_n),
+\t  .DDRCKP\t\t   (buffered_DDR_Clk),
+\t  .DDRCSB\t\t   (buffered_DDR_CS_n),
+\t  .DDRDM\t\t   (buffered_DDR_DM),
+\t  .DDRDQ\t\t   (buffered_DDR_DQ),
+\t  .DDRDQSN\t\t   (buffered_DDR_DQS_n),
+\t  .DDRDQSP\t\t   (buffered_DDR_DQS),
+\t  .DDRDRSTB                (buffered_DDR_DRSTB),
+\t  .DDRODT\t\t   (buffered_DDR_ODT),  
+\t  .DDRRASB\t\t   (buffered_DDR_RAS_n),
+\t  .DDRVRN                  (buffered_DDR_VRN),
+\t  .DDRVRP                  (buffered_DDR_VRP),
+\t  .DDRWEB                  (buffered_DDR_WEB),
+\t  .MIO\t\t\t   (buffered_MIO),
+\t  .PSCLK\t\t   (buffered_PS_CLK),  
+\t  .PSPORB\t\t   (buffered_PS_PORB),  
+\t  .PSSRSTB\t\t   (buffered_PS_SRSTB)  
+\t  
+
+\t);
+ \t
+ end
+ endgenerate
+
+
+// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
+// Otherwise a master connected to the ACP port will drive the AxUSER Ports
+assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
+assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
+
+  assign  SAXIACPARADDR_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR  : S_AXI_ACP_ARADDR;
+  assign  SAXIACPARBURST_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
+  assign  SAXIACPARCACHE_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
+  assign  SAXIACPARLEN_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN   : S_AXI_ACP_ARLEN;
+  assign  SAXIACPARLOCK_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK  : S_AXI_ACP_ARLOCK;
+  assign  SAXIACPARPROT_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT  : S_AXI_ACP_ARPROT;
+  assign  SAXIACPARSIZE_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE  : S_AXI_ACP_ARSIZE;
+  //assign  SAXIACPARUSER_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER  : S_AXI_ACP_ARUSER;
+  assign  SAXIACPARUSER_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER  : param_aruser;
+  
+  assign  SAXIACPARVALID_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
+  assign  SAXIACPAWADDR_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR  : S_AXI_ACP_AWADDR;
+  assign  SAXIACPAWBURST_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
+  
+  
+  assign  SAXIACPAWCACHE_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
+  assign  SAXIACPAWLEN_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN   : S_AXI_ACP_AWLEN;
+  assign  SAXIACPAWLOCK_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK  : S_AXI_ACP_AWLOCK;
+  assign  SAXIACPAWPROT_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT  : S_AXI_ACP_AWPROT;
+  assign  SAXIACPAWSIZE_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE  : S_AXI_ACP_AWSIZE;
+  //assign  SAXIACPAWUSER_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER  : S_AXI_ACP_AWUSER;
+  assign  SAXIACPAWUSER_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER  : param_awuser;
+  assign  SAXIACPAWVALID_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
+  assign  SAXIACPBREADY_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY  : S_AXI_ACP_BREADY;
+  assign  SAXIACPRREADY_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY  : S_AXI_ACP_RREADY;
+  assign  SAXIACPWDATA_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA   : S_AXI_ACP_WDATA;
+  assign  SAXIACPWLAST_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST   : S_AXI_ACP_WLAST;
+  assign  SAXIACPWSTRB_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB   : S_AXI_ACP_WSTRB;  
+  assign  SAXIACPWVALID_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID  : S_AXI_ACP_WVALID;      
+  
+  assign  SAXIACPARID_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID    : S_AXI_ACP_ARID;    
+  assign  SAXIACPAWID_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID    : S_AXI_ACP_AWID;      
+  assign  SAXIACPWID_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID     : S_AXI_ACP_WID;        
+  
+
+  generate
+    if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
+    
+    assign S_AXI_ACP_AWREADY          =   SAXIACPAWREADY_W;
+    assign S_AXI_ACP_WREADY           =   SAXIACPWREADY_W;
+    assign S_AXI_ACP_BID              =   SAXIACPBID_W;    
+    assign S_AXI_ACP_BRESP            =   SAXIACPBRESP_W;  
+    assign S_AXI_ACP_BVALID           =   SAXIACPBVALID_W;    
+    assign S_AXI_ACP_RDATA            =\t  SAXIACPRDATA_W;    
+    assign S_AXI_ACP_RID              =\t  SAXIACPRID_W;        
+    assign S_AXI_ACP_RLAST            =\t  SAXIACPRLAST_W;  
+    assign S_AXI_ACP_RRESP            =\t  SAXIACPRRESP_W;  
+    assign S_AXI_ACP_RVALID           =\t  SAXIACPRVALID_W; 
+    assign S_AXI_ACP_ARREADY          =\t  SAXIACPARREADY_W;
+    
+
+    end else begin : gen_atc
+    
+  processing_system7_v5_5_atc #(
+   .C_AXI_ID_WIDTH                   (C_S_AXI_ACP_ID_WIDTH),
+   .C_AXI_AWUSER_WIDTH               (5),
+   .C_AXI_ARUSER_WIDTH               (5)
+   )
+   
+  atc_i (
+
+   // Global Signals
+   .ACLK                                (S_AXI_ACP_ACLK_temp),
+   .ARESETN                             (S_AXI_ACP_ARESETN),
+
+   // Slave Interface Write Address Ports
+   .S_AXI_AWID                           (S_AXI_ACP_AWID),
+   .S_AXI_AWADDR                         (S_AXI_ACP_AWADDR),
+   .S_AXI_AWLEN                          (S_AXI_ACP_AWLEN),
+   .S_AXI_AWSIZE                         (S_AXI_ACP_AWSIZE),
+   .S_AXI_AWBURST                        (S_AXI_ACP_AWBURST),
+   .S_AXI_AWLOCK                         (S_AXI_ACP_AWLOCK),
+   .S_AXI_AWCACHE                        (S_AXI_ACP_AWCACHE),
+   .S_AXI_AWPROT                         (S_AXI_ACP_AWPROT),
+   //.S_AXI_AWUSER                         (S_AXI_ACP_AWUSER),
+   .S_AXI_AWUSER                         (param_awuser),
+   .S_AXI_AWVALID                        (S_AXI_ACP_AWVALID),
+   .S_AXI_AWREADY                        (S_AXI_ACP_AWREADY),
+   // Slave Interface Write Data Ports
+   .S_AXI_WID                            (S_AXI_ACP_WID),
+   .S_AXI_WDATA                          (S_AXI_ACP_WDATA),
+   .S_AXI_WSTRB                          (S_AXI_ACP_WSTRB),
+   .S_AXI_WLAST                          (S_AXI_ACP_WLAST),
+   .S_AXI_WUSER                          (),
+   .S_AXI_WVALID                         (S_AXI_ACP_WVALID),
+   .S_AXI_WREADY                         (S_AXI_ACP_WREADY),
+   // Slave Interface Write Response Ports
+   .S_AXI_BID                            (S_AXI_ACP_BID),
+   .S_AXI_BRESP                          (S_AXI_ACP_BRESP),
+   .S_AXI_BUSER                          (),
+   .S_AXI_BVALID                         (S_AXI_ACP_BVALID),
+   .S_AXI_BREADY                         (S_AXI_ACP_BREADY),
+   // Slave Interface Read Address Ports
+   .S_AXI_ARID                           (S_AXI_ACP_ARID),
+   .S_AXI_ARADDR                         (S_AXI_ACP_ARADDR),
+   .S_AXI_ARLEN                          (S_AXI_ACP_ARLEN),
+   .S_AXI_ARSIZE                         (S_AXI_ACP_ARSIZE),
+   .S_AXI_ARBURST                        (S_AXI_ACP_ARBURST),
+   .S_AXI_ARLOCK                         (S_AXI_ACP_ARLOCK),
+   .S_AXI_ARCACHE                        (S_AXI_ACP_ARCACHE),
+   .S_AXI_ARPROT                         (S_AXI_ACP_ARPROT),
+   //.S_AXI_ARUSER                         (S_AXI_ACP_ARUSER),
+   .S_AXI_ARUSER                         (param_aruser),
+   .S_AXI_ARVALID                        (S_AXI_ACP_ARVALID),
+   .S_AXI_ARREADY                        (S_AXI_ACP_ARREADY),
+   // Slave Interface Read Data Ports
+   .S_AXI_RID                            (S_AXI_ACP_RID),
+   .S_AXI_RDATA                          (S_AXI_ACP_RDATA),
+   .S_AXI_RRESP                          (S_AXI_ACP_RRESP),
+   .S_AXI_RLAST                          (S_AXI_ACP_RLAST),
+   .S_AXI_RUSER                          (),
+   .S_AXI_RVALID                         (S_AXI_ACP_RVALID),
+   .S_AXI_RREADY                         (S_AXI_ACP_RREADY),
+
+    // Slave Interface Write Address Ports
+   .M_AXI_AWID                           (S_AXI_ATC_AWID),
+   .M_AXI_AWADDR                         (S_AXI_ATC_AWADDR),
+   .M_AXI_AWLEN                          (S_AXI_ATC_AWLEN),
+   .M_AXI_AWSIZE                         (S_AXI_ATC_AWSIZE),
+   .M_AXI_AWBURST                        (S_AXI_ATC_AWBURST),
+   .M_AXI_AWLOCK                         (S_AXI_ATC_AWLOCK),
+   .M_AXI_AWCACHE                        (S_AXI_ATC_AWCACHE),
+   .M_AXI_AWPROT                         (S_AXI_ATC_AWPROT),
+   .M_AXI_AWUSER                         (S_AXI_ATC_AWUSER),
+   .M_AXI_AWVALID                        (S_AXI_ATC_AWVALID),
+   .M_AXI_AWREADY                        (SAXIACPAWREADY_W),
+   // Slave Interface Write Data Ports
+   .M_AXI_WID                            (S_AXI_ATC_WID),
+   .M_AXI_WDATA                          (S_AXI_ATC_WDATA),
+   .M_AXI_WSTRB                          (S_AXI_ATC_WSTRB),
+   .M_AXI_WLAST                          (S_AXI_ATC_WLAST),
+   .M_AXI_WUSER                          (),
+   .M_AXI_WVALID                         (S_AXI_ATC_WVALID),
+   .M_AXI_WREADY                         (SAXIACPWREADY_W),
+   // Slave Interface Write Response Ports
+   .M_AXI_BID                            (SAXIACPBID_W),
+   .M_AXI_BRESP                          (SAXIACPBRESP_W),
+   .M_AXI_BUSER                          (),
+   .M_AXI_BVALID                         (SAXIACPBVALID_W),
+   .M_AXI_BREADY                         (S_AXI_ATC_BREADY),
+   // Slave Interface Read Address Ports
+   .M_AXI_ARID                           (S_AXI_ATC_ARID),
+   .M_AXI_ARADDR                         (S_AXI_ATC_ARADDR),
+   .M_AXI_ARLEN                          (S_AXI_ATC_ARLEN),
+   .M_AXI_ARSIZE                         (S_AXI_ATC_ARSIZE),
+   .M_AXI_ARBURST                        (S_AXI_ATC_ARBURST),
+   .M_AXI_ARLOCK                         (S_AXI_ATC_ARLOCK),
+   .M_AXI_ARCACHE                        (S_AXI_ATC_ARCACHE),
+   .M_AXI_ARPROT                         (S_AXI_ATC_ARPROT),
+   .M_AXI_ARUSER                         (S_AXI_ATC_ARUSER),
+   .M_AXI_ARVALID                        (S_AXI_ATC_ARVALID),
+   .M_AXI_ARREADY                        (SAXIACPARREADY_W),
+   // Slave Interface Read Data Ports
+   .M_AXI_RID                            (SAXIACPRID_W),
+   .M_AXI_RDATA                          (SAXIACPRDATA_W),
+   .M_AXI_RRESP                          (SAXIACPRRESP_W),
+   .M_AXI_RLAST                          (SAXIACPRLAST_W),
+   .M_AXI_RUSER                          (),
+   .M_AXI_RVALID                         (SAXIACPRVALID_W),
+   .M_AXI_RREADY                         (S_AXI_ATC_RREADY),
+
+   
+   .ERROR_TRIGGER(),
+   .ERROR_TRANSACTION_ID()
+   );    
+
+
+
+    end
+  endgenerate
+
+
+
+
+endmodule
+
+
+
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:06 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top design_1_axi_gpio_1_0 -prefix
+//               design_1_axi_gpio_1_0_ design_1_axi_gpio_1_0_stub.v
+// Design      : design_1_axi_gpio_1_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_gpio,Vivado 2016.4"" *)
+module design_1_axi_gpio_1_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:36:35 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xlconcat_0_0_stub.v
+// Design      : design_1_xlconcat_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""xlconcat,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(In0, In1, dout)
+/* synthesis syn_black_box black_box_pad_pin=""In0[0:0],In1[0:0],dout[1:0]"" */;
+  input [0:0]In0;
+  input [0:0]In1;
+  output [1:0]dout;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:01 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top design_1_axi_gpio_0_0 -prefix
+//               design_1_axi_gpio_0_0_ design_1_axi_gpio_0_0_sim_netlist.v
+// Design      : design_1_axi_gpio_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_axi_gpio_0_0_GPIO_Core
+   (GPIO2_DBus_i,
+    GPIO_DBus_i,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    ip2bus_rdack_i,
+    ip2bus_wrack_i_D1_reg,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_o,
+    gpio2_io_t,
+    Q,
+    \\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ,
+    Read_Reg_Rst,
+    Read_Reg2_In,
+    s_axi_aclk,
+    Read_Reg_In,
+    SS,
+    bus2ip_rnw,
+    bus2ip_cs,
+    gpio_io_i,
+    gpio2_io_i,
+    E,
+    s_axi_wdata,
+    bus2ip_rnw_i_reg,
+    bus2ip_rnw_i_reg_0,
+    bus2ip_rnw_i_reg_1);
+  output [3:0]GPIO2_DBus_i;
+  output [3:0]GPIO_DBus_i;
+  output GPIO_xferAck_i;
+  output gpio_xferAck_Reg;
+  output ip2bus_rdack_i;
+  output ip2bus_wrack_i_D1_reg;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  output [3:0]gpio2_io_o;
+  output [3:0]gpio2_io_t;
+  output [3:0]Q;
+  output [3:0]\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
+  input Read_Reg_Rst;
+  input [0:3]Read_Reg2_In;
+  input s_axi_aclk;
+  input [0:3]Read_Reg_In;
+  input [0:0]SS;
+  input bus2ip_rnw;
+  input bus2ip_cs;
+  input [3:0]gpio_io_i;
+  input [3:0]gpio2_io_i;
+  input [0:0]E;
+  input [3:0]s_axi_wdata;
+  input [0:0]bus2ip_rnw_i_reg;
+  input [0:0]bus2ip_rnw_i_reg_0;
+  input [0:0]bus2ip_rnw_i_reg_1;
+
+  wire [3:0]\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire [0:0]SS;
+  wire bus2ip_cs;
+  wire bus2ip_rnw;
+  wire [0:0]bus2ip_rnw_i_reg;
+  wire [0:0]bus2ip_rnw_i_reg_0;
+  wire [0:0]bus2ip_rnw_i_reg_1;
+  wire [3:0]gpio2_io_i;
+  wire [0:3]gpio2_io_i_d2;
+  wire [3:0]gpio2_io_o;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_i;
+  wire [0:3]gpio_io_i_d2;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire iGPIO_xferAck;
+  wire ip2bus_rdack_i;
+  wire ip2bus_wrack_i_D1_reg;
+  wire s_axi_aclk;
+  wire [3:0]s_axi_wdata;
+
+  design_1_axi_gpio_0_0_cdc_sync \\Dual.INPUT_DOUBLE_REGS4 
+       (.gpio_io_i(gpio_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
+  design_1_axi_gpio_0_0_cdc_sync_0 \\Dual.INPUT_DOUBLE_REGS5 
+       (.gpio2_io_i(gpio2_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3]}));
+  FDRE \\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[0]),
+        .Q(GPIO2_DBus_i[3]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[1]),
+        .Q(GPIO2_DBus_i[2]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[2]),
+        .Q(GPIO2_DBus_i[1]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg2_In[3]),
+        .Q(GPIO2_DBus_i[0]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[0]),
+        .Q(GPIO_DBus_i[3]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[1]),
+        .Q(GPIO_DBus_i[2]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[2]),
+        .Q(GPIO_DBus_i[1]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(Read_Reg_In[3]),
+        .Q(GPIO_DBus_i[0]),
+        .R(Read_Reg_Rst));
+  FDRE \\Dual.gpio2_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[0]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[1]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[2]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio2_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i_d2[3]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[3]),
+        .Q(gpio2_io_o[3]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[2]),
+        .Q(gpio2_io_o[2]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[1]),
+        .Q(gpio2_io_o[1]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio2_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_0),
+        .D(s_axi_wdata[0]),
+        .Q(gpio2_io_o[0]),
+        .R(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[3]),
+        .Q(gpio2_io_t[3]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[2]),
+        .Q(gpio2_io_t[2]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[1]),
+        .Q(gpio2_io_t[1]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio2_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg_1),
+        .D(s_axi_wdata[0]),
+        .Q(gpio2_io_t[0]),
+        .S(SS));
+  FDRE \\Dual.gpio_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[0]),
+        .Q(\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [3]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[1]),
+        .Q(\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [2]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[2]),
+        .Q(\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [1]),
+        .R(1\'b0));
+  FDRE \\Dual.gpio_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[3]),
+        .Q(\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[3]),
+        .Q(gpio_io_o[3]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[2]),
+        .Q(gpio_io_o[2]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[1]),
+        .Q(gpio_io_o[1]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Dual.gpio_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(s_axi_wdata[0]),
+        .Q(gpio_io_o[0]),
+        .R(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[3]),
+        .Q(gpio_io_t[3]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[2]),
+        .Q(gpio_io_t[2]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[1]),
+        .Q(gpio_io_t[1]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Dual.gpio_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(bus2ip_rnw_i_reg),
+        .D(s_axi_wdata[0]),
+        .Q(gpio_io_t[0]),
+        .S(SS));
+  FDRE gpio_xferAck_Reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_xferAck_i),
+        .Q(gpio_xferAck_Reg),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    iGPIO_xferAck_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_cs),
+        .I2(gpio_xferAck_Reg),
+        .O(iGPIO_xferAck));
+  FDRE iGPIO_xferAck_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(iGPIO_xferAck),
+        .Q(GPIO_xferAck_i),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    ip2bus_rdack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_rdack_i));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    ip2bus_wrack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_wrack_i_D1_reg));
+endmodule
+
+module design_1_axi_gpio_0_0_address_decoder
+   (\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    Read_Reg_Rst,
+    s_axi_aclk,
+    Q,
+    is_read,
+    ip2bus_rdack_i_D1,
+    is_write_reg,
+    ip2bus_wrack_i_D1,
+    gpio2_io_t,
+    \\Dual.gpio2_Data_In_reg[0] ,
+    \\bus2ip_addr_i_reg[8] ,
+    bus2ip_rnw_i_reg,
+    rst_reg,
+    GPIO2_DBus_i,
+    GPIO_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    start2,
+    s_axi_aresetn);
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [3:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output Read_Reg_Rst;
+  input s_axi_aclk;
+  input [3:0]Q;
+  input is_read;
+  input ip2bus_rdack_i_D1;
+  input is_write_reg;
+  input ip2bus_wrack_i_D1;
+  input [3:0]gpio2_io_t;
+  input [3:0]\\Dual.gpio2_Data_In_reg[0] ;
+  input [2:0]\\bus2ip_addr_i_reg[8] ;
+  input bus2ip_rnw_i_reg;
+  input rst_reg;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input start2;
+  input s_axi_aresetn;
+
+  wire [3:0]D;
+  wire [3:0]\\Dual.gpio2_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire [2:0]\\bus2ip_addr_i_reg[8] ;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_write_reg;
+  wire rst_reg;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_wready;
+  wire start2;
+
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[28]_i_1 
+       (.I0(gpio2_io_t[3]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[0]));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[29]_i_1 
+       (.I0(gpio2_io_t[2]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[1]));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[30]_i_1 
+       (.I0(gpio2_io_t[1]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[2]));
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_1 
+       (.I0(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I1(gpio_xferAck_Reg),
+        .I2(bus2ip_rnw_i_reg),
+        .I3(GPIO_xferAck_i),
+        .O(Read_Reg_Rst));
+  LUT6 #(
+    .INIT(64\'h0A0000000C000000)) 
+    \\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_2 
+       (.I0(gpio2_io_t[0]),
+        .I1(\\Dual.gpio2_Data_In_reg[0] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [1]),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg2_In[3]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1 
+       (.I0(gpio_io_t[3]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [3]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[0]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1 
+       (.I0(gpio_io_t[2]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [2]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[1]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1 
+       (.I0(gpio_io_t[1]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[2]));
+  LUT6 #(
+    .INIT(64\'h000A0000000C0000)) 
+    \\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1 
+       (.I0(gpio_io_t[0]),
+        .I1(\\Dual.gpio_Data_In_reg[0] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(\\bus2ip_addr_i_reg[8] [0]),
+        .O(Read_Reg_In[3]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00001000)) 
+    \\Dual.gpio2_Data_Out[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(rst_reg),
+        .O(\\Dual.gpio2_Data_Out_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF10000000)) 
+    \\Dual.gpio2_OE[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [2]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(\\bus2ip_addr_i_reg[8] [1]),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(rst_reg),
+        .O(E));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00000100)) 
+    \\Dual.gpio_Data_Out[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(\\bus2ip_addr_i_reg[8] [0]),
+        .I5(rst_reg),
+        .O(\\Dual.gpio_Data_Out_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00040000)) 
+    \\Dual.gpio_OE[0]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\bus2ip_addr_i_reg[8] [0]),
+        .I2(\\bus2ip_addr_i_reg[8] [1]),
+        .I3(\\bus2ip_addr_i_reg[8] [2]),
+        .I4(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I5(rst_reg),
+        .O(\\Dual.gpio_OE_reg[0] ));
+  LUT5 #(
+    .INIT(32\'h000E0000)) 
+    \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1 
+       (.I0(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I1(start2),
+        .I2(s_axi_wready),
+        .I3(s_axi_arready),
+        .I4(s_axi_aresetn),
+        .O(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
+  FDRE \\MEM_DECODE_GEN[0].cs_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
+        .Q(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[28]_i_1 
+       (.I0(GPIO2_DBus_i[3]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[3]),
+        .O(D[3]));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[29]_i_1 
+       (.I0(GPIO2_DBus_i[2]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[2]),
+        .O(D[2]));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[30]_i_1 
+       (.I0(GPIO2_DBus_i[1]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[1]),
+        .O(D[1]));
+  LUT6 #(
+    .INIT(64\'hABAAAAAAA8AAAAAA)) 
+    \\ip2bus_data_i_D1[31]_i_1 
+       (.I0(GPIO2_DBus_i[0]),
+        .I1(\\bus2ip_addr_i_reg[8] [1]),
+        .I2(\\bus2ip_addr_i_reg[8] [2]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(bus2ip_rnw_i_reg),
+        .I5(GPIO_DBus_i[0]),
+        .O(D[0]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00020000)) 
+    s_axi_arready_INST_0
+       (.I0(Q[3]),
+        .I1(Q[2]),
+        .I2(Q[1]),
+        .I3(Q[0]),
+        .I4(is_read),
+        .I5(ip2bus_rdack_i_D1),
+        .O(s_axi_arready));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00020000)) 
+    s_axi_wready_INST_0
+       (.I0(Q[3]),
+        .I1(Q[2]),
+        .I2(Q[1]),
+        .I3(Q[0]),
+        .I4(is_write_reg),
+        .I5(ip2bus_wrack_i_D1),
+        .O(s_axi_wready));
+endmodule
+
+(* C_ALL_INPUTS = ""1"" *) (* C_ALL_INPUTS_2 = ""1"" *) (* C_ALL_OUTPUTS = ""0"" *) 
+(* C_ALL_OUTPUTS_2 = ""0"" *) (* C_DOUT_DEFAULT = ""0"" *) (* C_DOUT_DEFAULT_2 = ""0"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_GPIO2_WIDTH = ""4"" *) (* C_GPIO_WIDTH = ""4"" *) 
+(* C_INTERRUPT_PRESENT = ""0"" *) (* C_IS_DUAL = ""1"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* C_TRI_DEFAULT = ""-1"" *) (* C_TRI_DEFAULT_2 = ""-1"" *) 
+(* downgradeipidentifiedwarnings = ""yes"" *) (* ip_group = ""LOGICORE"" *) 
+module design_1_axi_gpio_0_0_axi_gpio
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_i,
+    gpio2_io_o,
+    gpio2_io_t);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rst"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* sigis = ""INTR_LEVEL_HIGH"" *) output ip2intc_irpt;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  input [3:0]gpio2_io_i;
+  output [3:0]gpio2_io_o;
+  output [3:0]gpio2_io_t;
+
+  wire \\<const0> ;
+  wire AXI_LITE_IPIF_I_n_11;
+  wire AXI_LITE_IPIF_I_n_12;
+  wire AXI_LITE_IPIF_I_n_21;
+  wire AXI_LITE_IPIF_I_n_22;
+  wire [28:31]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus;
+  wire [28:31]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [0:3]gpio2_Data_In;
+  wire [3:0]gpio2_io_i;
+  wire [3:0]gpio2_io_o;
+  wire [3:0]gpio2_io_t;
+  wire [0:3]gpio_Data_In;
+  wire gpio_core_1_n_11;
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]ip2bus_data_i_D1;
+  wire ip2bus_rdack_i;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rst"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  assign ip2intc_irpt = \\<const0> ;
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\<const0> ;
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\<const0> ;
+  assign s_axi_rdata[30] = \\<const0> ;
+  assign s_axi_rdata[29] = \\<const0> ;
+  assign s_axi_rdata[28] = \\<const0> ;
+  assign s_axi_rdata[27] = \\<const0> ;
+  assign s_axi_rdata[26] = \\<const0> ;
+  assign s_axi_rdata[25] = \\<const0> ;
+  assign s_axi_rdata[24] = \\<const0> ;
+  assign s_axi_rdata[23] = \\<const0> ;
+  assign s_axi_rdata[22] = \\<const0> ;
+  assign s_axi_rdata[21] = \\<const0> ;
+  assign s_axi_rdata[20] = \\<const0> ;
+  assign s_axi_rdata[19] = \\<const0> ;
+  assign s_axi_rdata[18] = \\<const0> ;
+  assign s_axi_rdata[17] = \\<const0> ;
+  assign s_axi_rdata[16] = \\<const0> ;
+  assign s_axi_rdata[15] = \\<const0> ;
+  assign s_axi_rdata[14] = \\<const0> ;
+  assign s_axi_rdata[13] = \\<const0> ;
+  assign s_axi_rdata[12] = \\<const0> ;
+  assign s_axi_rdata[11] = \\<const0> ;
+  assign s_axi_rdata[10] = \\<const0> ;
+  assign s_axi_rdata[9] = \\<const0> ;
+  assign s_axi_rdata[8] = \\<const0> ;
+  assign s_axi_rdata[7] = \\<const0> ;
+  assign s_axi_rdata[6] = \\<const0> ;
+  assign s_axi_rdata[5] = \\<const0> ;
+  assign s_axi_rdata[4] = \\<const0> ;
+  assign s_axi_rdata[3:0] = \\^s_axi_rdata [3:0];
+  assign s_axi_rresp[1] = \\<const0> ;
+  assign s_axi_rresp[0] = \\<const0> ;
+  design_1_axi_gpio_0_0_axi_lite_ipif AXI_LITE_IPIF_I
+       (.D(GPIO_DBus),
+        .\\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_12),
+        .\\Dual.gpio_Data_In_reg[0] ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .\\Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_22),
+        .\\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_21),
+        .E(AXI_LITE_IPIF_I_n_11),
+        .GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
+        .GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] (ip2bus_data_i_D1),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(\\^s_axi_rdata ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+  GND GND
+       (.G(\\<const0> ));
+  design_1_axi_gpio_0_0_GPIO_Core gpio_core_1
+       (.\\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .E(AXI_LITE_IPIF_I_n_22),
+        .GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
+        .GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .SS(bus2ip_reset),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_rnw(bus2ip_rnw),
+        .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_21),
+        .bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_12),
+        .bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_11),
+        .gpio2_io_i(gpio2_io_i),
+        .gpio2_io_o(gpio2_io_o),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i(ip2bus_rdack_i),
+        .ip2bus_wrack_i_D1_reg(gpio_core_1_n_11),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_wdata(s_axi_wdata[3:0]));
+  FDRE \\ip2bus_data_i_D1_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus[3]),
+        .Q(ip2bus_data_i_D1[3]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus[2]),
+        .Q(ip2bus_data_i_D1[2]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus[1]),
+        .Q(ip2bus_data_i_D1[1]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus[0]),
+        .Q(ip2bus_data_i_D1[0]),
+        .R(bus2ip_reset));
+  FDRE ip2bus_rdack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_i),
+        .Q(ip2bus_rdack_i_D1),
+        .R(bus2ip_reset));
+  FDRE ip2bus_wrack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_core_1_n_11),
+        .Q(ip2bus_wrack_i_D1),
+        .R(bus2ip_reset));
+endmodule
+
+module design_1_axi_gpio_0_0_axi_lite_ipif
+   (bus2ip_reset,
+    bus2ip_rnw,
+    bus2ip_cs,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    Read_Reg_Rst,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    s_axi_bready,
+    s_axi_rready,
+    s_axi_awaddr,
+    s_axi_araddr,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    gpio2_io_t,
+    Q,
+    GPIO2_DBus_i,
+    GPIO_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    s_axi_aresetn,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output bus2ip_reset;
+  output bus2ip_rnw;
+  output bus2ip_cs;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [3:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output Read_Reg_Rst;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input s_axi_bready;
+  input s_axi_rready;
+  input [2:0]s_axi_awaddr;
+  input [2:0]s_axi_araddr;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [3:0]gpio2_io_t;
+  input [3:0]Q;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input s_axi_aresetn;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  design_1_axi_gpio_0_0_slave_attachment I_SLAVE_ATTACHMENT
+       (.D(D),
+        .\\Dual.gpio2_Data_Out_reg[0] (\\Dual.gpio2_Data_Out_reg[0] ),
+        .\\Dual.gpio2_OE_reg[0] (bus2ip_rnw),
+        .\\Dual.gpio_Data_In_reg[0] (\\Dual.gpio_Data_In_reg[0] ),
+        .\\Dual.gpio_Data_Out_reg[0] (\\Dual.gpio_Data_Out_reg[0] ),
+        .\\Dual.gpio_OE_reg[0] (\\Dual.gpio_OE_reg[0] ),
+        .E(E),
+        .GPIO2_DBus_i(GPIO2_DBus_i),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
+        .Q(Q),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .bus2ip_rnw_i_reg_0(bus2ip_reset),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] (\\ip2bus_data_i_D1_reg[28] ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module design_1_axi_gpio_0_0_cdc_sync
+   (scndry_vect_out,
+    gpio_io_i,
+    s_axi_aclk);
+  output [3:0]scndry_vect_out;
+  input [3:0]gpio_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""cdc_sync"" *) 
+module design_1_axi_gpio_0_0_cdc_sync_0
+   (scndry_vect_out,
+    gpio2_io_i,
+    s_axi_aclk);
+  output [3:0]scndry_vect_out;
+  input [3:0]gpio2_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]gpio2_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio2_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_gpio_0_0,axi_gpio,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_gpio,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module design_1_axi_gpio_0_0
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    gpio_io_i,
+    gpio2_io_i);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_I"" *) input [3:0]gpio_io_i;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO2 TRI_I"" *) input [3:0]gpio2_io_i;
+
+  wire [3:0]gpio2_io_i;
+  wire [3:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire NLW_U0_ip2intc_irpt_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio2_io_o_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio2_io_t_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio_io_o_UNCONNECTED;
+  wire [3:0]NLW_U0_gpio_io_t_UNCONNECTED;
+
+  (* C_ALL_INPUTS = ""1"" *) 
+  (* C_ALL_INPUTS_2 = ""1"" *) 
+  (* C_ALL_OUTPUTS = ""0"" *) 
+  (* C_ALL_OUTPUTS_2 = ""0"" *) 
+  (* C_DOUT_DEFAULT = ""0"" *) 
+  (* C_DOUT_DEFAULT_2 = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_GPIO2_WIDTH = ""4"" *) 
+  (* C_GPIO_WIDTH = ""4"" *) 
+  (* C_INTERRUPT_PRESENT = ""0"" *) 
+  (* C_IS_DUAL = ""1"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_TRI_DEFAULT = ""-1"" *) 
+  (* C_TRI_DEFAULT_2 = ""-1"" *) 
+  (* downgradeipidentifiedwarnings = ""yes"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  design_1_axi_gpio_0_0_axi_gpio U0
+       (.gpio2_io_i(gpio2_io_i),
+        .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[3:0]),
+        .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[3:0]),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[3:0]),
+        .gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[3:0]),
+        .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module design_1_axi_gpio_0_0_slave_attachment
+   (bus2ip_rnw_i_reg_0,
+    \\Dual.gpio2_OE_reg[0] ,
+    \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    s_axi_wready,
+    Read_Reg2_In,
+    E,
+    \\Dual.gpio2_Data_Out_reg[0] ,
+    D,
+    Read_Reg_In,
+    \\Dual.gpio_OE_reg[0] ,
+    \\Dual.gpio_Data_Out_reg[0] ,
+    Read_Reg_Rst,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    s_axi_bready,
+    s_axi_rready,
+    s_axi_awaddr,
+    s_axi_araddr,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    gpio2_io_t,
+    Q,
+    GPIO2_DBus_i,
+    GPIO_DBus_i,
+    gpio_io_t,
+    \\Dual.gpio_Data_In_reg[0] ,
+    s_axi_aresetn,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output bus2ip_rnw_i_reg_0;
+  output \\Dual.gpio2_OE_reg[0] ;
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:3]Read_Reg2_In;
+  output [0:0]E;
+  output [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  output [3:0]D;
+  output [0:3]Read_Reg_In;
+  output [0:0]\\Dual.gpio_OE_reg[0] ;
+  output [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  output Read_Reg_Rst;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input s_axi_bready;
+  input s_axi_rready;
+  input [2:0]s_axi_awaddr;
+  input [2:0]s_axi_araddr;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [3:0]gpio2_io_t;
+  input [3:0]Q;
+  input [3:0]GPIO2_DBus_i;
+  input [3:0]GPIO_DBus_i;
+  input [3:0]gpio_io_t;
+  input [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  input s_axi_aresetn;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]\\Dual.gpio2_Data_Out_reg[0] ;
+  wire \\Dual.gpio2_OE_reg[0] ;
+  wire [3:0]\\Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Dual.gpio_OE_reg[0] ;
+  wire [0:0]E;
+  wire [3:0]GPIO2_DBus_i;
+  wire [3:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  wire [3:0]Q;
+  wire [0:3]Read_Reg2_In;
+  wire [0:3]Read_Reg_In;
+  wire Read_Reg_Rst;
+  wire [0:6]bus2ip_addr;
+  wire \\bus2ip_addr_i[2]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[3]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_1_n_0 ;
+  wire bus2ip_rnw_i06_out;
+  wire bus2ip_rnw_i_reg_0;
+  wire clear;
+  wire [3:0]gpio2_io_t;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_write;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire [1:0]p_0_out;
+  wire p_1_in;
+  wire [3:0]plusOp;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [3:0]s_axi_rdata;
+  wire s_axi_rdata_i;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire \\state[1]_i_2_n_0 ;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[1]),
+        .I1(state[0]),
+        .O(clear));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(clear));
+  design_1_axi_gpio_0_0_address_decoder I_DECODER
+       (.D(D),
+        .\\Dual.gpio2_Data_In_reg[0] (Q),
+        .\\Dual.gpio2_Data_Out_reg[0] (\\Dual.gpio2_Data_Out_reg[0] ),
+        .\\Dual.gpio_Data_In_reg[0] (\\Dual.gpio_Data_In_reg[0] ),
+        .\\Dual.gpio_Data_Out_reg[0] (\\Dual.gpio_Data_Out_reg[0] ),
+        .\\Dual.gpio_OE_reg[0] (\\Dual.gpio_OE_reg[0] ),
+        .E(E),
+        .GPIO2_DBus_i(GPIO2_DBus_i),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .Read_Reg2_In(Read_Reg2_In),
+        .Read_Reg_In(Read_Reg_In),
+        .Read_Reg_Rst(Read_Reg_Rst),
+        .\\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
+        .bus2ip_rnw_i_reg(\\Dual.gpio2_OE_reg[0] ),
+        .gpio2_io_t(gpio2_io_t),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .rst_reg(bus2ip_rnw_i_reg_0),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_wready(s_axi_wready),
+        .start2(start2));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_awaddr[0]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[0]),
+        .O(\\bus2ip_addr_i[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_awaddr[1]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[1]),
+        .O(\\bus2ip_addr_i[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hABAAA8AA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_awaddr[2]),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .O(\\bus2ip_addr_i[8]_i_1_n_0 ));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(\\bus2ip_addr_i[2]_i_1_n_0 ),
+        .Q(bus2ip_addr[6]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(\\bus2ip_addr_i[3]_i_1_n_0 ),
+        .Q(bus2ip_addr[5]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .Q(bus2ip_addr[0]),
+        .R(bus2ip_rnw_i_reg_0));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT3 #(
+    .INIT(8\'h02)) 
+    bus2ip_rnw_i_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state[0]),
+        .I2(state[1]),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(start2_i_1_n_0),
+        .D(bus2ip_rnw_i06_out),
+        .Q(\\Dual.gpio2_OE_reg[0] ),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT5 #(
+    .INIT(32\'h3FFA000A)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(\\state[1]_i_2_n_0 ),
+        .I2(state[1]),
+        .I3(state[0]),
+        .I4(is_read),
+        .O(is_read_i_1_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT6 #(
+    .INIT(64\'h1000FFFF10000000)) 
+    is_write_i_1
+       (.I0(state[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_axi_wvalid),
+        .I3(s_axi_awvalid),
+        .I4(is_write),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hF88800000000FFFF)) 
+    is_write_i_2
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .I4(state[1]),
+        .I5(state[0]),
+        .O(is_write));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    rst_i_1
+       (.I0(s_axi_aresetn),
+        .O(p_1_in));
+  FDRE rst_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(bus2ip_rnw_i_reg_0),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_wready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[3]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(s_axi_rdata_i));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[28] [0]),
+        .Q(s_axi_rdata[0]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[28] [1]),
+        .Q(s_axi_rdata[1]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[28] [2]),
+        .Q(s_axi_rdata[2]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(s_axi_rdata_i),
+        .D(\\ip2bus_data_i_D1_reg[28] [3]),
+        .Q(s_axi_rdata[3]),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_arready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT5 #(
+    .INIT(32\'h000000F8)) 
+    start2_i_1
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_arvalid),
+        .I3(state[0]),
+        .I4(state[1]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(bus2ip_rnw_i_reg_0));
+  LUT5 #(
+    .INIT(32\'h0FFFAACC)) 
+    \\state[0]_i_1 
+       (.I0(s_axi_wready),
+        .I1(s_axi_arvalid),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(p_0_out[0]));
+  LUT6 #(
+    .INIT(64\'h2E2E2E2ECCCCFFCC)) 
+    \\state[1]_i_1 
+       (.I0(s_axi_arready),
+        .I1(state[1]),
+        .I2(\\state[1]_i_2_n_0 ),
+        .I3(\\state[1]_i_3_n_0 ),
+        .I4(s_axi_arvalid),
+        .I5(state[0]),
+        .O(p_0_out[1]));
+  LUT4 #(
+    .INIT(16\'hF888)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(\\state[1]_i_2_n_0 ));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\state[1]_i_3 
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[0]),
+        .Q(state[0]),
+        .R(bus2ip_rnw_i_reg_0));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[1]),
+        .Q(state[1]),
+        .R(bus2ip_rnw_i_reg_0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:11:41 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
+// Design      : design_1_processing_system7_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""processing_system7_v5_5_processing_system7,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    SDIO0_WP,
+    UART0_TX,
+    UART0_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    FCLK_CLK0,
+    FCLK_RESET0_N,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_I"" *) input I2C0_SDA_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_O"" *) output I2C0_SDA_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SDA_T"" *) output I2C0_SDA_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_I"" *) input I2C0_SCL_I;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_O"" *) output I2C0_SCL_O;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:iic:1.0 IIC_0 SCL_T"" *) output I2C0_SCL_T;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:sdio:1.0 SDIO_0 WP"" *) input SDIO0_WP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 TxD"" *) output UART0_TX;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:uart:1.0 UART_0 RxD"" *) input UART0_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"" *) output [1:0]USB0_PORT_INDCTL;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"" *) output USB0_VBUS_PWRSELECT;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"" *) input USB0_VBUS_PWRFAULT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"" *) output M_AXI_GP0_ARVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"" *) output M_AXI_GP0_AWVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"" *) output M_AXI_GP0_BREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"" *) output M_AXI_GP0_RREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"" *) output M_AXI_GP0_WLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"" *) output M_AXI_GP0_WVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"" *) output [11:0]M_AXI_GP0_ARID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"" *) output [11:0]M_AXI_GP0_AWID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"" *) output [11:0]M_AXI_GP0_WID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"" *) output [1:0]M_AXI_GP0_ARBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"" *) output [1:0]M_AXI_GP0_ARLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"" *) output [2:0]M_AXI_GP0_ARSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"" *) output [1:0]M_AXI_GP0_AWBURST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"" *) output [1:0]M_AXI_GP0_AWLOCK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"" *) output [2:0]M_AXI_GP0_AWSIZE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"" *) output [2:0]M_AXI_GP0_ARPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"" *) output [2:0]M_AXI_GP0_AWPROT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"" *) output [31:0]M_AXI_GP0_ARADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"" *) output [31:0]M_AXI_GP0_AWADDR;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"" *) output [31:0]M_AXI_GP0_WDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"" *) output [3:0]M_AXI_GP0_ARCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"" *) output [3:0]M_AXI_GP0_ARLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"" *) output [3:0]M_AXI_GP0_ARQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"" *) output [3:0]M_AXI_GP0_AWCACHE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"" *) output [3:0]M_AXI_GP0_AWLEN;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"" *) output [3:0]M_AXI_GP0_AWQOS;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"" *) output [3:0]M_AXI_GP0_WSTRB;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"" *) input M_AXI_GP0_ACLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"" *) input M_AXI_GP0_ARREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"" *) input M_AXI_GP0_AWREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"" *) input M_AXI_GP0_BVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"" *) input M_AXI_GP0_RLAST;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"" *) input M_AXI_GP0_RVALID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"" *) input M_AXI_GP0_WREADY;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"" *) input [11:0]M_AXI_GP0_BID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"" *) input [11:0]M_AXI_GP0_RID;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"" *) input [1:0]M_AXI_GP0_BRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"" *) input [1:0]M_AXI_GP0_RRESP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"" *) input [31:0]M_AXI_GP0_RDATA;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"" *) output FCLK_CLK0;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"" *) output FCLK_RESET0_N;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"" *) inout [53:0]MIO;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CAS_N"" *) inout DDR_CAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CKE"" *) inout DDR_CKE;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_N"" *) inout DDR_Clk_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CK_P"" *) inout DDR_Clk;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR CS_N"" *) inout DDR_CS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RESET_N"" *) inout DDR_DRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ODT"" *) inout DDR_ODT;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR RAS_N"" *) inout DDR_RAS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR WE_N"" *) inout DDR_WEB;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR BA"" *) inout [2:0]DDR_BankAddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR ADDR"" *) inout [14:0]DDR_Addr;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"" *) inout DDR_VRN;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"" *) inout DDR_VRP;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DM"" *) inout [3:0]DDR_DM;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQ"" *) inout [31:0]DDR_DQ;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_N"" *) inout [3:0]DDR_DQS_n;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:ddrx:1.0 DDR DQS_P"" *) inout [3:0]DDR_DQS;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"" *) inout PS_SRSTB;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"" *) inout PS_CLK;
+  (* X_INTERFACE_INFO = ""xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"" *) inout PS_PORB;
+
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire FCLK_CLK0;
+  wire FCLK_RESET0_N;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [2:0]M_AXI_GP0_ARSIZE;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [2:0]M_AXI_GP0_AWSIZE;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_WP;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
+  wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
+  wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA0_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA1_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA2_RSTN_UNCONNECTED;
+  wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
+  wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
+  wire NLW_inst_DMA3_RSTN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
+  wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
+  wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
+  wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
+  wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK1_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK2_UNCONNECTED;
+  wire NLW_inst_FCLK_CLK3_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
+  wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
+  wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
+  wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
+  wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
+  wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
+  wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
+  wire NLW_inst_PJTAG_TDO_UNCONNECTED;
+  wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO0_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO0_LED_UNCONNECTED;
+  wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
+  wire NLW_inst_SDIO1_CLK_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
+  wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
+  wire NLW_inst_SDIO1_LED_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI0_SS_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
+  wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
+  wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_O_UNCONNECTED;
+  wire NLW_inst_SPI1_SS_T_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
+  wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
+  wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
+  wire NLW_inst_TRACE_CTL_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
+  wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
+  wire NLW_inst_UART0_DTRN_UNCONNECTED;
+  wire NLW_inst_UART0_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_DTRN_UNCONNECTED;
+  wire NLW_inst_UART1_RTSN_UNCONNECTED;
+  wire NLW_inst_UART1_TX_UNCONNECTED;
+  wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
+  wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
+  wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
+  wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
+  wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
+  wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
+  wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
+  wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
+  wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
+  wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
+  wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
+  wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
+  wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
+  wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
+  wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
+  wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
+  wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
+  wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
+  wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
+  wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
+  wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
+PULLUP pullup_MIO_0
+       (.O(MIO[0]));
+PULLUP pullup_MIO_9
+       (.O(MIO[9]));
+PULLUP pullup_MIO_10
+       (.O(MIO[10]));
+PULLUP pullup_MIO_11
+       (.O(MIO[11]));
+PULLUP pullup_MIO_12
+       (.O(MIO[12]));
+PULLUP pullup_MIO_13
+       (.O(MIO[13]));
+PULLUP pullup_MIO_14
+       (.O(MIO[14]));
+PULLUP pullup_MIO_15
+       (.O(MIO[15]));
+PULLUP pullup_MIO_46
+       (.O(MIO[46]));
+
+  (* C_DM_WIDTH = ""4"" *) 
+  (* C_DQS_WIDTH = ""4"" *) 
+  (* C_DQ_WIDTH = ""32"" *) 
+  (* C_EMIO_GPIO_WIDTH = ""64"" *) 
+  (* C_EN_EMIO_ENET0 = ""0"" *) 
+  (* C_EN_EMIO_ENET1 = ""0"" *) 
+  (* C_EN_EMIO_PJTAG = ""0"" *) 
+  (* C_EN_EMIO_TRACE = ""0"" *) 
+  (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+  (* C_FCLK_CLK1_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK2_BUF = ""FALSE"" *) 
+  (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+  (* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) 
+  (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+  (* C_INCLUDE_TRACE_BUFFER = ""0"" *) 
+  (* C_IRQ_F2P_MODE = ""DIRECT"" *) 
+  (* C_MIO_PRIMITIVE = ""54"" *) 
+  (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) 
+  (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) 
+  (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+  (* C_NUM_F2P_INTR_INPUTS = ""1"" *) 
+  (* C_PACKAGE_NAME = ""clg400"" *) 
+  (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+  (* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) 
+  (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+  (* C_S_AXI_GP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP0_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) 
+  (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+  (* C_S_AXI_HP3_ID_WIDTH = ""6"" *) 
+  (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) 
+  (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+  (* C_TRACE_INTERNAL_WIDTH = ""2"" *) 
+  (* C_TRACE_PIPELINE_WIDTH = ""8"" *) 
+  (* C_USE_AXI_NONSECURE = ""0"" *) 
+  (* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) 
+  (* C_USE_M_AXI_GP0 = ""1"" *) 
+  (* C_USE_M_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_ACP = ""0"" *) 
+  (* C_USE_S_AXI_GP0 = ""0"" *) 
+  (* C_USE_S_AXI_GP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP0 = ""0"" *) 
+  (* C_USE_S_AXI_HP1 = ""0"" *) 
+  (* C_USE_S_AXI_HP2 = ""0"" *) 
+  (* C_USE_S_AXI_HP3 = ""0"" *) 
+  (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) 
+  (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+  (* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
+       (.CAN0_PHY_RX(1\'b0),
+        .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
+        .CAN1_PHY_RX(1\'b0),
+        .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
+        .Core0_nFIQ(1\'b0),
+        .Core0_nIRQ(1\'b0),
+        .Core1_nFIQ(1\'b0),
+        .Core1_nIRQ(1\'b0),
+        .DDR_ARB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .DDR_Addr(DDR_Addr),
+        .DDR_BankAddr(DDR_BankAddr),
+        .DDR_CAS_n(DDR_CAS_n),
+        .DDR_CKE(DDR_CKE),
+        .DDR_CS_n(DDR_CS_n),
+        .DDR_Clk(DDR_Clk),
+        .DDR_Clk_n(DDR_Clk_n),
+        .DDR_DM(DDR_DM),
+        .DDR_DQ(DDR_DQ),
+        .DDR_DQS(DDR_DQS),
+        .DDR_DQS_n(DDR_DQS_n),
+        .DDR_DRSTB(DDR_DRSTB),
+        .DDR_ODT(DDR_ODT),
+        .DDR_RAS_n(DDR_RAS_n),
+        .DDR_VRN(DDR_VRN),
+        .DDR_VRP(DDR_VRP),
+        .DDR_WEB(DDR_WEB),
+        .DMA0_ACLK(1\'b0),
+        .DMA0_DAREADY(1\'b0),
+        .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
+        .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
+        .DMA0_DRLAST(1\'b0),
+        .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
+        .DMA0_DRTYPE({1\'b0,1\'b0}),
+        .DMA0_DRVALID(1\'b0),
+        .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
+        .DMA1_ACLK(1\'b0),
+        .DMA1_DAREADY(1\'b0),
+        .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
+        .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
+        .DMA1_DRLAST(1\'b0),
+        .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
+        .DMA1_DRTYPE({1\'b0,1\'b0}),
+        .DMA1_DRVALID(1\'b0),
+        .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
+        .DMA2_ACLK(1\'b0),
+        .DMA2_DAREADY(1\'b0),
+        .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
+        .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
+        .DMA2_DRLAST(1\'b0),
+        .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
+        .DMA2_DRTYPE({1\'b0,1\'b0}),
+        .DMA2_DRVALID(1\'b0),
+        .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
+        .DMA3_ACLK(1\'b0),
+        .DMA3_DAREADY(1\'b0),
+        .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
+        .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
+        .DMA3_DRLAST(1\'b0),
+        .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
+        .DMA3_DRTYPE({1\'b0,1\'b0}),
+        .DMA3_DRVALID(1\'b0),
+        .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
+        .ENET0_EXT_INTIN(1\'b0),
+        .ENET0_GMII_COL(1\'b0),
+        .ENET0_GMII_CRS(1\'b0),
+        .ENET0_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET0_GMII_RX_CLK(1\'b0),
+        .ENET0_GMII_RX_DV(1\'b0),
+        .ENET0_GMII_RX_ER(1\'b0),
+        .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET0_GMII_TX_CLK(1\'b0),
+        .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
+        .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
+        .ENET0_MDIO_I(1\'b0),
+        .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
+        .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
+        .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
+        .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
+        .ENET1_EXT_INTIN(1\'b0),
+        .ENET1_GMII_COL(1\'b0),
+        .ENET1_GMII_CRS(1\'b0),
+        .ENET1_GMII_RXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .ENET1_GMII_RX_CLK(1\'b0),
+        .ENET1_GMII_RX_DV(1\'b0),
+        .ENET1_GMII_RX_ER(1\'b0),
+        .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
+        .ENET1_GMII_TX_CLK(1\'b0),
+        .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
+        .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
+        .ENET1_MDIO_I(1\'b0),
+        .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
+        .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
+        .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
+        .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
+        .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
+        .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
+        .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
+        .EVENT_EVENTI(1\'b0),
+        .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
+        .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
+        .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
+        .FCLK_CLK0(FCLK_CLK0),
+        .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
+        .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
+        .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
+        .FCLK_CLKTRIG0_N(1\'b0),
+        .FCLK_CLKTRIG1_N(1\'b0),
+        .FCLK_CLKTRIG2_N(1\'b0),
+        .FCLK_CLKTRIG3_N(1\'b0),
+        .FCLK_RESET0_N(FCLK_RESET0_N),
+        .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
+        .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
+        .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
+        .FPGA_IDLE_N(1\'b0),
+        .FTMD_TRACEIN_ATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_CLK(1\'b0),
+        .FTMD_TRACEIN_DATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMD_TRACEIN_VALID(1\'b0),
+        .FTMT_F2P_DEBUG({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
+        .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
+        .FTMT_F2P_TRIG_0(1\'b0),
+        .FTMT_F2P_TRIG_1(1\'b0),
+        .FTMT_F2P_TRIG_2(1\'b0),
+        .FTMT_F2P_TRIG_3(1\'b0),
+        .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
+        .FTMT_P2F_TRIGACK_0(1\'b0),
+        .FTMT_P2F_TRIGACK_1(1\'b0),
+        .FTMT_P2F_TRIGACK_2(1\'b0),
+        .FTMT_P2F_TRIGACK_3(1\'b0),
+        .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
+        .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
+        .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
+        .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
+        .GPIO_I({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
+        .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
+        .I2C0_SCL_I(I2C0_SCL_I),
+        .I2C0_SCL_O(I2C0_SCL_O),
+        .I2C0_SCL_T(I2C0_SCL_T),
+        .I2C0_SDA_I(I2C0_SDA_I),
+        .I2C0_SDA_O(I2C0_SDA_O),
+        .I2C0_SDA_T(I2C0_SDA_T),
+        .I2C1_SCL_I(1\'b0),
+        .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
+        .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
+        .I2C1_SDA_I(1\'b0),
+        .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
+        .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
+        .IRQ_F2P(1\'b0),
+        .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
+        .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
+        .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
+        .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
+        .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
+        .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
+        .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
+        .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
+        .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
+        .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
+        .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
+        .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
+        .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
+        .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
+        .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
+        .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
+        .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
+        .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
+        .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
+        .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
+        .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
+        .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
+        .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
+        .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
+        .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
+        .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
+        .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
+        .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
+        .MIO(MIO),
+        .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+        .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+        .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+        .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+        .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
+        .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+        .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+        .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+        .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+        .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+        .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+        .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+        .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+        .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+        .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+        .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+        .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+        .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+        .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+        .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+        .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+        .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+        .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+        .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+        .M_AXI_GP0_BID(M_AXI_GP0_BID),
+        .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+        .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+        .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+        .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+        .M_AXI_GP0_RID(M_AXI_GP0_RID),
+        .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+        .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+        .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+        .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+        .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+        .M_AXI_GP0_WID(M_AXI_GP0_WID),
+        .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+        .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+        .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+        .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+        .M_AXI_GP1_ACLK(1\'b0),
+        .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
+        .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_ARREADY(1\'b0),
+        .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
+        .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
+        .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
+        .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
+        .M_AXI_GP1_AWREADY(1\'b0),
+        .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
+        .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
+        .M_AXI_GP1_BID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
+        .M_AXI_GP1_BRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_BVALID(1\'b0),
+        .M_AXI_GP1_RDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .M_AXI_GP1_RLAST(1\'b0),
+        .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
+        .M_AXI_GP1_RRESP({1\'b0,1\'b0}),
+        .M_AXI_GP1_RVALID(1\'b0),
+        .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
+        .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
+        .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
+        .M_AXI_GP1_WREADY(1\'b0),
+        .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
+        .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
+        .PJTAG_TCK(1\'b0),
+        .PJTAG_TDI(1\'b0),
+        .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
+        .PJTAG_TMS(1\'b0),
+        .PS_CLK(PS_CLK),
+        .PS_PORB(PS_PORB),
+        .PS_SRSTB(PS_SRSTB),
+        .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
+        .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO0_CDN(1\'b0),
+        .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
+        .SDIO0_CLK_FB(1\'b0),
+        .SDIO0_CMD_I(1\'b0),
+        .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
+        .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
+        .SDIO0_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
+        .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
+        .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
+        .SDIO0_WP(SDIO0_WP),
+        .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
+        .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
+        .SDIO1_CDN(1\'b0),
+        .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
+        .SDIO1_CLK_FB(1\'b0),
+        .SDIO1_CMD_I(1\'b0),
+        .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
+        .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
+        .SDIO1_DATA_I({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
+        .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
+        .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
+        .SDIO1_WP(1\'b0),
+        .SPI0_MISO_I(1\'b0),
+        .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
+        .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
+        .SPI0_MOSI_I(1\'b0),
+        .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
+        .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
+        .SPI0_SCLK_I(1\'b0),
+        .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
+        .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
+        .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
+        .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
+        .SPI0_SS_I(1\'b0),
+        .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
+        .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
+        .SPI1_MISO_I(1\'b0),
+        .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
+        .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
+        .SPI1_MOSI_I(1\'b0),
+        .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
+        .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
+        .SPI1_SCLK_I(1\'b0),
+        .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
+        .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
+        .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
+        .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
+        .SPI1_SS_I(1\'b0),
+        .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
+        .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
+        .SRAM_INTIN(1\'b0),
+        .S_AXI_ACP_ACLK(1\'b0),
+        .S_AXI_ACP_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
+        .S_AXI_ACP_ARID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
+        .S_AXI_ACP_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_ARVALID(1\'b0),
+        .S_AXI_ACP_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_ACP_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
+        .S_AXI_ACP_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWUSER({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_AWVALID(1\'b0),
+        .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_BREADY(1\'b0),
+        .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
+        .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
+        .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
+        .S_AXI_ACP_RREADY(1\'b0),
+        .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
+        .S_AXI_ACP_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WID({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WLAST(1\'b0),
+        .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
+        .S_AXI_ACP_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_ACP_WVALID(1\'b0),
+        .S_AXI_GP0_ACLK(1\'b0),
+        .S_AXI_GP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
+        .S_AXI_GP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
+        .S_AXI_GP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_ARVALID(1\'b0),
+        .S_AXI_GP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
+        .S_AXI_GP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_AWVALID(1\'b0),
+        .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_BREADY(1\'b0),
+        .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
+        .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
+        .S_AXI_GP0_RREADY(1\'b0),
+        .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
+        .S_AXI_GP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WLAST(1\'b0),
+        .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
+        .S_AXI_GP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP0_WVALID(1\'b0),
+        .S_AXI_GP1_ACLK(1\'b0),
+        .S_AXI_GP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
+        .S_AXI_GP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
+        .S_AXI_GP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_ARVALID(1\'b0),
+        .S_AXI_GP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_GP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
+        .S_AXI_GP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_AWVALID(1\'b0),
+        .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_BREADY(1\'b0),
+        .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
+        .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
+        .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
+        .S_AXI_GP1_RREADY(1\'b0),
+        .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
+        .S_AXI_GP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WLAST(1\'b0),
+        .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
+        .S_AXI_GP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_GP1_WVALID(1\'b0),
+        .S_AXI_HP0_ACLK(1\'b0),
+        .S_AXI_HP0_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
+        .S_AXI_HP0_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
+        .S_AXI_HP0_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_ARVALID(1\'b0),
+        .S_AXI_HP0_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP0_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
+        .S_AXI_HP0_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_AWVALID(1\'b0),
+        .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_BREADY(1\'b0),
+        .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
+        .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP0_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
+        .S_AXI_HP0_RREADY(1\'b0),
+        .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
+        .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP0_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WLAST(1\'b0),
+        .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
+        .S_AXI_HP0_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP0_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP0_WVALID(1\'b0),
+        .S_AXI_HP1_ACLK(1\'b0),
+        .S_AXI_HP1_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
+        .S_AXI_HP1_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
+        .S_AXI_HP1_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_ARVALID(1\'b0),
+        .S_AXI_HP1_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP1_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
+        .S_AXI_HP1_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_AWVALID(1\'b0),
+        .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_BREADY(1\'b0),
+        .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
+        .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP1_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
+        .S_AXI_HP1_RREADY(1\'b0),
+        .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
+        .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP1_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WLAST(1\'b0),
+        .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
+        .S_AXI_HP1_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP1_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP1_WVALID(1\'b0),
+        .S_AXI_HP2_ACLK(1\'b0),
+        .S_AXI_HP2_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
+        .S_AXI_HP2_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
+        .S_AXI_HP2_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_ARVALID(1\'b0),
+        .S_AXI_HP2_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP2_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
+        .S_AXI_HP2_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_AWVALID(1\'b0),
+        .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_BREADY(1\'b0),
+        .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
+        .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP2_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
+        .S_AXI_HP2_RREADY(1\'b0),
+        .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
+        .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP2_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WLAST(1\'b0),
+        .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
+        .S_AXI_HP2_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP2_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP2_WVALID(1\'b0),
+        .S_AXI_HP3_ACLK(1\'b0),
+        .S_AXI_HP3_ARADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
+        .S_AXI_HP3_ARID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_ARPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
+        .S_AXI_HP3_ARSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_ARVALID(1\'b0),
+        .S_AXI_HP3_AWADDR({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWBURST({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWCACHE({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLEN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWLOCK({1\'b0,1\'b0}),
+        .S_AXI_HP3_AWPROT({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWQOS({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
+        .S_AXI_HP3_AWSIZE({1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_AWVALID(1\'b0),
+        .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_BREADY(1\'b0),
+        .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
+        .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
+        .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
+        .S_AXI_HP3_RDISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
+        .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
+        .S_AXI_HP3_RREADY(1\'b0),
+        .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
+        .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
+        .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
+        .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
+        .S_AXI_HP3_WDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WID({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WLAST(1\'b0),
+        .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
+        .S_AXI_HP3_WRISSUECAP1_EN(1\'b0),
+        .S_AXI_HP3_WSTRB({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .S_AXI_HP3_WVALID(1\'b0),
+        .TRACE_CLK(1\'b0),
+        .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
+        .TRACE_CT'b'L(NLW_inst_TRACE_CTL_UNCONNECTED),
+        .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
+        .TTC0_CLK0_IN(1\'b0),
+        .TTC0_CLK1_IN(1\'b0),
+        .TTC0_CLK2_IN(1\'b0),
+        .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
+        .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
+        .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
+        .TTC1_CLK0_IN(1\'b0),
+        .TTC1_CLK1_IN(1\'b0),
+        .TTC1_CLK2_IN(1\'b0),
+        .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
+        .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
+        .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
+        .UART0_CTSN(1\'b0),
+        .UART0_DCDN(1\'b0),
+        .UART0_DSRN(1\'b0),
+        .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
+        .UART0_RIN(1\'b0),
+        .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
+        .UART0_RX(UART0_RX),
+        .UART0_TX(UART0_TX),
+        .UART1_CTSN(1\'b0),
+        .UART1_DCDN(1\'b0),
+        .UART1_DSRN(1\'b0),
+        .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
+        .UART1_RIN(1\'b0),
+        .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
+        .UART1_RX(1\'b1),
+        .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
+        .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
+        .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
+        .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
+        .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
+        .USB1_VBUS_PWRFAULT(1\'b0),
+        .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
+        .WDT_CLK_IN(1\'b0),
+        .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
+endmodule
+
+(* C_DM_WIDTH = ""4"" *) (* C_DQS_WIDTH = ""4"" *) (* C_DQ_WIDTH = ""32"" *) 
+(* C_EMIO_GPIO_WIDTH = ""64"" *) (* C_EN_EMIO_ENET0 = ""0"" *) (* C_EN_EMIO_ENET1 = ""0"" *) 
+(* C_EN_EMIO_PJTAG = ""0"" *) (* C_EN_EMIO_TRACE = ""0"" *) (* C_FCLK_CLK0_BUF = ""TRUE"" *) 
+(* C_FCLK_CLK1_BUF = ""FALSE"" *) (* C_FCLK_CLK2_BUF = ""FALSE"" *) (* C_FCLK_CLK3_BUF = ""FALSE"" *) 
+(* C_GP0_EN_MODIFIABLE_TXN = ""0"" *) (* C_GP1_EN_MODIFIABLE_TXN = ""0"" *) (* C_INCLUDE_ACP_TRANS_CHECK = ""0"" *) 
+(* C_INCLUDE_TRACE_BUFFER = ""0"" *) (* C_IRQ_F2P_MODE = ""DIRECT"" *) (* C_MIO_PRIMITIVE = ""54"" *) 
+(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP0_ID_WIDTH = ""12"" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = ""12"" *) 
+(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = ""0"" *) (* C_M_AXI_GP1_ID_WIDTH = ""12"" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = ""12"" *) 
+(* C_NUM_F2P_INTR_INPUTS = ""1"" *) (* C_PACKAGE_NAME = ""clg400"" *) (* C_PS7_SI_REV = ""PRODUCTION"" *) 
+(* C_S_AXI_ACP_ARUSER_VAL = ""31"" *) (* C_S_AXI_ACP_AWUSER_VAL = ""31"" *) (* C_S_AXI_ACP_ID_WIDTH = ""3"" *) 
+(* C_S_AXI_GP0_ID_WIDTH = ""6"" *) (* C_S_AXI_GP1_ID_WIDTH = ""6"" *) (* C_S_AXI_HP0_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP0_ID_WIDTH = ""6"" *) (* C_S_AXI_HP1_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP1_ID_WIDTH = ""6"" *) 
+(* C_S_AXI_HP2_DATA_WIDTH = ""64"" *) (* C_S_AXI_HP2_ID_WIDTH = ""6"" *) (* C_S_AXI_HP3_DATA_WIDTH = ""64"" *) 
+(* C_S_AXI_HP3_ID_WIDTH = ""6"" *) (* C_TRACE_BUFFER_CLOCK_DELAY = ""12"" *) (* C_TRACE_BUFFER_FIFO_SIZE = ""128"" *) 
+(* C_TRACE_INTERNAL_WIDTH = ""2"" *) (* C_TRACE_PIPELINE_WIDTH = ""8"" *) (* C_USE_AXI_NONSECURE = ""0"" *) 
+(* C_USE_DEFAULT_ACP_USER_VAL = ""0"" *) (* C_USE_M_AXI_GP0 = ""1"" *) (* C_USE_M_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_ACP = ""0"" *) (* C_USE_S_AXI_GP0 = ""0"" *) (* C_USE_S_AXI_GP1 = ""0"" *) 
+(* C_USE_S_AXI_HP0 = ""0"" *) (* C_USE_S_AXI_HP1 = ""0"" *) (* C_USE_S_AXI_HP2 = ""0"" *) 
+(* C_USE_S_AXI_HP3 = ""0"" *) (* HW_HANDOFF = ""design_1_processing_system7_0_0.hwdef"" *) (* POWER = ""<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"" *) 
+(* USE_TRACE_DATA_EDGE_DETECTOR = ""0"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
+   (CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TDI,
+    PJTAG_TDO,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    TRACE_CLK_OUT,
+    USB0_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_PORT_INDCTL,
+    USB1_VBUS_PWRSELECT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARESETN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARESETN,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARESETN,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARESETN,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_ARESETN,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARESETN,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARESETN,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARESETN,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARESETN,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_RSTN,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_RSTN,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_RSTN,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_RSTN,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA3_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DRTYPE,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG_0,
+    FTMT_F2P_TRIGACK_0,
+    FTMT_F2P_TRIG_1,
+    FTMT_F2P_TRIGACK_1,
+    FTMT_F2P_TRIG_2,
+    FTMT_F2P_TRIGACK_2,
+    FTMT_F2P_TRIG_3,
+    FTMT_F2P_TRIGACK_3,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK_0,
+    FTMT_P2F_TRIG_0,
+    FTMT_P2F_TRIGACK_1,
+    FTMT_P2F_TRIG_1,
+    FTMT_P2F_TRIGACK_2,
+    FTMT_P2F_TRIG_2,
+    FTMT_P2F_TRIGACK_3,
+    FTMT_P2F_TRIG_3,
+    FTMT_P2F_DEBUG,
+    FPGA_IDLE_N,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    DDR_ARB,
+    MIO,
+    DDR_CAS_n,
+    DDR_CKE,
+    DDR_Clk_n,
+    DDR_Clk,
+    DDR_CS_n,
+    DDR_DRSTB,
+    DDR_ODT,
+    DDR_RAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_VRN,
+    DDR_VRP,
+    DDR_DM,
+    DDR_DQ,
+    DDR_DQS_n,
+    DDR_DQS,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB);
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0]ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input ENET0_EXT_INTIN;
+  input [7:0]ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0]ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input ENET1_EXT_INTIN;
+  input [7:0]ENET1_GMII_RXD;
+  input [63:0]GPIO_I;
+  output [63:0]GPIO_O;
+  output [63:0]GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TDI;
+  output PJTAG_TDO;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0]SDIO0_DATA_I;
+  output [3:0]SDIO0_DATA_O;
+  output [3:0]SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0]SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0]SDIO1_DATA_I;
+  output [3:0]SDIO1_DATA_O;
+  output [3:0]SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0]SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [1:0]TRACE_DATA;
+  output TRACE_CLK_OUT;
+  output [1:0]USB0_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  output [1:0]USB1_PORT_INDCTL;
+  output USB1_VBUS_PWRSELECT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARESETN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [11:0]M_AXI_GP0_ARID;
+  output [11:0]M_AXI_GP0_AWID;
+  output [11:0]M_AXI_GP0_WID;
+  output [1:0]M_AXI_GP0_ARBURST;
+  output [1:0]M_AXI_GP0_ARLOCK;
+  output [2:0]M_AXI_GP0_ARSIZE;
+  output [1:0]M_AXI_GP0_AWBURST;
+  output [1:0]M_AXI_GP0_AWLOCK;
+  output [2:0]M_AXI_GP0_AWSIZE;
+  output [2:0]M_AXI_GP0_ARPROT;
+  output [2:0]M_AXI_GP0_AWPROT;
+  output [31:0]M_AXI_GP0_ARADDR;
+  output [31:0]M_AXI_GP0_AWADDR;
+  output [31:0]M_AXI_GP0_WDATA;
+  output [3:0]M_AXI_GP0_ARCACHE;
+  output [3:0]M_AXI_GP0_ARLEN;
+  output [3:0]M_AXI_GP0_ARQOS;
+  output [3:0]M_AXI_GP0_AWCACHE;
+  output [3:0]M_AXI_GP0_AWLEN;
+  output [3:0]M_AXI_GP0_AWQOS;
+  output [3:0]M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [11:0]M_AXI_GP0_BID;
+  input [11:0]M_AXI_GP0_RID;
+  input [1:0]M_AXI_GP0_BRESP;
+  input [1:0]M_AXI_GP0_RRESP;
+  input [31:0]M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARESETN;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [11:0]M_AXI_GP1_ARID;
+  output [11:0]M_AXI_GP1_AWID;
+  output [11:0]M_AXI_GP1_WID;
+  output [1:0]M_AXI_GP1_ARBURST;
+  output [1:0]M_AXI_GP1_ARLOCK;
+  output [2:0]M_AXI_GP1_ARSIZE;
+  output [1:0]M_AXI_GP1_AWBURST;
+  output [1:0]M_AXI_GP1_AWLOCK;
+  output [2:0]M_AXI_GP1_AWSIZE;
+  output [2:0]M_AXI_GP1_ARPROT;
+  output [2:0]M_AXI_GP1_AWPROT;
+  output [31:0]M_AXI_GP1_ARADDR;
+  output [31:0]M_AXI_GP1_AWADDR;
+  output [31:0]M_AXI_GP1_WDATA;
+  output [3:0]M_AXI_GP1_ARCACHE;
+  output [3:0]M_AXI_GP1_ARLEN;
+  output [3:0]M_AXI_GP1_ARQOS;
+  output [3:0]M_AXI_GP1_AWCACHE;
+  output [3:0]M_AXI_GP1_AWLEN;
+  output [3:0]M_AXI_GP1_AWQOS;
+  output [3:0]M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [11:0]M_AXI_GP1_BID;
+  input [11:0]M_AXI_GP1_RID;
+  input [1:0]M_AXI_GP1_BRESP;
+  input [1:0]M_AXI_GP1_RRESP;
+  input [31:0]M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARESETN;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0]S_AXI_GP0_BRESP;
+  output [1:0]S_AXI_GP0_RRESP;
+  output [31:0]S_AXI_GP0_RDATA;
+  output [5:0]S_AXI_GP0_BID;
+  output [5:0]S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0]S_AXI_GP0_ARBURST;
+  input [1:0]S_AXI_GP0_ARLOCK;
+  input [2:0]S_AXI_GP0_ARSIZE;
+  input [1:0]S_AXI_GP0_AWBURST;
+  input [1:0]S_AXI_GP0_AWLOCK;
+  input [2:0]S_AXI_GP0_AWSIZE;
+  input [2:0]S_AXI_GP0_ARPROT;
+  input [2:0]S_AXI_GP0_AWPROT;
+  input [31:0]S_AXI_GP0_ARADDR;
+  input [31:0]S_AXI_GP0_AWADDR;
+  input [31:0]S_AXI_GP0_WDATA;
+  input [3:0]S_AXI_GP0_ARCACHE;
+  input [3:0]S_AXI_GP0_ARLEN;
+  input [3:0]S_AXI_GP0_ARQOS;
+  input [3:0]S_AXI_GP0_AWCACHE;
+  input [3:0]S_AXI_GP0_AWLEN;
+  input [3:0]S_AXI_GP0_AWQOS;
+  input [3:0]S_AXI_GP0_WSTRB;
+  input [5:0]S_AXI_GP0_ARID;
+  input [5:0]S_AXI_GP0_AWID;
+  input [5:0]S_AXI_GP0_WID;
+  output S_AXI_GP1_ARESETN;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0]S_AXI_GP1_BRESP;
+  output [1:0]S_AXI_GP1_RRESP;
+  output [31:0]S_AXI_GP1_RDATA;
+  output [5:0]S_AXI_GP1_BID;
+  output [5:0]S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0]S_AXI_GP1_ARBURST;
+  input [1:0]S_AXI_GP1_ARLOCK;
+  input [2:0]S_AXI_GP1_ARSIZE;
+  input [1:0]S_AXI_GP1_AWBURST;
+  input [1:0]S_AXI_GP1_AWLOCK;
+  input [2:0]S_AXI_GP1_AWSIZE;
+  input [2:0]S_AXI_GP1_ARPROT;
+  input [2:0]S_AXI_GP1_AWPROT;
+  input [31:0]S_AXI_GP1_ARADDR;
+  input [31:0]S_AXI_GP1_AWADDR;
+  input [31:0]S_AXI_GP1_WDATA;
+  input [3:0]S_AXI_GP1_ARCACHE;
+  input [3:0]S_AXI_GP1_ARLEN;
+  input [3:0]S_AXI_GP1_ARQOS;
+  input [3:0]S_AXI_GP1_AWCACHE;
+  input [3:0]S_AXI_GP1_AWLEN;
+  input [3:0]S_AXI_GP1_AWQOS;
+  input [3:0]S_AXI_GP1_WSTRB;
+  input [5:0]S_AXI_GP1_ARID;
+  input [5:0]S_AXI_GP1_AWID;
+  input [5:0]S_AXI_GP1_WID;
+  output S_AXI_ACP_ARESETN;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0]S_AXI_ACP_BRESP;
+  output [1:0]S_AXI_ACP_RRESP;
+  output [2:0]S_AXI_ACP_BID;
+  output [2:0]S_AXI_ACP_RID;
+  output [63:0]S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0]S_AXI_ACP_ARID;
+  input [2:0]S_AXI_ACP_ARPROT;
+  input [2:0]S_AXI_ACP_AWID;
+  input [2:0]S_AXI_ACP_AWPROT;
+  input [2:0]S_AXI_ACP_WID;
+  input [31:0]S_AXI_ACP_ARADDR;
+  input [31:0]S_AXI_ACP_AWADDR;
+  input [3:0]S_AXI_ACP_ARCACHE;
+  input [3:0]S_AXI_ACP_ARLEN;
+  input [3:0]S_AXI_ACP_ARQOS;
+  input [3:0]S_AXI_ACP_AWCACHE;
+  input [3:0]S_AXI_ACP_AWLEN;
+  input [3:0]S_AXI_ACP_AWQOS;
+  input [1:0]S_AXI_ACP_ARBURST;
+  input [1:0]S_AXI_ACP_ARLOCK;
+  input [2:0]S_AXI_ACP_ARSIZE;
+  input [1:0]S_AXI_ACP_AWBURST;
+  input [1:0]S_AXI_ACP_AWLOCK;
+  input [2:0]S_AXI_ACP_AWSIZE;
+  input [4:0]S_AXI_ACP_ARUSER;
+  input [4:0]S_AXI_ACP_AWUSER;
+  input [63:0]S_AXI_ACP_WDATA;
+  input [7:0]S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARESETN;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0]S_AXI_HP0_BRESP;
+  output [1:0]S_AXI_HP0_RRESP;
+  output [5:0]S_AXI_HP0_BID;
+  output [5:0]S_AXI_HP0_RID;
+  output [63:0]S_AXI_HP0_RDATA;
+  output [7:0]S_AXI_HP0_RCOUNT;
+  output [7:0]S_AXI_HP0_WCOUNT;
+  output [2:0]S_AXI_HP0_RACOUNT;
+  output [5:0]S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0]S_AXI_HP0_ARBURST;
+  input [1:0]S_AXI_HP0_ARLOCK;
+  input [2:0]S_AXI_HP0_ARSIZE;
+  input [1:0]S_AXI_HP0_AWBURST;
+  input [1:0]S_AXI_HP0_AWLOCK;
+  input [2:0]S_AXI_HP0_AWSIZE;
+  input [2:0]S_AXI_HP0_ARPROT;
+  input [2:0]S_AXI_HP0_AWPROT;
+  input [31:0]S_AXI_HP0_ARADDR;
+  input [31:0]S_AXI_HP0_AWADDR;
+  input [3:0]S_AXI_HP0_ARCACHE;
+  input [3:0]S_AXI_HP0_ARLEN;
+  input [3:0]S_AXI_HP0_ARQOS;
+  input [3:0]S_AXI_HP0_AWCACHE;
+  input [3:0]S_AXI_HP0_AWLEN;
+  input [3:0]S_AXI_HP0_AWQOS;
+  input [5:0]S_AXI_HP0_ARID;
+  input [5:0]S_AXI_HP0_AWID;
+  input [5:0]S_AXI_HP0_WID;
+  input [63:0]S_AXI_HP0_WDATA;
+  input [7:0]S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARESETN;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0]S_AXI_HP1_BRESP;
+  output [1:0]S_AXI_HP1_RRESP;
+  output [5:0]S_AXI_HP1_BID;
+  output [5:0]S_AXI_HP1_RID;
+  output [63:0]S_AXI_HP1_RDATA;
+  output [7:0]S_AXI_HP1_RCOUNT;
+  output [7:0]S_AXI_HP1_WCOUNT;
+  output [2:0]S_AXI_HP1_RACOUNT;
+  output [5:0]S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0]S_AXI_HP1_ARBURST;
+  input [1:0]S_AXI_HP1_ARLOCK;
+  input [2:0]S_AXI_HP1_ARSIZE;
+  input [1:0]S_AXI_HP1_AWBURST;
+  input [1:0]S_AXI_HP1_AWLOCK;
+  input [2:0]S_AXI_HP1_AWSIZE;
+  input [2:0]S_AXI_HP1_ARPROT;
+  input [2:0]S_AXI_HP1_AWPROT;
+  input [31:0]S_AXI_HP1_ARADDR;
+  input [31:0]S_AXI_HP1_AWADDR;
+  input [3:0]S_AXI_HP1_ARCACHE;
+  input [3:0]S_AXI_HP1_ARLEN;
+  input [3:0]S_AXI_HP1_ARQOS;
+  input [3:0]S_AXI_HP1_AWCACHE;
+  input [3:0]S_AXI_HP1_AWLEN;
+  input [3:0]S_AXI_HP1_AWQOS;
+  input [5:0]S_AXI_HP1_ARID;
+  input [5:0]S_AXI_HP1_AWID;
+  input [5:0]S_AXI_HP1_WID;
+  input [63:0]S_AXI_HP1_WDATA;
+  input [7:0]S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARESETN;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0]S_AXI_HP2_BRESP;
+  output [1:0]S_AXI_HP2_RRESP;
+  output [5:0]S_AXI_HP2_BID;
+  output [5:0]S_AXI_HP2_RID;
+  output [63:0]S_AXI_HP2_RDATA;
+  output [7:0]S_AXI_HP2_RCOUNT;
+  output [7:0]S_AXI_HP2_WCOUNT;
+  output [2:0]S_AXI_HP2_RACOUNT;
+  output [5:0]S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0]S_AXI_HP2_ARBURST;
+  input [1:0]S_AXI_HP2_ARLOCK;
+  input [2:0]S_AXI_HP2_ARSIZE;
+  input [1:0]S_AXI_HP2_AWBURST;
+  input [1:0]S_AXI_HP2_AWLOCK;
+  input [2:0]S_AXI_HP2_AWSIZE;
+  input [2:0]S_AXI_HP2_ARPROT;
+  input [2:0]S_AXI_HP2_AWPROT;
+  input [31:0]S_AXI_HP2_ARADDR;
+  input [31:0]S_AXI_HP2_AWADDR;
+  input [3:0]S_AXI_HP2_ARCACHE;
+  input [3:0]S_AXI_HP2_ARLEN;
+  input [3:0]S_AXI_HP2_ARQOS;
+  input [3:0]S_AXI_HP2_AWCACHE;
+  input [3:0]S_AXI_HP2_AWLEN;
+  input [3:0]S_AXI_HP2_AWQOS;
+  input [5:0]S_AXI_HP2_ARID;
+  input [5:0]S_AXI_HP2_AWID;
+  input [5:0]S_AXI_HP2_WID;
+  input [63:0]S_AXI_HP2_WDATA;
+  input [7:0]S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARESETN;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0]S_AXI_HP3_BRESP;
+  output [1:0]S_AXI_HP3_RRESP;
+  output [5:0]S_AXI_HP3_BID;
+  output [5:0]S_AXI_HP3_RID;
+  output [63:0]S_AXI_HP3_RDATA;
+  output [7:0]S_AXI_HP3_RCOUNT;
+  output [7:0]S_AXI_HP3_WCOUNT;
+  output [2:0]S_AXI_HP3_RACOUNT;
+  output [5:0]S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0]S_AXI_HP3_ARBURST;
+  input [1:0]S_AXI_HP3_ARLOCK;
+  input [2:0]S_AXI_HP3_ARSIZE;
+  input [1:0]S_AXI_HP3_AWBURST;
+  input [1:0]S_AXI_HP3_AWLOCK;
+  input [2:0]S_AXI_HP3_AWSIZE;
+  input [2:0]S_AXI_HP3_ARPROT;
+  input [2:0]S_AXI_HP3_AWPROT;
+  input [31:0]S_AXI_HP3_ARADDR;
+  input [31:0]S_AXI_HP3_AWADDR;
+  input [3:0]S_AXI_HP3_ARCACHE;
+  input [3:0]S_AXI_HP3_ARLEN;
+  input [3:0]S_AXI_HP3_ARQOS;
+  input [3:0]S_AXI_HP3_AWCACHE;
+  input [3:0]S_AXI_HP3_AWLEN;
+  input [3:0]S_AXI_HP3_AWQOS;
+  input [5:0]S_AXI_HP3_ARID;
+  input [5:0]S_AXI_HP3_AWID;
+  input [5:0]S_AXI_HP3_WID;
+  input [63:0]S_AXI_HP3_WDATA;
+  input [7:0]S_AXI_HP3_WSTRB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+  input [0:0]IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output [1:0]DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  output DMA0_RSTN;
+  output [1:0]DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  output DMA1_RSTN;
+  output [1:0]DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  output DMA2_RSTN;
+  output [1:0]DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  output DMA3_RSTN;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input DMA3_DRVALID;
+  input [1:0]DMA0_DRTYPE;
+  input [1:0]DMA1_DRTYPE;
+  input [1:0]DMA2_DRTYPE;
+  input [1:0]DMA3_DRTYPE;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input [31:0]FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0]FTMD_TRACEIN_ATID;
+  input FTMT_F2P_TRIG_0;
+  output FTMT_F2P_TRIGACK_0;
+  input FTMT_F2P_TRIG_1;
+  output FTMT_F2P_TRIGACK_1;
+  input FTMT_F2P_TRIG_2;
+  output FTMT_F2P_TRIGACK_2;
+  input FTMT_F2P_TRIG_3;
+  output FTMT_F2P_TRIGACK_3;
+  input [31:0]FTMT_F2P_DEBUG;
+  input FTMT_P2F_TRIGACK_0;
+  output FTMT_P2F_TRIG_0;
+  input FTMT_P2F_TRIGACK_1;
+  output FTMT_P2F_TRIG_1;
+  input FTMT_P2F_TRIGACK_2;
+  output FTMT_P2F_TRIG_2;
+  input FTMT_P2F_TRIGACK_3;
+  output FTMT_P2F_TRIG_3;
+  output [31:0]FTMT_P2F_DEBUG;
+  input FPGA_IDLE_N;
+  output EVENT_EVENTO;
+  output [1:0]EVENT_STANDBYWFE;
+  output [1:0]EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  input [3:0]DDR_ARB;
+  inout [53:0]MIO;
+  inout DDR_CAS_n;
+  inout DDR_CKE;
+  inout DDR_Clk_n;
+  inout DDR_Clk;
+  inout DDR_CS_n;
+  inout DDR_DRSTB;
+  inout DDR_ODT;
+  inout DDR_RAS_n;
+  inout DDR_WEB;
+  inout [2:0]DDR_BankAddr;
+  inout [14:0]DDR_Addr;
+  inout DDR_VRN;
+  inout DDR_VRP;
+  inout [3:0]DDR_DM;
+  inout [31:0]DDR_DQ;
+  inout [3:0]DDR_DQS_n;
+  inout [3:0]DDR_DQS;
+  inout PS_SRSTB;
+  inout PS_CLK;
+  inout PS_PORB;
+
+  wire \\<const0> ;
+  wire CAN0_PHY_RX;
+  wire CAN0_PHY_TX;
+  wire CAN1_PHY_RX;
+  wire CAN1_PHY_TX;
+  wire Core0_nFIQ;
+  wire Core0_nIRQ;
+  wire Core1_nFIQ;
+  wire Core1_nIRQ;
+  wire [3:0]DDR_ARB;
+  wire [14:0]DDR_Addr;
+  wire [2:0]DDR_BankAddr;
+  wire DDR_CAS_n;
+  wire DDR_CKE;
+  wire DDR_CS_n;
+  wire DDR_Clk;
+  wire DDR_Clk_n;
+  wire [3:0]DDR_DM;
+  wire [31:0]DDR_DQ;
+  wire [3:0]DDR_DQS;
+  wire [3:0]DDR_DQS_n;
+  wire DDR_DRSTB;
+  wire DDR_ODT;
+  wire DDR_RAS_n;
+  wire DDR_VRN;
+  wire DDR_VRP;
+  wire DDR_WEB;
+  wire DMA0_ACLK;
+  wire DMA0_DAREADY;
+  wire [1:0]DMA0_DATYPE;
+  wire DMA0_DAVALID;
+  wire DMA0_DRLAST;
+  wire DMA0_DRREADY;
+  wire [1:0]DMA0_DRTYPE;
+  wire DMA0_DRVALID;
+  wire DMA0_RSTN;
+  wire DMA1_ACLK;
+  wire DMA1_DAREADY;
+  wire [1:0]DMA1_DATYPE;
+  wire DMA1_DAVALID;
+  wire DMA1_DRLAST;
+  wire DMA1_DRREADY;
+  wire [1:0]DMA1_DRTYPE;
+  wire DMA1_DRVALID;
+  wire DMA1_RSTN;
+  wire DMA2_ACLK;
+  wire DMA2_DAREADY;
+  wire [1:0]DMA2_DATYPE;
+  wire DMA2_DAVALID;
+  wire DMA2_DRLAST;
+  wire DMA2_DRREADY;
+  wire [1:0]DMA2_DRTYPE;
+  wire DMA2_DRVALID;
+  wire DMA2_RSTN;
+  wire DMA3_ACLK;
+  wire DMA3_DAREADY;
+  wire [1:0]DMA3_DATYPE;
+  wire DMA3_DAVALID;
+  wire DMA3_DRLAST;
+  wire DMA3_DRREADY;
+  wire [1:0]DMA3_DRTYPE;
+  wire DMA3_DRVALID;
+  wire DMA3_RSTN;
+  wire ENET0_EXT_INTIN;
+  wire ENET0_GMII_RX_CLK;
+  wire ENET0_GMII_TX_CLK;
+  wire ENET0_MDIO_I;
+  wire ENET0_MDIO_MDC;
+  wire ENET0_MDIO_O;
+  wire ENET0_MDIO_T;
+  wire ENET0_MDIO_T_n;
+  wire ENET0_PTP_DELAY_REQ_RX;
+  wire ENET0_PTP_DELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_REQ_RX;
+  wire ENET0_PTP_PDELAY_REQ_TX;
+  wire ENET0_PTP_PDELAY_RESP_RX;
+  wire ENET0_PTP_PDELAY_RESP_TX;
+  wire ENET0_PTP_SYNC_FRAME_RX;
+  wire ENET0_PTP_SYNC_FRAME_TX;
+  wire ENET0_SOF_RX;
+  wire ENET0_SOF_TX;
+  wire ENET1_EXT_INTIN;
+  wire ENET1_GMII_RX_CLK;
+  wire ENET1_GMII_TX_CLK;
+  wire ENET1_MDIO_I;
+  wire ENET1_MDIO_MDC;
+  wire ENET1_MDIO_O;
+  wire ENET1_MDIO_T;
+  wire ENET1_MDIO_T_n;
+  wire ENET1_PTP_DELAY_REQ_RX;
+  wire ENET1_PTP_DELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_REQ_RX;
+  wire ENET1_PTP_PDELAY_REQ_TX;
+  wire ENET1_PTP_PDELAY_RESP_RX;
+  wire ENET1_PTP_PDELAY_RESP_TX;
+  wire ENET1_PTP_SYNC_FRAME_RX;
+  wire ENET1_PTP_SYNC_FRAME_TX;
+  wire ENET1_SOF_RX;
+  wire ENET1_SOF_TX;
+  wire EVENT_EVENTI;
+  wire EVENT_EVENTO;
+  wire [1:0]EVENT_STANDBYWFE;
+  wire [1:0]EVENT_STANDBYWFI;
+  wire FCLK_CLK0;
+  wire FCLK_CLK1;
+  wire FCLK_CLK2;
+  wire FCLK_CLK3;
+  wire [0:0]FCLK_CLK_unbuffered;
+  wire FCLK_RESET0_N;
+  wire FCLK_RESET1_N;
+  wire FCLK_RESET2_N;
+  wire FCLK_RESET3_N;
+  wire FPGA_IDLE_N;
+  wire FTMD_TRACEIN_CLK;
+  wire [31:0]FTMT_F2P_DEBUG;
+  wire FTMT_F2P_TRIGACK_0;
+  wire FTMT_F2P_TRIGACK_1;
+  wire FTMT_F2P_TRIGACK_2;
+  wire FTMT_F2P_TRIGACK_3;
+  wire FTMT_F2P_TRIG_0;
+  wire FTMT_F2P_TRIG_1;
+  wire FTMT_F2P_TRIG_2;
+  wire FTMT_F2P_TRIG_3;
+  wire [31:0]FTMT_P2F_DEBUG;
+  wire FTMT_P2F_TRIGACK_0;
+  wire FTMT_P2F_TRIGACK_1;
+  wire FTMT_P2F_TRIGACK_2;
+  wire FTMT_P2F_TRIGACK_3;
+  wire FTMT_P2F_TRIG_0;
+  wire FTMT_P2F_TRIG_1;
+  wire FTMT_P2F_TRIG_2;
+  wire FTMT_P2F_TRIG_3;
+  wire [63:0]GPIO_I;
+  wire [63:0]GPIO_O;
+  wire [63:0]GPIO_T;
+  wire I2C0_SCL_I;
+  wire I2C0_SCL_O;
+  wire I2C0_SCL_T;
+  wire I2C0_SCL_T_n;
+  wire I2C0_SDA_I;
+  wire I2C0_SDA_O;
+  wire I2C0_SDA_T;
+  wire I2C0_SDA_T_n;
+  wire I2C1_SCL_I;
+  wire I2C1_SCL_O;
+  wire I2C1_SCL_T;
+  wire I2C1_SCL_T_n;
+  wire I2C1_SDA_I;
+  wire I2C1_SDA_O;
+  wire I2C1_SDA_T;
+  wire I2C1_SDA_T_n;
+  wire [0:0]IRQ_F2P;
+  wire IRQ_P2F_CAN0;
+  wire IRQ_P2F_CAN1;
+  wire IRQ_P2F_CTI;
+  wire IRQ_P2F_DMAC0;
+  wire IRQ_P2F_DMAC1;
+  wire IRQ_P2F_DMAC2;
+  wire IRQ_P2F_DMAC3;
+  wire IRQ_P2F_DMAC4;
+  wire IRQ_P2F_DMAC5;
+  wire IRQ_P2F_DMAC6;
+  wire IRQ_P2F_DMAC7;
+  wire IRQ_P2F_DMAC_ABORT;
+  wire IRQ_P2F_ENET0;
+  wire IRQ_P2F_ENET1;
+  wire IRQ_P2F_ENET_WAKE0;
+  wire IRQ_P2F_ENET_WAKE1;
+  wire IRQ_P2F_GPIO;
+  wire IRQ_P2F_I2C0;
+  wire IRQ_P2F_I2C1;
+  wire IRQ_P2F_QSPI;
+  wire IRQ_P2F_SDIO0;
+  wire IRQ_P2F_SDIO1;
+  wire IRQ_P2F_SMC;
+  wire IRQ_P2F_SPI0;
+  wire IRQ_P2F_SPI1;
+  wire IRQ_P2F_UART0;
+  wire IRQ_P2F_UART1;
+  wire IRQ_P2F_USB0;
+  wire IRQ_P2F_USB1;
+  wire [53:0]MIO;
+  wire M_AXI_GP0_ACLK;
+  wire [31:0]M_AXI_GP0_ARADDR;
+  wire [1:0]M_AXI_GP0_ARBURST;
+  wire [3:0]M_AXI_GP0_ARCACHE;
+  wire M_AXI_GP0_ARESETN;
+  wire [11:0]M_AXI_GP0_ARID;
+  wire [3:0]M_AXI_GP0_ARLEN;
+  wire [1:0]M_AXI_GP0_ARLOCK;
+  wire [2:0]M_AXI_GP0_ARPROT;
+  wire [3:0]M_AXI_GP0_ARQOS;
+  wire M_AXI_GP0_ARREADY;
+  wire [1:0]\\^M_AXI_GP0_ARSIZE ;
+  wire M_AXI_GP0_ARVALID;
+  wire [31:0]M_AXI_GP0_AWADDR;
+  wire [1:0]M_AXI_GP0_AWBURST;
+  wire [3:0]M_AXI_GP0_AWCACHE;
+  wire [11:0]M_AXI_GP0_AWID;
+  wire [3:0]M_AXI_GP0_AWLEN;
+  wire [1:0]M_AXI_GP0_AWLOCK;
+  wire [2:0]M_AXI_GP0_AWPROT;
+  wire [3:0]M_AXI_GP0_AWQOS;
+  wire M_AXI_GP0_AWREADY;
+  wire [1:0]\\^M_AXI_GP0_AWSIZE ;
+  wire M_AXI_GP0_AWVALID;
+  wire [11:0]M_AXI_GP0_BID;
+  wire M_AXI_GP0_BREADY;
+  wire [1:0]M_AXI_GP0_BRESP;
+  wire M_AXI_GP0_BVALID;
+  wire [31:0]M_AXI_GP0_RDATA;
+  wire [11:0]M_AXI_GP0_RID;
+  wire M_AXI_GP0_RLAST;
+  wire M_AXI_GP0_RREADY;
+  wire [1:0]M_AXI_GP0_RRESP;
+  wire M_AXI_GP0_RVALID;
+  wire [31:0]M_AXI_GP0_WDATA;
+  wire [11:0]M_AXI_GP0_WID;
+  wire M_AXI_GP0_WLAST;
+  wire M_AXI_GP0_WREADY;
+  wire [3:0]M_AXI_GP0_WSTRB;
+  wire M_AXI_GP0_WVALID;
+  wire M_AXI_GP1_ACLK;
+  wire [31:0]M_AXI_GP1_ARADDR;
+  wire [1:0]M_AXI_GP1_ARBURST;
+  wire [3:0]M_AXI_GP1_ARCACHE;
+  wire M_AXI_GP1_ARESETN;
+  wire [11:0]M_AXI_GP1_ARID;
+  wire [3:0]M_AXI_GP1_ARLEN;
+  wire [1:0]M_AXI_GP1_ARLOCK;
+  wire [2:0]M_AXI_GP1_ARPROT;
+  wire [3:0]M_AXI_GP1_ARQOS;
+  wire M_AXI_GP1_ARREADY;
+  wire [1:0]\\^M_AXI_GP1_ARSIZE ;
+  wire M_AXI_GP1_ARVALID;
+  wire [31:0]M_AXI_GP1_AWADDR;
+  wire [1:0]M_AXI_GP1_AWBURST;
+  wire [3:0]M_AXI_GP1_AWCACHE;
+  wire [11:0]M_AXI_GP1_AWID;
+  wire [3:0]M_AXI_GP1_AWLEN;
+  wire [1:0]M_AXI_GP1_AWLOCK;
+  wire [2:0]M_AXI_GP1_AWPROT;
+  wire [3:0]M_AXI_GP1_AWQOS;
+  wire M_AXI_GP1_AWREADY;
+  wire [1:0]\\^M_AXI_GP1_AWSIZE ;
+  wire M_AXI_GP1_AWVALID;
+  wire [11:0]M_AXI_GP1_BID;
+  wire M_AXI_GP1_BREADY;
+  wire [1:0]M_AXI_GP1_BRESP;
+  wire M_AXI_GP1_BVALID;
+  wire [31:0]M_AXI_GP1_RDATA;
+  wire [11:0]M_AXI_GP1_RID;
+  wire M_AXI_GP1_RLAST;
+  wire M_AXI_GP1_RREADY;
+  wire [1:0]M_AXI_GP1_RRESP;
+  wire M_AXI_GP1_RVALID;
+  wire [31:0]M_AXI_GP1_WDATA;
+  wire [11:0]M_AXI_GP1_WID;
+  wire M_AXI_GP1_WLAST;
+  wire M_AXI_GP1_WREADY;
+  wire [3:0]M_AXI_GP1_WSTRB;
+  wire M_AXI_GP1_WVALID;
+  wire PJTAG_TCK;
+  wire PJTAG_TDI;
+  wire PJTAG_TMS;
+  wire PS_CLK;
+  wire PS_PORB;
+  wire PS_SRSTB;
+  wire SDIO0_BUSPOW;
+  wire [2:0]SDIO0_BUSVOLT;
+  wire SDIO0_CDN;
+  wire SDIO0_CLK;
+  wire SDIO0_CLK_FB;
+  wire SDIO0_CMD_I;
+  wire SDIO0_CMD_O;
+  wire SDIO0_CMD_T;
+  wire SDIO0_CMD_T_n;
+  wire [3:0]SDIO0_DATA_I;
+  wire [3:0]SDIO0_DATA_O;
+  wire [3:0]SDIO0_DATA_T;
+  wire [3:0]SDIO0_DATA_T_n;
+  wire SDIO0_LED;
+  wire SDIO0_WP;
+  wire SDIO1_BUSPOW;
+  wire [2:0]SDIO1_BUSVOLT;
+  wire SDIO1_CDN;
+  wire SDIO1_CLK;
+  wire SDIO1_CLK_FB;
+  wire SDIO1_CMD_I;
+  wire SDIO1_CMD_O;
+  wire SDIO1_CMD_T;
+  wire SDIO1_CMD_T_n;
+  wire [3:0]SDIO1_DATA_I;
+  wire [3:0]SDIO1_DATA_O;
+  wire [3:0]SDIO1_DATA_T;
+  wire [3:0]SDIO1_DATA_T_n;
+  wire SDIO1_LED;
+  wire SDIO1_WP;
+  wire SPI0_MISO_I;
+  wire SPI0_MISO_O;
+  wire SPI0_MISO_T;
+  wire SPI0_MISO_T_n;
+  wire SPI0_MOSI_I;
+  wire SPI0_MOSI_O;
+  wire SPI0_MOSI_T;
+  wire SPI0_MOSI_T_n;
+  wire SPI0_SCLK_I;
+  wire SPI0_SCLK_O;
+  wire SPI0_SCLK_T;
+  wire SPI0_SCLK_T_n;
+  wire SPI0_SS1_O;
+  wire SPI0_SS2_O;
+  wire SPI0_SS_I;
+  wire SPI0_SS_O;
+  wire SPI0_SS_T;
+  wire SPI0_SS_T_n;
+  wire SPI1_MISO_I;
+  wire SPI1_MISO_O;
+  wire SPI1_MISO_T;
+  wire SPI1_MISO_T_n;
+  wire SPI1_MOSI_I;
+  wire SPI1_MOSI_O;
+  wire SPI1_MOSI_T;
+  wire SPI1_MOSI_T_n;
+  wire SPI1_SCLK_I;
+  wire SPI1_SCLK_O;
+  wire SPI1_SCLK_T;
+  wire SPI1_SCLK_T_n;
+  wire SPI1_SS1_O;
+  wire SPI1_SS2_O;
+  wire SPI1_SS_I;
+  wire SPI1_SS_O;
+  wire SPI1_SS_T;
+  wire SPI1_SS_T_n;
+  wire SRAM_INTIN;
+  wire S_AXI_ACP_ACLK;
+  wire [31:0]S_AXI_ACP_ARADDR;
+  wire [1:0]S_AXI_ACP_ARBURST;
+  wire [3:0]S_AXI_ACP_ARCACHE;
+  wire S_AXI_ACP_ARESETN;
+  wire [2:0]S_AXI_ACP_ARID;
+  wire [3:0]S_AXI_ACP_ARLEN;
+  wire [1:0]S_AXI_ACP_ARLOCK;
+  wire [2:0]S_AXI_ACP_ARPROT;
+  wire [3:0]S_AXI_ACP_ARQOS;
+  wire S_AXI_ACP_ARREADY;
+  wire [2:0]S_AXI_ACP_ARSIZE;
+  wire [4:0]S_AXI_ACP_ARUSER;
+  wire S_AXI_ACP_ARVALID;
+  wire [31:0]S_AXI_ACP_AWADDR;
+  wire [1:0]S_AXI_ACP_AWBURST;
+  wire [3:0]S_AXI_ACP_AWCACHE;
+  wire [2:0]S_AXI_ACP_AWID;
+  wire [3:0]S_AXI_ACP_AWLEN;
+  wire [1:0]S_AXI_ACP_AWLOCK;
+  wire [2:0]S_AXI_ACP_AWPROT;
+  wire [3:0]S_AXI_ACP_AWQOS;
+  wire S_AXI_ACP_AWREADY;
+  wire [2:0]S_AXI_ACP_AWSIZE;
+  wire [4:0]S_AXI_ACP_AWUSER;
+  wire S_AXI_ACP_AWVALID;
+  wire [2:0]S_AXI_ACP_BID;
+  wire S_AXI_ACP_BREADY;
+  wire [1:0]S_AXI_ACP_BRESP;
+  wire S_AXI_ACP_BVALID;
+  wire [63:0]S_AXI_ACP_RDATA;
+  wire [2:0]S_AXI_ACP_RID;
+  wire S_AXI_ACP_RLAST;
+  wire S_AXI_ACP_RREADY;
+  wire [1:0]S_AXI_ACP_RRESP;
+  wire S_AXI_ACP_RVALID;
+  wire [63:0]S_AXI_ACP_WDATA;
+  wire [2:0]S_AXI_ACP_WID;
+  wire S_AXI_ACP_WLAST;
+  wire S_AXI_ACP_WREADY;
+  wire [7:0]S_AXI_ACP_WSTRB;
+  wire S_AXI_ACP_WVALID;
+  wire S_AXI_GP0_ACLK;
+  wire [31:0]S_AXI_GP0_ARADDR;
+  wire [1:0]S_AXI_GP0_ARBURST;
+  wire [3:0]S_AXI_GP0_ARCACHE;
+  wire S_AXI_GP0_ARESETN;
+  wire [5:0]S_AXI_GP0_ARID;
+  wire [3:0]S_AXI_GP0_ARLEN;
+  wire [1:0]S_AXI_GP0_ARLOCK;
+  wire [2:0]S_AXI_GP0_ARPROT;
+  wire [3:0]S_AXI_GP0_ARQOS;
+  wire S_AXI_GP0_ARREADY;
+  wire [2:0]S_AXI_GP0_ARSIZE;
+  wire S_AXI_GP0_ARVALID;
+  wire [31:0]S_AXI_GP0_AWADDR;
+  wire [1:0]S_AXI_GP0_AWBURST;
+  wire [3:0]S_AXI_GP0_AWCACHE;
+  wire [5:0]S_AXI_GP0_AWID;
+  wire [3:0]S_AXI_GP0_AWLEN;
+  wire [1:0]S_AXI_GP0_AWLOCK;
+  wire [2:0]S_AXI_GP0_AWPROT;
+  wire [3:0]S_AXI_GP0_AWQOS;
+  wire S_AXI_GP0_AWREADY;
+  wire [2:0]S_AXI_GP0_AWSIZE;
+  wire S_AXI_GP0_AWVALID;
+  wire [5:0]S_AXI_GP0_BID;
+  wire S_AXI_GP0_BREADY;
+  wire [1:0]S_AXI_GP0_BRESP;
+  wire S_AXI_GP0_BVALID;
+  wire [31:0]S_AXI_GP0_RDATA;
+  wire [5:0]S_AXI_GP0_RID;
+  wire S_AXI_GP0_RLAST;
+  wire S_AXI_GP0_RREADY;
+  wire [1:0]S_AXI_GP0_RRESP;
+  wire S_AXI_GP0_RVALID;
+  wire [31:0]S_AXI_GP0_WDATA;
+  wire [5:0]S_AXI_GP0_WID;
+  wire S_AXI_GP0_WLAST;
+  wire S_AXI_GP0_WREADY;
+  wire [3:0]S_AXI_GP0_WSTRB;
+  wire S_AXI_GP0_WVALID;
+  wire S_AXI_GP1_ACLK;
+  wire [31:0]S_AXI_GP1_ARADDR;
+  wire [1:0]S_AXI_GP1_ARBURST;
+  wire [3:0]S_AXI_GP1_ARCACHE;
+  wire S_AXI_GP1_ARESETN;
+  wire [5:0]S_AXI_GP1_ARID;
+  wire [3:0]S_AXI_GP1_ARLEN;
+  wire [1:0]S_AXI_GP1_ARLOCK;
+  wire [2:0]S_AXI_GP1_ARPROT;
+  wire [3:0]S_AXI_GP1_ARQOS;
+  wire S_AXI_GP1_ARREADY;
+  wire [2:0]S_AXI_GP1_ARSIZE;
+  wire S_AXI_GP1_ARVALID;
+  wire [31:0]S_AXI_GP1_AWADDR;
+  wire [1:0]S_AXI_GP1_AWBURST;
+  wire [3:0]S_AXI_GP1_AWCACHE;
+  wire [5:0]S_AXI_GP1_AWID;
+  wire [3:0]S_AXI_GP1_AWLEN;
+  wire [1:0]S_AXI_GP1_AWLOCK;
+  wire [2:0]S_AXI_GP1_AWPROT;
+  wire [3:0]S_AXI_GP1_AWQOS;
+  wire S_AXI_GP1_AWREADY;
+  wire [2:0]S_AXI_GP1_AWSIZE;
+  wire S_AXI_GP1_AWVALID;
+  wire [5:0]S_AXI_GP1_BID;
+  wire S_AXI_GP1_BREADY;
+  wire [1:0]S_AXI_GP1_BRESP;
+  wire S_AXI_GP1_BVALID;
+  wire [31:0]S_AXI_GP1_RDATA;
+  wire [5:0]S_AXI_GP1_RID;
+  wire S_AXI_GP1_RLAST;
+  wire S_AXI_GP1_RREADY;
+  wire [1:0]S_AXI_GP1_RRESP;
+  wire S_AXI_GP1_RVALID;
+  wire [31:0]S_AXI_GP1_WDATA;
+  wire [5:0]S_AXI_GP1_WID;
+  wire S_AXI_GP1_WLAST;
+  wire S_AXI_GP1_WREADY;
+  wire [3:0]S_AXI_GP1_WSTRB;
+  wire S_AXI_GP1_WVALID;
+  wire S_AXI_HP0_ACLK;
+  wire [31:0]S_AXI_HP0_ARADDR;
+  wire [1:0]S_AXI_HP0_ARBURST;
+  wire [3:0]S_AXI_HP0_ARCACHE;
+  wire S_AXI_HP0_ARESETN;
+  wire [5:0]S_AXI_HP0_ARID;
+  wire [3:0]S_AXI_HP0_ARLEN;
+  wire [1:0]S_AXI_HP0_ARLOCK;
+  wire [2:0]S_AXI_HP0_ARPROT;
+  wire [3:0]S_AXI_HP0_ARQOS;
+  wire S_AXI_HP0_ARREADY;
+  wire [2:0]S_AXI_HP0_ARSIZE;
+  wire S_AXI_HP0_ARVALID;
+  wire [31:0]S_AXI_HP0_AWADDR;
+  wire [1:0]S_AXI_HP0_AWBURST;
+  wire [3:0]S_AXI_HP0_AWCACHE;
+  wire [5:0]S_AXI_HP0_AWID;
+  wire [3:0]S_AXI_HP0_AWLEN;
+  wire [1:0]S_AXI_HP0_AWLOCK;
+  wire [2:0]S_AXI_HP0_AWPROT;
+  wire [3:0]S_AXI_HP0_AWQOS;
+  wire S_AXI_HP0_AWREADY;
+  wire [2:0]S_AXI_HP0_AWSIZE;
+  wire S_AXI_HP0_AWVALID;
+  wire [5:0]S_AXI_HP0_BID;
+  wire S_AXI_HP0_BREADY;
+  wire [1:0]S_AXI_HP0_BRESP;
+  wire S_AXI_HP0_BVALID;
+  wire [2:0]S_AXI_HP0_RACOUNT;
+  wire [7:0]S_AXI_HP0_RCOUNT;
+  wire [63:0]S_AXI_HP0_RDATA;
+  wire S_AXI_HP0_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP0_RID;
+  wire S_AXI_HP0_RLAST;
+  wire S_AXI_HP0_RREADY;
+  wire [1:0]S_AXI_HP0_RRESP;
+  wire S_AXI_HP0_RVALID;
+  wire [5:0]S_AXI_HP0_WACOUNT;
+  wire [7:0]S_AXI_HP0_WCOUNT;
+  wire [63:0]S_AXI_HP0_WDATA;
+  wire [5:0]S_AXI_HP0_WID;
+  wire S_AXI_HP0_WLAST;
+  wire S_AXI_HP0_WREADY;
+  wire S_AXI_HP0_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP0_WSTRB;
+  wire S_AXI_HP0_WVALID;
+  wire S_AXI_HP1_ACLK;
+  wire [31:0]S_AXI_HP1_ARADDR;
+  wire [1:0]S_AXI_HP1_ARBURST;
+  wire [3:0]S_AXI_HP1_ARCACHE;
+  wire S_AXI_HP1_ARESETN;
+  wire [5:0]S_AXI_HP1_ARID;
+  wire [3:0]S_AXI_HP1_ARLEN;
+  wire [1:0]S_AXI_HP1_ARLOCK;
+  wire [2:0]S_AXI_HP1_ARPROT;
+  wire [3:0]S_AXI_HP1_ARQOS;
+  wire S_AXI_HP1_ARREADY;
+  wire [2:0]S_AXI_HP1_ARSIZE;
+  wire S_AXI_HP1_ARVALID;
+  wire [31:0]S_AXI_HP1_AWADDR;
+  wire [1:0]S_AXI_HP1_AWBURST;
+  wire [3:0]S_AXI_HP1_AWCACHE;
+  wire [5:0]S_AXI_HP1_AWID;
+  wire [3:0]S_AXI_HP1_AWLEN;
+  wire [1:0]S_AXI_HP1_AWLOCK;
+  wire [2:0]S_AXI_HP1_AWPROT;
+  wire [3:0]S_AXI_HP1_AWQOS;
+  wire S_AXI_HP1_AWREADY;
+  wire [2:0]S_AXI_HP1_AWSIZE;
+  wire S_AXI_HP1_AWVALID;
+  wire [5:0]S_AXI_HP1_BID;
+  wire S_AXI_HP1_BREADY;
+  wire [1:0]S_AXI_HP1_BRESP;
+  wire S_AXI_HP1_BVALID;
+  wire [2:0]S_AXI_HP1_RACOUNT;
+  wire [7:0]S_AXI_HP1_RCOUNT;
+  wire [63:0]S_AXI_HP1_RDATA;
+  wire S_AXI_HP1_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP1_RID;
+  wire S_AXI_HP1_RLAST;
+  wire S_AXI_HP1_RREADY;
+  wire [1:0]S_AXI_HP1_RRESP;
+  wire S_AXI_HP1_RVALID;
+  wire [5:0]S_AXI_HP1_WACOUNT;
+  wire [7:0]S_AXI_HP1_WCOUNT;
+  wire [63:0]S_AXI_HP1_WDATA;
+  wire [5:0]S_AXI_HP1_WID;
+  wire S_AXI_HP1_WLAST;
+  wire S_AXI_HP1_WREADY;
+  wire S_AXI_HP1_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP1_WSTRB;
+  wire S_AXI_HP1_WVALID;
+  wire S_AXI_HP2_ACLK;
+  wire [31:0]S_AXI_HP2_ARADDR;
+  wire [1:0]S_AXI_HP2_ARBURST;
+  wire [3:0]S_AXI_HP2_ARCACHE;
+  wire S_AXI_HP2_ARESETN;
+  wire [5:0]S_AXI_HP2_ARID;
+  wire [3:0]S_AXI_HP2_ARLEN;
+  wire [1:0]S_AXI_HP2_ARLOCK;
+  wire [2:0]S_AXI_HP2_ARPROT;
+  wire [3:0]S_AXI_HP2_ARQOS;
+  wire S_AXI_HP2_ARREADY;
+  wire [2:0]S_AXI_HP2_ARSIZE;
+  wire S_AXI_HP2_ARVALID;
+  wire [31:0]S_AXI_HP2_AWADDR;
+  wire [1:0]S_AXI_HP2_AWBURST;
+  wire [3:0]S_AXI_HP2_AWCACHE;
+  wire [5:0]S_AXI_HP2_AWID;
+  wire [3:0]S_AXI_HP2_AWLEN;
+  wire [1:0]S_AXI_HP2_AWLOCK;
+  wire [2:0]S_AXI_HP2_AWPROT;
+  wire [3:0]S_AXI_HP2_AWQOS;
+  wire S_AXI_HP2_AWREADY;
+  wire [2:0]S_AXI_HP2_AWSIZE;
+  wire S_AXI_HP2_AWVALID;
+  wire [5:0]S_AXI_HP2_BID;
+  wire S_AXI_HP2_BREADY;
+  wire [1:0]S_AXI_HP2_BRESP;
+  wire S_AXI_HP2_BVALID;
+  wire [2:0]S_AXI_HP2_RACOUNT;
+  wire [7:0]S_AXI_HP2_RCOUNT;
+  wire [63:0]S_AXI_HP2_RDATA;
+  wire S_AXI_HP2_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP2_RID;
+  wire S_AXI_HP2_RLAST;
+  wire S_AXI_HP2_RREADY;
+  wire [1:0]S_AXI_HP2_RRESP;
+  wire S_AXI_HP2_RVALID;
+  wire [5:0]S_AXI_HP2_WACOUNT;
+  wire [7:0]S_AXI_HP2_WCOUNT;
+  wire [63:0]S_AXI_HP2_WDATA;
+  wire [5:0]S_AXI_HP2_WID;
+  wire S_AXI_HP2_WLAST;
+  wire S_AXI_HP2_WREADY;
+  wire S_AXI_HP2_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP2_WSTRB;
+  wire S_AXI_HP2_WVALID;
+  wire S_AXI_HP3_ACLK;
+  wire [31:0]S_AXI_HP3_ARADDR;
+  wire [1:0]S_AXI_HP3_ARBURST;
+  wire [3:0]S_AXI_HP3_ARCACHE;
+  wire S_AXI_HP3_ARESETN;
+  wire [5:0]S_AXI_HP3_ARID;
+  wire [3:0]S_AXI_HP3_ARLEN;
+  wire [1:0]S_AXI_HP3_ARLOCK;
+  wire [2:0]S_AXI_HP3_ARPROT;
+  wire [3:0]S_AXI_HP3_ARQOS;
+  wire S_AXI_HP3_ARREADY;
+  wire [2:0]S_AXI_HP3_ARSIZE;
+  wire S_AXI_HP3_ARVALID;
+  wire [31:0]S_AXI_HP3_AWADDR;
+  wire [1:0]S_AXI_HP3_AWBURST;
+  wire [3:0]S_AXI_HP3_AWCACHE;
+  wire [5:0]S_AXI_HP3_AWID;
+  wire [3:0]S_AXI_HP3_AWLEN;
+  wire [1:0]S_AXI_HP3_AWLOCK;
+  wire [2:0]S_AXI_HP3_AWPROT;
+  wire [3:0]S_AXI_HP3_AWQOS;
+  wire S_AXI_HP3_AWREADY;
+  wire [2:0]S_AXI_HP3_AWSIZE;
+  wire S_AXI_HP3_AWVALID;
+  wire [5:0]S_AXI_HP3_BID;
+  wire S_AXI_HP3_BREADY;
+  wire [1:0]S_AXI_HP3_BRESP;
+  wire S_AXI_HP3_BVALID;
+  wire [2:0]S_AXI_HP3_RACOUNT;
+  wire [7:0]S_AXI_HP3_RCOUNT;
+  wire [63:0]S_AXI_HP3_RDATA;
+  wire S_AXI_HP3_RDISSUECAP1_EN;
+  wire [5:0]S_AXI_HP3_RID;
+  wire S_AXI_HP3_RLAST;
+  wire S_AXI_HP3_RREADY;
+  wire [1:0]S_AXI_HP3_RRESP;
+  wire S_AXI_HP3_RVALID;
+  wire [5:0]S_AXI_HP3_WACOUNT;
+  wire [7:0]S_AXI_HP3_WCOUNT;
+  wire [63:0]S_AXI_HP3_WDATA;
+  wire [5:0]S_AXI_HP3_WID;
+  wire S_AXI_HP3_WLAST;
+  wire S_AXI_HP3_WREADY;
+  wire S_AXI_HP3_WRISSUECAP1_EN;
+  wire [7:0]S_AXI_HP3_WSTRB;
+  wire S_AXI_HP3_WVALID;
+  wire TRACE_CLK;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire \\TRACE_CTL_PIPE[7] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[0] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[1] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[2] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[3] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[4] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[5] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[6] ;
+  (* RTL_KEEP = ""true"" *) wire [1:0]\\TRACE_DATA_PIPE[7] ;
+  wire TTC0_CLK0_IN;
+  wire TTC0_CLK1_IN;
+  wire TTC0_CLK2_IN;
+  wire TTC0_WAVE0_OUT;
+  wire TTC0_WAVE1_OUT;
+  wire TTC0_WAVE2_OUT;
+  wire TTC1_CLK0_IN;
+  wire TTC1_CLK1_IN;
+  wire TTC1_CLK2_IN;
+  wire TTC1_WAVE0_OUT;
+  wire TTC1_WAVE1_OUT;
+  wire TTC1_WAVE2_OUT;
+  wire UART0_CTSN;
+  wire UART0_DCDN;
+  wire UART0_DSRN;
+  wire UART0_DTRN;
+  wire UART0_RIN;
+  wire UART0_RTSN;
+  wire UART0_RX;
+  wire UART0_TX;
+  wire UART1_CTSN;
+  wire UART1_DCDN;
+  wire UART1_DSRN;
+  wire UART1_DTRN;
+  wire UART1_RIN;
+  wire UART1_RTSN;
+  wire UART1_RX;
+  wire UART1_TX;
+  wire [1:0]USB0_PORT_INDCTL;
+  wire USB0_VBUS_PWRFAULT;
+  wire USB0_VBUS_PWRSELECT;
+  wire [1:0]USB1_PORT_INDCTL;
+  wire USB1_VBUS_PWRFAULT;
+  wire USB1_VBUS_PWRSELECT;
+  wire WDT_CLK_IN;
+  wire WDT_RST_OUT;
+  wire [14:0]buffered_DDR_Addr;
+  wire [2:0]buffered_DDR_BankAddr;
+  wire buffered_DDR_CAS_n;
+  wire buffered_DDR_CKE;
+  wire buffered_DDR_CS_n;
+  wire buffered_DDR_Clk;
+  wire buffered_DDR_Clk_n;
+  wire [3:0]buffered_DDR_DM;
+  wire [31:0]buffered_DDR_DQ;
+  wire [3:0]buffered_DDR_DQS;
+  wire [3:0]buffered_DDR_DQS_n;
+  wire buffered_DDR_DRSTB;
+  wire buffered_DDR_ODT;
+  wire buffered_DDR_RAS_n;
+  wire buffered_DDR_VRN;
+  wire buffered_DDR_VRP'b';
+  wire buffered_DDR_WEB;
+  wire [53:0]buffered_MIO;
+  wire buffered_PS_CLK;
+  wire buffered_PS_PORB;
+  wire buffered_PS_SRSTB;
+  wire [63:0]gpio_out_t_n;
+  wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
+  wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
+  wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
+  wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
+  wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
+
+  assign ENET0_GMII_TXD[7] = \\<const0> ;
+  assign ENET0_GMII_TXD[6] = \\<const0> ;
+  assign ENET0_GMII_TXD[5] = \\<const0> ;
+  assign ENET0_GMII_TXD[4] = \\<const0> ;
+  assign ENET0_GMII_TXD[3] = \\<const0> ;
+  assign ENET0_GMII_TXD[2] = \\<const0> ;
+  assign ENET0_GMII_TXD[1] = \\<const0> ;
+  assign ENET0_GMII_TXD[0] = \\<const0> ;
+  assign ENET0_GMII_TX_EN = \\<const0> ;
+  assign ENET0_GMII_TX_ER = \\<const0> ;
+  assign ENET1_GMII_TXD[7] = \\<const0> ;
+  assign ENET1_GMII_TXD[6] = \\<const0> ;
+  assign ENET1_GMII_TXD[5] = \\<const0> ;
+  assign ENET1_GMII_TXD[4] = \\<const0> ;
+  assign ENET1_GMII_TXD[3] = \\<const0> ;
+  assign ENET1_GMII_TXD[2] = \\<const0> ;
+  assign ENET1_GMII_TXD[1] = \\<const0> ;
+  assign ENET1_GMII_TXD[0] = \\<const0> ;
+  assign ENET1_GMII_TX_EN = \\<const0> ;
+  assign ENET1_GMII_TX_ER = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_ARSIZE[1:0] = \\^M_AXI_GP0_ARSIZE [1:0];
+  assign M_AXI_GP0_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP0_AWSIZE[1:0] = \\^M_AXI_GP0_AWSIZE [1:0];
+  assign M_AXI_GP1_ARSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_ARSIZE[1:0] = \\^M_AXI_GP1_ARSIZE [1:0];
+  assign M_AXI_GP1_AWSIZE[2] = \\<const0> ;
+  assign M_AXI_GP1_AWSIZE[1:0] = \\^M_AXI_GP1_AWSIZE [1:0];
+  assign PJTAG_TDO = \\<const0> ;
+  assign TRACE_CLK_OUT = \\<const0> ;
+  assign TRACE_CTL = \\TRACE_CTL_PIPE[0] ;
+  assign TRACE_DATA[1:0] = \\TRACE_DATA_PIPE[0] ;
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CAS_n_BIBUF
+       (.IO(buffered_DDR_CAS_n),
+        .PAD(DDR_CAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CKE_BIBUF
+       (.IO(buffered_DDR_CKE),
+        .PAD(DDR_CKE));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_CS_n_BIBUF
+       (.IO(buffered_DDR_CS_n),
+        .PAD(DDR_CS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_BIBUF
+       (.IO(buffered_DDR_Clk),
+        .PAD(DDR_Clk));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_Clk_n_BIBUF
+       (.IO(buffered_DDR_Clk_n),
+        .PAD(DDR_Clk_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_DRSTB_BIBUF
+       (.IO(buffered_DDR_DRSTB),
+        .PAD(DDR_DRSTB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_ODT_BIBUF
+       (.IO(buffered_DDR_ODT),
+        .PAD(DDR_ODT));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_RAS_n_BIBUF
+       (.IO(buffered_DDR_RAS_n),
+        .PAD(DDR_RAS_n));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRN_BIBUF
+       (.IO(buffered_DDR_VRN),
+        .PAD(DDR_VRN));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_VRP_BIBUF
+       (.IO(buffered_DDR_VRP),
+        .PAD(DDR_VRP));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF DDR_WEB_BIBUF
+       (.IO(buffered_DDR_WEB),
+        .PAD(DDR_WEB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET0_MDIO_T_INST_0
+       (.I0(ENET0_MDIO_T_n),
+        .O(ENET0_MDIO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    ENET1_MDIO_T_INST_0
+       (.I0(ENET1_MDIO_T_n),
+        .O(ENET1_MDIO_T));
+  GND GND
+       (.G(\\<const0> ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[0]_INST_0 
+       (.I0(gpio_out_t_n[0]),
+        .O(GPIO_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[10]_INST_0 
+       (.I0(gpio_out_t_n[10]),
+        .O(GPIO_T[10]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[11]_INST_0 
+       (.I0(gpio_out_t_n[11]),
+        .O(GPIO_T[11]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[12]_INST_0 
+       (.I0(gpio_out_t_n[12]),
+        .O(GPIO_T[12]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[13]_INST_0 
+       (.I0(gpio_out_t_n[13]),
+        .O(GPIO_T[13]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[14]_INST_0 
+       (.I0(gpio_out_t_n[14]),
+        .O(GPIO_T[14]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[15]_INST_0 
+       (.I0(gpio_out_t_n[15]),
+        .O(GPIO_T[15]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[16]_INST_0 
+       (.I0(gpio_out_t_n[16]),
+        .O(GPIO_T[16]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[17]_INST_0 
+       (.I0(gpio_out_t_n[17]),
+        .O(GPIO_T[17]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[18]_INST_0 
+       (.I0(gpio_out_t_n[18]),
+        .O(GPIO_T[18]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[19]_INST_0 
+       (.I0(gpio_out_t_n[19]),
+        .O(GPIO_T[19]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[1]_INST_0 
+       (.I0(gpio_out_t_n[1]),
+        .O(GPIO_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[20]_INST_0 
+       (.I0(gpio_out_t_n[20]),
+        .O(GPIO_T[20]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[21]_INST_0 
+       (.I0(gpio_out_t_n[21]),
+        .O(GPIO_T[21]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[22]_INST_0 
+       (.I0(gpio_out_t_n[22]),
+        .O(GPIO_T[22]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[23]_INST_0 
+       (.I0(gpio_out_t_n[23]),
+        .O(GPIO_T[23]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[24]_INST_0 
+       (.I0(gpio_out_t_n[24]),
+        .O(GPIO_T[24]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[25]_INST_0 
+       (.I0(gpio_out_t_n[25]),
+        .O(GPIO_T[25]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[26]_INST_0 
+       (.I0(gpio_out_t_n[26]),
+        .O(GPIO_T[26]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[27]_INST_0 
+       (.I0(gpio_out_t_n[27]),
+        .O(GPIO_T[27]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[28]_INST_0 
+       (.I0(gpio_out_t_n[28]),
+        .O(GPIO_T[28]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[29]_INST_0 
+       (.I0(gpio_out_t_n[29]),
+        .O(GPIO_T[29]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[2]_INST_0 
+       (.I0(gpio_out_t_n[2]),
+        .O(GPIO_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[30]_INST_0 
+       (.I0(gpio_out_t_n[30]),
+        .O(GPIO_T[30]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[31]_INST_0 
+       (.I0(gpio_out_t_n[31]),
+        .O(GPIO_T[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[32]_INST_0 
+       (.I0(gpio_out_t_n[32]),
+        .O(GPIO_T[32]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[33]_INST_0 
+       (.I0(gpio_out_t_n[33]),
+        .O(GPIO_T[33]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[34]_INST_0 
+       (.I0(gpio_out_t_n[34]),
+        .O(GPIO_T[34]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[35]_INST_0 
+       (.I0(gpio_out_t_n[35]),
+        .O(GPIO_T[35]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[36]_INST_0 
+       (.I0(gpio_out_t_n[36]),
+        .O(GPIO_T[36]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[37]_INST_0 
+       (.I0(gpio_out_t_n[37]),
+        .O(GPIO_T[37]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[38]_INST_0 
+       (.I0(gpio_out_t_n[38]),
+        .O(GPIO_T[38]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[39]_INST_0 
+       (.I0(gpio_out_t_n[39]),
+        .O(GPIO_T[39]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[3]_INST_0 
+       (.I0(gpio_out_t_n[3]),
+        .O(GPIO_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[40]_INST_0 
+       (.I0(gpio_out_t_n[40]),
+        .O(GPIO_T[40]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[41]_INST_0 
+       (.I0(gpio_out_t_n[41]),
+        .O(GPIO_T[41]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[42]_INST_0 
+       (.I0(gpio_out_t_n[42]),
+        .O(GPIO_T[42]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[43]_INST_0 
+       (.I0(gpio_out_t_n[43]),
+        .O(GPIO_T[43]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[44]_INST_0 
+       (.I0(gpio_out_t_n[44]),
+        .O(GPIO_T[44]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[45]_INST_0 
+       (.I0(gpio_out_t_n[45]),
+        .O(GPIO_T[45]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[46]_INST_0 
+       (.I0(gpio_out_t_n[46]),
+        .O(GPIO_T[46]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[47]_INST_0 
+       (.I0(gpio_out_t_n[47]),
+        .O(GPIO_T[47]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[48]_INST_0 
+       (.I0(gpio_out_t_n[48]),
+        .O(GPIO_T[48]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[49]_INST_0 
+       (.I0(gpio_out_t_n[49]),
+        .O(GPIO_T[49]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[4]_INST_0 
+       (.I0(gpio_out_t_n[4]),
+        .O(GPIO_T[4]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[50]_INST_0 
+       (.I0(gpio_out_t_n[50]),
+        .O(GPIO_T[50]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[51]_INST_0 
+       (.I0(gpio_out_t_n[51]),
+        .O(GPIO_T[51]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[52]_INST_0 
+       (.I0(gpio_out_t_n[52]),
+        .O(GPIO_T[52]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[53]_INST_0 
+       (.I0(gpio_out_t_n[53]),
+        .O(GPIO_T[53]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[54]_INST_0 
+       (.I0(gpio_out_t_n[54]),
+        .O(GPIO_T[54]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[55]_INST_0 
+       (.I0(gpio_out_t_n[55]),
+        .O(GPIO_T[55]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[56]_INST_0 
+       (.I0(gpio_out_t_n[56]),
+        .O(GPIO_T[56]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[57]_INST_0 
+       (.I0(gpio_out_t_n[57]),
+        .O(GPIO_T[57]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[58]_INST_0 
+       (.I0(gpio_out_t_n[58]),
+        .O(GPIO_T[58]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[59]_INST_0 
+       (.I0(gpio_out_t_n[59]),
+        .O(GPIO_T[59]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[5]_INST_0 
+       (.I0(gpio_out_t_n[5]),
+        .O(GPIO_T[5]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[60]_INST_0 
+       (.I0(gpio_out_t_n[60]),
+        .O(GPIO_T[60]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[61]_INST_0 
+       (.I0(gpio_out_t_n[61]),
+        .O(GPIO_T[61]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[62]_INST_0 
+       (.I0(gpio_out_t_n[62]),
+        .O(GPIO_T[62]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[63]_INST_0 
+       (.I0(gpio_out_t_n[63]),
+        .O(GPIO_T[63]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[6]_INST_0 
+       (.I0(gpio_out_t_n[6]),
+        .O(GPIO_T[6]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[7]_INST_0 
+       (.I0(gpio_out_t_n[7]),
+        .O(GPIO_T[7]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[8]_INST_0 
+       (.I0(gpio_out_t_n[8]),
+        .O(GPIO_T[8]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\GPIO_T[9]_INST_0 
+       (.I0(gpio_out_t_n[9]),
+        .O(GPIO_T[9]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SCL_T_INST_0
+       (.I0(I2C0_SCL_T_n),
+        .O(I2C0_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C0_SDA_T_INST_0
+       (.I0(I2C0_SDA_T_n),
+        .O(I2C0_SDA_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SCL_T_INST_0
+       (.I0(I2C1_SCL_T_n),
+        .O(I2C1_SCL_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    I2C1_SDA_T_INST_0
+       (.I0(I2C1_SDA_T_n),
+        .O(I2C1_SDA_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  PS7 PS7_i
+       (.DDRA(buffered_DDR_Addr),
+        .DDRARB(DDR_ARB),
+        .DDRBA(buffered_DDR_BankAddr),
+        .DDRCASB(buffered_DDR_CAS_n),
+        .DDRCKE(buffered_DDR_CKE),
+        .DDRCKN(buffered_DDR_Clk_n),
+        .DDRCKP(buffered_DDR_Clk),
+        .DDRCSB(buffered_DDR_CS_n),
+        .DDRDM(buffered_DDR_DM),
+        .DDRDQ(buffered_DDR_DQ),
+        .DDRDQSN(buffered_DDR_DQS_n),
+        .DDRDQSP(buffered_DDR_DQS),
+        .DDRDRSTB(buffered_DDR_DRSTB),
+        .DDRODT(buffered_DDR_ODT),
+        .DDRRASB(buffered_DDR_RAS_n),
+        .DDRVRN(buffered_DDR_VRN),
+        .DDRVRP(buffered_DDR_VRP),
+        .DDRWEB(buffered_DDR_WEB),
+        .DMA0ACLK(DMA0_ACLK),
+        .DMA0DAREADY(DMA0_DAREADY),
+        .DMA0DATYPE(DMA0_DATYPE),
+        .DMA0DAVALID(DMA0_DAVALID),
+        .DMA0DRLAST(DMA0_DRLAST),
+        .DMA0DRREADY(DMA0_DRREADY),
+        .DMA0DRTYPE(DMA0_DRTYPE),
+        .DMA0DRVALID(DMA0_DRVALID),
+        .DMA0RSTN(DMA0_RSTN),
+        .DMA1ACLK(DMA1_ACLK),
+        .DMA1DAREADY(DMA1_DAREADY),
+        .DMA1DATYPE(DMA1_DATYPE),
+        .DMA1DAVALID(DMA1_DAVALID),
+        .DMA1DRLAST(DMA1_DRLAST),
+        .DMA1DRREADY(DMA1_DRREADY),
+        .DMA1DRTYPE(DMA1_DRTYPE),
+        .DMA1DRVALID(DMA1_DRVALID),
+        .DMA1RSTN(DMA1_RSTN),
+        .DMA2ACLK(DMA2_ACLK),
+        .DMA2DAREADY(DMA2_DAREADY),
+        .DMA2DATYPE(DMA2_DATYPE),
+        .DMA2DAVALID(DMA2_DAVALID),
+        .DMA2DRLAST(DMA2_DRLAST),
+        .DMA2DRREADY(DMA2_DRREADY),
+        .DMA2DRTYPE(DMA2_DRTYPE),
+        .DMA2DRVALID(DMA2_DRVALID),
+        .DMA2RSTN(DMA2_RSTN),
+        .DMA3ACLK(DMA3_ACLK),
+        .DMA3DAREADY(DMA3_DAREADY),
+        .DMA3DATYPE(DMA3_DATYPE),
+        .DMA3DAVALID(DMA3_DAVALID),
+        .DMA3DRLAST(DMA3_DRLAST),
+        .DMA3DRREADY(DMA3_DRREADY),
+        .DMA3DRTYPE(DMA3_DRTYPE),
+        .DMA3DRVALID(DMA3_DRVALID),
+        .DMA3RSTN(DMA3_RSTN),
+        .EMIOCAN0PHYRX(CAN0_PHY_RX),
+        .EMIOCAN0PHYTX(CAN0_PHY_TX),
+        .EMIOCAN1PHYRX(CAN1_PHY_RX),
+        .EMIOCAN1PHYTX(CAN1_PHY_TX),
+        .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
+        .EMIOENET0GMIICOL(1\'b0),
+        .EMIOENET0GMIICRS(1\'b0),
+        .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
+        .EMIOENET0GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET0GMIIRXDV(1\'b0),
+        .EMIOENET0GMIIRXER(1\'b0),
+        .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
+        .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
+        .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
+        .EMIOENET0MDIOI(ENET0_MDIO_I),
+        .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
+        .EMIOENET0MDIOO(ENET0_MDIO_O),
+        .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
+        .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
+        .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
+        .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
+        .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+        .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+        .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
+        .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
+        .EMIOENET0SOFRX(ENET0_SOF_RX),
+        .EMIOENET0SOFTX(ENET0_SOF_TX),
+        .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
+        .EMIOENET1GMIICOL(1\'b0),
+        .EMIOENET1GMIICRS(1\'b0),
+        .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
+        .EMIOENET1GMIIRXD({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .EMIOENET1GMIIRXDV(1\'b0),
+        .EMIOENET1GMIIRXER(1\'b0),
+        .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
+        .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
+        .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
+        .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
+        .EMIOENET1MDIOI(ENET1_MDIO_I),
+        .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
+        .EMIOENET1MDIOO(ENET1_MDIO_O),
+        .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
+        .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
+        .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
+        .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
+        .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+        .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+        .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
+        .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
+        .EMIOENET1SOFRX(ENET1_SOF_RX),
+        .EMIOENET1SOFTX(ENET1_SOF_TX),
+        .EMIOGPIOI(GPIO_I),
+        .EMIOGPIOO(GPIO_O),
+        .EMIOGPIOTN(gpio_out_t_n),
+        .EMIOI2C0SCLI(I2C0_SCL_I),
+        .EMIOI2C0SCLO(I2C0_SCL_O),
+        .EMIOI2C0SCLTN(I2C0_SCL_T_n),
+        .EMIOI2C0SDAI(I2C0_SDA_I),
+        .EMIOI2C0SDAO(I2C0_SDA_O),
+        .EMIOI2C0SDATN(I2C0_SDA_T_n),
+        .EMIOI2C1SCLI(I2C1_SCL_I),
+        .EMIOI2C1SCLO(I2C1_SCL_O),
+        .EMIOI2C1SCLTN(I2C1_SCL_T_n),
+        .EMIOI2C1SDAI(I2C1_SDA_I),
+        .EMIOI2C1SDAO(I2C1_SDA_O),
+        .EMIOI2C1SDATN(I2C1_SDA_T_n),
+        .EMIOPJTAGTCK(PJTAG_TCK),
+        .EMIOPJTAGTDI(PJTAG_TDI),
+        .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
+        .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
+        .EMIOPJTAGTMS(PJTAG_TMS),
+        .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
+        .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
+        .EMIOSDIO0CDN(SDIO0_CDN),
+        .EMIOSDIO0CLK(SDIO0_CLK),
+        .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
+        .EMIOSDIO0CMDI(SDIO0_CMD_I),
+        .EMIOSDIO0CMDO(SDIO0_CMD_O),
+        .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
+        .EMIOSDIO0DATAI(SDIO0_DATA_I),
+        .EMIOSDIO0DATAO(SDIO0_DATA_O),
+        .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
+        .EMIOSDIO0LED(SDIO0_LED),
+        .EMIOSDIO0WP(SDIO0_WP),
+        .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
+        .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
+        .EMIOSDIO1CDN(SDIO1_CDN),
+        .EMIOSDIO1CLK(SDIO1_CLK),
+        .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
+        .EMIOSDIO1CMDI(SDIO1_CMD_I),
+        .EMIOSDIO1CMDO(SDIO1_CMD_O),
+        .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
+        .EMIOSDIO1DATAI(SDIO1_DATA_I),
+        .EMIOSDIO1DATAO(SDIO1_DATA_O),
+        .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
+        .EMIOSDIO1LED(SDIO1_LED),
+        .EMIOSDIO1WP(SDIO1_WP),
+        .EMIOSPI0MI(SPI0_MISO_I),
+        .EMIOSPI0MO(SPI0_MOSI_O),
+        .EMIOSPI0MOTN(SPI0_MOSI_T_n),
+        .EMIOSPI0SCLKI(SPI0_SCLK_I),
+        .EMIOSPI0SCLKO(SPI0_SCLK_O),
+        .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
+        .EMIOSPI0SI(SPI0_MOSI_I),
+        .EMIOSPI0SO(SPI0_MISO_O),
+        .EMIOSPI0SSIN(SPI0_SS_I),
+        .EMIOSPI0SSNTN(SPI0_SS_T_n),
+        .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+        .EMIOSPI0STN(SPI0_MISO_T_n),
+        .EMIOSPI1MI(SPI1_MISO_I),
+        .EMIOSPI1MO(SPI1_MOSI_O),
+        .EMIOSPI1MOTN(SPI1_MOSI_T_n),
+        .EMIOSPI1SCLKI(SPI1_SCLK_I),
+        .EMIOSPI1SCLKO(SPI1_SCLK_O),
+        .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
+        .EMIOSPI1SI(SPI1_MOSI_I),
+        .EMIOSPI1SO(SPI1_MISO_O),
+        .EMIOSPI1SSIN(SPI1_SS_I),
+        .EMIOSPI1SSNTN(SPI1_SS_T_n),
+        .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+        .EMIOSPI1STN(SPI1_MISO_T_n),
+        .EMIOSRAMINTIN(SRAM_INTIN),
+        .EMIOTRACECLK(TRACE_CLK),
+        .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
+        .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
+        .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
+        .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+        .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
+        .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+        .EMIOUART0CTSN(UART0_CTSN),
+        .EMIOUART0DCDN(UART0_DCDN),
+        .EMIOUART0DSRN(UART0_DSRN),
+        .EMIOUART0DTRN(UART0_DTRN),
+        .EMIOUART0RIN(UART0_RIN),
+        .EMIOUART0RTSN(UART0_RTSN),
+        .EMIOUART0RX(UART0_RX),
+        .EMIOUART0TX(UART0_TX),
+        .EMIOUART1CTSN(UART1_CTSN),
+        .EMIOUART1DCDN(UART1_DCDN),
+        .EMIOUART1DSRN(UART1_DSRN),
+        .EMIOUART1DTRN(UART1_DTRN),
+        .EMIOUART1RIN(UART1_RIN),
+        .EMIOUART1RTSN(UART1_RTSN),
+        .EMIOUART1RX(UART1_RX),
+        .EMIOUART1TX(UART1_TX),
+        .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
+        .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
+        .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
+        .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
+        .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
+        .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
+        .EMIOWDTCLKI(WDT_CLK_IN),
+        .EMIOWDTRSTO(WDT_RST_OUT),
+        .EVENTEVENTI(EVENT_EVENTI),
+        .EVENTEVENTO(EVENT_EVENTO),
+        .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
+        .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
+        .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
+        .FCLKCLKTRIGN({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
+        .FPGAIDLEN(FPGA_IDLE_N),
+        .FTMDTRACEINATID({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
+        .FTMDTRACEINDATA({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .FTMDTRACEINVALID(1\'b0),
+        .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
+        .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+        .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+        .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
+        .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+        .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
+        .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,IRQ_F2P}),
+        .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
+        .MAXIGP0ACLK(M_AXI_GP0_ACLK),
+        .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
+        .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
+        .MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
+        .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
+        .MAXIGP0ARID(M_AXI_GP0_ARID),
+        .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
+        .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
+        .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
+        .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
+        .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
+        .MAXIGP0ARSIZE(\\^M_AXI_GP0_ARSIZE ),
+        .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
+        .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
+        .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
+        .MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
+        .MAXIGP0AWID(M_AXI_GP0_AWID),
+        .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
+        .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
+        .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
+        .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
+        .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
+        .MAXIGP0AWSIZE(\\^M_AXI_GP0_AWSIZE ),
+        .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
+        .MAXIGP0BID(M_AXI_GP0_BID),
+        .MAXIGP0BREADY(M_AXI_GP0_BREADY),
+        .MAXIGP0BRESP(M_AXI_GP0_BRESP),
+        .MAXIGP0BVALID(M_AXI_GP0_BVALID),
+        .MAXIGP0RDATA(M_AXI_GP0_RDATA),
+        .MAXIGP0RID(M_AXI_GP0_RID),
+        .MAXIGP0RLAST(M_AXI_GP0_RLAST),
+        .MAXIGP0RREADY(M_AXI_GP0_RREADY),
+        .MAXIGP0RRESP(M_AXI_GP0_RRESP),
+        .MAXIGP0RVALID(M_AXI_GP0_RVALID),
+        .MAXIGP0WDATA(M_AXI_GP0_WDATA),
+        .MAXIGP0WID(M_AXI_GP0_WID),
+        .MAXIGP0WLAST(M_AXI_GP0_WLAST),
+        .MAXIGP0WREADY(M_AXI_GP0_WREADY),
+        .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
+        .MAXIGP0WVALID(M_AXI_GP0_WVALID),
+        .MAXIGP1ACLK(M_AXI_GP1_ACLK),
+        .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
+        .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
+        .MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
+        .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
+        .MAXIGP1ARID(M_AXI_GP1_ARID),
+        .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
+        .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
+        .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
+        .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
+        .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
+        .MAXIGP1ARSIZE(\\^M_AXI_GP1_ARSIZE ),
+        .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
+        .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
+        .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
+        .MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
+        .MAXIGP1AWID(M_AXI_GP1_AWID),
+        .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
+        .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
+        .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
+        .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
+        .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
+        .MAXIGP1AWSIZE(\\^M_AXI_GP1_AWSIZE ),
+        .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
+        .MAXIGP1BID(M_AXI_GP1_BID),
+        .MAXIGP1BREADY(M_AXI_GP1_BREADY),
+        .MAXIGP1BRESP(M_AXI_GP1_BRESP),
+        .MAXIGP1BVALID(M_AXI_GP1_BVALID),
+        .MAXIGP1RDATA(M_AXI_GP1_RDATA),
+        .MAXIGP1RID(M_AXI_GP1_RID),
+        .MAXIGP1RLAST(M_AXI_GP1_RLAST),
+        .MAXIGP1RREADY(M_AXI_GP1_RREADY),
+        .MAXIGP1RRESP(M_AXI_GP1_RRESP),
+        .MAXIGP1RVALID(M_AXI_GP1_RVALID),
+        .MAXIGP1WDATA(M_AXI_GP1_WDATA),
+        .MAXIGP1WID(M_AXI_GP1_WID),
+        .MAXIGP1WLAST(M_AXI_GP1_WLAST),
+        .MAXIGP1WREADY(M_AXI_GP1_WREADY),
+        .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
+        .MAXIGP1WVALID(M_AXI_GP1_WVALID),
+        .MIO(buffered_MIO),
+        .PSCLK(buffered_PS_CLK),
+        .PSPORB(buffered_PS_PORB),
+        .PSSRSTB(buffered_PS_SRSTB),
+        .SAXIACPACLK(S_AXI_ACP_ACLK),
+        .SAXIACPARADDR(S_AXI_ACP_ARADDR),
+        .SAXIACPARBURST(S_AXI_ACP_ARBURST),
+        .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
+        .SAXIACPARESETN(S_AXI_ACP_ARESETN),
+        .SAXIACPARID(S_AXI_ACP_ARID),
+        .SAXIACPARLEN(S_AXI_ACP_ARLEN),
+        .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
+        .SAXIACPARPROT(S_AXI_ACP_ARPROT),
+        .SAXIACPARQOS(S_AXI_ACP_ARQOS),
+        .SAXIACPARREADY(S_AXI_ACP_ARREADY),
+        .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
+        .SAXIACPARUSER(S_AXI_ACP_ARUSER),
+        .SAXIACPARVALID(S_AXI_ACP_ARVALID),
+        .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
+        .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
+        .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
+        .SAXIACPAWID(S_AXI_ACP_AWID),
+        .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
+        .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
+        .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
+        .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
+        .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
+        .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
+        .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
+        .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
+        .SAXIACPBID(S_AXI_ACP_BID),
+        .SAXIACPBREADY(S_AXI_ACP_BREADY),
+        .SAXIACPBRESP(S_AXI_ACP_BRESP),
+        .SAXIACPBVALID(S_AXI_ACP_BVALID),
+        .SAXIACPRDATA(S_AXI_ACP_RDATA),
+        .SAXIACPRID(S_AXI_ACP_RID),
+        .SAXIACPRLAST(S_AXI_ACP_RLAST),
+        .SAXIACPRREADY(S_AXI_ACP_RREADY),
+        .SAXIACPRRESP(S_AXI_ACP_RRESP),
+        .SAXIACPRVALID(S_AXI_ACP_RVALID),
+        .SAXIACPWDATA(S_AXI_ACP_WDATA),
+        .SAXIACPWID(S_AXI_ACP_WID),
+        .SAXIACPWLAST(S_AXI_ACP_WLAST),
+        .SAXIACPWREADY(S_AXI_ACP_WREADY),
+        .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
+        .SAXIACPWVALID(S_AXI_ACP_WVALID),
+        .SAXIGP0ACLK(S_AXI_GP0_ACLK),
+        .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
+        .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
+        .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
+        .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
+        .SAXIGP0ARID(S_AXI_GP0_ARID),
+        .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
+        .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
+        .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
+        .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
+        .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
+        .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
+        .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
+        .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
+        .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
+        .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
+        .SAXIGP0AWID(S_AXI_GP0_AWID),
+        .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
+        .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
+        .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
+        .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
+        .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
+        .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
+        .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
+        .SAXIGP0BID(S_AXI_GP0_BID),
+        .SAXIGP0BREADY(S_AXI_GP0_BREADY),
+        .SAXIGP0BRESP(S_AXI_GP0_BRESP),
+        .SAXIGP0BVALID(S_AXI_GP0_BVALID),
+        .SAXIGP0RDATA(S_AXI_GP0_RDATA),
+        .SAXIGP0RID(S_AXI_GP0_RID),
+        .SAXIGP0RLAST(S_AXI_GP0_RLAST),
+        .SAXIGP0RREADY(S_AXI_GP0_RREADY),
+        .SAXIGP0RRESP(S_AXI_GP0_RRESP),
+        .SAXIGP0RVALID(S_AXI_GP0_RVALID),
+        .SAXIGP0WDATA(S_AXI_GP0_WDATA),
+        .SAXIGP0WID(S_AXI_GP0_WID),
+        .SAXIGP0WLAST(S_AXI_GP0_WLAST),
+        .SAXIGP0WREADY(S_AXI_GP0_WREADY),
+        .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
+        .SAXIGP0WVALID(S_AXI_GP0_WVALID),
+        .SAXIGP1ACLK(S_AXI_GP1_ACLK),
+        .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
+        .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
+        .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
+        .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
+        .SAXIGP1ARID(S_AXI_GP1_ARID),
+        .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
+        .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
+        .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
+        .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
+        .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
+        .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
+        .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
+        .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
+        .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
+        .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
+        .SAXIGP1AWID(S_AXI_GP1_AWID),
+        .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
+        .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
+        .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
+        .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
+        .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
+        .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
+        .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
+        .SAXIGP1BID(S_AXI_GP1_BID),
+        .SAXIGP1BREADY(S_AXI_GP1_BREADY),
+        .SAXIGP1BRESP(S_AXI_GP1_BRESP),
+        .SAXIGP1BVALID(S_AXI_GP1_BVALID),
+        .SAXIGP1RDATA(S_AXI_GP1_RDATA),
+        .SAXIGP1RID(S_AXI_GP1_RID),
+        .SAXIGP1RLAST(S_AXI_GP1_RLAST),
+        .SAXIGP1RREADY(S_AXI_GP1_RREADY),
+        .SAXIGP1RRESP(S_AXI_GP1_RRESP),
+        .SAXIGP1RVALID(S_AXI_GP1_RVALID),
+        .SAXIGP1WDATA(S_AXI_GP1_WDATA),
+        .SAXIGP1WID(S_AXI_GP1_WID),
+        .SAXIGP1WLAST(S_AXI_GP1_WLAST),
+        .SAXIGP1WREADY(S_AXI_GP1_WREADY),
+        .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
+        .SAXIGP1WVALID(S_AXI_GP1_WVALID),
+        .SAXIHP0ACLK(S_AXI_HP0_ACLK),
+        .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
+        .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
+        .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
+        .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
+        .SAXIHP0ARID(S_AXI_HP0_ARID),
+        .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
+        .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
+        .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
+        .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
+        .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
+        .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
+        .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
+        .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
+        .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
+        .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
+        .SAXIHP0AWID(S_AXI_HP0_AWID),
+        .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
+        .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
+        .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
+        .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
+        .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
+        .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
+        .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
+        .SAXIHP0BID(S_AXI_HP0_BID),
+        .SAXIHP0BREADY(S_AXI_HP0_BREADY),
+        .SAXIHP0BRESP(S_AXI_HP0_BRESP),
+        .SAXIHP0BVALID(S_AXI_HP0_BVALID),
+        .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
+        .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
+        .SAXIHP0RDATA(S_AXI_HP0_RDATA),
+        .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
+        .SAXIHP0RID(S_AXI_HP0_RID),
+        .SAXIHP0RLAST(S_AXI_HP0_RLAST),
+        .SAXIHP0RREADY(S_AXI_HP0_RREADY),
+        .SAXIHP0RRESP(S_AXI_HP0_RRESP),
+        .SAXIHP0RVALID(S_AXI_HP0_RVALID),
+        .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
+        .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
+        .SAXIHP0WDATA(S_AXI_HP0_WDATA),
+        .SAXIHP0WID(S_AXI_HP0_WID),
+        .SAXIHP0WLAST(S_AXI_HP0_WLAST),
+        .SAXIHP0WREADY(S_AXI_HP0_WREADY),
+        .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
+        .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
+        .SAXIHP0WVALID(S_AXI_HP0_WVALID),
+        .SAXIHP1ACLK(S_AXI_HP1_ACLK),
+        .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
+        .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
+        .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
+        .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
+        .SAXIHP1ARID(S_AXI_HP1_ARID),
+        .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
+        .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
+        .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
+        .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
+        .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
+        .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
+        .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
+        .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
+        .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
+        .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
+        .SAXIHP1AWID(S_AXI_HP1_AWID),
+        .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
+        .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
+        .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
+        .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
+        .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
+        .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
+        .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
+        .SAXIHP1BID(S_AXI_HP1_BID),
+        .SAXIHP1BREADY(S_AXI_HP1_BREADY),
+        .SAXIHP1BRESP(S_AXI_HP1_BRESP),
+        .SAXIHP1BVALID(S_AXI_HP1_BVALID),
+        .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
+        .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
+        .SAXIHP1RDATA(S_AXI_HP1_RDATA),
+        .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
+        .SAXIHP1RID(S_AXI_HP1_RID),
+        .SAXIHP1RLAST(S_AXI_HP1_RLAST),
+        .SAXIHP1RREADY(S_AXI_HP1_RREADY),
+        .SAXIHP1RRESP(S_AXI_HP1_RRESP),
+        .SAXIHP1RVALID(S_AXI_HP1_RVALID),
+        .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
+        .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
+        .SAXIHP1WDATA(S_AXI_HP1_WDATA),
+        .SAXIHP1WID(S_AXI_HP1_WID),
+        .SAXIHP1WLAST(S_AXI_HP1_WLAST),
+        .SAXIHP1WREADY(S_AXI_HP1_WREADY),
+        .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
+        .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
+        .SAXIHP1WVALID(S_AXI_HP1_WVALID),
+        .SAXIHP2ACLK(S_AXI_HP2_ACLK),
+        .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
+        .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
+        .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
+        .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
+        .SAXIHP2ARID(S_AXI_HP2_ARID),
+        .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
+        .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
+        .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
+        .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
+        .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
+        .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
+        .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
+        .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
+        .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
+        .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
+        .SAXIHP2AWID(S_AXI_HP2_AWID),
+        .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
+        .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
+        .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
+        .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
+        .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
+        .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
+        .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
+        .SAXIHP2BID(S_AXI_HP2_BID),
+        .SAXIHP2BREADY(S_AXI_HP2_BREADY),
+        .SAXIHP2BRESP(S_AXI_HP2_BRESP),
+        .SAXIHP2BVALID(S_AXI_HP2_BVALID),
+        .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
+        .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
+        .SAXIHP2RDATA(S_AXI_HP2_RDATA),
+        .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
+        .SAXIHP2RID(S_AXI_HP2_RID),
+        .SAXIHP2RLAST(S_AXI_HP2_RLAST),
+        .SAXIHP2RREADY(S_AXI_HP2_RREADY),
+        .SAXIHP2RRESP(S_AXI_HP2_RRESP),
+        .SAXIHP2RVALID(S_AXI_HP2_RVALID),
+        .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
+        .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
+        .SAXIHP2WDATA(S_AXI_HP2_WDATA),
+        .SAXIHP2WID(S_AXI_HP2_WID),
+        .SAXIHP2WLAST(S_AXI_HP2_WLAST),
+        .SAXIHP2WREADY(S_AXI_HP2_WREADY),
+        .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
+        .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
+        .SAXIHP2WVALID(S_AXI_HP2_WVALID),
+        .SAXIHP3ACLK(S_AXI_HP3_ACLK),
+        .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
+        .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
+        .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
+        .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
+        .SAXIHP3ARID(S_AXI_HP3_ARID),
+        .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
+        .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
+        .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
+        .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
+        .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
+        .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
+        .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
+        .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
+        .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
+        .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
+        .SAXIHP3AWID(S_AXI_HP3_AWID),
+        .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
+        .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
+        .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
+        .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
+        .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
+        .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
+        .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
+        .SAXIHP3BID(S_AXI_HP3_BID),
+        .SAXIHP3BREADY(S_AXI_HP3_BREADY),
+        .SAXIHP3BRESP(S_AXI_HP3_BRESP),
+        .SAXIHP3BVALID(S_AXI_HP3_BVALID),
+        .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
+        .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
+        .SAXIHP3RDATA(S_AXI_HP3_RDATA),
+        .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
+        .SAXIHP3RID(S_AXI_HP3_RID),
+        .SAXIHP3RLAST(S_AXI_HP3_RLAST),
+        .SAXIHP3RREADY(S_AXI_HP3_RREADY),
+        .SAXIHP3RRESP(S_AXI_HP3_RRESP),
+        .SAXIHP3RVALID(S_AXI_HP3_RVALID),
+        .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
+        .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
+        .SAXIHP3WDATA(S_AXI_HP3_WDATA),
+        .SAXIHP3WID(S_AXI_HP3_WID),
+        .SAXIHP3WLAST(S_AXI_HP3_WLAST),
+        .SAXIHP3WREADY(S_AXI_HP3_WREADY),
+        .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
+        .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
+        .SAXIHP3WVALID(S_AXI_HP3_WVALID));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_CLK_BIBUF
+       (.IO(buffered_PS_CLK),
+        .PAD(PS_CLK));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_PORB_BIBUF
+       (.IO(buffered_PS_PORB),
+        .PAD(PS_PORB));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF PS_SRSTB_BIBUF
+       (.IO(buffered_PS_SRSTB),
+        .PAD(PS_SRSTB));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO0_CMD_T_INST_0
+       (.I0(SDIO0_CMD_T_n),
+        .O(SDIO0_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[0]_INST_0 
+       (.I0(SDIO0_DATA_T_n[0]),
+        .O(SDIO0_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[1]_INST_0 
+       (.I0(SDIO0_DATA_T_n[1]),
+        .O(SDIO0_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[2]_INST_0 
+       (.I0(SDIO0_DATA_T_n[2]),
+        .O(SDIO0_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO0_DATA_T[3]_INST_0 
+       (.I0(SDIO0_DATA_T_n[3]),
+        .O(SDIO0_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SDIO1_CMD_T_INST_0
+       (.I0(SDIO1_CMD_T_n),
+        .O(SDIO1_CMD_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[0]_INST_0 
+       (.I0(SDIO1_DATA_T_n[0]),
+        .O(SDIO1_DATA_T[0]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[1]_INST_0 
+       (.I0(SDIO1_DATA_T_n[1]),
+        .O(SDIO1_DATA_T[1]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[2]_INST_0 
+       (.I0(SDIO1_DATA_T_n[2]),
+        .O(SDIO1_DATA_T[2]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\SDIO1_DATA_T[3]_INST_0 
+       (.I0(SDIO1_DATA_T_n[3]),
+        .O(SDIO1_DATA_T[3]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MISO_T_INST_0
+       (.I0(SPI0_MISO_T_n),
+        .O(SPI0_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_MOSI_T_INST_0
+       (.I0(SPI0_MOSI_T_n),
+        .O(SPI0_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SCLK_T_INST_0
+       (.I0(SPI0_SCLK_T_n),
+        .O(SPI0_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI0_SS_T_INST_0
+       (.I0(SPI0_SS_T_n),
+        .O(SPI0_SS_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MISO_T_INST_0
+       (.I0(SPI1_MISO_T_n),
+        .O(SPI1_MISO_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_MOSI_T_INST_0
+       (.I0(SPI1_MOSI_T_n),
+        .O(SPI1_MOSI_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SCLK_T_INST_0
+       (.I0(SPI1_SCLK_T_n),
+        .O(SPI1_SCLK_T));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    SPI1_SS_T_INST_0
+       (.I0(SPI1_SS_T_n),
+        .O(SPI1_SS_T));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BUFG \\buffer_fclk_clk_0.FCLK_CLK_0_BUFG 
+       (.I(FCLK_CLK_unbuffered),
+        .O(FCLK_CLK0));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[0].MIO_BIBUF 
+       (.IO(buffered_MIO[0]),
+        .PAD(MIO[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[10].MIO_BIBUF 
+       (.IO(buffered_MIO[10]),
+        .PAD(MIO[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[11].MIO_BIBUF 
+       (.IO(buffered_MIO[11]),
+        .PAD(MIO[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[12].MIO_BIBUF 
+       (.IO(buffered_MIO[12]),
+        .PAD(MIO[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[13].MIO_BIBUF 
+       (.IO(buffered_MIO[13]),
+        .PAD(MIO[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[14].MIO_BIBUF 
+       (.IO(buffered_MIO[14]),
+        .PAD(MIO[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[15].MIO_BIBUF 
+       (.IO(buffered_MIO[15]),
+        .PAD(MIO[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[16].MIO_BIBUF 
+       (.IO(buffered_MIO[16]),
+        .PAD(MIO[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[17].MIO_BIBUF 
+       (.IO(buffered_MIO[17]),
+        .PAD(MIO[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[18].MIO_BIBUF 
+       (.IO(buffered_MIO[18]),
+        .PAD(MIO[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[19].MIO_BIBUF 
+       (.IO(buffered_MIO[19]),
+        .PAD(MIO[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[1].MIO_BIBUF 
+       (.IO(buffered_MIO[1]),
+        .PAD(MIO[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[20].MIO_BIBUF 
+       (.IO(buffered_MIO[20]),
+        .PAD(MIO[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[21].MIO_BIBUF 
+       (.IO(buffered_MIO[21]),
+        .PAD(MIO[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[22].MIO_BIBUF 
+       (.IO(buffered_MIO[22]),
+        .PAD(MIO[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[23].MIO_BIBUF 
+       (.IO(buffered_MIO[23]),
+        .PAD(MIO[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[24].MIO_BIBUF 
+       (.IO(buffered_MIO[24]),
+        .PAD(MIO[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[25].MIO_BIBUF 
+       (.IO(buffered_MIO[25]),
+        .PAD(MIO[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[26].MIO_BIBUF 
+       (.IO(buffered_MIO[26]),
+        .PAD(MIO[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[27].MIO_BIBUF 
+       (.IO(buffered_MIO[27]),
+        .PAD(MIO[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[28].MIO_BIBUF 
+       (.IO(buffered_MIO[28]),
+        .PAD(MIO[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[29].MIO_BIBUF 
+       (.IO(buffered_MIO[29]),
+        .PAD(MIO[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[2].MIO_BIBUF 
+       (.IO(buffered_MIO[2]),
+        .PAD(MIO[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[30].MIO_BIBUF 
+       (.IO(buffered_MIO[30]),
+        .PAD(MIO[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[31].MIO_BIBUF 
+       (.IO(buffered_MIO[31]),
+        .PAD(MIO[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[32].MIO_BIBUF 
+       (.IO(buffered_MIO[32]),
+        .PAD(MIO[32]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[33].MIO_BIBUF 
+       (.IO(buffered_MIO[33]),
+        .PAD(MIO[33]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[34].MIO_BIBUF 
+       (.IO(buffered_MIO[34]),
+        .PAD(MIO[34]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[35].MIO_BIBUF 
+       (.IO(buffered_MIO[35]),
+        .PAD(MIO[35]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[36].MIO_BIBUF 
+       (.IO(buffered_MIO[36]),
+        .PAD(MIO[36]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[37].MIO_BIBUF 
+       (.IO(buffered_MIO[37]),
+        .PAD(MIO[37]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[38].MIO_BIBUF 
+       (.IO(buffered_MIO[38]),
+        .PAD(MIO[38]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[39].MIO_BIBUF 
+       (.IO(buffered_MIO[39]),
+        .PAD(MIO[39]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[3].MIO_BIBUF 
+       (.IO(buffered_MIO[3]),
+        .PAD(MIO[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[40].MIO_BIBUF 
+       (.IO(buffered_MIO[40]),
+        .PAD(MIO[40]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[41].MIO_BIBUF 
+       (.IO(buffered_MIO[41]),
+        .PAD(MIO[41]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[42].MIO_BIBUF 
+       (.IO(buffered_MIO[42]),
+        .PAD(MIO[42]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[43].MIO_BIBUF 
+       (.IO(buffered_MIO[43]),
+        .PAD(MIO[43]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[44].MIO_BIBUF 
+       (.IO(buffered_MIO[44]),
+        .PAD(MIO[44]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[45].MIO_BIBUF 
+       (.IO(buffered_MIO[45]),
+        .PAD(MIO[45]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[46].MIO_BIBUF 
+       (.IO(buffered_MIO[46]),
+        .PAD(MIO[46]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[47].MIO_BIBUF 
+       (.IO(buffered_MIO[47]),
+        .PAD(MIO[47]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[48].MIO_BIBUF 
+       (.IO(buffered_MIO[48]),
+        .PAD(MIO[48]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[49].MIO_BIBUF 
+       (.IO(buffered_MIO[49]),
+        .PAD(MIO[49]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[4].MIO_BIBUF 
+       (.IO(buffered_MIO[4]),
+        .PAD(MIO[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[50].MIO_BIBUF 
+       (.IO(buffered_MIO[50]),
+        .PAD(MIO[50]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[51].MIO_BIBUF 
+       (.IO(buffered_MIO[51]),
+        .PAD(MIO[51]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[52].MIO_BIBUF 
+       (.IO(buffered_MIO[52]),
+        .PAD(MIO[52]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[53].MIO_BIBUF 
+       (.IO(buffered_MIO[53]),
+        .PAD(MIO[53]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[5].MIO_BIBUF 
+       (.IO(buffered_MIO[5]),
+        .PAD(MIO[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[6].MIO_BIBUF 
+       (.IO(buffered_MIO[6]),
+        .PAD(MIO[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[7].MIO_BIBUF 
+       (.IO(buffered_MIO[7]),
+        .PAD(MIO[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[8].MIO_BIBUF 
+       (.IO(buffered_MIO[8]),
+        .PAD(MIO[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk13[9].MIO_BIBUF 
+       (.IO(buffered_MIO[9]),
+        .PAD(MIO[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[0].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[0]),
+        .PAD(DDR_BankAddr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[1].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[1]),
+        .PAD(DDR_BankAddr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk14[2].DDR_BankAddr_BIBUF 
+       (.IO(buffered_DDR_BankAddr[2]),
+        .PAD(DDR_BankAddr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[0].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[0]),
+        .PAD(DDR_Addr[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[10].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[10]),
+        .PAD(DDR_Addr[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[11].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[11]),
+        .PAD(DDR_Addr[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[12].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[12]),
+        .PAD(DDR_Addr[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[13].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[13]),
+        .PAD(DDR_Addr[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[14].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[14]),
+        .PAD(DDR_Addr[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[1].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[1]),
+        .PAD(DDR_Addr[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[2].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[2]),
+        .PAD(DDR_Addr[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[3].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[3]),
+        .PAD(DDR_Addr[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[4].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[4]),
+        .PAD(DDR_Addr[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[5].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[5]),
+        .PAD(DDR_Addr[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[6].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[6]),
+        .PAD(DDR_Addr[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[7].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[7]),
+        .PAD(DDR_Addr[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[8].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[8]),
+        .PAD(DDR_Addr[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk15[9].DDR_Addr_BIBUF 
+       (.IO(buffered_DDR_Addr[9]),
+        .PAD(DDR_Addr[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[0].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[0]),
+        .PAD(DDR_DM[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[1].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[1]),
+        .PAD(DDR_DM[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[2].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[2]),
+        .PAD(DDR_DM[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk16[3].DDR_DM_BIBUF 
+       (.IO(buffered_DDR_DM[3]),
+        .PAD(DDR_DM[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[0].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[0]),
+        .PAD(DDR_DQ[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[10].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[10]),
+        .PAD(DDR_DQ[10]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[11].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[11]),
+        .PAD(DDR_DQ[11]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[12].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[12]),
+        .PAD(DDR_DQ[12]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[13].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[13]),
+        .PAD(DDR_DQ[13]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[14].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[14]),
+        .PAD(DDR_DQ[14]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[15].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[15]),
+        .PAD(DDR_DQ[15]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[16].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[16]),
+        .PAD(DDR_DQ[16]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[17].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[17]),
+        .PAD(DDR_DQ[17]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[18].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[18]),
+        .PAD(DDR_DQ[18]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[19].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[19]),
+        .PAD(DDR_DQ[19]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[1].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[1]),
+        .PAD(DDR_DQ[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[20].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[20]),
+        .PAD(DDR_DQ[20]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[21].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[21]),
+        .PAD(DDR_DQ[21]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[22].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[22]),
+        .PAD(DDR_DQ[22]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[23].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[23]),
+        .PAD(DDR_DQ[23]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[24].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[24]),
+        .PAD(DDR_DQ[24]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[25].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[25]),
+        .PAD(DDR_DQ[25]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[26].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[26]),
+        .PAD(DDR_DQ[26]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[27].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[27]),
+        .PAD(DDR_DQ[27]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[28].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[28]),
+        .PAD(DDR_DQ[28]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[29].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[29]),
+        .PAD(DDR_DQ[29]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[2].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[2]),
+        .PAD(DDR_DQ[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[30].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[30]),
+        .PAD(DDR_DQ[30]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[31].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[31]),
+        .PAD(DDR_DQ[31]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[3].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[3]),
+        .PAD(DDR_DQ[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[4].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[4]),
+        .PAD(DDR_DQ[4]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[5].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[5]),
+        .PAD(DDR_DQ[5]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[6].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[6]),
+        .PAD(DDR_DQ[6]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[7].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[7]),
+        .PAD(DDR_DQ[7]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[8].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[8]),
+        .PAD(DDR_DQ[8]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk17[9].DDR_DQ_BIBUF 
+       (.IO(buffered_DDR_DQ[9]),
+        .PAD(DDR_DQ[9]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[0].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[0]),
+        .PAD(DDR_DQS_n[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[1].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[1]),
+        .PAD(DDR_DQS_n[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[2].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[2]),
+        .PAD(DDR_DQS_n[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk18[3].DDR_DQS_n_BIBUF 
+       (.IO(buffered_DDR_DQS_n[3]),
+        .PAD(DDR_DQS_n[3]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[0].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[0]),
+        .PAD(DDR_DQS[0]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[1].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[1]),
+        .PAD(DDR_DQS[1]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[2].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[2]),
+        .PAD(DDR_DQS[2]));
+  (* BOX_TYPE = ""PRIMITIVE"" *) 
+  BIBUF \\genblk19[3].DDR_DQS_BIBUF 
+       (.IO(buffered_DDR_DQS[3]),
+        .PAD(DDR_DQS[3]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_0
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[0] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_1
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_10
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_11
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[7] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_12
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_13
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[6] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_14
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_15
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[5] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_16
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_17
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[4] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_18
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_19
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[3] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_2
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[0] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_20
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_21
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[2] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_22
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [1]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_23
+       (.I0(1\'b0),
+        .O(\\TRACE_DATA_PIPE[1] [0]));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_3
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[7] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_4
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[6] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_5
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[5] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_6
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[4] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_7
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[3] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_8
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[2] ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    i_9
+       (.I0(1\'b0),
+        .O(\\TRACE_CTL_PIPE[1] ));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:57:55 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_auto_pc_0_sim_netlist.v
+// Design      : design_1_auto_pc_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* C_AXI_ADDR_WIDTH = ""32"" *) (* C_AXI_ARUSER_WIDTH = ""1"" *) (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+(* C_AXI_BUSER_WIDTH = ""1"" *) (* C_AXI_DATA_WIDTH = ""32"" *) (* C_AXI_ID_WIDTH = ""12"" *) 
+(* C_AXI_RUSER_WIDTH = ""1"" *) (* C_AXI_SUPPORTS_READ = ""1"" *) (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+(* C_AXI_SUPPORTS_WRITE = ""1"" *) (* C_AXI_WUSER_WIDTH = ""1"" *) (* C_FAMILY = ""zynq"" *) 
+(* C_IGNORE_ID = ""0"" *) (* C_M_AXI_PROTOCOL = ""2"" *) (* C_S_AXI_PROTOCOL = ""1"" *) 
+(* C_TRANSLATION_MODE = ""2"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* P_AXI3 = ""1"" *) 
+(* P_AXI4 = ""0"" *) (* P_AXILITE = ""2"" *) (* P_AXILITE_SIZE = ""3\'b010"" *) 
+(* P_CONVERSION = ""2"" *) (* P_DECERR = ""2\'b11"" *) (* P_INCR = ""2\'b01"" *) 
+(* P_PROTECTION = ""1"" *) (* P_SLVERR = ""2\'b10"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_axi_protocol_converter
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awregion,
+    s_axi_awqos,
+    s_axi_awuser,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wuser,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_buser,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arregion,
+    s_axi_arqos,
+    s_axi_aruser,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_ruser,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awid,
+    m_axi_awaddr,
+    m_axi_awlen,
+    m_axi_awsize,
+    m_axi_awburst,
+    m_axi_awlock,
+    m_axi_awcache,
+    m_axi_awprot,
+    m_axi_awregion,
+    m_axi_awqos,
+    m_axi_awuser,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wid,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wlast,
+    m_axi_wuser,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bid,
+    m_axi_bresp,
+    m_axi_buser,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_arid,
+    m_axi_araddr,
+    m_axi_arlen,
+    m_axi_arsize,
+    m_axi_arburst,
+    m_axi_arlock,
+    m_axi_arcache,
+    m_axi_arprot,
+    m_axi_arregion,
+    m_axi_arqos,
+    m_axi_aruser,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rlast,
+    m_axi_ruser,
+    m_axi_rvalid,
+    m_axi_rready);
+  input aclk;
+  input aresetn;
+  input [11:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [3:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awregion;
+  input [3:0]s_axi_awqos;
+  input [0:0]s_axi_awuser;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [11:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wlast;
+  input [0:0]s_axi_wuser;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [11:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_buser;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [11:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [3:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arregion;
+  input [3:0]s_axi_arqos;
+  input [0:0]s_axi_aruser;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [11:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rlast;
+  output [0:0]s_axi_ruser;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output [11:0]m_axi_awid;
+  output [31:0]m_axi_awaddr;
+  output [7:0]m_axi_awlen;
+  output [2:0]m_axi_awsize;
+  output [1:0]m_axi_awburst;
+  output [0:0]m_axi_awlock;
+  output [3:0]m_axi_awcache;
+  output [2:0]m_axi_awprot;
+  output [3:0]m_axi_awregion;
+  output [3:0]m_axi_awqos;
+  output [0:0]m_axi_awuser;
+  output m_axi_awvalid;
+  input m_axi_awready;
+  output [11:0]m_axi_wid;
+  output [31:0]m_axi_wdata;
+  output [3:0]m_axi_wstrb;
+  output m_axi_wlast;
+  output [0:0]m_axi_wuser;
+  output m_axi_wvalid;
+  input m_axi_wready;
+  input [11:0]m_axi_bid;
+  input [1:0]m_axi_bresp;
+  input [0:0]m_axi_buser;
+  input m_axi_bvalid;
+  output m_axi_bready;
+  output [11:0]m_axi_arid;
+  output [31:0]m_axi_araddr;
+  output [7:0]m_axi_arlen;
+  output [2:0]m_axi_arsize;
+  output [1:0]m_axi_arburst;
+  output [0:0]m_axi_arlock;
+  output [3:0]m_axi_arcache;
+  output [2:0]m_axi_arprot;
+  output [3:0]m_axi_arregion;
+  output [3:0]m_axi_arqos;
+  output [0:0]m_axi_aruser;
+  output m_axi_arvalid;
+  input m_axi_arready;
+  input [11:0]m_axi_rid;
+  input [31:0]m_axi_rdata;
+  input [1:0]m_axi_rresp;
+  input m_axi_rlast;
+  input [0:0]m_axi_ruser;
+  input m_axi_rvalid;
+  output m_axi_rready;
+
+  wire \\<const0> ;
+  wire \\<const1> ;
+  wire aclk;
+  wire aresetn;
+  wire [31:0]m_axi_araddr;
+  wire [2:0]m_axi_arprot;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire [31:0]m_axi_awaddr;
+  wire [2:0]m_axi_awprot;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire m_axi_bready;
+  wire [1:0]m_axi_bresp;
+  wire m_axi_bvalid;
+  wire [31:0]m_axi_rdata;
+  wire m_axi_rready;
+  wire [1:0]m_axi_rresp;
+  wire m_axi_rvalid;
+  wire m_axi_wready;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [2:0]s_axi_arprot;
+  wire s_axi_arready;
+  wire [2:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [2:0]s_axi_awprot;
+  wire s_axi_awready;
+  wire [2:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire [11:0]s_axi_bid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [11:0]s_axi_rid;
+  wire s_axi_rlast;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+
+  assign m_axi_arburst[1] = \\<const0> ;
+  assign m_axi_arburst[0] = \\<const1> ;
+  assign m_axi_arcache[3] = \\<const0> ;
+  assign m_axi_arcache[2] = \\<const0> ;
+  assign m_axi_arcache[1] = \\<const0> ;
+  assign m_axi_arcache[0] = \\<const0> ;
+  assign m_axi_arid[11] = \\<const0> ;
+  assign m_axi_arid[10] = \\<const0> ;
+  assign m_axi_arid[9] = \\<const0> ;
+  assign m_axi_arid[8] = \\<const0> ;
+  assign m_axi_arid[7] = \\<const0> ;
+  assign m_axi_arid[6] = \\<const0> ;
+  assign m_axi_arid[5] = \\<const0> ;
+  assign m_axi_arid[4] = \\<const0> ;
+  assign m_axi_arid[3] = \\<const0> ;
+  assign m_axi_arid[2] = \\<const0> ;
+  assign m_axi_arid[1] = \\<const0> ;
+  assign m_axi_arid[0] = \\<const0> ;
+  assign m_axi_arlen[7] = \\<const0> ;
+  assign m_axi_arlen[6] = \\<const0> ;
+  assign m_axi_arlen[5] = \\<const0> ;
+  assign m_axi_arlen[4] = \\<const0> ;
+  assign m_axi_arlen[3] = \\<const0> ;
+  assign m_axi_arlen[2] = \\<const0> ;
+  assign m_axi_arlen[1] = \\<const0> ;
+  assign m_axi_arlen[0] = \\<const0> ;
+  assign m_axi_arlock[0] = \\<const0> ;
+  assign m_axi_arqos[3] = \\<const0> ;
+  assign m_axi_arqos[2] = \\<const0> ;
+  assign m_axi_arqos[1] = \\<const0> ;
+  assign m_axi_arqos[0] = \\<const0> ;
+  assign m_axi_arregion[3] = \\<const0> ;
+  assign m_axi_arregion[2] = \\<const0> ;
+  assign m_axi_arregion[1] = \\<const0> ;
+  assign m_axi_arregion[0] = \\<const0> ;
+  assign m_axi_arsize[2] = \\<const0> ;
+  assign m_axi_arsize[1] = \\<const1> ;
+  assign m_axi_arsize[0] = \\<const0> ;
+  assign m_axi_aruser[0] = \\<const0> ;
+  assign m_axi_awburst[1] = \\<const0> ;
+  assign m_axi_awburst[0] = \\<const1> ;
+  assign m_axi_awcache[3] = \\<const0> ;
+  assign m_axi_awcache[2] = \\<const0> ;
+  assign m_axi_awcache[1] = \\<const0> ;
+  assign m_axi_awcache[0] = \\<const0> ;
+  assign m_axi_awid[11] = \\<const0> ;
+  assign m_axi_awid[10] = \\<const0> ;
+  assign m_axi_awid[9] = \\<const0> ;
+  assign m_axi_awid[8] = \\<const0> ;
+  assign m_axi_awid[7] = \\<const0> ;
+  assign m_axi_awid[6] = \\<const0> ;
+  assign m_axi_awid[5] = \\<const0> ;
+  assign m_axi_awid[4] = \\<const0> ;
+  assign m_axi_awid[3] = \\<const0> ;
+  assign m_axi_awid[2] = \\<const0> ;
+  assign m_axi_awid[1] = \\<const0> ;
+  assign m_axi_awid[0] = \\<const0> ;
+  assign m_axi_awlen[7] = \\<const0> ;
+  assign m_axi_awlen[6] = \\<const0> ;
+  assign m_axi_awlen[5] = \\<const0> ;
+  assign m_axi_awlen[4] = \\<const0> ;
+  assign m_axi_awlen[3] = \\<const0> ;
+  assign m_axi_awlen[2] = \\<const0> ;
+  assign m_axi_awlen[1] = \\<const0> ;
+  assign m_axi_awlen[0] = \\<const0> ;
+  assign m_axi_awlock[0] = \\<const0> ;
+  assign m_axi_awqos[3] = \\<const0> ;
+  assign m_axi_awqos[2] = \\<const0> ;
+  assign m_axi_awqos[1] = \\<const0> ;
+  assign m_axi_awqos[0] = \\<const0> ;
+  assign m_axi_awregion[3] = \\<const0> ;
+  assign m_axi_awregion[2] = \\<const0> ;
+  assign m_axi_awregion[1] = \\<const0> ;
+  assign m_axi_awregion[0] = \\<const0> ;
+  assign m_axi_awsize[2] = \\<const0> ;
+  assign m_axi_awsize[1] = \\<const1> ;
+  assign m_axi_awsize[0] = \\<const0> ;
+  assign m_axi_awuser[0] = \\<const0> ;
+  assign m_axi_wdata[31:0] = s_axi_wdata;
+  assign m_axi_wid[11] = \\<const0> ;
+  assign m_axi_wid[10] = \\<const0> ;
+  assign m_axi_wid[9] = \\<const0> ;
+  assign m_axi_wid[8] = \\<const0> ;
+  assign m_axi_wid[7] = \\<const0> ;
+  assign m_axi_wid[6] = \\<const0> ;
+  assign m_axi_wid[5] = \\<const0> ;
+  assign m_axi_wid[4] = \\<const0> ;
+  assign m_axi_wid[3] = \\<const0> ;
+  assign m_axi_wid[2] = \\<const0> ;
+  assign m_axi_wid[1] = \\<const0> ;
+  assign m_axi_wid[0] = \\<const0> ;
+  assign m_axi_wlast = \\<const1> ;
+  assign m_axi_wstrb[3:0] = s_axi_wstrb;
+  assign m_axi_wuser[0] = \\<const0> ;
+  assign m_axi_wvalid = s_axi_wvalid;
+  assign s_axi_buser[0] = \\<const0> ;
+  assign s_axi_ruser[0] = \\<const0> ;
+  assign s_axi_wready = m_axi_wready;
+  GND GND
+       (.G(\\<const0> ));
+  VCC VCC
+       (.P(\\<const1> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s \\gen_axilite.gen_b2s_conv.axilite_b2s 
+       (.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .in({m_axi_rresp,m_axi_rdata}),
+        .m_axi_araddr(m_axi_araddr[11:0]),
+        .\\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr[11:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rvalid(m_axi_rvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize(s_axi_arsize[1:0]),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize(s_axi_awsize[1:0]),
+        .s_axi_awvalid(s_axi_awvalid),
+        .\\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s
+   (s_axi_rvalid,
+    s_axi_awready,
+    Q,
+    s_axi_arready,
+    \\m_axi_arprot[2] ,
+    s_axi_bvalid,
+    \\s_axi_bid[11] ,
+    \\s_axi_rid[11] ,
+    m_axi_awvalid,
+    m_axi_bready,
+    m_axi_arvalid,
+    m_axi_rready,
+    m_axi_awaddr,
+    m_axi_araddr,
+    m_axi_arready,
+    s_axi_rready,
+    aclk,
+    in,
+    s_axi_awid,
+    s_axi_awlen,
+    s_axi_awburst,
+    s_axi_awsize,
+    s_axi_awprot,
+    s_axi_awaddr,
+    m_axi_bresp,
+    s_axi_arid,
+    s_axi_arlen,
+    s_axi_arburst,
+    s_axi_arsize,
+    s_axi_arprot,
+    s_axi_araddr,
+    m_axi_awready,
+    s_axi_awvalid,
+    m_axi_bvalid,
+    m_axi_rvalid,
+    s_axi_bready,
+    s_axi_arvalid,
+    aresetn);
+  output s_axi_rvalid;
+  output s_axi_awready;
+  output [22:0]Q;
+  output s_axi_arready;
+  output [22:0]\\m_axi_arprot[2] ;
+  output s_axi_bvalid;
+  output [13:0]\\s_axi_bid[11] ;
+  output [46:0]\\s_axi_rid[11] ;
+  output m_axi_awvalid;
+  output m_axi_bready;
+  output m_axi_arvalid;
+  output m_axi_rready;
+  output [11:0]m_axi_awaddr;
+  output [11:0]m_axi_araddr;
+  input m_axi_arready;
+  input s_axi_rready;
+  input aclk;
+  input [33:0]in;
+  input [11:0]s_axi_awid;
+  input [3:0]s_axi_awlen;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awsize;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_awaddr;
+  input [1:0]m_axi_bresp;
+  input [11:0]s_axi_arid;
+  input [3:0]s_axi_arlen;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arsize;
+  input [2:0]s_axi_arprot;
+  input [31:0]s_axi_araddr;
+  input m_axi_awready;
+  input s_axi_awvalid;
+  input m_axi_bvalid;
+  input m_axi_rvalid;
+  input s_axi_bready;
+  input s_axi_arvalid;
+  input aresetn;
+
+  wire [11:4]C;
+  wire [22:0]Q;
+  wire \\RD.ar_channel_0_n_14 ;
+  wire \\RD.ar_channel_0_n_15 ;
+  wire \\RD.ar_channel_0_n_44 ;
+  wire \\RD.ar_channel_0_n_45 ;
+  wire \\RD.ar_channel_0_n_46 ;
+  wire \\RD.ar_channel_0_n_47 ;
+  wire \\RD.ar_channel_0_n_5 ;
+  wire \\RD.r_channel_0_n_0 ;
+  wire \\RD.r_channel_0_n_1 ;
+  wire SI_REG_n_10;
+  wire SI_REG_n_132;
+  wire SI_REG_n_133;
+  wire SI_REG_n_134;
+  wire SI_REG_n_135;
+  wire SI_REG_n_136;
+  wire SI_REG_n_137;
+  wire SI_REG_n_138;
+  wire SI_REG_n_139;
+  wire SI_REG_n_140;
+  wire SI_REG_n_141;
+  wire SI_REG_n_142;
+  wire SI_REG_n_143;
+  wire SI_REG_n_144;
+  wire SI_REG_n_145;
+  wire SI_REG_n_146;
+  wire SI_REG_n_147;
+  wire SI_REG_n_148;
+  wire SI_REG_n_149;
+  wire SI_REG_n_154;
+  wire SI_REG_n_155;
+  wire SI_REG_n_157;
+  wire SI_REG_n_160;
+  wire SI_REG_n_164;
+  wire SI_REG_n_165;
+  wire SI_REG_n_166;
+  wire SI_REG_n_167;
+  wire SI_REG_n_168;
+  wire SI_REG_n_169;
+  wire SI_REG_n_170;
+  wire SI_REG_n_171;
+  wire SI_REG_n_172;
+  wire SI_REG_n_173;
+  wire SI_REG_n_174;
+  wire SI_REG_n_175;
+  wire SI_REG_n_176;
+  wire SI_REG_n_177;
+  wire SI_REG_n_178;
+  wire SI_REG_n_179;
+  wire SI_REG_n_180;
+  wire SI_REG_n_181;
+  wire SI_REG_n_182;
+  wire SI_REG_n_183;
+  wire SI_REG_n_184;
+  wire \\WR.aw_channel_0_n_47 ;
+  wire \\WR.aw_channel_0_n_48 ;
+  wire \\WR.aw_channel_0_n_49 ;
+  wire \\WR.aw_channel_0_n_50 ;
+  wire \\WR.aw_channel_0_n_7 ;
+  wire \\WR.b_channel_0_n_1 ;
+  wire \\WR.b_channel_0_n_2 ;
+  wire \\WR.b_channel_0_n_3 ;
+  wire aclk;
+  wire \\ar_pipe/m_valid_i0 ;
+  wire \\ar_pipe/p_1_in ;
+  wire areset_d1;
+  wire areset_d1_i_1_n_0;
+  wire aresetn;
+  wire [1:0]\\aw_cmd_fsm_0/state ;
+  wire \\aw_pipe/p_1_in ;
+  wire [11:0]b_awid;
+  wire [3:0]b_awlen;
+  wire b_push;
+  wire [3:0]\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ;
+  wire [3:0]\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ;
+  wire \\cmd_translator_0/incr_cmd_0/sel_first ;
+  wire \\cmd_translator_0/incr_cmd_0/sel_first_4 ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
+  wire [3:1]\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ;
+  wire [2:1]\\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
+  wire [2:0]\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
+  wire [3:0]\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ;
+  wire [33:0]in;
+  wire [11:0]m_axi_araddr;
+  wire [22:0]\\m_axi_arprot[2] ;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire [11:0]m_axi_awaddr;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire m_axi_bready;
+  wire [1:0]m_axi_bresp;
+  wire m_axi_bvalid;
+  wire m_axi_rready;
+  wire m_axi_rvalid;
+  wire r_push;
+  wire r_rlast;
+  wire [11:0]s_arid;
+  wire [11:0]s_arid_r;
+  wire [11:0]s_awid;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [2:0]s_axi_arprot;
+  wire s_axi_arready;
+  wire [1:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [2:0]s_axi_awprot;
+  wire s_axi_awready;
+  wire [1:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire [13:0]\\s_axi_bid[11] ;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [46:0]\\s_axi_rid[11] ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire shandshake;
+  wire [11:0]si_rs_araddr;
+  wire [1:1]si_rs_arburst;
+  wire [3:0]si_rs_arlen;
+  wire [1:0]si_rs_arsize;
+  wire si_rs_arvalid;
+  wire [11:0]si_rs_awaddr;
+  wire [1:1]si_rs_awburst;
+  wire [3:0]si_rs_awlen;
+  wire [1:0]si_rs_awsize;
+  wire si_rs_awvalid;
+  wire [11:0]si_rs_bid;
+  wire si_rs_bready;
+  wire [1:0]si_rs_bresp;
+  wire si_rs_bvalid;
+  wire [31:0]si_rs_rdata;
+  wire [11:0]si_rs_rid;
+  wire si_rs_rlast;
+  wire si_rs_rready;
+  wire [1:0]si_rs_rresp;
+  wire [3:0]wrap_cnt;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_ar_channel \\RD.ar_channel_0 
+       (.CO(SI_REG_n_145),
+        .D(\\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
+        .E(\\ar_pipe/p_1_in ),
+        .O({SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149}),
+        .Q(\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
+        .S({\\RD.ar_channel_0_n_44 ,\\RD.ar_channel_0_n_45 ,\\RD.ar_channel_0_n_46 ,\\RD.ar_channel_0_n_47 }),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\axaddr_incr_reg[3] (\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
+        .axaddr_offset(\\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
+        .\\axaddr_offset_r_reg[3] (\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
+        .\\axaddr_offset_r_reg[3]_0 (SI_REG_n_160),
+        .\\cnt_read_reg[1]_rep__0 (\\RD.r_channel_0_n_1 ),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .\\m_payload_i_reg[0] (\\RD.ar_channel_0_n_14 ),
+        .\\m_payload_i_reg[0]_0 (\\RD.ar_channel_0_n_15 ),
+        .\\m_payload_i_reg[11] ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
+        .\\m_payload_i_reg[35] (SI_REG_n_164),
+        .\\m_payload_i_reg[35]_0 (SI_REG_n_165),
+        .\\m_payload_i_reg[38] (SI_REG_n_184),
+        .\\m_payload_i_reg[3] (SI_REG_n_175),
+        .\\m_payload_i_reg[3]_0 ({SI_REG_n_137,SI_REG_n_138,SI_REG_n_139,SI_REG_n_140}),
+        .\\m_payload_i_reg[44] (SI_REG_n_166),
+        .\\m_payload_i_reg[47] (SI_REG_n_167),
+        .\\m_payload_i_reg[47]_0 (\\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
+        .\\m_payload_i_reg[61] ({s_arid,si_rs_arlen,si_rs_arburst,si_rs_arsize,si_rs_araddr}),
+        .\\m_payload_i_reg[6] ({SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174}),
+        .m_valid_i0(\\ar_pipe/m_valid_i0 ),
+        .\\r_arid_r_reg[11] (s_arid_r),
+        .r_push(r_push),
+        .r_rlast(r_rlast),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_ready_i_reg(s_axi_arready),
+        .sel_first(\\cmd_translator_0/incr_cmd_0/sel_first ),
+        .si_rs_arvalid(si_rs_arvalid),
+        .\\wrap_boundary_axaddr_r_reg[11] (\\RD.ar_channel_0_n_5 ),
+        .\\wrap_second_len_r_reg[0] (SI_REG_n_157));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_r_channel \\RD.r_channel_0 
+       (.D(s_arid_r),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .in(in),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_valid_i_reg(\\RD.r_channel_0_n_0 ),
+        .out({si_rs_rresp,si_rs_rdata}),
+        .r_push(r_push),
+        .r_rlast(r_rlast),
+        .si_rs_rready(si_rs_rready),
+        .\\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
+        .\\state_reg[1]_rep (\\RD.r_channel_0_n_1 ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axi_register_slice SI_REG
+       (.CO(SI_REG_n_132),
+        .D({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}),
+        .E(\\aw_pipe/p_1_in ),
+        .O({SI_REG_n_133,SI_REG_n_134,SI_REG_n_135,SI_REG_n_136}),
+        .Q({s_awid,si_rs_awlen,si_rs_awburst,si_rs_awsize,Q,si_rs_awaddr}),
+        .S({\\WR.aw_channel_0_n_47 ,\\WR.aw_channel_0_n_48 ,\\WR.aw_channel_0_n_49 ,\\WR.aw_channel_0_n_50 }),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .axaddr_incr_reg(\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
+        .\\axaddr_incr_reg[11] (C),
+        .\\axaddr_incr_reg[11]_0 ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
+        .\\axaddr_incr_reg[3] ({SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149}),
+        .\\axaddr_incr_reg[3]_0 (\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
+        .\\axaddr_incr_reg[7] ({SI_REG_n_137,SI_REG_n_138,SI_REG_n_139,SI_REG_n_140}),
+        .\\axaddr_incr_reg[7]_0 (SI_REG_n_145),
+        .axaddr_offset(\\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
+        .axaddr_offset_0(\\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
+        .\\axaddr_offset_r_reg[0] (SI_REG_n_175),
+        .\\axaddr_offset_r_reg[1] (SI_REG_n_164),
+        .\\axaddr_offset_r_reg[3] (\\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
+        .\\axaddr_offset_r_reg[3]_0 (\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
+        .\\axaddr_offset_r_reg[3]_1 (\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
+        .\\axlen_cnt_reg[3] (SI_REG_n_154),
+        .\\axlen_cnt_reg[3]_0 (SI_REG_n_167),
+        .b_push(b_push),
+        .\\cnt_read_reg[3]_rep__2 (\\RD.r_channel_0_n_0 ),
+        .\\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
+        .\\m_axi_araddr[10] (SI_REG_n_184),
+        .\\m_axi_awaddr[10] (SI_REG_n_183),
+        .\\m_payload_i_reg[3] ({\\RD.ar_channel_0_n_44 ,\\RD.ar_channel_0_n_45 ,\\RD.ar_channel_0_n_46 ,\\RD.ar_channel_0_n_47 }),
+        .m_valid_i0(\\ar_pipe/m_valid_i0 ),
+        .next_pending_r_reg(SI_REG_n_155),
+        .next_pending_r_reg_0(SI_REG_n_166),
+        .out(si_rs_bid),
+        .r_push_r_reg({si_rs_rid,si_rs_rlast}),
+        .\\s_arid_r_reg[11] ({s_arid,si_rs_arlen,si_rs_arburst,si_rs_arsize,\\m_axi_arprot[2] ,si_rs_araddr}),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize(s_axi_arsize),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize(s_axi_awsize),
+        .s_axi_awvalid(s_axi_awvalid),
+        .\\s_axi_bid[11] (\\s_axi_bid[11] ),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rid[11] (\\s_axi_rid[11] ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .\\s_bresp_acc_reg[1] (si_rs_bresp),
+        .sel_first(\\cmd_translator_0/incr_cmd_0/sel_first_4 ),
+        .sel_first_1(\\cmd_translator_0/incr_cmd_0/sel_first ),
+        .shandshake(shandshake),
+        .si_rs_arvalid(si_rs_arvalid),
+        .si_rs_awvalid(si_rs_awvalid),
+        .si_rs_bready(si_rs_bready),
+        .si_rs_bvalid(si_rs_bvalid),
+        .si_rs_rready(si_rs_rready),
+        .\\state_reg[0]_rep (\\RD.ar_channel_0_n_15 ),
+        .\\state_reg[1] (\\WR.aw_channel_0_n_7 ),
+        .\\state_reg[1]_0 (\\aw_cmd_fsm_0/state ),
+        .\\state_reg[1]_rep (\\RD.ar_channel_0_n_5 ),
+        .\\state_reg[1]_rep_0 (\\RD.ar_channel_0_n_14 ),
+        .\\state_reg[1]_rep_1 (\\ar_pipe/p_1_in ),
+        .\\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174}),
+        .\\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
+        .\\wrap_cnt_r_reg[2] (SI_REG_n_157),
+        .\\wrap_cnt_r_reg[2]_0 (SI_REG_n_160),
+        .wrap_second_len(\\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
+        .\\wrap_second_len_r_reg[2] (\\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
+        .\\wrap_second_len_r_reg[2]_0 (\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
+        .\\wrap_second_len_r_reg[3] (SI_REG_n_165),
+        .\\wrap_second_len_r_reg[3]_0 (\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_aw_channel \\WR.aw_channel_0 
+       (.CO(SI_REG_n_132),
+        .D(\\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
+        .E(\\aw_pipe/p_1_in ),
+        .O({SI_REG_n_133,SI_REG_n_134,SI_REG_n_135,SI_REG_n_136}),
+        .Q(\\aw_cmd_fsm_0/state ),
+        .S({\\WR.aw_channel_0_n_47 ,\\WR.aw_channel_0_n_48 ,\\WR.aw_channel_0_n_49 ,\\WR.aw_channel_0_n_50 }),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\axaddr_incr_reg[3] (\\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
+        .\\axaddr_offset_r_reg[3] (\\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
+        .b_push(b_push),
+        .\\cnt_read_reg[0]_rep__0 (\\WR.b_channel_0_n_1 ),
+        .\\cnt_read_reg[1]_rep__0 (\\WR.b_channel_0_n_3 ),
+        .\\cnt_read_reg[1]_rep__0_0 (\\WR.b_channel_0_n_2 ),
+        .in({b_awid,b_awlen}),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .\\m_payload_i_reg[11] (C),
+        .\\m_payload_i_reg[38] (SI_REG_n_183),
+        .\\m_payload_i_reg[46] (SI_REG_n_155),
+        .\\m_payload_i_reg[47] (SI_REG_n_154),
+        .\\m_payload_i_reg[61] ({s_awid,si_rs_awlen,si_rs_awburst,si_rs_awsize,si_rs_awaddr}),
+        .\\m_payload_i_reg[6] ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
+        .sel_first(\\cmd_translator_0/incr_cmd_0/sel_first_4 ),
+        .si_rs_awvalid(si_rs_awvalid),
+        .\\wrap_boundary_axaddr_r_reg[0] (\\WR.aw_channel_0_n_7 ),
+        .\\wrap_second_len_r_reg[3] (\\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ),
+        .\\wrap_second_len_r_reg[3]_0 (\\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
+        .\\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_b_channel \\WR.b_channel_0 
+       (.aclk(aclk),
+        .areset_d1(areset_d1),
+        .b_push(b_push),
+        .\\cnt_read_reg[0]_rep__0 (\\WR.b_channel_0_n_1 ),
+        .\\cnt_read_reg[1]_rep__0 (\\WR.b_channel_0_n_2 ),
+        .in({b_awid,b_awlen}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .out(si_rs_bid),
+        .shandshake(shandshake),
+        .si_rs_bready(si_rs_bready),
+        .si_rs_bvalid(si_rs_bvalid),
+        .\\skid_buffer_reg[1] (si_rs_bresp),
+        .\\state_reg[0] (\\WR.b_channel_0_n_3 ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    areset_d1_i_1
+       (.I0(aresetn),
+        .O(areset_d1_i_1_n_0));
+  FDRE areset_d1_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(areset_d1_i_1_n_0),
+        .Q(areset_d1),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_ar_channel
+   (\\axaddr_incr_reg[3] ,
+    sel_first,
+    \\wrap_boundary_axaddr_r_reg[11] ,
+    Q,
+    axaddr_offset,
+    \\axaddr_offset_r_reg[3] ,
+    r_push,
+    \\m_payload_i_reg[0] ,
+    \\m_payload_i_reg[0]_0 ,
+    m_axi_arvalid,
+    r_rlast,
+    m_valid_i0,
+    E,
+    m_axi_araddr,
+    \\r_arid_r_reg[11] ,
+    S,
+    aclk,
+    O,
+    \\m_payload_i_reg[47] ,
+    m_axi_arready,
+    si_rs_arvalid,
+    \\axaddr_offset_r_reg[3]_0 ,
+    \\m_payload_i_reg[61] ,
+    CO,
+    \\cnt_read_reg[1]_rep__0 ,
+    D,
+    \\m_payload_i_reg[35] ,
+    \\m_payload_i_reg[47]_0 ,
+    \\m_payload_i_reg[35]_0 ,
+    \\m_payload_i_reg[3] ,
+    \\m_payload_i_reg[44] ,
+    areset_d1,
+    \\m_payload_i_reg[3]_0 ,
+    \\m_payload_i_reg[11] ,
+    s_axi_arvalid,
+    s_ready_i_reg,
+    \\m_payload_i_reg[38] ,
+    \\wrap_second_len_r_reg[0] ,
+    \\m_payload_i_reg[6] );
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output sel_first;
+  output \\wrap_boundary_axaddr_r_reg[11] ;
+  output [2:0]Q;
+  output [0:0]axaddr_offset;
+  output [2:0]\\axaddr_offset_r_reg[3] ;
+  output r_push;
+  output \\m_payload_i_reg[0] ;
+  output \\m_payload_i_reg[0]_0 ;
+  output m_axi_arvalid;
+  output r_rlast;
+  output m_valid_i0;
+  output [0:0]E;
+  output [11:0]m_axi_araddr;
+  output [11:0]\\r_arid_r_reg[11] ;
+  output [3:0]S;
+  input aclk;
+  input [3:0]O;
+  input \\m_payload_i_reg[47] ;
+  input m_axi_arready;
+  input si_rs_arvalid;
+  input \\axaddr_offset_r_reg[3]_0 ;
+  input [30:0]\\m_payload_i_reg[61] ;
+  input [0:0]CO;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input [1:0]D;
+  input \\m_payload_i_reg[35] ;
+  input [2:0]\\m_payload_i_reg[47]_0 ;
+  input \\m_payload_i_reg[35]_0 ;
+  input \\m_payload_i_reg[3] ;
+  input \\m_payload_i_reg[44] ;
+  input areset_d1;
+  input [3:0]\\m_payload_i_reg[3]_0 ;
+  input [3:0]\\m_payload_i_reg[11] ;
+  input s_axi_arvalid;
+  input s_ready_i_reg;
+  input \\m_payload_i_reg[38] ;
+  input [0:0]\\wrap_second_len_r_reg[0] ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [0:0]CO;
+  wire [1:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [2:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire ar_cmd_fsm_0_n_0;
+  wire ar_cmd_fsm_0_n_10;
+  wire ar_cmd_fsm_0_n_13;
+  wire ar_cmd_fsm_0_n_17;
+  wire ar_cmd_fsm_0_n_18;
+  wire ar_cmd_fsm_0_n_22;
+  wire ar_cmd_fsm_0_n_23;
+  wire ar_cmd_fsm_0_n_3;
+  wire ar_cmd_fsm_0_n_4;
+  wire ar_cmd_fsm_0_n_6;
+  wire areset_d1;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [0:0]axaddr_offset;
+  wire [2:0]\\axaddr_offset_r_reg[3] ;
+  wire \\axaddr_offset_r_reg[3]_0 ;
+  wire cmd_translator_0_n_1;
+  wire cmd_translator_0_n_10;
+  wire cmd_translator_0_n_11;
+  wire cmd_translator_0_n_13;
+  wire cmd_translator_0_n_2;
+  wire cmd_translator_0_n_8;
+  wire cmd_translator_0_n_9;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire incr_next_pending;
+  wire [11:0]m_axi_araddr;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire \\m_payload_i_reg[0] ;
+  wire \\m_payload_i_reg[0]_0 ;
+  wire [3:0]\\m_payload_i_reg[11] ;
+  wire \\m_payload_i_reg[35] ;
+  wire \\m_payload_i_reg[35]_0 ;
+  wire \\m_payload_i_reg[38] ;
+  wire \\m_payload_i_reg[3] ;
+  wire [3:0]\\m_payload_i_reg[3]_0 ;
+  wire \\m_payload_i_reg[44] ;
+  wire \\m_payload_i_reg[47] ;
+  wire [2:0]\\m_payload_i_reg[47]_0 ;
+  wire [30:0]\\m_payload_i_reg[61] ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire m_valid_i0;
+  wire [11:0]\\r_arid_r_reg[11] ;
+  wire r_push;
+  wire r_rlast;
+  wire s_axi_arvalid;
+  wire s_ready_i_reg;
+  wire sel_first;
+  wire sel_first_i;
+  wire si_rs_arvalid;
+  wire [1:0]state;
+  wire \\wrap_boundary_axaddr_r_reg[11] ;
+  wire [0:0]\\wrap_cmd_0/axaddr_offset_r ;
+  wire [3:0]\\wrap_cmd_0/wrap_second_len ;
+  wire [3:3]\\wrap_cmd_0/wrap_second_len_r ;
+  wire wrap_next_pending;
+  wire [0:0]\\wrap_second_len_r_reg[0] ;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm ar_cmd_fsm_0
+       (.D({ar_cmd_fsm_0_n_3,ar_cmd_fsm_0_n_4}),
+        .E(\\wrap_boundary_axaddr_r_reg[11] ),
+        .Q(state),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\axaddr_incr_reg[11] (ar_cmd_fsm_0_n_18),
+        .\\axaddr_offset_r_reg[0] (axaddr_offset),
+        .\\axaddr_offset_r_reg[0]_0 (\\wrap_cmd_0/axaddr_offset_r ),
+        .\\axaddr_offset_r_reg[3] (\\axaddr_offset_r_reg[3]_0 ),
+        .\\axlen_cnt_reg[0] (ar_cmd_fsm_0_n_6),
+        .\\axlen_cnt_reg[0]_0 (cmd_translator_0_n_9),
+        .\\axlen_cnt_reg[3] (ar_cmd_fsm_0_n_17),
+        .\\axlen_cnt_reg[6] (cmd_translator_0_n_10),
+        .\\axlen_cnt_reg[7] (ar_cmd_fsm_0_n_0),
+        .\\cnt_read_reg[1]_rep__0 (\\cnt_read_reg[1]_rep__0 ),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .\\m_payload_i_reg[0] (\\m_payload_i_reg[0] ),
+        .\\m_payload_i_reg[0]_0 (\\m_payload_i_reg[0]_0 ),
+        .\\m_payload_i_reg[0]_1 (E),
+        .\\m_payload_i_reg[35] (\\m_payload_i_reg[35] ),
+        .\\m_payload_i_reg[35]_0 (\\m_payload_i_reg[35]_0 ),
+        .\\m_payload_i_reg[3] (\\m_payload_i_reg[3] ),
+        .\\m_payload_i_reg[44] (\\m_payload_i_reg[61] [15:14]),
+        .\\m_payload_i_reg[44]_0 (\\m_payload_i_reg[44] ),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47]_0 [2:1]),
+        .m_valid_i0(m_valid_i0),
+        .next_pending_r_reg(cmd_translator_0_n_1),
+        .r_push_r_reg(r_push),
+        .s_axburst_eq0_reg(ar_cmd_fsm_0_n_10),
+        .s_axburst_eq1_reg(ar_cmd_fsm_0_n_13),
+        .s_axburst_eq1_reg_0(cmd_translator_0_n_13),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_ready_i_reg(s_ready_i_reg),
+        .sel_first_i(sel_first_i),
+        .sel_first_reg(ar_cmd_fsm_0_n_22),
+        .sel_first_reg_0(ar_cmd_fsm_0_n_23),
+        .sel_first_reg_1(cmd_translator_0_n_2),
+        .sel_first_reg_2(sel_first),
+        .sel_first_reg_3(cmd_translator_0_n_8),
+        .si_rs_arvalid(si_rs_arvalid),
+        .\\state_reg[0]_0 (cmd_translator_0_n_11),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[2] (D),
+        .\\wrap_second_len_r_reg[3] ({\\wrap_cmd_0/wrap_second_len [3],\\wrap_cmd_0/wrap_second_len [0]}),
+        .\\wrap_second_len_r_reg[3]_0 ({\\wrap_cmd_0/wrap_second_len_r ,Q[0]}));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1 cmd_translator_0
+       (.CO(CO),
+        .D(ar_cmd_fsm_0_n_6),
+        .E(\\wrap_boundary_axaddr_r_reg[11] ),
+        .O(O),
+        .Q(cmd_translator_0_n_9),
+        .S(S),
+        .aclk(aclk),
+        .\\axaddr_incr_reg[11] (sel_first),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_offset_r_reg[3] ({\\axaddr_offset_r_reg[3] ,\\wrap_cmd_0/axaddr_offset_r }),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3]_0 ),
+        .\\axlen_cnt_reg[1] (cmd_translator_0_n_10),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arready(m_axi_arready),
+        .\\m_payload_i_reg[11] (\\m_payload_i_reg[11] ),
+        .\\m_payload_i_reg[35] (\\m_payload_i_reg[35] ),
+        .\\m_payload_i_reg[38] (\\m_payload_i_reg[38] ),
+        .\\m_payload_i_reg[39] (ar_cmd_fsm_0_n_10),
+        .\\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_13),
+        .\\m_payload_i_reg[3] (\\m_payload_i_reg[3]_0 ),
+        .\\m_payload_i_reg[44] (\\m_payload_i_reg[44] ),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47] ),
+        .\\m_payload_i_reg[47]_0 (\\m_payload_i_reg[61] [18:0]),
+        .\\m_payload_i_reg[47]_1 ({\\m_payload_i_reg[47]_0 ,axaddr_offset}),
+        .\\m_payload_i_reg[6] (\\m_payload_i_reg[6] ),
+        .m_valid_i_reg(ar_cmd_fsm_0_n_17),
+        .next_pending_r_reg(cmd_translator_0_n_1),
+        .next_pending_r_reg_0(cmd_translator_0_n_11),
+        .r_rlast(r_rlast),
+        .sel_first_i(sel_first_i),
+        .sel_first_reg_0(cmd_translator_0_n_2),
+        .sel_first_reg_1(cmd_translator_0_n_8),
+        .sel_first_reg_2(ar_cmd_fsm_0_n_18),
+        .sel_first_reg_3(ar_cmd_fsm_0_n_22),
+        .sel_first_reg_4(ar_cmd_fsm_0_n_23),
+        .si_rs_arvalid(si_rs_arvalid),
+        .\\state_reg[0]_rep (cmd_translator_0_n_13),
+        .\\state_reg[1] (state),
+        .\\state_reg[1]_0 (ar_cmd_fsm_0_n_0),
+        .\\state_reg[1]_rep (r_push),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[3] ({\\wrap_cmd_0/wrap_second_len_r ,Q}),
+        .\\wrap_second_len_r_reg[3]_0 ({\\wrap_cmd_0/wrap_second_len [3],D,\\wrap_cmd_0/wrap_second_len [0]}),
+        .\\wrap_second_len_r_reg[3]_1 ({ar_cmd_fsm_0_n_3,\\wrap_second_len_r_reg[0] ,ar_cmd_fsm_0_n_4}));
+  FDRE \\s_arid_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [19]),
+        .Q(\\r_arid_r_reg[11] [0]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[10] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [29]),
+        .Q(\\r_arid_r_reg[11] [10]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[11] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [30]),
+        .Q(\\r_arid_r_reg[11] [11]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [20]),
+        .Q(\\r_arid_r_reg[11] [1]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [21]),
+        .Q(\\r_arid_r_reg[11] [2]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [22]),
+        .Q(\\r_arid_r_reg[11] [3]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [23]),
+        .Q(\\r_arid_r_reg[11] [4]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[5] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [24]),
+        .Q(\\r_arid_r_reg[11] [5]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[6] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [25]),
+        .Q(\\r_arid_r_reg[11] [6]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[7] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [26]),
+        .Q(\\r_arid_r_reg[11] [7]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[8] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [27]),
+        .Q(\\r_arid_r_reg[11] [8]),
+        .R(1\'b0));
+  FDRE \\s_arid_r_reg[9] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [28]),
+        .Q(\\r_arid_r_reg[11] [9]),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_aw_channel
+   (\\axaddr_incr_reg[3] ,
+    sel_first,
+    Q,
+    \\wrap_boundary_axaddr_r_reg[0] ,
+    E,
+    b_push,
+    m_axi_awvalid,
+    m_axi_awaddr,
+    \\axaddr_offset_r_reg[3] ,
+    \\wrap_second_len_r_reg[3] ,
+    in,
+    S,
+    aclk,
+    O,
+    si_rs_awvalid,
+    \\m_payload_i_reg[47] ,
+    \\m_payload_i_reg[61] ,
+    CO,
+    \\m_payload_i_reg[46] ,
+    areset_d1,
+    \\cnt_read_reg[1]_rep__0 ,
+    m_axi_awready,
+    \\cnt_read_reg[1]_rep__0_0 ,
+    \\cnt_read_reg[0]_rep__0 ,
+    \\m_payload_i_reg[11] ,
+    \\m_payload_i_reg[38] ,
+    D,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\wrap_second_len_r_reg[3]_1 ,
+    \\m_payload_i_reg[6] );
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output sel_first;
+  output [1:0]Q;
+  output \\wrap_boundary_axaddr_r_reg[0] ;
+  output [0:0]E;
+  output b_push;
+  output m_axi_awvalid;
+  output [11:0]m_axi_awaddr;
+  output [3:0]\\axaddr_offset_r_reg[3] ;
+  output [3:0]\\wrap_second_len_r_reg[3] ;
+  output [15:0]in;
+  output [3:0]S;
+  input aclk;
+  input [3:0]O;
+  input si_rs_awvalid;
+  input \\m_payload_i_reg[47] ;
+  input [30:0]\\m_payload_i_reg[61] ;
+  input [0:0]CO;
+  input \\m_payload_i_reg[46] ;
+  input areset_d1;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input m_axi_awready;
+  input \\cnt_read_reg[1]_rep__0_0 ;
+  input \\cnt_read_reg[0]_rep__0 ;
+  input [7:0]\\m_payload_i_reg[11] ;
+  input \\m_payload_i_reg[38] ;
+  input [3:0]D;
+  input [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [0:0]CO;
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [1:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire areset_d1;
+  wire aw_cmd_fsm_0_n_0;
+  wire aw_cmd_fsm_0_n_10;
+  wire aw_cmd_fsm_0_n_14;
+  wire aw_cmd_fsm_0_n_15;
+  wire aw_cmd_fsm_0_n_3;
+  wire aw_cmd_fsm_0_n_5;
+  wire aw_cmd_fsm_0_n_6;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3] ;
+  wire b_push;
+  wire cmd_translator_0_n_0;
+  wire cmd_translator_0_n_1;
+  wire cmd_translator_0_n_10;
+  wire cmd_translator_0_n_11;
+  wire cmd_translator_0_n_2;
+  wire cmd_translator_0_n_9;
+  wire \\cnt_read_reg[0]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0_0 ;
+  wire [15:0]in;
+  wire incr_next_pending;
+  wire [11:0]m_axi_awaddr;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire [7:0]\\m_payload_i_reg[11] ;
+  wire \\m_payload_i_reg[38] ;
+  wire \\m_payload_i_reg[46] ;
+  wire \\m_payload_i_reg[47] ;
+  wire [30:0]\\m_payload_i_reg[61] ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire sel_first;
+  wire sel_first__0;
+  wire sel_first_i;
+  wire si_rs_awvalid;
+  wire \\wrap_boundary_axaddr_r_reg[0] ;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3] ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_1 ;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm aw_cmd_fsm_0
+       (.E(aw_cmd_fsm_0_n_0),
+        .Q(Q),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\axlen_cnt_reg[3] (cmd_translator_0_n_11),
+        .\\axlen_cnt_reg[7] (aw_cmd_fsm_0_n_5),
+        .\\axlen_cnt_reg[7]_0 (cmd_translator_0_n_9),
+        .b_push(b_push),
+        .\\cnt_read_reg[0]_rep__0 (\\cnt_read_reg[0]_rep__0 ),
+        .\\cnt_read_reg[1]_rep__0 (\\cnt_read_reg[1]_rep__0 ),
+        .\\cnt_read_reg[1]_rep__0_0 (\\cnt_read_reg[1]_rep__0_0 ),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .\\m_payload_i_reg[0] (E),
+        .\\m_payload_i_reg[39] (\\m_payload_i_reg[61] [14]),
+        .\\m_payload_i_reg[46] (\\m_payload_i_reg[46] ),
+        .next_pending_r_reg(cmd_translator_0_n_0),
+        .next_pending_r_reg_0(cmd_translator_0_n_1),
+        .s_axburst_eq0_reg(aw_cmd_fsm_0_n_6),
+        .s_axburst_eq1_reg(aw_cmd_fsm_0_n_10),
+        .s_axburst_eq1_reg_0(cmd_translator_0_n_10),
+        .sel_first__0(sel_first__0),
+        .sel_first_i(sel_first_i),
+        .sel_first_reg(aw_cmd_fsm_0_n_3),
+        .sel_first_reg_0(aw_cmd_fsm_0_n_14),
+        .sel_first_reg_1(aw_cmd_fsm_0_n_15),
+        .sel_first_reg_2(cmd_translator_0_n_2),
+        .sel_first_reg_3(sel_first),
+        .si_rs_awvalid(si_rs_awvalid),
+        .\\wrap_boundary_axaddr_r_reg[0] (\\wrap_boundary_axaddr_r_reg[0] ),
+        .wrap_next_pending(wrap_next_pending));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_cmd_translator cmd_translator_0
+       (.CO(CO),
+        .D(D),
+        .E(\\wrap_boundary_axaddr_r_reg[0] ),
+        .O(O),
+        .Q(Q),
+        .S(S),
+        .aclk(aclk),
+        .\\axaddr_incr_reg[11] (sel_first),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_offset_r_reg[3] (\\axaddr_offset_r_reg[3] ),
+        .\\axlen_cnt_reg[0] (cmd_translator_0_n_9),
+        .\\cnt_read_reg[1]_rep__0 (aw_cmd_fsm_0_n_3),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_awaddr(m_axi_awaddr),
+        .\\m_payload_i_reg[11] (\\m_payload_i_reg[11] ),
+        .\\m_payload_i_reg[38] (\\m_payload_i_reg[38] ),
+        .\\m_payload_i_reg[39] (aw_cmd_fsm_0_n_6),
+        .\\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_10),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47] ),
+        .\\m_payload_i_reg[47]_0 (\\m_payload_i_reg[61] [18:0]),
+        .\\m_payload_i_reg[6] (\\m_payload_i_reg[6] ),
+        .next_pending_r_reg(cmd_translator_0_n_0),
+        .next_pending_r_reg_0(cmd_translator_0_n_1),
+        .next_pending_r_reg_1(cmd_translator_0_n_11),
+        .sel_first__0(sel_first__0),
+        .sel_first_i(sel_first_i),
+        .sel_first_reg_0(cmd_translator_0_n_2),
+        .sel_first_reg_1(aw_cmd_fsm_0_n_14),
+        .sel_first_reg_2(aw_cmd_fsm_0_n_15),
+        .si_rs_awvalid(si_rs_awvalid),
+        .\\state_reg[0] (cmd_translator_0_n_10),
+        .\\state_reg[0]_0 (aw_cmd_fsm_0_n_0),
+        .\\state_reg[0]_1 (aw_cmd_fsm_0_n_5),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[3] (\\wrap_second_len_r_reg[3] ),
+        .\\wrap_second_len_r_reg[3]_0 (\\wrap_second_len_r_reg[3]_0 ),
+        .\\wrap_second_len_r_reg[3]_1 (\\wrap_second_len_r_reg[3]_1 ));
+  FDRE \\s_awid_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [19]),
+        .Q(in[4]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[10] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [29]),
+        .Q(in[14]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[11] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [30]),
+        .Q(in[15]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [20]),
+        .Q(in[5]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [21]),
+        .Q(in[6]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [22]),
+        .Q(in[7]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [23]),
+        .Q(in[8]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[5] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [24]),
+        .Q(in[9]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[6] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [25]),
+        .Q(in[10]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[7] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [26]),
+        .Q(in[11]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[8] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [27]),
+        .Q(in[12]),
+        .R(1\'b0));
+  FDRE \\s_awid_r_reg[9] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [28]),
+        .Q(in[13]),
+        .R(1\'b0));
+  FDRE \\s_awlen_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [15]),
+        .Q(in[0]),
+        .R(1\'b0));
+  FDRE \\s_awlen_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [16]),
+        .Q(in[1]),
+        .R(1\'b0));
+  FDRE \\s_awlen_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [17]),
+        .Q(in[2]),
+        .R(1\'b0));
+  FDRE \\s_awlen_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[61] [18]),
+        .Q(in[3]),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_b_channel
+   (si_rs_bvalid,
+    \\cnt_read_reg[0]_rep__0 ,
+    \\cnt_read_reg[1]_rep__0 ,
+    \\state_reg[0] ,
+    m_axi_bready,
+    out,
+    \\skid_buffer_reg[1] ,
+    shandshake,
+    aclk,
+    b_push,
+    m_axi_bvalid,
+    areset_d1,
+    si_rs_bready,
+    in,
+    m_axi_bresp);
+  output si_rs_bvalid;
+  output \\cnt_read_reg[0]_rep__0 ;
+  output \\cnt_read_reg[1]_rep__0 ;
+  output \\state_reg[0] ;
+  output m_axi_bready;
+  output [11:0]out;
+  output [1:0]\\skid_buffer_reg[1] ;
+  input shandshake;
+  input aclk;
+  input b_push;
+  input m_axi_bvalid;
+  input areset_d1;
+  input si_rs_bready;
+  input [15:0]in;
+  input [1:0]m_axi_bresp;
+
+  wire aclk;
+  wire areset_d1;
+  wire b_push;
+  wire bid_fifo_0_n_5;
+  wire \\bresp_cnt[7]_i_3_n_0 ;
+  wire [7:0]bresp_cnt_reg__0;
+  wire bresp_push;
+  wire [1:0]cnt_read;
+  wire \\cnt_read_reg[0]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire [15:0]in;
+  wire m_axi_bready;
+  wire [1:0]m_axi_bresp;
+  wire m_axi_bvalid;
+  wire mhandshake;
+  wire mhandshake_r;
+  wire [11:0]out;
+  wire [7:0]p_0_in;
+  wire s_bresp_acc0;
+  wire \\s_bresp_acc[0]_i_1_n_0 ;
+  wire \\s_bresp_acc[1]_i_1_n_0 ;
+  wire \\s_bresp_acc_reg_n_0_[0] ;
+  wire \\s_bresp_acc_reg_n_0_[1] ;
+  wire shandshake;
+  wire shandshake_r;
+  wire si_rs_bready;
+  wire si_rs_bvalid;
+  wire [1:0]\\skid_buffer_reg[1] ;
+  wire \\state_reg[0] ;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_simple_fifo bid_fifo_0
+       (.Q(bresp_cnt_reg__0),
+        .SR(s_bresp_acc0),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .b_push(b_push),
+        .bresp_push(bresp_push),
+        .bvalid_i_reg(bid_fifo_0_n_5),
+        .\\cnt_read_reg[0]_rep__0_0 (\\cnt_read_reg[0]_rep__0 ),
+        .\\cnt_read_reg[1]_0 (cnt_read),
+        .\\cnt_read_reg[1]_rep__0_0 (\\cnt_read_reg[1]_rep__0 ),
+        .in(in),
+        .mhandshake_r(mhandshake_r),
+        .out(out),
+        .shandshake_r(shandshake_r),
+        .si_rs_bready(si_rs_bready),
+        .si_rs_bvalid(si_rs_bvalid),
+        .\\state_reg[0] (\\state_reg[0] ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\bresp_cnt[0]_i_1 
+       (.I0(bresp_cnt_reg__0[0]),
+        .O(p_0_in[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair117"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\bresp_cnt[1]_i_1 
+       (.I0(bresp_cnt_reg__0[0]),
+        .I1(bresp_cnt_reg__0[1]),
+        .O(p_0_in[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair117"" *) 
+  LUT3 #(
+    .INIT(8\'h6A)) 
+    \\bresp_cnt[2]_i_1 
+       (.I0(bresp_cnt_reg__0[2]),
+        .I1(bresp_cnt_reg__0[1]),
+        .I2(bresp_cnt_reg__0[0]),
+        .O(p_0_in[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair115"" *) 
+  LUT4 #(
+    .INIT(16\'h6AAA)) 
+    \\bresp_cnt[3]_i_1 
+       (.I0(bresp_cnt_reg__0[3]),
+        .I1(bresp_cnt_reg__0[0]),
+        .I2(bresp_cnt_reg__0[1]),
+        .I3(bresp_cnt_reg__0[2]),
+        .O(p_0_in[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair115"" *) 
+  LUT5 #(
+    .INIT(32\'h6AAAAAAA)) 
+    \\bresp_cnt[4]_i_1 
+       (.I0(bresp_cnt_reg__0[4]),
+        .I1(bresp_cnt_reg__0[2]),
+        .I2(bresp_cnt_reg__0[1]),
+        .I3(bresp_cnt_reg__0[0]),
+        .I4(bresp_cnt_reg__0[3]),
+        .O(p_0_in[4]));
+  LUT6 #(
+    .INIT(64\'h6AAAAAAAAAAAAAAA)) 
+    \\bresp_cnt[5]_i_1 
+       (.I0(bresp_cnt_reg__0[5]),
+        .I1(bresp_cnt_reg__0[3]),
+        .I2(bresp_cnt_reg__0[0]),
+        .I3(bresp_cnt_reg__0[1]),
+        .I4(bresp_cnt_reg__0[2]),
+        .I5(bresp_cnt_reg__0[4]),
+        .O(p_0_in[5]));
+  (* SOFT_HLUTNM = ""soft_lutpair116"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\bresp_cnt[6]_i_1 
+       (.I0(bresp_cnt_reg__0[6]),
+        .I1(\\bresp_cnt[7]_i_3_n_0 ),
+        .O(p_0_in[6]));
+  (* SOFT_HLUTNM = ""soft_lutpair116"" *) 
+  LUT3 #(
+    .INIT(8\'h6A)) 
+    \\bresp_cnt[7]_i_2 
+       (.I0(bresp_cnt_reg__0[7]),
+        .I1(\\bresp_cnt[7]_i_3_n_0 ),
+        .I2(bresp_cnt_reg__0[6]),
+        .O(p_0_in[7]));
+  LUT6 #(
+    .INIT(64\'h8000000000000000)) 
+    \\bresp_cnt[7]_i_3 
+       (.I0(bresp_cnt_reg__0[5]),
+        .I1(bresp_cnt_reg__0[3]),
+        .I2(bresp_cnt_reg__0[0]),
+        .I3(bresp_cnt_reg__0[1]),
+        .I4(bresp_cnt_reg__0[2]),
+        .I5(bresp_cnt_reg__0[4]),
+        .O(\\bresp_cnt[7]_i_3_n_0 ));
+  FDRE \\bresp_cnt_reg[0] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[0]),
+        .Q(bresp_cnt_reg__0[0]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[1] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[1]),
+        .Q(bresp_cnt_reg__0[1]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[2] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[2]),
+        .Q(bresp_cnt_reg__0[2]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[3] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[3]),
+        .Q(bresp_cnt_reg__0[3]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[4] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[4]),
+        .Q(bresp_cnt_reg__0[4]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[5] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[5]),
+        .Q(bresp_cnt_reg__0[5]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[6] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[6]),
+        .Q(bresp_cnt_reg__0[6]),
+        .R(s_bresp_acc0));
+  FDRE \\bresp_cnt_reg[7] 
+       (.C(aclk),
+        .CE(mhandshake_r),
+        .D(p_0_in[7]),
+        .Q(bresp_cnt_reg__0[7]),
+        .R(s_bresp_acc0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0 bresp_fifo_0
+       (.Q(cnt_read),
+        .aclk(aclk),
+        .areset_d1(areset_d1),
+        .bresp_push(bresp_push),
+        .in({\\s_bresp_acc_reg_n_0_[1] ,\\s_bresp_acc_reg_n_0_[0] }),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bvalid(m_axi_bvalid),
+        .mhandshake(mhandshake),
+        .mhandshake_r(mhandshake_r),
+        .shandshake_r(shandshake_r),
+        .\\skid_buffer_reg[1] (\\skid_buffer_reg[1] ));
+  FDRE bvalid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(bid_fifo_0_n_5),
+        .Q(si_rs_bvalid),
+        .R(1\'b0));
+  FDRE mhandshake_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(mhandshake),
+        .Q(mhandshake_r),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h00000000EACECCCC)) 
+    \\s_bresp_acc[0]_i_1 
+       (.I0(m_axi_bresp[0]),
+        .I1(\\s_bresp_acc_reg_n_0_[0] ),
+        .I2(\\s_bresp_acc_reg_n_0_[1] ),
+        .I3(m_axi_bresp[1]),
+        .I4(mhandshake),
+        .I5(s_bresp_acc0),
+        .O(\\s_bresp_acc[0]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h00EA)) 
+    \\s_bresp_acc[1]_i_1 
+       (.I0(\\s_bresp_acc_reg_n_0_[1] ),
+        .I1(m_axi_bresp[1]),
+        .I2(mhandshake),
+        .I3(s_bresp_acc0),
+        .O(\\s_bresp_acc[1]_i_1_n_0 ));
+  FDRE \\s_bresp_acc_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_bresp_acc[0]_i_1_n_0 ),
+        .Q(\\s_bresp_acc_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\s_bresp_acc_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_bresp_acc[1]_i_1_n_0 ),
+        .Q(\\s_bresp_acc_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE shandshake_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(shandshake),
+        .Q(shandshake_r),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_cmd_translator
+   (next_pending_r_reg,
+    next_pending_r_reg_0,
+    sel_first_reg_0,
+    \\axaddr_incr_reg[3] ,
+    \\axaddr_incr_reg[11] ,
+    sel_first__0,
+    \\axlen_cnt_reg[0] ,
+    \\state_reg[0] ,
+    next_pending_r_reg_1,
+    m_axi_awaddr,
+    \\axaddr_offset_r_reg[3] ,
+    \\wrap_second_len_r_reg[3] ,
+    S,
+    incr_next_pending,
+    aclk,
+    wrap_next_pending,
+    sel_first_i,
+    \\m_payload_i_reg[39] ,
+    \\m_payload_i_reg[39]_0 ,
+    O,
+    sel_first_reg_1,
+    sel_first_reg_2,
+    \\m_payload_i_reg[47] ,
+    Q,
+    si_rs_awvalid,
+    \\m_payload_i_reg[47]_0 ,
+    E,
+    CO,
+    \\cnt_read_reg[1]_rep__0 ,
+    \\m_payload_i_reg[11] ,
+    \\m_payload_i_reg[38] ,
+    \\state_reg[0]_0 ,
+    \\state_reg[0]_1 ,
+    D,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\wrap_second_len_r_reg[3]_1 ,
+    \\m_payload_i_reg[6] );
+  output next_pending_r_reg;
+  output next_pending_r_reg_0;
+  output sel_first_reg_0;
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output \\axaddr_incr_reg[11] ;
+  output sel_first__0;
+  output \\axlen_cnt_reg[0] ;
+  output \\state_reg[0] ;
+  output next_pending_r_reg_1;
+  output [11:0]m_axi_awaddr;
+  output [3:0]\\axaddr_offset_r_reg[3] ;
+  output [3:0]\\wrap_second_len_r_reg[3] ;
+  output [3:0]S;
+  input incr_next_pending;
+  input aclk;
+  input wrap_next_pending;
+  input sel_first_i;
+  input \\m_payload_i_reg[39] ;
+  input \\m_payload_i_reg[39]_0 ;
+  input [3:0]O;
+  input sel_first_reg_1;
+  input sel_first_reg_2;
+  input \\m_payload_i_reg[47] ;
+  input [1:0]Q;
+  input si_rs_awvalid;
+  input [18:0]\\m_payload_i_reg[47]_0 ;
+  input [0:0]E;
+  input [0:0]CO;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input [7:0]\\m_payload_i_reg[11] ;
+  input \\m_payload_i_reg[38] ;
+  input [0:0]\\state_reg[0]_0 ;
+  input \\state_reg[0]_1 ;
+  input [3:0]D;
+  input [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [0:0]CO;
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [1:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire [11:4]axaddr_incr_reg;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire axaddr_incr_reg_11__s_net_1;
+  wire [3:0]\\axaddr_offset_r_reg[3] ;
+  wire \\axlen_cnt_reg[0] ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire incr_next_pending;
+  wire [11:0]m_axi_awaddr;
+  wire [7:0]\\m_payload_i_reg[11] ;
+  wire \\m_payload_i_reg[38] ;
+  wire \\m_payload_i_reg[39] ;
+  wire \\m_payload_i_reg[39]_0 ;
+  wire \\m_payload_i_reg[47] ;
+  wire [18:0]\\m_payload_i_reg[47]_0 ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire next_pending_r_reg;
+  wire next_pending_r_reg_0;
+  wire next_pending_r_reg_1;
+  wire s_axburst_eq0;
+  wire s_axburst_eq1;
+  wire sel_first__0;
+  wire sel_first_i;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire sel_first_reg_2;
+  wire si_rs_awvalid;
+  wire \\state_reg[0] ;
+  wire [0:0]\\state_reg[0]_0 ;
+  wire \\state_reg[0]_1 ;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3] ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_1 ;
+
+  assign \\axaddr_incr_reg[11]  = axaddr_incr_reg_11__s_net_1;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_incr_cmd incr_cmd_0
+       (.CO(CO),
+        .E(E),
+        .O(O),
+        .Q(Q),
+        .S(S),
+        .aclk(aclk),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
+        .\\axaddr_incr_reg[3]_0 (\\axaddr_incr_reg[3] ),
+        .\\axlen_cnt_reg[0]_0 (\\axlen_cnt_reg[0] ),
+        .\\cnt_read_reg[1]_rep__0 (\\cnt_read_reg[1]_rep__0 ),
+        .incr_next_pending(incr_next_pending),
+        .\\m_payload_i_reg[11] (\\m_payload_i_reg[11] ),
+        .\\m_payload_i_reg[46] ({\\m_payload_i_reg[47]_0 [17:15],\\m_payload_i_reg[47]_0 [13:12],\\m_payload_i_reg[47]_0 [3:0]}),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47] ),
+        .next_pending_r_reg_0(next_pending_r_reg),
+        .sel_first_reg_0(sel_first_reg_1),
+        .si_rs_awvalid(si_rs_awvalid),
+        .\\state_reg[0] (\\state_reg[0]_0 ),
+        .\\state_reg[0]_0 (\\state_reg[0]_1 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\memory_reg[3][0]_srl4_i_2 
+       (.I0(s_axburst_eq1),
+        .I1(\\m_payload_i_reg[47]_0 [14]),
+        .I2(s_axburst_eq0),
+        .O(\\state_reg[0] ));
+  FDRE s_axburst_eq0_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[39] ),
+        .Q(s_axburst_eq0),
+        .R(1\'b0));
+  FDRE s_axburst_eq1_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[39]_0 ),
+        .Q(s_axburst_eq1),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_i),
+        .Q(sel_first_reg_0),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_wrap_cmd wrap_cmd_0
+       (.D(D),
+        .E(E),
+        .aclk(aclk),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3] ),
+        .\\cnt_read_reg[1]_rep__0 (\\cnt_read_reg[1]_rep__0 ),
+        .m_axi_awaddr(m_axi_awaddr),
+        .\\m_payload_i_reg[38] (\\m_payload_i_reg[38] ),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47]_0 ),
+        .\\m_payload_i_reg[6] (\\m_payload_i_reg[6] ),
+        .next_pending_r_reg_0(next_pending_r_reg_0),
+        .next_pending_r_reg_1(next_pending_r_reg_1),
+        .sel_first_reg_0(sel_first__0),
+        .sel_first_reg_1(sel_first_reg_2),
+        .\\state_reg[0] (\\state_reg[0]_0 ),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[3]_0 (\\wrap_second_len_r_reg[3] ),
+        .\\wrap_second_len_r_reg[3]_1 (\\wrap_second_len_r_reg[3]_0 ),
+        .\\wrap_second_len_r_reg[3]_2 (\\wrap_second_len_r_reg[3]_1 ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_cmd_translator"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_cmd_translator'b'_1
+   (incr_next_pending,
+    next_pending_r_reg,
+    sel_first_reg_0,
+    \\axaddr_incr_reg[3] ,
+    \\axaddr_incr_reg[11] ,
+    sel_first_reg_1,
+    Q,
+    \\axlen_cnt_reg[1] ,
+    next_pending_r_reg_0,
+    r_rlast,
+    \\state_reg[0]_rep ,
+    m_axi_araddr,
+    \\wrap_second_len_r_reg[3] ,
+    \\axaddr_offset_r_reg[3] ,
+    S,
+    aclk,
+    wrap_next_pending,
+    sel_first_i,
+    \\m_payload_i_reg[39] ,
+    \\m_payload_i_reg[39]_0 ,
+    sel_first_reg_2,
+    O,
+    sel_first_reg_3,
+    sel_first_reg_4,
+    \\m_payload_i_reg[47] ,
+    E,
+    \\m_payload_i_reg[47]_0 ,
+    \\state_reg[1] ,
+    si_rs_arvalid,
+    CO,
+    \\state_reg[1]_rep ,
+    \\m_payload_i_reg[44] ,
+    \\m_payload_i_reg[3] ,
+    \\m_payload_i_reg[11] ,
+    \\m_payload_i_reg[38] ,
+    \\axaddr_offset_r_reg[3]_0 ,
+    \\m_payload_i_reg[35] ,
+    m_valid_i_reg,
+    D,
+    \\state_reg[1]_0 ,
+    \\m_payload_i_reg[47]_1 ,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\wrap_second_len_r_reg[3]_1 ,
+    \\m_payload_i_reg[6] ,
+    m_axi_arready);
+  output incr_next_pending;
+  output next_pending_r_reg;
+  output sel_first_reg_0;
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output \\axaddr_incr_reg[11] ;
+  output sel_first_reg_1;
+  output [0:0]Q;
+  output \\axlen_cnt_reg[1] ;
+  output next_pending_r_reg_0;
+  output r_rlast;
+  output \\state_reg[0]_rep ;
+  output [11:0]m_axi_araddr;
+  output [3:0]\\wrap_second_len_r_reg[3] ;
+  output [3:0]\\axaddr_offset_r_reg[3] ;
+  output [3:0]S;
+  input aclk;
+  input wrap_next_pending;
+  input sel_first_i;
+  input \\m_payload_i_reg[39] ;
+  input \\m_payload_i_reg[39]_0 ;
+  input sel_first_reg_2;
+  input [3:0]O;
+  input sel_first_reg_3;
+  input sel_first_reg_4;
+  input \\m_payload_i_reg[47] ;
+  input [0:0]E;
+  input [18:0]\\m_payload_i_reg[47]_0 ;
+  input [1:0]\\state_reg[1] ;
+  input si_rs_arvalid;
+  input [0:0]CO;
+  input \\state_reg[1]_rep ;
+  input \\m_payload_i_reg[44] ;
+  input [3:0]\\m_payload_i_reg[3] ;
+  input [3:0]\\m_payload_i_reg[11] ;
+  input \\m_payload_i_reg[38] ;
+  input \\axaddr_offset_r_reg[3]_0 ;
+  input \\m_payload_i_reg[35] ;
+  input [0:0]m_valid_i_reg;
+  input [0:0]D;
+  input \\state_reg[1]_0 ;
+  input [3:0]\\m_payload_i_reg[47]_1 ;
+  input [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input [2:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+  input m_axi_arready;
+
+  wire [0:0]CO;
+  wire [0:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [0:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire [11:4]axaddr_incr_reg;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire axaddr_incr_reg_11__s_net_1;
+  wire [3:0]\\axaddr_offset_r_reg[3] ;
+  wire \\axaddr_offset_r_reg[3]_0 ;
+  wire \\axlen_cnt_reg[1] ;
+  wire incr_next_pending;
+  wire [11:0]m_axi_araddr;
+  wire m_axi_arready;
+  wire [3:0]\\m_payload_i_reg[11] ;
+  wire \\m_payload_i_reg[35] ;
+  wire \\m_payload_i_reg[38] ;
+  wire \\m_payload_i_reg[39] ;
+  wire \\m_payload_i_reg[39]_0 ;
+  wire [3:0]\\m_payload_i_reg[3] ;
+  wire \\m_payload_i_reg[44] ;
+  wire \\m_payload_i_reg[47] ;
+  wire [18:0]\\m_payload_i_reg[47]_0 ;
+  wire [3:0]\\m_payload_i_reg[47]_1 ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire [0:0]m_valid_i_reg;
+  wire next_pending_r_reg;
+  wire next_pending_r_reg_0;
+  wire r_rlast;
+  wire s_axburst_eq0;
+  wire s_axburst_eq1;
+  wire sel_first_i;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire sel_first_reg_2;
+  wire sel_first_reg_3;
+  wire sel_first_reg_4;
+  wire si_rs_arvalid;
+  wire \\state_reg[0]_rep ;
+  wire [1:0]\\state_reg[1] ;
+  wire \\state_reg[1]_0 ;
+  wire \\state_reg[1]_rep ;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3] ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [2:0]\\wrap_second_len_r_reg[3]_1 ;
+
+  assign \\axaddr_incr_reg[11]  = axaddr_incr_reg_11__s_net_1;
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2 incr_cmd_0
+       (.CO(CO),
+        .D(D),
+        .E(E),
+        .O(O),
+        .Q(Q),
+        .S(S),
+        .aclk(aclk),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
+        .\\axaddr_incr_reg[3]_0 (\\axaddr_incr_reg[3] ),
+        .\\axlen_cnt_reg[1]_0 (\\axlen_cnt_reg[1] ),
+        .incr_next_pending(incr_next_pending),
+        .m_axi_arready(m_axi_arready),
+        .\\m_payload_i_reg[11] (\\m_payload_i_reg[11] ),
+        .\\m_payload_i_reg[3] (\\m_payload_i_reg[3] ),
+        .\\m_payload_i_reg[44] (\\m_payload_i_reg[44] ),
+        .\\m_payload_i_reg[46] ({\\m_payload_i_reg[47]_0 [17:16],\\m_payload_i_reg[47]_0 [13:12],\\m_payload_i_reg[47]_0 [3:0]}),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47] ),
+        .m_valid_i_reg(m_valid_i_reg),
+        .sel_first_reg_0(sel_first_reg_2),
+        .sel_first_reg_1(sel_first_reg_3),
+        .\\state_reg[1] (\\state_reg[1]_0 ),
+        .\\state_reg[1]_0 (\\state_reg[1] ),
+        .\\state_reg[1]_rep (\\state_reg[1]_rep ));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT3 #(
+    .INIT(8\'h1D)) 
+    r_rlast_r_i_1
+       (.I0(s_axburst_eq0),
+        .I1(\\m_payload_i_reg[47]_0 [14]),
+        .I2(s_axburst_eq1),
+        .O(r_rlast));
+  FDRE s_axburst_eq0_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[39] ),
+        .Q(s_axburst_eq0),
+        .R(1\'b0));
+  FDRE s_axburst_eq1_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[39]_0 ),
+        .Q(s_axburst_eq1),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_i),
+        .Q(sel_first_reg_0),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\state[1]_i_2 
+       (.I0(s_axburst_eq1),
+        .I1(\\m_payload_i_reg[47]_0 [14]),
+        .I2(s_axburst_eq0),
+        .O(\\state_reg[0]_rep ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3 wrap_cmd_0
+       (.E(E),
+        .aclk(aclk),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3] ),
+        .\\axaddr_offset_r_reg[3]_1 (\\axaddr_offset_r_reg[3]_0 ),
+        .m_axi_araddr(m_axi_araddr),
+        .\\m_payload_i_reg[35] (\\m_payload_i_reg[35] ),
+        .\\m_payload_i_reg[38] (\\m_payload_i_reg[38] ),
+        .\\m_payload_i_reg[47] (\\m_payload_i_reg[47]_0 ),
+        .\\m_payload_i_reg[47]_0 (\\m_payload_i_reg[47]_1 ),
+        .\\m_payload_i_reg[6] (\\m_payload_i_reg[6] ),
+        .m_valid_i_reg(m_valid_i_reg),
+        .next_pending_r_reg_0(next_pending_r_reg),
+        .next_pending_r_reg_1(next_pending_r_reg_0),
+        .sel_first_reg_0(sel_first_reg_1),
+        .sel_first_reg_1(sel_first_reg_4),
+        .si_rs_arvalid(si_rs_arvalid),
+        .\\state_reg[1] (\\state_reg[1] ),
+        .\\state_reg[1]_rep (\\state_reg[1]_rep ),
+        .wrap_next_pending(wrap_next_pending),
+        .\\wrap_second_len_r_reg[3]_0 (\\wrap_second_len_r_reg[3] ),
+        .\\wrap_second_len_r_reg[3]_1 (\\wrap_second_len_r_reg[3]_0 ),
+        .\\wrap_second_len_r_reg[3]_2 (\\wrap_second_len_r_reg[3]_1 ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_incr_cmd
+   (next_pending_r_reg_0,
+    \\axaddr_incr_reg[3]_0 ,
+    axaddr_incr_reg,
+    \\axaddr_incr_reg[11]_0 ,
+    \\axlen_cnt_reg[0]_0 ,
+    S,
+    incr_next_pending,
+    aclk,
+    O,
+    sel_first_reg_0,
+    \\m_payload_i_reg[47] ,
+    Q,
+    si_rs_awvalid,
+    \\m_payload_i_reg[46] ,
+    E,
+    CO,
+    \\cnt_read_reg[1]_rep__0 ,
+    \\m_payload_i_reg[11] ,
+    \\state_reg[0] ,
+    \\state_reg[0]_0 );
+  output next_pending_r_reg_0;
+  output [3:0]\\axaddr_incr_reg[3]_0 ;
+  output [7:0]axaddr_incr_reg;
+  output \\axaddr_incr_reg[11]_0 ;
+  output \\axlen_cnt_reg[0]_0 ;
+  output [3:0]S;
+  input incr_next_pending;
+  input aclk;
+  input [3:0]O;
+  input sel_first_reg_0;
+  input \\m_payload_i_reg[47] ;
+  input [1:0]Q;
+  input si_rs_awvalid;
+  input [8:0]\\m_payload_i_reg[46] ;
+  input [0:0]E;
+  input [0:0]CO;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input [7:0]\\m_payload_i_reg[11] ;
+  input [0:0]\\state_reg[0] ;
+  input \\state_reg[0]_0 ;
+
+  wire [0:0]CO;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [1:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire \\axaddr_incr[0]_i_1_n_0 ;
+  wire \\axaddr_incr[4]_i_2_n_0 ;
+  wire \\axaddr_incr[4]_i_3_n_0 ;
+  wire \\axaddr_incr[4]_i_4_n_0 ;
+  wire \\axaddr_incr[4]_i_5_n_0 ;
+  wire \\axaddr_incr[8]_i_2_n_0 ;
+  wire \\axaddr_incr[8]_i_3_n_0 ;
+  wire \\axaddr_incr[8]_i_4_n_0 ;
+  wire \\axaddr_incr[8]_i_5_n_0 ;
+  wire [7:0]axaddr_incr_reg;
+  wire \\axaddr_incr_reg[11]_0 ;
+  wire [3:0]\\axaddr_incr_reg[3]_0 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_0 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_1 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_2 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_3 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_4 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_5 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_6 ;
+  wire \\axaddr_incr_reg[4]_i_1_n_7 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_1 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_2 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_3 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_4 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_5 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_6 ;
+  wire \\axaddr_incr_reg[8]_i_1_n_7 ;
+  wire \\axlen_cnt[0]_i_1__1_n_0 ;
+  wire \\axlen_cnt[3]_i_2_n_0 ;
+  wire \\axlen_cnt[4]_i_1_n_0 ;
+  wire \\axlen_cnt[5]_i_1_n_0 ;
+  wire \\axlen_cnt[6]_i_1_n_0 ;
+  wire \\axlen_cnt[7]_i_2_n_0 ;
+  wire \\axlen_cnt[7]_i_3_n_0 ;
+  wire \\axlen_cnt_reg[0]_0 ;
+  wire \\axlen_cnt_reg_n_0_[0] ;
+  wire \\axlen_cnt_reg_n_0_[1] ;
+  wire \\axlen_cnt_reg_n_0_[2] ;
+  wire \\axlen_cnt_reg_n_0_[3] ;
+  wire \\axlen_cnt_reg_n_0_[4] ;
+  wire \\axlen_cnt_reg_n_0_[5] ;
+  wire \\axlen_cnt_reg_n_0_[6] ;
+  wire \\axlen_cnt_reg_n_0_[7] ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire incr_next_pending;
+  wire [7:0]\\m_payload_i_reg[11] ;
+  wire [8:0]\\m_payload_i_reg[46] ;
+  wire \\m_payload_i_reg[47] ;
+  wire next_pending_r_i_5_n_0;
+  wire next_pending_r_reg_0;
+  wire [2:1]p_1_in;
+  wire sel_first_reg_0;
+  wire si_rs_awvalid;
+  wire [0:0]\\state_reg[0] ;
+  wire \\state_reg[0]_0 ;
+  wire [3:3]\\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED ;
+
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\axaddr_incr[0]_i_1 
+       (.I0(\\axaddr_incr_reg[11]_0 ),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .O(\\axaddr_incr[0]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16\'h9AAA)) 
+    \\axaddr_incr[0]_i_15 
+       (.I0(\\m_payload_i_reg[46] [3]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(\\m_payload_i_reg[46] [4]),
+        .I3(\\m_payload_i_reg[46] [5]),
+        .O(S[3]));
+  LUT4 #(
+    .INIT(16\'h0A9A)) 
+    \\axaddr_incr[0]_i_16 
+       (.I0(\\m_payload_i_reg[46] [2]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(\\m_payload_i_reg[46] [5]),
+        .I3(\\m_payload_i_reg[46] [4]),
+        .O(S[2]));
+  LUT4 #(
+    .INIT(16\'h009A)) 
+    \\axaddr_incr[0]_i_17 
+       (.I0(\\m_payload_i_reg[46] [1]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(\\m_payload_i_reg[46] [4]),
+        .I3(\\m_payload_i_reg[46] [5]),
+        .O(S[1]));
+  LUT4 #(
+    .INIT(16\'h0009)) 
+    \\axaddr_incr[0]_i_18 
+       (.I0(\\m_payload_i_reg[46] [0]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(\\m_payload_i_reg[46] [4]),
+        .I3(\\m_payload_i_reg[46] [5]),
+        .O(S[0]));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_2 
+       (.I0(\\m_payload_i_reg[11] [3]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[3]),
+        .O(\\axaddr_incr[4]_i_2_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_3 
+       (.I0(\\m_payload_i_reg[11] [2]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[2]),
+        .O(\\axaddr_incr[4]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_4 
+       (.I0(\\m_payload_i_reg[11] [1]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[1]),
+        .O(\\axaddr_incr[4]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_5 
+       (.I0(\\m_payload_i_reg[11] [0]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[0]),
+        .O(\\axaddr_incr[4]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_2 
+       (.I0(\\m_payload_i_reg[11] [7]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[7]),
+        .O(\\axaddr_incr[8]_i_2_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_3 
+       (.I0(\\m_payload_i_reg[11] [6]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[6]),
+        .O(\\axaddr_incr[8]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_4 
+       (.I0(\\m_payload_i_reg[11] [5]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[5]),
+        .O(\\axaddr_incr[8]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_5 
+       (.I0(\\m_payload_i_reg[11] [4]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[4]),
+        .O(\\axaddr_incr[8]_i_5_n_0 ));
+  FDRE \\axaddr_incr_reg[0] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(O[0]),
+        .Q(\\axaddr_incr_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[10] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[8]_i_1_n_5 ),
+        .Q(axaddr_incr_reg[6]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[11] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[8]_i_1_n_4 ),
+        .Q(axaddr_incr_reg[7]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[1] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(O[1]),
+        .Q(\\axaddr_incr_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[2] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(O[2]),
+        .Q(\\axaddr_incr_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[3] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(O[3]),
+        .Q(\\axaddr_incr_reg[3]_0 [3]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[4] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[4]_i_1_n_7 ),
+        .Q(axaddr_incr_reg[0]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_incr_reg[4]_i_1 
+       (.CI(CO),
+        .CO({\\axaddr_incr_reg[4]_i_1_n_0 ,\\axaddr_incr_reg[4]_i_1_n_1 ,\\axaddr_incr_reg[4]_i_1_n_2 ,\\axaddr_incr_reg[4]_i_1_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_incr_reg[4]_i_1_n_4 ,\\axaddr_incr_reg[4]_i_1_n_5 ,\\axaddr_incr_reg[4]_i_1_n_6 ,\\axaddr_incr_reg[4]_i_1_n_7 }),
+        .S({\\axaddr_incr[4]_i_2_n_0 ,\\axaddr_incr[4]_i_3_n_0 ,\\axaddr_incr[4]_i_4_n_0 ,\\axaddr_incr[4]_i_5_n_0 }));
+  FDRE \\axaddr_incr_reg[5] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[4]_i_1_n_6 ),
+        .Q(axaddr_incr_reg[1]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[6] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[4]_i_1_n_5 ),
+        .Q(axaddr_incr_reg[2]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[7] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[4]_i_1_n_4 ),
+        .Q(axaddr_incr_reg[3]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[8] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[8]_i_1_n_7 ),
+        .Q(axaddr_incr_reg[4]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_incr_reg[8]_i_1 
+       (.CI(\\axaddr_incr_reg[4]_i_1_n_0 ),
+        .CO({\\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED [3],\\axaddr_incr_reg[8]_i_1_n_1 ,\\axaddr_incr_reg[8]_i_1_n_2 ,\\axaddr_incr_reg[8]_i_1_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_incr_reg[8]_i_1_n_4 ,\\axaddr_incr_reg[8]_i_1_n_5 ,\\axaddr_incr_reg[8]_i_1_n_6 ,\\axaddr_incr_reg[8]_i_1_n_7 }),
+        .S({\\axaddr_incr[8]_i_2_n_0 ,\\axaddr_incr[8]_i_3_n_0 ,\\axaddr_incr[8]_i_4_n_0 ,\\axaddr_incr[8]_i_5_n_0 }));
+  FDRE \\axaddr_incr_reg[9] 
+       (.C(aclk),
+        .CE(\\axaddr_incr[0]_i_1_n_0 ),
+        .D(\\axaddr_incr_reg[8]_i_1_n_6 ),
+        .Q(axaddr_incr_reg[5]),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h44444F4444444444)) 
+    \\axlen_cnt[0]_i_1__1 
+       (.I0(\\axlen_cnt_reg_n_0_[0] ),
+        .I1(\\axlen_cnt_reg[0]_0 ),
+        .I2(Q[1]),
+        .I3(si_rs_awvalid),
+        .I4(Q[0]),
+        .I5(\\m_payload_i_reg[46] [6]),
+        .O(\\axlen_cnt[0]_i_1__1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hF88F8888)) 
+    \\axlen_cnt[1]_i_1 
+       (.I0(E),
+        .I1(\\m_payload_i_reg[46] [7]),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(\\axlen_cnt_reg[0]_0 ),
+        .O(p_1_in[1]));
+  LUT6 #(
+    .INIT(64\'hF8F8F88F88888888)) 
+    \\axlen_cnt[2]_i_1 
+       (.I0(E),
+        .I1(\\m_payload_i_reg[46] [8]),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(\\axlen_cnt_reg_n_0_[1] ),
+        .I5(\\axlen_cnt_reg[0]_0 ),
+        .O(p_1_in[2]));
+  LUT6 #(
+    .INIT(64\'hAAA90000FFFFFFFF)) 
+    \\axlen_cnt[3]_i_2 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(\\axlen_cnt_reg[0]_0 ),
+        .I5(\\m_payload_i_reg[47] ),
+        .O(\\axlen_cnt[3]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair107"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAAAAA9)) 
+    \\axlen_cnt[4]_i_1 
+       (.I0(\\axlen_cnt_reg_n_0_[4] ),
+        .I1(\\axlen_cnt_reg_n_0_[3] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .O(\\axlen_cnt[4]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAAAAA9)) 
+    \\axlen_cnt[5]_i_1 
+       (.I0(\\axlen_cnt_reg_n_0_[5] ),
+        .I1(\\axlen_cnt_reg_n_0_[0] ),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(\\axlen_cnt_reg_n_0_[4] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[5]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair108"" *) 
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axlen_cnt[6]_i_1 
+       (.I0(\\axlen_cnt_reg_n_0_[6] ),
+        .I1(\\axlen_cnt_reg_n_0_[5] ),
+        .I2(\\axlen_cnt[7]_i_3_n_0 ),
+        .O(\\axlen_cnt[6]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair108"" *) 
+  LUT4 #(
+    .INIT(16\'hA9AA)) 
+    \\axlen_cnt[7]_i_2 
+       (.I0(\\axlen_cnt_reg_n_0_[7] ),
+        .I1(\\axlen_cnt_reg_n_0_[5] ),
+        .I2(\\axlen_cnt_reg_n_0_[6] ),
+        .I3(\\axlen_cnt[7]_i_3_n_0 ),
+        .O(\\axlen_cnt[7]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair107"" *) 
+  LUT5 #(
+    .INIT(32\'h00000001)) 
+    \\axlen_cnt[7]_i_3 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[4] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[2] ),
+        .I4(\\axlen_cnt_reg_n_0_[0] ),
+        .O(\\axlen_cnt[7]_i_3_n_0 ));
+  FDRE \\axlen_cnt_reg[0] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[0]_i_1__1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[1] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(p_1_in[1]),
+        .Q(\\axlen_cnt_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[2] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(p_1_in[2]),
+        .Q(\\axlen_cnt_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[3] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[3]_i_2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[4] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[4]_i_1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[4] ),
+        .R(\\state_reg[0]_0 ));
+  FDRE \\axlen_cnt_reg[5] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[5]_i_1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[5] ),
+        .R(\\state_reg[0]_0 ));
+  FDRE \\axlen_cnt_reg[6] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[6]_i_1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[6] ),
+        .R(\\state_reg[0]_0 ));
+  FDRE \\axlen_cnt_reg[7] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[7]_i_2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[7] ),
+        .R(\\state_reg[0]_0 ));
+  LUT5 #(
+    .INIT(32\'h55545555)) 
+    next_pending_r_i_4__0
+       (.I0(E),
+        .I1(\\axlen_cnt_reg_n_0_[7] ),
+        .I2(\\axlen_cnt_reg_n_0_[6] ),
+        .I3(\\axlen_cnt_reg_n_0_[5] ),
+        .I4(next_pending_r_i_5_n_0),
+        .O(\\axlen_cnt_reg[0]_0 ));
+  LUT4 #(
+    .INIT(16\'h0001)) 
+    next_pending_r_i_5
+       (.I0(\\axlen_cnt_reg_n_0_[2] ),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(\\axlen_cnt_reg_n_0_[4] ),
+        .I3(\\axlen_cnt_reg_n_0_[3] ),
+        .O(next_pending_r_i_5_n_0));
+  FDRE next_pending_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(incr_next_pending),
+        .Q(next_pending_r_reg_0),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_reg_0),
+        .Q(\\axaddr_incr_reg[11]_0 ),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_incr_cmd"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2
+   (incr_next_pending,
+    \\axaddr_incr_reg[3]_0 ,
+    axaddr_incr_reg,
+    \\axaddr_incr_reg[11]_0 ,
+    Q,
+    \\axlen_cnt_reg[1]_0 ,
+    S,
+    aclk,
+    sel_first_reg_0,
+    O,
+    sel_first_reg_1,
+    \\m_payload_i_reg[47] ,
+    E,
+    CO,
+    \\m_payload_i_reg[46] ,
+    \\state_reg[1]_rep ,
+    \\m_payload_i_reg[44] ,
+    \\m_payload_i_reg[3] ,
+    \\m_payload_i_reg[11] ,
+    m_valid_i_reg,
+    D,
+    \\state_reg[1] ,
+    m_axi_arready,
+    \\state_reg[1]_0 );
+  output incr_next_pending;
+  output [3:0]\\axaddr_incr_reg[3]_0 ;
+  output [7:0]axaddr_incr_reg;
+  output \\axaddr_incr_reg[11]_0 ;
+  output [0:0]Q;
+  output \\axlen_cnt_reg[1]_0 ;
+  output [3:0]S;
+  input aclk;
+  input sel_first_reg_0;
+  input [3:0]O;
+  input sel_first_reg_1;
+  input \\m_payload_i_reg[47] ;
+  input [0:0]E;
+  input [0:0]CO;
+  input [7:0]\\m_payload_i_reg[46] ;
+  input \\state_reg[1]_rep ;
+  input \\m_payload_i_reg[44] ;
+  input [3:0]\\m_payload_i_reg[3] ;
+  input [3:0]\\m_payload_i_reg[11] ;
+  input [0:0]m_valid_i_reg;
+  input [0:0]D;
+  input \\state_reg[1] ;
+  input m_axi_arready;
+  input [1:0]\\state_reg[1]_0 ;
+
+  wire [0:0]CO;
+  wire [0:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [0:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire \\axaddr_incr[4]_i_2__0_n_0 ;
+  wire \\axaddr_incr[4]_i_3__0_n_0 ;
+  wire \\axaddr_incr[4]_i_4__0_n_0 ;
+  wire \\axaddr_incr[4]_i_5__0_n_0 ;
+  wire \\axaddr_incr[8]_i_2__0_n_0 ;
+  wire \\axaddr_incr[8]_i_3__0_n_0 ;
+  wire \\axaddr_incr[8]_i_4__0_n_0 ;
+  wire \\axaddr_incr[8]_i_5__0_n_0 ;
+  wire [7:0]axaddr_incr_reg;
+  wire \\axaddr_incr_reg[11]_0 ;
+  wire [3:0]\\axaddr_incr_reg[3]_0 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_0 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_1 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_2 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_3 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_4 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_5 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_6 ;
+  wire \\axaddr_incr_reg[4]_i_1__0_n_7 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_1 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_2 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_3 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_4 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_5 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_6 ;
+  wire \\axaddr_incr_reg[8]_i_1__0_n_7 ;
+  wire \\axlen_cnt[1]_i_1__1_n_0 ;
+  wire \\axlen_cnt[2]_i_1__1_n_0 ;
+  wire \\axlen_cnt[3]_i_2__0_n_0 ;
+  wire \\axlen_cnt[4]_i_1__0_n_0 ;
+  wire \\axlen_cnt[5]_i_1__0_n_0 ;
+  wire \\axlen_cnt[6]_i_1__0_n_0 ;
+  wire \\axlen_cnt[7]_i_2__0_n_0 ;
+  wire \\axlen_cnt[7]_i_3__0_n_0 ;
+  wire \\axlen_cnt_reg[1]_0 ;
+  wire \\axlen_cnt_reg_n_0_[1] ;
+  wire \\axlen_cnt_reg_n_0_[2] ;
+  wire \\axlen_cnt_reg_n_0_[3] ;
+  wire \\axlen_cnt_reg_n_0_[4] ;
+  wire \\axlen_cnt_reg_n_0_[5] ;
+  wire \\axlen_cnt_reg_n_0_[6] ;
+  wire \\axlen_cnt_reg_n_0_[7] ;
+  wire incr_next_pending;
+  wire m_axi_arready;
+  wire [3:0]\\m_payload_i_reg[11] ;
+  wire [3:0]\\m_payload_i_reg[3] ;
+  wire \\m_payload_i_reg[44] ;
+  wire [7:0]\\m_payload_i_reg[46] ;
+  wire \\m_payload_i_reg[47] ;
+  wire [0:0]m_valid_i_reg;
+  wire next_pending_r_i_2__1_n_0;
+  wire next_pending_r_i_4_n_0;
+  wire next_pending_r_reg_n_0;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire \\state_reg[1] ;
+  wire [1:0]\\state_reg[1]_0 ;
+  wire \\state_reg[1]_rep ;
+  wire [3:3]\\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED ;
+
+  LUT6 #(
+    .INIT(64\'hAAAA6AAAAAAAAAAA)) 
+    \\axaddr_incr[0]_i_15 
+       (.I0(\\m_payload_i_reg[46] [3]),
+        .I1(\\m_payload_i_reg[46] [4]),
+        .I2(\\m_payload_i_reg[46] [5]),
+        .I3(m_axi_arready),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\state_reg[1]_0 [0]),
+        .O(S[3]));
+  LUT6 #(
+    .INIT(64\'h2A2A262A2A2A2A2A)) 
+    \\axaddr_incr[0]_i_16 
+       (.I0(\\m_payload_i_reg[46] [2]),
+        .I1(\\m_payload_i_reg[46] [5]),
+        .I2(\\m_payload_i_reg[46] [4]),
+        .I3(m_axi_arready),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\state_reg[1]_0 [0]),
+        .O(S[2]));
+  LUT6 #(
+    .INIT(64\'h0A0A060A0A0A0A0A)) 
+    \\axaddr_incr[0]_i_17 
+       (.I0(\\m_payload_i_reg[46] [1]),
+        .I1(\\m_payload_i_reg[46] [4]),
+        .I2(\\m_payload_i_reg[46] [5]),
+        .I3(m_axi_arready),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\state_reg[1]_0 [0]),
+        .O(S[1]));
+  LUT6 #(
+    .INIT(64\'h0202010202020202)) 
+    \\axaddr_incr[0]_i_18 
+       (.I0(\\m_payload_i_reg[46] [0]),
+        .I1(\\m_payload_i_reg[46] [4]),
+        .I2(\\m_payload_i_reg[46] [5]),
+        .I3(m_axi_arready),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\state_reg[1]_0 [0]),
+        .O(S[0]));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_2__0 
+       (.I0(\\m_payload_i_reg[3] [3]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[3]),
+        .O(\\axaddr_incr[4]_i_2__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_3__0 
+       (.I0(\\m_payload_i_reg[3] [2]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[2]),
+        .O(\\axaddr_incr[4]_i_3__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_4__0 
+       (.I0(\\m_payload_i_reg[3] [1]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[1]),
+        .O(\\axaddr_incr[4]_i_4__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[4]_i_5__0 
+       (.I0(\\m_payload_i_reg[3] [0]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[0]),
+        .O(\\axaddr_incr[4]_i_5__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_2__0 
+       (.I0(\\m_payload_i_reg[11] [3]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[7]),
+        .O(\\axaddr_incr[8]_i_2__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_3__0 
+       (.I0(\\m_payload_i_reg[11] [2]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[6]),
+        .O(\\axaddr_incr[8]_i_3__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_4__0 
+       (.I0(\\m_payload_i_reg[11] [1]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[5]),
+        .O(\\axaddr_incr[8]_i_4__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_incr[8]_i_5__0 
+       (.I0(\\m_payload_i_reg[11] [0]),
+        .I1(\\axaddr_incr_reg[11]_0 ),
+        .I2(axaddr_incr_reg[4]),
+        .O(\\axaddr_incr[8]_i_5__0_n_0 ));
+  FDRE \\axaddr_incr_reg[0] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(O[0]),
+        .Q(\\axaddr_incr_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[10] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[8]_i_1__0_n_5 ),
+        .Q(axaddr_incr_reg[6]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[11] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[8]_i_1__0_n_4 ),
+        .Q(axaddr_incr_reg[7]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[1] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(O[1]),
+        .Q(\\axaddr_incr_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[2] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(O[2]),
+        .Q(\\axaddr_incr_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[3] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(O[3]),
+        .Q(\\axaddr_incr_reg[3]_0 [3]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[4] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[4]_i_1__0_n_7 ),
+        .Q(axaddr_incr_reg[0]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_incr_reg[4]_i_1__0 
+       (.CI(CO),
+        .CO({\\axaddr_incr_reg[4]_i_1__0_n_0 ,\\axaddr_incr_reg[4]_i_1__0_n_1 ,\\axaddr_incr_reg[4]_i_1__0_n_2 ,\\axaddr_incr_reg[4]_i_1__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_incr_reg[4]_i_1__0_n_4 ,\\axaddr_incr_reg[4]_i_1__0_n_5 ,\\axaddr_incr_reg[4]_i_1__0_n_6 ,\\axaddr_incr_reg[4]_i_1__0_n_7 }),
+        .S({\\axaddr_incr[4]_i_2__0_n_0 ,\\axaddr_incr[4]_i_3__0_n_0 ,\\axaddr_incr[4]_i_4__0_n_0 ,\\axaddr_incr[4]_i_5__0_n_0 }));
+  FDRE \\axaddr_incr_reg[5] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[4]_i_1__0_n_6 ),
+        .Q(axaddr_incr_reg[1]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[6] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[4]_i_1__0_n_5 ),
+        .Q(axaddr_incr_reg[2]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[7] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[4]_i_1__0_n_4 ),
+        .Q(axaddr_incr_reg[3]),
+        .R(1\'b0));
+  FDRE \\axaddr_incr_reg[8] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[8]_i_1__0_n_7 ),
+        .Q(axaddr_incr_reg[4]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_incr_reg[8]_i_1__0 
+       (.CI(\\axaddr_incr_reg[4]_i_1__0_n_0 ),
+        .CO({\\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED [3],\\axaddr_incr_reg[8]_i_1__0_n_1 ,\\axaddr_incr_reg[8]_i_1__0_n_2 ,\\axaddr_incr_reg[8]_i_1__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_incr_reg[8]_i_1__0_n_4 ,\\axaddr_incr_reg[8]_i_1__0_n_5 ,\\axaddr_incr_reg[8]_i_1__0_n_6 ,\\axaddr_incr_reg[8]_i_1__0_n_7 }),
+        .S({\\axaddr_incr[8]_i_2__0_n_0 ,\\axaddr_incr[8]_i_3__0_n_0 ,\\axaddr_incr[8]_i_4__0_n_0 ,\\axaddr_incr[8]_i_5__0_n_0 }));
+  FDRE \\axaddr_incr_reg[9] 
+       (.C(aclk),
+        .CE(sel_first_reg_0),
+        .D(\\axaddr_incr_reg[8]_i_1__0_n_6 ),
+        .Q(axaddr_incr_reg[5]),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hF88F8888)) 
+    \\axlen_cnt[1]_i_1__1 
+       (.I0(E),
+        .I1(\\m_payload_i_reg[46] [6]),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(Q),
+        .I4(\\axlen_cnt_reg[1]_0 ),
+        .O(\\axlen_cnt[1]_i_1__1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hF8F8F88F88888888)) 
+    \\axlen_cnt[2]_i_1__1 
+       (.I0(E),
+        .I1(\\m_payload_i_reg[46] [7]),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(Q),
+        .I4(\\axlen_cnt_reg_n_0_[1] ),
+        .I5(\\axlen_cnt_reg[1]_0 ),
+        .O(\\axlen_cnt[2]_i_1__1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAA90000FFFFFFFF)) 
+    \\axlen_cnt[3]_i_2__0 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(Q),
+        .I4(\\axlen_cnt_reg[1]_0 ),
+        .I5(\\m_payload_i_reg[47] ),
+        .O(\\axlen_cnt[3]_i_2__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT5 #(
+    .INIT(32\'h55545555)) 
+    \\axlen_cnt[3]_i_3__0 
+       (.I0(E),
+        .I1(\\axlen_cnt_reg_n_0_[6] ),
+        .I2(\\axlen_cnt_reg_n_0_[5] ),
+        .I3(\\axlen_cnt_reg_n_0_[7] ),
+        .I4(next_pending_r_i_4_n_0),
+        .O(\\axlen_cnt_reg[1]_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAAAAA9)) 
+    \\axlen_cnt[4]_i_1__0 
+       (.I0(\\axlen_cnt_reg_n_0_[4] ),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(Q),
+        .I3(\\axlen_cnt_reg_n_0_[2] ),
+        .I4(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[4]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAAAAA9)) 
+    \\axlen_cnt[5]_i_1__0 
+       (.I0(\\axlen_cnt_reg_n_0_[5] ),
+        .I1(Q),
+        .I2(\\axlen_cnt_reg_n_0_[3] ),
+        .I3(\\axlen_cnt_reg_n_0_[2] ),
+        .I4(\\axlen_cnt_reg_n_0_[4] ),
+        .I5(\\axlen_cnt_reg_n_0_[1] ),
+        .O(\\axlen_cnt[5]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT3 #(
+    .INIT(8\'hA6)) 
+    \\axlen_cnt[6]_i_1__0 
+       (.I0(\\axlen_cnt_reg_n_0_[6] ),
+        .I1(\\axlen_cnt[7]_i_3__0_n_0 ),
+        .I2(\\axlen_cnt_reg_n_0_[5] ),
+        .O(\\axlen_cnt[6]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT4 #(
+    .INIT(16\'hA9AA)) 
+    \\axlen_cnt[7]_i_2__0 
+       (.I0(\\axlen_cnt_reg_n_0_[7] ),
+        .I1(\\axlen_cnt_reg_n_0_[5] ),
+        .I2(\\axlen_cnt_reg_n_0_[6] ),
+        .I3(\\axlen_cnt[7]_i_3__0_n_0 ),
+        .O(\\axlen_cnt[7]_i_2__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT5 #(
+    .INIT(32\'h00000001)) 
+    \\axlen_cnt[7]_i_3__0 
+       (.I0(\\axlen_cnt_reg_n_0_[1] ),
+        .I1(\\axlen_cnt_reg_n_0_[4] ),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\axlen_cnt_reg_n_0_[3] ),
+        .I4(Q),
+        .O(\\axlen_cnt[7]_i_3__0_n_0 ));
+  FDRE \\axlen_cnt_reg[0] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(D),
+        .Q(Q),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[1] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[1]_i_1__1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[2] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[2]_i_1__1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[3] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[3]_i_2__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[4] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[4]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[4] ),
+        .R(\\state_reg[1] ));
+  FDRE \\axlen_cnt_reg[5] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[5]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[5] ),
+        .R(\\state_reg[1] ));
+  FDRE \\axlen_cnt_reg[6] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[6]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[6] ),
+        .R(\\state_reg[1] ));
+  FDRE \\axlen_cnt_reg[7] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[7]_i_2__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[7] ),
+        .R(\\state_reg[1] ));
+  LUT5 #(
+    .INIT(32\'hFFFF505C)) 
+    next_pending_r_i_1__2
+       (.I0(next_pending_r_i_2__1_n_0),
+        .I1(next_pending_r_reg_n_0),
+        .I2(\\state_reg[1]_rep ),
+        .I3(E),
+        .I4(\\m_payload_i_reg[44] ),
+        .O(incr_next_pending));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT4 #(
+    .INIT(16\'h0002)) 
+    next_pending_r_i_2__1
+       (.I0(next_pending_r_i_4_n_0),
+        .I1(\\axlen_cnt_reg_n_0_[7] ),
+        .I2(\\axlen_cnt_reg_n_0_[5] ),
+        .I3(\\axlen_cnt_reg_n_0_[6] ),
+        .O(next_pending_r_i_2__1_n_0));
+  LUT4 #(
+    .INIT(16\'h0001)) 
+    next_pending_r_i_4
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[4] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .O(next_pending_r_i_4_n_0));
+  FDRE next_pending_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(incr_next_pending),
+        .Q(next_pending_r_reg_n_0),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_reg_1),
+        .Q(\\axaddr_incr_reg[11]_0 ),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_r_channel
+   (m_valid_i_reg,
+    \\state_reg[1]_rep ,
+    m_axi_rready,
+    out,
+    \\skid_buffer_reg[46] ,
+    r_push,
+    aclk,
+    r_rlast,
+    si_rs_rready,
+    m_axi_rvalid,
+    in,
+    areset_d1,
+    D);
+  output m_valid_i_reg;
+  output \\state_reg[1]_rep ;
+  output m_axi_rready;
+  output [33:0]out;
+  output [12:0]\\skid_buffer_reg[46] ;
+  input r_push;
+  input aclk;
+  input r_rlast;
+  input si_rs_rready;
+  input m_axi_rvalid;
+  input [33:0]in;
+  input areset_d1;
+  input [11:0]D;
+
+  wire [11:0]D;
+  wire aclk;
+  wire areset_d1;
+  wire [33:0]in;
+  wire m_axi_rready;
+  wire m_axi_rvalid;
+  wire m_valid_i_reg;
+  wire [33:0]out;
+  wire r_push;
+  wire r_push_r;
+  wire r_rlast;
+  wire rd_data_fifo_0_n_0;
+  wire rd_data_fifo_0_n_3;
+  wire si_rs_rready;
+  wire [12:0]\\skid_buffer_reg[46] ;
+  wire \\state_reg[1]_rep ;
+  wire [12:0]trans_in;
+  wire transaction_fifo_0_n_1;
+
+  FDRE \\r_arid_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[0]),
+        .Q(trans_in[1]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[10] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[10]),
+        .Q(trans_in[11]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[11] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[11]),
+        .Q(trans_in[12]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[1]),
+        .Q(trans_in[2]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[2]),
+        .Q(trans_in[3]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[3]),
+        .Q(trans_in[4]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[4]),
+        .Q(trans_in[5]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[5] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[5]),
+        .Q(trans_in[6]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[6] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[6]),
+        .Q(trans_in[7]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[7] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[7]),
+        .Q(trans_in[8]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[8] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[8]),
+        .Q(trans_in[9]),
+        .R(1\'b0));
+  FDRE \\r_arid_r_reg[9] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[9]),
+        .Q(trans_in[10]),
+        .R(1\'b0));
+  FDRE r_push_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(r_push),
+        .Q(r_push_r),
+        .R(1\'b0));
+  FDRE r_rlast_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(r_rlast),
+        .Q(trans_in[0]),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1 rd_data_fifo_0
+       (.aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\cnt_read_reg[1]_rep__3_0 (rd_data_fifo_0_n_0),
+        .\\cnt_read_reg[2]_rep__0_0 (transaction_fifo_0_n_1),
+        .in(in),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_valid_i_reg(m_valid_i_reg),
+        .out(out),
+        .si_rs_rready(si_rs_rready),
+        .\\state_reg[1]_rep (rd_data_fifo_0_n_3));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2 transaction_fifo_0
+       (.aclk(aclk),
+        .areset_d1(areset_d1),
+        .\\cnt_read_reg[0]_rep__3 (rd_data_fifo_0_n_3),
+        .\\cnt_read_reg[3]_rep__2 (m_valid_i_reg),
+        .in(trans_in),
+        .m_valid_i_reg(transaction_fifo_0_n_1),
+        .r_push_r(r_push_r),
+        .s_ready_i_reg(rd_data_fifo_0_n_0),
+        .si_rs_rready(si_rs_rready),
+        .\\skid_buffer_reg[46] (\\skid_buffer_reg[46] ),
+        .\\state_reg[1]_rep (\\state_reg[1]_rep ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm
+   (\\axlen_cnt_reg[7] ,
+    Q,
+    D,
+    \\axaddr_offset_r_reg[0] ,
+    \\axlen_cnt_reg[0] ,
+    \\wrap_second_len_r_reg[3] ,
+    E,
+    s_axburst_eq0_reg,
+    wrap_next_pending,
+    sel_first_i,
+    s_axburst_eq1_reg,
+    r_push_r_reg,
+    \\m_payload_i_reg[0] ,
+    \\m_payload_i_reg[0]_0 ,
+    \\axlen_cnt_reg[3] ,
+    \\axaddr_incr_reg[11] ,
+    m_axi_arvalid,
+    m_valid_i0,
+    \\m_payload_i_reg[0]_1 ,
+    sel_first_reg,
+    sel_first_reg_0,
+    m_axi_arready,
+    si_rs_arvalid,
+    \\axlen_cnt_reg[6] ,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\axaddr_offset_r_reg[3] ,
+    \\cnt_read_reg[1]_rep__0 ,
+    s_axburst_eq1_reg_0,
+    \\m_payload_i_reg[44] ,
+    \\axlen_cnt_reg[0]_0 ,
+    \\wrap_second_len_r_reg[2] ,
+    \\m_payload_i_reg[35] ,
+    \\m_payload_i_reg[47] ,
+    \\m_payload_i_reg[35]_0 ,
+    \\axaddr_offset_r_reg[0]_0 ,
+    \\m_payload_i_reg[3] ,
+    incr_next_pending,
+    \\m_payload_i_reg[44]_0 ,
+    \\state_reg[0]_0 ,
+    next_pending_r_reg,
+    areset_d1,
+    sel_first_reg_1,
+    sel_first_reg_2,
+    s_axi_arvalid,
+    s_ready_i_reg,
+    sel_first_reg_3,
+    aclk);
+  output \\axlen_cnt_reg[7] ;
+  output [1:0]Q;
+  output [1:0]D;
+  output [0:0]\\axaddr_offset_r_reg[0] ;
+  output [0:0]\\axlen_cnt_reg[0] ;
+  output [1:0]\\wrap_second_len_r_reg[3] ;
+  output [0:0]E;
+  output s_axburst_eq0_reg;
+  output wrap_next_pending;
+  output sel_first_i;
+  output s_axburst_eq1_reg;
+  output r_push_r_reg;
+  output \\m_payload_i_reg[0] ;
+  output \\m_payload_i_reg[0]_0 ;
+  output [0:0]\\axlen_cnt_reg[3] ;
+  output \\axaddr_incr_reg[11] ;
+  output m_axi_arvalid;
+  output m_valid_i0;
+  output [0:0]\\m_payload_i_reg[0]_1 ;
+  output sel_first_reg;
+  output sel_first_reg_0;
+  input m_axi_arready;
+  input si_rs_arvalid;
+  input \\axlen_cnt_reg[6] ;
+  input [1:0]\\wrap_second_len_r_reg[3]_0 ;
+  input \\axaddr_offset_r_reg[3] ;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input s_axburst_eq1_reg_0;
+  input [1:0]\\m_payload_i_reg[44] ;
+  input [0:0]\\axlen_cnt_reg[0]_0 ;
+  input [1:0]\\wrap_second_len_r_reg[2] ;
+  input \\m_payload_i_reg[35] ;
+  input [1:0]\\m_payload_i_reg[47] ;
+  input \\m_payload_i_reg[35]_0 ;
+  input [0:0]\\axaddr_offset_r_reg[0]_0 ;
+  input \\m_payload_i_reg[3] ;
+  input incr_next_pending;
+  input \\m_payload_i_reg[44]_0 ;
+  input \\state_reg[0]_0 ;
+  input next_pending_r_reg;
+  input areset_d1;
+  input sel_first_reg_1;
+  input sel_first_reg_2;
+  input s_axi_arvalid;
+  input s_ready_i_reg;
+  input sel_first_reg_3;
+  input aclk;
+
+  wire [1:0]D;
+  wire [0:0]E;
+  wire [1:0]Q;
+  wire aclk;
+  wire areset_d1;
+  wire \\axaddr_incr_reg[11] ;
+  wire [0:0]\\axaddr_offset_r_reg[0] ;
+  wire [0:0]\\axaddr_offset_r_reg[0]_0 ;
+  wire \\axaddr_offset_r_reg[3] ;
+  wire [0:0]\\axlen_cnt_reg[0] ;
+  wire [0:0]\\axlen_cnt_reg[0]_0 ;
+  wire [0:0]\\axlen_cnt_reg[3] ;
+  wire \\axlen_cnt_reg[6] ;
+  wire \\axlen_cnt_reg[7] ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire incr_next_pending;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire \\m_payload_i_reg[0] ;
+  wire \\m_payload_i_reg[0]_0 ;
+  wire [0:0]\\m_payload_i_reg[0]_1 ;
+  wire \\m_payload_i_reg[35] ;
+  wire \\m_payload_i_reg[35]_0 ;
+  wire \\m_payload_i_reg[3] ;
+  wire [1:0]\\m_payload_i_reg[44] ;
+  wire \\m_payload_i_reg[44]_0 ;
+  wire [1:0]\\m_payload_i_reg[47] ;
+  wire m_valid_i0;
+  wire next_pending_r_reg;
+  wire [1:0]next_state;
+  wire r_push_r_reg;
+  wire s_axburst_eq0_reg;
+  wire s_axburst_eq1_reg;
+  wire s_axburst_eq1_reg_0;
+  wire s_axi_arvalid;
+  wire s_ready_i_reg;
+  wire sel_first_i;
+  wire sel_first_reg;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire sel_first_reg_2;
+  wire sel_first_reg_3;
+  wire si_rs_arvalid;
+  wire \\state_reg[0]_0 ;
+  wire \\wrap_cnt_r[3]_i_2__0_n_0 ;
+  wire wrap_next_pending;
+  wire [1:0]\\wrap_second_len_r_reg[2] ;
+  wire [1:0]\\wrap_second_len_r_reg[3] ;
+  wire [1:0]\\wrap_second_len_r_reg[3]_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'hAEAA)) 
+    \\axaddr_incr[0]_i_1__0 
+       (.I0(sel_first_reg_2),
+        .I1(\\m_payload_i_reg[0]_0 ),
+        .I2(\\m_payload_i_reg[0] ),
+        .I3(m_axi_arready),
+        .O(\\axaddr_incr_reg[11] ));
+  LUT6 #(
+    .INIT(64\'hAAAAACAAAAAAA0AA)) 
+    \\axaddr_offset_r[0]_i_1__0 
+       (.I0(\\axaddr_offset_r_reg[0]_0 ),
+        .I1(\\m_payload_i_reg[44] [1]),
+        .I2(Q[0]),
+        .I3(si_rs_arvalid),
+        .I4(Q[1]),
+        .I5(\\m_payload_i_reg[3] ),
+        .O(\\axaddr_offset_r_reg[0] ));
+  LUT6 #(
+    .INIT(64\'h0400FFFF04000400)) 
+    \\axlen_cnt[0]_i_1 
+       (.I0(Q[1]),
+        .I1(si_rs_arvalid),
+        .I2(Q[0]),
+        .I3(\\m_payload_i_reg[44] [1]),
+        .I4(\\axlen_cnt_reg[0]_0 ),
+        .I5(\\axlen_cnt_reg[6] ),
+        .O(\\axlen_cnt_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h0E02)) 
+    \\axlen_cnt[3]_i_1 
+       (.I0(si_rs_arvalid),
+        .I1(\\m_payload_i_reg[0]_0 ),
+        .I2(\\m_payload_i_reg[0] ),
+        .I3(m_axi_arready),
+        .O(\\axlen_cnt_reg[3] ));
+  LUT5 #(
+    .INIT(32\'h00002320)) 
+    \\axlen_cnt[7]_i_1 
+       (.I0(m_axi_arready),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(si_rs_arvalid),
+        .I4(\\axlen_cnt_reg[6] ),
+        .O(\\axlen_cnt_reg[7] ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    m_axi_arvalid_INST_0
+       (.I0(\\m_payload_i_reg[0]_0 ),
+        .I1(\\m_payload_i_reg[0] ),
+        .O(m_axi_arvalid));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'h8F)) 
+    \\m_payload_i[31]_i_1__0 
+       (.I0(\\m_payload_i_reg[0] ),
+        .I1(\\m_payload_i_reg[0]_0 ),
+        .I2(si_rs_arvalid),
+        .O(\\m_payload_i_reg[0]_1 ));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'hFF70FFFF)) 
+    m_valid_i_i_1__1
+       (.I0(\\m_payload_i_reg[0] ),
+        .I1(\\m_payload_i_reg[0]_0 ),
+        .I2(si_rs_arvalid),
+        .I3(s_axi_arvalid),
+        .I4(s_ready_i_reg),
+        .O(m_valid_i0));
+  LUT5 #(
+    .INIT(32\'hFFABEEAA)) 
+    next_pending_r_i_1__1
+       (.I0(\\m_payload_i_reg[44]_0 ),
+        .I1(r_push_r_reg),
+        .I2(E),
+        .I3(\\state_reg[0]_0 ),
+        .I4(next_pending_r_reg),
+        .O(wrap_next_pending));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h20)) 
+    r_push_r_i_1
+       (.I0(m_axi_arready),
+        .I1(\\m_payload_i_reg[0] ),
+        .I2(\\m_payload_i_reg[0]_0 ),
+        .O(r_push_r_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    s_axburst_eq0_i_1__0
+       (.I0(wrap_next_pending),
+        .I1(\\m_payload_i_reg[44] [0]),
+        .I2(sel_first_i),
+        .I3(incr_next_pending),
+        .O(s_axburst_eq0_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT4 #(
+    .INIT(16\'hABA8)) 
+    s_axburst_eq1_i_1__0
+       (.I0(wrap_next_pending),
+        .I1(\\m_payload_i_reg[44] [0]),
+        .I2(sel_first_i),
+        .I3(incr_next_pending),
+        .O(s_axburst_eq1_reg));
+  LUT6 #(
+    .INIT(64\'hFFCFFFFFCCCCCCEE)) 
+    sel_first_i_1__0
+       (.I0(si_rs_arvalid),
+        .I1(areset_d1),
+        .I2(m_axi_arready),
+        .I3(\\m_payload_i_reg[0] ),
+        .I4(\\m_payload_i_reg[0]_0 ),
+        .I5(sel_first_reg_1),
+        .O(sel_first_i));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFC4C4CFCC)) 
+    sel_first_i_1__3
+       (.I0(m_axi_arready),
+        .I1(sel_first_reg_2),
+        .I2(Q[1]),
+        .I3(si_rs_arvalid),
+        .I4(Q[0]),
+        .I5(areset_d1),
+        .O(sel_first_reg));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFC4C4CFCC)) 
+    sel_first_i_1__4
+       (.I0(m_axi_arready),
+        .I1(sel_first_reg_3),
+        .I2(Q[1]),
+        .I3(si_rs_arvalid),
+        .I4(Q[0]),
+        .I5(areset_d1),
+        .O(sel_first_reg_0));
+  LUT6 #(
+    .INIT(64\'h000033333FFF2222)) 
+    \\state[0]_i_1__0 
+       (.I0(si_rs_arvalid),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(s_axburst_eq1_reg_0),
+        .I3(m_axi_arready),
+        .I4(Q[0]),
+        .I5(Q[1]),
+        .O(next_state[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h0FC00040)) 
+    \\state[1]_i_1__0 
+       (.I0(s_axburst_eq1_reg_0),
+        .I1(m_axi_arready),
+        .I2(\\m_payload_i_reg[0]_0 ),
+        .I3(\\m_payload_i_reg[0] ),
+        .I4(\\cnt_read_reg[1]_rep__0 ),
+        .O(next_state[1]));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""state_reg[0]"" *) 
+  FDRE \\state_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[0]),
+        .Q(Q[0]),
+        .R(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""state_reg[0]"" *) 
+  FDRE \\state_reg[0]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[0]),
+        .Q(\\m_payload_i_reg[0]_0 ),
+        .R(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""state_reg[1]"" *) 
+  FDRE \\state_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[1]),
+        .Q(Q[1]),
+        .R(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""state_reg[1]"" *) 
+  FDRE \\state_reg[1]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[1]),
+        .Q(\\m_payload_i_reg[0] ),
+        .R(areset_d1));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\wrap_boundary_axaddr_r[11]_i_1 
+       (.I0(\\m_payload_i_reg[0] ),
+        .I1(si_rs_arvalid),
+        .I2(\\m_payload_i_reg[0]_0 ),
+        .O(E));
+  LUT6 #(
+    .INIT(64\'h5575AA8A5545AA8A)) 
+    \\wrap_cnt_r[0]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[3]_0 [0]),
+        .I1(Q[0]),
+        .I2(si_rs_arvalid),
+        .I3(Q[1]),
+        .I4(\\axaddr_offset_r_reg[3] ),
+        .I5(\\axaddr_offset_r_reg[0] ),
+        .O(D[0]));
+  LUT4 #(
+    .INIT(16\'hA6AA)) 
+    \\wrap_cnt_r[3]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[3] [1]),
+        .I1(\\wrap_second_len_r_reg[2] [0]),
+        .I2(\\wrap_cnt_r[3]_i_2__0_n_0 ),
+        .I3(\\wrap_second_len_r_reg[2] [1]),
+        .O(D[1]));
+  LUT6 #(
+    .INIT(64\'hDD11DD11DD11DDF1)) 
+    \\wrap_cnt_r[3]_i_2__0 
+       (.I0(\\wrap_second_len_r_reg[3]_0 [0]),
+        .I1(E),
+        .I2(\\m_payload_i_reg[35] ),
+        .I3(\\axaddr_offset_r_reg[0] ),
+        .I4(\\m_payload_i_reg[47] [0]),
+        .I5(\\m_payload_i_reg[47] [1]),
+        .O(\\wrap_cnt_r[3]_i_2__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAA8AAA8AAABAAA8A)) 
+    \\wrap_second_len_r[0]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[3]_0 [0]),
+        .I1(Q[0]),
+        .I2(si_rs_arvalid),
+        .I3(Q[1]),
+        .I4(\\axaddr_offset_r_reg[3] ),
+        .I5(\\axaddr_offset_r_reg[0] ),
+        .O(\\wrap_second_len_r_reg[3] [0]));
+  LUT6 #(
+    .INIT(64\'hFFFFF4FF44444444)) 
+    \\wrap_second_len_r[3]_i_1__0 
+       (.I0(E),
+        .I1(\\wrap_second_len_r_reg[3]_0 [1]),
+        .I2(\\axaddr_offset_r_reg[0] ),
+        .I3(\\m_payload_i_reg[35] ),
+        .I4(\\m_payload_i_reg[47] [0]),
+        .I5(\\m_payload_i_reg[35]_0 ),
+        .O(\\wrap_second_len_r_reg[3] [1]));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_simple_fifo
+   (\\cnt_read_reg[0]_rep__0_0 ,
+    \\cnt_read_reg[1]_rep__0_0 ,
+    \\state_reg[0] ,
+    SR,
+    bresp_push,
+    bvalid_i_reg,
+    out,
+    b_push,
+    shandshake_r,
+    areset_d1,
+    Q,
+    mhandshake_r,
+    si_rs_bready,
+    si_rs_bvalid,
+    \\cnt_read_reg[1]_0 ,
+    in,
+    aclk);
+  output \\cnt_read_reg[0]_rep__0_0 ;
+  output \\cnt_read_reg[1]_rep__0_0 ;
+  output \\state_reg[0] ;
+  output [0:0]SR;
+  output bresp_push;
+  output bvalid_i_reg;
+  output [11:0]out;
+  input b_push;
+  input shandshake_r;
+  input areset_d1;
+  input [7:0]Q;
+  input mhandshake_r;
+  input si_rs_bready;
+  input si_rs_bvalid;
+  input [1:0]\\cnt_read_reg[1]_0 ;
+  input [15:0]in;
+  input aclk;
+
+  wire [7:0]Q;
+  wire [0:0]SR;
+  wire aclk;
+  wire areset_d1;
+  wire b_push;
+  wire bresp_push;
+  wire bvalid_i_i_2_n_0;
+  wire bvalid_i_reg;
+  wire [1:1]cnt_read;
+  wire \\cnt_read[0]_i_1_n_0 ;
+  wire [1:0]cnt_read_0;
+  wire \\cnt_read_reg[0]_rep__0_0 ;
+  wire \\cnt_read_reg[0]_rep_n_0 ;
+  wire [1:0]\\cnt_read_reg[1]_0 ;
+  wire \\cnt_read_reg[1]_rep__0_0 ;
+  wire \\cnt_read_reg[1]_rep_n_0 ;
+  wire [15:0]in;
+  wire \\memory_reg[3][0]_srl4_i_2__0_n_0 ;
+  wire \\memory_reg[3][0]_srl4_i_3_n_0 ;
+  wire \\memory_reg[3][0]_srl4_i_4_n_0 ;
+  wire \\memory_reg[3][0]_srl4_n_0 ;
+  wire \\memory_reg[3][1]_srl4_n_0 ;
+  wire \\memory_reg[3][2]_srl4_n_0 ;
+  wire \\memory_reg[3][3]_srl4_n_0 ;
+  wire mhandshake_r;
+  wire [11:0]out;
+  wire shandshake_r;
+  wire si_rs_bready;
+  wire si_rs_bvalid;
+  wire \\state_reg[0] ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair112"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\bresp_cnt[7]_i_1 
+       (.I0(areset_d1),
+        .I1(bresp_push),
+        .O(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair112"" *) 
+  LUT4 #(
+    .INIT(16\'h002A)) 
+    bvalid_i_i_1
+       (.I0(bvalid_i_i_2_n_0),
+        .I1(si_rs_bready),
+        .I2(si_rs_bvalid),
+        .I3(areset_d1),
+        .O(bvalid_i_reg));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF00070707)) 
+    bvalid_i_i_2
+       (.I0(\\cnt_read_reg[0]_rep__0_0 ),
+        .I1(\\cnt_read_reg[1]_rep__0_0 ),
+        .I2(shandshake_r),
+        .I3(\\cnt_read_reg[1]_0 [1]),
+        .I4(\\cnt_read_reg[1]_0 [0]),
+        .I5(si_rs_bvalid),
+        .O(bvalid_i_i_2_n_0));
+  (* SOFT_HLUTNM = ""soft_lutpair111"" *) 
+  LUT3 #(
+    .INIT(8\'h96)) 
+    \\cnt_read[0]_i_1 
+       (.I0(\\cnt_read_reg[0]_rep__0_0 ),
+        .I1(b_push),
+        .I2(shandshake_r),
+        .O(\\cnt_read[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair111"" *) 
+  LUT4 #(
+    .INIT(16\'hE718)) 
+    \\cnt_read[1]_i_1 
+       (.I0(\\cnt_read_reg[0]_rep__0_0 ),
+        .I1(b_push),
+        .I2(shandshake_r),
+        .I3(\\cnt_read_reg[1]_rep__0_0 ),
+        .O(cnt_read));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1_n_0 ),
+        .Q(cnt_read_0[0]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__0_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(cnt_read),
+        .Q(cnt_read_0[1]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(cnt_read),
+        .Q(\\cnt_read_reg[1]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(cnt_read),
+        .Q(\\cnt_read_reg[1]_rep__0_0 ),
+        .S(areset_d1));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][0]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[0]),
+        .Q(\\memory_reg[3][0]_srl4_n_0 ));
+  LUT6 #(
+    .INIT(64\'h0000000000000082)) 
+    \\memory_reg[3][0]_srl4_i_1__0 
+       (.I0(\\memory_reg[3][0]_srl4_i_2__0_n_0 ),
+        .I1(\\memory_reg[3][1]_srl4_n_0 ),
+        .I2(Q[1]),
+        .I3(Q[7]),
+        .I4(\\memory_reg[3][0]_srl4_i_3_n_0 ),
+        .I5(\\memory_reg[3][0]_srl4_i_4_n_0 ),
+        .O(bresp_push));
+  LUT5 #(
+    .INIT(32\'h04000004)) 
+    \\memory_reg[3][0]_srl4_i_2__0 
+       (.I0(Q[5]),
+        .I1(mhandshake_r),
+        .I2(Q[4]),
+        .I3(\\memory_reg[3][3]_srl4_n_0 ),
+        .I4(Q[3]),
+        .O(\\memory_reg[3][0]_srl4_i_2__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair110"" *) 
+  LUT5 #(
+    .INIT(32\'hFFAEAEAE)) 
+    \\memory_reg[3][0]_srl4_i_3 
+       (.I0(Q[6]),
+        .I1(\\memory_reg[3][0]_srl4_n_0 ),
+        .I2(Q[0]),
+        .I3(\\cnt_read_reg[1]_rep__0_0 ),
+        .I4(\\cnt_read_reg[0]_rep__0_0 ),
+        .O(\\memory_reg[3][0]_srl4_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'h2FF2)) 
+    \\memory_reg[3][0]_srl4_i_4 
+       (.I0(Q[0]),
+        .I1(\\memory_reg[3][0]_srl4_n_0 ),
+        .I2(\\memory_reg[3][2]_srl4_n_0 ),
+        .I3(Q[2]),
+        .O(\\memory_reg[3][0]_srl4_i_4_n_0 ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][10]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[6]),
+        .Q(out[2]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][11]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[7]),
+        .Q(out[3]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][12]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[8]),
+        .Q(out[4]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][13]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[9]),
+        .Q(out[5]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][14]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[10]),
+        .Q(out[6]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][15]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[11]),
+        .Q(out[7]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][16]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[12]),
+        .Q(out[8]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][17]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[13]),
+        .Q(out[9]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][18]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[14]),
+        .Q(out[10]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][19]_srl4 
+       (.A0(cnt_read_0[0]),
+        .A1(cnt_read_0[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[15]),
+        .Q(out[11]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][1]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[1]),
+        .Q(\\memory_reg[3][1]_srl4_n_0 ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][2]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[2]),
+        .Q(\\memory_reg[3][2]_srl4_n_0 ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][3]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[3]),
+        .Q(\\memory_reg[3][3]_srl4_n_0 ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][8]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[4]),
+        .Q(out[0]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][9]_srl4 
+       (.A0(\\cnt_read_reg[0]_rep_n_0 ),
+        .A1(\\cnt_read_reg[1]_rep_n_0 ),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(b_push),
+        .CLK(aclk),
+        .D(in[5]),
+        .Q(out[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair110"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\state[0]_i_2 
+       (.I0(\\cnt_read_reg[1]_rep__0_0 ),
+        .I1(\\cnt_read_reg[0]_rep__0_0 ),
+        .O(\\state_reg[0] ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_simple_fifo"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0
+   (Q,
+    mhandshake,
+    m_axi_bready,
+    \\skid_buffer_reg[1] ,
+    bresp_push,
+    shandshake_r,
+    m_axi_bvalid,
+    mhandshake_r,
+    in,
+    aclk,
+    areset_d1);
+  output [1:0]Q;
+  output mhandshake;
+  output m_axi_bready;
+  output [1:0]\\skid_buffer_reg[1] ;
+  input bresp_push;
+  input shandshake_r;
+  input m_axi_bvalid;
+  input mhandshake_r;
+  input [1:0]in;
+  input aclk;
+  input areset_d1;
+
+  wire [1:0]Q;
+  wire aclk;
+  wire areset_d1;
+  wire bresp_push;
+  wire \\cnt_read[0]_i_1__0_n_0 ;
+  wire \\cnt_read[1]_i_1__0_n_0 ;
+  wire [1:0]in;
+  wire m_axi_bready;
+  wire m_axi_bvalid;
+  wire mhandshake;
+  wire mhandshake_r;
+  wire shandshake_r;
+  wire [1:0]\\skid_buffer_reg[1] ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair114"" *) 
+  LUT3 #(
+    .INIT(8\'h96)) 
+    \\cnt_read[0]_i_1__0 
+       (.I0(Q[0]),
+        .I1(bresp_push),
+        .I2(shandshake_r),
+        .O(\\cnt_read[0]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair114"" *) 
+  LUT4 #(
+    .INIT(16\'hE718)) 
+    \\cnt_read[1]_i_1__0 
+       (.I0(Q[0]),
+        .I1(bresp_push),
+        .I2(shandshake_r),
+        .I3(Q[1]),
+        .O(\\cnt_read[1]_i_1__0_n_0 ));
+  (* KEEP = ""yes"" *) 
+  FDSE \\cnt_read_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__0_n_0 ),
+        .Q(Q[0]),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  FDSE \\cnt_read_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__0_n_0 ),
+        .Q(Q[1]),
+        .S(areset_d1));
+  (* SOFT_HLUTNM = ""soft_lutpair113"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    m_axi_bready_INST_0
+       (.I0(Q[1]),
+        .I1(Q[0]),
+        .I2(mhandshake_r),
+        .O(m_axi_bready));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][0]_srl4 
+       (.A0(Q[0]),
+        .A1(Q[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(bresp_push),
+        .CLK(aclk),
+        .D(in[0]),
+        .Q(\\skid_buffer_reg[1] [0]));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "" *) 
+  SRL16E #(
+    .INIT(16\'h0000)) 
+    \\memory_reg[3][1]_srl4 
+       (.A0(Q[0]),
+        .A1(Q[1]),
+        .A2(1\'b0),
+        .A3(1\'b0),
+        .CE(bresp_push),
+        .CLK(aclk),
+        .D(in[1]),
+        .Q(\\skid_buffer_reg[1] [1]));
+  (* SOFT_HLUTNM = ""soft_lutpair113"" *) 
+  LUT4 #(
+    .INIT(16\'h2000)) 
+    mhandshake_r_i_1
+       (.I0(m_axi_bvalid),
+        .I1(mhandshake_r),
+        .I2(Q[0]),
+        .I3(Q[1]),
+        .O(mhandshake));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_simple_fifo"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1
+   (\\cnt_read_reg[1]_rep__3_0 ,
+    m_valid_i_reg,
+    m_axi_rready,
+    \\state_reg[1]_rep ,
+    out,
+    si_rs_rready,
+    m_axi_rvalid,
+    \\cnt_read_reg[2]_rep__0_0 ,
+    in,
+    aclk,
+    areset_d1);
+  output \\cnt_read_reg[1]_rep__3_0 ;
+  output m_valid_i_reg;
+  output m_axi_rready;
+  output \\state_reg[1]_rep ;
+  output [33:0]out;
+  input si_rs_rready;
+  input m_axi_rvalid;
+  input \\cnt_read_reg[2]_rep__0_0 ;
+  input [33:0]in;
+  input aclk;
+  input areset_d1;
+
+  wire aclk;
+  wire areset_d1;
+  wire [4:0]cnt_read;
+  wire \\cnt_read[0]_i_1__1_n_0 ;
+  wire \\cnt_read[1]_i_1__1_n_0 ;
+  wire \\cnt_read[2]_i_1_n_0 ;
+  wire \\cnt_read[3]_i_1_n_0 ;
+  wire \\cnt_read[3]_i_2_n_0 ;
+  wire \\cnt_read[4]_i_1_n_0 ;
+  wire \\cnt_read[4]_i_2_n_0 ;
+  wire \\cnt_read[4]_i_3_n_0 ;
+  wire \\cnt_read_reg[0]_rep__0_n_0 ;
+  wire \\cnt_read_reg[0]_rep__1_n_0 ;
+  wire \\cnt_read_reg[0]_rep__2_n_0 ;
+  wire \\cnt_read_reg[0]_rep__3_n_0 ;
+  wire \\cnt_read_reg[0]_rep_n_0 ;
+  wire \\cnt_read_reg[1]_rep__0_n_0 ;
+  wire \\cnt_read_reg[1]_rep__1_n_0 ;
+  wire \\cnt_read_reg[1]_rep__2_n_0 ;
+  wire \\cnt_read_reg[1]_rep__3_0 ;
+  wire \\cnt_read_reg[1]_rep__3_n_0 ;
+  wire \\cnt_read_reg[1]_rep_n_0 ;
+  wire \\cnt_read_reg[2]_rep__0_0 ;
+  wire \\cnt_read_reg[2]_rep__0_n_0 ;
+  wire \\cnt_read_reg[2]_rep__1_n_0 ;
+  wire \\cnt_read_reg[2]_rep__2_n_0 ;
+  wire \\cnt_read_reg[2]_rep_n_0 ;
+  wire \\cnt_read_reg[3]_rep__0_n_0 ;
+  wire \\cnt_read_reg[3]_rep__1_n_0 ;
+  wire \\cnt_read_reg[3]_rep__2_n_0 ;
+  wire \\cnt_read_reg[3]_rep_n_0 ;
+  wire \\cnt_read_reg[4]_rep__0_n_0 ;
+  wire \\cnt_read_reg[4]_rep__1_n_0 ;
+  wire \\cnt_read_reg[4]_rep__2_n_0 ;
+  wire \\cnt_read_reg[4]_rep_n_0 ;
+  wire [33:0]in;
+  wire m_axi_rready;
+  wire m_axi_rvalid;
+  wire m_valid_i_reg;
+  wire [33:0]out;
+  wire si_rs_rready;
+  wire \\state_reg[1]_rep ;
+  wire wr_en0;
+  wire \\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
+
+  LUT3 #(
+    .INIT(8\'h96)) 
+    \\cnt_read[0]_i_1__1 
+       (.I0(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[1]_rep__3_0 ),
+        .I2(\\cnt_read[3]_i_2_n_0 ),
+        .O(\\cnt_read[0]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'hE718)) 
+    \\cnt_read[1]_i_1__1 
+       (.I0(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[1]_rep__3_0 ),
+        .I2(\\cnt_read[3]_i_2_n_0 ),
+        .I3(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .O(\\cnt_read[1]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT5 #(
+    .INIT(32\'hFE7F0180)) 
+    \\cnt_read[2]_i_1 
+       (.I0(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_0 ),
+        .I3(\\cnt_read[3]_i_2_n_0 ),
+        .I4(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .O(\\cnt_read[2]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'hDFFFFFFB20000004)) 
+    \\cnt_read[3]_i_1 
+       (.I0(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .I1(\\cnt_read[3]_i_2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_0 ),
+        .I3(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I4(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I5(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .O(\\cnt_read[3]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h08808880FFFFFFFF)) 
+    \\cnt_read[3]_i_2 
+       (.I0(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I3(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I4(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I5(m_axi_rvalid),
+        .O(\\cnt_read[3]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\cnt_read[3]_i_3 
+       (.I0(m_valid_i_reg),
+        .I1(si_rs_rready),
+        .O(\\cnt_read_reg[1]_rep__3_0 ));
+  LUT5 #(
+    .INIT(32\'h9AA69AAA)) 
+    \\cnt_read[4]_i_1 
+       (.I0(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .I1(\\cnt_read[4]_i_2_n_0 ),
+        .I2(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I3(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I4(\\cnt_read[4]_i_3_n_0 ),
+        .O(\\cnt_read[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFFF7F77)) 
+    \\cnt_read[4]_i_2 
+       (.I0(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I1(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I2(m_valid_i_reg),
+        .I3(si_rs_rready),
+        .I4(\\cnt_read[3]_i_2_n_0 ),
+        .O(\\cnt_read[4]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT5 #(
+    .INIT(32\'h00000400)) 
+    \\cnt_read[4]_i_3 
+       (.I0(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .I1(si_rs_rready),
+        .I2(m_valid_i_reg),
+        .I3(\\cnt_read[3]_i_2_n_0 ),
+        .I4(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .O(\\cnt_read[4]_i_3_n_0 ));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(cnt_read[0]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__3 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(cnt_read[1]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__3 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__1_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(cnt_read[2]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(cnt_read[3]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(cnt_read[4]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep__2 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .S(areset_d1));
+  LUT5 #(
+    .INIT(32\'hF77F777F)) 
+    m_axi_rready_INST_0
+       (.I0(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__2_n_0 ),
+        .I3(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I4(\\cnt_read_reg[0]_rep__2_n_0 ),
+        .O(m_axi_rready));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF80000000)) 
+    m_valid_i_i_2
+       (.I0(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I1(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I3(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I4(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I5(\\cnt_read_reg[2]_rep__0_0 ),
+        .O(m_valid_i_reg));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][0]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[0]),
+        .Q(out[0]),
+        .Q31(\\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
+  LUT6 #(
+    .INIT(64\'h800AAAAAAAAAAAAA)) 
+    \\memory_reg[31][0]_srl32_i_1 
+       (.I0(m_axi_rvalid),
+        .I1(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I2(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I3(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I4(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I5(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .O(wr_en0));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][10]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[10]),
+        .Q(out[10]),
+        .Q31(\\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][11]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[11]),
+        .Q(out[11]),
+        .Q31(\\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][12]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[12]),
+        .Q(out[12]),
+        .Q31(\\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][13]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[13]),
+        .Q(out[13]),
+        .Q31(\\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][14]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[14]),
+        .Q(out[14]),
+        .Q31(\\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][15]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[15]),
+        .Q(out[15]),
+        .Q31(\\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][16]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[16]),
+        .Q(out[16]),
+        .Q31(\\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][17]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[17]),
+        .Q(out[17]),
+        .Q31(\\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][18]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[18]),
+        .Q(out[18]),
+        .Q31(\\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][19]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[19]),
+        .Q(out[19]),
+        .Q31(\\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][1]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[1]),
+        .Q(out[1]),
+        .Q31(\\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][20]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[20]),
+        .Q(out[20]),
+        .Q31(\\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][21]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[21]),
+        .Q(out[21]),
+        .Q31(\\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][22]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[22]),
+        .Q(out[22]),
+        .Q31(\\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][23]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[23]),
+        .Q(out[23]),
+        .Q31(\\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][24]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[24]),
+        .Q(out[24]),
+        .Q31(\\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][25]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[25]),
+        .Q(out[25]),
+        .Q31(\\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][26]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[26]),
+        .Q(out[26]),
+        .Q31(\\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][27]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[27]),
+        .Q(out[27]),
+        .Q31(\\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][28]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[28]),
+        .Q(out[28]),
+        .Q31(\\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][29]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[29]),
+        .Q(out[29]),
+        .Q31(\\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][2]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[2]),
+        .Q(out[2]),
+        .Q31(\\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][30]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[30]),
+        .Q(out[30]),
+        .Q31(\\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][31]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[31]),
+        .Q(out[31]),
+        .Q31(\\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][32]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[32]),
+        .Q(out[32]),
+        .Q31(\\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][33]_srl32 
+       (.A(cnt_read),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[33]),
+        .Q(out[33]),
+        .Q31(\\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][3]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[3]),
+        .Q(out[3]),
+        .Q31(\\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][4]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[4]),
+        .Q(out[4]),
+        .Q31(\\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][5]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[5]),
+        .Q(out[5]),
+        .Q31(\\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][6]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__1_n_0 ,\\cnt_read_reg[3]_rep__1_n_0 ,\\cnt_read_reg[2]_rep__1_n_0 ,\\cnt_read_reg[1]_rep__1_n_0 ,\\cnt_read_reg[0]_rep__1_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[6]),
+        .Q(out[6]),
+        .Q31(\\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][7]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[7]),
+        .Q(out[7]),
+        .Q31(\\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][8]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[8]),
+        .Q(out[8]),
+        .Q31(\\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][9]_srl32 
+       (.A({\\cnt_read_reg[4]_rep__0_n_0 ,\\cnt_read_reg[3]_rep__0_n_0 ,\\cnt_read_reg[2]_rep__0_n_0 ,\\cnt_read_reg[1]_rep__0_n_0 ,\\cnt_read_reg[0]_rep__0_n_0 }),
+        .CE(wr_en0),
+        .CLK(aclk),
+        .D(in[9]),
+        .Q(out[9]),
+        .Q31(\\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
+  LUT5 #(
+    .INIT(32\'h7C000000)) 
+    \\state[1]_i_4 
+       (.I0(\\cnt_read_reg[0]_rep__3_n_0 ),
+        .I1(\\cnt_read_reg[2]_rep__2_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__3_n_0 ),
+        .I3(\\cnt_read_reg[3]_rep__2_n_0 ),
+        .I4(\\cnt_read_reg[4]_rep__2_n_0 ),
+        .O(\\state_reg[1]_rep ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_simple_fifo"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_simple_fifo'b'__parameterized2
+   (\\state_reg[1]_rep ,
+    m_valid_i_reg,
+    \\skid_buffer_reg[46] ,
+    s_ready_i_reg,
+    r_push_r,
+    si_rs_rready,
+    \\cnt_read_reg[3]_rep__2 ,
+    \\cnt_read_reg[0]_rep__3 ,
+    in,
+    aclk,
+    areset_d1);
+  output \\state_reg[1]_rep ;
+  output m_valid_i_reg;
+  output [12:0]\\skid_buffer_reg[46] ;
+  input s_ready_i_reg;
+  input r_push_r;
+  input si_rs_rready;
+  input \\cnt_read_reg[3]_rep__2 ;
+  input \\cnt_read_reg[0]_rep__3 ;
+  input [12:0]in;
+  input aclk;
+  input areset_d1;
+
+  wire aclk;
+  wire areset_d1;
+  wire [4:0]cnt_read;
+  wire \\cnt_read[0]_i_1__2_n_0 ;
+  wire \\cnt_read[1]_i_1__2_n_0 ;
+  wire \\cnt_read[2]_i_1__0_n_0 ;
+  wire \\cnt_read[3]_i_1__0_n_0 ;
+  wire \\cnt_read[4]_i_1__0_n_0 ;
+  wire \\cnt_read[4]_i_2__0_n_0 ;
+  wire \\cnt_read[4]_i_3__0_n_0 ;
+  wire \\cnt_read_reg[0]_rep__0_n_0 ;
+  wire \\cnt_read_reg[0]_rep__1_n_0 ;
+  wire \\cnt_read_reg[0]_rep__3 ;
+  wire \\cnt_read_reg[0]_rep_n_0 ;
+  wire \\cnt_read_reg[1]_rep__0_n_0 ;
+  wire \\cnt_read_reg[1]_rep_n_0 ;
+  wire \\cnt_read_reg[2]_rep__0_n_0 ;
+  wire \\cnt_read_reg[2]_rep_n_0 ;
+  wire \\cnt_read_reg[3]_rep__0_n_0 ;
+  wire \\cnt_read_reg[3]_rep__2 ;
+  wire \\cnt_read_reg[3]_rep_n_0 ;
+  wire \\cnt_read_reg[4]_rep__0_n_0 ;
+  wire \\cnt_read_reg[4]_rep_n_0 ;
+  wire [12:0]in;
+  wire m_valid_i_reg;
+  wire r_push_r;
+  wire s_ready_i_reg;
+  wire si_rs_rready;
+  wire [12:0]\\skid_buffer_reg[46] ;
+  wire \\state_reg[1]_rep ;
+  wire \\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
+  wire \\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT3 #(
+    .INIT(8\'h69)) 
+    \\cnt_read[0]_i_1__2 
+       (.I0(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .I1(s_ready_i_reg),
+        .I2(r_push_r),
+        .O(\\cnt_read[0]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT4 #(
+    .INIT(16\'h7E81)) 
+    \\cnt_read[1]_i_1__2 
+       (.I0(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .I1(r_push_r),
+        .I2(s_ready_i_reg),
+        .I3(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .O(\\cnt_read[1]_i_1__2_n_0 ));
+  LUT5 #(
+    .INIT(32\'h7FFE8001)) 
+    \\cnt_read[2]_i_1__0 
+       (.I0(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I1(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .I2(r_push_r),
+        .I3(s_ready_i_reg),
+        .I4(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .O(\\cnt_read[2]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'h7FFFFFFE80000001)) 
+    \\cnt_read[3]_i_1__0 
+       (.I0(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I1(s_ready_i_reg),
+        .I2(r_push_r),
+        .I3(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .I4(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .I5(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .O(\\cnt_read[3]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'h9AA69AAA)) 
+    \\cnt_read[4]_i_1__0 
+       (.I0(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .I1(\\cnt_read[4]_i_2__0_n_0 ),
+        .I2(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .I3(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .I4(\\cnt_read[4]_i_3__0_n_0 ),
+        .O(\\cnt_read[4]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'h5DFFFFFF)) 
+    \\cnt_read[4]_i_2__0 
+       (.I0(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I1(si_rs_rready),
+        .I2(\\cnt_read_reg[3]_rep__2 ),
+        .I3(r_push_r),
+        .I4(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .O(\\cnt_read[4]_i_2__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'h00000010)) 
+    \\cnt_read[4]_i_3__0 
+       (.I0(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .I1(r_push_r),
+        .I2(si_rs_rready),
+        .I3(\\cnt_read_reg[3]_rep__2 ),
+        .I4(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .O(\\cnt_read[4]_i_3__0_n_0 ));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__2_n_0 ),
+        .Q(cnt_read[0]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[0]"" *) 
+  FDSE \\cnt_read_reg[0]_rep__1 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[0]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__2_n_0 ),
+        .Q(cnt_read[1]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[1]"" *) 
+  FDSE \\cnt_read_reg[1]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[1]_i_1__2_n_0 ),
+        .Q(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1__0_n_0 ),
+        .Q(cnt_read[2]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[2]"" *) 
+  FDSE \\cnt_read_reg[2]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[2]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1__0_n_0 ),
+        .Q(cnt_read[3]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[3]"" *) 
+  FDSE \\cnt_read_reg[3]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[3]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .S(areset_d1));
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1__0_n_0 ),
+        .Q(cnt_read[4]),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep_n_0 ),
+        .S(areset_d1));
+  (* IS_FANOUT_CONSTRAINED = ""1"" *) 
+  (* KEEP = ""yes"" *) 
+  (* ORIG_CELL_NAME = ""cnt_read_reg[4]"" *) 
+  FDSE \\cnt_read_reg[4]_rep__0 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\cnt_read[4]_i_1__0_n_0 ),
+        .Q(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .S(areset_d1));
+  LUT5 #(
+    .INIT(32\'h80000000)) 
+    m_valid_i_i_3
+       (.I0(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .I1(\\cnt_read_reg[0]_rep__1_n_0 ),
+        .I2(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I3(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .I4(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .O(m_valid_i_reg));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][0]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[0]),
+        .Q(\\skid_buffer_reg[46] [0]),
+        .Q31(\\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][10]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[10]),
+        .Q(\\skid_buffer_reg[46] [10]),
+        .Q31(\\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][11]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[11]),
+        .Q(\\skid_buffer_reg[46] [11]),
+        .Q31(\\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][12]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[12]),
+        .Q(\\skid_buffer_reg[46] [12]),
+        .Q31(\\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][1]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[1]),
+        .Q(\\skid_buffer_reg[46] [1]),
+        .Q31(\\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][2]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[2]),
+        .Q(\\skid_buffer_reg[46] [2]),
+        .Q31(\\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][3]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[3]),
+        .Q(\\skid_buffer_reg[46] [3]),
+        .Q31(\\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][4]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[4]),
+        .Q(\\skid_buffer_reg[46] [4]),
+        .Q31(\\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][5]_srl32 
+       (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[5]),
+        .Q(\\skid_buffer_reg[46] [5]),
+        .Q31(\\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][6]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[6]),
+        .Q(\\skid_buffer_reg[46] [6]),
+        .Q31(\\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][7]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[7]),
+        .Q(\\skid_buffer_reg[46] [7]),
+        .Q31(\\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][8]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[8]),
+        .Q(\\skid_buffer_reg[46] [8]),
+        .Q31(\\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
+  (* srl_bus_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "" *) 
+  (* srl_name = ""inst/\\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "" *) 
+  SRLC32E #(
+    .INIT(32\'h00000000)) 
+    \\memory_reg[31][9]_srl32 
+       (.A(cnt_read),
+        .CE(r_push_r),
+        .CLK(aclk),
+        .D(in[9]),
+        .Q(\\skid_buffer_reg[46] [9]),
+        .Q31(\\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
+  LUT6 #(
+    .INIT(64\'hBFEEAAAAAAAAAAAA)) 
+    \\state[1]_i_3 
+       (.I0(\\cnt_read_reg[0]_rep__3 ),
+        .I1(\\cnt_read_reg[1]_rep__0_n_0 ),
+        .I2(\\cnt_read_reg[0]_rep__0_n_0 ),
+        .I3(\\cnt_read_reg[2]_rep__0_n_0 ),
+        .I4(\\cnt_read_reg[4]_rep__0_n_0 ),
+        .I5(\\cnt_read_reg[3]_rep__0_n_0 ),
+        .O(\\state_reg[1]_rep ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm
+   (E,
+    Q,
+    sel_first_reg,
+    \\wrap_boundary_axaddr_r_reg[0] ,
+    \\axlen_cnt_reg[7] ,
+    s_axburst_eq0_reg,
+    wrap_next_pending,
+    sel_first_i,
+    incr_next_pending,
+    s_axburst_eq1_reg,
+    \\m_payload_i_reg[0] ,
+    b_push,
+    m_axi_awvalid,
+    sel_first_reg_0,
+    sel_first_reg_1,
+    si_rs_awvalid,
+    \\axlen_cnt_reg[7]_0 ,
+    \\m_payload_i_reg[39] ,
+    \\m_payload_i_reg[46] ,
+    next_pending_r_reg,
+    next_pending_r_reg_0,
+    \\axlen_cnt_reg[3] ,
+    areset_d1,
+    sel_first_reg_2,
+    \\cnt_read_reg[1]_rep__0 ,
+    s_axburst_eq1_reg_0,
+    m_axi_awready,
+    \\cnt_read_reg[1]_rep__0_0 ,
+    \\cnt_read_reg[0]_rep__0 ,
+    sel_first_reg_3,
+    sel_first__0,
+    aclk);
+  output [0:0]E;
+  output [1:0]Q;
+  output sel_first_reg;
+  output [0:0]\\wrap_boundary_axaddr_r_reg[0] ;
+  output \\axlen_cnt_reg[7] ;
+  output s_axburst_eq0_reg;
+  output wrap_next_pending;
+  output sel_first_i;
+  output incr_next_pending;
+  output s_axburst_eq1_reg;
+  output [0:0]\\m_payload_i_reg[0] ;
+  output b_push;
+  output m_axi_awvalid;
+  output sel_first_reg_0;
+  output sel_first_reg_1;
+  input si_rs_awvalid;
+  input \\axlen_cnt_reg[7]_0 ;
+  input [0:0]\\m_payload_i_reg[39] ;
+  input \\m_payload_i_reg[46] ;
+  input next_pending_r_reg;
+  input next_pending_r_reg_0;
+  input \\axlen_cnt_reg[3] ;
+  input areset_d1;
+  input sel_first_reg_2;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input s_axburst_eq1_reg_0;
+  input m_axi_awready;
+  input \\cnt_read_reg[1]_rep__0_0 ;
+  input \\cnt_read_reg[0]_rep__0 ;
+  input sel_first_reg_3;
+  input sel_first__0;
+  input aclk;
+
+  wire [0:0]E;
+  wire [1:0]Q;
+  wire aclk;
+  wire areset_d1;
+  wire \\axlen_cnt_reg[3] ;
+  wire \\axlen_cnt_reg[7] ;
+  wire \\axlen_cnt_reg[7]_0 ;
+  wire b_push;
+  wire \\cnt_read_reg[0]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire \\cnt_read_reg[1]_rep__0_0 ;
+  wire incr_next_pending;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire [0:0]\\m_payload_i_reg[0] ;
+  wire [0:0]\\m_payload_i_reg[39] ;
+  wire \\m_payload_i_reg[46] ;
+  wire next_pending_r_reg;
+  wire next_pending_r_reg_0;
+  wire [1:0]next_state;
+  wire s_axburst_eq0_reg;
+  wire s_axburst_eq1_reg;
+  wire s_axburst_eq1_reg_0;
+  wire sel_first__0;
+  wire sel_first_i;
+  wire sel_first_reg;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire sel_first_reg_2;
+  wire sel_first_reg_3;
+  wire si_rs_awvalid;
+  wire [0:0]\\wrap_boundary_axaddr_r_reg[0] ;
+  wire wrap_next_pending;
+
+  (* SOFT_HLUTNM = ""soft_lutpair104"" *) 
+  LUT4 #(
+    .INIT(16\'h04FF)) 
+    \\axlen_cnt[3]_i_1__0 
+       (.I0(Q[0]),
+        .I1(si_rs_awvalid),
+        .I2(Q[1]),
+        .I3(sel_first_reg),
+        .O(E));
+  (* SOFT_HLUTNM = ""soft_lutpair104"" *) 
+  LUT5 #(
+    .INIT(32\'h000004FF)) 
+    \\axlen_cnt[7]_i_1__0 
+       (.I0(Q[0]),
+        .I1(si_rs_awvalid),
+        .I2(Q[1]),
+        .I3(sel_first_reg),
+        .I4(\\axlen_cnt_reg[7]_0 ),
+        .O(\\axlen_cnt_reg[7] ));
+  (* SOFT_HLUTNM = ""soft_lutpair106"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    m_axi_awvalid_INST_0
+       (.I0(Q[0]),
+        .I1(Q[1]),
+        .O(m_axi_awvalid));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_payload_i[31]_i_1 
+       (.I0(b_push),
+        .I1(si_rs_awvalid),
+        .O(\\m_payload_i_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hA000A0A0A800A8A8)) 
+    \\memory_reg[3][0]_srl4_i_1 
+       (.I0(Q[0]),
+        .I1(m_axi_awready),
+        .I2(Q[1]),
+        .I3(\\cnt_read_reg[0]_rep__0 ),
+        .I4(\\cnt_read_reg[1]_rep__0_0 ),
+        .I5(s_axburst_eq1_reg_0),
+        .O(b_push));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    next_pending_r_i_1
+       (.I0(\\m_payload_i_reg[46] ),
+        .I1(\\wrap_boundary_axaddr_r_reg[0] ),
+        .I2(next_pending_r_reg),
+        .I3(sel_first_reg),
+        .I4(\\axlen_cnt_reg[7]_0 ),
+        .O(incr_next_pending));
+  LUT5 #(
+    .INIT(32\'hB888B8BB)) 
+    next_pending_r_i_1__0
+       (.I0(\\m_payload_i_reg[46] ),
+        .I1(\\wrap_boundary_axaddr_r_reg[0] ),
+        .I2(next_pending_r_reg_0),
+        .I3(sel_first_reg),
+        .I4(\\axlen_cnt_reg[3] ),
+        .O(wrap_next_pending));
+  LUT6 #(
+    .INIT(64\'h0CAE0CFF00FF00FF)) 
+    next_pending_r_i_3
+       (.I0(s_axburst_eq1_reg_0),
+        .I1(\\cnt_read_reg[1]_rep__0_0 ),
+        .I2(\\cnt_read_reg[0]_rep__0 ),
+        .I3(Q[1]),
+        .I4(m_axi_awready),
+        .I5(Q[0]),
+        .O(sel_first_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair105"" *) 
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    s_axburst_eq0_i_1
+       (.I0(wrap_next_pending),
+        .I1(\\m_payload_i_reg[39] ),
+        .I2(sel_first_i),
+        .I3(incr_next_pending),
+        .O(s_axburst_eq0_reg));
+  (* SOFT_HLUTNM = ""soft_lutpair105"" *) 
+  LUT4 #(
+    .INIT(16\'hABA8)) 
+    s_axburst_eq1_i_1
+       (.I0(wrap_next_pending),
+        .I1(\\m_payload_i_reg[39] ),
+        .I2(sel_first_i),
+        .I3(incr_next_pending),
+        .O(s_axburst_eq1_reg));
+  LUT6 #(
+    .INIT(64\'hFFFFFF04FF04FF04)) 
+    sel_first_i_1
+       (.I0(Q[1]),
+        .I1(si_rs_awvalid),
+        .I2(Q[0]),
+        .I3(areset_d1),
+        .I4(sel_first_reg),
+        .I5(sel_first_reg_2),
+        .O(sel_first_i));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF88888F88)) 
+    sel_first_i_1__1
+       (.I0(sel_first_reg),
+        .I1(sel_first_reg_3),
+        .I2(Q[1]),
+        .I3(si_rs_awvalid),
+        .I4(Q[0]),
+        .I5(areset_d1),
+        .O(sel_first_reg_0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF88888F88)) 
+    sel_first_i_1__2
+       (.I0(sel_first_reg),
+        .I1(sel_first__0),
+        .I2(Q[1]),
+        .I3(si_rs_awvalid),
+        .I4(Q[0]),
+        .I5(areset_d1),
+        .O(sel_first_reg_1));
+  LUT6 #(
+    .INIT(64\'hF232FE32FE3EFE3E)) 
+    \\state[0]_i_1 
+       (.I0(si_rs_awvalid),
+        .I1(Q[0]),
+        .I2(Q[1]),
+        .I3(\\cnt_read_reg[1]_rep__0 ),
+        .I4(s_axburst_eq1_reg_0),
+        .I5(m_axi_awready),
+        .O(next_state[0]));
+  LUT6 #(
+    .INIT(64\'h20E0202000E00000)) 
+    \\state[1]_i_1 
+       (.I0(m_axi_awready),
+        .I1(Q[1]),
+        .I2(Q[0]),
+        .I3(\\cnt_read_reg[0]_rep__0 ),
+        .I4(\\cnt_read_reg[1]_rep__0_0 ),
+        .I5(s_axburst_eq1_reg_0),
+        .O(next_state[1]));
+  (* KEEP = ""yes"" *) 
+  FDRE \\state_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[0]),
+        .Q(Q[0]),
+        .R(areset_d1));
+  (* KEEP = ""yes"" *) 
+  FDRE \\state_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(next_state[1]),
+        .Q(Q[1]),
+        .R(areset_d1));
+  (* SOFT_HLUTNM = ""soft_lutpair106"" *) 
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\wrap_boundary_axaddr_r[11]_i_1__0 
+       (.I0(Q[1]),
+        .I1(si_rs_awvalid),
+        .I2(Q[0]),
+        .O(\\wrap_boundary_axaddr_r_reg[0] ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_wrap_cmd
+   (next_pending_r_reg_0,
+    sel_first_reg_0,
+    next_pending_r_reg_1,
+    m_axi_awaddr,
+    \\axaddr_offset_r_reg[3]_0 ,
+    \\wrap_second_len_r_reg[3]_0 ,
+    wrap_next_pending,
+    aclk,
+    sel_first_reg_1,
+    E,
+    \\m_payload_i_reg[47] ,
+    \\cnt_read_reg[1]_rep__0 ,
+    axaddr_incr_reg,
+    \\m_payload_i_reg[38] ,
+    \\axaddr_incr_reg[3] ,
+    D,
+    \\wrap_second_len_r_reg[3]_1 ,
+    \\state_reg[0] ,
+    \\wrap_second_len_r_reg[3]_2 ,
+    \\m_payload_i_reg[6] );
+  output next_pending_r_reg_0;
+  output sel_first_reg_0;
+  output next_pending_r_reg_1;
+  output [11:0]m_axi_awaddr;
+  output [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  output [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input wrap_next_pending;
+  input aclk;
+  input sel_first_reg_1;
+  input [0:0]E;
+  input [18:0]\\m_payload_i_reg[47] ;
+  input \\cnt_read_reg[1]_rep__0 ;
+  input [7:0]axaddr_incr_reg;
+  input \\m_payload_i_reg[38] ;
+  input [3:0]\\axaddr_incr_reg[3] ;
+  input [3:0]D;
+  input [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [0:0]\\state_reg[0] ;
+  input [3:0]\\wrap_second_len_r_reg[3]_2 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire aclk;
+  wire [7:0]axaddr_incr_reg;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire [11:0]axaddr_wrap;
+  wire [11:0]axaddr_wrap0;
+  wire \\axaddr_wrap[0]_i_1_n_0 ;
+  wire \\axaddr_wrap[10]_i_1_n_0 ;
+  wire \\axaddr_wrap[11]_i_1_n_0 ;
+  wire \\axaddr_wrap[11]_i_3_n_0 ;
+  wire \\axaddr_wrap[11]_i_4_n_0 ;
+  wire \\axaddr_wrap[11]_i_5_n_0 ;
+  wire \\axaddr_wrap[11]_i_6_n_0 ;
+  wire \\axaddr_wrap[11]_i_7_n_0 ;
+  wire \\axaddr_wrap[11]_i_8_n_0 ;
+  wire \\axaddr_wrap[1]_i_1_n_0 ;
+  wire \\axaddr_wrap[2]_i_1_n_0 ;
+  wire \\axaddr_wrap[3]_i_1_n_0 ;
+  wire \\axaddr_wrap[3]_i_3_n_0 ;
+  wire \\axaddr_wrap[3]_i_4_n_0 ;
+  wire \\axaddr_wrap[3]_i_5_n_0 ;
+  wire \\axaddr_wrap[3]_i_6_n_0 ;
+  wire \\axaddr_wrap[4]_i_1_n_0 ;
+  wire \\axaddr_wrap[5]_i_1_n_0 ;
+  wire \\axaddr_wrap[6]_i_1_n_0 ;
+  wire \\axaddr_wrap[7]_i_1_n_0 ;
+  wire \\axaddr_wrap[7]_i_3_n_0 ;
+  wire \\axaddr_wrap[7]_i_4_n_0 ;
+  wire \\axaddr_wrap[7]_i_5_n_0 ;
+  wire \\axaddr_wrap[7]_i_6_n_0 ;
+  wire \\axaddr_wrap[8]_i_1_n_0 ;
+  wire \\axaddr_wrap[9]_i_1_n_0 ;
+  wire \\axaddr_wrap_reg[11]_i_2_n_1 ;
+  wire \\axaddr_wrap_reg[11]_i_2_n_2 ;
+  wire \\axaddr_wrap_reg[11]_i_2_n_3 ;
+  wire \\axaddr_wrap_reg[3]_i_2_n_0 ;
+  wire \\axaddr_wrap_reg[3]_i_2_n_1 ;
+  wire \\axaddr_wrap_reg[3]_i_2_n_2 ;
+  wire \\axaddr_wrap_reg[3]_i_2_n_3 ;
+  wire \\axaddr_wrap_reg[7]_i_2_n_0 ;
+  wire \\axaddr_wrap_reg[7]_i_2_n_1 ;
+  wire \\axaddr_wrap_reg[7]_i_2_n_2 ;
+  wire \\axaddr_wrap_reg[7]_i_2_n_3 ;
+  wire \\axlen_cnt[0]_i_1__2_n_0 ;
+  wire \\axlen_cnt[1]_i_1__0_n_0 ;
+  wire \\axlen_cnt[2]_i_1__0_n_0 ;
+  wire \\axlen_cnt[3]_i_1__1_n_0 ;
+  wire \\axlen_cnt_reg_n_0_[0] ;
+  wire \\axlen_cnt_reg_n_0_[1] ;
+  wire \\axlen_cnt_reg_n_0_[2] ;
+  wire \\axlen_cnt_reg_n_0_[3] ;
+  wire \\cnt_read_reg[1]_rep__0 ;
+  wire [11:0]m_axi_awaddr;
+  wire \\m_payload_i_reg[38] ;
+  wire [18:0]\\m_payload_i_reg[47] ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire next_pending_r_reg_0;
+  wire next_pending_r_reg_1;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire [0:0]\\state_reg[0] ;
+  wire [11:0]wrap_boundary_axaddr_r;
+  wire [3:0]wrap_cnt_r;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_2 ;
+  wire [3:3]\\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED ;
+
+  FDRE \\axaddr_offset_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[0]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[1]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[2]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(D[3]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [3]),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[0]_i_1 
+       (.I0(\\m_payload_i_reg[47] [0]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[0]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[0]),
+        .O(\\axaddr_wrap[0]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[10]_i_1 
+       (.I0(\\m_payload_i_reg[47] [10]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[10]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[10]),
+        .O(\\axaddr_wrap[10]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[11]_i_1 
+       (.I0(\\m_payload_i_reg[47] [11]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[11]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[11]),
+        .O(\\axaddr_wrap[11]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair109"" *) 
+  LUT3 #(
+    .INIT(8\'hBE)) 
+    \\axaddr_wrap[11]_i_3 
+       (.I0(\\axaddr_wrap[11]_i_8_n_0 ),
+        .I1(wrap_cnt_r[3]),
+        .I2(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axaddr_wrap[11]_i_3_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_4 
+       (.I0(axaddr_wrap[11]),
+        .O(\\axaddr_wrap[11]_i_4_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_5 
+       (.I0(axaddr_wrap[10]),
+        .O(\\axaddr_wrap[11]_i_5_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_6 
+       (.I0(axaddr_wrap[9]),
+        .O(\\axaddr_wrap[11]_i_6_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_7 
+       (.I0(axaddr_wrap[8]),
+        .O(\\axaddr_wrap[11]_i_7_n_0 ));
+  LUT6 #(
+    .INIT(64\'h6FF6FFFFFFFF6FF6)) 
+    \\axaddr_wrap[11]_i_8 
+       (.I0(wrap_cnt_r[2]),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(wrap_cnt_r[1]),
+        .I4(\\axlen_cnt_reg_n_0_[0] ),
+        .I5(wrap_cnt_r[0]),
+        .O(\\axaddr_wrap[11]_i_8_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[1]_i_1 
+       (.I0(\\m_payload_i_reg[47] [1]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[1]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[1]),
+        .O(\\axaddr_wrap[1]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[2]_i_1 
+       (.I0(\\m_payload_i_reg[47] [2]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[2]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[2]),
+        .O(\\axaddr_wrap[2]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[3]_i_1 
+       (.I0(\\m_payload_i_reg[47] [3]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[3]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[3]),
+        .O(\\axaddr_wrap[3]_i_1_n_0 ));
+  LUT3 #(
+    .INIT(8\'h6A)) 
+    \\axaddr_wrap[3]_i_3 
+       (.I0(axaddr_wrap[3]),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axaddr_wrap[3]_i_4 
+       (.I0(axaddr_wrap[2]),
+        .I1(\\m_payload_i_reg[47] [12]),
+        .I2(\\m_payload_i_reg[47] [13]),
+        .O(\\axaddr_wrap[3]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axaddr_wrap[3]_i_5 
+       (.I0(axaddr_wrap[1]),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8\'hA9)) 
+    \\axaddr_wrap[3]_i_6 
+       (.I0(axaddr_wrap[0]),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_6_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[4]_i_1 
+       (.I0(\\m_payload_i_reg[47] [4]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[4]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[4]),
+        .O(\\axaddr_wrap[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[5]_i_1 
+       (.I0(\\m_payload_i_reg[47] [5]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[5]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[5]),
+        .O(\\axaddr_wrap[5]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[6]_i_1 
+       (.I0(\\m_payload_i_reg[47] [6]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[6]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[6]),
+        .O(\\axaddr_wrap[6]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[7]_i_1 
+       (.I0(\\m_payload_i_reg[47] [7]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[7]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[7]),
+        .O(\\axaddr_wrap[7]_i_1_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_3 
+       (.I0(axaddr_wrap[7]),
+        .O(\\axaddr_wrap[7]_i_3_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_4 
+       (.I0(axaddr_wrap[6]),
+        .O(\\axaddr_wrap[7]_i_4_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_5 
+       (.I0(axaddr_wrap[5]),
+        .O(\\axaddr_wrap[7]_i_5_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_6 
+       (.I0(axaddr_wrap[4]),
+        .O(\\axaddr_wrap[7]_i_6_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[8]_i_1 
+       (.I0(\\m_payload_i_reg[47] [8]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[8]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[8]),
+        .O(\\axaddr_wrap[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8BBB888)) 
+    \\axaddr_wrap[9]_i_1 
+       (.I0(\\m_payload_i_reg[47] [9]),
+        .I1(\\cnt_read_reg[1]_rep__0 ),
+        .I2(axaddr_wrap0[9]),
+        .I3(\\axaddr_wrap[11]_i_3_n_0 ),
+        .I4(wrap_boundary_axaddr_r[9]),
+        .O(\\axaddr_wrap[9]_i_1_n_0 ));
+  FDRE \\axaddr_wrap_reg[0] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[0]_i_1_n_0 ),
+        .Q(axaddr_wrap[0]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[10] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[10]_i_1_n_0 ),
+        .Q(axaddr_wrap[10]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[11] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[11]_i_1_n_0 ),
+        .Q(axaddr_wrap[11]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[11]_i_2 
+       (.CI(\\axaddr_wrap_reg[7]_i_2_n_0 ),
+        .CO({\\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED [3],\\axaddr_wrap_reg[11]_i_2_n_1 ,\\axaddr_wrap_reg[11]_i_2_n_2 ,\\axaddr_wrap_reg[11]_i_2_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(axaddr_wrap0[11:8]),
+        .S({\\axaddr_wrap[11]_i_4_n_0 ,\\axaddr_wrap[11]_i_5_n_0 ,\\axaddr_wrap[11]_i_6_n_0 ,\\axaddr_wrap[11]_i_7_n_0 }));
+  FDRE \\axaddr_wrap_reg[1] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[1]_i_1_n_0 ),
+        .Q(axaddr_wrap[1]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[2] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[2]_i_1_n_0 ),
+        .Q(axaddr_wrap[2]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[3] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[3]_i_1_n_0 ),
+        .Q(axaddr_wrap[3]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[3]_i_2 
+       (.CI(1\'b0),
+        .CO({\\axaddr_wrap_reg[3]_i_2_n_0 ,\\axaddr_wrap_reg[3]_i_2_n_1 ,\\axaddr_wrap_reg[3]_i_2_n_2 ,\\axaddr_wrap_reg[3]_i_2_n_3 }),
+        .CYINIT(1\'b0),
+        .DI(axaddr_wrap[3:0]),
+        .O(axaddr_wrap0[3:0]),
+        .S({\\axaddr_wrap[3]_i_3_n_0 ,\\axaddr_wrap[3]_i_4_n_0 ,\\axaddr_wrap[3]_i_5_n_0 ,\\axaddr_wrap[3]_i_6_n_0 }));
+  FDRE \\axaddr_wrap_reg[4] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[4]_i_1_n_0 ),
+        .Q(axaddr_wrap[4]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[5] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[5]_i_1_n_0 ),
+        .Q(axaddr_wrap[5]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[6] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[6]_i_1_n_0 ),
+        .Q(axaddr_wrap[6]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[7] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[7]_i_1_n_0 ),
+        .Q(axaddr_wrap[7]),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[7]_i_2 
+       (.CI(\\axaddr_wrap_reg[3]_i_2_n_0 ),
+        .CO({\\axaddr_wrap_reg[7]_i_2_n_0 ,\\axaddr_wrap_reg[7]_i_2_n_1 ,\\axaddr_wrap_reg[7]_i_2_n_2 ,\\axaddr_wrap_reg[7]_i_2_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(axaddr_wrap0[7:4]),
+        .S({\\axaddr_wrap[7]_i_3_n_0 ,\\axaddr_wrap[7]_i_4_n_0 ,\\axaddr_wrap[7]_i_5_n_0 ,\\axaddr_wrap[7]_i_6_n_0 }));
+  FDRE \\axaddr_wrap_reg[8] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[8]_i_1_n_0 ),
+        .Q(axaddr_wrap[8]),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[9] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axaddr_wrap[9]_i_1_n_0 ),
+        .Q(axaddr_wrap[9]),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hFFFF555400005554)) 
+    \\axlen_cnt[0]_i_1__2 
+       (.I0(\\axlen_cnt_reg_n_0_[0] ),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\axlen_cnt_reg_n_0_[3] ),
+        .I4(E),
+        .I5(\\m_payload_i_reg[47] [15]),
+        .O(\\axlen_cnt[0]_i_1__2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAC3AAC3AAC3AAC0)) 
+    \\axlen_cnt[1]_i_1__0 
+       (.I0(\\m_payload_i_reg[47] [16]),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(E),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[1]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAACCC3AAAACCC0)) 
+    \\axlen_cnt[2]_i_1__0 
+       (.I0(\\m_payload_i_reg[47] [17]),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(E),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[2]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFAAA80000AAA8)) 
+    \\axlen_cnt[3]_i_1__1 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(E),
+        .I5(\\m_payload_i_reg[47] [18]),
+        .O(\\axlen_cnt[3]_i_1__1_n_0 ));
+  FDRE \\axlen_cnt_reg[0] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[0]_i_1__2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[1] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[1]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[2] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[2]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[3] 
+       (.C(aclk),
+        .CE(\\state_reg[0] ),
+        .D(\\axlen_cnt[3]_i_1__1_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[3] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[0]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[0]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [0]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [0]),
+        .O(m_axi_awaddr[0]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[10]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[10]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[6]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [10]),
+        .O(m_axi_awaddr[10]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[11]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[11]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[7]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [11]),
+        .O(m_axi_awaddr[11]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[1]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[1]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [1]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [1]),
+        .O(m_axi_awaddr[1]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[2]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[2]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [2]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [2]),
+        .O(m_axi_awaddr[2]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[3]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[3]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [3]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [3]),
+        .O(m_axi_awaddr[3]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[4]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[4]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[0]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [4]),
+        .O(m_axi_awaddr[4]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[5]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[5]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[1]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [5]),
+        .O(m_axi_awaddr[5]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[6]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[6]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[2]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [6]),
+        .O(m_axi_awaddr[6]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[7]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[7]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[3]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [7]),
+        .O(m_axi_awaddr[7]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[8]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[8]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[4]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [8]),
+        .O(m_axi_awaddr[8]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_awaddr[9]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(axaddr_wrap[9]),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[5]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [9]),
+        .O(m_axi_awaddr[9]));
+  (* SOFT_HLUTNM = ""soft_lutpair109"" *) 
+  LUT3 #(
+    .INIT(8\'h01)) 
+    next_pending_r_i_2__0
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .O(next_pending_r_reg_1));
+  FDRE next_pending_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(wrap_next_pending),
+        .Q(next_pending_r_reg_0),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_reg_1),
+        .Q(sel_first_reg_0),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [0]),
+        .Q(wrap_boundary_axaddr_r[0]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [10]),
+        .Q(wrap_boundary_axaddr_r[10]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [11]),
+        .Q(wrap_boundary_axaddr_r[11]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [1]),
+        .Q(wrap_boundary_axaddr_r[1]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [2]),
+        .Q(wrap_boundary_axaddr_r[2]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [3]),
+        .Q(wrap_boundary_axaddr_r[3]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [4]),
+        .Q(wrap_boundary_axaddr_r[4]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [5]),
+        .Q(wrap_boundary_axaddr_r[5]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [6]),
+        .Q(wrap_boundary_axaddr_r[6]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [7]),
+        .Q(wrap_boundary_axaddr_r[7]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [8]),
+        .Q(wrap_boundary_axaddr_r[8]),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [9]),
+        .Q(wrap_boundary_axaddr_r[9]),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [0]),
+        .Q(wrap_cnt_r[0]),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [1]),
+        .Q(wrap_cnt_r[1]),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [2]),
+        .Q(wrap_cnt_r[2]),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [3]),
+        .Q(wrap_cnt_r[3]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [0]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [1]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [2]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [3]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [3]),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_protocol_converter_v2_1_11_b2s_wrap_cmd"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3
+   (next_pending_r_reg_0,
+    sel_first_reg_0,
+    next_pending_r_reg_1,
+    m_axi_araddr,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\axaddr_offset_r_reg[3]_0 ,
+    wrap_next_pending,
+    aclk,
+    sel_first_reg_1,
+    E,
+    \\m_payload_i_reg[47] ,
+    \\state_reg[1] ,
+    si_rs_arvalid,
+    \\state_reg[1]_rep ,
+    axaddr_incr_reg,
+    \\m_payload_i_reg[38] ,
+    \\axaddr_incr_reg[3] ,
+    \\axaddr_offset_r_reg[3]_1 ,
+    \\m_payload_i_reg[35] ,
+    \\m_payload_i_reg[47]_0 ,
+    \\wrap_second_len_r_reg[3]_1 ,
+    m_valid_i_reg,
+    \\wrap_second_len_r_reg[3]_2 ,
+    \\m_payload_i_reg[6] );
+  output next_pending_r_reg_0;
+  output sel_first_reg_0;
+  output next_pending_r_reg_1;
+  output [11:0]m_axi_araddr;
+  output [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  output [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  input wrap_next_pending;
+  input aclk;
+  input sel_first_reg_1;
+  input [0:0]E;
+  input [18:0]\\m_payload_i_reg[47] ;
+  input [1:0]\\state_reg[1] ;
+  input si_rs_arvalid;
+  input \\state_reg[1]_rep ;
+  input [7:0]axaddr_incr_reg;
+  input \\m_payload_i_reg[38] ;
+  input [3:0]\\axaddr_incr_reg[3] ;
+  input \\axaddr_offset_r_reg[3]_1 ;
+  input \\m_payload_i_reg[35] ;
+  input [3:0]\\m_payload_i_reg[47]_0 ;
+  input [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  input [0:0]m_valid_i_reg;
+  input [2:0]\\wrap_second_len_r_reg[3]_2 ;
+  input [6:0]\\m_payload_i_reg[6] ;
+
+  wire [0:0]E;
+  wire aclk;
+  wire [7:0]axaddr_incr_reg;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire \\axaddr_offset_r_reg[3]_1 ;
+  wire \\axaddr_wrap[0]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[10]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_3__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_4__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_5__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_6__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_7__0_n_0 ;
+  wire \\axaddr_wrap[11]_i_8__0_n_0 ;
+  wire \\axaddr_wrap[1]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[2]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[3]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[3]_i_3_n_0 ;
+  wire \\axaddr_wrap[3]_i_4_n_0 ;
+  wire \\axaddr_wrap[3]_i_5_n_0 ;
+  wire \\axaddr_wrap[3]_i_6_n_0 ;
+  wire \\axaddr_wrap[4]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[5]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[6]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_3__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_4__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_5__0_n_0 ;
+  wire \\axaddr_wrap[7]_i_6__0_n_0 ;
+  wire \\axaddr_wrap[8]_i_1__0_n_0 ;
+  wire \\axaddr_wrap[9]_i_1__0_n_0 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_1 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_2 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_3 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_4 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_5 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_6 ;
+  wire \\axaddr_wrap_reg[11]_i_2__0_n_7 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_0 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_1 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_2 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_3 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_4 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_5 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_6 ;
+  wire \\axaddr_wrap_reg[3]_i_2__0_n_7 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_0 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_1 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_2 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_3 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_4 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_5 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_6 ;
+  wire \\axaddr_wrap_reg[7]_i_2__0_n_7 ;
+  wire \\axaddr_wrap_reg_n_0_[0] ;
+  wire \\axaddr_wrap_reg_n_0_[10] ;
+  wire \\axaddr_wrap_reg_n_0_[11] ;
+  wire \\axaddr_wrap_reg_n_0_[1] ;
+  wire \\axaddr_wrap_reg_n_0_[2] ;
+  wire \\axaddr_wrap_reg_n_0_[3] ;
+  wire \\axaddr_wrap_reg_n_0_[4] ;
+  wire \\axaddr_wrap_reg_n_0_[5] ;
+  wire \\axaddr_wrap_reg_n_0_[6] ;
+  wire \\axaddr_wrap_reg_n_0_[7] ;
+  wire \\axaddr_wrap_reg_n_0_[8] ;
+  wire \\axaddr_wrap_reg_n_0_[9] ;
+  wire \\axlen_cnt[0]_i_1__0_n_0 ;
+  wire \\axlen_cnt[1]_i_1__2_n_0 ;
+  wire \\axlen_cnt[2]_i_1__2_n_0 ;
+  wire \\axlen_cnt[3]_i_1__2_n_0 ;
+  wire \\axlen_cnt_reg_n_0_[0] ;
+  wire \\axlen_cnt_reg_n_0_[1] ;
+  wire \\axlen_cnt_reg_n_0_[2] ;
+  wire \\axlen_cnt_reg_n_0_[3] ;
+  wire [11:0]m_axi_araddr;
+  wire \\m_payload_i_reg[35] ;
+  wire \\m_payload_i_reg[38] ;
+  wire [18:0]\\m_payload_i_reg[47] ;
+  wire [3:0]\\m_payload_i_reg[47]_0 ;
+  wire [6:0]\\m_payload_i_reg[6] ;
+  wire [0:0]m_valid_i_reg;
+  wire next_pending_r_reg_0;
+  wire next_pending_r_reg_1;
+  wire sel_first_reg_0;
+  wire sel_first_reg_1;
+  wire si_rs_arvalid;
+  wire [1:0]\\state_reg[1] ;
+  wire \\state_reg[1]_rep ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[0] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[10] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[11] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[1] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[2] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[3] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[4] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[5] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[6] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[7] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[8] ;
+  wire \\wrap_boundary_axaddr_r_reg_n_0_[9] ;
+  wire \\wrap_cnt_r[1]_i_1_n_0 ;
+  wire \\wrap_cnt_r_reg_n_0_[0] ;
+  wire \\wrap_cnt_r_reg_n_0_[1] ;
+  wire \\wrap_cnt_r_reg_n_0_[2] ;
+  wire \\wrap_cnt_r_reg_n_0_[3] ;
+  wire wrap_next_pending;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_1 ;
+  wire [2:0]\\wrap_second_len_r_reg[3]_2 ;
+  wire [3:3]\\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED ;
+
+  FDRE \\axaddr_offset_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[47]_0 [0]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[47]_0 [1]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[47]_0 [2]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\axaddr_offset_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_payload_i_reg[47]_0 [3]),
+        .Q(\\axaddr_offset_r_reg[3]_0 [3]),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[0]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[3]_i_2__0_n_7 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[0] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [0]),
+        .O(\\axaddr_wrap[0]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[10]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[11]_i_2__0_n_5 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[10] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [10]),
+        .O(\\axaddr_wrap[10]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[11]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[11]_i_2__0_n_4 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[11] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [11]),
+        .O(\\axaddr_wrap[11]_i_1__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hF6)) 
+    \\axaddr_wrap[11]_i_3__0 
+       (.I0(\\wrap_cnt_r_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[3] ),
+        .I2(\\axaddr_wrap[11]_i_8__0_n_0 ),
+        .O(\\axaddr_wrap[11]_i_3__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_4__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[11] ),
+        .O(\\axaddr_wrap[11]_i_4__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_5__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[10] ),
+        .O(\\axaddr_wrap[11]_i_5__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_6__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[9] ),
+        .O(\\axaddr_wrap[11]_i_6__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[11]_i_7__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[8] ),
+        .O(\\axaddr_wrap[11]_i_7__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'h6FF6FFFFFFFF6FF6)) 
+    \\axaddr_wrap[11]_i_8__0 
+       (.I0(\\wrap_cnt_r_reg_n_0_[0] ),
+        .I1(\\axlen_cnt_reg_n_0_[0] ),
+        .I2(\\axlen_cnt_reg_n_0_[2] ),
+        .I3(\\wrap_cnt_r_reg_n_0_[2] ),
+        .I4(\\axlen_cnt_reg_n_0_[1] ),
+        .I5(\\wrap_cnt_r_reg_n_0_[1] ),
+        .O(\\axaddr_wrap[11]_i_8__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[1]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[3]_i_2__0_n_6 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[1] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [1]),
+        .O(\\axaddr_wrap[1]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[2]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[3]_i_2__0_n_5 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[2] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [2]),
+        .O(\\axaddr_wrap[2]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[3]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[3]_i_2__0_n_4 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[3] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [3]),
+        .O(\\axaddr_wrap[3]_i_1__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h6A)) 
+    \\axaddr_wrap[3]_i_3 
+       (.I0(\\axaddr_wrap_reg_n_0_[3] ),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axaddr_wrap[3]_i_4 
+       (.I0(\\axaddr_wrap_reg_n_0_[2] ),
+        .I1(\\m_payload_i_reg[47] [12]),
+        .I2(\\m_payload_i_reg[47] [13]),
+        .O(\\axaddr_wrap[3]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\axaddr_wrap[3]_i_5 
+       (.I0(\\axaddr_wrap_reg_n_0_[1] ),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8\'hA9)) 
+    \\axaddr_wrap[3]_i_6 
+       (.I0(\\axaddr_wrap_reg_n_0_[0] ),
+        .I1(\\m_payload_i_reg[47] [13]),
+        .I2(\\m_payload_i_reg[47] [12]),
+        .O(\\axaddr_wrap[3]_i_6_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[4]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[7]_i_2__0_n_7 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[4] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [4]),
+        .O(\\axaddr_wrap[4]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[5]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[7]_i_2__0_n_6 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[5] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [5]),
+        .O(\\axaddr_wrap[5]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[6]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[7]_i_2__0_n_5 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[6] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [6]),
+        .O(\\axaddr_wrap[6]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[7]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[7]_i_2__0_n_4 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[7] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [7]),
+        .O(\\axaddr_wrap[7]_i_1__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_3__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[7] ),
+        .O(\\axaddr_wrap[7]_i_3__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_4__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[6] ),
+        .O(\\axaddr_wrap[7]_i_4__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_5__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[5] ),
+        .O(\\axaddr_wrap[7]_i_5__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_wrap[7]_i_6__0 
+       (.I0(\\axaddr_wrap_reg_n_0_[4] ),
+        .O(\\axaddr_wrap[7]_i_6__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[8]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[11]_i_2__0_n_7 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[8] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [8]),
+        .O(\\axaddr_wrap[8]_i_1__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hB8FFB800)) 
+    \\axaddr_wrap[9]_i_1__0 
+       (.I0(\\axaddr_wrap_reg[11]_i_2__0_n_6 ),
+        .I1(\\axaddr_wrap[11]_i_3__0_n_0 ),
+        .I2(\\wrap_boundary_axaddr_r_reg_n_0_[9] ),
+        .I3(\\state_reg[1]_rep ),
+        .I4(\\m_payload_i_reg[47] [9]),
+        .O(\\axaddr_wrap[9]_i_1__0_n_0 ));
+  FDRE \\axaddr_wrap_reg[0] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[0]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[10] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[10]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[11] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[11]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[11] ),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[11]_i_2__0 
+       (.CI(\\axaddr_wrap_reg[7]_i_2__0_n_0 ),
+        .CO({\\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED [3],\\axaddr_wrap_reg[11]_i_2__0_n_1 ,\\axaddr_wrap_reg[11]_i_2__0_n_2 ,\\axaddr_wrap_reg[11]_i_2__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_wrap_reg[11]_i_2__0_n_4 ,\\axaddr_wrap_reg[11]_i_2__0_n_5 ,\\axaddr_wrap_reg[11]_i_2__0_n_6 ,\\axaddr_wrap_reg[11]_i_2__0_n_7 }),
+        .S({\\axaddr_wrap[11]_i_4__0_n_0 ,\\axaddr_wrap[11]_i_5__0_n_0 ,\\axaddr_wrap[11]_i_6__0_n_0 ,\\axaddr_wrap[11]_i_7__0_n_0 }));
+  FDRE \\axaddr_wrap_reg[1] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[1]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[2] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[2]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[3] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[3]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[3] ),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[3]_i_2__0 
+       (.CI(1\'b0),
+        .CO({\\axaddr_wrap_reg[3]_i_2__0_n_0 ,\\axaddr_wrap_reg[3]_i_2__0_n_1 ,\\axaddr_wrap_reg[3]_i_2__0_n_2 ,\\axaddr_wrap_reg[3]_i_2__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({\\axaddr_wrap_reg_n_0_[3] ,\\axaddr_wrap_reg_n_0_[2] ,\\axaddr_wrap_reg_n_0_[1] ,\\axaddr_wrap_reg_n_0_[0] }),
+        .O({\\axaddr_wrap_reg[3]_i_2__0_n_4 ,\\axaddr_wrap_reg[3]_i_2__0_n_5 ,\\axaddr_wrap_reg[3]_i_2__0_n_6 ,\\axaddr_wrap_reg[3]_i_2__0_n_7 }),
+        .S({\\axaddr_wrap[3]_i_3_n_0 ,\\axaddr_wrap[3]_i_4_n_0 ,\\axaddr_wrap[3]_i_5_n_0 ,\\axaddr_wrap[3]_i_6_n_0 }));
+  FDRE \\axaddr_wrap_reg[4] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[4]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[5] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[5]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[6] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[6]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[7] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[7]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[7] ),
+        .R(1\'b0));
+  CARRY4 \\axaddr_wrap_reg[7]_i_2__0 
+       (.CI(\\axaddr_wrap_reg[3]_i_2__0_n_0 ),
+        .CO({\\axaddr_wrap_reg[7]_i_2__0_n_0 ,\\axaddr_wrap_reg[7]_i_2__0_n_1 ,\\axaddr_wrap_reg[7]_i_2__0_n_2 ,\\axaddr_wrap_reg[7]_i_2__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O({\\axaddr_wrap_reg[7]_i_2__0_n_4 ,\\axaddr_wrap_reg[7]_i_2__0_n_5 ,\\axaddr_wrap_reg[7]_i_2__0_n_6 ,\\axaddr_wrap_reg[7]_i_2__0_n_7 }),
+        .S({\\axaddr_wrap[7]_i_3__0_n_0 ,\\axaddr_wrap[7]_i_4__0_n_0 ,\\axaddr_wrap[7]_i_5__0_n_0 ,\\axaddr_wrap[7]_i_6__0_n_0 }));
+  FDRE \\axaddr_wrap_reg[8] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[8]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\axaddr_wrap_reg[9] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axaddr_wrap[9]_i_1__0_n_0 ),
+        .Q(\\axaddr_wrap_reg_n_0_[9] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hA3A3A3A3A3A3A3A0)) 
+    \\axlen_cnt[0]_i_1__0 
+       (.I0(\\m_payload_i_reg[47] [15]),
+        .I1(\\axlen_cnt_reg_n_0_[0] ),
+        .I2(E),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[0]_i_1__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAC3AAC3AAC3AAC0)) 
+    \\axlen_cnt[1]_i_1__2 
+       (.I0(\\m_payload_i_reg[47] [16]),
+        .I1(\\axlen_cnt_reg_n_0_[1] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(E),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[1]_i_1__2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAAAACCC3AAAACCC0)) 
+    \\axlen_cnt[2]_i_1__2 
+       (.I0(\\m_payload_i_reg[47] [17]),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[0] ),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(E),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(\\axlen_cnt[2]_i_1__2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFAAA80000AAA8)) 
+    \\axlen_cnt[3]_i_1__2 
+       (.I0(\\axlen_cnt_reg_n_0_[3] ),
+        .I1(\\axlen_cnt_reg_n_0_[2] ),
+        .I2(\\axlen_cnt_reg_n_0_[1] ),
+        .I3(\\axlen_cnt_reg_n_0_[0] ),
+        .I4(E),
+        .I5(\\m_payload_i_reg[47] [18]),
+        .O(\\axlen_cnt[3]_i_1__2_n_0 ));
+  FDRE \\axlen_cnt_reg[0] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[0]_i_1__0_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[1] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[1]_i_1__2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[2] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[2]_i_1__2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\axlen_cnt_reg[3] 
+       (.C(aclk),
+        .CE(m_valid_i_reg),
+        .D(\\axlen_cnt[3]_i_1__2_n_0 ),
+        .Q(\\axlen_cnt_reg_n_0_[3] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[0]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[0] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [0]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [0]),
+        .O(m_axi_araddr[0]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[10]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[10] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[6]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [10]),
+        .O(m_axi_araddr[10]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[11]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[11] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[7]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [11]),
+        .O(m_axi_araddr[11]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[1]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[1] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [1]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [1]),
+        .O(m_axi_araddr[1]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[2]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[2] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [2]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [2]),
+        .O(m_axi_araddr[2]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[3]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[3] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(\\axaddr_incr_reg[3] [3]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [3]),
+        .O(m_axi_araddr[3]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[4]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[4] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[0]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [4]),
+        .O(m_axi_araddr[4]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[5]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[5] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[1]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [5]),
+        .O(m_axi_araddr[5]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[6]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[6] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[2]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [6]),
+        .O(m_axi_araddr[6]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[7]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[7] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[3]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [7]),
+        .O(m_axi_araddr[7]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[8]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[8] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[4]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [8]),
+        .O(m_axi_araddr[8]));
+  LUT6 #(
+    .INIT(64\'hEFE0EFEF4F404040)) 
+    \\m_axi_araddr[9]_INST_0 
+       (.I0(sel_first_reg_0),
+        .I1(\\axaddr_wrap_reg_n_0_[9] ),
+        .I2(\\m_payload_i_reg[47] [14]),
+        .I3(axaddr_incr_reg[5]),
+        .I4(\\m_payload_i_reg[38] ),
+        .I5(\\m_payload_i_reg[47] [9]),
+        .O(m_axi_araddr[9]));
+  LUT6 #(
+    .INIT(64\'hFBFBFBFBFBFBFB00)) 
+    next_pending_r_i_2__2
+       (.I0(\\state_reg[1] [0]),
+        .I1(si_rs_arvalid),
+        .I2(\\state_reg[1] [1]),
+        .I3(\\axlen_cnt_reg_n_0_[1] ),
+        .I4(\\axlen_cnt_reg_n_0_[2] ),
+        .I5(\\axlen_cnt_reg_n_0_[3] ),
+        .O(next_pending_r_reg_1));
+  FDRE next_pending_r_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(wrap_next_pending),
+        .Q(next_pending_r_reg_0),
+        .R(1\'b0));
+  FDRE sel_first_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(sel_first_reg_1),
+        .Q(sel_first_reg_0),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [0]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [10]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [11]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [1]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [2]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [3]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [4]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [5]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[6] [6]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [7]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [8]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\wrap_boundary_axaddr_r_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(\\m_payload_i_reg[47] [9]),
+        .Q(\\wrap_boundary_axaddr_r_reg_n_0_[9] ),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h13D320E0)) 
+    \\wrap_cnt_r[1]_i_1 
+       (.I0(\\wrap_second_len_r_reg[3]_0 [0]),
+        .I1(E),
+        .I2(\\axaddr_offset_r_reg[3]_1 ),
+        .I3(\\m_payload_i_reg[35] ),
+        .I4(\\wrap_second_len_r_reg[3]_0 [1]),
+        .O(\\wrap_cnt_r[1]_i_1_n_0 ));
+  FDRE \\wrap_cnt_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [0]),
+        .Q(\\wrap_cnt_r_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_cnt_r[1]_i_1_n_0 ),
+        .Q(\\wrap_cnt_r_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [1]),
+        .Q(\\wrap_cnt_r_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\wrap_cnt_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_2 [2]),
+        .Q(\\wrap_cnt_r_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [0]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [0]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [1]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [1]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [2]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [2]),
+        .R(1\'b0));
+  FDRE \\wrap_second_len_r_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\wrap_second_len_r_reg[3]_1 [3]),
+        .Q(\\wrap_second_len_r_reg[3]_0 [3]),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axi_register_slice
+   (s_axi_awready,
+    s_axi_arready,
+    si_rs_awvalid,
+    s_axi_bvalid,
+    si_rs_bready,
+    si_rs_arvalid,
+    s_axi_rvalid,
+    si_rs_rready,
+    D,
+    wrap_second_len,
+    Q,
+    \\s_arid_r_reg[11] ,
+    \\axaddr_incr_reg[11] ,
+    CO,
+    O,
+    \\axaddr_incr_reg[7] ,
+    \\axaddr_incr_reg[11]_0 ,
+    \\axaddr_incr_reg[7]_0 ,
+    \\axaddr_incr_reg[3] ,
+    axaddr_offset,
+    \\axlen_cnt_reg[3] ,
+    next_pending_r_reg,
+    shandshake,
+    \\wrap_cnt_r_reg[2] ,
+    \\wrap_second_len_r_reg[2] ,
+    \\wrap_cnt_r_reg[2]_0 ,
+    \\axaddr_offset_r_reg[3] ,
+    \\axaddr_offset_r_reg[1] ,
+    \\wrap_second_len_r_reg[3] ,
+    next_pending_r_reg_0,
+    \\axlen_cnt_reg[3]_0 ,
+    \\wrap_boundary_axaddr_r_reg[6] ,
+    \\axaddr_offset_r_reg[0] ,
+    \\wrap_boundary_axaddr_r_reg[6]_0 ,
+    \\m_axi_awaddr[10] ,
+    \\m_axi_araddr[10] ,
+    \\s_axi_bid[11] ,
+    \\s_axi_rid[11] ,
+    aclk,
+    m_valid_i0,
+    aresetn,
+    \\cnt_read_reg[3]_rep__2 ,
+    s_axi_rready,
+    S,
+    \\m_payload_i_reg[3] ,
+    \\state_reg[1] ,
+    \\wrap_second_len_r_reg[3]_0 ,
+    \\state_reg[1]_0 ,
+    \\axaddr_offset_r_reg[3]_0 ,
+    s_axi_awvalid,
+    b_push,
+    si_rs_bvalid,
+    \\wrap_second_len_r_reg[2]_0 ,
+    \\state_reg[1]_rep ,
+    axaddr_offset_0,
+    \\axaddr_offset_r_reg[3]_1 ,
+    \\state_reg[1]_rep_0 ,
+    \\state_reg[0]_rep ,
+    sel_first,
+    sel_first_1,
+    s_axi_bready,
+    s_axi_arvalid,
+    s_axi_awid,
+    s_axi_awlen,
+    s_axi_awburst,
+    s_axi_awsize,
+    s_axi_awprot,
+    s_axi_awaddr,
+    s_axi_arid,
+    s_axi_arlen,
+    s_axi_arburst,
+    s_axi_arsize,
+    s_axi_arprot,
+    s_axi_araddr,
+    out,
+    \\s_bresp_acc_reg[1] ,
+    r_push_r_reg,
+    \\cnt_read_reg[4] ,
+    axaddr_incr_reg,
+    \\axaddr_incr_reg[3]_0 ,
+    E,
+    \\state_reg[1]_rep_1 );
+  output s_axi_awready;
+  output s_axi_arready;
+  output si_rs_awvalid;
+  output s_axi_bvalid;
+  output si_rs_bready;
+  output si_rs_arvalid;
+  output s_axi_rvalid;
+  output si_rs_rready;
+  output [3:0]D;
+  output [3:0]wrap_second_len;
+  output [53:0]Q;
+  output [53:0]\\s_arid_r_reg[11] ;
+  output [7:0]\\axaddr_incr_reg[11] ;
+  output [0:0]CO;
+  output [3:0]O;
+  output [3:0]\\axaddr_incr_reg[7] ;
+  output [3:0]\\axaddr_incr_reg[11]_0 ;
+  output [0:0]\\axaddr_incr_reg[7]_0 ;
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output [3:0]axaddr_offset;
+  output \\axlen_cnt_reg[3] ;
+  output next_pending_r_reg;
+  output shandshake;
+  output [0:0]\\wrap_cnt_r_reg[2] ;
+  output [1:0]\\wrap_second_len_r_reg[2] ;
+  output \\wrap_cnt_r_reg[2]_0 ;
+  output [2:0]\\axaddr_offset_r_reg[3] ;
+  output \\axaddr_offset_r_reg[1] ;
+  output \\wrap_second_len_r_reg[3] ;
+  output next_pending_r_reg_0;
+  output \\axlen_cnt_reg[3]_0 ;
+  output [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  output \\axaddr_offset_r_reg[0] ;
+  output [6:0]\\wrap_boundary_axaddr_r_reg[6]_0 ;
+  output \\m_axi_awaddr[10] ;
+  output \\m_axi_araddr[10] ;
+  output [13:0]\\s_axi_bid[11] ;
+  output [46:0]\\s_axi_rid[11] ;
+  input aclk;
+  input m_valid_i0;
+  input aresetn;
+  input \\cnt_read_reg[3]_rep__2 ;
+  input s_axi_rready;
+  input [3:0]S;
+  input [3:0]\\m_payload_i_reg[3] ;
+  input \\state_reg[1] ;
+  input [3:0]\\wrap_second_len_r_reg[3]_0 ;
+  input [1:0]\\state_reg[1]_0 ;
+  input [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  input s_axi_awvalid;
+  input b_push;
+  input si_rs_bvalid;
+  input [2:0]\\wrap_second_len_r_reg[2]_0 ;
+  input \\state_reg[1]_rep ;
+  input [0:0]axaddr_offset_0;
+  input [2:0]\\axaddr_offset_r_reg[3]_1 ;
+  input \\state_reg[1]_rep_0 ;
+  input \\state_reg[0]_rep ;
+  input sel_first;
+  input sel_first_1;
+  input s_axi_bready;
+  input s_axi_arvalid;
+  input [11:0]s_axi_awid;
+  input [3:0]s_axi_awlen;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awsize;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_awaddr;
+  input [11:0]s_axi_arid;
+  input [3:0]s_axi_arlen;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arsize;
+  input [2:0]s_axi_arprot;
+  input [31:0]s_axi_araddr;
+  input [11:0]out;
+  input [1:0]\\s_bresp_acc_reg[1] ;
+  input [12:0]r_push_r_reg;
+  input [33:0]\\cnt_read_reg[4] ;
+  input [3:0]axaddr_incr_reg;
+  input [3:0]\\axaddr_incr_reg[3]_0 ;
+  input [0:0]E;
+  input [0:0]\\state_reg[1]_rep_1 ;
+
+  wire [0:0]CO;
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [53:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire ar_pipe_n_2;
+  wire aresetn;
+  wire aw_pipe_n_1;
+  wire aw_pipe_n_92;
+  wire [3:0]axaddr_incr_reg;
+  wire [7:0]\\axaddr_incr_reg[11] ;
+  wire [3:0]\\axaddr_incr_reg[11]_0 ;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_incr_reg[3]_0 ;
+  wire [3:0]\\axaddr_incr_reg[7] ;
+  wire [0:0]\\axaddr_incr_reg[7]_0 ;
+  wire [3:0]axaddr_offset;
+  wire [0:0]axaddr_offset_0;
+  wire \\axaddr_offset_r_reg[0] ;
+  wire \\axaddr_offset_r_reg[1] ;
+  wire [2:0]\\axaddr_offset_r_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire [2:0]\\axaddr_offset_r_reg[3]_1 ;
+  wire \\axlen_cnt_reg[3] ;
+  wire \\axlen_cnt_reg[3]_0 ;
+  wire b_push;
+  wire \\cnt_read_reg[3]_rep__2 ;
+  wire [33:0]\\cnt_read_reg[4] ;
+  wire \\m_axi_araddr[10] ;
+  wire \\m_axi_awaddr[10] ;
+  wire [3:0]\\m_payload_i_reg[3] ;
+  wire m_valid_i0;
+  wire next_pending_r_reg;
+  wire next_pending_r_reg_0;
+  wire [11:0]out;
+  wire [12:0]r_push_r_reg;
+  wire [53:0]\\s_arid_r_reg[11] ;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [2:0]s_axi_arprot;
+  wire s_axi_arready;
+  wire [1:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [2:0]s_axi_awprot;
+  wire s_axi_awready;
+  wire [1:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire [13:0]\\s_axi_bid[11] ;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [46:0]\\s_axi_rid[11] ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [1:0]\\s_bresp_acc_reg[1] ;
+  wire sel_first;
+  wire sel_first_1;
+  wire shandshake;
+  wire si_rs_arvalid;
+  wire si_rs_awvalid;
+  wire si_rs_bready;
+  wire si_rs_bvalid;
+  wire si_rs_rready;
+  wire \\state_reg[0]_rep ;
+  wire \\state_reg[1] ;
+  wire [1:0]\\state_reg[1]_0 ;
+  wire \\state_reg[1]_rep ;
+  wire \\state_reg[1]_rep_0 ;
+  wire [0:0]\\state_reg[1]_rep_1 ;
+  wire [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  wire [6:0]\\wrap_boundary_axaddr_r_reg[6]_0 ;
+  wire [0:0]\\wrap_cnt_r_reg[2] ;
+  wire \\wrap_cnt_r_reg[2]_0 ;
+  wire [3:0]wrap_second_len;
+  wire [1:0]\\wrap_second_len_r_reg[2] ;
+  wire [2:0]\\wrap_second_len_r_reg[2]_0 ;
+  wire \\wrap_second_len_r_reg[3] ;
+  wire [3:0]\\wrap_second_len_r_reg[3]_0 ;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice ar_pipe
+       (.Q(\\s_arid_r_reg[11] ),
+        .aclk(aclk),
+        .\\aresetn_d_reg[0] (aw_pipe_n_1),
+        .\\aresetn_d_reg[0]_0 (aw_pipe_n_92),
+        .\\axaddr_incr_reg[11] (\\axaddr_incr_reg[11]_0 ),
+        .\\axaddr_incr_reg[3] (\\axaddr_incr_reg[3] ),
+        .\\axaddr_incr_reg[3]_0 (\\axaddr_incr_reg[3]_0 ),
+        .\\axaddr_incr_reg[7] (\\axaddr_incr_reg[7] ),
+        .\\axaddr_incr_reg[7]_0 (\\axaddr_incr_reg[7]_0 ),
+        .axaddr_offset_0(axaddr_offset_0),
+        .\\axaddr_offset_r_reg[0] (\\axaddr_offset_r_reg[0] ),
+        .\\axaddr_offset_r_reg[1] (\\axaddr_offset_r_reg[1] ),
+        .\\axaddr_offset_r_reg[2] (\\axaddr_offset_r_reg[3] [1]),
+        .\\axaddr_offset_r_reg[3] ({\\axaddr_offset_r_reg[3] [2],\\axaddr_offset_r_reg[3] [0]}),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3]_1 ),
+        .\\axlen_cnt_reg[3] (\\axlen_cnt_reg[3]_0 ),
+        .\\m_axi_araddr[10] (\\m_axi_araddr[10] ),
+        .\\m_payload_i_reg[3]_0 (\\m_payload_i_reg[3] ),
+        .m_valid_i0(m_valid_i0),
+        .m_valid_i_reg_0(ar_pipe_n_2),
+        .next_pending_r_reg(next_pending_r_reg_0),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize(s_axi_arsize),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_ready_i_reg_0(si_rs_arvalid),
+        .sel_first_1(sel_first_1),
+        .\\state_reg[0]_rep (\\state_reg[0]_rep ),
+        .\\state_reg[1]_rep (\\state_reg[1]_rep ),
+        .\\state_reg[1]_rep_0 (\\state_reg[1]_rep_0 ),
+        .\\state_reg[1]_rep_1 (\\state_reg[1]_rep_1 ),
+        .\\wrap_boundary_axaddr_r_reg[6] (\\wrap_boundary_axaddr_r_reg[6] ),
+        .\\wrap_cnt_r_reg[2] (\\wrap_cnt_r_reg[2] ),
+        .\\wrap_cnt_r_reg[2]_0 (\\wrap_cnt_r_reg[2]_0 ),
+        .\\wrap_second_len_r_reg[2] (\\wrap_second_len_r_reg[2] ),
+        .\\wrap_second_len_r_reg[2]_0 (\\wrap_second_len_r_reg[2]_0 ),
+        .\\wrap_second_len_r_reg[3] (\\wrap_second_len_r_reg[3] ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice_0 aw_pipe
+       (.CO(CO),
+        .D(D),
+        .E(E),
+        .O(O),
+        .Q(Q),
+        .S(S),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .\\aresetn_d_reg[1]_inv (aw_pipe_n_92),
+        .\\aresetn_d_reg[1]_inv_0 (ar_pipe_n_2),
+        .axaddr_incr_reg(axaddr_incr_reg),
+        .\\axaddr_incr_reg[11] (\\axaddr_incr_reg[11] ),
+        .axaddr_offset({axaddr_offset[2],axaddr_offset[0]}),
+        .\\axaddr_offset_r_reg[1] (axaddr_offset[1]),
+        .\\axaddr_offset_r_reg[3] (axaddr_offset[3]),
+        .\\axaddr_offset_r_reg[3]_0 (\\axaddr_offset_r_reg[3]_0 ),
+        .\\axlen_cnt_reg[3] (\\axlen_cnt_reg[3] ),
+        .b_push(b_push),
+        .\\m_axi_awaddr[10] (\\m_axi_awaddr[10] ),
+        .m_valid_i_reg_0(si_rs_awvalid),
+        .next_pending_r_reg(next_pending_r_reg),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize(s_axi_awsize),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_ready_i_reg_0(aw_pipe_n_1),
+        .sel_first(sel_first),
+        .\\state_reg[1] (\\state_reg[1] ),
+        .\\state_reg[1]_0 (\\state_reg[1]_0 ),
+        .\\wrap_boundary_axaddr_r_reg[6] (\\wrap_boundary_axaddr_r_reg[6]_0 ),
+        .wrap_second_len({wrap_second_len[3:2],wrap_second_len[0]}),
+        .\\wrap_second_len_r_reg[1] (wrap_second_len[1]),
+        .\\wrap_second_len_r_reg[3] (\\wrap_second_len_r_reg[3]_0 ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice__parameterized1 b_pipe
+       (.aclk(aclk),
+        .\\aresetn_d_reg[0] (aw_pipe_n_1),
+        .\\aresetn_d_reg[1]_inv (ar_pipe_n_2),
+        .out(out),
+        .\\s_axi_bid[11] (\\s_axi_bid[11] ),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_bresp_acc_reg[1] (\\s_bresp_acc_reg[1] ),
+        .shandshake(shandshake),
+        .si_rs_bvalid(si_rs_bvalid),
+        .\\skid_buffer_reg[0]_0 (si_rs_bready));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice__parameterized2 r_pipe
+       (.aclk(aclk),
+        .\\aresetn_d_reg[0] (aw_pipe_n_1),
+        .\\aresetn_d_reg[1]_inv (ar_pipe_n_2),
+        .\\cnt_read_reg[3]_rep__2 (\\cnt_read_reg[3]_rep__2 ),
+        .\\cnt_read_reg[4] (\\cnt_read_reg[4] ),
+        .r_push_r_reg(r_push_r_reg),
+        .\\s_axi_rid[11] (\\s_axi_rid[11] ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .\\skid_buffer_reg[0]_0 (si_rs_rready));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice
+   (s_axi_arready,
+    s_ready_i_reg_0,
+    m_valid_i_reg_0,
+    Q,
+    \\axaddr_incr_reg[7] ,
+    \\axaddr_incr_reg[11] ,
+    \\axaddr_incr_reg[7]_0 ,
+    \\axaddr_incr_reg[3] ,
+    \\wrap_cnt_r_reg[2] ,
+    \\wrap_second_len_r_reg[2] ,
+    \\wrap_cnt_r_reg[2]_0 ,
+    \\axaddr_offset_r_reg[2] ,
+    \\axaddr_offset_r_reg[3] ,
+    \\axaddr_offset_r_reg[1] ,
+    \\wrap_second_len_r_reg[3] ,
+    next_pending_r_reg,
+    \\axlen_cnt_reg[3] ,
+    \\wrap_boundary_axaddr_r_reg[6] ,
+    \\axaddr_offset_r_reg[0] ,
+    \\m_axi_araddr[10] ,
+    \\aresetn_d_reg[0] ,
+    aclk,
+    m_valid_i0,
+    \\aresetn_d_reg[0]_0 ,
+    \\m_payload_i_reg[3]_0 ,
+    \\wrap_second_len_r_reg[2]_0 ,
+    \\state_reg[1]_rep ,
+    axaddr_offset_0,
+    \\axaddr_offset_r_reg[3]_0 ,
+    \\state_reg[1]_rep_0 ,
+    \\state_reg[0]_rep ,
+    sel_first_1,
+    s_axi_arvalid,
+    s_axi_arid,
+    s_axi_arlen,
+    s_axi_arburst,
+    s_axi_arsize,
+    s_axi_arprot,
+    s_axi_araddr,
+    \\axaddr_incr_reg[3]_0 ,
+    \\state_reg[1]_rep_1 );
+  output s_axi_arready;
+  output s_ready_i_reg_0;
+  output m_valid_i_reg_0;
+  output [53:0]Q;
+  output [3:0]\\axaddr_incr_reg[7] ;
+  output [3:0]\\axaddr_incr_reg[11] ;
+  output [0:0]\\axaddr_incr_reg[7]_0 ;
+  output [3:0]\\axaddr_incr_reg[3] ;
+  output [0:0]\\wrap_cnt_r_reg[2] ;
+  output [1:0]\\wrap_second_len_r_reg[2] ;
+  output \\wrap_cnt_r_reg[2]_0 ;
+  output \\axaddr_offset_r_reg[2] ;
+  output [1:0]\\axaddr_offset_r_reg[3] ;
+  output \\axaddr_offset_r_reg[1] ;
+  output \\wrap_second_len_r_reg[3] ;
+  output next_pending_r_reg;
+  output \\axlen_cnt_reg[3] ;
+  output [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  output \\axaddr_offset_r_reg[0] ;
+  output \\m_axi_araddr[10] ;
+  input \\aresetn_d_reg[0] ;
+  input aclk;
+  input m_valid_i0;
+  input \\aresetn_d_reg[0]_0 ;
+  input [3:0]\\m_payload_i_reg[3]_0 ;
+  input [2:0]\\wrap_second_len_r_reg[2]_0 ;
+  input \\state_reg[1]_rep ;
+  input [0:0]axaddr_offset_0;
+  input [2:0]\\axaddr_offset_r_reg[3]_0 ;
+  input \\state_reg[1]_rep_0 ;
+  input \\state_reg[0]_rep ;
+  input sel_first_1;
+  input s_axi_arvalid;
+  input [11:0]s_axi_arid;
+  input [3:0]s_axi_arlen;
+  input [1:0]s_axi_arburst;
+  input [1:0]s_axi_arsize;
+  input [2:0]s_axi_arprot;
+  input [31:0]s_axi_araddr;
+  input [3:0]\\axaddr_incr_reg[3]_0 ;
+  input [0:0]\\state_reg[1]_rep_1 ;
+
+  wire [53:0]Q;
+  wire aclk;
+  wire \\aresetn_d_reg[0] ;
+  wire \\aresetn_d_reg[0]_0 ;
+  wire \\axaddr_incr[0]_i_10__0_n_0 ;
+  wire \\axaddr_incr[0]_i_12__0_n_0 ;
+  wire \\axaddr_incr[0]_i_13__0_n_0 ;
+  wire \\axaddr_incr[0]_i_14__0_n_0 ;
+  wire \\axaddr_incr[0]_i_3__0_n_0 ;
+  wire \\axaddr_incr[0]_i_4__0_n_0 ;
+  wire \\axaddr_incr[0]_i_5__0_n_0 ;
+  wire \\axaddr_incr[0]_i_6__0_n_0 ;
+  wire \\axaddr_incr[0]_i_7__0_n_0 ;
+  wire \\axaddr_incr[0]_i_8__0_n_0 ;
+  wire \\axaddr_incr[0]_i_9__0_n_0 ;
+  wire \\axaddr_incr[4]_i_10__0_n_0 ;
+  wire \\axaddr_incr[4]_i_7__0_n_0 ;
+  wire \\axaddr_incr[4]_i_8__0_n_0 ;
+  wire \\axaddr_incr[4]_i_9__0_n_0 ;
+  wire \\axaddr_incr[8]_i_10__0_n_0 ;
+  wire \\axaddr_incr[8]_i_7__0_n_0 ;
+  wire \\axaddr_incr[8]_i_8__0_n_0 ;
+  wire \\axaddr_incr[8]_i_9__0_n_0 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_0 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_1 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_2 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_3 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_4 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_5 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_6 ;
+  wire \\axaddr_incr_reg[0]_i_11__0_n_7 ;
+  wire \\axaddr_incr_reg[0]_i_2__0_n_1 ;
+  wire \\axaddr_incr_reg[0]_i_2__0_n_2 ;
+  wire \\axaddr_incr_reg[0]_i_2__0_n_3 ;
+  wire [3:0]\\axaddr_incr_reg[11] ;
+  wire [3:0]\\axaddr_incr_reg[3] ;
+  wire [3:0]\\axaddr_incr_reg[3]_0 ;
+  wire \\axaddr_incr_reg[4]_i_6__0_n_0 ;
+  wire \\axaddr_incr_reg[4]_i_6__0_n_1 ;
+  wire \\axaddr_incr_reg[4]_i_6__0_n_2 ;
+  wire \\axaddr_incr_reg[4]_i_6__0_n_3 ;
+  wire [3:0]\\axaddr_incr_reg[7] ;
+  wire [0:0]\\axaddr_incr_reg[7]_0 ;
+  wire \\axaddr_incr_reg[8]_i_6__0_n_1 ;
+  wire \\axaddr_incr_reg[8]_i_6__0_n_2 ;
+  wire \\axaddr_incr_reg[8]_i_6__0_n_3 ;
+  wire [0:0]axaddr_offset_0;
+  wire \\axaddr_offset_r[1]_i_3_n_0 ;
+  wire \\axaddr_offset_r[2]_i_2__0_n_0 ;
+  wire \\axaddr_offset_r[2]_i_3__0_n_0 ;
+  wire \\axaddr_offset_r[3]_i_2__0_n_0 ;
+  wire \\axaddr_offset_r_reg[0] ;
+  wire \\axaddr_offset_r_reg[1] ;
+  wire \\axaddr_offset_r_reg[2] ;
+  wire [1:0]\\axaddr_offset_r_reg[3] ;
+  wire [2:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire \\axlen_cnt_reg[3] ;
+  wire \\m_axi_araddr[10] ;
+  wire \\m_payload_i[0]_i_1__0_n_0 ;
+  wire \\m_payload_i[10]_i_1__0_n_0 ;
+  wire \\m_payload_i[11]_i_1__0_n_0 ;
+  wire \\m_payload_i[12]_i_1__0_n_0 ;
+  wire \\m_payload_i[13]_i_1__1_n_0 ;
+  wire \\m_payload_i[14]_i_1__0_n_0 ;
+  wire \\m_payload_i[15]_i_1__0_n_0 ;
+  wire \\m_payload_i[16]_i_1__0_n_0 ;
+  wire \\m_payload_i[17]_i_1__0_n_0 ;
+  wire \\m_payload_i[18]_i_1__0_n_0 ;
+  wire \\m_payload_i[19]_i_1__0_n_0 ;
+  wire \\m_payload_i[1]_i_1__0_n_0 ;
+  wire \\m_payload_i[20]_i_1__0_n_0 ;
+  wire \\m_payload_i[21]_i_1__0_n_0 ;
+  wire \\m_payload_i[22]_i_1__0_n_0 ;
+  wire \\m_payload_i[23]_i_1__0_n_0 ;
+  wire \\m_payload_i[24]_i_1__0_n_0 ;
+  wire \\m_payload_i[25]_i_1__0_n_0 ;
+  wire \\m_payload_i[26]_i_1__0_n_0 ;
+  wire \\m_payload_i[27]_i_1__0_n_0 ;
+  wire \\m_payload_i[28]_i_1__0_n_0 ;
+  wire \\m_payload_i[29]_i_1__0_n_0 ;
+  wire \\m_payload_i[2]_i_1__0_n_0 ;
+  wire \\m_payload_i[30]_i_1__0_n_0 ;
+  wire \\m_payload_i[31]_i_2__0_n_0 ;
+  wire \\m_payload_i[32]_i_1__0_n_0 ;
+  wire \\m_payload_i[33]_i_1__0_n_0 ;
+  wire \\m_payload_i[34]_i_1__0_n_0 ;
+  wire \\m_payload_i[35]_i_1__0_n_0 ;
+  wire \\m_payload_i[36]_i_1__0_n_0 ;
+  wire \\m_payload_i[38]_i_1__0_n_0 ;
+  wire \\m_payload_i[39]_i_1__0_n_0 ;
+  wire \\m_payload_i[3]_i_1__0_n_0 ;
+  wire \\m_payload_i[44]_i_1__0_n_0 ;
+  wire \\m_payload_i[45]_i_1__0_n_0 ;
+  wire \\m_payload_i[46]_i_1__1_n_0 ;
+  wire \\m_payload_i[47]_i_1__0_n_0 ;
+  wire \\m_payload_i[4]_i_1__0_n_0 ;
+  wire \\m_payload_i[50]_i_1__0_n_0 ;
+  wire \\m_payload_i[51]_i_1__0_n_0 ;
+  wire \\m_payload_i[52]_i_1__0_n_0 ;
+  wire \\m_payload_i[53]_i_1__0_n_0 ;
+  wire \\m_payload_i[54]_i_1__0_n_0 ;
+  wire \\m_payload_i[55]_i_1__0_n_0 ;
+  wire \\m_payload_i[56]_i_1__0_n_0 ;
+  wire \\m_payload_i[57]_i_1__0_n_0 ;
+  wire \\m_payload_i[58]_i_1__0_n_0 ;
+  wire \\m_payload_i[59]_i_1__0_n_0 ;
+  wire \\m_payload_i[5]_i_1__0_n_0 ;
+  wire \\m_payload_i[60]_i_1__0_n_0 ;
+  wire \\m_payload_i[61]_i_1__0_n_0 ;
+  wire \\m_payload_i[6]_i_1__0_n_0 ;
+  wire \\m_payload_i[7]_i_1__0_n_0 ;
+  wire \\m_payload_i[8]_i_1__0_n_0 ;
+  wire \\m_payload_i[9]_i_1__0_n_0 ;
+  wire [3:0]\\m_payload_i_reg[3]_0 ;
+  wire \\m_payload_i_reg_n_0_[38] ;
+  wire m_valid_i0;
+  wire m_valid_i_reg_0;
+  wire next_pending_r_reg;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [2:0]s_axi_arprot;
+  wire s_axi_arready;
+  wire [1:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire s_ready_i0;
+  wire s_ready_i_reg_0;
+  wire sel_first_1;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[2'b'4] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[35] ;
+  wire \\skid_buffer_reg_n_0_[36] ;
+  wire \\skid_buffer_reg_n_0_[38] ;
+  wire \\skid_buffer_reg_n_0_[39] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[44] ;
+  wire \\skid_buffer_reg_n_0_[45] ;
+  wire \\skid_buffer_reg_n_0_[46] ;
+  wire \\skid_buffer_reg_n_0_[47] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[50] ;
+  wire \\skid_buffer_reg_n_0_[51] ;
+  wire \\skid_buffer_reg_n_0_[52] ;
+  wire \\skid_buffer_reg_n_0_[53] ;
+  wire \\skid_buffer_reg_n_0_[54] ;
+  wire \\skid_buffer_reg_n_0_[55] ;
+  wire \\skid_buffer_reg_n_0_[56] ;
+  wire \\skid_buffer_reg_n_0_[57] ;
+  wire \\skid_buffer_reg_n_0_[58] ;
+  wire \\skid_buffer_reg_n_0_[59] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[60] ;
+  wire \\skid_buffer_reg_n_0_[61] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire \\state_reg[0]_rep ;
+  wire \\state_reg[1]_rep ;
+  wire \\state_reg[1]_rep_0 ;
+  wire [0:0]\\state_reg[1]_rep_1 ;
+  wire \\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
+  wire [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  wire [0:0]\\wrap_cnt_r_reg[2] ;
+  wire \\wrap_cnt_r_reg[2]_0 ;
+  wire [1:0]\\wrap_second_len_r_reg[2] ;
+  wire [2:0]\\wrap_second_len_r_reg[2]_0 ;
+  wire \\wrap_second_len_r_reg[3] ;
+  wire [3:3]\\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED ;
+
+  FDRE #(
+    .INIT(1\'b1)) 
+    \\aresetn_d_reg[1]_inv 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\aresetn_d_reg[0]_0 ),
+        .Q(m_valid_i_reg_0),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hFFE100E1)) 
+    \\axaddr_incr[0]_i_10__0 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(\\axaddr_incr_reg[3]_0 [0]),
+        .I3(sel_first_1),
+        .I4(\\axaddr_incr_reg[0]_i_11__0_n_7 ),
+        .O(\\axaddr_incr[0]_i_10__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h2A)) 
+    \\axaddr_incr[0]_i_12__0 
+       (.I0(Q[2]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .O(\\axaddr_incr[0]_i_12__0_n_0 ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\axaddr_incr[0]_i_13__0 
+       (.I0(Q[1]),
+        .I1(Q[36]),
+        .O(\\axaddr_incr[0]_i_13__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h02)) 
+    \\axaddr_incr[0]_i_14__0 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .O(\\axaddr_incr[0]_i_14__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\axaddr_incr[0]_i_3__0 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first_1),
+        .O(\\axaddr_incr[0]_i_3__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\axaddr_incr[0]_i_4__0 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(sel_first_1),
+        .O(\\axaddr_incr[0]_i_4__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\axaddr_incr[0]_i_5__0 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first_1),
+        .O(\\axaddr_incr[0]_i_5__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'h01)) 
+    \\axaddr_incr[0]_i_6__0 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first_1),
+        .O(\\axaddr_incr[0]_i_6__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFF780078)) 
+    \\axaddr_incr[0]_i_7__0 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(\\axaddr_incr_reg[3]_0 [3]),
+        .I3(sel_first_1),
+        .I4(\\axaddr_incr_reg[0]_i_11__0_n_4 ),
+        .O(\\axaddr_incr[0]_i_7__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFD200D2)) 
+    \\axaddr_incr[0]_i_8__0 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(\\axaddr_incr_reg[3]_0 [2]),
+        .I3(sel_first_1),
+        .I4(\\axaddr_incr_reg[0]_i_11__0_n_5 ),
+        .O(\\axaddr_incr[0]_i_8__0_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFD200D2)) 
+    \\axaddr_incr[0]_i_9__0 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(\\axaddr_incr_reg[3]_0 [1]),
+        .I3(sel_first_1),
+        .I4(\\axaddr_incr_reg[0]_i_11__0_n_6 ),
+        .O(\\axaddr_incr[0]_i_9__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_10__0 
+       (.I0(Q[4]),
+        .O(\\axaddr_incr[4]_i_10__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_7__0 
+       (.I0(Q[7]),
+        .O(\\axaddr_incr[4]_i_7__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_8__0 
+       (.I0(Q[6]),
+        .O(\\axaddr_incr[4]_i_8__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_9__0 
+       (.I0(Q[5]),
+        .O(\\axaddr_incr[4]_i_9__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_10__0 
+       (.I0(Q[8]),
+        .O(\\axaddr_incr[8]_i_10__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_7__0 
+       (.I0(Q[11]),
+        .O(\\axaddr_incr[8]_i_7__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_8__0 
+       (.I0(Q[10]),
+        .O(\\axaddr_incr[8]_i_8__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_9__0 
+       (.I0(Q[9]),
+        .O(\\axaddr_incr[8]_i_9__0_n_0 ));
+  CARRY4 \\axaddr_incr_reg[0]_i_11__0 
+       (.CI(1\'b0),
+        .CO({\\axaddr_incr_reg[0]_i_11__0_n_0 ,\\axaddr_incr_reg[0]_i_11__0_n_1 ,\\axaddr_incr_reg[0]_i_11__0_n_2 ,\\axaddr_incr_reg[0]_i_11__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({Q[3],\\axaddr_incr[0]_i_12__0_n_0 ,\\axaddr_incr[0]_i_13__0_n_0 ,\\axaddr_incr[0]_i_14__0_n_0 }),
+        .O({\\axaddr_incr_reg[0]_i_11__0_n_4 ,\\axaddr_incr_reg[0]_i_11__0_n_5 ,\\axaddr_incr_reg[0]_i_11__0_n_6 ,\\axaddr_incr_reg[0]_i_11__0_n_7 }),
+        .S(\\m_payload_i_reg[3]_0 ));
+  CARRY4 \\axaddr_incr_reg[0]_i_2__0 
+       (.CI(1\'b0),
+        .CO({\\axaddr_incr_reg[7]_0 ,\\axaddr_incr_reg[0]_i_2__0_n_1 ,\\axaddr_incr_reg[0]_i_2__0_n_2 ,\\axaddr_incr_reg[0]_i_2__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({\\axaddr_incr[0]_i_3__0_n_0 ,\\axaddr_incr[0]_i_4__0_n_0 ,\\axaddr_incr[0]_i_5__0_n_0 ,\\axaddr_incr[0]_i_6__0_n_0 }),
+        .O(\\axaddr_incr_reg[3] ),
+        .S({\\axaddr_incr[0]_i_7__0_n_0 ,\\axaddr_incr[0]_i_8__0_n_0 ,\\axaddr_incr[0]_i_9__0_n_0 ,\\axaddr_incr[0]_i_10__0_n_0 }));
+  CARRY4 \\axaddr_incr_reg[4]_i_6__0 
+       (.CI(\\axaddr_incr_reg[0]_i_11__0_n_0 ),
+        .CO({\\axaddr_incr_reg[4]_i_6__0_n_0 ,\\axaddr_incr_reg[4]_i_6__0_n_1 ,\\axaddr_incr_reg[4]_i_6__0_n_2 ,\\axaddr_incr_reg[4]_i_6__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(\\axaddr_incr_reg[7] ),
+        .S({\\axaddr_incr[4]_i_7__0_n_0 ,\\axaddr_incr[4]_i_8__0_n_0 ,\\axaddr_incr[4]_i_9__0_n_0 ,\\axaddr_incr[4]_i_10__0_n_0 }));
+  CARRY4 \\axaddr_incr_reg[8]_i_6__0 
+       (.CI(\\axaddr_incr_reg[4]_i_6__0_n_0 ),
+        .CO({\\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED [3],\\axaddr_incr_reg[8]_i_6__0_n_1 ,\\axaddr_incr_reg[8]_i_6__0_n_2 ,\\axaddr_incr_reg[8]_i_6__0_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(\\axaddr_incr_reg[11] ),
+        .S({\\axaddr_incr[8]_i_7__0_n_0 ,\\axaddr_incr[8]_i_8__0_n_0 ,\\axaddr_incr[8]_i_9__0_n_0 ,\\axaddr_incr[8]_i_10__0_n_0 }));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[0]_i_2__0 
+       (.I0(Q[3]),
+        .I1(Q[1]),
+        .I2(Q[35]),
+        .I3(Q[2]),
+        .I4(Q[36]),
+        .I5(Q[0]),
+        .O(\\axaddr_offset_r_reg[0] ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\axaddr_offset_r[1]_i_1__0 
+       (.I0(\\axaddr_offset_r_reg[1] ),
+        .O(\\axaddr_offset_r_reg[3] [0]));
+  LUT6 #(
+    .INIT(64\'h1FDF00001FDFFFFF)) 
+    \\axaddr_offset_r[1]_i_2 
+       (.I0(\\axaddr_offset_r[1]_i_3_n_0 ),
+        .I1(Q[35]),
+        .I2(Q[39]),
+        .I3(\\axaddr_offset_r[2]_i_3__0_n_0 ),
+        .I4(\\state_reg[1]_rep ),
+        .I5(\\axaddr_offset_r_reg[3]_0 [0]),
+        .O(\\axaddr_offset_r_reg[1] ));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[1]_i_3 
+       (.I0(Q[3]),
+        .I1(Q[36]),
+        .I2(Q[1]),
+        .O(\\axaddr_offset_r[1]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAC00FFFFAC000000)) 
+    \\axaddr_offset_r[2]_i_1__0 
+       (.I0(\\axaddr_offset_r[2]_i_2__0_n_0 ),
+        .I1(\\axaddr_offset_r[2]_i_3__0_n_0 ),
+        .I2(Q[35]),
+        .I3(Q[40]),
+        .I4(\\state_reg[1]_rep ),
+        .I5(\\axaddr_offset_r_reg[3]_0 [1]),
+        .O(\\axaddr_offset_r_reg[2] ));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[2]_i_2__0 
+       (.I0(Q[5]),
+        .I1(Q[36]),
+        .I2(Q[3]),
+        .O(\\axaddr_offset_r[2]_i_2__0_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[2]_i_3__0 
+       (.I0(Q[4]),
+        .I1(Q[36]),
+        .I2(Q[2]),
+        .O(\\axaddr_offset_r[2]_i_3__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFF8FF00000800)) 
+    \\axaddr_offset_r[3]_i_1__0 
+       (.I0(Q[41]),
+        .I1(\\axaddr_offset_r[3]_i_2__0_n_0 ),
+        .I2(\\state_reg[1]_rep_0 ),
+        .I3(s_ready_i_reg_0),
+        .I4(\\state_reg[0]_rep ),
+        .I5(\\axaddr_offset_r_reg[3]_0 [2]),
+        .O(\\axaddr_offset_r_reg[3] [1]));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[3]_i_2__0 
+       (.I0(Q[6]),
+        .I1(Q[4]),
+        .I2(Q[35]),
+        .I3(Q[5]),
+        .I4(Q[36]),
+        .I5(Q[3]),
+        .O(\\axaddr_offset_r[3]_i_2__0_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\axlen_cnt[3]_i_4 
+       (.I0(Q[41]),
+        .I1(\\state_reg[0]_rep ),
+        .I2(s_ready_i_reg_0),
+        .I3(\\state_reg[1]_rep_0 ),
+        .O(\\axlen_cnt_reg[3] ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\m_axi_araddr[11]_INST_0_i_1 
+       (.I0(\\m_payload_i_reg_n_0_[38] ),
+        .I1(sel_first_1),
+        .O(\\m_axi_araddr[10] ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[0]_i_1__0 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[0] ),
+        .O(\\m_payload_i[0]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair36"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1__0 
+       (.I0(s_axi_araddr[10]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(\\m_payload_i[10]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair35"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1__0 
+       (.I0(s_axi_araddr[11]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(\\m_payload_i[11]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair33"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1__0 
+       (.I0(s_axi_araddr[12]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(\\m_payload_i[12]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair35"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1__1 
+       (.I0(s_axi_araddr[13]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(\\m_payload_i[13]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair34"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1__0 
+       (.I0(s_axi_araddr[14]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(\\m_payload_i[14]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair34"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1__0 
+       (.I0(s_axi_araddr[15]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(\\m_payload_i[15]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair33"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1__0 
+       (.I0(s_axi_araddr[16]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(\\m_payload_i[16]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair32"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1__0 
+       (.I0(s_axi_araddr[17]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(\\m_payload_i[17]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1__0 
+       (.I0(s_axi_araddr[18]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(\\m_payload_i[18]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair32"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1__0 
+       (.I0(s_axi_araddr[19]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(\\m_payload_i[19]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair40"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[1]_i_1__0 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[1] ),
+        .O(\\m_payload_i[1]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair31"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1__0 
+       (.I0(s_axi_araddr[20]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(\\m_payload_i[20]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair31"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1__0 
+       (.I0(s_axi_araddr[21]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(\\m_payload_i[21]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1__0 
+       (.I0(s_axi_araddr[22]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(\\m_payload_i[22]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1__0 
+       (.I0(s_axi_araddr[23]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(\\m_payload_i[23]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1__0 
+       (.I0(s_axi_araddr[24]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(\\m_payload_i[24]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1__0 
+       (.I0(s_axi_araddr[25]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(\\m_payload_i[25]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1__0 
+       (.I0(s_axi_araddr[26]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(\\m_payload_i[26]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1__0 
+       (.I0(s_axi_araddr[27]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(\\m_payload_i[27]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1__0 
+       (.I0(s_axi_araddr[28]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(\\m_payload_i[28]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1__0 
+       (.I0(s_axi_araddr[29]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(\\m_payload_i[29]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair40"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[2]_i_1__0 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[2] ),
+        .O(\\m_payload_i[2]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1__0 
+       (.I0(s_axi_araddr[30]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(\\m_payload_i[30]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_2__0 
+       (.I0(s_axi_araddr[31]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(\\m_payload_i[31]_i_2__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1__0 
+       (.I0(s_axi_arprot[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(\\m_payload_i[32]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1__0 
+       (.I0(s_axi_arprot[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(\\m_payload_i[33]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_1__0 
+       (.I0(s_axi_arprot[2]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(\\m_payload_i[34]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[35]_i_1__0 
+       (.I0(s_axi_arsize[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[35] ),
+        .O(\\m_payload_i[35]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[36]_i_1__0 
+       (.I0(s_axi_arsize[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[36] ),
+        .O(\\m_payload_i[36]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[38]_i_1__0 
+       (.I0(s_axi_arburst[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[38] ),
+        .O(\\m_payload_i[38]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[39]_i_1__0 
+       (.I0(s_axi_arburst[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[39] ),
+        .O(\\m_payload_i[39]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair39"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1__0 
+       (.I0(s_axi_araddr[3]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(\\m_payload_i[3]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[44]_i_1__0 
+       (.I0(s_axi_arlen[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[44] ),
+        .O(\\m_payload_i[44]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[45]_i_1__0 
+       (.I0(s_axi_arlen[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[45] ),
+        .O(\\m_payload_i[45]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[46]_i_1__1 
+       (.I0(s_axi_arlen[2]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[46] ),
+        .O(\\m_payload_i[46]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[47]_i_1__0 
+       (.I0(s_axi_arlen[3]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[47] ),
+        .O(\\m_payload_i[47]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair39"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1__0 
+       (.I0(s_axi_araddr[4]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(\\m_payload_i[4]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[50]_i_1__0 
+       (.I0(s_axi_arid[0]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[50] ),
+        .O(\\m_payload_i[50]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[51]_i_1__0 
+       (.I0(s_axi_arid[1]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[51] ),
+        .O(\\m_payload_i[51]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[52]_i_1__0 
+       (.I0(s_axi_arid[2]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[52] ),
+        .O(\\m_payload_i[52]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[53]_i_1__0 
+       (.I0(s_axi_arid[3]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[53] ),
+        .O(\\m_payload_i[53]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[54]_i_1__0 
+       (.I0(s_axi_arid[4]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[54] ),
+        .O(\\m_payload_i[54]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[55]_i_1__0 
+       (.I0(s_axi_arid[5]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[55] ),
+        .O(\\m_payload_i[55]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[56]_i_1__0 
+       (.I0(s_axi_arid[6]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[56] ),
+        .O(\\m_payload_i[56]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[57]_i_1__0 
+       (.I0(s_axi_arid[7]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[57] ),
+        .O(\\m_payload_i[57]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[58]_i_1__0 
+       (.I0(s_axi_arid[8]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[58] ),
+        .O(\\m_payload_i[58]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[59]_i_1__0 
+       (.I0(s_axi_arid[9]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[59] ),
+        .O(\\m_payload_i[59]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair38"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1__0 
+       (.I0(s_axi_araddr[5]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(\\m_payload_i[5]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[60]_i_1__0 
+       (.I0(s_axi_arid[10]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[60] ),
+        .O(\\m_payload_i[60]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[61]_i_1__0 
+       (.I0(s_axi_arid[11]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[61] ),
+        .O(\\m_payload_i[61]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair38"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1__0 
+       (.I0(s_axi_araddr[6]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(\\m_payload_i[6]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair37"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1__0 
+       (.I0(s_axi_araddr[7]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(\\m_payload_i[7]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair36"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1__0 
+       (.I0(s_axi_araddr[8]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(\\m_payload_i[8]_i_1__0_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair37"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1__0 
+       (.I0(s_axi_araddr[9]),
+        .I1(s_axi_arready),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(\\m_payload_i[9]_i_1__0_n_0 ));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[0]_i_1__0_n_0 ),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[10]_i_1__0_n_0 ),
+        .Q(Q[10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[11]_i_1__0_n_0 ),
+        .Q(Q[11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[12]_i_1__0_n_0 ),
+        .Q(Q[12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[13]_i_1__1_n_0 ),
+        .Q(Q[13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[14]_i_1__0_n_0 ),
+        .Q(Q[14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[15]_i_1__0_n_0 ),
+        .Q(Q[15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[16]_i_1__0_n_0 ),
+        .Q(Q[16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[17]_i_1__0_n_0 ),
+        .Q(Q[17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[18]_i_1__0_n_0 ),
+        .Q(Q[18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[19]_i_1__0_n_0 ),
+        .Q(Q[19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[1]_i_1__0_n_0 ),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[20]_i_1__0_n_0 ),
+        .Q(Q[20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[21]_i_1__0_n_0 ),
+        .Q(Q[21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[22]_i_1__0_n_0 ),
+        .Q(Q[22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[23]_i_1__0_n_0 ),
+        .Q(Q[23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[24]_i_1__0_n_0 ),
+        .Q(Q[24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[25]_i_1__0_n_0 ),
+        .Q(Q[25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[26]_i_1__0_n_0 ),
+        .Q(Q[26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[27]_i_1__0_n_0 ),
+        .Q(Q[27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[28]_i_1__0_n_0 ),
+        .Q(Q[28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[29]_i_1__0_n_0 ),
+        .Q(Q[29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[2]_i_1__0_n_0 ),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[30]_i_1__0_n_0 ),
+        .Q(Q[30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[31]_i_2__0_n_0 ),
+        .Q(Q[31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[32]_i_1__0_n_0 ),
+        .Q(Q[32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[33]_i_1__0_n_0 ),
+        .Q(Q[33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[34]_i_1__0_n_0 ),
+        .Q(Q[34]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[35] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[35]_i_1__0_n_0 ),
+        .Q(Q[35]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[36] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[36]_i_1__0_n_0 ),
+        .Q(Q[36]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[38] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[38]_i_1__0_n_0 ),
+        .Q(\\m_payload_i_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[39] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[39]_i_1__0_n_0 ),
+        .Q(Q[37]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[3]_i_1__0_n_0 ),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[44] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[44]_i_1__0_n_0 ),
+        .Q(Q[38]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[45] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[45]_i_1__0_n_0 ),
+        .Q(Q[39]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[46] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[46]_i_1__1_n_0 ),
+        .Q(Q[40]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[47] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[47]_i_1__0_n_0 ),
+        .Q(Q[41]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[4]_i_1__0_n_0 ),
+        .Q(Q[4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[50] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[50]_i_1__0_n_0 ),
+        .Q(Q[42]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[51] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[51]_i_1__0_n_0 ),
+        .Q(Q[43]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[52] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[52]_i_1__0_n_0 ),
+        .Q(Q[44]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[53] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[53]_i_1__0_n_0 ),
+        .Q(Q[45]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[54] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[54]_i_1__0_n_0 ),
+        .Q(Q[46]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[55] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[55]_i_1__0_n_0 ),
+        .Q(Q[47]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[56] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[56]_i_1__0_n_0 ),
+        .Q(Q[48]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[57] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[57]_i_1__0_n_0 ),
+        .Q(Q[49]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[58] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[58]_i_1__0_n_0 ),
+        .Q(Q[50]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[59] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[59]_i_1__0_n_0 ),
+        .Q(Q[51]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[5]_i_1__0_n_0 ),
+        .Q(Q[5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[60] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[60]_i_1__0_n_0 ),
+        .Q(Q[52]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[61] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[61]_i_1__0_n_0 ),
+        .Q(Q[53]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[6]_i_1__0_n_0 ),
+        .Q(Q[6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[7]_i_1__0_n_0 ),
+        .Q(Q[7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[8]_i_1__0_n_0 ),
+        .Q(Q[8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(\\state_reg[1]_rep_1 ),
+        .D(\\m_payload_i[9]_i_1__0_n_0 ),
+        .Q(Q[9]),
+        .R(1\'b0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i0),
+        .Q(s_ready_i_reg_0),
+        .R(m_valid_i_reg_0));
+  LUT5 #(
+    .INIT(32\'hAAAAAAA8)) 
+    next_pending_r_i_3__0
+       (.I0(\\state_reg[1]_rep ),
+        .I1(Q[38]),
+        .I2(Q[41]),
+        .I3(Q[39]),
+        .I4(Q[40]),
+        .O(next_pending_r_reg));
+  LUT5 #(
+    .INIT(32\'hF444FFFF)) 
+    s_ready_i_i_1__0
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_arready),
+        .I2(\\state_reg[1]_rep_0 ),
+        .I3(\\state_reg[0]_rep ),
+        .I4(s_ready_i_reg_0),
+        .O(s_ready_i0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i0),
+        .Q(s_axi_arready),
+        .R(\\aresetn_d_reg[0] ));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[10]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[11]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[12]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[13]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[14]),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[15]),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[16]),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[17]),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[18]),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[19]),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[20]),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[21]),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[22]),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[23]),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[24]),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[25]),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[26]),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[27]),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[28]),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[29]),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[30]),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[31]),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arprot[0]),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arprot[1]),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arprot[2]),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[35] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arsize[0]),
+        .Q(\\skid_buffer_reg_n_0_[35] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[36] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arsize[1]),
+        .Q(\\skid_buffer_reg_n_0_[36] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[38] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arburst[0]),
+        .Q(\\skid_buffer_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[39] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arburst[1]),
+        .Q(\\skid_buffer_reg_n_0_[39] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[3]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[44] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arlen[0]),
+        .Q(\\skid_buffer_reg_n_0_[44] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[45] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arlen[1]),
+        .Q(\\skid_buffer_reg_n_0_[45] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[46] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arlen[2]),
+        .Q(\\skid_buffer_reg_n_0_[46] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[47] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arlen[3]),
+        .Q(\\skid_buffer_reg_n_0_[47] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[4]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[50] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[0]),
+        .Q(\\skid_buffer_reg_n_0_[50] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[51] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[1]),
+        .Q(\\skid_buffer_reg_n_0_[51] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[52] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[2]),
+        .Q(\\skid_buffer_reg_n_0_[52] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[53] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[3]),
+        .Q(\\skid_buffer_reg_n_0_[53] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[54] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[4]),
+        .Q(\\skid_buffer_reg_n_0_[54] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[55] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[5]),
+        .Q(\\skid_buffer_reg_n_0_[55] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[56] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[6]),
+        .Q(\\skid_buffer_reg_n_0_[56] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[57] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[7]),
+        .Q(\\skid_buffer_reg_n_0_[57] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[58] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[8]),
+        .Q(\\skid_buffer_reg_n_0_[58] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[59] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[9]),
+        .Q(\\skid_buffer_reg_n_0_[59] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[5]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[60] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[10]),
+        .Q(\\skid_buffer_reg_n_0_[60] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[61] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_arid[11]),
+        .Q(\\skid_buffer_reg_n_0_[61] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[6]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[7]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[8]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(s_axi_arready),
+        .D(s_axi_araddr[9]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hAA8A)) 
+    \\wrap_boundary_axaddr_r[0]_i_1__0 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[38]),
+        .I3(Q[35]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [0]));
+  LUT5 #(
+    .INIT(32\'h8A888AAA)) 
+    \\wrap_boundary_axaddr_r[1]_i_1__0 
+       (.I0(Q[1]),
+        .I1(Q[36]),
+        .I2(Q[38]),
+        .I3(Q[35]),
+        .I4(Q[39]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [1]));
+  LUT6 #(
+    .INIT(64\'h8888082AAAAA082A)) 
+    \\wrap_boundary_axaddr_r[2]_i_1 
+       (.I0(Q[2]),
+        .I1(Q[35]),
+        .I2(Q[39]),
+        .I3(Q[40]),
+        .I4(Q[36]),
+        .I5(Q[38]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [2]));
+  LUT6 #(
+    .INIT(64\'h020202A2A2A202A2)) 
+    \\wrap_boundary_axaddr_r[3]_i_1__0 
+       (.I0(Q[3]),
+        .I1(\\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
+        .I2(Q[36]),
+        .I3(Q[39]),
+        .I4(Q[35]),
+        .I5(Q[38]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [3]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\wrap_boundary_axaddr_r[3]_i_2__0 
+       (.I0(Q[40]),
+        .I1(Q[35]),
+        .I2(Q[41]),
+        .O(\\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
+  LUT6 #(
+    .INIT(64\'h002AA02A0A2AAA2A)) 
+    \\wrap_boundary_axaddr_r[4]_i_1 
+       (.I0(Q[4]),
+        .I1(Q[41]),
+        .I2(Q[35]),
+        .I3(Q[36]),
+        .I4(Q[39]),
+        .I5(Q[40]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [4]));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT5 #(
+    .INIT(32\'h2A222AAA)) 
+    \\wrap_boundary_axaddr_r[5]_i_1__0 
+       (.I0(Q[5]),
+        .I1(Q[36]),
+        .I2(Q[40]),
+        .I3(Q[35]),
+        .I4(Q[41]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [5]));
+  LUT4 #(
+    .INIT(16\'h2AAA)) 
+    \\wrap_boundary_axaddr_r[6]_i_1__0 
+       (.I0(Q[6]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .I3(Q[41]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [6]));
+  LUT6 #(
+    .INIT(64\'hA656AAAAAAAAAAAA)) 
+    \\wrap_cnt_r[2]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[2] [1]),
+        .I1(\\wrap_second_len_r_reg[2]_0 [0]),
+        .I2(\\state_reg[1]_rep ),
+        .I3(axaddr_offset_0),
+        .I4(\\wrap_cnt_r_reg[2]_0 ),
+        .I5(\\wrap_second_len_r_reg[2] [0]),
+        .O(\\wrap_cnt_r_reg[2] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFBAFFFFFFFF)) 
+    \\wrap_second_len_r[0]_i_2__0 
+       (.I0(\\wrap_second_len_r_reg[3] ),
+        .I1(\\state_reg[1]_rep ),
+        .I2(\\axaddr_offset_r_reg[3]_0 [2]),
+        .I3(\\axaddr_offset_r_reg[2] ),
+        .I4(axaddr_offset_0),
+        .I5(\\axaddr_offset_r_reg[1] ),
+        .O(\\wrap_cnt_r_reg[2]_0 ));
+  LUT6 #(
+    .INIT(64\'h0EF0FFFF0EF00000)) 
+    \\wrap_second_len_r[1]_i_1__0 
+       (.I0(\\axaddr_offset_r_reg[2] ),
+        .I1(\\axaddr_offset_r_reg[3] [1]),
+        .I2(axaddr_offset_0),
+        .I3(\\axaddr_offset_r_reg[1] ),
+        .I4(\\state_reg[1]_rep ),
+        .I5(\\wrap_second_len_r_reg[2]_0 [1]),
+        .O(\\wrap_second_len_r_reg[2] [0]));
+  LUT6 #(
+    .INIT(64\'hD2D0FFFFD2D00000)) 
+    \\wrap_second_len_r[2]_i_1__0 
+       (.I0(\\axaddr_offset_r_reg[1] ),
+        .I1(axaddr_offset_0),
+        .I2(\\axaddr_offset_r_reg[2] ),
+        .I3(\\axaddr_offset_r_reg[3] [1]),
+        .I4(\\state_reg[1]_rep ),
+        .I5(\\wrap_second_len_r_reg[2]_0 [2]),
+        .O(\\wrap_second_len_r_reg[2] [1]));
+  LUT6 #(
+    .INIT(64\'h00000000EEE222E2)) 
+    \\wrap_second_len_r[3]_i_2__0 
+       (.I0(\\axaddr_offset_r[2]_i_2__0_n_0 ),
+        .I1(Q[35]),
+        .I2(Q[4]),
+        .I3(Q[36]),
+        .I4(Q[6]),
+        .I5(\\axlen_cnt_reg[3] ),
+        .O(\\wrap_second_len_r_reg[3] ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_register_slice_v2_1_11_axic_register_slice"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice_0
+   (s_axi_awready,
+    s_ready_i_reg_0,
+    m_valid_i_reg_0,
+    D,
+    \\wrap_second_len_r_reg[1] ,
+    Q,
+    \\axaddr_incr_reg[11] ,
+    CO,
+    O,
+    wrap_second_len,
+    \\axaddr_offset_r_reg[1] ,
+    \\axaddr_offset_r_reg[3] ,
+    axaddr_offset,
+    \\axlen_cnt_reg[3] ,
+    next_pending_r_reg,
+    \\wrap_boundary_axaddr_r_reg[6] ,
+    \\m_axi_awaddr[10] ,
+    \\aresetn_d_reg[1]_inv ,
+    aclk,
+    \\aresetn_d_reg[1]_inv_0 ,
+    aresetn,
+    S,
+    \\state_reg[1] ,
+    \\wrap_second_len_r_reg[3] ,
+    \\state_reg[1]_0 ,
+    \\axaddr_offset_r_reg[3]_0 ,
+    s_axi_awvalid,
+    b_push,
+    sel_first,
+    s_axi_awid,
+    s_axi_awlen,
+    s_axi_awburst,
+    s_axi_awsize,
+    s_axi_awprot,
+    s_axi_awaddr,
+    axaddr_incr_reg,
+    E);
+  output s_axi_awready;
+  output s_ready_i_reg_0;
+  output m_valid_i_reg_0;
+  output [3:0]D;
+  output \\wrap_second_len_r_reg[1] ;
+  output [53:0]Q;
+  output [7:0]\\axaddr_incr_reg[11] ;
+  output [0:0]CO;
+  output [3:0]O;
+  output [2:0]wrap_second_len;
+  output \\axaddr_offset_r_reg[1] ;
+  output \\axaddr_offset_r_reg[3] ;
+  output [1:0]axaddr_offset;
+  output \\axlen_cnt_reg[3] ;
+  output next_pending_r_reg;
+  output [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  output \\m_axi_awaddr[10] ;
+  output \\aresetn_d_reg[1]_inv ;
+  input aclk;
+  input \\aresetn_d_reg[1]_inv_0 ;
+  input aresetn;
+  input [3:0]S;
+  input \\state_reg[1] ;
+  input [3:0]\\wrap_second_len_r_reg[3] ;
+  input [1:0]\\state_reg[1]_0 ;
+  input [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  input s_axi_awvalid;
+  input b_push;
+  input sel_first;
+  input [11:0]s_axi_awid;
+  input [3:0]s_axi_awlen;
+  input [1:0]s_axi_awburst;
+  input [1:0]s_axi_awsize;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_awaddr;
+  input [3:0]axaddr_incr_reg;
+  input [0:0]E;
+
+  wire [3:0]C;
+  wire [0:0]CO;
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [3:0]O;
+  wire [53:0]Q;
+  wire [3:0]S;
+  wire aclk;
+  wire aresetn;
+  wire \\aresetn_d_reg[1]_inv ;
+  wire \\aresetn_d_reg[1]_inv_0 ;
+  wire \\aresetn_d_reg_n_0_[0] ;
+  wire \\axaddr_incr[0]_i_10_n_0 ;
+  wire \\axaddr_incr[0]_i_12_n_0 ;
+  wire \\axaddr_incr[0]_i_13_n_0 ;
+  wire \\axaddr_incr[0]_i_14_n_0 ;
+  wire \\axaddr_incr[0]_i_3_n_0 ;
+  wire \\axaddr_incr[0]_i_4_n_0 ;
+  wire \\axaddr_incr[0]_i_5_n_0 ;
+  wire \\axaddr_incr[0]_i_6_n_0 ;
+  wire \\axaddr_incr[0]_i_7_n_0 ;
+  wire \\axaddr_incr[0]_i_8_n_0 ;
+  wire \\axaddr_incr[0]_i_9_n_0 ;
+  wire \\axaddr_incr[4]_i_10_n_0 ;
+  wire \\axaddr_incr[4]_i_7_n_0 ;
+  wire \\axaddr_incr[4]_i_8_n_0 ;
+  wire \\axaddr_incr[4]_i_9_n_0 ;
+  wire \\axaddr_incr[8]_i_10_n_0 ;
+  wire \\axaddr_incr[8]_i_7_n_0 ;
+  wire \\axaddr_incr[8]_i_8_n_0 ;
+  wire \\axaddr_incr[8]_i_9_n_0 ;
+  wire [3:0]axaddr_incr_reg;
+  wire \\axaddr_incr_reg[0]_i_11_n_0 ;
+  wire \\axaddr_incr_reg[0]_i_11_n_1 ;
+  wire \\axaddr_incr_reg[0]_i_11_n_2 ;
+  wire \\axaddr_incr_reg[0]_i_11_n_3 ;
+  wire \\axaddr_incr_reg[0]_i_2_n_1 ;
+  wire \\axaddr_incr_reg[0]_i_2_n_2 ;
+  wire \\axaddr_incr_reg[0]_i_2_n_3 ;
+  wire [7:0]\\axaddr_incr_reg[11] ;
+  wire \\axaddr_incr_reg[4]_i_6_n_0 ;
+  wire \\axaddr_incr_reg[4]_i_6_n_1 ;
+  wire \\axaddr_incr_reg[4]_i_6_n_2 ;
+  wire \\axaddr_incr_reg[4]_i_6_n_3 ;
+  wire \\axaddr_incr_reg[8]_i_6_n_1 ;
+  wire \\axaddr_incr_reg[8]_i_6_n_2 ;
+  wire \\axaddr_incr_reg[8]_i_6_n_3 ;
+  wire [1:0]axaddr_offset;
+  wire \\axaddr_offset_r[0]_i_2_n_0 ;
+  wire \\axaddr_offset_r[0]_i_3_n_0 ;
+  wire \\axaddr_offset_r[1]_i_2__0_n_0 ;
+  wire \\axaddr_offset_r[2]_i_2_n_0 ;
+  wire \\axaddr_offset_r[2]_i_3_n_0 ;
+  wire \\axaddr_offset_r[2]_i_4_n_0 ;
+  wire \\axaddr_offset_r[3]_i_2_n_0 ;
+  wire \\axaddr_offset_r_reg[1] ;
+  wire \\axaddr_offset_r_reg[3] ;
+  wire [3:0]\\axaddr_offset_r_reg[3]_0 ;
+  wire \\axlen_cnt_reg[3] ;
+  wire b_push;
+  wire \\m_axi_awaddr[10] ;
+  wire \\m_payload_i_reg_n_0_[38] ;
+  wire m_valid_i0;
+  wire m_valid_i_reg_0;
+  wire next_pending_r_reg;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [2:0]s_axi_awprot;
+  wire s_axi_awready;
+  wire [1:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire s_ready_i0;
+  wire s_ready_i_reg_0;
+  wire sel_first;
+  wire [61:0]skid_buffer;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[35] ;
+  wire \\skid_buffer_reg_n_0_[36] ;
+  wire \\skid_buffer_reg_n_0_[38] ;
+  wire \\skid_buffer_reg_n_0_[39] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[44] ;
+  wire \\skid_buffer_reg_n_0_[45] ;
+  wire \\skid_buffer_reg_n_0_[46] ;
+  wire \\skid_buffer_reg_n_0_[47] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[50] ;
+  wire \\skid_buffer_reg_n_0_[51] ;
+  wire \\skid_buffer_reg_n_0_[52] ;
+  wire \\skid_buffer_reg_n_0_[53] ;
+  wire \\skid_buffer_reg_n_0_[54] ;
+  wire \\skid_buffer_reg_n_0_[55] ;
+  wire \\skid_buffer_reg_n_0_[56] ;
+  wire \\skid_buffer_reg_n_0_[57] ;
+  wire \\skid_buffer_reg_n_0_[58] ;
+  wire \\skid_buffer_reg_n_0_[59] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[60] ;
+  wire \\skid_buffer_reg_n_0_[61] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire \\state_reg[1] ;
+  wire [1:0]\\state_reg[1]_0 ;
+  wire \\wrap_boundary_axaddr_r[3]_i_2_n_0 ;
+  wire [6:0]\\wrap_boundary_axaddr_r_reg[6] ;
+  wire \\wrap_cnt_r[3]_i_2_n_0 ;
+  wire \\wrap_cnt_r[3]_i_3_n_0 ;
+  wire [2:0]wrap_second_len;
+  wire \\wrap_second_len_r[0]_i_2_n_0 ;
+  wire \\wrap_second_len_r[0]_i_3_n_0 ;
+  wire \\wrap_second_len_r[0]_i_4_n_0 ;
+  wire \\wrap_second_len_r[0]_i_5_n_0 ;
+  wire \\wrap_second_len_r[3]_i_2_n_0 ;
+  wire \\wrap_second_len_r_reg[1] ;
+  wire [3:0]\\wrap_second_len_r_reg[3] ;
+  wire [3:3]\\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED ;
+
+  LUT2 #(
+    .INIT(4\'h7)) 
+    \\aresetn_d[1]_inv_i_1 
+       (.I0(\\aresetn_d_reg_n_0_[0] ),
+        .I1(aresetn),
+        .O(\\aresetn_d_reg[1]_inv ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(aresetn),
+        .Q(\\aresetn_d_reg_n_0_[0] ),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'hFFE100E1)) 
+    \\axaddr_incr[0]_i_10 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(axaddr_incr_reg[0]),
+        .I3(sel_first),
+        .I4(C[0]),
+        .O(\\axaddr_incr[0]_i_10_n_0 ));
+  LUT3 #(
+    .INIT(8\'h2A)) 
+    \\axaddr_incr[0]_i_12 
+       (.I0(Q[2]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .O(\\axaddr_incr[0]_i_12_n_0 ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\axaddr_incr[0]_i_13 
+       (.I0(Q[1]),
+        .I1(Q[36]),
+        .O(\\axaddr_incr[0]_i_13_n_0 ));
+  LUT3 #(
+    .INIT(8\'h02)) 
+    \\axaddr_incr[0]_i_14 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .O(\\axaddr_incr[0]_i_14_n_0 ));
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\axaddr_incr[0]_i_3 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first),
+        .O(\\axaddr_incr[0]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\axaddr_incr[0]_i_4 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(sel_first),
+        .O(\\axaddr_incr[0]_i_4_n_0 ));
+  LUT3 #(
+    .INIT(8\'h04)) 
+    \\axaddr_incr[0]_i_5 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first),
+        .O(\\axaddr_incr[0]_i_5_n_0 ));
+  LUT3 #(
+    .INIT(8\'h01)) 
+    \\axaddr_incr[0]_i_6 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(sel_first),
+        .O(\\axaddr_incr[0]_i_6_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFF780078)) 
+    \\axaddr_incr[0]_i_7 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(axaddr_incr_reg[3]),
+        .I3(sel_first),
+        .I4(C[3]),
+        .O(\\axaddr_incr[0]_i_7_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFD200D2)) 
+    \\axaddr_incr[0]_i_8 
+       (.I0(Q[36]),
+        .I1(Q[35]),
+        .I2(axaddr_incr_reg[2]),
+        .I3(sel_first),
+        .I4(C[2]),
+        .O(\\axaddr_incr[0]_i_8_n_0 ));
+  LUT5 #(
+    .INIT(32\'hFFD200D2)) 
+    \\axaddr_incr[0]_i_9 
+       (.I0(Q[35]),
+        .I1(Q[36]),
+        .I2(axaddr_incr_reg[1]),
+        .I3(sel_first),
+        .I4(C[1]),
+        .O(\\axaddr_incr[0]_i_9_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_10 
+       (.I0(Q[4]),
+        .O(\\axaddr_incr[4]_i_10_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_7 
+       (.I0(Q[7]),
+        .O(\\axaddr_incr[4]_i_7_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_8 
+       (.I0(Q[6]),
+        .O(\\axaddr_incr[4]_i_8_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[4]_i_9 
+       (.I0(Q[5]),
+        .O(\\axaddr_incr[4]_i_9_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_10 
+       (.I0(Q[8]),
+        .O(\\axaddr_incr[8]_i_10_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_7 
+       (.I0(Q[11]),
+        .O(\\axaddr_incr[8]_i_7_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_8 
+       (.I0(Q[10]),
+        .O(\\axaddr_incr[8]_i_8_n_0 ));
+  LUT1 #(
+    .INIT(2\'h2)) 
+    \\axaddr_incr[8]_i_9 
+       (.I0(Q[9]),
+        .O(\\axaddr_incr[8]_i_9_n_0 ));
+  CARRY4 \\axaddr_incr_reg[0]_i_11 
+       (.CI(1\'b0),
+        .CO({\\axaddr_incr_reg[0]_i_11_n_0 ,\\axaddr_incr_reg[0]_i_11_n_1 ,\\axaddr_incr_reg[0]_i_11_n_2 ,\\axaddr_incr_reg[0]_i_11_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({Q[3],\\axaddr_incr[0]_i_12_n_0 ,\\axaddr_incr[0]_i_13_n_0 ,\\axaddr_incr[0]_i_14_n_0 }),
+        .O(C),
+        .S(S));
+  CARRY4 \\axaddr_incr_reg[0]_i_2 
+       (.CI(1\'b0),
+        .CO({CO,\\axaddr_incr_reg[0]_i_2_n_1 ,\\axaddr_incr_reg[0]_i_2_n_2 ,\\axaddr_incr_reg[0]_i_2_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({\\axaddr_incr[0]_i_3_n_0 ,\\axaddr_incr[0]_i_4_n_0 ,\\axaddr_incr[0]_i_5_n_0 ,\\axaddr_incr[0]_i_6_n_0 }),
+        .O(O),
+        .S({\\axaddr_incr[0]_i_7_n_0 ,\\axaddr_incr[0]_i_8_n_0 ,\\axaddr_incr[0]_i_9_n_0 ,\\axaddr_incr[0]_i_10_n_0 }));
+  CARRY4 \\axaddr_incr_reg[4]_i_6 
+       (.CI(\\axaddr_incr_reg[0]_i_11_n_0 ),
+        .CO({\\axaddr_incr_reg[4]_i_6_n_0 ,\\axaddr_incr_reg[4]_i_6_n_1 ,\\axaddr_incr_reg[4]_i_6_n_2 ,\\axaddr_incr_reg[4]_i_6_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(\\axaddr_incr_reg[11] [3:0]),
+        .S({\\axaddr_incr[4]_i_7_n_0 ,\\axaddr_incr[4]_i_8_n_0 ,\\axaddr_incr[4]_i_9_n_0 ,\\axaddr_incr[4]_i_10_n_0 }));
+  CARRY4 \\axaddr_incr_reg[8]_i_6 
+       (.CI(\\axaddr_incr_reg[4]_i_6_n_0 ),
+        .CO({\\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED [3],\\axaddr_incr_reg[8]_i_6_n_1 ,\\axaddr_incr_reg[8]_i_6_n_2 ,\\axaddr_incr_reg[8]_i_6_n_3 }),
+        .CYINIT(1\'b0),
+        .DI({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .O(\\axaddr_incr_reg[11] [7:4]),
+        .S({\\axaddr_incr[8]_i_7_n_0 ,\\axaddr_incr[8]_i_8_n_0 ,\\axaddr_incr[8]_i_9_n_0 ,\\axaddr_incr[8]_i_10_n_0 }));
+  (* SOFT_HLUTNM = ""soft_lutpair41"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\axaddr_offset_r[0]_i_1 
+       (.I0(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .O(axaddr_offset[0]));
+  LUT6 #(
+    .INIT(64\'h00000700FFFFF7FF)) 
+    \\axaddr_offset_r[0]_i_2 
+       (.I0(Q[38]),
+        .I1(\\axaddr_offset_r[0]_i_3_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\axaddr_offset_r_reg[3]_0 [0]),
+        .O(\\axaddr_offset_r[0]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[0]_i_3 
+       (.I0(Q[3]),
+        .I1(Q[1]),
+        .I2(Q[35]),
+        .I3(Q[2]),
+        .I4(Q[36]),
+        .I5(Q[0]),
+        .O(\\axaddr_offset_r[0]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFF8FF00000800)) 
+    \\axaddr_offset_r[1]_i_1 
+       (.I0(Q[39]),
+        .I1(\\axaddr_offset_r[1]_i_2__0_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\axaddr_offset_r_reg[3]_0 [1]),
+        .O(\\axaddr_offset_r_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[1]_i_2__0 
+       (.I0(Q[4]),
+        .I1(Q[2]),
+        .I2(Q[35]),
+        .I3(Q[3]),
+        .I4(Q[36]),
+        .I5(Q[1]),
+        .O(\\axaddr_offset_r[1]_i_2__0_n_0 ));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\axaddr_offset_r[2]_i_1 
+       (.I0(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .O(axaddr_offset[1]));
+  LUT6 #(
+    .INIT(64\'h03FFF3FF55555555)) 
+    \\axaddr_offset_r[2]_i_2 
+       (.I0(\\axaddr_offset_r_reg[3]_0 [2]),
+        .I1(\\axaddr_offset_r[2]_i_3_n_0 ),
+        .I2(Q[35]),
+        .I3(Q[40]),
+        .I4(\\axaddr_offset_r[2]_i_4_n_0 ),
+        .I5(\\state_reg[1] ),
+        .O(\\axaddr_offset_r[2]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair45"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[2]_i_3 
+       (.I0(Q[4]),
+        .I1(Q[36]),
+        .I2(Q[2]),
+        .O(\\axaddr_offset_r[2]_i_3_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair45"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\axaddr_offset_r[2]_i_4 
+       (.I0(Q[5]),
+        .I1(Q[36]),
+        .I2(Q[3]),
+        .O(\\axaddr_offset_r[2]_i_4_n_0 ));
+  LUT6 #(
+    .INIT(64\'hFFFFF8FF00000800)) 
+    \\axaddr_offset_r[3]_i_1 
+       (.I0(Q[41]),
+        .I1(\\axaddr_offset_r[3]_i_2_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\axaddr_offset_r_reg[3]_0 [3]),
+        .O(\\axaddr_offset_r_reg[3] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\axaddr_offset_r[3]_i_2 
+       (.I0(Q[6]),
+        .I1(Q[4]),
+        .I2(Q[35]),
+        .I3(Q[5]),
+        .I4(Q[36]),
+        .I5(Q[3]),
+        .O(\\axaddr_offset_r[3]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair44"" *) 
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\axlen_cnt[3]_i_3 
+       (.I0(Q[41]),
+        .I1(\\state_reg[1]_0 [0]),
+        .I2(m_valid_i_reg_0),
+        .I3(\\state_reg[1]_0 [1]),
+        .O(\\axlen_cnt_reg[3] ));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\m_axi_awaddr[11]_INST_0_i_1 
+       (.I0(\\m_payload_i_reg_n_0_[38] ),
+        .I1(sel_first),
+        .O(\\m_axi_awaddr[10] ));
+  (* SOFT_HLUTNM = ""soft_lutpair47"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[0]_i_1 
+       (.I0(s_axi_awaddr[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[0] ),
+        .O(skid_buffer[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair69"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1 
+       (.I0(s_axi_awaddr[10]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(skid_buffer[10]));
+  (* SOFT_HLUTNM = ""soft_lutpair69"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1 
+       (.I0(s_axi_awaddr[11]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(skid_buffer[11]));
+  (* SOFT_HLUTNM = ""soft_lutpair68"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1 
+       (.I0(s_axi_awaddr[12]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(skid_buffer[12]));
+  (* SOFT_HLUTNM = ""soft_lutpair68"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1__0 
+       (.I0(s_axi_awaddr[13]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(skid_buffer[13]));
+  (* SOFT_HLUTNM = ""soft_lutpair67"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1 
+       (.I0(s_axi_awaddr[14]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(skid_buffer[14]));
+  (* SOFT_HLUTNM = ""soft_lutpair67"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1 
+       (.I0(s_axi_awaddr[15]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(skid_buffer[15]));
+  (* SOFT_HLUTNM = ""soft_lutpair66"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1 
+       (.I0(s_axi_awaddr[16]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(skid_buffer[16]));
+  (* SOFT_HLUTNM = ""soft_lutpair66"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1 
+       (.I0(s_axi_awaddr[17]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(skid_buffer[17]));
+  (* SOFT_HLUTNM = ""soft_lutpair65"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1 
+       (.I0(s_axi_awaddr[18]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(skid_buffer[18]));
+  (* SOFT_HLUTNM = ""soft_lutpair65"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1 
+       (.I0(s_axi_awaddr[19]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(skid_buffer[19]));
+  (* SOFT_HLUTNM = ""soft_lutpair46"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[1]_i_1 
+       (.I0(s_axi_awaddr[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[1] ),
+        .O(skid_buffer[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair64"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1 
+       (.I0(s_axi_awaddr[20]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(skid_buffer[20]));
+  (* SOFT_HLUTNM = ""soft_lutpair64"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1 
+       (.I0(s_axi_awaddr[21]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(skid_buffer[21]));
+  (* SOFT_HLUTNM = ""soft_lutpair63"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1 
+       (.I0(s_axi_awaddr[22]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(skid_buffer[22]));
+  (* SOFT_HLUTNM = ""soft_lutpair63"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1 
+       (.I0(s_axi_awaddr[23]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(skid_buffer[23]));
+  (* SOFT_HLUTNM = ""soft_lutpair62"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1 
+       (.I0(s_axi_awaddr[24]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(skid_buffer[24]));
+  (* SOFT_HLUTNM = ""soft_lutpair62"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1 
+       (.I0(s_axi_awaddr[25]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(skid_buffer[25]));
+  (* SOFT_HLUTNM = ""soft_lutpair61"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1 
+       (.I0(s_axi_awaddr[26]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(skid_buffer[26]));
+  (* SOFT_HLUTNM = ""soft_lutpair61"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1 
+       (.I0(s_axi_awaddr[27]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(skid_buffer[27]));
+  (* SOFT_HLUTNM = ""soft_lutpair60"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1 
+       (.I0(s_axi_awaddr[28]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(skid_buffer[28]));
+  (* SOFT_HLUTNM = ""soft_lutpair60"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1 
+       (.I0(s_axi_awaddr[29]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(skid_buffer[29]));
+  (* SOFT_HLUTNM = ""soft_lutpair52"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[2]_i_1 
+       (.I0(s_axi_awaddr[2]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[2] ),
+        .O(skid_buffer[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair59"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1 
+       (.I0(s_axi_awaddr[30]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(skid_buffer[30]));
+  (* SOFT_HLUTNM = ""soft_lutpair59"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_2 
+       (.I0(s_axi_awaddr[31]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(skid_buffer[31]));
+  (* SOFT_HLUTNM = ""soft_lutpair58"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1 
+       (.I0(s_axi_awprot[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(skid_buffer[32]));
+  (* SOFT_HLUTNM = ""soft_lutpair58"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1 
+       (.I0(s_axi_awprot[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(skid_buffer[33]));
+  (* SOFT_HLUTNM = ""soft_lutpair57"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_1 
+       (.I0(s_axi_awprot[2]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(skid_buffer[34]));
+  (* SOFT_HLUTNM = ""soft_lutpair57"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[35]_i_1 
+       (.I0(s_axi_awsize[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[35] ),
+        .O(skid_buffer[35]));
+  (* SOFT_HLUTNM = ""soft_lutpair56"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[36]_i_1 
+       (.I0(s_axi_awsize[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[36] ),
+        .O(skid_buffer[36]));
+  (* SOFT_HLUTNM = ""soft_lutpair56"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[38]_i_1 
+       (.I0(s_axi_awburst[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[38] ),
+        .O(skid_buffer[38]));
+  (* SOFT_HLUTNM = ""soft_lutpair55"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[39]_i_1 
+       (.I0(s_axi_awburst[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[39] ),
+        .O(skid_buffer[39]));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1 
+       (.I0(s_axi_awaddr[3]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(skid_buffer[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair55"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[44]_i_1 
+       (.I0(s_axi_awlen[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[44] ),
+        .O(skid_buffer[44]));
+  (* SOFT_HLUTNM = ""soft_lutpair54"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[45]_i_1 
+       (.I0(s_axi_awlen[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[45] ),
+        .O(skid_buffer[45]));
+  (* SOFT_HLUTNM = ""soft_lutpair54"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[46]_i_1__0 
+       (.I0(s_axi_awlen[2]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[46] ),
+        .O(skid_buffer[46]));
+  (* SOFT_HLUTNM = ""soft_lutpair53"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[47]_i_1 
+       (.I0(s_axi_awlen[3]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[47] ),
+        .O(skid_buffer[47]));
+  (* SOFT_HLUTNM = ""soft_lutpair72"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1 
+       (.I0(s_axi_awaddr[4]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(skid_buffer[4]));
+  (* SOFT_HLUTNM = ""soft_lutpair53"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[50]_i_1 
+       (.I0(s_axi_awid[0]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[50] ),
+        .O(skid_buffer[50]));
+  (* SOFT_HLUTNM = ""soft_lutpair52"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[51]_i_1 
+       (.I0(s_axi_awid[1]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[51] ),
+        .O(skid_buffer[51]));
+  (* SOFT_HLUTNM = ""soft_lutpair48"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[52]_i_1 
+       (.I0(s_axi_awid[2]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[52] ),
+        .O(skid_buffer[52]));
+  (* SOFT_HLUTNM = ""soft_lutpair51"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[53]_i_1 
+       (.I0(s_axi_awid[3]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[53] ),
+        .O(skid_buffer[53]));
+  (* SOFT_HLUTNM = ""soft_lutpair51"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[54]_i_1 
+       (.I0(s_axi_awid[4]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[54] ),
+        .O(skid_buffer[54]));
+  (* SOFT_HLUTNM = ""soft_lutpair50"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[55]_i_1 
+       (.I0(s_axi_awid[5]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[55] ),
+        .O(skid_buffer[55]));
+  (* SOFT_HLUTNM = ""soft_lutpair50"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[56]_i_1 
+       (.I0(s_axi_awid[6]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[56] ),
+        .O(skid_buffer[56]));
+  (* SOFT_HLUTNM = ""soft_lutpair49"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[57]_i_1 
+       (.I0(s_axi_awid[7]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[57] ),
+        .O(skid_buffer[57]));
+  (* SOFT_HLUTNM = ""soft_lutpair49"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[58]_i_1 
+       (.I0(s_axi_awid[8]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[58] ),
+        .O(skid_buffer[58]));
+  (* SOFT_HLUTNM = ""soft_lutpair48"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[59]_i_1 
+       (.I0(s_axi_awid[9]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[59] ),
+        .O(skid_buffer[59]));
+  (* SOFT_HLUTNM = ""soft_lutpair72"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1 
+       (.I0(s_axi_awaddr[5]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(skid_buffer[5]));
+  (* SOFT_HLUTNM = ""soft_lutpair47"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[60]_i_1 
+       (.I0(s_axi_awid[10]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[60] ),
+        .O(skid_buffer[60]));
+  (* SOFT_HLUTNM = ""soft_lutpair46"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[61]_i_1 
+       (.I0(s_axi_awid[11]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[61] ),
+        .O(skid_buffer[61]));
+  (* SOFT_HLUTNM = ""soft_lutpair71"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1 
+       (.I0(s_axi_awaddr[6]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(skid_buffer[6]));
+  (* SOFT_HLUTNM = ""soft_lutpair71"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1 
+       (.I0(s_axi_awaddr[7]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(skid_buffer[7]));
+  (* SOFT_HLUTNM = ""soft_lutpair70"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1 
+       (.I0(s_axi_awaddr[8]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(skid_buffer[8]));
+  (* SOFT_HLUTNM = ""soft_lutpair70"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1 
+       (.I0(s_axi_awaddr[9]),
+        .I1(s_axi_awready),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(skid_buffer[9]));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[0]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[10]),
+        .Q(Q[10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[11]),
+        .Q(Q[11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[12]),
+        .Q(Q[12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[13]),
+        .Q(Q[13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[14]),
+        .Q(Q[14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[15]),
+        .Q(Q[15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[16]),
+        .Q(Q[16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[17]),
+        .Q(Q[17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[18]),
+        .Q(Q[18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[19]),
+        .Q(Q[19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[1]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[20]),
+        .Q(Q[20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[21]),
+        .Q(Q[21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[22]),
+        .Q(Q[22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[23]),
+        .Q(Q[23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[24]),
+        .Q(Q[24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[25]),
+        .Q(Q[25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[26]),
+        .Q(Q[26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[27]),
+        .Q(Q[27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[28]),
+        .Q(Q[28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[29]),
+        .Q(Q[29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[2]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[30]),
+        .Q(Q[30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[31]),
+        .Q(Q[31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[32]),
+        .Q(Q[32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[33]),
+        .Q(Q[33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[34]),
+        .Q(Q[34]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[35] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[35]),
+        .Q(Q[35]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[36] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[36]),
+        .Q(Q[36]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[38] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[38]),
+        .Q(\\m_payload_i_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[39] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[39]),
+        .Q(Q[37]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[3]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[44] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[44]),
+        .Q(Q[38]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[45] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[45]),
+        .Q(Q[39]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[46] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[46]),
+        .Q(Q[40]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[47] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[47]),
+        .Q(Q[41]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[4]),
+        .Q(Q[4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[50] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[50]),
+        .Q(Q[42]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[51] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[51]),
+        .Q(Q[43]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[52] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[52]),
+        .Q(Q[44]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[53] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[53]),
+        .Q(Q[45]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[54] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[54]),
+        .Q(Q[46]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[55] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[55]),
+        .Q(Q[47]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[56] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[56]),
+        .Q(Q[48]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[57] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[57]),
+        .Q(Q[49]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[58] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[58]),
+        .Q(Q[50]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[59] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[59]),
+        .Q(Q[51]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[5]),
+        .Q(Q[5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[60] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[60]),
+        .Q(Q[52]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[61] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[61]),
+        .Q(Q[53]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[6]),
+        .Q(Q[6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[7]),
+        .Q(Q[7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[8]),
+        .Q(Q[8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[9]),
+        .Q(Q[9]),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hF4FF)) 
+    m_valid_i_i_1
+       (.I0(b_push),
+        .I1(m_valid_i_reg_0),
+        .I2(s_axi_awvalid),
+        .I3(s_axi_awready),
+        .O(m_valid_i0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i0),
+        .Q(m_valid_i_reg_0),
+        .R(\\aresetn_d_reg[1]_inv_0 ));
+  LUT4 #(
+    .INIT(16\'hFFFE)) 
+    next_pending_r_i_2
+       (.I0(Q[40]),
+        .I1(Q[39]),
+        .I2(Q[41]),
+        .I3(Q[38]),
+        .O(next_pending_r_reg));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    s_ready_i_i_1__1
+       (.I0(\\aresetn_d_reg_n_0_[0] ),
+        .O(s_ready_i_reg_0));
+  LUT4 #(
+    .INIT(16\'hF4FF)) 
+    s_ready_i_i_2
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_awready),
+        .I2(b_push),
+        .I3(m_valid_i_reg_0),
+        .O(s_ready_i0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i0),
+        .Q(s_axi_awready),
+        .R(s_ready_i_reg_0));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[10]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[11]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[12]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[13]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[14]),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[15]),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[16]),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[17]),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[18]),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[19]),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[20]),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[21]),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[22]),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[23]),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[24]),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[25]),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[26]),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[27]),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[28]),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[29]),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[30]),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[31]),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awprot[0]),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awprot[1]),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awprot[2]),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[35] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awsize[0]),
+        .Q(\\skid_buffer_reg_n_0_[35] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[36] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awsize[1]),
+        .Q(\\skid_buffer_reg_n_0_[36] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[38] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awburst[0]),
+        .Q(\\skid_buffer_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[39] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awburst[1]),
+        .Q(\\skid_buffer_reg_n_0_[39] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[3]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[44] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awlen[0]),
+        .Q(\\skid_buffer_reg_n_0_[44] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[45] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awlen[1]),
+        .Q(\\skid_buffer_reg_n_0_[45] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[46] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awlen[2]),
+        .Q(\\skid_buffer_reg_n_0_[46] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[47] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awlen[3]),
+        .Q(\\skid_buffer_reg_n_0_[47] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[4]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[50] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[0]),
+        .Q(\\skid_buffer_reg_n_0_[50] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[51] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[1]),
+        .Q(\\skid_buffer_reg_n_0_[51] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[52] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[2]),
+        .Q(\\skid_buffer_reg_n_0_[52] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[53] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[3]),
+        .Q(\\skid_buffer_reg_n_0_[53] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[54] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[4]),
+        .Q(\\skid_buffer_reg_n_0_[54] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[55] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[5]),
+        .Q(\\skid_buffer_reg_n_0_[55] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[56] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[6]),
+        .Q(\\skid_buffer_reg_n_0_[56] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[57] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[7]),
+        .Q(\\skid_buffer_reg_n_0_[57] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[58] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[8]),
+        .Q(\\skid_buffer_reg_n_0_[58] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[59] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[9]),
+        .Q(\\skid_buffer_reg_n_0_[59] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[5]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[60] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[10]),
+        .Q(\\skid_buffer_reg_n_0_[60] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[61] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awid[11]),
+        .Q(\\skid_buffer_reg_n_0_[61] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[6]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[7]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[8]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(s_axi_awready),
+        .D(s_axi_awaddr[9]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hAA8A)) 
+    \\wrap_boundary_axaddr_r[0]_i_1 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[38]),
+        .I3(Q[35]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [0]));
+  LUT5 #(
+    .INIT(32\'h8A888AAA)) 
+    \\wrap_boundary_axaddr_r[1]_i_1 
+       (.I0(Q[1]),
+        .I1(Q[36]),
+        .I2(Q[38]),
+        .I3(Q[35]),
+        .I4(Q[39]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [1]));
+  LUT6 #(
+    .INIT(64\'hA0A002A2AAAA02A2)) 
+    \\wrap_boundary_axaddr_r[2]_i_1__0 
+       (.I0(Q[2]),
+        .I1(Q[40]),
+        .I2(Q[35]),
+        .I3(Q[39]),
+        .I4(Q[36]),
+        .I5(Q[38]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [2]));
+  LUT6 #(
+    .INIT(64\'h020202A2A2A202A2)) 
+    \\wrap_boundary_axaddr_r[3]_i_1 
+       (.I0(Q[3]),
+        .I1(\\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
+        .I2(Q[36]),
+        .I3(Q[39]),
+        .I4(Q[35]),
+        .I5(Q[38]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [3]));
+  (* SOFT_HLUTNM = ""soft_lutpair42"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\wrap_boundary_axaddr_r[3]_i_2 
+       (.I0(Q[40]),
+        .I1(Q[35]),
+        .I2(Q[41]),
+        .O(\\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'h002A0A2AA02AAA2A)) 
+    \\wrap_boundary_axaddr_r[4]_i_1__0 
+       (.I0(Q['b'4]),
+        .I1(Q[41]),
+        .I2(Q[35]),
+        .I3(Q[36]),
+        .I4(Q[40]),
+        .I5(Q[39]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [4]));
+  (* SOFT_HLUTNM = ""soft_lutpair42"" *) 
+  LUT5 #(
+    .INIT(32\'h2A222AAA)) 
+    \\wrap_boundary_axaddr_r[5]_i_1 
+       (.I0(Q[5]),
+        .I1(Q[36]),
+        .I2(Q[40]),
+        .I3(Q[35]),
+        .I4(Q[41]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [5]));
+  LUT4 #(
+    .INIT(16\'h2AAA)) 
+    \\wrap_boundary_axaddr_r[6]_i_1 
+       (.I0(Q[6]),
+        .I1(Q[36]),
+        .I2(Q[35]),
+        .I3(Q[41]),
+        .O(\\wrap_boundary_axaddr_r_reg[6] [6]));
+  LUT6 #(
+    .INIT(64\'hDDDDD8DDAAAAA8AA)) 
+    \\wrap_cnt_r[0]_i_1 
+       (.I0(\\wrap_second_len_r[0]_i_2_n_0 ),
+        .I1(\\wrap_second_len_r[0]_i_3_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\wrap_second_len_r_reg[3] [0]),
+        .O(D[0]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\wrap_cnt_r[1]_i_1__0 
+       (.I0(\\wrap_second_len_r_reg[1] ),
+        .I1(\\wrap_cnt_r[3]_i_2_n_0 ),
+        .O(D[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair43"" *) 
+  LUT3 #(
+    .INIT(8\'h9A)) 
+    \\wrap_cnt_r[2]_i_1 
+       (.I0(wrap_second_len[1]),
+        .I1(\\wrap_cnt_r[3]_i_2_n_0 ),
+        .I2(\\wrap_second_len_r_reg[1] ),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair43"" *) 
+  LUT4 #(
+    .INIT(16\'hA6AA)) 
+    \\wrap_cnt_r[3]_i_1 
+       (.I0(wrap_second_len[2]),
+        .I1(\\wrap_second_len_r_reg[1] ),
+        .I2(\\wrap_cnt_r[3]_i_2_n_0 ),
+        .I3(wrap_second_len[1]),
+        .O(D[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair41"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAABAAA)) 
+    \\wrap_cnt_r[3]_i_2 
+       (.I0(\\wrap_cnt_r[3]_i_3_n_0 ),
+        .I1(\\axaddr_offset_r_reg[1] ),
+        .I2(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I3(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .I4(\\axaddr_offset_r_reg[3] ),
+        .O(\\wrap_cnt_r[3]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'h00000800FFFFF8FF)) 
+    \\wrap_cnt_r[3]_i_3 
+       (.I0(Q[38]),
+        .I1(\\axaddr_offset_r[0]_i_3_n_0 ),
+        .I2(\\state_reg[1]_0 [1]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [0]),
+        .I5(\\wrap_second_len_r_reg[3] [0]),
+        .O(\\wrap_cnt_r[3]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64\'h00000000CCCCCACC)) 
+    \\wrap_second_len_r[0]_i_1 
+       (.I0(\\wrap_second_len_r[0]_i_2_n_0 ),
+        .I1(\\wrap_second_len_r_reg[3] [0]),
+        .I2(\\state_reg[1]_0 [0]),
+        .I3(m_valid_i_reg_0),
+        .I4(\\state_reg[1]_0 [1]),
+        .I5(\\wrap_second_len_r[0]_i_3_n_0 ),
+        .O(wrap_second_len[0]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFF2FFFFFF)) 
+    \\wrap_second_len_r[0]_i_2 
+       (.I0(\\axaddr_offset_r_reg[3]_0 [3]),
+        .I1(\\state_reg[1] ),
+        .I2(\\wrap_second_len_r[3]_i_2_n_0 ),
+        .I3(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .I4(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I5(\\axaddr_offset_r_reg[1] ),
+        .O(\\wrap_second_len_r[0]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64\'h00000000FFE200E2)) 
+    \\wrap_second_len_r[0]_i_3 
+       (.I0(Q[0]),
+        .I1(Q[36]),
+        .I2(Q[2]),
+        .I3(Q[35]),
+        .I4(\\wrap_second_len_r[0]_i_4_n_0 ),
+        .I5(\\wrap_second_len_r[0]_i_5_n_0 ),
+        .O(\\wrap_second_len_r[0]_i_3_n_0 ));
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\wrap_second_len_r[0]_i_4 
+       (.I0(Q[3]),
+        .I1(Q[36]),
+        .I2(Q[1]),
+        .O(\\wrap_second_len_r[0]_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair44"" *) 
+  LUT4 #(
+    .INIT(16\'hFFDF)) 
+    \\wrap_second_len_r[0]_i_5 
+       (.I0(Q[38]),
+        .I1(\\state_reg[1]_0 [0]),
+        .I2(m_valid_i_reg_0),
+        .I3(\\state_reg[1]_0 [1]),
+        .O(\\wrap_second_len_r[0]_i_5_n_0 ));
+  LUT6 #(
+    .INIT(64\'h2EE22E222EE22EE2)) 
+    \\wrap_second_len_r[1]_i_1 
+       (.I0(\\wrap_second_len_r_reg[3] [1]),
+        .I1(\\state_reg[1] ),
+        .I2(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I3(\\axaddr_offset_r_reg[1] ),
+        .I4(\\axaddr_offset_r_reg[3] ),
+        .I5(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .O(\\wrap_second_len_r_reg[1] ));
+  LUT6 #(
+    .INIT(64\'h08F3FFFF08F30000)) 
+    \\wrap_second_len_r[2]_i_1 
+       (.I0(\\axaddr_offset_r_reg[3] ),
+        .I1(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I2(\\axaddr_offset_r_reg[1] ),
+        .I3(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .I4(\\state_reg[1] ),
+        .I5(\\wrap_second_len_r_reg[3] [2]),
+        .O(wrap_second_len[1]));
+  LUT6 #(
+    .INIT(64\'hBF00FFFFBF00BF00)) 
+    \\wrap_second_len_r[3]_i_1 
+       (.I0(\\axaddr_offset_r_reg[1] ),
+        .I1(\\axaddr_offset_r[0]_i_2_n_0 ),
+        .I2(\\axaddr_offset_r[2]_i_2_n_0 ),
+        .I3(\\wrap_second_len_r[3]_i_2_n_0 ),
+        .I4(\\state_reg[1] ),
+        .I5(\\wrap_second_len_r_reg[3] [3]),
+        .O(wrap_second_len[2]));
+  LUT6 #(
+    .INIT(64\'h00000000EEE222E2)) 
+    \\wrap_second_len_r[3]_i_2 
+       (.I0(\\axaddr_offset_r[2]_i_4_n_0 ),
+        .I1(Q[35]),
+        .I2(Q[4]),
+        .I3(Q[36]),
+        .I4(Q[6]),
+        .I5(\\axlen_cnt_reg[3] ),
+        .O(\\wrap_second_len_r[3]_i_2_n_0 ));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_register_slice_v2_1_11_axic_register_slice"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice__parameterized1
+   (s_axi_bvalid,
+    \\skid_buffer_reg[0]_0 ,
+    shandshake,
+    \\s_axi_bid[11] ,
+    \\aresetn_d_reg[1]_inv ,
+    aclk,
+    \\aresetn_d_reg[0] ,
+    si_rs_bvalid,
+    s_axi_bready,
+    out,
+    \\s_bresp_acc_reg[1] );
+  output s_axi_bvalid;
+  output \\skid_buffer_reg[0]_0 ;
+  output shandshake;
+  output [13:0]\\s_axi_bid[11] ;
+  input \\aresetn_d_reg[1]_inv ;
+  input aclk;
+  input \\aresetn_d_reg[0] ;
+  input si_rs_bvalid;
+  input s_axi_bready;
+  input [11:0]out;
+  input [1:0]\\s_bresp_acc_reg[1] ;
+
+  wire aclk;
+  wire \\aresetn_d_reg[0] ;
+  wire \\aresetn_d_reg[1]_inv ;
+  wire \\m_payload_i[0]_i_1__1_n_0 ;
+  wire \\m_payload_i[10]_i_1__1_n_0 ;
+  wire \\m_payload_i[11]_i_1__1_n_0 ;
+  wire \\m_payload_i[12]_i_1__1_n_0 ;
+  wire \\m_payload_i[13]_i_2_n_0 ;
+  wire \\m_payload_i[1]_i_1__1_n_0 ;
+  wire \\m_payload_i[2]_i_1__1_n_0 ;
+  wire \\m_payload_i[3]_i_1__1_n_0 ;
+  wire \\m_payload_i[4]_i_1__1_n_0 ;
+  wire \\m_payload_i[5]_i_1__1_n_0 ;
+  wire \\m_payload_i[6]_i_1__1_n_0 ;
+  wire \\m_payload_i[7]_i_1__1_n_0 ;
+  wire \\m_payload_i[8]_i_1__1_n_0 ;
+  wire \\m_payload_i[9]_i_1__1_n_0 ;
+  wire m_valid_i0;
+  wire [11:0]out;
+  wire p_1_in;
+  wire [13:0]\\s_axi_bid[11] ;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [1:0]\\s_bresp_acc_reg[1] ;
+  wire s_ready_i0;
+  wire shandshake;
+  wire si_rs_bvalid;
+  wire \\skid_buffer_reg[0]_0 ;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair80"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[0]_i_1__1 
+       (.I0(\\s_bresp_acc_reg[1] [0]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[0] ),
+        .O(\\m_payload_i[0]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair75"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1__1 
+       (.I0(out[8]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(\\m_payload_i[10]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair74"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1__1 
+       (.I0(out[9]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(\\m_payload_i[11]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair75"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1__1 
+       (.I0(out[10]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(\\m_payload_i[12]_i_1__1_n_0 ));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_payload_i[13]_i_1 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .O(p_1_in));
+  (* SOFT_HLUTNM = ""soft_lutpair74"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_2 
+       (.I0(out[11]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(\\m_payload_i[13]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair80"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[1]_i_1__1 
+       (.I0(\\s_bresp_acc_reg[1] [1]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[1] ),
+        .O(\\m_payload_i[1]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair79"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[2]_i_1__1 
+       (.I0(out[0]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[2] ),
+        .O(\\m_payload_i[2]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair79"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1__1 
+       (.I0(out[1]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(\\m_payload_i[3]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair78"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1__1 
+       (.I0(out[2]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(\\m_payload_i[4]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair78"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1__1 
+       (.I0(out[3]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(\\m_payload_i[5]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair77"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1__1 
+       (.I0(out[4]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(\\m_payload_i[6]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair77"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1__1 
+       (.I0(out[5]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(\\m_payload_i[7]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair76"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1__1 
+       (.I0(out[6]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(\\m_payload_i[8]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair76"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1__1 
+       (.I0(out[7]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(\\m_payload_i[9]_i_1__1_n_0 ));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[0]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[10]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[11]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[12]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[13]_i_2_n_0 ),
+        .Q(\\s_axi_bid[11] [13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[1]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[2]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[3]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[4]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[5]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[6]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[7]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[8]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[9]_i_1__1_n_0 ),
+        .Q(\\s_axi_bid[11] [9]),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'hF4FF)) 
+    m_valid_i_i_1__0
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(si_rs_bvalid),
+        .I3(\\skid_buffer_reg[0]_0 ),
+        .O(m_valid_i0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i0),
+        .Q(s_axi_bvalid),
+        .R(\\aresetn_d_reg[1]_inv ));
+  (* SOFT_HLUTNM = ""soft_lutpair73"" *) 
+  LUT4 #(
+    .INIT(16\'hF4FF)) 
+    s_ready_i_i_1
+       (.I0(si_rs_bvalid),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(s_axi_bready),
+        .I3(s_axi_bvalid),
+        .O(s_ready_i0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i0),
+        .Q(\\skid_buffer_reg[0]_0 ),
+        .R(\\aresetn_d_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair73"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    shandshake_r_i_1
+       (.I0(\\skid_buffer_reg[0]_0 ),
+        .I1(si_rs_bvalid),
+        .O(shandshake));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\s_bresp_acc_reg[1] [0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[8]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[9]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[10]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[11]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\s_bresp_acc_reg[1] [1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[0]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[1]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[2]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[3]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[4]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[5]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[6]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(out[7]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_register_slice_v2_1_11_axic_register_slice"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice__parameterized2
+   (s_axi_rvalid,
+    \\skid_buffer_reg[0]_0 ,
+    \\s_axi_rid[11] ,
+    \\aresetn_d_reg[1]_inv ,
+    aclk,
+    \\aresetn_d_reg[0] ,
+    \\cnt_read_reg[3]_rep__2 ,
+    s_axi_rready,
+    r_push_r_reg,
+    \\cnt_read_reg[4] );
+  output s_axi_rvalid;
+  output \\skid_buffer_reg[0]_0 ;
+  output [46:0]\\s_axi_rid[11] ;
+  input \\aresetn_d_reg[1]_inv ;
+  input aclk;
+  input \\aresetn_d_reg[0] ;
+  input \\cnt_read_reg[3]_rep__2 ;
+  input s_axi_rready;
+  input [12:0]r_push_r_reg;
+  input [33:0]\\cnt_read_reg[4] ;
+
+  wire aclk;
+  wire \\aresetn_d_reg[0] ;
+  wire \\aresetn_d_reg[1]_inv ;
+  wire \\cnt_read_reg[3]_rep__2 ;
+  wire [33:0]\\cnt_read_reg[4] ;
+  wire \\m_payload_i[0]_i_1__2_n_0 ;
+  wire \\m_payload_i[10]_i_1__2_n_0 ;
+  wire \\m_payload_i[11]_i_1__2_n_0 ;
+  wire \\m_payload_i[12]_i_1__2_n_0 ;
+  wire \\m_payload_i[13]_i_1__2_n_0 ;
+  wire \\m_payload_i[14]_i_1__1_n_0 ;
+  wire \\m_payload_i[15]_i_1__1_n_0 ;
+  wire \\m_payload_i[16]_i_1__1_n_0 ;
+  wire \\m_payload_i[17]_i_1__1_n_0 ;
+  wire \\m_payload_i[18]_i_1__1_n_0 ;
+  wire \\m_payload_i[19]_i_1__1_n_0 ;
+  wire \\m_payload_i[1]_i_1__2_n_0 ;
+  wire \\m_payload_i[20]_i_1__1_n_0 ;
+  wire \\m_payload_i[21]_i_1__1_n_0 ;
+  wire \\m_payload_i[22]_i_1__1_n_0 ;
+  wire \\m_payload_i[23]_i_1__1_n_0 ;
+  wire \\m_payload_i[24]_i_1__1_n_0 ;
+  wire \\m_payload_i[25]_i_1__1_n_0 ;
+  wire \\m_payload_i[26]_i_1__1_n_0 ;
+  wire \\m_payload_i[27]_i_1__1_n_0 ;
+  wire \\m_payload_i[28]_i_1__1_n_0 ;
+  wire \\m_payload_i[29]_i_1__1_n_0 ;
+  wire \\m_payload_i[2]_i_1__2_n_0 ;
+  wire \\m_payload_i[30]_i_1__1_n_0 ;
+  wire \\m_payload_i[31]_i_1__1_n_0 ;
+  wire \\m_payload_i[32]_i_1__1_n_0 ;
+  wire \\m_payload_i[33]_i_1__1_n_0 ;
+  wire \\m_payload_i[34]_i_1__1_n_0 ;
+  wire \\m_payload_i[35]_i_1__1_n_0 ;
+  wire \\m_payload_i[36]_i_1__1_n_0 ;
+  wire \\m_payload_i[37]_i_1_n_0 ;
+  wire \\m_payload_i[38]_i_1__1_n_0 ;
+  wire \\m_payload_i[39]_i_1__1_n_0 ;
+  wire \\m_payload_i[3]_i_1__2_n_0 ;
+  wire \\m_payload_i[40]_i_1_n_0 ;
+  wire \\m_payload_i[41]_i_1_n_0 ;
+  wire \\m_payload_i[42]_i_1_n_0 ;
+  wire \\m_payload_i[43]_i_1_n_0 ;
+  wire \\m_payload_i[44]_i_1__1_n_0 ;
+  wire \\m_payload_i[45]_i_1__1_n_0 ;
+  wire \\m_payload_i[46]_i_2_n_0 ;
+  wire \\m_payload_i[4]_i_1__2_n_0 ;
+  wire \\m_payload_i[5]_i_1__2_n_0 ;
+  wire \\m_payload_i[6]_i_1__2_n_0 ;
+  wire \\m_payload_i[7]_i_1__2_n_0 ;
+  wire \\m_payload_i[8]_i_1__2_n_0 ;
+  wire \\m_payload_i[9]_i_1__2_n_0 ;
+  wire m_valid_i_i_1__2_n_0;
+  wire p_1_in;
+  wire [12:0]r_push_r_reg;
+  wire [46:0]\\s_axi_rid[11] ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_ready_i_i_1__2_n_0;
+  wire \\skid_buffer_reg[0]_0 ;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[35] ;
+  wire \\skid_buffer_reg_n_0_[36] ;
+  wire \\skid_buffer_reg_n_0_[37] ;
+  wire \\skid_buffer_reg_n_0_[38] ;
+  wire \\skid_buffer_reg_n_0_[39] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[40] ;
+  wire \\skid_buffer_reg_n_0_[41] ;
+  wire \\skid_buffer_reg_n_0_[42] ;
+  wire \\skid_buffer_reg_n_0_[43] ;
+  wire \\skid_buffer_reg_n_0_[44] ;
+  wire \\skid_buffer_reg_n_0_[45] ;
+  wire \\skid_buffer_reg_n_0_[46] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[0]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [0]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[0] ),
+        .O(\\m_payload_i[0]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair99"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [10]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(\\m_payload_i[10]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair98"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [11]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(\\m_payload_i[11]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair98"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [12]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(\\m_payload_i[12]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair97"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [13]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(\\m_payload_i[13]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair97"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [14]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(\\m_payload_i[14]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair96"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [15]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(\\m_payload_i[15]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair96"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [16]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(\\m_payload_i[16]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair95"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [17]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(\\m_payload_i[17]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair95"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [18]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(\\m_payload_i[18]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair94"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [19]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(\\m_payload_i[19]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair103"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[1]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [1]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[1] ),
+        .O(\\m_payload_i[1]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair94"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [20]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(\\m_payload_i[20]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair93"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [21]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(\\m_payload_i[21]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair93"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [22]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(\\m_payload_i[22]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair92"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [23]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(\\m_payload_i[23]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair92"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [24]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(\\m_payload_i[24]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair91"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [25]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(\\m_payload_i[25]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair91"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [26]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(\\m_payload_i[26]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair90"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [27]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(\\m_payload_i[27]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair90"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [28]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(\\m_payload_i[28]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair89"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [29]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(\\m_payload_i[29]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair103"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[2]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [2]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[2] ),
+        .O(\\m_payload_i[2]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair89"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [30]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(\\m_payload_i[30]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair88"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [31]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(\\m_payload_i[31]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair88"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [32]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(\\m_payload_i[32]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair87"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1__1 
+       (.I0(\\cnt_read_reg[4] [33]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(\\m_payload_i[33]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair87"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_1__1 
+       (.I0(r_push_r_reg[0]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(\\m_payload_i[34]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair86"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[35]_i_1__1 
+       (.I0(r_push_r_reg[1]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[35] ),
+        .O(\\m_payload_i[35]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair86"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[36]_i_1__1 
+       (.I0(r_push_r_reg[2]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[36] ),
+        .O(\\m_payload_i[36]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair85"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[37]_i_1 
+       (.I0(r_push_r_reg[3]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[37] ),
+        .O(\\m_payload_i[37]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair85"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[38]_i_1__1 
+       (.I0(r_push_r_reg[4]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[38] ),
+        .O(\\m_payload_i[38]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair84"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[39]_i_1__1 
+       (.I0(r_push_r_reg[5]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[39] ),
+        .O(\\m_payload_i[39]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair102"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [3]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(\\m_payload_i[3]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair84"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[40]_i_1 
+       (.I0(r_push_r_reg[6]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[40] ),
+        .O(\\m_payload_i[40]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair83"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[41]_i_1 
+       (.I0(r_push_r_reg[7]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[41] ),
+        .O(\\m_payload_i[41]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair83"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[42]_i_1 
+       (.I0(r_push_r_reg[8]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[42] ),
+        .O(\\m_payload_i[42]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair82"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[43]_i_1 
+       (.I0(r_push_r_reg[9]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[43] ),
+        .O(\\m_payload_i[43]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair81"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[44]_i_1__1 
+       (.I0(r_push_r_reg[10]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[44] ),
+        .O(\\m_payload_i[44]_i_1__1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair82"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[45]_i_1__1 
+       (.I0(r_push_r_reg[11]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[45] ),
+        .O(\\m_payload_i[45]_i_1__1_n_0 ));
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\m_payload_i[46]_i_1 
+       (.I0(s_axi_rready),
+        .I1(s_axi_rvalid),
+        .O(p_1_in));
+  (* SOFT_HLUTNM = ""soft_lutpair81"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[46]_i_2 
+       (.I0(r_push_r_reg[12]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[46] ),
+        .O(\\m_payload_i[46]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair102"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [4]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(\\m_payload_i[4]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair101"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [5]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(\\m_payload_i[5]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair101"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [6]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(\\m_payload_i[6]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair100"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [7]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(\\m_payload_i[7]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair100"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [8]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(\\m_payload_i[8]_i_1__2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair99"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1__2 
+       (.I0(\\cnt_read_reg[4] [9]),
+        .I1(\\skid_buffer_reg[0]_0 ),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(\\m_payload_i[9]_i_1__2_n_0 ));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[0]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[10]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[11]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[12]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[13]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[14]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[15]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[16]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[17]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[18]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[19]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[1]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[20]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[21]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[22]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[23]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[24]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[25]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[26]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[27]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[28]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[29]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[2]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[30]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[31]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[32]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[33]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[34]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [34]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[35] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[35]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [35]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[36] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[36]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [36]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[37] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[37]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [37]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[38] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[38]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [38]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[39] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[39]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [39]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[3]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[40] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[40]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [40]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[41] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[41]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [41]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[42] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[42]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [42]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[43] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[43]_i_1_n_0 ),
+        .Q(\\s_axi_rid[11] [43]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[44] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[44]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [44]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[45] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[45]_i_1__1_n_0 ),
+        .Q(\\s_axi_rid[11] [45]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[46] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[46]_i_2_n_0 ),
+        .Q(\\s_axi_rid[11] [46]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[4]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[5]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[6]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[7]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[8]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [8]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(p_1_in),
+        .D(\\m_payload_i[9]_i_1__2_n_0 ),
+        .Q(\\s_axi_rid[11] [9]),
+        .R(1\'b0));
+  LUT4 #(
+    .INIT(16\'h4FFF)) 
+    m_valid_i_i_1__2
+       (.I0(s_axi_rready),
+        .I1(s_axi_rvalid),
+        .I2(\\skid_buffer_reg[0]_0 ),
+        .I3(\\cnt_read_reg[3]_rep__2 ),
+        .O(m_valid_i_i_1__2_n_0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i_i_1__2_n_0),
+        .Q(s_axi_rvalid),
+        .R(\\aresetn_d_reg[1]_inv ));
+  LUT4 #(
+    .INIT(16\'hF8FF)) 
+    s_ready_i_i_1__2
+       (.I0(\\skid_buffer_reg[0]_0 ),
+        .I1(\\cnt_read_reg[3]_rep__2 ),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(s_ready_i_i_1__2_n_0));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(s_ready_i_i_1__2_n_0),
+        .Q(\\skid_buffer_reg[0]_0 ),
+        .R(\\aresetn_d_reg[0] ));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [10]),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [11]),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [12]),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [13]),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [14]),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [15]),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [16]),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [17]),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [18]),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [19]),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [20]),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [21]),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [22]),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [23]),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [24]),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [25]),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [26]),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [27]),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [28]),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [29]),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [30]),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [31]),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [32]),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [33]),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[0]),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[35] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[1]),
+        .Q(\\skid_buffer_reg_n_0_[35] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[36] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[2]),
+        .Q(\\skid_buffer_reg_n_0_[36] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[37] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[3]),
+        .Q(\\skid_buffer_reg_n_0_[37] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[38] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[4]),
+        .Q(\\skid_buffer_reg_n_0_[38] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[39] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[5]),
+        .Q(\\skid_buffer_reg_n_0_[39] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [3]),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[40] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[6]),
+        .Q(\\skid_buffer_reg_n_0_[40] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[41] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[7]),
+        .Q(\\skid_buffer_reg_n_0_[41] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[42] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[8]),
+        .Q(\\skid_buffer_reg_n_0_[42] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[43] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[9]),
+        .Q(\\skid_buffer_reg_n_0_[43] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[44] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[10]),
+        .Q(\\skid_buffer_reg_n_0_[44] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[45] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[11]),
+        .Q(\\skid_buffer_reg_n_0_[45] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[46] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(r_push_r_reg[12]),
+        .Q(\\skid_buffer_reg_n_0_[46] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [4]),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [5]),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [6]),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [7]),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [8]),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(\\skid_buffer_reg[0]_0 ),
+        .D(\\cnt_read_reg[4] [9]),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awqos,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arqos,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awaddr,
+    m_axi_awprot,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bresp,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_araddr,
+    m_axi_arprot,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rvalid,
+    m_axi_rready);
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLK CLK"" *) input aclk;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RST RST"" *) input aresetn;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWID"" *) input [11:0]s_axi_awid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [31:0]s_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWLEN"" *) input [3:0]s_axi_awlen;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"" *) input [2:0]s_axi_awsize;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWBURST"" *) input [1:0]s_axi_awburst;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"" *) input [1:0]s_axi_awlock;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"" *) input [3:0]s_axi_awcache;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWPROT"" *) input [2:0]s_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWQOS"" *) input [3:0]s_axi_awqos;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *) input s_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WID"" *) input [11:0]s_axi_wid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WLAST"" *) input s_axi_wlast;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BID"" *) output [11:0]s_axi_bid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARID"" *) input [11:0]s_axi_arid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [31:0]s_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARLEN"" *) input [3:0]s_axi_arlen;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"" *) input [2:0]s_axi_arsize;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARBURST"" *) input [1:0]s_axi_arburst;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"" *) input [1:0]s_axi_arlock;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"" *) input [3:0]s_axi_arcache;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARPROT"" *) input [2:0]s_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARQOS"" *) input [3:0]s_axi_arqos;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RID"" *) output [11:0]s_axi_rid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RLAST"" *) output s_axi_rlast;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWADDR"" *) output [31:0]m_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWPROT"" *) output [2:0]m_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWVALID"" *) output m_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWREADY"" *) input m_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WDATA"" *) output [31:0]m_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WSTRB"" *) output [3:0]m_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WVALID"" *) output m_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WREADY"" *) input m_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BRESP"" *) input [1:0]m_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BVALID"" *) input m_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BREADY"" *) output m_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARADDR"" *) output [31:0]m_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARPROT"" *) output [2:0]m_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARVALID"" *) output m_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARREADY"" *) input m_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RDATA"" *) input [31:0]m_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RRESP"" *) input [1:0]m_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RVALID"" *) input m_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RREADY"" *) output m_axi_rready;
+
+  wire aclk;
+  wire aresetn;
+  wire [31:0]m_axi_araddr;
+  wire [2:0]m_axi_arprot;
+  wire m_axi_arready;
+  wire m_axi_arvalid;
+  wire [31:0]m_axi_awaddr;
+  wire [2:0]m_axi_awprot;
+  wire m_axi_awready;
+  wire m_axi_awvalid;
+  wire m_axi_bready;
+  wire [1:0]m_axi_bresp;
+  wire m_axi_bvalid;
+  wire [31:0]m_axi_rdata;
+  wire m_axi_rready;
+  wire [1:0]m_axi_rresp;
+  wire m_axi_rvalid;
+  wire [31:0]m_axi_wdata;
+  wire m_axi_wready;
+  wire [3:0]m_axi_wstrb;
+  wire m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [1:0]s_axi_arburst;
+  wire [3:0]s_axi_arcache;
+  wire [11:0]s_axi_arid;
+  wire [3:0]s_axi_arlen;
+  wire [1:0]s_axi_arlock;
+  wire [2:0]s_axi_arprot;
+  wire [3:0]s_axi_arqos;
+  wire s_axi_arready;
+  wire [2:0]s_axi_arsize;
+  wire s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [1:0]s_axi_awburst;
+  wire [3:0]s_axi_awcache;
+  wire [11:0]s_axi_awid;
+  wire [3:0]s_axi_awlen;
+  wire [1:0]s_axi_awlock;
+  wire [2:0]s_axi_awprot;
+  wire [3:0]s_axi_awqos;
+  wire s_axi_awready;
+  wire [2:0]s_axi_awsize;
+  wire s_axi_awvalid;
+  wire [11:0]s_axi_bid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [11:0]s_axi_rid;
+  wire s_axi_rlast;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [11:0]s_axi_wid;
+  wire s_axi_wlast;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire NLW_inst_m_axi_wlast_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+  wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
+  wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+  wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
+  wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+  (* C_AXI_ADDR_WIDTH = ""32"" *) 
+  (* C_AXI_ARUSER_WIDTH = ""1"" *) 
+  (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+  (* C_AXI_BUSER_WIDTH = ""1"" *) 
+  (* C_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_AXI_ID_WIDTH = ""12"" *) 
+  (* C_AXI_RUSER_WIDTH = ""1"" *) 
+  (* C_AXI_SUPPORTS_READ = ""1"" *) 
+  (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+  (* C_AXI_SUPPORTS_WRITE = ""1"" *) 
+  (* C_AXI_WUSER_WIDTH = ""1"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_IGNORE_ID = ""0"" *) 
+  (* C_M_AXI_PROTOCOL = ""2"" *) 
+  (* C_S_AXI_PROTOCOL = ""1"" *) 
+  (* C_TRANSLATION_MODE = ""2"" *) 
+  (* DowngradeIPIdentifiedWarnings = ""yes"" *) 
+  (* P_AXI3 = ""1"" *) 
+  (* P_AXI4 = ""0"" *) 
+  (* P_AXILITE = ""2"" *) 
+  (* P_AXILITE_SIZE = ""3\'b010"" *) 
+  (* P_CONVERSION = ""2"" *) 
+  (* P_DECERR = ""2\'b11"" *) 
+  (* P_INCR = ""2\'b01"" *) 
+  (* P_PROTECTION = ""1"" *) 
+  (* P_SLVERR = ""2\'b10"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_11_axi_protocol_converter inst
+       (.aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
+        .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
+        .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
+        .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
+        .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
+        .m_axi_arprot(m_axi_arprot),
+        .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
+        .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
+        .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
+        .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
+        .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
+        .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
+        .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
+        .m_axi_awprot(m_axi_awprot),
+        .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
+        .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
+        .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bid({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_buser(1\'b0),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rid({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .m_axi_rlast(1\'b1),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_ruser(1\'b0),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wdata(m_axi_wdata),
+        .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
+        .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wstrb(m_axi_wstrb),
+        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst(s_axi_arburst),
+        .s_axi_arcache(s_axi_arcache),
+        .s_axi_arid(s_axi_arid),
+        .s_axi_arlen(s_axi_arlen),
+        .s_axi_arlock(s_axi_arlock),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arqos(s_axi_arqos),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arregion({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arsize(s_axi_arsize),
+        .s_axi_aruser(1\'b0),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst(s_axi_awburst),
+        .s_axi_awcache(s_axi_awcache),
+        .s_axi_awid(s_axi_awid),
+        .s_axi_awlen(s_axi_awlen),
+        .s_axi_awlock(s_axi_awlock),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awqos(s_axi_awqos),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awregion({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awsize(s_axi_awsize),
+        .s_axi_awuser(1\'b0),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bid(s_axi_bid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rid(s_axi_rid),
+        .s_axi_rlast(s_axi_rlast),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wid(s_axi_wid),
+        .s_axi_wlast(s_axi_wlast),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wuser(1\'b0),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, ""Critical
+// Applications""). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
+// IP Revision: 12
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = ""yes"" *)
+module design_1_xbar_0 (
+  aclk,
+  aresetn,
+  s_axi_awaddr,
+  s_axi_awprot,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arprot,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLKIF CLK"" *)
+input wire aclk;
+(* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RSTIF RST"" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"" *)
+input wire [0 : 0] s_axi_awvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"" *)
+output wire [0 : 0] s_axi_awready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WDATA"" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WVALID"" *)
+input wire [0 : 0] s_axi_wvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WREADY"" *)
+output wire [0 : 0] s_axi_wready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BRESP"" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BVALID"" *)
+output wire [0 : 0] s_axi_bvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BREADY"" *)
+input wire [0 : 0] s_axi_bready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"" *)
+input wire [0 : 0] s_axi_arvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"" *)
+output wire [0 : 0] s_axi_arready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RDATA"" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RRESP"" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RVALID"" *)
+output wire [0 : 0] s_axi_rvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RREADY"" *)
+input wire [0 : 0] s_axi_rready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]"" *)
+output wire [95 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]"" *)
+output wire [8 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_awvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_awready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]"" *)
+output wire [95 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]"" *)
+output wire [11 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_wvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_wready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]"" *)
+input wire [5 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_bvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_bready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]"" *)
+output wire [95 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]"" *)
+output wire [8 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_arvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_arready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]"" *)
+input wire [95 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]"" *)
+input wire [5 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]"" *)
+input wire [2 : 0] m_axi_rvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]"" *)
+output wire [2 : 0] m_axi_rready;
+
+  axi_crossbar_v2_1_12_axi_crossbar #(
+    .C_FAMILY(""zynq""),
+    .C_NUM_SLAVE_SLOTS(1),
+    .C_NUM_MASTER_SLOTS(3),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_PROTOCOL(2),
+    .C_NUM_ADDR_RANGES(1),
+    .C_M_AXI_BASE_ADDR(192\'Hffffffffffffffff00000000412100000000000041200000),
+    .C_M_AXI_ADDR_WIDTH(96\'H000000000000001000000010),
+    .C_S_AXI_BASE_ID(32\'H00000000),
+    .C_S_AXI_THREAD_ID_WIDTH(32\'H00000000),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_M_AXI_WRITE_CONNECTIVITY(96\'H000000010000000100000001),
+    .C_M_AXI_READ_CONNECTIVITY(96\'H000000010000000100000001),
+    .C_R_REGISTER(1),
+    .C_S_AXI_SINGLE_THREAD(32\'H00000001),
+    .C_S_AXI_WRITE_ACCEPTANCE(32\'H00000001),
+    .C_S_AXI_READ_ACCEPTANCE(32\'H00000001),
+    .C_M_AXI_WRITE_ISSUING(96\'H000000010000000100000001),
+    .C_M_AXI_READ_ISSUING(96\'H000000010000000100000001),
+    .C_S_AXI_ARB_PRIORITY(32\'H00000000),
+    .C_M_AXI_SECURE(96\'H000000000000000000000000),
+    .C_CONNECTIVITY_MODE(0)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(1\'H0),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(8\'H00),
+    .s_axi_awsize(3\'H0),
+    .s_axi_awburst(2\'H0),
+    .s_axi_awlock(1\'H0),
+    .s_axi_awcache(4\'H0),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(4\'H0),
+    .s_axi_awuser(1\'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(1\'H0),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(1\'H1),
+    .s_axi_wuser(1\'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(1\'H0),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(8\'H00),
+    .s_axi_arsize(3\'H0),
+    .s_axi_arburst(2\'H0),
+    .s_axi_arlock(1\'H0),
+    .s_axi_arcache(4\'H0),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(4\'H0),
+    .s_axi_aruser(1\'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(3\'H0),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(3\'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(3\'H0),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(3\'H7),
+    .m_axi_ruser(3\'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:37:25 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
+// Design      : design_1_xbar_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, 
+  s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr, 
+  m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, 
+  m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, 
+  m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
+/* synthesis syn_black_box black_box_pad_pin=""aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]"" */;
+  input aclk;
+  input aresetn;
+  input [31:0]s_axi_awaddr;
+  input [2:0]s_axi_awprot;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [31:0]s_axi_araddr;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [95:0]m_axi_awaddr;
+  output [8:0]m_axi_awprot;
+  output [2:0]m_axi_awvalid;
+  input [2:0]m_axi_awready;
+  output [95:0]m_axi_wdata;
+  output [11:0]m_axi_wstrb;
+  output [2:0]m_axi_wvalid;
+  input [2:0]m_axi_wready;
+  input [5:0]m_axi_bresp;
+  input [2:0]m_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [95:0]m_axi_araddr;
+  output [8:0]m_axi_arprot;
+  output [2:0]m_axi_arvalid;
+  input [2:0]m_axi_arready;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rvalid;
+  output [2:0]m_axi_rready;
+endmodule
+"
+"// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: addr_arbiter_sasd.v
+//
+// Description: 
+//   Hybrid priority + round-robin arbiter.
+//   Read & write requests combined (read preferred) at each slot
+//   Muxes AR and AW channel payload inputs based on arbitration results.
+//-----------------------------------------------------------------------------
+//
+// Structure:
+//    addr_arbiter_sasd
+//      mux_enc
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_addr_arbiter_sasd #
+  (
+   parameter         C_FAMILY                         = ""none"", 
+   parameter integer C_NUM_S                = 1, 
+   parameter integer C_NUM_S_LOG                = 1, 
+   parameter integer C_AMESG_WIDTH                 = 1, 
+   parameter         C_GRANT_ENC        = 0,
+   parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY             = {C_NUM_S{32\'h00000000}}
+                       // Arbitration priority among each SI slot. 
+                       // Higher values indicate higher priority.
+                       // Format: C_NUM_SLAVE_SLOTS{Bit32};
+                       // Range: \'h0-\'hF.
+   )
+  (
+   // Global Signals
+   input  wire                                      ACLK,
+   input  wire                                      ARESET,
+   // Slave Ports
+   input  wire [C_NUM_S*C_AMESG_WIDTH-1:0]  S_AWMESG,
+   input  wire [C_NUM_S*C_AMESG_WIDTH-1:0]  S_ARMESG,
+   input  wire [C_NUM_S-1:0]                S_AWVALID,
+   output wire [C_NUM_S-1:0]                S_AWREADY,
+   input  wire [C_NUM_S-1:0]                S_ARVALID,
+   output wire [C_NUM_S-1:0]                S_ARREADY,
+   // Master Ports
+   output wire [C_AMESG_WIDTH-1:0]          M_AMESG,
+   output wire [C_NUM_S_LOG-1:0]            M_GRANT_ENC,
+   output wire [C_NUM_S-1:0]                M_GRANT_HOT,
+   output wire                              M_GRANT_RNW,
+   output wire                              M_GRANT_ANY,
+   output wire                              M_AWVALID,
+   input  wire                              M_AWREADY,
+   output wire                              M_ARVALID,
+   input  wire                              M_ARREADY
+   );
+   
+  // Generates a mask for all input slots that are priority based
+  function [C_NUM_S-1:0] f_prio_mask
+    (
+      input integer null_arg
+    );
+    reg   [C_NUM_S-1:0]            mask;
+    integer                        i;    
+    begin
+      mask = 0;    
+      for (i=0; i < C_NUM_S; i=i+1) begin
+        mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);
+      end 
+      f_prio_mask = mask;
+    end   
+  endfunction
+  
+  // Convert 16-bit one-hot to 4-bit binary
+  function [3:0] f_hot2enc
+    (
+      input [15:0]  one_hot
+    );
+    begin
+      f_hot2enc[0] = |(one_hot & 16\'b1010101010101010);
+      f_hot2enc[1] = |(one_hot & 16\'b1100110011001100);
+      f_hot2enc[2] = |(one_hot & 16\'b1111000011110000);
+      f_hot2enc[3] = |(one_hot & 16\'b1111111100000000);
+    end
+  endfunction
+
+  localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);
+
+  reg                     m_valid_i;
+  reg [C_NUM_S-1:0]       s_ready_i;
+  reg [C_NUM_S-1:0]       s_awvalid_reg;
+  reg [C_NUM_S-1:0]       s_arvalid_reg;
+  wire [15:0]             s_avalid;
+  wire                    m_aready;
+  wire [C_NUM_S-1:0]      rnw;
+  reg                     grant_rnw;
+  reg [C_NUM_S_LOG-1:0]   m_grant_enc_i;
+  reg [C_NUM_S-1:0]       m_grant_hot_i; 
+  reg [C_NUM_S-1:0]       last_rr_hot;
+  reg                     any_grant;
+  reg                     any_prio;
+  reg [C_NUM_S-1:0]       which_prio_hot;
+  reg [C_NUM_S_LOG-1:0]   which_prio_enc;          
+  reg [4:0]               current_highest;
+  reg [15:0]              next_prio_hot;
+  reg [C_NUM_S_LOG-1:0]   next_prio_enc;    
+  reg                     found_prio;
+  wire [C_NUM_S-1:0]      valid_rr;
+  reg [15:0]              next_rr_hot;
+  reg [C_NUM_S_LOG-1:0]   next_rr_enc;    
+  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
+  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
+  reg                     found_rr;
+  wire [C_NUM_S-1:0]      next_hot;
+  wire [C_NUM_S_LOG-1:0]  next_enc;    
+  integer                 i;
+  wire  [C_AMESG_WIDTH-1:0] amesg_mux;
+  reg   [C_AMESG_WIDTH-1:0] m_amesg_i;
+  wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg;
+  genvar                  gen_si;
+
+  always @(posedge ACLK) begin
+    if (ARESET) begin
+      s_awvalid_reg <= 0;
+      s_arvalid_reg <= 0;
+    end else if (|s_ready_i) begin
+      s_awvalid_reg <= 0;
+      s_arvalid_reg <= 0;
+    end else begin
+      s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg;
+      s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg);
+    end
+  end
+  
+  assign s_avalid = S_AWVALID | S_ARVALID;
+  assign M_AWVALID = m_valid_i & ~grant_rnw;
+  assign M_ARVALID = m_valid_i & grant_rnw;
+  assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}};
+  assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}};
+  assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0;
+  assign M_GRANT_HOT = m_grant_hot_i;
+  assign M_GRANT_RNW = grant_rnw;
+  assign rnw = S_ARVALID & ~s_awvalid_reg;
+  assign M_AMESG = m_amesg_i;
+  assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY;
+  
+  generate
+    for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux
+      assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH];
+    end  // gen_mesg_mux
+         
+    if (C_NUM_S>1) begin : gen_arbiter
+    
+      /////////////////////////////////////////////////////////////////////////////
+      // Grant a new request when there is none still pending.
+      // If no qualified requests found, de-assert M_VALID.
+      /////////////////////////////////////////////////////////////////////////////
+      
+      assign M_GRANT_ANY = any_grant;
+      assign next_hot = found_prio ? next_prio_hot : next_rr_hot;
+      assign next_enc = found_prio ? next_prio_enc : next_rr_enc;
+      
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          m_valid_i <= 0;
+          s_ready_i <= 0;
+          m_grant_hot_i <= 0;
+          m_grant_enc_i <= 0;
+          any_grant <= 1\'b0;
+          last_rr_hot <= {1\'b1, {C_NUM_S-1{1\'b0}}};
+          grant_rnw <= 1\'b0;
+        end else begin
+          s_ready_i <= 0;
+          if (m_valid_i) begin
+            // Stall 1 cycle after each master-side completion.
+            if (m_aready) begin  // Master-side completion
+              m_valid_i <= 1\'b0;
+              m_grant_hot_i <= 0;
+              any_grant <= 1\'b0;
+            end
+          end else if (any_grant) begin
+            m_valid_i <= 1\'b1;
+            s_ready_i <= m_grant_hot_i;  // Assert S_AW/READY for 1 cycle to complete SI address transfer
+          end else begin
+            if (found_prio | found_rr) begin
+              m_grant_hot_i <= next_hot;
+              m_grant_enc_i <= next_enc;
+              any_grant <= 1\'b1;
+              grant_rnw <= |(rnw & next_hot);
+              if (~found_prio) begin
+                last_rr_hot <= next_rr_hot;
+              end
+            end
+          end
+        end
+      end
+    
+      /////////////////////////////////////////////////////////////////////////////
+      // Fixed Priority arbiter
+      // Selects next request to grant from among inputs with PRIO > 0, if any.
+      /////////////////////////////////////////////////////////////////////////////
+      
+      always @ * begin : ALG_PRIO
+        integer ip;
+        any_prio = 1\'b0;
+        which_prio_hot = 0;        
+        which_prio_enc = 0;    
+        current_highest = 0;    
+        for (ip=0; ip < C_NUM_S; ip=ip+1) begin
+          if (P_PRIO_MASK[ip] & ({1\'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin
+            if (s_avalid[ip]) begin
+              current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];
+              any_prio = 1\'b1;
+              which_prio_hot = 1\'b1 << ip;
+              which_prio_enc = ip;
+            end
+          end   
+        end
+        found_prio = any_prio;
+        next_prio_hot = which_prio_hot;
+        next_prio_enc = which_prio_enc;
+      end
+     
+      /////////////////////////////////////////////////////////////////////////////
+      // Round-robin arbiter
+      // Selects next request to grant from among inputs with PRIO = 0, if any.
+      /////////////////////////////////////////////////////////////////////////////
+      
+      assign valid_rr = ~P_PRIO_MASK & s_avalid;
+      
+      always @ * begin : ALG_RR
+        integer ir, jr, nr;
+        next_rr_hot = 0;
+        for (ir=0;ir<C_NUM_S;ir=ir+1) begin
+          nr = (ir>0) ? (ir-1) : (C_NUM_S-1);
+          carry_rr[ir*C_NUM_S] = last_rr_hot[nr];
+          mask_rr[ir*C_NUM_S] = ~valid_rr[nr];
+          for (jr=1;jr<C_NUM_S;jr=jr+1) begin
+            nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);
+            carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);
+            if (jr < C_NUM_S-1) begin
+              mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];
+            end
+          end   
+          next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];
+        end
+        next_rr_enc = f_hot2enc(next_rr_hot);
+        found_rr = |(next_rr_hot);
+      end
+  
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (""rtl""),
+         .C_RATIO       (C_NUM_S),
+         .C_SEL_WIDTH   (C_NUM_S_LOG),
+         .C_DATA_WIDTH  (C_AMESG_WIDTH)
+        ) si_amesg_mux_inst 
+        (
+         .S   (next_enc),
+         .A   (s_amesg),
+         .O   (amesg_mux),
+         .OE  (1\'b1)
+        ); 
+        
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          m_amesg_i <= 0;
+        end else if (~any_grant) begin
+          m_amesg_i <= amesg_mux;
+        end
+      end
+    
+    end else begin : gen_no_arbiter
+      
+      assign M_GRANT_ANY = m_grant_hot_i;
+
+      always @ (posedge ACLK) begin
+        if (ARESET) begin
+          m_valid_i <= 1\'b0;
+          s_ready_i <= 1\'b0;
+          m_grant_enc_i <= 0;
+          m_grant_hot_i <= 1\'b0;
+          grant_rnw <= 1\'b0;
+        end else begin
+          s_ready_i <= 1\'b0;
+          if (m_valid_i) begin
+            if (m_aready) begin
+              m_valid_i <= 1\'b0;
+              m_grant_hot_i <= 1\'b0;
+            end
+          end else if (m_grant_hot_i) begin
+            m_valid_i <= 1\'b1;
+            s_ready_i[0] <= 1\'b1;  // Assert S_AW/READY for 1 cycle to complete SI address transfer
+          end else if (s_avalid[0]) begin
+            m_grant_hot_i <= 1\'b1;
+            grant_rnw <= rnw[0];
+          end
+        end
+      end
+      
+      always @ (posedge ACLK) begin
+        if (ARESET) begin
+          m_amesg_i <= 0;
+        end else if (~m_grant_hot_i) begin
+          m_amesg_i <= s_amesg;
+        end
+      end
+    
+    end  // gen_arbiter
+  endgenerate
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: addr_arbiter.v
+//
+// Description: 
+//   Instantiates generic priority encoder.
+//   Each request is qualified if its target has not reached its issuing limit.
+//   Muxes mesg and target inputs based on arbitration results.
+//-----------------------------------------------------------------------------
+//
+// Structure:
+//    addr_arbiter
+//      mux_enc
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_addr_arbiter #
+  (
+   parameter         C_FAMILY                         = ""none"", 
+   parameter integer C_NUM_S                = 1, 
+   parameter integer C_NUM_S_LOG                = 1, 
+   parameter integer C_NUM_M               = 1, 
+   parameter integer C_MESG_WIDTH                 = 1, 
+   parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY             = {C_NUM_S{32\'h00000000}}
+                       // Arbitration priority among each SI slot. 
+                       // Higher values indicate higher priority.
+                       // Format: C_NUM_SLAVE_SLOTS{Bit32};
+                       // Range: \'h0-\'hF.
+   )
+  (
+   // Global Signals
+   input  wire                                      ACLK,
+   input  wire                                      ARESET,
+   // Slave Ports
+   input  wire [C_NUM_S*C_MESG_WIDTH-1:0]  S_MESG,
+   input  wire [C_NUM_S*C_NUM_M-1:0]                S_TARGET_HOT,
+   input  wire [C_NUM_S-1:0]                S_VALID,
+   input  wire [C_NUM_S-1:0]                S_VALID_QUAL,
+   output wire [C_NUM_S-1:0]                S_READY,
+   // Master Ports
+   output wire [C_MESG_WIDTH-1:0]                    M_MESG,
+   output wire [C_NUM_M-1:0]                           M_TARGET_HOT,
+   output wire [C_NUM_S_LOG-1:0]                      M_GRANT_ENC,
+   output wire                                        M_VALID,
+   input  wire                                        M_READY,
+   // Sideband input
+   input  wire [C_NUM_M-1:0]                ISSUING_LIMIT
+   );
+   
+  // Generates a mask for all input slots that are priority based
+  function [C_NUM_S-1:0] f_prio_mask
+    (
+      input integer null_arg
+    );
+    reg   [C_NUM_S-1:0]            mask;
+    integer                        i;    
+    begin
+      mask = 0;    
+      for (i=0; i < C_NUM_S; i=i+1) begin
+        mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);
+      end 
+      f_prio_mask = mask;
+    end   
+  endfunction
+  
+  // Convert 16-bit one-hot to 4-bit binary
+  function [3:0] f_hot2enc
+    (
+      input [15:0]  one_hot
+    );
+    begin
+      f_hot2enc[0] = |(one_hot & 16\'b1010101010101010);
+      f_hot2enc[1] = |(one_hot & 16\'b1100110011001100);
+      f_hot2enc[2] = |(one_hot & 16\'b1111000011110000);
+      f_hot2enc[3] = |(one_hot & 16\'b1111111100000000);
+    end
+  endfunction
+
+  localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);
+
+  reg                     m_valid_i;
+  reg [C_NUM_S-1:0]       s_ready_i;
+  reg [C_NUM_S-1:0]       qual_reg;
+  reg [C_NUM_S-1:0]       grant_hot; 
+  reg [C_NUM_S-1:0]       last_rr_hot;
+  reg                     any_grant;
+  reg                     any_prio;
+  reg                     found_prio;
+  reg [C_NUM_S-1:0]       which_prio_hot;
+  reg [C_NUM_S-1:0]       next_prio_hot;
+  reg [C_NUM_S_LOG-1:0]   which_prio_enc;          
+  reg [C_NUM_S_LOG-1:0]   next_prio_enc;    
+  reg [4:0]               current_highest;
+  wire [C_NUM_S-1:0]      valid_rr;
+  reg [15:0]              next_rr_hot;
+  reg [C_NUM_S_LOG-1:0]   next_rr_enc;    
+  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
+  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
+  reg                     found_rr;
+  wire [C_NUM_S-1:0]      next_hot;
+  wire [C_NUM_S_LOG-1:0]  next_enc;    
+  reg                     prio_stall;
+  integer                 i;
+  wire [C_NUM_S-1:0]      valid_qual_i;
+  reg  [C_NUM_S_LOG-1:0]  m_grant_enc_i;
+  reg  [C_NUM_M-1:0]      m_target_hot_i;
+  wire [C_NUM_M-1:0]      m_target_hot_mux;
+  reg  [C_MESG_WIDTH-1:0] m_mesg_i;
+  wire [C_MESG_WIDTH-1:0] m_mesg_mux;
+  genvar                  gen_si;
+
+  assign M_VALID = m_valid_i;
+  assign S_READY = s_ready_i;
+  assign M_GRANT_ENC = m_grant_enc_i;
+  assign M_MESG = m_mesg_i;
+  assign M_TARGET_HOT = m_target_hot_i;
+  
+  generate
+    if (C_NUM_S>1) begin : gen_arbiter
+      
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          qual_reg <= 0;
+        end else begin 
+          qual_reg <= valid_qual_i | ~S_VALID; // Don\'t disqualify when bus not VALID (valid_qual_i would be garbage)
+        end
+      end
+    
+      for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_req_qual
+        assign valid_qual_i[gen_si] = S_VALID_QUAL[gen_si] & (|(S_TARGET_HOT[gen_si*C_NUM_M+:C_NUM_M] & ~ISSUING_LIMIT));
+      end
+    
+      /////////////////////////////////////////////////////////////////////////////
+      // Grant a new request when there is none still pending.
+      // If no qualified requests found, de-assert M_VALID.
+      /////////////////////////////////////////////////////////////////////////////
+      
+      assign next_hot = found_prio ? next_prio_hot : next_rr_hot;
+      assign next_enc = found_prio ? next_prio_enc : next_rr_enc;
+      
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          m_valid_i <= 0;
+          s_ready_i <= 0;
+          grant_hot <= 0;
+          any_grant <= 1\'b0;
+          m_grant_enc_i <= 0;
+          last_rr_hot <= {1\'b1, {C_NUM_S-1{1\'b0}}};
+          m_target_hot_i <= 0;
+        end else begin
+          s_ready_i <= 0;
+          if (m_valid_i) begin
+            // Stall 1 cycle after each master-side completion.
+            if (M_READY) begin  // Master-side completion
+              m_valid_i <= 1\'b0;
+              grant_hot <= 0;
+              any_grant <= 1\'b0;
+            end
+          end else if (any_grant) begin
+            m_valid_i <= 1\'b1;
+            s_ready_i <= grant_hot;  // Assert S_AW/READY for 1 cycle to complete SI address transfer (regardless of M_AREADY)
+          end else begin
+            if ((found_prio | found_rr) & ~prio_stall) begin
+              // Waste 1 cycle and re-arbitrate if target of highest prio hit issuing limit in previous cycle (valid_qual_i).
+              if (|(next_hot & valid_qual_i)) begin  
+                grant_hot <= next_hot;
+                m_grant_enc_i <= next_enc;
+                any_grant <= 1\'b1;
+                if (~found_prio) begin
+                  last_rr_hot <= next_rr_hot;
+                end
+                m_target_hot_i <= m_target_hot_mux;
+              end
+            end
+          end
+        end
+      end
+    
+      /////////////////////////////////////////////////////////////////////////////
+      // Fixed Priority arbiter
+      // Selects next request to grant from among inputs with PRIO > 0, if any.
+      /////////////////////////////////////////////////////////////////////////////
+          
+      always @ * begin : ALG_PRIO
+        integer ip;
+        any_prio = 1\'b0;
+        prio_stall = 1\'b0;
+        which_prio_hot = 0;        
+        which_prio_enc = 0;    
+        current_highest = 0;    
+        for (ip=0; ip < C_NUM_S; ip=ip+1) begin
+          // Disqualify slot if target hit issuing limit (pass to lower prio slot).
+          if (P_PRIO_MASK[ip] & S_VALID[ip] & qual_reg[ip]) begin
+            if ({1\'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest) begin
+              current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];
+              // Stall 1 cycle when highest prio is recovering from SI-side handshake.
+              // (Do not allow lower-prio slot to win arbitration.)
+              if (s_ready_i[ip]) begin
+                any_prio = 1\'b0;
+                prio_stall = 1\'b1;
+                which_prio_hot = 0;
+                which_prio_enc = 0;
+              end else begin
+                any_prio = 1\'b1;
+                which_prio_hot = 1\'b1 << ip;
+                which_prio_enc = ip;
+              end
+            end
+          end   
+        end
+        found_prio = any_prio;
+        next_prio_hot = which_prio_hot;
+        next_prio_enc = which_prio_enc;
+      end
+     
+      /////////////////////////////////////////////////////////////////////////////
+      // Round-robin arbiter
+      // Selects next request to grant from among inputs with PRIO = 0, if any.
+      /////////////////////////////////////////////////////////////////////////////
+      
+      // Disqualify slot if target hit issuing limit 2 or more cycles earlier (pass to next RR slot).
+      // Disqualify for 1 cycle a slot that is recovering from SI-side handshake (s_ready_i),
+      //   and allow arbitration to pass to any other RR requester.
+      assign valid_rr = ~P_PRIO_MASK & S_VALID & ~s_ready_i & qual_reg;
+      
+      always @ * begin : ALG_RR
+        integer ir, jr, nr;
+        next_rr_hot = 0;
+        for (ir=0;ir<C_NUM_S;ir=ir+1) begin
+          nr = (ir>0) ? (ir-1) : (C_NUM_S-1);
+          carry_rr[ir*C_NUM_S] = last_rr_hot[nr];
+          mask_rr[ir*C_NUM_S] = ~valid_rr[nr];
+          for (jr=1;jr<C_NUM_S;jr=jr+1) begin
+            nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);
+            carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);
+            if (jr < C_NUM_S-1) begin
+              mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];
+            end
+          end   
+          next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];
+        end
+        next_rr_enc = f_hot2enc(next_rr_hot);
+        found_rr = |(next_rr_hot);
+      end
+  
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (""rtl""),
+         .C_RATIO       (C_NUM_S),
+         .C_SEL_WIDTH   (C_NUM_S_LOG),
+         .C_DATA_WIDTH  (C_MESG_WIDTH)
+        ) mux_mesg 
+        (
+         .S   (m_grant_enc_i),
+         .A   (S_MESG),
+         .O   (m_mesg_mux),
+         .OE  (1\'b1)
+        ); 
+        
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (""rtl""),
+         .C_RATIO       (C_NUM_S),
+         .C_SEL_WIDTH   (C_NUM_S_LOG),
+         .C_DATA_WIDTH  (C_NUM_M)
+        ) si_amesg_mux_inst 
+        (
+         .S   (next_enc),
+         .A   (S_TARGET_HOT),
+         .O   (m_target_hot_mux),
+         .OE  (1\'b1)
+        ); 
+        
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          m_mesg_i <= 0;
+        end else if (~m_valid_i) begin
+          m_mesg_i <= m_mesg_mux;
+        end
+      end
+    
+    end else begin : gen_no_arbiter
+      
+      assign valid_qual_i = S_VALID_QUAL & |(S_TARGET_HOT & ~ISSUING_LIMIT);
+      
+      always @ (posedge ACLK) begin
+        if (ARESET) begin
+          m_valid_i <= 1\'b0;
+          s_ready_i <= 1\'b0;
+          m_grant_enc_i <= 0;
+        end else begin
+          s_ready_i <= 1\'b0;
+          if (m_valid_i) begin
+            if (M_READY) begin
+              m_valid_i <= 1\'b0;
+            end
+          end else if (S_VALID[0] & valid_qual_i[0] & ~s_ready_i) begin
+            m_valid_i <= 1\'b1;
+            s_ready_i <= 1\'b1;
+            m_target_hot_i <= S_TARGET_HOT;
+          end
+        end
+      end
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          m_mesg_i <= 0;
+        end else if (~m_valid_i) begin
+          m_mesg_i <= S_MESG;
+        end
+      end
+      
+      
+    end  // gen_arbiter
+  endgenerate
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Addr Decoder
+// Each received address is compared to base and high address pairs for each 
+//   of a set of decode targets. 
+// The matching target\'s index (if any) is output combinatorially.
+// If the decode is successful (matches any target), the MATCH output is asserted.
+// For each target, a set of alternative address ranges may be specified.
+// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
+//   alternative address ranges iterate within each target.
+// The alternative range which matches the address is also output as REGION.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   addr_decoder
+//      comparator_static
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_addr_decoder #
+  (
+   parameter         C_FAMILY          = ""none"",
+   parameter integer C_NUM_TARGETS     = 2,  // Number of decode targets = [1:16]
+   parameter integer C_NUM_TARGETS_LOG = 1,  // Log2(C_NUM_TARGETS)
+   parameter integer C_NUM_RANGES      = 1, // Number of alternative ranges that
+                                             //    can match each target [1:16]
+   parameter integer C_ADDR_WIDTH      = 32, // Width of decoder operand and of
+                                             //   each base and high address [2:64]
+   parameter integer C_TARGET_ENC      = 0,  // Enable encoded target output
+   parameter integer C_TARGET_HOT      = 1,  // Enable 1-hot target output
+   parameter integer C_REGION_ENC      = 0,   // Enable REGION output
+   parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1\'b1}}, 
+   parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1\'b0}}, 
+   parameter [C_NUM_TARGETS:0]    C_TARGET_QUAL                 = {C_NUM_TARGETS{1\'b1}},
+                       // Indicates whether each target has connectivity.
+                       // Format: C_NUM_TARGETS{Bit1}.
+   parameter integer   C_RESOLUTION                 = 0,
+                       // Number of low-order ADDR bits that can be ignored when decoding.
+   parameter integer   C_COMPARATOR_THRESHOLD       = 6
+                       // Number of decoded ADDR bits above which will implement comparator_static.
+   )
+  (
+   input  wire [C_ADDR_WIDTH-1:0]      ADDR,        // Decoder input operand
+   output wire [C_NUM_TARGETS-1:0]     TARGET_HOT,  // Target matching address (1-hot)
+   output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC,  // Target matching address (encoded)
+   output wire                         MATCH,       // Decode successful
+   output wire [3:0]                   REGION      // Range within target matching address (encoded)
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  genvar target_cnt;
+  genvar region_cnt;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Function to detect addrs is in the addressable range.
+  // Only compare 4KB page address (ignore low-order 12 bits)
+  function  decode_address;
+    input [C_ADDR_WIDTH-1:0] base, high, addr;
+    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
+    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
+    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
+    reg   [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
+  begin
+    addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
+    base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
+    high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
+    if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
+      decode_address = 1\'b0;
+    end else begin
+      mask  = base_page ^ high_page;
+      if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
+        decode_address = 1\'b1;
+      end else begin
+        decode_address = 1\'b0;
+      end
+    end
+  end
+  endfunction
+  
+  // Generates a binary coded from onehotone encoded
+  function [3:0] f_hot2enc
+    (
+      input [15:0]  one_hot
+    );
+    begin
+      f_hot2enc[0] = |(one_hot & 16\'b1010101010101010);
+      f_hot2enc[1] = |(one_hot & 16\'b1100110011001100);
+      f_hot2enc[2] = |(one_hot & 16\'b1111000011110000);
+      f_hot2enc[3] = |(one_hot & 16\'b1111111100000000);
+    end
+  endfunction
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  wire [C_NUM_TARGETS-1:0]              TARGET_HOT_I;     // Target matching address (1-hot).
+  wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT;      // For address hit (1-hot).
+  wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG;  // For address hit (1-hot).
+  wire [C_NUM_RANGES-1:0]               REGION_HOT;       // Reginon matching address (1-hot).
+  wire [3:0]                            TARGET_ENC_I;     // Internal version of encoded hit. 
+  /////////////////////////////////////////////////////////////////////////////
+  // Generate detection per region per target.
+  generate
+    for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
+      for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
+        // Detect if this is an address hit (including used region decoding).
+        if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
+          if (C_TARGET_QUAL[target_cnt] &&
+              ((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
+               (C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
+            generic_baseblocks_v2_1_0_comparator_static #
+            (
+            .C_FAMILY(""rtl""),
+            .C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
+            .C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
+            ) addr_decode_comparator
+            (
+            .CIN(1\'b1),
+            .A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
+              ~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
+                C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
+            .COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
+            );
+          end else begin : gen_null_range
+            assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1\'b0;
+          end
+        end else begin : gen_no_comparator_static
+          assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ? 
+                                    decode_address(
+                                      C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
+                                      C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
+                                      ADDR)
+                                    : 1\'b0;
+        end  // gen_comparator_static
+        assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
+      end  // gen_region
+      
+      // All regions are non-overlapping
+      // => Or all the region detections for this target to determine if it is a hit.
+      assign TARGET_HOT_I[target_cnt]  = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
+    end  // gen_target
+    
+    for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region_or
+      assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
+    end  // gen_region_or
+  endgenerate
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // All regions are non-overlapping
+  // => Or all the target hit detections if it is a match.
+  assign MATCH = | TARGET_HOT_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Assign conditional onehot target output signal.
+  generate
+    if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
+      assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
+    end else begin : NO_TARGET_ONEHOT
+      assign TARGET_HOT = {C_NUM_TARGETS{1\'b0}};
+    end
+  endgenerate
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Assign conditional encoded target output signal.
+  generate
+    if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
+      assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
+      assign TARGET_ENC   = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
+    end else begin : NO_TARGET_ENCODED
+      assign TARGET_ENC = {C_NUM_TARGETS_LOG{1\'b0}};
+    end
+  endgenerate
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Assign conditional encoded region output signal.
+  generate
+    if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
+      assign REGION = f_hot2enc(REGION_HOT);
+    end else begin : NO_REGION_ENCODED
+      assign REGION = 4\'b0;
+    end
+  endgenerate
+  
+  
+endmodule
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Round-Robin Arbiter for R and B channel responses
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//    arbiter_resp
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_arbiter_resp #
+  (
+   parameter         C_FAMILY       = ""none"",
+   parameter integer C_NUM_S        = 4,      // Number of requesting Slave ports = [2:16]
+   parameter integer C_NUM_S_LOG    = 2,      // Log2(C_NUM_S)
+   parameter integer C_GRANT_ENC    = 0,      // Enable encoded grant output
+   parameter integer C_GRANT_HOT    = 1       // Enable 1-hot grant output
+   )
+  (
+   // Global Inputs
+   input  wire                     ACLK,
+   input  wire                     ARESET,
+   // Slave  Ports
+   input  wire [C_NUM_S-1:0]       S_VALID,      // Request from each slave
+   output wire [C_NUM_S-1:0]       S_READY,      // Grant response to each slave
+   // Master Ports
+   output wire [C_NUM_S_LOG-1:0]   M_GRANT_ENC,  // Granted slave index (encoded)
+   output wire [C_NUM_S-1:0]       M_GRANT_HOT,  // Granted slave index (1-hot)
+   output wire                     M_VALID,      // Grant event
+   input  wire                     M_READY
+   );
+
+  // Generates a binary coded from onehotone encoded
+  function [4:0] f_hot2enc
+    (
+      input [16:0]  one_hot
+    );
+    begin
+      f_hot2enc[0] = |(one_hot & 17\'b01010101010101010);
+      f_hot2enc[1] = |(one_hot & 17\'b01100110011001100);
+      f_hot2enc[2] = |(one_hot & 17\'b01111000011110000);
+      f_hot2enc[3] = |(one_hot & 17\'b01111111100000000);
+      f_hot2enc[4] = |(one_hot & 17\'b10000000000000000);
+    end
+  endfunction
+
+  (* use_clock_enable = ""yes"" *)
+  reg [C_NUM_S-1:0]      chosen;
+  
+  wire [C_NUM_S-1:0]     grant_hot; 
+  wire                   master_selected; 
+  wire                   active_master;
+  wire                   need_arbitration;
+  wire                   m_valid_i;
+  wire [C_NUM_S-1:0]     s_ready_i;
+  wire                   access_done;
+  reg [C_NUM_S-1:0]      last_rr_hot;
+  wire [C_NUM_S-1:0]     valid_rr;
+  reg [C_NUM_S-1:0]      next_rr_hot;
+  reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
+  reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
+  integer                 i;
+  integer                 j;
+  integer                 n;
+  
+  /////////////////////////////////////////////////////////////////////////////
+  //   
+  // Implementation of the arbiter outputs independant of arbitration
+  //
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Mask the current requests with the chosen master
+  assign grant_hot        = chosen & S_VALID;
+
+  // See if we have a selected master
+  assign master_selected  = |grant_hot[0+:C_NUM_S];
+
+  // See if we have current requests
+  assign active_master    = |S_VALID;
+
+  // Access is completed
+  assign access_done = m_valid_i & M_READY;
+  
+  // Need to handle if we drive S_ready combinatorial and without an IDLE state
+
+  // Drive S_READY on the master who has been chosen when we get a M_READY
+  assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
+
+  // Drive M_VALID if we have a selected master
+  assign m_valid_i = master_selected;
+                
+  // If we have request and not a selected master, we need to arbitrate a new chosen 
+  assign need_arbitration = (active_master & ~master_selected) | access_done;
+
+  // need internal signals of the output signals
+  assign M_VALID = m_valid_i;
+  assign S_READY = s_ready_i;
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Assign conditional onehot target output signal.
+  assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1\'b0}};
+  /////////////////////////////////////////////////////////////////////////////
+  // Assign conditional encoded target output signal.
+  assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1\'b0}};
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Select a new chosen when we need to arbitrate
+  // If we don\'t have a new chosen, keep the old one since it\'s a good chance
+  // that it will do another request
+  always @(posedge ACLK)
+    begin
+      if (ARESET) begin
+        chosen <= {C_NUM_S{1\'b0}};
+        last_rr_hot <= {1\'b1, {C_NUM_S-1{1\'b0}}};
+      end else if (need_arbitration) begin
+        chosen <= next_rr_hot;   
+        if (|next_rr_hot) last_rr_hot <= next_rr_hot;
+      end
+    end
+
+  assign valid_rr =  S_VALID;
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Round-robin arbiter
+  // Selects next request to grant from among inputs with PRIO = 0, if any.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  always @ * begin
+    next_rr_hot = 0;
+    for (i=0;i<C_NUM_S;i=i+1) begin
+      n = (i>0) ? (i-1) : (C_NUM_S-1);
+      carry_rr[i*C_NUM_S] = last_rr_hot[n];
+      mask_rr[i*C_NUM_S] = ~valid_rr[n];
+      for (j=1;j<C_NUM_S;j=j+1) begin
+        n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
+        carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
+        if (j < C_NUM_S-1) begin
+          mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
+        end
+      end   
+      next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
+    end
+  end
+  
+endmodule
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: crossbar_sasd.v
+//
+// Description: 
+//   This module is a M-master to N-slave AXI axi_crossbar_v2_1_12_crossbar switch.
+//   Single transaction issuing, single arbiter (both W&R), single data pathways.
+//   The interface of this module consists of a vectored slave and master interface
+//     in which all slots are sized and synchronized to the native width and clock 
+//     of the interconnect, and are all AXI4 protocol.
+//   All width, clock and protocol conversions are done outside this block, as are
+//     any pipeline registers or data FIFOs.
+//   This module contains all arbitration, decoders and channel multiple'b'xing logic.
+//     It also contains the diagnostic registers and control interface.
+//
+//--------------------------------------------------------------------------
+//
+// Structure:
+//    crossbar_sasd
+//      addr_arbiter_sasd
+//        mux_enc
+//      addr_decoder
+//        comparator_static
+//      splitter
+//      mux_enc
+//      axic_register_slice
+//      decerr_slave
+//      
+//-----------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_crossbar_sasd #
+  (
+   parameter         C_FAMILY                       = ""none"", 
+   parameter integer C_NUM_SLAVE_SLOTS              =   1, 
+   parameter integer C_NUM_MASTER_SLOTS             =   1, 
+   parameter integer C_NUM_ADDR_RANGES              = 1,
+   parameter integer C_AXI_ID_WIDTH                   = 1, 
+   parameter integer C_AXI_ADDR_WIDTH                 = 32, 
+   parameter integer C_AXI_DATA_WIDTH = 32, 
+   parameter integer C_AXI_PROTOCOL                 = 0, 
+   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b1}}, 
+   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b0}}, 
+   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1\'b0}},
+   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1\'b0}},
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+   parameter integer C_AXI_ARUSER_WIDTH               = 1,
+   parameter integer C_AXI_WUSER_WIDTH                = 1,
+   parameter integer C_AXI_RUSER_WIDTH                = 1,
+   parameter integer C_AXI_BUSER_WIDTH                = 1,
+   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE           = {C_NUM_SLAVE_SLOTS{1\'b1}}, 
+   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ            = {C_NUM_SLAVE_SLOTS{1\'b1}}, 
+   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE           = {C_NUM_MASTER_SLOTS{1\'b1}}, 
+   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ            = {C_NUM_MASTER_SLOTS{1\'b1}}, 
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = {C_NUM_SLAVE_SLOTS{32\'h00000000}},
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = {C_NUM_MASTER_SLOTS{32\'h00000000}},
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32\'h00000000}},
+   parameter integer C_R_REGISTER               = 0,
+   parameter integer C_RANGE_CHECK                    = 0,
+   parameter integer C_ADDR_DECODE                    = 0,
+   parameter integer C_DEBUG              = 1
+   )
+  (
+   // Global Signals
+   input  wire                                                    ACLK,
+   input  wire                                                    ARESETN,
+   // Slave Interface Write Address Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_AWID,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_AWLEN,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWSIZE,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWBURST,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWLOCK,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWCACHE,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWPROT,
+//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWREGION,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWQOS,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWVALID,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWREADY,
+   // Slave Interface Write Data Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_WID,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_WDATA,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]   S_AXI_WSTRB,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WLAST,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WVALID,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WREADY,
+   // Slave Interface Write Response Ports
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_BID,
+   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_BRESP,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BVALID,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BREADY,
+   // Slave Interface Read Address Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_ARID,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,
+   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_ARLEN,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARSIZE,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARBURST,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARLOCK,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARCACHE,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARPROT,
+//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARREGION,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARQOS,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARVALID,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARREADY,
+   // Slave Interface Read Data Ports
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_RID,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA,
+   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_RRESP,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RLAST,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RVALID,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RREADY,
+   // Master Interface Write Address Port
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_AWID,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_AWADDR,
+   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_AWLEN,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWSIZE,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWBURST,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWLOCK,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWCACHE,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWPROT,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWREGION,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWQOS,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        M_AXI_AWUSER,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWVALID,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWREADY,
+   // Master Interface Write Data Ports
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_WID,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_WDATA,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]  M_AXI_WSTRB,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WLAST,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         M_AXI_WUSER,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WVALID,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WREADY,
+   // Master Interface Write Response Ports
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_BID,  // Unused
+   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_BRESP,
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BVALID,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BREADY,
+   // Master Interface Read Address Port
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_ARID,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_ARADDR,
+   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_ARLEN,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARSIZE,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARBURST,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARLOCK,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARCACHE,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARPROT,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARREGION,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARQOS,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        M_AXI_ARUSER,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARVALID,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARREADY,
+   // Master Interface Read Data Ports
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_RID,  // Unused
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_RDATA,
+   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_RRESP,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RLAST,
+   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]         M_AXI_RUSER,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RVALID,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RREADY
+   );
+   
+  localparam integer  P_AXI4 = 0;
+  localparam integer  P_AXI3 = 1;
+  localparam integer  P_AXILITE = 2;
+  localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS;
+  localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1;
+  localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1;
+  localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1;
+  localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH;
+  localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;
+  localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4;
+  localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;
+  localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH;
+  localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;
+  localparam [31:0]   P_AXILITE_ERRMODE = 32\'h00000001;
+  localparam integer P_NONSECURE_BIT = 1; 
+  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE);  // Mask of secure MI-slots
+  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0);  // Mask of axilite rule-check MI-slots
+  localparam [1:0]   P_FIXED = 2\'b00;
+  localparam integer P_BYPASS = 0;
+  localparam integer P_LIGHTWT = 7;
+  localparam integer P_FULLY_REG = 1;
+  localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ?  // ""Automatic"" reg-slice
+        (C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) :  // Bypass if no R-channel mux
+        C_R_REGISTER;
+  localparam P_DECERR = 2\'b11;
+
+  //---------------------------------------------------------------------------
+  // Functions
+  //---------------------------------------------------------------------------
+  // Ceiling of log2(x)
+  function integer f_ceil_log2
+    (
+     input integer x
+     );
+    integer acc;
+    begin
+      acc=0;
+      while ((2**acc) < x)
+        acc = acc + 1;
+      f_ceil_log2 = acc;
+    end
+  endfunction
+
+  // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value
+  //   only for end-point SI-slots
+  function [C_AXI_ID_WIDTH-1:0] f_extend_ID
+    (
+     input [C_AXI_ID_WIDTH-1:0] s_id,
+     input integer slot
+     );
+    begin
+      f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));
+    end
+  endfunction
+
+  // Convert Bit32 vector of range [0,1] to Bit1 vector on MI
+  function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi
+    (input [C_NUM_MASTER_SLOTS*32-1:0] vec32);
+    integer mi;
+    begin
+      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
+        f_bit32to1_mi[mi] = vec32[mi*32];
+      end
+    end
+  endfunction
+
+  // AxiLite error-checking mask (on MI)      
+  function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite
+    (
+      input integer null_arg
+    );
+    integer mi;
+    begin
+      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
+        f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
+      end
+    end
+  endfunction
+
+  genvar gen_si_slot;
+  genvar gen_mi_slot;
+  wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0]                      si_awmesg          ;
+  wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0]                      si_armesg          ;
+  wire [P_AMESG_WIDTH-1:0]                                        aa_amesg         ;
+  wire [C_AXI_ID_WIDTH-1:0]                                       mi_aid            ;
+  wire [C_AXI_ADDR_WIDTH-1:0]                                     mi_aaddr          ;
+  wire [8-1:0]                                                    mi_alen           ;
+  wire [3-1:0]                                                    mi_asize          ;
+  wire [2-1:0]                                                    mi_alock          ;
+  wire [3-1:0]                                                    mi_aprot          ;
+  wire [2-1:0]                                                    mi_aburst        ;
+  wire [4-1:0]                                                    mi_acache        ;
+  wire [4-1:0]                                                    mi_aregion        ;
+  wire [4-1:0]                                                    mi_aqos        ;
+  wire [P_AXI_AUSER_WIDTH-1:0]                                    mi_auser        ;
+  wire [4-1:0]                                                    target_region        ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  aa_grant_hot     ;
+  wire [P_NUM_SLAVE_SLOTS_LOG-1:0]                                  aa_grant_enc     ;
+  wire                                                            aa_grant_rnw ;
+  wire                                                            aa_grant_any ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                                   target_mi_hot    ;
+  wire [P_NUM_MASTER_SLOTS_LOG-1:0]                                   target_mi_enc    ;
+  reg  [P_NUM_MASTER_SLOTS_DE-1:0]                               m_atarget_hot    ;
+  reg  [P_NUM_MASTER_SLOTS_DE_LOG-1:0]                               m_atarget_enc    ;
+  wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0]                               m_atarget_enc_comb    ;
+  wire                                                            match;
+  wire                                                            any_error         ;
+  wire [7:0]                                                      m_aerror_i         ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_awvalid            ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_awready            ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_arvalid            ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_arready            ;
+  wire                                                            aa_awvalid         ;
+  wire                                                            aa_awready         ;
+  wire                                                            aa_arvalid         ;
+  wire                                                            aa_arready         ;
+  wire                                                            mi_awvalid_en;
+  wire                                                            mi_awready_mux;
+  wire                                                            mi_arvalid_en;
+  wire                                                            mi_arready_mux;
+  wire                                                            w_transfer_en;
+  wire                                                            w_complete_mux;
+  wire                                                            b_transfer_en;
+  wire                                                            b_complete_mux;
+  wire                                                            r_transfer_en;
+  wire                                                            r_complete_mux;
+  wire                                                            target_secure;
+  wire                                                            target_write;
+  wire                                                            target_read;
+  wire                                                            target_axilite;
+  
+  wire [P_BMESG_WIDTH-1:0]                                        si_bmesg           ;
+  wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0]                 mi_bmesg           ;
+  wire [P_NUM_MASTER_SLOTS_DE*2-1:0]                             mi_bresp           ;
+  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0]             mi_buser           ;
+  wire [2-1:0]                                                    si_bresp           ;
+  wire [C_AXI_BUSER_WIDTH-1:0]                                    si_buser           ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_bvalid          ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_bready          ;
+  wire                                                            aa_bvalid          ;
+  wire                                                            aa_bready         ;
+  wire                                                            si_bready         ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_bvalid;
+  
+  wire [P_RMESG_WIDTH-1:0]                                        aa_rmesg           ;
+  wire [P_RMESG_WIDTH-1:0]                                        sr_rmesg           ;
+  wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0]                 mi_rmesg           ;
+  wire [P_NUM_MASTER_SLOTS_DE*2-1:0]                             mi_rresp           ;
+  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0]             mi_ruser           ;
+  wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0]          mi_rdata              ;
+  wire [P_NUM_MASTER_SLOTS_DE*1-1:0]                             mi_rlast              ;
+  wire [2-1:0]                                                    si_rresp           ;
+  wire [C_AXI_RUSER_WIDTH-1:0]                                    si_ruser           ;
+  wire [C_AXI_DATA_WIDTH-1:0]                                 si_rdata              ;
+  wire                                                            si_rlast              ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_rvalid          ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_rready          ;
+  wire                                                            aa_rvalid          ;
+  wire                                                            aa_rready         ;
+  wire                                                            sr_rvalid          ;
+  wire                                                            si_rready         ;
+  wire                                                            sr_rready         ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_rvalid;
+  
+  wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0]                      si_wmesg           ;
+  wire [P_WMESG_WIDTH-1:0]                                        mi_wmesg           ;
+  wire [C_AXI_ID_WIDTH-1:0]                                    mi_wid              ;
+  wire [C_AXI_DATA_WIDTH-1:0]                            mi_wdata              ;
+  wire [C_AXI_DATA_WIDTH/8-1:0]                          mi_wstrb              ;
+  wire [C_AXI_WUSER_WIDTH-1:0]                                    mi_wuser              ;
+  wire [1-1:0]                                                    mi_wlast              ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_wvalid          ;
+  wire [P_NUM_MASTER_SLOTS_DE-1:0]                             mi_wready          ;
+  wire                                                            aa_wvalid          ;
+  wire                                                            aa_wready         ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                                    si_wready;
+  
+  reg  [7:0]                                                      debug_r_beat_cnt_i;
+  reg  [7:0]                                                      debug_w_beat_cnt_i;
+  reg  [7:0]                                                      debug_aw_trans_seq_i;
+  reg  [7:0]                                                      debug_ar_trans_seq_i;
+
+  reg aresetn_d = 1\'b0; // Reset delay register
+  always @(posedge ACLK) begin
+    if (~ARESETN) begin
+      aresetn_d <= 1\'b0;
+    end else begin
+      aresetn_d <= ARESETN;
+    end
+  end
+  wire reset;
+  assign reset = ~aresetn_d;
+
+  generate
+    axi_crossbar_v2_1_12_addr_arbiter_sasd #
+      (
+       .C_FAMILY                (C_FAMILY),
+       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),
+       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),
+       .C_AMESG_WIDTH            (P_AMESG_WIDTH),
+       .C_GRANT_ENC             (1),
+       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)
+       )
+      addr_arbiter_inst
+        (
+         .ACLK                  (ACLK),
+         .ARESET                (reset),
+         // Vector of SI-side AW command request inputs
+         .S_AWMESG                (si_awmesg),
+         .S_ARMESG                (si_armesg),
+         .S_AWVALID               (S_AXI_AWVALID),
+         .S_AWREADY               (S_AXI_AWREADY),
+         .S_ARVALID               (S_AXI_ARVALID),
+         .S_ARREADY               (S_AXI_ARREADY),
+         .M_GRANT_ENC           (aa_grant_enc),
+         .M_GRANT_HOT           (aa_grant_hot),  // SI-slot 1-hot mask of granted command
+         .M_GRANT_ANY             (aa_grant_any),
+         .M_GRANT_RNW             (aa_grant_rnw),
+         .M_AMESG                (aa_amesg),  // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID.
+         .M_AWVALID               (aa_awvalid),
+         .M_AWREADY               (aa_awready),
+         .M_ARVALID               (aa_arvalid),
+         .M_ARREADY               (aa_arready)
+         );
+
+    if (C_ADDR_DECODE) begin : gen_addr_decoder
+      axi_crossbar_v2_1_12_addr_decoder #
+        (
+          .C_FAMILY          (C_FAMILY),
+          .C_NUM_TARGETS     (C_NUM_MASTER_SLOTS),
+          .C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG),
+          .C_NUM_RANGES      (C_NUM_ADDR_RANGES),
+          .C_ADDR_WIDTH      (C_AXI_ADDR_WIDTH),
+          .C_TARGET_ENC      (1),
+          .C_TARGET_HOT      (1),
+          .C_REGION_ENC      (1),
+          .C_BASE_ADDR      (C_M_AXI_BASE_ADDR),
+          .C_HIGH_ADDR      (C_M_AXI_HIGH_ADDR),
+          .C_TARGET_QUAL     ({C_NUM_MASTER_SLOTS{1\'b1}}),
+          .C_RESOLUTION      (2)
+        ) 
+        addr_decoder_inst 
+        (
+          .ADDR             (mi_aaddr),        
+          .TARGET_HOT       (target_mi_hot),  
+          .TARGET_ENC       (target_mi_enc),  
+          .MATCH            (match),       
+          .REGION           (target_region)      
+        );
+    end else begin : gen_no_addr_decoder
+      assign target_mi_hot = 1;
+      assign match = 1\'b1;
+      assign target_region = 4\'b0000;
+    end  // gen_addr_decoder
+    
+    // AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion.
+    axi_crossbar_v2_1_12_splitter #  
+      (
+        .C_NUM_M                (3)
+      )
+      splitter_aw
+      (
+         .ACLK                  (ACLK),
+         .ARESET                (reset),
+         .S_VALID              (aa_awvalid),
+         .S_READY              (aa_awready),
+         .M_VALID              ({mi_awvalid_en, w_transfer_en, b_transfer_en}),
+         .M_READY              ({mi_awready_mux, w_complete_mux, b_complete_mux})
+      );
+    
+    // AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion.
+    axi_crossbar_v2_1_12_splitter #  
+      (
+        .C_NUM_M                (2)
+      )
+      splitter_ar
+      (
+         .ACLK                  (ACLK),
+         .ARESET                (reset),
+         .S_VALID              (aa_arvalid),
+         .S_READY              (aa_arready),
+         .M_VALID              ({mi_arvalid_en, r_transfer_en}),
+         .M_READY              ({mi_arready_mux, r_complete_mux})
+      );
+    
+    assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
+    assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE);
+    assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ);
+    assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK);
+    
+    assign any_error = C_RANGE_CHECK && (m_aerror_i != 0);             // DECERR if error-detection enabled and any error condition.
+    assign m_aerror_i[0] = ~match;                                     // Invalid target address
+    assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation
+    assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) || 
+      (mi_asize[1:0] == 2\'b11) || (mi_asize[2] == 1\'b1));              // AxiLite access violation
+    assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) ||
+      (aa_grant_rnw && ~target_read);                                  // R/W direction unsupported by target
+    assign m_aerror_i[7:4] = 4\'b0000;                                     // Reserved
+    assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc;  // Select MI slot or decerr_slave
+      
+    always @(posedge ACLK) begin
+      if (reset) begin
+        m_atarget_hot <= 0;
+        m_atarget_enc <= 0;
+      end else begin
+        m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1\'b1, {C_NUM_MASTER_SLOTS{1\'b0}}} : {1\'b0, target_mi_hot});  // Select MI slot or decerr_slave
+        m_atarget_enc <= m_atarget_enc_comb;
+      end
+    end
+    
+    // Receive AWREADY from targeted MI.
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),
+       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),
+       .C_DATA_WIDTH  (1)
+      ) mi_awready_mux_inst 
+      (
+       .S   (m_atarget_enc),
+       .A   (mi_awready),
+       .O   (mi_awready_mux),
+       .OE  (mi_awvalid_en)
+      ); 
+      
+    // Receive ARREADY from targeted MI.
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),
+       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),
+       .C_DATA_WIDTH  (1)
+      ) mi_arready_mux_inst 
+      (
+       .S   (m_atarget_enc),
+       .A   (mi_arready),
+       .O   (mi_arready_mux),
+       .OE  (mi_arvalid_en)
+      ); 
+      
+    assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}};  // Assert AWVALID on targeted MI.
+    assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}};  // Assert ARVALID on targeted MI.
+    assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS];  // Propagate to MI slots.
+    assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS];  // Propagate to MI slots.
+    assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;  // Copy from MI slots.
+    assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;  // Copy from MI slots.
+    
+    // Receive WREADY from targeted MI.
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),
+       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),
+       .C_DATA_WIDTH  (1)
+      ) mi_wready_mux_inst 
+      (
+       .S   (m_atarget_enc),
+       .A   (mi_wready),
+       .O   (aa_wready),
+       .OE  (w_transfer_en)
+      ); 
+      
+    assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}};  // Assert WVALID on targeted MI.
+    assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}};  // Assert WREADY on granted SI.
+    assign S_AXI_WREADY = si_wready;
+    assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast;  // W burst complete on on designated SI/MI.
+    
+    // Receive RREADY from granted SI.
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (C_NUM_SLAVE_SLOTS),
+       .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),
+       .C_DATA_WIDTH  (1)
+      ) si_rready_mux_inst 
+      (
+       .S   (aa_grant_enc),
+       .A   (S_AXI_RREADY),
+       .O   (si_rready),
+       .OE  (r_transfer_en)
+      ); 
+      
+    assign sr_rready = si_rready & r_transfer_en;
+    assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}};  // Assert RREADY on targeted MI.
+    assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}};  // Assert RVALID on granted SI.
+    assign S_AXI_RVALID = si_rvalid;
+    assign r_complete_mux = sr_rready & sr_rvalid & si_rlast;  // R burst complete on on designated SI/MI.
+    
+    // Receive BREADY from granted SI.
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (C_NUM_SLAVE_SLOTS),
+       .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),
+       .C_DATA_WIDTH  (1)
+      ) si_bready_mux_inst 
+      (
+       .S   (aa_grant_enc),
+       .A   (S_AXI_BREADY),
+       .O   (si_bready),
+       .OE  (b_transfer_en)
+      ); 
+      
+    assign aa_bready = si_bready & b_transfer_en;
+    assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}};  // Assert BREADY on targeted MI.
+    assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}};  // Assert BVALID on granted SI.
+    assign S_AXI_BVALID = si_bvalid;
+    assign b_complete_mux = aa_bready & aa_bvalid;  // B transfer complete on on designated SI/MI.
+    
+    for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg
+      assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = {  // Concatenate from MSB to LSB
+        4\'b0000,
+//        S_AXI_ARREGION[gen_si_slot*4+:4],
+        S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH],
+        S_AXI_ARQOS[gen_si_slot*4+:4],
+        S_AXI_ARCACHE[gen_si_slot*4+:4],
+        S_AXI_ARBURST[gen_si_slot*2+:2],
+        S_AXI_ARPROT[gen_si_slot*3+:3],
+        S_AXI_ARLOCK[gen_si_slot*2+:2],
+        S_AXI_ARSIZE[gen_si_slot*3+:3],
+        S_AXI_ARLEN[gen_si_slot*8+:8],
+        S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],
+        f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot)
+        };
+      assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = {  // Concatenate from MSB to LSB
+        4\'b0000,
+//        S_AXI_AWREGION[gen_si_slot*4+:4],
+        S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH],
+        S_AXI_AWQOS[gen_si_slot*4+:4],
+        S_AXI_AWCACHE[gen_si_slot*4+:4],
+        S_AXI_AWBURST[gen_si_slot*2+:2],
+        S_AXI_AWPROT[gen_si_slot*3+:3],
+        S_AXI_AWLOCK[gen_si_slot*2+:2],
+        S_AXI_AWSIZE[gen_si_slot*3+:3],
+        S_AXI_AWLEN[gen_si_slot*8+:8],
+        S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],
+        f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)
+        };
+    end  // gen_si_amesg
+    
+    assign mi_aid        = aa_amesg[0 +: C_AXI_ID_WIDTH];
+    assign mi_aaddr      = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH];
+    assign mi_alen       = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8];
+    assign mi_asize      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3];
+    assign mi_alock      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2];
+    assign mi_aprot      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3];
+    assign mi_aburst     = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2];
+    assign mi_acache     = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4];
+    assign mi_aqos       = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4];
+    assign mi_auser      = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH];
+    assign mi_aregion    = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4];
+      
+    // Broadcast AW transfer payload to all MI-slots
+    assign M_AXI_AWID        = {C_NUM_MASTER_SLOTS{mi_aid}};
+    assign M_AXI_AWADDR      = {C_NUM_MASTER_SLOTS{mi_aaddr}};
+    assign M_AXI_AWLEN       = {C_NUM_MASTER_SLOTS{mi_alen }};
+    assign M_AXI_AWSIZE      = {C_NUM_MASTER_SLOTS{mi_asize}};
+    assign M_AXI_AWLOCK      = {C_NUM_MASTER_SLOTS{mi_alock}};
+    assign M_AXI_AWPROT      = {C_NUM_MASTER_SLOTS{mi_aprot}};
+    assign M_AXI_AWREGION    = {C_NUM_MASTER_SLOTS{mi_aregion}};
+    assign M_AXI_AWBURST     = {C_NUM_MASTER_SLOTS{mi_aburst}};
+    assign M_AXI_AWCACHE     = {C_NUM_MASTER_SLOTS{mi_acache}};
+    assign M_AXI_AWQOS       = {C_NUM_MASTER_SLOTS{mi_aqos  }};
+    assign M_AXI_AWUSER      = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }};
+    
+    // Broadcast AR transfer payload to all MI-slots
+    assign M_AXI_ARID        = {C_NUM_MASTER_SLOTS{mi_aid}};
+    assign M_AXI_ARADDR      = {C_NUM_MASTER_SLOTS{mi_aaddr}};                        
+    assign M_AXI_ARLEN       = {C_NUM_MASTER_SLOTS{mi_alen }};                        
+    assign M_AXI_ARSIZE      = {C_NUM_MASTER_SLOTS{mi_asize}};                        
+    assign M_AXI_ARLOCK      = {C_NUM_MASTER_SLOTS{mi_alock}};                        
+    assign M_AXI_ARPROT      = {C_NUM_MASTER_SLOTS{mi_aprot}};                        
+    assign M_AXI_ARREGION    = {C_NUM_MASTER_SLOTS{mi_aregion}};                          
+    assign M_AXI_ARBURST     = {C_NUM_MASTER_SLOTS{mi_aburst}};                       
+    assign M_AXI_ARCACHE     = {C_NUM_MASTER_SLOTS{mi_acache}};                       
+    assign M_AXI_ARQOS       = {C_NUM_MASTER_SLOTS{mi_aqos  }};                       
+    assign M_AXI_ARUSER      = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }};
+    
+    // W-channel MI handshakes
+    assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];
+    assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;
+    // Broadcast W transfer payload to all MI-slots
+    assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}};
+    assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}};
+    assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}};
+    assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}};
+    assign M_AXI_WID =   {C_NUM_MASTER_SLOTS{mi_wid}};
+    
+    // Broadcast R transfer payload to all SI-slots
+    assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}};
+    assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}};
+    assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}};
+    assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}};
+    assign S_AXI_RID =   {C_NUM_SLAVE_SLOTS{mi_aid}};
+    
+    // Broadcast B transfer payload to all SI-slots
+    assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}};
+    assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}};
+    assign S_AXI_BID =   {C_NUM_SLAVE_SLOTS{mi_aid}};
+    
+    if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
+      // SI WVALID mux.
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (""rtl""),
+         .C_RATIO       (C_NUM_SLAVE_SLOTS),
+         .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),
+         .C_DATA_WIDTH  (1)
+        ) si_w_valid_mux_inst 
+        (
+         .S   (aa_grant_enc),
+         .A   (S_AXI_WVALID),
+         .O   (aa_wvalid),
+         .OE  (w_transfer_en)
+        ); 
+      
+      // SI W-channel payload mux
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (""rtl""),
+         .C_RATIO       (C_NUM_SLAVE_SLOTS),
+         .C_SEL_WIDTH   (P_NUM_SLAVE_SLOTS_LOG),
+         .C_DATA_WIDTH  (P_WMESG_WIDTH)
+        ) si_w_payload_mux_inst 
+        (
+         .S   (aa_grant_enc),
+         .A   (si_wmesg),
+         .O   (mi_wmesg),
+         .OE  (1\'b1)
+        ); 
+        
+      for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg
+        assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = {  // Concatenate from MSB to LSB
+          ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1\'b0),
+          S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],
+          S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],
+          S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
+          S_AXI_WLAST[gen_si_slot*1+:1]
+        };
+      end  // gen_wmesg
+      
+      assign mi_wlast = mi_wmesg[0];
+      assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH];
+      assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];
+      assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];
+      assign mi_wid =   mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];
+    end else begin : gen_no_wmux
+      assign aa_wvalid = w_transfer_en & S_AXI_WVALID;
+      assign mi_wlast  = S_AXI_WLAST;
+      assign mi_wdata  = S_AXI_WDATA;
+      assign mi_wstrb  = S_AXI_WSTRB;
+      assign mi_wuser  = S_AXI_WUSER;
+      assign mi_wid =    S_AXI_WID;
+    end  // gen_wmux
+    
+    // Receive RVALID from targeted MI.
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),
+       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),
+       .C_DATA_WIDTH  (1)
+      ) mi_rvalid_mux_inst 
+      (
+       .S   (m_atarget_enc),
+       .A   (mi_rvalid),
+       .O   (aa_rvalid),
+       .OE  (r_transfer_en)
+      ); 
+      
+    // MI R-channel payload mux
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),
+       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),
+       .C_DATA_WIDTH  (P_RMESG_WIDTH)
+      ) mi_rmesg_mux_inst 
+      (
+       .S   (m_atarget_enc),
+       .A   (mi_rmesg),
+       .O   (aa_rmesg),
+       .OE  (1\'b1)
+      ); 
+      
+    axi_register_slice_v2_1_11_axic_register_slice #
+      (
+       .C_FAMILY (C_FAMILY),
+       .C_DATA_WIDTH (P_RMESG_WIDTH),
+       .C_REG_CONFIG (P_R_REG_CONFIG)
+       )
+      reg_slice_r
+      (
+       // System Signals
+       .ACLK(ACLK),
+       .ARESET(reset),
+
+       // Slave side
+       .S_PAYLOAD_DATA(aa_rmesg),
+       .S_VALID(aa_rvalid),
+       .S_READY(aa_rready),
+
+       // Master side
+       .M_PAYLOAD_DATA(sr_rmesg),
+       .M_VALID(sr_rvalid),
+       .M_READY(sr_rready)
+       );
+
+    assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; 
+    assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; 
+    assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;
+    assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;
+    assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;
+    assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];
+    
+    for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg
+      assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = {  // Concatenate from MSB to LSB
+        mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],
+        mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
+        mi_rresp[gen_mi_slot*2+:2],
+        mi_rlast[gen_mi_slot*1+:1]
+      };
+    end  // gen_rmesg
+    
+    assign si_rlast = sr_rmesg[0];
+    assign si_rresp = sr_rmesg[1 +: 2];
+    assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH];
+    assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH];
+      
+    // Receive BVALID from targeted MI.
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),
+       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),
+       .C_DATA_WIDTH  (1)
+      ) mi_bvalid_mux_inst 
+      (
+       .S   (m_atarget_enc),
+       .A   (mi_bvalid),
+       .O   (aa_bvalid),
+       .OE  (b_transfer_en)
+      ); 
+      
+    // MI B-channel payload mux
+    generic_baseblocks_v2_1_0_mux_enc # 
+      (
+       .C_FAMILY      (""rtl""),
+       .C_RATIO       (P_NUM_MASTER_SLOTS_DE),
+       .C_SEL_WIDTH   (P_NUM_MASTER_SLOTS_DE_LOG),
+       .C_DATA_WIDTH  (P_BMESG_WIDTH)
+      ) mi_bmesg_mux_inst 
+      (
+       .S   (m_atarget_enc),
+       .A   (mi_bmesg),
+       .O   (si_bmesg),
+       .OE  (1\'b1)
+      ); 
+      
+    assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; 
+    assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;
+    assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;
+    assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];
+    
+    for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg
+      assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = {  // Concatenate from MSB to LSB
+        mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],
+        mi_bresp[gen_mi_slot*2+:2]
+      };
+    end  // gen_bmesg
+    
+    assign si_bresp = si_bmesg[0 +: 2];
+    assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH];
+    
+    if (C_DEBUG) begin : gen_debug_trans_seq
+      // DEBUG WRITE TRANSACTION SEQUENCE COUNTER
+      always @(posedge ACLK) begin
+        if (reset) begin
+          debug_aw_trans_seq_i <= 1;
+        end else begin
+          if (aa_awvalid && aa_awready) begin
+            debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;
+          end
+        end
+      end
+  
+      // DEBUG READ TRANSACTION SEQUENCE COUNTER
+      always @(posedge ACLK) begin
+        if (reset) begin
+          debug_ar_trans_seq_i <= 1;
+        end else begin
+          if (aa_arvalid && aa_arready) begin
+            debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;
+          end
+        end
+      end
+      
+      // DEBUG WRITE BEAT COUNTER 
+      always @(posedge ACLK) begin
+        if (reset) begin
+          debug_w_beat_cnt_i <= 0;
+        end else if (aa_wready & aa_wvalid) begin
+          if (mi_wlast) begin
+            debug_w_beat_cnt_i <= 0;
+          end else begin
+            debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1;
+          end
+        end
+      end  // Clocked process
+    
+      // DEBUG READ BEAT COUNTER 
+      always @(posedge ACLK) begin
+        if (reset) begin
+          debug_r_beat_cnt_i <= 0;
+        end else if (sr_rready & sr_rvalid) begin
+          if (si_rlast) begin
+            debug_r_beat_cnt_i <= 0;
+          end else begin
+            debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
+          end
+        end
+      end  // Clocked process
+    
+    end  // gen_debug_trans_seq
+
+    if (C_RANGE_CHECK) begin : gen_decerr
+      // Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler
+      axi_crossbar_v2_1_12_decerr_slave #
+        (
+         .C_AXI_ID_WIDTH                 (1),
+         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),
+         .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
+         .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),
+         .C_AXI_PROTOCOL                 (C_AXI_PROTOCOL),
+         .C_RESP                         (P_DECERR) 
+        )
+        decerr_slave_inst
+          (
+           .S_AXI_ACLK (ACLK),
+           .S_AXI_ARESET (reset),
+           .S_AXI_AWID (1\'b0),
+           .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),
+           .S_AXI_WLAST (mi_wlast),
+           .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),
+           .S_AXI_BID (),
+           .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),
+           .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),
+           .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),
+           .S_AXI_ARID (1\'b0),
+           .S_AXI_ARLEN (mi_alen),
+           .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),
+           .S_AXI_RID (),
+           .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
+           .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),
+           .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),
+           .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),
+           .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])
+         );
+    end  // gen_decerr
+
+  endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: crossbar.v
+//
+// Description: 
+//   This module is a M-master to N-slave AXI axi_crossbar_v2_1_12_crossbar switch.
+//   The interface of this module consists of a vectored slave and master interface
+//     in which all slots are sized and synchronized to the native width and clock 
+//     of the interconnect.
+//   The SAMD axi_crossbar_v2_1_12_crossbar supports only AXI4 and AXI3 protocols.
+//   All width, clock and protocol conversions are done outside this block, as are
+//     any pipeline registers or data FIFOs.
+//   This module contains all arbitration, decoders and channel multiplexing logic.
+//     It also contains the diagnostic registers and control interface.
+//
+//-----------------------------------------------------------------------------
+//
+// Structure:
+//    crossbar
+//      si_transactor
+//        addr_decoder
+//          comparator_static
+//        mux_enc
+//        axic_srl_fifo
+//        arbiter_resp
+//      splitter
+//      wdata_router
+//        axic_reg_srl_fifo
+//      wdata_mux
+//        axic_reg_srl_fifo
+//        mux_enc
+//      addr_decoder
+//        comparator_static
+//      axic_srl_fifo
+//      axi_register_slice
+//      addr_arbiter
+//        mux_enc
+//      decerr_slave
+//      
+//-----------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifie'b'dWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_crossbar #
+  (
+   parameter         C_FAMILY                       = ""none"", 
+   parameter integer C_NUM_SLAVE_SLOTS              =   1, 
+   parameter integer C_NUM_MASTER_SLOTS             =   1, 
+   parameter integer C_NUM_ADDR_RANGES              = 1,
+   parameter integer C_AXI_ID_WIDTH                   = 1, 
+   parameter integer C_AXI_ADDR_WIDTH                 = 32, 
+   parameter integer C_AXI_DATA_WIDTH = 32, 
+   parameter integer C_AXI_PROTOCOL           = 0, 
+   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b1}}, 
+   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b0}}, 
+   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1\'b0}},
+   parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1\'b0}},
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32\'h00000000}}, 
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
+   parameter integer C_AXI_AWUSER_WIDTH = 1,
+   parameter integer C_AXI_ARUSER_WIDTH = 1,
+   parameter integer C_AXI_WUSER_WIDTH = 1,
+   parameter integer C_AXI_RUSER_WIDTH = 1,
+   parameter integer C_AXI_BUSER_WIDTH = 1,
+   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE           = {C_NUM_SLAVE_SLOTS{1\'b1}}, 
+   parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ            = {C_NUM_SLAVE_SLOTS{1\'b1}}, 
+   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE           = {C_NUM_MASTER_SLOTS{1\'b1}}, 
+   parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ            = {C_NUM_MASTER_SLOTS{1\'b1}}, 
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1\'b1}},
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1\'b1}},
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD                 = {C_NUM_SLAVE_SLOTS{32\'h00000000}}, 
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE         = {C_NUM_SLAVE_SLOTS{32\'h00000001}},
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE          = {C_NUM_SLAVE_SLOTS{32\'h00000001}},
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING            = {C_NUM_MASTER_SLOTS{32\'h00000001}},
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING            = {C_NUM_MASTER_SLOTS{32\'h00000001}},
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = {C_NUM_SLAVE_SLOTS{32\'h00000000}},
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = {C_NUM_MASTER_SLOTS{32\'h00000000}},
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32\'h00000000}},
+   parameter integer C_RANGE_CHECK                    = 0,
+   parameter integer C_ADDR_DECODE                    = 0,
+   parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH  = {C_NUM_MASTER_SLOTS+1{32\'h00000000}},
+   parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH  = {C_NUM_MASTER_SLOTS+1{32\'h00000000}},
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32\'h00000000}},
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32\'h00000000}},
+   parameter integer C_DEBUG              = 1
+   )
+  (
+   // Global Signals
+   input  wire                                                    ACLK,
+   input  wire                                                    ARESETN,
+   // Slave Interface Write Address Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_AWID,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_AWLEN,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWSIZE,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWBURST,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_AWLOCK,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWCACHE,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_AWPROT,
+//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWREGION,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_AWQOS,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWVALID,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_AWREADY,
+   // Slave Interface Write Data Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_WID,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_WDATA,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]   S_AXI_WSTRB,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WLAST,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WVALID,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_WREADY,
+   // Slave Interface Write Response Ports
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_BID,
+   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_BRESP,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BVALID,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_BREADY,
+   // Slave Interface Read Address Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_ARID,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,
+   input  wire [C_NUM_SLAVE_SLOTS*8-1:0]                          S_AXI_ARLEN,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARSIZE,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARBURST,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_ARLOCK,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARCACHE,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          S_AXI_ARPROT,
+//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARREGION,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          S_AXI_ARQOS,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARVALID,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_ARREADY,
+   // Slave Interface Read Data Ports
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]           S_AXI_RID,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA,
+   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          S_AXI_RRESP,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RLAST,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RVALID,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            S_AXI_RREADY,
+   // Master Interface Write Address Port
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_AWID,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_AWADDR,
+   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_AWLEN,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWSIZE,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWBURST,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_AWLOCK,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWCACHE,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_AWPROT,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWREGION,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_AWQOS,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        M_AXI_AWUSER,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWVALID,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_AWREADY,
+   // Master Interface Write Data Ports
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_WID,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_WDATA,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]  M_AXI_WSTRB,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WLAST,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         M_AXI_WUSER,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WVALID,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_WREADY,
+   // Master Interface Write Response Ports
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_BID,
+   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_BRESP,
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BVALID,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_BREADY,
+   // Master Interface Read Address Port
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_ARID,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          M_AXI_ARADDR,
+   output wire [C_NUM_MASTER_SLOTS*8-1:0]                         M_AXI_ARLEN,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARSIZE,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARBURST,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_ARLOCK,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARCACHE,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         M_AXI_ARPROT,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARREGION,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         M_AXI_ARQOS,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        M_AXI_ARUSER,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARVALID,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_ARREADY,
+   // Master Interface Read Data Ports
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]          M_AXI_RID,
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]    M_AXI_RDATA,
+   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         M_AXI_RRESP,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RLAST,
+   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]         M_AXI_RUSER,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RVALID,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           M_AXI_RREADY
+   );
+   
+  localparam integer  P_AXI4 = 0;
+  localparam integer  P_AXI3 = 1;
+  localparam integer  P_AXILITE = 2;
+  localparam integer P_WRITE = 0;
+  localparam integer P_READ = 1;
+  localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS);
+  localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2);
+  localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;
+  localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH;
+  localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH;
+  localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH;
+  localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH;
+  localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;
+  localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH;
+  localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;
+  localparam [31:0] P_BYPASS  = 32\'h00000000;
+  localparam [31:0] P_FWD_REV = 32\'h00000001;
+  localparam [31:0] P_SIMPLE  = 32\'h00000007;
+  localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1\'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]};
+  localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1\'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]};
+  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1\'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};
+  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1\'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};
+  localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0);
+  localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0);
+  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32\'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};
+  localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32\'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};
+  localparam P_DECERR = 2\'b11;
+
+  //---------------------------------------------------------------------------
+  // Functions
+  //---------------------------------------------------------------------------
+  // Ceiling of log2(x)
+  function integer f_ceil_log2
+    (
+     input integer x
+     );
+    integer acc;
+    begin
+      acc=0;
+      while ((2**acc) < x)
+        acc = acc + 1;
+      f_ceil_log2 = acc;
+    end
+  endfunction
+
+  // Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value
+  //   only for end-point SI-slots
+  function [C_AXI_ID_WIDTH-1:0] f_extend_ID
+    (
+     input [C_AXI_ID_WIDTH-1:0] s_id,
+     input integer slot
+     );
+    begin
+      f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));
+    end
+  endfunction
+
+  // Write connectivity array transposed
+  function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity
+    (
+      input integer null_arg
+     );
+    integer si_slot;
+    integer mi_slot;
+    reg  [C_NUM_SLAVE_SLOTS*32-1:0]  result;
+    begin
+      result = {C_NUM_SLAVE_SLOTS*32{1\'b1}};
+      for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin
+        for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin
+          result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot];
+        end
+      end
+    f_si_write_connectivity = result;
+    end
+  endfunction
+
+  // Read connectivity array transposed
+  function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity
+    (
+      input integer null_arg
+     );
+    integer si_slot;
+    integer mi_slot;
+    reg  [C_NUM_SLAVE_SLOTS*32-1:0]  result;
+    begin
+      result = {C_NUM_SLAVE_SLOTS*32{1\'b1}};
+      for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin
+        for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin
+          result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot];
+        end
+      end
+    f_si_read_connectivity = result;
+    end
+  endfunction
+
+  genvar gen_si_slot;
+  genvar gen_mi_slot;
+  wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0]                  si_st_awmesg          ;
+  wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0]                  st_tmp_awmesg         ;
+  wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0]                  tmp_aa_awmesg         ;
+  wire [P_AA_AWMESG_WIDTH-1:0]                                    aa_mi_awmesg          ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]                     st_aa_awid            ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]                   st_aa_awaddr          ;
+  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_awlen           ;
+  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_awsize          ;
+  wire [C_NUM_SLAVE_SLOTS*2-1:0]                                  st_aa_awlock          ;
+  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_awprot          ;
+  wire [C_NUM_SLAVE_SLOTS*4-1:0]                                  st_aa_awregion        ;
+  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_awerror         ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_aa_awtarget_hot    ;
+  wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0]         st_aa_awtarget_enc    ;
+  wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0]                              aa_wm_awgrant_enc     ;
+  wire [(C_NUM_MASTER_SLOTS+1)-1:0]                               aa_mi_awtarget_hot    ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_awvalid_qual    ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_ss_awvalid         ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_ss_awready         ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_wr_awvalid         ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_wr_awready         ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_aa_awvalid         ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  ss_aa_awready         ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             sa_wm_awvalid         ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             sa_wm_awready         ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awvalid            ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awready            ;
+  wire                                                            aa_sa_awvalid         ;
+  wire                                                            aa_sa_awready         ;
+  wire                                                            aa_mi_arready         ;
+  wire                                                            mi_awvalid_en         ;
+  wire                                                            sa_wm_awvalid_en      ;
+  wire                                                            sa_wm_awready_mux     ;
+  wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0]                  si_st_armesg          ;
+  wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0]                  st_tmp_armesg         ;
+  wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0]                  tmp_aa_armesg         ;
+  wire [P_AA_ARMESG_WIDTH-1:0]                                    aa_mi_armesg          ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]                     st_aa_arid            ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]                   st_aa_araddr          ;
+  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_arlen           ;
+  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_arsize          ;
+  wire [C_NUM_SLAVE_SLOTS*2-1:0]                                  st_aa_arlock          ;
+  wire [C_NUM_SLAVE_SLOTS*3-1:0]                                  st_aa_arprot          ;
+  wire [C_NUM_SLAVE_SLOTS*4-1:0]                                  st_aa_arregion        ;
+  wire [C_NUM_SLAVE_SLOTS*8-1:0]                                  st_aa_arerror         ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_aa_artarget_hot    ;
+  wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0]         st_aa_artarget_enc    ;
+  wire [(C_NUM_MASTER_SLOTS+1)-1:0]                               aa_mi_artarget_hot    ;
+  wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0]                              aa_mi_argrant_enc     ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arvalid_qual    ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arvalid         ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  st_aa_arready         ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_arvalid            ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_arready            ;
+  wire                                                            aa_mi_arvalid         ;
+  wire                                                            mi_awready_mux        ;
+  wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0]                   st_si_bmesg           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0]              st_mr_bmesg           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                st_mr_bid             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             st_mr_bresp           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0]             st_mr_buser           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_bvalid          ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_bready          ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_bready         ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_bid_target     ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_mr_bid_target     ;
+  wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0]         debug_bid_target_i    ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             bid_match             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_bid                ;
+  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             mi_bresp              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0]             mi_buser              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_bvalid             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_bready             ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             bready_carry          ;
+  wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0]                   st_si_rmesg           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0]              st_mr_rmesg           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                st_mr_rid             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]     st_mr_rdata           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0]             st_mr_ruser           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rlast           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             st_mr_rresp           ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rvalid          ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             st_mr_rready          ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_rready         ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             st_tmp_rid_target     ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_mr_rid_target     ;
+  wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0]         debug_rid_target_i    ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             rid_match             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_rid                ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          mi_rdata              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0]             mi_ruser              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rlast              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*2-1:0]                             mi_rresp              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rvalid             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_rready             ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             rready_carry          ;
+  wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0]                   si_wr_wmesg           ;
+  wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0]                   wr_wm_wmesg           ;
+  wire [C_NUM_SLAVE_SLOTS*1-1:0]                                  wr_wm_wlast           ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             wr_tmp_wvalid         ;
+  wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0]             wr_tmp_wready         ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_wm_wvalid         ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0]             tmp_wm_wready         ;
+  wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0]              wm_mr_wmesg              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          wm_mr_wdata              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0]        wm_mr_wstrb              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                wm_mr_wid              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0]             wm_mr_wuser              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wlast              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wvalid             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             wm_mr_wready             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0]          mi_wdata              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0]        mi_wstrb              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0]             mi_wuser              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0]                mi_wid              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wlast              ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wvalid             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_wready             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             w_cmd_push            ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             w_cmd_pop             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             r_cmd_push            ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             r_cmd_pop             ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_awmaxissuing      ;
+  wire [(C_NUM_MASTER_SLOTS+1)*1-1:0]                             mi_armaxissuing      ;
+  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             w_issuing_cnt        ;
+  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             r_issuing_cnt        ;
+  reg  [8-1:0]                                                    debug_aw_trans_seq_i    ;
+  reg  [8-1:0]                                                    debug_ar_trans_seq_i    ;
+  wire [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             debug_w_trans_seq_i     ;
+  reg  [(C_NUM_MASTER_SLOTS+1)*8-1:0]                             debug_w_beat_cnt_i      ;
+
+  reg aresetn_d = 1\'b0; // Reset delay register
+  always @(posedge ACLK) begin
+    if (~ARESETN) begin
+      aresetn_d <= 1\'b0;
+    end else begin
+      aresetn_d <= ARESETN;
+    end
+  end
+  wire reset;
+  assign reset = ~aresetn_d;
+
+  generate
+    for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots
+      if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read
+        axi_crossbar_v2_1_12_si_transactor #  // ""ST"": SI Transactor (read channel)
+          (
+           .C_FAMILY                (C_FAMILY),
+           .C_SI                    (gen_si_slot),
+           .C_DIR                   (P_READ),
+           .C_NUM_ADDR_RANGES       (C_NUM_ADDR_RANGES),
+           .C_NUM_M                 (C_NUM_MASTER_SLOTS),
+           .C_NUM_M_LOG             (P_NUM_MASTER_SLOTS_LOG),
+           .C_ACCEPTANCE            (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]),
+           .C_ACCEPTANCE_LOG        (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]),
+           .C_ID_WIDTH              (C_AXI_ID_WIDTH),
+           .C_THREAD_ID_WIDTH       (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),
+           .C_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
+           .C_AMESG_WIDTH           (P_ST_ARMESG_WIDTH),
+           .C_RMESG_WIDTH           (P_ST_RMESG_WIDTH),
+           .C_BASE_ID               (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
+           .C_HIGH_ID               (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
+           .C_SINGLE_THREAD         (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),
+           .C_BASE_ADDR             (C_M_AXI_BASE_ADDR),
+           .C_HIGH_ADDR             (C_M_AXI_HIGH_ADDR),
+           .C_TARGET_QUAL           (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),
+           .C_M_AXI_SECURE          (C_M_AXI_SECURE),
+           .C_RANGE_CHECK           (C_RANGE_CHECK),
+           .C_ADDR_DECODE           (C_ADDR_DECODE),
+           .C_ERR_MODE              (C_M_AXI_ERR_MODE),
+           .C_DEBUG                 (C_DEBUG)
+           )
+          si_transactor_ar
+            (
+             .ACLK                  (ACLK),
+             .ARESET                (reset),
+             .S_AID                 (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),
+             .S_AADDR               (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
+             .S_ALEN                (S_AXI_ARLEN[gen_si_slot*8+:8]),
+             .S_ASIZE               (S_AXI_ARSIZE[gen_si_slot*3+:3]),
+             .S_ABURST              (S_AXI_ARBURST[gen_si_slot*2+:2]),
+             .S_ALOCK               (S_AXI_ARLOCK[gen_si_slot*2+:2]),
+             .S_APROT               (S_AXI_ARPROT[gen_si_slot*3+:3]),
+//             .S_AREGION             (S_AXI_ARREGION[gen_si_slot*4+:4]),
+             .S_AMESG               (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),
+             .S_AVALID              (S_AXI_ARVALID[gen_si_slot]),
+             .S_AREADY              (S_AXI_ARREADY[gen_si_slot]),
+             .M_AID                 (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
+             .M_AADDR               (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
+             .M_ALEN                (st_aa_arlen[gen_si_slot*8+:8]),
+             .M_ASIZE               (st_aa_arsize[gen_si_slot*3+:3]),
+             .M_ALOCK               (st_aa_arlock[gen_si_slot*2+:2]),
+             .M_APROT               (st_aa_arprot[gen_si_slot*3+:3]),
+             .M_AREGION             (st_aa_arregion[gen_si_slot*4+:4]),
+             .M_AMESG               (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),
+             .M_ATARGET_HOT         (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
+             .M_ATARGET_ENC         (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),
+             .M_AERROR              (st_aa_arerror[gen_si_slot*8+:8]),
+             .M_AVALID_QUAL         (st_aa_arvalid_qual[gen_si_slot]),
+             .M_AVALID              (st_aa_arvalid[gen_si_slot]),
+             .M_AREADY              (st_aa_arready[gen_si_slot]),
+             .S_RID                 (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
+             .S_RMESG               (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]),
+             .S_RLAST               (S_AXI_RLAST[gen_si_slot]),
+             .S_RVALID              (S_AXI_RVALID[gen_si_slot]),
+             .S_RREADY              (S_AXI_RREADY[gen_si_slot]),
+             .M_RID                 (st_mr_rid),
+             .M_RLAST               (st_mr_rlast),
+             .M_RMESG               (st_mr_rmesg),
+             .M_RVALID              (st_mr_rvalid),
+             .M_RREADY              (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
+             .M_RTARGET             (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
+             .DEBUG_A_TRANS_SEQ     (C_DEBUG ? debug_ar_trans_seq_i : 8\'h0)
+             );
+        
+        assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = {
+          S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH],
+          S_AXI_ARQOS[gen_si_slot*4+:4],
+          S_AXI_ARCACHE[gen_si_slot*4+:4],
+          S_AXI_ARBURST[gen_si_slot*2+:2]
+          };
+        assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = {
+          st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH],
+          st_aa_arregion[gen_si_slot*4+:4],
+          st_aa_arprot[gen_si_slot*3+:3],
+          st_aa_arlock[gen_si_slot*2+:2],
+          st_aa_arsize[gen_si_slot*3+:3],
+          st_aa_arlen[gen_si_slot*8+:8],
+          st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],
+          st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]
+          };
+        assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2];
+        assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH];
+        assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH];
+      end else begin : gen_no_si_read
+        assign S_AXI_ARREADY[gen_si_slot] = 1\'b0;
+        assign st_aa_arvalid[gen_si_slot] = 1\'b0;
+        assign st_aa_arvalid_qual[gen_si_slot] = 1\'b1;
+        assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0;
+        assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
+        assign S_AXI_RRESP[gen_si_slot*2+:2] = 0;
+        assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;
+        assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
+        assign S_AXI_RVALID[gen_si_slot] = 1\'b0;
+        assign S_AXI_RLAST[gen_si_slot] = 1\'b0;
+        assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
+        assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
+      end  // gen_si_read
+        
+      if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write
+        axi_crossbar_v2_1_12_si_transactor #  // ""ST"": SI Transactor (write channel)
+          (
+           .C_FAMILY                (C_FAMILY),
+           .C_SI                    (gen_si_slot),
+           .C_DIR                   (P_WRITE),
+           .C_NUM_ADDR_RANGES       (C_NUM_ADDR_RANGES),
+           .C_NUM_M                 (C_NUM_MASTER_SLOTS),
+           .C_NUM_M_LOG             (P_NUM_MASTER_SLOTS_LOG),
+           .C_ACCEPTANCE            (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]),
+           .C_ACCEPTANCE_LOG        (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]),
+           .C_ID_WIDTH              (C_AXI_ID_WIDTH),
+           .C_THREAD_ID_WIDTH       (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),
+           .C_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
+           .C_AMESG_WIDTH           (P_ST_AWMESG_WIDTH),
+           .C_RMESG_WIDTH           (P_ST_BMESG_WIDTH),
+           .C_BASE_ID               (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
+           .C_HIGH_ID               (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
+           .C_SINGLE_THREAD         (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),
+           .C_BASE_ADDR             (C_M_AXI_BASE_ADDR),
+           .C_HIGH_ADDR             (C_M_AXI_HIGH_ADDR),
+           .C_TARGET_QUAL           (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),
+           .C_M_AXI_SECURE          (C_M_AXI_SECURE),
+           .C_RANGE_CHECK           (C_RANGE_CHECK),
+           .C_ADDR_DECODE           (C_ADDR_DECODE),
+           .C_ERR_MODE              (C_M_AXI_ERR_MODE),
+           .C_DEBUG                 (C_DEBUG)
+           )
+          si_transactor_aw
+            (
+             .ACLK                  (ACLK),
+             .ARESET                (reset),
+             .S_AID                 (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),
+             .S_AADDR               (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
+             .S_ALEN                (S_AXI_AWLEN[gen_si_slot*8+:8]),
+             .S_ASIZE               (S_AXI_AWSIZE[gen_si_slot*3+:3]),
+             .S_ABURST              (S_AXI_AWBURST[gen_si_slot*2+:2]),
+             .S_ALOCK               (S_AXI_AWLOCK[gen_si_slot*2+:2]),
+             .S_APROT               (S_AXI_AWPROT[gen_si_slot*3+:3]),
+//             .S_AREGION             (S_AXI_AWREGION[gen_si_slot*4+:4]),
+             .S_AMESG               (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),
+             .S_AVALID              (S_AXI_AWVALID[gen_si_slot]),
+             .S_AREADY              (S_AXI_AWREADY[gen_si_slot]),
+             .M_AID                 (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
+             .M_AADDR               (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
+             .M_ALEN                (st_aa_awlen[gen_si_slot*8+:8]),
+             .M_ASIZE               (st_aa_awsize[gen_si_slot*3+:3]),
+             .M_ALOCK               (st_aa_awlock[gen_si_slot*2+:2]),
+             .M_APROT               (st_aa_awprot[gen_si_slot*3+:3]),
+             .M_AREGION             (st_aa_awregion[gen_si_slot*4+:4]),
+             .M_AMESG               (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),
+             .M_ATARGET_HOT         (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
+             .M_ATARGET_ENC         (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),
+             .M_AERROR              (st_aa_awerror[gen_si_slot*8+:8]),
+             .M_AVALID_QUAL         (st_aa_awvalid_qual[gen_si_slot]),
+             .M_AVALID              (st_ss_awvalid[gen_si_slot]),
+             .M_AREADY              (st_ss_awready[gen_si_slot]),
+             .S_RID                 (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
+             .S_RMESG               (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]),
+             .S_RLAST               (),
+             .S_RVALID              (S_AXI_BVALID[gen_si_slot]),
+             .S_RREADY              (S_AXI_BREADY[gen_si_slot]),
+             .M_RID                 (st_mr_bid),
+             .M_RLAST               ({(C_NUM_MASTER_SLOTS+1){1\'b1}}),
+             .M_RMESG               (st_mr_bmesg),
+             .M_RVALID              (st_mr_bvalid),
+             .M_RREADY              (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
+             .M_RTARGET             (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
+             .DEBUG_A_TRANS_SEQ     (C_DEBUG ? debug_aw_trans_seq_i : 8\'h0)
+             );
+        
+        // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
+        assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = {
+          S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH],
+          S_AXI_AWQOS[gen_si_slot*4+:4],
+          S_AXI_AWCACHE[gen_si_slot*4+:4],
+          S_AXI_AWBURST[gen_si_slot*2+:2]
+          };
+        assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = {
+          st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH],
+          st_aa_awregion[gen_si_slot*4+:4],
+          st_aa_awprot[gen_si_slot*3+:3],
+          st_aa_awlock[gen_si_slot*2+:2],
+          st_aa_awsize[gen_si_slot*3+:3],
+          st_aa_awlen[gen_si_slot*8+:8],
+          st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],
+          st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]
+          };
+        assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2];
+        assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH];
+                       
+        // AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration
+        axi_crossbar_v2_1_12_splitter #  // ""SS"": Splitter from SI-Transactor (write channel)
+          (
+            .C_NUM_M                (2)
+          )
+          splitter_aw_si
+          (
+             .ACLK                  (ACLK),
+             .ARESET                (reset),
+             .S_VALID              (st_ss_awvalid[gen_si_slot]),
+             .S_READY              (st_ss_awready[gen_si_slot]),
+             .M_VALID              ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}),
+             .M_READY              ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]})
+          );
+      
+        axi_crossbar_v2_1_12_wdata_router #  // ""WR"": Write data Router
+          (
+           .C_FAMILY                   (C_FAMILY),
+           .C_NUM_MASTER_SLOTS         (C_NUM_MASTER_SLOTS+1),
+           .C_SELECT_WIDTH             (P_NUM_MASTER_SLOTS_LOG+1),
+           .C_WMESG_WIDTH               (P_WR_WMESG_WIDTH),
+           .C_FIFO_DEPTH_LOG           (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6])
+           )
+          wdata_router_w
+            (
+             .ACLK    (ACLK),
+             .ARESET  (reset),
+             // Write transfer input from the current SI-slot
+             .S_WMESG  (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),
+             .S_WLAST  (S_AXI_WLAST[gen_si_slot]),
+             .S_WVALID (S_AXI_WVALID[gen_si_slot]),
+             .S_WREADY (S_AXI_WREADY[gen_si_slot]),
+             // Vector of write transfer outputs to each MI-slot\'s W-mux
+             .M_WMESG  (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]),
+             .M_WLAST  (wr_wm_wlast[gen_si_slot]),
+             .M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
+             .M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
+             // AW command push from local SI-slot
+             .S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),  // Target MI-slot
+             .S_AVALID  (ss_wr_awvalid[gen_si_slot]),
+             .S_AREADY  (ss_wr_awready[gen_si_slot])
+             );
+             
+        assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = {
+          ((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1\'b0),
+          S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],
+          S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],
+          S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]
+        };        
+      end else begin : gen_no_si_write
+        assign S_AXI_AWREADY[gen_si_slot] = 1\'b0;
+        assign ss_aa_awvalid[gen_si_slot] = 1\'b0;
+        assign st_aa_awvalid_qual[gen_si_slot] = 1\'b1;
+        assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0;
+        assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
+        assign S_AXI_BRESP[gen_si_slot*2+:2] = 0;
+        assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;
+        assign S_AXI_BVALID[gen_si_slot] = 1\'b0;
+        assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
+        assign S_AXI_WREADY[gen_si_slot] = 1\'b0;
+        assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0;
+        assign wr_wm_wlast[gen_si_slot] = 1\'b0;
+        assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
+        assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
+      end  // gen_si_write
+    end  // gen_slave_slots
+    
+    for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots
+      if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read
+        if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder
+          axi_crossbar_v2_1_12_addr_decoder #
+            (
+              .C_FAMILY          (C_FAMILY),
+              .C_NUM_TARGETS     (C_NUM_SLAVE_SLOTS),
+              .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),
+              .C_NUM_RANGES      (1),
+              .C_ADDR_WIDTH      (C_AXI_ID_WIDTH),
+              .C_TARGET_ENC      (C_DEBUG),
+              .C_TARGET_HOT      (1),
+              .C_REGION_ENC      (0),
+              .C_BASE_ADDR       (C_S_AXI_BASE_ID),
+              .C_HIGH_ADDR       (C_S_AXI_HIGH_ID),
+              .C_TARGET_QUAL     (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),
+              .C_RESOLUTION      (0)
+            ) 
+            rid_decoder_inst 
+            (
+              .ADDR             (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),        
+              .TARGET_HOT       (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),  
+              .TARGET_ENC       (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),  
+              .MATCH            (rid_match[gen_mi_slot]),       
+              .REGION           ()      
+            );
+        end else begin : gen_no_rid_decoder
+          assign tmp_mr_rid_target[gen_mi_slot] = 1\'b1;  // All response transfers route to solo SI-slot.
+          assign rid_match[gen_mi_slot] = 1\'b1;
+        end
+        
+        assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = {
+          st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
+          st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH], 
+          st_mr_rresp[gen_mi_slot*2+:2]
+          }; 
+      end else begin : gen_no_mi_read
+        assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
+        assign rid_match[gen_mi_slot] = 1\'b0;
+        assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0;
+      end  // gen_mi_read
+      
+      if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write
+        if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder
+          axi_crossbar_v2_1_12_addr_decoder #
+            (
+              .C_FAMILY          (C_FAMILY),
+              .C_NUM_TARGETS     (C_NUM_SLAVE_SLOTS),
+              .C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),
+              .C_NUM_RANGES      (1),
+              .C_ADDR_WIDTH      (C_AXI_ID_WIDTH),
+              .C_TARGET_ENC      (C_DEBUG),
+              .C_TARGET_HOT      (1),
+              .C_REGION_ENC      (0),
+              .C_BASE_ADDR       (C_S_AXI_BASE_ID),
+              .C_HIGH_ADDR       (C_S_AXI_HIGH_ID),
+              .C_TARGET_QUAL     (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),
+              .C_RESOLUTION      (0)
+            ) 
+            bid_decoder_inst 
+            (
+              .ADDR             (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),        
+              .TARGET_HOT       (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),  
+              .TARGET_ENC       (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),  
+              .MATCH            (bid_match[gen_mi_slot]),       
+              .REGION           ()      
+            );
+        end else begin : gen_no_bid_decoder
+          assign tmp_mr_bid_target[gen_mi_slot] = 1\'b1;  // All response transfers route to solo SI-slot.
+          assign bid_match[gen_mi_slot] = 1\'b1;
+        end
+      
+        axi_crossbar_v2_1_12_wdata_mux #  // ""WM"": Write data Mux, per MI-slot (incl error-handler)
+          (
+           .C_FAMILY                   (C_FAMILY),
+           .C_NUM_SLAVE_SLOTS         (C_NUM_SLAVE_SLOTS),
+           .C_SELECT_WIDTH     (P_NUM_SLAVE_SLOTS_LOG),
+           .C_WMESG_WIDTH               (P_WR_WMESG_WIDTH),
+           .C_FIFO_DEPTH_LOG           (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6])
+           )
+          wdata_mux_w
+            (
+             .ACLK    (ACLK),
+             .ARESET  (reset),
+             // Vector of write transfer inputs from each SI-slot\'s W-router
+             .S_WMESG  (wr_wm_wmesg),
+             .S_WLAST  (wr_wm_wlast),
+             .S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
+             .S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
+             // Write transfer output to the current MI-slot
+             .M_WMESG  (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),
+             .M_WLAST  (wm_mr_wlast[gen_mi_slot]),
+             .M_WVALID (wm_mr_wvalid[gen_mi_slot]),
+             .M_WREADY (wm_mr_wready[gen_mi_slot]),
+             // AW command push from AW arbiter output
+             .S_ASELECT (aa_wm_awgrant_enc),  // SI-slot selected by arbiter
+             .S_AVALID  (sa_wm_awvalid[gen_mi_slot]),
+             .S_AREADY  (sa_wm_awready[gen_mi_slot])
+             );
+             
+        if (C_DEBUG) begin : gen_debug_w
+          // DEBUG WRITE BEAT COUNTER
+          always @(posedge ACLK) begin
+            if (reset) begin
+              debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;
+            end else begin
+              if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin
+                if (mi_wlast[gen_mi_slot]) begin
+                  debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;
+                end else begin
+                  debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1;
+                end
+              end
+            end
+          end  // clocked process
+  
+          // DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE
+          axi_data_fifo_v2_1_10_axic_srl_fifo #
+            (
+             .C_FAMILY          (C_FAMILY),
+             .C_FIFO_WIDTH      (8),
+             .C_FIFO_DEPTH_LOG  (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]),
+             .C_USE_FULL        (0)
+             )
+            debug_w_seq_fifo
+              (
+               .ACLK    (ACLK),
+               .ARESET  (reset),
+               .S_MESG  (debug_aw_trans_seq_i),
+               .S_VALID (sa_wm_awvalid[gen_mi_slot]),
+               .S_READY (),
+               .M_MESG  (debug_w_trans_seq_i[gen_mi_slot*8+:8]),
+               .M_VALID (),
+               .M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot])
+              );
+        end  // gen_debug_w
+             
+        assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH];
+        assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];
+        assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];
+        assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];
+        assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = {
+          st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],
+          st_mr_bresp[gen_mi_slot*2+:2]
+          }; 
+      end else begin : gen_no_mi_write
+        assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
+        assign bid_match[gen_mi_slot] = 1\'b0;
+        assign wm_mr_wvalid[gen_mi_slot] = 0;
+        assign wm_mr_wlast[gen_mi_slot] = 0;
+        assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
+        assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0;
+        assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0;
+        assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
+        assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0;
+        assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
+        assign sa_wm_awready[gen_mi_slot] = 0;
+      end  // gen_mi_write
+      
+      for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si
+        // Transpose handshakes from W-router (SxM) to W-mux (MxS).
+        assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];
+        assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
+        // Transpose response enables from ID decoders (MxS) to si_transactors (SxM).
+        assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
+        assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
+      end  // gen_trans_si
+      
+      assign bready_carry[gen_mi_slot] =  st_tmp_bready[gen_mi_slot];
+      assign rready_carry[gen_mi_slot] =  st_tmp_rready[gen_mi_slot];
+      for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si
+        assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] =  // Generate M_BREADY if ...
+          bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] |  // For any SI-slot (OR carry-chain across all SI-slots), ...
+          st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];  // The write SI transactor indicates BREADY for that MI-slot.
+        assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] =  // Generate M_RREADY if ...
+          rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] |  // For any SI-slot (OR carry-chain across all SI-slots), ...
+          st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];  // The write SI transactor indicates RREADY for that MI-slot.
+      end  // gen_resp_carry_si
+           
+      assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];
+      assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];
+      assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];
+      assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];
+      // Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit.
+      assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == 
+          P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot];
+      assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] == 
+          P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot];
+      
+      always @(posedge ACLK) begin
+        if (reset) begin
+          w_issuing_cnt[gen_mi_slot*8+:8] <= 0;  // Some high-order bits remain constant 0
+          r_issuing_cnt[gen_mi_slot*8+:8] <= 0;  // Some high-order bits remain constant 0
+        end else begin
+          if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin
+            w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;
+          end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin
+            w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;
+          end
+          if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin
+            r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;
+          end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin
+            r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;
+          end
+        end
+      end  // Clocked process
+      
+      // Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs.
+      //   (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.)
+      //   Reg-slice incurs +1 latency, but no bubble-cycles.
+      axi_register_slice_v2_1_11_axi_register_slice #  // ""MR"": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured)
+        (
+          .C_FAMILY                         (C_FAMILY),
+          .C_AXI_PROTOCOL                   ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4),
+          .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
+          .C_AXI_ADDR_WIDTH                 (1),
+          .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
+          .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),
+          .C_AXI_AWUSER_WIDTH               (1),
+          .C_AXI_ARUSER_WIDTH               (1),
+          .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),
+          .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
+          .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),
+          .C_REG_CONFIG_AW                  (P_BYPASS),
+          .C_REG_CONFIG_AR                  (P_BYPASS),
+          .C_REG_CONFIG_W                   (P_BYPASS),
+          .C_REG_CONFIG_R                   (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS),
+          .C_REG_CONFIG_B                   (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS)
+        )
+        reg_slice_mi 
+        (
+          .aresetn                          (ARESETN),
+          .aclk                             (ACLK),
+          .s_axi_awid                       ({C_AXI_ID_WIDTH{1\'b0}}),
+          .s_axi_awaddr                     ({1{1\'b0}}),
+          .s_axi_awlen                      ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1\'b0}}),
+          .s_axi_awsize                     ({3{1\'b0}}),
+          .s_axi_awburst                    ({2{1\'b0}}),
+          .s_axi_awlock                     ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1\'b0}}),
+          .s_axi_awcache                    ({4{1\'b0}}),
+          .s_axi_awprot                     ({3{1\'b0}}),
+          .s_axi_awregion                   ({4{1\'b0}}),
+          .s_axi_awqos                      ({4{1\'b0}}),
+          .s_axi_awuser                     ({1{1\'b0}}),
+          .s_axi_awvalid                    ({1{1\'b0}}),
+          .s_axi_awready                    (),
+          .s_axi_wid                        (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
+          .s_axi_wdata                      (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
+          .s_axi_wstrb                      (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),
+          .s_axi_wlast                      (wm_mr_wlast[gen_mi_slot]),
+          .s_axi_wuser                      (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),
+          .s_axi_wvalid                     (wm_mr_wvalid[gen_mi_slot]),
+          .s_axi_wready                     (wm_mr_wready[gen_mi_slot]),
+          .s_axi_bid                        (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]         ),
+          .s_axi_bresp                      (st_mr_bresp[gen_mi_slot*2+:2]                                 ),
+          .s_axi_buser                      (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),
+          .s_axi_bvalid                     (st_mr_bvalid[gen_mi_slot*1+:1]                                ),
+          .s_axi_bready                     (st_mr_bready[gen_mi_slot*1+:1]                                ),
+          .s_axi_arid                       ({C_AXI_ID_WIDTH{1\'b0}}),
+          .s_axi_araddr                     ({1{1\'b0}}),
+          .s_axi_arlen                      ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1\'b0}}),
+          .s_axi_arsize                     ({3{1\'b0}}),
+          .s_axi_arburst                    ({2{1\'b0}}),
+          .s_axi_arlock                     ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1\'b0}}),
+          .s_axi_arcache                    ({4{1\'b0}}),
+          .s_axi_arprot                     ({3{1\'b0}}),
+          .s_axi_arregion                   ({4{1\'b0}}),
+          .s_axi_arqos                      ({4{1\'b0}}),
+          .s_axi_aruser                     ({1{1\'b0}}),
+          .s_axi_arvalid                    ({1{1\'b0}}),
+          .s_axi_arready                    (),
+          .s_axi_rid                        (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),
+          .s_axi_rdata                      (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]  ),
+          .s_axi_rresp                      (st_mr_rresp[gen_mi_slot*2+:2]                                                  ),
+          .s_axi_rlast                      (st_mr_rlast[gen_mi_slot*1+:1]                                                  ),
+          .s_axi_ruser                      (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                  ),
+          .s_axi_rvalid                     (st_mr_rvalid[gen_mi_slot*1+:1]                                                 ),
+          .s_axi_rready                     (st_mr_rready[gen_mi_slot*1+:1]                                                 ),
+          .m_axi_awid                       (),
+          .m_axi_awaddr                     (),
+          .m_axi_awlen                      (),
+          .m_axi_awsize                     (),
+          .m_axi_awburst                    (),
+          .m_axi_awlock                     (),
+          .m_axi_awcache                    (),
+          .m_axi_awprot                     (),
+          .m_axi_awregion                   (),
+          .m_axi_awqos                      (),
+          .m_axi_awuser                     (),
+          .m_axi_awvalid                    (),
+          .m_axi_awready                    ({1{1\'b0}}),
+          .m_axi_wid                        (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
+          .m_axi_wdata                      (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
+          .m_axi_wstrb                      (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),
+          .m_axi_wlast                      (mi_wlast[gen_mi_slot]),
+          .m_axi_wuser                      (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),
+          .m_axi_wvalid                     (mi_wvalid[gen_mi_slot]),
+          .m_axi_wready                     (mi_wready[gen_mi_slot]),
+          .m_axi_bid                        (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),
+          .m_axi_bresp                      (mi_bresp[gen_mi_slot*2+:2]                                                  ),
+          .m_axi_buser                      (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                  ),
+          .m_axi_bvalid                     (mi_bvalid[gen_mi_slot*1+:1]                                                 ),
+          .m_axi_bready                     (mi_bready[gen_mi_slot*1+:1]                                                 ),
+          .m_axi_arid                       (),
+          .m_axi_araddr                     (),
+          .m_axi_arlen                      (),
+          .m_axi_arsize                     (),
+          .m_axi_arburst                    (),
+          .m_axi_arlock                     (),
+          .m_axi_arcache                    (),
+          .m_axi_arprot                     (),
+          .m_axi_arregion                   (),
+          .m_axi_arqos                      (),
+          .m_axi_aruser                     (),
+          .m_axi_arvalid                    (),
+          .m_axi_arready                    ({1{1\'b0}}),
+          .m_axi_rid                        (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                          ),
+          .m_axi_rdata                      (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]  ),
+          .m_axi_rresp                      (mi_rresp[gen_mi_slot*2+:2]                                                  ),
+          .m_axi_rlast                      (mi_rlast[gen_mi_slot*1+:1]                                                  ),
+          .m_axi_ruser                      (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                  ),
+          .m_axi_rvalid                     (mi_rvalid[gen_mi_slot*1+:1]                                                 ),
+          .m_axi_rready                     (mi_rready[gen_mi_slot*1+:1]                                                 )
+        );
+    end  // gen_master_slots (Next gen_mi_slot)
+  
+    // Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot.
+    assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; 
+    assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1]; 
+    // Assign MI-side B, R and W channel ports (exclude error handler signals).
+    assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID;
+    assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID; 
+    assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;
+    assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;
+    assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];
+    assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID;
+    assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST; 
+    assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID; 
+    assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;
+    assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;
+    assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;
+    assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];
+    assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS];
+    assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];
+    assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH];
+    assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0;
+    assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH];
+    assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8];
+    assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;
+
+    axi_crossbar_v2_1_12_addr_arbiter #  // ""AA"": Addr Arbiter (AW channel)
+      (
+       .C_FAMILY                (C_FAMILY),
+       .C_NUM_M                 (C_NUM_MASTER_SLOTS+1),
+       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),
+       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),
+       .C_MESG_WIDTH            (P_AA_AWMESG_WIDTH),
+       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)
+       )
+      addr_arbiter_aw
+        (
+         .ACLK                  (ACLK),
+         .ARESET                (reset),
+         // Vector of SI-side AW command requ'b'est inputs
+         .S_MESG                (tmp_aa_awmesg),
+         .S_TARGET_HOT          (st_aa_awtarget_hot),
+         .S_VALID               (ss_aa_awvalid),
+         .S_VALID_QUAL          (st_aa_awvalid_qual),
+         .S_READY               (ss_aa_awready),
+         // Granted AW command output
+         .M_MESG                (aa_mi_awmesg),
+         .M_TARGET_HOT          (aa_mi_awtarget_hot),  // MI-slot targeted by granted command
+         .M_GRANT_ENC           (aa_wm_awgrant_enc),  // SI-slot index of granted command
+         .M_VALID               (aa_sa_awvalid),
+         .M_READY               (aa_sa_awready),
+         .ISSUING_LIMIT        (mi_awmaxissuing)
+        );
+         
+    // Broadcast AW transfer payload to all MI-slots
+    assign M_AXI_AWID        = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}};
+    assign M_AXI_AWADDR      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};
+    assign M_AXI_AWLEN       = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};
+    assign M_AXI_AWSIZE      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};
+    assign M_AXI_AWLOCK      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};
+    assign M_AXI_AWPROT      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};
+    assign M_AXI_AWREGION    = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};
+    assign M_AXI_AWBURST     = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};
+    assign M_AXI_AWCACHE     = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};
+    assign M_AXI_AWQOS       = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};
+    assign M_AXI_AWUSER      = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}};
+         
+    axi_crossbar_v2_1_12_addr_arbiter #  // ""AA"": Addr Arbiter (AR channel)
+      (
+       .C_FAMILY                (C_FAMILY),
+       .C_NUM_M                 (C_NUM_MASTER_SLOTS+1),
+       .C_NUM_S                 (C_NUM_SLAVE_SLOTS),
+       .C_NUM_S_LOG             (P_NUM_SLAVE_SLOTS_LOG),
+       .C_MESG_WIDTH            (P_AA_ARMESG_WIDTH),
+       .C_ARB_PRIORITY          (C_S_AXI_ARB_PRIORITY)
+       )
+      addr_arbiter_ar
+        (
+         .ACLK                  (ACLK),
+         .ARESET                (reset),
+         // Vector of SI-side AR command request inputs
+         .S_MESG                (tmp_aa_armesg),
+         .S_TARGET_HOT          (st_aa_artarget_hot),
+         .S_VALID_QUAL          (st_aa_arvalid_qual),
+         .S_VALID               (st_aa_arvalid),
+         .S_READY               (st_aa_arready),
+         // Granted AR command output
+         .M_MESG                (aa_mi_armesg),
+         .M_TARGET_HOT          (aa_mi_artarget_hot),  // MI-slot targeted by granted command
+         .M_GRANT_ENC           (aa_mi_argrant_enc),
+         .M_VALID               (aa_mi_arvalid),  // SI-slot index of granted command
+         .M_READY               (aa_mi_arready),
+         .ISSUING_LIMIT        (mi_armaxissuing)
+        );
+    
+    if (C_DEBUG) begin : gen_debug_trans_seq
+      // DEBUG WRITE TRANSACTION SEQUENCE COUNTER
+      always @(posedge ACLK) begin
+        if (reset) begin
+          debug_aw_trans_seq_i <= 1;
+        end else begin
+          if (aa_sa_awvalid && aa_sa_awready) begin
+            debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;
+          end
+        end
+      end
+  
+      // DEBUG READ TRANSACTION SEQUENCE COUNTER
+      always @(posedge ACLK) begin
+        if (reset) begin
+          debug_ar_trans_seq_i <= 1;
+        end else begin
+          if (aa_mi_arvalid && aa_mi_arready) begin
+            debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;
+          end
+        end
+      end
+    end  // gen_debug_trans_seq
+
+    // Broadcast AR transfer payload to all MI-slots
+    assign M_AXI_ARID        = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}};
+    assign M_AXI_ARADDR      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};
+    assign M_AXI_ARLEN       = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};
+    assign M_AXI_ARSIZE      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};
+    assign M_AXI_ARLOCK      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};
+    assign M_AXI_ARPROT      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};
+    assign M_AXI_ARREGION    = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};
+    assign M_AXI_ARBURST     = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};
+    assign M_AXI_ARCACHE     = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};
+    assign M_AXI_ARQOS       = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};
+    assign M_AXI_ARUSER      = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}};
+         
+    // AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push).
+    axi_crossbar_v2_1_12_splitter #  // ""SA"": Splitter for Write Addr Arbiter
+      (
+        .C_NUM_M                (2)
+      )
+      splitter_aw_mi
+      (
+         .ACLK                  (ACLK),
+         .ARESET                (reset),
+         .S_VALID              (aa_sa_awvalid),
+         .S_READY              (aa_sa_awready),
+         .M_VALID              ({mi_awvalid_en, sa_wm_awvalid_en}),
+         .M_READY              ({mi_awready_mux, sa_wm_awready_mux})
+      );
+      
+    assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}};
+    assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready);
+    assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS];  // Slot C_NUM_MASTER_SLOTS+1 is the error handler
+    assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;
+    assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}};
+    assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready);
+    
+    assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}};
+    assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready);
+    assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS];  // Slot C_NUM_MASTER_SLOTS+1 is the error handler
+    assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;
+    
+    // MI-slot # C_NUM_MASTER_SLOTS is the error handler
+    if (C_RANGE_CHECK) begin : gen_decerr_slave
+      axi_crossbar_v2_1_12_decerr_slave #
+        (
+         .C_AXI_ID_WIDTH                 (C_AXI_ID_WIDTH),
+         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),
+         .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
+         .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),
+         .C_AXI_PROTOCOL                 (C_AXI_PROTOCOL),
+         .C_RESP                         (P_DECERR) 
+        )
+        decerr_slave_inst
+          (
+           .S_AXI_ACLK (ACLK),
+           .S_AXI_ARESET (reset),
+           .S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]),
+           .S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),
+           .S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]),
+           .S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),
+           .S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
+           .S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),
+           .S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),
+           .S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),
+           .S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]),
+           .S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]),
+           .S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),
+           .S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
+           .S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
+           .S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),
+           .S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),
+           .S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),
+           .S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),
+           .S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])
+         );
+    end else begin : gen_no_decerr_slave
+      assign mi_awready[C_NUM_MASTER_SLOTS] = 1\'b0;
+      assign mi_wready[C_NUM_MASTER_SLOTS] = 1\'b0;
+      assign mi_arready[C_NUM_MASTER_SLOTS] = 1\'b0;
+      assign mi_awready[C_NUM_MASTER_SLOTS] = 1\'b0;
+      assign mi_awready[C_NUM_MASTER_SLOTS] = 1\'b0;
+      assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                    = 0;
+      assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2]                                            = 0;
+      assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]            = 0;
+      assign mi_bvalid[C_NUM_MASTER_SLOTS]                                                = 1\'b0;
+      assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                    = 0;
+      assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0; 
+      assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2]                                            = 0; 
+      assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]            = 0; 
+      assign mi_rlast[C_NUM_MASTER_SLOTS]                                                  = 1\'b0;
+      assign mi_rvalid[C_NUM_MASTER_SLOTS]                                                 = 1\'b0;
+    end  // gen_decerr_slave
+  endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: decerr_slave.v
+//
+// Description: 
+//   Phantom slave interface used to complete W, R and B channel transfers when an
+//   erroneous transaction is trapped in the crossbar.
+//--------------------------------------------------------------------------
+//
+// Structure:
+//    decerr_slave
+//    
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_decerr_slave #
+  (
+   parameter integer C_AXI_ID_WIDTH           = 1,
+   parameter integer C_AXI_DATA_WIDTH         = 32,
+   parameter integer C_AXI_BUSER_WIDTH        = 1,
+   parameter integer C_AXI_RUSER_WIDTH        = 1,
+   parameter integer C_AXI_PROTOCOL           = 0,
+   parameter integer C_RESP                   = 2\'b11   
+   )
+  (
+   input wire S_AXI_ACLK,
+   input wire S_AXI_ARESET,
+   input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
+   input wire S_AXI_AWVALID,
+   output wire S_AXI_AWREADY,
+   input wire S_AXI_WLAST,
+   input wire S_AXI_WVALID,
+   output wire S_AXI_WREADY,
+   output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
+   output wire [1:0] S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire S_AXI_BVALID,
+   input wire S_AXI_BREADY,
+   input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
+   input wire [7:0] S_AXI_ARLEN,
+   input wire S_AXI_ARVALID,
+   output wire S_AXI_ARREADY,
+   output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
+   output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
+   output wire [1:0] S_AXI_RRESP,
+   output wire [C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,
+   output wire S_AXI_RLAST,
+   output wire S_AXI_RVALID,
+   input wire S_AXI_RREADY
+   );
+   
+  reg s_axi_awready_i;
+  reg s_axi_wready_i;
+  reg s_axi_bvalid_i;
+  reg s_axi_arready_i;
+  reg s_axi_rvalid_i;
+  
+  localparam P_WRITE_IDLE = 2\'b00;
+  localparam P_WRITE_DATA = 2\'b01;
+  localparam P_WRITE_RESP = 2\'b10;
+  localparam P_READ_IDLE = 1\'b0;
+  localparam P_READ_DATA = 1\'b1;
+  localparam integer  P_AXI4 = 0;
+  localparam integer  P_AXI3 = 1;
+  localparam integer  P_AXILITE = 2;
+   
+  assign S_AXI_BRESP = C_RESP;
+  assign S_AXI_RRESP = C_RESP;
+  assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1\'b0}};
+  assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1\'b0}};
+  assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1\'b0}};
+  assign S_AXI_AWREADY = s_axi_awready_i;
+  assign S_AXI_WREADY = s_axi_wready_i;
+  assign S_AXI_BVALID = s_axi_bvalid_i;
+  assign S_AXI_ARREADY = s_axi_arready_i;
+  assign S_AXI_RVALID = s_axi_rvalid_i;
+  
+  generate
+  if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
+    
+    assign S_AXI_RLAST = 1\'b1;
+    assign S_AXI_BID = 0;
+    assign S_AXI_RID = 0;
+    
+    always @(posedge S_AXI_ACLK) begin
+      if (S_AXI_ARESET) begin
+        s_axi_awready_i <= 1\'b0;
+        s_axi_wready_i <= 1\'b0;
+        s_axi_bvalid_i <= 1\'b0;
+      end else begin
+        if (s_axi_bvalid_i) begin
+          if (S_AXI_BREADY) begin
+            s_axi_bvalid_i <= 1\'b0;
+          end
+        end else if (S_AXI_AWVALID & S_AXI_WVALID) begin
+          if (s_axi_awready_i) begin
+            s_axi_awready_i <= 1\'b0;
+            s_axi_wready_i <= 1\'b0;
+            s_axi_bvalid_i <= 1\'b1;
+          end else begin
+            s_axi_awready_i <= 1\'b1;
+            s_axi_wready_i <= 1\'b1;
+          end
+        end
+      end
+    end
+           
+    always @(posedge S_AXI_ACLK) begin
+      if (S_AXI_ARESET) begin
+        s_axi_arready_i <= 1\'b0;
+        s_axi_rvalid_i <= 1\'b0;
+      end else begin
+        if (s_axi_rvalid_i) begin
+          if (S_AXI_RREADY) begin
+            s_axi_rvalid_i <= 1\'b0;
+          end
+        end else if (S_AXI_ARVALID & s_axi_arready_i) begin
+          s_axi_arready_i <= 1\'b0;
+          s_axi_rvalid_i <= 1\'b1;
+        end else begin
+          s_axi_arready_i <= 1\'b1;
+        end
+      end
+    end
+        
+  end else begin : gen_axi
+  
+    reg s_axi_rlast_i;
+    reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
+    reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
+    reg [7:0] read_cnt;
+    reg [1:0] write_cs;
+    reg [0:0] read_cs;
+  
+    assign S_AXI_RLAST = s_axi_rlast_i;
+    assign S_AXI_BID = s_axi_bid_i;
+    assign S_AXI_RID = s_axi_rid_i;
+  
+    always @(posedge S_AXI_ACLK) begin
+      if (S_AXI_ARESET) begin
+        write_cs <= P_WRITE_IDLE;
+        s_axi_awready_i <= 1\'b0;
+        s_axi_wready_i <= 1\'b0;
+        s_axi_bvalid_i <= 1\'b0;
+        s_axi_bid_i <= 0;
+      end else begin
+        case (write_cs) 
+          P_WRITE_IDLE: 
+            begin
+              if (S_AXI_AWVALID & s_axi_awready_i) begin
+                s_axi_awready_i <= 1\'b0;
+                s_axi_bid_i <= S_AXI_AWID;
+                s_axi_wready_i <= 1\'b1;
+                write_cs <= P_WRITE_DATA;
+              end else begin
+                s_axi_awready_i <= 1\'b1;
+              end
+            end
+          P_WRITE_DATA:
+            begin
+              if (S_AXI_WVALID & S_AXI_WLAST) begin
+                s_axi_wready_i <= 1\'b0;
+                s_axi_bvalid_i <= 1\'b1;
+                write_cs <= P_WRITE_RESP;
+              end
+            end
+          P_WRITE_RESP:
+            begin
+              if (S_AXI_BREADY) begin
+                s_axi_bvalid_i <= 1\'b0;
+                s_axi_awready_i <= 1\'b1;
+                write_cs <= P_WRITE_IDLE;
+              end
+            end
+        endcase
+      end
+    end
+  
+    always @(posedge S_AXI_ACLK) begin
+      if (S_AXI_ARESET) begin
+        read_cs <= P_READ_IDLE;
+        s_axi_arready_i <= 1\'b0;
+        s_axi_rvalid_i <= 1\'b0;
+        s_axi_rlast_i <= 1\'b0;
+        s_axi_rid_i <= 0;
+        read_cnt <= 0;
+      end else begin
+        case (read_cs) 
+          P_READ_IDLE: 
+            begin
+              if (S_AXI_ARVALID & s_axi_arready_i) begin
+                s_axi_arready_i <= 1\'b0;
+                s_axi_rid_i <= S_AXI_ARID;
+                read_cnt <= S_AXI_ARLEN;
+                s_axi_rvalid_i <= 1\'b1;
+                if (S_AXI_ARLEN == 0) begin
+                  s_axi_rlast_i <= 1\'b1;
+                end else begin
+                  s_axi_rlast_i <= 1\'b0;
+                end
+                read_cs <= P_READ_DATA;
+              end else begin
+                s_axi_arready_i <= 1\'b1;
+              end
+            end
+          P_READ_DATA:
+            begin
+              if (S_AXI_RREADY) begin
+                if (read_cnt == 0) begin
+                  s_axi_rvalid_i <= 1\'b0;
+                  s_axi_rlast_i <= 1\'b0;
+                  s_axi_arready_i <= 1\'b1;
+                  read_cs <= P_READ_IDLE;
+                end else begin
+                  if (read_cnt == 1) begin
+                    s_axi_rlast_i <= 1\'b1;
+                  end
+                  read_cnt <= read_cnt - 1;
+                end
+              end
+            end
+        endcase
+      end
+    end
+  
+  end  
+  endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: si_transactor.v
+//
+// Description: 
+//   This module manages multi-threaded transactions for one SI-slot.
+//   The module interface consists of a 1-slave to 1-master address channel, plus a
+//     (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
+//   The module maintains transaction thread control registers that count the
+//     number of outstanding transations for each thread and the target MI-slot.
+//   On the address channel, the module decodes addresses to select among MI-slots 
+//     accessible to the SI-slot where it is instantiated.
+//     It then qualifies whether each received transaction
+//     should be propagated as a request to the address channel arbiter.
+//     Transactions are blocked while there is any outstanding transaction to a 
+//     different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
+//   On the response channel, the module mulitplexes transfers from each of the 
+//     MI-slots whenever a transfer targets the ID of an active thread,
+//     arbitrating between MI-slots if multiple threads respond concurrently.
+//
+//--------------------------------------------------------------------------
+//
+// Structure:
+//    si_transactor
+//      addr_decoder
+//        comparator_static
+//      mux_enc
+//      axic_srl_fifo
+//      arbiter_resp
+//      
+//-----------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_si_transactor #
+  (
+   parameter         C_FAMILY                       = ""none"", 
+   parameter integer C_SI             =   0, // SI-slot number of current instance.
+   parameter integer C_DIR             =   0, // Direction: 0 = Write; 1 = Read.
+   parameter integer C_NUM_ADDR_RANGES = 1,
+   parameter integer C_NUM_M             =   2, 
+   parameter integer C_NUM_M_LOG             =   1, 
+   parameter integer C_ACCEPTANCE             =   1,  // Acceptance limit of this SI-slot.
+   parameter integer C_ACCEPTANCE_LOG             =   0,  // Width of acceptance counter for this SI-slot.
+   parameter integer C_ID_WIDTH                   = 1, 
+   parameter integer C_THREAD_ID_WIDTH                  = 0,
+   parameter integer C_ADDR_WIDTH                 = 32, 
+   parameter integer C_AMESG_WIDTH = 1,  // Used for AW or AR channel payload, depending on instantiation.
+   parameter integer C_RMESG_WIDTH = 1,  // Used for B or R channel payload, depending on instantiation.
+   parameter [C_ID_WIDTH-1:0]  C_BASE_ID                  = {C_ID_WIDTH{1\'b0}},
+   parameter [C_ID_WIDTH-1:0]  C_HIGH_ID                  = {C_ID_WIDTH{1\'b0}},
+   parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1\'b1}}, 
+   parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1\'b0}}, 
+   parameter integer C_SINGLE_THREAD             =   0,
+   parameter [C_NUM_M-1:0]    C_TARGET_QUAL                 = {C_NUM_M{1\'b1}},
+   parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE                   = {C_NUM_M{32\'h00000000}},
+   parameter integer C_RANGE_CHECK                    = 0,
+   parameter integer C_ADDR_DECODE           =0,
+   parameter [C_NUM_M*32-1:0] C_ERR_MODE            = {C_NUM_M{32\'h00000000}},
+   parameter integer C_DEBUG                = 1
+   )
+  (
+   // Global Signals
+   input  wire                                                    ACLK,
+   input  wire                                                    ARESET,
+   // Slave Address Channel Interface Ports
+   input  wire [C_ID_WIDTH-1:0]           S_AID,
+   input  wire [C_ADDR_WIDTH-1:0]          S_AADDR,
+   input  wire [8-1:0]                    S_ALEN,
+   input  wire [3-1:0]                    S_ASIZE,
+   input  wire [2-1:0]                    S_ABURST,
+   input  wire [2-1:0]                    S_ALOCK,
+   input  wire [3-1:0]                    S_APROT,
+//   input  wire [4-1:0]                    S_AREGION,
+   input  wire [C_AMESG_WIDTH-1:0]         S_AMESG,
+   input  wire                             S_AVALID,
+   output wire                             S_AREADY,
+   // Master Address Channel Interface Ports
+   output wire [C_ID_WIDTH-1:0]          M_AID,
+   output wire [C_ADDR_WIDTH-1:0]          M_AADDR,
+   output  wire [8-1:0]                    M_ALEN,
+   output  wire [3-1:0]                    M_ASIZE,
+   output  wire [2-1:0]                    M_ALOCK,
+   output  wire [3-1:0]                    M_APROT,
+   output wire [4-1:0]                         M_AREGION,
+   output wire [C_AMESG_WIDTH-1:0]                         M_AMESG,
+   output wire [(C_NUM_M+1)-1:0]                         M_ATARGET_HOT,
+   output wire [(C_NUM_M_LOG+1)-1:0]                         M_ATARGET_ENC,
+   output wire [7:0]                         M_AERROR,
+   output wire                            M_AVALID_QUAL,
+   output wire                            M_AVALID,
+   input  wire                            M_AREADY,
+   // Slave Response Channel Interface Ports
+   output  wire [C_ID_WIDTH-1:0]           S_RID,
+   output  wire [C_RMESG_WIDTH-1:0]         S_RMESG,
+   output  wire                             S_RLAST,
+   output  wire                             S_RVALID,
+   input wire                             S_RREADY,
+   // Master Response Channel Interface Ports
+   input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0]          M_RID,
+   input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0]             M_RMESG,
+   input wire [(C_NUM_M+1)-1:0]                           M_RLAST,
+   input wire [(C_NUM_M+1)-1:0]                           M_RVALID,
+   output  wire [(C_NUM_M+1)-1:0]                           M_RREADY,
+   input wire [(C_NUM_M+1)-1:0]           M_RTARGET,  // Does response ID from each MI-slot target this SI slot?
+   input wire [8-1:0]                        DEBUG_A_TRANS_SEQ
+   );
+
+  localparam integer P_WRITE = 0;
+  localparam integer P_READ = 1;
+  localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
+  localparam [31:0]   P_AXILITE_ERRMODE = 32\'h00000001;
+  localparam integer P_NONSECURE_BIT = 1; 
+  localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
+  localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0);  // Mask of AxiLite MI-slots
+  localparam [1:0]   P_FIXED = 2\'b00;
+  localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
+  localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1; 
+  localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
+  localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
+  localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE);  // Mask of secure MI-slots
+  
+  // Ceiling of log2(x)
+  function integer f_ceil_log2
+    (
+     input integer x
+     );
+    integer acc;
+    begin
+      acc=0;
+      while ((2**acc) < x)
+        acc = acc + 1;
+      f_ceil_log2 = acc;
+    end
+  endfunction
+
+  // AxiLite protocol flag vector      
+  function [C_NUM_M-1:0] f_m_axilite
+    (
+      input integer null_arg
+    );
+    integer mi;
+    begin
+      for (mi=0; mi<C_NUM_M; mi=mi+1) begin
+        f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
+      end
+    end
+  endfunction
+
+  // Convert Bit32 vector of range [0,1] to Bit1 vector on MI
+  function [C_NUM_M-1:0] f_bit32to1_mi
+    (input [C_NUM_M*32-1:0] vec32);
+    integer mi;
+    begin
+      for (mi=0; mi<C_NUM_M; mi=mi+1) begin
+        f_bit32to1_mi[mi] = vec32[mi*32];
+      end
+    end
+  endfunction
+  
+  wire [C_NUM_M-1:0] target_mi_hot;
+  wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
+  wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
+  wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
+  wire match;
+  wire [3:0] target_region;
+  wire [3:0] m_aregion_i;
+  wire m_avalid_i;
+  wire s_aready_i;
+  wire any_error;
+  wire s_rvalid_i;
+  wire [C_ID_WIDTH-1:0] s_rid_i;
+  wire s_rlast_i;
+  wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
+  wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
+  wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
+  wire [(C_NUM_M+1)-1:0] m_rready_arb;
+  wire [(C_NUM_M+1)-1:0] m_rready_i;
+  wire target_secure;
+  wire target_axilite;
+  wire m_avalid_qual_i;
+  wire [7:0] m_aerror_i;
+  
+  genvar gen_mi;
+  genvar gen_thread;
+    
+  generate
+    if (C_ADDR_DECODE) begin : gen_addr_decoder
+      axi_crossbar_v2_1_12_addr_decoder #
+        (
+          .C_FAMILY          (C_FAMILY),
+          .C_NUM_TARGETS     (C_NUM_M),
+          .C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
+          .C_NUM_RANGES      (C_NUM_ADDR_RANGES),
+          .C_ADDR_WIDTH      (C_ADDR_WIDTH),
+          .C_TARGET_ENC      (1),
+          .C_TARGET_HOT      (1),
+          .C_REGION_ENC      (1),
+          .C_BASE_ADDR      (C_BASE_ADDR),
+          .C_HIGH_ADDR      (C_HIGH_ADDR),
+          .C_TARGET_QUAL     (C_TARGET_QUAL),
+          .C_RESOLUTION      (2)
+        ) 
+        addr_decoder_inst 
+        (
+          .ADDR             (S_AADDR),        
+          .TARGET_HOT       (target_mi_hot),  
+          .TARGET_ENC       (target_mi_enc),  
+          .MATCH            (match),       
+          .REGION           (target_region)      
+        );
+    end else begin : gen_no_addr_decoder
+      assign target_mi_hot = 1;
+      assign target_mi_enc = 0;
+      assign match = 1\'b1;
+      assign target_region = 4\'b0000;
+    end
+  endgenerate
+  
+  assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
+  assign target_axilite = |(target_mi_hot & P_M_AXILITE);
+
+  assign any_error = C_RANGE_CHECK && (m_aerror_i != 0);            // DECERR if error-detection enabled and any error condition.
+  assign m_aerror_i[0] = ~match;                                    // Invalid target address
+  assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
+  assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) || 
+    (S_ASIZE[1:0] == 2\'b11) || (S_ASIZE[2] == 1\'b1));               // AxiLite access violation
+  assign m_aerror_i[7:3] = 5\'b00000;                                    // Reserved
+  assign M_ATARGET_HOT = m_atarget_hot_i;
+  assign m_atarget_hot_i = (any_error ? {1\'b1, {C_NUM_M{1\'b0}}} : {1\'b0, target_mi_hot});
+  assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
+    
+  assign M_AVALID = m_avalid_i;
+  assign m_avalid_i = S_AVALID;
+  assign M_AVALID_QUAL = m_avalid_qual_i; 
+  assign S_AREADY = s_aready_i;
+  assign s_aready_i = M_AREADY;
+  assign M_AERROR = m_aerror_i;
+  assign M_ATARGET_ENC = m_atarget_enc_i;
+  assign m_aregion_i = any_error ? 4\'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4\'b0000;
+//  assign m_aregion_i = any_error ? 4\'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
+  assign M_AREGION = m_aregion_i;
+  assign M_AID = S_AID;
+  assign M_AADDR = S_AADDR;
+  assign M_ALEN = S_ALEN;
+  assign M_ASIZE = S_ASIZE;
+  assign M_ALOCK = S_ALOCK;
+  assign M_APROT = S_APROT;
+  assign M_AMESG = S_AMESG;
+  
+  assign S_RVALID = s_rvalid_i;
+  assign M_RREADY = m_rready_i;
+  assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
+  assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
+  assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
+  assign S_RID = s_rid_i;
+  assign S_RLAST = s_rlast_i;
+  assign m_rvalid_qual = M_RVALID & M_RTARGET;
+  assign m_rready_i = m_rready_arb & M_RTARGET;
+
+  generate
+    for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
+      // Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
+      assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
+               M_RLAST[gen_mi],
+               M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
+               M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
+               };
+    end  // gen_rmesg_mi
+
+    if (C_ACCEPTANCE == 1) begin : gen_single_issue
+      wire  cmd_push;
+      wire  cmd_pop;
+      reg  [(C_NUM_M+1)-1:0] active_target_hot;
+      reg  [P_NUM_M_DE_LOG-1:0] active_target_enc;
+      reg  accept_cnt;
+      reg  [8-1:0] debug_r_beat_cnt_i;
+      wire [8-1:0] debug_r_trans_seq_i;
+
+      assign cmd_push = M_AREADY;
+      assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i;  // Pop command queue if end of read burst
+      assign m_avalid_qual_i = ~accept_cnt | cmd_pop;  // Ready for arbitration if no outstanding transaction or transaction being completed
+
+      always @(posedge ACLK) begin 
+        if (ARESET) begin
+          accept_cnt <= 1\'b0;
+          active_target_enc <= 0;
+          active_target_hot <= 0;
+        end else begin
+          if (cmd_push) begin
+            active_target_enc <= m_atarget_enc_i;
+            active_target_hot <= m_atarget_hot_i;
+            accept_cnt <= 1\'b1;
+          end else if (cmd_pop) begin
+            accept_cnt <= 1\'b0;
+          end
+        end 
+      end  // Clocked process
+        
+      assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
+      assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
+                 
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (C_FAMILY),
+         .C_RATIO       (C_NUM_M+1),
+         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),
+         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)
+        ) mux_resp_single_issue
+        (
+         .S   (active_target_enc),
+         .A   (mi_rmux_mesg),
+         .O   (si_rmux_mesg),
+         .OE  (1\'b1)
+        ); 
+        
+      if (C_DEBUG) begin : gen_debug_r_single_issue
+        // DEBUG READ BEAT COUNTER (only meaningful for R-channel)
+        always @(posedge ACLK) begin
+          if (ARESET) begin
+            debug_r_beat_cnt_i <= 0;
+          end else if (C_DIR == P_READ) begin
+            if (s_rvalid_i && S_RREADY) begin
+              if (s_rlast_i) begin
+                debug_r_beat_cnt_i <= 0;
+              end else begin
+                debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
+              end
+            end
+          end else begin
+            debug_r_beat_cnt_i <= 0;            
+          end
+        end  // Clocked process
+        
+        // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
+        axi_data_fifo_v2_1_10_axic_srl_fifo #
+          (
+           .C_FAMILY          (C_FAMILY),
+           .C_FIFO_WIDTH      (8),
+           .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),
+           .C_USE_FULL        (0)
+           )
+          debug_r_seq_fifo_single_issue
+            (
+             .ACLK    (ACLK),
+             .ARESET  (ARESET),
+             .S_MESG  (DEBUG_A_TRANS_SEQ),
+             .S_VALID (cmd_push),
+             .S_READY (),
+             .M_MESG  (debug_r_trans_seq_i),
+             .M_VALID (),
+             .M_READY (cmd_pop)
+            );
+            
+      end  // gen_debug_r
+      
+    end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
+      wire  s_avalid_en;
+      wire  cmd_push;
+      wire  cmd_pop;
+      reg  [C_ID_WIDTH-1:0] active_id;
+      reg  [(C_NUM_M+1)-1:0] active_target_hot;
+      reg  [P_NUM_M_DE_LOG-1:0] active_target_enc;
+      reg  [4-1:0] active_region;
+      reg  [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
+      reg  [8-1:0] debug_r_beat_cnt_i;
+      wire [8-1:0] debug_r_trans_seq_i;
+      wire accept_limit ;
+
+      // Implement single-region-per-ID cyclic dependency avoidance method.
+      assign s_avalid_en =  // This transaction is qualified to request arbitration if ...
+        (accept_cnt == 0) ||  // Either there are no outstanding transactions, or ...
+        (((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) &&  // the current transaction ID matches the previous, and ...
+        (active_target_enc == m_atarget_enc_i) &&  // all outstanding transactions are to the same target MI ...
+        (active_region == m_aregion_i));  // and to the same REGION.
+      
+      assign cmd_push = M_AREADY;
+      assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i;  // Pop command queue if end of read burst
+      assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop;  // Allow next push if a transaction is currently being completed
+      assign m_avalid_qual_i = s_avalid_en & ~accept_limit; 
+      
+      always @(posedge ACLK) begin 
+        if (ARESET) begin
+          accept_cnt <= 0;
+          active_id <= 0;
+          active_target_enc <= 0;
+          active_target_hot <= 0;
+          active_region <= 0;
+        end else begin
+          if (cmd_push) begin
+            active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
+            active_target_enc <= m_atarget_enc_i;
+            active_target_hot <= m_atarget_hot_i;
+            active_region <= m_aregion_i;
+            if (~cmd_pop) begin
+              accept_cnt <= accept_cnt + 1;
+            end
+          end else begin
+            if (cmd_pop & (accept_cnt != 0)) begin
+              accept_cnt <= accept_cnt - 1;
+            end
+          end
+        end 
+      end  // Clocked process
+        
+      assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
+      assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
+                 
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (C_FAMILY),
+         .C_RATIO       (C_NUM_M+1),
+         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),
+         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)
+        ) mux_resp_single_thread
+        (
+         .S   (active_target_enc),
+         .A   (mi_rmux_mesg),
+         .O   (si_rmux_mesg),
+         .OE  (1\'b1)
+        ); 
+        
+      if (C_DEBUG) begin : gen_debug_r_single_thread
+        // DEBUG READ BEAT COUNTER (only meaningful for R-channel)
+        always @(posedge ACLK) begin
+          if (ARESET) begin
+            debug_r_beat_cnt_i <= 0;
+          end else if (C_DIR == P_READ) begin
+            if (s_rvalid_i && S_RREADY) begin
+              if (s_rlast_i) begin
+                debug_r_beat_cnt_i <= 0;
+              end else begin
+                debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
+              end
+            end
+          end else begin
+            debug_r_beat_cnt_i <= 0;            
+          end
+        end  // Clocked process
+        
+        // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
+        axi_data_fifo_v2_1_10_axic_srl_fifo #
+          (
+           .C_FAMILY          (C_FAMILY),
+           .C_FIFO_WIDTH      (8),
+           .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),
+           .C_USE_FULL        (0)
+           )
+          debug_r_seq_fifo_single_thread
+            (
+             .ACLK    (ACLK),
+             .ARESET  (ARESET),
+             .S_MESG  (DEBUG_A_TRANS_SEQ),
+             .S_VALID (cmd_push),
+             .S_READY (),
+             .M_MESG  (debug_r_trans_seq_i),
+             .M_VALID (),
+             .M_READY (cmd_pop)
+            );
+            
+      end  // gen_debug_r
+      
+    end else begin : gen_multi_thread
+      wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
+      reg  [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
+      wire [P_NUM_THREADS-1:0] s_avalid_en;
+      wire [P_NUM_THREADS-1:0] thread_valid;
+      wire [P_NUM_THREADS-1:0] aid_match;
+      wire [P_NUM_THREADS-1:0] rid_match;
+      wire [P_NUM_THREADS-1:0] cmd_push;
+      wire [P_NUM_THREADS-1:0] cmd_pop;
+      wire [P_NUM_THREADS:0]   accum_push;
+      reg  [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
+      reg  [P_NUM_THREADS*8-1:0] active_target;
+      reg  [P_NUM_THREADS*8-1:0] active_region;
+      reg  [P_NUM_THREADS*8-1:0] active_cnt;
+      reg  [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
+      wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
+      wire any_aid_match;
+      wire any_rid_match;
+      wire accept_limit;
+      wire any_push;
+      wire any_pop;
+        
+      axi_crossbar_v2_1_12_arbiter_resp #  // Multi-thread response arbiter
+        (
+         .C_FAMILY                (C_FAMILY),
+         .C_NUM_S                 (C_NUM_M+1),
+         .C_NUM_S_LOG             (P_NUM_M_DE_LOG),
+         .C_GRANT_ENC            (1),
+         .C_GRANT_HOT            (0)
+         )
+        arbiter_resp_inst
+          (
+           .ACLK                  (ACLK),
+           .ARESET                (ARESET),
+           .S_VALID               (m_rvalid_qual),
+           .S_READY               (m_rready_arb),
+           .M_GRANT_HOT           (),
+           .M_GRANT_ENC           (resp_select),
+           .M_VALID               (s_rvalid_i),
+           .M_READY               (S_RREADY)
+           );
+                 
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (C_FAMILY),
+         .C_RATIO       (C_NUM_M+1),
+         .C_SEL_WIDTH   (P_NUM_M_DE_LOG),
+         .C_DATA_WIDTH  (P_RMUX_MESG_WIDTH)
+        ) mux_resp_multi_thread
+        (
+         .S   (resp_select),
+         .A   (mi_rmux_mesg),
+         .O   (si_rmux_mesg),
+         .OE  (1\'b1)
+        ); 
+        
+      assign any_push = M_AREADY;
+      assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
+      assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop;  // Allow next push if a transaction is currently being completed
+        assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit;  // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
+        assign any_aid_match = |aid_match;
+        assign any_rid_match = |rid_match;
+        assign accum_push[0] = 1\'b0;
+        
+        always @(posedge ACLK) begin
+          if (ARESET) begin
+            accept_cnt <= 0; 
+          end else begin
+            if (any_push & ~any_pop) begin
+              accept_cnt <= accept_cnt + 1;
+          end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
+              accept_cnt <= accept_cnt - 1;
+            end
+          end 
+        end  // Clocked process
+          
+        for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
+          assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
+          assign aid_match[gen_thread] =  // The currect thread is active for the requested transaction if
+            thread_valid[gen_thread] &&  // this thread slot is not vacant, and
+          ((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);  // the requested ID matches the active ID for this thread.
+          assign s_avalid_en[gen_thread] =  // The current request is qualified against this thread slot if
+            (~aid_match[gen_thread]) ||  // This thread slot is not active for the requested ID, or
+            ((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) &&  // this outstanding transaction was to the same target and
+            (m_aregion_i == active_region[gen_thread*8+:4'b']));  // to the same region.
+          
+          // cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
+          assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
+          assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
+          
+          // cmd_pop points to the position of the active thread that matches the current RID.
+        assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
+          assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
+        
+          always @(posedge ACLK) begin
+            if (ARESET) begin
+              active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
+              active_target[gen_thread*8+:8] <= 0;
+              active_region[gen_thread*8+:8] <= 0;
+              active_cnt[gen_thread*8+:8] <= 0; 
+            end else begin
+              if (cmd_push[gen_thread]) begin
+              active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
+                active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
+                active_region[gen_thread*8+:4] <= m_aregion_i;
+                if (~cmd_pop[gen_thread]) begin
+                  active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
+                end
+              end else if (cmd_pop[gen_thread]) begin
+                  active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
+              end
+            end 
+          end  // Clocked process
+            
+        if (C_DEBUG) begin : gen_debug_r_multi_thread
+            // DEBUG READ BEAT COUNTER (only meaningful for R-channel)
+            always @(posedge ACLK) begin
+              if (ARESET) begin
+                debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
+              end else if (C_DIR == P_READ) begin
+                if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
+                  if (s_rlast_i) begin
+                    debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
+                  end else begin
+                    debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
+                  end
+                end
+              end else begin
+                debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;            
+              end
+            end  // Clocked process
+            
+            // DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
+            axi_data_fifo_v2_1_10_axic_srl_fifo #
+              (
+               .C_FAMILY          (C_FAMILY),
+               .C_FIFO_WIDTH      (8),
+               .C_FIFO_DEPTH_LOG  (C_ACCEPTANCE_LOG+1),
+               .C_USE_FULL        (0)
+               )
+            debug_r_seq_fifo_multi_thread
+                (
+                 .ACLK    (ACLK),
+                 .ARESET  (ARESET),
+                 .S_MESG  (DEBUG_A_TRANS_SEQ),
+                 .S_VALID (cmd_push[gen_thread]),
+                 .S_READY (),
+                 .M_MESG  (debug_r_trans_seq_i[gen_thread*8+:8]),
+                 .M_VALID (),
+                 .M_READY (cmd_pop[gen_thread])
+                );
+        end  // gen_debug_r_multi_thread
+      end  // Next gen_thread_loop
+            
+    end  // thread control
+        
+  endgenerate
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: AXI Splitter
+// Each transfer received on the AXI handshake slave port is replicated onto 
+//   each of the master ports, and is completed back to the slave (S_READY) 
+//   once all master ports have completed.
+//   
+// M_VALID is asserted combinatorially from S_VALID assertion.
+// Each M_VALID is masked off beginning the cycle after each M_READY is
+//   received (if S_READY remains low) until the cycle after both S_VALID
+//   and S_READY are asserted.
+// S_READY is asserted combinatorially when the last (or all) of the M_READY
+//   inputs have been received.
+// If all M_READYs are asserted when S_VALID is asserted, back-to-back
+//   handshakes can occur without bubble cycles.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   splitter
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_splitter #
+  (
+   parameter integer C_NUM_M = 2  // Number of master ports = [2:16]
+   )
+  (
+   // Global Signals
+   input  wire                             ACLK,
+   input  wire                             ARESET,
+   // Slave  Port
+   input  wire                             S_VALID,
+   output wire                             S_READY,
+   // Master Ports
+   output wire [C_NUM_M-1:0]               M_VALID,
+   input  wire [C_NUM_M-1:0]               M_READY
+   );
+
+   reg  [C_NUM_M-1:0] m_ready_d;
+   wire               s_ready_i;
+   wire [C_NUM_M-1:0] m_valid_i;
+
+   always @(posedge ACLK) begin
+      if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1\'b0}};
+      else                    m_ready_d <= m_ready_d | (m_valid_i & M_READY);
+   end
+
+   assign s_ready_i = &(m_ready_d | M_READY);
+   assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;
+   assign M_VALID = m_valid_i;
+   assign S_READY = s_ready_i;
+
+endmodule
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: wdata_mux.v
+//
+// Description: 
+//   Contains MI-side write command queue.
+//   SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
+//   Queue is popped when WLAST data beat is transferred.
+//   W-channel input from SI-slot selected by queue output is transferred to MI-side output .
+//--------------------------------------------------------------------------
+//
+// Structure:
+//    wdata_mux
+//      axic_reg_srl_fifo
+//      mux_enc
+//      
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_wdata_mux #
+  (
+   parameter         C_FAMILY       = ""none"", // FPGA Family.
+   parameter integer C_WMESG_WIDTH            =  1, // Width of W-channel payload.
+   parameter integer C_NUM_SLAVE_SLOTS     =  1, // Number of S_* ports.
+   parameter integer C_SELECT_WIDTH      =  1, // Width of ASELECT.
+   parameter integer C_FIFO_DEPTH_LOG     =  0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
+   )
+  (
+   // System Signals
+   input  wire                                        ACLK,
+   input  wire                                        ARESET,
+   // Slave Data Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0]     S_WMESG,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                S_WLAST,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                S_WVALID,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                S_WREADY,
+   // Master Data Ports
+   output wire [C_WMESG_WIDTH-1:0]                       M_WMESG,
+   output wire                                        M_WLAST,
+   output wire                                        M_WVALID,
+   input  wire                                        M_WREADY,
+   // Write Command Ports
+   input  wire [C_SELECT_WIDTH-1:0]                 S_ASELECT,  // SI-slot index from AW arbiter
+   input  wire                                        S_AVALID,
+   output wire                                        S_AREADY
+   );
+
+  localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5;  // Max depth = 32
+  
+  // Decode select input to 1-hot
+  function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
+      input [C_SELECT_WIDTH-1:0] sel
+    );
+    integer i;
+    begin
+      for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
+        f_decoder[i] = (sel == i);
+      end
+    end
+  endfunction
+
+  wire                                          m_valid_i;
+  wire                                          m_last_i;
+  wire [C_NUM_SLAVE_SLOTS-1:0]             m_select_hot;
+  wire [C_SELECT_WIDTH-1:0]                 m_select_enc;
+  wire                                          m_avalid;
+  wire                                          m_aready;
+  
+  generate
+    if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
+      // SI-side write command queue
+      axi_data_fifo_v2_1_10_axic_reg_srl_fifo #
+        (
+         .C_FAMILY          (C_FAMILY),
+         .C_FIFO_WIDTH      (C_SELECT_WIDTH),
+         .C_FIFO_DEPTH_LOG  (P_FIFO_DEPTH_LOG),
+         .C_USE_FULL        (0)
+         )
+        wmux_aw_fifo
+          (
+           .ACLK    (ACLK),
+           .ARESET  (ARESET),
+           .S_MESG  (S_ASELECT),
+           .S_VALID (S_AVALID),
+           .S_READY (S_AREADY),
+           .M_MESG  (m_select_enc),
+           .M_VALID (m_avalid),
+           .M_READY (m_aready)
+           );
+    
+      assign m_select_hot = f_decoder(m_select_enc);
+      
+      // Instantiate MUX
+      generic_baseblocks_v2_1_0_mux_enc # 
+        (
+         .C_FAMILY      (""rtl""),
+         .C_RATIO       (C_NUM_SLAVE_SLOTS),
+         .C_SEL_WIDTH   (C_SELECT_WIDTH),
+         .C_DATA_WIDTH  (C_WMESG_WIDTH)
+        ) mux_w 
+        (
+         .S   (m_select_enc),
+         .A   (S_WMESG),
+         .O   (M_WMESG),
+         .OE  (1\'b1)
+        ); 
+        
+      assign m_last_i  = |(S_WLAST & m_select_hot);
+      assign m_valid_i = |(S_WVALID & m_select_hot);
+      
+      assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
+      assign M_WLAST = m_last_i;
+      assign M_WVALID = m_valid_i & m_avalid;
+      assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
+    end else begin : gen_no_wmux
+      assign S_AREADY = 1\'b1;
+      assign M_WVALID = S_WVALID;
+      assign S_WREADY = M_WREADY;
+      assign M_WLAST = S_WLAST;
+      assign M_WMESG = S_WMESG;
+    end
+  endgenerate
+  
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: wdata_router.v
+//
+// Description: 
+//   Contains SI-side write command queue.
+//   Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
+//   Queue is popped when WLAST data beat is transferred.
+//   W-channel input is transferred to MI-slot output selected by queue output.
+//--------------------------------------------------------------------------
+//
+// Structure:
+//    wdata_router
+//      axic_reg_srl_fifo
+//      
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_wdata_router #
+  (
+   parameter         C_FAMILY       = ""none"", // FPGA Family.
+   parameter integer C_WMESG_WIDTH          = 1, // Width of all data signals
+   parameter integer C_NUM_MASTER_SLOTS     = 1, // Number of M_* ports.
+   parameter integer C_SELECT_WIDTH     =  1, // Width of S_ASELECT.
+   parameter integer C_FIFO_DEPTH_LOG     =  0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
+   )
+  (
+   // System Signals
+   input  wire                                        ACLK,
+   input  wire                                        ARESET,
+   // Slave Data Ports
+   input  wire [C_WMESG_WIDTH-1:0]                    S_WMESG,
+   input  wire                                        S_WLAST,
+   input  wire                                        S_WVALID,
+   output wire                                        S_WREADY,
+   // Master Data Ports
+   output wire [C_WMESG_WIDTH-1:0]                    M_WMESG,  // Broadcast to all MI-slots
+   output wire                                        M_WLAST,  // Broadcast to all MI-slots
+   output wire [C_NUM_MASTER_SLOTS-1:0]               M_WVALID,  // Per MI-slot
+   input  wire [C_NUM_MASTER_SLOTS-1:0]               M_WREADY,  // Per MI-slot
+   // Address Arbiter Ports
+   input  wire [C_SELECT_WIDTH-1:0]                   S_ASELECT,  // Target MI-slot index from SI-side AW command
+   input  wire                                        S_AVALID,
+   output wire                                        S_AREADY
+   );
+
+  localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5;  // Max depth = 32
+
+  // Decode select input to 1-hot
+  function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
+      input [C_SELECT_WIDTH-1:0] sel
+    );
+    integer i;
+    begin
+      for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
+        f_decoder[i] = (sel == i);
+      end
+    end
+  endfunction
+
+  //---------------------------------------------------------------------------
+  // Internal signal declarations
+  //---------------------------------------------------------------------------
+  wire [C_NUM_MASTER_SLOTS-1:0]             m_select_hot;
+  wire [C_SELECT_WIDTH-1:0]                 m_select_enc;
+  wire                                          m_avalid;
+  wire                                          m_aready;
+  
+  //---------------------------------------------------------------------------
+  // Router
+  //---------------------------------------------------------------------------
+
+  // SI-side write command queue
+  axi_data_fifo_v2_1_10_axic_reg_srl_fifo #
+    (
+     .C_FAMILY          (C_FAMILY),
+     .C_FIFO_WIDTH      (C_SELECT_WIDTH),
+     .C_FIFO_DEPTH_LOG  (P_FIFO_DEPTH_LOG),
+     .C_USE_FULL        (1)
+     )
+    wrouter_aw_fifo
+      (
+       .ACLK    (ACLK),
+       .ARESET  (ARESET),
+       .S_MESG  (S_ASELECT),
+       .S_VALID (S_AVALID),
+       .S_READY (S_AREADY),
+       .M_MESG  (m_select_enc),
+       .M_VALID (m_avalid),
+       .M_READY (m_aready)
+       );
+
+  assign m_select_hot = f_decoder(m_select_enc);
+  
+  // W-channel payload and LAST are broadcast to all MI-slot\'s W-mux
+  assign M_WMESG   = S_WMESG;
+  assign M_WLAST =   S_WLAST;
+  
+  // Assert m_aready when last beat acknowledged by slave
+  assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
+
+  // M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
+  // The slot selected by the head of the queue (m_select_enc) is enabled.
+  assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
+
+  // S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
+  assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
+  
+endmodule
+
+`default_nettype wire
+
+
+// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// File name: axi_crossbar.v
+//-----------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings=""yes"" *) 
+module axi_crossbar_v2_1_12_axi_crossbar # (
+   parameter         C_FAMILY                         = ""rtl"", 
+                       // FPGA Base Family. Current version: virtex6 or spartan6.
+   parameter integer C_NUM_SLAVE_SLOTS                = 1, 
+                       // Number of Slave Interface (SI) slots for connecting 
+                       // to master IP. Range: 1-16.
+   parameter integer C_NUM_MASTER_SLOTS               = 2, 
+                       // Number of Master Interface (MI) slots for connecting 
+                       // to slave IP. Range: 1-16.                       
+   parameter integer C_AXI_ID_WIDTH                   = 1, 
+                       // Width of ID signals propagated by the Interconnect.
+                       // Width of ID signals produced on all MI slots.
+                       // Range: 1-32.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32, 
+                       // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and 
+                       // m_axi_araddr for all SI/MI slots.
+                       // Range: 1-64.
+   parameter integer C_AXI_DATA_WIDTH        = 32, 
+                       // Data width of the internal interconnect write and read 
+                       // data paths.
+                       // Range: 32, 64, 128, 256, 512, 1024.
+   parameter integer C_AXI_PROTOCOL                 = 0, 
+                       // 0 = ""AXI4"",
+                       // 1 = ""AXI3"", 
+                       // 2 = ""AXI4LITE""
+                       //   Propagate WID only when C_AXI_PROTOCOL = 1.
+   parameter integer C_NUM_ADDR_RANGES = 1,
+                       // Number of BASE/HIGH_ADDR pairs per MI slot.
+                       // Range: 1-16.
+   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128\'h00000000001000000000000000000000,
+                       // Base address of each range of each MI slot. 
+                       // For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1\'b1}}. 
+                       //   (Bit positions above C_AXI_ADDR_WIDTH are ignored.)
+                       // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.
+   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64\'H0000000c0000000c, 
+                       // Number of low-order address bits that are used to select locations within each address range of each MI slot.
+                       // The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.
+                       // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.
+                       // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32\'h00000000.
+                       // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.
+                       // Range: 0 - C_AXI_ADDR_WIDTH.
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32\'h00000000,
+                       // Base ID of each SI slot. 
+                       // Format: C_NUM_SLAVE_SLOTS{Bit32};
+                       // Range: 0 to 2**C_AXI_ID_WIDTH-1.
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32\'h00000000,
+                       // Number of low-order ID bits a connected master may vary to select a transaction thread.
+                       // Format: C_NUM_SLAVE_SLOTS{Bit32};
+                       // Range: 0 - C_AXI_ID_WIDTH.
+   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,
+                       // 1 = Propagate all USER signals, 0 = Dont propagate.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals for all SI slots and MI slots. 
+                       // Range: 1-1024.
+   parameter integer C_AXI_ARUSER_WIDTH               = 1,
+                       // Width of ARUSER signals for all SI slots and MI slots. 
+                       // Range: 1-1024.
+   parameter integer C_AXI_WUSER_WIDTH                = 1,
+                       // Width of WUSER signals for all SI slots and MI slots. 
+                       // Range: 1-1024.
+   parameter integer C_AXI_RUSER_WIDTH                = 1,
+                       // Width of RUSER signals for all SI slots and MI slots. 
+                       // Range: 1-1024.
+   parameter integer C_AXI_BUSER_WIDTH                = 1,
+                       // Width of BUSER signals for all SI slots and MI slots. 
+                       // Range: 1-1024.
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64\'hFFFFFFFFFFFFFFFF,
+                       // Multi-pathway write connectivity from each SI slot (N) to each 
+                       // MI slot (M):
+                       // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
+                       // Format: C_NUM_MASTER_SLOTS{Bit32}; 
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64\'hFFFFFFFFFFFFFFFF,
+                       // Multi-pathway read connectivity from each SI slot (N) to each 
+                       // MI slot (M):
+                       // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
+                       // Format: C_NUM_MASTER_SLOTS{Bit32}; 
+   parameter integer C_R_REGISTER               = 0,
+                       // Insert register slice on R channel in the crossbar. (Valid only for SASD)
+                       // Range: Reg-slice type (0-8).
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD                 = 32\'h00000000, 
+                       // 0 = Implement separate command queues per ID thread.
+                       // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
+                       // Format: C_NUM_SLAVE_SLOTS{Bit32}; 
+                       // Range: 0, 1
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE         = 32\'H00000002,
+                       // Maximum number of active write transactions that each SI 
+                       // slot can accept. (Valid only for SAMD)
+                       // Format: C_NUM_SLAVE_SLOTS{Bit32}; 
+                       // Range: 1-32.
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE          = 32\'H00000002,
+                       // Maximum number of active read transactions that each SI 
+                       // slot can accept. (Valid only for SAMD)
+                       // Format: C_NUM_SLAVE_SLOTS{Bit32};
+                       // Range: 1-32.
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING            = 64\'H0000000400000004,
+                       // Maximum number of data-active write transactions that 
+                       // each MI slot can generate at any one time. (Valid only for SAMD)
+                       // Format: C_NUM_MASTER_SLOTS{Bit32};
+                       // Range: 1-32.
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING            = 64\'H0000000400000004,
+                       // Maximum number of active read transactions that 
+                       // each MI slot can generate at any one time. (Valid only for SAMD)
+                       // Format: C_NUM_MASTER_SLOTS{Bit32};
+                       // Range: 1-32.
+   parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY             = 32\'h00000000,
+                       // Arbitration priority among each SI slot. 
+                       // Higher values indicate higher priority.
+                       // Format: C_NUM_SLAVE_SLOTS{Bit32};
+                       // Range: 0-15.
+   parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE                   = 32\'h00000000,
+                       // Indicates whether each MI slot connects to a secure slave 
+                       // (allows only TrustZone secure access).
+                       // Format: C_NUM_MASTER_SLOTS{Bit32}.
+                       // Range: 0, 1
+   parameter integer C_CONNECTIVITY_MODE = 1
+                       // 0 = Shared-Address Shared-Data (SASD).
+                       // 1 = Shared-Address Multi-Data (SAMD).
+                       // Default 1 (on) for simulation; default 0 (off) for implementation.
+)
+(
+   // Global Signals
+   input  wire                                                    aclk,
+   input  wire                                                    aresetn,
+   // Slave Interface Write Address Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_awid,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           s_axi_awaddr,
+   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_awsize,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_awburst,
+   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awcache,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_awprot,
+//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awregion,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_awqos,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]         s_axi_awuser,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_awvalid,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_awready,
+   // Slave Interface Write Data Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_wid,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]           s_axi_wdata,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]         s_axi_wstrb,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wlast,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]          s_axi_wuser,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wvalid,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_wready,
+   // Slave Interface Write Response Ports
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_bid,
+   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_bresp,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]          s_axi_buser,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_bvalid,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_bready,
+   // Slave Interface Read Address Ports
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_arid,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]           s_axi_araddr,
+   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_arsize,
+   input  wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_arburst,
+   input  wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arcache,
+   input  wire [C_NUM_SLAVE_SLOTS*3-1:0]                          s_axi_arprot,
+//   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arregion,
+   input  wire [C_NUM_SLAVE_SLOTS*4-1:0]                          s_axi_arqos,
+   input  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]         s_axi_aruser,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_arvalid,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_arready,
+   // Slave Interface Read Data Ports
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]             s_axi_rid,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]           s_axi_rdata,
+   output wire [C_NUM_SLAVE_SLOTS*2-1:0]                          s_axi_rresp,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rlast,
+   output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]          s_axi_ruser,
+   output wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rvalid,
+   input  wire [C_NUM_SLAVE_SLOTS-1:0]                            s_axi_rready,
+   // Master Interface Write Address Port
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_awid,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          m_axi_awaddr,
+   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_awsize,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_awburst,
+   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awcache,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_awprot,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awregion,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_awqos,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]        m_axi_awuser,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_awvalid,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_awready,
+   // Master Interface Write Data Ports
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_wid,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]          m_axi_wdata,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]        m_axi_wstrb,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wlast,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]         m_axi_wuser,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wvalid,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_wready,
+   // Master Interface Write Response Ports
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_bid,
+   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_bresp,
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]         m_axi_buser,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_bvalid,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_bready,
+   // Master Interface Read Address Port
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_arid,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]          m_axi_araddr,
+   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_arsize,
+   output wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_arburst,
+   output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arcache,
+   output wire [C_NUM_MASTER_SLOTS*3-1:0]                         m_axi_arprot,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arregion,
+   output wire [C_NUM_MASTER_SLOTS*4-1:0]                         m_axi_arqos,
+   output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]        m_axi_aruser,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_arvalid,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_arready,
+   // Master Interface Read Data Ports
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]            m_axi_rid,
+   input  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]          m_axi_rdata,
+   input  wire [C_NUM_MASTER_SLOTS*2-1:0]                         m_axi_rresp,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rlast,
+   input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]          m_axi_ruser,
+   input  wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rvalid,
+   output wire [C_NUM_MASTER_SLOTS-1:0]                           m_axi_rready
+);
+
+  localparam [64:0] P_ONES = {65{1\'b1}};
+  localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);
+  localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);
+  localparam integer  P_AXI4 = 0;
+  localparam integer  P_AXI3 = 1;
+  localparam integer  P_AXILITE = 2;
+  localparam [2:0]   P_AXILITE_SIZE = 3\'b010;
+  localparam [1:0]   P_INCR = 2\'b01;
+  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);
+  localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);
+  localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);
+  localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);
+  localparam integer C_DEBUG              = 1;
+  localparam integer P_RANGE_CHECK                    = 1;
+                       // 1 (non-zero) = Detect and issue DECERR on the following conditions:
+                       //   a. address range mismatch (no valid MI slot)
+                       //   b. Burst or >32-bit transfer to AxiLite slave
+                       //   c. TrustZone access violation
+                       //   d. R/W direction unsupported by target
+                       // 0 = Pass all transactions (no DECERR):
+                       //   a. Omit DECERR detection and response logic
+                       //   b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION
+                       //      when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.
+                       //   c. Unpredictable target MI-slot if address mismatch and >1 MI-slot
+                       //   d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave
+                       // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.
+  localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0;  // Always 1
+  localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE            = {C_NUM_MASTER_SLOTS{32\'h00000000}};
+                       // Transaction error detection (per MI-slot)
+                       // 0 = None; 1 = AXI4Lite burst violation
+                       // Format: C_NUM_MASTER_SLOTS{Bit32};
+  localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;
+  localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;
+  localparam P_FAMILY = ((C_FAMILY == ""virtex7"") || (C_FAMILY == ""kintex7"") || (C_FAMILY == ""artix7"") || (C_FAMILY == ""zynq"")) ? C_FAMILY : ""rtl"";
+
+  function integer f_ceil_log2
+    (
+     input integer x
+     );
+    integer acc;
+    begin
+      acc=0;
+      while ((2**acc) < x)
+        acc = acc + 1;
+      f_ceil_log2 = acc;
+    end
+  endfunction
+
+  // Widths of all write issuance counters implemented in axi_crossbar_v2_1_12_crossbar (before counter carry-out bit)
+  function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec
+    (input null_arg);
+    integer mi;
+    reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
+    begin
+      result = 0;
+      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
+        result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32\'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);
+      end
+      result[C_NUM_MASTER_SLOTS*32+:32] = 32\'h0;
+      f_write_issue_width_vec = result;
+    end
+  endfunction
+
+  // Widths of all read issuance counters implemented in axi_crossbar_v2_1_12_crossbar (before counter carry-out bit)
+  function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec
+    (input null_arg);
+    integer mi;
+    reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
+    begin
+      result = 0;
+      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
+        result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32\'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);
+      end
+      result[C_NUM_MASTER_SLOTS*32+:32] = 32\'h0;
+      f_read_issue_width_vec = result;
+    end
+  endfunction
+
+  // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_12_crossbar (before counter carry-out bit)
+  function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec
+    (input null_arg);
+    integer si;
+    reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
+    begin
+      result = 0;
+      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
+        result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32\'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);
+      end
+      f_write_accept_width_vec = result;
+    end
+  endfunction
+
+  // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_12_crossbar (before counter carry-out bit)
+  function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec
+    (input null_arg);
+    integer si;
+    reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
+    begin
+      result = 0;
+      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
+        result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32\'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);
+      end
+      f_read_accept_width_vec = result;
+    end
+  endfunction
+
+  // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format
+  function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id
+    (input null_arg);
+    integer si;
+    reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
+    begin
+      result = 0;
+      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
+        result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];
+      end
+      f_base_id = result;
+    end
+  endfunction
+
+  // Construct P_S_HIGH_ID vector
+  function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id
+    (input null_arg);
+    integer si;
+    reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
+    begin
+      result = 0;
+      for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
+        result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
+          ({1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1\'b1}} :
+          (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
+      end
+      f_high_id = result;
+    end
+  endfunction
+
+  // Construct P_M_HIGH_ADDR vector
+  function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr
+    (input null_arg);
+    integer ar;
+    reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;
+    begin
+      result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1\'b0}};
+      for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin
+        result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64\'h00000000_00000000 : 
+          ({1\'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1\'b1}} :
+          (C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1\'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));
+      end
+      f_high_addr = result;
+    end
+  endfunction
+
+  // Generate a mask of valid ID bits for a given SI slot.
+  function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask
+    (input integer si);
+    begin
+      f_thread_id_mask = 
+        (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1\'b0}} : 
+        ({1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1\'b1}} :
+        ({C_AXI_ID_WIDTH{1\'b0}} | ~(P_ONES << {1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
+      end
+  endfunction
+
+  // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value
+  //   only for end-point SI-slots
+  function [C_AXI_ID_WIDTH-1:0] f_extend_ID (
+    input [C_AXI_ID_WIDTH-1:0] s_id,
+    input integer si
+    );
+    begin
+      f_extend_ID = 
+        (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] : 
+        ({1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :
+        (C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id &  ~(P_ONES << {1\'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));
+    end
+  endfunction
+
+  // Bit vector of SI slots with at least one write connection.
+  function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write
+    (input null_arg);
+    integer mi;
+    reg [C_NUM_SLAVE_SLOTS-1:0] result;
+    begin
+      result = {C_NUM_SLAVE_SLOTS{1\'b0}};
+      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
+        result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
+      end
+      f_s_supports_write = result;
+    end
+  endfunction
+
+  // Bit vector of SI slots with at least one read connection.
+  function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read
+    (input null_arg);
+    integer mi;
+    reg [C_NUM_SLAVE_SLOTS-1:0] result;
+    begin
+      result = {C_NUM_SLAVE_SLOTS{1\'b0}};
+      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
+        result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
+      end
+      f_s_supports_read = result;
+    end
+  endfunction
+
+  // Bit vector of MI slots with at least one write connection.
+  function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write
+    (input null_arg);
+    integer mi;
+    begin
+      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
+        f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
+      end
+    end
+  endfunction
+
+  // Bit vector of MI slots with at least one read connection.
+  function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read
+    (input null_arg);
+    integer mi;
+    begin
+      for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
+        f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
+      end
+    end
+  endfunction
+
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_awid            ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]        si_cb_awaddr          ;
+  wire [C_NUM_SLAVE_SLOTS*8-1:0]                       si_cb_awlen           ;
+  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_awsize          ;
+  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_awburst         ;
+  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_awlock          ;
+  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awcache         ;
+  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_awprot          ;
+//  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awregion        ;
+  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_awqos           ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0]      si_cb_awuser          ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_awvalid         ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_awready         ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_wid            ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]        si_cb_wdata           ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0]      si_cb_wstrb           ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wlast           ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0]       si_cb_wuser           ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wvalid          ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_wready          ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_bid             ;
+  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_bresp           ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0]       si_cb_buser           ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_bvalid          ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_bready          ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_arid            ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0]        si_cb_araddr          ;
+  wire [C_NUM_SLAVE_SLOTS*8-1:0]                       si_cb_arlen           ;
+  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_arsize          ;
+  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_arburst         ;
+  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_arlock          ;
+  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arcache         ;
+  wire [C_NUM_SLAVE_SLOTS*3-1:0]                       si_cb_arprot          ;
+//  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arregion        ;
+  wire [C_NUM_SLAVE_SLOTS*4-1:0]                       si_cb_arqos           ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0]      si_cb_aruser          ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_arvalid         ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_arready         ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0]          si_cb_rid             ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0]        si_cb_rdata           ;
+  wire [C_NUM_SLAVE_SLOTS*2-1:0]                       si_cb_rresp           ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rlast           ;
+  wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0]       si_cb_ruser           ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rvalid          ;
+  wire [C_NUM_SLAVE_SLOTS-1:0]                         si_cb_rready          ;
+
+  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_awid            ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]       cb_mi_awaddr          ;
+  wire [C_NUM_MASTER_SLOTS*8-1:0]                      cb_mi_awlen           ;
+  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_awsize          ;
+  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_awburst         ;
+  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_awlock          ;
+  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awcache         ;
+  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_awprot          ;
+  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awregion        ;
+  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_awqos           ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0]     cb_mi_awuser          ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_awvalid         ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_awready         ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_wid             ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]       cb_mi_wdata           ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0]     cb_mi_wstrb           ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wlast           ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0]      cb_mi_wuser           ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wvalid          ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_wready          ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_bid             ;
+  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_bresp           ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0]      cb_mi_buser           ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_bvalid          ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_bready          ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_arid            ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0]       cb_mi_araddr          ;
+  wire [C_NUM_MASTER_SLOTS*8-1:0]                      cb_mi_arlen           ;
+  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_arsize          ;
+  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_arburst         ;
+  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_arlock          ;
+  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arcache         ;
+  wire [C_NUM_MASTER_SLOTS*3-1:0]                      cb_mi_arprot          ;
+  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arregion        ;
+  wire [C_NUM_MASTER_SLOTS*4-1:0]                      cb_mi_arqos           ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0]     cb_mi_aruser          ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_arvalid         ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_arready         ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0]         cb_mi_rid             ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0]       cb_mi_rdata           ;
+  wire [C_NUM_MASTER_SLOTS*2-1:0]                      cb_mi_rresp           ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rlast           ;
+  wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0]      cb_mi_ruser           ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rvalid          ;
+  wire [C_NUM_MASTER_SLOTS-1:0]                        cb_mi_rready          ;
+  
+  genvar slot;
+
+generate
+    for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff
+      assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))              : 0 ;
+      assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;
+      assign si_cb_awlen[slot*8+:8]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;
+      assign si_cb_awsize[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awsize[slot*3+:3]                                                     : P_AXILITE_SIZE ;
+      assign si_cb_awburst[slot*2+:2]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awburst[slot*2+:2]                                                    : P_INCR ;
+      assign si_cb_awlock[slot*2+:2]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? {1\'b0, s_axi_awlock[slot*P_LOCK+:1]}                                             : 0 ;
+      assign si_cb_awcache[slot*4+:4]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awcache[slot*4+:4]                                                    : 0 ;
+      assign si_cb_awprot[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awprot[slot*3+:3]                                                     : 0 ;
+      assign si_cb_awqos[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_awqos[slot*4+:4]                                                      : 0 ;
+//      assign si_cb_awregion[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4)                                ) ? s_axi_awregion[slot*4+:4]                                                      : 0 ;
+      assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   : 0 ;
+      assign si_cb_awvalid[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_awvalid[slot*1+:1]                                                    : 0 ;
+      assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3)                                   ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))   : 0 ;
+      assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;
+      assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
+      assign si_cb_wlast[slot*1+:1]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_wlast[slot*1+:1]                                                      : 1\'b1 ;
+      assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      : 0 ;
+      assign si_cb_wvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_wvalid[slot*1+:1]                                                     : 0 ;
+      assign si_cb_bready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? s_axi_bready[slot*1+:1]                                                     : 0 ;
+      assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))              : 0 ;
+      assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;
+      assign si_cb_arlen[slot*8+:8]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;
+      assign si_cb_arsize[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arsize[slot*3+:3]                                                     : P_AXILITE_SIZE ;
+      assign si_cb_arburst[slot*2+:2]                                                    = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arburst[slot*2+:2]                                                    : P_INCR ;
+      assign si_cb_arlock[slot*2+:2]                                                     = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? {1\'b0, s_axi_arlock[slot*P_LOCK+:1]}                                             : 0 ;
+      assign si_cb_arcache[slot*4+:4]                                                    = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                  ) ? s_axi_arcache[slot*4+:4]                                                    : 0 ;
+      assign si_cb_arprot[slot*3+:3]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_arprot[slot*3+:3]                                                     : 0 ;
+      assign si_cb_arqos[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? s_axi_arqos[slot*4+:4]                                                      : 0 ;
+//      assign si_cb_arregion[slot*4+:4]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4)                                ) ? s_axi_arregion[slot*4+:4]                                                      : 0 ;
+      assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   : 0 ;
+      assign si_cb_arvalid[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_arvalid[slot*1+:1]                                                    : 0 ;
+      assign si_cb_rready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? s_axi_rready[slot*1+:1]                                                     : 0 ;                                       
+
+      assign s_axi_awready[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_awready[slot*1+:1]                                                    : 0 ;
+      assign s_axi_wready[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_wready[slot*1+:1]                                                     : 0 ;
+      assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))               : 0 ;
+      assign s_axi_bresp[slot*2+:2]                                                      = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_bresp[slot*2+:2]                                                      : 0 ;
+      assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      : 0 ;
+      assign s_axi_bvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? si_cb_bvalid[slot*1+:1]                                                     : 0 ;
+      assign s_axi_arready[slot*1+:1]                                                    = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_arready[slot*1+:1]                                                    : 0 ;
+      assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot))               : 0 ;
+      assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;
+      assign s_axi_rresp[slot*2+:2]                                                      = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rresp[slot*2+:2]                                                      : 0 ;
+      assign s_axi_rlast[slot*1+:1]                                                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? si_cb_rlast[slot*1+:1]                                                      : 0 ;
+      assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      = (P_S_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      : 0 ;
+      assign s_axi_rvalid[slot*1+:1]                                                     = (P_S_AXI_SUPPORTS_READ[slot]                                                                             ) ? si_cb_rvalid[slot*1+:1]                                                     : 0 ;
+    end  // gen_si_tieoff
+
+    for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff
+      assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             : 0 ;
+      assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;
+      assign m_axi_awlen[slot*P_LEN+:P_LEN]                                              = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4                             ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;
+      assign m_axi_awsize[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awsize[slot*3+:3]                                                     : 0 ;
+      assign m_axi_awburst[slot*2+:2]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awburst[slot*2+:2]                                                    : 0 ;
+      assign m_axi_awlock[slot*P_LOCK+:P_LOCK]                                           = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awlock[slot*2+:1]                                                     : 0 ;
+      assign m_axi_awcache[slot*4+:4]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awcache[slot*4+:4]                                                    : 0 ;
+      assign m_axi_awprot[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awprot[slot*3+:3]                                                     : 0 ;
+      assign m_axi_awregion[slot*4+:4]                                                   = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL==P_AXI4)                                 ) ? cb_mi_awregion[slot*4+:4]                                                   : 0 ;
+      assign m_axi_awqos[slot*4+:4]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_awqos[slot*4+:4]                                                      : 0 ;
+      assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH]                   : 0 ;
+      assign m_axi_awvalid[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_awvalid[slot*1+:1]                                                    : 0 ;
+      assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;
+      assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;
+      assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
+      assign m_axi_wlast[slot*1+:1]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_wlast[slot*1+:1]                                                      : 0 ;
+      assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]                      : 0 ;
+      assign m_axi_wvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_wvalid[slot*1+:1]                                                     : 0 ;
+      assign m_axi_bready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? cb_mi_bready[slot*1+:1]                                                     : 0 ;
+      assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                             = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                            : 0 ;
+      assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]                       : 0 ;
+      assign m_axi_arlen[slot*P_LEN+:P_LEN]                                              = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4                             ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;
+      assign m_axi_arsize[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arsize[slot*3+:3]                                                     : 0 ;
+      assign m_axi_arburst[slot*2+:2]                                                    = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arburst[slot*2+:2]                                                    : 0 ;
+      assign m_axi_arlock[slot*P_LOCK+:P_LOCK]                                           = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arlock[slot*2+:1]                                                     : 0 ;
+      assign m_axi_arcache[slot*4+:4]                                                    = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arcache[slot*4+:4]                                                    : 0 ;
+      assign m_axi_arprot[slot*3+:3]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_arprot[slot*3+:3]                                                     : 0 ;
+      assign m_axi_arregion[slot*4+:4]                                                   = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL==P_AXI4)                                 ) ? cb_mi_arregion[slot*4+:4]                                                   : 0 ;
+      assign m_axi_arqos[slot*4+:4]                                                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                 ) ? cb_mi_arqos[slot*4+:4]                                                      : 0 ;
+      assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH]                   : 0 ;
+      assign m_axi_arvalid[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_arvalid[slot*1+:1]                                                    : 0 ;
+      assign m_axi_rready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? cb_mi_rready[slot*1+:1]                                                     : 0 ;
+
+      assign cb_mi_awready[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_awready[slot*1+:1]                                                    : 0 ;
+      assign cb_mi_wready[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_wready[slot*1+:1]                                                     : 0 ;
+      assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;
+      assign cb_mi_bresp[slot*2+:2]                                                      = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_bresp[slot*2+:2]                                                      : 0 ;
+      assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]                      : 0 ;
+      assign cb_mi_bvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_WRITE[slot]                                                                            ) ? m_axi_bvalid[slot*1+:1]                                                     : 0 ;
+      assign cb_mi_arready[slot*1+:1]                                                    = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_arready[slot*1+:1]                                                    : 0 ;
+      assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]                              : 0 ;
+      assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]                        = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]     : 0 ;
+      assign cb_mi_rresp[slot*2+:2]                                                      = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rresp[slot*2+:2]                                                      : 0 ;
+      assign cb_mi_rlast[slot*1+:1]                                                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE)                                ) ? m_axi_rlast[slot*1+:1]                                                      : 1\'b1 ;
+      assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      = (P_M_AXI_SUPPORTS_READ[slot]  && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]                      : 0 ;
+      assign cb_mi_rvalid[slot*1+:1]                                                     = (P_M_AXI_SUPPORTS_READ[slot]                                                                             ) ? m_axi_rvalid[slot*1+:1]                                                     : 0 ;
+    end  // gen_mi_tieoff
+
+    if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd
+      axi_crossbar_v2_1_12_crossbar_sasd #
+      (
+        .C_FAMILY                         (P_FAMILY),
+        .C_NUM_SLAVE_SLOTS                ('b'C_NUM_SLAVE_SLOTS),
+        .C_NUM_MASTER_SLOTS               (C_NUM_MASTER_SLOTS),
+        .C_NUM_ADDR_RANGES                (C_NUM_ADDR_RANGES),
+        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
+        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
+        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
+        .C_AXI_PROTOCOL                   (C_AXI_PROTOCOL),
+        .C_M_AXI_BASE_ADDR                (C_M_AXI_BASE_ADDR),
+        .C_M_AXI_HIGH_ADDR                (f_high_addr(0)),
+        .C_S_AXI_BASE_ID                  (P_S_AXI_BASE_ID),
+        .C_S_AXI_HIGH_ID                  (P_S_AXI_HIGH_ID),
+        .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),
+        .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),
+        .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),
+        .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),
+        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
+        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),
+        .C_S_AXI_SUPPORTS_WRITE           (P_S_AXI_SUPPORTS_WRITE),
+        .C_S_AXI_SUPPORTS_READ            (P_S_AXI_SUPPORTS_READ),
+        .C_M_AXI_SUPPORTS_WRITE           (P_M_AXI_SUPPORTS_WRITE),
+        .C_M_AXI_SUPPORTS_READ            (P_M_AXI_SUPPORTS_READ),
+        .C_S_AXI_ARB_PRIORITY             (C_S_AXI_ARB_PRIORITY),
+        .C_M_AXI_SECURE                   (C_M_AXI_SECURE),
+        .C_R_REGISTER                     (C_R_REGISTER),
+        .C_RANGE_CHECK                    (P_RANGE_CHECK),
+        .C_ADDR_DECODE                    (P_ADDR_DECODE),
+        .C_M_AXI_ERR_MODE                 (P_M_AXI_ERR_MODE),
+        .C_DEBUG                          (C_DEBUG)
+      )
+        crossbar_sasd_0
+      (
+          .ACLK                             (aclk),
+          .ARESETN                          (aresetn),
+          .S_AXI_AWID                       (si_cb_awid           ),
+          .S_AXI_AWADDR                     (si_cb_awaddr         ),
+          .S_AXI_AWLEN                      (si_cb_awlen          ),
+          .S_AXI_AWSIZE                     (si_cb_awsize         ),
+          .S_AXI_AWBURST                    (si_cb_awburst        ),
+          .S_AXI_AWLOCK                     (si_cb_awlock         ),
+          .S_AXI_AWCACHE                    (si_cb_awcache        ),
+          .S_AXI_AWPROT                     (si_cb_awprot         ),
+//          .S_AXI_AWREGION                   (si_cb_awregion       ),
+          .S_AXI_AWQOS                      (si_cb_awqos          ),
+          .S_AXI_AWUSER                     (si_cb_awuser         ),
+          .S_AXI_AWVALID                    (si_cb_awvalid        ),
+          .S_AXI_AWREADY                    (si_cb_awready        ),
+          .S_AXI_WID                        (si_cb_wid             ),
+          .S_AXI_WDATA                      (si_cb_wdata          ),
+          .S_AXI_WSTRB                      (si_cb_wstrb          ),
+          .S_AXI_WLAST                      (si_cb_wlast          ),
+          .S_AXI_WUSER                      (si_cb_wuser          ),
+          .S_AXI_WVALID                     (si_cb_wvalid         ),
+          .S_AXI_WREADY                     (si_cb_wready         ),
+          .S_AXI_BID                        (si_cb_bid            ),
+          .S_AXI_BRESP                      (si_cb_bresp          ),
+          .S_AXI_BUSER                      (si_cb_buser          ),
+          .S_AXI_BVALID                     (si_cb_bvalid         ),
+          .S_AXI_BREADY                     (si_cb_bready         ),
+          .S_AXI_ARID                       (si_cb_arid           ),
+          .S_AXI_ARADDR                     (si_cb_araddr         ),
+          .S_AXI_ARLEN                      (si_cb_arlen          ),
+          .S_AXI_ARSIZE                     (si_cb_arsize         ),
+          .S_AXI_ARBURST                    (si_cb_arburst        ),
+          .S_AXI_ARLOCK                     (si_cb_arlock         ),
+          .S_AXI_ARCACHE                    (si_cb_arcache        ),
+          .S_AXI_ARPROT                     (si_cb_arprot         ),
+//          .S_AXI_ARREGION                   (si_cb_arregion       ),
+          .S_AXI_ARQOS                      (si_cb_arqos          ),
+          .S_AXI_ARUSER                     (si_cb_aruser         ),
+          .S_AXI_ARVALID                    (si_cb_arvalid        ),
+          .S_AXI_ARREADY                    (si_cb_arready        ),
+          .S_AXI_RID                        (si_cb_rid            ),
+          .S_AXI_RDATA                      (si_cb_rdata          ),
+          .S_AXI_RRESP                      (si_cb_rresp          ),
+          .S_AXI_RLAST                      (si_cb_rlast          ),
+          .S_AXI_RUSER                      (si_cb_ruser          ),
+          .S_AXI_RVALID                     (si_cb_rvalid         ),
+          .S_AXI_RREADY                     (si_cb_rready         ),
+          .M_AXI_AWID                       (cb_mi_awid           ),
+          .M_AXI_AWADDR                     (cb_mi_awaddr         ),
+          .M_AXI_AWLEN                      (cb_mi_awlen          ),
+          .M_AXI_AWSIZE                     (cb_mi_awsize         ),
+          .M_AXI_AWBURST                    (cb_mi_awburst        ),
+          .M_AXI_AWLOCK                     (cb_mi_awlock         ),
+          .M_AXI_AWCACHE                    (cb_mi_awcache        ),
+          .M_AXI_AWPROT                     (cb_mi_awprot         ),
+          .M_AXI_AWREGION                   (cb_mi_awregion       ),
+          .M_AXI_AWQOS                      (cb_mi_awqos          ),
+          .M_AXI_AWUSER                     (cb_mi_awuser         ),
+          .M_AXI_AWVALID                    (cb_mi_awvalid        ),
+          .M_AXI_AWREADY                    (cb_mi_awready        ),
+          .M_AXI_WID                        (cb_mi_wid             ),
+          .M_AXI_WDATA                      (cb_mi_wdata          ),
+          .M_AXI_WSTRB                      (cb_mi_wstrb          ),
+          .M_AXI_WLAST                      (cb_mi_wlast          ),
+          .M_AXI_WUSER                      (cb_mi_wuser          ),
+          .M_AXI_WVALID                     (cb_mi_wvalid         ),
+          .M_AXI_WREADY                     (cb_mi_wready         ),
+          .M_AXI_BID                        (cb_mi_bid            ),
+          .M_AXI_BRESP                      (cb_mi_bresp          ),
+          .M_AXI_BUSER                      (cb_mi_buser          ),
+          .M_AXI_BVALID                     (cb_mi_bvalid         ),
+          .M_AXI_BREADY                     (cb_mi_bready         ),
+          .M_AXI_ARID                       (cb_mi_arid           ),
+          .M_AXI_ARADDR                     (cb_mi_araddr         ),
+          .M_AXI_ARLEN                      (cb_mi_arlen          ),
+          .M_AXI_ARSIZE                     (cb_mi_arsize         ),
+          .M_AXI_ARBURST                    (cb_mi_arburst        ),
+          .M_AXI_ARLOCK                     (cb_mi_arlock         ),
+          .M_AXI_ARCACHE                    (cb_mi_arcache        ),
+          .M_AXI_ARPROT                     (cb_mi_arprot         ),
+          .M_AXI_ARREGION                   (cb_mi_arregion       ),
+          .M_AXI_ARQOS                      (cb_mi_arqos          ),
+          .M_AXI_ARUSER                     (cb_mi_aruser         ),
+          .M_AXI_ARVALID                    (cb_mi_arvalid        ),
+          .M_AXI_ARREADY                    (cb_mi_arready        ),
+          .M_AXI_RID                        (cb_mi_rid            ),
+          .M_AXI_RDATA                      (cb_mi_rdata          ),
+          .M_AXI_RRESP                      (cb_mi_rresp          ),
+          .M_AXI_RLAST                      (cb_mi_rlast          ),
+          .M_AXI_RUSER                      (cb_mi_ruser          ),
+          .M_AXI_RVALID                     (cb_mi_rvalid         ),
+          .M_AXI_RREADY                     (cb_mi_rready         )
+      );
+    end else begin : gen_samd
+      axi_crossbar_v2_1_12_crossbar #
+      (
+        .C_FAMILY                         (P_FAMILY),
+        .C_NUM_SLAVE_SLOTS                (C_NUM_SLAVE_SLOTS),
+        .C_NUM_MASTER_SLOTS               (C_NUM_MASTER_SLOTS),
+        .C_NUM_ADDR_RANGES                (C_NUM_ADDR_RANGES),
+        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
+        .C_S_AXI_THREAD_ID_WIDTH          (C_S_AXI_THREAD_ID_WIDTH),
+        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
+        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
+        .C_AXI_PROTOCOL                   (C_AXI_PROTOCOL),
+        .C_M_AXI_BASE_ADDR                (C_M_AXI_BASE_ADDR),
+        .C_M_AXI_HIGH_ADDR                (f_high_addr(0)),
+        .C_S_AXI_BASE_ID                  (P_S_AXI_BASE_ID),
+        .C_S_AXI_HIGH_ID                  (P_S_AXI_HIGH_ID),
+        .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),
+        .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),
+        .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),
+        .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),
+        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
+        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),
+        .C_S_AXI_SUPPORTS_WRITE           (P_S_AXI_SUPPORTS_WRITE),
+        .C_S_AXI_SUPPORTS_READ            (P_S_AXI_SUPPORTS_READ),
+        .C_M_AXI_SUPPORTS_WRITE           (P_M_AXI_SUPPORTS_WRITE),
+        .C_M_AXI_SUPPORTS_READ            (P_M_AXI_SUPPORTS_READ),
+        .C_M_AXI_WRITE_CONNECTIVITY       (C_M_AXI_WRITE_CONNECTIVITY),
+        .C_M_AXI_READ_CONNECTIVITY        (C_M_AXI_READ_CONNECTIVITY),
+        .C_S_AXI_SINGLE_THREAD            (C_S_AXI_SINGLE_THREAD),
+        .C_S_AXI_WRITE_ACCEPTANCE         (C_S_AXI_WRITE_ACCEPTANCE),
+        .C_S_AXI_READ_ACCEPTANCE          (C_S_AXI_READ_ACCEPTANCE),
+        .C_M_AXI_WRITE_ISSUING            (C_M_AXI_WRITE_ISSUING),
+        .C_M_AXI_READ_ISSUING             (C_M_AXI_READ_ISSUING),
+        .C_S_AXI_ARB_PRIORITY             (C_S_AXI_ARB_PRIORITY),
+        .C_M_AXI_SECURE                   (C_M_AXI_SECURE),
+        .C_RANGE_CHECK                    (P_RANGE_CHECK),
+        .C_ADDR_DECODE                    (P_ADDR_DECODE),
+        .C_W_ISSUE_WIDTH                  (f_write_issue_width_vec(0) ),
+        .C_R_ISSUE_WIDTH                  (f_read_issue_width_vec(0) ),
+        .C_W_ACCEPT_WIDTH                 (f_write_accept_width_vec(0)),
+        .C_R_ACCEPT_WIDTH                 (f_read_accept_width_vec(0)),
+        .C_M_AXI_ERR_MODE                 (P_M_AXI_ERR_MODE),
+        .C_DEBUG                          (C_DEBUG)
+      )
+        crossbar_samd 
+      (
+          .ACLK                             (aclk),
+          .ARESETN                          (aresetn),
+          .S_AXI_AWID                       (si_cb_awid             ),
+          .S_AXI_AWADDR                     (si_cb_awaddr           ),
+          .S_AXI_AWLEN                      (si_cb_awlen            ),
+          .S_AXI_AWSIZE                     (si_cb_awsize           ),
+          .S_AXI_AWBURST                    (si_cb_awburst          ),
+          .S_AXI_AWLOCK                     (si_cb_awlock           ),
+          .S_AXI_AWCACHE                    (si_cb_awcache          ),
+          .S_AXI_AWPROT                     (si_cb_awprot           ),
+//          .S_AXI_AWREGION                   (si_cb_awregion       ),
+          .S_AXI_AWQOS                      (si_cb_awqos            ),
+          .S_AXI_AWUSER                     (si_cb_awuser           ),
+          .S_AXI_AWVALID                    (si_cb_awvalid          ),
+          .S_AXI_AWREADY                    (si_cb_awready          ),
+          .S_AXI_WID                        (si_cb_wid             ),
+          .S_AXI_WDATA                      (si_cb_wdata            ),
+          .S_AXI_WSTRB                      (si_cb_wstrb            ),
+          .S_AXI_WLAST                      (si_cb_wlast            ),
+          .S_AXI_WUSER                      (si_cb_wuser            ),
+          .S_AXI_WVALID                     (si_cb_wvalid           ),
+          .S_AXI_WREADY                     (si_cb_wready           ),
+          .S_AXI_BID                        (si_cb_bid              ),
+          .S_AXI_BRESP                      (si_cb_bresp            ),
+          .S_AXI_BUSER                      (si_cb_buser            ),
+          .S_AXI_BVALID                     (si_cb_bvalid           ),
+          .S_AXI_BREADY                     (si_cb_bready           ),
+          .S_AXI_ARID                       (si_cb_arid             ),
+          .S_AXI_ARADDR                     (si_cb_araddr           ),
+          .S_AXI_ARLEN                      (si_cb_arlen            ),
+          .S_AXI_ARSIZE                     (si_cb_arsize           ),
+          .S_AXI_ARBURST                    (si_cb_arburst          ),
+          .S_AXI_ARLOCK                     (si_cb_arlock           ),
+          .S_AXI_ARCACHE                    (si_cb_arcache          ),
+          .S_AXI_ARPROT                     (si_cb_arprot           ),
+//          .S_AXI_ARREGION                   (si_cb_arregion       ),
+          .S_AXI_ARQOS                      (si_cb_arqos            ),
+          .S_AXI_ARUSER                     (si_cb_aruser           ),
+          .S_AXI_ARVALID                    (si_cb_arvalid          ),
+          .S_AXI_ARREADY                    (si_cb_arready          ),
+          .S_AXI_RID                        (si_cb_rid              ),
+          .S_AXI_RDATA                      (si_cb_rdata            ),
+          .S_AXI_RRESP                      (si_cb_rresp            ),
+          .S_AXI_RLAST                      (si_cb_rlast            ),
+          .S_AXI_RUSER                      (si_cb_ruser            ),
+          .S_AXI_RVALID                     (si_cb_rvalid           ),
+          .S_AXI_RREADY                     (si_cb_rready           ),
+          .M_AXI_AWID                       (cb_mi_awid             ),
+          .M_AXI_AWADDR                     (cb_mi_awaddr           ),
+          .M_AXI_AWLEN                      (cb_mi_awlen            ),
+          .M_AXI_AWSIZE                     (cb_mi_awsize           ),
+          .M_AXI_AWBURST                    (cb_mi_awburst          ),
+          .M_AXI_AWLOCK                     (cb_mi_awlock           ),
+          .M_AXI_AWCACHE                    (cb_mi_awcache          ),
+          .M_AXI_AWPROT                     (cb_mi_awprot           ),
+          .M_AXI_AWREGION                   (cb_mi_awregion         ),
+          .M_AXI_AWQOS                      (cb_mi_awqos            ),
+          .M_AXI_AWUSER                     (cb_mi_awuser           ),
+          .M_AXI_AWVALID                    (cb_mi_awvalid          ),
+          .M_AXI_AWREADY                    (cb_mi_awready          ),
+          .M_AXI_WID                        (cb_mi_wid             ),
+          .M_AXI_WDATA                      (cb_mi_wdata            ),
+          .M_AXI_WSTRB                      (cb_mi_wstrb            ),
+          .M_AXI_WLAST                      (cb_mi_wlast            ),
+          .M_AXI_WUSER                      (cb_mi_wuser            ),
+          .M_AXI_WVALID                     (cb_mi_wvalid           ),
+          .M_AXI_WREADY                     (cb_mi_wready           ),
+          .M_AXI_BID                        (cb_mi_bid              ),
+          .M_AXI_BRESP                      (cb_mi_bresp            ),
+          .M_AXI_BUSER                      (cb_mi_buser            ),
+          .M_AXI_BVALID                     (cb_mi_bvalid           ),
+          .M_AXI_BREADY                     (cb_mi_bready           ),
+          .M_AXI_ARID                       (cb_mi_arid             ),
+          .M_AXI_ARADDR                     (cb_mi_araddr           ),
+          .M_AXI_ARLEN                      (cb_mi_arlen            ),
+          .M_AXI_ARSIZE                     (cb_mi_arsize           ),
+          .M_AXI_ARBURST                    (cb_mi_arburst          ),
+          .M_AXI_ARLOCK                     (cb_mi_arlock           ),
+          .M_AXI_ARCACHE                    (cb_mi_arcache          ),
+          .M_AXI_ARPROT                     (cb_mi_arprot           ),
+          .M_AXI_ARREGION                   (cb_mi_arregion         ),
+          .M_AXI_ARQOS                      (cb_mi_arqos            ),
+          .M_AXI_ARUSER                     (cb_mi_aruser           ),
+          .M_AXI_ARVALID                    (cb_mi_arvalid          ),
+          .M_AXI_ARREADY                    (cb_mi_arready          ),
+          .M_AXI_RID                        (cb_mi_rid              ),
+          .M_AXI_RDATA                      (cb_mi_rdata            ),
+          .M_AXI_RRESP                      (cb_mi_rresp            ),
+          .M_AXI_RLAST                      (cb_mi_rlast            ),
+          .M_AXI_RUSER                      (cb_mi_ruser            ),
+          .M_AXI_RVALID                     (cb_mi_rvalid           ),
+          .M_AXI_RREADY                     (cb_mi_rready           )
+      );
+    end  // gen_samd
+//  end  // gen_crossbar
+endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+"
+"// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, ""Critical
+// -- Applications""). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   w_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_w_atc #
+  (
+   parameter         C_FAMILY                         = ""rtl"",
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4,
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_DATA_WIDTH                 = 64,
+                       // Width of all DATA signals on SI and MI side of checker.
+                       // Range: 64.
+   parameter integer C_AXI_WUSER_WIDTH                = 1
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface (In)
+   input  wire                                  cmd_w_valid,
+   input  wire                                  cmd_w_check,
+   input  wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id,
+   output wire                                  cmd_w_ready,
+   
+   // Command Interface (Out)
+   output wire                                  cmd_b_push,
+   output wire                                  cmd_b_error,
+   output reg  [C_AXI_ID_WIDTH-1:0]             cmd_b_id,
+   input  wire                                  cmd_b_full,
+   
+   // Slave Interface Write Port
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_WID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0]         S_AXI_WSTRB,
+   input  wire                                  S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire                                  S_AXI_WVALID,
+   output wire                                  S_AXI_WREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0]         M_AXI_WSTRB,
+   output wire                                  M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]          M_AXI_WUSER,
+   output wire                                  M_AXI_WVALID,
+   input  wire                                  M_AXI_WREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detecttion.
+  wire                                any_strb_deasserted;
+  wire                                incoming_strb_issue;
+  reg                                 first_word;
+  reg                                 strb_issue;
+  
+  // Data flow.
+  wire                                data_pop;
+  wire                                cmd_b_push_blocked;
+  reg                                 cmd_b_push_i;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Detect error:
+  //
+  // Detect and accumulate error when a transaction shall be scanned for
+  // potential issues.
+  // Accumulation of error is restarted for each ne transaction. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Check stobe information
+  assign any_strb_deasserted  = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1\'b1}} );
+  assign incoming_strb_issue  = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
+  
+  // Keep track of first word in a transaction.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      first_word  <= 1\'b1;
+    end else if ( data_pop ) begin
+      first_word  <= S_AXI_WLAST;
+    end
+  end
+  
+  // Keep track of error status.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      strb_issue  <= 1\'b0;
+      cmd_b_id    <= {C_AXI_ID_WIDTH{1\'b0}};
+    end else if ( data_pop ) begin
+      if ( first_word ) begin
+        strb_issue  <= incoming_strb_issue;
+      end else begin
+        strb_issue  <= incoming_strb_issue | strb_issue;
+      end
+      cmd_b_id    <= cmd_w_id;
+    end
+  end
+  
+  assign cmd_b_error  = strb_issue;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Control command queue to B:
+  //
+  // Push command to B queue when all data for the transaction has flowed  
+  // through.
+  // Delay pipelined command until there is room in the Queue.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detect when data is popped.
+  assign data_pop   = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; 
+  
+  // Push command when last word in transfered (pipelined).
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_push_i  <= 1\'b0;
+    end else begin
+      cmd_b_push_i  <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
+    end
+  end
+  
+  // Detect if pipelined push is blocked.
+  assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
+  
+  // Assign output.
+  assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Stall commands if FIFO is full or there is no valid command information 
+  // from AW. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign M_AXI_WVALID   = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
+  
+  // Return ready with push back.
+  assign S_AXI_WREADY   = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
+  
+  // End of burst.
+  assign cmd_w_ready    = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Write propagation:
+  //
+  // All information is simply forwarded on from the SI- to MI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign M_AXI_WID      = S_AXI_WID;
+  assign M_AXI_WDATA    = S_AXI_WDATA;
+  assign M_AXI_WSTRB    = S_AXI_WSTRB;
+  assign M_AXI_WLAST    = S_AXI_WLAST;
+  assign M_AXI_WUSER    = S_AXI_WUSER;
+  
+  
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Sun Jan 22 23:54:06 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top design_1_axi_gpio_1_0 -prefix
+//               design_1_axi_gpio_1_0_ design_1_axi_gpio_1_0_sim_netlist.v
+// Design      : design_1_axi_gpio_1_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_axi_gpio_1_0_GPIO_Core
+   (D,
+    GPIO_xferAck_i,
+    gpio_xferAck_Reg,
+    ip2bus_rdack_i,
+    ip2bus_wrack_i_D1_reg,
+    gpio_io_o,
+    gpio_io_t,
+    Q,
+    bus2ip_rnw_i_reg,
+    \\Not_Dual.gpio_Data_In_reg[3]_0 ,
+    s_axi_aclk,
+    \\Not_Dual.gpio_Data_In_reg[2]_0 ,
+    \\Not_Dual.gpio_Data_In_reg[1]_0 ,
+    GPIO_DBus_i,
+    SS,
+    bus2ip_rnw,
+    bus2ip_cs,
+    gpio_io_i,
+    E,
+    \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
+    rst_reg);
+  output [3:0]D;
+  output GPIO_xferAck_i;
+  output gpio_xferAck_Reg;
+  output ip2bus_rdack_i;
+  output ip2bus_wrack_i_D1_reg;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  output [3:0]Q;
+  input bus2ip_rnw_i_reg;
+  input \\Not_Dual.gpio_Data_In_reg[3]_0 ;
+  input s_axi_aclk;
+  input \\Not_Dual.gpio_Data_In_reg[2]_0 ;
+  input \\Not_Dual.gpio_Data_In_reg[1]_0 ;
+  input [0:0]GPIO_DBus_i;
+  input [0:0]SS;
+  input bus2ip_rnw;
+  input bus2ip_cs;
+  input [3:0]gpio_io_i;
+  input [0:0]E;
+  input [3:0]\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  input [0:0]rst_reg;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  wire \\Not_Dual.gpio_Data_In_reg[1]_0 ;
+  wire \\Not_Dual.gpio_Data_In_reg[2]_0 ;
+  wire \\Not_Dual.gpio_Data_In_reg[3]_0 ;
+  wire [3:0]Q;
+  wire [0:0]SS;
+  wire bus2ip_cs;
+  wire bus2ip_rnw;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio_io_i;
+  wire [0:3]gpio_io_i_d2;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire iGPIO_xferAck;
+  wire ip2bus_rdack_i;
+  wire ip2bus_wrack_i_D1_reg;
+  wire [0:0]rst_reg;
+  wire s_axi_aclk;
+
+  design_1_axi_gpio_1_0_cdc_sync \\Not_Dual.INPUT_DOUBLE_REGS3 
+       (.gpio_io_i(gpio_io_i),
+        .s_axi_aclk(s_axi_aclk),
+        .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
+  FDRE \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_DBus_i),
+        .Q(D[3]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[1]_0 ),
+        .Q(D[2]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[2]_0 ),
+        .Q(D[1]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\Not_Dual.gpio_Data_In_reg[3]_0 ),
+        .Q(D[0]),
+        .R(bus2ip_rnw_i_reg));
+  FDRE \\Not_Dual.gpio_Data_In_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[0]),
+        .Q(Q[3]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[1]),
+        .Q(Q[2]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[2]),
+        .Q(Q[1]),
+        .R(1\'b0));
+  FDRE \\Not_Dual.gpio_Data_In_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i_d2[3]),
+        .Q(Q[0]),
+        .R(1\'b0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
+        .Q(gpio_io_o[3]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
+        .Q(gpio_io_o[2]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
+        .Q(gpio_io_o[1]),
+        .R(SS));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\Not_Dual.gpio_Data_Out_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
+        .Q(gpio_io_o[0]),
+        .R(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
+        .Q(gpio_io_t[3]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
+        .Q(gpio_io_t[2]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
+        .Q(gpio_io_t[1]),
+        .S(SS));
+  FDSE #(
+    .INIT(1\'b1)) 
+    \\Not_Dual.gpio_OE_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(rst_reg),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
+        .Q(gpio_io_t[0]),
+        .S(SS));
+  FDRE gpio_xferAck_Reg_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(GPIO_xferAck_i),
+        .Q(gpio_xferAck_Reg),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'h02)) 
+    iGPIO_xferAck_i_1
+       (.I0(bus2ip_cs),
+        .I1(gpio_xferAck_Reg),
+        .I2(GPIO_xferAck_i),
+        .O(iGPIO_xferAck));
+  FDRE iGPIO_xferAck_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(iGPIO_xferAck),
+        .Q(GPIO_xferAck_i),
+        .R(SS));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    ip2bus_rdack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_rdack_i));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    ip2bus_wrack_i_D1_i_1
+       (.I0(GPIO_xferAck_i),
+        .I1(bus2ip_rnw),
+        .O(ip2bus_wrack_i_D1_reg));
+endmodule
+
+module design_1_axi_gpio_1_0_address_decoder
+   (\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_arready,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_aclk,
+    rst_reg,
+    bus2ip_rnw_i_reg,
+    Q,
+    ip2bus_rdack_i_D1,
+    is_read,
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
+    ip2bus_wrack_i_D1,
+    is_write_reg,
+    \\Not_Dual.gpio_Data_In_reg[0] ,
+    gpio_io_t,
+    s_axi_wdata,
+    start2_reg,
+    s_axi_aresetn,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i);
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_arready;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  input s_axi_aclk;
+  input rst_reg;
+  input bus2ip_rnw_i_reg;
+  input [2:0]Q;
+  input ip2bus_rdack_i_D1;
+  input is_read;
+  input [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  input ip2bus_wrack_i_D1;
+  input is_write_reg;
+  input [3:0]\\Not_Dual.gpio_Data_In_reg[0] ;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input start2_reg;
+  input s_axi_aresetn;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire [3:0]\\Not_Dual.gpio_Data_In_reg[0] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [2:0]Q;
+  wire bus2ip_rnw_i_reg;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_write_reg;
+  wire rst_reg;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire start2_reg;
+
+  LUT5 #(
+    .INIT(32\'h000000E0)) 
+    \\MEM_DECODE_GEN[0].cs_out_i[0]_i_1 
+       (.I0(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I1(start2_reg),
+        .I2(s_axi_aresetn),
+        .I3(s_axi_arready),
+        .I4(s_axi_wready),
+        .O(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
+  FDRE \\MEM_DECODE_GEN[0].cs_out_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(\\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
+        .Q(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [3]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[3]),
+        .O(GPIO_DBus_i));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [2]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[2]),
+        .O(\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [1]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[1]),
+        .O(\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ));
+  LUT4 #(
+    .INIT(16\'hFFF7)) 
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1 
+       (.I0(bus2ip_rnw_i_reg),
+        .I1(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I2(gpio_xferAck_Reg),
+        .I3(GPIO_xferAck_i),
+        .O(\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ));
+  LUT6 #(
+    .INIT(64\'h000000E000000020)) 
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_2 
+       (.I0(\\Not_Dual.gpio_Data_In_reg[0] [0]),
+        .I1(Q[0]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[1]),
+        .I5(gpio_io_t[0]),
+        .O(\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAAABAA)) 
+    \\Not_Dual.gpio_Data_Out[0]_i_1 
+       (.I0(rst_reg),
+        .I1(bus2ip_rnw_i_reg),
+        .I2(Q[0]),
+        .I3(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I4(Q[2]),
+        .I5(Q[1]),
+        .O(E));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[0]_i_2 
+       (.I0(s_axi_wdata[3]),
+        .I1(s_axi_wdata[7]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[3]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[1]_i_1 
+       (.I0(s_axi_wdata[2]),
+        .I1(s_axi_wdata[6]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[2]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[2]_i_1 
+       (.I0(s_axi_wdata[1]),
+        .I1(s_axi_wdata[5]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[1]));
+  LUT4 #(
+    .INIT(16\'hCCAC)) 
+    \\Not_Dual.gpio_Data_Out[3]_i_1 
+       (.I0(s_axi_wdata[0]),
+        .I1(s_axi_wdata[4]),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[1]),
+        .O(D[0]));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAABAAAAA)) 
+    \\Not_Dual.gpio_OE[0]_i_1 
+       (.I0(rst_reg),
+        .I1(bus2ip_rnw_i_reg),
+        .I2(\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
+        .I3(Q[2]),
+        .I4(Q[0]),
+        .I5(Q[1]),
+        .O(\\Not_Dual.gpio_OE_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAEAAAA)) 
+    s_axi_arready_INST_0
+       (.I0(ip2bus_rdack_i_D1),
+        .I1(is_read),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
+        .I5(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
+        .O(s_axi_arready));
+  LUT6 #(
+    .INIT(64\'hAAAAAAAAAAAEAAAA)) 
+    s_axi_wready_INST_0
+       (.I0(ip2bus_wrack_i_D1),
+        .I1(is_write_reg),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
+        .I4(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
+        .I5(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
+        .O(s_axi_wready));
+endmodule
+
+(* C_ALL_INPUTS = ""0"" *) (* C_ALL_INPUTS_2 = ""0"" *) (* C_ALL_OUTPUTS = ""0"" *) 
+(* C_ALL_OUTPUTS_2 = ""0"" *) (* C_DOUT_DEFAULT = ""0"" *) (* C_DOUT_DEFAULT_2 = ""0"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_GPIO2_WIDTH = ""32"" *) (* C_GPIO_WIDTH = ""4"" *) 
+(* C_INTERRUPT_PRESENT = ""0"" *) (* C_IS_DUAL = ""0"" *) (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+(* C_S_AXI_DATA_WIDTH = ""32"" *) (* C_TRI_DEFAULT = ""-1"" *) (* C_TRI_DEFAULT_2 = ""-1"" *) 
+(* downgradeipidentifiedwarnings = ""yes"" *) (* ip_group = ""LOGICORE"" *) 
+module design_1_axi_gpio_1_0_axi_gpio
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    ip2intc_irpt,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t,
+    gpio2_io_i,
+    gpio2_io_o,
+    gpio2_io_t);
+  (* max_fanout = ""10000"" *) (* sigis = ""Clk"" *) input s_axi_aclk;
+  (* max_fanout = ""10000"" *) (* sigis = ""Rst"" *) input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  (* sigis = ""INTR_LEVEL_HIGH"" *) output ip2intc_irpt;
+  input [3:0]gpio_io_i;
+  output [3:0]gpio_io_o;
+  output [3:0]gpio_io_t;
+  input [31:0]gpio2_io_i;
+  output [31:0]gpio2_io_o;
+  output [31:0]gpio2_io_t;
+
+  wire \\<const0> ;
+  wire \\<const1> ;
+  wire AXI_LITE_IPIF_I_n_10;
+  wire AXI_LITE_IPIF_I_n_11;
+  wire AXI_LITE_IPIF_I_n_12;
+  wire AXI_LITE_IPIF_I_n_17;
+  wire AXI_LITE_IPIF_I_n_6;
+  wire AXI_LITE_IPIF_I_n_7;
+  wire [0:3]DBus_Reg;
+  wire [28:28]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [0:3]gpio_Data_In;
+  wire gpio_core_1_n_7;
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [28:31]ip2bus_data;
+  wire [28:31]ip2bus_data_i_D1;
+  wire ip2bus_rdack_i;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Clk"" *) wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  (* MAX_FANOUT = ""10000"" *) (* RTL_MAX_FANOUT = ""found"" *) (* sigis = ""Rst"" *) wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]\\^s_axi_rdata ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  assign gpio2_io_o[31] = \\<const0> ;
+  assign gpio2_io_o[30] = \\<const0> ;
+  assign gpio2_io_o[29] = \\<const0> ;
+  assign gpio2_io_o[28] = \\<const0> ;
+  assign gpio2_io_o[27] = \\<const0> ;
+  assign gpio2_io_o[26] = \\<const0> ;
+  assign gpio2_io_o[25] = \\<const0> ;
+  assign gpio2_io_o[24] = \\<const0> ;
+  assign gpio2_io_o[23] = \\<const0> ;
+  assign gpio2_io_o[22] = \\<const0> ;
+  assign gpio2_io_o[21] = \\<const0> ;
+  assign gpio2_io_o[20] = \\<const0> ;
+  assign gpio2_io_o[19] = \\<const0> ;
+  assign gpio2_io_o[18] = \\<const0> ;
+  assign gpio2_io_o[17] = \\<const0> ;
+  assign gpio2_io_o[16] = \\<const0> ;
+  assign gpio2_io_o[15] = \\<const0> ;
+  assign gpio2_io_o[14] = \\<const0> ;
+  assign gpio2_io_o[13] = \\<const0> ;
+  assign gpio2_io_o[12] = \\<const0> ;
+  assign gpio2_io_o[11] = \\<const0> ;
+  assign gpio2_io_o[10] = \\<const0> ;
+  assign gpio2_io_o[9] = \\<const0> ;
+  assign gpio2_io_o[8] = \\<const0> ;
+  assign gpio2_io_o[7] = \\<const0> ;
+  assign gpio2_io_o[6] = \\<const0> ;
+  assign gpio2_io_o[5] = \\<const0> ;
+  assign gpio2_io_o[4] = \\<const0> ;
+  assign gpio2_io_o[3] = \\<const0> ;
+  assign gpio2_io_o[2] = \\<const0> ;
+  assign gpio2_io_o[1] = \\<const0> ;
+  assign gpio2_io_o[0] = \\<const0> ;
+  assign gpio2_io_t[31] = \\<const1> ;
+  assign gpio2_io_t[30] = \\<const1> ;
+  assign gpio2_io_t[29] = \\<const1> ;
+  assign gpio2_io_t[28] = \\<const1> ;
+  assign gpio2_io_t[27] = \\<const1> ;
+  assign gpio2_io_t[26] = \\<const1> ;
+  assign gpio2_io_t[25] = \\<const1> ;
+  assign gpio2_io_t[24] = \\<const1> ;
+  assign gpio2_io_t[23] = \\<const1> ;
+  assign gpio2_io_t[22] = \\<const1> ;
+  assign gpio2_io_t[21] = \\<const1> ;
+  assign gpio2_io_t[20] = \\<const1> ;
+  assign gpio2_io_t[19] = \\<const1> ;
+  assign gpio2_io_t[18] = \\<const1> ;
+  assign gpio2_io_t[17] = \\<const1> ;
+  assign gpio2_io_t[16] = \\<const1> ;
+  assign gpio2_io_t[15] = \\<const1> ;
+  assign gpio2_io_t[14] = \\<const1> ;
+  assign gpio2_io_t[13] = \\<const1> ;
+  assign gpio2_io_t[12] = \\<const1> ;
+  assign gpio2_io_t[11] = \\<const1> ;
+  assign gpio2_io_t[10] = \\<const1> ;
+  assign gpio2_io_t[9] = \\<const1> ;
+  assign gpio2_io_t[8] = \\<const1> ;
+  assign gpio2_io_t[7] = \\<const1> ;
+  assign gpio2_io_t[6] = \\<const1> ;
+  assign gpio2_io_t[5] = \\<const1> ;
+  assign gpio2_io_t[4] = \\<const1> ;
+  assign gpio2_io_t[3] = \\<const1> ;
+  assign gpio2_io_t[2] = \\<const1> ;
+  assign gpio2_io_t[1] = \\<const1> ;
+  assign gpio2_io_t[0] = \\<const1> ;
+  assign ip2intc_irpt = \\<const0> ;
+  assign s_axi_awready = s_axi_wready;
+  assign s_axi_bresp[1] = \\<const0> ;
+  assign s_axi_bresp[0] = \\<const0> ;
+  assign s_axi_rdata[31] = \\<const0> ;
+  assign s_axi_rdata[30] = \\<const0> ;
+  assign s_axi_rdata[29] = \\<const0> ;
+  assign s_axi_rdata[28] = \\<const0> ;
+  assign s_axi_rdata[27] = \\<const0> ;
+  assign s_axi_rdata[26] = \\<const0> ;
+  assign s_axi_rdata[25] = \\<const0> ;
+  assign s_axi_rdata[24] = \\<const0> ;
+  assign s_axi_rdata[23] = \\<const0> ;
+  assign s_axi_rdata[22] = \\<const0> ;
+  assign s_axi_rdata[21] = \\<const0> ;
+  assign s_axi_rdata[20] = \\<const0> ;
+  assign s_axi_rdata[19] = \\<const0> ;
+  assign s_axi_rdata[18] = \\<const0> ;
+  assign s_axi_rdata[17] = \\<const0> ;
+  assign s_axi_rdata[16] = \\<const0> ;
+  assign s_axi_rdata[15] = \\<const0> ;
+  assign s_axi_rdata[14] = \\<const0> ;
+  assign s_axi_rdata[13] = \\<const0> ;
+  assign s_axi_rdata[12] = \\<const0> ;
+  assign s_axi_rdata[11] = \\<const0> ;
+  assign s_axi_rdata[10] = \\<const0> ;
+  assign s_axi_rdata[9] = \\<const0> ;
+  assign s_axi_rdata[8] = \\<const0> ;
+  assign s_axi_rdata[7] = \\<const0> ;
+  assign s_axi_rdata[6] = \\<const0> ;
+  assign s_axi_rdata[5] = \\<const0> ;
+  assign s_axi_rdata[4] = \\<const0> ;
+  assign s_axi_rdata[3:0] = \\^s_axi_rdata [3:0];
+  assign s_axi_rresp[1] = \\<const0> ;
+  assign s_axi_rresp[0] = \\<const0> ;
+  design_1_axi_gpio_1_0_axi_lite_ipif AXI_LITE_IPIF_I
+       (.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3]}),
+        .E(AXI_LITE_IPIF_I_n_6),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_17),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_10),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_11),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_12),
+        .\\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_reset(bus2ip_reset),
+        .bus2ip_rnw(bus2ip_rnw),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] ({ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(\\^s_axi_rdata ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata({s_axi_wdata[31:28],s_axi_wdata[3:0]}),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+  GND GND
+       (.G(\\<const0> ));
+  VCC VCC
+       (.P(\\<const1> ));
+  design_1_axi_gpio_1_0_GPIO_Core gpio_core_1
+       (.D({ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
+        .E(AXI_LITE_IPIF_I_n_6),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3]}),
+        .\\Not_Dual.gpio_Data_In_reg[1]_0 (AXI_LITE_IPIF_I_n_10),
+        .\\Not_Dual.gpio_Data_In_reg[2]_0 (AXI_LITE_IPIF_I_n_11),
+        .\\Not_Dual.gpio_Data_In_reg[3]_0 (AXI_LITE_IPIF_I_n_12),
+        .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
+        .SS(bus2ip_reset),
+        .bus2ip_cs(bus2ip_cs),
+        .bus2ip_rnw(bus2ip_rnw),
+        .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_17),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i(ip2bus_rdack_i),
+        .ip2bus_wrack_i_D1_reg(gpio_core_1_n_7),
+        .rst_reg(AXI_LITE_IPIF_I_n_7),
+        .s_axi_aclk(s_axi_aclk));
+  FDRE \\ip2bus_data_i_D1_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[28]),
+        .Q(ip2bus_data_i_D1[28]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[29]),
+        .Q(ip2bus_data_i_D1[29]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[30]),
+        .Q(ip2bus_data_i_D1[30]),
+        .R(bus2ip_reset));
+  FDRE \\ip2bus_data_i_D1_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_data[31]),
+        .Q(ip2bus_data_i_D1[31]),
+        .R(bus2ip_reset));
+  FDRE ip2bus_rdack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(ip2bus_rdack_i),
+        .Q(ip2bus_rdack_i_D1),
+        .R(bus2ip_reset));
+  FDRE ip2bus_wrack_i_D1_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_core_1_n_7),
+        .Q(ip2bus_wrack_i_D1),
+        .R(bus2ip_reset));
+endmodule
+
+module design_1_axi_gpio_1_0_axi_lite_ipif
+   (bus2ip_reset,
+    bus2ip_rnw,
+    bus2ip_cs,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_aresetn,
+    s_axi_rready,
+    s_axi_bready,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    Q,
+    gpio_io_t,
+    s_axi_wdata,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output bus2ip_reset;
+  output bus2ip_rnw;
+  output bus2ip_cs;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [2:0]s_axi_araddr;
+  input [2:0]s_axi_awaddr;
+  input s_axi_aresetn;
+  input s_axi_rready;
+  input s_axi_bready;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input [3:0]Q;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [3:0]Q;
+  wire bus2ip_cs;
+  wire bus2ip_reset;
+  wire bus2ip_rnw;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [3:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  design_1_axi_gpio_1_0_slave_attachment I_SLAVE_ATTACHMENT
+       (.D(D),
+        .E(E),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ),
+        .\\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw),
+        .\\Not_Dual.gpio_OE_reg[0] (\\Not_Dual.gpio_OE_reg[0] ),
+        .Q(Q),
+        .SR(bus2ip_reset),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .\\ip2bus_data_i_D1_reg[28] (\\ip2bus_data_i_D1_reg[28] ),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module design_1_axi_gpio_1_0_cdc_sync
+   (scndry_vect_out,
+    gpio_io_i,
+    s_axi_aclk);
+  output [3:0]scndry_vect_out;
+  input [3:0]gpio_io_i;
+  input s_axi_aclk;
+
+  wire [3:0]gpio_io_i;
+  wire s_axi_aclk;
+  wire s_level_out_bus_d1_cdc_to_0;
+  wire s_level_out_bus_d1_cdc_to_1;
+  wire s_level_out_bus_d1_cdc_to_2;
+  wire s_level_out_bus_d1_cdc_to_3;
+  wire s_level_out_bus_d2_0;
+  wire s_level_out_bus_d2_1;
+  wire s_level_out_bus_d2_2;
+  wire s_level_out_bus_d2_3;
+  wire s_level_out_bus_d3_0;
+  wire s_level_out_bus_d3_1;
+  wire s_level_out_bus_d3_2;
+  wire s_level_out_bus_d3_3;
+  wire [3:0]scndry_vect_out;
+
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_0),
+        .Q(s_level_out_bus_d2_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_1),
+        .Q(s_level_out_bus_d2_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_2),
+        .Q(s_level_out_bus_d2_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d1_cdc_to_3),
+        .Q(s_level_out_bus_d2_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_0),
+        .Q(s_level_out_bus_d3_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_1),
+        .Q(s_level_out_bus_d3_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_2),
+        .Q(s_level_out_bus_d3_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d2_3),
+        .Q(s_level_out_bus_d3_3),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_0),
+        .Q(scndry_vect_out[0]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_1),
+        .Q(scndry_vect_out[1]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_2),
+        .Q(scndry_vect_out[2]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_level_out_bus_d3_3),
+        .Q(scndry_vect_out[3]),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[0]),
+        .Q(s_level_out_bus_d1_cdc_to_0),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[1]),
+        .Q(s_level_out_bus_d1_cdc_to_1),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[2]),
+        .Q(s_level_out_bus_d1_cdc_to_2),
+        .R(1\'b0));
+  (* ASYNC_REG *) 
+  (* XILINX_LEGACY_PRIM = ""FDR"" *) 
+  (* box_type = ""PRIMITIVE"" *) 
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(gpio_io_i[3]),
+        .Q(s_level_out_bus_d1_cdc_to_3),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_axi_gpio_1_0,axi_gpio,{}"" *) (* downgradeipidentifiedwarnings = ""yes"" *) (* x_core_info = ""axi_gpio,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module design_1_axi_gpio_1_0
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    gpio_io_i,
+    gpio_io_o,
+    gpio_io_t);
+  (* x_interface_info = ""xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"" *) input s_axi_aclk;
+  (* x_interface_info = ""xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"" *) input s_axi_aresetn;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *) input [8:0]s_axi_awaddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *) input s_axi_awvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *) output s_axi_awready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *) input s_axi_wvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *) output s_axi_wready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *) output s_axi_bvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *) input s_axi_bready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *) input [8:0]s_axi_araddr;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *) input s_axi_arvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *) output s_axi_arready;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *) output s_axi_rvalid;
+  (* x_interface_info = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *) input s_axi_rready;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_I"" *) input [3:0]gpio_io_i;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_O"" *) output [3:0]gpio_io_o;
+  (* x_interface_info = ""xilinx.com:interface:gpio:1.0 GPIO TRI_T"" *) output [3:0]gpio_io_t;
+
+  wire [3:0]gpio_io_i;
+  wire [3:0]gpio_io_o;
+  wire [3:0]gpio_io_t;
+  wire s_axi_aclk;
+  wire [8:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [8:0]s_axi_awaddr;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire s_axi_wvalid;
+  wire NLW_U0_ip2intc_irpt_UNCONNECTED;
+  wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
+  wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
+
+  (* C_ALL_INPUTS = ""0"" *) 
+  (* C_ALL_INPUTS_2 = ""0"" *) 
+  (* C_ALL_OUTPUTS = ""0"" *) 
+  (* C_ALL_OUTPUTS_2 = ""0"" *) 
+  (* C_DOUT_DEFAULT = ""0"" *) 
+  (* C_DOUT_DEFAULT_2 = ""0"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_GPIO2_WIDTH = ""32"" *) 
+  (* C_GPIO_WIDTH = ""4"" *) 
+  (* C_INTERRUPT_PRESENT = ""0"" *) 
+  (* C_IS_DUAL = ""0"" *) 
+  (* C_S_AXI_ADDR_WIDTH = ""9"" *) 
+  (* C_S_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_TRI_DEFAULT = ""-1"" *) 
+  (* C_TRI_DEFAULT_2 = ""-1"" *) 
+  (* downgradeipidentifiedwarnings = ""yes"" *) 
+  (* ip_group = ""LOGICORE"" *) 
+  design_1_axi_gpio_1_0_axi_gpio U0
+       (.gpio2_io_i({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
+        .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
+        .gpio_io_i(gpio_io_i),
+        .gpio_io_o(gpio_io_o),
+        .gpio_io_t(gpio_io_t),
+        .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module design_1_axi_gpio_1_0_slave_attachment
+   (SR,
+    \\Not_Dual.gpio_Data_Out_reg[0] ,
+    \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
+    s_axi_rvalid,
+    s_axi_bvalid,
+    s_axi_arready,
+    E,
+    \\Not_Dual.gpio_OE_reg[0] ,
+    s_axi_wready,
+    GPIO_DBus_i,
+    \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ,
+    \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ,
+    \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ,
+    D,
+    \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ,
+    s_axi_rdata,
+    s_axi_aclk,
+    s_axi_arvalid,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_araddr,
+    s_axi_awaddr,
+    s_axi_aresetn,
+    s_axi_rready,
+    s_axi_bready,
+    ip2bus_rdack_i_D1,
+    ip2bus_wrack_i_D1,
+    Q,
+    gpio_io_t,
+    s_axi_wdata,
+    gpio_xferAck_Reg,
+    GPIO_xferAck_i,
+    \\ip2bus_data_i_D1_reg[28] );
+  output SR;
+  output \\Not_Dual.gpio_Data_Out_reg[0] ;
+  output \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  output s_axi_rvalid;
+  output s_axi_bvalid;
+  output s_axi_arready;
+  output [0:0]E;
+  output [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  output s_axi_wready;
+  output [0:0]GPIO_DBus_i;
+  output \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  output \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  output \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  output [3:0]D;
+  output \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  output [3:0]s_axi_rdata;
+  input s_axi_aclk;
+  input s_axi_arvalid;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input [2:0]s_axi_araddr;
+  input [2:0]s_axi_awaddr;
+  input s_axi_aresetn;
+  input s_axi_rready;
+  input s_axi_bready;
+  input ip2bus_rdack_i_D1;
+  input ip2bus_wrack_i_D1;
+  input [3:0]Q;
+  input [3:0]gpio_io_t;
+  input [7:0]s_axi_wdata;
+  input gpio_xferAck_Reg;
+  input GPIO_xferAck_i;
+  input [3:0]\\ip2bus_data_i_D1_reg[28] ;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [0:0]GPIO_DBus_i;
+  wire GPIO_xferAck_i;
+  wire [3:0]\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
+  wire \\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
+  wire \\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ;
+  wire \\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ;
+  wire \\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ;
+  wire \\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ;
+  wire \\Not_Dual.gpio_Data_Out_reg[0] ;
+  wire [0:0]\\Not_Dual.gpio_OE_reg[0] ;
+  wire [3:0]Q;
+  wire SR;
+  wire [0:6]bus2ip_addr;
+  wire \\bus2ip_addr_i[2]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[3]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_1_n_0 ;
+  wire \\bus2ip_addr_i[8]_i_2_n_0 ;
+  wire bus2ip_rnw_i06_out;
+  wire clear;
+  wire [3:0]gpio_io_t;
+  wire gpio_xferAck_Reg;
+  wire [3:0]\\ip2bus_data_i_D1_reg[28] ;
+  wire ip2bus_rdack_i_D1;
+  wire ip2bus_wrack_i_D1;
+  wire is_read;
+  wire is_read_i_1_n_0;
+  wire is_write;
+  wire is_write_i_1_n_0;
+  wire is_write_reg_n_0;
+  wire [1:0]p_0_out;
+  wire p_1_in;
+  wire [3:0]plusOp;
+  wire s_axi_aclk;
+  wire [2:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire [2:0]s_axi_awaddr;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_i_i_1_n_0;
+  wire [3:0]s_axi_rdata;
+  wire \\s_axi_rdata_i[3]_i_1_n_0 ;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_i_i_1_n_0;
+  wire [7:0]s_axi_wdata;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+  wire start2;
+  wire start2_i_1_n_0;
+  wire [1:0]state;
+  wire state1__2;
+  wire \\state[1]_i_3_n_0 ;
+
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .O(plusOp[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT2 #(
+    .INIT(4\'h6)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .O(plusOp[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT3 #(
+    .INIT(8\'h78)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .O(plusOp[2]));
+  LUT2 #(
+    .INIT(4\'h9)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(clear));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'h7F80)) 
+    \\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 
+       (.I0(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .I1(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .I2(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .I3(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .O(plusOp[3]));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[0]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[1]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[2]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
+        .R(clear));
+  FDRE \\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(plusOp[3]),
+        .Q(\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
+        .R(clear));
+  design_1_axi_gpio_1_0_address_decoder I_DECODER
+       (.D(D),
+        .E(E),
+        .GPIO_DBus_i(GPIO_DBus_i),
+        .GPIO_xferAck_i(GPIO_xferAck_i),
+        .\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
+        .\\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
+        .\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] (\\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28] ),
+        .\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] (\\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29] ),
+        .\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] (\\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30] ),
+        .\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] (\\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31] ),
+        .\\Not_Dual.gpio_Data_In_reg[0] (Q),
+        .\\Not_Dual.gpio_OE_reg[0] (\\Not_Dual.gpio_OE_reg[0] ),
+        .Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
+        .bus2ip_rnw_i_reg(\\Not_Dual.gpio_Data_Out_reg[0] ),
+        .gpio_io_t(gpio_io_t),
+        .gpio_xferAck_Reg(gpio_xferAck_Reg),
+        .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
+        .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
+        .is_read(is_read),
+        .is_write_reg(is_write_reg_n_0),
+        .rst_reg(SR),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wready(s_axi_wready),
+        .start2_reg(start2));
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[2]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_awaddr[0]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[2]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[3]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_awaddr[1]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h000000EA)) 
+    \\bus2ip_addr_i[8]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_wvalid),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(\\bus2ip_addr_i[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'hCCCACCCC)) 
+    \\bus2ip_addr_i[8]_i_2 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_awaddr[2]),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(s_axi_arvalid),
+        .O(\\bus2ip_addr_i[8]_i_2_n_0 ));
+  FDRE \\bus2ip_addr_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[2]_i_1_n_0 ),
+        .Q(bus2ip_addr[6]),
+        .R(SR));
+  FDRE \\bus2ip_addr_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[3]_i_1_n_0 ),
+        .Q(bus2ip_addr[5]),
+        .R(SR));
+  FDRE \\bus2ip_addr_i_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(\\bus2ip_addr_i[8]_i_2_n_0 ),
+        .Q(bus2ip_addr[0]),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT3 #(
+    .INIT(8\'h10)) 
+    bus2ip_rnw_i_i_1
+       (.I0(state[0]),
+        .I1(state[1]),
+        .I2(s_axi_arvalid),
+        .O(bus2ip_rnw_i06_out));
+  FDRE bus2ip_rnw_i_reg
+       (.C(s_axi_aclk),
+        .CE(\\bus2ip_addr_i[8]_i_1_n_0 ),
+        .D(bus2ip_rnw_i06_out),
+        .Q(\\Not_Dual.gpio_Data_Out_reg[0] ),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h3FFA000A)) 
+    is_read_i_1
+       (.I0(s_axi_arvalid),
+        .I1(state1__2),
+        .I2(state[0]),
+        .I3(state[1]),
+        .I4(is_read),
+        .O(is_read_i_1_n_0));
+  FDRE is_read_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_read_i_1_n_0),
+        .Q(is_read),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0040FFFF00400000)) 
+    is_write_i_1
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_wvalid),
+        .I3(state[1]),
+        .I4(is_write),
+        .I5(is_write_reg_n_0),
+        .O(is_write_i_1_n_0));
+  LUT6 #(
+    .INIT(64\'hF88800000000FFFF)) 
+    is_write_i_2
+       (.I0(s_axi_rvalid),
+        .I1(s_axi_rready),
+        .I2(s_axi_bvalid),
+        .I3(s_axi_bready),
+        .I4(state[0]),
+        .I5(state[1]),
+        .O(is_write));
+  FDRE is_write_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(is_write_i_1_n_0),
+        .Q(is_write_reg_n_0),
+        .R(SR));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    rst_i_1
+       (.I0(s_axi_aresetn),
+        .O(p_1_in));
+  FDRE rst_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_1_in),
+        .Q(SR),
+        .R(1\'b0));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_bvalid_i_i_1
+       (.I0(s_axi_wready),
+        .I1(state[1]),
+        .I2(state[0]),
+        .I3(s_axi_bready),
+        .I4(s_axi_bvalid),
+        .O(s_axi_bvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_bvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_bvalid_i_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(SR));
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_rdata_i[3]_i_1 
+       (.I0(state[0]),
+        .I1(state[1]),
+        .O(\\s_axi_rdata_i[3]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [0]),
+        .Q(s_axi_rdata[0]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [1]),
+        .Q(s_axi_rdata[1]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [2]),
+        .Q(s_axi_rdata[2]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\s_axi_rdata_i_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(\\s_axi_rdata_i[3]_i_1_n_0 ),
+        .D(\\ip2bus_data_i_D1_reg[28] [3]),
+        .Q(s_axi_rdata[3]),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h08FF0808)) 
+    s_axi_rvalid_i_i_1
+       (.I0(s_axi_arready),
+        .I1(state[0]),
+        .I2(state[1]),
+        .I3(s_axi_rready),
+        .I4(s_axi_rvalid),
+        .O(s_axi_rvalid_i_i_1_n_0));
+  FDRE #(
+    .INIT(1\'b0)) 
+    s_axi_rvalid_i_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(s_axi_rvalid_i_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h000000F8)) 
+    start2_i_1
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_arvalid),
+        .I3(state[1]),
+        .I4(state[0]),
+        .O(start2_i_1_n_0));
+  FDRE start2_reg
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(start2_i_1_n_0),
+        .Q(start2),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h77FC44FC)) 
+    \\state[0]_i_1 
+       (.I0(state1__2),
+        .I1(state[0]),
+        .I2(s_axi_arvalid),
+        .I3(state[1]),
+        .I4(s_axi_wready),
+        .O(p_0_out[0]));
+  LUT5 #(
+    .INIT(32\'h5FFC50FC)) 
+    \\state[1]_i_1 
+       (.I0(state1__2),
+        .I1(\\state[1]_i_3_n_0 ),
+        .I2(state[1]),
+        .I3(state[0]),
+        .I4(s_axi_arready),
+        .O(p_0_out[1]));
+  LUT4 #(
+    .INIT(16\'hF888)) 
+    \\state[1]_i_2 
+       (.I0(s_axi_bready),
+        .I1(s_axi_bvalid),
+        .I2(s_axi_rready),
+        .I3(s_axi_rvalid),
+        .O(state1__2));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT3 #(
+    .INIT(8\'h08)) 
+    \\state[1]_i_3 
+       (.I0(s_axi_wvalid),
+        .I1(s_axi_awvalid),
+        .I2(s_axi_arvalid),
+        .O(\\state[1]_i_3_n_0 ));
+  FDRE \\state_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[0]),
+        .Q(state[0]),
+        .R(SR));
+  FDRE \\state_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1\'b1),
+        .D(p_0_out[1]),
+        .Q(state[1]),
+        .R(SR));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"/*
+ *******************************************************************************
+ *
+ * FIFO Generator - Verilog Behavioral Model
+ *
+ *******************************************************************************
+ *
+ * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
+ *
+ * This file contains confidential and proprietary information
+ * of Xilinx, Inc. and is protected under U.S. and
+ * international copyright and other intellectual property
+ * laws.
+ *
+ * DISCLAIMER
+ * This disclaimer is not a license and does not grant any
+ * rights to the materials distributed herewith. Except as
+ * otherwise provided in a valid license issued to you by
+ * Xilinx, and to the maximum extent permitted by applicable
+ * law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+ * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ * (2) Xilinx shall not be liable (whether in contract or tort,
+ * including negligence, or under any other theory of
+ * liability) for any loss or damage of any kind or nature
+ * related to, arising under or in connection with these
+ * materials, including for any direct, or any indirect,
+ * special, incidental, or consequential loss or damage
+ * (including loss of data, profits, goodwill, or any type of
+ * loss or damage suffered as a result of any action brought
+ * by a third party) even if such damage or loss was
+ * reasonably foreseeable or Xilinx had been advised of the
+ * possibility of the same.
+ *
+ * CRITICAL APPLICATIONS
+ * Xilinx products are not designed or intended to be fail-
+ * safe, or for use in any application requiring fail-safe
+ * performance, such as life-support or safety devices or
+ * systems, Class III medical devices, nuclear facilities,
+ * applications related to the deployment of airbags, or any
+ * other applications that could lead to death, personal
+ * injury, or severe property or environmental damage
+ * (individually and collectively, ""Critical
+ * Applications""). Customer assumes the sole risk and
+ * liability of any use of Xilinx products in Critical
+ * Applications, subject only to applicable laws and
+ * regulations governing limitations on product liability.
+ *
+ * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ * PART OF THIS FILE AT ALL TIMES.
+ *
+ *******************************************************************************
+ *******************************************************************************
+ *
+ * Filename: fifo_generator_vlog_beh.v
+ *
+ * Author     : Xilinx
+ *
+ *******************************************************************************
+ * Structure:
+ * 
+ * fifo_generator_vlog_beh.v
+ *    |
+ *    +-fifo_generator_v13_1_3_bhv_ver_as
+ *    |
+ *    +-fifo_generator_v13_1_3_bhv_ver_ss
+ *    |
+ *    +-fifo_generator_v13_1_3_bhv_ver_preload0
+ * 
+ *******************************************************************************
+ * Description:
+ *
+ * The Verilog behavioral model for the FIFO Generator.
+ *
+ *   The behavioral model has three parts:
+ *      - The behavioral model for independent clocks FIFOs (_as)
+ *      - The behavioral model for common clock FIFOs (_ss)
+ *      - The ""preload logic"" block which implements First-word Fall-through
+ * 
+ *******************************************************************************
+ * Description:
+ *  The verilog behavioral model for the FIFO generator core.
+ *
+ *******************************************************************************
+ */
+
+`timescale 1ps/1ps
+`ifndef TCQ
+ `define TCQ 100
+`endif
+
+
+/*******************************************************************************
+ * Declaration of top-level module
+ ******************************************************************************/
+module fifo_generator_vlog_beh
+  #(
+    //-----------------------------------------------------------------------
+    // Generic Declarations
+    //-----------------------------------------------------------------------
+    parameter C_COMMON_CLOCK                 = 0,
+    parameter C_COUNT_TYPE                   = 0,
+    parameter C_DATA_COUNT_WIDTH             = 2,
+    parameter C_DEFAULT_VALUE                = """",
+    parameter C_DIN_WIDTH                    = 8,
+    parameter C_DOUT_RST_VAL                 = """",
+    parameter C_DOUT_WIDTH                   = 8,
+    parameter C_ENABLE_RLOCS                 = 0,
+    parameter C_FAMILY                       = """",
+    parameter C_FULL_FLAGS_RST_VAL           = 1,
+    parameter C_HAS_ALMOST_EMPTY             = 0,
+    parameter C_HAS_ALMOST_FULL              = 0,
+    parameter C_HAS_BACKUP                   = 0,
+    parameter C_HAS_DATA_COUNT               = 0,
+    parameter C_HAS_INT_CLK                  = 0,
+    parameter C_HAS_MEMINIT_FILE             = 0,
+    parameter C_HAS_OVERFLOW                 = 0,
+    parameter C_HAS_RD_DATA_COUNT            = 0,
+    parameter C_HAS_RD_RST                   = 0,
+    parameter C_HAS_RST                      = 1,
+    parameter C_HAS_SRST                     = 0,
+    parameter C_HAS_UNDERFLOW                = 0,
+    parameter C_HAS_VALID                    = 0,
+    parameter C_HAS_WR_ACK                   = 0,
+    parameter C_HAS_WR_DATA_COUNT            = 0,
+    parameter C_HAS_WR_RST                   = 0,
+    parameter C_IMPLEMENTATION_TYPE          = 0,
+    parameter C_INIT_WR_PNTR_VAL             = 0,
+    parameter C_MEMORY_TYPE                  = 1,
+    parameter C_MIF_FILE_NAME                = """",
+    parameter C_OPTIMIZATION_MODE            = 0,
+    parameter C_OVERFLOW_LOW                 = 0,
+    parameter C_EN_SAFETY_CKT                = 0,
+    parameter C_PRELOAD_LATENCY              = 1,
+    parameter C_PRELOAD_REGS                 = 0,
+    parameter C_PRIM_FIFO_TYPE               = ""4kx4"",
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
+    parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
+    parameter C_PROG_EMPTY_TYPE              = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL  = 0,
+    parameter C_PROG_FULL_THRESH_NEGATE_VAL  = 0,
+    parameter C_PROG_FULL_TYPE               = 0,
+    parameter C_RD_DATA_COUNT_WIDTH          = 2,
+    parameter C_RD_DEPTH                     = 256,
+    parameter C_RD_FREQ                      = 1,
+    parameter C_RD_PNTR_WIDTH                = 8,
+    parameter C_UNDERFLOW_LOW                = 0,
+    parameter C_USE_DOUT_RST                 = 0,
+    parameter C_USE_ECC                      = 0,
+    parameter C_USE_EMBEDDED_REG             = 0,
+    parameter C_USE_PIPELINE_REG             = 0,
+    parameter C_POWER_SAVING_MODE            = 0,
+    parameter C_USE_FIFO16_FLAGS             = 0,
+    parameter C_USE_FWFT_DATA_COUNT          = 0,
+    parameter C_VALID_LOW                    = 0,
+    parameter C_WR_ACK_LOW                   = 0,
+    parameter C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter C_WR_DEPTH                     = 256,
+    parameter C_WR_FREQ                      = 1,
+    parameter C_WR_PNTR_WIDTH                = 8,
+    parameter C_WR_RESPONSE_LATENCY          = 1,
+    parameter C_MSGON_VAL                    = 1,
+    parameter C_ENABLE_RST_SYNC              = 1,
+    parameter C_ERROR_INJECTION_TYPE         = 0,
+    parameter C_SYNCHRONIZER_STAGE           = 2,
+
+    // AXI Interface related parameters start here
+    parameter C_INTERFACE_TYPE               = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
+    parameter C_AXI_TYPE                     = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
+    parameter C_HAS_AXI_WR_CHANNEL           = 0,
+    parameter C_HAS_AXI_RD_CHANNEL           = 0,
+    parameter C_HAS_SLAVE_CE                 = 0,
+    parameter C_HAS_MASTER_CE                = 0,
+    parameter C_ADD_NGC_CONSTRAINT           = 0,
+    parameter C_USE_COMMON_UNDERFLOW         = 0,
+    parameter C_USE_COMMON_OVERFLOW          = 0,
+    parameter C_USE_DEFAULT_SETTINGS         = 0,
+
+    // AXI Full/Lite
+    parameter C_AXI_ID_WIDTH                 = 0,
+    parameter C_AXI_ADDR_WIDTH               = 0,
+    parameter C_AXI_DATA_WIDTH               = 0,
+    parameter C_AXI_LEN_WIDTH                = 8,
+    parameter C_AXI_LOCK_WIDTH               = 2,
+    parameter C_HAS_AXI_ID                   = 0,
+    parameter C_HAS_AXI_AWUSER               = 0,
+    parameter C_HAS_AXI_WUSER                = 0,
+    parameter C_HAS_AXI_BUSER                = 0,
+    parameter C_HAS_AXI_ARUSER               = 0,
+    parameter C_HAS_AXI_RUSER                = 0,
+    parameter C_AXI_ARUSER_WIDTH             = 0,
+    parameter C_AXI_AWUSER_WIDTH             = 0,
+    parameter C_AXI_WUSER_WIDTH              = 0,
+    parameter C_AXI_BUSER_WIDTH              = 0,
+    parameter C_AXI_RUSER_WIDTH              = 0,
+
+    // AXI Streaming
+    parameter C_HAS_AXIS_TDATA               = 0,
+    parameter C_HAS_AXIS_TID                 = 0,
+    parameter C_HAS_AXIS_TDEST               = 0,
+    parameter C_HAS_AXIS_TUSER               = 0,
+    parameter C_HAS_AXIS_TREADY              = 0,
+    parameter C_HAS_AXIS_TLAST               = 0,
+    parameter C_HAS_AXIS_TSTRB               = 0,
+    parameter C_HAS_AXIS_TKEEP               = 0,
+    parameter C_AXIS_TDATA_WIDTH             = 1,
+    parameter C_AXIS_TID_WIDTH               = 1,
+    parameter C_AXIS_TDEST_WIDTH             = 1,
+    parameter C_AXIS_TUSER_WIDTH             = 1,
+    parameter C_AXIS_TSTRB_WIDTH             = 1,
+    parameter C_AXIS_TKEEP_WIDTH             = 1,
+
+    // AXI Channel Type
+    // WACH --> Write Address Channel
+    // WDCH --> Write Data Channel
+    // WRCH --> Write Response Channel
+    // RACH --> Read Address Channel
+    // RDCH --> Read Data Channel
+    // AXIS --> AXI Streaming
+    parameter C_WACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
+    parameter C_WDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+    parameter C_WRCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+    parameter C_RACH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+    parameter C_RDCH_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+    parameter C_AXIS_TYPE                    = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
+
+    // AXI Implementation Type
+    // 1 = Common Clock Block RAM FIFO
+    // 2 = Common Clock Distributed RAM FIFO
+    // 11 = Independent Clock Block RAM FIFO
+    // 12 = Independent Clock Distributed RAM FIFO
+    parameter C_IMPLEMENTATION_TYPE_WACH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_WDCH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_WRCH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_RACH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_RDCH     = 0,
+    parameter C_IMPLEMENTATION_TYPE_AXIS     = 0,
+
+    // AXI FIFO Type
+    // 0 = Data FIFO
+    // 1 = Packet FIFO
+    // 2 = Low Latency Sync FIFO
+    // 3 = Low Latency Async FIFO
+    parameter C_APPLICATION_TYPE_WACH        = 0,
+    parameter C_APPLICATION_TYPE_WDCH        = 0,
+    parameter C_APPLICATION_TYPE_WRCH        = 0,
+    parameter C_APPLICATION_TYPE_RACH        = 0,
+    parameter C_APPLICATION_TYPE_RDCH        = 0,
+    parameter C_APPLICATION_TYPE_AXIS        = 0,
+
+    // AXI Built-in FIFO Primitive Type
+    // 512x36, 1kx18, 2kx9, 4kx4, etc
+    parameter C_PRIM_FIFO_TYPE_WACH          = ""512x36"",
+    parameter C_PRIM_FIFO_TYPE_WDCH          = ""512x36"",
+    parameter C_PRIM_FIFO_TYPE_WRCH          = ""512x36"",
+    parameter C_PRIM_FIFO_TYPE_RACH          = ""512x36"",
+    parameter C_PRIM_FIFO_TYPE_RDCH          = ""512x36"",
+    parameter C_PRIM_FIFO_TYPE_AXIS          = ""512x36"",
+
+    // Enable ECC
+    // 0 = ECC disabled
+    // 1 = ECC enabled
+    parameter C_USE_ECC_WACH                 = 0,
+    parameter C_USE_ECC_WDCH                 = 0,
+    parameter C_USE_ECC_WRCH                 = 0,
+    parameter C_USE_ECC_RACH                 = 0,
+    parameter C_USE_ECC_RDCH                 = 0,
+    parameter C_USE_ECC_AXIS                 = 0,
+
+    // ECC Error Injection Type
+    // 0 = No Error Injection
+    // 1 = Single Bit Error Injection
+    // 2 = Double Bit Error Injection
+    // 3 = Single Bit and Double Bit Error Injection
+    parameter C_ERROR_INJECTION_TYPE_WACH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_WDCH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_WRCH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_RACH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_RDCH    = 0,
+    parameter C_ERROR_INJECTION_TYPE_AXIS    = 0,
+
+    // Input Data Width
+    // Accumulation of all AXI input signal\'s width
+    parameter C_DIN_WIDTH_WACH               = 1,
+    parameter C_DIN_WIDTH_WDCH               = 1,
+    parameter C_DIN_WIDTH_WRCH               = 1,
+    parameter C_DIN_WIDTH_RACH               = 1,
+    parameter C_DIN_WIDTH_RDCH               = 1,
+    parameter C_DIN_WIDTH_AXIS               = 1,
+
+    parameter C_WR_DEPTH_WACH                = 16,
+    parameter C_WR_DEPTH_WDCH                = 16,
+    parameter C_WR_DEPTH_WRCH                = 16,
+    parameter C_WR_DEPTH_RACH                = 16,
+    parameter C_WR_DEPTH_RDCH                = 16,
+    parameter C_WR_DEPTH_AXIS                = 16,
+
+    parameter C_WR_PNTR_WIDTH_WACH           = 4,
+    parameter C_WR_PNTR_WIDTH_WDCH           = 4,
+    parameter C_WR_PNTR_WIDTH_WRCH           = 4,
+    parameter C_WR_PNTR_WIDTH_RACH           = 4,
+    parameter C_WR_PNTR_WIDTH_RDCH           = 4,
+    parameter C_WR_PNTR_WIDTH_AXIS           = 4,
+
+    parameter C_HAS_DATA_COUNTS_WACH         = 0,
+    parameter C_HAS_DATA_COUNTS_WDCH         = 0,
+    parameter C_HAS_DATA_COUNTS_WRCH         = 0,
+    parameter C_HAS_DATA_COUNTS_RACH         = 0,
+    parameter C_HAS_DATA_COUNTS_RDCH         = 0,
+    parameter C_HAS_DATA_COUNTS_AXIS         = 0,
+
+    parameter C_HAS_PROG_FLAGS_WACH          = 0,
+    parameter C_HAS_PROG_FLAGS_WDCH          = 0,
+    parameter C_HAS_PROG_FLAGS_WRCH          = 0,
+    parameter C_HAS_PROG_FLAGS_RACH          = 0,
+    parameter C_HAS_PROG_FLAGS_RDCH          = 0,
+    parameter C_HAS_PROG_FLAGS_AXIS          = 0,
+
+    parameter C_PROG_FULL_TYPE_WACH          = 0,
+    parameter C_PROG_FULL_TYPE_WDCH          = 0,
+    parameter C_PROG_FULL_TYPE_WRCH          = 0,
+    parameter C_PROG_FULL_TYPE_RACH          = 0,
+    parameter C_PROG_FULL_TYPE_RDCH          = 0,
+    parameter C_PROG_FULL_TYPE_AXIS          = 0,
+
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH      = 0,
+    parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS      = 0,
+
+    parameter C_PROG_EMPTY_TYPE_WACH         = 0,
+    parameter C_PROG_EMPTY_TYPE_WDCH         = 0,
+    parameter C_PROG_EMPTY_TYPE_WRCH         = 0,
+    parameter C_PROG_EMPTY_TYPE_RACH         = 0,
+    parameter C_PROG_EMPTY_TYPE_RDCH         = 0,
+    parameter C_PROG_EMPTY_TYPE_AXIS         = 0,
+
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH     = 0,
+    parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS     = 0,
+
+    parameter C_REG_SLICE_MODE_WACH          = 0,
+    parameter C_REG_SLICE_MODE_WDCH          = 0,
+    parameter C_REG_SLICE_MODE_WRCH          = 0,
+    parameter C_REG_SLICE_MODE_RACH          = 0,
+    parameter C_REG_SLICE_MODE_RDCH          = 0,
+    parameter C_REG_SLICE_MODE_AXIS          = 0
+
+    )
+
+   (
+    //------------------------------------------------------------------------------
+    // Input and Output Declarations
+    //------------------------------------------------------------------------------
+
+    // Conventional FIFO Interface Signals
+    input                               backup,
+    input                               backup_marker,
+    input                               clk,
+    input                               rst,
+    input                               srst,
+    input                               wr_clk,
+    input                               wr_rst,
+    input                               rd_clk,
+    input                               rd_rst,
+    input [C_DIN_WIDTH-1:0]             din,
+    input                               wr_en,
+    input                               rd_en,
+    // Optional inputs
+    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh,
+    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_assert,
+    input [C_RD_PNTR_WIDTH-1:0]         prog_empty_thresh_negate,
+    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh,
+    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_assert,
+    input [C_WR_PNTR_WIDTH-1:0]         prog_full_thresh_negate,
+    input                               int_clk,
+    input                               injectdbiterr,
+    input                               injectsbiterr,
+    input                               sleep,
+
+    output [C_DOUT_WIDTH-1:0]           dout,
+    output                              full,
+    output                              almost_full,
+    output                              wr_ack,
+    output                              overflow,
+    output                              empty,
+    output                              almost_empty,
+    output                              valid,
+    output                              underflow,
+    output [C_DATA_COUNT_WIDTH-1:0]     data_count,
+    output [C_RD_DATA_COUNT_WIDTH-1:0]  rd_data_count,
+    output [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count,
+    output                              prog_full,
+    output                              prog_empty,
+    output                              sbiterr,
+    output                              dbiterr,
+    output                              wr_rst_busy,
+    output                              rd_rst_busy,
+
+
+    // AXI Global Signal
+    input                               m_aclk,
+    input                               s_aclk,
+    input                               s_aresetn,
+    input                               s_aclk_en,
+    input                               m_aclk_en,
+    
+    // AXI Full/Lite Slave Write Channel (write side)
+    input [C_AXI_ID_WIDTH-1:0]          s_axi_awid,
+    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr,
+    input [C_AXI_LEN_WIDTH-1:0]         s_axi_awlen,
+    input [3-1:0]                       s_axi_awsize,
+    input [2-1:0]                       s_axi_awburst,
+    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_awlock,
+    input [4-1:0]                       s_axi_awcache,
+    input [3-1:0]                       s_axi_awprot,
+    input [4-1:0]                       s_axi_awqos,
+    input [4-1:0]                       s_axi_awregion,
+    input [C_AXI_AWUSER_WIDTH-1:0]      s_axi_awuser,
+    input                               s_axi_awvalid,
+    output                              s_axi_awready,
+    input [C_AXI_ID_WIDTH-1:0]          s_axi_wid,
+    input [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata,
+    input [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb,
+    input                               s_axi_wlast,
+    input [C_AXI_WUSER_WIDTH-1:0]       s_axi_wuser,
+    input                               s_axi_wvalid,
+    output                              s_axi_wready,
+    output [C_AXI_ID_WIDTH-1:0]         s_axi_bid,
+    output [2-1:0]                      s_axi_bresp,
+    output [C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,
+    output                              s_axi_bvalid,
+    input                               s_axi_bready,
+    
+    // AXI Full/Lite Master Write Channel (read side)
+    output [C_AXI_ID_WIDTH-1:0]         m_axi_awid,
+    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_awaddr,
+    output [C_AXI_LEN_WIDTH-1:0]        m_axi_awlen,
+    output [3-1:0]                      m_axi_awsize,
+    output [2-1:0]                      m_axi_awburst,
+    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_awlock,
+    output [4-1:0]                      m_axi_awcache,
+    output [3-1:0]                      m_axi_awprot,
+    output [4-1:0]                      m_axi_awqos,
+    output [4-1:0]                      m_axi_awregion,
+    output [C_AXI_AWUSER_WIDTH-1:0]     m_axi_awuser,
+    output                              m_axi_awvalid,
+    input                               m_axi_awready,
+    output [C_AXI_ID_WIDTH-1:0]         m_axi_wid,
+    output [C_AXI_DATA_WIDTH-1:0]       m_axi_wdata,
+    output [C_AXI_DATA_WIDTH/8-1:0]     m_axi_wstrb,
+    output                              m_axi_wlast,
+    output [C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,
+    output                              m_axi_wvalid,
+    input                               m_axi_wready,
+    input [C_AXI_ID_WIDTH-1:0]          m_axi_bid,
+    input [2-1:0]                       m_axi_bresp,
+    input [C_AXI_BUSER_WIDTH-1:0]       m_axi_buser,
+    input                               m_axi_bvalid,
+    output                              m_axi_bready,
+    
+    
+    // AXI Full/Lite Slave Read Channel (write side)
+    input [C_AXI_ID_WIDTH-1:0]          s_axi_arid,
+    input [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr, 
+    input [C_AXI_LEN_WIDTH-1:0]         s_axi_arlen,
+    input [3-1:0]                       s_axi_arsize,
+    input [2-1:0]                       s_axi_arburst,
+    input [C_AXI_LOCK_WIDTH-1:0]        s_axi_arlock,
+    input [4-1:0]                       s_axi_arcache,
+    input [3-1:0]                       s_axi_arprot,
+    input [4-1:0]                       s_axi_arqos,
+    input [4-1:0]                       s_axi_arregion,
+    input [C_AXI_ARUSER_WIDTH-1:0]      s_axi_aruser,
+    input                               s_axi_arvalid,
+    output                              s_axi_arready,
+    output [C_AXI_ID_WIDTH-1:0]         s_axi_rid,       
+    output [C_AXI_DATA_WIDTH-1:0]       s_axi_rdata, 
+    output [2-1:0]                      s_axi_rresp,
+    output                              s_axi_rlast,
+    output [C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,
+    output                              s_axi_rvalid,
+    input                               s_axi_rready,
+    
+    
+    
+    // AXI Full/Lite Master Read Channel (read side)
+    output [C_AXI_ID_WIDTH-1:0]         m_axi_arid,        
+    output [C_AXI_ADDR_WIDTH-1:0]       m_axi_araddr,  
+    output [C_AXI_LEN_WIDTH-1:0]        m_axi_arlen,
+    output [3-1:0]                      m_axi_arsize,
+    output [2-1:0]                      m_axi_arburst,
+    output [C_AXI_LOCK_WIDTH-1:0]       m_axi_arlock,
+    output [4-1:0]                      m_axi_arcache,
+    output [3-1:0]                      m_axi_arprot,
+    output [4-1:0]                      m_axi_arqos,
+    output [4-1:0]                      m_axi_arregion,
+    output [C_AXI_ARUSER_WIDTH-1:0]     m_axi_aruser,
+    output                              m_axi_arvalid,
+    input                               m_axi_arready,
+    input [C_AXI_ID_WIDTH-1:0]          m_axi_rid,        
+    input [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata,  
+    input [2-1:0]                       m_axi_rresp,
+    input                               m_axi_rlast,
+    input [C_AXI_RUSER_WIDTH-1:0]       m_axi_ruser,
+    input                               m_axi_rvalid,
+    output                              m_axi_rready,
+    
+    
+    // AXI Streaming Slave Signals (Write side)
+    input                               s_axis_tvalid,
+    output                              s_axis_tready,
+    input [C_AXIS_TDATA_WIDTH-1:0]      s_axis_tdata,
+    input [C_AXIS_TSTRB_WIDTH-1:0]      s_axis_tstrb,
+    input [C_AXIS_TKEEP_WIDTH-1:0]      s_axis_tkeep,
+    input                               s_axis_tlast,
+    input [C_AXIS_TID_WIDTH-1:0]        s_axis_tid,
+    input [C_AXIS_TDEST_WIDTH-1:0]      s_axis_tdest,
+    input [C_AXIS_TUSER_WIDTH-1:0]      s_axis_tuser,
+    
+    // AXI Streaming Master Signals (Read side)
+    output                              m_axis_tvalid,
+    input                               m_axis_tready,
+    output [C_AXIS_TDATA_WIDTH-1:0]     m_axis_tdata,
+    output [C_AXIS_TSTRB_WIDTH-1:0]     m_axis_tstrb,
+    output [C_AXIS_TKEEP_WIDTH-1:0]     m_axis_tkeep,
+    output                              m_axis_tlast,
+    output [C_AXIS_TID_WIDTH-1:0]       m_axis_tid,
+    output [C_AXIS_TDEST_WIDTH-1:0]     m_axis_tdest,
+    output [C_AXIS_TUSER_WIDTH-1:0]     m_axis_tuser,
+    
+           
+    
+    
+    // AXI Full/Lite Write Address Channel signals
+    input                               axi_aw_injectsbiterr,
+    input                               axi_aw_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_WACH-1:0]   axi_aw_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_data_count,
+    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_wr_data_count,
+    output [C_WR_PNTR_WIDTH_WACH:0]     axi_aw_rd_data_count,
+    output                              axi_aw_sbiterr,
+    output                              axi_aw_dbiterr,
+    output                              axi_aw_overflow,
+    output                              axi_aw_underflow,
+    output                              axi_aw_prog_full,
+    output                              axi_aw_prog_empty,
+    
+    
+    // AXI Full/Lite Write Data Channel signals
+    input                               axi_w_injectsbiterr,
+    input                               axi_w_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_WDCH-1:0]   axi_w_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_data_count,
+    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_wr_data_count,
+    output [C_WR_PNTR_WIDTH_WDCH:0]     axi_w_rd_data_count,
+    output                              axi_w_sbiterr,
+    output                              axi_w_dbiterr,
+    output                              axi_w_overflow,
+    output                              axi_w_underflow,
+    output                              axi_w_prog_full,
+    output                              axi_w_prog_empty,
+    
+    
+    // AXI Full/Lite Write Response Channel signals
+    input                               axi_b_injectsbiterr,
+    input                               axi_b_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_WRCH-1:0]   axi_b_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_data_count,
+    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_wr_data_count,
+    output [C_WR_PNTR_WIDTH_WRCH:0]     axi_b_rd_data_count,
+    output                              axi_b_sbiterr,
+    output                              axi_b_dbiterr,
+    output                              axi_b_overflow,
+    output                              axi_b_underflow,
+    output                              axi_b_prog_full,
+    output                              axi_b_prog_empty,
+    
+    
+    
+    // AXI Full/Lite Read Address Channel signals
+    input                               axi_ar_injectsbiterr,
+    input                               axi_ar_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_RACH-1:0]   axi_ar_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_data_count,
+    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_wr_data_count,
+    output [C_WR_PNTR_WIDTH_RACH:0]     axi_ar_rd_data_count,
+    output                              axi_ar_sbiterr,
+    output                              axi_ar_dbiterr,
+    output                              axi_ar_overflow,
+    output                              axi_ar_underflow,
+    output                              axi_ar_prog_full,
+    output                              axi_ar_prog_empty,
+
+    
+    // AXI Full/Lite Read Data Channel Signals
+    input                               axi_r_injectsbiterr,
+    input                               axi_r_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_RDCH-1:0]   axi_r_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_data_count,
+    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_wr_data_count,
+    output [C_WR_PNTR_WIDTH_RDCH:0]     axi_r_rd_data_count,
+    output                              axi_r_sbiterr,
+    output                              axi_r_dbiterr,
+    output                              axi_r_overflow,
+    output                              axi_r_underflow,
+    output                              axi_r_prog_full,
+    output                              axi_r_prog_empty,
+
+    
+    // AXI Streaming FIFO Related Signals
+    input                               axis_injectsbiterr,
+    input                               axis_injectdbiterr,
+    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_full_thresh,
+    input  [C_WR_PNTR_WIDTH_AXIS-1:0]   axis_prog_empty_thresh,
+    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_data_count,
+    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_wr_data_count,
+    output [C_WR_PNTR_WIDTH_AXIS:0]     axis_rd_data_count,
+    output                              axis_sbiterr,
+    output                              axis_dbiterr,
+    output                              axis_overflow,
+    output                              axis_underflow,
+    output                              axis_prog_full,
+    output                              axis_prog_empty
+
+    );
+
+    wire                              BACKUP;
+    wire                              BACKUP_MARKER;
+    wire                              CLK;
+    wire                              RST;
+    wire                              SRST;
+    wire                              WR_CLK;
+    wire                              WR_RST;
+    wire                              RD_CLK;
+    wire                              RD_RST;
+    wire [C_DIN_WIDTH-1:0]            DIN;
+    wire                              WR_EN;
+    wire                              RD_EN;
+    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;
+    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;
+    wire [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;
+    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;
+    wire [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;
+    wire                              INT_CLK;
+    wire                              INJECTDBITERR;
+    wire                              INJECTSBITERR;
+    wire                              SLEEP;
+    wire [C_DOUT_WIDTH-1:0]           DOUT;
+    wire                              FULL;
+    wire                              ALMOST_FULL;
+    wire                              WR_ACK;
+    wire                              OVERFLOW;
+    wire                              EMPTY;
+    wire                              ALMOST_EMPTY;
+    wire                              VALID;
+    wire                              UNDERFLOW;
+    wire [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT;
+    wire [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT;
+    wire [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT;
+    wire                              PROG_FULL;
+    wire                              PROG_EMPTY;
+    wire                              SBITERR;
+    wire                              DBITERR;
+    wire                              WR_RST_BUSY;
+    wire                              RD_RST_BUSY;
+    wire                              M_ACLK;
+    wire                              S_ACLK;
+    wire                              S_ARESETN;
+    wire                              S_ACLK_EN;
+    wire                              M_ACLK_EN;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_AWID;
+    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_AWADDR;
+    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_AWLEN;
+    wire [3-1:0]                      S_AXI_AWSIZE;
+    wire [2-1:0]                      S_AXI_AWBURST;
+    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_AWLOCK;
+    wire [4-1:0]                      S_AXI_AWCACHE;
+    wire [3-1:0]                      S_AXI_AWPROT;
+    wire [4-1:0]                      S_AXI_AWQOS;
+    wire [4-1:0]                      S_AXI_AWREGION;
+    wire [C_AXI_AWUSER_WIDTH-1:0]     S_AXI_AWUSER;
+    wire                              S_AXI_AWVALID;
+    wire                              S_AXI_AWREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_WID;
+    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_WDATA;
+    wire [C_AXI_DATA_WIDTH/8-1:0]     S_AXI_WSTRB;
+    wire                              S_AXI_WLAST;
+    wire [C_AXI_WUSER_WIDTH-1:0]      S_AXI_WUSER;
+    wire                              S_AXI_WVALID;
+    wire                              S_AXI_WREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_BID;
+    wire [2-1:0]                      S_AXI_BRESP;
+    wire [C_AXI_BUSER_WIDTH-1:0]      S_AXI_BUSER;
+    wire                              S_AXI_BVALID;
+    wire                              S_AXI_BREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_AWID;
+    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_AWADDR;
+    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_AWLEN;
+    wire [3-1:0]                      M_AXI_AWSIZE;
+    wire [2-1:0]                      M_AXI_AWBURST;
+    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_AWLOCK;
+    wire [4-1:0]                      M_AXI_AWCACHE;
+    wire [3-1:0]                      M_AXI_AWPROT;
+    wire [4-1:0]                      M_AXI_AWQOS;
+    wire [4-1:0]                      M_AXI_AWREGION;
+    wire [C_AXI_AWUSER_WIDTH-1:0]     M_AXI_AWUSER;
+    wire                              M_AXI_AWVALID;
+    wire                              M_AXI_AWREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_WID;
+    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_WDATA;
+    wire [C_AXI_DATA_WIDTH/8-1:0]     M_AXI_WSTRB;
+    wire                              M_AXI_WLAST;
+    wire [C_AXI_WUSER_WIDTH-1:0]      M_AXI_WUSER;
+    wire                              M_AXI_WVALID;
+    wire                              M_AXI_WREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_BID;
+    wire [2-1:0]                      M_AXI_BRESP;
+    wire [C_AXI_BUSER_WIDTH-1:0]      M_AXI_BUSER;
+    wire                              M_AXI_BVALID;
+    wire                              M_AXI_BREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_ARID;
+    wire [C_AXI_ADDR_WIDTH-1:0]       S_AXI_ARADDR; 
+    wire [C_AXI_LEN_WIDTH-1:0]        S_AXI_ARLEN;
+    wire [3-1:0]                      S_AXI_ARSIZE;
+    wire [2-1:0]                      S_AXI_ARBURST;
+    wire [C_AXI_LOCK_WIDTH-1:0]       S_AXI_ARLOCK;
+    wire [4-1:0]                      S_AXI_ARCACHE;
+    wire [3-1:0]                      S_AXI_ARPROT;
+    wire [4-1:0]                      S_AXI_ARQOS;
+    wire [4-1:0]                      S_AXI_ARREGION;
+    wire [C_AXI_ARUSER_WIDTH-1:0]     S_AXI_ARUSER;
+    wire                              S_AXI_ARVALID;
+    wire                              S_AXI_ARREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         S_AXI_RID;       
+    wire [C_AXI_DATA_WIDTH-1:0]       S_AXI_RDATA; 
+    wire [2-1:0]                      S_AXI_RRESP;
+    wire                              S_AXI_RLAST;
+    wire [C_AXI_RUSER_WIDTH-1:0]      S_AXI_RUSER;
+    wire                              S_AXI_RVALID;
+    wire                              S_AXI_RREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_ARID;        
+    wire [C_AXI_ADDR_WIDTH-1:0]       M_AXI_ARADDR;  
+    wire [C_AXI_LEN_WIDTH-1:0]        M_AXI_ARLEN;
+    wire [3-1:0]                      M_AXI_ARSIZE;
+    wire [2-1:0]                      M_AXI_ARBURST;
+    wire [C_AXI_LOCK_WIDTH-1:0]       M_AXI_ARLOCK;
+    wire [4-1:0]                      M_AXI_ARCACHE;
+    wire [3-1:0]                      M_AXI_ARPROT;
+    wire [4-1:0]                      M_AXI_ARQOS;
+    wire [4-1:0]                      M_AXI_ARREGION;
+    wire [C_AXI_ARUSER_WIDTH-1:0]     M_AXI_ARUSER;
+    wire                              M_AXI_ARVALID;
+    wire                              M_AXI_ARREADY;
+    wire [C_AXI_ID_WIDTH-1:0]         M_AXI_RID;        
+    wire [C_AXI_DATA_WIDTH-1:0]       M_AXI_RDATA;  
+    wire [2-1:0]                      M_AXI_RRESP;
+    wire                              M_AXI_RLAST;
+    wire [C_AXI_RUSER_WIDTH-1:0]      M_AXI_RUSER;
+    wire                              M_AXI_RVALID;
+    wire                              M_AXI_RREADY;
+    wire                              S_AXIS_TVALID;
+    wire                              S_AXIS_TREADY;
+    wire [C_AXIS_TDATA_WIDTH-1:0]     S_AXIS_TDATA;
+    wire [C_AXIS_TSTRB_WIDTH-1:0]     S_AXIS_TSTRB;
+    wire [C_AXIS_TKEEP_WIDTH-1:0]     S_AXIS_TKEEP;
+    wire                              S_AXIS_TLAST;
+    wire [C_AXIS_TID_WIDTH-1:0]       S_AXIS_TID;
+    wire [C_AXIS_TDEST_WIDTH-1:0]     S_AXIS_TDEST;
+    wire [C_AXIS_TUSER_WIDTH-1:0]     S_AXIS_TUSER;
+    wire                              M_AXIS_TVALID;
+    wire                              M_AXIS_TREADY;
+    wire [C_AXIS_TDATA_WIDTH-1:0]     M_AXIS_TDATA;
+    wire [C_AXIS_TSTRB_WIDTH-1:0]     M_AXIS_TSTRB;
+    wire [C_AXIS_TKEEP_WIDTH-1:0]     M_AXIS_TKEEP;
+    wire                              M_AXIS_TLAST;
+    wire [C_AXIS_TID_WIDTH-1:0]       M_AXIS_TID;
+    wire [C_AXIS_TDEST_WIDTH-1:0]     M_AXIS_TDEST;
+    wire [C_AXIS_TUSER_WIDTH-1:0]     M_AXIS_TUSER;
+    wire                              AXI_AW_INJECTSBITERR;
+    wire                              AXI_AW_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_WACH-1:0]   AXI_AW_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WACH:0]     AXI_AW_RD_DATA_COUNT;
+    wire                              AXI_AW_SBITERR;
+    wire                              AXI_AW_DBITERR;
+    wire                              AXI_AW_OVERFLOW;
+    wire                              AXI_AW_UNDERFLOW;
+    wire                              AXI_AW_PROG_FULL;
+    wire                              AXI_AW_PROG_EMPTY;
+    wire                              AXI_W_INJECTSBITERR;
+    wire                              AXI_W_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_WDCH-1:0]   AXI_W_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WDCH:0]     AXI_W_RD_DATA_COUNT;
+    wire                              AXI_W_SBITERR;
+    wire                              AXI_W_DBITERR;
+    wire                              AXI_W_OVERFLOW;
+    wire                              AXI_W_UNDERFLOW;
+    wire                              AXI_W_PROG_FULL;
+    wire                              AXI_W_PROG_EMPTY;
+    wire                              AXI_B_INJECTSBITERR;
+    wire                              AXI_B_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_WRCH-1:0]   AXI_B_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_WRCH:0]     AXI_B_RD_DATA_COUNT;
+    wire                              AXI_B_SBITERR;
+    wire                              AXI_B_DBITERR;
+    wire                              AXI_B_OVERFLOW;
+    wire                              AXI_B_UNDERFLOW;
+    wire                              AXI_B_PROG_FULL;
+    wire                              AXI_B_PROG_EMPTY;
+    wire                              AXI_AR_INJECTSBITERR;
+    wire                              AXI_AR_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_RACH-1:0]   AXI_AR_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_RACH:0]     AXI_AR_RD_DATA_COUNT;
+    wire                              AXI_AR_SBITERR;
+    wire                              AXI_AR_DBITERR;
+    wire                              AXI_AR_OVERFLOW;
+    wire                              AXI_AR_UNDERFLOW;
+    wire                              AXI_AR_PROG_FULL;
+    wire                              AXI_AR_PROG_EMPTY;
+    wire                              AXI_R_INJECTSBITERR;
+    wire                              AXI_R_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_RDCH-1:0]   AXI_R_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_RDCH:0]     AXI_R_RD_DATA_COUNT;
+    wire                              AXI_R_SBITERR;
+    wire                              AXI_R_DBITERR;
+    wire                              AXI_R_OVERFLOW;
+    wire                              AXI_R_UNDERFLOW;
+    wire                              AXI_R_PROG_FULL;
+    wire                              AXI_R_PROG_EMPTY;
+    wire                              AXIS_INJECTSBITERR;
+    wire                              AXIS_INJECTDBITERR;
+    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_FULL_THRESH;
+    wire [C_WR_PNTR_WIDTH_AXIS-1:0]   AXIS_PROG_EMPTY_THRESH;
+    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_WR_DATA_COUNT;
+    wire [C_WR_PNTR_WIDTH_AXIS:0]     AXIS_RD_DATA_COUNT;
+    wire                              AXIS_SBITERR;
+    wire                              AXIS_DBITERR;
+    wire                              AXIS_OVERFLOW;
+    wire                              AXIS_UNDERFLOW;
+    wire                              AXIS_PROG_FULL;
+    wire                              AXIS_PROG_EMPTY;
+    wire [C_WR_DATA_COUNT_WIDTH-1:0]  wr_data_count_in;
+    wire                              wr_rst_int;
+    wire                              rd_rst_int;
+    wire                              wr_rst_busy_o;
+    wire                              wr_rst_busy_ntve;
+    wire                              wr_rst_busy_axis;
+    wire                              wr_rst_busy_wach;
+    wire                              wr_rst_busy_wdch;
+    wire                              wr_rst_busy_wrch;
+    wire                              wr_rst_busy_rach;
+    wire                              wr_rst_busy_rdch;
+
+
+
+  function integer find_log2;
+    input integer int_val;
+    integer i,j;
+    begin
+      i = 1;
+      j = 0;
+      for (i = 1; i < int_val; i = i*2) begin
+        j = j + 1;
+      end
+      find_log2 = j;
+    end
+  endfunction
+
+
+
+
+    // Conventional FIFO Interface Signals
+    assign BACKUP                 = backup;
+    assign BACKUP_MARKER          = backup_marker;
+    assign CLK                    = clk;
+    assign RST                    = rst;
+    assign SRST                   = srst;
+    assign WR_CLK                 = wr_clk;
+    assign WR_RST                 = wr_rst;
+    assign RD_CLK                 = rd_clk;
+    assign RD_RST                 = rd_rst;
+    assign WR_EN                  = wr_en;
+    assign RD_EN                  = rd_en;
+    assign INT_CLK                = int_clk;
+    assign INJECTDBITERR          = injectdbiterr;
+    assign INJECTSBITERR          = injectsbiterr;
+    assign SLEEP                  = sleep;
+    assign full                   = FULL;
+    assign almost_full            = ALMOST_FULL;
+    assign wr_ack                 = WR_ACK;
+    assign overflow               = OVERFLOW;
+    assign empty                  = EMPTY;
+    assign almost_empty           = ALMOST_EMPTY;
+    assign valid                  = VALID;
+    assign underflow              = UNDERFLOW;
+    assign prog_full              = PROG_FULL;
+    assign prog_empty             = PROG_EMPTY;
+    assign sbiterr                = SBITERR;
+    assign dbiterr                = DBITERR;
+//    assign wr_rst_busy            = WR_RST_BUSY | wr_rst_busy_o;
+    assign wr_rst_busy            = wr_rst_busy_o;
+    assign rd_rst_busy            = RD_RST_BUSY;
+    assign M_ACLK                 = m_aclk;
+    assign S_ACLK                 = s_aclk;
+    assign S_ARESETN              = s_aresetn;
+    assign S_ACLK_EN              = s_aclk_en;
+    assign M_ACLK_EN              = m_aclk_en;
+    assign S_AXI_AWVALID          = s_axi_awvalid;
+    assign s_axi_awready          = S_AXI_AWREADY;
+    assign S_AXI_WLAST            = s_axi_wlast;
+    assign S_AXI_WVALID           = s_axi_wvalid;
+    assign s_axi_wready           = S_AXI_WREADY;
+    assign s_axi_bvalid           = S_AXI_BVALID;
+    assign S_AXI_BREADY           = s_axi_bready;
+    assign m_axi_awvalid          = M_AXI_AWVALID;
+    assign M_AXI_AWREADY          = m_axi_awready;
+    assign m_axi_wlast            = M_AXI_WLAST;
+    assign m_axi_wvalid           = M_AXI_WVALID;
+    assign M_AXI_WREADY           = m_axi_wready;
+    assign M_AXI_BVALID           = m_axi_bvalid;
+    assign m_axi_bready           = M_AXI_BREADY;
+    assign S_AXI_ARVALID          = s_axi_arvalid;
+    assign s_axi_arready          = S_AXI_ARREADY;
+    assign s_axi_rlast            = S_AXI_RLAST;
+    assign s_axi_rvalid           = S_AXI_RVALID;
+    assign S_AXI_RREADY           = s_axi_rready;
+    assign m_axi_arvalid          = M_AXI_ARVALID;
+    assign M_AXI_ARREADY          = m_axi_arready;
+    assign M_AXI_RLAST            = m_axi_rlast;
+    assign M_AXI_RVALID           = m_axi_rvalid;
+    assign m_axi_rready           = M_AXI_RREADY;
+    assign S_AXIS_TVALID          = s_axis_tvalid;
+    assign s_axis_tready          = S_AXIS_TREADY;
+    assign S_AXIS_TLAST           = s_axis_tlast;
+    assign m_axis_tvalid          = M_AXIS_TVALID;
+    assign M_AXIS_TREADY          = m_axis_tready;
+    assign m_axis_tlast           = M_AXIS_TLAST;
+    assign AXI_AW_INJECTSBITERR   = axi_aw_injectsbiterr;
+    assign AXI_AW_INJECTDBITERR   = axi_aw_injectdbiterr;
+    assign axi_aw_sbiterr         = AXI_AW_SBITERR;
+    assign axi_aw_dbiterr         = AXI_AW_DBITERR;
+    assign axi_aw_overflow        = AXI_AW_OVERFLOW;
+    assign axi_aw_underflow       = AXI_AW_UNDERFLOW;
+    assign axi_aw_prog_full       = AXI_AW_PROG_FULL;
+    assign axi_aw_prog_empty      = AXI_AW_PROG_EMPTY;
+    assign AXI_W_INJECTSBITERR    = axi_w_injectsbiterr;
+    assign AXI_W_INJECTDBITERR    = axi_w_injectdbiterr;
+    assign axi_w_sbiterr          = AXI_W_SBITERR;
+    assign axi_w_dbiterr          = AXI_W_DBITERR;
+    assign axi_w_overflow         = AXI_W_OVERFLOW;
+    assign axi_w_underflow        = AXI_W_UNDERFLOW;
+    assign axi_w_prog_full        = AXI_W_PROG_FULL;
+    assign axi_w_prog_empty       = AXI_W_PROG_EMPTY;
+    assign AXI_B_INJECTSBITERR    = axi_b_injectsbiterr;
+    assign AXI_B_INJECTDBITERR    = axi_b_injectdbiterr;
+    assign axi_b_sbiterr          = AXI_B_SBITERR;
+    assign axi_b_dbiterr          = AXI_B_DBITERR;
+    assign axi_b_overflow         = AXI_B_OVERFLOW;
+    assign axi_b_underflow        = AXI_B_UNDERFLOW;
+    assign axi_b_prog_full        = AXI_B_PROG_FULL;
+    assign axi_b_prog_empty       = AXI_B_PROG_EMPTY;
+    assign AXI_AR_INJECTSBITERR   = axi_ar_injectsbiterr;
+    assign AXI_AR_INJECTDBITERR   = axi_ar_injectdbiterr;
+    assign axi_ar_sbiterr         = AXI_AR_SBITERR;
+    assign axi_ar_dbiterr         = AXI_AR_DBITERR;
+    assign axi_ar_overflow        = AXI_AR_OVERFLOW;
+    assign axi_ar_underflow       = AXI_AR_UNDERFLOW;
+    assign axi_ar_prog_full       = AXI_AR_PROG_FULL;
+    assign axi_ar_prog_empty      = AXI_AR_PROG_EMPTY;
+    assign AXI_R_INJECTSBITERR    = axi_r_injectsbiterr;
+    assign AXI_R_INJECTDBITERR    = axi_r_injectdbiterr;
+    assign axi_r_sbiterr          = AXI_R_SBITERR;
+    assign axi_r_dbiterr          = AXI_R_DBITERR;
+    assign axi_r_overflow         = AXI_R_OVERFLOW;
+    assign axi_r_underflow        = AXI_R_UNDERFLOW;
+    assign axi_r_prog_full        = AXI_R_PROG_FULL;
+    assign axi_r_prog_empty       = AXI_R_PROG_EMPTY;
+    assign AXIS_INJECTSBITERR     = axis_injectsbiterr;
+    assign AXIS_INJECTDBITERR     = axis_injectdbiterr;
+    assign axis_sbiterr           = AXIS_SBITERR;
+    assign axis_dbiterr           = AXIS_DBITERR;
+    assign axis_overflow          = AXIS_OVERFLOW;
+    assign axis_underflow         = AXIS_UNDERFLOW;
+    assign axis_prog_full         = AXIS_PROG_FULL;
+    assign axis_prog_empty        = AXIS_PROG_EMPTY;
+
+
+    assign DIN                       = din;
+    assign PROG_EMPTY_THRESH         = prog_empty_thresh;
+    assign PROG_EMPTY_THRESH_ASSERT  = prog_empty_thresh_assert;
+    assign PROG_EMPTY_THRESH_NEGATE  = prog_empty_thresh_negate;
+    assign PROG_FULL_THRESH          = prog_full_thresh;
+    assign PROG_FULL_THRESH_ASSERT   = prog_full_thresh_assert;
+    assign PROG_FULL_THRESH_NEGATE   = prog_full_thresh_negate;
+    assign dout                      = DOUT;
+    assign data_count                = DATA_COUNT;
+    assign rd_data_count             = RD_DATA_COUNT;
+    assign wr_data_count             = WR_DATA_COUNT;
+    assign S_AXI_AWID                = s_axi_awid;
+    assign S_AXI_AWADDR              = s_axi_awaddr;
+    assign S_AXI_AWLEN               = s_axi_awlen;
+    assign S_AXI_AWSIZE              = s_axi_awsize;
+    assign S_AXI_AWBURST             = s_axi_awburst;
+    assign S_AXI_AWLOCK              = s_axi_awlock;
+    assign S_AXI_AWCACHE             = s_axi_awcache;
+    assign S_AXI_AWPROT              = s_axi_awprot;
+    assign S_AXI_AWQOS               = s_axi_awqos;
+    assign S_AXI_AWREGION            = s_axi_awregion;
+    assign S_AXI_AWUSER              = s_axi_awuser;
+    assign S_AXI_WID                 = s_axi_wid;
+    assign S_AXI_WDATA               = s_axi_wdata;
+    assign S_AXI_WSTRB               = s_axi_wstrb;
+    assign S_AXI_WUSER               = s_axi_wuser;
+    assign s_axi_bid                 = S_AXI_BID;
+    assign s_axi_bresp               = S_AXI_BRESP;
+    assign s_axi_buser               = S_AXI_BUSER;
+    assign m_axi_awid                = M_AXI_AWID;
+    assign m_axi_awaddr              = M_AXI_AWADDR;
+    assign m_axi_awlen               = M_AXI_AWLEN;
+    assign m_axi_awsize              = M_AXI_AWSIZE;
+    assign m_axi_awburst             = M_AXI_AWBURST;
+    assign m_axi_awlock              = M_AXI_AWLOCK;
+    assign m_axi_awcache             = M_AXI_AWCACHE;
+    assign m_axi_awprot              = M_AXI_AWPROT;
+    assign m_axi_awqos               = M_AXI_AWQOS;
+    assign m_axi_awregion            = M_AXI_AWREGION;
+    assign m_axi_awuser              = M_AXI_AWUSER;
+    assign m_axi_wid                 = M_AXI_WID;
+    assign m_axi_wdata               = M_AXI_WDATA;
+    assign m_axi_wstrb               = M_AXI_WSTRB;
+    assign m_axi_wuser               = M_AXI_WUSER;
+    assign M_AXI_BID                 = m_axi_bid;
+    assign M_AXI_BRESP               = m_axi_bresp;
+    assign M_AXI_BUSER               = m_axi_buser;
+    assign S_AXI_ARID                = s_axi_arid;
+    assign S_AXI_ARADDR              = s_axi_araddr; 
+    assign S_AXI_ARLEN               = s_axi_arlen;
+    assign S_AXI_ARSIZE              = s_axi_arsize;
+    assign S_AXI_ARBURST             = s_axi_arburst;
+    assign S_AXI_ARLOCK              = s_axi_arlock;
+    assign S_AXI_ARCACHE             = s_axi_arcache;
+    assign S_AXI_ARPROT              = s_axi_arprot;
+    assign S_AXI_ARQOS               = s_axi_arqos;
+    assign S_AXI_ARREGION            = s_axi_arregion;
+    assign S_AXI_ARUSER              = s_axi_aruser;
+    assign s_axi_rid                 = S_AXI_RID;
+    assign s_axi_rdata               = S_AXI_RDATA;
+    assign s_axi_rresp               = S_AXI_RRESP;
+    assign s_axi_ruser               = S_AXI_RUSER;
+    assign m_axi_arid                = M_AXI_ARID;        
+    assign m_axi_araddr              = M_AXI_ARADDR;  
+    assign m_axi_arlen               = M_AXI_ARLEN;
+    assign m_axi_arsize              = M_AXI_ARSIZE;
+    assign m_axi_arburst             = M_AXI_ARBURST;
+    assign m_axi_arlock              = M_AXI_ARLOCK;
+    assign m_axi_arcache             = M_AXI_ARCACHE;
+    assign m_axi_arprot              = M_AXI_ARPROT;
+    assign m_axi_arqos               = M_AXI_ARQOS;
+    assign m_axi_arregion            = M_AXI_ARREGION;
+    assign m_axi_aruser              = M_AXI_ARUSER;
+    assign M_AXI_RID                 = m_axi_rid;        
+    assign M_AXI_RDATA               = m_axi_rdata;  
+    assign M_AXI_RRESP               = m_axi_rresp;
+    assign M_AXI_RUSER               = m_axi_ruser;
+    assign S_AXIS_TDATA              = s_axis_tdata;
+    assign S_AXIS_TSTRB              = s_axis_tstrb;
+    assign S_AXIS_TKEEP              = s_axis_tkeep;
+    assign S_AXIS_TID                = s_axis_tid;
+    assign S_AXIS_TDEST              = s_axis_tdest;
+    assign S_AXIS_TUSER              = s_axis_tuser;
+    assign m_axis_tdata              = M_AXIS_TDATA;
+    assign m_axis_tstrb              = M_AXIS_TSTRB;
+    assign m_axis_tkeep              = M_AXIS_TKEEP;
+    assign m_axis_tid                = M_AXIS_TID;
+    assign m_axis_tdest              = M_AXIS_TDEST;
+    assign m_axis_tuser              = M_AXIS_TUSER;
+    assign AXI_AW_PROG_FULL_THRESH   = axi_aw_prog_full_thresh;
+    assign AXI_AW_PROG_EMPTY_THRESH  = axi_aw_prog_empty_thresh;
+    assign axi_aw_data_count         = AXI_AW_DATA_COUNT;
+    assign axi_aw_wr_data_count      = AXI_AW_WR_DATA_COUNT;
+    assign axi_aw_rd_data_count      = AXI_AW_RD_DATA_COUNT;
+    assign AXI_W_PROG_FULL_THRESH    = axi_w_prog_full_thresh;
+    assign AXI_W_PROG_EMPTY_THRESH   = axi_w_prog_empty_thresh;
+    assign axi_w_data_count          = AXI_W_DATA_COUNT;
+    assign axi_w_wr_data_count       = AXI_W_WR_DATA_COUNT;
+    assign axi_w_rd_data_count       = AXI_W_RD_DATA_COUNT;
+    assign AXI_B_PROG_FULL_THRESH    = axi_b_prog_full_thresh;
+    assign AXI_B_PROG_EMPTY_THRESH   = axi_b_prog_empty_thresh;
+    assign axi_b_data_count          = AXI_B_DATA_COUNT;
+    assign axi_b_wr_data_count       = AXI_B_WR_DATA_COUNT;
+    assign axi_b_rd_data_count       = AXI_B_RD_DATA_COUNT;
+    assign AXI_AR_PROG_FULL_THRESH   = axi_ar_prog_full_thresh;
+    assign AXI_AR_PROG_EMPTY_THRESH  = axi_ar_prog_empty_thresh;
+    assign axi_ar_data_count         = AXI_AR_DATA_COUNT;
+    assign axi_ar_wr_data_count      = AXI_AR_WR_DATA_COUNT;
+    assign axi_ar_rd_data_count      = AXI_AR_RD_DATA_COUNT;
+    assign AXI_R_PROG_FULL_THRESH    = axi_r_prog_full_thresh;
+    assign AXI_R_PROG_EMPTY_THRESH   = axi_r_prog_empty_thresh;
+    assign axi_r_data_count          = AXI_R_DATA_COUNT;
+    assign axi_r_wr_data_count       = AXI_R_WR_DATA_COUNT;
+    assign axi_r_rd_data_count       = AXI_R_RD_DATA_COUNT;
+    assign AXIS_PROG_FULL_THRESH     = axis_prog_full_thresh;
+    assign AXIS_PROG_EMPTY_THRESH    = axis_prog_empty_thresh;
+    assign axis_data_count           = AXIS_DATA_COUNT;
+    assign axis_wr_data_count        = AXIS_WR_DATA_COUNT;
+    assign axis_rd_data_count        = AXIS_RD_DATA_COUNT;
+
+
+  generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
+
+    fifo_generator_v13_1_3_CO'b'NV_VER
+      #(
+        .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),
+        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),
+        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),
+        .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),
+        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),
+        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),
+        .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
+        .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),
+        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),
+        .C_FAMILY\t\t\t(C_FAMILY),
+        .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),
+        .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),
+        .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),
+        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),
+        .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),
+        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),
+        .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),
+        .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),
+        .C_HAS_RST\t\t\t(C_HAS_RST),
+        .C_HAS_SRST\t\t\t(C_HAS_SRST),
+        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),
+        .C_HAS_VALID\t\t\t(C_HAS_VALID),
+        .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),
+        .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),
+        .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),
+        .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),
+        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),
+        .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),
+        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),
+        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),
+        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),
+        .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),
+        .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),
+        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),
+        .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),
+        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),
+        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),
+        .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),
+        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),
+        .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),
+        .C_RD_DEPTH\t\t\t(C_RD_DEPTH),
+        .C_RD_FREQ\t\t\t(C_RD_FREQ),
+        .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),
+        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),
+        .C_USE_DOUT_RST                 (C_USE_DOUT_RST),
+        .C_USE_ECC                      (C_USE_ECC),
+        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),
+        .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),
+        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),
+        .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),
+        .C_VALID_LOW\t\t\t(C_VALID_LOW),
+        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),
+        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),
+        .C_WR_DEPTH\t\t\t(C_WR_DEPTH),
+        .C_WR_FREQ\t\t\t(C_WR_FREQ),
+        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),
+        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (C_ENABLE_RST_SYNC),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE),
+        .C_AXI_TYPE                     (C_AXI_TYPE),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE)
+      )
+    fifo_generator_v13_1_3_conv_dut
+      (
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .CLK                      (CLK),
+        .RST                      (RST),
+        .SRST                     (SRST),
+        .WR_CLK                   (WR_CLK),
+        .WR_RST                   (WR_RST),
+        .RD_CLK                   (RD_CLK),
+        .RD_RST                   (RD_RST),
+        .DIN                      (DIN),
+        .WR_EN                    (WR_EN),
+        .RD_EN                    (RD_EN),
+        .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
+        .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
+        .PROG_FULL_THRESH         (PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),
+        .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),
+        .INT_CLK                  (INT_CLK),
+        .INJECTDBITERR            (INJECTDBITERR), 
+        .INJECTSBITERR            (INJECTSBITERR),
+  
+        .DOUT                     (DOUT),
+        .FULL                     (FULL),
+        .ALMOST_FULL              (ALMOST_FULL),
+        .WR_ACK                   (WR_ACK),
+        .OVERFLOW                 (OVERFLOW),
+        .EMPTY                    (EMPTY),
+        .ALMOST_EMPTY             (ALMOST_EMPTY),
+        .VALID                    (VALID),
+        .UNDERFLOW                (UNDERFLOW),
+        .DATA_COUNT               (DATA_COUNT),
+        .RD_DATA_COUNT            (RD_DATA_COUNT),
+        .WR_DATA_COUNT            (wr_data_count_in),
+        .PROG_FULL                (PROG_FULL),
+        .PROG_EMPTY               (PROG_EMPTY),
+        .SBITERR                  (SBITERR),
+        .DBITERR                  (DBITERR),
+        .wr_rst_busy_o            (wr_rst_busy_o),
+        .wr_rst_busy              (wr_rst_busy_i),
+        .rd_rst_busy              (rd_rst_busy),
+        .wr_rst_i_out             (wr_rst_int),
+        .rd_rst_i_out             (rd_rst_int)
+       );
+  end endgenerate
+
+
+
+  localparam IS_8SERIES         = (C_FAMILY == ""virtexu"" || C_FAMILY == ""kintexu"" || C_FAMILY == ""artixu"" || C_FAMILY == ""virtexuplus"" || C_FAMILY == ""zynquplus"" || C_FAMILY == ""kintexuplus"") ? 1 : 0;
+  localparam C_AXI_SIZE_WIDTH   = 3;
+  localparam C_AXI_BURST_WIDTH  = 2;
+  localparam C_AXI_CACHE_WIDTH  = 4;
+  localparam C_AXI_PROT_WIDTH   = 3;
+  localparam C_AXI_QOS_WIDTH    = 4;
+  localparam C_AXI_REGION_WIDTH = 4;
+  localparam C_AXI_BRESP_WIDTH  = 2;
+  localparam C_AXI_RRESP_WIDTH  = 2;
+
+  localparam IS_AXI_STREAMING  = C_INTERFACE_TYPE == 1 ? 1 : 0;
+  localparam TDATA_OFFSET      = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
+  localparam TSTRB_OFFSET      = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
+  localparam TKEEP_OFFSET      = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
+  localparam TID_OFFSET        = C_HAS_AXIS_TID   == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
+  localparam TDEST_OFFSET      = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
+  localparam TUSER_OFFSET      = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
+  localparam LOG_DEPTH_AXIS    = find_log2(C_WR_DEPTH_AXIS); 
+  localparam LOG_WR_DEPTH      = find_log2(C_WR_DEPTH); 
+
+
+  function [LOG_DEPTH_AXIS-1:0] bin2gray;
+      input [LOG_DEPTH_AXIS-1:0] x;
+      begin
+         bin2gray = x ^ (x>>1);
+      end
+   endfunction
+
+  function [LOG_DEPTH_AXIS-1:0] gray2bin;
+      input [LOG_DEPTH_AXIS-1:0] x;
+      integer                i;
+      begin
+         gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
+         for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
+            gray2bin[i] =  gray2bin[i+1] ^ x[i];
+         end
+      end
+   endfunction
+
+wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
+wire  [LOG_WR_DEPTH-1 : 0]  w_q [0:C_SYNCHRONIZER_STAGE] ;
+wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE]  ;
+reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
+reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
+reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
+reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
+wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
+wire [LOG_WR_DEPTH : 0] r_inv_pad;
+wire [LOG_WR_DEPTH-1 : 0] d_cnt;
+reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
+reg adj_w_cnt_rd_pad_0 = 0;
+reg r_inv_pad_0 = 0;
+
+
+   genvar l;
+
+   generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
+     fifo_generator_v13_1_3_sync_stage
+       #(
+         .C_WIDTH  (LOG_WR_DEPTH)
+        )
+     rd_stg_inst
+        (
+         .RST      (rd_rst_int), 
+         .CLK      (RD_CLK), 
+         .DIN      (w_q[l-1]), 
+         .DOUT     (w_q[l])
+        );
+   end endgenerate // gpkt_cnt_sync_stage
+
+
+
+      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
+    assign wr_eop_ad = WR_EN & !(FULL);
+    assign rd_eop_ad = RD_EN & !(EMPTY);
+
+
+  always @ (posedge wr_rst_int or posedge WR_CLK)
+    begin
+      if (wr_rst_int)
+        w_cnt    <= 1\'b0;
+      else if (wr_eop_ad)
+        w_cnt    <= w_cnt + 1;
+    end
+
+  always @ (posedge wr_rst_int or posedge WR_CLK)
+    begin
+      if (wr_rst_int)
+        w_cnt_gc    <= 1\'b0;
+      else 
+        w_cnt_gc    <= bin2gray(w_cnt);
+    end
+
+
+    assign  w_q[0]  = w_cnt_gc;
+    assign  w_cnt_gc_asreg_last       = w_q[C_SYNCHRONIZER_STAGE];
+
+
+
+  always @ (posedge rd_rst_int or posedge RD_CLK)
+    begin
+      if (rd_rst_int)
+        w_cnt_rd    <= 1\'b0;
+      else 
+        w_cnt_rd    <= gray2bin(w_cnt_gc_asreg_last);
+    end
+
+  always @ (posedge rd_rst_int or posedge RD_CLK)
+    begin
+      if (rd_rst_int)
+        r_cnt    <= 1\'b0;
+      else if (rd_eop_ad)
+        r_cnt    <= r_cnt + 1;
+    end
+
+
+  // Take the difference of write and read packet count
+  // Logic is similar to rd_pe_as
+   assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
+   assign r_inv_pad[LOG_WR_DEPTH : 1]        = ~r_cnt;
+   assign adj_w_cnt_rd_pad[0]                = adj_w_cnt_rd_pad_0;
+   assign r_inv_pad[0]                       = r_inv_pad_0;
+
+
+  always @ ( rd_eop_ad )
+    begin
+      if (!rd_eop_ad) begin
+        adj_w_cnt_rd_pad_0    <= 1\'b1;
+        r_inv_pad_0           <= 1\'b1;
+      end else begin 
+        adj_w_cnt_rd_pad_0    <= 1\'b0;
+        r_inv_pad_0           <= 1\'b0;
+      end\t
+    end
+
+  always @ (posedge rd_rst_int or posedge RD_CLK)
+    begin
+      if (rd_rst_int)
+        d_cnt_pad    <= 1\'b0;
+      else 
+        d_cnt_pad    <= adj_w_cnt_rd_pad + r_inv_pad ;
+    end
+
+   assign  d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
+   assign  WR_DATA_COUNT = d_cnt;
+
+  end endgenerate // fifo_ic_adapter
+
+      generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
+   assign  WR_DATA_COUNT = wr_data_count_in;
+
+  end endgenerate // fifo_icn_adapter
+
+
+
+  wire                          inverted_reset = ~S_ARESETN;
+  wire                          axi_rs_rst;
+  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_din          ;
+  wire  [C_DIN_WIDTH_AXIS-1:0]  axis_dout         ;
+  wire                          axis_full         ;
+  wire                          axis_almost_full  ;
+  wire                          axis_empty        ;
+  wire                          axis_s_axis_tready;
+  wire                          axis_m_axis_tvalid;
+  wire                          axis_wr_en        ;
+  wire                          axis_rd_en        ;
+  wire                          axis_we           ;
+  wire                          axis_re           ;
+  wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
+  reg                           axis_pkt_read = 1\'b0;
+  wire                          axis_rd_rst;
+  wire                          axis_wr_rst;
+
+  generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
+               C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
+      reg                           rst_d1 = 0        ;
+      reg                           rst_d2 = 0        ;
+      reg [3:0]                    axi_rst = 4\'h0     ;
+      always @ (posedge inverted_reset or posedge S_ACLK) begin
+        if (inverted_reset) begin
+          rst_d1         <= 1\'b1;
+          rst_d2         <= 1\'b1;
+          axi_rst        <= 4\'hf;
+        end else begin
+          rst_d1         <= #`TCQ 1\'b0;
+          rst_d2         <= #`TCQ rst_d1;
+          axi_rst        <= #`TCQ {axi_rst[2:0],1\'b0};
+        end
+      end
+
+      assign axi_rs_rst = axi_rst[3];//rst_d2;
+  end endgenerate // gaxi_rs_rst
+
+  generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
+
+    // Write protection when almost full or prog_full is high
+    assign axis_we    = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : 
+                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign axis_re    = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
+                        (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
+    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? axis_we & S_ACLK_EN : axis_we;
+    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
+
+    fifo_generator_v13_1_3_CONV_VER
+      #(
+        .C_FAMILY\t\t\t(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_INTERFACE_TYPE               (C_INTERFACE_TYPE),
+        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_AXIS == 2  || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1  || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
+        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI
+        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),
+        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),
+        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),
+        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),
+        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),
+        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),
+        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),
+        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
+        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
+        .C_USE_ECC                      (C_USE_ECC_AXIS),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_AXIS),
+        .C_HAS_ALMOST_EMPTY\t\t(0),
+        .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+        .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),
+        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST\t\t\t(0),
+        .C_HAS_RD_RST\t\t\t(0),
+        .C_HAS_RST\t\t\t(1),
+        .C_HAS_SRST\t\t\t(0),
+        .C_DOUT_RST_VAL\t\t\t(0),
+
+        .C_HAS_VALID\t\t\t(0),
+        .C_VALID_LOW\t\t\t(C_VALID_LOW),
+        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK\t\t\t(0),
+        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),
+        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),
+        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
+        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ\t\t\t(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ\t\t\t(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_1_3_axis_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (S_ACLK),
+        .RD_CLK                   (M_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1\'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (axis_wr_en),
+        .RD_EN                    (axis_rd_en),
+        .PROG_FULL_THRESH         (AXIS_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_AXIS{1\'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_AXIS{1\'b0}}),
+        .PROG_EMPTY_THRESH        (AXIS_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1\'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1\'b0}}),
+        .INJECTDBITERR            (AXIS_INJECTDBITERR), 
+        .INJECTSBITERR            (AXIS_INJECTSBITERR),
+  
+        .DIN                      (axis_din),
+        .DOUT                     (axis_dout),
+        .FULL                     (axis_full),
+        .EMPTY                    (axis_empty),
+        .ALMOST_FULL              (axis_almost_full),
+        .PROG_FULL                (AXIS_PROG_FULL),
+        .ALMOST_EMPTY             (),
+        .PROG_EMPTY               (AXIS_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (AXIS_OVERFLOW),
+        .VALID                    (),
+        .UNDERFLOW                (AXIS_UNDERFLOW),
+        .DATA_COUNT               (axis_dc),
+        .RD_DATA_COUNT            (AXIS_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXIS_WR_DATA_COUNT),
+        .SBITERR                  (AXIS_SBITERR),
+        .DBITERR                  (AXIS_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_axis),
+        .rd_rst_busy              (rd_rst_busy_axis),
+        .wr_rst_i_out             (axis_wr_rst),
+        .rd_rst_i_out             (axis_rd_rst),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign axis_s_axis_tready    = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
+    assign axis_m_axis_tvalid    = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
+    assign S_AXIS_TREADY         = axis_s_axis_tready;
+    assign M_AXIS_TVALID         = axis_m_axis_tvalid;
+
+  end endgenerate // axi_streaming
+
+  wire axis_wr_eop;
+  reg  axis_wr_eop_d1 = 1\'b0;
+  wire axis_rd_eop;
+  integer  axis_pkt_cnt;
+
+  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
+    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
+    assign axis_rd_eop = axis_rd_en & axis_dout[0];
+
+    always @ (posedge inverted_reset or posedge S_ACLK)
+    begin
+      if (inverted_reset)
+        axis_pkt_read    <= 1\'b0;
+      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
+        axis_pkt_read    <= 1\'b0;
+      else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
+        axis_pkt_read    <= 1\'b1;
+    end
+
+    always @ (posedge inverted_reset or posedge S_ACLK)
+    begin
+      if (inverted_reset)
+        axis_wr_eop_d1    <= 1\'b0;
+      else
+        axis_wr_eop_d1   <= axis_wr_eop;
+    end
+
+    always @ (posedge inverted_reset or posedge S_ACLK)
+    begin
+      if (inverted_reset)
+        axis_pkt_cnt    <= 0;
+      else if (axis_wr_eop_d1 && ~axis_rd_eop)
+        axis_pkt_cnt    <= axis_pkt_cnt + 1;
+      else if (axis_rd_eop && ~axis_wr_eop_d1)
+        axis_pkt_cnt    <= axis_pkt_cnt - 1;
+    end
+  end endgenerate // gaxis_pkt_fifo_cc
+
+
+reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
+wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
+wire axis_rd_has_rst;
+wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
+wire  [LOG_DEPTH_AXIS-1 : 0]  wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
+wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
+wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE]  ;
+reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
+reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
+reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
+wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
+wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
+wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
+reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
+reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
+reg rpkt_inv_pad_0 = 0;
+wire axis_af_rd ;
+
+generate if (C_HAS_RST == 1) begin : rst_blk_has
+  assign axis_rd_has_rst = axis_rd_rst;
+end endgenerate //rst_blk_has
+
+generate if (C_HAS_RST == 0) begin :rst_blk_no
+  assign axis_rd_has_rst = 1\'b0;
+end endgenerate //rst_blk_no
+
+   genvar i;
+
+   generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
+     fifo_generator_v13_1_3_sync_stage
+       #(
+         .C_WIDTH  (LOG_DEPTH_AXIS)
+        )
+     rd_stg_inst
+        (
+         .RST      (axis_rd_has_rst), 
+         .CLK      (M_ACLK), 
+         .DIN      (wpkt_q[i-1]), 
+         .DOUT     (wpkt_q[i])
+        );
+ 
+     fifo_generator_v13_1_3_sync_stage
+       #(
+         .C_WIDTH  (1)
+        )
+     wr_stg_inst
+        (
+         .RST      (axis_rd_has_rst), 
+         .CLK      (M_ACLK), 
+         .DIN      (axis_af_q[i-1]), 
+         .DOUT     (axis_af_q[i])
+        );
+   end endgenerate // gpkt_cnt_sync_stage
+
+
+  generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
+    assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
+    assign axis_rd_eop = axis_rd_en & axis_dout[0];
+
+    always @ (posedge axis_rd_has_rst or posedge M_ACLK)
+    begin
+      if (axis_rd_has_rst)
+        axis_pkt_read    <= 1\'b0;
+      else if (axis_rd_eop && (diff_pkt_cnt == 1))
+        axis_pkt_read    <= 1\'b0;
+      else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
+        axis_pkt_read    <= 1\'b1;
+    end
+
+  always @ (posedge axis_wr_rst or posedge S_ACLK)
+    begin
+      if (axis_wr_rst)
+        axis_wpkt_cnt    <= 1\'b0;
+      else if (axis_wr_eop)
+        axis_wpkt_cnt    <= axis_wpkt_cnt + 1;
+    end
+
+  always @ (posedge axis_wr_rst or posedge S_ACLK)
+    begin
+      if (axis_wr_rst)
+        axis_wpkt_cnt_gc    <= 1\'b0;
+      else 
+        axis_wpkt_cnt_gc    <= bin2gray(axis_wpkt_cnt);
+    end
+
+
+    assign  wpkt_q[0]  = axis_wpkt_cnt_gc;
+    assign  axis_wpkt_cnt_gc_asreg_last       = wpkt_q[C_SYNCHRONIZER_STAGE];
+    assign  axis_af_q[0]                      = axis_almost_full;
+    //assign  axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
+    assign  axis_af_rd                        = axis_af_q[C_SYNCHRONIZER_STAGE];
+
+
+
+  always @ (posedge axis_rd_has_rst or posedge M_ACLK)
+    begin
+      if (axis_rd_has_rst)
+        axis_wpkt_cnt_rd    <= 1\'b0;
+      else 
+        axis_wpkt_cnt_rd    <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
+    end
+
+  always @ (posedge axis_rd_rst or posedge M_ACLK)
+    begin
+      if (axis_rd_has_rst)
+        axis_rpkt_cnt    <= 1\'b0;
+      else if (axis_rd_eop)
+        axis_rpkt_cnt    <= axis_rpkt_cnt + 1;
+    end
+
+
+  // Take the difference of write and read packet count
+  // Logic is similar to rd_pe_as
+   assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
+   assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1]             = ~axis_rpkt_cnt;
+   assign adj_axis_wpkt_cnt_rd_pad[0]                                = adj_axis_wpkt_cnt_rd_pad_0;
+   assign rpkt_inv_pad[0]                                            = rpkt_inv_pad_0;
+
+
+  always @ ( axis_rd_eop )
+    begin
+      if (!axis_rd_eop) begin
+        adj_axis_wpkt_cnt_rd_pad_0    <= 1\'b1;
+        rpkt_inv_pad_0                <= 1\'b1;
+      end else begin 
+        adj_axis_wpkt_cnt_rd_pad_0    <= 1\'b0;
+        rpkt_inv_pad_0                <= 1\'b0;
+      end\t
+    end
+
+  always @ (posedge axis_rd_rst or posedge M_ACLK)
+    begin
+      if (axis_rd_has_rst)
+        diff_pkt_cnt_pad    <= 1\'b0;
+      else 
+        diff_pkt_cnt_pad    <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
+    end
+
+   assign  diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
+
+
+
+
+
+   end endgenerate // gaxis_pkt_fifo_ic
+
+
+
+
+  // Generate the accurate data count for axi stream packet fifo configuration
+  reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
+  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
+    always @ (posedge inverted_reset or posedge S_ACLK)
+    begin
+      if (inverted_reset)
+        axis_dc_pkt_fifo <= 0;
+      else if (axis_wr_en && (~axis_rd_en))
+        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
+      else if (~axis_wr_en && axis_rd_en)
+        axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
+    end
+    assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
+  end endgenerate // gdc_pkt
+
+  generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
+    assign AXIS_DATA_COUNT = 0;
+  end endgenerate // gndc_pkt
+
+  generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
+    assign AXIS_DATA_COUNT = axis_dc;
+  end endgenerate // gdc
+
+  // Register Slice for Write Address Channel
+  generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
+    assign axis_wr_en = (C_HAS_SLAVE_CE == 1)  ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
+    assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
+
+    fifo_generator_v13_1_3_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_AXIS),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_AXIS)
+            )
+    axis_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (axi_rs_rst),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (axis_din),
+          .S_VALID                   (axis_wr_en),
+          .S_READY                   (S_AXIS_TREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (axis_dout),
+          .M_VALID                   (M_AXIS_TVALID),
+          .M_READY                   (axis_rd_en)
+          );
+  end endgenerate // gaxis_reg_slice
+
+
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
+    assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
+    assign M_AXIS_TDATA   = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
+    assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
+    assign M_AXIS_TSTRB   = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
+    assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
+    assign M_AXIS_TKEEP   = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
+    assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
+    assign M_AXIS_TID     = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
+    assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
+    assign M_AXIS_TDEST   = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
+    assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
+    assign M_AXIS_TUSER   = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
+  end endgenerate
+
+  generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
+    assign axis_din[0] = S_AXIS_TLAST;
+    assign M_AXIS_TLAST   = axis_dout[0];
+  end endgenerate
+
+  //###########################################################################
+  //  AXI FULL Write Channel (axi_write_channel)
+  //###########################################################################
+
+  localparam IS_AXI_FULL       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
+  localparam IS_AXI_LITE       = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
+
+  localparam IS_AXI_FULL_WACH  = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_FULL_WDCH  = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_FULL_WRCH  = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_FULL_RACH  = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_FULL_RDCH  = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
+
+  localparam IS_AXI_LITE_WACH  = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_LITE_WDCH  = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_LITE_WRCH  = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_LITE_RACH  = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
+  localparam IS_AXI_LITE_RDCH  = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
+
+  localparam IS_WR_ADDR_CH     = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
+  localparam IS_WR_DATA_CH     = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
+  localparam IS_WR_RESP_CH     = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
+  localparam IS_RD_ADDR_CH     = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
+  localparam IS_RD_DATA_CH     = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
+
+  localparam AWID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
+  localparam AWADDR_OFFSET     = AWID_OFFSET - C_AXI_ADDR_WIDTH;
+  localparam AWLEN_OFFSET      = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
+  localparam AWSIZE_OFFSET     = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
+  localparam AWBURST_OFFSET    = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
+  localparam AWLOCK_OFFSET     = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
+  localparam AWCACHE_OFFSET    = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
+  localparam AWPROT_OFFSET     = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
+  localparam AWQOS_OFFSET      = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
+  localparam AWREGION_OFFSET   = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
+  localparam AWUSER_OFFSET     = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
+
+  localparam WID_OFFSET        = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
+  localparam WDATA_OFFSET      = WID_OFFSET - C_AXI_DATA_WIDTH;
+  localparam WSTRB_OFFSET      = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
+  localparam WUSER_OFFSET      = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
+
+  localparam BID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
+  localparam BRESP_OFFSET      = BID_OFFSET - C_AXI_BRESP_WIDTH;
+  localparam BUSER_OFFSET      = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
+
+
+  wire  [C_DIN_WIDTH_WACH-1:0]  wach_din          ;
+  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout         ;
+  wire  [C_DIN_WIDTH_WACH-1:0]  wach_dout_pkt     ;
+  wire                          wach_full         ;
+  wire                          wach_almost_full  ;
+  wire                          wach_prog_full    ;
+  wire                          wach_empty        ;
+  wire                          wach_almost_empty ;
+  wire                          wach_prog_empty   ;
+  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_din          ;
+  wire  [C_DIN_WIDTH_WDCH-1:0]  wdch_dout         ;
+  wire                          wdch_full         ;
+  wire                          wdch_almost_full  ;
+  wire                          wdch_prog_full    ;
+  wire                          wdch_empty        ;
+  wire                          wdch_almost_empty ;
+  wire                          wdch_prog_empty   ;
+  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_din          ;
+  wire  [C_DIN_WIDTH_WRCH-1:0]  wrch_dout         ;
+  wire                          wrch_full         ;
+  wire                          wrch_almost_full  ;
+  wire                          wrch_prog_full    ;
+  wire                          wrch_empty        ;
+  wire                          wrch_almost_empty ;
+  wire                          wrch_prog_empty   ;
+  wire                          axi_aw_underflow_i;
+  wire                          axi_w_underflow_i ;
+  wire                          axi_b_underflow_i ;
+  wire                          axi_aw_overflow_i ;
+  wire                          axi_w_overflow_i  ;
+  wire                          axi_b_overflow_i  ;
+  wire                          axi_wr_underflow_i;
+  wire                          axi_wr_overflow_i ;
+  wire                          wach_s_axi_awready;
+  wire                          wach_m_axi_awvalid;
+  wire                          wach_wr_en        ;
+  wire                          wach_rd_en        ;
+  wire                          wdch_s_axi_wready ;
+  wire                          wdch_m_axi_wvalid ;
+  wire                          wdch_wr_en        ;
+  wire                          wdch_rd_en        ;
+  wire                          wrch_s_axi_bvalid ;
+  wire                          wrch_m_axi_bready ;
+  wire                          wrch_wr_en        ;
+  wire                          wrch_rd_en        ;
+  wire                          txn_count_up      ;
+  wire                          txn_count_down    ;
+  wire                          awvalid_en        ;
+  wire                          awvalid_pkt       ;
+  wire                          awready_pkt       ;
+  integer                       wr_pkt_count      ;
+  wire                          wach_we           ;
+  wire                          wach_re           ;
+  wire                          wdch_we           ;
+  wire                          wdch_re           ;
+  wire                          wrch_we           ;
+  wire                          wrch_re           ;
+
+  generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
+    // Write protection when almost full or prog_full is high
+    assign wach_we    = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign wach_re    = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? 
+                        wach_m_axi_awvalid & awready_pkt & awvalid_en : 
+                        (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? 
+                        M_AXI_AWREADY && wach_m_axi_awvalid :
+                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? 
+                        awready_pkt & awvalid_en : 
+                        (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? 
+                        M_AXI_AWREADY : 1\'b0;
+    assign wach_wr_en = (C_HAS_SLAVE_CE == 1)  ? wach_we & S_ACLK_EN : wach_we;
+    assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
+
+    fifo_generator_v13_1_3_CONV_VER
+      #(
+        .C_FAMILY\t\t\t(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_WACH == 2  || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1  || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI
+        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),
+        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),
+        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),
+        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),
+        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),
+        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),
+        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),
+        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
+        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
+        .C_USE_ECC                      (C_USE_ECC_WACH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WACH),
+        .C_HAS_ALMOST_EMPTY\t\t(0),
+        .C_HAS_ALMOST_FULL\t\t(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST\t\t\t(0),
+        .C_HAS_RD_RST\t\t\t(0),
+        .C_HAS_RST\t\t\t(1),
+        .C_HAS_SRST\t\t\t(0),
+        .C_DOUT_RST_VAL\t\t\t(0),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
+        .C_HAS_VALID\t\t\t(0),
+        .C_VALID_LOW\t\t\t(C_VALID_LOW),
+        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK\t\t\t(0),
+        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),
+        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),
+        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG\t\t(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ\t\t\t(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ\t\t\t(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_1_3_wach_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (S_ACLK),
+        .RD_CLK                   (M_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1\'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (wach_wr_en),
+        .RD_EN                    (wach_rd_en),
+        .PROG_FULL_THRESH         (AXI_AW_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WACH{1\'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WACH{1\'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_AW_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1\'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1\'b0}}),
+        .INJECTDBITERR            (AXI_AW_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_AW_INJECTSBITERR),
+  
+        .DIN                      (wach_din),
+        .DOUT                     (wach_dout_pkt),
+        .FULL                     (wach_full),
+        .EMPTY                    (wach_empty),
+        .ALMOST_FULL              (),
+        .PROG_FULL                (AXI_AW_PROG_FULL),
+        .ALMOST_EMPTY             (),
+        .PROG_EMPTY               (AXI_AW_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_aw_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_aw_underflow_i),
+        .DATA_COUNT               (AXI_AW_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_AW_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_AW_WR_DATA_COUNT),
+        .SBITERR                  (AXI_AW_SBITERR),
+        .DBITERR                  (AXI_AW_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_wach),
+        .rd_rst_busy              (rd_rst_busy_wach),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign wach_s_axi_awready    = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
+    assign wach_m_axi_awvalid   = ~wach_empty;
+    assign S_AXI_AWREADY        = wach_s_axi_awready;
+
+    assign AXI_AW_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
+    assign AXI_AW_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_aw_overflow_i  : 0;
+
+  end endgenerate // axi_write_address_channel
+
+  // Register Slice for Write Address Channel
+  generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
+
+    fifo_generator_v13_1_3_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_WACH)
+            )
+    wach_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (axi_rs_rst),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (wach_din),
+          .S_VALID                   (S_AXI_AWVALID),
+          .S_READY                   (S_AXI_AWREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (wach_dout),
+          .M_VALID                   (M_AXI_AWVALID),
+          .M_READY                   (M_AXI_AWREADY)
+          );
+  end endgenerate // gwach_reg_slice
+  
+  generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
+
+    fifo_generator_v13_1_3_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_WACH),
+            .C_REG_CONFIG            (1)
+            )
+    wach_pkt_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (wach_dout_pkt),
+          .S_VALID                   (awvalid_pkt),
+          .S_READY                   (awready_pkt),
+
+          // Master side
+          .M_PAYLOAD_DATA            (wach_dout),
+          .M_VALID                   (M_AXI_AWVALID),
+          .M_READY                   (M_AXI_AWREADY)
+          );
+
+    assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
+
+    assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; 
+    assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
+
+    always@(posedge S_ACLK or posedge inverted_reset) begin
+      if(inverted_reset == 1) begin
+\twr_pkt_count <= 0;
+      end else begin
+\tif(txn_count_up == 1 && txn_count_down == 0) begin
+\t  wr_pkt_count <= wr_pkt_count + 1;
+\tend else if(txn_count_up == 0 && txn_count_down == 1) begin
+\t  wr_pkt_count <= wr_pkt_count - 1;
+\tend
+      end
+    end //Always end
+    assign awvalid_en = (wr_pkt_count > 0)?1:0;
+  end endgenerate
+  
+  generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
+    assign awvalid_en    = 1;    
+    assign wach_dout     = wach_dout_pkt;
+    assign M_AXI_AWVALID = wach_m_axi_awvalid;
+  end
+  endgenerate
+
+
+
+  generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
+    // Write protection when almost full or prog_full is high
+    assign wdch_we    = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign wdch_re    = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
+    assign wdch_wr_en = (C_HAS_SLAVE_CE == 1)  ? wdch_we & S_ACLK_EN : wdch_we;
+    assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
+
+
+    fifo_generator_v13_1_3_CONV_VER
+      #(
+        .C_FAMILY\t\t\t(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_WDCH == 2  || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1  || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI
+        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),
+        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),
+        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),
+        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),
+        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),
+        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),
+        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),
+        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
+        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
+        .C_USE_ECC                      (C_USE_ECC_WDCH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WDCH),
+        .C_HAS_ALMOST_EMPTY\t\t(0),
+        .C_HAS_ALMOST_FULL\t\t(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WDCH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST\t\t\t(0),
+        .C_HAS_RD_RST\t\t\t(0),
+        .C_HAS_RST\t\t\t(1),
+        .C_HAS_SRST\t\t\t(0),
+        .C_DOUT_RST_VAL\t\t\t(0),
+
+        .C_HAS_VALID\t\t\t(0),
+        .C_VALID_LOW\t\t\t(C_VALID_LOW),
+        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK\t\t\t(0),
+        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),
+        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),
+        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG\t\t(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
+        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ\t\t\t(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ\t\t\t(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_1_3_wdch_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (S_ACLK),
+        .RD_CLK                   (M_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1\'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (wdch_wr_en),
+        .RD_EN                    (wdch_rd_en),
+        .PROG_FULL_THRESH         (AXI_W_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WDCH{1\'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WDCH{1\'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_W_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1\'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1\'b0}}),
+        .INJECTDBITERR            (AXI_W_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_W_INJECTSBITERR),
+  
+        .DIN                      (wdch_din),
+        .DOUT                     (wdch_dout),
+        .FULL                     (wdch_full),
+        .EMPTY                    (wdch_empty),
+        .ALMOST_FULL              (),
+        .PROG_FULL                (AXI_W_PROG_FULL),
+        .ALMOST_EMPTY             (),
+        .PROG_EMPTY               (AXI_W_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_w_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_w_underflow_i),
+        .DATA_COUNT               (AXI_W_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_W_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_W_WR_DATA_COUNT),
+        .SBITERR                  (AXI_W_SBITERR),
+        .DBITERR                  (AXI_W_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_wdch),
+        .rd_rst_busy              (rd_rst_busy_wdch),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign wdch_s_axi_wready     = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
+    assign wdch_m_axi_wvalid = ~wdch_empty;
+    assign S_AXI_WREADY      = wdch_s_axi_wready;
+    assign M_AXI_WVALID      = wdch_m_axi_wvalid;
+
+    assign AXI_W_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i  : 0;
+    assign AXI_W_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_w_overflow_i   : 0;
+
+  end endgenerate // axi_write_data_channel
+
+  // Register Slice for Write Data Channel
+  generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
+
+    fifo_generator_v13_1_3_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_WDCH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_WDCH)
+            )
+    wdch_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (axi_rs_rst),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (wdch_din),
+          .S_VALID                   (S_AXI_WVALID),
+          .S_READY                   (S_AXI_WREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (wdch_dout),
+          .M_VALID                   (M_AXI_WVALID),
+          .M_READY                   (M_AXI_WREADY)
+          );
+  end endgenerate // gwdch_reg_slice
+
+  generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
+    // Write protection when almost full or prog_full is high
+    assign wrch_we    = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign wrch_re    = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
+    assign wrch_wr_en = (C_HAS_MASTER_CE == 1)  ? wrch_we & M_ACLK_EN : wrch_we;
+    assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
+
+    fifo_generator_v13_1_3_CONV_VER
+      #(
+        .C_FAMILY\t\t\t(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_WRCH == 2  || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1  || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI
+        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),
+        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),
+        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),
+        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),
+        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),
+        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),
+        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),
+        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
+        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
+        .C_USE_ECC                      (C_USE_ECC_WRCH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_WRCH),
+        .C_HAS_ALMOST_EMPTY\t\t(0),
+        .C_HAS_ALMOST_FULL\t\t(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_WRCH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST\t\t\t(0),
+        .C_HAS_RD_RST\t\t\t(0),
+        .C_HAS_RST\t\t\t(1),
+        .C_HAS_SRST\t\t\t(0),
+        .C_DOUT_RST_VAL\t\t\t(0),
+
+        .C_HAS_VALID\t\t\t(0),
+        .C_VALID_LOW\t\t\t(C_VALID_LOW),
+        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK\t\t\t(0),
+        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),
+        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),
+        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG\t\t(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
+        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ\t\t\t(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ\t\t\t(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_1_3_wrch_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (M_ACLK),
+        .RD_CLK                   (S_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1\'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (wrch_wr_en),
+        .RD_EN                    (wrch_rd_en),
+        .PROG_FULL_THRESH         (AXI_B_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_WRCH{1\'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_WRCH{1\'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_B_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1\'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1\'b0}}),
+        .INJECTDBITERR            (AXI_B_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_B_INJECTSBITERR),
+  
+        .DIN                      (wrch_din),
+        .DOUT                     (wrch_dout),
+        .FULL                     (wrch_full),
+        .EMPTY                    (wrch_empty),
+        .ALMOST_FULL              (),
+        .ALMOST_EMPTY             (),
+        .PROG_FULL                (AXI_B_PROG_FULL),
+        .PROG_EMPTY               (AXI_B_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_b_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_b_underflow_i),
+        .DATA_COUNT               (AXI_B_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_B_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_B_WR_DATA_COUNT),
+        .SBITERR                  (AXI_B_SBITERR),
+        .DBITERR                  (AXI_B_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_wrch),
+        .rd_rst_busy              (rd_rst_busy_wrch),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign wrch_s_axi_bvalid = ~wrch_empty;
+    assign wrch_m_axi_bready     = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
+    assign S_AXI_BVALID      = wrch_s_axi_bvalid;
+    assign M_AXI_BREADY      = wrch_m_axi_bready;
+
+    assign AXI_B_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i  : 0;
+    assign AXI_B_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_b_overflow_i   : 0;
+  end endgenerate // axi_write_resp_channel
+
+  // Register Slice for Write Response Channel
+  generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
+
+    fifo_generator_v13_1_3_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_WRCH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_WRCH)
+            )
+    wrch_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (axi_rs_rst),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (wrch_din),
+          .S_VALID                   (M_AXI_BVALID),
+          .S_READY                   (M_AXI_BREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (wrch_dout),
+          .M_VALID                   (S_AXI_BVALID),
+          .M_READY                   (S_AXI_BREADY)
+          );
+  end endgenerate // gwrch_reg_slice
+
+
+    assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW  == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
+    assign axi_wr_overflow_i  = C_USE_COMMON_OVERFLOW   == 1 ? (axi_aw_overflow_i  || axi_w_overflow_i  || axi_b_overflow_i)  : 0;
+
+  generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
+    assign M_AXI_AWADDR    = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];    
+    assign M_AXI_AWLEN     = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];    
+    assign M_AXI_AWSIZE    = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];    
+    assign M_AXI_AWBURST   = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];    
+    assign M_AXI_AWLOCK    = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];    
+    assign M_AXI_AWCACHE   = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];    
+    assign M_AXI_AWPROT    = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];    
+    assign M_AXI_AWQOS     = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];    
+    assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET]    = S_AXI_AWADDR;
+    assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET]   = S_AXI_AWLEN;
+    assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET]   = S_AXI_AWSIZE;
+    assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
+    assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
+    assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
+    assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
+    assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET]   = S_AXI_AWQOS;
+  end endgenerate // axi_wach_output
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
+    assign M_AXI_AWREGION  = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];    
+  end endgenerate // axi_awregion
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
+    assign M_AXI_AWREGION  = 0;    
+  end endgenerate // naxi_awregion
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
+    assign M_AXI_AWUSER  = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];    
+  end endgenerate // axi_awuser
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
+    assign M_AXI_AWUSER  = 0;    
+  end endgenerate // naxi_awuser
+
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
+    assign M_AXI_AWID      = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
+  end endgenerate //axi_awid
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
+    assign M_AXI_AWID      = 0;
+  end endgenerate //naxi_awid
+
+  generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
+    assign M_AXI_WDATA     = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
+    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
+    assign M_AXI_WLAST     = wdch_dout[0];
+    assign wdch_din[WID_OFFSET-1:WDATA_OFFSET]   = S_AXI_WDATA;
+    assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
+    assign wdch_din[0]   = S_AXI_WLAST;
+  end endgenerate // axi_wdch_output
+
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
+    assign M_AXI_WID       = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
+  end endgenerate
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
+    assign M_AXI_WID       = 0;
+  end endgenerate
+
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
+    assign M_AXI_WUSER     = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];    
+  end endgenerate
+  generate if (C_HAS_AXI_WUSER == 0) begin
+    assign M_AXI_WUSER       = 0;
+  end endgenerate
+
+  generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
+    assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; 
+    assign wrch_din[BID_OFFSET-1:BRESP_OFFSET]   = M_AXI_BRESP;
+  end endgenerate // axi_wrch_output
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
+    assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
+  end endgenerate // axi_buser
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
+    assign S_AXI_BUSER = 0;
+  end endgenerate // naxi_buser
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_b'b'id
+    assign S_AXI_BID   =  wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
+  end endgenerate // axi_bid
+  
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
+    assign S_AXI_BID   =  0 ;
+  end endgenerate // naxi_bid  
+
+
+  generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
+    assign wach_din        = {S_AXI_AWADDR, S_AXI_AWPROT};
+    assign M_AXI_AWADDR    = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];    
+    assign M_AXI_AWPROT    = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];    
+  end endgenerate // axi_wach_output1
+
+  generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
+    assign wdch_din        = {S_AXI_WDATA, S_AXI_WSTRB};
+    assign M_AXI_WDATA     = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
+    assign M_AXI_WSTRB     = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
+  end endgenerate // axi_wdch_output1
+
+  generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
+    assign wrch_din        = M_AXI_BRESP;
+    assign S_AXI_BRESP     = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; 
+  end endgenerate // axi_wrch_output1
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
+    assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET]     = S_AXI_AWUSER;
+  end endgenerate // gwach_din1
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
+    assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET]     = S_AXI_AWID;
+  end endgenerate // gwach_din2
+
+  generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
+    assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET]     = S_AXI_AWREGION;
+  end endgenerate // gwach_din3
+
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
+    assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
+  end endgenerate // gwdch_din1
+
+  generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
+    assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
+  end endgenerate // gwdch_din2
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
+    assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET]    = M_AXI_BUSER;
+  end endgenerate // gwrch_din1
+
+  generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
+    assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET]    = M_AXI_BID;
+  end endgenerate // gwrch_din2
+
+  //end of  axi_write_channel
+
+  //###########################################################################
+  //  AXI FULL Read Channel (axi_read_channel)
+  //###########################################################################
+  wire [C_DIN_WIDTH_RACH-1:0]        rach_din            ;
+  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout           ;
+  wire [C_DIN_WIDTH_RACH-1:0]        rach_dout_pkt       ;
+  wire                               rach_full           ;
+  wire                               rach_almost_full    ;
+  wire                               rach_prog_full      ;
+  wire                               rach_empty          ;
+  wire                               rach_almost_empty   ;
+  wire                               rach_prog_empty     ;
+  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_din            ;
+  wire [C_DIN_WIDTH_RDCH-1:0]        rdch_dout           ;
+  wire                               rdch_full           ;
+  wire                               rdch_almost_full    ;
+  wire                               rdch_prog_full      ;
+  wire                               rdch_empty          ;
+  wire                               rdch_almost_empty   ;
+  wire                               rdch_prog_empty     ;
+  wire                               axi_ar_underflow_i  ;
+  wire                               axi_r_underflow_i   ;
+  wire                               axi_ar_overflow_i   ;
+  wire                               axi_r_overflow_i    ;
+  wire                               axi_rd_underflow_i  ;
+  wire                               axi_rd_overflow_i   ;
+  wire                               rach_s_axi_arready  ;
+  wire                               rach_m_axi_arvalid  ;
+  wire                               rach_wr_en          ;
+  wire                               rach_rd_en          ;
+  wire                               rdch_m_axi_rready   ;
+  wire                               rdch_s_axi_rvalid   ;
+  wire                               rdch_wr_en          ;
+  wire                               rdch_rd_en          ;
+  wire                               arvalid_pkt         ;
+  wire                               arready_pkt         ;
+  wire                               arvalid_en          ;
+  wire                               rdch_rd_ok          ;
+  wire                               accept_next_pkt     ;
+  integer                            rdch_free_space     ;
+  integer                            rdch_commited_space ;
+  wire                               rach_we             ;
+  wire                               rach_re             ;
+  wire                               rdch_we             ;
+  wire                               rdch_re             ;
+
+  localparam ARID_OFFSET       = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
+  localparam ARADDR_OFFSET     = ARID_OFFSET - C_AXI_ADDR_WIDTH;
+  localparam ARLEN_OFFSET      = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
+  localparam ARSIZE_OFFSET     = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
+  localparam ARBURST_OFFSET    = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
+  localparam ARLOCK_OFFSET     = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
+  localparam ARCACHE_OFFSET    = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
+  localparam ARPROT_OFFSET     = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
+  localparam ARQOS_OFFSET      = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
+  localparam ARREGION_OFFSET   = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
+  localparam ARUSER_OFFSET     = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
+
+  localparam RID_OFFSET        = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
+  localparam RDATA_OFFSET      = RID_OFFSET - C_AXI_DATA_WIDTH;
+  localparam RRESP_OFFSET      = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
+  localparam RUSER_OFFSET      = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
+
+
+  generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
+
+    // Write protection when almost full or prog_full is high
+    assign rach_we    = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
+
+    // Read protection when almost empty or prog_empty is high
+//    assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
+    assign rach_re    = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? 
+                        rach_m_axi_arvalid & arready_pkt & arvalid_en : 
+                        (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? 
+                        M_AXI_ARREADY && rach_m_axi_arvalid :
+                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? 
+                        arready_pkt & arvalid_en : 
+                        (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? 
+                        M_AXI_ARREADY : 1\'b0;
+    assign rach_wr_en = (C_HAS_SLAVE_CE == 1)  ? rach_we & S_ACLK_EN : rach_we;
+    assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
+
+
+    fifo_generator_v13_1_3_CONV_VER
+      #(
+        .C_FAMILY\t\t\t(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_RACH == 2  || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1  || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI
+        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),
+        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),
+        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),
+        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),
+        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),
+        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),
+        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),
+        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
+        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
+        .C_USE_ECC                      (C_USE_ECC_RACH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RACH),
+        .C_HAS_ALMOST_EMPTY\t\t(0),
+        .C_HAS_ALMOST_FULL\t\t(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST\t\t\t(0),
+        .C_HAS_RD_RST\t\t\t(0),
+        .C_HAS_RST\t\t\t(1),
+        .C_HAS_SRST\t\t\t(0),
+        .C_DOUT_RST_VAL\t\t\t(0),
+
+        .C_HAS_VALID\t\t\t(0),
+        .C_VALID_LOW\t\t\t(C_VALID_LOW),
+        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK\t\t\t(0),
+        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),
+        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),
+        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG\t\t(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
+        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ\t\t\t(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ\t\t\t(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_1_3_rach_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (S_ACLK),
+        .RD_CLK                   (M_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1\'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (rach_wr_en),
+        .RD_EN                    (rach_rd_en),
+        .PROG_FULL_THRESH         (AXI_AR_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RACH{1\'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RACH{1\'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_AR_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1\'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1\'b0}}),
+        .INJECTDBITERR            (AXI_AR_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_AR_INJECTSBITERR),
+  
+        .DIN                      (rach_din),
+        .DOUT                     (rach_dout_pkt),
+        .FULL                     (rach_full),
+        .EMPTY                    (rach_empty),
+        .ALMOST_FULL              (),
+        .ALMOST_EMPTY             (),
+        .PROG_FULL                (AXI_AR_PROG_FULL),
+        .PROG_EMPTY               (AXI_AR_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_ar_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_ar_underflow_i),
+        .DATA_COUNT               (AXI_AR_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_AR_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_AR_WR_DATA_COUNT),
+        .SBITERR                  (AXI_AR_SBITERR),
+        .DBITERR                  (AXI_AR_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_rach),
+        .rd_rst_busy              (rd_rst_busy_rach),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign rach_s_axi_arready    = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
+    assign rach_m_axi_arvalid = ~rach_empty;
+    assign S_AXI_ARREADY      = rach_s_axi_arready;
+
+    assign AXI_AR_UNDERFLOW  = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
+    assign AXI_AR_OVERFLOW   = C_USE_COMMON_OVERFLOW  == 0 ? axi_ar_overflow_i  : 0;
+
+  end endgenerate // axi_read_addr_channel
+
+  // Register Slice for Read Address Channel
+  generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
+
+    fifo_generator_v13_1_3_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_RACH)
+            )
+    rach_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (axi_rs_rst),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (rach_din),
+          .S_VALID                   (S_AXI_ARVALID),
+          .S_READY                   (S_AXI_ARREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (rach_dout),
+          .M_VALID                   (M_AXI_ARVALID),
+          .M_READY                   (M_AXI_ARREADY)
+          );
+  end endgenerate // grach_reg_slice
+
+  // Register Slice for Read Address Channel for MM Packet FIFO
+  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
+
+    fifo_generator_v13_1_3_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_RACH),
+            .C_REG_CONFIG            (1)
+            )
+    reg_slice_mm_pkt_fifo_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (inverted_reset),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (rach_dout_pkt),
+          .S_VALID                   (arvalid_pkt),
+          .S_READY                   (arready_pkt),
+
+          // Master side
+          .M_PAYLOAD_DATA            (rach_dout),
+          .M_VALID                   (M_AXI_ARVALID),
+          .M_READY                   (M_AXI_ARREADY)
+          );
+  end endgenerate // grach_reg_slice_mm_pkt_fifo
+
+  
+  generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
+    assign M_AXI_ARVALID      = rach_m_axi_arvalid;
+    assign rach_dout          = rach_dout_pkt;
+  end endgenerate // grach_m_axi_arvalid
+  
+  
+  generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
+    assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
+    assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
+    assign accept_next_pkt  = rach_m_axi_arvalid && arready_pkt && arvalid_en;
+
+    always@(posedge S_ACLK or posedge inverted_reset) begin
+      if(inverted_reset) begin
+\trdch_commited_space <= 0;
+      end else begin
+\tif(rdch_rd_ok && !accept_next_pkt) begin
+\t  rdch_commited_space <= rdch_commited_space-1;
+\tend else if(!rdch_rd_ok && accept_next_pkt) begin
+\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
+\tend else if(rdch_rd_ok && accept_next_pkt) begin
+\t  rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
+\tend
+      end
+    end //Always end
+
+    always@(*) begin
+      rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
+    end
+
+    assign arvalid_en = (rdch_free_space >= 0)?1:0;
+  end
+  endgenerate
+  
+  generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
+    assign arvalid_en = 1;    
+  end
+  endgenerate
+
+  generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
+
+    // Write protection when almost full or prog_full is high
+    assign rdch_we    = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready  & M_AXI_RVALID : M_AXI_RVALID;
+
+    // Read protection when almost empty or prog_empty is high
+    assign rdch_re    = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid  & S_AXI_RREADY : S_AXI_RREADY;
+    assign rdch_wr_en = (C_HAS_MASTER_CE == 1)  ? rdch_we & M_ACLK_EN : rdch_we;
+    assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
+
+    fifo_generator_v13_1_3_CONV_VER
+      #(
+        .C_FAMILY\t\t\t(C_FAMILY),
+        .C_COMMON_CLOCK                 (C_COMMON_CLOCK),
+        .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
+                                         (C_IMPLEMENTATION_TYPE_RDCH == 2  || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
+        .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1  || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
+                                         (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
+        .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI
+        .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI
+        .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),
+        .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),
+        .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),
+        .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),
+        .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),
+        .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),
+        .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),
+        .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),
+        .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
+        .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),
+        .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
+        .C_USE_ECC                      (C_USE_ECC_RDCH),
+        .C_ERROR_INJECTION_TYPE         (C_ERROR_INJECTION_TYPE_RDCH),
+        .C_HAS_ALMOST_EMPTY\t\t(0),
+        .C_HAS_ALMOST_FULL\t\t(0),
+        .C_AXI_TYPE                     (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
+
+        .C_FIFO_TYPE                    (C_APPLICATION_TYPE_RDCH),
+        .C_SYNCHRONIZER_STAGE           (C_SYNCHRONIZER_STAGE),
+
+        .C_HAS_WR_RST\t\t\t(0),
+        .C_HAS_RD_RST\t\t\t(0),
+        .C_HAS_RST\t\t\t(1),
+        .C_HAS_SRST\t\t\t(0),
+        .C_DOUT_RST_VAL\t\t\t(0),
+
+        .C_HAS_VALID\t\t\t(0),
+        .C_VALID_LOW\t\t\t(C_VALID_LOW),
+        .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),
+        .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),
+        .C_HAS_WR_ACK\t\t\t(0),
+        .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),
+        .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),
+        .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),
+
+        .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
+        .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),
+        .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
+        .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),
+        .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true
+        .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
+        .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),
+        .C_FULL_FLAGS_RST_VAL           (1),
+        .C_USE_EMBEDDED_REG\t\t(0),
+        .C_USE_DOUT_RST                 (0),
+        .C_MSGON_VAL                    (C_MSGON_VAL),
+        .C_ENABLE_RST_SYNC              (1),
+        .C_EN_SAFETY_CKT                ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
+        .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),
+        .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),
+        .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),
+        .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),
+        .C_HAS_INT_CLK                  (C_HAS_INT_CLK),
+        .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),
+        .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),
+        .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),
+        .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),
+        .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),
+        .C_RD_FREQ\t\t\t(C_RD_FREQ),
+        .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),
+        .C_WR_FREQ\t\t\t(C_WR_FREQ),
+        .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)
+      )
+    fifo_generator_v13_1_3_rdch_dut
+      (
+        .CLK                      (S_ACLK),
+        .WR_CLK                   (M_ACLK),
+        .RD_CLK                   (S_ACLK),
+        .RST                      (inverted_reset),
+        .SRST                     (1\'b0),
+        .WR_RST                   (inverted_reset),
+        .RD_RST                   (inverted_reset),
+        .WR_EN                    (rdch_wr_en),
+        .RD_EN                    (rdch_rd_en),
+        .PROG_FULL_THRESH         (AXI_R_PROG_FULL_THRESH),
+        .PROG_FULL_THRESH_ASSERT  ({C_WR_PNTR_WIDTH_RDCH{1\'b0}}),
+        .PROG_FULL_THRESH_NEGATE  ({C_WR_PNTR_WIDTH_RDCH{1\'b0}}),
+        .PROG_EMPTY_THRESH        (AXI_R_PROG_EMPTY_THRESH),
+        .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1\'b0}}),
+        .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1\'b0}}),
+        .INJECTDBITERR            (AXI_R_INJECTDBITERR), 
+        .INJECTSBITERR            (AXI_R_INJECTSBITERR),
+  
+        .DIN                      (rdch_din),
+        .DOUT                     (rdch_dout),
+        .FULL                     (rdch_full),
+        .EMPTY                    (rdch_empty),
+        .ALMOST_FULL              (),
+        .ALMOST_EMPTY             (),
+        .PROG_FULL                (AXI_R_PROG_FULL),
+        .PROG_EMPTY               (AXI_R_PROG_EMPTY),
+  
+        .WR_ACK                   (),
+        .OVERFLOW                 (axi_r_overflow_i),
+        .VALID                    (),
+        .UNDERFLOW                (axi_r_underflow_i),
+        .DATA_COUNT               (AXI_R_DATA_COUNT),
+        .RD_DATA_COUNT            (AXI_R_RD_DATA_COUNT),
+        .WR_DATA_COUNT            (AXI_R_WR_DATA_COUNT),
+        .SBITERR                  (AXI_R_SBITERR),
+        .DBITERR                  (AXI_R_DBITERR),
+        .wr_rst_busy              (wr_rst_busy_rdch),
+        .rd_rst_busy              (rd_rst_busy_rdch),
+        .wr_rst_i_out             (),
+        .rd_rst_i_out             (),
+  
+        .BACKUP                   (BACKUP),
+        .BACKUP_MARKER            (BACKUP_MARKER),
+        .INT_CLK                  (INT_CLK)
+       );
+
+    assign rdch_s_axi_rvalid = ~rdch_empty;
+    assign rdch_m_axi_rready     = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
+    assign S_AXI_RVALID      = rdch_s_axi_rvalid;
+    assign M_AXI_RREADY      = rdch_m_axi_rready;
+
+    assign AXI_R_UNDERFLOW   = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i  : 0;
+    assign AXI_R_OVERFLOW    = C_USE_COMMON_OVERFLOW  == 0 ? axi_r_overflow_i   : 0;
+
+  end endgenerate //axi_read_data_channel
+
+  // Register Slice for read Data Channel
+  generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
+
+    fifo_generator_v13_1_3_axic_reg_slice
+          #(
+            .C_FAMILY                (C_FAMILY),
+            .C_DATA_WIDTH            (C_DIN_WIDTH_RDCH),
+            .C_REG_CONFIG            (C_REG_SLICE_MODE_RDCH)
+            )
+    rdch_reg_slice_inst
+        (
+          // System Signals
+          .ACLK                      (S_ACLK),
+          .ARESET                    (axi_rs_rst),
+
+          // Slave side
+          .S_PAYLOAD_DATA            (rdch_din),
+          .S_VALID                   (M_AXI_RVALID),
+          .S_READY                   (M_AXI_RREADY),
+
+          // Master side
+          .M_PAYLOAD_DATA            (rdch_dout),
+          .M_VALID                   (S_AXI_RVALID),
+          .M_READY                   (S_AXI_RREADY)
+          );
+  end endgenerate // grdch_reg_slice
+
+
+    assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
+    assign axi_rd_overflow_i  = C_USE_COMMON_OVERFLOW  == 1 ? (axi_ar_overflow_i  || axi_r_overflow_i) : 0;
+
+
+  generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
+    assign M_AXI_ARADDR    = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];    
+    assign M_AXI_ARLEN     = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];    
+    assign M_AXI_ARSIZE    = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];    
+    assign M_AXI_ARBURST   = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];    
+    assign M_AXI_ARLOCK    = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];    
+    assign M_AXI_ARCACHE   = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];    
+    assign M_AXI_ARPROT    = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];    
+    assign M_AXI_ARQOS     = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];    
+    assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET]    = S_AXI_ARADDR;
+    assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET]   = S_AXI_ARLEN;
+    assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET]   = S_AXI_ARSIZE;
+    assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
+    assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
+    assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
+    assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
+    assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET]   = S_AXI_ARQOS;
+  end endgenerate // axi_full_rach_output
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
+    assign M_AXI_ARREGION  = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];    
+  end endgenerate // axi_arregion
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
+    assign M_AXI_ARREGION  = 0;    
+  end endgenerate // naxi_arregion
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
+    assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];    
+  end endgenerate // axi_aruser
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
+    assign M_AXI_ARUSER = 0;    
+  end endgenerate // naxi_aruser
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
+    assign M_AXI_ARID      = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
+  end endgenerate // axi_arid
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
+    assign M_AXI_ARID      = 0;
+  end endgenerate // naxi_arid
+
+  generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
+    assign S_AXI_RDATA     = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
+    assign S_AXI_RRESP     = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
+    assign S_AXI_RLAST     = rdch_dout[0];
+    assign rdch_din[RID_OFFSET-1:RDATA_OFFSET]   = M_AXI_RDATA;
+    assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
+    assign rdch_din[0] = M_AXI_RLAST;
+  end endgenerate // axi_full_rdch_output
+  
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
+    assign S_AXI_RUSER     = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
+  end endgenerate // axi_full_ruser_output
+
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
+    assign S_AXI_RUSER     =  0;
+  end endgenerate // axi_full_nruser_output
+  
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
+    assign S_AXI_RID       = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
+  end endgenerate // axi_rid
+
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
+    assign S_AXI_RID       = 0;
+  end endgenerate // naxi_rid
+
+  generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
+    assign rach_din      = {S_AXI_ARADDR, S_AXI_ARPROT};
+    assign M_AXI_ARADDR  = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
+    assign M_AXI_ARPROT  = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
+  end endgenerate // axi_lite_rach_output
+
+  generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
+    assign rdch_din      = {M_AXI_RDATA, M_AXI_RRESP};
+    assign S_AXI_RDATA   = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
+    assign S_AXI_RRESP   = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
+  end endgenerate // axi_lite_rdch_output
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
+    assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET]     = S_AXI_ARUSER;
+  end endgenerate // grach_din1
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
+    assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET]     = S_AXI_ARID;
+  end endgenerate // grach_din2
+
+  generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
+    assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
+  end endgenerate
+
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
+    assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET]     = M_AXI_RUSER;
+  end endgenerate // grdch_din1
+
+  generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
+    assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
+  end endgenerate // grdch_din2
+
+  //end of axi_read_channel
+
+  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
+    assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
+                       (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
+                       (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
+  end endgenerate // gaxi_comm_uf
+
+  generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
+    assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
+                      (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
+                      (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
+  end endgenerate // gaxi_comm_of
+  
+  //-------------------------------------------------------------------------
+  //-------------------------------------------------------------------------
+  //-------------------------------------------------------------------------
+  // Pass Through Logic or Wiring Logic
+  //-------------------------------------------------------------------------
+  //-------------------------------------------------------------------------
+  //-------------------------------------------------------------------------
+  
+  //-------------------------------------------------------------------------
+  // Pass Through Logic for Read Channel
+  //-------------------------------------------------------------------------
+
+  // Wiring logic for Write Address Channel
+  generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
+    assign M_AXI_AWID      = S_AXI_AWID;
+    assign M_AXI_AWADDR    = S_AXI_AWADDR;
+    assign M_AXI_AWLEN     = S_AXI_AWLEN;
+    assign M_AXI_AWSIZE    = S_AXI_AWSIZE;
+    assign M_AXI_AWBURST   = S_AXI_AWBURST;
+    assign M_AXI_AWLOCK    = S_AXI_AWLOCK;
+    assign M_AXI_AWCACHE   = S_AXI_AWCACHE;
+    assign M_AXI_AWPROT    = S_AXI_AWPROT;
+    assign M_AXI_AWQOS     = S_AXI_AWQOS;
+    assign M_AXI_AWREGION  = S_AXI_AWREGION;
+    assign M_AXI_AWUSER    = S_AXI_AWUSER;
+    assign S_AXI_AWREADY   = M_AXI_AWREADY;
+    assign M_AXI_AWVALID   = S_AXI_AWVALID;
+  end endgenerate // gwach_pass_through;
+
+  // Wiring logic for Write Data Channel
+  generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
+    assign M_AXI_WID       = S_AXI_WID;
+    assign M_AXI_WDATA     = S_AXI_WDATA;
+    assign M_AXI_WSTRB     = S_AXI_WSTRB;
+    assign M_AXI_WLAST     = S_AXI_WLAST;
+    assign M_AXI_WUSER     = S_AXI_WUSER;
+    assign S_AXI_WREADY    = M_AXI_WREADY;
+    assign M_AXI_WVALID    = S_AXI_WVALID;
+  end endgenerate // gwdch_pass_through;
+
+  // Wiring logic for Write Response Channel
+  generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
+    assign S_AXI_BID       = M_AXI_BID;
+    assign S_AXI_BRESP     = M_AXI_BRESP;
+    assign S_AXI_BUSER     = M_AXI_BUSER;
+    assign M_AXI_BREADY    = S_AXI_BREADY;
+    assign S_AXI_BVALID    = M_AXI_BVALID;
+  end endgenerate // gwrch_pass_through;
+
+  //-------------------------------------------------------------------------
+  // Pass Through Logic for Read Channel
+  //-------------------------------------------------------------------------
+
+  // Wiring logic for Read Address Channel
+  generate if (C_RACH_TYPE == 2) begin : grach_pass_through
+    assign M_AXI_ARID      = S_AXI_ARID;
+    assign M_AXI_ARADDR    = S_AXI_ARADDR;
+    assign M_AXI_ARLEN     = S_AXI_ARLEN;
+    assign M_AXI_ARSIZE    = S_AXI_ARSIZE;
+    assign M_AXI_ARBURST   = S_AXI_ARBURST;
+    assign M_AXI_ARLOCK    = S_AXI_ARLOCK;
+    assign M_AXI_ARCACHE   = S_AXI_ARCACHE;
+    assign M_AXI_ARPROT    = S_AXI_ARPROT;
+    assign M_AXI_ARQOS     = S_AXI_ARQOS;
+    assign M_AXI_ARREGION  = S_AXI_ARREGION;
+    assign M_AXI_ARUSER    = S_AXI_ARUSER;
+    assign S_AXI_ARREADY   = M_AXI_ARREADY;
+    assign M_AXI_ARVALID   = S_AXI_ARVALID;
+  end endgenerate // grach_pass_through;
+
+  // Wiring logic for Read Data Channel 
+  generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
+    assign S_AXI_RID      = M_AXI_RID;
+    assign S_AXI_RLAST    = M_AXI_RLAST;
+    assign S_AXI_RUSER    = M_AXI_RUSER;
+    assign S_AXI_RDATA    = M_AXI_RDATA;
+    assign S_AXI_RRESP    = M_AXI_RRESP;
+    assign S_AXI_RVALID   = M_AXI_RVALID;
+    assign M_AXI_RREADY   = S_AXI_RREADY;
+  end endgenerate // grdch_pass_through;
+
+  // Wiring logic for AXI Streaming
+  generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
+    assign M_AXIS_TDATA   = S_AXIS_TDATA;
+    assign M_AXIS_TSTRB   = S_AXIS_TSTRB;
+    assign M_AXIS_TKEEP   = S_AXIS_TKEEP;
+    assign M_AXIS_TID     = S_AXIS_TID;
+    assign M_AXIS_TDEST   = S_AXIS_TDEST;
+    assign M_AXIS_TUSER   = S_AXIS_TUSER;
+    assign M_AXIS_TLAST   = S_AXIS_TLAST;
+    assign S_AXIS_TREADY  = M_AXIS_TREADY;
+    assign M_AXIS_TVALID  = S_AXIS_TVALID;
+  end endgenerate // gaxis_pass_through;
+
+
+endmodule //fifo_generator_v13_1_3
+
+
+
+/*******************************************************************************
+ * Declaration of top-level module for Conventional FIFO
+ ******************************************************************************/
+module fifo_generator_v13_1_3_CONV_VER
+  #(
+    parameter  C_COMMON_CLOCK                 = 0,
+    parameter  C_INTERFACE_TYPE               = 0,
+    parameter  C_EN_SAFETY_CKT                = 0,
+    parameter  C_COUNT_TYPE                   = 0,
+    parameter  C_DATA_COUNT_WIDTH             = 2,
+    parameter  C_DEFAULT_VALUE                = """",
+    parameter  C_DIN_WIDTH                    = 8,
+    parameter  C_DOUT_RST_VAL                 = """",
+    parameter  C_DOUT_WIDTH                   = 8,
+    parameter  C_ENABLE_RLOCS                 = 0,
+    parameter  C_FAMILY                       = ""virtex7"", //Not allowed in Verilog model
+    parameter  C_FULL_FLAGS_RST_VAL           = 1,
+    parameter  C_HAS_ALMOST_EMPTY             = 0,
+    parameter  C_HAS_ALMOST_FULL              = 0,
+    parameter  C_HAS_BACKUP                   = 0,
+    parameter  C_HAS_DATA_COUNT               = 0,
+    parameter  C_HAS_INT_CLK                  = 0,
+    parameter  C_HAS_MEMINIT_FILE             = 0,
+    parameter  C_HAS_OVERFLOW                 = 0,
+    parameter  C_HAS_RD_DATA_COUNT            = 0,
+    parameter  C_HAS_RD_RST                   = 0,
+    parameter  C_HAS_RST                      = 0,
+    parameter  C_HAS_SRST                     = 0,
+    parameter  C_HAS_UNDERFLOW                = 0,
+    parameter  C_HAS_VALID                    = 0,
+    parameter  C_HAS_WR_ACK                   = 0,
+    parameter  C_HAS_WR_DATA_COUNT            = 0,
+    parameter  C_HAS_WR_RST                   = 0,
+    parameter  C_IMPLEMENTATION_TYPE          = 0,
+    parameter  C_INIT_WR_PNTR_VAL             = 0,
+    parameter  C_MEMORY_TYPE                  = 1,
+    parameter  C_MIF_FILE_NAME                = """",
+    parameter  C_OPTIMIZATION_MODE            = 0,
+    parameter  C_OVERFLOW_LOW                 = 0,
+    parameter  C_PRELOAD_LATENCY              = 1,
+    parameter  C_PRELOAD_REGS                 = 0,
+    parameter  C_PRIM_FIFO_TYPE               = """",
+    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
+    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
+    parameter  C_PROG_EMPTY_TYPE              = 0,
+    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,
+    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,
+    parameter  C_PROG_FULL_TYPE               = 0,
+    parameter  C_RD_DATA_COUNT_WIDTH          = 2,
+    parameter  C_RD_DEPTH                     = 256,
+    parameter  C_RD_FREQ                      = 1,
+    parameter  C_RD_PNTR_WIDTH                = 8,
+    parameter  C_UNDERFLOW_LOW                = 0,
+    parameter  C_USE_DOUT_RST                 = 0,
+    parameter  C_USE_ECC                      = 0,
+    parameter  C_USE_EMBEDDED_REG             = 0,
+    parameter  C_USE_FIFO16_FLAGS             = 0,
+    parameter  C_USE_FWFT_DATA_COUNT          = 0,
+    parameter  C_VALID_LOW                    = 0,
+    parameter  C_WR_ACK_LOW                   = 0,
+    parameter  C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter  C_WR_DEPTH                     = 256,
+    parameter  C_WR_FREQ                      = 1,
+    parameter  C_WR_PNTR_WIDTH                = 8,
+    parameter  C_WR_RESPONSE_LATENCY          = 1,
+    parameter  C_MSGON_VAL                    = 1,
+    parameter  C_ENABLE_RST_SYNC              = 1,
+    parameter  C_ERROR_INJECTION_TYPE         = 0,
+    parameter  C_FIFO_TYPE                    = 0,
+    parameter  C_SYNCHRONIZER_STAGE           = 2,
+    parameter  C_AXI_TYPE                     = 0
+   )
+
+  (
+   input                               BACKUP,
+   input                               BACKUP_MARKER,
+   input                               CLK,
+   input                               RST,
+   input                               SRST,
+   input                               WR_CLK,
+   input                               WR_RST,
+   input                               RD_CLK,
+   input                               RD_RST,
+   input [C_DIN_WIDTH-1:0]             DIN,
+   input                               WR_EN,
+   input                               RD_EN,
+   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH,
+   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_ASSERT,
+   input [C_RD_PNTR_WIDTH-1:0]         PROG_EMPTY_THRESH_NEGATE,
+   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH,
+   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_ASSERT,
+   input [C_WR_PNTR_WIDTH-1:0]         PROG_FULL_THRESH_NEGATE,
+   input                               INT_CLK,
+   input                               INJECTDBITERR,
+   input                               INJECTSBITERR,
+  
+   output [C_DOUT_WIDTH-1:0]           DOUT,
+   output                              FULL,
+   output                              ALMOST_FULL,
+   output                              WR_ACK,
+   output                              OVERFLOW,
+   output                              EMPTY,
+   output                              ALMOST_EMPTY,
+   output                              VALID,
+   output                              UNDERFLOW,
+   output [C_DATA_COUNT_WIDTH-1:0]     DATA_COUNT,
+   output [C_RD_DATA_COUNT_WIDTH-1:0]  RD_DATA_COUNT,
+   output [C_WR_DATA_COUNT_WIDTH-1:0]  WR_DATA_COUNT,
+   output                              PROG_FULL,
+   output                              PROG_EMPTY,
+   output                              SBITERR,
+   output                              DBITERR,
+   output                              wr_rst_busy_o,
+   output                              wr_rst_busy,
+   output                              rd_rst_busy,
+   output                              wr_rst_i_out,
+   output                              rd_rst_i_out
+  );
+
+/*
+ ******************************************************************************
+ * Definition of Parameters
+ ******************************************************************************
+ *     C_COMMON_CLOCK                : Common Clock (1), Independent Clocks (0)
+ *     C_COUNT_TYPE                  :    *not used
+ *     C_DATA_COUNT_WIDTH            : Width of DATA_COUNT bus
+ *     C_DEFAULT_VALUE               :    *not used
+ *     C_DIN_WIDTH                   : Width of DIN bus
+ *     C_DOUT_RST_VAL                : Reset value of DOUT
+ *     C_DOUT_WIDTH                  : Width of DOUT bus
+ *     C_ENABLE_RLOCS                :    *not used
+ *     C_FAMILY                      : not used in bhv model
+ *     C_FULL_FLAGS_RST_VAL          : Full flags rst val (0 or 1)
+ *     C_HAS_ALMOST_EMPTY            : 1=Core has ALMOST_EMPTY flag
+ *     C_HAS_ALMOST_FULL             : 1=Core has ALMOST_FULL flag
+ *     C_HAS_BACKUP                  :    *not used
+ *     C_HAS_DATA_COUNT              : 1=Core has DATA_COUNT bus
+ *     C_HAS_INT_CLK                 : not used in bhv model
+ *     C_HAS_MEMINIT_FILE            :    *not used
+ *     C_HAS_OVERFLOW                : 1=Core has OVERFLOW flag
+ *     C_HAS_RD_DATA_COUNT           : 1=Core has RD_DATA_COUNT bus
+ *     C_HAS_RD_RST                  :    *not used
+ *     C_HAS_RST                     : 1=Core has Async Rst
+ *     C_HAS_SRST                    : 1=Core has Sync Rst
+ *     C_HAS_UNDERFLOW               : 1=Core has UNDERFLOW flag
+ *     C_HAS_VALID                   : 1=Core has VALID flag
+ *     C_HAS_WR_ACK                  : 1=Core has WR_ACK flag
+ *     C_HAS_WR_DATA_COUNT           : 1=Core has WR_DATA_COUNT bus
+ *     C_HAS_WR_RST                  :    *not used
+ *     C_IMPLEMENTATION_TYPE         : 0=Common-Clock Bram/Dram
+ *                                     1=Common-Clock ShiftRam
+ *                                     2=Indep. Clocks Bram/Dram
+ *                                     3=Virtex-4 Built-in
+ *                                     4=Virtex-5 Built-in
+ *     C_INIT_WR_PNTR_VAL            :   *not used
+ *     C_MEMORY_TYPE                 : 1=Block RAM
+ *                                     2=Distributed RAM
+ *                                     3=Shift RAM
+ *                                     4=Built-in FIFO
+ *     C_MIF_FILE_NAME               :   *not used
+ *     C_OPTIMIZATION_MODE           :   *not used
+ *     C_OVERFLOW_LOW                : 1=OVERFLOW active low
+ *     C_PRELOAD_LATENCY             : Latency of read: 0, 1, 2
+ *     C_PRELOAD_REGS                : 1=Use output registers
+ *     C_PRIM_FIFO_TYPE              : not used in bhv model
+ *     C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
+ *     C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
+ *     C_PROG_EMPTY_TYPE             : 0=No programmable empty
+ *                                     1=Single prog empty thresh constant
+ *                                     2=Multiple prog empty thresh constants
+ *                                     3=Single prog empty thresh input
+ *                                     4=Multiple prog empty thresh inputs
+ *     C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
+ *     C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
+ *     C_PROG_FULL_TYPE              : 0=No prog full
+ *                                     1=Single prog full thresh constant
+ *                                     2=Multiple prog full thresh constants
+ *                                     3=Single prog full thresh input
+ *                                     4=Multiple prog full thresh inputs
+ *     C_RD_DATA_COUNT_WIDTH         : Width of RD_DATA_COUNT bus
+ *     C_RD_DEPTH                    : Depth of read interface (2^N)
+ *     C_RD_FREQ                     : not used in bhv model
+ *     C_RD_PNTR_WIDTH               : always log2(C_RD_DEPTH)
+ *     C_UNDERFLOW_LOW               : 1=UNDERFLOW active low
+ *     C_USE_DOUT_RST                : 1=Resets DOUT on RST
+ *     C_USE_ECC                     : Used for error injection purpose
+ *     C_USE_EMBEDDED_REG            : 1=Use BRAM embedded output register
+ *     C_USE_FIFO16_FLAGS            : not used in bhv model
+ *     C_USE_FWFT_DATA_COUNT         : 1=Use extra logic for FWFT data count
+ *     C_VALID_LOW                   : 1=VALID active low
+ *     C_WR_ACK_LOW                  : 1=WR_ACK active low
+ *     C_WR_DATA_COUNT_WIDTH         : Width of WR_DATA_COUNT bus
+ *     C_WR_DEPTH                    : Depth of write interface (2^N)
+ *     C_WR_FREQ                     : not used in bhv model
+ *     C_WR_PNTR_WIDTH               : always log2(C_WR_DEPTH)
+ *     C_WR_RESPONSE_LATENCY         :    *not used
+ *     C_MSGON_VAL                   :    *not used by bhv model
+ *     C_ENABLE_RST_SYNC             : 0 = Use WR_RST & RD_RST
+ *                                     1 = Use RST
+ *     C_ERROR_INJECTION_TYPE        : 0 = No error injection
+ *                                     1 = Single bit error injection only
+ *                                     2 = Double bit error injection only
+ *                                     3 = Single and double bit error injection
+ ******************************************************************************
+ * Definition of Ports
+ ******************************************************************************
+ *   BACKUP       : Not used
+ *   BACKUP_MARKER: Not used
+ *   CLK          : Clock
+ *   DIN          : Input data bus
+ *   PROG_EMPTY_THRESH       : Threshold for Programmable Empty Flag
+ *   PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
+ *   PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
+ *   PROG_FULL_THRESH        : Threshold for Programmable Full Flag
+ *   PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
+ *   PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
+ *   RD_CLK       : Read Domain Clock
+ *   RD_EN        : Read enable
+ *   RD_RST       : Read Reset
+ *   RST          : Asynchronous Reset
+ *   SRST         : Synchronous Reset
+ *   WR_CLK       : Write Domain Clock
+ *   WR_EN        : Write enable
+ *   WR_RST       : Write Reset
+ *   INT_CLK      : Internal Clock
+ *   INJECTSBITERR: Inject Signle bit error
+ *   INJECTDBITERR: Inject Double bit error
+ *   ALMOST_EMPTY : One word remaining in FIFO
+ *   ALMOST_FULL  : One empty space remaining in FIFO
+ *   DATA_COUNT   : Number of data words in fifo( synchronous to CLK)
+ *   DOUT         : Output data bus
+ *   EMPTY        : Empty flag
+ *   FULL         : Full flag
+ *   OVERFLOW     : Last write rejected
+ *   PROG_EMPTY   : Programmable Empty Flag
+ *   PROG_FULL    : Programmable Full Flag
+ *   RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
+ *   UNDERFLOW    : Last read rejected
+ *   VALID        : Last read acknowledged, DOUT bus VALID
+ *   WR_ACK       : Last write acknowledged
+ *   WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
+ *   SBITERR      : Single Bit ECC Error Detected
+ *   DBITERR      : Double Bit ECC Error Detected
+ ******************************************************************************
+ */
+
+  //----------------------------------------------------------------------------
+  //- Internal Signals for delayed input signals
+  //- All the input signals except Clock are delayed by 100 ps and then given to
+  //- the models.
+  //----------------------------------------------------------------------------
+ 
+  reg                         rst_delayed                       ;
+  reg                         empty_fb                       ;
+  reg                         srst_delayed                      ;
+  reg                         wr_rst_delayed                    ;
+  reg                         rd_rst_delayed                    ;
+  reg                         wr_en_delayed                     ;
+  reg                         rd_en_delayed                     ;
+  reg  [C_DIN_WIDTH-1:0]      din_delayed                       ;
+  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_delayed         ;
+  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_assert_delayed  ;
+  reg  [C_RD_PNTR_WIDTH-1:0]  prog_empty_thresh_negate_delayed  ;
+  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_delayed          ;
+  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_assert_delayed   ;
+  reg  [C_WR_PNTR_WIDTH-1:0]  prog_full_thresh_negate_delayed   ;
+  reg                         injectdbiterr_delayed             ;
+  reg                         injectsbiterr_delayed             ;
+   wire                        empty_p0_out;
+
+  always @* rst_delayed                       <= #`TCQ RST                      ;
+  always @* empty_fb                       <= #`TCQ empty_p0_out                      ;
+  always @* srst_delayed                      <= #`TCQ SRST                     ; 
+  always @* wr_rst_delayed                    <= #`TCQ WR_RST                   ; 
+  always @* rd_rst_delayed                    <= #`TCQ RD_RST                   ; 
+  always @* din_delayed                       <= #`TCQ DIN                      ; 
+  always @* wr_en_delayed                     <= #`TCQ WR_EN                    ; 
+  always @* rd_en_delayed                     <= #`TCQ RD_EN                    ; 
+  always @* prog_empty_thresh_delayed         <= #`TCQ PROG_EMPTY_THRESH        ; 
+  always @* prog_empty_thresh_assert_delayed  <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; 
+  always @* prog_empty_thresh_negate_delayed  <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; 
+  always @* prog_full_thresh_delayed          <= #`TCQ PROG_FULL_THRESH         ; 
+  always @* prog_full_thresh_assert_delayed   <= #`TCQ PROG_FULL_THRESH_ASSERT  ; 
+  always @* prog_full_thresh_negate_delayed   <= #`TCQ PROG_FULL_THRESH_NEGATE  ; 
+  always @* injectdbiterr_delayed             <= #`TCQ INJECTDBITERR            ; 
+  always @* injectsbiterr_delayed             <= #`TCQ INJECTSBITERR            ; 
+
+  /*****************************************************************************
+   * Derived parameters
+   ****************************************************************************/
+  //There are 2 Verilog behavioral models
+  // 0 = Common-Clock FIFO/ShiftRam FIFO
+  // 1 = Independent Clocks FIFO
+  // 2 = Low Latency Synchronous FIFO
+  // 3 = Low Latency Asynchronous FIFO
+  localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
+                              (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
+  localparam IS_8SERIES         = (C_FAMILY == ""virtexu"" || C_FAMILY == ""kintexu"" || C_FAMILY == ""artixu"" || C_FAMILY == ""virtexuplus"" || C_FAMILY == ""zynquplus"" || C_FAMILY == ""kintexuplus"") ? 1 : 0;
+
+  //Internal reset signals
+  reg                                rd_rst_asreg    = 0;
+  wire                               rd_rst_asreg_d1;
+  wire                               rd_rst_asreg_d2;
+  reg                                rd_rst_asreg_d3 = 0;
+  reg                                rd_rst_reg      = 0;
+  wire                               rd_rst_comb;
+  reg                                wr_rst_d0       = 0;
+  reg                                wr_rst_d1       = 0;
+  reg                                wr_rst_d2       = 0;
+  reg                                rd_rst_d0       = 0;
+  reg                                rd_rst_d1       = 0;
+  reg                                rd_rst_d2       = 0;
+  reg                                rd_rst_d3       = 0;
+  reg                                wrrst_done      = 0;
+  reg                                rdrst_done      = 0;
+  reg                                wr_rst_asreg    = 0;
+  wire                               wr_rst_asreg_d1;
+  wire                               wr_rst_asreg_d2;
+  reg                                wr_rst_asreg_d3 = 0;
+  reg                                rd_rst_wr_d0    = 0;
+  reg                                rd_rst_wr_d1    = 0;
+  reg                                rd_rst_wr_d2    = 0;
+  reg                                wr_rst_reg      = 0;
+  reg                                rst_active_i    = 1\'b1;
+  reg                                rst_delayed_d1  = 1\'b1;
+  reg                                rst_delayed_d2  = 1\'b1;
+  wire                               wr_rst_comb;
+  wire                               wr_rst_i;
+  wire                               rd_rst_i;
+  wire                               rst_i;
+
+  //Internal reset signals
+  reg                                rst_asreg    = 0;
+  reg                                srst_asreg    = 0;
+  wire                               rst_asreg_d1;
+  wire                               rst_asreg_d2;
+  reg                                srst_asreg_d1 = 0;
+  reg                                srst_asreg_d2 = 0;
+  reg                                rst_reg      = 0;
+  reg                                srst_reg      = 0;
+  wire                               rst_comb;
+  wire                               srst_comb;
+  reg                                rst_full_gen_i = 0;
+  reg                                rst_full_ff_i = 0;
+  reg  [2:0]                         sckt_ff0_bsy_o_i = {3{1\'b0}};
+                                     
+  wire                               RD_CLK_P0_IN;
+  wire                               RST_P0_IN;
+  wire                               RD_EN_FIFO_IN;
+  wire                               RD_EN_P0_IN;
+
+  wire                               ALMOST_EMPTY_FIFO_OUT;
+  wire                               ALMOST_FULL_FIFO_OUT;
+  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;
+  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;
+  wire                               EMPTY_FIFO_OUT;
+  wire                               fifo_empty_fb;
+  wire                               FULL_FIFO_OUT;
+  wire                               OVERFLOW_FIFO_OUT;
+  wire                               PROG_EMPTY_FIFO_OUT;
+  wire                               PROG_FULL_FIFO_OUT;
+  wire                               VALID_FIFO_OUT;
+  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;
+  wire                               UNDERFLOW_FIFO_OUT;
+  wire                               WR_ACK_FIFO_OUT;
+  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;
+
+
+  //***************************************************************************
+  // Internal Signals
+  //   The core uses either the internal_ wires or the preload0_ wires depending
+  //     on whether the core uses Preload0 or not.
+  //   When using preload0, the internal signals connect the internal core to
+  //     the preload logic, and the external core\'s interfaces are tied to the
+  //     preload0 signals from the preload logic.
+  //***************************************************************************
+  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;
+  wire                               VALID_P0_OUT;
+  wire                               EMPTY_P0_OUT;
+  wire                               ALMOSTEMPTY_P0_OUT;
+  reg                                EMPTY_P0_OUT_Q;
+  reg                                ALMOSTEMPTY_P0_OUT_Q;
+  wire                               UNDERFLOW_P0_OUT;
+  wire                               RDEN_P0_OUT;
+  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;
+  wire                               EMPTY_P0_IN;
+  reg  [31:0]                        DATA_COUNT_FWFT;
+  reg                                SS_FWFT_WR  ;
+  reg                                SS_FWFT_RD ;
+
+  wire                               sbiterr_fifo_out;
+  wire                               dbiterr_fifo_out;
+  wire                               inject_sbit_err;
+  wire                               inject_dbit_err;
+  wire                               safety_ckt_wr_rst;
+  wire                               safety_ckt_rd_rst;
+  reg                                sckt_wr_rst_i_q = 1\'b0;
+ 
+  wire                               w_fab_read_data_valid_i;
+  wire                               w_read_data_valid_i;
+  wire                               w_ram_valid_i;
+  // Assign 0 if not selected to avoid \'X\' propogation to S/DBITERR.
+  assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
+                           injectsbiterr_delayed : 0;
+  assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
+                           injectdbiterr_delayed : 0;
+                           
+  assign wr_rst_i_out = wr_rst_i;
+  assign rd_rst_i_out = rd_rst_i;
+  assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
+  generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
+    wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
+    always @ (posedge clk_i)
+      sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; 
+  end endgenerate 
+// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
+// parameter (1=Independent Clocks, 0=Common Clock)
+
+  localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
+generate
+case (C_VERILOG_IMPL)
+0 : begin : block1
+  //Common Clock Behavioral Model
+  fifo_generator_v13_1_3_bhv_ver_ss
+  #(
+    .C_FAMILY                            (C_FAMILY),
+    .C_DATA_COUNT_WIDTH                  (C_DATA_COUNT_WIDTH),            
+    .C_DIN_WIDTH                         (C_DIN_WIDTH),                   
+    .C_DOUT_RST_VAL                      (C_DOUT_RST_VAL),                
+    .C_DOUT_WIDTH                        (C_DOUT_WIDTH),                  
+    .C_FULL_FLAGS_RST_VAL                (FULL_FLAGS_RST_VAL),            
+    .C_HAS_ALMOST_EMPTY                  (C_HAS_ALMOST_EMPTY),            
+    .C_HAS_ALMOST_FULL                   ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),             
+    .C_HAS_DATA_COUNT                    (C_HAS_DATA_COUNT),              
+    .C_HAS_OVERFLOW                      (C_HAS_OVERFLOW),                
+    .C_HAS_RD_DATA_COUNT                 (C_HAS_RD_DATA_COUNT),           
+    .C_HAS_RST                           (C_HAS_RST),                     
+    .C_HAS_SRST                          (C_HAS_SRST),                    
+    .C_HAS_UNDERFLOW                     (C_HAS_UNDERFLOW),               
+    .C_HAS_VALID                         (C_HAS_VALID),                   
+    .C_HAS_WR_ACK                        (C_HAS_WR_ACK),                  
+    .C_HAS_WR_DATA_COUNT                 (C_HAS_WR_DATA_COUNT),           
+    .C_IMPLEMENTATION_TYPE               (C_IMPLEMENTATION_TYPE),         
+    .C_MEMORY_TYPE                       (C_MEMORY_TYPE),                 
+    .C_OVERFLOW_LOW                      (C_OVERFLOW_LOW),                
+    .C_PRELOAD_LATENCY                   (C_PRELOAD_LATENCY),             
+    .C_PRELOAD_REGS                      (C_PRELOAD_REGS),                
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL      (C_PROG_EMPTY_THRESH_ASSERT_VAL),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL      (C_PROG_EMPTY_THRESH_NEGATE_VAL),
+    .C_PROG_EMPTY_TYPE                   (C_PROG_EMPTY_TYPE),             
+    .C_PROG_FULL_THRESH_ASSERT_VAL       (C_PROG_FULL_THRESH_ASSERT_VAL), 
+    .C_PROG_FULL_THRESH_NEGATE_VAL       (C_PROG_FULL_THRESH_NEGATE_VAL), 
+    .C_PROG_FULL_TYPE                    (C_PROG_FULL_TYPE),              
+    .C_RD_DATA_COUNT_WIDTH               (C_RD_DATA_COUNT_WIDTH),         
+    .C_RD_DEPTH                          (C_RD_DEPTH),                    
+    .C_RD_PNTR_WIDTH                     (C_RD_PNTR_WIDTH),               
+    .C_UNDERFLOW_LOW                     (C_UNDERFLOW_LOW),               
+    .C_USE_DOUT_RST                      (C_USE_DOUT_RST),                
+    .C_USE_EMBEDDED_REG                  (C_USE_EMBEDDED_REG),
+    .C_EN_SAFETY_CKT                     (C_EN_SAFETY_CKT),            
+    .C_USE_FWFT_DATA_COUNT               (C_USE_FWFT_DATA_COUNT),         
+    .C_VALID_LOW                         (C_VALID_LOW),                   
+    .C_WR_ACK_LOW                        (C_WR_ACK_LOW),                  
+    .C_WR_DATA_COUNT_WIDTH               (C_WR_DATA_COUNT_WIDTH),         
+    .C_WR_DEPTH                          (C_WR_DEPTH),                    
+    .C_WR_PNTR_WIDTH                     (C_WR_PNTR_WIDTH),               
+    .C_USE_ECC                           (C_USE_ECC),                     
+    .C_ENABLE_RST_SYNC                   (C_ENABLE_RST_SYNC),             
+    .C_ERROR_INJECTION_TYPE              (C_ERROR_INJECTION_TYPE),
+    .C_FIFO_TYPE                         (C_FIFO_TYPE)                     
+  )
+  gen_ss
+  (
+    .SAFETY_CKT_WR_RST        (safety_ckt_wr_rst),
+    .CLK                      (CLK),
+    .RST                      (rst_i),
+    .SRST                     (srst_delayed),
+    .RST_FULL_GEN             (rst_full_gen_i),
+    .RST_FULL_FF              (rst_full_ff_i),
+    .DIN                      (din_delayed),
+    .WR_EN                    (wr_en_delayed),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .RD_EN_USER               (rd_en_delayed),
+    .USER_EMPTY_FB            (empty_fb),
+    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),
+    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
+    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
+    .PROG_FULL_THRESH         (prog_full_thresh_delayed),
+    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),
+    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),
+    .INJECTSBITERR            (inject_sbit_err),
+    .INJECTDBITERR            (inject_dbit_err),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .EMPTY_FB                 (fifo_empty_fb),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),
+    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
+    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),
+    .WR_RST_BUSY              (wr_rst_busy),
+    .RD_RST_BUSY              (rd_rst_busy),
+    .SBITERR                  (sbiterr_fifo_out),
+    .DBITERR                  (dbiterr_fifo_out)
+   );
+end
+1 : begin : block1
+  //Independent Clocks Behavioral Model
+  fifo_generator_v13_1_3_bhv_ver_as
+  #(
+    .C_FAMILY                          (C_FAMILY),
+    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),
+    .C_DIN_WIDTH                       (C_DIN_WIDTH),
+    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),
+    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),
+    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),
+    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),
+    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),
+    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),
+    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),
+    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),
+    .C_HAS_RST                         (C_HAS_RST),
+    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),
+    .C_HAS_VALID                       (C_HAS_VALID),
+    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),
+    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),
+    .C_IMPLEMENTATION_TYPE             'b'(C_IMPLEMENTATION_TYPE),
+    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),
+    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),
+    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),
+    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),
+    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),
+    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),
+    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),
+    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),
+    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),
+    .C_RD_DEPTH                        (C_RD_DEPTH),
+    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),
+    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),
+    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),
+    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),
+    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT), 
+    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),
+    .C_VALID_LOW                       (C_VALID_LOW),
+    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),
+    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),
+    .C_WR_DEPTH                        (C_WR_DEPTH),
+    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),
+    .C_USE_ECC                         (C_USE_ECC),
+    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),
+    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),
+    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)
+  )
+  gen_as
+  (
+    .SAFETY_CKT_WR_RST        (safety_ckt_wr_rst),
+    .SAFETY_CKT_RD_RST        (safety_ckt_rd_rst),
+    .WR_CLK                   (WR_CLK),
+    .RD_CLK                   (RD_CLK),
+    .RST                      (rst_i),
+    .RST_FULL_GEN             (rst_full_gen_i),
+    .RST_FULL_FF              (rst_full_ff_i),
+    .WR_RST                   (wr_rst_i),
+    .RD_RST                   (rd_rst_i),
+    .DIN                      (din_delayed),
+    .WR_EN                    (wr_en_delayed),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .RD_EN_USER               (rd_en_delayed),
+    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),
+    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
+    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
+    .PROG_FULL_THRESH         (prog_full_thresh_delayed),
+    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),
+    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),
+    .INJECTSBITERR            (inject_sbit_err),
+    .INJECTDBITERR            (inject_dbit_err),
+    .USER_EMPTY_FB            (EMPTY_P0_OUT),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .EMPTY_FB                 (fifo_empty_fb),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
+    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),
+    .SBITERR                  (sbiterr_fifo_out),
+    .fab_read_data_valid_i    (w_fab_read_data_valid_i),
+    .read_data_valid_i        (w_read_data_valid_i),
+    .ram_valid_i              (w_ram_valid_i),
+    .DBITERR                  (dbiterr_fifo_out)
+   );
+end
+
+2 : begin : ll_afifo_inst
+  fifo_generator_v13_1_3_beh_ver_ll_afifo
+  #(
+    .C_DIN_WIDTH                    (C_DIN_WIDTH),
+    .C_DOUT_RST_VAL                 (C_DOUT_RST_VAL),
+    .C_DOUT_WIDTH                   (C_DOUT_WIDTH),
+    .C_FULL_FLAGS_RST_VAL           (C_FULL_FLAGS_RST_VAL),
+    .C_HAS_RD_DATA_COUNT            (C_HAS_RD_DATA_COUNT),
+    .C_HAS_WR_DATA_COUNT            (C_HAS_WR_DATA_COUNT),
+    .C_RD_DEPTH                     (C_RD_DEPTH),
+    .C_RD_PNTR_WIDTH                (C_RD_PNTR_WIDTH),
+    .C_USE_DOUT_RST                 (C_USE_DOUT_RST),
+    .C_WR_DATA_COUNT_WIDTH          (C_WR_DATA_COUNT_WIDTH),
+    .C_WR_DEPTH                     (C_WR_DEPTH),
+    .C_WR_PNTR_WIDTH                (C_WR_PNTR_WIDTH),
+    .C_FIFO_TYPE                    (C_FIFO_TYPE)
+   )
+  gen_ll_afifo
+  (
+    .DIN                        (din_delayed),
+    .RD_CLK                     (RD_CLK),
+    .RD_EN                      (rd_en_delayed),
+    .WR_RST                     (wr_rst_i),
+    .RD_RST                     (rd_rst_i),
+    .WR_CLK                     (WR_CLK),
+    .WR_EN                      (wr_en_delayed),
+    .DOUT                       (DOUT),
+    .EMPTY                      (EMPTY),
+    .FULL                       (FULL)
+  );
+end
+default : begin : block1
+  //Independent Clocks Behavioral Model
+  fifo_generator_v13_1_3_bhv_ver_as
+  #(
+    .C_FAMILY                          (C_FAMILY),
+    .C_DATA_COUNT_WIDTH                (C_DATA_COUNT_WIDTH),
+    .C_DIN_WIDTH                       (C_DIN_WIDTH),
+    .C_DOUT_RST_VAL                    (C_DOUT_RST_VAL),
+    .C_DOUT_WIDTH                      (C_DOUT_WIDTH),
+    .C_FULL_FLAGS_RST_VAL              (C_FULL_FLAGS_RST_VAL),
+    .C_HAS_ALMOST_EMPTY                (C_HAS_ALMOST_EMPTY),
+    .C_HAS_ALMOST_FULL                 (C_HAS_ALMOST_FULL),
+    .C_HAS_DATA_COUNT                  (C_HAS_DATA_COUNT),
+    .C_HAS_OVERFLOW                    (C_HAS_OVERFLOW),
+    .C_HAS_RD_DATA_COUNT               (C_HAS_RD_DATA_COUNT),
+    .C_HAS_RST                         (C_HAS_RST),
+    .C_HAS_UNDERFLOW                   (C_HAS_UNDERFLOW),
+    .C_HAS_VALID                       (C_HAS_VALID),
+    .C_HAS_WR_ACK                      (C_HAS_WR_ACK),
+    .C_HAS_WR_DATA_COUNT               (C_HAS_WR_DATA_COUNT),
+    .C_IMPLEMENTATION_TYPE             (C_IMPLEMENTATION_TYPE),
+    .C_MEMORY_TYPE                     (C_MEMORY_TYPE),
+    .C_OVERFLOW_LOW                    (C_OVERFLOW_LOW),
+    .C_PRELOAD_LATENCY                 (C_PRELOAD_LATENCY),
+    .C_PRELOAD_REGS                    (C_PRELOAD_REGS),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL    (C_PROG_EMPTY_THRESH_ASSERT_VAL),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL    (C_PROG_EMPTY_THRESH_NEGATE_VAL),
+    .C_PROG_EMPTY_TYPE                 (C_PROG_EMPTY_TYPE),
+    .C_PROG_FULL_THRESH_ASSERT_VAL     (C_PROG_FULL_THRESH_ASSERT_VAL),
+    .C_PROG_FULL_THRESH_NEGATE_VAL     (C_PROG_FULL_THRESH_NEGATE_VAL),
+    .C_PROG_FULL_TYPE                  (C_PROG_FULL_TYPE),
+    .C_RD_DATA_COUNT_WIDTH             (C_RD_DATA_COUNT_WIDTH),
+    .C_RD_DEPTH                        (C_RD_DEPTH),
+    .C_RD_PNTR_WIDTH                   (C_RD_PNTR_WIDTH),
+    .C_UNDERFLOW_LOW                   (C_UNDERFLOW_LOW),
+    .C_USE_DOUT_RST                    (C_USE_DOUT_RST),
+    .C_USE_EMBEDDED_REG                (C_USE_EMBEDDED_REG),
+    .C_EN_SAFETY_CKT                   (C_EN_SAFETY_CKT),
+    .C_USE_FWFT_DATA_COUNT             (C_USE_FWFT_DATA_COUNT),
+    .C_VALID_LOW                       (C_VALID_LOW),
+    .C_WR_ACK_LOW                      (C_WR_ACK_LOW),
+    .C_WR_DATA_COUNT_WIDTH             (C_WR_DATA_COUNT_WIDTH),
+    .C_WR_DEPTH                        (C_WR_DEPTH),
+    .C_WR_PNTR_WIDTH                   (C_WR_PNTR_WIDTH),
+    .C_USE_ECC                         (C_USE_ECC),
+    .C_SYNCHRONIZER_STAGE              (C_SYNCHRONIZER_STAGE),
+    .C_ENABLE_RST_SYNC                 (C_ENABLE_RST_SYNC),
+    .C_ERROR_INJECTION_TYPE            (C_ERROR_INJECTION_TYPE)
+  )
+  gen_as
+  (
+    .SAFETY_CKT_WR_RST        (safety_ckt_wr_rst),
+    .SAFETY_CKT_RD_RST        (safety_ckt_rd_rst),
+    .WR_CLK                   (WR_CLK),
+    .RD_CLK                   (RD_CLK),
+    .RST                      (rst_i),
+    .RST_FULL_GEN             (rst_full_gen_i),
+    .RST_FULL_FF              (rst_full_ff_i),
+    .WR_RST                   (wr_rst_i),
+    .RD_RST                   (rd_rst_i),
+    .DIN                      (din_delayed),
+    .WR_EN                    (wr_en_delayed),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .RD_EN_USER               (rd_en_delayed),
+    .PROG_EMPTY_THRESH        (prog_empty_thresh_delayed),
+    .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
+    .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
+    .PROG_FULL_THRESH         (prog_full_thresh_delayed),
+    .PROG_FULL_THRESH_ASSERT  (prog_full_thresh_assert_delayed),
+    .PROG_FULL_THRESH_NEGATE  (prog_full_thresh_negate_delayed),
+    .INJECTSBITERR            (inject_sbit_err),
+    .INJECTDBITERR            (inject_dbit_err),
+    .USER_EMPTY_FB            (EMPTY_P0_OUT),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .EMPTY_FB                 (fifo_empty_fb),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
+    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT),
+    .SBITERR                  (sbiterr_fifo_out),
+    .DBITERR                  (dbiterr_fifo_out)
+   );
+end
+
+endcase
+endgenerate
+
+
+   //**************************************************************************
+   // Connect Internal Signals
+   //   (Signals labeled internal_*)
+   //  In the normal case, these signals tie directly to the FIFO\'s inputs and
+   //    outputs.
+   //  In the case of Preload Latency 0 or 1, there are intermediate
+   //    signals between the internal FIFO and the preload logic.
+   //**************************************************************************
+   
+   
+   //***********************************************
+   // If First-Word Fall-Through, instantiate
+   // the preload0 (FWFT) module
+   //***********************************************
+   wire                        rd_en_to_fwft_fifo;
+   wire                        sbiterr_fwft;
+   wire                        dbiterr_fwft;
+   wire [C_DOUT_WIDTH-1:0]     dout_fwft;
+   wire                        empty_fwft;
+   wire                        rd_en_fifo_in;
+   wire                        stage2_reg_en_i;
+   wire [1:0]                  valid_stages_i;
+   wire                        rst_fwft;
+   //wire                        empty_p0_out;
+   reg  [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = \'b1;
+
+   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
+   localparam IS_PKT_FIFO      = (C_FIFO_TYPE == 1) ? 1 : 0;
+   localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
+   assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1\'b0;
+
+   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
+
+
+         fifo_generator_v13_1_3_bhv_ver_preload0
+           #(
+             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),
+             .C_DOUT_WIDTH        (C_DOUT_WIDTH),
+             .C_HAS_RST           (C_HAS_RST),
+             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),
+             .C_HAS_SRST          (C_HAS_SRST),
+             .C_USE_DOUT_RST      (C_USE_DOUT_RST),
+             .C_USE_EMBEDDED_REG  (C_USE_EMBEDDED_REG),
+             .C_USE_ECC           (C_USE_ECC),
+             .C_USERVALID_LOW     (C_VALID_LOW),
+             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
+             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),
+             .C_MEMORY_TYPE       (C_MEMORY_TYPE),
+             .C_FIFO_TYPE         (C_FIFO_TYPE)
+             )
+             fgpl0
+               (
+                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
+                .RD_CLK           (RD_CLK_P0_IN),
+                .RD_RST           (RST_P0_IN),
+                .SRST             (srst_delayed),
+                .WR_RST_BUSY      (wr_rst_busy),
+                .RD_RST_BUSY      (rd_rst_busy),
+                .RD_EN            (RD_EN_P0_IN),
+                .FIFOEMPTY        (EMPTY_P0_IN),
+                .FIFODATA         (DATA_P0_IN),
+                .FIFOSBITERR      (sbiterr_fifo_out),
+                .FIFODBITERR      (dbiterr_fifo_out),
+                // Output
+                .USERDATA         (dout_fwft),
+                .USERVALID        (VALID_P0_OUT),
+                .USEREMPTY        (empty_fwft),
+                .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),
+                .USERUNDERFLOW    (UNDERFLOW_P0_OUT),
+                .RAMVALID         (),
+                .FIFORDEN         (rd_en_fifo_in),
+                .USERSBITERR      (sbiterr_fwft),
+                .USERDBITERR      (dbiterr_fwft),
+                .STAGE2_REG_EN    (stage2_reg_en_i),
+                .fab_read_data_valid_i_o    (w_fab_read_data_valid_i),
+                .read_data_valid_i_o        (w_read_data_valid_i),
+                .ram_valid_i_o              (w_ram_valid_i),
+                .VALID_STAGES                (valid_stages_i)
+                );
+
+         
+         //***********************************************
+         // Connect inputs to preload (FWFT) module
+         //***********************************************
+         //Connect the RD_CLK of the Preload (FWFT) module to CLK if we 
+         // have a common-clock FIFO, or RD_CLK if we have an 
+         // independent clock FIFO
+         assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
+         assign RST_P0_IN          = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
+         assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
+         assign EMPTY_P0_IN        = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
+         assign DATA_P0_IN         = DOUT_FIFO_OUT;
+         
+         //***********************************************
+         // Connect outputs from preload (FWFT) module
+         //***********************************************
+         assign VALID              = VALID_P0_OUT ;
+         assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;
+         assign UNDERFLOW          = UNDERFLOW_P0_OUT ;
+         
+         assign RD_EN_FIFO_IN      = rd_en_fifo_in;
+         
+         
+         //***********************************************
+         // Create DATA_COUNT from First-Word Fall-Through
+         // data count
+         //***********************************************
+         assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
+           (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : 
+           DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];  
+         
+         //***********************************************
+         // Create DATA_COUNT from First-Word Fall-Through
+         // data count
+         //***********************************************
+         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
+            if (RST_P0_IN) begin
+               EMPTY_P0_OUT_Q       <= 1;
+               ALMOSTEMPTY_P0_OUT_Q <= 1;
+            end else begin
+               EMPTY_P0_OUT_Q       <= #`TCQ empty_p0_out;
+//               EMPTY_P0_OUT_Q       <= #`TCQ EMPTY_FIFO_OUT;
+               ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
+            end
+         end //always
+         
+         
+         //***********************************************
+         // logic for common-clock data count when FWFT is selected
+         //***********************************************
+         initial begin
+            SS_FWFT_RD = 1\'b0;
+            DATA_COUNT_FWFT = 0 ;
+            SS_FWFT_WR   = 1\'b0 ;
+         end //initial
+         
+         
+         //***********************************************
+         // common-clock data count is implemented as an
+         // up-down counter. SS_FWFT_WR and SS_FWFT_RD
+         // are the up/down enables for the counter.
+         //***********************************************
+         always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
+            if (C_VALID_LOW == 1) begin
+              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
+            end else begin
+              SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
+            end
+            SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT))  ;
+         end 
+
+         //***********************************************
+         // common-clock data count is implemented as an
+         // up-down counter for FWFT. This always block 
+         // calculates the counter.
+         //***********************************************
+         always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
+            if (RST_P0_IN) begin
+               DATA_COUNT_FWFT      <= 0;
+            end else begin
+               //if (srst_delayed && (C_HAS_SRST == 1) ) begin
+               if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
+                  DATA_COUNT_FWFT      <= #`TCQ 0;
+               end else begin
+                  case ( {SS_FWFT_WR, SS_FWFT_RD})
+                    2\'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
+                    2\'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
+                    2\'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
+                    2\'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
+                  endcase  
+               end //if SRST
+            end //IF RST
+         end //always
+
+      end endgenerate // : block2
+
+    // AXI Streaming Packet FIFO
+    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count       = 0;
+    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count       = 0;
+    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_plus1 = 0;
+    reg  [C_RD_PNTR_WIDTH-1:0]  rd_pkt_count_reg   = 0;
+    reg                         partial_packet     = 0;
+    reg                         stage1_eop_d1      = 0;
+    reg                         rd_en_fifo_in_d1   = 0;
+    reg                         eop_at_stage2      = 0;
+    reg                         ram_pkt_empty      = 0;
+    reg                         ram_pkt_empty_d1   = 0;
+
+    wire [C_DOUT_WIDTH-1:0]     dout_p0_out;
+    wire                        packet_empty_wr;
+    wire                        wr_rst_fwft_pkt_fifo;
+    wire                        dummy_wr_eop;
+    wire                        ram_wr_en_pkt_fifo;
+    wire                        wr_eop;
+    wire                        ram_rd_en_compare;
+    wire                        stage1_eop;
+    wire                        pkt_ready_to_read;
+    wire                        rd_en_2_stage2;
+
+    // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
+    // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
+    // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
+    // write packet count
+    generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
+       always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin 
+          if (wr_rst_fwft_pkt_fifo)
+             partial_packet   <= 1\'b0;
+          else begin
+             if (srst_delayed | wr_rst_busy | rd_rst_busy)
+                partial_packet <= #`TCQ 1\'b0;
+             else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
+                partial_packet <= #`TCQ 1\'b1;
+             else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
+                partial_packet <= #`TCQ 1\'b0;
+          end
+        end
+    end endgenerate // gdummy_wr_eop
+
+    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
+      assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1\'b0;
+      assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
+      assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
+  
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+        if (rst_fwft) begin
+          stage1_eop_d1    <= 1\'b0;
+          rd_en_fifo_in_d1 <= 1\'b0;
+        end else begin
+          if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
+            stage1_eop_d1    <= #`TCQ 1\'b0;
+            rd_en_fifo_in_d1 <= #`TCQ 1\'b0;
+          end else begin
+            stage1_eop_d1    <= #`TCQ stage1_eop;
+            rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
+          end
+        end
+      end
+      assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
+      assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
+      assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
+      assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
+
+
+         fifo_generator_v13_1_3_bhv_ver_preload0
+           #(
+             .C_DOUT_RST_VAL      (C_DOUT_RST_VAL),
+             .C_DOUT_WIDTH        (C_DOUT_WIDTH),
+             .C_HAS_RST           (C_HAS_RST),
+             .C_HAS_SRST          (C_HAS_SRST),
+             .C_USE_DOUT_RST      (C_USE_DOUT_RST),
+             .C_USE_ECC           (C_USE_ECC),
+             .C_USERVALID_LOW     (C_VALID_LOW),
+             .C_EN_SAFETY_CKT     (C_EN_SAFETY_CKT),
+             .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
+             .C_ENABLE_RST_SYNC   (C_ENABLE_RST_SYNC),
+             .C_MEMORY_TYPE       (C_MEMORY_TYPE),
+             .C_FIFO_TYPE         (2) // Enable low latency fwft logic
+             )
+         pkt_fifo_fwft
+               (
+                .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
+                .RD_CLK           (RD_CLK_P0_IN),
+                .RD_RST           (rst_fwft),
+                .SRST             (srst_delayed),
+                .WR_RST_BUSY      (wr_rst_busy),
+                .RD_RST_BUSY      (rd_rst_busy),
+                .RD_EN            (rd_en_delayed),
+                .FIFOEMPTY        (pkt_ready_to_read),
+                .FIFODATA         (dout_fwft),
+                .FIFOSBITERR      (sbiterr_fwft),
+                .FIFODBITERR      (dbiterr_fwft),
+                // Output
+                .USERDATA         (dout_p0_out),
+                .USERVALID        (),
+                .USEREMPTY        (empty_p0_out),
+                .USERALMOSTEMPTY  (),
+                .USERUNDERFLOW    (),
+                .RAMVALID         (),
+                .FIFORDEN         (rd_en_2_stage2),
+                .USERSBITERR      (SBITERR),
+                .USERDBITERR      (DBITERR),
+                .STAGE2_REG_EN    (),
+                .VALID_STAGES     ()
+                );
+
+      assign pkt_ready_to_read  = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
+      assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
+
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+        if (rst_fwft)
+          eop_at_stage2 <= 1\'b0;
+        else if (stage2_reg_en_i)
+          eop_at_stage2 <= #`TCQ stage1_eop;
+      end
+
+      //---------------------------------------------------------------------------
+      // Write and Read Packet Count
+      //---------------------------------------------------------------------------
+      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin 
+         if (wr_rst_fwft_pkt_fifo)
+            wr_pkt_count  <= 0;
+         else if (srst_delayed  | wr_rst_busy | rd_rst_busy)
+            wr_pkt_count  <= #`TCQ 0;
+         else if (wr_eop)
+            wr_pkt_count  <= #`TCQ wr_pkt_count + 1;
+      end
+    
+    end endgenerate // gpkt_fifo_fwft
+
+    assign DOUT               = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
+    assign EMPTY              = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
+
+    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft) begin
+            rd_pkt_count       <= 0;
+            rd_pkt_count_plus1 <= 1;
+         end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
+            rd_pkt_count       <= #`TCQ 0;
+            rd_pkt_count_plus1 <= #`TCQ 1;
+         end else if (stage2_reg_en_i && stage1_eop) begin
+            rd_pkt_count       <= #`TCQ rd_pkt_count + 1;
+            rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
+         end
+      end
+
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft) begin
+            ram_pkt_empty    <= 1\'b1;
+            ram_pkt_empty_d1 <= 1\'b1;
+         end else if (SRST | wr_rst_busy | rd_rst_busy) begin
+            ram_pkt_empty    <= #`TCQ 1\'b1;
+            ram_pkt_empty_d1 <= #`TCQ 1\'b1;
+         end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
+            ram_pkt_empty    <= #`TCQ 1\'b0;
+            ram_pkt_empty_d1 <= #`TCQ 1\'b0;
+         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
+            ram_pkt_empty    <= #`TCQ 1\'b1;
+         end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
+            ram_pkt_empty_d1 <= #`TCQ 1\'b1;
+         end
+      end
+    end endgenerate //grss_pkt_cnt
+    
+    localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
+    reg  [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
+    reg  [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_b2g = 0;
+    wire [C_WR_PNTR_WIDTH-1:0]  wr_pkt_count_rd;
+    generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
+      // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
+      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
+         if (wr_rst_fwft_pkt_fifo)
+            wr_pkt_count_b2g  <= 0;
+         else
+            wr_pkt_count_b2g  <= #`TCQ wr_pkt_count;
+      end
+
+      // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft)
+            wr_pkt_count_q       <= 0;
+         else
+            wr_pkt_count_q       <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
+      end
+
+      always @* begin
+        if (stage1_eop)
+           rd_pkt_count    <= rd_pkt_count_reg + 1;
+        else
+           rd_pkt_count    <= rd_pkt_count_reg;
+      end
+
+      assign wr_pkt_count_rd    = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
+
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft)
+            rd_pkt_count_reg       <= 0;
+         else if (rd_en_fifo_in)
+            rd_pkt_count_reg       <= #`TCQ rd_pkt_count;
+      end
+
+      always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin 
+         if (rst_fwft) begin
+            ram_pkt_empty    <= 1\'b1;
+            ram_pkt_empty_d1 <= 1\'b1;
+         end else if (rd_pkt_count != wr_pkt_count_rd) begin
+            ram_pkt_empty    <= #`TCQ 1\'b0;
+            ram_pkt_empty_d1 <= #`TCQ 1\'b0;
+         end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
+            ram_pkt_empty    <= #`TCQ 1\'b1;
+         end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
+            ram_pkt_empty_d1 <= #`TCQ 1\'b1;
+         end
+      end
+
+      // Synchronize the empty in write domain
+      always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
+         if (wr_rst_fwft_pkt_fifo)
+            pkt_empty_sync  <= \'b1;
+         else
+            pkt_empty_sync  <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
+      end
+
+    end endgenerate //gras_pkt_cnt
+
+   generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
+
+     //***********************************************
+     // If NOT First-Word Fall-Through, wire the outputs
+     // of the internal _ss or _as FIFO directly to the
+     // output, and do not instantiate the preload0
+     // module.
+     //***********************************************
+
+     assign RD_CLK_P0_IN       = 0;
+     assign RST_P0_IN          = 0;
+     assign RD_EN_P0_IN        = 0;
+
+     assign RD_EN_FIFO_IN      = rd_en_delayed;
+
+     assign DOUT               = DOUT_FIFO_OUT;
+     assign DATA_P0_IN         = 0;
+     assign VALID              = VALID_FIFO_OUT;
+     assign EMPTY              = EMPTY_FIFO_OUT;
+     assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;
+     assign EMPTY_P0_IN        = 0;
+     assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;
+     assign DATA_COUNT         = DATA_COUNT_FIFO_OUT;
+     assign SBITERR            = sbiterr_fifo_out;
+     assign DBITERR            = dbiterr_fifo_out;
+
+   end endgenerate // STD_FIFO
+
+   generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
+     assign empty_p0_out       = empty_fwft;
+     assign SBITERR            = sbiterr_fwft;
+     assign DBITERR            = dbiterr_fwft;
+     assign DOUT               = dout_fwft;
+     assign RD_EN_P0_IN        = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
+
+   end endgenerate // NO_PKT_FIFO
+
+   //***********************************************
+   // Connect user flags to internal signals
+   //***********************************************
+   
+   //If we are using extra logic for the FWFT data count, then override the
+   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
+   //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
+   generate
+      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
+      if (C_COMMON_CLOCK == 0) begin : block_ic
+         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
+      end //block_ic
+      else begin
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+      end 
+      end //block3
+   endgenerate
+   
+   //If we are using extra logic for the FWFT data count, then override the
+   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
+   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
+   generate
+      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
+       if (C_COMMON_CLOCK == 0) begin : block_ic
+         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
+       end 
+       else begin
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+        end 
+      end //block30
+   endgenerate
+
+
+    
+   //If we are using extra logic for the FWFT data count, then override the
+   //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
+   //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
+   generate
+      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
+       if (C_COMMON_CLOCK == 0) begin : block_ic_both
+         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
+       end 
+       else begin
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+        end 
+      end //block30_both
+   endgenerate
+
+ generate
+      if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
+      if (C_COMMON_CLOCK == 0) begin : block_ic_both
+         assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
+      end //block_ic_both
+      else begin
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+      end 
+      end //block3_both
+   endgenerate
+
+
+   //If we are not using extra logic for the FWFT data count,
+   //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
+   //internal FIFO instance  
+   generate
+      if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
+         assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+      end
+   endgenerate
+
+   //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
+   //FIFO instance
+   generate
+      if (C_USE_FWFT_DATA_COUNT==1) begin : block4
+         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
+      end
+      else begin : block4
+         assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
+      end
+   endgenerate
+
+
+   //Connect other flags to the internal FIFO instance
+   assign       FULL        = FULL_FIFO_OUT;
+   assign       ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
+   assign       WR_ACK      = WR_ACK_FIFO_OUT;
+   assign       OVERFLOW    = OVERFLOW_FIFO_OUT;
+   assign       PROG_FULL   = PROG_FULL_FIFO_OUT;
+   assign       PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;
+
+
+  /**************************************************************************
+  * find_log2
+  *   Returns the \'log2\' value for the input value for the supported ratios
+  ***************************************************************************/
+  function integer find_log2;
+    input integer int_val;
+    integer i,j;
+    begin
+      i = 1;
+      j = 0;
+      for (i = 1; i < int_val; i = i*2) begin
+        j = j + 1;
+      end
+      find_log2 = j;
+    end
+  endfunction
+
+   // if an asynchronous FIFO has been selected, display a message that the FIFO
+   //   will not be cycle-accurate in simulation
+   initial begin
+      if (C_IMPLEMENTATION_TYPE == 2) begin
+         $display(""WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information."");
+      end else if (C_MEMORY_TYPE == 4) begin
+         $display(""FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado."");
+         $finish;
+      end
+
+      if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
+         $display(""FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH."");
+         $finish;
+      end
+
+      if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
+         $display(""FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH."");
+         $finish;
+      end
+
+      if (C_USE_ECC == 1) begin
+         if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
+            $display(""FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration."");
+            $finish;
+         end
+         if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
+            $display(""FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection."");
+            $finish;
+         end
+      end
+
+   end //initial
+
+  /**************************************************************************
+  * Internal reset logic
+  **************************************************************************/
+  assign wr_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
+  assign rd_rst_i         = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
+  assign rst_i            = C_HAS_RST ? rst_reg : 0;
+
+  wire rst_2_sync;
+  wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST; 
+  wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
+  wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
+  localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
+                               (C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
+  reg  [RST_SYNC_STAGES-1:0] wrst_reg    = {RST_SYNC_STAGES{1\'b0}};
+  reg  [RST_SYNC_STAGES-1:0] rrst_reg    = {RST_SYNC_STAGES{1\'b0}};
+  reg  [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1\'b0}};
+  reg  [RST_SYNC_STAGES-1:0] wrst_q      = {RST_SYNC_STAGES{1\'b0}};
+  reg  [RST_SYNC_STAGES-1:0] rrst_q      = {RST_SYNC_STAGES{1\'b0}};
+  reg  [RST_SYNC_STAGES-1:0] rrst_wr     = {RST_SYNC_STAGES{1\'b0}};
+  reg  [RST_SYNC_STAGES-1:0] wrst_ext    = {RST_SYNC_STAGES{1\'b0}};
+  reg  [1:0] wrst_cc  = {2{1\'b0}};
+  reg  [1:0] rrst_cc  = {2{1\'b0}};
+
+  generate 
+      if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
+         reg[1:0] rst_d1_safety                  =1;
+         reg[1:0] rst_d2_safety                  =1;
+         reg[1:0] rst_d3_safety                  =1;
+         reg[1:0] rst_d4_safety                  =1;
+         reg[1:0] rst_d5_safety                  =1;
+         reg[1:0] rst_d6_safety                  =1;
+         reg[1:0] rst_d7_safety                  =1;
+       always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
+             if (rst_2_sync_safety == 1\'b1) begin
+                 rst_d1_safety <= 1\'b1;
+                 rst_d2_safety <= 1\'b1;
+                 rst_d3_safety <= 1\'b1;
+                 rst_d4_safety <= 1\'b1;
+                 rst_d5_safety <= 1\'b1;
+                 rst_d6_safety <= 1\'b1;
+                 rst_d7_safety <= 1\'b1;
+              end
+              else begin
+                 rst_d1_safety <= #`TCQ 1\'b0;
+                 rst_d2_safety <= #`TCQ rst_d1_safety;
+                 rst_d3_safety <= #`TCQ rst_d2_safety;
+                 rst_d4_safety <= #`TCQ rst_d3_safety;
+                 rst_d5_safety <= #`TCQ rst_d4_safety;
+                 rst_d6_safety <= #`TCQ rst_d5_safety;
+                 rst_d7_safety <= #`TCQ rst_d6_safety;
+              end //if
+              end //prst
+        always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
+              if(rst_d7_safety == 1 && WR_EN == 1) begin 
+              $display(""WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.""); 
+              
+              end //if
+              end //always
+        end // grst_safety_ckt
+  endgenerate     
+     
+// if (C_EN_SAFET_CKT == 1)
+// assertion:the reset shud be atleast 3 cycles wide. 
+
+  generate
+    reg  safety_ckt_wr_rst_i  = 1\'b0;
+      if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
+        always @* begin
+          wr_rst_reg <= wr_rst_delayed;
+          rd_rst_reg <= rd_rst_delayed;
+          rst_reg    <= 1\'b0;
+          srst_reg    <= 1\'b0;
+        end
+        assign rst_2_sync  = wr_rst_delayed;
+        assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1\'b0;
+        assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1\'b0;
+        assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1\'b0;
+        assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1\'b0;
+      // end : gnrst_sync
+      end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
+        reg  fifo_wrst_done = 1\'b0;
+        reg  fifo_rrst_done = 1\'b0;
+        reg  sckt_wrst_i    = 1\'b0;
+        reg  sckt_wrst_i_q  = 1\'b0;
+        reg  rd_rst_active   = 1\'b0;
+        reg  rd_rst_middle   = 1\'b0;
+        reg  sckt_rd_rst_d1  = 1\'b0;
+        reg  [1:0] rst_delayed_ic_w = 2\'h0;
+        wire rst_delayed_ic_w_i;
+        reg  [1:0] rst_delayed_ic_r = 2\'h0;
+        wire rst_delayed_ic_r_i;
+        wire arst_sync_rst;
+        wire fifo_rst_done;
+        wire fifo_rst_active;
+        assign wr_rst_comb      = !wr_rst_asreg_d2 && wr_rst_asreg;
+        assign rd_rst_comb      = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
+        assign rst_2_sync       = rst_delayed_ic_w_i;
+        assign arst_sync_rst    = arst_sync_q[RST_SYNC_STAGES-1];
+        assign wr_rst_busy      = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1\'b0;
+        assign rd_rst_busy      = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1\'b0;
+        assign fifo_rst_done    = fifo_wrst_done & fifo_rrst_done;
+        assign fifo_rst_active  = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
+
+        always @(posedge WR_CLK or posedge rst_delayed) begin
+          if (rst_delayed == 1\'b1 && C_HAS_RST)
+            rst_delayed_ic_w <= 2\'b11;
+          else
+            rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1\'b0};
+        end
+        assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
+
+        always @(posedge RD_CLK or posedge rst_delayed) begin
+          if (rst_delayed == 1\'b1 && C_HAS_RST)
+            rst_delayed_ic_r <= 2\'b11;
+          else
+            rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1\'b0};
+        end
+        assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
+
+        always @(posedge WR_CLK) begin
+          sckt_wrst_i_q       <= #`TCQ sckt_wrst_i;
+          sckt_wr_rst_i_q     <= #`TCQ wr_rst_busy;
+          safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
+          if (arst_sync_rst && ~fifo_rst_active)
+            sckt_wrst_i <= #`TCQ 1\'b1;
+          else if (sckt_wrst_i && fifo_rst_done)
+              sckt_wrst_i <= #`TCQ 1\'b0;
+          else
+            sckt_wrst_i <= #`TCQ sckt_wrst_i;
+
+          if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
+            fifo_rrst_done <= #`TCQ 1\'b1;
+          else if (fifo_rst_done)
+            fifo_rrst_done <= #`TCQ 1\'b0;
+          else
+            fifo_rrst_done <= #`TCQ fifo_rrst_done;
+
+          if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
+            fifo_wrst_done <= #`TCQ 1\'b1;
+          else if (fifo_rst_done)
+            fifo_wrst_done <= #`TCQ 1\'b0;
+          else
+            fifo_wrst_done <= #`TCQ fifo_wrst_done;
+        end   
+
+        always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
+          if (rst_delayed_ic_w_i == 1\'b1) begin
+            wr_rst_asreg <= 1\'b1;
+          end else begin
+            if (wr_rst_asreg_d1 == 1\'b1) begin
+              wr_rst_asreg <= #`TCQ 1\'b0;
+            end else begin
+              wr_rst_asreg <= #`TCQ wr_rst_asreg;
+            end
+          end    
+        end   
+
+        always @(posedge WR_CLK or posedge rst_delayed) begin
+          if (rst_delayed == 1\'b1) begin
+            wr_rst_asreg <= 1\'b1;
+          end else begin
+            if (wr_rst_asreg_d1 == 1\'b1) begin
+              wr_rst_asreg <= #`TCQ 1\'b0;
+            end else begin
+              wr_rst_asreg <= #`TCQ wr_rst_asreg;
+            end
+          end    
+        end   
+
+        always @(posedge WR_CLK) begin
+          wrst_reg    <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
+          wrst_ext    <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
+          rrst_wr     <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
+          arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
+        end
+
+        assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
+        assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
+        assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1\'b0;
+
+        always @(posedge WR_CLK or posedge wr_rst_comb) begin
+          if (wr_rst_comb == 1\'b1) begin
+            wr_rst_reg <= 1\'b1;
+          end else begin
+            wr_rst_reg <= #`TCQ 1\'b0;
+          end    
+        end   
+
+        always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
+          if (rst_delayed_ic_r_i == 1\'b1) begin
+            rd_rst_asreg  <= 1\'b1;
+          end else begin
+            if (rd_rst_asreg_d1 == 1\'b1) begin
+              rd_rst_asreg <= #`TCQ 1\'b0;
+            end else begin
+              rd_rst_asreg <= #`TCQ rd_rst_asreg;
+            end
+          end    
+        end   
+
+        always @(posedge RD_CLK) begin
+          rrst_reg        <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
+          rrst_q          <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
+          rrst_cc         <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
+          sckt_rd_rst_d1  <= #`TCQ safety_ckt_rd_rst;
+          if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
+            rd_rst_active <= #`TCQ 1\'b1;
+            rd_rst_middle <= #`TCQ 1\'b1;
+          end else if (safety_ckt_rd_rst)
+            rd_rst_active <= #`TCQ 1\'b0;
+          else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
+            rd_rst_middle <= #`TCQ 1\'b0;
+        end
+        assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
+        assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
+        assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1\'b0;
+
+        always @(posedge RD_CLK or posedge rd_rst_comb) begin
+          if (rd_rst_comb == 1\'b1) begin
+            rd_rst_reg <= 1\'b1;
+          end else begin
+            rd_rst_reg <= #`TCQ 1\'b0;
+          end    
+        end   
+      // end : g7s_ic_rst
+      end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
+        reg  [1:0] rst_delayed_cc   = 2\'h0;
+        wire rst_delayed_cc_i;
+        assign rst_comb    = !rst_asreg_d2 && rst_asreg;     
+        assign rst_2_sync  = rst_delayed_cc_i;
+        assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1\'b0;
+        assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1\'b0;
+ 
+        always @(posedge CLK or posedge rst_delayed) begin
+          if (rst_delayed == 1\'b1)
+            rst_delayed_cc <= 2\'b11;
+          else
+            rst_delayed_cc <= #`TCQ {rst_delayed_cc,1\'b0};
+        end   
+        assign rst_delayed_cc_i = rst_delayed_cc[1];
+ 
+        always @(posedge CLK or posedge rst_delayed_cc_i) begin
+          if (rst_delayed_cc_i == 1\'b1) begin
+            rst_asreg <= 1\'b1;
+          end else begin
+            if (rst_asreg_d1 == 1\'b1) begin
+              rst_asreg <= #`TCQ 1\'b0;
+            end else begin
+              rst_asreg <= #`TCQ rst_asreg;
+            end
+          end    
+        end   
+        
+        always @(posedge CLK) begin
+          wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
+          wrst_cc  <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
+          sckt_wr_rst_i_q     <= #`TCQ wr_rst_busy;
+          safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
+          arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
+        end
+        assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
+        assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
+        assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1\'b0;
+        assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1\'b0;
+
+        always @(posedge CLK or posedge rst_comb) begin
+          if (rst_comb == 1\'b1) begin
+            rst_reg <= 1\'b1;
+          end else begin
+            rst_reg <= #`TCQ 1\'b0;
+          end    
+        end   
+      // end : g7s_cc_rst
+      end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
+        assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
+        assign rd_rst_busy = rst_reg;
+        assign rst_2_sync = srst_delayed;
+        always @* rst_full_ff_i  <= rst_reg;
+        always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
+        assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1\'b0;
+        assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1\'b0;
+
+        always @(posedge CLK) begin
+          rst_delayed_d1 <= #`TCQ srst_delayed;
+          rst_delayed_d2 <= #`TCQ rst_delayed_d1;
+          sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
+          if (rst_reg || rst_delayed_d2) begin
+            rst_active_i <= #`TCQ 1\'b1;
+          end else begin
+            rst_active_i <= #`TCQ rst_reg;
+          end    
+        end   
+        always @(posedge CLK) begin
+          if (~rst_reg && srst_delayed) begin
+             rst_reg <= #`TCQ 1\'b1;
+           end else if (rst_reg) begin
+             rst_reg <= #`TCQ 1\'b0;
+           end else begin
+             rst_reg <= #`TCQ rst_reg;
+           end    
+        end   
+      // end : g8s_cc_rst
+      end else begin 
+        assign wr_rst_busy = 1\'b0;
+        assign rd_rst_busy = 1\'b0;
+        assign safety_ckt_wr_rst = 1\'b0;
+        assign safety_ckt_rd_rst = 1\'b0;
+      end
+  endgenerate 
+
+  generate
+    if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
+    // RST_FULL_GEN replaces the reset falling edge detection used to de-assert
+    // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
+
+    // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
+    // PROG_FULL
+      reg rst_d1 = 1\'b0;
+      reg rst_d2 = 1\'b0;
+      reg rst_d3 = 1\'b0;
+      reg rst_d4 = 1\'b0;
+      reg rst_d5 = 1\'b0;
+
+      always @ (posedge rst_2_sync or posedge clk_2_sync) begin
+        if (rst_2_sync) begin
+          rst_d1         <= 1\'b1;
+          rst_d2         <= 1\'b1;
+          rst_d3         <= 1\'b1;
+          rst_d4         <= 1\'b1;
+        end else begin
+          if (srst_delayed) begin
+            rst_d1         <= #`TCQ 1\'b1;
+            rst_d2         <= #`TCQ 1\'b1;
+            rst_d3         <= #`TCQ 1\'b1;
+            rst_d4         <= #`TCQ 1\'b1;
+          end else begin
+            rst_d1         <= #`TCQ wr_rst_busy;
+            rst_d2         <= #`TCQ rst_d1;
+            rst_d3         <= #`TCQ rst_d2 | safety_ckt_wr_rst;
+            rst_d4         <= #`TCQ rst_d3;
+          end
+        end
+      end
+
+      always @* rst_full_ff_i  <= (C_HAS_SRST == 0) ? rst_d2 : 1\'b0 ;
+      always @* rst_full_gen_i <= rst_d3;
+
+    end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
+      always @* rst_full_ff_i  <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
+    end
+  endgenerate // grstd1
+
+endmodule //fifo_generator_v13_1_3_conv_ver
+
+
+module fifo_generator_v13_1_3_sync_stage
+  #(
+    parameter  C_WIDTH          = 10
+   )
+   (
+    input                     RST,
+    input                     CLK,
+    input       [C_WIDTH-1:0] DIN,
+    output reg  [C_WIDTH-1:0] DOUT = 0
+   );
+   always @ (posedge RST or posedge CLK) begin
+     if (RST)
+       DOUT <= 0;
+     else
+       DOUT <= #`TCQ DIN;
+   end
+endmodule // fifo_generator_v13_1_3_sync_stage
+
+/*******************************************************************************
+ * Declaration of Independent-Clocks FIFO Module
+ ******************************************************************************/
+module fifo_generator_v13_1_3_bhv_ver_as
+   
+  /***************************************************************************
+   * Declare user parameters and their defaults
+   ***************************************************************************/
+  #(
+    parameter  C_FAMILY                       = ""virtex7"",
+    parameter  C_DATA_COUNT_WIDTH             = 2,
+    parameter  C_DIN_WIDTH                    = 8,
+    parameter  C_DOUT_RST_VAL                 = """",
+    parameter  C_DOUT_WIDTH                   = 8,
+    parameter  C_FULL_FLAGS_RST_VAL           = 1,
+    parameter  C_HAS_ALMOST_EMPTY             = 0,
+    parameter  C_HAS_ALMOST_FULL              = 0,
+    parameter  C_HAS_DATA_COUNT               = 0,
+    parameter  C_HAS_OVERFLOW                 = 0,
+    parameter  C_HAS_RD_DATA_COUNT            = 0,
+    parameter  C_HAS_RST                      = 0,
+    parameter  C_HAS_UNDERFLOW                = 0,
+    parameter  C_HAS_VALID                    = 0,
+    parameter  C_HAS_WR_ACK                   = 0,
+    parameter  C_HAS_WR_DATA_COUNT            = 0,
+    parameter  C_IMPLEMENTATION_TYPE          = 0,
+    parameter  C_MEMORY_TYPE                  = 1,
+    parameter  C_OVERFLOW_LOW                 = 0,
+    parameter  C_PRELOAD_LATENCY              = 1,
+    parameter  C_PRELOAD_REGS                 = 0,
+    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
+    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
+    parameter  C_PROG_EMPTY_TYPE              = 0,
+    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,
+    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,
+    parameter  C_PROG_FULL_TYPE               = 0,
+    parameter  C_RD_DATA_COUNT_WIDTH          = 2,
+    parameter  C_RD_DEPTH                     = 256,
+    parameter  C_RD_PNTR_WIDTH                = 8,
+    parameter  C_UNDERFLOW_LOW                = 0,
+    parameter  C_USE_DOUT_RST                 = 0,
+    parameter  C_USE_EMBEDDED_REG             = 0,
+    parameter  C_EN_SAFETY_CKT                = 0,
+    parameter  C_USE_FWFT_DATA_COUNT          = 0,
+    parameter  C_VALID_LOW                    = 0,
+    parameter  C_WR_ACK_LOW                   = 0,
+    parameter  C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter  C_WR_DEPTH                     = 256,
+    parameter  C_WR_PNTR_WIDTH                = 8,
+    parameter  C_USE_ECC                      = 0, 
+    parameter  C_ENABLE_RST_SYNC              = 1,
+    parameter  C_ERROR_INJECTION_TYPE         = 0,
+    parameter  C_SYNCHRONIZER_STAGE           = 2 
+   )
+
+  /***************************************************************************
+   * Declare Input and Output Ports
+   ***************************************************************************/
+  (
+   input                                         SAFETY_CKT_WR_RST,
+   input                                         SAFETY_CKT_RD_RST,
+   input       [C_DIN_WIDTH-1:0]                 DIN,
+   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH,
+   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_ASSERT,
+   input       [C_RD_PNTR_WIDTH-1:0]             PROG_EMPTY_THRESH_NEGATE,
+   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH,
+   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_ASSERT,
+   input       [C_WR_PNTR_WIDTH-1:0]             PROG_FULL_THRESH_NEGATE,
+   input                                         RD_CLK,
+   input                                         RD_EN,
+   input                                         RD_EN_USER,
+   input                                         RST,
+   input                                         RST_FULL_GEN,
+   input                                         RST_FULL_FF,
+   input                                         WR_RST,
+   input                                         RD_RST,
+   input                                         WR_CLK,
+   input                                         WR_EN,
+   input                                         INJECTDBITERR,
+   input                                         INJECTSBITERR,
+   input                                         USER_EMPTY_FB,
+   input                                         fab_read_data_valid_i,
+   input                                         read_data_valid_i,
+   input                                         ram_valid_i,
+   output reg                                    ALMOST_EMPTY = 1\'b1,
+   output reg                                    ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
+   output      [C_DOUT_WIDTH-1:0]                DOUT,
+   output reg                                    EMPTY = 1\'b1,
+   output reg                                    EMPTY_FB = 1\'b1,
+   output reg                                    FULL = C_FULL_FLAGS_RST_VAL,
+   output                                        OVERFLOW,
+   output                                        PROG_EMPTY,
+   output                                        PROG_FULL,
+   output                                        VALID,
+   output      [C_RD_DATA_COUNT_WIDTH-1:0]       RD_DATA_COUNT,
+   output                                        UNDERFLOW,
+   output                                        WR_ACK,
+   output      [C_WR_DATA_COUNT_WIDTH-1:0]       WR_DATA_COUNT,
+   output                                        SBITERR,
+   output                                        DBITERR
+  );
+
+
+   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
+   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
+   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
+   
+  
+   /***************************************************************************
+    * Parameters used as constants
+    **************************************************************************/
+  localparam IS_8SERIES         = (C_FAMILY == ""virtexu"" || C_FAMILY == ""kintexu"" || C_FAMILY == ""artixu"" || C_FAMILY == ""virtexuplus"" || C_FAMILY == ""zynquplus"" || C_FAMILY == ""kintexuplus"") ? 1 : 0;
+   //When RST is present, set FULL reset value to \'1\'.
+   //If core has no RST, make sure FULL powers-on as \'0\'.
+   localparam C_DEPTH_RATIO_WR =  
+      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
+   localparam C_DEPTH_RATIO_RD =  
+      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
+   localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
+   localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
+
+   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC
+   //  -----------------|------------------|-----------------|---------------
+   //  1                | 8                | C_RD_PNTR_WIDTH | 2
+   //  1                | 4                | C_RD_PNTR_WIDTH | 2
+   //  1                | 2                | C_RD_PNTR_WIDTH | 2
+   //  1                | 1                | C_WR_PNTR_WIDTH | 2
+   //  2                | 1                | C_WR_PNTR_WIDTH | 4
+   //  4                | 1                | C_WR_PNTR_WIDTH | 8
+   //  8                | 1                | C_WR_PNTR_WIDTH | 16
+   
+   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
+   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
+
+   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
+   
+   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
+   
+   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
+   
+   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
+
+
+
+   /**************************************************************************
+    * FIFO Contents Trac'b'king and Data Count Calculations
+    *************************************************************************/
+   
+   // Memory which will be used to simulate a FIFO
+   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
+   // Local parameters used to determine whether to inject ECC error or not
+   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
+   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
+   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
+   localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
+   // Array that holds the error injection type (single/double bit error) on 
+   // a specific write operation, which is returned on read to corrupt the
+   // output data.
+   reg [1:0] ecc_err[C_WR_DEPTH-1:0];
+
+   //The amount of data stored in the FIFO at any time is given
+   // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
+   // domain.
+   //num_wr_bits is calculated by considering the total words in the FIFO,
+   // and the state of the read pointer (which may not have yet crossed clock
+   // domains.)
+   //num_rd_bits is calculated by considering the total words in the FIFO,
+   // and the state of the write pointer (which may not have yet crossed clock
+   // domains.)
+   reg [31:0]  num_wr_bits;
+   reg [31:0]  num_rd_bits;
+   reg [31:0]  next_num_wr_bits;
+   reg [31:0]  next_num_rd_bits;
+
+   //The write pointer - tracks write operations
+   // (Works opposite to core: wr_ptr is a DOWN counter)
+   reg  [31:0]                 wr_ptr;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;
+   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;
+   wire                        wr_rst_i = WR_RST;
+   reg                         wr_rst_d1      =0;
+
+   //The read pointer - tracks read operations
+   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
+   reg  [31:0]                 rd_ptr;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;
+   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;
+   wire                        rd_rst_i = RD_RST;
+   wire                        ram_rd_en;
+   wire                        empty_int;
+   wire                        almost_empty_int;
+   wire                        ram_wr_en;
+   wire                        full_int;
+   wire                        almost_full_int;
+   reg                         ram_rd_en_d1 = 1\'b0;
+   reg                         fab_rd_en_d1 = 1\'b0;
+
+
+
+   // Delayed ram_rd_en is needed only for STD Embedded register option
+   generate
+     if (C_PRELOAD_LATENCY == 2) begin : grd_d
+       always @ (posedge RD_CLK or posedge rd_rst_i) begin
+         if (rd_rst_i)
+           ram_rd_en_d1 <= 1\'b0;
+         else
+           ram_rd_en_d1 <= #`TCQ ram_rd_en;
+       end
+     end
+   endgenerate
+   
+    generate
+     if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
+       always @ (posedge RD_CLK or posedge rd_rst_i) begin
+         if (rd_rst_i)
+           ram_rd_en_d1 <= 1\'b0;
+         else
+           ram_rd_en_d1 <= #`TCQ ram_rd_en;
+           fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
+       end
+     end
+   endgenerate
+
+  
+
+   // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
+   generate
+     if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
+       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
+       assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
+     end else begin : rdl // Read depth lesser than or equal to write depth
+       assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+     end
+   endgenerate
+
+   // Generate Empty and Almost Empty
+  // ram_rd_en used to determine EMPTY should depend on the EMPTY.
+   assign ram_rd_en        = RD_EN & !EMPTY;
+   assign empty_int        = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1\'h1))));
+   assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1\'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2\'h2))));
+
+   // Register Empty and Almost Empty
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+       if (rd_rst_i) begin
+         EMPTY             <= 1\'b1;
+         ALMOST_EMPTY      <= 1\'b1;
+         rd_data_count_int <= {C_RD_PNTR_WIDTH{1\'b0}};
+       end else begin
+         rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1\'b0};
+
+         if (empty_int)
+           EMPTY           <= #`TCQ 1\'b1;
+         else
+           EMPTY           <= #`TCQ 1\'b0;
+
+         if (!EMPTY) begin
+           if (almost_empty_int)
+             ALMOST_EMPTY  <= #`TCQ 1\'b1;
+           else
+             ALMOST_EMPTY  <= #`TCQ 1\'b0;
+         end
+       end // rd_rst_i
+     end // always
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+       if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
+         EMPTY_FB     <= 1\'b1;
+       end else begin
+         if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
+           EMPTY_FB   <= #`TCQ 1\'b1;
+         else if (empty_int)
+           EMPTY_FB   <= #`TCQ 1\'b1;
+         else
+           EMPTY_FB   <= #`TCQ 1\'b0;
+       end // rd_rst_i
+     end // always
+
+   // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
+   generate
+     if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
+       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
+       assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
+     end else begin : wdl // Write depth lesser than or equal to read depth
+       assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
+     end
+   endgenerate
+
+  // Generate FULL and ALMOST_FULL
+  // ram_wr_en used to determine FULL should depend on the FULL.
+  assign ram_wr_en       = WR_EN & !FULL;
+  assign full_int        = ((adj_rd_pntr_wr == (wr_pntr+1\'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2\'h2))));
+  assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2\'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3\'h3))));
+
+   // Register FULL and ALMOST_FULL Empty
+   always @ (posedge WR_CLK or posedge RST_FULL_FF)
+     begin
+       if (RST_FULL_FF) begin
+         FULL             <= C_FULL_FLAGS_RST_VAL;
+         ALMOST_FULL      <= C_FULL_FLAGS_RST_VAL;
+       end else begin
+         if (full_int) begin
+           FULL           <= #`TCQ 1\'b1;
+         end else begin
+           FULL           <= #`TCQ 1\'b0;
+         end
+
+         if (RST_FULL_GEN) begin
+           ALMOST_FULL    <= #`TCQ 1\'b0;
+         end else if (!FULL) begin
+           if (almost_full_int)
+             ALMOST_FULL  <= #`TCQ 1\'b1;
+           else
+             ALMOST_FULL  <= #`TCQ 1\'b0;
+         end
+       end // wr_rst_i
+     end // always
+   always @ (posedge WR_CLK or posedge wr_rst_i)
+     begin
+       if (wr_rst_i) begin
+         wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1\'b0}};
+       end else begin
+         wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1\'b0};
+       end // wr_rst_i
+     end // always
+
+   // Determine which stage in FWFT registers are valid
+   reg stage1_valid = 0;
+   reg stage2_valid = 0;
+   generate
+     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
+       always @ (posedge RD_CLK or posedge rd_rst_i) begin
+         if (rd_rst_i) begin
+           stage1_valid     <= 0;
+           stage2_valid     <= 0;
+         end else begin
+
+           if (!stage1_valid && !stage2_valid) begin
+             if (!EMPTY)
+               stage1_valid    <= #`TCQ 1\'b1;
+             else
+               stage1_valid    <= #`TCQ 1\'b0;
+           end else if (stage1_valid && !stage2_valid) begin
+             if (EMPTY) begin
+               stage1_valid    <= #`TCQ 1\'b0;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1\'b1;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end
+           end else if (!stage1_valid && stage2_valid) begin
+             if (EMPTY && RD_EN_USER) begin
+               stage1_valid    <= #`TCQ 1\'b0;
+               stage2_valid    <= #`TCQ 1\'b0;
+             end else if (!EMPTY && RD_EN_USER) begin
+               stage1_valid    <= #`TCQ 1\'b1;
+               stage2_valid    <= #`TCQ 1\'b0;
+             end else if (!EMPTY && !RD_EN_USER) begin
+               stage1_valid    <= #`TCQ 1\'b1;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1\'b0;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end
+           end else if (stage1_valid && stage2_valid) begin
+             if (EMPTY && RD_EN_USER) begin
+               stage1_valid    <= #`TCQ 1\'b0;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1\'b1;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end
+           end else begin
+             stage1_valid    <= #`TCQ 1\'b0;
+             stage2_valid    <= #`TCQ 1\'b0;
+           end
+         end // rd_rst_i
+       end // always
+     end
+   endgenerate
+
+   //Pointers passed into opposite clock domain
+   reg [31:0]  wr_ptr_rdclk;
+   reg [31:0]  wr_ptr_rdclk_next;
+   reg [31:0]  rd_ptr_wrclk;
+   reg [31:0]  rd_ptr_wrclk_next;
+
+   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port
+   // (Do not include data in FWFT stages)
+   //Used to calculate PROG_EMPTY.
+   wire [31:0] num_read_words_pe = 
+     num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
+
+   //Amount of data stored in the FIFO scaled to the narrowest (deepest) port
+   // (Do not include data in FWFT stages)
+   //Used to calculate PROG_FULL.
+   wire [31:0] num_write_words_pf =
+     num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
+
+   /**************************
+    * Read Data Count
+    *************************/
+
+   reg [31:0] num_read_words_dc;
+   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
+   
+   always @(num_rd_bits) begin
+     if (C_USE_FWFT_DATA_COUNT) begin
+        
+        //If using extra logic for FWFT Data Counts, 
+        // then scale FIFO contents to read domain, 
+        // and add two read words for FWFT stages
+        //This value is only a temporary value and not used in the code.
+        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_read_words_sized_i = 
+          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
+        
+     end else begin
+        
+        //If not using extra logic for FWFT Data Counts, 
+        // then scale FIFO contents to read domain.
+        //This value is only a temporary value and not used in the code.
+        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_read_words_sized_i = 
+          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
+        
+     end //if (C_USE_FWFT_DATA_COUNT)
+   end //always
+
+   
+   /**************************
+    * Write Data Count
+    *************************/
+
+   reg [31:0] num_write_words_dc;
+   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
+   
+   always @(num_wr_bits) begin
+     if (C_USE_FWFT_DATA_COUNT) begin
+        
+        //Calculate the Data Count value for the number of write words, 
+        // when using First-Word Fall-Through with extra logic for Data 
+        // Counts. This takes into consideration the number of words that 
+        // are expected to be stored in the FWFT register stages (it always 
+        // assumes they are filled).
+        //This value is scaled to the Write Domain.
+        //The expression (((A-1)/B))+1 divides A/B, but takes the 
+        // ceiling of the result.
+        //When num_wr_bits==0, set the result manually to prevent 
+        // division errors.
+        //EXTRA_WORDS_DC is the number of words added to write_words 
+        // due to FWFT.
+        //This value is only a temporary value and not used in the code.
+        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
+        
+        //Trim the write words for use with WR_DATA_COUNT
+        num_write_words_sized_i = 
+          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
+        
+     end else begin
+        
+        //Calculate the Data Count value for the number of write words, when NOT
+        // using First-Word Fall-Through with extra logic for Data Counts. This 
+        // calculates only the number of words in the internal FIFO.
+        //The expression (((A-1)/B))+1 divides A/B, but takes the 
+        // ceiling of the result.
+        //This value is scaled to the Write Domain.
+        //When num_wr_bits==0, set the result manually to prevent 
+        // division errors.
+        //This value is only a temporary value and not used in the code.
+        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_write_words_sized_i = 
+          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
+        
+     end //if (C_USE_FWFT_DATA_COUNT)
+   end //always
+
+    
+    
+   /***************************************************************************
+    * Internal registers and wires
+    **************************************************************************/
+
+   //Temporary signals used for calculating the model\'s outputs. These
+   //are only used in the assign statements immediately following wire,
+   //parameter, and function declarations.
+   wire [C_DOUT_WIDTH-1:0] ideal_dout_out;      
+   wire valid_i;
+   wire valid_out1;
+   wire valid_out2;
+   wire valid_out;  
+   wire underflow_i;
+
+   //Ideal FIFO signals. These are the raw output of the behavioral model,
+   //which behaves like an ideal FIFO.
+   reg [1:0]               err_type                 = 0;
+   reg [1:0]               err_type_d1              = 0;
+   reg [1:0]               err_type_both              = 0;
+   reg [C_DOUT_WIDTH-1:0]  ideal_dout               = 0;
+   reg [C_DOUT_WIDTH-1:0]  ideal_dout_d1            = 0;
+   reg [C_DOUT_WIDTH-1:0]  ideal_dout_both            = 0;
+   reg                     ideal_wr_ack             = 0;
+   reg                     ideal_valid              = 0;
+   reg                     ideal_overflow           = C_OVERFLOW_LOW;
+   reg                     ideal_underflow          = C_UNDERFLOW_LOW;
+   reg                     ideal_prog_full          = 0;
+   reg                     ideal_prog_empty         = 1;
+   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
+   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
+
+   //Assorted reg values for delayed versions of signals   
+   reg         valid_d1     = 0;
+   reg         valid_d2     = 0; 
+   
+   //user specified value for reseting the size of the fifo
+   reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;
+   
+   //temporary registers for WR_RESPONSE_LATENCY feature
+   
+   integer                           tmp_wr_listsize;
+   integer                           tmp_rd_listsize;
+   
+   //Signal for registered version of prog full and empty
+   
+   //Threshold values for Programmable Flags
+   integer                           prog_empty_actual_thresh_assert;
+   integer                           prog_empty_actual_thresh_negate;
+   integer                           prog_full_actual_thresh_assert;
+   integer                           prog_full_actual_thresh_negate;
+   
+
+  /****************************************************************************
+   * Function Declarations
+   ***************************************************************************/
+
+  /**************************************************************************
+   * write_fifo
+   *   This task writes a word to the FIFO memory and updates the 
+   * write pointer.
+   *   FIFO size is relative to write domain.
+  ***************************************************************************/
+  task write_fifo;
+    begin
+      memory[wr_ptr]     <= DIN;
+      wr_pntr <= #`TCQ wr_pntr + 1;
+      // Store the type of error injection (double/single) on write
+      case (C_ERROR_INJECTION_TYPE)
+        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};
+        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1\'b0};
+        1:       ecc_err[wr_ptr]    <= {1\'b0,INJECTSBITERR};
+        default: ecc_err[wr_ptr]    <= 0;
+      endcase
+      // (Works opposite to core: wr_ptr is a DOWN counter)
+      if (wr_ptr == 0) begin
+        wr_ptr          <= C_WR_DEPTH - 1;
+      end else begin
+        wr_ptr          <= wr_ptr - 1;
+      end
+    end
+  endtask // write_fifo
+
+  /**************************************************************************
+   * read_fifo
+   *   This task reads a word from the FIFO memory and updates the read 
+   * pointer. It\'s output is the ideal_dout bus.
+   *   FIFO size is relative to write domain.
+   ***************************************************************************/
+  task read_fifo;
+    integer i;
+    reg [C_DOUT_WIDTH-1:0]      tmp_dout;
+    reg [C_DIN_WIDTH-1:0]       memory_read;
+    reg [31:0]                  tmp_rd_ptr;
+    reg [31:0]                  rd_ptr_high;
+    reg [31:0]                  rd_ptr_low;
+    reg [1:0]                   tmp_ecc_err;
+    begin
+      rd_pntr <= #`TCQ rd_pntr + 1;
+      // output is wider than input
+      if (reads_per_write == 0) begin
+        tmp_dout = 0;
+        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
+        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
+          tmp_dout = tmp_dout << C_DIN_WIDTH;
+          tmp_dout = tmp_dout | memory[tmp_rd_ptr];
+           
+          // (Works opposite to core: rd_ptr is a DOWN counter)
+          if (tmp_rd_ptr == 0) begin
+            tmp_rd_ptr = C_WR_DEPTH - 1;
+          end else begin
+            tmp_rd_ptr = tmp_rd_ptr - 1;
+          end
+        end
+
+      // output is symmetric
+      end else if (reads_per_write == 1) begin
+        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
+        // Retreive the error injection type. Based on the error injection type
+        // corrupt the output data.
+        tmp_ecc_err = ecc_err[rd_ptr];
+        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
+          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
+            if (C_DOUT_WIDTH == 1) begin
+              $display(""FAILURE : Data width must be >= 2 for double bit error injection."");
+              $finish;
+            end else if (C_DOUT_WIDTH == 2)
+              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
+            else
+              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
+          end else begin
+            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
+          end
+          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
+        end else begin
+          err_type <= 0;
+        end
+
+      // input is wider than output
+      end else begin
+        rd_ptr_high = rd_ptr >> log2_reads_per_write;
+        rd_ptr_low  = rd_ptr & (reads_per_write - 1);
+        memory_read = memory[rd_ptr_high];
+        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
+      end
+      ideal_dout <= tmp_dout;
+       
+      // (Works opposite to core: rd_ptr is a DOWN counter)
+      if (rd_ptr == 0) begin
+        rd_ptr <= C_RD_DEPTH - 1;
+      end else begin
+        rd_ptr <= rd_ptr - 1;
+      end
+    end
+  endtask
+
+  /**************************************************************************
+  * log2_val
+  *   Returns the \'log2\' value for the input value for the supported ratios
+  ***************************************************************************/
+  function [31:0] log2_val;
+    input [31:0] binary_val;
+
+    begin
+      if (binary_val == 8) begin
+        log2_val = 3;
+      end else if (binary_val == 4) begin
+        log2_val = 2;
+      end else begin
+        log2_val = 1;
+      end
+    end
+  endfunction
+
+  /***********************************************************************
+  * hexstr_conv
+  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+  ***********************************************************************/
+  function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = \'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8\'b00000000 :
+          begin
+            bin = 4\'b0000;
+            i = -1;
+          end
+          8\'b00110000 : bin = 4\'b0000;
+          8\'b00110001 : bin = 4\'b0001;
+          8\'b00110010 : bin = 4\'b0010;
+          8\'b00110011 : bin = 4\'b0011;
+          8\'b00110100 : bin = 4\'b0100;
+          8\'b00110101 : bin = 4\'b0101;
+          8\'b00110110 : bin = 4\'b0110;
+          8\'b00110111 : bin = 4\'b0111;
+          8\'b00111000 : bin = 4\'b1000;
+          8\'b00111001 : bin = 4\'b1001;
+          8\'b01000001 : bin = 4\'b1010;
+          8\'b01000010 : bin = 4\'b1011;
+          8\'b01000011 : bin = 4\'b1100;
+          8\'b01000100 : bin = 4\'b1101;
+          8\'b01000101 : bin = 4\'b1110;
+          8\'b01000110 : bin = 4\'b1111;
+          8\'b01100001 : bin = 4\'b1010;
+          8\'b01100010 : bin = 4\'b1011;
+          8\'b01100011 : bin = 4\'b1100;
+          8\'b01100100 : bin = 4\'b1101;
+          8\'b01100101 : bin = 4\'b1110;
+          8\'b01100110 : bin = 4\'b1111;
+          default :
+          begin
+            bin = 4\'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_DOUT_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  /*************************************************************************
+  * Initialize Signals for clean power-on simulation
+  *************************************************************************/
+   initial begin
+      num_wr_bits        = 0;
+      num_rd_bits        = 0;
+      next_num_wr_bits   = 0;
+      next_num_rd_bits   = 0;
+      rd_ptr             = C_RD_DEPTH - 1;
+      wr_ptr             = C_WR_DEPTH - 1;
+      wr_pntr            = 0;
+      rd_pntr            = 0;
+      rd_ptr_wrclk       = rd_ptr;
+      wr_ptr_rdclk       = wr_ptr;
+      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);
+      ideal_dout         = dout_reset_val;
+      err_type           = 0;
+      err_type_d1        = 0;
+      err_type_both      = 0;
+      ideal_dout_d1      = dout_reset_val;
+      ideal_wr_ack       = 1\'b0;
+      ideal_valid        = 1\'b0;
+      valid_d1           = 1\'b0;
+      valid_d2           = 1\'b0;
+      ideal_overflow     = C_OVERFLOW_LOW;
+      ideal_underflow    = C_UNDERFLOW_LOW;
+      ideal_wr_count     = 0;
+      ideal_rd_count     = 0;
+      ideal_prog_full    = 1\'b0;
+      ideal_prog_empty   = 1\'b1;
+    end
+
+
+  /*************************************************************************
+   * Connect the module inputs and outputs to the internal signals of the 
+   * behavioral model.
+   *************************************************************************/
+   //Inputs
+   /*
+    wire [C_DIN_WIDTH-1:0] DIN;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;   
+   wire RD_CLK;
+   wire RD_EN;
+   wire RST;
+   wire WR_CLK;
+   wire WR_EN;
+    */
+
+   //***************************************************************************
+   // Dout may change behavior based on latency
+   //***************************************************************************
+   assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
+                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
+                         ideal_dout_d1: ideal_dout;   
+   assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; 
+
+   //***************************************************************************
+   // Assign SBITERR and DBITERR based on latency 
+   //***************************************************************************
+   assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && 
+                    (C_PRELOAD_LATENCY == 2 &&
+                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
+                    err_type_d1[0]: err_type[0]; 
+   assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
+                    (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
+                    err_type_d1[1]: err_type[1]; 
+  
+   //***************************************************************************
+   // Safety-ckt logic with embedded reg/fabric reg
+   //***************************************************************************
+     generate
+         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
+         
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+
+       //  if (C_HAS_VALID == 1) begin
+       //       assign valid_out = valid_d1;
+       //  end
+             
+        always@(posedge RD_CLK)
+          begin
+          rst_delayed_sft1 <= #`TCQ rd_rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+          end
+        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
+          begin
+          if( rst_delayed_sft4 == 1\'b1 || rd_rst_i == 1\'b1) 
+              ram_rd_en_d1 <= #`TCQ 1\'b0;
+          else 
+               ram_rd_en_d1 <= #`TCQ ram_rd_en;
+          end
+          
+        always@(posedge rst_delayed_sft2 or posedge RD_CLK) 
+           begin
+           if (rst_delayed_sft2 == 1\'b1) begin
+              if (C_USE_DOUT_RST == 1\'b1) begin
+                  @(posedge RD_CLK)
+                   ideal_dout_d1 <= #`TCQ dout_reset_val;
+              end
+           end
+           else begin
+                   if (ram_rd_en_d1) begin
+                   ideal_dout_d1   <= #`TCQ ideal_dout;
+                   err_type_d1[0] <= #`TCQ err_type[0];
+                   err_type_d1[1] <= #`TCQ err_type[1];
+                   end
+             end 
+           end  
+      end 
+      endgenerate   
+
+//***************************************************************************
+   // Safety-ckt logic with embedded reg + fabric reg
+   //***************************************************************************
+     generate
+         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
+         
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+
+        always@(posedge RD_CLK) begin
+          rst_delayed_sft1 <= #`TCQ rd_rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+        end
+        always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
+          if( rst_delayed_sft4 == 1\'b1 || rd_rst_i == 1\'b1) 
+              ram_rd_en_d1 <= #`TCQ 1\'b0;
+          else begin
+               ram_rd_en_d1 <= #`TCQ ram_rd_en;
+               fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
+          end
+        end
+          
+        always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
+           if (rst_delayed_sft2 == 1\'b1) begin
+              if (C_USE_DOUT_RST == 1\'b1) begin
+                   @(posedge RD_CLK)
+                   ideal_dout_d1 <= #`TCQ dout_reset_val;
+                   ideal_dout_both <= #`TCQ dout_reset_val;
+              end
+           end else begin
+             if (ram_rd_en_d1) begin
+               ideal_dout_both   <= #`TCQ ideal_dout;
+               err_type_both[0] <= #`TCQ err_type[0];
+               err_type_both[1] <= #`TCQ err_type[1];
+             end
+              
+             if (fab_rd_en_d1) begin
+               ideal_dout_d1   <= #`TCQ ideal_dout_both;
+               err_type_d1[0] <= #`TCQ err_type_both[0];
+               err_type_d1[1] <= #`TCQ err_type_both[1];
+             end
+           end 
+         end      
+      end 
+      endgenerate    
+ 
+   //***************************************************************************
+   // Overflow may be active-low
+   //***************************************************************************
+   generate
+      if (C_HAS_OVERFLOW==1) begin : blockOF1
+   assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
+      end
+   endgenerate
+
+   assign PROG_EMPTY = ideal_prog_empty;
+   assign PROG_FULL  = ideal_prog_full;
+
+   //***************************************************************************
+   // Valid may change behavior based on latency or active-low
+   //***************************************************************************
+   generate
+      if (C_HAS_VALID==1) begin : blockVL1
+   assign valid_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
+   assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
+                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
+                       valid_d1: valid_i;  
+   assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
+                       (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
+                       valid_d2: valid_i; 
+   assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
+   assign VALID     = valid_out ? !C_VALID_LOW : C_VALID_LOW;
+     end
+   endgenerate
+
+
+   //***************************************************************************
+   // Underflow may change behavior based on latency or active-low   
+   //***************************************************************************
+   generate
+      if (C_HAS_UNDERFLOW==1) begin : blockUF1
+   assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
+   assign UNDERFLOW   = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
+    end
+   endgenerate
+
+   //***************************************************************************
+   // Write acknowledge may be active low
+   //***************************************************************************
+   generate
+      if (C_HAS_WR_ACK==1) begin : blockWK1
+   assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
+     end
+   endgenerate
+
+
+   //***************************************************************************
+   // Generate RD_DATA_COUNT if Use Extra Logic option is selected
+   //***************************************************************************
+   generate
+      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
+
+      reg  [C_PNTR_WIDTH-1:0]  adjusted_wr_pntr = 0;
+      reg  [C_PNTR_WIDTH-1:0]  adjusted_rd_pntr = 0;
+      wire [C_PNTR_WIDTH-1:0]  diff_wr_rd_tmp;
+      wire [C_PNTR_WIDTH:0]    diff_wr_rd;
+      reg  [C_PNTR_WIDTH:0]    wr_data_count_i  = 0;
+        always @* begin
+          if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
+            adjusted_wr_pntr = wr_pntr;
+            adjusted_rd_pntr = 0;
+            adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
+          end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
+            adjusted_rd_pntr = rd_pntr_wr;
+            adjusted_wr_pntr = 0;
+            adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
+          end else begin
+            adjusted_wr_pntr = wr_pntr;
+            adjusted_rd_pntr = rd_pntr_wr;
+          end
+        end // always @*
+
+        assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
+        assign diff_wr_rd     = {1\'b0,diff_wr_rd_tmp};
+
+        always @ (posedge wr_rst_i or posedge WR_CLK)
+        begin
+            if (wr_rst_i)
+              wr_data_count_i <= 0;
+            else
+              wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
+        end // always @ (posedge WR_CLK or posedge WR_CLK)
+
+        always @* begin
+          if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
+            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
+          else
+            wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
+        end // always @*
+      end // wdc_fwft_ext
+   endgenerate
+
+   //***************************************************************************
+   // Generate RD_DATA_COUNT if Use Extra Logic option is selected
+   //***************************************************************************
+   reg  [C_RD_PNTR_WIDTH:0]    rdc_fwft_ext_as  = 0;
+
+   generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
+      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
+      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;
+      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;
+      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;
+        always @* begin
+          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
+            adjusted_wr_pntr_rd = 0;
+            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
+          end else begin
+            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+          end
+        end // always @*
+
+        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
+        assign diff_rd_wr     = {1\'b0,diff_rd_wr_tmp};
+
+
+   always @ (posedge rd_rst_i or posedge RD_CLK)
+        begin
+            if (rd_rst_i) begin
+              rdc_fwft_ext_as   <= 0;
+            end else begin
+              if (!stage2_valid)
+                rdc_fwft_ext_as <= #`TCQ 0;
+              else if (!stage1_valid && stage2_valid)
+                rdc_fwft_ext_as <= #`TCQ 1;
+              else
+                rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2\'h2;
+            end 
+        end // always @ (posedge WR_CLK or posedge WR_CLK)
+      end // rdc_fwft_ext
+ end
+   endgenerate
+
+
+  generate if (C_USE_EMBEDDED_REG == 3) begin
+     if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
+      reg  [C_RD_PNTR_WIDTH-1:0]  adjusted_wr_pntr_rd = 0;
+      wire [C_RD_PNTR_WIDTH-1:0]  diff_rd_wr_tmp;
+      wire [C_RD_PNTR_WIDTH:0]    diff_rd_wr;
+        always @* begin
+          if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
+            adjusted_wr_pntr_rd = 0;
+            adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
+          end else begin
+            adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+          end
+        end // always @*
+
+        assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
+        assign diff_rd_wr     = {1\'b0,diff_rd_wr_tmp};
+        wire [C_RD_PNTR_WIDTH:0]  diff_rd_wr_1;
+   //     assign diff_rd_wr_1 = diff_rd_wr +2\'h2;
+
+       always @ (posedge rd_rst_i or posedge RD_CLK)
+        begin
+            if (rd_rst_i) begin
+              rdc_fwft_ext_as   <= #`TCQ 0;
+            end else begin
+          //if (fab_read_data_valid_i == 1\'b0 && ((ram_valid_i == 1\'b0 && read_data_valid_i ==1\'b0) || (ram_valid_i == 1\'b0 && read_data_valid_i ==1\'b1) || (ram_valid_i == 1\'b1 && read_data_valid_i ==1\'b0) || (ram_valid_i == 1\'b1 && read_data_valid_i ==1\'b1)))
+          //    rdc_fwft_ext_as <= 1\'b0;
+          //else if (fab_read_data_valid_i == 1\'b1 && ((ram_valid_i == 1\'b0 && read_data_valid_i ==1\'b0) || (ram_valid_i == 1\'b0 && read_data_valid_i ==1\'b1))) 
+          //    rdc_fwft_ext_as <= 1\'b1;
+          //else
+            rdc_fwft_ext_as <= diff_rd_wr + 2\'h2 ;
+        end
+
+
+
+end
+end
+end
+endgenerate
+          
+
+   //***************************************************************************
+   // Assign the read data count value only if it is selected, 
+   // otherwise output zeros.
+   //***************************************************************************
+   generate
+      if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
+   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
+          rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
+          rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
+      end
+   endgenerate
+
+   generate
+      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
+   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1\'b0}};
+      end
+   endgenerate
+
+   //***************************************************************************
+   // Assign the write data count value only if it is selected, 
+   // otherwise output zeros
+   //***************************************************************************
+   generate
+      if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
+   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
+          wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
+          wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
+      end
+   endgenerate
+   
+   generate
+      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
+   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1\'b0}};
+      end
+   endgenerate
+
+
+  /**************************************************************************
+  * Assorted registers for delayed versions of signals
+  **************************************************************************/
+  //Capture delayed version of valid
+  generate
+      if (C_HAS_VALID==1) begin : blockVL2
+  always @(posedge RD_CLK or posedge rd_rst_i) begin
+    if (rd_rst_i == 1\'b1) begin
+      valid_d1 <= 1\'b0;
+      valid_d2 <= 1\'b0;
+    end else begin
+      valid_d1 <= #`TCQ valid_i;
+      valid_d2 <= #`TCQ valid_d1;
+    end 
+//    if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
+  //      valid_d2 <= #`TCQ valid_d1;
+      //  end 
+  end 
+      end
+ endgenerate  
+   
+  //Capture delayed version of dout
+  /**************************************************************************
+    *embedded/fabric reg with no safety ckt
+    **************************************************************************/
+  generate 
+       if (C_USE_EMBEDDED_REG < 3) begin
+  always @(posedge RD_CLK or posedge rd_rst_i) begin
+    if (rd_rst_i == 1\'b1) begin
+       if (C_USE_DOUT_RST == 1\'b1) begin
+         @(posedge RD_CLK)
+           ideal_dout_d1   <= #`TCQ dout_reset_val;
+           ideal_dout   <= #`TCQ dout_reset_val;
+       end
+      // Reset err_type only if ECC is not selected
+      if (C_USE_ECC == 0)
+        err_type_d1     <= #`TCQ 0;
+     end else if (ram_rd_en_d1) begin
+      ideal_dout_d1   <= #`TCQ ideal_dout;
+      err_type_d1     <= #`TCQ err_type;
+           end    
+  end  
+   
+end  
+endgenerate 
+/**************************************************************************
+    *embedded + fabric reg with no safety ckt
+    **************************************************************************/
+
+generate 
+  if (C_USE_EMBEDDED_REG == 3) begin
+    always @(posedge RD_CLK or posedge rd_rst_i) begin
+      if (rd_rst_i == 1\'b1) begin
+        if (C_USE_DOUT_RST == 1\'b1) begin
+           @(posedge RD_CLK)
+             ideal_dout    <= #`TCQ dout_reset_val;
+             ideal_dout_d1   <= #`TCQ dout_reset_val;
+             ideal_dout_both   <= #`TCQ dout_reset_val;
+        end
+        // Reset err_type only if ECC is not selected
+        if (C_USE_ECC == 0) begin
+          err_type_d1     <= #`TCQ 0;
+          err_type_both   <= #`TCQ 0;
+        end
+      end else begin
+         if (ram_rd_en_d1) begin
+           ideal_dout_both   <= #`TCQ ideal_dout;
+           err_type_both     <= #`TCQ err_type;
+         end    
+         if (fab_rd_en_d1) begin
+           ideal_dout_d1   <= #`TCQ ideal_dout_both;
+           err_type_d1     <= #`TCQ err_type_both;
+         end
+      end
+    end  
+  end  
+endgenerate 
+
+  
+   /**************************************************************************
+    * Overflow and Underflow Flag calculation
+    *  (handled separately because they don\'t support rst)
+    **************************************************************************/
+   generate
+     if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
+       always @(posedge WR_CLK) begin
+         ideal_overflow    <= #`TCQ WR_EN & FULL;
+       end
+     end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
+       always @(posedge WR_CLK) begin
+         //ideal_overflow    <= #`TCQ WR_EN & (FULL | wr_rst_i);
+         ideal_overflow    <= #`TCQ WR_EN & (FULL );
+       end
+     end
+   endgenerate
+
+   generate
+     if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
+       always @(posedge RD_CLK) begin
+         ideal_underflow    <= #`TCQ EMPTY & RD_EN;
+       end
+     end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
+       always @(posedge RD_CLK) begin
+         ideal_underflow    <= #`TCQ (EMPTY) & RD_EN;
+         //ideal_underflow    <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
+       end
+     end
+   endgenerate
+
+   /**************************************************************************
+   * Write/Read Pointer Synchronization
+   **************************************************************************/
+   localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
+   wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
+   wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
+   genvar gss;
+
+   generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
+     fifo_generator_v13_1_3_sync_stage
+       #(
+         .C_WIDTH  (C_WR_PNTR_WIDTH)
+        )
+     rd_stg_inst
+        (
+         .RST      (rd_rst_i), 
+         .CLK      (RD_CLK), 
+         .DIN      (wr_pntr_sync_stgs[gss-1]), 
+         .DOUT     (wr_pntr_sync_stgs[gss])
+        );
+ 
+     fifo_generator_v13_1_3_sync_stage
+       #(
+         .C_WIDTH  (C_RD_PNTR_WIDTH)
+        )
+     wr_stg_inst
+        (
+         .RST      (wr_rst_i), 
+         .CLK      (WR_CLK), 
+         .DIN      (rd_pntr_sync_stgs[gss-1]), 
+         .DOUT     (rd_pntr_sync_stgs[gss])
+        );
+   end endgenerate // Sync_stage_inst
+
+   assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
+   assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
+   always@* begin
+     wr_pntr_rd           <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
+     rd_pntr_wr           <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
+   end
+
+   /**************************************************************************
+   * Write Domain Logic
+   **************************************************************************/
+   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
+   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
+     if (wr_rst_i == 1\'b1 && C_EN_SAFETY_CKT == 0)
+       wr_pntr           <= 0;
+     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1\'b1)
+       wr_pntr           <= #`TCQ 0;
+   end
+   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
+
+     /****** Reset fifo (case 1)***************************************/
+     if (wr_rst_i == 1\'b1) begin
+       num_wr_bits       <= 0;
+       next_num_wr_bits   = 0;
+       wr_ptr            <= C_WR_DEPTH - 1;
+       rd_ptr_wrclk      <= C_RD_DEPTH - 1;
+       ideal_wr_ack      <= 0;
+       ideal_wr_count    <= 0;
+       tmp_wr_listsize    = 0;
+       rd_ptr_wrclk_next <= 0;
+       wr_pntr_rd1       <= 0;
+
+     end else begin //wr_rst_i==0
+
+       wr_pntr_rd1   <= #`TCQ wr_pntr;
+
+       //Determine the current number of words in the FIFO
+       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
+                         num_wr_bits/C_DIN_WIDTH;
+       rd_ptr_wrclk_next = rd_ptr;
+       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
+                                          - rd_ptr_wrclk_next);
+       end else begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
+       end
+
+       //If this is a write, handle the write by adding the value
+       // to the linked list, and updating all outputs appropriately
+       if (WR_EN == 1\'b1) begin
+         if (FULL == 1\'b1) begin
+
+           //If the FIFO is full, do NOT perform the write,
+           // update flags accordingly
+           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD 
+             >= C_FIFO_WR_DEPTH) begin
+             //write unsuccessful - do not change contents
+
+             //Do not acknowledge the write
+             ideal_wr_ack      <= #`TCQ 0;
+             //Reminder that FIFO is still full
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+           //If the FIFO is one from full, but reporting full
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
+                C_FIFO_WR_DEPTH-1) begin
+             //No change to FIFO
+
+             //Write not successful
+             ideal_wr_ack      <= #`TCQ 0;
+             //With DEPTH-1 words in the FIFO, it is almost_full
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+
+           //If the FIFO is completely empty, but it is
+           // reporting FULL for some reason (like reset)
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
+                C_FIFO_WR_DEPTH-2) begin
+             //No change to FIFO
+
+             //Write not successful
+             ideal_wr_ack      <= #`TCQ 0;
+             //FIFO is really not close to full, so change flag status.
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+           end //(tmp_wr_listsize == 0)
+
+         end else begin
+
+           //If the FIFO is full, do NOT perform the write,
+           // update flags accordingly
+           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
+              C_FIFO_WR_DEPTH) begin
+             //write unsuccessful - do not change contents
+
+             //Do not acknowledge the write
+             ideal_wr_ack       <= #`TCQ 0;
+             //Reminder that FIFO is still full
+
+             ideal_wr_count     <= #`TCQ num_write_words_sized_i;
+
+           //If the FIFO is one from full
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
+                C_FIFO_WR_DEPTH-1) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
+
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= #`TCQ 1;
+             //This write is CAUSING the FIFO to go full
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+           //If the FIFO is 2 from full
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == 
+                C_FIFO_WR_DEPTH-2) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= #`TCQ 1;
+             //Still 2 from full
+
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+           //If the FIFO is not close to being full
+           end else 
+             if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
+                C_FIFO_WR_DEPTH-2) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= #`TCQ 1;
+             //Not even close to full.
+
+             ideal_wr_count    <= num_write_words_sized_i;
+
+           end
+
+         end
+
+       end else begin //(WR_EN == 1\'b1)
+
+         //If user did not attempt a write, then do not
+         // give ack or err
+         ideal_wr_ack   <= #`TCQ 0;
+         ideal_wr_count <= #`TCQ num_write_words_sized_i;
+       end
+       num_wr_bits       <= #`TCQ next_num_wr_bits;
+       rd_ptr_wrclk      <= #`TCQ rd_ptr;
+
+     end //wr_rst_i==0
+   end // gen_fifo_w
+
+
+  /***************************************************************************
+   * Programmable FULL flags
+   ***************************************************************************/
+
+   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
+   wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
+
+   generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : 'b'FWFT
+     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
+     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
+   end else begin // STD
+     assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
+     assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
+   end endgenerate
+
+   always @(posedge WR_CLK or posedge wr_rst_i) begin
+
+     if (wr_rst_i == 1\'b1) begin
+       diff_pntr         <= 0;
+     end else begin
+       if (ram_wr_en)
+         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2\'h1);
+       else if (!ram_wr_en)
+         diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
+    end
+  end
+
+
+   always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
+
+     if (RST_FULL_FF == 1\'b1) begin
+       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;
+     end else begin
+
+       if (RST_FULL_GEN)
+         ideal_prog_full   <= #`TCQ 0;
+       //Single Programmable Full Constant Threshold
+       else if (C_PROG_FULL_TYPE == 1) begin
+         if (FULL == 0) begin
+           if (diff_pntr >= pf_thr_assert_val)
+             ideal_prog_full <= #`TCQ 1;
+           else
+             ideal_prog_full <= #`TCQ 0;
+         end else
+           ideal_prog_full   <= #`TCQ ideal_prog_full;
+       //Two Programmable Full Constant Thresholds
+       end else if (C_PROG_FULL_TYPE == 2) begin
+         if (FULL == 0) begin
+           if (diff_pntr >= pf_thr_assert_val)
+             ideal_prog_full <= #`TCQ 1;
+           else if (diff_pntr < pf_thr_negate_val)
+             ideal_prog_full <= #`TCQ 0;
+           else
+             ideal_prog_full <= #`TCQ ideal_prog_full;
+         end else
+           ideal_prog_full   <= #`TCQ ideal_prog_full;
+       //Single Programmable Full Threshold Input
+       end else if (C_PROG_FULL_TYPE == 3) begin
+         if (FULL == 0) begin
+           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
+             if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
+               ideal_prog_full <= #`TCQ 1;
+             else
+               ideal_prog_full <= #`TCQ 0;
+           end else begin // STD
+             if (diff_pntr >= PROG_FULL_THRESH)
+               ideal_prog_full <= #`TCQ 1;
+             else
+               ideal_prog_full <= #`TCQ 0;
+           end
+         end else
+           ideal_prog_full   <= #`TCQ ideal_prog_full;
+       //Two Programmable Full Threshold Inputs
+       end else if (C_PROG_FULL_TYPE == 4) begin
+         if (FULL == 0) begin
+           if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
+             if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
+               ideal_prog_full <= #`TCQ 1;
+             else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
+               ideal_prog_full <= #`TCQ 0;
+             else
+               ideal_prog_full <= #`TCQ ideal_prog_full;
+           end else begin // STD
+             if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
+               ideal_prog_full <= #`TCQ 1;
+             else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
+               ideal_prog_full <= #`TCQ 0;
+             else
+               ideal_prog_full <= #`TCQ ideal_prog_full;
+           end
+         end else
+           ideal_prog_full   <= #`TCQ ideal_prog_full;
+       end // C_PROG_FULL_TYPE
+
+     end //wr_rst_i==0
+   end //
+
+   
+   /**************************************************************************
+   * Read Domain Logic
+   **************************************************************************/
+
+
+   /*********************************************************
+    * Programmable EMPTY flags
+    *********************************************************/
+   //Determine the Assert and Negate thresholds for Programmable Empty
+
+   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
+   wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
+   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd      = 0;
+
+   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
+
+     if (rd_rst_i) begin
+       diff_pntr_rd       <= 0;
+       ideal_prog_empty   <= 1\'b1;
+     end else begin
+       if (ram_rd_en)
+         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1\'h1;
+       else if (!ram_rd_en)
+         diff_pntr_rd       <=  #`TCQ (adj_wr_pntr_rd - rd_pntr);
+       else
+         diff_pntr_rd       <=  #`TCQ diff_pntr_rd;
+  
+       if (C_PROG_EMPTY_TYPE == 1) begin
+         if (EMPTY == 0) begin
+           if (diff_pntr_rd <= pe_thr_assert_val)
+             ideal_prog_empty <= #`TCQ 1;
+           else
+             ideal_prog_empty <= #`TCQ 0;
+         end else
+           ideal_prog_empty   <= #`TCQ ideal_prog_empty;
+       end else if (C_PROG_EMPTY_TYPE == 2) begin
+         if (EMPTY == 0) begin
+           if (diff_pntr_rd <= pe_thr_assert_val)
+             ideal_prog_empty <= #`TCQ 1;
+           else if (diff_pntr_rd > pe_thr_negate_val)
+             ideal_prog_empty <= #`TCQ 0;
+           else
+             ideal_prog_empty <= #`TCQ ideal_prog_empty;
+         end else
+           ideal_prog_empty   <= #`TCQ ideal_prog_empty;
+       end else if (C_PROG_EMPTY_TYPE == 3) begin
+         if (EMPTY == 0) begin
+           if (diff_pntr_rd <= pe_thr_assert_val)
+             ideal_prog_empty <= #`TCQ 1;
+           else
+             ideal_prog_empty <= #`TCQ 0;
+         end else
+           ideal_prog_empty   <= #`TCQ ideal_prog_empty;
+       end else if (C_PROG_EMPTY_TYPE == 4) begin
+         if (EMPTY == 0) begin
+           if (diff_pntr_rd <= pe_thr_assert_val)
+             ideal_prog_empty <= #`TCQ 1;
+           else if (diff_pntr_rd > pe_thr_negate_val)
+             ideal_prog_empty <= #`TCQ 0;
+           else
+             ideal_prog_empty <= #`TCQ ideal_prog_empty;
+         end else
+           ideal_prog_empty   <= #`TCQ ideal_prog_empty;
+       end  //C_PROG_EMPTY_TYPE
+     end
+   end // gen_pe
+
+   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
+     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                PROG_EMPTY_THRESH - 2\'h2 : PROG_EMPTY_THRESH;
+   end endgenerate // single_pe_thr_input
+
+   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
+     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                PROG_EMPTY_THRESH_ASSERT - 2\'h2 : PROG_EMPTY_THRESH_ASSERT;
+     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                PROG_EMPTY_THRESH_NEGATE - 2\'h2 : PROG_EMPTY_THRESH_NEGATE;
+   end endgenerate // multiple_pe_thr_input
+
+   generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
+     assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                C_PROG_EMPTY_THRESH_ASSERT_VAL - 2\'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
+     assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
+                                C_PROG_EMPTY_THRESH_NEGATE_VAL - 2\'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
+   end endgenerate // single_multiple_pe_thr_const
+
+   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
+     if (rd_rst_i && C_EN_SAFETY_CKT == 0)
+       rd_pntr            <= 0;
+     else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1\'b1)
+       rd_pntr            <= #`TCQ 0;
+   end
+   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
+
+     /****** Reset fifo (case 1)***************************************/
+     if (rd_rst_i) begin
+       num_rd_bits        <= 0;
+       next_num_rd_bits    = 0;
+       rd_ptr             <= C_RD_DEPTH -1;
+       rd_pntr_wr1        <= 0;
+       wr_ptr_rdclk       <= C_WR_DEPTH -1;
+  
+       // DRAM resets asynchronously
+       if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
+          ideal_dout    <= dout_reset_val;
+  
+       // Reset err_type only if ECC is not selected
+       if (C_USE_ECC == 0) begin
+         err_type         <= 0;
+         err_type_d1      <= 0;
+         err_type_both    <= 0;
+       end
+       ideal_valid        <= 1\'b0;
+       ideal_rd_count     <= 0;
+
+     end else begin //rd_rst_i==0
+
+       rd_pntr_wr1   <= #`TCQ rd_pntr;
+
+       //Determine the current number of words in the FIFO
+       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
+                         num_rd_bits/C_DOUT_WIDTH;
+       wr_ptr_rdclk_next = wr_ptr;
+
+       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
+         next_num_rd_bits = num_rd_bits +
+                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
+                                         - wr_ptr_rdclk_next);
+       end else begin
+         next_num_rd_bits = num_rd_bits +
+                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
+       end
+
+       /*****************************************************************/
+       // Read Operation - Read Latency 1
+       /*****************************************************************/
+       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
+                 ideal_valid        <= #`TCQ 1\'b0;
+
+         if (ram_rd_en == 1\'b1) begin
+
+           if (EMPTY == 1\'b1) begin
+
+             //If the FIFO is completely empty, and is reporting empty
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= #`TCQ 1\'b0;
+                 //Reminder that FIFO is still empty
+
+                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+               end // if (tmp_rd_listsize <= 0)
+
+             //If the FIFO is one from empty, but it is reporting empty
+             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= #`TCQ 1\'b0;
+                 //Note that FIFO is no longer empty, but is almost empty (has one word left)
+
+                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+               end // if (tmp_rd_listsize == 1)
+
+             //If the FIFO is two from empty, and is reporting empty
+             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= #`TCQ 1\'b0;
+                 //Fifo has two words, so is neither empty or almost empty
+
+                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+               end // if (tmp_rd_listsize == 2)
+
+             //If the FIFO is not close to empty, but is reporting that it is
+             // Treat the FIFO as empty this time, but unset EMPTY flags.
+             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid <= #`TCQ 1\'b0;
+                 //Note that the FIFO is No Longer Empty or Almost Empty
+
+                 ideal_rd_count <= #`TCQ num_read_words_sized_i;
+
+               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+             end // else: if(ideal_empty == 1\'b1)
+
+           else //if (ideal_empty == 1\'b0)
+             begin
+
+               //If the FIFO is completely full, and we are successfully reading from it
+               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1\'b1;
+                   //Not close to empty
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
+
+               //If the FIFO is not close to being empty
+               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1\'b1;
+                   //Not close to empty
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+
+               //If the FIFO is two from empty
+               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1\'b1;
+                   //Fifo is not yet empty. It is going almost_empty
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == 2)
+
+               //If the FIFO is one from empty
+               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1\'b1;
+                   //Note that FIFO is GOING empty
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == 1)
+
+
+               //If the FIFO is completely empty
+               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
+                 begin
+                   //Do not change the contents of the FIFO
+
+                   //Do not acknowledge the read from empty FIFO
+                   ideal_valid        <= #`TCQ 1\'b0;
+
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize <= 0)
+
+             end // if (ideal_empty == 1\'b0)
+
+           end //(RD_EN == 1\'b1)
+
+         else //if (RD_EN == 1\'b0)
+           begin
+             //If user did not attempt a read, do not give an ack or err
+             ideal_valid          <= #`TCQ 1\'b0;
+
+             ideal_rd_count       <= #`TCQ num_read_words_sized_i;
+
+           end // else: !if(RD_EN == 1\'b1)
+
+       /*****************************************************************/
+       // Read Operation - Read Latency 0
+       /*****************************************************************/
+       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+                 ideal_valid        <= #`TCQ 1\'b0;
+         if (ram_rd_en == 1\'b1) begin
+
+           if (EMPTY == 1\'b1) begin
+
+             //If the FIFO is completely empty, and is reporting empty
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1\'b0;
+               //Reminder that FIFO is still empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is one from empty, but it is reporting empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1\'b0;
+               //Note that FIFO is no longer empty, but is almost empty (has one word left)
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is two from empty, and is reporting empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1\'b0;
+               //Fifo has two words, so is neither empty or almost empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+               //If the FIFO is not close to empty, but is reporting that it is
+             // Treat the FIFO as empty this time, but unset EMPTY flags.
+             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
+                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1\'b0;
+               //Note that the FIFO is No Longer Empty or Almost Empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+
+           end else begin
+
+             //If the FIFO is completely full, and we are successfully reading from it
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= #`TCQ 1\'b1;
+               //Not close to empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is not close to being empty
+             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
+                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= #`TCQ 1\'b1;
+               //Not close to empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is two from empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= #`TCQ 1\'b1;
+               //Fifo is not yet empty. It is going almost_empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is one from empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= #`TCQ 1\'b1;
+               //Note that FIFO is GOING empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             //If the FIFO is completely empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= #`TCQ 1\'b0;
+               //Reminder that FIFO is still empty
+
+               ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+             end // if (tmp_rd_listsize <= 0)
+
+           end // if (ideal_empty == 1\'b0)
+
+         end else begin//(RD_EN == 1\'b0)
+
+         
+           //If user did not attempt a read, do not give an ack or err
+           ideal_valid           <= #`TCQ 1\'b0;
+           ideal_rd_count        <= #`TCQ num_read_words_sized_i;
+
+         end // else: !if(RD_EN == 1\'b1)
+       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
+
+       num_rd_bits      <= #`TCQ next_num_rd_bits;
+       wr_ptr_rdclk     <= #`TCQ wr_ptr;
+     end //rd_rst_i==0
+   end //always gen_fifo_r_as
+
+endmodule // fifo_generator_v13_1_3_bhv_ver_as
+
+
+/*******************************************************************************
+ * Declaration of Low Latency Asynchronous FIFO
+ ******************************************************************************/
+module fifo_generator_v13_1_3_beh_ver_ll_afifo
+   
+  /***************************************************************************
+   * Declare user parameters and their defaults
+   ***************************************************************************/
+  #(
+    parameter  C_DIN_WIDTH                    = 8,
+    parameter  C_DOUT_RST_VAL                 = """",
+    parameter  C_DOUT_WIDTH                   = 8,
+    parameter  C_FULL_FLAGS_RST_VAL           = 1,
+    parameter  C_HAS_RD_DATA_COUNT            = 0,
+    parameter  C_HAS_WR_DATA_COUNT            = 0,
+    parameter  C_RD_DEPTH                     = 256,
+    parameter  C_RD_PNTR_WIDTH                = 8,
+    parameter  C_USE_DOUT_RST                 = 0,
+    parameter  C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter  C_WR_DEPTH                     = 256,
+    parameter  C_WR_PNTR_WIDTH                = 8,
+    parameter  C_FIFO_TYPE                    = 0
+   )
+
+  /***************************************************************************
+   * Declare Input and Output Ports
+   ***************************************************************************/
+  (
+   input       [C_DIN_WIDTH-1:0]                 DIN,
+   input                                         RD_CLK,
+   input                                         RD_EN,
+   input                                         WR_RST,
+   input                                         RD_RST,
+   input                                         WR_CLK,
+   input                                         WR_EN,
+   output reg  [C_DOUT_WIDTH-1:0]                DOUT = 0,
+   output reg                                    EMPTY = 1\'b1,
+   output reg                                    FULL = C_FULL_FLAGS_RST_VAL
+  );
+
+  //-----------------------------------------------------------------------------
+  // Low Latency Asynchronous FIFO
+  //-----------------------------------------------------------------------------
+
+  // Memory which will be used to simulate a FIFO
+  reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
+  integer i;
+  initial begin
+    for (i = 0; i < C_WR_DEPTH; i = i + 1)
+      memory[i] = 0;
+  end
+
+  reg  [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
+  wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
+  reg  [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
+  reg                        ll_afifo_full    = 1\'b0;
+  reg                        ll_afifo_empty   = 1\'b1;
+  wire                       write_allow;
+  wire                       read_allow;
+
+  assign write_allow = WR_EN & ~ll_afifo_full;
+  assign read_allow  = RD_EN & ~ll_afifo_empty;
+
+  //-----------------------------------------------------------------------------
+  // Write Pointer Generation
+  //-----------------------------------------------------------------------------
+  always @(posedge WR_CLK or posedge WR_RST) begin
+    if (WR_RST)
+      wr_pntr_ll_afifo   <= 0;
+    else if (write_allow)
+      wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
+  end
+
+  //-----------------------------------------------------------------------------
+  // Read Pointer Generation
+  //-----------------------------------------------------------------------------
+  always @(posedge RD_CLK or posedge RD_RST) begin
+    if (RD_RST)
+      rd_pntr_ll_afifo_q   <= 0;
+    else
+      rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
+  end
+  assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
+  
+  //-----------------------------------------------------------------------------
+  // Fill the Memory
+  //-----------------------------------------------------------------------------
+  always @(posedge WR_CLK) begin
+    if (write_allow)
+      memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
+  end
+
+  //-----------------------------------------------------------------------------
+  // Generate DOUT
+  //-----------------------------------------------------------------------------
+  always @(posedge RD_CLK) begin
+      DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
+  end
+
+  //-----------------------------------------------------------------------------
+  // Generate EMPTY
+  //-----------------------------------------------------------------------------
+  always @(posedge RD_CLK or posedge RD_RST) begin
+    if (RD_RST)
+      ll_afifo_empty   <= 1\'b1;
+    else
+      ll_afifo_empty   <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | 
+                           (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2\'h1))));
+  end
+
+  //-----------------------------------------------------------------------------
+  // Generate FULL
+  //-----------------------------------------------------------------------------
+  always @(posedge WR_CLK or posedge WR_RST) begin
+    if (WR_RST)
+      ll_afifo_full   <= 1\'b1;
+    else
+      ll_afifo_full   <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2\'h1)) | 
+                           (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2\'h2))));
+  end
+
+  always @* begin
+    FULL  <= ll_afifo_full;
+    EMPTY <= ll_afifo_empty;
+  end
+
+endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
+
+/*******************************************************************************
+ * Declaration of top-level module
+ ******************************************************************************/
+module fifo_generator_v13_1_3_bhv_ver_ss
+   
+  /**************************************************************************
+   * Declare user parameters and their defaults
+   *************************************************************************/
+  #(
+    parameter  C_FAMILY                       = ""virtex7"",
+    parameter  C_DATA_COUNT_WIDTH             = 2,
+    parameter  C_DIN_WIDTH                    = 8,
+    parameter  C_DOUT_RST_VAL                 = """",
+    parameter  C_DOUT_WIDTH                   = 8,
+    parameter  C_FULL_FLAGS_RST_VAL           = 1,
+    parameter  C_HAS_ALMOST_EMPTY             = 0,
+    parameter  C_HAS_ALMOST_FULL              = 0,
+    parameter  C_HAS_DATA_COUNT               = 0,
+    parameter  C_HAS_OVERFLOW                 = 0,
+    parameter  C_HAS_RD_DATA_COUNT            = 0,
+    parameter  C_HAS_RST                      = 0,
+    parameter  C_HAS_SRST                     = 0,
+    parameter  C_HAS_UNDERFLOW                = 0,
+    parameter  C_HAS_VALID                    = 0,
+    parameter  C_HAS_WR_ACK                   = 0,
+    parameter  C_HAS_WR_DATA_COUNT            = 0,
+    parameter  C_IMPLEMENTATION_TYPE          = 0,
+    parameter  C_MEMORY_TYPE                  = 1,
+    parameter  C_OVERFLOW_LOW                 = 0,
+    parameter  C_PRELOAD_LATENCY              = 1,
+    parameter  C_PRELOAD_REGS                 = 0,
+    parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
+    parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
+    parameter  C_PROG_EMPTY_TYPE              = 0,
+    parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0,
+    parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0,
+    parameter  C_PROG_FULL_TYPE               = 0,
+    parameter  C_RD_DATA_COUNT_WIDTH          = 2,
+    parameter  C_RD_DEPTH                     = 256,
+    parameter  C_RD_PNTR_WIDTH                = 8,
+    parameter  C_UNDERFLOW_LOW                = 0,
+    parameter  C_USE_DOUT_RST                 = 0,
+    parameter  C_USE_EMBEDDED_REG             = 0,
+    parameter  C_EN_SAFETY_CKT                = 0,
+    parameter  C_USE_FWFT_DATA_COUNT          = 0,
+    parameter  C_VALID_LOW                    = 0,
+    parameter  C_WR_ACK_LOW                   = 0,
+    parameter  C_WR_DATA_COUNT_WIDTH          = 2,
+    parameter  C_WR_DEPTH                     = 256,
+    parameter  C_WR_PNTR_WIDTH                = 8,
+    parameter  C_USE_ECC                      = 0, 
+    parameter  C_ENABLE_RST_SYNC              = 1,
+    parameter  C_ERROR_INJECTION_TYPE         = 0,
+    parameter  C_FIFO_TYPE                    = 0 
+   )
+   
+  /**************************************************************************
+   * Declare Input and Output Ports
+   *************************************************************************/
+   (
+    //Inputs
+    input                                 SAFETY_CKT_WR_RST,
+    input                                 CLK,
+    input       [C_DIN_WIDTH-1:0]         DIN,
+    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH,
+    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_ASSERT,
+    input       [C_RD_PNTR_WIDTH-1:0]     PROG_EMPTY_THRESH_NEGATE,
+    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH,
+    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_ASSERT,
+    input       [C_WR_PNTR_WIDTH-1:0]     PROG_FULL_THRESH_NEGATE,
+    input                                 RD_EN,
+    input                                 RD_EN_USER,
+    input                                 USER_EMPTY_FB,
+    input                                 RST,
+    input                                 RST_FULL_GEN,
+    input                                 RST_FULL_FF,
+    input                                 SRST,
+    input                                 WR_EN,
+    input                                 INJECTDBITERR,
+    input                                 INJECTSBITERR,
+    input                                 WR_RST_BUSY,
+    input                                 RD_RST_BUSY,
+                                    
+    //Outputs                       
+    output                                ALMOST_EMPTY,
+    output                                ALMOST_FULL,
+    output reg   [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
+    output       [C_DOUT_WIDTH-1:0]       DOUT,
+    output                                EMPTY,
+    output reg                            EMPTY_FB = 1\'b1,
+    output                                FULL,
+    output                                OVERFLOW,
+    output [C_RD_DATA_COUNT_WIDTH-1:0]    RD_DATA_COUNT,
+    output [C_WR_DATA_COUNT_WIDTH-1:0]    WR_DATA_COUNT,
+    output                                PROG_EMPTY,
+    output                                PROG_FULL,
+    output                                VALID,
+    output                                UNDERFLOW,
+    output                                WR_ACK,
+    output                                SBITERR,
+    output                                DBITERR
+   );
+
+
+   reg  [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
+   reg  [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
+   wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
+   wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
+   reg  [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
+   /***************************************************************************
+    * Parameters used as constants
+    **************************************************************************/
+  localparam IS_8SERIES         = (C_FAMILY == ""virtexu"" || C_FAMILY == ""kintexu"" || C_FAMILY == ""artixu"" || C_FAMILY == ""virtexuplus"" || C_FAMILY == ""zynquplus"" || C_FAMILY == ""kintexuplus"") ? 1 : 0;
+   localparam C_DEPTH_RATIO_WR =  
+      (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
+   localparam C_DEPTH_RATIO_RD =  
+      (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
+   //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
+   //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
+   localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; 
+
+
+   //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC
+   //  -----------------|------------------|-----------------|---------------
+   //  1                | 8                | C_RD_PNTR_WIDTH | 2
+   //  1                | 4                | C_RD_PNTR_WIDTH | 2
+   //  1                | 2                | C_RD_PNTR_WIDTH | 2
+   //  1                | 1                | C_WR_PNTR_WIDTH | 2
+   //  2                | 1                | C_WR_PNTR_WIDTH | 4
+   //  4                | 1                | C_WR_PNTR_WIDTH | 8
+   //  8                | 1                | C_WR_PNTR_WIDTH | 16
+   
+   localparam C_PNTR_WIDTH  = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
+   wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
+   wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
+   //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
+   localparam  EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
+   //localparam  EXTRA_WORDS_PE_PARAM  = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
+
+   localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
+   
+   localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
+   
+   localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
+   
+   localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
+
+
+   //When RST is present, set FULL reset value to \'1\'.
+   //If core has no RST, make sure FULL powers-on as \'0\'.
+   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not 
+   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
+   // Therefore, during SRST, all the FULL flags reset to 0.
+   localparam                      C_HAS_FAST_FIFO = 0;
+   localparam                      C_FIFO_WR_DEPTH = C_WR_DEPTH;
+   localparam                      C_FIFO_RD_DEPTH = C_RD_DEPTH;
+   // Local parameters used to determine whether to inject ECC error or not
+   localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
+   localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
+   localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
+   localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
+   localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
+   localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
+   localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
+  localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1\'b1}}; 
+  localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1\'b1}}; 
+
+
+   /**************************************************************************
+    * FIFO Contents Tracking and Data Count Calculations
+    *************************************************************************/
+   // Memory which will be used to simulate a FIFO
+   reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
+   reg [1:0] ecc_err[C_WR_DEPTH-1:0];
+
+   
+   /**************************************************************************
+    * Internal Registers and wires
+    *************************************************************************/
+
+   //Temporary signals used for calculating the model\'s outputs. These
+   //are only used in the assign statements immediately following wire,
+   //parameter, and function declarations.
+   wire                           underflow_i;
+   wire                           valid_i;
+   wire                           valid_out;
+   reg [31:0]  num_wr_bits;
+   reg [31:0]  num_rd_bits;
+   reg [31:0]  next_num_wr_bits;
+   reg [31:0]  next_num_rd_bits;
+
+   //The write pointer - tracks write operations
+   // (Works opposite to core: wr_ptr is a DOWN counter)
+   reg  [31:0]                 wr_ptr;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd1    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd2    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd3    = 0;
+   reg  [C_WR_PNTR_WIDTH-1:0]  wr_pntr_rd     = 0;
+   reg                         wr_rst_d1      =0;
+
+   //The read pointer - tracks read operations
+   // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
+   reg  [31:0]                 rd_ptr;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr1 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr2 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr3 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr4 = 0;
+   reg  [C_RD_PNTR_WIDTH-1:0]  rd_pntr_wr  = 0;
+
+   wire                        ram_rd_en;
+   wire                        empty_int;
+   wire                        almost_empty_int;
+   wire                        ram_wr_en;
+   wire                        full_int;
+   wire                        almost_full_int;
+   reg                         ram_rd_en_reg = 1\'b0;
+   reg                         ram_rd_en_d1 = 1\'b0;
+   reg                         fab_rd_en_d1 = 1\'b0;
+   wire                         srst_rrst_busy;
+
+
+
+   //Ideal FIFO signals. These are the raw output of the behavioral model,
+   //which behaves like an ideal FIFO.
+   reg [1:0]                      err_type           = 0;
+   reg [1:0]                      err_type_d1        = 0;
+   reg [1:0]                      err_type_both      = 0;
+   reg  [C_DOUT_WIDTH-1:0]        ideal_dout         = 0;
+   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_d1      = 0;
+   reg  [C_DOUT_WIDTH-1:0]        ideal_dout_both      = 0;
+   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;
+   wire                           fwft_enabled;
+   reg                            ideal_wr_ack       = 0;
+   reg                            ideal_valid        = 0;
+   reg                            ideal_overflow     = C_OVERFLOW_LOW;
+   reg                            ideal_underflow    = C_UNDERFLOW_LOW;
+
+   reg                            full_i             = C_FULL_FLAGS_RST_VAL;
+   reg                            full_i_temp        = 0;
+   reg                            empty_i            = 1;
+   reg                            almost_full_i      = 0;
+   reg                            almost_empty_i     = 1;
+   reg                            prog_full_i        = 0;
+   reg                            prog_empty_i       = 1;
+   reg [C_WR_PNTR_WIDTH-1:0]      wr_pntr            = 0;
+   reg [C_RD_PNTR_WIDTH-1:0]      rd_pntr            = 0;
+   wire [C_RD_PNTR_WIDTH-1:0]  adj_wr_pntr_rd;
+   wire [C_WR_PNTR_WIDTH-1:0]  adj_rd_pntr_wr;
+   reg [C_RD_PNTR_WIDTH-1:0]      diff_count         = 0;
+
+   reg                            write_allow_q      = 0;
+   reg                            read_allow_q       = 0;
+   reg                            valid_d1           = 0;
+   reg                            valid_both           = 0;
+   reg                            valid_d2           = 0;
+   wire                           rst_i;
+   wire                           srst_i;
+
+   //user specified value for reseting the size of the fifo
+   reg [C_DOUT_WIDTH-1:0]         dout_reset_val = 0;
+
+   reg [31:0]  wr_ptr_rdclk;
+   reg [31:0]  wr_ptr_rdclk_next;
+   reg [31:0]  rd_ptr_wrclk;
+   reg [31:0]  rd_ptr_wrclk_next;
+
+
+
+
+   /****************************************************************************
+    * Function Declarations
+    ***************************************************************************/
+
+   /****************************************************************************
+    * hexstr_conv
+    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+    ***************************************************************************/
+    function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = \'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
+        case (def_data[7:0])
+          8\'b00000000 : begin
+            bin = 4\'b0000;
+            i = -1;
+          end
+          8\'b00110000 : bin = 4\'b0000;
+          8\'b00110001 : bin = 4\'b0001;
+          8\'b00110010 : bin = 4\'b0010;
+          8\'b00110011 : bin = 4\'b0011;
+          8\'b00110100 : bin = 4\'b0100;
+          8\'b00110101 : bin = 4\'b0101;
+          8\'b00110110 : bin = 4\'b0110;
+          8\'b00110111 : bin = 4\'b0111;
+          8\'b00111000 : bin = 4\'b1000;
+          8\'b00111001 : bin = 4\'b1001;
+          8\'b01000001 : bin = 4\'b1010;
+          8\'b01000010 : bin = 4\'b1011;
+          8\'b01000011 : bin = 4\'b1100;
+          8\'b01000100 : bin = 4\'b1101;
+          8\'b01000101 : bin = 4\'b1110;
+          8\'b01000110 : bin = 4\'b1111;
+          8\'b01100001 : bin = 4\'b1010;
+          8\'b01100010 : bin = 4\'b1011;
+          8\'b01100011 : bin = 4\'b1100;
+          8\'b01100100 : bin = 4\'b1101;
+          8\'b01100101 : bin = 4\'b1110;
+          8\'b01100110 : bin = 4\'b1111;
+          default : begin
+            bin = 4\'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1) begin
+          if ((index*4)+j < C_DOUT_WIDTH) begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+ /**************************************************************************
+  * log2_val
+  *   Returns the \'log2\' value for the input value for the supported ratios
+  ***************************************************************************/
+  function [31:0] log2_val;
+    input [31:0] binary_val;
+
+    begin
+      if (binary_val == 8) begin
+        log2_val = 3;
+      end else if (binary_val == 4) begin
+        log2_val = 2;
+      end else begin
+        log2_val = 1;
+      end
+    end
+  endfunction
+
+   reg                     ideal_prog_full          = 0;
+   reg                     ideal_prog_empty         = 1;
+   reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
+   reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
+
+   //Assorted reg values for delayed versions of signals   
+   //reg         valid_d1     = 0;
+   
+   
+   //user specified value for reseting the size of the fifo
+   //reg [C_DOUT_WIDTH-1:0]            dout_reset_val = 0;
+   
+   //temporary registers for WR_RESPONSE_LATENCY feature
+   
+   integer                           tmp_wr_listsize;
+   integer                           tmp_rd_listsize;
+   
+   //Signal for registered version of prog full and empty
+   
+   //Threshold values for Programmable Flags
+   integer                           prog_empty_actual_thresh_assert;
+   integer                           prog_empty_actual_thresh_negate;
+   integer                           prog_full_actual_thresh_assert;
+   integer                           prog_full_actual_thresh_negate;
+
+
+ /**************************************************************************
+   * write_fifo
+   *   This task writes a word to the FIFO memory and updates the 
+   * write pointer.
+   *   FIFO size is relative to write domain.
+  ***************************************************************************/
+  task write_fifo;
+    begin
+      memory[wr_ptr]     <= DIN;
+      wr_pntr <= #`TCQ wr_pntr + 1;
+      // Store the type of error injection (double/single) on write
+      case (C_ERROR_INJECTION_TYPE)
+        3:       ecc_err[wr_ptr]    <= {INJECTDBITERR,INJECTSBITERR};
+        2:       ecc_err[wr_ptr]    <= {INJECTDBITERR,1\'b0};
+        1:       ecc_err[wr_ptr]    <= {1\'b0,INJECTSBITERR};
+        default: ecc_err[wr_ptr]    <= 0;
+      endcase
+      // (Works opposite to core: wr_ptr is a DOWN counter)
+      if (wr_ptr == 0) begin
+        wr_ptr          <= C_WR_DEPTH - 1;
+      end else begin
+        wr_ptr          <= wr_ptr - 1;
+      end
+    end
+  endtask // write_fifo
+
+  /**************************************************************************
+   * read_fifo
+   *   This task reads a word from the FIFO memory and updates the read 
+   * pointer. It\'s output is the ideal_dout bus.
+   *   FIFO size is relative to write domain.
+   ***************************************************************************/
+  task read_fifo;
+    integer i;
+    reg [C_DOUT_WIDTH-1:0]      tmp_dout;
+    reg [C_DIN_WIDTH-1:0]       memory_read;
+    reg [31:0]                  tmp_rd_ptr;
+    reg [31:0]                  rd_ptr_high;
+    reg [31:0]                  rd_ptr_low;
+    reg [1:0]                   tmp_ecc_err;
+    begin
+      rd_pntr <= #`TCQ rd_pntr + 1;
+
+      // output is wider than input
+      if (reads_per_write == 0) begin
+        tmp_dout = 0;
+        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
+        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
+          tmp_dout = tmp_dout << C_DIN_WIDTH;
+          tmp_dout = tmp_dout | memory[tmp_rd_ptr];
+           
+          // (Works opposite to core: rd_ptr is a DOWN counter)
+          if (tmp_rd_ptr == 0) begin
+            tmp_rd_ptr = C_WR_DEPTH - 1;
+          end else begin
+            tmp_rd_ptr = tmp_rd_ptr - 1;
+          end
+        end
+
+      // output is symmetric
+      end else if (reads_per_write == 1) begin
+        tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
+        // Retreive the error injection type. Based on the error injection type
+        // corrupt the output data.
+        tmp_ecc_err = ecc_err[rd_ptr];
+        if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
+          if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
+            if (C_DOUT_WIDTH == 1) begin
+              $display(""FAILURE : Data width must be >= 2 for double bit error injection."");
+              $finish;
+            end else if (C_DOUT_WIDTH == 2)
+              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
+            else
+              tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
+          end else begin
+            tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
+          end
+          err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
+        end else begin
+          err_type <= 0;
+        end
+
+      // input is wider than output
+      end else begin
+        rd_ptr_high = rd_ptr >> log2_reads_per_write;
+        rd_ptr_low  = rd_ptr & (reads_per_write - 1);
+        memory_read = memory[rd_ptr_high];
+        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
+      end
+      ideal_dout <= tmp_dout;
+       
+      // (Works opposite to core: rd_ptr is a DOWN counter)
+     if (rd_ptr == 0) begin
+        rd_ptr <= C_RD_DEPTH - 1;
+      end else begin
+        rd_ptr <= rd_ptr - 1;
+      end
+
+     end
+  endtask
+
+
+   
+  /*************************************************************************
+  * Initialize Signals for clean power-on simulation
+  *************************************************************************/
+   initial begin
+      num_wr_bits        = 0;
+      num_rd_bits        = 0;
+      next_num_wr_bits   = 0;
+      next_num_rd_bits   = 0;
+      rd_ptr             = C_RD_DEPTH - 1;
+      wr_ptr             = C_WR_DEPTH - 1;
+      wr_pntr            = 0;
+      rd_pntr            = 0;
+      rd_ptr_wrclk       = rd_ptr;
+      wr_ptr_rdclk       = wr_ptr;
+      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);
+      ideal_dout         = dout_reset_val;
+      err_type           = 0;
+      err_type_d1        = 0;
+      err_type_both      = 0;
+      ideal_dout_d1      = dout_reset_val;
+      ideal_dout_both    = dout_reset_val;
+      ideal_wr_ack       = 1\'b0;
+      ideal_valid        = 1\'b0;
+      valid_d1           = 1\'b0;
+      valid_both         = 1\'b0;
+      ideal_overflow     = C_OVERFLOW_LOW;
+      ideal_underflow    = C_UNDERFLOW_LOW;
+      ideal_wr_count     = 0;
+      ideal_rd_count     = 0;
+      ideal_prog_full    = 1\'b0;
+      ideal_prog_empty   = 1\'b1;
+
+   end
+
+
+  /*************************************************************************
+   * Connect the module inputs and outputs to the internal signals of the
+   * behavioral model.
+   *************************************************************************/
+   //Inputs
+   /*
+   wire CLK;
+   wire [C_DIN_WIDTH-1:0] DIN;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
+   wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
+   wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
+   wire RD_EN;
+   wire RST;
+   wire WR_EN;
+    */
+
+  // Assign ALMOST_EPMTY
+  generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
+    assign ALMOST_EMPTY = almost_empty_i;
+  end else begin : gnae
+    assign ALMOST_EMPTY = 0;
+  end endgenerate // gae
+
+  // Assign ALMOST_FULL
+  generate if (C_HAS_ALMOST_FULL==1) begin : gaf
+    assign ALMOST_FULL  = almost_full_i;
+  end else begin : gnaf
+    assign ALMOST_FULL  = 0;
+  end endgenerate // gaf
+
+   // Dout may change behavior based on latency
+  localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
+                         1: 0;
+  assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
+                         1: 0;
+  assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
+                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
+                         ideal_dout_d1: ideal_dout; 
+  assign DOUT = ideal_dout_out;
+
+  // Assign SBITERR and DBITERR based on latency 
+  assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && 
+                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
+                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
+                   err_type_d1[0]: err_type[0]; 
+  assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
+                   ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
+                    (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
+                   err_type_d1[1]: err_type[1]; 
+
+  assign EMPTY         = empty_i;
+  assign FULL          = full_i;
+  //saftey_ckt with one register
+
+  generate
+         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
+         
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+         
+        always@(posedge CLK)
+          begin
+          rst_delayed_sft1 <= #`TCQ rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+          end
+        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
+          begin
+          if( rst_delayed_sft2 == 1\'b1 || rst_i == 1\'b1) begin 
+              ram_rd_en_d1 <= #`TCQ 1\'b0;
+              valid_d1 <= #`TCQ 1\'b0;
+          end
+          else begin
+               ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
+               valid_d1 <= #`TCQ valid_i;
+          end
+          end
+          
+           always@(posedge rst_delayed_sft2 or posedge CLK) 
+           begin
+           if (rst_delayed_sft2 == 1\'b1) begin
+              if (C_USE_DOUT_RST == 1\'b1) begin
+                   @(posedge CLK)
+                   ideal_dout_d1 <= #`TCQ dout_reset_val;
+              end
+              end
+           else if (srst_rrst_busy == 1\'b1) begin
+                   if (C_USE_DOUT_RST == 1\'b1) begin
+                   ideal_dout_d1 <= #`TCQ dout_reset_val;
+                   end
+           end else if (ram_rd_en_d1) begin
+                   ideal_dout_d1   <= #`TCQ ideal_dout;
+                   err_type_d1[0] <= #`TCQ err_type[0];
+                   err_type_d1[1] <= #`TCQ err_type[1];
+                end
+           end   
+      end //if 
+      endgenerate   
+
+//safety ckt with both registers
+
+generate
+         if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
+         
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+         
+        always@(posedge CLK) begin
+          rst_delayed_sft1 <= #`TCQ rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+        end
+        always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
+          if (rst_delayed_sft2 == 1\'b1 || rst_i == 1\'b1) begin 
+            ram_rd_en_d1 <= #`TCQ 1\'b0;
+            valid_d1 <= #`TCQ 1\'b0;
+          end else begin
+            ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
+            fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
+            valid_both <= #`TCQ valid_i;
+            valid_d1 <= #`TCQ valid_both;
+          end
+        end
+
+        always@(posedge rst_delayed_sft2 or posedge CLK) begin
+          if (rst_delayed_sft2 == 1\'b1) begin
+             if (C_USE_DOUT_RST == 1\'b1) begin
+                   @(posedge CLK)
+                  ideal_dout_d1 <= #`TCQ dout_reset_val;
+             end
+          end else if (srst_rrst_busy == 1\'b1) begin
+             if (C_USE_DOUT_RST == 1\'b1) begin
+               ideal_dout_d1 <= #`TCQ dout_reset_val;
+             end
+          end else begin 
+            if (ram_rd_en_d1) begin
+               ideal_dout_both   <= #`TCQ ideal_dout;
+               err_type_both[0] <= #`TCQ err_type[0];
+               err_type_both[1] <= #`TCQ err_type[1];
+             end
+             if (fab_rd_en_d1) begin
+               ideal_dout_d1   <= #`TCQ ideal_dout_both;
+               err_type_d1[0] <= #`TCQ err_type_both[0];
+               err_type_d1[1] <= #`TCQ err_type_both[1];
+            end
+          end
+        end
+      end //if 
+      endgenerate    
+ 
+ 
+  //Overflow may be active-low
+  generate if (C_HAS_OVERFLOW==1) begin : gof
+    assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
+  end else begin : gnof
+    assign OVERFLOW = 0;
+  end endgenerate // gof
+
+  assign PROG_EMPTY    = prog_empty_i;
+  assign PROG_FULL     = prog_full_i;
+
+   //Valid may change behavior based on latency or active-low
+  generate if (C_HAS_VALID==1) begin : gvalid
+    assign valid_i       = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
+    assign valid_out     = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
+                            valid_d1 : valid_i; 
+    assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;
+  end else begin : gnvalid
+    assign VALID         = 0;
+  end endgenerate // gvalid
+
+  //Trim data count differently depending on set widths
+  generate if (C_HAS_DATA_COUNT == 1) begin : gdc
+    always @* begin
+      diff_count <= wr_pntr - rd_pntr;
+      if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
+        DATA_COUNT[C_RD_PNTR_WIDTH-1:0]  <= diff_count;
+        DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1\'b0 ; 
+      end else begin
+        DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
+      end
+    end
+//  end else begin : gndc
+//    always @* DATA_COUNT <= 0;
+  end endgenerate // gdc
+
+  //Underflow may change behavior based on latency or active-low
+  generate if (C_HAS_UNDERFLOW==1) begin : guf
+    assign underflow_i   = ideal_underflow;
+    assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
+  end else begin : gnuf
+    assign UNDERFLOW     = 0;
+  end endgenerate // guf
+ 
+
+  //Write acknowledge may be active low 
+  generate if (C_HAS_WR_ACK==1) begin : gwr_ack
+    assign WR_ACK        = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
+  end else begin : gnwr_ack
+    assign WR_ACK        = 0;
+  end endgenerate // gwr_ack
+
+
+  /*****************************************************************************
+   * Internal reset logic 
+   ****************************************************************************/
+  assign srst_i        = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
+  assign rst_i            = C_HAS_RST ? RST : 0;
+  assign srst_wrst_busy   = srst_i;
+  assign srst_rrst_busy   = srst_i;
+
+   /**************************************************************************
+    * Assorted registers for delayed versions of signals
+    **************************************************************************/
+   //Capture delayed version of valid
+   generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
+     always @(posedge CLK or posedge rst_i) begin
+        if (rst_i == 1\'b1) begin
+           valid_d1 <= 1\'b0;
+        end else begin
+           if (srst_rrst_busy) begin
+              valid_d1 <= #`TCQ 1\'b0;
+           end else begin
+              valid_d1 <= #`TCQ valid_i;
+           end
+        end    
+     end // always @ (posedge CLK or posedge rst_i)
+     end 
+   endgenerate // blockVL20
+
+  generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin 
+     always @(posedge CLK or posedge rst_i) begin
+        if (rst_i == 1\'b1) begin
+           valid_d1   <= 1\'b0;
+         'b'  valid_both <= 1\'b0;
+        end else begin
+           if (srst_rrst_busy) begin
+              valid_d1 <= #`TCQ 1\'b0;
+              valid_both <= #`TCQ 1\'b0;
+              
+           end else begin
+              valid_both <= #`TCQ valid_i;
+               valid_d1 <= #`TCQ valid_both;
+           end
+        end    
+     end // always @ (posedge CLK or posedge rst_i)
+  end
+ endgenerate // blockVL20
+
+
+   // Determine which stage in FWFT registers are valid
+   reg stage1_valid = 0;
+   reg stage2_valid = 0;
+   generate
+     if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
+       always @ (posedge CLK or posedge rst_i) begin
+         if (rst_i) begin
+           stage1_valid     <= #`TCQ 0;
+           stage2_valid     <= #`TCQ 0;
+         end else begin
+
+           if (!stage1_valid && !stage2_valid) begin
+             if (!EMPTY)
+               stage1_valid    <= #`TCQ 1\'b1;
+             else
+               stage1_valid    <= #`TCQ 1\'b0;
+           end else if (stage1_valid && !stage2_valid) begin
+             if (EMPTY) begin
+               stage1_valid    <= #`TCQ 1\'b0;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1\'b1;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end
+           end else if (!stage1_valid && stage2_valid) begin
+             if (EMPTY && RD_EN) begin
+               stage1_valid    <= #`TCQ 1\'b0;
+               stage2_valid    <= #`TCQ 1\'b0;
+             end else if (!EMPTY && RD_EN) begin
+               stage1_valid    <= #`TCQ 1\'b1;
+               stage2_valid    <= #`TCQ 1\'b0;
+             end else if (!EMPTY && !RD_EN) begin
+               stage1_valid    <= #`TCQ 1\'b1;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1\'b0;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end
+           end else if (stage1_valid && stage2_valid) begin
+             if (EMPTY && RD_EN) begin
+               stage1_valid    <= #`TCQ 1\'b0;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end else begin
+               stage1_valid    <= #`TCQ 1\'b1;
+               stage2_valid    <= #`TCQ 1\'b1;
+             end
+           end else begin
+             stage1_valid    <= #`TCQ 1\'b0;
+             stage2_valid    <= #`TCQ 1\'b0;
+           end
+         end // rd_rst_i
+       end // always
+     end
+   endgenerate
+
+
+
+   //***************************************************************************
+   // Assign the read data count value only if it is selected, 
+   // otherwise output zeros.
+   //***************************************************************************
+   generate
+      if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
+       assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
+      end
+   endgenerate
+
+   generate
+      if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
+   assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1\'b0}};
+      end
+   endgenerate
+
+   //***************************************************************************
+   // Assign the write data count value only if it is selected, 
+   // otherwise output zeros
+   //***************************************************************************
+   generate
+      if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
+       assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
+      end
+   endgenerate
+   
+   generate
+      if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
+   assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1\'b0}};
+      end
+   endgenerate
+   
+   //reg ram_rd_en_d1 = 1\'b0;
+   //Capture delayed version of dout
+   generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
+   always @(posedge CLK or posedge rst_i) begin
+      if (rst_i == 1\'b1) begin
+         // Reset err_type only if ECC is not selected
+         if (C_USE_ECC == 0) begin
+            err_type_d1      <= #`TCQ 0;
+            err_type_both    <= #`TCQ 0;
+         end
+         // DRAM and SRAM reset asynchronously
+         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+         end
+         ram_rd_en_d1 <= #`TCQ 1\'b0;
+        if (C_USE_DOUT_RST == 1) begin
+            @(posedge CLK)
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+        end
+      end else begin
+         ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
+         if (srst_rrst_busy) begin
+            ram_rd_en_d1 <= #`TCQ 1\'b0;
+            // Reset err_type only if ECC is not selected
+            if (C_USE_ECC == 0) begin
+               err_type_d1   <= #`TCQ 0;
+               err_type_both <= #`TCQ 0;
+            end
+            // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
+            if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
+               ideal_dout_d1 <= #`TCQ dout_reset_val;
+            end 
+         if (C_USE_DOUT_RST == 1) begin
+           // @(posedge CLK)
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+         end
+         end else begin
+            if (ram_rd_en_d1 ) begin
+            ideal_dout_d1 <= #`TCQ ideal_dout;
+            err_type_d1   <= #`TCQ err_type;
+            end
+         end
+      end    
+   end   // always
+end
+endgenerate 
+
+//no safety ckt with both registers
+ generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
+   always @(posedge CLK or posedge rst_i) begin
+      if (rst_i == 1\'b1) begin
+          ram_rd_en_d1 <= #`TCQ 1\'b0;
+          fab_rd_en_d1 <= #`TCQ 1\'b0;
+         // Reset err_type only if ECC is not selected
+         if (C_USE_ECC == 0) begin
+            err_type_d1      <= #`TCQ 0;
+            err_type_both    <= #`TCQ 0;
+         end
+         // DRAM and SRAM reset asynchronously
+         if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+            ideal_dout_both <= #`TCQ dout_reset_val; 
+            
+      end
+        if (C_USE_DOUT_RST == 1) begin
+            @(posedge CLK)
+            ideal_dout_d1 <= #`TCQ dout_reset_val;
+            ideal_dout_both <= #`TCQ dout_reset_val;
+       end
+      end else begin
+         if (srst_rrst_busy) begin 
+           ram_rd_en_d1 <= #`TCQ 1\'b0;
+           fab_rd_en_d1 <= #`TCQ 1\'b0;
+           // Reset err_type only if ECC is not selected
+           if (C_USE_ECC == 0) begin
+              err_type_d1   <= #`TCQ 0;
+              err_type_both <= #`TCQ 0;
+           end
+           // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
+           if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
+              ideal_dout_d1 <= #`TCQ dout_reset_val;
+           end 
+           if (C_USE_DOUT_RST == 1) begin
+             ideal_dout_d1 <= #`TCQ dout_reset_val;
+           end
+         end else begin
+           ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
+           fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
+           if (ram_rd_en_d1 ) begin
+             ideal_dout_both <= #`TCQ ideal_dout;
+             err_type_both   <= #`TCQ err_type;
+           end
+           if (fab_rd_en_d1 ) begin
+             ideal_dout_d1 <= #`TCQ ideal_dout_both;
+             err_type_d1   <= #`TCQ err_type_both;
+           end
+         end
+      end    
+   end   // always
+end
+endgenerate 
+   /**************************************************************************
+    * Overflow and Underflow Flag calculation
+    *  (handled separately because they don\'t support rst)
+    **************************************************************************/
+   generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
+     always @(posedge CLK) begin
+       ideal_overflow    <= #`TCQ WR_EN & full_i;
+     end
+   end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
+     always @(posedge CLK) begin
+       //ideal_overflow    <= #`TCQ WR_EN & (rst_i | full_i);
+       ideal_overflow    <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
+     end
+   end endgenerate // blockOF20
+ 
+   generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
+     always @(posedge CLK) begin
+       ideal_underflow   <= #`TCQ empty_i & RD_EN;
+     end
+   end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
+     always @(posedge CLK) begin
+       //ideal_underflow   <= #`TCQ (rst_i | empty_i) & RD_EN;
+       ideal_underflow   <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
+     end
+   end endgenerate // blockUF20
+
+
+   /**************************
+    * Read Data Count
+    *************************/
+
+   reg [31:0] num_read_words_dc;
+   reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
+   
+   always @(num_rd_bits) begin
+     if (C_USE_FWFT_DATA_COUNT) begin
+        
+        //If using extra logic for FWFT Data Counts, 
+        // then scale FIFO contents to read domain, 
+        // and add two read words for FWFT stages
+        //This value is only a temporary value and not used in the code.
+        num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_read_words_sized_i = 
+          num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
+        
+     end else begin
+        
+        //If not using extra logic for FWFT Data Counts, 
+        // then scale FIFO contents to read domain.
+        //This value is only a temporary value and not used in the code.
+        num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_read_words_sized_i = 
+          num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
+        
+     end //if (C_USE_FWFT_DATA_COUNT)
+   end //always
+
+   
+   /**************************
+    * Write Data Count
+    *************************/
+
+   reg [31:0] num_write_words_dc;
+   reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
+   
+   always @(num_wr_bits) begin
+     if (C_USE_FWFT_DATA_COUNT) begin
+        
+        //Calculate the Data Count value for the number of write words, 
+        // when using First-Word Fall-Through with extra logic for Data 
+        // Counts. This takes into consideration the number of words that 
+        // are expected to be stored in the FWFT register stages (it always 
+        // assumes they are filled).
+        //This value is scaled to the Write Domain.
+        //The expression (((A-1)/B))+1 divides A/B, but takes the 
+        // ceiling of the result.
+        //When num_wr_bits==0, set the result manually to prevent 
+        // division errors.
+        //EXTRA_WORDS_DC is the number of words added to write_words 
+        // due to FWFT.
+        //This value is only a temporary value and not used in the code.
+        num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC :  (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
+        
+        //Trim the write words for use with WR_DATA_COUNT
+        num_write_words_sized_i = 
+          num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
+        
+     end else begin
+        
+        //Calculate the Data Count value for the number of write words, when NOT
+        // using First-Word Fall-Through with extra logic for Data Counts. This 
+        // calculates only the number of words in the internal FIFO.
+        //The expression (((A-1)/B))+1 divides A/B, but takes the 
+        // ceiling of the result.
+        //This value is scaled to the Write Domain.
+        //When num_wr_bits==0, set the result manually to prevent 
+        // division errors.
+        //This value is only a temporary value and not used in the code.
+        num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
+        
+        //Trim the read words for use with RD_DATA_COUNT
+        num_write_words_sized_i = 
+          num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
+        
+     end //if (C_USE_FWFT_DATA_COUNT)
+   end //always
+
+
+  /*************************************************************************
+   * Write and Read Logic  
+   ************************************************************************/
+   wire              write_allow;
+   wire              read_allow;
+   wire              read_allow_dc;
+   wire              write_only;
+   wire              read_only;
+   //wire              write_only_q;
+   reg              write_only_q;
+   //wire              read_only_q;
+   reg              read_only_q;
+   reg              full_reg;
+   reg              rst_full_ff_reg1;
+   reg              rst_full_ff_reg2;
+   wire              ram_full_comb;
+   wire              carry;
+   
+   assign write_allow  = WR_EN & ~full_i;
+   assign read_allow   = RD_EN & ~empty_i;
+   assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
+   //assign write_only   = write_allow & ~read_allow;
+   //assign write_only_q = write_allow_q;
+   //assign read_only    = read_allow    & ~write_allow;
+   //assign read_only_q  = read_allow_q ;
+   wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
+   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
+   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
+   reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
+   reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
+   wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
+   wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
+   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
+   reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
+   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
+   wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
+
+   assign diff_pntr_pe_max = DIFF_MAX_RD;
+   assign diff_pntr_max = DIFF_MAX_WR;
+
+
+
+   generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
+    assign write_only   = write_allow & ~read_allow;
+    assign read_only    = read_allow    & ~write_allow;
+    end endgenerate
+    generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
+     assign read_only   = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
+     assign write_only    = write_allow    & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
+    end endgenerate
+    generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
+     assign read_only   = read_allow & ~(write_allow  & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
+     assign write_only    = write_allow &  &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
+    end endgenerate
+
+
+   //-----------------------------------------------------------------------------
+   // Write and Read pointer generation
+   //-----------------------------------------------------------------------------
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i && C_EN_SAFETY_CKT == 0) begin
+       wr_pntr         <= 0;
+       rd_pntr         <= 0;
+     end else begin
+       if (srst_i) begin
+         wr_pntr       <= #`TCQ 0;
+         rd_pntr       <= #`TCQ 0;
+       end else begin
+         if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
+         if (read_allow)  rd_pntr <= #`TCQ rd_pntr + 1;
+       end
+     end
+   end
+
+   generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
+   always @(posedge CLK) begin
+     if (write_allow) begin
+       if (ENABLE_ERR_INJECTION == 1)
+         memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
+       else
+         memory[wr_pntr] <= #`TCQ DIN;
+     end
+   end
+
+   reg  [C_DATA_WIDTH-1:0] dout_tmp_q;
+   reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
+   reg  [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
+   always @(posedge CLK) begin
+     dout_tmp_q <= #`TCQ ideal_dout;
+   end
+
+
+
+     always @* begin
+       if (read_allow)
+         ideal_dout <= memory[rd_pntr];
+       else
+         ideal_dout <= dout_tmp_q;
+     end
+   end endgenerate // gll_dm_dout
+
+
+   /**************************************************************************
+   * Write Domain Logic
+   **************************************************************************/
+   assign ram_rd_en        = RD_EN & !EMPTY;
+
+   //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
+   generate if (C_FIFO_TYPE != 2) begin : gnll_din
+   always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
+
+     /****** Reset fifo (case 1)***************************************/
+     if (rst_i == 1\'b1) begin
+       num_wr_bits       <= #`TCQ 0;
+       next_num_wr_bits   = #`TCQ 0;
+       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;
+       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;
+       ideal_wr_ack      <= #`TCQ 0;
+       ideal_wr_count    <= #`TCQ 0;
+       tmp_wr_listsize    = #`TCQ 0;
+       rd_ptr_wrclk_next <= #`TCQ 0;
+       wr_pntr           <= #`TCQ 0;
+       wr_pntr_rd1       <= #`TCQ 0;
+
+     end else begin //rst_i==0
+     if (srst_wrst_busy) begin
+       num_wr_bits       <= #`TCQ 0;
+       next_num_wr_bits   = #`TCQ 0;
+       wr_ptr            <= #`TCQ C_WR_DEPTH - 1;
+       rd_ptr_wrclk      <= #`TCQ C_RD_DEPTH - 1;
+       ideal_wr_ack      <= #`TCQ 0;
+       ideal_wr_count    <= #`TCQ 0;
+       tmp_wr_listsize    = #`TCQ 0;
+       rd_ptr_wrclk_next <= #`TCQ 0;
+       wr_pntr           <= #`TCQ 0;
+       wr_pntr_rd1       <= #`TCQ 0;
+     end else begin//srst_i=0
+
+       wr_pntr_rd1   <= #`TCQ wr_pntr;
+
+       //Determine the current number of words in the FIFO
+       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
+                         num_wr_bits/C_DIN_WIDTH;
+       rd_ptr_wrclk_next = rd_ptr;
+       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
+                                          - rd_ptr_wrclk_next);
+       end else begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
+       end
+
+       if (WR_EN == 1\'b1) begin
+         if (FULL == 1\'b1) begin
+
+             ideal_wr_ack      <= #`TCQ 0;
+             //Reminder that FIFO is still full
+             ideal_wr_count    <= #`TCQ num_write_words_sized_i;
+
+         end else begin
+             write_fifo;
+             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;
+             //Write successful, so issue acknowledge
+             // and no error  
+             ideal_wr_ack      <= #`TCQ 1;
+             //Not even close to full.
+             ideal_wr_count    <= num_write_words_sized_i;
+
+           //end
+
+         end
+
+       end else begin //(WR_EN == 1\'b1)
+
+         //If user did not attempt a write, then do not
+         // give ack or err
+         ideal_wr_ack   <= #`TCQ 0;
+         ideal_wr_count <= #`TCQ num_write_words_sized_i;
+       end
+       num_wr_bits       <= #`TCQ next_num_wr_bits;
+       rd_ptr_wrclk      <= #`TCQ rd_ptr;
+
+     end //srst_i==0
+     end //wr_rst_i==0
+   end // gen_fifo_w
+    end endgenerate
+
+   generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
+     always @(posedge CLK) begin
+       if (rst_i || srst_rrst_busy) begin
+         if (C_USE_DOUT_RST == 1) begin
+           ideal_dout <= #`TCQ dout_reset_val;
+           ideal_dout_both <= #`TCQ dout_reset_val;
+         end
+       end
+     end
+    end endgenerate
+
+
+
+
+   generate if (C_FIFO_TYPE != 2) begin : gnll_dout
+   always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
+
+     /****** Reset fifo (case 1)***************************************/
+     if (rst_i) begin
+       num_rd_bits        <= #`TCQ 0;
+       next_num_rd_bits    = #`TCQ 0;
+       rd_ptr             <= #`TCQ C_RD_DEPTH -1;
+       rd_pntr            <= #`TCQ 0;
+       //rd_pntr_wr1       <= #`TCQ 0;
+       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;
+  
+       // DRAM resets asynchronously
+       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
+          ideal_dout    <= #`TCQ dout_reset_val;
+  
+       // Reset err_type only if ECC is not selected
+       if (C_USE_ECC == 0) begin
+         err_type         <= #`TCQ 0;
+         err_type_d1      <= 0;
+         err_type_both    <= 0;
+       end
+       ideal_valid        <= #`TCQ 1\'b0;
+       ideal_rd_count     <= #`TCQ 0;
+
+     end else begin //rd_rst_i==0
+     if (srst_rrst_busy) begin
+       num_rd_bits        <= #`TCQ 0;
+       next_num_rd_bits    = #`TCQ 0;
+       rd_ptr             <= #`TCQ C_RD_DEPTH -1;
+       rd_pntr            <= #`TCQ 0;
+       //rd_pntr_wr1       <= #`TCQ 0;
+       wr_ptr_rdclk       <= #`TCQ C_WR_DEPTH -1;
+  
+       // DRAM resets synchronously
+       if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
+          ideal_dout    <= #`TCQ dout_reset_val;
+  
+       // Reset err_type only if ECC is not selected
+       if (C_USE_ECC == 0) begin
+         err_type         <= #`TCQ 0;
+         err_type_d1      <= #`TCQ 0;
+         err_type_both    <= #`TCQ 0;
+       end
+       ideal_valid        <= #`TCQ 1\'b0;
+       ideal_rd_count     <= #`TCQ 0;
+      end //srst_i
+      else begin
+
+       //rd_pntr_wr1   <= #`TCQ rd_pntr;
+
+       //Determine the current number of words in the FIFO
+       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
+                         num_rd_bits/C_DOUT_WIDTH;
+       wr_ptr_rdclk_next = wr_ptr;
+
+       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
+         next_num_rd_bits = num_rd_bits +
+                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
+                                         - wr_ptr_rdclk_next);
+       end else begin
+         next_num_rd_bits = num_rd_bits +
+                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
+       end
+
+         if (RD_EN == 1\'b1) begin
+
+           if (EMPTY == 1\'b1) begin
+                 ideal_valid        <= #`TCQ 1\'b0;
+                 ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+               end 
+           else 
+             begin
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= #`TCQ 1\'b1;
+                   ideal_rd_count     <= #`TCQ num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == 2)
+         end
+
+       num_rd_bits      <= #`TCQ next_num_rd_bits;
+       wr_ptr_rdclk     <= #`TCQ wr_ptr;
+     end //s_rst_i==0
+     end //rd_rst_i==0
+   end //always
+  end endgenerate
+
+   //-----------------------------------------------------------------------------
+   // Generate diff_pntr for PROG_FULL generation
+   // Generate diff_pntr_pe for PROG_EMPTY generation
+   //-----------------------------------------------------------------------------
+   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
+     always @(posedge CLK ) begin
+       if (rst_i) begin
+         write_only_q   <= 1\'b0;
+         read_only_q    <= 1\'b0;
+         diff_pntr_reg1       <= 0;
+         diff_pntr_pe_reg1    <= 0;
+         diff_pntr_reg2       <= 0;
+         diff_pntr_pe_reg2    <= 0;
+       end else begin
+         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
+          if (srst_rrst_busy) begin
+           read_only_q  <= #`TCQ 1\'b0;
+           diff_pntr_pe_reg1  <= #`TCQ 0;
+           diff_pntr_pe_reg2  <= #`TCQ 0;
+          end
+          if (srst_wrst_busy) begin
+           write_only_q <= #`TCQ 1\'b0;
+           diff_pntr_reg1     <= #`TCQ 0;
+           diff_pntr_reg2     <= #`TCQ 0;
+          end
+         end else begin
+           write_only_q <= #`TCQ write_only;
+           read_only_q  <= #`TCQ read_only;
+           diff_pntr_reg2  <= #`TCQ diff_pntr_reg1;
+           diff_pntr_pe_reg2  <= #`TCQ diff_pntr_pe_reg1;
+
+           // Add 1 to the difference pointer value when only write happens.
+           if (write_only)  
+             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
+           else
+             diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
+
+           // Add 1 to the difference pointer value when write or both write & read or no write & read happen.
+           if (read_only)  
+             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
+           else
+             diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
+         end
+       end
+     end
+   assign diff_pntr_pe = diff_pntr_pe_reg1;
+   assign diff_pntr = diff_pntr_reg1;
+   end endgenerate // reg_write_allow
+
+   generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
+    assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1\'b1};
+    assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1\'b1};
+     always @(posedge CLK ) begin
+       if (rst_i) begin
+         diff_pntr_pe_asym    <= 0;
+         diff_pntr_reg1       <= 0;
+         full_reg             <= 0;
+         rst_full_ff_reg1     <= 1;
+         rst_full_ff_reg2     <= 1;
+         diff_pntr_pe_reg1    <= 0;
+       end else begin
+         if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
+          if (srst_wrst_busy)
+           diff_pntr_reg1     <= #`TCQ 0;
+          if (srst_rrst_busy)
+           full_reg             <=  #`TCQ 0;
+           rst_full_ff_reg1     <=  #`TCQ 1;
+           rst_full_ff_reg2     <=  #`TCQ 1;
+           diff_pntr_pe_asym    <=  #`TCQ 0;
+           diff_pntr_pe_reg1  <= #`TCQ 0;
+         end else begin
+             diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
+             full_reg          <= #`TCQ full_i;
+             rst_full_ff_reg1  <=  #`TCQ RST_FULL_FF;
+             rst_full_ff_reg2  <=  #`TCQ rst_full_ff_reg1;
+           if (~full_i) begin  
+             diff_pntr_reg1 <=  #`TCQ wr_pntr - adj_rd_pntr_wr;
+          end
+         end
+       end
+     end
+   assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
+   assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
+   assign diff_pntr = diff_pntr_reg1;
+   end endgenerate // reg_write_allow_asym
+
+
+   //-----------------------------------------------------------------------------
+   // Generate FULL flag
+   //-----------------------------------------------------------------------------
+   wire                 comp0;
+   wire                 comp1;
+   wire                 going_full;
+   wire                 leaving_full;
+ 
+ generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin :  gpad \t
+    assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
+    assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
+  end endgenerate
+
+  generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin :  gtrim 
+    assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
+  end endgenerate
+
+   assign comp1         = (adj_rd_pntr_wr == (wr_pntr + 1\'b1));
+   assign comp0         = (adj_rd_pntr_wr == wr_pntr);
+
+    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
+     assign going_full    = (comp1 & write_allow & ~read_allow);
+     assign leaving_full  = (comp0 & read_allow) | RST_FULL_GEN;
+    end endgenerate
+
+    // Write data width is bigger than read data width
+    // Write depth is smaller than read depth
+    // One write could be equal to 2 or 4 or 8 reads
+    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
+      assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
+      assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
+    end endgenerate
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp 
+      assign going_full = (comp1 & write_allow & ~read_allow);
+      assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
+    end endgenerate
+
+
+   assign ram_full_comb = going_full | (~leaving_full & full_i);
+
+   always @(posedge CLK or posedge RST_FULL_FF) begin
+     if (RST_FULL_FF)
+       full_i   <= C_FULL_FLAGS_RST_VAL;
+     else if (srst_wrst_busy)
+       full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;
+     else
+       full_i   <= #`TCQ ram_full_comb;
+    end
+
+   //-----------------------------------------------------------------------------
+   // Generate EMPTY flag
+   //-----------------------------------------------------------------------------
+   wire                 ecomp0;
+   wire                 ecomp1;
+   wire                 going_empty;
+   wire                 leaving_empty;
+   wire                 ram_empty_comb;
+
+  
+ generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin :  pad \t
+    assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
+    assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
+  end endgenerate
+
+  generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin :  trim 
+    assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+  end endgenerate
+
+   assign ecomp1         = (adj_wr_pntr_rd == (rd_pntr + 1\'b1));
+   assign ecomp0         = (adj_wr_pntr_rd == rd_pntr);
+
+
+    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
+     assign going_empty    = (ecomp1 & ~write_allow & read_allow);
+     assign leaving_empty  = (ecomp0 & write_allow);
+    end endgenerate
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
+      assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
+      assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
+    end endgenerate
+  
+   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp 
+      assign going_empty = (ecomp1 & ~write_allow & read_allow);
+      assign leaving_empty =(ecomp0 & write_allow);
+    end endgenerate
+
+
+
+    assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
+
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i)
+       empty_i  <= 1\'b1;
+     else if (srst_rrst_busy)
+       empty_i  <= #`TCQ 1\'b1;
+     else
+       empty_i  <= #`TCQ ram_empty_comb;
+    end
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i && C_EN_SAFETY_CKT == 0) begin
+       EMPTY_FB     <= 1\'b1;
+     end else begin
+       if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
+         EMPTY_FB   <= #`TCQ 1\'b1;
+       else
+         EMPTY_FB   <= #`TCQ ram_empty_comb;
+     end
+   end // always
+
+   //-----------------------------------------------------------------------------
+   // Generate Read and write data counts for asymmetic common clock
+   //-----------------------------------------------------------------------------
+
+    reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; 
+    wire [C_GRTR_PNTR_WIDTH :0] ratio; 
+    wire decr_by_one;
+    wire incr_by_ratio;
+    wire incr_by_one;
+    wire decr_by_ratio;
+
+   localparam IS_FWFT          = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
+
+   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr 
+      assign ratio         = C_DEPTH_RATIO_RD;
+      assign decr_by_one   = (IS_FWFT == 1)? read_allow_dc : read_allow;
+      assign incr_by_ratio = write_allow;
+
+      always @(posedge CLK or posedge rst_i) begin
+       if (rst_i)
+         count_dc  <= #`TCQ 0;
+       else if (srst_wrst_busy)
+         count_dc  <= #`TCQ 0;
+       else begin
+\t if (decr_by_one) begin
+\t   if (!incr_by_ratio) 
+            count_dc <= #`TCQ count_dc - 1;
+           else
+\t    count_dc <= #`TCQ count_dc - 1  + ratio ;
+\t end
+\t else begin
+\t   if (!incr_by_ratio) 
+            count_dc <= #`TCQ count_dc ;
+           else
+\t    count_dc <= #`TCQ count_dc + ratio ;
+\tend
+       end
+       end
+
+       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
+       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
+
+    end endgenerate
+
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd 
+      assign ratio         = C_DEPTH_RATIO_WR;
+      assign incr_by_one   = write_allow;
+      assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
+
+      always @(posedge CLK or posedge rst_i) begin
+       if (rst_i)
+         count_dc  <= #`TCQ 0;
+       else if (srst_wrst_busy)
+         count_dc  <= #`TCQ 0;
+       else begin
+\t if (incr_by_one) begin
+\t   if (!decr_by_ratio) 
+            count_dc <= #`TCQ count_dc + 1;
+           else
+\t    count_dc <= #`TCQ count_dc + 1  - ratio ;
+\t end
+\t else begin
+\t   if (!decr_by_ratio) 
+            count_dc <= #`TCQ count_dc ;
+           else
+\t    count_dc <= #`TCQ count_dc - ratio ;
+\tend
+       end
+       end
+
+       assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
+       assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
+
+    end endgenerate
+
+
+
+
+
+
+   //-----------------------------------------------------------------------------
+   // Generate WR_ACK flag
+   //-----------------------------------------------------------------------------
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i)
+       ideal_wr_ack  <= 1\'b0;
+     else if (srst_wrst_busy)
+       ideal_wr_ack  <= #`TCQ 1\'b0;
+     else if (WR_EN & ~full_i)
+       ideal_wr_ack  <= #`TCQ 1\'b1;
+     else
+       ideal_wr_ack  <= #`TCQ 1\'b0;
+    end
+
+   //-----------------------------------------------------------------------------
+   // Generate VALID flag
+   //-----------------------------------------------------------------------------
+   always @(posedge CLK or posedge rst_i) begin
+     if (rst_i)
+       ideal_valid  <= 1\'b0;
+     else if (srst_rrst_busy)
+       ideal_valid  <= #`TCQ 1\'b0;
+     else if (RD_EN & ~empty_i)
+       ideal_valid  <= #`TCQ 1\'b1;
+     else
+       ideal_valid  <= #`TCQ 1\'b0;
+    end
+
+
+   //-----------------------------------------------------------------------------
+   // Generate ALMOST_FULL flag
+   //-----------------------------------------------------------------------------
+   //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
+
+     wire                 fcomp2;
+     wire                 going_afull;
+     wire                 leaving_afull;
+     wire                 ram_afull_comb;
+
+
+   assign fcomp2         = (adj_rd_pntr_wr == (wr_pntr + 2\'h2));
+
+    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
+     assign going_afull    = (fcomp2 & write_allow & ~read_allow);
+     assign leaving_afull  = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
+    end endgenerate
+
+    // Write data width is bigger than read data width
+    // Write depth is smaller than read depth
+    // One write could be equal to 2 or 4 or 8 reads
+    generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
+      assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
+      assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
+    end endgenerate
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp 
+      assign going_afull = (fcomp2 & write_allow & ~read_allow);
+      assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
+    end endgenerate
+
+     assign ram_afull_comb  = going_afull | (~leaving_afull & almost_full_i);
+
+
+     always @(posedge CLK or posedge RST_FULL_FF) begin
+       if (RST_FULL_FF)
+         almost_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else if (srst_wrst_busy)
+         almost_full_i   <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else
+         almost_full_i   <= #`TCQ ram_afull_comb;
+      end
+  // end endgenerate // gaf_ss
+
+   //-----------------------------------------------------------------------------
+   // Generate ALMOST_EMPTY flag
+   //-----------------------------------------------------------------------------
+   //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
+
+     wire                 ecomp2;
+     wire                 going_aempty;
+     wire                 leaving_aempty;
+     wire                 ram_aempty_comb;
+      
+     assign ecomp2          = (adj_wr_pntr_rd == (rd_pntr + 2\'h2));
+   
+    generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
+     assign going_aempty    = (ecomp2 & ~write_allow & read_allow);
+     assign leaving_aempty  = (ecomp1 & write_allow & ~read_allow);
+    end endgenerate
+
+    generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
+      assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
+      assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
+    end endgenerate
+  
+   generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp 
+      assign going_aempty = (ecomp2 & ~write_allow & read_allow);
+      assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
+    end endgenerate
+
+
+     assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
+
+     always @(posedge CLK or posedge rst_i) begin
+       if (rst_i)
+         almost_empty_i  <= 1\'b1;
+       else if (srst_rrst_busy)
+         almost_empty_i  <= #`TCQ 1\'b1;
+       else
+         almost_empty_i  <= #`TCQ ram_aempty_comb;
+      end
+  // end endgenerate // gae_ss
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL
+   //-----------------------------------------------------------------------------
+
+   localparam  C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? 
+                                  C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT 
+                                  C_PROG_FULL_THRESH_ASSERT_VAL; // STD
+   localparam  C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? 
+                                  C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
+                                  C_PROG_FULL_THRESH_NEGATE_VAL; // STD
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL for single programmable threshold constant
+   //-----------------------------------------------------------------------------
+   wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;   
+   generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
+     always @(posedge CLK or posedge RST_FULL_FF) begin
+       if (RST_FULL_FF && C_HAS_RST)
+         prog_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else begin 
+         if (srst_wrst_busy)
+           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (RST_FULL_GEN)
+          prog_full_i <= #`TCQ 1\'b0;
+         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
+           prog_full_i <= #`TCQ 1\'b1;
+         else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
+           prog_full_i <= #`TCQ 1\'b0;
+         else
+           prog_full_i <= #`TCQ prog_full_i;
+       end
+       else begin
+       if (RST_FULL_GEN)
+        prog_full_i <= #`TCQ 1\'b0;
+       else if (~RST_FULL_GEN ) begin 
+        if (diff_pntr>= C_PF_ASSERT_VAL )
+          prog_full_i <= #`TCQ 1\'b1;
+        else if  ((diff_pntr) < C_PF_ASSERT_VAL )
+        prog_full_i <= #`TCQ 1\'b0;
+       else
+         prog_full_i <= #`TCQ 1\'b0;
+        end 
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+       end
+      end
+     end
+   end endgenerate // single_pf_const
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL for multiple programmable threshold constants
+   //-----------------------------------------------------------------------------
+   generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
+     always @(posedge CLK or posedge RST_FULL_FF) begin
+       //if (RST_FULL_FF)
+       if (RST_FULL_FF && C_HAS_RST)
+         prog_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else begin
+         if (srst_wrst_busy)
+           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (RST_FULL_GEN)
+           prog_full_i <= #`TCQ 1\'b0;
+         else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
+           prog_full_i <= #`TCQ 1\'b1;
+         else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
+           prog_full_i <= #`TCQ 1\'b0;
+         else
+           prog_full_i <= #`TCQ prog_full_i;
+       end
+       else begin
+       if (RST_FULL_GEN)
+        prog_full_i <= #`TCQ 1\'b0;
+       else if (~RST_FULL_GEN ) begin 
+        if (diff_pntr >= C_PF_ASSERT_VAL )
+          prog_full_i <= #`TCQ 1\'b1;
+       else if  (diff_pntr < C_PF_NEGATE_VAL)
+         prog_full_i <= #`TCQ 1\'b0;
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+        end 
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+       end
+      end
+     end
+   end endgenerate //multiple_pf_const
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL for single programmable threshold input port
+   //-----------------------------------------------------------------------------
+   wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? 
+                                               PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
+                                               PROG_FULL_THRESH; // STD
+   generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
+
+     always @(posedge CLK or posedge RST_FULL_FF) begin//0
+       //if (RST_FULL_FF)
+       if (RST_FULL_FF && C_HAS_RST)
+         prog_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else begin //1
+         if (srst_wrst_busy)
+           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else if (IS_ASYMMETRY == 0) begin//2 
+         if (RST_FULL_GEN)
+           prog_full_i <= #`TCQ 1\'b0;
+         else if (~almost_full_i) begin//3
+           if (diff_pntr > pf3_assert_val)
+             prog_full_i <= #`TCQ 1\'b1;
+           else if (diff_pntr == pf3_assert_val) begin//4
+             if (read_only_q)
+               prog_full_i <= #`TCQ 1\'b0;
+             else
+               prog_full_i <= #`TCQ 1\'b1;
+           end else//4
+             prog_full_i <= #`TCQ 1\'b0;
+         end else//3
+           prog_full_i <= #`TCQ prog_full_i;
+       end //2
+       else begin//5
+       if (RST_FULL_GEN)
+        prog_full_i <= #`TCQ 1\'b0;
+       else if (~full_i ) begin//6 
+        if (diff_pntr >= pf3_assert_val )
+          prog_full_i <= #`TCQ 1\'b1;
+        else if  (diff_pntr < pf3_assert_val) begin//7
+         prog_full_i <= #`TCQ 1\'b0;
+       end//7
+       end//6
+      else
+           prog_full_i <= #`TCQ prog_full_i;
+       end//5
+     end//1
+     end//0
+   end endgenerate //single_pf_input
+  
+   //-----------------------------------------------------------------------------
+   // Generate PROG_FULL for multiple programmable threshold input ports
+   //-----------------------------------------------------------------------------
+   wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? 
+                                               (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
+                                               PROG_FULL_THRESH_ASSERT; // STD
+   wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? 
+                                               (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
+                                               PROG_FULL_THRESH_NEGATE; // STD
+
+   generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
+     always @(posedge CLK or posedge RST_FULL_FF) begin
+       if (RST_FULL_FF && C_HAS_RST)
+         prog_full_i   <= C_FULL_FLAGS_RST_VAL;
+       else begin
+         if (srst_wrst_busy)
+           prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (RST_FULL_GEN)
+           prog_full_i <= #`TCQ 1\'b0;
+         else if (~almost_full_i) begin
+           if (diff_pntr >= pf_assert_val)
+             prog_full_i <= #`TCQ 1\'b1;
+           else if ((diff_pntr == pf_negate_val && read_only_q) ||
+                  diff_pntr < pf_negate_val)
+             prog_full_i <= #`TCQ 1\'b0;
+           else
+             prog_full_i <= #`TCQ prog_full_i;
+         end else
+           prog_full_i <= #`TCQ prog_full_i;
+       end
+       else begin
+       if (RST_FULL_GEN)
+        prog_full_i <= #`TCQ 1\'b0;
+       else if (~full_i ) begin 
+        if (diff_pntr >= pf_assert_val )
+          prog_full_i <= #`TCQ 1\'b1;
+       else if (diff_pntr < pf_negate_val) 
+         prog_full_i <= #`TCQ 1\'b0;
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+        end 
+       else
+         prog_full_i <= #`TCQ prog_full_i;
+       end
+
+     end
+   end
+   end endgenerate //multiple_pf_inputs
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY
+   //-----------------------------------------------------------------------------
+   localparam  C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
+                                  C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
+                                  C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
+   localparam  C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
+                                  C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
+                                  C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY for single programmable threshold constant
+   //-----------------------------------------------------------------------------
+   generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
+     always @(posedge CLK or posedge rst_i) begin
+       //if (rst_i) 
+       if (rst_i && C_HAS_RST) 
+         prog_empty_i  <= 1\'b1;
+       else begin
+         if (srst_rrst_busy) 
+           prog_empty_i <= #`TCQ 1\'b1;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
+           prog_empty_i <= #`TCQ 1\'b1;
+         else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
+           prog_empty_i <= #`TCQ 1\'b0;
+         else
+           prog_empty_i <= #`TCQ prog_empty_i;
+       end
+       else begin
+       if (~rst_i ) begin 
+        if (diff_pntr_pe <= C_PE_ASSERT_VAL)
+          prog_empty_i <= #`TCQ 1\'b1;
+        else if  (diff_pntr_pe > C_PE_ASSERT_VAL)
+         prog_empty_i <= #`TCQ 1\'b0;
+        end 
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+       end
+     end
+     end
+   end endgenerate // single_pe_const
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY for multiple programmable threshold constants
+   //-----------------------------------------------------------------------------
+   generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
+     always @(posedge CLK or posedge rst_i) begin
+       //if (rst_i)
+       if (rst_i && C_HAS_RST) 
+         prog_empty_i  <= 1\'b1;
+       else begin
+         if (srst_rrst_busy)
+           prog_empty_i <= #`TCQ 1\'b1;
+       else if (IS_ASYMMETRY == 0) begin 
+         if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
+           prog_empty_i <= #`TCQ 1\'b1;
+         else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
+           prog_empty_i <= #`TCQ 1\'b0;
+         else
+           prog_empty_i <= #`TCQ prog_empty_i;
+       end
+       else begin
+       if (~rst_i ) begin 
+        if (diff_pntr_pe <= C_PE_ASSERT_VAL )
+          prog_empty_i <= #`TCQ 1\'b1;
+        else if (diff_pntr_pe > C_PE_NEGATE_VAL) 
+         prog_empty_i <= #`TCQ 1\'b0;
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+        end 
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+       end
+
+     end
+
+     end
+   end endgenerate //multiple_pe_const
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY for single programmable threshold input port
+   //-----------------------------------------------------------------------------
+   wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
+                                               (PROG_EMPTY_THRESH -2) : // FWFT
+                                                PROG_EMPTY_THRESH; // STD
+   generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
+     always @(posedge CLK or posedge rst_i) begin
+       //if (rst_i)
+       if (rst_i && C_HAS_RST) 
+         prog_empty_i  <= 1\'b1;
+       else begin
+         if (srst_rrst_busy)
+           prog_empty_i <= #`TCQ 1\'b1;
+       else if (IS_ASYMMETRY == 0) begin 
+          if (~almost_full_i) begin
+           if (diff_pntr_pe < pe3_assert_val)
+             prog_empty_i <= #`TCQ 1\'b1;
+           else if (diff_pntr_pe == pe3_assert_val) begin
+             if (write_only_q)
+               prog_empty_i <= #`TCQ 1\'b0;
+             else
+               prog_empty_i <= #`TCQ 1\'b1;
+           end else
+             prog_empty_i <= #`TCQ 1\'b0;
+         end else
+           prog_empty_i <= #`TCQ prog_empty_i;
+       end
+       else begin
+        if (diff_pntr_pe <= pe3_assert_val )
+          prog_empty_i <= #`TCQ 1\'b1;
+        else if  (diff_pntr_pe > pe3_assert_val)
+         prog_empty_i <= #`TCQ 1\'b0;
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+        end 
+     end
+
+     end
+   end endgenerate // single_pe_input
+
+   //-----------------------------------------------------------------------------
+   // Generate PROG_EMPTY for multiple programmable threshold input ports
+   //-----------------------------------------------------------------------------
+   wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
+                                               (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
+                                                PROG_EMPTY_THRESH_ASSERT; // STD
+   wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
+                                               (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
+                                                PROG_EMPTY_THRESH_NEGATE; // STD
+   generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
+     always @(posedge CLK or posedge rst_i) begin
+       //if (rst_i)
+       if (rst_i && C_HAS_RST) 
+         prog_empty_i  <= 1\'b1;
+       else begin
+         if (srst_rrst_busy)
+           prog_empty_i <= #`TCQ 1\'b1;
+      else if (IS_ASYMMETRY == 0) begin 
+          if (~almost_full_i) begin
+           if (diff_pntr_pe <= pe4_assert_val)
+             prog_empty_i <= #`TCQ 1\'b1;
+           else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || 
+                     (diff_pntr_pe > pe4_negate_val)) begin
+             prog_empty_i <= #`TCQ 1\'b0;
+           end else
+             prog_empty_i <= #`TCQ prog_empty_i;
+         end else
+           prog_empty_i <= #`TCQ prog_empty_i;
+       end
+       else begin
+        if (diff_pntr_pe <= pe4_assert_val )
+          prog_empty_i <= #`TCQ 1\'b1;
+        else if (diff_pntr_pe > pe4_negate_val) 
+         prog_empty_i <= #`TCQ 1\'b0;
+       else
+         prog_empty_i <= #`TCQ prog_empty_i;
+        end 
+     end
+     end
+   end endgenerate // multiple_pe_inputs
+
+endmodule // fifo_generator_v13_1_3_bhv_ver_ss
+
+
+
+/**************************************************************************
+ * First-Word Fall-Through module (preload 0)
+ **************************************************************************/
+module fifo_generator_v13_1_3_bhv_ver_preload0
+  #(
+    parameter  C_DOUT_RST_VAL            = """",
+    parameter  C_DOUT_WIDTH              = 8,
+    parameter  C_HAS_RST                 = 0,
+    parameter  C_ENABLE_RST_SYNC         = 0,
+    parameter  C_HAS_SRST                = 0,
+    parameter  C_USE_EMBEDDED_REG        = 0,
+    parameter  C_EN_SAFETY_CKT           = 0, 
+    parameter  C_USE_DOUT_RST            = 0,
+    parameter  C_USE_ECC                 = 0,
+    parameter  C_USERVALID_LOW           = 0,
+    parameter  C_USERUNDERFLOW_LOW       = 0,
+    parameter  C_MEMORY_TYPE             = 0,
+    parameter  C_FIFO_TYPE               = 0
+  )
+  (
+    //Inputs
+    input                          SAFETY_CKT_RD_RST,
+    input                          RD_CLK,
+    input                          RD_RST,
+    input                          SRST,
+    input                          WR_RST_BUSY,
+    input                          RD_RST_BUSY,
+    input                          RD_EN,
+    input                          FIFOEMPTY,
+    input       [C_DOUT_WIDTH-1:0] FIFODATA,
+    input                          FIFOSBITERR,
+    input                          FIFODBITERR,
+   
+    //Outputs
+    output reg  [C_DOUT_WIDTH-1:0] USERDATA,
+    output                         USERVALID,
+    output                         USERUNDERFLOW,
+    output                         USEREMPTY,
+    output                         USERALMOSTEMPTY,
+    output                         RAMVALID,
+    output                         FIFORDEN,
+    output reg                     USERSBITERR,
+    output reg                     USERDBITERR,
+    output reg                     STAGE2_REG_EN,
+    output                         fab_read_data_valid_i_o,
+    output                         read_data_valid_i_o,
+    output                         ram_valid_i_o,
+    output      [1:0]              VALID_STAGES 
+  );
+ //Internal signals
+ wire                      preloadstage1;
+ wire                      preloadstage2;
+ reg                       ram_valid_i;
+ reg                       fab_valid;
+ reg                       read_data_valid_i;
+ reg                       fab_read_data_valid_i;
+ reg                       fab_read_data_valid_i_1;
+ reg                       ram_valid_i_d;
+ reg                       read_data_valid_i_d;
+ reg                       fab_read_data_valid_i_d;
+ wire                      ram_regout_en;
+ reg                       ram_regout_en_d1;
+ reg                       ram_regout_en_d2;
+ wire                      fab_regout_en;
+ wire                      ram_rd_en;
+ reg                       empty_i        = 1\'b1;
+ reg                       empty_sckt     = 1\'b1;
+ reg                       sckt_rrst_q    = 1\'b0;
+ reg                       sckt_rrst_done = 1\'b0;
+ reg                       empty_q        = 1\'b1;
+ reg                       rd_en_q        = 1\'b0;
+ reg                       almost_empty_i = 1\'b1;
+ reg                       almost_empty_q = 1\'b1;
+ wire                      rd_rst_i;
+ wire                      srst_i;
+ reg  [C_DOUT_WIDTH-1:0]   userdata_both;
+ wire                      uservalid_both;
+ wire                      uservalid_one;
+ reg                       user_sbiterr_both = 1\'b0;
+ reg                       user_dbiterr_both = 1\'b0;
+  
+assign ram_valid_i_o = ram_valid_i;
+assign read_data_valid_i_o = read_data_valid_i;
+assign fab_read_data_valid_i_o = fab_read_data_valid_i; 
+
+
+
+/*************************************************************************
+* FUNCTIONS
+*************************************************************************/
+
+   /*************************************************************************
+    * hexstr_conv
+    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+    ***********************************************************************/
+    function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = \'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8\'b00000000 :
+          begin
+            bin = 4\'b0000;
+            i = -1;
+          end
+          8\'b00110000 : bin = 4\'b0000;
+          8\'b00110001 : bin = 4\'b0001;
+          8\'b00110010 : bin = 4\'b0010;
+          8\'b00110011 : bin = 4\'b0011;
+          8\'b00110100 : bin = 4\'b0100;
+          8\'b00110101 : bin = 4\'b0101;
+          8\'b00110110 : bin = 4\'b0110;
+          8\'b00110111 : bin = 4\'b0111;
+          8\'b00111000 : bin = 4\'b1000;
+          8\'b00111001 : bin = 4\'b1001;
+          8\'b01000001 : bin = 4\'b1010;
+          8\'b01000010 : bin = 4\'b1011;
+          8\'b01000011 : bin = 4\'b1100;
+          8\'b01000100 : bin = 4\'b1101;
+          8\'b01000101 : bin = 4\'b1110;
+          8\'b01000110 : bin = 4\'b1111;
+          8\'b01100001 : bin = 4\'b1010;
+          8\'b01100010 : bin = 4\'b1011;
+          8\'b01100011 : bin = 4\'b1100;
+          8\'b01100100 : bin = 4\'b1101;
+          8\'b01100101 : bin = 4\'b1110;
+          8\'b01100110 : bin = 4\'b1111;
+          default :
+          begin
+            bin = 4\'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_DOUT_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+   
+   //*************************************************************************
+   //  Set power-on states for regs
+   //*************************************************************************
+   initial begin
+      ram_valid_i       = 1\'b0;
+      fab_valid         = 1\'b0;
+      read_data_valid_i = 1\'b0;
+      fab_read_data_valid_i = 1\'b0;
+      fab_read_data_valid_i_1 = 1\'b0;
+      USERDATA          = hexstr_conv(C_DOUT_RST_VAL);
+      userdata_both          = hexstr_conv(C_DOUT_RST_VAL);
+      USERSBITERR       = 1\'b0;
+      USERDBITERR       = 1\'b0;
+      user_sbiterr_both = 1\'b0;
+      user_dbiterr_both = 1\'b0;
+   end //initial
+
+   //***************************************************************************
+   //  connect up optional reset
+   //***************************************************************************
+   assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
+   assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
+
+   reg  sckt_rd_rst_fwft = 1\'b0;
+   reg  fwft_rst_done_i  = 1\'b0;
+   wire fwft_rst_done;
+   assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1\'b1;
+   always @ (posedge RD_CLK) begin
+     sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
+   end
+
+   always @ (posedge rd_rst_i or posedge RD_CLK) begin
+     if (rd_rst_i)
+       fwft_rst_done_i  <= 1\'b0;
+     else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
+       fwft_rst_done_i  <= #`TCQ 1\'b1;
+   end
+
+   localparam INVALID             = 0;
+   localparam STAGE1_VALID        = 2;
+   localparam STAGE2_VALID        = 1;
+   localparam BOTH_STAGES_VALID   = 3;
+
+   reg  [1:0] curr_fwft_state = INVALID;
+   reg  [1:0] next_fwft_state = INVALID;
+
+
+generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
+         always @* begin
+         case (curr_fwft_state)
+            INVALID: begin
+               if (~FIFOEMPTY)
+                  next_fwft_state     <= STAGE1_VALID;
+               else
+                  next_fwft_state     <= INVALID;
+               end
+            STAGE1_VALID: begin
+               if (FIFOEMPTY)
+                  next_fwft_state     <= STAGE2_VALID;
+               else
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               end
+            STAGE2_VALID: begin
+               if (FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= INVALID;
+               else if (~FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= STAGE1_VALID;
+               else if (~FIFOEMPTY && ~RD_EN)
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               else
+                  next_fwft_state     <= STAGE2_VALID;
+               end
+            BOTH_STAGES_VALID: begin
+               if (FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= STAGE2_VALID;
+               else if (~FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               else
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               end
+            default: next_fwft_state     <= INVALID;
+         endcase
+      end
+
+      always @ (posedge rd_rst_i or posedge RD_CLK) begin
+         if (rd_rst_i && C_EN_SAFETY_CKT == 0)
+            curr_fwft_state  <= INVALID;
+         else if (srst_i)
+            curr_fwft_state  <= #`TCQ INVALID;
+         else
+            curr_fwft_state  <= #`TCQ next_fwft_state;
+      end
+
+      always @* begin
+         case (curr_fwft_state)
+            INVALID:           STAGE2_REG_EN <= 1\'b0;
+            STAGE1_VALID:      STAGE2_REG_EN <= 1\'b1;
+            STAGE2_VALID:      STAGE2_REG_EN <= 1\'b0;
+            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
+            default:           STAGE2_REG_EN <= 1\'b0;
+         endcase
+      end
+
+ 
+    assign VALID_STAGES = curr_fwft_state;
+
+     //***************************************************************************
+     //  preloadstage2 indicates that stage2 needs to be updated. This is true
+     //  whenever read_data_valid is false, and RAM_valid is true.
+     //***************************************************************************
+     
+     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
+    
+
+     //***************************************************************************
+     //  preloadstage1 indicates that stage1 needs to be updated. This is true
+     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
+     //  false (indicating that Stage1 needs updating), or preloadstage2 is active
+     //  (indicating that Stage2 is going to update, so Stage1, therefore, mu'b'st
+     //  also be updated to keep it valid.
+     //***************************************************************************
+     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
+  
+     //***************************************************************************
+     // Calculate RAM_REGOUT_EN
+     //  The output registers are controlled by the ram_regout_en signal.
+     //  These registers should be updated either when the output in Stage2 is
+     //  invalid (preloadstage2), OR when the user is reading, in which case the
+     //  Stage2 value will go invalid unless it is replenished.
+     //***************************************************************************
+     assign ram_regout_en = preloadstage2;
+
+     //***************************************************************************
+     // Calculate RAM_RD_EN
+     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
+     //  update the value in Stage1.
+     //   One case when this happens is when preloadstage1=true, which indicates
+     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically
+     //  be updated.
+     //   The other case is when the user is reading from the FIFO, which 
+     // guarantees that Stage1 or Stage2 will be invalid on the next clock 
+     // cycle, unless it is replinished by data from the memory. So, as long 
+     // as the RAM has data in it, a read of the RAM should occur.
+     //***************************************************************************
+     assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
+   end
+endgenerate // gnll_fifo
+
+   reg curr_state         = 0;
+   reg next_state         = 0;
+   reg leaving_empty_fwft = 0;
+   reg going_empty_fwft   = 0;
+   reg empty_i_q          = 0;
+   reg ram_rd_en_fwft     = 0;
+   generate if (C_FIFO_TYPE == 2) begin : gll_fifo
+     always @* begin // FSM fo FWFT
+       case (curr_state)
+         1\'b0: begin
+           if (~FIFOEMPTY)
+             next_state <= 1\'b1;
+           else
+             next_state <= 1\'b0;
+           end
+         1\'b1: begin
+           if (FIFOEMPTY && RD_EN)
+             next_state <= 1\'b0;
+           else
+             next_state <= 1\'b1;
+           end
+         default: next_state <= 1\'b0;
+       endcase
+     end
+
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i) begin
+           empty_i       <= 1\'b1;
+           empty_i_q     <= 1\'b1;
+           ram_valid_i   <= 1\'b0;
+        end else if (srst_i) begin
+           empty_i       <= #`TCQ 1\'b1;
+           empty_i_q     <= #`TCQ 1\'b1;
+           ram_valid_i   <= #`TCQ 1\'b0;
+        end else begin
+           empty_i       <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
+           empty_i_q     <= #`TCQ FIFOEMPTY;
+           ram_valid_i   <= #`TCQ next_state;
+        end
+     end //always
+
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
+           curr_state    <= 1\'b0;
+        end else if (srst_i) begin
+           curr_state    <= #`TCQ 1\'b0;
+        end else begin
+           curr_state    <= #`TCQ next_state;
+        end
+     end //always
+
+     wire                  fe_of_empty; 
+     assign fe_of_empty   = empty_i_q & ~FIFOEMPTY;
+
+     always @* begin // Finding leaving empty
+       case (curr_state)
+         1\'b0:    leaving_empty_fwft <= fe_of_empty;
+         1\'b1:    leaving_empty_fwft <= 1\'b1;
+         default: leaving_empty_fwft <= 1\'b0;
+       endcase
+     end
+
+     always @* begin // Finding going empty
+       case (curr_state)
+         1\'b1:    going_empty_fwft <= FIFOEMPTY & RD_EN;
+         default: going_empty_fwft <= 1\'b0;
+       endcase
+     end
+
+     always @* begin // Generating FWFT rd_en
+       case (curr_state)
+         1\'b0:    ram_rd_en_fwft <= ~FIFOEMPTY;
+         1\'b1:    ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
+         default: ram_rd_en_fwft <= 1\'b0;
+       endcase
+     end
+
+     assign ram_regout_en = ram_rd_en_fwft;
+     //assign ram_regout_en_d1 = ram_rd_en_fwft;
+     //assign ram_regout_en_d2 = ram_rd_en_fwft;
+     assign ram_rd_en     = ram_rd_en_fwft;
+   end endgenerate // gll_fifo
+
+
+   //***************************************************************************
+   // Calculate RAMVALID_P0_OUT
+   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
+   //
+   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then
+   //   RAMVALID_P0_OUT is certainly going to be true.
+   //   If the RAM is not being read from, but the output registers are being
+   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
+   //   therefore causing RAMVALID_P0_OUT to be false.
+   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.
+   //***************************************************************************
+   // PROCESS regout_valid
+   generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin  
+        if (rd_rst_i) begin 
+           // asynchronous reset (active high)
+           ram_valid_i     <= #`TCQ 1\'b0;
+        end else begin
+           if (srst_i) begin 
+              // synchronous reset (active high)
+              ram_valid_i     <= #`TCQ 1\'b0;
+           end else begin
+              if (ram_rd_en == 1\'b1) begin
+                 ram_valid_i   <= #`TCQ 1\'b1;
+              end else begin
+                 if (ram_regout_en == 1\'b1)
+                   ram_valid_i <= #`TCQ 1\'b0;
+                 else
+                   ram_valid_i <= #`TCQ ram_valid_i;
+              end
+           end //srst_i
+        end //rd_rst_i
+     end //always
+   end endgenerate // gnll_fifo_ram_valid
+   
+   //***************************************************************************
+   // Calculate READ_DATA_VALID
+   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
+   //  Stage2 has valid data whenever Stage1 had valid data and 
+   //  ram_regout_en_i=1, such that the data in Stage1 is propogated 
+   //  into Stage2.
+   //***************************************************************************
+  
+ generate if(C_USE_EMBEDDED_REG < 3) begin
+ always @ (posedge RD_CLK or posedge rd_rst_i) begin
+      if (rd_rst_i)
+        read_data_valid_i <= #`TCQ 1\'b0;
+      else if (srst_i)
+        read_data_valid_i <= #`TCQ 1\'b0;
+      else
+        read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
+   end //always
+end 
+endgenerate
+
+   
+   
+   //**************************************************************************
+   // Calculate EMPTY
+   //  Defined as the inverse of READ_DATA_VALID
+   //
+   // Description:
+   //
+   //  If read_data_valid_i indicates that the output is not valid,
+   // and there is no valid data on the output of the ram to preload it
+   // with, then we will report empty.
+   //
+   //  If there is no valid data on the output of the ram and we are
+   // reading, then the FIFO will go empty.
+   //
+   //**************************************************************************
+   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i) begin
+           // asynchronous reset (active high)
+           empty_i <= #`TCQ 1\'b1;
+        end else begin
+           if (srst_i) begin
+              // synchronous reset (active high)
+              empty_i <= #`TCQ 1\'b1;
+           end else begin
+              // rising clock edge
+              empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
+           end
+        end
+     end //always
+   end endgenerate // gnll_fifo_empty
+   
+   // Register RD_EN from user to calculate USERUNDERFLOW.
+   // Register empty_i to calculate USERUNDERFLOW.
+   always @ (posedge RD_CLK) begin
+     rd_en_q <= #`TCQ RD_EN;
+     empty_q <= #`TCQ empty_i;
+   end //always
+   
+   
+   //***************************************************************************
+   // Calculate user_almost_empty
+   //  user_almost_empty is defined such that, unless more words are written
+   //  to the FIFO, the next read will cause the FIFO to go EMPTY.
+   //
+   //  In most cases, whenever the output registers are updated (due to a user
+   // read or a preload condition), then user_almost_empty will update to
+   // whatever RAM_EMPTY is.
+   //
+   //  The exception is when the output is valid, the user is not reading, and
+   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the
+   // memory, so we need to make sure user_almost_empty deasserts properly under
+   // this condition.
+   //***************************************************************************
+ generate if ( C_USE_EMBEDDED_REG < 3) begin
+  always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+        if (rd_rst_i) begin         // asynchronous reset (active high)
+             almost_empty_i <= #`TCQ 1\'b1;
+             almost_empty_q <= #`TCQ 1\'b1;
+        end else begin // rising clock edge
+           if (srst_i) begin          // synchronous reset (active high)
+              almost_empty_i <= #`TCQ 1\'b1;
+              almost_empty_q <= #`TCQ 1\'b1;
+           end else begin
+              if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
+                 almost_empty_i <= #`TCQ FIFOEMPTY;
+              end
+              almost_empty_q   <= #`TCQ empty_i;
+           end
+        end
+     end //always
+end
+endgenerate
+   
+   
+     
+  // BRAM resets synchronously
+ generate 
+        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
+   always @ ( posedge rd_rst_i)
+     begin
+        if (rd_rst_i || srst_i) begin
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
+           @(posedge RD_CLK)
+            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+        end
+     end //always
+
+ 
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+        if (rd_rst_i) begin //asynchronous reset (active high)
+          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+            USERSBITERR    <= #`TCQ 0;
+            USERDBITERR    <= #`TCQ 0;
+          end
+          // DRAM resets asynchronously
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)
+             USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+        end
+        end  else begin // rising clock edge
+          if (srst_i) begin
+            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+              USERSBITERR  <= #`TCQ 0;
+              USERDBITERR  <= #`TCQ 0;
+            end
+            if (C_USE_DOUT_RST == 1) begin
+              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+          end
+          end  else if (fwft_rst_done) begin
+            if (ram_regout_en) begin
+               USERDATA     <= #`TCQ FIFODATA;
+               USERSBITERR  <= #`TCQ FIFOSBITERR;
+               USERDBITERR  <= #`TCQ FIFODBITERR;
+            end
+          end
+        end
+     end //always
+   end   //if
+  endgenerate
+//safety ckt with one register
+generate
+       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+         
+        always@(posedge RD_CLK)
+          begin
+          rst_delayed_sft1 <= #`TCQ rd_rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+          end
+        always @ (posedge RD_CLK)
+     begin
+        if (rd_rst_i || srst_i) begin
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1\'b1) begin
+            @(posedge RD_CLK)
+            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+          end
+        end
+     end //always
+ 
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+        if (rd_rst_i) begin //asynchronous reset (active high)
+          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+            USERSBITERR    <= #`TCQ 0;
+            USERDBITERR    <= #`TCQ 0;
+          end
+          // DRAM resets asynchronously
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)
+          //@(posedge RD_CLK)
+            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+         end 
+       end
+        else begin // rising clock edge
+          if (srst_i) begin
+            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+              USERSBITERR  <= #`TCQ 0;
+              USERDBITERR  <= #`TCQ 0;
+            end
+            if (C_USE_DOUT_RST == 1) begin
+            //  @(posedge RD_CLK)
+              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+          end
+          end else if (fwft_rst_done) begin
+            if (ram_regout_en == 1\'b1 && rd_rst_i == 1\'b0) begin
+               USERDATA     <= #`TCQ FIFODATA;
+               USERSBITERR  <= #`TCQ FIFOSBITERR;
+               USERDBITERR  <= #`TCQ FIFODBITERR;
+            end          
+          end
+        end
+       end //always
+  end //if
+endgenerate
+
+
+generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
+         
+
+      always @* begin
+         case (curr_fwft_state)
+            INVALID: begin
+               if (~FIFOEMPTY)
+                  next_fwft_state     <= STAGE1_VALID;
+               else
+                  next_fwft_state     <= INVALID;
+               end
+            STAGE1_VALID: begin
+               if (FIFOEMPTY)
+                  next_fwft_state     <= STAGE2_VALID;
+               else
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               end
+            STAGE2_VALID: begin
+               if (FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= INVALID;
+               else if (~FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= STAGE1_VALID;
+               else if (~FIFOEMPTY && ~RD_EN)
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               else
+                  next_fwft_state     <= STAGE2_VALID;
+               end
+            BOTH_STAGES_VALID: begin
+               if (FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= STAGE2_VALID;
+               else if (~FIFOEMPTY && RD_EN)
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               else
+                  next_fwft_state     <= BOTH_STAGES_VALID;
+               end
+            default: next_fwft_state     <= INVALID;
+         endcase
+      end
+
+      always @ (posedge rd_rst_i or posedge RD_CLK) begin
+         if (rd_rst_i && C_EN_SAFETY_CKT == 0)
+            curr_fwft_state  <= INVALID;
+         else if (srst_i)
+            curr_fwft_state  <= #`TCQ INVALID;
+         else
+            curr_fwft_state  <= #`TCQ next_fwft_state;
+      end
+
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
+            if (rd_rst_i == 1) begin
+                ram_regout_en_d1 <= #`TCQ 1\'b0;
+            end
+            else begin
+                 if (srst_i == 1\'b1) 
+                 ram_regout_en_d1 <= #`TCQ 1\'b0;
+                 else
+                 ram_regout_en_d1 <= #`TCQ ram_regout_en;
+                 end
+            end //always
+   //  assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
+       assign fab_regout_en = ((ram_valid_i == 1\'b0 || ram_valid_i == 1\'b1) && read_data_valid_i == 1\'b1 && fab_read_data_valid_i == 1\'b0 )? 1\'b1: ((ram_valid_i == 1\'b0 || ram_valid_i == 1\'b1) && read_data_valid_i == 1\'b1 && fab_read_data_valid_i == 1\'b1) ? RD_EN : 1\'b0;
+
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
+            if (rd_rst_i == 1) begin
+                ram_regout_en_d2 <= #`TCQ 1\'b0;
+            end
+            else begin
+                 if (srst_i == 1\'b1) 
+                 ram_regout_en_d2 <= #`TCQ 1\'b0;
+                 else
+                 ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
+                 end
+            end //always
+
+    
+
+      always @* begin
+         case (curr_fwft_state)
+            INVALID:           STAGE2_REG_EN <= 1\'b0;
+            STAGE1_VALID:      STAGE2_REG_EN <= 1\'b1;
+            STAGE2_VALID:      STAGE2_REG_EN <= 1\'b0;
+            BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
+            default:           STAGE2_REG_EN <= 1\'b0;
+         endcase
+      end
+
+     always @ (posedge RD_CLK) begin
+        ram_valid_i_d <= #`TCQ ram_valid_i;
+        read_data_valid_i_d <= #`TCQ read_data_valid_i;
+        fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
+
+     end
+    assign VALID_STAGES = curr_fwft_state;
+
+     //***************************************************************************
+     //  preloadstage2 indicates that stage2 needs to be updated. This is true
+     //  whenever read_data_valid is false, and RAM_valid is true.
+     //***************************************************************************
+    
+     assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
+
+     //***************************************************************************
+     //  preloadstage1 indicates that stage1 needs to be updated. This is true
+     //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
+     //  false (indicating that Stage1 needs updating), or preloadstage2 is active
+     //  (indicating that Stage2 is going to update, so Stage1, therefore, must
+     //  also be updated to keep it valid.
+     //***************************************************************************
+     assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
+  
+     //***************************************************************************
+     // Calculate RAM_REGOUT_EN
+     //  The output registers are controlled by the ram_regout_en signal.
+     //  These registers should be updated either when the output in Stage2 is
+     //  invalid (preloadstage2), OR when the user is reading, in which case the
+     //  Stage2 value will go invalid unless it is replenished.
+     //***************************************************************************
+     assign ram_regout_en = (ram_valid_i == 1\'b1 && (read_data_valid_i == 1\'b0 || fab_read_data_valid_i == 1\'b0)) ? 1\'b1 : (read_data_valid_i == 1\'b1 && fab_read_data_valid_i == 1\'b1 && ram_valid_i == 1\'b1) ? RD_EN : 1\'b0;
+
+     //***************************************************************************
+     // Calculate RAM_RD_EN
+     //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
+     //  update the value in Stage1.
+     //   One case when this happens is when preloadstage1=true, which indicates
+     //  that the data in Stage1 or Stage2 is invalid, and needs to automatically
+     //  be updated.
+     //   The other case is when the user is reading from the FIFO, which 
+     // guarantees that Stage1 or Stage2 will be invalid on the next clock 
+     // cycle, unless it is replinished by data from the memory. So, as long 
+     // as the RAM has data in it, a read of the RAM should occur.
+     //***************************************************************************
+     assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
+   end
+   endgenerate // gnll_fifo
+
+   
+
+   //***************************************************************************
+   // Calculate RAMVALID_P0_OUT
+   //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
+   //
+   //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then
+   //   RAMVALID_P0_OUT is certainly going to be true.
+   //   If the RAM is not being read from, but the output registers are being
+   //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
+   //   therefore causing RAMVALID_P0_OUT to be false   //   Otherwise, RAMVALID_P0_OUT will remain unchanged.
+   //***************************************************************************
+   // PROCESS regout_valid
+     generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
+
+     
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin  
+        if (rd_rst_i) begin 
+           // asynchronous reset (active high)
+           fab_valid     <= #`TCQ 1\'b0;
+        end else begin
+           if (srst_i) begin 
+              // synchronous reset (active high)
+              fab_valid    <= #`TCQ 1\'b0;
+           end else begin
+              if (ram_regout_en == 1\'b1) begin
+                 fab_valid  <= #`TCQ 1\'b1;
+              end else begin
+                 if (fab_regout_en == 1\'b1)
+                   fab_valid <= #`TCQ 1\'b0;
+                 else
+                   fab_valid <= #`TCQ fab_valid;
+              end
+           end //srst_i
+        end //rd_rst_i
+     end //always
+   end endgenerate // gnll_fifo_fab_valid
+
+   
+   //***************************************************************************
+   // Calculate READ_DATA_VALID
+   //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
+   //  Stage2 has valid data whenever Stage1 had valid data and 
+   //  ram_regout_en_i=1, such that the data in Stage1 is propogated 
+   //  into Stage2.
+   //***************************************************************************
+    generate if(C_USE_EMBEDDED_REG == 3) begin
+   always @ (posedge RD_CLK or posedge rd_rst_i) begin
+      if (rd_rst_i)
+        read_data_valid_i <= #`TCQ 1\'b0;
+      else if (srst_i)
+        read_data_valid_i <= #`TCQ 1\'b0;
+      else begin
+        if (ram_regout_en == 1\'b1) begin
+          read_data_valid_i <= #`TCQ 1\'b1;
+        end else begin
+         if (fab_regout_en == 1\'b1)
+          read_data_valid_i <= #`TCQ 1\'b0;
+        else
+          read_data_valid_i <= #`TCQ read_data_valid_i;
+        end 
+      end 
+   end //always
+end
+endgenerate
+
+//generate if(C_USE_EMBEDDED_REG == 3) begin
+//   always @ (posedge RD_CLK or posedge rd_rst_i) begin
+//      if (rd_rst_i)
+//        read_data_valid_i <= #`TCQ 1\'b0;
+//      else if (srst_i)
+//        read_data_valid_i <= #`TCQ 1\'b0;
+//
+//      if (ram_regout_en == 1\'b1) begin
+//        fab_read_data_valid_i <= #`TCQ 1\'b0;
+//      end else begin
+//       if (fab_regout_en == 1\'b1)
+//        fab_read_data_valid_i <= #`TCQ 1\'b1;
+//      else
+//        fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
+//      end 
+//   end //always
+//end
+//endgenerate
+
+     generate if(C_USE_EMBEDDED_REG == 3 ) begin 
+    always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
+      if (rd_rst_i)
+        fab_read_data_valid_i <= #`TCQ 1\'b0;
+      else if (srst_i)
+        fab_read_data_valid_i <= #`TCQ 1\'b0;
+      else 
+        fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
+   end //always
+end
+endgenerate
+ 
+always @ (posedge RD_CLK ) begin : proc_del1
+             begin
+                 fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
+              end
+            end //always
+ 
+ 
+   //**************************************************************************
+   // Calculate EMPTY
+   //  Defined as the inverse of READ_DATA_VALID
+   //
+   // Description:
+   //
+   //  If read_data_valid_i indicates that the output is not valid,
+   // and there is no valid data on the output of the ram to preload it
+   // with, then we will report empty.
+   //
+   //  If there is no valid data on the output of the ram and we are
+   // reading, then the FIFO will go empty.
+   //
+   //**************************************************************************
+   generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i) begin
+           // asynchronous reset (active high)
+           empty_i <= #`TCQ 1\'b1;
+        end else begin
+           if (srst_i) begin
+              // synchronous reset (active high)
+              empty_i <= #`TCQ 1\'b1;
+           end else begin
+              // rising clock edge
+              empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
+           end
+        end
+     end //always
+   end endgenerate // gnll_fifo_empty_both
+   
+   // Register RD_EN from user to calculate USERUNDERFLOW.
+   // Register empty_i to calculate USERUNDERFLOW.
+   always @ (posedge RD_CLK) begin
+     rd_en_q <= #`TCQ RD_EN;
+     empty_q <= #`TCQ empty_i;
+   end //always
+   
+   
+   //***************************************************************************
+   // Calculate user_almost_empty
+   //  user_almost_empty is defined such that, unless more words are written
+   //  to the FIFO, the next read will cause the FIFO to go EMPTY.
+   //
+   //  In most cases, whenever the output registers are updated (due to a user
+   // read or a preload condition), then user_almost_empty will update to
+   // whatever RAM_EMPTY is.
+   //
+   //  The exception is when the output is valid, the user is not reading, and
+   // Stage1 is not empty. In this condition, Stage1 will be preloaded from the
+   // memory, so we need to make sure user_almost_empty deasserts properly under
+   // this condition.
+   //***************************************************************************
+   reg FIFOEMPTY_1;
+   generate if (C_USE_EMBEDDED_REG == 3 ) begin
+    always @(posedge RD_CLK) begin
+            FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
+           end
+    end
+endgenerate
+    generate if (C_USE_EMBEDDED_REG == 3 ) begin
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+   begin
+      if (rd_rst_i) begin         // asynchronous reset (active high)
+           almost_empty_i <= #`TCQ 1\'b1;
+             almost_empty_q <= #`TCQ 1\'b1;
+        end else begin // rising clock edge
+           if (srst_i) begin          // synchronous reset (active high)
+              almost_empty_i <= #`TCQ 1\'b1;
+              almost_empty_q <= #`TCQ 1\'b1;
+           end else begin
+              if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
+                 almost_empty_i <= #`TCQ (~ram_valid_i);
+              end
+              almost_empty_q   <= #`TCQ empty_i;
+           end
+        end
+     end //always
+end
+endgenerate
+     always @ (posedge RD_CLK or posedge rd_rst_i) begin
+        if (rd_rst_i) begin
+           empty_sckt <= #`TCQ 1\'b1;
+           sckt_rrst_q <= #`TCQ 1\'b0;
+           sckt_rrst_done <= #`TCQ 1\'b0;
+        end else begin
+           sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
+           if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
+              sckt_rrst_done <= #`TCQ 1\'b1;
+           end else if (sckt_rrst_done) begin
+              // rising clock edge
+              empty_sckt <= #`TCQ 1\'b0;
+           end
+        end
+     end //always
+   
+   
+//   assign USEREMPTY       = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
+   assign USEREMPTY       = empty_i;
+   assign USERALMOSTEMPTY = almost_empty_i;
+   assign FIFORDEN        = ram_rd_en;
+   assign RAMVALID        = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
+   assign uservalid_both       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3)  ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1\'b0);
+   assign uservalid_one       = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3)  ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1\'b0);
+   assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
+   assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
+//no safety ckt with both reg
+generate 
+        if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
+   always @ (posedge RD_CLK)
+     begin
+        if (rd_rst_i || srst_i) begin
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
+            USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+            user_sbiterr_both <= #`TCQ 0;
+            user_dbiterr_both <= #`TCQ 0;
+        end
+     end //always
+
+ 
+   always @ (posedge RD_CLK or posedge rd_rst_i)
+     begin
+        if (rd_rst_i) begin //asynchronous reset (active high)
+          if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+            USERSBITERR    <= #`TCQ 0;
+            USERDBITERR    <= #`TCQ 0;
+            user_sbiterr_both <= #`TCQ 0;
+            user_dbiterr_both <= #`TCQ 0;
+          end
+          // DRAM resets asynchronously
+          if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin  //asynchronous reset (active high)
+            USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+            userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+            user_sbiterr_both <= #`TCQ 0;
+            user_dbiterr_both <= #`TCQ 0;
+        end
+        end  else begin // rising clock edge
+          if (srst_i) begin
+            if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+              USERSBITERR  <= #`TCQ 0;
+              USERDBITERR  <= #`TCQ 0;
+              user_sbiterr_both <= #`TCQ 0;
+              user_dbiterr_both <= #`TCQ 0;
+            end
+            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
+              USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+              userdata_both   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+              user_sbiterr_both <= #`TCQ 0;
+              user_dbiterr_both <= #`TCQ 0;
+            end
+          end else begin
+            if (fwft_rst_done) begin
+              if (ram_regout_en) begin
+                 userdata_both     <= #`TCQ FIFODATA; 
+                 user_dbiterr_both <= #`TCQ FIFODBITERR;
+                 user_sbiterr_both <= #`TCQ FIFOSBITERR; 
+              end
+              if (fab_regout_en) begin
+                 USERDATA     <= #`TCQ userdata_both;
+                 USERDBITERR  <= #`TCQ user_dbiterr_both;
+                 USERSBITERR  <= #`TCQ user_sbiterr_both; 
+              end             
+            end             
+          end
+        end
+     end //always
+   end   //if
+  endgenerate
+
+//safety_ckt with both registers
+ generate
+       if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d1;
+         reg [C_DOUT_WIDTH-1:0]     dout_rst_val_d2;
+         reg [1:0] rst_delayed_sft1              =1;
+         reg [1:0] rst_delayed_sft2              =1;
+         reg [1:0] rst_delayed_sft3              =1;
+         reg [1:0] rst_delayed_sft4              =1;
+         
+        always@(posedge RD_CLK) begin
+          rst_delayed_sft1 <= #`TCQ rd_rst_i;
+          rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
+          rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; 
+          rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
+        end
+        always @ (posedge RD_CLK) begin
+          if (rd_rst_i || srst_i) begin
+            if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1\'b1) begin
+              @(posedge RD_CLK)
+              USERDATA     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+               userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+              user_sbiterr_both <= #`TCQ 0;
+              user_dbiterr_both <= #`TCQ 0;
+            end
+          end
+        end //always
+ 
+   always @ (posedge RD_CLK or posedge rd_rst_i) begin
+     if (rd_rst_i) begin //asynchronous reset (active high)
+       if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+         USERSBITERR       <= #`TCQ 0;
+         USERDBITERR       <= #`TCQ 0;
+         user_sbiterr_both <= #`TCQ 0;
+         user_dbiterr_both <= #`TCQ 0;
+       end
+       // DRAM resets asynchronously
+       if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin  //asynchronous reset (active high)
+         USERDATA          <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+         userdata_both     <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+         user_sbiterr_both <= #`TCQ 0;
+         user_dbiterr_both <= #`TCQ 0;
+       end 
+     end else begin // rising clock edge
+       if (srst_i) begin
+         if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
+           USERSBITERR       <= #`TCQ 0;
+           USERDBITERR       <= #`TCQ 0;
+           user_sbiterr_both <= #`TCQ 0;
+           user_dbiterr_both <= #`TCQ 0;
+         end
+         if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
+           USERDATA   <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
+         end
+       end else if (fwft_rst_done) begin
+         if (ram_regout_en == 1\'b1 && rd_rst_i == 1\'b0) begin
+            userdata_both     <= #`TCQ FIFODATA;
+            user_dbiterr_both <= #`TCQ FIFODBITERR;
+            user_sbiterr_both <= #`TCQ FIFOSBITERR; 
+         end
+         if (fab_regout_en == 1\'b1 && rd_rst_i == 1\'b0) begin
+            USERDATA          <= #`TCQ userdata_both;
+            USERDBITERR       <= #`TCQ user_dbiterr_both;
+            USERSBITERR       <= #`TCQ user_sbiterr_both;
+         end
+       end
+     end
+   end //always
+  end //if
+endgenerate
+
+endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
+
+
+//-----------------------------------------------------------------------------
+//
+// Register Slice
+//   Register one AXI channel on forward and/or reverse signal path
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   reg_slice
+//
+//--------------------------------------------------------------------------
+
+module fifo_generator_v13_1_3_axic_reg_slice #
+  (
+   parameter C_FAMILY     = ""virtex7"",
+   parameter C_DATA_WIDTH = 32,
+   parameter C_REG_CONFIG = 32\'h00000000
+   )
+  (
+   // System Signals
+   input  wire                      ACLK,
+   input  wire                      ARESET,
+
+   // Slave side
+   input  wire [C_DATA_WIDTH-1:0]   S_PAYLOAD_DATA,
+   input  wire                      S_VALID,
+   output wire                      S_READY,
+
+   // Master side
+   output wire [C_DATA_WIDTH-1:0]   M_PAYLOAD_DATA,
+   output wire                      M_VALID,
+   input  wire                      M_READY
+   );
+
+  generate
+  ////////////////////////////////////////////////////////////////////
+  //
+  // Both FWD and REV mode
+  //
+  ////////////////////////////////////////////////////////////////////
+    if (C_REG_CONFIG == 32\'h00000000)
+    begin
+      reg [1:0] state;
+      localparam [1:0] 
+        ZERO = 2\'b10,
+        ONE  = 2\'b11,
+        TWO  = 2\'b01;
+      
+      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
+      reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
+      reg                    load_s1;
+      wire                   load_s2;
+      wire                   load_s1_from_s2;
+      reg                    s_ready_i; //local signal of output
+      wire                   m_valid_i; //local signal of output
+
+      // assign local signal to its output signal
+      assign S_READY = s_ready_i;
+      assign M_VALID = m_valid_i;
+
+      reg  areset_d1; // Reset delay register
+      always @(posedge ACLK) begin
+        areset_d1 <= ARESET;
+      end
+      
+      // Load storage1 with either slave side data or from storage2
+      always @(posedge ACLK) 
+      begin
+        if (load_s1)
+          if (load_s1_from_s2)
+            storage_data1 <= storage_data2;
+          else
+            storage_data1 <= S_PAYLOAD_DATA;        
+      end
+
+      // Load storage2 with slave side data
+      always @(posedge ACLK) 
+      begin
+        if (load_s2)
+          storage_data2 <= S_PAYLOAD_DATA;
+      end
+
+      assign M_PAYLOAD_DATA = storage_data1;
+
+      // Always load s2 on a valid transaction even if it\'s unnecessary
+      assign load_s2 = S_VALID & s_ready_i;
+
+      // Loading s1
+      always @ *
+      begin
+        if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
+             // Load when ONE if we both have read and write at the same time
+             ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
+             // Load when TWO and we have a transaction on Master side
+             ((state == TWO) && (M_READY == 1)))
+          load_s1 = 1\'b1;
+        else
+          load_s1 = 1\'b0;
+      end // always @ *
+
+      assign load_s1_from_s2 = (state == TWO);
+                       
+      // State Machine for handling output signals
+      always @(posedge ACLK) begin
+        if (ARESET) begin
+          s_ready_i <= 1\'b0;
+          state <= ZERO;
+        end else if (areset_d1) begin
+          s_ready_i <= 1\'b1;
+        end else begin
+          case (state)
+            // No transaction stored locally
+            ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
+
+            // One transaction stored locally
+            ONE: begin
+              if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
+              if (~M_READY & S_VALID) begin
+                state <= TWO;  // Got another one so move to TWO
+                s_ready_i <= 1\'b0;
+              end
+            end
+
+            // TWO transaction stored locally
+            TWO: if (M_READY) begin
+              state <= ONE; // Read out one so move to ONE
+              s_ready_i <= 1\'b1;
+            end
+          endcase // case (state)
+        end
+      end // always @ (posedge ACLK)
+      
+      assign m_valid_i = state[0];
+
+    end // if (C_REG_CONFIG == 1)
+  ////////////////////////////////////////////////////////////////////
+  //
+  // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
+  // Operates same as 1-deep FIFO
+  //
+  ////////////////////////////////////////////////////////////////////
+    else if (C_REG_CONFIG == 32\'h00000001)
+    begin
+      reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
+      reg                    s_ready_i; //local signal of output
+      reg                    m_valid_i; //local signal of output
+
+      // assign local signal to its output signal
+      assign S_READY = s_ready_i;
+      assign M_VALID = m_valid_i;
+
+      reg  areset_d1; // Reset delay register
+      always @(posedge ACLK) begin
+        areset_d1 <= ARESET;
+      end
+      
+      // Load storage1 with slave side data
+      always @(posedge ACLK) 
+      begin
+        if (ARESET) begin
+          s_ready_i <= 1\'b0;
+          m_valid_i <= 1\'b0;
+        end else if (areset_d1) begin
+          s_ready_i <= 1\'b1;
+        end else if (m_valid_i & M_READY) begin
+          s_ready_i <= 1\'b1;
+          m_valid_i <= 1\'b0;
+        end else if (S_VALID & s_ready_i) begin
+          s_ready_i <= 1\'b0;
+          m_valid_i <= 1\'b1;
+        end
+        if (~m_valid_i) begin
+          storage_data1 <= S_PAYLOAD_DATA;        
+        end
+      end
+      assign M_PAYLOAD_DATA = storage_data1;
+    end // if (C_REG_CONFIG == 7)
+    
+    else begin : default_case
+      // Passthrough
+      assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
+      assign M_VALID        = S_VALID;
+      assign S_READY        = M_READY;      
+    end
+
+  endgenerate
+endmodule // reg_slice
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:37:11 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_stub.v
+// Design      : design_1_axi_intc_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_intc,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, intr, irq)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,intr[0:0],irq"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [0:0]intr;
+  output irq;
+endmodule
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:36:35 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xlconcat_0_0_sim_netlist.v
+// Design      : design_1_xlconcat_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = ""design_1_xlconcat_0_0,xlconcat,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""xlconcat,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (In0,
+    In1,
+    dout);
+  input [0:0]In0;
+  input [0:0]In1;
+  output [1:0]dout;
+
+  wire [0:0]In0;
+  wire [0:0]In1;
+
+  assign dout[1] = In1;
+  assign dout[0] = In0;
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 09 23:35:45 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_sim_netlist.v
+// Design      : design_1_xbar_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd
+   (aa_grant_any,
+    m_valid_i,
+    SR,
+    aa_grant_rnw,
+    D,
+    Q,
+    \\m_atarget_hot_reg[2] ,
+    \\gen_axilite.s_axi_rvalid_i_reg ,
+    s_ready_i_reg,
+    E,
+    m_valid_i_reg,
+    m_ready_d0,
+    s_axi_bvalid,
+    m_axi_bready,
+    \\m_ready_d_reg[0] ,
+    \\gen_axilite.s_axi_bvalid_i_reg ,
+    s_axi_wready,
+    m_axi_wvalid,
+    \\m_ready_d_reg[2] ,
+    \\gen_axilite.s_axi_bvalid_i_reg_0 ,
+    m_axi_awvalid,
+    m_axi_arvalid,
+    s_axi_awready,
+    s_axi_arready,
+    \\gen_axilite.s_axi_bvalid_i_reg_1 ,
+    \\gen_axilite.s_axi_awready_i_reg ,
+    aclk,
+    m_ready_d,
+    \\aresetn_d_reg[1] ,
+    aresetn_d,
+    m_ready_d_0,
+    \\gen_axilite.s_axi_awready_i_reg_0 ,
+    \\gen_axilite.s_axi_bvalid_i_reg_2 ,
+    \\m_atarget_hot_reg[3] ,
+    s_axi_bready,
+    \\gen_axilite.s_axi_awready_i_reg_1 ,
+    s_axi_wvalid,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    m_ready_d0_1,
+    aa_rready,
+    \\gen_axilite.s_axi_rvalid_i_reg_0 ,
+    s_axi_rready,
+    sr_rvalid,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    \\m_ready_d_reg[0]_0 ,
+    s_axi_awvalid,
+    mi_wready,
+    mi_bvalid);
+  output aa_grant_any;
+  output m_valid_i;
+  output [0:0]SR;
+  output aa_grant_rnw;
+  output [3:0]D;
+  output [34:0]Q;
+  output \\m_atarget_hot_reg[2] ;
+  output \\gen_axilite.s_axi_rvalid_i_reg ;
+  output s_ready_i_reg;
+  output [0:0]E;
+  output m_valid_i_reg;
+  output [0:0]m_ready_d0;
+  output [0:0]s_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output \\m_ready_d_reg[0] ;
+  output \\gen_axilite.s_axi_bvalid_i_reg ;
+  output [0:0]s_axi_wready;
+  output [2:0]m_axi_wvalid;
+  output \\m_ready_d_reg[2] ;
+  output \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  output [2:0]m_axi_awvalid;
+  output [2:0]m_axi_arvalid;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output \\gen_axilite.s_axi_bvalid_i_reg_1 ;
+  output \\gen_axilite.s_axi_awready_i_reg ;
+  input aclk;
+  input [1:0]m_ready_d;
+  input [1:0]\\aresetn_d_reg[1] ;
+  input aresetn_d;
+  input [2:0]m_ready_d_0;
+  input \\gen_axilite.s_axi_awready_i_reg_0 ;
+  input \\gen_axilite.s_axi_bvalid_i_reg_2 ;
+  input [3:0]\\m_atarget_hot_reg[3] ;
+  input [0:0]s_axi_bready;
+  input \\gen_axilite.s_axi_awready_i_reg_1 ;
+  input [0:0]s_axi_wvalid;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input [0:0]m_ready_d0_1;
+  input aa_rready;
+  input \\gen_axilite.s_axi_rvalid_i_reg_0 ;
+  input [0:0]s_axi_rready;
+  input sr_rvalid;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input \\m_ready_d_reg[0]_0 ;
+  input [0:0]s_axi_awvalid;
+  input [0:0]mi_wready;
+  input [0:0]mi_bvalid;
+
+  wire [3:0]D;
+  wire [0:0]E;
+  wire [34:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire aresetn_d;
+  wire [1:0]\\aresetn_d_reg[1] ;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg ;
+  wire \\gen_axilite.s_axi_awready_i_reg_0 ;
+  wire \\gen_axilite.s_axi_awready_i_reg_1 ;
+  wire \\gen_axilite.s_axi_bvalid_i_i_2_n_0 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_0 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_1 ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg_2 ;
+  wire \\gen_axilite.s_axi_rvalid_i_reg ;
+  wire \\gen_axilite.s_axi_rvalid_i_reg_0 ;
+  wire \\gen_no_arbiter.grant_rnw_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_3_n_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i[0]_i_4_n_0 ;
+  wire \\gen_no_arbiter.m_valid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.m_valid_i_i_2_n_0 ;
+  wire \\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
+  wire \\m_atarget_hot[3]_i_3_n_0 ;
+  wire \\m_atarget_hot[3]_i_4_n_0 ;
+  wire \\m_atarget_hot_reg[2] ;
+  wire [3:0]\\m_atarget_hot_reg[3] ;
+  wire [2:0]m_axi_arvalid;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [2:0]m_axi_wvalid;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire [0:0]m_ready_d0_1;
+  wire [2:0]m_ready_d_0;
+  wire \\m_ready_d_reg[0] ;
+  wire \\m_ready_d_reg[0]_0 ;
+  wire \\m_ready_d_reg[2] ;
+  wire m_valid_i;
+  wire m_valid_i_i_2_n_0;
+  wire m_valid_i_reg;
+  wire [0:0]mi_bvalid;
+  wire [0:0]mi_wready;
+  wire p_0_in1_in;
+  wire [48:1]s_amesg;
+  wire \\s_arvalid_reg[0]_i_1_n_0 ;
+  wire \\s_arvalid_reg_reg_n_0_[0] ;
+  wire s_awvalid_reg;
+  wire \\s_awvalid_reg[0]_i_1_n_0 ;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [0:0]s_axi_bvalid;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire s_ready_i;
+  wire s_ready_i_reg;
+  wire sr_rvalid;
+
+  LUT6 #(
+    .INIT(64\'hFFFFFFFB00000004)) 
+    \\gen_axilite.s_axi_awready_i_i_1 
+       (.I0(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .I1(\\m_atarget_hot_reg[3] [3]),
+        .I2(m_ready_d_0[2]),
+        .I3(\\gen_no_arbiter.m_grant_hot_i[0]_i_4_n_0 ),
+        .I4(mi_bvalid),
+        .I5(mi_wready),
+        .O(\\gen_axilite.s_axi_awready_i_reg ));
+  LUT6 #(
+    .INIT(64\'hAFAFAFAF00300000)) 
+    \\gen_axilite.s_axi_bvalid_i_i_1 
+       (.I0(\\gen_axilite.s_axi_bvalid_i_reg ),
+        .I1(\\gen_axilite.s_axi_bvalid_i_reg_0 ),
+        .I2(\\m_atarget_hot_reg[3] [3]),
+        .I3(\\gen_axilite.s_axi_bvalid_i_i_2_n_0 ),
+        .I4(mi_wready),
+        .I5(mi_bvalid),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg_1 ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT3 #(
+    .INIT(8\'hFB)) 
+    \\gen_axilite.s_axi_bvalid_i_i_2 
+       (.I0(m_ready_d_0[2]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .O(\\gen_axilite.s_axi_bvalid_i_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT3 #(
+    .INIT(8\'h40)) 
+    \\gen_axilite.s_axi_rvalid_i_i_2 
+       (.I0(m_ready_d[1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .O(\\gen_axilite.s_axi_rvalid_i_reg ));
+  LUT6 #(
+    .INIT(64\'hFFFFFF4700000044)) 
+    \\gen_no_arbiter.grant_rnw_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_arvalid),
+        .I2(s_axi_awvalid),
+        .I3(aa_grant_any),
+        .I4(m_valid_i),
+        .I5(aa_grant_rnw),
+        .O(\\gen_no_arbiter.grant_rnw_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.grant_rnw_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.grant_rnw_i_1_n_0 ),
+        .Q(aa_grant_rnw),
+        .R(SR));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[10]_i_1 
+       (.I0(s_axi_araddr[9]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[9]),
+        .O(s_amesg[10]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[11]_i_1 
+       (.I0(s_axi_araddr[10]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[10]),
+        .O(s_amesg[11]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[12]_i_1 
+       (.I0(s_axi_araddr[11]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[11]),
+        .O(s_amesg[12]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[13]_i_1 
+       (.I0(s_axi_araddr[12]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[12]),
+        .O(s_amesg[13]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[14]_i_1 
+       (.I0(s_axi_araddr[13]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[13]),
+        .O(s_amesg[14]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[15]_i_1 
+       (.I0(s_axi_araddr[14]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[14]),
+        .O(s_amesg[15]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[16]_i_1 
+       (.I0(s_axi_araddr[15]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[15]),
+        .O(s_amesg[16]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[17]_i_1 
+       (.I0(s_axi_araddr[16]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[16]),
+        .O(s_amesg[17]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[18]_i_1 
+       (.I0(s_axi_araddr[17]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[17]),
+        .O(s_amesg[18]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[19]_i_1 
+       (.I0(s_axi_araddr[18]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[18]),
+        .O(s_amesg[19]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[1]_i_1 
+       (.I0(s_axi_araddr[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[0]),
+        .O(s_amesg[1]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[20]_i_1 
+       (.I0(s_axi_araddr[19]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[19]),
+        .O(s_amesg[20]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[21]_i_1 
+       (.I0(s_axi_araddr[20]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[20]),
+        .O(s_amesg[21]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[22]_i_1 
+       (.I0(s_axi_araddr[21]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[21]),
+        .O(s_amesg[22]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[23]_i_1 
+       (.I0(s_axi_araddr[22]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[22]),
+        .O(s_amesg[23]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[24]_i_1 
+       (.I0(s_axi_araddr[23]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[23]),
+        .O(s_amesg[24]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[25]_i_1 
+       (.I0(s_axi_araddr[24]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[24]),
+        .O(s_amesg[25]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[26]_i_1 
+       (.I0(s_axi_araddr[25]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[25]),
+        .O(s_amesg[26]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[27]_i_1 
+       (.I0(s_axi_araddr[26]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[26]),
+        .O(s_amesg[27]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[28]_i_1 
+       (.I0(s_axi_araddr[27]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[27]),
+        .O(s_amesg[28]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[29]_i_1 
+       (.I0(s_axi_araddr[28]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[28]),
+        .O(s_amesg[29]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[2]_i_1 
+       (.I0(s_axi_araddr[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[1]),
+        .O(s_amesg[2]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[30]_i_1 
+       (.I0(s_axi_araddr[29]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[29]),
+        .O(s_amesg[30]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[31]_i_1 
+       (.I0(s_axi_araddr[30]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[30]),
+        .O(s_amesg[31]));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_1 
+       (.I0(aresetn_d),
+        .O(SR));
+  LUT1 #(
+    .INIT(2\'h1)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_2 
+       (.I0(aa_grant_any),
+        .O(p_0_in1_in));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[32]_i_3 
+       (.I0(s_axi_araddr[31]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[31]),
+        .O(s_amesg[32]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[3]_i_1 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[2]),
+        .O(s_amesg[3]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[46]_i_1 
+       (.I0(s_axi_arprot[0]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[0]),
+        .O(s_amesg[46]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[47]_i_1 
+       (.I0(s_axi_arprot[1]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[1]),
+        .O(s_amesg[47]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[48]_i_1 
+       (.I0(s_axi_arprot[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awprot[2]),
+        .O(s_amesg[48]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[4]_i_1 
+       (.I0(s_axi_araddr[3]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[3]),
+        .O(s_amesg[4]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[5]_i_1 
+       (.I0(s_axi_araddr[4]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[4]),
+        .O(s_amesg[5]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[6]_i_1 
+       (.I0(s_axi_araddr[5]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[5]),
+        .O(s_amesg[6]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[7]_i_1 
+       (.I0(s_axi_araddr[6]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[6]),
+        .O(s_amesg[7]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[8]_i_1 
+       (.I0(s_axi_araddr[7]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[7]),
+        .O(s_amesg[8]));
+  LUT4 #(
+    .INIT(16\'hFB08)) 
+    \\gen_no_arbiter.m_amesg_i[9]_i_1 
+       (.I0(s_axi_araddr[8]),
+        .I1(s_axi_arvalid),
+        .I2(s_awvalid_reg),
+        .I3(s_axi_awaddr[8]),
+        .O(s_amesg[9]));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[10] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[10]),
+        .Q(Q[9]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[11] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[11]),
+        .Q(Q[10]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[12] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[12]),
+        .Q(Q[11]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[13] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[13]),
+        .Q(Q[12]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[14] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[14]),
+        .Q(Q[13]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[15] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[15]),
+        .Q(Q[14]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[16] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[16]),
+        .Q(Q[15]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[17] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[17]),
+        .Q(Q[16]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[18] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[18]),
+        .Q(Q[17]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[19] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[19]),
+        .Q(Q[18]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[1] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[1]),
+        .Q(Q[0]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[20] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[20]),
+        .Q(Q[19]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[21] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[21]),
+        .Q(Q[20]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[22] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[22]),
+        .Q(Q[21]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[23] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[23]),
+        .Q(Q[22]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[24] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[24]),
+        .Q(Q[23]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[25] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[25]),
+        .Q(Q[24]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[26] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[26]),
+        .Q(Q[25]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[27] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[27]),
+        .Q(Q[26]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[28] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[28]),
+        .Q(Q[27]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[29] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[29]),
+        .Q(Q[28]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[2] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[2]),
+        .Q(Q[1]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[30] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[30]),
+        .Q(Q[29]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[31] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[31]),
+        .Q(Q[30]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[32] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[32]),
+        .Q(Q[31]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[3] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[3]),
+        .Q(Q[2]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[46] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[46]),
+        .Q(Q[32]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[47] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[47]),
+        .Q(Q[33]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[48] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[48]),
+        .Q(Q[34]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[4] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[4]),
+        .Q(Q[3]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[5] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[5]),
+        .Q(Q[4]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[6] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[6]),
+        .Q(Q[5]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[7] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[7]),
+        .Q(Q[6]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[8] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[8]),
+        .Q(Q[7]),
+        .R(SR));
+  FDRE \\gen_no_arbiter.m_amesg_i_reg[9] 
+       (.C(aclk),
+        .CE(p_0_in1_in),
+        .D(s_amesg[9]),
+        .Q(Q[8]),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0808080808000808)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_1 
+       (.I0(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
+        .I1(aresetn_d),
+        .I2(\\gen_no_arbiter.m_grant_hot_i[0]_i_3_n_0 ),
+        .I3(\\gen_no_arbiter.m_grant_hot_i[0]_i_4_n_0 ),
+        .I4(m_ready_d0),
+        .I5(\\m_ready_d_reg[0]_0 ),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT4 #(
+    .INIT(16\'hF0FE)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_2 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_awvalid),
+        .I2(aa_grant_any),
+        .I3(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'hE0000000)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_3 
+       (.I0(m_ready_d[1]),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(m_ready_d0_1),
+        .I3(aa_grant_rnw),
+        .I4(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_3_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT2 #(
+    .INIT(4\'hB)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_4 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .O(\\gen_no_arbiter.m_grant_hot_i[0]_i_4_n_0 ));
+  FDRE \\gen_no_arbiter.m_grant_hot_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
+        .Q(aa_grant_any),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h0BFBFFFF0BFB0000)) 
+    \\gen_no_arbiter.m_valid_i_i_1 
+       (.I0(\\m_ready_d_reg[0]_0 ),
+        .I1(m_ready_d0),
+        .I2(aa_grant_rnw),
+        .I3(\\gen_no_arbiter.m_valid_i_i_2_n_0 ),
+        .I4(m_valid_i),
+        .I5(aa_grant_any),
+        .O(\\gen_no_arbiter.m_valid_i_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair3"" *) 
+  LUT5 #(
+    .INIT(32\'hAAAA8000)) 
+    \\gen_no_arbiter.m_valid_i_i_2 
+       (.I0(m_ready_d0_1),
+        .I1(\\gen_axilite.s_axi_arready_i_reg ),
+        .I2(aa_grant_rnw),
+        .I3(m_valid_i),
+        .I4(m_ready_d[1]),
+        .O(\\gen_no_arbiter.m_valid_i_i_2_n_0 ));
+  FDRE \\gen_no_arbiter.m_valid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.m_valid_i_i_1_n_0 ),
+        .Q(m_valid_i),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair5"" *) 
+  LUT3 #(
+    .INIT(8\'h40)) 
+    \\gen_no_arbiter.s_ready_i[0]_i_1 
+       (.I0(m_valid_i),
+        .I1(aa_grant_any),
+        .I2(aresetn_d),
+        .O(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
+  FDRE \\gen_no_arbiter.s_ready_i_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
+        .Q(s_ready_i),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h0010)) 
+    \\m_atarget_hot[0]_i_1 
+       (.I0(\\m_atarget_hot_reg[2] ),
+        .I1(Q[17]),
+        .I2(aa_grant_any),
+        .I3(Q[16]),
+        .O(D[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT4 #(
+    .INIT(16\'h1000)) 
+    \\m_atarget_hot[1]_i_1 
+       (.I0(Q[17]),
+        .I1(\\m_atarget_hot_reg[2] ),
+        .I2(Q[16]),
+        .I3(aa_grant_any),
+        .O(D[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair6"" *) 
+  LUT4 #(
+    .INIT(16\'h0400)) 
+    \\m_atarget_hot[2]_i_1 
+       (.I0(Q[16]),
+        .I1(Q[17]),
+        .I2(\\m_atarget_hot_reg[2] ),
+        .I3(aa_grant_any),
+        .O(D[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair7"" *) 
+  LUT4 #(
+    .INIT(16\'hEC00)) 
+    \\m_atarget_hot[3]_i_1 
+       (.I0(Q[17]),
+        .I1(\\m_atarget_hot_reg[2] ),
+        .I2(Q[16]),
+        .I3(aa_grant_any),
+        .O(D[3]));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFFFFFFFFEF)) 
+    \\m_atarget_hot[3]_i_2 
+       (.I0(\\m_atarget_hot[3]_i_3_n_0 ),
+        .I1(\\m_atarget_hot[3]_i_4_n_0 ),
+        .I2(Q[24]),
+        .I3(Q[20]),
+        .I4(Q[26]),
+        .I5(Q[25]),
+        .O(\\m_atarget_hot_reg[2] ));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFEFFFFFFFF)) 
+    \\m_atarget_hot[3]_i_3 
+       (.I0(Q[27]),
+        .I1(Q[31]),
+        .I2(Q[28]),
+        .I3(Q[23]),
+        .I4(Q[22]),
+        .I5(Q[21]),
+        .O(\\m_atarget_hot[3]_i_3_n_0 ));
+  LUT4 #(
+    .INIT(16\'hFFEF)) 
+    \\m_atarget_hot[3]_i_4 
+       (.I0(Q[29]),
+        .I1(Q[18]),
+        .I2(Q[30]),
+        .I3(Q[19]),
+        .O(\\m_atarget_hot[3]_i_4_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [0]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(m_ready_d[1]),
+        .O(m_axi_arvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [1]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(m_ready_d[1]),
+        .O(m_axi_arvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT4 #(
+    .INIT(16\'h0080)) 
+    \\m_axi_arvalid[2]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [2]),
+        .I1(m_valid_i),
+        .I2(aa_grant_rnw),
+        .I3(m_ready_d[1]),
+        .O(m_axi_arvalid[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair10"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[2]),
+        .O(m_axi_awvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair9"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [1]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[2]),
+        .O(m_axi_awvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair11"" *) 
+  LUT4 #(
+    .INIT(16\'h0020)) 
+    \\m_axi_awvalid[2]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [2]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(m_ready_d_0[2]),
+        .O(m_axi_awvalid[2]));
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_bready[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [0]),
+        .I1(s_axi_bready),
+        .I2(m_ready_d_0[0]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_bready[0]));
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_bready[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [1]),
+        .I1(s_axi_bready),
+        .I2(m_ready_d_0[0]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_bready[1]));
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_bready[2]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [2]),
+        .I1(s_axi_bready),
+        .I2(m_ready_d_0[0]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_bready[2]));
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[0]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [0]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d_0[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair1"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[1]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [1]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d_0[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\m_axi_wvalid[2]_INST_0 
+       (.I0(\\m_atarget_hot_reg[3] [2]),
+        .I1(s_axi_wvalid),
+        .I2(m_ready_d_0[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(m_axi_wvalid[2]));
+  LUT5 #(
+    .INIT(32\'h4000FFFF)) 
+    \\m_payload_i[34]_i_1 
+       (.I0(m_ready_d[0]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(s_axi_rready),
+        .I4(sr_rvalid),
+        .O(E));
+  (* SOFT_HLUTNM = ""soft_lutpair0"" *) 
+  LUT4 #(
+    .INIT(16\'hFBFF)) 
+    \\m_ready_d[0]_i_2 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d_0[1]),
+        .I3(s_axi_wvalid),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT5 #(
+    .INIT(32\'h0B0F0F0F)) 
+    \\m_ready_d[0]_i_3 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d_0[0]),
+        .I3(s_axi_bready),
+        .I4(\\gen_axilite.s_axi_bvalid_i_reg_2 ),
+        .O(\\m_ready_d_reg[0] ));
+  (* SOFT_HLUTNM = ""soft_lutpair4"" *) 
+  LUT4 #(
+    .INIT(16\'hBAAA)) 
+    \\m_ready_d[2]_i_2 
+       (.I0(m_ready_d_0[2]),
+        .I1(aa_grant_rnw),
+        .I2(m_valid_i),
+        .I3(\\gen_axilite.s_axi_awready_i_reg_0 ),
+        .O(m_ready_d0));
+  LUT5 #(
+    .INIT(32\'h0B0F0F0F)) 
+    \\m_ready_d[2]_i_3 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d_0[1]),
+        .I3(s_axi_wvalid),
+        .I4(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .O(\\m_ready_d_reg[2] ));
+  (* SOFT_HLUTNM = ""soft_lutpair2"" *) 
+  LUT4 #(
+    .INIT(16\'hFBFF)) 
+    \\m_ready_d[2]_i_4 
+       (.I0(aa_grant_rnw),
+        .I1(m_valid_i),
+        .I2(m_ready_d_0[0]),
+        .I3(s_axi_bready),
+        .O(\\gen_axilite.s_axi_bvalid_i_reg ));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'h2A)) 
+    m_valid_i_i_1
+       (.I0(\\aresetn_d_reg[1] [1]),
+        .I1(E),
+        .I2(m_valid_i_i_2_n_0),
+        .O(m_valid_i_reg));
+  LUT5 #(
+    .INIT(32\'h8AAAAAAA)) 
+    m_valid_i_i_2
+       (.I0(aa_rready),
+        .I1(m_ready_d[0]),
+        .I2(aa_grant_rnw),
+        .I3(m_valid_i),
+        .I4(\\gen_axilite.s_axi_rvalid_i_reg_0 ),
+        .O(m_valid_i_i_2_n_0));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT4 #(
+    .INIT(16\'h0040)) 
+    \\s_arvalid_reg[0]_i_1 
+       (.I0(s_awvalid_reg),
+        .I1(s_axi_arvalid),
+        .I2(aresetn_d),
+        .I3(s_ready_i),
+        .O(\\s_arvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_arvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_arvalid_reg[0]_i_1_n_0 ),
+        .Q(\\s_arvalid_reg_reg_n_0_[0] ),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'h0000000000D00000)) 
+    \\s_awvalid_reg[0]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_awvalid_reg),
+        .I2(s_axi_awvalid),
+        .I3(\\s_arvalid_reg_reg_n_0_[0] ),
+        .I4(aresetn_d),
+        .I5(s_ready_i),
+        .O(\\s_awvalid_reg[0]_i_1_n_0 ));
+  FDRE \\s_awvalid_reg_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\s_awvalid_reg[0]_i_1_n_0 ),
+        .Q(s_awvalid_reg),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair13"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_arready[0]_INST_0 
+       (.I0(aa_grant_rnw),
+        .I1(s_ready_i),
+        .O(s_axi_arready));
+  (* SOFT_HLUTNM = ""soft_lutpair8"" *) 
+  LUT2 #(
+    .INIT(4\'h2)) 
+    \\s_axi_awready[0]_INST_0 
+       (.I0(s_ready_i),
+        .I1(aa_grant_rnw),
+        .O(s_axi_awready));
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\s_axi_bvalid[0]_INST_0 
+       (.I0(\\gen_axilite.s_axi_bvalid_i_reg_2 ),
+        .I1(aa_grant_any),
+        .I2(m_ready_d_0[0]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(s_axi_bvalid));
+  LUT5 #(
+    .INIT(32\'h00000800)) 
+    \\s_axi_wready[0]_INST_0 
+       (.I0(\\gen_axilite.s_axi_awready_i_reg_1 ),
+        .I1(aa_grant_any),
+        .I2(m_ready_d_0[1]),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .O(s_axi_wready));
+  (* SOFT_HLUTNM = ""soft_lutpair12"" *) 
+  LUT3 #(
+    .INIT(8\'hA8)) 
+    s_ready_i_i_1
+       (.I0(\\aresetn_d_reg[1] [0]),
+        .I1(E),
+        .I2(m_valid_i_i_2_n_0),
+        .O(s_ready_i_reg));
+endmodule
+
+(* C_AXI_ADDR_WIDTH = ""32"" *) (* C_AXI_ARUSER_WIDTH = ""1"" *) (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+(* C_AXI_BUSER_WIDTH = ""1"" *) (* C_AXI_DATA_WIDTH = ""32"" *) (* C_AXI_ID_WIDTH = ""1"" *) 
+(* C_AXI_PROTOCOL = ""2"" *) (* C_AXI_RUSER_WIDTH = ""1"" *) (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+(* C_AXI_WUSER_WIDTH = ""1"" *) (* C_CONNECTIVITY_MODE = ""0"" *) (* C_DEBUG = ""1"" *) 
+(* C_FAMILY = ""zynq"" *) (* C_M_AXI_ADDR_WIDTH = ""96\'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"" *) (* C_M_AXI_BASE_ADDR = ""192\'b000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+(* C_M_AXI_READ_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_READ_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_SECURE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+(* C_M_AXI_WRITE_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_M_AXI_WRITE_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) (* C_NUM_ADDR_RANGES = ""1"" *) 
+(* C_NUM_MASTER_SLOTS = ""3"" *) (* C_NUM_SLAVE_SLOTS = ""1"" *) (* C_R_REGISTER = ""1"" *) 
+(* C_S_AXI_ARB_PRIORITY = ""0"" *) (* C_S_AXI_BASE_ID = ""0"" *) (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+(* C_S_AXI_SINGLE_THREAD = ""1"" *) (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+(* DowngradeIPIdentifiedWarnings = ""yes"" *) (* P_ADDR_DECODE = ""1"" *) (* P_AXI3 = ""1"" *) 
+(* P_AXI4 = ""0"" *) (* P_AXILITE = ""2"" *) (* P_AXILITE_SIZE = ""3\'b010"" *) 
+(* P_FAMILY = ""zynq"" *) (* P_INCR = ""2\'b01"" *) (* P_LEN = ""8"" *) 
+(* P_LOCK = ""1"" *) (* P_M_AXI_ERR_MODE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) (* P_M_AXI_SUPPORTS_READ = ""3\'b111"" *) 
+(* P_M_AXI_SUPPORTS_WRITE = ""3\'b111"" *) (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) (* P_RANGE_CHECK = ""1"" *) 
+(* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+(* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar
+   (aclk,
+    aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awlock,
+    s_axi_awcache,
+    s_axi_awprot,
+    s_axi_awqos,
+    s_axi_awuser,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wid,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wuser,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_buser,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arlock,
+    s_axi_arcache,
+    s_axi_arprot,
+    s_axi_arqos,
+    s_axi_aruser,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_ruser,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awid,
+    m_axi_awaddr,
+    m_axi_awlen,
+    m_axi_awsize,
+    m_axi_awburst,
+    m_axi_awlock,
+    m_axi_awcache,
+    m_axi_awprot,
+    m_axi_awregion,
+    m_axi_awqos,
+    m_axi_awuser,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wid,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wlast,
+    m_axi_wuser,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bid,
+    m_axi_bresp,
+    m_axi_buser,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_arid,
+    m_axi_araddr,
+    m_axi_arlen,
+    m_axi_arsize,
+    m_axi_arburst,
+    m_axi_arlock,
+    m_axi_arcache,
+    m_axi_arprot,
+    m_axi_arregion,
+    m_axi_arqos,
+    m_axi_aruser,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rlast,
+    m_axi_ruser,
+    m_axi_rvalid,
+    m_axi_rready);
+  input aclk;
+  input aresetn;
+  input [0:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [7:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input [0:0]s_axi_awlock;
+  input [3:0]s_axi_awcache;
+  input [2:0]s_axi_awprot;
+  input [3:0]s_axi_awqos;
+  input [0:0]s_axi_awuser;
+  input [0:0]s_axi_awvalid;
+  output [0:0]s_axi_awready;
+  input [0:0]s_axi_wid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input [0:0]s_axi_wlast;
+  input [0:0]s_axi_wuser;
+  input [0:0]s_axi_wvalid;
+  output [0:0]s_axi_wready;
+  output [0:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output [0:0]s_axi_buser;
+  output [0:0]s_axi_bvalid;
+  input [0:0]s_axi_bready;
+  input [0:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [7:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input [0:0]s_axi_arlock;
+  input [3:0]s_axi_arcache;
+  input [2:0]s_axi_arprot;
+  input [3:0]s_axi_arqos;
+  input [0:0]s_axi_aruser;
+  input [0:0]s_axi_arvalid;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rid;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output [0:0]s_axi_rlast;
+  output [0:0]s_axi_ruser;
+  output [0:0]s_axi_rvalid;
+  input [0:0]s_axi_rready;
+  output [2:0]m_axi_awid;
+  output [95:0]m_axi_awaddr;
+  output [23:0]m_axi_awlen;
+  output [8:0]m_axi_awsize;
+  output [5:0]m_axi_awburst;
+  output [2:0]m_axi_awlock;
+  output [11:0]m_axi_awcache;
+  output [8:0]m_axi_awprot;
+  output [11:0]m_axi_awregion;
+  output [11:0]m_axi_awqos;
+  output [2:0]m_axi_awuser;
+  output [2:0]m_axi_awvalid;
+  input [2:0]m_axi_awready;
+  output [2:0]m_axi_wid;
+  output [95:0]m_axi_wdata;
+  output [11:0]m_axi_wstrb;
+  output [2:0]m_axi_wlast;
+  output [2:0]m_axi_wuser;
+  output [2:0]m_axi_wvalid;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bid;
+  input [5:0]m_axi_bresp;
+  input [2:0]m_axi_buser;
+  input [2:0]m_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [2:0]m_axi_arid;
+  output [95:0]m_axi_araddr;
+  output [23:0]m_axi_arlen;
+  output [8:0]m_axi_arsize;
+  output [5:0]m_axi_arburst;
+  output [2:0]m_axi_arlock;
+  output [11:0]m_axi_arcache;
+  output [8:0]m_axi_arprot;
+  output [11:0]m_axi_arregion;
+  output [11:0]m_axi_arqos;
+  output [2:0]m_axi_aruser;
+  output [2:0]m_axi_arvalid;
+  input [2:0]m_axi_arready;
+  input [2:0]m_axi_rid;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [2:0]m_axi_rlast;
+  input [2:0]m_axi_ruser;
+  input [2:0]m_axi_rvalid;
+  output [2:0]m_axi_rready;
+
+  wire \\<const0> ;
+  wire aclk;
+  wire aresetn;
+  wire [15:0]\\^m_axi_araddr ;
+  wire [2:0]\\^m_axi_arprot ;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_arvalid;
+  wire [95:80]\\^m_axi_awaddr ;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [2:0]m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+
+  assign m_axi_araddr[95:80] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[79:64] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[63:48] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_araddr[31:16] = \\^m_axi_awaddr [95:80];
+  assign m_axi_araddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_arburst[5] = \\<const0> ;
+  assign m_axi_arburst[4] = \\<const0> ;
+  assign m_axi_arburst[3] = \\<const0> ;
+  assign m_axi_arburst[2] = \\<const0> ;
+  assign m_axi_arburst[1] = \\<const0> ;
+  assign m_axi_arburst[0] = \\<const0> ;
+  assign m_axi_arcache[11] = \\<const0> ;
+  assign m_axi_arcache[10] = \\<const0> ;
+  assign m_axi_arcache[9] = \\<const0> ;
+  assign m_axi_arcache[8] = \\<const0> ;
+  assign m_axi_arcache[7] = \\<const0> ;
+  assign m_axi_arcache[6] = \\<const0> ;
+  assign m_axi_arcache[5] = \\<const0> ;
+  assign m_axi_arcache[4] = \\<const0> ;
+  assign m_axi_arcache[3] = \\<const0> ;
+  assign m_axi_arcache[2] = \\<const0> ;
+  assign m_axi_arcache[1] = \\<const0> ;
+  assign m_axi_arcache[0] = \\<const0> ;
+  assign m_axi_arid[2] = \\<const0> ;
+  assign m_axi_arid[1] = \\<const0> ;
+  assign m_axi_arid[0] = \\<const0> ;
+  assign m_axi_arlen[23] = \\<const0> ;
+  assign m_axi_arlen[22] = \\<const0> ;
+  assign m_axi_arlen[21] = \\<const0> ;
+  assign m_axi_arlen[20] = \\<const0> ;
+  assign m_axi_arlen[19] = \\<const0> ;
+  assign m_axi_arlen[18] = \\<const0> ;
+  assign m_axi_arlen[17] = \\<const0> ;
+  assign m_axi_arlen[16] = \\<const0> ;
+  assign m_axi_arlen[15] = \\<const0> ;
+  assign m_axi_arlen[14] = \\<const0> ;
+  assign m_axi_arlen[13] = \\<const0> ;
+  assign m_axi_arlen[12] = \\<const0> ;
+  assign m_axi_arlen[11] = \\<const0> ;
+  assign m_axi_arlen[10] = \\<const0> ;
+  assign m_axi_arlen[9] = \\<const0> ;
+  assign m_axi_arlen[8] = \\<const0> ;
+  assign m_axi_arlen[7] = \\<const0> ;
+  assign m_axi_arlen[6] = \\<const0> ;
+  assign m_axi_arlen[5] = \\<const0> ;
+  assign m_axi_arlen[4] = \\<const0> ;
+  assign m_axi_arlen[3] = \\<const0> ;
+  assign m_axi_arlen[2] = \\<const0> ;
+  assign m_axi_arlen[1] = \\<const0> ;
+  assign m_axi_arlen[0] = \\<const0> ;
+  assign m_axi_arlock[2] = \\<const0> ;
+  assign m_axi_arlock[1] = \\<const0> ;
+  assign m_axi_arlock[0] = \\<const0> ;
+  assign m_axi_arprot[8:6] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_arprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_arqos[11] = \\<const0> ;
+  assign m_axi_arqos[10] = \\<const0> ;
+  assign m_axi_arqos[9] = \\<const0> ;
+  assign m_axi_arqos[8] = \\<const0> ;
+  assign m_axi_arqos[7] = \\<const0> ;
+  assign m_axi_arqos[6] = \\<const0> ;
+  assign m_axi_arqos[5] = \\<const0> ;
+  assign m_axi_arqos[4] = \\<const0> ;
+  assign m_axi_arqos[3] = \\<const0> ;
+  assign m_axi_arqos[2] = \\<const0> ;
+  assign m_axi_arqos[1] = \\<const0> ;
+  assign m_axi_arqos[0] = \\<const0> ;
+  assign m_axi_arregion[11] = \\<const0> ;
+  assign m_axi_arregion[10] = \\<const0> ;
+  assign m_axi_arregion[9] = \\<const0> ;
+  assign m_axi_arregion[8] = \\<const0> ;
+  assign m_axi_arregion[7] = \\<const0> ;
+  assign m_axi_arregion[6] = \\<const0> ;
+  assign m_axi_arregion[5] = \\<const0> ;
+  assign m_axi_arregion[4] = \\<const0> ;
+  assign m_axi_arregion[3] = \\<const0> ;
+  assign m_axi_arregion[2] = \\<const0> ;
+  assign m_axi_arregion[1] = \\<const0> ;
+  assign m_axi_arregion[0] = \\<const0> ;
+  assign m_axi_arsize[8] = \\<const0> ;
+  assign m_axi_arsize[7] = \\<const0> ;
+  assign m_axi_arsize[6] = \\<const0> ;
+  assign m_axi_arsize[5] = \\<const0> ;
+  assign m_axi_arsize[4] = \\<const0> ;
+  assign m_axi_arsize[3] = \\<const0> ;
+  assign m_axi_arsize[2] = \\<const0> ;
+  assign m_axi_arsize[1] = \\<const0> ;
+  assign m_axi_arsize[0] = \\<const0> ;
+  assign m_axi_aruser[2] = \\<const0> ;
+  assign m_axi_aruser[1] = \\<const0> ;
+  assign m_axi_aruser[0] = \\<const0> ;
+  assign m_axi_awaddr[95:80] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[79:64] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[63:48] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[47:32] = \\^m_axi_araddr [15:0];
+  assign m_axi_awaddr[31:16] = \\^m_axi_awaddr [95:80];
+  assign m_axi_awaddr[15:0] = \\^m_axi_araddr [15:0];
+  assign m_axi_awburst[5] = \\<const0> ;
+  assign m_axi_awburst[4] = \\<const0> ;
+  assign m_axi_awburst[3] = \\<const0> ;
+  assign m_axi_awburst[2] = \\<const0> ;
+  assign m_axi_awburst[1] = \\<const0> ;
+  assign m_axi_awburst[0] = \\<const0> ;
+  assign m_axi_awcache[11] = \\<const0> ;
+  assign m_axi_awcache[10] = \\<const0> ;
+  assign m_axi_awcache[9] = \\<const0> ;
+  assign m_axi_awcache[8] = \\<const0> ;
+  assign m_axi_awcache[7] = \\<const0> ;
+  assign m_axi_awcache[6] = \\<const0> ;
+  assign m_axi_awcache[5] = \\<const0> ;
+  assign m_axi_awcache[4] = \\<const0> ;
+  assign m_axi_awcache[3] = \\<const0> ;
+  assign m_axi_awcache[2] = \\<const0> ;
+  assign m_axi_awcache[1] = \\<const0> ;
+  assign m_axi_awcache[0] = \\<const0> ;
+  assign m_axi_awid[2] = \\<const0> ;
+  assign m_axi_awid[1] = \\<const0> ;
+  assign m_axi_awid[0] = \\<const0> ;
+  assign m_axi_awlen[23] = \\<const0> ;
+  assign m_axi_awlen[22] = \\<const0> ;
+  assign m_axi_awlen[21] = \\<const0> ;
+  assign m_axi_awlen[20] = \\<const0> ;
+  assign m_axi_awlen[19] = \\<const0> ;
+  assign m_axi_awlen[18] = \\<const0> ;
+  assign m_axi_awlen[17] = \\<const0> ;
+  assign m_axi_awlen[16] = \\<const0> ;
+  assign m_axi_awlen[15] = \\<const0> ;
+  assign m_axi_awlen[14] = \\<const0> ;
+  assign m_axi_awlen[13] = \\<const0> ;
+  assign m_axi_awlen[12] = \\<const0> ;
+  assign m_axi_awlen[11] = \\<const0> ;
+  assign m_axi_awlen[10] = \\<const0> ;
+  assign m_axi_awlen[9] = \\<const0> ;
+  assign m_axi_awlen[8] = \\<const0> ;
+  assign m_axi_awlen[7] = \\<const0> ;
+  assign m_axi_awlen[6] = \\<const0> ;
+  assign m_axi_awlen[5] = \\<const0> ;
+  assign m_axi_awlen[4] = \\<const0> ;
+  assign m_axi_awlen[3] = \\<const0> ;
+  assign m_axi_awlen[2] = \\<const0> ;
+  assign m_axi_awlen[1] = \\<const0> ;
+  assign m_axi_awlen[0] = \\<const0> ;
+  assign m_axi_awlock[2] = \\<const0> ;
+  assign m_axi_awlock[1] = \\<const0> ;
+  assign m_axi_awlock[0] = \\<const0> ;
+  assign m_axi_awprot[8:6] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[5:3] = \\^m_axi_arprot [2:0];
+  assign m_axi_awprot[2:0] = \\^m_axi_arprot [2:0];
+  assign m_axi_awqos[11] = \\<const0> ;
+  assign m_axi_awqos[10] = \\<const0> ;
+  assign m_axi_awqos[9] = \\<const0> ;
+  assign m_axi_awqos[8] = \\<const0> ;
+  assign m_axi_awqos[7] = \\<const0> ;
+  assign m_axi_awqos[6] = \\<const0> ;
+  assign m_axi_awqos[5] = \\<const0> ;
+  assign m_axi_awqos[4] = \\<const0> ;
+  assign m_axi_awqos[3] = \\<const0> ;
+  assign m_axi_awqos[2] = \\<const0> ;
+  assign m_axi_awqos[1] = \\<const0> ;
+  assign m_axi_awqos[0] = \\<const0> ;
+  assign m_axi_awregion[11] = \\<const0> ;
+  assign m_axi_awregion[10] = \\<const0> ;
+  assign m_axi_awregion[9] = \\<const0> ;
+  assign m_axi_awregion[8] = \\<const0> ;
+  assign m_axi_awregion[7] = \\<const0> ;
+  assign m_axi_awregion[6] = \\<const0> ;
+  assign m_axi_awregion[5] = \\<const0> ;
+  assign m_axi_awregion[4] = \\<const0> ;
+  assign m_axi_awregion[3] = \\<const0> ;
+  assign m_axi_awregion[2] = \\<const0> ;
+  assign m_axi_awregion[1] = \\<const0> ;
+  assign m_axi_awregion[0] = \\<const0> ;
+  assign m_axi_awsize[8] = \\<const0> ;
+  assign m_axi_awsize[7] = \\<const0> ;
+  assign m_axi_awsize[6] = \\<const0> ;
+  assign m_axi_awsize[5] = \\<const0> ;
+  assign m_axi_awsize[4] = \\<const0> ;
+  assign m_axi_awsize[3] = \\<const0> ;
+  assign m_axi_awsize[2] = \\<const0> ;
+  assign m_axi_awsize[1] = \\<const0> ;
+  assign m_axi_awsize[0] = \\<const0> ;
+  assign m_axi_awuser[2] = \\<const0> ;
+  assign m_axi_awuser[1] = \\<const0> ;
+  assign m_axi_awuser[0] = \\<const0> ;
+  assign m_axi_wdata[95:64] = s_axi_wdata;
+  assign m_axi_wdata[63:32] = s_axi_wdata;
+  assign m_axi_wdata[31:0] = s_axi_wdata;
+  assign m_axi_wid[2] = \\<const0> ;
+  assign m_axi_wid[1] = \\<const0> ;
+  assign m_axi_wid[0] = \\<const0> ;
+  assign m_axi_wlast[2] = \\<const0> ;
+  assign m_axi_wlast[1] = \\<const0> ;
+  assign m_axi_wlast[0] = \\<const0> ;
+  assign m_axi_wstrb[11:8] = s_axi_wstrb;
+  assign m_axi_wstrb[7:4] = s_axi_wstrb;
+  assign m_axi_wstrb[3:0] = s_axi_wstrb;
+  assign m_axi_wuser[2] = \\<const0> ;
+  assign m_axi_wuser[1] = \\<const0> ;
+  assign m_axi_wuser[0] = \\<const0> ;
+  assign s_axi_bid[0] = \\<const0> ;
+  assign s_axi_buser[0] = \\<const0> ;
+  assign s_axi_rid[0] = \\<const0> ;
+  assign s_axi_rlast[0] = \\<const0> ;
+  assign s_axi_ruser[0] = \\<const0> ;
+  GND GND
+       (.G(\\<const0> ));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd \\gen_sasd.crossbar_sasd_0 
+       (.Q({\\^m_axi_arprot ,\\^m_axi_awaddr ,\\^m_axi_araddr }),
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_bvalid(s_axi_bvalid),
+        .\\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_crossbar_sasd
+   (Q,
+    \\s_axi_rdata[31] ,
+    s_axi_bvalid,
+    m_axi_bready,
+    s_axi_wready,
+    m_axi_wvalid,
+    m_axi_awvalid,
+    m_axi_arvalid,
+    s_axi_awready,
+    s_axi_arready,
+    s_axi_rvalid,
+    m_axi_rready,
+    s_axi_bresp,
+    aresetn,
+    aclk,
+    s_axi_bready,
+    s_axi_wvalid,
+    s_axi_rready,
+    m_axi_wready,
+    m_axi_bvalid,
+    m_axi_awready,
+    m_axi_arready,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_awprot,
+    s_axi_araddr,
+    s_axi_awaddr,
+    m_axi_rvalid,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_bresp,
+    s_axi_awvalid);
+  output [34:0]Q;
+  output [33:0]\\s_axi_rdata[31] ;
+  output [0:0]s_axi_bvalid;
+  output [2:0]m_axi_bready;
+  output [0:0]s_axi_wready;
+  output [2:0]m_axi_wvalid;
+  output [2:0]m_axi_awvalid;
+  output [2:0]m_axi_arvalid;
+  output [0:0]s_axi_awready;
+  output [0:0]s_axi_arready;
+  output [0:0]s_axi_rvalid;
+  output [2:0]m_axi_rready;
+  output [1:0]s_axi_bresp;
+  input aresetn;
+  input aclk;
+  input [0:0]s_axi_bready;
+  input [0:0]s_axi_wvalid;
+  input [0:0]s_axi_rready;
+  input [2:0]m_axi_wready;
+  input [2:0]m_axi_bvalid;
+  input [2:0]m_axi_awready;
+  input [2:0]m_axi_arready;
+  input [2:0]s_axi_arprot;
+  input [0:0]s_axi_arvalid;
+  input [2:0]s_axi_awprot;
+  input [31:0]s_axi_araddr;
+  input [31:0]s_axi_awaddr;
+  input [2:0]m_axi_rvalid;
+  input [95:0]m_axi_rdata;
+  input [5:0]m_axi_rresp;
+  input [5:0]m_axi_bresp;
+  input [0:0]s_axi_awvalid;
+
+  wire [34:0]Q;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire addr_arbiter_inst_n_4;
+  wire addr_arbiter_inst_n_43;
+  wire addr_arbiter_inst_n_44;
+  wire addr_arbiter_inst_n_45;
+  wire addr_arbiter_inst_n_47;
+  wire addr_arbiter_inst_n_5;
+  wire addr_arbiter_inst_n_53;
+  wire addr_arbiter_inst_n_54;
+  wire addr_arbiter_inst_n_59;
+  wire addr_arbiter_inst_n_6;
+  wire addr_arbiter_inst_n_60;
+  wire addr_arbiter_inst_n_69;
+  wire addr_arbiter_inst_n_70;
+  wire aresetn;
+  wire aresetn_d;
+  wire \\gen_decerr.decerr_slave_inst_n_2 ;
+  wire \\gen_decerr.decerr_slave_inst_n_3 ;
+  wire \\gen_decerr.decerr_slave_inst_n_4 ;
+  wire \\gen_decerr.decerr_slave_inst_n_5 ;
+  wire \\gen_decerr.decerr_slave_inst_n_6 ;
+  wire \\gen_decerr.decerr_slave_inst_n_7 ;
+  wire [1:0]m_atarget_enc;
+  wire \\m_atarget_enc[0]_i_1_n_0 ;
+  wire \\m_atarget_enc[1]_i_1_n_0 ;
+  wire [3:0]m_atarget_hot;
+  wire [0:0]m_atarget_hot0;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_arvalid;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [2:0]m_axi_wvalid;
+  wire [1:0]m_ready_d;
+  wire [2:2]m_ready_d0;
+  wire [0:0]m_ready_d0_0;
+  wire [2:0]m_ready_d_1;
+  wire m_valid_i;
+  wire [3:3]mi_bvalid;
+  wire [3:3]mi_wready;
+  wire p_1_in;
+  wire reg_slice_r_n_7;
+  wire reg_slice_r_n_8;
+  wire reset;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire [0:0]s_axi_wready;
+  wire [0:0]s_axi_wvalid;
+  wire sr_rvalid;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_addr_arbiter_sasd addr_arbiter_inst
+       (.D({addr_arbiter_inst_n_4,addr_arbiter_inst_n_5,addr_arbiter_inst_n_6,m_atarget_hot0}),
+        .E(p_1_in),
+        .Q(Q),
+        .SR(reset),
+        .aa_grant_any(aa_grant_any),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\aresetn_d_reg[1] ({reg_slice_r_n_7,reg_slice_r_n_8}),
+        .\\gen_axilite.s_axi_arready_i_reg (\\gen_decerr.decerr_slave_inst_n_6 ),
+        .\\gen_axilite.s_axi_awready_i_reg (addr_arbiter_inst_n_70),
+        .\\gen_axilite.s_axi_awready_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\gen_axilite.s_axi_awready_i_reg_1 (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_54),
+        .\\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_60),
+        .\\gen_axilite.s_axi_bvalid_i_reg_1 (addr_arbiter_inst_n_69),
+        .\\gen_axilite.s_axi_bvalid_i_reg_2 (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\gen_axilite.s_axi_rvalid_i_reg (addr_arbiter_inst_n_44),
+        .\\gen_axilite.s_axi_rvalid_i_reg_0 (\\gen_decerr.decerr_slave_inst_n_7 ),
+        .\\m_atarget_hot_reg[2] (addr_arbiter_inst_n_43),
+        .\\m_atarget_hot_reg[3] (m_atarget_hot),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_wvalid(m_axi_wvalid),
+        .m_ready_d(m_ready_d),
+        .m_ready_d0(m_ready_d0),
+        .m_ready_d0_1(m_ready_d0_0),
+        .m_ready_d_0(m_ready_d_1),
+        .\\m_ready_d_reg[0] (addr_arbiter_inst_n_53),
+        .\\m_ready_d_reg[0]_0 (\\gen_decerr.decerr_slave_inst_n_2 ),
+        .\\m_ready_d_reg[2] (addr_arbiter_inst_n_59),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg(addr_arbiter_inst_n_47),
+        .mi_bvalid(mi_bvalid),
+        .mi_wready(mi_wready),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid),
+        .s_ready_i_reg(addr_arbiter_inst_n_45),
+        .sr_rvalid(sr_rvalid));
+  FDRE #(
+    .INIT(1\'b0)) 
+    aresetn_d_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(aresetn),
+        .Q(aresetn_d),
+        .R(1\'b0));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave \\gen_decerr.decerr_slave_inst 
+       (.Q(m_atarget_enc),
+        .SR(reset),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_54),
+        .\\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_60),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0] (\\gen_decerr.decerr_slave_inst_n_2 ),
+        .\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (\\gen_decerr.decerr_slave_inst_n_5 ),
+        .\\m_atarget_hot_reg[3] (addr_arbiter_inst_n_69),
+        .\\m_atarget_hot_reg[3]_0 (addr_arbiter_inst_n_70),
+        .\\m_atarget_hot_reg[3]_1 (m_atarget_hot[3]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wready(m_axi_wready),
+        .m_ready_d(m_ready_d_1[1:0]),
+        .\\m_ready_d_reg[0] (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\m_ready_d_reg[1] (\\gen_decerr.decerr_slave_inst_n_6 ),
+        .\\m_ready_d_reg[1]_0 (addr_arbiter_inst_n_44),
+        .\\m_ready_d_reg[2] (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .m_valid_i_reg(\\gen_decerr.decerr_slave_inst_n_7 ),
+        .mi_bvalid(mi_bvalid),
+        .mi_wready(mi_wready));
+  (* SOFT_HLUTNM = ""soft_lutpair33"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\m_atarget_enc[0]_i_1 
+       (.I0(addr_arbiter_inst_n_43),
+        .I1(Q[16]),
+        .O(\\m_atarget_enc[0]_i_1_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair33"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\m_atarget_enc[1]_i_1 
+       (.I0(Q[17]),
+        .I1(addr_arbiter_inst_n_43),
+        .O(\\m_atarget_enc[1]_i_1_n_0 ));
+  FDRE \\m_atarget_enc_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_enc[0]_i_1_n_0 ),
+        .Q(m_atarget_enc[0]),
+        .R(reset));
+  FDRE \\m_atarget_enc_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_enc[1]_i_1_n_0 ),
+        .Q(m_atarget_enc[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_atarget_hot0),
+        .Q(m_atarget_hot[0]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_6),
+        .Q(m_atarget_hot[1]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_5),
+        .Q(m_atarget_hot[2]),
+        .R(reset));
+  FDRE \\m_atarget_hot_reg[3] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(addr_arbiter_inst_n_4),
+        .Q(m_atarget_hot[3]),
+        .R(reset));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice reg_slice_r
+       (.E(p_1_in),
+        .Q(m_atarget_hot[2:0]),
+        .SR(reset),
+        .aa_grant_any(aa_grant_any),
+        .aa_grant_rnw(aa_grant_rnw),
+        .aa_rready(aa_rready),
+        .aclk(aclk),
+        .\\aresetn_d_reg[0]_0 (addr_arbiter_inst_n_45),
+        .\\aresetn_d_reg[1]_0 (addr_arbiter_inst_n_47),
+        .\\m_atarget_enc_reg[1] (m_atarget_enc),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_ready_d(m_ready_d[0]),
+        .m_ready_d0(m_ready_d0_0),
+        .m_valid_i(m_valid_i),
+        .m_valid_i_reg_0({reg_slice_r_n_7,reg_slice_r_n_8}),
+        .\\s_axi_rdata[31] (\\s_axi_rdata[31] ),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .sr_rvalid(sr_rvalid));
+  LUT5 #(
+    .INIT(32\'hFEF2CEC2)) 
+    \\s_axi_bresp[0]_INST_0 
+       (.I0(m_axi_bresp[0]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_bresp[2]),
+        .I4(m_axi_bresp[4]),
+        .O(s_axi_bresp[0]));
+  LUT5 #(
+    .INIT(32\'hFEF2CEC2)) 
+    \\s_axi_bresp[1]_INST_0 
+       (.I0(m_axi_bresp[1]),
+        .I1(m_atarget_enc[0]),
+        .I2(m_atarget_enc[1]),
+        .I3(m_axi_bresp[3]),
+        .I4(m_axi_bresp[5]),
+        .O(s_axi_bresp[1]));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0 splitter_ar
+       (.aa_grant_rnw(aa_grant_rnw),
+        .aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_arready_i_reg (\\gen_decerr.decerr_slave_inst_n_6 ),
+        .m_ready_d(m_ready_d),
+        .m_ready_d0(m_ready_d0_0),
+        .m_valid_i(m_valid_i));
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter splitter_aw
+       (.aclk(aclk),
+        .aresetn_d(aresetn_d),
+        .\\gen_axilite.s_axi_awready_i_reg (\\gen_decerr.decerr_slave_inst_n_4 ),
+        .\\gen_axilite.s_axi_bvalid_i_reg (\\gen_decerr.decerr_slave_inst_n_3 ),
+        .\\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_59),
+        .\\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_54),
+        .\\gen_no_arbiter.grant_rnw_reg_1 (addr_arbiter_inst_n_60),
+        .\\gen_no_arbiter.grant_rnw_reg_2 (addr_arbiter_inst_n_53),
+        .m_ready_d(m_ready_d_1),
+        .m_ready_d0(m_ready_d0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_decerr_slave
+   (mi_bvalid,
+    mi_wready,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0] ,
+    \\m_ready_d_reg[2] ,
+    \\m_ready_d_reg[0] ,
+    \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
+    \\m_ready_d_reg[1] ,
+    m_valid_i_reg,
+    SR,
+    \\m_atarget_hot_reg[3] ,
+    aclk,
+    \\m_atarget_hot_reg[3]_0 ,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    m_ready_d,
+    \\gen_no_arbiter.grant_rnw_reg_0 ,
+    m_axi_wready,
+    Q,
+    m_axi_bvalid,
+    m_axi_awready,
+    m_axi_arready,
+    m_axi_rvalid,
+    \\m_ready_d_reg[1]_0 ,
+    aa_rready,
+    \\m_atarget_hot_reg[3]_1 ,
+    aresetn_d);
+  output [0:0]mi_bvalid;
+  output [0:0]mi_wready;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0] ;
+  output \\m_ready_d_reg[2] ;
+  output \\m_ready_d_reg[0] ;
+  output \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  output \\m_ready_d_reg[1] ;
+  output m_valid_i_reg;
+  input [0:0]SR;
+  input \\m_atarget_hot_reg[3] ;
+  input aclk;
+  input \\m_atarget_hot_reg[3]_0 ;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input [1:0]m_ready_d;
+  input \\gen_no_arbiter.grant_rnw_reg_0 ;
+  input [2:0]m_axi_wready;
+  input [1:0]Q;
+  input [2:0]m_axi_bvalid;
+  input [2:0]m_axi_awready;
+  input [2:0]m_axi_arready;
+  input [2:0]m_axi_rvalid;
+  input \\m_ready_d_reg[1]_0 ;
+  input aa_rready;
+  input [0:0]\\m_atarget_hot_reg[3]_1 ;
+  input aresetn_d;
+
+  wire [1:0]Q;
+  wire [0:0]SR;
+  wire aa_rready;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_i_1_n_0 ;
+  wire \\gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg_0 ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0] ;
+  wire \\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
+  wire \\m_atarget_hot_reg[3] ;
+  wire \\m_atarget_hot_reg[3]_0 ;
+  wire [0:0]\\m_atarget_hot_reg[3]_1 ;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_bvalid;
+  wire [2:0]m_axi_rvalid;
+  wire [2:0]m_axi_wready;
+  wire [1:0]m_ready_d;
+  wire \\m_ready_d_reg[0] ;
+  wire \\m_ready_d_reg[1] ;
+  wire \\m_ready_d_reg[1]_0 ;
+  wire \\m_ready_d_reg[2] ;
+  wire m_valid_i_reg;
+  wire [3:3]mi_arready;
+  wire [0:0]mi_bvalid;
+  wire [3:3]mi_rvalid;
+  wire [0:0]mi_wready;
+
+  LUT5 #(
+    .INIT(32\'hAA2A00AA)) 
+    \\gen_axilite.s_axi_arready_i_i_1 
+       (.I0(aresetn_d),
+        .I1(\\m_ready_d_reg[1]_0 ),
+        .I2(\\m_atarget_hot_reg[3]_1 ),
+        .I3(mi_rvalid),
+        .I4(mi_arready),
+        .O(\\gen_axilite.s_axi_arready_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_arready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_arready_i_i_1_n_0 ),
+        .Q(mi_arready),
+        .R(1\'b0));
+  FDRE \\gen_axilite.s_axi_awready_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_hot_reg[3]_0 ),
+        .Q(mi_wready),
+        .R(SR));
+  FDRE \\gen_axilite.s_axi_bvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_atarget_hot_reg[3] ),
+        .Q(mi_bvalid),
+        .R(SR));
+  LUT5 #(
+    .INIT(32\'h0F88FF00)) 
+    \\gen_axilite.s_axi_rvalid_i_i_1 
+       (.I0(mi_arready),
+        .I1(\\m_ready_d_reg[1]_0 ),
+        .I2(aa_rready),
+        .I3(mi_rvalid),
+        .I4(\\m_atarget_hot_reg[3]_1 ),
+        .O(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
+  FDRE \\gen_axilite.s_axi_rvalid_i_reg 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
+        .Q(mi_rvalid),
+        .R(SR));
+  LUT6 #(
+    .INIT(64\'h0D0D0D0DFFFF0DFF)) 
+    \\gen_no_arbiter.m_grant_hot_i[0]_i_5 
+       (.I0(\\m_ready_d_reg[2] ),
+        .I1(\\gen_no_arbiter.grant_rnw_reg ),
+        .I2(m_ready_d[0]),
+        .I3(\\m_ready_d_reg[0] ),
+        .I4(\\gen_no_arbiter.grant_rnw_reg_0 ),
+        .I5(m_ready_d[1]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\m_ready_d[1]_i_3 
+       (.I0(mi_arready),
+        .I1(m_axi_arready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_arready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_arready[0]),
+        .O(\\m_ready_d_reg[1] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\m_ready_d[2]_i_5 
+       (.I0(mi_wready),
+        .I1(m_axi_awready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_awready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_awready[0]),
+        .O(\\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    m_valid_i_i_3
+       (.I0(mi_rvalid),
+        .I1(m_axi_rvalid[1]),
+        .I2(Q[0]),
+        .I3(m_axi_rvalid[2]),
+        .I4(Q[1]),
+        .I5(m_axi_rvalid[0]),
+        .O(m_valid_i_reg));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\s_axi_bvalid[0]_INST_0_i_1 
+       (.I0(mi_bvalid),
+        .I1(m_axi_bvalid[1]),
+        .I2(Q[0]),
+        .I3(m_axi_bvalid[2]),
+        .I4(Q[1]),
+        .I5(m_axi_bvalid[0]),
+        .O(\\m_ready_d_reg[2] ));
+  LUT6 #(
+    .INIT(64\'hAFA0CFCFAFA0C0C0)) 
+    \\s_axi_wready[0]_INST_0_i_1 
+       (.I0(mi_wready),
+        .I1(m_axi_wready[1]),
+        .I2(Q[0]),
+        .I3(m_axi_wready[2]),
+        .I4(Q[1]),
+        .I5(m_axi_wready[0]),
+        .O(\\m_ready_d_reg[0] ));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter
+   (m_ready_d,
+    aresetn_d,
+    m_ready_d0,
+    \\gen_no_arbiter.grant_rnw_reg ,
+    \\gen_no_arbiter.grant_rnw_reg_0 ,
+    \\gen_axilite.s_axi_bvalid_i_reg ,
+    \\gen_no_arbiter.grant_rnw_reg_1 ,
+    \\gen_axilite.s_axi_awready_i_reg ,
+    \\gen_no_arbiter.grant_rnw_reg_2 ,
+    aclk);
+  output [2:0]m_ready_d;
+  input aresetn_d;
+  input [0:0]m_ready_d0;
+  input \\gen_no_arbiter.grant_rnw_reg ;
+  input \\gen_no_arbiter.grant_rnw_reg_0 ;
+  input \\gen_axilite.s_axi_bvalid_i_reg ;
+  input \\gen_no_arbiter.grant_rnw_reg_1 ;
+  input \\gen_axilite.s_axi_awready_i_reg ;
+  input \\gen_no_arbiter.grant_rnw_reg_2 ;
+  input aclk;
+
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_awready_i_reg ;
+  wire \\gen_axilite.s_axi_bvalid_i_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg ;
+  wire \\gen_no_arbiter.grant_rnw_reg_0 ;
+  wire \\gen_no_arbiter.grant_rnw_reg_1 ;
+  wire \\gen_no_arbiter.grant_rnw_reg_2 ;
+  wire [2:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire \\m_ready_d[2]_i_1_n_0 ;
+
+  LUT6 #(
+    .INIT(64\'h000000002A222A2A)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(m_ready_d[1]),
+        .I3(\\gen_no_arbiter.grant_rnw_reg_1 ),
+        .I4(\\gen_axilite.s_axi_awready_i_reg ),
+        .I5(\\gen_no_arbiter.grant_rnw_reg_2 ),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h02'b'0A0202020A020A)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\gen_no_arbiter.grant_rnw_reg ),
+        .I3(m_ready_d[0]),
+        .I4(\\gen_no_arbiter.grant_rnw_reg_0 ),
+        .I5(\\gen_axilite.s_axi_bvalid_i_reg ),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h8088808080888088)) 
+    \\m_ready_d[2]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\gen_no_arbiter.grant_rnw_reg ),
+        .I3(m_ready_d[0]),
+        .I4(\\gen_no_arbiter.grant_rnw_reg_0 ),
+        .I5(\\gen_axilite.s_axi_bvalid_i_reg ),
+        .O(\\m_ready_d[2]_i_1_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[2]_i_1_n_0 ),
+        .Q(m_ready_d[2]),
+        .R(1\'b0));
+endmodule
+
+(* ORIG_REF_NAME = ""axi_crossbar_v2_1_12_splitter"" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_splitter__parameterized0
+   (m_ready_d,
+    aresetn_d,
+    m_ready_d0,
+    \\gen_axilite.s_axi_arready_i_reg ,
+    aa_grant_rnw,
+    m_valid_i,
+    aclk);
+  output [1:0]m_ready_d;
+  input aresetn_d;
+  input [0:0]m_ready_d0;
+  input \\gen_axilite.s_axi_arready_i_reg ;
+  input aa_grant_rnw;
+  input m_valid_i;
+  input aclk;
+
+  wire aa_grant_rnw;
+  wire aclk;
+  wire aresetn_d;
+  wire \\gen_axilite.s_axi_arready_i_reg ;
+  wire [1:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire \\m_ready_d[0]_i_1_n_0 ;
+  wire \\m_ready_d[1]_i_1_n_0 ;
+  wire m_valid_i;
+
+  LUT6 #(
+    .INIT(64\'h0000000008888888)) 
+    \\m_ready_d[0]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\gen_axilite.s_axi_arready_i_reg ),
+        .I3(aa_grant_rnw),
+        .I4(m_valid_i),
+        .I5(m_ready_d[1]),
+        .O(\\m_ready_d[0]_i_1_n_0 ));
+  LUT6 #(
+    .INIT(64\'h2222222220000000)) 
+    \\m_ready_d[1]_i_1 
+       (.I0(aresetn_d),
+        .I1(m_ready_d0),
+        .I2(\\gen_axilite.s_axi_arready_i_reg ),
+        .I3(aa_grant_rnw),
+        .I4(m_valid_i),
+        .I5(m_ready_d[1]),
+        .O(\\m_ready_d[1]_i_1_n_0 ));
+  FDRE \\m_ready_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[0]_i_1_n_0 ),
+        .Q(m_ready_d[0]),
+        .R(1\'b0));
+  FDRE \\m_ready_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\m_ready_d[1]_i_1_n_0 ),
+        .Q(m_ready_d[1]),
+        .R(1\'b0));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_11_axic_register_slice
+   (sr_rvalid,
+    aa_rready,
+    m_ready_d0,
+    s_axi_rvalid,
+    m_axi_rready,
+    m_valid_i_reg_0,
+    \\s_axi_rdata[31] ,
+    \\aresetn_d_reg[1]_0 ,
+    aclk,
+    \\aresetn_d_reg[0]_0 ,
+    s_axi_rready,
+    m_valid_i,
+    aa_grant_rnw,
+    m_ready_d,
+    aa_grant_any,
+    Q,
+    m_axi_rdata,
+    \\m_atarget_enc_reg[1] ,
+    m_axi_rresp,
+    SR,
+    E);
+  output sr_rvalid;
+  output aa_rready;
+  output [0:0]m_ready_d0;
+  output [0:0]s_axi_rvalid;
+  output [2:0]m_axi_rready;
+  output [1:0]m_valid_i_reg_0;
+  output [33:0]\\s_axi_rdata[31] ;
+  input \\aresetn_d_reg[1]_0 ;
+  input aclk;
+  input \\aresetn_d_reg[0]_0 ;
+  input [0:0]s_axi_rready;
+  input m_valid_i;
+  input aa_grant_rnw;
+  input [0:0]m_ready_d;
+  input aa_grant_any;
+  input [2:0]Q;
+  input [95:0]m_axi_rdata;
+  input [1:0]\\m_atarget_enc_reg[1] ;
+  input [5:0]m_axi_rresp;
+  input [0:0]SR;
+  input [0:0]E;
+
+  wire [0:0]E;
+  wire [2:0]Q;
+  wire [0:0]SR;
+  wire aa_grant_any;
+  wire aa_grant_rnw;
+  wire aa_rready;
+  wire aclk;
+  wire \\aresetn_d_reg[0]_0 ;
+  wire \\aresetn_d_reg[1]_0 ;
+  wire [1:0]\\m_atarget_enc_reg[1] ;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire \\m_payload_i[1]_i_2_n_0 ;
+  wire \\m_payload_i[2]_i_2_n_0 ;
+  wire \\m_payload_i_reg_n_0_[0] ;
+  wire [0:0]m_ready_d;
+  wire [0:0]m_ready_d0;
+  wire m_valid_i;
+  wire [1:0]m_valid_i_reg_0;
+  wire [33:0]\\s_axi_rdata[31] ;
+  wire [0:0]s_axi_rready;
+  wire [0:0]s_axi_rvalid;
+  wire [34:0]skid_buffer;
+  wire \\skid_buffer[10]_i_1_n_0 ;
+  wire \\skid_buffer[11]_i_1_n_0 ;
+  wire \\skid_buffer[12]_i_1_n_0 ;
+  wire \\skid_buffer[13]_i_1_n_0 ;
+  wire \\skid_buffer[14]_i_1_n_0 ;
+  wire \\skid_buffer[15]_i_1_n_0 ;
+  wire \\skid_buffer[16]_i_1_n_0 ;
+  wire \\skid_buffer[17]_i_1_n_0 ;
+  wire \\skid_buffer[18]_i_1_n_0 ;
+  wire \\skid_buffer[19]_i_1_n_0 ;
+  wire \\skid_buffer[20]_i_1_n_0 ;
+  wire \\skid_buffer[21]_i_1_n_0 ;
+  wire \\skid_buffer[22]_i_1_n_0 ;
+  wire \\skid_buffer[23]_i_1_n_0 ;
+  wire \\skid_buffer[24]_i_1_n_0 ;
+  wire \\skid_buffer[25]_i_1_n_0 ;
+  wire \\skid_buffer[26]_i_1_n_0 ;
+  wire \\skid_buffer[27]_i_1_n_0 ;
+  wire \\skid_buffer[28]_i_1_n_0 ;
+  wire \\skid_buffer[29]_i_1_n_0 ;
+  wire \\skid_buffer[30]_i_1_n_0 ;
+  wire \\skid_buffer[31]_i_1_n_0 ;
+  wire \\skid_buffer[32]_i_1_n_0 ;
+  wire \\skid_buffer[33]_i_1_n_0 ;
+  wire \\skid_buffer[34]_i_1_n_0 ;
+  wire \\skid_buffer[3]_i_1_n_0 ;
+  wire \\skid_buffer[4]_i_1_n_0 ;
+  wire \\skid_buffer[5]_i_1_n_0 ;
+  wire \\skid_buffer[6]_i_1_n_0 ;
+  wire \\skid_buffer[7]_i_1_n_0 ;
+  wire \\skid_buffer[8]_i_1_n_0 ;
+  wire \\skid_buffer[9]_i_1_n_0 ;
+  wire \\skid_buffer_reg_n_0_[0] ;
+  wire \\skid_buffer_reg_n_0_[10] ;
+  wire \\skid_buffer_reg_n_0_[11] ;
+  wire \\skid_buffer_reg_n_0_[12] ;
+  wire \\skid_buffer_reg_n_0_[13] ;
+  wire \\skid_buffer_reg_n_0_[14] ;
+  wire \\skid_buffer_reg_n_0_[15] ;
+  wire \\skid_buffer_reg_n_0_[16] ;
+  wire \\skid_buffer_reg_n_0_[17] ;
+  wire \\skid_buffer_reg_n_0_[18] ;
+  wire \\skid_buffer_reg_n_0_[19] ;
+  wire \\skid_buffer_reg_n_0_[1] ;
+  wire \\skid_buffer_reg_n_0_[20] ;
+  wire \\skid_buffer_reg_n_0_[21] ;
+  wire \\skid_buffer_reg_n_0_[22] ;
+  wire \\skid_buffer_reg_n_0_[23] ;
+  wire \\skid_buffer_reg_n_0_[24] ;
+  wire \\skid_buffer_reg_n_0_[25] ;
+  wire \\skid_buffer_reg_n_0_[26] ;
+  wire \\skid_buffer_reg_n_0_[27] ;
+  wire \\skid_buffer_reg_n_0_[28] ;
+  wire \\skid_buffer_reg_n_0_[29] ;
+  wire \\skid_buffer_reg_n_0_[2] ;
+  wire \\skid_buffer_reg_n_0_[30] ;
+  wire \\skid_buffer_reg_n_0_[31] ;
+  wire \\skid_buffer_reg_n_0_[32] ;
+  wire \\skid_buffer_reg_n_0_[33] ;
+  wire \\skid_buffer_reg_n_0_[34] ;
+  wire \\skid_buffer_reg_n_0_[3] ;
+  wire \\skid_buffer_reg_n_0_[4] ;
+  wire \\skid_buffer_reg_n_0_[5] ;
+  wire \\skid_buffer_reg_n_0_[6] ;
+  wire \\skid_buffer_reg_n_0_[7] ;
+  wire \\skid_buffer_reg_n_0_[8] ;
+  wire \\skid_buffer_reg_n_0_[9] ;
+  wire sr_rvalid;
+
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(1\'b1),
+        .Q(m_valid_i_reg_0[0]),
+        .R(SR));
+  FDRE #(
+    .INIT(1\'b0)) 
+    \\aresetn_d_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(m_valid_i_reg_0[0]),
+        .Q(m_valid_i_reg_0[1]),
+        .R(SR));
+  (* SOFT_HLUTNM = ""soft_lutpair32"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[0]_INST_0 
+       (.I0(aa_rready),
+        .I1(Q[0]),
+        .O(m_axi_rready[0]));
+  (* SOFT_HLUTNM = ""soft_lutpair32"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[1]_INST_0 
+       (.I0(aa_rready),
+        .I1(Q[1]),
+        .O(m_axi_rready[1]));
+  (* SOFT_HLUTNM = ""soft_lutpair31"" *) 
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\m_axi_rready[2]_INST_0 
+       (.I0(aa_rready),
+        .I1(Q[2]),
+        .O(m_axi_rready[2]));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[10]_i_1 
+       (.I0(\\skid_buffer[10]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[10] ),
+        .O(skid_buffer[10]));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[11]_i_1 
+       (.I0(\\skid_buffer[11]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[11] ),
+        .O(skid_buffer[11]));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[12]_i_1 
+       (.I0(\\skid_buffer[12]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[12] ),
+        .O(skid_buffer[12]));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[13]_i_1 
+       (.I0(\\skid_buffer[13]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[13] ),
+        .O(skid_buffer[13]));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[14]_i_1 
+       (.I0(\\skid_buffer[14]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[14] ),
+        .O(skid_buffer[14]));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[15]_i_1 
+       (.I0(\\skid_buffer[15]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[15] ),
+        .O(skid_buffer[15]));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[16]_i_1 
+       (.I0(\\skid_buffer[16]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[16] ),
+        .O(skid_buffer[16]));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[17]_i_1 
+       (.I0(\\skid_buffer[17]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[17] ),
+        .O(skid_buffer[17]));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[18]_i_1 
+       (.I0(\\skid_buffer[18]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[18] ),
+        .O(skid_buffer[18]));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[19]_i_1 
+       (.I0(\\skid_buffer[19]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[19] ),
+        .O(skid_buffer[19]));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT3 #(
+    .INIT(8\'h0E)) 
+    \\m_payload_i[1]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[1] ),
+        .I1(aa_rready),
+        .I2(\\m_payload_i[1]_i_2_n_0 ),
+        .O(skid_buffer[1]));
+  LUT6 #(
+    .INIT(64\'h0055330F00000000)) 
+    \\m_payload_i[1]_i_2 
+       (.I0(m_axi_rresp[2]),
+        .I1(m_axi_rresp[4]),
+        .I2(m_axi_rresp[0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(\\m_atarget_enc_reg[1] [0]),
+        .I5(aa_rready),
+        .O(\\m_payload_i[1]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[20]_i_1 
+       (.I0(\\skid_buffer[20]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[20] ),
+        .O(skid_buffer[20]));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[21]_i_1 
+       (.I0(\\skid_buffer[21]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[21] ),
+        .O(skid_buffer[21]));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[22]_i_1 
+       (.I0(\\skid_buffer[22]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[22] ),
+        .O(skid_buffer[22]));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[23]_i_1 
+       (.I0(\\skid_buffer[23]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[23] ),
+        .O(skid_buffer[23]));
+  (* SOFT_HLUTNM = ""soft_lutpair21"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[24]_i_1 
+       (.I0(\\skid_buffer[24]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[24] ),
+        .O(skid_buffer[24]));
+  (* SOFT_HLUTNM = ""soft_lutpair22"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[25]_i_1 
+       (.I0(\\skid_buffer[25]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[25] ),
+        .O(skid_buffer[25]));
+  (* SOFT_HLUTNM = ""soft_lutpair23"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[26]_i_1 
+       (.I0(\\skid_buffer[26]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[26] ),
+        .O(skid_buffer[26]));
+  (* SOFT_HLUTNM = ""soft_lutpair24"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[27]_i_1 
+       (.I0(\\skid_buffer[27]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[27] ),
+        .O(skid_buffer[27]));
+  (* SOFT_HLUTNM = ""soft_lutpair25"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[28]_i_1 
+       (.I0(\\skid_buffer[28]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[28] ),
+        .O(skid_buffer[28]));
+  (* SOFT_HLUTNM = ""soft_lutpair26"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[29]_i_1 
+       (.I0(\\skid_buffer[29]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[29] ),
+        .O(skid_buffer[29]));
+  (* SOFT_HLUTNM = ""soft_lutpair30"" *) 
+  LUT3 #(
+    .INIT(8\'h0E)) 
+    \\m_payload_i[2]_i_1 
+       (.I0(\\skid_buffer_reg_n_0_[2] ),
+        .I1(aa_rready),
+        .I2(\\m_payload_i[2]_i_2_n_0 ),
+        .O(skid_buffer[2]));
+  LUT6 #(
+    .INIT(64\'h00440C0000440CCC)) 
+    \\m_payload_i[2]_i_2 
+       (.I0(m_axi_rresp[5]),
+        .I1(aa_rready),
+        .I2(m_axi_rresp[3]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(\\m_atarget_enc_reg[1] [1]),
+        .I5(m_axi_rresp[1]),
+        .O(\\m_payload_i[2]_i_2_n_0 ));
+  (* SOFT_HLUTNM = ""soft_lutpair27"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[30]_i_1 
+       (.I0(\\skid_buffer[30]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[30] ),
+        .O(skid_buffer[30]));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[31]_i_1 
+       (.I0(\\skid_buffer[31]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[31] ),
+        .O(skid_buffer[31]));
+  (* SOFT_HLUTNM = ""soft_lutpair28"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[32]_i_1 
+       (.I0(\\skid_buffer[32]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[32] ),
+        .O(skid_buffer[32]));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[33]_i_1 
+       (.I0(\\skid_buffer[33]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[33] ),
+        .O(skid_buffer[33]));
+  (* SOFT_HLUTNM = ""soft_lutpair29"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[34]_i_2 
+       (.I0(\\skid_buffer[34]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[34] ),
+        .O(skid_buffer[34]));
+  (* SOFT_HLUTNM = ""soft_lutpair14"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[3]_i_1 
+       (.I0(\\skid_buffer[3]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[3] ),
+        .O(skid_buffer[3]));
+  (* SOFT_HLUTNM = ""soft_lutpair15"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[4]_i_1 
+       (.I0(\\skid_buffer[4]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[4] ),
+        .O(skid_buffer[4]));
+  (* SOFT_HLUTNM = ""soft_lutpair16"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[5]_i_1 
+       (.I0(\\skid_buffer[5]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[5] ),
+        .O(skid_buffer[5]));
+  (* SOFT_HLUTNM = ""soft_lutpair17"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[6]_i_1 
+       (.I0(\\skid_buffer[6]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[6] ),
+        .O(skid_buffer[6]));
+  (* SOFT_HLUTNM = ""soft_lutpair18"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[7]_i_1 
+       (.I0(\\skid_buffer[7]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[7] ),
+        .O(skid_buffer[7]));
+  (* SOFT_HLUTNM = ""soft_lutpair19"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[8]_i_1 
+       (.I0(\\skid_buffer[8]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[8] ),
+        .O(skid_buffer[8]));
+  (* SOFT_HLUTNM = ""soft_lutpair20"" *) 
+  LUT3 #(
+    .INIT(8\'hB8)) 
+    \\m_payload_i[9]_i_1 
+       (.I0(\\skid_buffer[9]_i_1_n_0 ),
+        .I1(aa_rready),
+        .I2(\\skid_buffer_reg_n_0_[9] ),
+        .O(skid_buffer[9]));
+  FDRE \\m_payload_i_reg[0] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[0]),
+        .Q(\\m_payload_i_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[10] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[10]),
+        .Q(\\s_axi_rdata[31] [9]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[11] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[11]),
+        .Q(\\s_axi_rdata[31] [10]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[12] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[12]),
+        .Q(\\s_axi_rdata[31] [11]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[13] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[13]),
+        .Q(\\s_axi_rdata[31] [12]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[14] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[14]),
+        .Q(\\s_axi_rdata[31] [13]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[15] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[15]),
+        .Q(\\s_axi_rdata[31] [14]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[16] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[16]),
+        .Q(\\s_axi_rdata[31] [15]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[17] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[17]),
+        .Q(\\s_axi_rdata[31] [16]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[18] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[18]),
+        .Q(\\s_axi_rdata[31] [17]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[19] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[19]),
+        .Q(\\s_axi_rdata[31] [18]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[1] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[1]),
+        .Q(\\s_axi_rdata[31] [0]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[20] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[20]),
+        .Q(\\s_axi_rdata[31] [19]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[21] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[21]),
+        .Q(\\s_axi_rdata[31] [20]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[22] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[22]),
+        .Q(\\s_axi_rdata[31] [21]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[23] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[23]),
+        .Q(\\s_axi_rdata[31] [22]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[24] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[24]),
+        .Q(\\s_axi_rdata[31] [23]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[25] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[25]),
+        .Q(\\s_axi_rdata[31] [24]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[26] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[26]),
+        .Q(\\s_axi_rdata[31] [25]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[27] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[27]),
+        .Q(\\s_axi_rdata[31] [26]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[28] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[28]),
+        .Q(\\s_axi_rdata[31] [27]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[29] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[29]),
+        .Q(\\s_axi_rdata[31] [28]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[2] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[2]),
+        .Q(\\s_axi_rdata[31] [1]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[30] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[30]),
+        .Q(\\s_axi_rdata[31] [29]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[31] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[31]),
+        .Q(\\s_axi_rdata[31] [30]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[32] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[32]),
+        .Q(\\s_axi_rdata[31] [31]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[33] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[33]),
+        .Q(\\s_axi_rdata[31] [32]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[34] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[34]),
+        .Q(\\s_axi_rdata[31] [33]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[3] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[3]),
+        .Q(\\s_axi_rdata[31] [2]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[4] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[4]),
+        .Q(\\s_axi_rdata[31] [3]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[5] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[5]),
+        .Q(\\s_axi_rdata[31] [4]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[6] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[6]),
+        .Q(\\s_axi_rdata[31] [5]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[7] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[7]),
+        .Q(\\s_axi_rdata[31] [6]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[8] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[8]),
+        .Q(\\s_axi_rdata[31] [7]),
+        .R(1\'b0));
+  FDRE \\m_payload_i_reg[9] 
+       (.C(aclk),
+        .CE(E),
+        .D(skid_buffer[9]),
+        .Q(\\s_axi_rdata[31] [8]),
+        .R(1\'b0));
+  LUT6 #(
+    .INIT(64\'hFFFFFFFF80000000)) 
+    \\m_ready_d[1]_i_2 
+       (.I0(\\m_payload_i_reg_n_0_[0] ),
+        .I1(sr_rvalid),
+        .I2(s_axi_rready),
+        .I3(m_valid_i),
+        .I4(aa_grant_rnw),
+        .I5(m_ready_d),
+        .O(m_ready_d0));
+  FDRE m_valid_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\aresetn_d_reg[1]_0 ),
+        .Q(sr_rvalid),
+        .R(1\'b0));
+  LUT2 #(
+    .INIT(4\'h8)) 
+    \\s_axi_rvalid[0]_INST_0 
+       (.I0(sr_rvalid),
+        .I1(aa_grant_any),
+        .O(s_axi_rvalid));
+  FDRE s_ready_i_reg
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(\\aresetn_d_reg[0]_0 ),
+        .Q(aa_rready),
+        .R(1\'b0));
+  (* SOFT_HLUTNM = ""soft_lutpair31"" *) 
+  LUT2 #(
+    .INIT(4\'hE)) 
+    \\skid_buffer[0]_i_1 
+       (.I0(aa_rready),
+        .I1(\\skid_buffer_reg_n_0_[0] ),
+        .O(skid_buffer[0]));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[10]_i_1 
+       (.I0(m_axi_rdata[71]),
+        .I1(m_axi_rdata[39]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[7]),
+        .O(\\skid_buffer[10]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[11]_i_1 
+       (.I0(m_axi_rdata[72]),
+        .I1(m_axi_rdata[40]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[8]),
+        .O(\\skid_buffer[11]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[12]_i_1 
+       (.I0(m_axi_rdata[9]),
+        .I1(m_axi_rdata[73]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[41]),
+        .O(\\skid_buffer[12]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[13]_i_1 
+       (.I0(m_axi_rdata[10]),
+        .I1(m_axi_rdata[74]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[42]),
+        .O(\\skid_buffer[13]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[14]_i_1 
+       (.I0(m_axi_rdata[75]),
+        .I1(m_axi_rdata[43]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[11]),
+        .O(\\skid_buffer[14]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[15]_i_1 
+       (.I0(m_axi_rdata[76]),
+        .I1(m_axi_rdata[44]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[12]),
+        .O(\\skid_buffer[15]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[16]_i_1 
+       (.I0(m_axi_rdata[13]),
+        .I1(m_axi_rdata[77]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[45]),
+        .O(\\skid_buffer[16]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[17]_i_1 
+       (.I0(m_axi_rdata[78]),
+        .I1(m_axi_rdata[46]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[14]),
+        .O(\\skid_buffer[17]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[18]_i_1 
+       (.I0(m_axi_rdata[79]),
+        .I1(m_axi_rdata[47]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[15]),
+        .O(\\skid_buffer[18]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[19]_i_1 
+       (.I0(m_axi_rdata[80]),
+        .I1(m_axi_rdata[48]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[16]),
+        .O(\\skid_buffer[19]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[20]_i_1 
+       (.I0(m_axi_rdata[81]),
+        .I1(m_axi_rdata[49]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[17]),
+        .O(\\skid_buffer[20]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[21]_i_1 
+       (.I0(m_axi_rdata[18]),
+        .I1(m_axi_rdata[50]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[82]),
+        .O(\\skid_buffer[21]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[22]_i_1 
+       (.I0(m_axi_rdata[83]),
+        .I1(m_axi_rdata[51]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[19]),
+        .O(\\skid_buffer[22]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[23]_i_1 
+       (.I0(m_axi_rdata[20]),
+        .I1(m_axi_rdata[84]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[52]),
+        .O(\\skid_buffer[23]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[24]_i_1 
+       (.I0(m_axi_rdata[85]),
+        .I1(m_axi_rdata[53]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[21]),
+        .O(\\skid_buffer[24]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[25]_i_1 
+       (.I0(m_axi_rdata[86]),
+        .I1(m_axi_rdata[54]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[22]),
+        .O(\\skid_buffer[25]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[26]_i_1 
+       (.I0(m_axi_rdata[87]),
+        .I1(m_axi_rdata[55]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[23]),
+        .O(\\skid_buffer[26]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[27]_i_1 
+       (.I0(m_axi_rdata[88]),
+        .I1(m_axi_rdata[56]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[24]),
+        .O(\\skid_buffer[27]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[28]_i_1 
+       (.I0(m_axi_rdata[25]),
+        .I1(m_axi_rdata[57]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[89]),
+        .O(\\skid_buffer[28]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[29]_i_1 
+       (.I0(m_axi_rdata[90]),
+        .I1(m_axi_rdata[58]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[26]),
+        .O(\\skid_buffer[29]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[30]_i_1 
+       (.I0(m_axi_rdata[91]),
+        .I1(m_axi_rdata[59]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[27]),
+        .O(\\skid_buffer[30]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[31]_i_1 
+       (.I0(m_axi_rdata[92]),
+        .I1(m_axi_rdata[60]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[28]),
+        .O(\\skid_buffer[31]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[32]_i_1 
+       (.I0(m_axi_rdata[93]),
+        .I1(m_axi_rdata[61]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[29]),
+        .O(\\skid_buffer[32]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0CAF0CA0)) 
+    \\skid_buffer[33]_i_1 
+       (.I0(m_axi_rdata[62]),
+        .I1(m_axi_rdata[94]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[30]),
+        .O(\\skid_buffer[33]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0FCA00CA)) 
+    \\skid_buffer[34]_i_1 
+       (.I0(m_axi_rdata[31]),
+        .I1(m_axi_rdata[95]),
+        .I2(\\m_atarget_enc_reg[1] [1]),
+        .I3(\\m_atarget_enc_reg[1] [0]),
+        .I4(m_axi_rdata[63]),
+        .O(\\skid_buffer[34]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[3]_i_1 
+       (.I0(m_axi_rdata[64]),
+        .I1(m_axi_rdata[32]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[0]),
+        .O(\\skid_buffer[3]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[4]_i_1 
+       (.I0(m_axi_rdata[65]),
+        .I1(m_axi_rdata[33]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[1]),
+        .O(\\skid_buffer[4]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[5]_i_1 
+       (.I0(m_axi_rdata[66]),
+        .I1(m_axi_rdata[34]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[2]),
+        .O(\\skid_buffer[5]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[6]_i_1 
+       (.I0(m_axi_rdata[67]),
+        .I1(m_axi_rdata[35]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[3]),
+        .O(\\skid_buffer[6]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[7]_i_1 
+       (.I0(m_axi_rdata[68]),
+        .I1(m_axi_rdata[36]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[4]),
+        .O(\\skid_buffer[7]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[8]_i_1 
+       (.I0(m_axi_rdata[69]),
+        .I1(m_axi_rdata[37]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[5]),
+        .O(\\skid_buffer[8]_i_1_n_0 ));
+  LUT5 #(
+    .INIT(32\'h0ACF0AC0)) 
+    \\skid_buffer[9]_i_1 
+       (.I0(m_axi_rdata[70]),
+        .I1(m_axi_rdata[38]),
+        .I2(\\m_atarget_enc_reg[1] [0]),
+        .I3(\\m_atarget_enc_reg[1] [1]),
+        .I4(m_axi_rdata[6]),
+        .O(\\skid_buffer[9]_i_1_n_0 ));
+  FDRE \\skid_buffer_reg[0] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[0]),
+        .Q(\\skid_buffer_reg_n_0_[0] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[10] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[10]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[10] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[11] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[11]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[11] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[12] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[12]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[12] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[13] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[13]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[13] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[14] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[14]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[14] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[15] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[15]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[15] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[16] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[16]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[16] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[17] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[17]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[17] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[18] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[18]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[18] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[19] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[19]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[19] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[1] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[1]),
+        .Q(\\skid_buffer_reg_n_0_[1] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[20] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[20]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[20] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[21] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[21]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[21] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[22] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[22]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[22] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[23] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[23]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[23] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[24] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[24]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[24] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[25] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[25]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[25] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[26] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[26]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[26] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[27] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[27]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[27] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[28] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[28]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[28] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[29] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[29]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[29] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[2] 
+       (.C(aclk),
+        .CE(1\'b1),
+        .D(skid_buffer[2]),
+        .Q(\\skid_buffer_reg_n_0_[2] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[30] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[30]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[30] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[31] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[31]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[31] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[32] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[32]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[32] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[33] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[33]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[33] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[34] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[34]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[34] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[3] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[3]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[3] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[4] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[4]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[4] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[5] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[5]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[5] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[6] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[6]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[6] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[7] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[7]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[7] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[8] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[8]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[8] ),
+        .R(1\'b0));
+  FDRE \\skid_buffer_reg[9] 
+       (.C(aclk),
+        .CE(aa_rready),
+        .D(\\skid_buffer[9]_i_1_n_0 ),
+        .Q(\\skid_buffer_reg_n_0_[9] ),
+        .R(1\'b0));
+endmodule
+
+(* CHECK_LICENSE_TYPE = ""design_1_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}"" *) (* DowngradeIPIdentifiedWarnings = ""yes"" *) (* X_CORE_INFO = ""axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"" *) 
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (aclk,
+    aresetn,
+    s_axi_awaddr,
+    s_axi_awprot,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arprot,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    m_axi_awaddr,
+    m_axi_awprot,
+    m_axi_awvalid,
+    m_axi_awready,
+    m_axi_wdata,
+    m_axi_wstrb,
+    m_axi_wvalid,
+    m_axi_wready,
+    m_axi_bresp,
+    m_axi_bvalid,
+    m_axi_bready,
+    m_axi_araddr,
+    m_axi_arprot,
+    m_axi_arvalid,
+    m_axi_arready,
+    m_axi_rdata,
+    m_axi_rresp,
+    m_axi_rvalid,
+    m_axi_rready);
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLKIF CLK"" *) input aclk;
+  (* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RSTIF RST"" *) input aresetn;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"" *) input [31:0]s_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"" *) input [2:0]s_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"" *) input [0:0]s_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"" *) output [0:0]s_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WDATA"" *) input [31:0]s_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"" *) input [3:0]s_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WVALID"" *) input [0:0]s_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI WREADY"" *) output [0:0]s_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BRESP"" *) output [1:0]s_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BVALID"" *) output [0:0]s_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI BREADY"" *) input [0:0]s_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"" *) input [31:0]s_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"" *) input [2:0]s_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"" *) input [0:0]s_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"" *) output [0:0]s_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RDATA"" *) output [31:0]s_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RRESP"" *) output [1:0]s_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RVALID"" *) output [0:0]s_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S00_AXI RREADY"" *) input [0:0]s_axi_rready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]"" *) output [95:0]m_axi_awaddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]"" *) output [8:0]m_axi_awprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]"" *) output [2:0]m_axi_awvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]"" *) input [2:0]m_axi_awready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]"" *) output [95:0]m_axi_wdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]"" *) output [11:0]m_axi_wstrb;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]"" *) output [2:0]m_axi_wvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]"" *) input [2:0]m_axi_wready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]"" *) input [5:0]m_axi_bresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]"" *) input [2:0]m_axi_bvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]"" *) output [2:0]m_axi_bready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]"" *) output [95:0]m_axi_araddr;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]"" *) output [8:0]m_axi_arprot;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]"" *) output [2:0]m_axi_arvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]"" *) input [2:0]m_axi_arready;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]"" *) input [95:0]m_axi_rdata;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]"" *) input [5:0]m_axi_rresp;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]"" *) input [2:0]m_axi_rvalid;
+  (* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]"" *) output [2:0]m_axi_rready;
+
+  wire aclk;
+  wire aresetn;
+  wire [95:0]m_axi_araddr;
+  wire [8:0]m_axi_arprot;
+  wire [2:0]m_axi_arready;
+  wire [2:0]m_axi_arvalid;
+  wire [95:0]m_axi_awaddr;
+  wire [8:0]m_axi_awprot;
+  wire [2:0]m_axi_awready;
+  wire [2:0]m_axi_awvalid;
+  wire [2:0]m_axi_bready;
+  wire [5:0]m_axi_bresp;
+  wire [2:0]m_axi_bvalid;
+  wire [95:0]m_axi_rdata;
+  wire [2:0]m_axi_rready;
+  wire [5:0]m_axi_rresp;
+  wire [2:0]m_axi_rvalid;
+  wire [95:0]m_axi_wdata;
+  wire [2:0]m_axi_wready;
+  wire [11:0]m_axi_wstrb;
+  wire [2:0]m_axi_wvalid;
+  wire [31:0]s_axi_araddr;
+  wire [2:0]s_axi_arprot;
+  wire [0:0]s_axi_arready;
+  wire [0:0]s_axi_arvalid;
+  wire [31:0]s_axi_awaddr;
+  wire [2:0]s_axi_awprot;
+  wire [0:0]s_axi_awready;
+  wire [0:0]s_axi_awvalid;
+  wire [0:0]s_axi_bready;
+  wire [1:0]s_axi_bresp;
+  wire [0:0]s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire [0:0]s_axi_rready;
+  wire [1:0]s_axi_rresp;
+  wire [0:0]s_axi_rvalid;
+  wire [31:0]s_axi_wdata;
+  wire [0:0]s_axi_wready;
+  wire [3:0]s_axi_wstrb;
+  wire [0:0]s_axi_wvalid;
+  wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED;
+  wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+  wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+  wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED;
+  wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+  wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+  wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED;
+  wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
+  wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+  (* C_AXI_ADDR_WIDTH = ""32"" *) 
+  (* C_AXI_ARUSER_WIDTH = ""1"" *) 
+  (* C_AXI_AWUSER_WIDTH = ""1"" *) 
+  (* C_AXI_BUSER_WIDTH = ""1"" *) 
+  (* C_AXI_DATA_WIDTH = ""32"" *) 
+  (* C_AXI_ID_WIDTH = ""1"" *) 
+  (* C_AXI_PROTOCOL = ""2"" *) 
+  (* C_AXI_RUSER_WIDTH = ""1"" *) 
+  (* C_AXI_SUPPORTS_USER_SIGNALS = ""0"" *) 
+  (* C_AXI_WUSER_WIDTH = ""1"" *) 
+  (* C_CONNECTIVITY_MODE = ""0"" *) 
+  (* C_DEBUG = ""1"" *) 
+  (* C_FAMILY = ""zynq"" *) 
+  (* C_M_AXI_ADDR_WIDTH = ""96\'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"" *) 
+  (* C_M_AXI_BASE_ADDR = ""192\'b000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"" *) 
+  (* C_M_AXI_READ_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_READ_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_SECURE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* C_M_AXI_WRITE_CONNECTIVITY = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_M_AXI_WRITE_ISSUING = ""96\'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"" *) 
+  (* C_NUM_ADDR_RANGES = ""1"" *) 
+  (* C_NUM_MASTER_SLOTS = ""3"" *) 
+  (* C_NUM_SLAVE_SLOTS = ""1"" *) 
+  (* C_R_REGISTER = ""1"" *) 
+  (* C_S_AXI_ARB_PRIORITY = ""0"" *) 
+  (* C_S_AXI_BASE_ID = ""0"" *) 
+  (* C_S_AXI_READ_ACCEPTANCE = ""1"" *) 
+  (* C_S_AXI_SINGLE_THREAD = ""1"" *) 
+  (* C_S_AXI_THREAD_ID_WIDTH = ""0"" *) 
+  (* C_S_AXI_WRITE_ACCEPTANCE = ""1"" *) 
+  (* DowngradeIPIdentifiedWarnings = ""yes"" *) 
+  (* P_ADDR_DECODE = ""1"" *) 
+  (* P_AXI3 = ""1"" *) 
+  (* P_AXI4 = ""0"" *) 
+  (* P_AXILITE = ""2"" *) 
+  (* P_AXILITE_SIZE = ""3\'b010"" *) 
+  (* P_FAMILY = ""zynq"" *) 
+  (* P_INCR = ""2\'b01"" *) 
+  (* P_LEN = ""8"" *) 
+  (* P_LOCK = ""1"" *) 
+  (* P_M_AXI_ERR_MODE = ""96\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_M_AXI_SUPPORTS_READ = ""3\'b111"" *) 
+  (* P_M_AXI_SUPPORTS_WRITE = ""3\'b111"" *) 
+  (* P_ONES = ""65\'b11111111111111111111111111111111111111111111111111111111111111111"" *) 
+  (* P_RANGE_CHECK = ""1"" *) 
+  (* P_S_AXI_BASE_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_HIGH_ID = ""64\'b0000000000000000000000000000000000000000000000000000000000000000"" *) 
+  (* P_S_AXI_SUPPORTS_READ = ""1\'b1"" *) 
+  (* P_S_AXI_SUPPORTS_WRITE = ""1\'b1"" *) 
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_12_axi_crossbar inst
+       (.aclk(aclk),
+        .aresetn(aresetn),
+        .m_axi_araddr(m_axi_araddr),
+        .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]),
+        .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]),
+        .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]),
+        .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]),
+        .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]),
+        .m_axi_arprot(m_axi_arprot),
+        .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]),
+        .m_axi_arready(m_axi_arready),
+        .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
+        .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]),
+        .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
+        .m_axi_arvalid(m_axi_arvalid),
+        .m_axi_awaddr(m_axi_awaddr),
+        .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]),
+        .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]),
+        .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]),
+        .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]),
+        .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]),
+        .m_axi_awprot(m_axi_awprot),
+        .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]),
+        .m_axi_awready(m_axi_awready),
+        .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
+        .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]),
+        .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
+        .m_axi_awvalid(m_axi_awvalid),
+        .m_axi_bid({1\'b0,1\'b0,1\'b0}),
+        .m_axi_bready(m_axi_bready),
+        .m_axi_bresp(m_axi_bresp),
+        .m_axi_buser({1\'b0,1\'b0,1\'b0}),
+        .m_axi_bvalid(m_axi_bvalid),
+        .m_axi_rdata(m_axi_rdata),
+        .m_axi_rid({1\'b0,1\'b0,1\'b0}),
+        .m_axi_rlast({1\'b1,1\'b1,1\'b1}),
+        .m_axi_rready(m_axi_rready),
+        .m_axi_rresp(m_axi_rresp),
+        .m_axi_ruser({1\'b0,1\'b0,1\'b0}),
+        .m_axi_rvalid(m_axi_rvalid),
+        .m_axi_wdata(m_axi_wdata),
+        .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]),
+        .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]),
+        .m_axi_wready(m_axi_wready),
+        .m_axi_wstrb(m_axi_wstrb),
+        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
+        .m_axi_wvalid(m_axi_wvalid),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_arburst({1\'b0,1\'b0}),
+        .s_axi_arcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arid(1\'b0),
+        .s_axi_arlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arlock(1\'b0),
+        .s_axi_arprot(s_axi_arprot),
+        .s_axi_arqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_arready(s_axi_arready),
+        .s_axi_arsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_aruser(1\'b0),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awaddr(s_axi_awaddr),
+        .s_axi_awburst({1\'b0,1\'b0}),
+        .s_axi_awcache({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awid(1\'b0),
+        .s_axi_awlen({1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awlock(1\'b0),
+        .s_axi_awprot(s_axi_awprot),
+        .s_axi_awqos({1\'b0,1\'b0,1\'b0,1\'b0}),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awsize({1\'b0,1\'b0,1\'b0}),
+        .s_axi_awuser(1\'b0),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bresp(s_axi_bresp),
+        .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
+        .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rresp(s_axi_rresp),
+        .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wdata(s_axi_wdata),
+        .s_axi_wid(1\'b0),
+        .s_axi_wlast(1\'b1),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wstrb(s_axi_wstrb),
+        .s_axi_wuser(1\'b0),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1\'bz;
+    reg JTAG_USER_TDO2_GLBL = 1\'bz;
+    reg JTAG_USER_TDO3_GLBL = 1\'bz;
+    reg JTAG_USER_TDO4_GLBL = 1\'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+\tGSR_int = 1\'b1;
+\tPRLD_int = 1\'b1;
+\t#(ROC_WIDTH)
+\tGSR_int = 1\'b0;
+\tPRLD_int = 1\'b0;
+    end
+
+    initial begin
+\tGTS_int = 1\'b1;
+\t#(TOC_WIDTH)
+\tGTS_int = 1\'b0;
+    end
+
+endmodule
+`endif
+"
+"/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_arb_wr.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between 2 write requests from 2 ports.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_arb_wr(
+ rstn,
+ sw_clk,
+ qos1,
+ qos2,
+ prt_dv1,
+ prt_dv2,
+ prt_data1,
+ prt_data2,
+ prt_addr1,
+ prt_addr2,
+ prt_bytes1,
+ prt_bytes2,
+ prt_ack1,
+ prt_ack2,
+ prt_qos,
+ prt_req,
+ prt_data,
+ prt_addr,
+ prt_bytes,
+ prt_ack
+
+);
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+input rstn, sw_clk;
+input [axi_qos_width-1:0] qos1,qos2;
+input [max_burst_bits-1:0] prt_data1,prt_data2;
+input [addr_width-1:0] prt_addr1,prt_addr2;
+input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
+input prt_dv1, prt_dv2, prt_ack;
+output reg prt_ack1,prt_ack2,prt_req;
+output reg [max_burst_bits-1:0] prt_data;
+output reg [addr_width-1:0] prt_addr;
+output reg [max_burst_bytes_width:0] prt_bytes;
+output reg [axi_qos_width-1:0] prt_qos;
+
+parameter wait_req = 2\'b00, serv_req1 = 2\'b01, serv_req2 = 2\'b10,wait_ack_low = 2\'b11;
+reg [1:0] state,temp_state;
+
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ state = wait_req;
+ prt_req = 1\'b0;
+ prt_ack1 = 1\'b0;
+ prt_ack2 = 1\'b0;
+ prt_qos = 0;
+end else begin
+ case(state)
+ wait_req:begin  
+         state = wait_req;
+         prt_ack1 = 1\'b0;
+         prt_ack2 = 1\'b0; 
+         prt_req = 1\'b0;
+         if(prt_dv1 && !prt_dv2) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+           prt_qos = qos1;
+         end else if(!prt_dv1 && prt_dv2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_dv1 && prt_dv2) begin
+           if(qos1 > qos2) begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_data = prt_data1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end else if(qos1 < qos2) begin
+             prt_req = 1;
+             prt_qos = qos2;
+             prt_data = prt_data2;
+             prt_addr = prt_addr2;
+             prt_bytes = prt_bytes2;
+             state = serv_req2;
+           end else begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_data = prt_data1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end
+         end
+       end 
+ serv_req1:begin  
+         state = serv_req1; 
+         prt_ack2 = 1\'b0;
+         if(prt_ack) begin 
+           prt_ack1 = 1\'b1;
+           prt_req = 0;
+           if(prt_dv2) begin
+             prt_req = 1;
+             prt_qos = qos2;
+             prt_data = prt_data2;
+             prt_addr = prt_addr2;
+             prt_bytes = prt_bytes2;
+             state = serv_req2;
+           end else begin
+         //    state = wait_req;
+         state = wait_ack_low;
+           end
+         end
+       end 
+ serv_req2:begin
+         state = serv_req2; 
+         prt_ack1 = 1\'b0;
+         if(prt_ack) begin 
+           prt_ack2 = 1\'b1;
+           prt_req = 0;
+           if(prt_dv1) begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_data = prt_data1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end else begin
+         state = wait_ack_low;
+         //    state = wait_req;
+           end
+         end
+       end 
+ wait_ack_low:begin
+         prt_ack1 = 1\'b0;
+         prt_ack2 = 1\'b0;
+         state = wait_ack_low;
+         if(!prt_ack)
+           state = wait_req;
+       end  
+ endcase
+end /// if else
+end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_arb_rd.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between 2 read requests from 2 ports.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_arb_rd(
+ rstn,
+ sw_clk,
+
+ qos1,
+ qos2,
+
+ prt_req1,
+ prt_req2,
+ prt_bytes1,
+ prt_bytes2,
+ prt_addr1,
+ prt_addr2,
+ prt_data1,
+ prt_data2,
+ prt_dv1,
+ prt_dv2,
+
+ prt_req,
+ prt_qos,
+ prt_addr,
+ prt_bytes,
+ prt_data,
+ prt_dv
+
+);
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+input rstn, sw_clk;
+input [axi_qos_width-1:0] qos1,qos2;
+input prt_req1, prt_req2;
+input [addr_width-1:0] prt_addr1, prt_addr2;
+input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2;
+output reg prt_dv1, prt_dv2;
+output reg [max_burst_bits-1:0] prt_data1,prt_data2;
+
+output reg prt_req;
+output reg [axi_qos_width-1:0] prt_qos;
+output reg [addr_width-1:0] prt_addr;
+output reg [max_burst_bytes_width:0] prt_bytes;
+input [max_burst_bits-1:0] prt_data;
+input prt_dv;
+
+parameter wait_req = 2\'b00, serv_req1 = 2\'b01, serv_req2 = 2\'b10,wait_dv_low = 2\'b11;
+reg [1:0] state;
+
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ state = wait_req;
+ prt_req = 1\'b0;
+ prt_dv1 = 1\'b0;
+ prt_dv2 = 1\'b0;
+ prt_qos = 0;
+end else begin
+ case(state)
+ wait_req:begin  
+         state = wait_req;
+         prt_dv1 = 1\'b0;
+         prt_dv2 = 1\'b0;
+         prt_req = 0;
+         if(prt_req1 && !prt_req2) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(!prt_req1 && prt_req2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_req1 && prt_req2) begin
+           if(qos1 > qos2) begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end else if(qos1 < qos2) begin
+             prt_req = 1;
+             prt_addr = prt_addr2;
+             prt_qos = qos2;
+             prt_bytes = prt_bytes2;
+             state = serv_req2;
+           end else begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end
+         end
+       end 
+ serv_req1:begin  
+         state = serv_req1; 
+         prt_dv2 = 1\'b0;
+         if(prt_dv) begin 
+           prt_dv1 = 1\'b1;
+           prt_data1 = prt_data;
+           prt_req = 0;
+           if(prt_req2) begin
+             prt_req = 1;
+             prt_qos = qos2;
+             prt_addr = prt_addr2;
+             prt_bytes = prt_bytes2;
+             state = serv_req2;
+           end else begin
+             state = wait_dv_low;
+             //state = wait_req;
+           end
+         end
+       end 
+ serv_req2:begin
+         state = serv_req2; 
+         prt_dv1 = 1\'b0;
+         if(prt_dv) begin 
+           prt_dv2 = 1\'b1;
+           prt_data2 = prt_data;
+           prt_req = 0;
+           if(prt_req1) begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end else begin
+             state = wait_dv_low;
+             //state = wait_req;
+           end
+         end
+       end 
+
+ wait_dv_low:begin
+         prt_dv1 = 1\'b0;
+         prt_dv2 = 1\'b0;
+         state = wait_dv_low;
+         if(!prt_dv)
+           state = wait_req;
+       end  
+ endcase
+end /// if else
+end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_arb_wr_4.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between 4 write requests from 4 ports.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_arb_wr_4(
+ rstn,
+ sw_clk,
+
+ qos1,
+ qos2,
+ qos3,
+ qos4,
+
+ prt_dv1,
+ prt_dv2,
+ prt_dv3,
+ prt_dv4,
+
+ prt_data1,
+ prt_data2,
+ prt_data3,
+ prt_data4,
+
+ prt_addr1,
+ prt_addr2,
+ prt_addr3,
+ prt_addr4,
+
+ prt_bytes1,
+ prt_bytes2,
+ prt_bytes3,
+ prt_bytes4,
+
+ prt_ack1,
+ prt_ack2,
+ prt_ack3,
+ prt_ack4,
+
+ prt_qos,
+ prt_req,
+ prt_data,
+ prt_addr,
+ prt_bytes,
+ prt_ack
+
+);
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+input rstn, sw_clk;
+input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
+input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
+input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
+input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
+input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
+output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
+output reg [max_burst_bits-1:0] prt_data;
+output reg [addr_width-1:0] prt_addr;
+output reg [max_burst_bytes_width:0] prt_bytes;
+output reg [axi_qos_width-1:0] prt_qos;
+parameter wait_req = 3\'b000, serv_req1 = 3\'b001, serv_req2 = 3\'b010, serv_req3 = 3\'b011, serv_req4 = 4\'b100,wait_ack_low = 3\'b101;
+reg [2:0] state;
+
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ state = wait_req;
+ prt_req = 1\'b0;
+ prt_ack1 = 1\'b0;
+ prt_ack2 = 1\'b0;
+ prt_ack3 = 1\'b0;
+ prt_ack4 = 1\'b0;
+ prt_qos = 0;
+end else begin
+ case(state)
+ wait_req:begin  
+         state = wait_req;
+         prt_ack1 = 1\'b0;
+         prt_ack2 = 1\'b0;
+         prt_ack3 = 1\'b0;
+         prt_ack4 = 1\'b0;
+         prt_req = 0;
+         if(prt_dv1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_dv2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_dv3) begin
+           state = serv_req3;
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_data = prt_data3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_dv4) begin
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_data = prt_data4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+           state = serv_req4;
+         end
+       end 
+ serv_req1:begin  
+         state = serv_req1;
+         prt_ack2 = 1\'b0;
+         prt_ack3 = 1\'b0;
+         prt_ack4 = 1\'b0;
+       if(prt_ack)begin 
+           prt_ack1 = 1\'b1;
+           //state = wait_req;
+           state = wait_ack_low;
+           prt_req = 0;
+         if(prt_dv2) begin
+           state = serv_req2;
+           prt_qos = qos2;
+           prt_req = 1;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_dv3) begin
+           state = serv_req3;
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_data = prt_data3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_dv4) begin
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_data = prt_data4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+           state = serv_req4;
+         end
+       end 
+       end
+ serv_req2:begin  
+         state = serv_req2;
+         prt_ack1 = 1\'b0;
+         prt_ack3 = 1\'b0;
+         prt_ack4 = 1\'b0;
+       if(prt_ack)begin 
+           prt_ack2 = 1\'b1;
+           //state = wait_req;
+           state = wait_ack_low;
+           prt_req = 0;
+         if(prt_dv3) begin
+           state = serv_req3;
+           prt_qos = qos3;
+           prt_req = 1;
+           prt_data = prt_data3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_dv4) begin
+           state = serv_req4;
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_data = prt_data4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+         end else if(prt_dv1) begin
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+           state = serv_req1;
+         end
+       end
+       end 
+ serv_req3:begin  
+         state = serv_req3;
+         prt_ack1 = 1\'b0;
+         prt_ack2 = 1\'b0;
+         prt_ack4 = 1\'b0;
+       if(prt_ack)begin 
+           prt_ack3 = 1\'b1;
+//           state = wait_req;
+           state = wait_ack_low;
+           prt_req = 0;
+         if(prt_dv4) begin
+           state = serv_req4;
+           prt_qos = qos4;
+           prt_req = 1;
+           prt_data = prt_data4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+         end else if(prt_dv1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_dv2) begin
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+           state = serv_req2;
+         end
+       end
+       end 
+ serv_req4:begin  
+         state = serv_req4;
+         prt_ack1 = 1\'b0;
+         prt_ack2 = 1\'b0;
+         prt_ack3 = 1\'b0;
+       if(prt_ack)begin 
+           prt_ack4 = 1\'b1;
+           //state = wait_req;
+           state = wait_ack_low;
+           prt_req = 0;
+         if(prt_dv1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_dv2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_dv3) begin
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_data = prt_data3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+           state = serv_req3;
+         end
+       end
+       end 
+ wait_ack_low:begin
+         state = wait_ack_low;
+         prt_ack1 = 1\'b0;
+         prt_ack2 = 1\'b0;
+         prt_ack3 = 1\'b0;
+         prt_ack4 = 1\'b0;
+         if(!prt_ack)
+           state = wait_req;
+       end  
+ endcase
+end /// if else
+end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_arb_rd_4.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between 4 read requests from 4 ports.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_arb_rd_4(
+ rstn,
+ sw_clk,
+
+ qos1,
+ qos2,
+ qos3,
+ qos4,
+
+ prt_req1,
+ prt_req2,
+ prt_req3,
+ prt_req4,
+
+ prt_data1,
+ prt_data2,
+ prt_data3,
+ prt_data4,
+
+ prt_addr1,
+ prt_addr2,
+ prt_addr3,
+ prt_addr4,
+
+ prt_bytes1,
+ prt_bytes2,
+ prt_bytes3,
+ prt_bytes4,
+
+ prt_dv1,
+ prt_dv2,
+ prt_dv3,
+ prt_dv4,
+
+ prt_qos,
+ prt_req,
+ prt_data,
+ prt_addr,
+ prt_bytes,
+ prt_dv
+
+);
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+input rstn, sw_clk;
+input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
+input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
+output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
+input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
+input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
+output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
+input [max_burst_bits-1:0] prt_data;
+output reg [addr_width-1:0] prt_addr;
+output reg [max_burst_bytes_width:0] prt_bytes;
+output reg [axi_qos_width-1:0] prt_qos;
+
+parameter wait_req = 3\'b000, serv_req1 = 3\'b001, serv_req2 = 3\'b010, serv_req3 = 3\'b011, serv_req4 = 3\'b100, wait_dv_low=3\'b101;
+reg [2:0] state;
+
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ state = wait_req;
+ prt_req = 1\'b0;
+ prt_dv1 = 1\'b0;
+ prt_dv2 = 1\'b0;
+ prt_dv3 = 1\'b0;
+ prt_dv4 = 1\'b0;
+ prt_qos =    0;
+end else begin
+ case(state)
+ wait_req:begin  
+         state = wait_req;
+         prt_dv1 = 1\'b0;
+         prt_dv2 = 1\'b0;
+         prt_dv3 = 1\'b0;
+         prt_dv4 = 1\'b0;
+         prt_req = 1\'b0;
+         if(prt_req1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_req2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_req3) begin
+           state = serv_req3;
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_req4) begin
+           prt_req = 1;
+           prt_addr = prt_addr4;
+           prt_qos = qos4;
+           prt_bytes = prt_bytes4;
+           state = serv_req4;
+         end
+       end 
+ serv_req1:begin  
+         state = serv_req1;
+         prt_dv2 = 1\'b0;
+         prt_dv3 = 1\'b0;
+         prt_dv4 = 1\'b0;
+       if(prt_dv)begin 
+           prt_dv1 = 1\'b1;
+           prt_data1 = prt_data;
+           //state = wait_req;
+           state = wait_dv_low;
+           prt_req = 1\'b0;
+         if(prt_req2) begin
+           state = serv_req2;
+           prt_qos = qos2;
+           prt_req = 1;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_req3) begin
+           state = serv_req3;
+           prt_qos = qos3;
+           prt_req = 1;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_req4) begin
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+           state = serv_req4;
+         end
+       end 
+       end
+ serv_req2:begin  
+         state = serv_req2;
+         prt_dv1 = 1\'b0;
+         prt_dv3 = 1\'b0;
+         prt_dv4 = 1\'b0;
+       if(prt_dv)begin 
+           prt_dv2 = 1\'b1;
+           prt_data2 = prt_data;
+           //state = wait_req;
+           state = wait_dv_low;
+           prt_req = 1\'b0;
+         if(prt_req3) begin
+           state = serv_req3;
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_req4) begin
+           state = serv_req4;
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+         end else if(prt_req1) begin
+           prt_req = 1;
+           prt_addr = prt_addr1;
+           prt_qos = qos1;
+           prt_bytes = prt_bytes1;
+           state = serv_req1;
+         end
+       end
+       end 
+ serv_req3:begin  
+         state = serv_req3;
+         prt_dv1 = 1\'b0;
+         prt_dv2 = 1\'b0;
+         prt_dv4 = 1\'b0;
+       if(prt_dv)begin 
+           prt_dv3 = 1\'b1;
+           prt_data3 = prt_data;
+           //state = wait_req;
+           state = wait_dv_low;
+           prt_req = 1\'b0;
+         if(prt_req4) begin
+           state = serv_req4;
+           prt_qos = qos4;
+           prt_req = 1;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+         end else if(prt_req1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_req2) begin
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+           state = serv_req2;
+         end
+       end
+       end 
+ serv_req4:begin  
+         state = serv_req4;
+         prt_dv1 = 1\'b0;
+         prt_dv2 = 1\'b0;
+         prt_dv3 = 1\'b0;
+       if(prt_dv)begin 
+           prt_dv4 = 1\'b1;
+           prt_data4 = prt_data;
+           //state = wait_req;
+           state = wait_dv_low;
+           prt_req = 1\'b0;
+         if(prt_req1) begin
+           state = serv_req1;
+           prt_qos = qos1;
+           prt_req = 1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_req2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_req3) begin
+           prt_req = 1;
+           prt_addr = prt_addr3;
+           prt_qos = qos3;
+           prt_bytes = prt_bytes3;
+           state = serv_req3;
+         end
+       end
+       end 
+ wait_dv_low:begin
+         state = wait_dv_low;
+         prt_dv1 = 1\'b0;
+         prt_dv2 = 1\'b0;
+         prt_dv3 = 1\'b0;
+         prt_dv4 = 1\'b0;
+         if(!prt_dv)
+           state = wait_req;
+       end  
+ endcase
+end /// if else
+end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_arb_hp2_3.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between RD/WR requests from 2 ports.
+ *               Used for modelling the Top_Interconnect switch.
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_arb_hp2_3(
+ sw_clk,
+ rstn,
+ w_qos_hp2,
+ r_qos_hp2,
+ w_qos_hp3,
+ r_qos_hp3,
+
+ wr_ack_ddr_hp2,
+ wr_data_hp2,
+ wr_addr_hp2,
+ wr_bytes_hp2,
+ wr_dv_ddr_hp2,
+ rd_req_ddr_hp2,
+ rd_addr_hp2,
+ rd_bytes_hp2,
+ rd_data_ddr_hp2,
+ rd_dv_ddr_hp2,
+
+ wr_ack_ddr_hp3,
+ wr_data_hp3,
+ wr_addr_hp3,
+ wr_bytes_hp3,
+ wr_dv_ddr_hp3,
+ rd_req_ddr_hp3,
+ rd_addr_hp3,
+ rd_bytes_hp3,
+ rd_data_ddr_hp3,
+ rd_dv_ddr_hp3,
+
+ ddr_wr_ack,
+ ddr_wr_dv,
+ ddr_rd_req,
+ ddr_rd_dv,
+ ddr_rd_qos,
+ ddr_wr_qos,
+ 
+ ddr_wr_addr,
+ ddr_wr_data,
+ ddr_wr_bytes,
+ ddr_rd_addr,
+ ddr_rd_data,
+ ddr_rd_bytes
+
+);
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+input sw_clk;
+input rstn;
+input [axi_qos_width-1:0] w_qos_hp2;
+input [axi_qos_width-1:0] r_qos_hp2;
+input [axi_qos_width-1:0] w_qos_hp3;
+input [axi_qos_width-1:0] r_qos_hp3;
+input [axi_qos_width-1:0] ddr_rd_qos;
+input [axi_qos_width-1:0] ddr_wr_qos;
+
+output wr_ack_ddr_hp2;
+input [max_burst_bits-1:0] wr_data_hp2;
+input [addr_width-1:0] wr_addr_hp2;
+input [max_burst_bytes_width:0] wr_bytes_hp2;
+output wr_dv_ddr_hp2;
+
+input rd_req_ddr_hp2;
+input [addr_width-1:0] rd_addr_hp2;
+input [max_burst_bytes_width:0] rd_bytes_hp2;
+output [max_burst_bits-1:0] rd_data_ddr_hp2;
+output rd_dv_ddr_hp2;
+ 
+output wr_ack_ddr_hp3;
+input [max_burst_bits-1:0] wr_data_hp3;
+input [addr_width-1:0] wr_addr_hp3;
+input [max_burst_bytes_width:0] wr_bytes_hp3;
+output wr_dv_ddr_hp3;
+
+input rd_req_ddr_hp3;
+input [addr_width-1:0] rd_addr_hp3;
+input [max_burst_bytes_width:0] rd_bytes_hp3;
+output [max_burst_bits-1:0] rd_data_ddr_hp3;
+output rd_dv_ddr_hp3;
+ 
+input ddr_wr_ack;
+output ddr_wr_dv;
+output [addr_width-1:0]ddr_wr_addr;
+output [max_burst_bits-1:0]ddr_wr_data;
+output [max_burst_bytes_width:0]ddr_wr_bytes;
+
+input ddr_rd_dv;
+input [max_burst_bits-1:0] ddr_rd_data;
+output ddr_rd_req;
+output [addr_width-1:0] ddr_rd_addr;
+output [max_burst_bytes_width:0] ddr_rd_bytes;
+
+
+
+
+processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(w_qos_hp2),
+ .qos2(w_qos_hp3),
+ .prt_dv1(wr_dv_ddr_hp2),
+ .prt_dv2(wr_dv_ddr_hp3),
+ .prt_data1(wr_data_hp2),
+ .prt_data2(wr_data_hp3),
+ .prt_addr1(wr_addr_hp2),
+ .prt_addr2(wr_addr_hp3),
+ .prt_bytes1(wr_bytes_hp2),
+ .prt_bytes2(wr_bytes_hp3),
+ .prt_ack1(wr_ack_ddr_hp2),
+ .prt_ack2(wr_ack_ddr_hp3),
+ .prt_req(ddr_wr_dv),
+ .prt_qos(ddr_wr_qos),
+ .prt_data(ddr_wr_data),
+ .prt_addr(ddr_wr_addr),
+ .prt_bytes(ddr_wr_bytes),
+ .prt_ack(ddr_wr_ack)
+);
+
+processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_hp2),
+ .qos2(r_qos_hp3),
+ .prt_req1(rd_req_ddr_hp2),
+ .prt_req2(rd_req_ddr_hp3),
+ .prt_data1(rd_data_ddr_hp2),
+ .prt_data2(rd_data_ddr_hp3),
+ .prt_addr1(rd_addr_hp2),
+ .prt_addr2(rd_addr_hp3),
+ .prt_bytes1(rd_bytes_hp2),
+ .prt_bytes2(rd_bytes_hp3),
+ .prt_dv1(rd_dv_ddr_hp2),
+ .prt_dv2(rd_dv_ddr_hp3),
+ .prt_req(ddr_rd_req),
+ .prt_qos(ddr_rd_qos),
+ .prt_data(ddr_rd_data),
+ .prt_addr(ddr_rd_addr),
+ .prt_bytes(ddr_rd_bytes),
+ .prt_dv(ddr_rd_dv)
+);
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_arb_hp0_1.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between RD/WR requests from 2 ports.
+ *               Used for modelling the Top_Interconnect switch.
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_arb_hp0_1(
+ sw_clk,
+ rstn,
+ w_qos_hp0,
+ r_qos_hp0,
+ w_qos_hp1,
+ r_qos_hp1,
+
+ wr_ack_ddr_hp0,
+ wr_data_hp0,
+ wr_addr_hp0,
+ wr_bytes_hp0,
+ wr_dv_ddr_hp0,
+ rd_req_ddr_hp0,
+ rd_addr_hp0,
+ rd_bytes_hp0,
+ rd_data_ddr_hp0,
+ rd_dv_ddr_hp0,
+
+ wr_ack_ddr_hp1,
+ wr_data_hp1,
+ wr_addr_hp1,
+ wr_bytes_hp1,
+ wr_dv_ddr_hp1,
+ rd_req_ddr_hp1,
+ rd_addr_hp1,
+ rd_bytes_hp1,
+ rd_data_ddr_hp1,
+ rd_dv_ddr_hp1,
+
+ ddr_wr_ack,
+ ddr_wr_dv,
+ ddr_rd_req,
+ ddr_rd_dv,
+ ddr_rd_qos,
+ ddr_wr_qos,
+ 
+ ddr_wr_addr,
+ ddr_wr_data,
+ ddr_wr_bytes,
+ ddr_rd_addr,
+ ddr_rd_data,
+ ddr_rd_bytes
+
+);
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+input sw_clk;
+input rstn;
+input [axi_qos_width-1:0] w_qos_hp0;
+input [axi_qos_width-1:0] r_qos_hp0;
+input [axi_qos_width-1:0] w_qos_hp1;
+input [axi_qos_width-1:0] r_qos_hp1;
+input [axi_qos_width-1:0] ddr_rd_qos;
+input [axi_qos_width-1:0] ddr_wr_qos;
+
+output wr_ack_ddr_hp0;
+input [max_burst_bits-1:0] wr_data_hp0;
+input [addr_width-1:0] wr_addr_hp0;
+input [max_burst_bytes_width:0] wr_bytes_hp0;
+output wr_dv_ddr_hp0;
+
+input rd_req_ddr_hp0;
+input [addr_width-1:0] rd_addr_hp0;
+input [max_burst_bytes_width:0] rd_bytes_hp0;
+output [max_burst_bits-1:0] rd_data_ddr_hp0;
+output rd_dv_ddr_hp0;
+ 
+output wr_ack_ddr_hp1;
+input [max_burst_bits-1:0] wr_data_hp1;
+input [addr_width-1:0] wr_addr_hp1;
+input [max_burst_bytes_width:0] wr_bytes_hp1;
+output wr_dv_ddr_hp1;
+
+input rd_req_ddr_hp1;
+input [addr_width-1:0] rd_addr_hp1;
+input [max_burst_bytes_width:0] rd_bytes_hp1;
+output [max_burst_bits-1:0] rd_data_ddr_hp1;
+output rd_dv_ddr_hp1;
+ 
+input ddr_wr_ack;
+output ddr_wr_dv;
+output [addr_width-1:0]ddr_wr_addr;
+output [max_burst_bits-1:0]ddr_wr_data;
+output [max_burst_bytes_width:0]ddr_wr_bytes;
+
+input ddr_rd_dv;
+input [max_burst_bits-1:0] ddr_rd_data;
+output ddr_rd_req;
+output [addr_width-1:0] ddr_rd_addr;
+output [max_burst_bytes_width:0] ddr_rd_bytes;
+
+
+
+
+processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(w_qos_hp0),
+ .qos2(w_qos_hp1),
+ .prt_dv1(wr_dv_ddr_hp0),
+ .prt_dv2(wr_dv_ddr_hp1),
+ .prt_data1(wr_data_hp0),
+ .prt_data2(wr_data_hp1),
+ .prt_addr1(wr_addr_hp0),
+ .prt_addr2(wr_addr_hp1),
+ .prt_bytes1(wr_bytes_hp0),
+ .prt_bytes2(wr_bytes_hp1),
+ .prt_ack1(wr_ack_ddr_hp0),
+ .prt_ack2(wr_ack_ddr_hp1),
+ .prt_req(ddr_wr_dv),
+ .prt_qos(ddr_wr_qos),
+ .prt_data(ddr_wr_data),
+ .prt_addr(ddr_wr_addr),
+ .prt_bytes(ddr_wr_bytes),
+ .prt_ack(ddr_wr_ack)
+);
+
+processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_hp0),
+ .qos2(r_qos_hp1),
+ .prt_req1(rd_req_ddr_hp0),
+ .prt_req2(rd_req_ddr_hp1),
+ .prt_data1(rd_data_ddr_hp0),
+ .prt_data2(rd_data_ddr_hp1),
+ .prt_addr1(rd_addr_hp0),
+ .prt_addr2(rd_addr_hp1),
+ .prt_bytes1(rd_bytes_hp0),
+ .prt_bytes2(rd_bytes_hp1),
+ .prt_dv1(rd_dv_ddr_hp0),
+ .prt_dv2(rd_dv_ddr_hp1),
+ .prt_qos(ddr_rd_qos),
+ .prt_req(ddr_rd_req),
+ .prt_data(ddr_rd_data),
+ .prt_addr(ddr_rd_addr),
+ .prt_bytes(ddr_rd_bytes),
+ .prt_dv(ddr_rd_dv)
+);
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_ssw_hp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : SSW switch Model
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_ssw_hp(
+ sw_clk,
+ rstn,
+ w_qos_hp0,
+ r_qos_hp0,
+ w_qos_hp1,
+ r_qos_hp1,
+ w_qos_hp2,
+ r_qos_hp2,
+ w_qos_hp3,
+ r_qos_hp3,
+
+ wr_ack_ddr_hp0,
+ wr_data_hp0,
+ wr_addr_hp0,
+ wr_bytes_hp0,
+ wr_dv_ddr_hp0,
+ rd_req_ddr_hp0,
+ rd_addr_hp0,
+ rd_bytes_hp0,
+ rd_data_ddr_hp0,
+ rd_dv_ddr_hp0,
+
+ rd_data_ocm_hp0,
+ wr_ack_ocm_hp0,
+ wr_dv_ocm_hp0,
+ rd_req_ocm_hp0,
+ rd_dv_ocm_hp0,
+
+ wr_ack_ddr_hp1,
+ wr_data_hp1,
+ wr_addr_hp1,
+ wr_bytes_hp1,
+ wr_dv_ddr_hp1,
+ rd_req_ddr_hp1,
+ rd_addr_hp1,
+ rd_bytes_hp1,
+ rd_data_ddr_hp1,
+ rd_data_ocm_hp1,
+ rd_dv_ddr_hp1,
+
+ wr_ack_ocm_hp1,
+ wr_dv_ocm_hp1,
+ rd_req_ocm_hp1,
+ rd_dv_ocm_hp1,
+
+ wr_ack_ddr_hp2,
+ wr_data_hp2,
+ wr_addr_hp2,
+ wr_bytes_hp2,
+ wr_dv_ddr_hp2,
+ rd_req_ddr_hp2,
+ rd_addr_hp2,
+ rd_bytes_hp2,
+ rd_data_ddr_hp2,
+ rd_data_ocm_hp2,
+ rd_dv_ddr_hp2,
+
+ wr_ack_ocm_hp2,
+ wr_dv_ocm_hp2,
+ rd_req_ocm_hp2,
+ rd_dv_ocm_hp2,
+
+ wr_ack_ddr_hp3,
+ wr_data_hp3,
+ wr_addr_hp3,
+ wr_bytes_hp3,
+ wr_dv_ddr_hp3,
+ rd_req_ddr_hp3,
+ rd_addr_hp3,
+ rd_bytes_hp3,
+ rd_data_ocm_hp3,
+ rd_data_ddr_hp3,
+ rd_dv_ddr_hp3,
+
+ wr_ack_ocm_hp3,
+ wr_dv_ocm_hp3,
+ rd_req_ocm_hp3,
+ rd_dv_ocm_hp3,
+
+ ddr_wr_ack0,
+ ddr_wr_dv0,
+ ddr_rd_req0,
+ ddr_rd_dv0,
+ ddr_rd_qos0,
+ ddr_wr_qos0,
+
+ ddr_wr_addr0,
+ ddr_wr_data0,
+ ddr_wr_bytes0,
+ ddr_rd_addr0,
+ ddr_rd_data0,
+ ddr_rd_bytes0,
+
+ ddr_wr_ack1,
+ ddr_wr_dv1,
+ ddr_rd_req1,
+ ddr_rd_dv1,
+ ddr_rd_qos1,
+ ddr_wr_qos1,
+ ddr_wr_addr1,
+ ddr_wr_data1,
+ ddr_wr_bytes1,
+ ddr_rd_addr1,
+ ddr_rd_data1,
+ ddr_rd_bytes1,
+
+ ocm_wr_ack,
+ ocm_wr_dv,
+ ocm_rd_req,
+ ocm_rd_dv,
+
+ ocm_wr_qos,
+ ocm_rd_qos, 
+ ocm_wr_addr,
+ ocm_wr_data,
+ ocm_wr_bytes,
+ ocm_rd_addr,
+ ocm_rd_data,
+ ocm_rd_bytes
+ 
+
+
+);
+
+input sw_clk;
+input rstn;
+input [3:0] w_qos_hp0;
+input [3:0] r_qos_hp0;
+input [3:0] w_qos_hp1;
+input [3:0] r_qos_hp1;
+input [3:0] w_qos_hp2;
+input [3:0] r_qos_hp2;
+input [3:0] w_qos_hp3;
+input [3:0] r_qos_hp3;
+
+output [3:0] ddr_rd_qos0;
+output [3:0] ddr_wr_qos0;
+output [3:0] ddr_rd_qos1;
+output [3:0] ddr_wr_qos1;
+output [3:0] ocm_wr_qos;
+output [3:0] ocm_rd_qos; 
+
+output wr_ack_ddr_hp0;
+input [1023:0] wr_data_hp0;
+input [31:0] wr_addr_hp0;
+input [7:0] wr_bytes_hp0;
+output wr_dv_ddr_hp0;
+
+input rd_req_ddr_hp0;
+input [31:0] rd_addr_hp0;
+input [7:0] rd_bytes_hp0;
+output [1023:0] rd_data_ddr_hp0;
+output rd_dv_ddr_hp0;
+ 
+output wr_ack_ddr_hp1;
+input [1023:0] wr_data_hp1;
+input [31:0] wr_addr_hp1;
+input [7:0] wr_bytes_hp1;
+output wr_dv_ddr_hp1;
+
+input rd_req_ddr_hp1;
+input [31:0] rd_addr_hp1;
+input [7:0] rd_bytes_hp1;
+output [1023:0] rd_data_ddr_hp1;
+output rd_dv_ddr_hp1;
+
+output wr_ack_ddr_hp2;
+input [1023:0] wr_data_hp2;
+input [31:0] wr_addr_hp2;
+input [7:0] wr_bytes_hp2;
+output wr_dv_ddr_hp2;
+
+input rd_req_ddr_hp2;
+input [31:0] rd_addr_hp2;
+input [7:0] rd_bytes_hp2;
+output [1023:0] rd_data_ddr_hp2;
+output rd_dv_ddr_hp2;
+ 
+output wr_ack_ddr_hp3;
+input [1023:0] wr_data_hp3;
+input [31:0] wr_addr_hp3;
+input [7:0] wr_bytes_hp3;
+output wr_dv_ddr_hp3;
+
+input rd_req_ddr_hp3;
+input [31:0] rd_addr_hp3;
+input [7:0] rd_bytes_hp3;
+output [1023:0] rd_data_ddr_hp3;
+output rd_dv_ddr_hp3;
+
+input ddr_wr_ack0;
+output ddr_wr_dv0;
+output [31:0]ddr_wr_addr0;
+output [1023:0]ddr_wr_data0;
+output [7:0]ddr_wr_bytes0;
+
+input ddr_rd_dv0;
+input [1023:0] ddr_rd_data0;
+output ddr_rd_req0;
+output [31:0] ddr_rd_addr0;
+output [7:0] ddr_rd_bytes0;
+
+input ddr_wr_ack1;
+output ddr_wr_dv1;
+output [31:0]ddr_wr_addr1;
+output [1023:0]ddr_wr_data1;
+output [7:0]ddr_wr_bytes1;
+
+input ddr_rd_dv1;
+input [1023:0] ddr_rd_data1;
+output ddr_rd_req1;
+output [31:0] ddr_rd_addr1;
+output [7:0] ddr_rd_bytes1;
+
+output wr_ack_ocm_hp0;
+input wr_dv_ocm_hp0;
+input rd_req_ocm_hp0;
+output rd_dv_ocm_hp0;
+output [1023:0] rd_data_ocm_hp0;
+
+output wr_ack_ocm_hp1;
+input wr_dv_ocm_hp1;
+input rd_req_ocm_hp1;
+output rd_dv_ocm_hp1;
+output [1023:0] rd_data_ocm_hp1;
+
+output wr_ack_ocm_hp2;
+input wr_dv_ocm_hp2;
+input rd_req_ocm_hp2;
+output rd_dv_ocm_hp2;
+output [1023:0] rd_data_ocm_hp2;
+
+output wr_ack_ocm_hp3;
+input wr_dv_ocm_hp3;
+input rd_req_ocm_hp3;
+output rd_dv_ocm_hp3;
+output [1023:0] rd_data_ocm_hp3;
+
+input ocm_wr_ack;
+output ocm_wr_dv;
+output [31:0]ocm_wr_addr;
+output [1023:0]ocm_wr_data;
+output [7:0]ocm_wr_bytes;
+
+input ocm_rd_dv;
+input [1023:0] ocm_rd_data;
+output ocm_rd_req;
+output [31:0] ocm_rd_addr;
+output [7:0] ocm_rd_bytes;
+
+/* FOR DDR */
+processing_system7_bfm_v2_0_5_arb_hp0_1 ddr_hp01 (
+ .sw_clk(sw_clk),
+ .rstn(rstn),
+ .w_qos_hp0(w_qos_hp0),
+ .r_qos_hp0(r_qos_hp0),
+ .w_qos_hp1(w_qos_hp1),
+ .r_qos_hp1(r_qos_hp1),
+   
+ .wr_ack_ddr_hp0(wr_ack_ddr_hp0),
+ .wr_data_hp0(wr_data_hp0),
+ .wr_addr_hp0(wr_addr_hp0),
+ .wr_bytes_hp0(wr_bytes_hp0),
+ .wr_dv_ddr_hp0(wr_dv_ddr_hp0),
+ .rd_req_ddr_hp0(rd_req_ddr_hp0),
+ .rd_addr_hp0(rd_addr_hp0),
+ .rd_bytes_hp0(rd_bytes_hp0),
+ .rd_data_ddr_hp0(rd_data_ddr_hp0),
+ .rd_dv_ddr_hp0(rd_dv_ddr_hp0),
+   
+ .wr_ack_ddr_hp1(wr_ack_ddr_hp1),
+ .wr_data_hp1(wr_data_hp1),
+ .wr_addr_hp1(wr_addr_hp1),
+ .wr_bytes_hp1(wr_bytes_hp1),
+ .wr_dv_ddr_hp1(wr_dv_ddr_hp1),
+ .rd_req_ddr_hp1(rd_req_ddr_hp1),
+ .rd_addr_hp1(rd_addr_hp1),
+ .rd_bytes_hp1(rd_bytes_hp1),
+ .rd_data_ddr_hp1(rd_data_ddr_hp1),
+ .rd_dv_ddr_hp1(rd_dv_ddr_hp1),
+   
+ .ddr_wr_ack(ddr_wr_ack0),
+ .ddr_wr_dv(ddr_wr_dv0),
+ .ddr_rd_req(ddr_rd_req0),
+ .ddr_rd_dv(ddr_rd_dv0),
+ .ddr_rd_qos(ddr_rd_qos0),
+ .ddr_wr_qos(ddr_wr_qos0), 
+ .ddr_wr_addr(ddr_wr_addr0),
+ .ddr_wr_data(ddr_wr_data0),
+ .ddr_wr_bytes(ddr_wr_bytes0),
+ .ddr_rd_addr(ddr_rd_addr0),
+ .ddr_rd_data(ddr_rd_data0),
+ .ddr_rd_bytes(ddr_rd_bytes0)
+);
+
+/* FOR DDR */
+processing_system7_bfm_v2_0_5_arb_hp2_3 ddr_hp23 (
+ .sw_clk(sw_clk),
+ .rstn(rstn),
+ .w_qos_hp2(w_qos_hp2),
+ .r_qos_hp2(r_qos_hp2),
+ .w_qos_hp3(w_qos_hp3),
+ .r_qos_hp3(r_qos_hp3),
+   
+ .wr_ack_ddr_hp2(wr_ack_ddr_hp2),
+ .wr_data_hp2(wr_data_hp2),
+ .wr_addr_hp2(wr_addr_hp2),
+ .wr_bytes_hp2(wr_bytes_hp2),
+ .wr_dv_ddr_hp2(wr_dv_ddr_hp2),
+ .rd_req_ddr_hp2(rd_req_ddr_hp2),
+ .rd_addr_hp2(rd_addr_hp2),
+ .rd_bytes_hp2(rd_bytes_hp2),
+ .rd_data_ddr_hp2(rd_data_ddr_hp2),
+ .rd_dv_ddr_hp2(rd_dv_ddr_hp2),
+   
+ .wr_ack_ddr_hp3(wr_ack_ddr_hp3),
+ .wr_data_hp3(wr_data_hp3),
+ .wr_addr_hp3(wr_addr_hp3),
+ .wr_bytes_hp3(wr_bytes_hp3),
+ .wr_dv_ddr_hp3(wr_dv_ddr_hp3),
+ .rd_req_ddr_hp3(rd_req_ddr_hp3),
+ .rd_addr_hp3(rd_addr_hp3),
+ .rd_bytes_hp3(rd_bytes_hp3),
+ .rd_data_ddr_hp3(rd_data_ddr_hp3),
+ .rd_dv_ddr_hp3(rd_dv_ddr_hp3),
+   
+ .ddr_wr_ack(ddr_wr_ack1),
+ .ddr_wr_dv(ddr_wr_dv1),
+ .ddr_rd_req(ddr_rd_req1),
+ .ddr_rd_dv(ddr_rd_dv1),
+ .ddr_rd_qos(ddr_rd_qos1),
+ .ddr_wr_qos(ddr_wr_qos1), 
+
+ .ddr_wr_addr(ddr_wr_addr1),
+ .ddr_wr_data(ddr_wr_data1),
+ .ddr_wr_bytes(ddr_wr_bytes1),
+ .ddr_rd_addr(ddr_rd_addr1),
+ .ddr_rd_data(ddr_rd_data1),
+ .ddr_rd_bytes(ddr_rd_bytes1)
+);
+
+
+/* FOR OCM_WR */
+processing_system7_bfm_v2_0_5_arb_wr_4 ocm_wr_hp(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(w_qos_hp0),
+ .qos2(w_qos_hp1),
+ .qos3(w_qos_hp2),
+ .qos4(w_qos_hp3),
+   
+ .prt_dv1(wr_dv_ocm_hp0),
+ .prt_dv2(wr_dv_ocm_hp1),
+ .prt_dv3(wr_dv_ocm_hp2),
+ .prt_dv4(wr_dv_ocm_hp3),
+   
+ .prt_data1(wr_data_hp0),
+ .prt_data2(wr_data_hp1),
+ .prt_data3(wr_data_hp2),
+ .prt_data4(wr_data_hp3),
+   
+ .prt_addr1(wr_addr_hp0),
+ .prt_addr2(wr_addr_hp1),
+ .prt_addr3(wr_addr_hp2),
+ .prt_addr4(wr_addr_hp3),
+   
+ .prt_bytes1(wr_bytes_hp0),
+ .prt_bytes2(wr_bytes_hp1),
+ .prt_bytes3(wr_bytes_hp2),
+ .prt_bytes4(wr_bytes_hp3),
+   
+ .prt_ack1(wr_ack_ocm_hp0),
+ .prt_ack2(wr_ack_ocm_hp1),
+ .prt_ack3(wr_ack_ocm_hp2),
+ .prt_ack4(wr_ack_ocm_hp3),
+   
+ .prt_qos(ocm_wr_qos),
+ .prt_req(ocm_wr_dv),
+ .prt_data(ocm_wr_data),
+ .prt_addr(ocm_wr_addr),
+ .prt_bytes(ocm_wr_bytes),
+ .prt_ack(ocm_wr_ack)
+
+);
+
+/* FOR OCM_RD */
+processing_system7_bfm_v2_0_5_arb_rd_4 ocm_rd_hp(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(r_qos_hp0),
+ .qos2(r_qos_hp1),
+ .qos3(r_qos_hp2),
+ .qos4(r_qos_hp3),
+   
+ .prt_req1(rd_req_ocm_hp0),
+ .prt_req2(rd_req_ocm_hp1),
+ .prt_req3(rd_req_ocm_hp2),
+ .prt_req4(rd_req_ocm_hp3),
+   
+ .prt_data1(rd_data_ocm_hp0),
+ .prt_data2(rd_data_ocm_hp1),
+ .prt_data3(rd_data_ocm_hp2),
+ .prt_data4(rd_data_ocm_hp3),
+   
+ .prt_addr1(rd_addr_hp0),
+ .prt_addr2(rd_addr_hp1),
+ .prt_addr3(rd_addr_hp2),
+ .prt_addr4(rd_addr_hp3),
+   
+ .prt_bytes1(rd_bytes_hp0),
+ .prt_bytes2(rd_bytes_hp1),
+ .prt_bytes3(rd_bytes_hp2),
+ .prt_bytes4(rd_bytes_hp3),
+   
+ .prt_dv1(rd_dv_ocm_hp0),
+ .prt_dv2(rd_dv_ocm_hp1),
+ .prt_dv3(rd_dv_ocm_hp2),
+ .prt_dv4(rd_dv_ocm_hp3),
+   
+ .prt_qos(ocm_rd_qos),
+ .prt_req(ocm_rd_req),
+ .prt_data(ocm_rd_data),
+ .prt_addr(ocm_rd_addr),
+ .prt_bytes(ocm_rd_bytes),
+ .prt_dv(ocm_rd_dv)
+
+);
+
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_sparse_mem.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Sparse Memory Model
+ *
+ *****************************************************************************/
+
+/*** WA for CR # 695818 ***/
+`ifdef XILINX_SIMULATOR
+   `define XSIM_ISIM
+`endif
+`ifdef XILINX_ISIM
+   `define XSIM_ISIM
+`endif
+
+ `timescale 1ns/1ps
+module processing_system7_bfm_v2_0_5_sparse_mem();
+
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+parameter mem_size = 32\'h4000_0000; /// 1GB mem size
+parameter xsim_mem_size = 32\'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM)
+
+
+`ifdef XSIM_ISIM
+ reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+`else
+ reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // \'h10_0000 to \'h3FFF_FFFF - 1G mem
+`endif
+
+event mem_updated;
+reg check_we;
+reg [addr_width-1:0] check_up_add;
+reg [data_width-1:0] updated_data;
+
+/* preload memory from file */
+task automatic pre_load_mem_from_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+`ifdef XSIM_ISIM
+  case(start_addr[31:28])
+    4\'d0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits);
+    4\'d1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits);
+    4\'d2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits);
+    4\'d3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits);
+  endcase
+`else
+  $readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits);
+`endif
+endtask
+
+/* preload memory with some random data */
+task automatic pre_load_mem;
+input [1:0]  data_type;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+integer i;
+reg [addr_width-1:0] addr;
+begin
+addr = start_addr >> shft_addr_bits;
+for (i = 0; i < no_of_bytes; i = i + mem_width) begin
+   case(data_type)
+     ALL_RANDOM : set_data(addr , $random);
+     ALL_ZEROS  : set_data(addr , 32\'h0000_0000);
+     ALL_ONES   : set_data(addr , 32\'hFFFF_FFFF);
+     default    : set_data(addr , $random);
+   endcase
+   addr = addr+1;
+end 
+end
+endtask
+
+/* wait for memory update at certain location */
+task automatic wait_mem_update;
+input[addr_width-1:0] address;
+output[data_width-1:0] dataout;
+begin
+  check_up_add = address >> shft_addr_bits;
+  check_we = 1;
+  @(mem_updated); 
+  dataout = updated_data;
+  check_we = 0;
+end
+endtask
+
+/* internal task to write data in memory */
+task automatic set_data;
+input [addr_width-1:0] addr;
+input [data_width-1:0] data;
+begin
+if(check_we && (addr === check_up_add)) begin
+ updated_data = data;
+ -> mem_updated;
+end
+`ifdef XSIM_ISIM
+  case(addr[31:26])
+    6\'d0 : ddr_mem0[addr[25:0]] = data;
+    6\'d1 : ddr_mem1[addr[25:0]] = data;
+    6\'d2 : ddr_mem2[addr[25:0]] = data;
+    6\'d3 : ddr_mem3[addr[25:0]] = data;
+  endcase
+`else
+  ddr_mem[addr] = data;
+`endif
+end
+endtask
+
+/* internal task to read data from memory */
+task automatic get_data;
+input [addr_width-1:0] addr;
+output [data_width-1:0] data;
+begin
+`ifdef XSIM_ISIM
+  case(addr[31:26])
+    6\'d0 : data = ddr_mem0[addr[25:0]];
+    6\'d1 : data = ddr_mem1[addr[25:0]];
+    6\'d2 : data = ddr_mem2[addr[25:0]];
+    6\'d3 : data = ddr_mem3[addr[25:0]];
+  endcase
+`else
+  data = ddr_mem[addr];
+`endif
+end
+endtask
+
+/* Write memory */
+task write_mem;
+input [max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width:0] no_of_bytes;
+reg [addr_width-1:0] addr;
+reg [max_burst_bits-1 :0] wr_temp_data;
+reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
+integer bytes_left;
+integer pre_pad_bytes;
+integer post_pad_bytes;
+begin
+addr = start_addr >> shft_addr_bits;
+wr_temp_data = data;
+
+`ifdef XLNX_INT_DBG
+   $display(""[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\
+ Data (0x%0h)"",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); 
+`endif
+
+temp_data = wr_temp_data[data_width-1:0];
+bytes_left = no_of_bytes;
+/* when the no. of bytes to be updated is less than mem_width */
+if(bytes_left < mem_width) begin
+ /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
+ if(start_addr[shft_addr_bits-1:0] > 0) begin
+   //temp_data     = ddr_mem[addr];
+   get_data(addr,temp_data);
+   pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
+   repeat(pre_pad_bytes) temp_data = temp_data << 8;
+   repeat(pre_pad_bytes) begin
+     temp_data = temp_data >> 8;
+     temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
+     wr_temp_data = wr_temp_data >> 8;
+   end
+   bytes_left = bytes_left + pre_pad_bytes;
+ end
+ /* This is needed for post padding the data ...*/
+ post_pad_bytes = mem_width - bytes_left;
+ //post_pad_data  = ddr_mem[addr];
+ get_data(addr,post_pad_data);
+ repeat(post_pad_bytes) temp_data = temp_data << 8;
+ repeat(bytes_left) post_pad_data = post_pad_data >> 8;
+ repeat(post_pad_bytes) begin
+   temp_data = temp_data >> 8;
+   temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
+   post_pad_data = post_pad_data >> 8; 
+ end
+ //ddr_mem[addr] = temp_data;
+ set_data(addr,temp_data);
+end else begin
+ /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
+ if(start_addr[shft_addr_bits-1:0] > 0) begin
+  //temp_data     = ddr_mem[addr];
+  get_data(addr,temp_data);
+  pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
+  repeat(pre_pad_bytes) temp_data = temp_data << 8;
+  repeat(pre_pad_bytes) begin
+    temp_data = temp_data >> 8;
+    temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
+    wr_temp_data = wr_temp_data >> 8;
+    bytes_left = bytes_left -1;  
+  end
+ end else begin
+  wr_temp_data = wr_temp_data >> data_width;  
+  bytes_left = bytes_left - mem_width;
+ end
+ /* first data word end */
+ //ddr_mem[addr] = temp_data;
+ set_data(addr,temp_data);
+ addr = addr + 1;
+ while(bytes_left > (mem_width-1) ) begin  /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
+  //ddr_mem[addr] = wr_temp_data[data_width-1:0];
+  set_data(addr,wr_temp_data[data_width-1:0]);
+  addr = addr+1;
+  wr_temp_data = wr_temp_data >> data_width;
+  bytes_left = bytes_left - mem_width;
+ end
+ 
+ //post_pad_data   = ddr_mem[addr];
+ get_data(addr,post_pad_data);
+ post_pad_bytes  = mem_width - bytes_left;
+ /* This is needed for last transfer in unaliged burst */
+ if(bytes_left > 0) begin
+   temp_data = wr_temp_data[data_width-1:0];
+   repeat(post_pad_bytes) temp_data = temp_data << 8;
+   repeat(bytes_left) post_pad_data = post_pad_data >> 8;
+   repeat(post_pad_bytes) begin
+     temp_data = temp_data >> 8;
+     temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
+     post_pad_data = post_pad_data >> 8; 
+   end
+   //ddr_mem[addr] = temp_data;
+   set_data(addr,temp_data);
+ end
+end
+`ifdef XLNX_INT_DBG $display(""[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)"",$time, DISP_INT_INFO, start_addr ); 
+`endif
+end
+endtask
+
+/* read_memory */
+task read_mem;
+output[max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width :0] no_of_bytes;
+integer i;
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] temp_rd_data;
+reg [max_burst_bits-1:0] temp_data;
+integer pre_bytes;
+integer bytes_left;
+begin
+addr = start_addr >> shft_addr_bits;
+pre_bytes  = start_addr[shft_addr_bits-1:0];
+bytes_left = no_of_bytes;
+
+`ifdef XLNX_INT_DBG
+   $display(""[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes"",$time, DISP_INT_INFO, start_addr,no_of_bytes ); 
+`endif 
+
+/* Get first data ... if unaligned address */
+//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
+get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
+
+if(no_of_bytes < mem_width ) begin
+  temp_data = temp_data >> (pre_bytes * 8);
+  repeat(max_burst_bytes - mem_width)
+   temp_data = temp_data >> 8;
+
+end else begin
+  bytes_left = bytes_left - (mem_width - pre_bytes);
+  addr  = addr+1;
+  /* Got first data */
+  while (bytes_left > (mem_width-1) ) begin
+   temp_data = temp_data >> data_width;
+   //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
+   get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
+   addr = addr+1;
+   bytes_left = bytes_left - mem_width;
+  end 
+
+  /* Get last valid data in the burst*/
+  //temp_rd_data = ddr_mem[addr];
+  get_data(addr,temp_rd_data);
+  while(bytes_left > 0) begin
+    temp_data = temp_data >> 8;
+    temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
+    temp_rd_data = temp_rd_data >> 8;
+    bytes_left = bytes_left - 1;
+  end
+  /* align to the brst_byte length */
+  repeat(max_burst_bytes - no_of_bytes)
+    temp_data = temp_data >> 8;
+end 
+data = temp_data;
+`ifdef XLNX_INT_DBG
+   $display(""[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)"",$time, DISP_INT_INFO, start_addr, data ); 
+`endif 
+end
+endtask
+
+/* backdoor read to memory */
+task peek_mem_to_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+
+integer rd_fd;
+integer bytes;
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] rd_data;
+begin
+rd_fd = $fopen(file_name,""w"");
+bytes = no_of_bytes;
+
+addr = start_addr >> shft_addr_bits;
+while (bytes > 0) begin
+  get_data(addr,rd_data);
+  $fdisplayh(rd_fd,rd_data);
+  bytes = bytes - 4;
+  addr = addr + 1;
+end
+end
+endtask
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_reg_map.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Controller for Register Map Memory
+ *
+ *****************************************************************************/
+/*** WA for CR # 695818 ***/
+`ifdef XILINX_SIMULATOR
+   `define XSIM_ISIM
+`endif
+`ifdef XILINX_ISIM
+   `define XSIM_ISIM
+`endif
+
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_reg_map();
+
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+/* Register definitions */
+`include ""processing_system7_bfm_v2_0_5_reg_params.v""
+
+parameter mem_size = 32\'h2000_0000; ///as the memory is implemented 4 byte wide
+parameter xsim_mem_size = 32\'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB 
+
+`ifdef XSIM_ISIM
+ reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ parameter addr_offset_bits = 26;
+`else
+ reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; //  512 MB needed for reg space
+ parameter addr_offset_bits = 27;
+`endif
+
+/* preload reset_values from file */
+task automatic pre_load_rst_values;
+input dummy;
+begin
+ `include ""processing_system7_bfm_v2_0_5_reg_init.v"" /* This file has list of set_reset_data() calls to set the reset value for each register*/
+end
+endtask
+
+/* writes the reset data into the reg memory */
+task automatic set_reset_data;
+input [addr_width-1:0] address;
+input [data_width-1:0] data;
+reg   [addr_width-1:0] addr;
+begin
+addr = address >> 2; 
+`ifdef XSIM_ISIM
+  case(addr[addr_width-1:addr_offset_bits])
+    14 : reg_mem0[addr[addr_offset_bits-1:0]] = data;
+    15 : reg_mem1[addr[addr_offset_bits-1:0]] = data;
+  endcase
+`else
+  reg_mem[addr[addr_offset_bits-1:0]] = data;
+`endif
+end
+endtask
+
+/* writes the data into the reg memory */
+task automatic set_data;
+input [addr_width-1:0] addr;
+input [data_width-1:0] data;
+begin
+`ifdef XSIM_ISIM
+  case(addr[addr_width-1:addr_offset_bits])
+    6\'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data;
+    6\'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data;
+  endcase
+`else
+  reg_mem[addr[addr_offset_bits-1:0]] = data;
+`endif
+end
+endtask
+
+/* get the read data from reg mem */
+task automatic get_data;
+input [addr_width-1:0] addr;
+output [data_width-1:0] data;
+begin
+`ifdef XSIM_ISIM
+  case(addr[addr_width-1:addr_offset_bits])
+    6\'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]];
+    6\'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]];
+  endcase
+`else
+  data = reg_mem[addr[addr_offset_bits-1:0]];
+`endif
+end
+endtask
+
+/* read chunk of registers */
+task read_reg_mem;
+output[max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width:0] no_of_bytes;
+integer i;
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] temp_rd_data;
+reg [max_burst_bits-1:0] temp_data;
+integer bytes_left;
+begin
+addr = start_addr >> shft_addr_bits;
+bytes_left = no_of_bytes;
+
+`ifdef XLNX_INT_DBG
+   $display(""[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes"",$time, DISP_INT_INFO, start_addr,no_of_bytes ); 
+`endif 
+
+/* Get first data ... if unaligned address */
+get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]);
+
+if(no_of_bytes < mem_width ) begin
+  repeat(max_burst_bytes - mem_width)
+   temp_data = temp_data >> 8;
+
+end else begin
+  bytes_left = bytes_left - mem_width;
+  addr  = addr+1;
+  /* Got first data */
+  while (bytes_left > (mem_width-1) ) begin
+   temp_data = temp_data >> data_width;
+   get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
+   addr = addr+1;
+   bytes_left = bytes_left - mem_width;
+  end 
+
+  /* Get last valid data in the burst*/
+  get_data(addr,temp_rd_data);
+  while(bytes_left > 0) begin
+    temp_data = temp_data >> 8;
+    temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
+    temp_rd_data = temp_rd_data >> 8;
+    bytes_left = bytes_left - 1;
+  end
+  /* align to the brst_byte length */
+  repeat(max_burst_bytes - no_of_bytes)
+    temp_data = temp_data >> 8;
+end 
+data = temp_data;
+`ifdef XLNX_INT_DBG
+   $display(""[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)"",$time, DISP_INT_INFO, start_addr, data ); 
+`endif 
+end
+endtask
+
+initial 
+begin
+ pre_load_rst_values(1);
+end
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_ocm_mem.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics OCM model
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_ocm_mem();
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+parameter mem_size = 32\'h4_0000; /// 256 KB 
+parameter mem_addr_width = clogb2(mem_size/mem_width);
+
+reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory 
+
+/* preload memory from file */
+task automatic pre_load_mem_from_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+ $readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits);
+endtask
+
+/* preload memory with some random data */
+task automatic pre_load_mem;
+input [1:0]  data_type;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+integer i;
+reg [mem_addr_width-1:0] addr;
+begin
+addr = start_addr >> shft_addr_bits;
+
+for (i = 0; i < no_of_bytes; i = i + mem_width) begin
+   case(data_type)
+     ALL_RANDOM : ocm_memory[addr] = $random;
+     ALL_ZEROS  : ocm_memory[addr] = 32\'h0000_0000;
+     ALL_ONES   : ocm_memory[addr] = 32\'hFFFF_FFFF;
+     default    : ocm_memory[addr] = $random;
+   endcase
+   addr = addr+1;
+end 
+end
+endtask
+
+/* Write memory */
+task write_mem;
+input [max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width:0] no_of_bytes;
+reg [mem_addr_width-1:0] addr;
+reg [max_burst_bits-1 :0] wr_temp_data;
+reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
+integer bytes_left;
+integer pre_pad_bytes;
+integer post_pad_bytes;
+begin
+addr = start_addr >> shft_addr_bits;
+wr_temp_data = data;
+
+`ifdef XLNX_INT_DBG
+   $display(""[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\
+ Data (0x%0h)"",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); 
+`endif
+
+temp_data = wr_temp_data[data_width-1:0];
+bytes_left = no_of_bytes;
+/* when the no. of bytes to be updated is less than mem_width */
+if(bytes_left < mem_width) begin
+ /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
+ if(start_addr[shft_addr_bits-1:0] > 0) begin
+   temp_data     = ocm_memory[addr];
+   pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
+   repeat(pre_pad_bytes) temp_data = temp_data << 8;
+   repeat(pre_pad_bytes) begin
+     temp_data = temp_data >> 8;
+     temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
+     wr_temp_data = wr_temp_data >> 8;
+   end
+   bytes_left = bytes_left + pre_pad_bytes;
+ end
+ /* This is needed for post padding the data ...*/
+ post_pad_bytes = mem_width - bytes_left;
+ post_pad_data  = ocm_memory[addr];
+ repeat(post_pad_bytes) temp_data = temp_data << 8;
+ repeat(bytes_left) post_pad_data = post_pad_data >> 8;
+ repeat(post_pad_bytes) begin
+   temp_data = temp_data >> 8;
+   temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
+   post_pad_data = post_pad_data >> 8; 
+ end
+ ocm_memory[addr] = temp_data;
+end else begin
+ /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
+ if(start_addr[shft_addr_bits-1:0] > 0) begin
+  temp_data     = ocm_memory[addr];
+  pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
+  repeat(pre_pad_bytes) temp_data = temp_data << 8;
+  repeat(pre_pad_bytes) begin
+    temp_data = temp_data >> 8;
+    temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
+    wr_temp_data = wr_temp_data >> 8;
+    bytes_left = bytes_left -1;  
+  end
+ end else begin
+  wr_temp_data = wr_temp_data >> data_width;  
+  bytes_left = bytes_left - mem_width;
+ end
+ /* first data word end */
+ ocm_memory[addr] = temp_data;
+ addr = addr + 1;
+ while(bytes_left > (mem_width-1) ) begin  /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
+  ocm_memory[addr] = wr_temp_data[data_width-1:0];
+  addr = addr+1;
+  wr_temp_data = wr_temp_data >> data_width;
+  bytes_left = bytes_left - mem_width;
+ end
+ 
+ post_pad_data   = ocm_memory[addr];
+ post_pad_bytes  = mem_width - bytes_left;
+ /* This is needed for last transfer in unaliged burst */
+ if(bytes_left > 0) begin
+   temp_data = wr_temp_data[data_width-1:0];
+   repeat(post_pad_bytes) temp_data = temp_data << 8;
+   repeat(bytes_left) post_pad_data = post_pad_data >> 8;
+   repeat(post_pad_bytes) begin
+     temp_data = temp_data >> 8;
+     temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
+     post_pad_data = post_pad_data >> 8; 
+   end
+   ocm_memory[addr] = temp_data;
+ end
+end
+`ifdef XLNX_INT_DBG $display(""[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)"",$time, DISP_INT_INFO, start_addr ); 
+`endif
+end
+endtask
+
+/* read_memory */
+task read_mem;
+output[max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width:0] no_of_bytes;
+integer i;
+reg [mem_addr_width-1:0] addr;
+reg [data_width-1:0] temp_rd_data;
+reg [max_burst_bits-1:0] temp_data;
+integer pre_bytes;
+integer bytes_left;
+begin
+addr = start_addr >> shft_addr_bits;
+pre_bytes  = start_addr[shft_addr_bits-1:0];
+bytes_left = no_of_bytes;
+
+`ifdef XLNX_INT_DBG
+   $display(""[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes"",$time, DISP_INT_INFO, start_addr,no_of_bytes ); 
+`endif 
+
+/* Get first data ... if unaligned address */
+temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
+
+if(no_of_bytes < mem_width ) begin
+  temp_data = temp_data >> (pre_bytes * 8);
+  repeat(max_burst_bytes - mem_width)
+   temp_data = temp_data >> 8;
+
+end else begin
+  bytes_left = bytes_left - (mem_width - pre_bytes);
+  addr  = addr+1;
+  /* Got first data */
+  while (bytes_left > (mem_width-1) ) begin
+   temp_data = temp_data >> data_width;
+   temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
+   addr = addr+1;
+   bytes_left = bytes_left - mem_width;
+  end 
+
+  /* Get last valid data in the burst*/
+  temp_rd_data = ocm_memory[addr];
+  while(bytes_left > 0) begin
+    temp_data = temp_data >> 8;
+    temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
+    temp_rd_data = temp_rd_data >> 8;
+    bytes_left = bytes_left - 1;
+  end
+  /* align to the brst_byte length */
+  repeat(max_burst_bytes - no_of_bytes)
+    temp_data = temp_data >> 8;
+end 
+data = temp_data;
+`ifdef XLNX_INT_DBG
+   $display(""[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)"",$time, DISP_INT_INFO, start_addr, data ); 
+`endif 
+end
+endtask
+
+/* backdoor read to memory */
+task peek_mem_to_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+
+integer rd_fd;
+integer bytes;
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] rd_data;
+begin
+rd_fd = $fopen(file_name,""w"");
+bytes = no_of_bytes;
+
+addr = start_addr >> shft_addr_bits;
+while (bytes > 0) begin
+  rd_data = ocm_memory[addr];
+  $fdisplayh(rd_fd,rd_data);
+  bytes = bytes - 4;
+  addr = addr + 1;
+end
+end
+endtask
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_intr_wr_mem.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics interconnect for Writes between AFI and DDRC/OCM
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_intr_wr_mem(
+sw_clk,
+rstn,
+ 
+full,
+
+WR_DATA_ACK_OCM,
+WR_DATA_ACK_DDR,
+WR_ADDR,
+WR_DATA,
+WR_BYTES,
+WR_QOS,
+WR_DATA_VALID_OCM,
+WR_DATA_VALID_DDR
+);
+
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+/* local parameters for interconnect wr fifo model */
+
+input sw_clk, rstn;
+output full; 
+
+input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
+output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
+output reg [max_burst_bits-1:0] WR_DATA;
+output reg [addr_width-1:0] WR_ADDR;
+output reg [max_burst_bytes_width:0] WR_BYTES;
+output reg [axi_qos_width-1:0] WR_QOS;
+reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
+reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1];
+wire empty;
+
+assign empty = (wr_ptr === rd_ptr)?1\'b1: 1\'b0;
+assign full  = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1\'b1 :1\'b0;
+
+parameter SEND_DATA = 0,  WAIT_ACK = 1;
+reg state;
+
+task automatic write_mem;
+input [wr_fifo_data_bits-1:0] data;
+begin
+ wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data;
+ if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 
+   wr_ptr[intr_cnt_width-2:0] = 0;
+ else 
+   wr_ptr = wr_ptr + 1;
+end
+endtask
+
+always@(negedge rstn or posedge sw_clk)
+begin
+if(!rstn) begin
+ wr_ptr = 0;
+ rd_ptr = 0;
+ WR_DATA_VALID_DDR = 1\'b0;
+ WR_DATA_VALID_OCM = 1\'b0;
+ WR_QOS = 0;
+ state = SEND_DATA;
+end else begin
+ case(state)
+ SEND_DATA :begin
+    state = SEND_DATA;
+    WR_DATA_VALID_OCM = 1\'b0;
+    WR_DATA_VALID_DDR = 1\'b0;
+    if(!empty) begin
+      WR_DATA  = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb];
+      WR_ADDR  = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb];
+      WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
+      WR_QOS   = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb];
+      state  = WAIT_ACK;
+      case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]))
+       OCM_MEM : WR_DATA_VALID_OCM = 1;
+       DDR_MEM : WR_DATA_VALID_DDR = 1;
+       default : state = SEND_DATA;
+      endcase 
+      if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin
+\t    rd_ptr[intr_cnt_width-2:0] = 0;
+\t   end else begin
+        rd_ptr = rd_ptr+1;
+\t   end
+    end
+    end
+ WAIT_ACK :begin
+    state = WAIT_ACK;
+    if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin 
+      WR_DATA_VALID_OCM = 1\'b0;
+      WR_DATA_VALID_DDR = 1\'b0;
+      state = SEND_DATA;
+    end
+    end
+ endcase
+end
+end
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_intr_rd_mem.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics interconnect for Reads between AFI and DDRC/OCM
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_intr_rd_mem(
+sw_clk,
+rstn,
+ 
+full,
+empty,
+
+req,
+invalid_rd_req,
+rd_info,
+
+RD_DATA_OCM,
+RD_DATA_DDR,
+RD_DATA_VALID_OCM,
+RD_DATA_VALID_DDR
+
+);
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+input sw_clk, rstn;
+output full, empty;
+
+input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
+input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
+input req, invalid_rd_req;
+input [rd_info_bits-1:0] rd_info;
+
+reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
+reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
+wire full, empty;
+
+
+assign empty = (wr_ptr === rd_ptr)?1\'b1: 1\'b0;
+assign full  = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1\'b1 :1\'b0;
+
+/* read from the fifo */
+task read_mem;
+output [rd_afi_fifo_bits-1:0] data;
+begin
+ data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
+ if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 
+   rd_ptr[intr_cnt_width-2:0] = 0;
+ else 
+   rd_ptr = rd_ptr + 1;
+end
+endtask
+
+reg state;
+reg invalid_rd;
+/* write in the fifo */
+always@(negedge rstn or posedge sw_clk)
+begin
+if(!rstn) begin
+ wr_ptr  = 0;
+ rd_ptr  = 0;
+ state   = 0;
+ invalid_rd  = 0;
+end else begin
+ case (state)
+ 0 : begin
+  state  = 0;  
+  invalid_rd  = 0;
+  if(req)begin
+   state     = 1;
+   invalid_rd  = invalid_rd_req;
+  end
+ end
+ 1 : begin
+  state     = 1;
+  if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin 
+   if(RD_DATA_VALID_DDR)
+     rd_fifo[wr_ptr[intr_cnt_width-2:0]]  = {RD_DATA_DDR,rd_info};
+   else if(RD_DATA_VALID_OCM)
+     rd_fifo[wr_ptr[intr_cnt_width-2:0]]  = {RD_DATA_OCM,rd_info};
+   else 
+     rd_fifo[wr_ptr[intr_cnt_width-2:0]]  = rd_info;
+   if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 
+     wr_ptr[intr_cnt_width-2:0]  = 0;
+   else 
+     wr_ptr  = wr_ptr + 1;
+   state   = 0;
+   invalid_rd  = 0;
+  end
+ end
+ endcase
+end
+end
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_fmsw_gp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics FMSW switch.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_fmsw_gp(
+ sw_clk,
+ rstn,
+
+ w_qos_gp0,
+ r_qos_gp0,
+ wr_ack_ocm_gp0,
+ wr_ack_ddr_gp0,
+ wr_data_gp0,
+ wr_addr_gp0,
+ wr_bytes_gp0,
+ wr_dv_ocm_gp0,
+ wr_dv_ddr_gp0,
+ rd_req_ocm_gp0,
+ rd_req_ddr_gp0,
+ rd_req_reg_gp0,
+ rd_addr_gp0,
+ rd_bytes_gp0,
+ rd_data_ocm_gp0,
+ rd_data_ddr_gp0,
+ rd_data_reg_gp0,
+ rd_dv_ocm_gp0,
+ rd_dv_ddr_gp0,
+ rd_dv_reg_gp0,
+ 
+ w_qos_gp1,
+ r_qos_gp1,
+ wr_ack_ocm_gp1,
+ wr_ack_ddr_gp1,
+ wr_data_gp1,
+ wr_addr_gp1,
+ wr_bytes_gp1,
+ wr_dv_ocm_gp1,
+ wr_dv_ddr_gp1,
+ rd_req_ocm_gp1,
+ rd_req_ddr_gp1,
+ rd_req_reg_gp1,
+ rd_addr_gp1,
+ rd_bytes_gp1,
+ rd_data_ocm_gp1,
+ rd_data_ddr_gp1,
+ rd_data_reg_gp1,
+ rd_dv_ocm_gp1,
+ rd_dv_ddr_gp1,
+ rd_dv_reg_gp1,
+
+ ocm_wr_ack,
+ ocm_wr_dv,
+ ocm_rd_req,
+ ocm_rd_dv,
+ ddr_wr_ack,
+ ddr_wr_dv,
+ ddr_rd_req,
+ ddr_rd_dv,
+
+ reg_rd_req,
+ reg_rd_dv,
+
+ ocm_wr_qos,
+ ddr_wr_qos,
+ ocm_rd_qos,
+ ddr_rd_qos,
+ reg_rd_qos,
+
+ ocm_wr_addr,
+ ocm_wr_data,
+ ocm_wr_bytes,
+ ocm_rd_addr,
+ ocm_rd_data,
+ ocm_rd_bytes,
+
+ ddr_wr_addr,
+ ddr_wr_data,
+ ddr_wr_bytes,
+ ddr_rd_addr,
+ ddr_rd_data,
+ ddr_rd_bytes,
+
+ reg_rd_addr,
+ reg_rd_data,
+ reg_rd_bytes
+'b'
+);
+
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+input sw_clk;
+input rstn;
+
+input [axi_qos_width-1:0]w_qos_gp0;
+input [axi_qos_width-1:0]r_qos_gp0;
+input [axi_qos_width-1:0]w_qos_gp1;
+input [axi_qos_width-1:0]r_qos_gp1;
+
+output [axi_qos_width-1:0]ocm_wr_qos;
+output [axi_qos_width-1:0]ocm_rd_qos;
+output [axi_qos_width-1:0]ddr_wr_qos;
+output [axi_qos_width-1:0]ddr_rd_qos;
+output [axi_qos_width-1:0]reg_rd_qos;
+
+output wr_ack_ocm_gp0;
+output wr_ack_ddr_gp0;
+input [max_burst_bits-1:0] wr_data_gp0;
+input [addr_width-1:0] wr_addr_gp0;
+input [max_burst_bytes_width:0] wr_bytes_gp0;
+output wr_dv_ocm_gp0;
+output wr_dv_ddr_gp0;
+
+input rd_req_ocm_gp0;
+input rd_req_ddr_gp0;
+input rd_req_reg_gp0;
+input [addr_width-1:0] rd_addr_gp0;
+input [max_burst_bytes_width:0] rd_bytes_gp0;
+output [max_burst_bits-1:0] rd_data_ocm_gp0;
+output [max_burst_bits-1:0] rd_data_ddr_gp0;
+output [max_burst_bits-1:0] rd_data_reg_gp0;
+output rd_dv_ocm_gp0;
+output rd_dv_ddr_gp0;
+output rd_dv_reg_gp0;
+ 
+output wr_ack_ocm_gp1;
+output wr_ack_ddr_gp1;
+input [max_burst_bits-1:0] wr_data_gp1;
+input [addr_width-1:0] wr_addr_gp1;
+input [max_burst_bytes_width:0] wr_bytes_gp1;
+output wr_dv_ocm_gp1;
+output wr_dv_ddr_gp1;
+
+input rd_req_ocm_gp1;
+input rd_req_ddr_gp1;
+input rd_req_reg_gp1;
+input [addr_width-1:0] rd_addr_gp1;
+input [max_burst_bytes_width:0] rd_bytes_gp1;
+output [max_burst_bits-1:0] rd_data_ocm_gp1;
+output [max_burst_bits-1:0] rd_data_ddr_gp1;
+output [max_burst_bits-1:0] rd_data_reg_gp1;
+output rd_dv_ocm_gp1;
+output rd_dv_ddr_gp1;
+output rd_dv_reg_gp1;
+ 
+ 
+input ocm_wr_ack;
+output ocm_wr_dv;
+output [addr_width-1:0]ocm_wr_addr;
+output [max_burst_bits-1:0]ocm_wr_data;
+output [max_burst_bytes_width:0]ocm_wr_bytes;
+
+input ocm_rd_dv;
+input [max_burst_bits-1:0] ocm_rd_data;
+output ocm_rd_req;
+output [addr_width-1:0] ocm_rd_addr;
+output [max_burst_bytes_width:0] ocm_rd_bytes;
+
+input ddr_wr_ack;
+output ddr_wr_dv;
+output [addr_width-1:0]ddr_wr_addr;
+output [max_burst_bits-1:0]ddr_wr_data;
+output [max_burst_bytes_width:0]ddr_wr_bytes;
+
+input ddr_rd_dv;
+input [max_burst_bits-1:0] ddr_rd_data;
+output ddr_rd_req;
+output [addr_width-1:0] ddr_rd_addr;
+output [max_burst_bytes_width:0] ddr_rd_bytes;
+
+input reg_rd_dv;
+input [max_burst_bits-1:0] reg_rd_data;
+output reg_rd_req;
+output [addr_width-1:0] reg_rd_addr;
+output [max_burst_bytes_width:0] reg_rd_bytes;
+
+
+
+processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(w_qos_gp0),
+ .qos2(w_qos_gp1),
+ .prt_dv1(wr_dv_ocm_gp0),
+ .prt_dv2(wr_dv_ocm_gp1),
+ .prt_data1(wr_data_gp0),
+ .prt_data2(wr_data_gp1),
+ .prt_addr1(wr_addr_gp0),
+ .prt_addr2(wr_addr_gp1),
+ .prt_bytes1(wr_bytes_gp0),
+ .prt_bytes2(wr_bytes_gp1),
+ .prt_ack1(wr_ack_ocm_gp0),
+ .prt_ack2(wr_ack_ocm_gp1),
+ .prt_req(ocm_wr_dv),
+ .prt_qos(ocm_wr_qos),
+ .prt_data(ocm_wr_data),
+ .prt_addr(ocm_wr_addr),
+ .prt_bytes(ocm_wr_bytes),
+ .prt_ack(ocm_wr_ack)
+);
+
+processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(w_qos_gp0),
+ .qos2(w_qos_gp1),
+ .prt_dv1(wr_dv_ddr_gp0),
+ .prt_dv2(wr_dv_ddr_gp1),
+ .prt_data1(wr_data_gp0),
+ .prt_data2(wr_data_gp1),
+ .prt_addr1(wr_addr_gp0),
+ .prt_addr2(wr_addr_gp1),
+ .prt_bytes1(wr_bytes_gp0),
+ .prt_bytes2(wr_bytes_gp1),
+ .prt_ack1(wr_ack_ddr_gp0),
+ .prt_ack2(wr_ack_ddr_gp1),
+ .prt_req(ddr_wr_dv),
+ .prt_qos(ddr_wr_qos),
+ .prt_data(ddr_wr_data),
+ .prt_addr(ddr_wr_addr),
+ .prt_bytes(ddr_wr_bytes),
+ .prt_ack(ddr_wr_ack)
+);
+
+processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_gp0),
+ .qos2(r_qos_gp1),
+ .prt_req1(rd_req_ocm_gp0),
+ .prt_req2(rd_req_ocm_gp1),
+ .prt_data1(rd_data_ocm_gp0),
+ .prt_data2(rd_data_ocm_gp1),
+ .prt_addr1(rd_addr_gp0),
+ .prt_addr2(rd_addr_gp1),
+ .prt_bytes1(rd_bytes_gp0),
+ .prt_bytes2(rd_bytes_gp1),
+ .prt_dv1(rd_dv_ocm_gp0),
+ .prt_dv2(rd_dv_ocm_gp1),
+ .prt_req(ocm_rd_req),
+ .prt_qos(ocm_rd_qos),
+ .prt_data(ocm_rd_data),
+ .prt_addr(ocm_rd_addr),
+ .prt_bytes(ocm_rd_bytes),
+ .prt_dv(ocm_rd_dv)
+);
+
+processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_gp0),
+ .qos2(r_qos_gp1),
+ .prt_req1(rd_req_ddr_gp0),
+ .prt_req2(rd_req_ddr_gp1),
+ .prt_data1(rd_data_ddr_gp0),
+ .prt_data2(rd_data_ddr_gp1),
+ .prt_addr1(rd_addr_gp0),
+ .prt_addr2(rd_addr_gp1),
+ .prt_bytes1(rd_bytes_gp0),
+ .prt_bytes2(rd_bytes_gp1),
+ .prt_dv1(rd_dv_ddr_gp0),
+ .prt_dv2(rd_dv_ddr_gp1),
+ .prt_req(ddr_rd_req),
+ .prt_qos(ddr_rd_qos),
+ .prt_data(ddr_rd_data),
+ .prt_addr(ddr_rd_addr),
+ .prt_bytes(ddr_rd_bytes),
+ .prt_dv(ddr_rd_dv)
+);
+
+processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_gp0),
+ .qos2(r_qos_gp1),
+ .prt_req1(rd_req_reg_gp0),
+ .prt_req2(rd_req_reg_gp1),
+ .prt_data1(rd_data_reg_gp0),
+ .prt_data2(rd_data_reg_gp1),
+ .prt_addr1(rd_addr_gp0),
+ .prt_addr2(rd_addr_gp1),
+ .prt_bytes1(rd_bytes_gp0),
+ .prt_bytes2(rd_bytes_gp1),
+ .prt_dv1(rd_dv_reg_gp0),
+ .prt_dv2(rd_dv_reg_gp1),
+ .prt_req(reg_rd_req),
+ .prt_qos(reg_rd_qos),
+ .prt_data(reg_rd_data),
+ .prt_addr(reg_rd_addr),
+ .prt_bytes(reg_rd_bytes),
+ .prt_dv(reg_rd_dv)
+);
+
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_regc.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Controller for Register Map Memory
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_regc(
+ rstn,
+ sw_clk,
+
+/* Goes to port 0 of REG */
+ reg_rd_req_port0,
+ reg_rd_dv_port0,
+ reg_rd_addr_port0,
+ reg_rd_data_port0,
+ reg_rd_bytes_port0,
+ reg_rd_qos_port0,
+
+
+/* Goes to port 1 of REG */
+ reg_rd_req_port1,
+ reg_rd_dv_port1,
+ reg_rd_addr_port1,
+ reg_rd_data_port1,
+ reg_rd_bytes_port1,
+ reg_rd_qos_port1 
+
+);
+
+input rstn;
+input sw_clk;
+
+input reg_rd_req_port0;
+output reg_rd_dv_port0;
+input[31:0] reg_rd_addr_port0;
+output[1023:0] reg_rd_data_port0;
+input[7:0] reg_rd_bytes_port0;
+input [3:0] reg_rd_qos_port0;
+
+input reg_rd_req_port1;
+output reg_rd_dv_port1;
+input[31:0] reg_rd_addr_port1;
+output[1023:0] reg_rd_data_port1;
+input[7:0] reg_rd_bytes_port1;
+input[3:0] reg_rd_qos_port1;
+
+wire [3:0] rd_qos;
+reg [1023:0] rd_data;
+wire [31:0] rd_addr;
+wire [7:0] rd_bytes;
+reg rd_dv;
+wire rd_req;
+
+processing_system7_bfm_v2_0_5_arb_rd reg_read_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(reg_rd_qos_port0),
+ .qos2(reg_rd_qos_port1),
+   
+ .prt_req1(reg_rd_req_port0),
+ .prt_req2(reg_rd_req_port1),
+   
+ .prt_data1(reg_rd_data_port0),
+ .prt_data2(reg_rd_data_port1),
+   
+ .prt_addr1(reg_rd_addr_port0),
+ .prt_addr2(reg_rd_addr_port1),
+   
+ .prt_bytes1(reg_rd_bytes_port0),
+ .prt_bytes2(reg_rd_bytes_port1),
+   
+ .prt_dv1(reg_rd_dv_port0),
+ .prt_dv2(reg_rd_dv_port1),
+   
+ .prt_qos(rd_qos),
+ .prt_req(rd_req),
+ .prt_data(rd_data),
+ .prt_addr(rd_addr),
+ .prt_bytes(rd_bytes),
+ .prt_dv(rd_dv)
+
+);
+
+processing_system7_bfm_v2_0_5_reg_map regm();
+
+reg state;
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ rd_dv <= 0;
+ state <= 0;
+end else begin
+ case(state) 
+ 0:begin
+     state <= 0;
+     rd_dv <= 0;
+     if(rd_req) begin
+       regm.read_reg_mem(rd_data,rd_addr, rd_bytes); 
+       rd_dv <= 1;
+       state <= 1;
+     end
+
+   end
+ 1:begin
+       rd_dv  <= 0;
+       state <= 0;
+   end 
+
+ endcase
+end /// if
+end// always
+
+endmodule 
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_ocmc.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Controller for OCM model
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_ocmc(
+ rstn,
+ sw_clk,
+
+/* Goes to port 0 of OCM */
+ ocm_wr_ack_port0,
+ ocm_wr_dv_port0,
+ ocm_rd_req_port0,
+ ocm_rd_dv_port0,
+ ocm_wr_addr_port0,
+ ocm_wr_data_port0,
+ ocm_wr_bytes_port0,
+ ocm_rd_addr_port0,
+ ocm_rd_data_port0,
+ ocm_rd_bytes_port0,
+ ocm_wr_qos_port0,
+ ocm_rd_qos_port0,
+
+
+/* Goes to port 1 of OCM */
+ ocm_wr_ack_port1,
+ ocm_wr_dv_port1,
+ ocm_rd_req_port1,
+ ocm_rd_dv_port1,
+ ocm_wr_addr_port1,
+ ocm_wr_data_port1,
+ ocm_wr_bytes_port1,
+ ocm_rd_addr_port1,
+ ocm_rd_data_port1,
+ ocm_rd_bytes_port1,
+ ocm_wr_qos_port1,
+ ocm_rd_qos_port1 
+
+);
+
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+input rstn;
+input sw_clk;
+
+output ocm_wr_ack_port0;
+input ocm_wr_dv_port0;
+input ocm_rd_req_port0;
+output ocm_rd_dv_port0;
+input[addr_width-1:0] ocm_wr_addr_port0;
+input[max_burst_bits-1:0] ocm_wr_data_port0;
+input[max_burst_bytes_width:0] ocm_wr_bytes_port0;
+input[addr_width-1:0] ocm_rd_addr_port0;
+output[max_burst_bits-1:0] ocm_rd_data_port0;
+input[max_burst_bytes_width:0] ocm_rd_bytes_port0;
+input [axi_qos_width-1:0] ocm_wr_qos_port0;
+input [axi_qos_width-1:0] ocm_rd_qos_port0;
+
+output ocm_wr_ack_port1;
+input ocm_wr_dv_port1;
+input ocm_rd_req_port1;
+output ocm_rd_dv_port1;
+input[addr_width-1:0] ocm_wr_addr_port1;
+input[max_burst_bits-1:0] ocm_wr_data_port1;
+input[max_burst_bytes_width:0] ocm_wr_bytes_port1;
+input[addr_width-1:0] ocm_rd_addr_port1;
+output[max_burst_bits-1:0] ocm_rd_data_port1;
+input[max_burst_bytes_width:0] ocm_rd_bytes_port1;
+input[axi_qos_width-1:0] ocm_wr_qos_port1;
+input[axi_qos_width-1:0] ocm_rd_qos_port1;
+
+wire [axi_qos_width-1:0] wr_qos;
+wire wr_req;
+wire [max_burst_bits-1:0] wr_data;
+wire [addr_width-1:0] wr_addr;
+wire [max_burst_bytes_width:0] wr_bytes;
+reg wr_ack;
+
+wire [axi_qos_width-1:0] rd_qos;
+reg [max_burst_bits-1:0] rd_data;
+wire [addr_width-1:0] rd_addr;
+wire [max_burst_bytes_width:0] rd_bytes;
+reg rd_dv;
+wire rd_req;
+
+processing_system7_bfm_v2_0_5_arb_wr ocm_write_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(ocm_wr_qos_port0),
+ .qos2(ocm_wr_qos_port1),
+   
+ .prt_dv1(ocm_wr_dv_port0),
+ .prt_dv2(ocm_wr_dv_port1),
+   
+ .prt_data1(ocm_wr_data_port0),
+ .prt_data2(ocm_wr_data_port1),
+   
+ .prt_addr1(ocm_wr_addr_port0),
+ .prt_addr2(ocm_wr_addr_port1),
+   
+ .prt_bytes1(ocm_wr_bytes_port0),
+ .prt_bytes2(ocm_wr_bytes_port1),
+   
+ .prt_ack1(ocm_wr_ack_port0),
+ .prt_ack2(ocm_wr_ack_port1),
+   
+ .prt_qos(wr_qos),
+ .prt_req(wr_req),
+ .prt_data(wr_data),
+ .prt_addr(wr_addr),
+ .prt_bytes(wr_bytes),
+ .prt_ack(wr_ack)
+
+);
+
+processing_system7_bfm_v2_0_5_arb_rd ocm_read_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(ocm_rd_qos_port0),
+ .qos2(ocm_rd_qos_port1),
+   
+ .prt_req1(ocm_rd_req_port0),
+ .prt_req2(ocm_rd_req_port1),
+   
+ .prt_data1(ocm_rd_data_port0),
+ .prt_data2(ocm_rd_data_port1),
+   
+ .prt_addr1(ocm_rd_addr_port0),
+ .prt_addr2(ocm_rd_addr_port1),
+   
+ .prt_bytes1(ocm_rd_bytes_port0),
+ .prt_bytes2(ocm_rd_bytes_port1),
+   
+ .prt_dv1(ocm_rd_dv_port0),
+ .prt_dv2(ocm_rd_dv_port1),
+   
+ .prt_qos(rd_qos),
+ .prt_req(rd_req),
+ .prt_data(rd_data),
+ .prt_addr(rd_addr),
+ .prt_bytes(rd_bytes),
+ .prt_dv(rd_dv)
+
+);
+
+processing_system7_bfm_v2_0_5_ocm_mem ocm();
+
+reg [1:0] state;
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ wr_ack <= 0; 
+ rd_dv <= 0;
+ state <= 2\'d0;
+end else begin
+ case(state) 
+ 0:begin
+     state <= 0;
+     wr_ack <= 0;
+     rd_dv <= 0;
+     if(wr_req) begin
+       ocm.write_mem(wr_data , wr_addr, wr_bytes); 
+       wr_ack <= 1;
+       state <= 1;
+     end
+     if(rd_req) begin
+       ocm.read_mem(rd_data,rd_addr, rd_bytes); 
+       rd_dv <= 1;
+       state <= 1;
+     end
+
+   end
+ 1:begin
+       wr_ack <= 0;
+       rd_dv  <= 0;
+       state <= 0;
+   end 
+
+ endcase
+end /// if
+end// always
+
+endmodule 
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_interconnect_model.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics Top_interconnect Switch.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_interconnect_model (
+ rstn,
+ sw_clk, 
+ 
+ w_qos_gp0,
+ w_qos_gp1,
+ w_qos_hp0,
+ w_qos_hp1,
+ w_qos_hp2,
+ w_qos_hp3,
+
+ r_qos_gp0,
+ r_qos_gp1,
+ r_qos_hp0,
+ r_qos_hp1,
+ r_qos_hp2,
+ r_qos_hp3,
+
+ wr_ack_ddr_gp0,
+ wr_ack_ocm_gp0,
+ wr_data_gp0,
+ wr_addr_gp0,
+ wr_bytes_gp0,
+ wr_dv_ddr_gp0,
+ wr_dv_ocm_gp0,
+
+ rd_req_ddr_gp0,
+ rd_req_ocm_gp0,
+ rd_req_reg_gp0,
+ rd_addr_gp0,
+ rd_bytes_gp0,
+ rd_data_ddr_gp0,
+ rd_data_ocm_gp0,
+ rd_data_reg_gp0,
+ rd_dv_ddr_gp0,
+ rd_dv_ocm_gp0,
+ rd_dv_reg_gp0,
+
+ wr_ack_ddr_gp1,
+ wr_ack_ocm_gp1,
+ wr_data_gp1,
+ wr_addr_gp1,
+ wr_bytes_gp1,
+ wr_dv_ddr_gp1,
+ wr_dv_ocm_gp1,
+ rd_req_ddr_gp1,
+ rd_req_ocm_gp1,
+ rd_req_reg_gp1,
+ rd_addr_gp1,
+ rd_bytes_gp1,
+ rd_data_ddr_gp1,
+ rd_data_ocm_gp1,
+ rd_data_reg_gp1,
+ rd_dv_ddr_gp1,
+ rd_dv_ocm_gp1,
+ rd_dv_reg_gp1,
+
+ wr_ack_ddr_hp0,
+ wr_ack_ocm_hp0,
+ wr_data_hp0,
+ wr_addr_hp0,
+ wr_bytes_hp0,
+ wr_dv_ddr_hp0,
+ wr_dv_ocm_hp0,
+ rd_req_ddr_hp0,
+ rd_req_ocm_hp0,
+ rd_addr_hp0,
+ rd_bytes_hp0,
+ rd_data_ddr_hp0,
+ rd_data_ocm_hp0,
+ rd_dv_ddr_hp0,
+ rd_dv_ocm_hp0,
+
+ wr_ack_ddr_hp1,
+ wr_ack_ocm_hp1,
+ wr_data_hp1,
+ wr_addr_hp1,
+ wr_bytes_hp1,
+ wr_dv_ddr_hp1,
+ wr_dv_ocm_hp1,
+ rd_req_ddr_hp1,
+ rd_req_ocm_hp1,
+ rd_addr_hp1,
+ rd_bytes_hp1,
+ rd_data_ddr_hp1,
+ rd_data_ocm_hp1,
+ rd_dv_ddr_hp1,
+ rd_dv_ocm_hp1,
+
+ wr_ack_ddr_hp2,
+ wr_ack_ocm_hp2,
+ wr_data_hp2,
+ wr_addr_hp2,
+ wr_bytes_hp2,
+ wr_dv_ddr_hp2,
+ wr_dv_ocm_hp2,
+ rd_req_ddr_hp2,
+ rd_req_ocm_hp2,
+ rd_addr_hp2,
+ rd_bytes_hp2,
+ rd_data_ddr_hp2,
+ rd_data_ocm_hp2,
+ rd_dv_ddr_hp2,
+ rd_dv_ocm_hp2,
+
+ wr_ack_ddr_hp3,
+ wr_ack_ocm_hp3,
+ wr_data_hp3,
+ wr_addr_hp3,
+ wr_bytes_hp3,
+ wr_dv_ddr_hp3,
+ wr_dv_ocm_hp3,
+ rd_req_ddr_hp3,
+ rd_req_ocm_hp3,
+ rd_addr_hp3,
+ rd_bytes_hp3,
+ rd_data_ddr_hp3,
+ rd_data_ocm_hp3,
+ rd_dv_ddr_hp3,
+ rd_dv_ocm_hp3,
+
+/* Goes to port 1 of DDR */
+ ddr_wr_ack_port1,
+ ddr_wr_dv_port1,
+ ddr_rd_req_port1,
+ ddr_rd_dv_port1,
+ ddr_wr_addr_port1,
+ ddr_wr_data_port1,
+ ddr_wr_bytes_port1,
+ ddr_rd_addr_port1,
+ ddr_rd_data_port1,
+ ddr_rd_bytes_port1,
+ ddr_wr_qos_port1,
+ ddr_rd_qos_port1,
+
+/* Goes to port2 of DDR */
+ ddr_wr_ack_port2,
+ ddr_wr_dv_port2,
+ ddr_rd_req_port2,
+ ddr_rd_dv_port2,
+ ddr_wr_addr_port2,
+ ddr_wr_data_port2,
+ ddr_wr_bytes_port2,
+ ddr_rd_addr_port2,
+ ddr_rd_data_port2,
+ ddr_rd_bytes_port2,
+ ddr_wr_qos_port2,
+ ddr_rd_qos_port2,
+
+/* Goes to port3 of DDR */
+ ddr_wr_ack_port3,
+ ddr_wr_dv_port3,
+ ddr_rd_req_port3,
+ ddr_rd_dv_port3,
+ ddr_wr_addr_port3,
+ ddr_wr_data_port3,
+ ddr_wr_bytes_port3,
+ ddr_rd_addr_port3,
+ ddr_rd_data_port3,
+ ddr_rd_bytes_port3,
+ ddr_wr_qos_port3,
+ ddr_rd_qos_port3,
+
+/* Goes to port1 of OCM */
+ ocm_wr_qos_port1,
+ ocm_rd_qos_port1,
+ ocm_wr_dv_port1,
+ ocm_wr_data_port1,
+ ocm_wr_addr_port1,
+ ocm_wr_bytes_port1,
+ ocm_wr_ack_port1,
+ ocm_rd_req_port1,
+ ocm_rd_data_port1,
+ ocm_rd_addr_port1,
+ ocm_rd_bytes_port1,
+ ocm_rd_dv_port1,
+
+/* Goes to port1 for RegMap  */
+ reg_rd_qos_port1,
+ reg_rd_req_port1,
+ reg_rd_data_port1,
+ reg_rd_addr_port1,
+ reg_rd_bytes_port1,
+ reg_rd_dv_port1
+
+);
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+input rstn;
+input sw_clk;
+
+input [axi_qos_width-1:0] w_qos_gp0;
+input [axi_qos_width-1:0] w_qos_gp1;
+input [axi_qos_width-1:0] w_qos_hp0;
+input [axi_qos_width-1:0] w_qos_hp1;
+input [axi_qos_width-1:0] w_qos_hp2;
+input [axi_qos_width-1:0] w_qos_hp3;
+
+input [axi_qos_width-1:0] r_qos_gp0;
+input [axi_qos_width-1:0] r_qos_gp1;
+input [axi_qos_width-1:0] r_qos_hp0;
+input [axi_qos_width-1:0] r_qos_hp1;
+input [axi_qos_width-1:0] r_qos_hp2;
+input [axi_qos_width-1:0] r_qos_hp3;
+ 
+output [axi_qos_width-1:0] ocm_wr_qos_port1;
+output [axi_qos_width-1:0] ocm_rd_qos_port1;
+
+output wr_ack_ddr_gp0;
+output wr_ack_ocm_gp0;
+input[max_burst_bits-1:0] wr_data_gp0;
+input[addr_width-1:0] wr_addr_gp0;
+input[max_burst_bytes_width:0] wr_bytes_gp0;
+input wr_dv_ddr_gp0;
+input wr_dv_ocm_gp0;
+input rd_req_ddr_gp0;
+input rd_req_ocm_gp0;
+input rd_req_reg_gp0;
+input[addr_width-1:0] rd_addr_gp0;
+input[max_burst_bytes_width:0] rd_bytes_gp0;
+output[max_burst_bits-1:0] rd_data_ddr_gp0;
+output[max_burst_bits-1:0] rd_data_ocm_gp0;
+output[max_burst_bits-1:0] rd_data_reg_gp0;
+output rd_dv_ddr_gp0;
+output rd_dv_ocm_gp0;
+output rd_dv_reg_gp0;
+
+output wr_ack_ddr_gp1;
+output wr_ack_ocm_gp1;
+input[max_burst_bits-1:0] wr_data_gp1;
+input[addr_width-1:0] wr_addr_gp1;
+input[max_burst_bytes_width:0] wr_bytes_gp1;
+input wr_dv_ddr_gp1;
+input wr_dv_ocm_gp1;
+input rd_req_ddr_gp1;
+input rd_req_ocm_gp1;
+input rd_req_reg_gp1;
+input[addr_width-1:0] rd_addr_gp1;
+input[max_burst_bytes_width:0] rd_bytes_gp1;
+output[max_burst_bits-1:0] rd_data_ddr_gp1;
+output[max_burst_bits-1:0] rd_data_ocm_gp1;
+output[max_burst_bits-1:0] rd_data_reg_gp1;
+output rd_dv_ddr_gp1;
+output rd_dv_ocm_gp1;
+output rd_dv_reg_gp1;
+
+output wr_ack_ddr_hp0;
+output wr_ack_ocm_hp0;
+input[max_burst_bits-1:0] wr_data_hp0;
+input[addr_width-1:0] wr_addr_hp0;
+input[max_burst_bytes_width:0] wr_bytes_hp0;
+input wr_dv_ddr_hp0;
+input wr_dv_ocm_hp0;
+input rd_req_ddr_hp0;
+input rd_req_ocm_hp0;
+input[addr_width-1:0] rd_addr_hp0;
+input[max_burst_bytes_width:0] rd_bytes_hp0;
+output[max_burst_bits-1:0] rd_data_ddr_hp0;
+output[max_burst_bits-1:0] rd_data_ocm_hp0;
+output rd_dv_ddr_hp0;
+output rd_dv_ocm_hp0;
+
+output wr_ack_ddr_hp1;
+output wr_ack_ocm_hp1;
+input[max_burst_bits-1:0] wr_data_hp1;
+input[addr_width-1:0] wr_addr_hp1;
+input[max_burst_bytes_width:0] wr_bytes_hp1;
+input wr_dv_ddr_hp1;
+input wr_dv_ocm_hp1;
+input rd_req_ddr_hp1;
+input rd_req_ocm_hp1;
+input[addr_width-1:0] rd_addr_hp1;
+input[max_burst_bytes_width:0] rd_bytes_hp1;
+output[max_burst_bits-1:0] rd_data_ddr_hp1;
+output[max_burst_bits-1:0] rd_data_ocm_hp1;
+output rd_dv_ddr_hp1;
+output rd_dv_ocm_hp1;
+
+output wr_ack_ddr_hp2;
+output wr_ack_ocm_hp2;
+input[max_burst_bits-1:0] wr_data_hp2;
+input[addr_width-1:0] wr_addr_hp2;
+input[max_burst_bytes_width:0] wr_bytes_hp2;
+input wr_dv_ddr_hp2;
+input wr_dv_ocm_hp2;
+input rd_req_ddr_hp2;
+input rd_req_ocm_hp2;
+input[addr_width-1:0] rd_addr_hp2;
+input[max_burst_bytes_width:0] rd_bytes_hp2;
+output[max_burst_bits-1:0] rd_data_ddr_hp2;
+output[max_burst_bits-1:0] rd_data_ocm_hp2;
+output rd_dv_ddr_hp2;
+output rd_dv_ocm_hp2;
+
+output wr_ack_ddr_hp3;
+output wr_ack_ocm_hp3;
+input[max_burst_bits-1:0] wr_data_hp3;
+input[addr_width-1:0] wr_addr_hp3;
+input[max_burst_bytes_width:0] wr_bytes_hp3;
+input wr_dv_ddr_hp3;
+input wr_dv_ocm_hp3;
+input rd_req_ddr_hp3;
+input rd_req_ocm_hp3;
+input[addr_width-1:0] rd_addr_hp3;
+input[max_burst_bytes_width:0] rd_bytes_hp3;
+output[max_burst_bits-1:0] rd_data_ddr_hp3;
+output[max_burst_bits-1:0] rd_data_ocm_hp3;
+output rd_dv_ddr_hp3;
+output rd_dv_ocm_hp3;
+
+/* Goes to port 1 of DDR */
+input ddr_wr_ack_port1;
+output ddr_wr_dv_port1;
+output ddr_rd_req_port1;
+input ddr_rd_dv_port1;
+output[addr_width-1:0] ddr_wr_addr_port1;
+output[max_burst_bits-1:0] ddr_wr_data_port1;
+output[max_burst_bytes_width:0] ddr_wr_bytes_port1;
+output[addr_width-1:0] ddr_rd_addr_port1;
+input[max_burst_bits-1:0] ddr_rd_data_port1;
+output[max_burst_bytes_width:0] ddr_rd_bytes_port1;
+output [axi_qos_width-1:0] ddr_wr_qos_port1;
+output [axi_qos_width-1:0] ddr_rd_qos_port1;
+
+/* Goes to port2 of DDR */
+input ddr_wr_ack_port2;
+output ddr_wr_dv_port2;
+output ddr_rd_req_port2;
+input ddr_rd_dv_port2;
+output[addr_width-1:0] ddr_wr_addr_port2;
+output[max_burst_bits-1:0] ddr_wr_data_port2;
+output[max_burst_bytes_width:0] ddr_wr_bytes_port2;
+output[addr_width-1:0] ddr_rd_addr_port2;
+input[max_burst_bits-1:0] ddr_rd_data_port2;
+output[max_burst_bytes_width:0] ddr_rd_bytes_port2;
+output [axi_qos_width-1:0] ddr_wr_qos_port2;
+output [axi_qos_width-1:0] ddr_rd_qos_port2;
+
+/* Goes to port3 of DDR */
+input ddr_wr_ack_port3;
+output ddr_wr_dv_port3;
+output ddr_rd_req_port3;
+input ddr_rd_dv_port3;
+output[addr_width-1:0] ddr_wr_addr_port3;
+output[max_burst_bits-1:0] ddr_wr_data_port3;
+output[max_burst_bytes_width:0] ddr_wr_bytes_port3;
+output[addr_width-1:0] ddr_rd_addr_port3;
+input[max_burst_bits-1:0] ddr_rd_data_port3;
+output[max_burst_bytes_width:0] ddr_rd_bytes_port3;
+output [axi_qos_width-1:0] ddr_wr_qos_port3;
+output [axi_qos_width-1:0] ddr_rd_qos_port3;
+
+/* Goes to port1 of OCM */
+input ocm_wr_ack_port1;
+output ocm_wr_dv_port1;
+output ocm_rd_req_port1;
+input ocm_rd_dv_port1;
+output[max_burst_bits-1:0] ocm_wr_data_port1;
+output[addr_width-1:0] ocm_wr_addr_port1;
+output[max_burst_bytes_width:0] ocm_wr_bytes_port1;
+input[max_burst_bits-1:0] ocm_rd_data_port1;
+output[addr_width-1:0] ocm_rd_addr_port1;
+output[max_burst_bytes_width:0] ocm_rd_bytes_port1;
+
+/* Goes to port1 of REG */
+output [axi_qos_width-1:0] reg_rd_qos_port1;  
+output reg_rd_req_port1;
+input reg_rd_dv_port1;
+input[max_burst_bits-1:0] reg_rd_data_port1;
+output[addr_width-1:0] reg_rd_addr_port1;
+output[max_burst_bytes_width:0] reg_rd_bytes_port1;
+
+wire ocm_wr_dv_osw0;
+wire ocm_wr_dv_osw1;
+wire[max_burst_bits-1:0] ocm_wr_data_osw0;
+wire[max_burst_bits-1:0] ocm_wr_data_osw1;
+wire[addr_width-1:0] ocm_wr_addr_osw0;
+wire[addr_width-1:0] ocm_wr_addr_osw1;
+wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0;
+wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1;
+wire ocm_wr_ack_osw0;
+wire ocm_wr_ack_osw1;
+wire ocm_rd_req_osw0;
+wire ocm_rd_req_osw1;
+wire[max_burst_bits-1:0] ocm_rd_data_osw0;
+wire[max_burst_bits-1:0] ocm_rd_data_osw1;
+wire[addr_width-1:0] ocm_rd_addr_osw0;
+wire[addr_width-1:0] ocm_rd_addr_osw1;
+wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0;
+wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1;
+wire ocm_rd_dv_osw0;
+wire ocm_rd_dv_osw1;
+
+wire [axi_qos_width-1:0] ocm_wr_qos_osw0;
+wire [axi_qos_width-1:0] ocm_wr_qos_osw1;
+wire [axi_qos_width-1:0] ocm_rd_qos_osw0;
+wire [axi_qos_width-1:0] ocm_rd_qos_osw1;
+
+
+processing_system7_bfm_v2_0_5_fmsw_gp fmsw (
+ .sw_clk(sw_clk),
+ .rstn(rstn),
+   
+ .w_qos_gp0(w_qos_gp0),
+ .r_qos_gp0(r_qos_gp0),
+ .wr_ack_ocm_gp0(wr_ack_ocm_gp0),
+ .wr_ack_ddr_gp0(wr_ack_ddr_gp0),
+ .wr_data_gp0(wr_data_gp0),
+ .wr_addr_gp0(wr_addr_gp0),
+ .wr_bytes_gp0(wr_bytes_gp0),
+ .wr_dv_ocm_gp0(wr_dv_ocm_gp0),
+ .wr_dv_ddr_gp0(wr_dv_ddr_gp0),
+ .rd_req_ocm_gp0(rd_req_ocm_gp0),
+ .rd_req_ddr_gp0(rd_req_ddr_gp0),
+ .rd_req_reg_gp0(rd_req_reg_gp0),
+ .rd_addr_gp0(rd_addr_gp0),
+ .rd_bytes_gp0(rd_bytes_gp0),
+ .rd_data_ddr_gp0(rd_data_ddr_gp0),
+ .rd_data_ocm_gp0(rd_data_ocm_gp0),
+ .rd_data_reg_gp0(rd_data_reg_gp0),
+ .rd_dv_ocm_gp0(rd_dv_ocm_gp0),
+ .rd_dv_ddr_gp0(rd_dv_ddr_gp0),
+ .rd_dv_reg_gp0(rd_dv_reg_gp0),
+ 
+ .w_qos_gp1(w_qos_gp1),
+ .r_qos_gp1(r_qos_gp1),
+ .wr_ack_ocm_gp1(wr_ack_ocm_gp1),
+ .wr_ack_ddr_gp1(wr_ack_ddr_gp1),
+ .wr_data_gp1(wr_data_gp1),
+ .wr_addr_gp1(wr_addr_gp1),
+ .wr_bytes_gp1(wr_bytes_gp1),
+ .wr_dv_ocm_gp1(wr_dv_ocm_gp1),
+ .wr_dv_ddr_gp1(wr_dv_ddr_gp1),
+ .rd_req_ocm_gp1(rd_req_ocm_gp1),
+ .rd_req_ddr_gp1(rd_req_ddr_gp1),
+ .rd_req_reg_gp1(rd_req_reg_gp1),
+ .rd_addr_gp1(rd_addr_gp1),
+ .rd_bytes_gp1(rd_bytes_gp1),
+ .rd_data_ddr_gp1(rd_data_ddr_gp1),
+ .rd_data_ocm_gp1(rd_data_ocm_gp1),
+ .rd_data_reg_gp1(rd_data_reg_gp1),
+ .rd_dv_ocm_gp1(rd_dv_ocm_gp1),
+ .rd_dv_ddr_gp1(rd_dv_ddr_gp1),
+ .rd_dv_reg_gp1(rd_dv_reg_gp1),
+    
+ .ocm_wr_ack (ocm_wr_ack_osw0),
+ .ocm_wr_dv  (ocm_wr_dv_osw0),
+ .ocm_rd_req (ocm_rd_req_osw0),
+ .ocm_rd_dv  (ocm_rd_dv_osw0),
+ .ocm_wr_addr(ocm_wr_addr_osw0),
+ .ocm_wr_data(ocm_wr_data_osw0),
+ .ocm_wr_bytes(ocm_wr_bytes_osw0),
+ .ocm_rd_addr(ocm_rd_addr_osw0),
+ .ocm_rd_data(ocm_rd_data_osw0),
+ .ocm_rd_bytes(ocm_rd_bytes_osw0),
+
+ .ocm_wr_qos(ocm_wr_qos_osw0),
+ .ocm_rd_qos(ocm_rd_qos_osw0),
+ 
+ .ddr_wr_qos(ddr_wr_qos_port1),
+ .ddr_rd_qos(ddr_rd_qos_port1),
+
+ .reg_rd_qos(reg_rd_qos_port1),
+
+ .ddr_wr_ack(ddr_wr_ack_port1),
+ .ddr_wr_dv(ddr_wr_dv_port1),
+ .ddr_rd_req(ddr_rd_req_port1),
+ .ddr_rd_dv(ddr_rd_dv_port1),
+ .ddr_wr_addr(ddr_wr_addr_port1),
+ .ddr_wr_data(ddr_wr_data_port1),
+ .ddr_wr_bytes(ddr_wr_bytes_port1),
+ .ddr_rd_addr(ddr_rd_addr_port1),
+ .ddr_rd_data(ddr_rd_data_port1),
+ .ddr_rd_bytes(ddr_rd_bytes_port1),
+
+ .reg_rd_req(reg_rd_req_port1),
+ .reg_rd_dv(reg_rd_dv_port1),
+ .reg_rd_addr(reg_rd_addr_port1),
+ .reg_rd_data(reg_rd_data_port1),
+ .reg_rd_bytes(reg_rd_bytes_port1)
+);
+
+
+processing_system7_bfm_v2_0_5_ssw_hp ssw(
+ .sw_clk(sw_clk),
+ .rstn(rstn),
+ .w_qos_hp0(w_qos_hp0),
+ .r_qos_hp0(r_qos_hp0),
+ .w_qos_hp1(w_qos_hp1),
+ .r_qos_hp1(r_qos_hp1),
+ .w_qos_hp2(w_qos_hp2),
+ .r_qos_hp2(r_qos_hp2),
+ .w_qos_hp3(w_qos_hp3),
+ .r_qos_hp3(r_qos_hp3),
+   
+ .wr_ack_ddr_hp0(wr_ack_ddr_hp0),
+ .wr_data_hp0(wr_data_hp0),
+ .wr_addr_hp0(wr_addr_hp0),
+ .wr_bytes_hp0(wr_bytes_hp0),
+ .wr_dv_ddr_hp0(wr_dv_ddr_hp0),
+ .rd_req_ddr_hp0(rd_req_ddr_hp0),
+ .rd_addr_hp0(rd_addr_hp0),
+ .rd_bytes_hp0(rd_bytes_hp0),
+ .rd_data_ddr_hp0(rd_data_ddr_hp0),
+ .rd_data_ocm_hp0(rd_data_ocm_hp0),
+ .rd_dv_ddr_hp0(rd_dv_ddr_hp0),
+   
+ .wr_ack_ocm_hp0(wr_ack_ocm_hp0),
+ .wr_dv_ocm_hp0(wr_dv_ocm_hp0),
+ .rd_req_ocm_hp0(rd_req_ocm_hp0),
+ .rd_dv_ocm_hp0(rd_dv_ocm_hp0),
+   
+ .wr_ack_ddr_hp1(wr_ack_ddr_hp1),
+ .wr_data_hp1(wr_data_hp1),
+ .wr_addr_hp1(wr_addr_hp1),
+ .wr_bytes_hp1(wr_bytes_hp1),
+ .wr_dv_ddr_hp1(wr_dv_ddr_hp1),
+ .rd_req_ddr_hp1(rd_req_ddr_hp1),
+ .rd_addr_hp1(rd_addr_hp1),
+ .rd_bytes_hp1(rd_bytes_hp1),
+ .rd_data_ddr_hp1(rd_data_ddr_hp1),
+ .rd_data_ocm_hp1(rd_data_ocm_hp1),
+ .rd_dv_ddr_hp1(rd_dv_ddr_hp1),
+   
+ .wr_ack_ocm_hp1(wr_ack_ocm_hp1),
+ .wr_dv_ocm_hp1(wr_dv_ocm_hp1),
+ .rd_req_ocm_hp1(rd_req_ocm_hp1),
+ .rd_dv_ocm_hp1(rd_dv_ocm_hp1),
+   
+ .wr_ack_ddr_hp2(wr_ack_ddr_hp2),
+ .wr_data_hp2(wr_data_hp2),
+ .wr_addr_hp2(wr_addr_hp2),
+ .wr_bytes_hp2(wr_bytes_hp2),
+ .wr_dv_ddr_hp2(wr_dv_ddr_hp2),
+ .rd_req_ddr_hp2(rd_req_ddr_hp2),
+ .rd_addr_hp2(rd_addr_hp2),
+ .rd_bytes_hp2(rd_bytes_hp2),
+ .rd_data_ddr_hp2(rd_data_ddr_hp2),
+ .rd_data_ocm_hp2(rd_data_ocm_hp2),
+ .rd_dv_ddr_hp2(rd_dv_ddr_hp2),
+   
+ .wr_ack_ocm_hp2(wr_ack_ocm_hp2),
+ .wr_dv_ocm_hp2(wr_dv_ocm_hp2),
+ .rd_req_ocm_hp2(rd_req_ocm_hp2),
+ .rd_dv_ocm_hp2(rd_dv_ocm_hp2),
+   
+ .wr_ack_ddr_hp3(wr_ack_ddr_hp3),
+ .wr_data_hp3(wr_data_hp3),
+ .wr_addr_hp3(wr_addr_hp3),
+ .wr_bytes_hp3(wr_bytes_hp3),
+ .wr_dv_ddr_hp3(wr_dv_ddr_hp3),
+ .rd_req_ddr_hp3(rd_req_ddr_hp3),
+ .rd_addr_hp3(rd_addr_hp3),
+ .rd_bytes_hp3(rd_bytes_hp3),
+ .rd_data_ddr_hp3(rd_data_ddr_hp3),
+ .rd_data_ocm_hp3(rd_data_ocm_hp3),
+ .rd_dv_ddr_hp3(rd_dv_ddr_hp3),
+   
+ .wr_ack_ocm_hp3(wr_ack_ocm_hp3),
+ .wr_dv_ocm_hp3(wr_dv_ocm_hp3),
+ .rd_req_ocm_hp3(rd_req_ocm_hp3),
+ .rd_dv_ocm_hp3(rd_dv_ocm_hp3),
+   
+ .ddr_wr_ack0(ddr_wr_ack_port2),
+ .ddr_wr_dv0(ddr_wr_dv_port2),
+ .ddr_rd_req0(ddr_rd_req_port2),
+ .ddr_rd_dv0(ddr_rd_dv_port2),
+ .ddr_wr_addr0(ddr_wr_addr_port2),
+ .ddr_wr_data0(ddr_wr_data_port2),
+ .ddr_wr_bytes0(ddr_wr_bytes_port2),
+ .ddr_rd_addr0(ddr_rd_addr_port2),
+ .ddr_rd_data0(ddr_rd_data_port2),
+ .ddr_rd_bytes0(ddr_rd_bytes_port2),
+ .ddr_wr_qos0(ddr_wr_qos_port2),
+ .ddr_rd_qos0(ddr_rd_qos_port2),
+    
+ .ddr_wr_ack1(ddr_wr_ack_port3),
+ .ddr_wr_dv1(ddr_wr_dv_port3),
+ .ddr_rd_req1(ddr_rd_req_port3),
+ .ddr_rd_dv1(ddr_rd_dv_port3),
+ .ddr_wr_addr1(ddr_wr_addr_port3),
+ .ddr_wr_data1(ddr_wr_data_port3),
+ .ddr_wr_bytes1(ddr_wr_bytes_port3),
+ .ddr_rd_addr1(ddr_rd_addr_port3),
+ .ddr_rd_data1(ddr_rd_data_port3),
+ .ddr_rd_bytes1(ddr_rd_bytes_port3),
+ .ddr_wr_qos1(ddr_wr_qos_port3),
+ .ddr_rd_qos1(ddr_rd_qos_port3),
+
+ .ocm_wr_qos(ocm_wr_qos_osw1),
+ .ocm_rd_qos(ocm_rd_qos_osw1),
+ 
+ .ocm_wr_ack (ocm_wr_ack_osw1),
+ .ocm_wr_dv  (ocm_wr_dv_osw1),
+ .ocm_rd_req (ocm_rd_req_osw1),
+ .ocm_rd_dv  (ocm_rd_dv_osw1),
+ .ocm_wr_addr(ocm_wr_addr_osw1),
+ .ocm_wr_data(ocm_wr_data_osw1),
+ .ocm_wr_bytes(ocm_wr_bytes_osw1),
+ .ocm_rd_addr(ocm_rd_addr_osw1),
+ .ocm_rd_data(ocm_rd_data_osw1),
+ .ocm_rd_bytes(ocm_rd_bytes_osw1)
+
+);
+
+processing_system7_bfm_v2_0_5_arb_wr osw_wr (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(ocm_wr_qos_osw0), /// chk
+ .qos2(ocm_wr_qos_osw1), /// chk
+ .prt_dv1(ocm_wr_dv_osw0),
+ .prt_dv2(ocm_wr_dv_osw1),
+ .prt_data1(ocm_wr_data_osw0),
+ .prt_data2(ocm_wr_data_osw1),
+ .prt_addr1(ocm_wr_addr_osw0),
+ .prt_addr2(ocm_wr_addr_osw1),
+ .prt_bytes1(ocm_wr_bytes_osw0),
+ .prt_bytes2(ocm_wr_bytes_osw1),
+ .prt_ack1(ocm_wr_ack_osw0),
+ .prt_ack2(ocm_wr_ack_osw1),
+ .prt_req(ocm_wr_dv_port1),
+ .prt_qos(ocm_wr_qos_port1),
+ .prt_data(ocm_wr_data_port1),
+ .prt_addr(ocm_wr_addr_port1),
+ .prt_bytes(ocm_wr_bytes_port1),
+ .prt_ack(ocm_wr_ack_port1)
+);
+
+processing_system7_bfm_v2_0_5_arb_rd osw_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(ocm_rd_qos_osw0), // chk
+ .qos2(ocm_rd_qos_osw1), // chk
+ .prt_req1(ocm_rd_req_osw0),
+ .prt_req2(ocm_rd_req_osw1),
+ .prt_data1(ocm_rd_data_osw0),
+ .prt_data2(ocm_rd_data_osw1),
+ .prt_addr1(ocm_rd_addr_osw0),
+ .prt_addr2(ocm_rd_addr_osw1),
+ .prt_bytes1(ocm_rd_bytes_osw0),
+ .prt_bytes2(ocm_rd_bytes_osw1),
+ .prt_dv1(ocm_rd_dv_osw0),
+ .prt_dv2(ocm_rd_dv_osw1),
+ .prt_req(ocm_rd_req_port1),
+ .prt_qos(ocm_rd_qos_port1),
+ .prt_data(ocm_rd_data_port1),
+ .prt_addr(ocm_rd_addr_port1),
+ .prt_bytes(ocm_rd_bytes_port1),
+ .prt_dv(ocm_rd_dv_port1)
+);
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_gen_reset.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the
+ *               respective clocks.
+ *****************************************************************************/
+ `timescale 1ns/1ps
+module processing_system7_bfm_v2_0_5_gen_reset(
+ por_rst_n,
+ sys_rst_n,
+ rst_out_n,
+
+ m_axi_gp0_clk,
+ m_axi_gp1_clk,
+ s_axi_gp0_clk,
+ s_axi_gp1_clk,
+ s_axi_hp0_clk,
+ s_axi_hp1_clk,
+ s_axi_hp2_clk,
+ s_axi_hp3_clk,
+ s_axi_acp_clk,
+
+ m_axi_gp0_rstn,
+ m_axi_gp1_rstn,
+ s_axi_gp0_rstn,
+ s_axi_gp1_rstn,
+ s_axi_hp0_rstn,
+ s_axi_hp1_rstn,
+ s_axi_hp2_rstn,
+ s_axi_hp3_rstn,
+ s_axi_acp_rstn,
+
+ fclk_reset3_n,
+ fclk_reset2_n,
+ fclk_reset1_n,
+ fclk_reset0_n,
+
+ fpga_acp_reset_n,
+ fpga_gp_m0_reset_n,
+ fpga_gp_m1_reset_n,
+ fpga_gp_s0_reset_n,
+ fpga_gp_s1_reset_n,
+ fpga_hp_s0_reset_n,
+ fpga_hp_s1_reset_n,
+ fpga_hp_s2_reset_n,
+ fpga_hp_s3_reset_n
+
+);
+
+input por_rst_n;
+input sys_rst_n;
+input m_axi_gp0_clk;
+input m_axi_gp1_clk;
+input s_axi_gp0_clk;
+input s_axi_gp1_clk;
+input s_axi_hp0_clk;
+input s_axi_hp1_clk;
+input s_axi_hp2_clk;
+input s_axi_hp3_clk;
+input s_axi_acp_clk;
+
+output reg m_axi_gp0_rstn;
+output reg m_axi_gp1_rstn;
+output reg s_axi_gp0_rstn;
+output reg s_axi_gp1_rstn;
+output reg s_axi_hp0_rstn;
+output reg s_axi_hp1_rstn;
+output reg s_axi_hp2_rstn;
+output reg s_axi_hp3_rstn;
+output reg s_axi_acp_rstn;
+
+output rst_out_n;
+output fclk_reset3_n;
+output fclk_reset2_n;
+output fclk_reset1_n;
+output fclk_reset0_n;
+
+output fpga_acp_reset_n;
+output fpga_gp_m0_reset_n;
+output fpga_gp_m1_reset_n;
+output fpga_gp_s0_reset_n;
+output fpga_gp_s1_reset_n;
+output fpga_hp_s0_reset_n;
+output fpga_hp_s1_reset_n;
+output fpga_hp_s2_reset_n;
+output fpga_hp_s3_reset_n;
+
+reg [31:0] fabric_rst_n;
+
+reg r_m_axi_gp0_rstn;
+reg r_m_axi_gp1_rstn;
+reg r_s_axi_gp0_rstn;
+reg r_s_axi_gp1_rstn;
+reg r_s_axi_hp0_rstn;
+reg r_s_axi_hp1_rstn;
+reg r_s_axi_hp2_rstn;
+reg r_s_axi_hp3_rstn;
+reg r_s_axi_acp_rstn;
+
+assign rst_out_n = por_rst_n & sys_rst_n;
+
+assign fclk_reset0_n = !fabric_rst_n[0];
+assign fclk_reset1_n = !fabric_rst_n[1];
+assign fclk_reset2_n = !fabric_rst_n[2];
+assign fclk_reset3_n = !fabric_rst_n[3];
+
+assign fpga_acp_reset_n = !fabric_rst_n[24];
+
+assign fpga_hp_s3_reset_n = !fabric_rst_n[23];
+assign fpga_hp_s2_reset_n = !fabric_rst_n[22];
+assign fpga_hp_s1_reset_n = !fabric_rst_n[21];
+assign fpga_hp_s0_reset_n = !fabric_rst_n[20];
+
+assign fpga_gp_s1_reset_n = !fabric_rst_n[17];
+assign fpga_gp_s0_reset_n = !fabric_rst_n[16];
+assign fpga_gp_m1_reset_n = !fabric_rst_n[13];
+assign fpga_gp_m0_reset_n = !fabric_rst_n[12];
+
+task fpga_soft_reset;
+input[31:0] reset_ctrl;
+ begin 
+  fabric_rst_n[0] = reset_ctrl[0];
+  fabric_rst_n[1] = reset_ctrl[1];
+  fabric_rst_n[2] = reset_ctrl[2];
+  fabric_rst_n[3] = reset_ctrl[3];
+  
+  fabric_rst_n[12] = reset_ctrl[12];
+  fabric_rst_n[13] = reset_ctrl[13];
+  fabric_rst_n[16] = reset_ctrl[16];
+  fabric_rst_n[17] = reset_ctrl[17];
+  
+  fabric_rst_n[20] = reset_ctrl[20];
+  fabric_rst_n[21] = reset_ctrl[21];
+  fabric_rst_n[22] = reset_ctrl[22];
+  fabric_rst_n[23] = reset_ctrl[23];
+  
+  fabric_rst_n[24] = reset_ctrl[24];
+ end
+endtask
+
+always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32\'h01f3_300f;
+
+always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      m_axi_gp0_rstn = 1\'b0;
+\telse
+      m_axi_gp0_rstn = 1\'b1;
+  end
+
+always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      m_axi_gp1_rstn = 1\'b0;
+\telse
+      m_axi_gp1_rstn = 1\'b1;
+  end
+
+always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_gp0_rstn = 1\'b0;
+\telse
+      s_axi_gp0_rstn = 1\'b1;
+  end
+
+always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_gp1_rstn = 1\'b0;
+\telse
+      s_axi_gp1_rstn = 1\'b1;
+  end
+
+always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_hp0_rstn = 1\'b0;
+\telse
+      s_axi_hp0_rstn = 1\'b1;
+  end
+
+always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_hp1_rstn = 1\'b0;
+\telse
+      s_axi_hp1_rstn = 1\'b1;
+  end
+
+always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_hp2_rstn = 1\'b0;
+\telse
+      s_axi_hp2_rstn = 1\'b1;
+  end
+
+always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_hp3_rstn = 1\'b0;
+\telse
+      s_axi_hp3_rstn = 1\'b1;
+  end
+
+always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_acp_rstn = 1\'b0;
+\telse
+      s_axi_acp_rstn = 1\'b1;
+  end
+
+
+always@(*) begin
+  if ((por_rst_n!= 1\'b0) && (por_rst_n!= 1\'b1) && (sys_rst_n !=  1\'b0) && (sys_rst_n != 1\'b1)) begin
+     $display("" Error:processing_system7_bfm_v2_0_5_gen_reset.  PS_PORB and PS_SRSTB must be driven to known state"");
+     $finish();
+  end
+end
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_gen_clock.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that generates FCLK clocks and internal clock for Zynq BFM. 
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_gen_clock(
+ ps_clk, 
+ sw_clk,
+ 
+ fclk_clk3,
+ fclk_clk2,
+ fclk_clk1,
+ fclk_clk0
+);
+
+input ps_clk;
+output sw_clk;
+
+output fclk_clk3;
+output fclk_clk2;
+output fclk_clk1;
+output fclk_clk0;
+
+parameter freq_clk3 = 50;
+parameter freq_clk2 = 50;
+parameter freq_clk1 = 50;
+parameter freq_clk0 = 50;
+
+reg clk0 = 1\'b0;
+reg clk1 = 1\'b0;
+reg clk2 = 1\'b0;
+reg clk3 = 1\'b0;
+reg sw_clk = 1\'b0;
+
+assign fclk_clk0 = clk0;
+assign fclk_clk1 = clk1;
+assign fclk_clk2 = clk2;
+assign fclk_clk3 = clk3;
+ 
+real clk3_p = (1000.00/freq_clk3)/2;
+real clk2_p = (1000.00/freq_clk2)/2;
+real clk1_p = (1000.00/freq_clk1)/2;
+real clk0_p = (1000.00/freq_clk0)/2;
+
+always #(clk3_p) clk3 = !clk3;
+always #(clk2_p) clk2 = !clk2;
+always #(clk1_p) clk1 = !clk1;
+always #(clk0_p) clk0 = !clk0;
+
+always #(0.5) sw_clk = !sw_clk;
+
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_ddrc.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that acts as controller for sparse memory (DDR).
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_ddrc(
+ rstn,
+ sw_clk,
+
+/* Goes to port 0 of DDR */
+ ddr_wr_ack_port0,
+ ddr_wr_dv_port0,
+ ddr_rd_req_port0,
+ ddr_rd_dv_port0,
+ ddr_wr_addr_port0,
+ ddr_wr_data_port0,
+ ddr_wr_bytes_port0,
+ ddr_rd_addr_port0,
+ ddr_rd_data_port0,
+ ddr_rd_bytes_port0,
+ ddr_wr_qos_port0,
+ ddr_rd_qos_port0,
+
+
+/* Goes to port 1 of DDR */
+ ddr_wr_ack_port1,
+ ddr_wr_dv_port1,
+ ddr_rd_req_port1,
+ ddr_rd_dv_port1,
+ ddr_wr_addr_port1,
+ ddr_wr_data_port1,
+ ddr_wr_bytes_port1,
+ ddr_rd_addr_port1,
+ ddr_rd_data_port1,
+ ddr_rd_bytes_port1,
+ ddr_wr_qos_port1,
+ ddr_rd_qos_port1,
+
+/* Goes to port2 of DDR */
+ ddr_wr_ack_port2,
+ ddr_wr_dv_port2,
+ ddr_rd_req_port2,
+ ddr_rd_dv_port2,
+ ddr_wr_addr_port2,
+ ddr_wr_data_port2,
+ ddr_wr_bytes_port2,
+ ddr_rd_addr_port2,
+ ddr_rd_data_port2,
+ ddr_rd_bytes_port2,
+ ddr_wr_qos_port2,
+ ddr_rd_qos_port2,
+
+/* Goes to port3 of DDR */
+ ddr_wr_ack_port3,
+ ddr_wr_dv_port3,
+ ddr_rd_req_port3,
+ ddr_rd_dv_port3,
+ ddr_wr_addr_port3,
+ ddr_wr_data_port3,
+ ddr_wr_bytes_port3,
+ ddr_rd_addr_port3,
+ ddr_rd_data_port3,
+ ddr_rd_bytes_port3,
+ ddr_wr_qos_port3,
+ ddr_rd_qos_port3 
+
+);
+
+`include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+input rstn;
+input sw_clk;
+
+output ddr_wr_ack_port0;
+input ddr_wr_dv_port0;
+input ddr_rd_req_port0;
+output ddr_rd_dv_port0;
+input[addr_width-1:0] ddr_wr_addr_port0;
+input[max_burst_bits-1:0] ddr_wr_data_port0;
+input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
+input[addr_width-1:0] ddr_rd_addr_port0;
+output[max_burst_bits-1:0] ddr_rd_data_port0;
+input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
+input [axi_qos_width-1:0] ddr_wr_qos_port0;
+input [axi_qos_width-1:0] ddr_rd_qos_port0;
+
+output ddr_wr_ack_port1;
+input ddr_wr_dv_port1;
+input ddr_rd_req_port1;
+output ddr_rd_dv_port1;
+input[addr_width-1:0] ddr_wr_addr_port1;
+input[max_burst_bits-1:0] ddr_wr_data_port1;
+input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
+input[addr_width-1:0] ddr_rd_addr_port1;
+output[max_burst_bits-1:0] ddr_rd_data_port1;
+input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
+input[axi_qos_width-1:0] ddr_wr_qos_port1;
+input[axi_qos_width-1:0] ddr_rd_qos_port1;
+
+output ddr_wr_ack_port2;
+input ddr_wr_dv_port2;
+input ddr_rd_req_port2;
+output ddr_rd_dv_port2;
+input[addr_width-1:0] ddr_wr_addr_port2;
+input[max_burst_bits-1:0] ddr_wr_data_port2;
+input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
+input[addr_width-1:0] ddr_rd_addr_port2;
+output[max_burst_bits-1:0] ddr_rd_data_port2;
+input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
+input[axi_qos_width-1:0] ddr_wr_qos_port2;
+input[axi_qos_width-1:0] ddr_rd_qos_port2;
+
+output ddr_wr_ack_port3;
+input ddr_wr_dv_port3;
+input ddr_rd_req_port3;
+output ddr_rd_dv_port3;
+input[addr_width-1:0] ddr_wr_addr_port3;
+input[max_burst_bits-1:0] ddr_wr_data_port3;
+input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
+input[addr_width-1:0] ddr_rd_addr_port3;
+output[max_burst_bits-1:0] ddr_rd_data_port3;
+input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
+input[axi_qos_width-1:0] ddr_wr_qos_port3;
+input[axi_qos_width-1:0] ddr_rd_qos_port3;
+
+wire [axi_qos_width-1:0] wr_qos;
+wire wr_req;
+wire [max_burst_bits-1:0] wr_data;
+wire [addr_width-1:0] wr_addr;
+wire [max_burst_bytes_width:0] wr_bytes;
+reg wr_ack;
+
+wire [axi_qos_width-1:0] rd_qos;
+reg [max_burst_bits-1:0] rd_data;
+wire [addr_width-1:0] rd_addr;
+wire [max_burst_bytes_width:0] rd_bytes;
+reg rd_dv;
+wire rd_req;
+
+processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(ddr_wr_qos_port0),
+ .qos2(ddr_wr_qos_port1),
+ .qos3(ddr_wr_qos_port2),
+ .qos4(ddr_wr_qos_port3),
+   
+ .prt_dv1(ddr_wr_dv_port0),
+ .prt_dv2(ddr_wr_dv_port1),
+ .prt_dv3(ddr_wr_dv_port2),
+ .prt_dv4(ddr_wr_dv_port3),
+   
+ .prt_data1(ddr_wr_data_port0),
+ .prt_data2(ddr_wr_data_port1),
+ .prt_data3(ddr_wr_data_port2),
+ .prt_data4(ddr_wr_data_port3),
+   
+ .prt_addr1(ddr_wr_addr_port0),
+ .prt_addr2(ddr_wr_addr_port1),
+ .prt_addr3(ddr_wr_addr_port2),
+ .prt_addr4(ddr_wr_addr_port3),
+   
+ .prt_bytes1(ddr_wr_bytes_port0),
+ .prt_bytes2(ddr_wr_bytes_port1),
+ .prt_bytes3(ddr_wr_bytes_port2),
+ .prt_bytes4(ddr_wr_bytes_port3),
+   
+ .prt_ack1(ddr_wr_ack_port0),
+ .prt_ack2(ddr_wr_ack_port1),
+ .prt_ack3(ddr_wr_ack_port2),
+ .prt_ack4(ddr_wr_ack_port3),
+   
+ .prt_qos(wr_qos),
+ .prt_req(wr_req),
+ .prt_data(wr_data),
+ .prt_addr(wr_addr),
+ .prt_bytes(wr_bytes),
+ .prt_ack(wr_ack)
+
+);
+
+processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(ddr_rd_qos_port0),
+ .qos2(ddr_rd_qos_port1),
+ .qos3(ddr_rd_qos_port2),
+ .qos4(ddr_rd_qos_port3),
+   
+ .prt_req1(ddr_rd_req_port0),
+ .prt_req2(ddr_rd_req_port1),
+ .prt_req3(ddr_rd_req_port2),
+ .prt_req4(ddr_rd_req_port3),
+   
+ .prt_data1(ddr_rd_data_port0),
+ .prt_data2(ddr_rd_data_port1),
+ .prt_data3(ddr_rd_data_port2),
+ .prt_data4(ddr_rd_data_port3),
+   
+ .prt_addr1(ddr_rd_addr_port0),
+ .prt_addr2(ddr_rd_addr_port1),
+ .prt_addr3(ddr_rd_addr_port2),
+ .prt_addr4(ddr_rd_addr_port3),
+   
+ .prt_bytes1(ddr_rd_bytes_port0),
+ .prt_bytes2(ddr_rd_bytes_port1),
+ .prt_bytes3(ddr_rd_bytes_port2),
+ .prt_bytes4(ddr_rd_bytes_port3),
+   
+ .prt_dv1(ddr_rd_dv_port0),
+ .prt_dv2(ddr_rd_dv_port1),
+ .prt_dv3(ddr_rd_dv_port2),
+ .prt_dv4(ddr_rd_dv_port3),
+   
+ .prt_qos(rd_qos),
+ .prt_req(rd_req),
+ .prt_data(rd_data),
+ .prt_addr(rd_addr),
+ .prt_bytes(rd_bytes),
+ .prt_dv(rd_dv)
+
+);
+
+processing_system7_bfm_v2_0_5_sparse_mem ddr();
+
+reg [1:0] state;
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ wr_ack <= 0; 
+ rd_dv <= 0;
+ state <= 2\'d0;
+end else begin
+ case(state) 
+ 0:begin
+     state <= 0;
+     wr_ack <= 0;
+     rd_dv <= 0;
+     if(wr_req) begin
+       ddr.write_mem(wr_data , wr_addr, wr_bytes); 
+       wr_ack <= 1;
+       state <= 1;
+     end
+     if(rd_req) begin
+       ddr.read_mem(rd_data,rd_addr, rd_bytes); 
+       rd_dv <= 1;
+       state <= 1;
+     end
+
+   end
+ 1:begin
+       wr_ack <= 0;
+       rd_dv  <= 0;
+       state <= 0;
+   end 
+
+ endcase
+end /// if
+end// always
+
+endmodule 
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_axi_slave.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Model that acts as PS AXI Slave  port interface. 
+ *               It uses AXI3 Slave  BFM
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_axi_slave (
+  S_RESETN,
+
+  S_ARREADY,
+  S_AWREADY,
+  S_BVALID,
+  S_RLAST,
+  S_RVALID,
+  S_WREADY,
+  S_BRESP,
+  S_RRESP,
+  S_RDATA,
+  S_BID,
+  S_RID,
+  S_ACLK,
+  S_ARVALID,
+  S_AWVALID,
+  S_BREADY,
+  S_RREADY,
+  S_WLAST,
+  S_WVALID,
+  S_ARBURST,
+  S_ARLOCK,
+  S_ARSIZE,
+  S_AWBURST,
+  S_AWLOCK,
+  S_AWSIZE,
+  S_ARPROT,
+  S_AWPROT,
+  S_ARADDR,
+  S_AWADDR,
+  S_WDATA,
+  S_ARCACHE,
+  S_ARLEN,
+  S_AWCACHE,
+  S_AWLEN,
+  S_WSTRB,
+  S_ARID,
+  S_AWID,
+  S_WID,
+  
+  S_AWQOS,
+  S_ARQOS,
+
+  SW_CLK,
+  WR_DATA_ACK_OCM,
+  WR_DATA_ACK_DDR,
+  WR_ADDR,
+  WR_DATA,
+  WR_BYTES,
+  WR_DATA_VALID_OCM,
+  WR_DATA_VALID_DDR,
+  WR_QOS,
+
+  RD_QOS, 
+  RD_REQ_DDR,
+  RD_REQ_OCM,
+  RD_REQ_REG,
+  RD_ADDR,
+  RD_DATA_OCM,
+  RD_DATA_DDR,
+  RD_DATA_REG,
+  RD_BYTES,
+  RD_DATA_VALID_OCM,
+  RD_DATA_VALID_DDR,
+  RD_DATA_VALID_REG
+
+);
+  parameter enable_this_port = 0;  
+  parameter slave_name = ""Slave"";
+  parameter data_bus_width = 32;
+  parameter address_bus_width = 32;
+  parameter id_bus_width = 6;
+  parameter slave_base_address = 0;
+  parameter slave_high_address = 4;
+  parameter max_outstanding_transactions = 8;
+  parameter exclusive_access_supported = 0;
+  parameter max_wr_outstanding_transactions = 8;
+  parameter max_rd_outstanding_transactions = 8;
+  
+  `include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+  /* Local parameters only for this module */
+  /* Internal counters that are used as Read/Write pointers to the fifo\'s that store all the transaction info on all channles.
+     This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
+     1-bit extra width than the no.of.bits needed to represent the outstanding transactions
+     Extra bit helps in generating the empty and full flags
+  */
+  parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1);
+  parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1);
+
+  /* RESP data */
+  parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; 
+  parameter rsp_lsb = 0;
+  parameter rsp_msb = axi_rsp_width-1;
+  parameter rsp_id_lsb = rsp_msb + 1;  
+  parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;  
+
+  input  S_RESETN;
+
+  output  S_ARREADY;
+  output  S_AWREADY;
+  output  S_BVALID;
+  output  S_RLAST;
+  output  S_RVALID;
+  output  S_WREADY;
+  output  [axi_rsp_width-1:0] S_BRESP;
+  output  [axi_rsp_width-1:0] S_RRESP;
+  output  [data_bus_width-1:0] S_RDATA;
+  output  [id_bus_width-1:0] S_BID;
+  output  [id_bus_width-1:0] S_RID;
+  input S_ACLK;
+  input S_ARVALID;
+  input S_AWVALID;
+  input S_BREADY;
+  input S_RREADY;
+  input S_WLAST;
+  input S_WVALID;
+  input [axi_brst_type_width-1:0] S_ARBURST;
+  input [axi_lock_width-1:0] S_ARLOCK;
+  input [axi_size_width-1:0] S_ARSIZE;
+  input [axi_brst_type_width-1:0] S_AWBURST;
+  input [axi_lock_width-1:0] S_AWLOCK;
+  input [axi_size_width-1:0] S_AWSIZE;
+  input [axi_prot_width-1:0] S_ARPROT;
+  input [axi_prot_width-1:0] S_AWPROT;
+  input [address_bus_width-1:0] S_ARADDR;
+  input [address_bus_width-1:0] S_AWADDR;
+  input [data_bus_width-1:0] S_WDATA;
+  input [axi_cache_width-1:0] S_ARCACHE;
+  input [axi_cache_width-1:0] S_ARLEN;
+  
+  input [axi_qos_width-1:0] S_ARQOS;
+ 
+  input [axi_cache_width-1:0] S_AWCACHE;
+  input [axi_len_width-1:0] S_AWLEN;
+
+  input [axi_qos_width-1:0] S_AWQOS;
+  input [(data_bus_width/8)-1:0] S_WSTRB;
+  input [id_bus_width-1:0] S_ARID;
+  input [id_bus_width-1:0] S_AWID;
+  input [id_bus_width-1:0] S_WID;
+
+  input SW_CLK;
+  input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
+  output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
+  output reg [max_burst_bits-1:0] WR_DATA;
+  output reg [addr_width-1:0] WR_ADDR;
+  output reg [max_burst_bytes_width:0] WR_BYTES;
+  output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG;
+  output reg [addr_width-1:0] RD_ADDR;
+  input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG;
+  output reg[max_burst_bytes_width:0] RD_BYTES;
+  input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG;
+  output reg [axi_qos_width-1:0] WR_QOS, RD_QOS;
+  wire net_ARVALID;
+  wire net_AWVALID;
+  wire net_WVALID;
+
+  real s_aclk_period;
+
+  cdn_axi3_slave_bfm #(slave_name,
+                       data_bus_width,
+                       address_bus_width,
+                       id_bus_width, 
+                       slave_base_address,
+                       (slave_high_address- slave_base_address),
+                       max_outstanding_transactions,
+                       0, ///MEMORY_MODEL_MODE,
+                       exclusive_access_supported)
+  slave   (.ACLK    (S_ACLK),
+           .ARESETn (S_RESETN), /// confirm this
+           // Write Address Channel
+           .AWID    (S_AWID),
+           .AWADDR  (S_AWADDR),
+           .AWLEN   (S_AWLEN),
+           .AWSIZE  (S_AWSIZE),
+           .AWBURST (S_AWBURST),
+           .AWLOCK  (S_AWLOCK),
+           .AWCACHE (S_AWCACHE),
+           .AWPROT  (S_AWPROT),
+           .AWVALID (net_AWVALID),
+           .AWREADY (S_AWREADY),
+           // Write Data Channel Signals.
+           .WID    (S_WID),
+           .WDATA  (S_WDATA),
+           .WSTRB  (S_WSTRB), 
+           .WLAST  (S_WLAST), 
+           .WVALID (net_WVALID),
+           .WREADY (S_WREADY),
+           // Write Response Channel Signals.
+           .BID    (S_BID),
+           .BRESP  (S_BRESP),
+           .BVALID (S_BVALID),
+           .BREADY (S_BREADY),
+           // Read Address Channel Signals.
+           .ARID    (S_ARID),
+           .ARADDR  (S_ARADDR),
+           .ARLEN   (S_ARLEN),
+           .ARSIZE  (S_ARSIZE),
+           .ARBURST (S_ARBURST),
+           .ARLOCK  (S_ARLOCK),
+           .ARCACHE (S_ARCACHE),
+           .ARPROT  (S_ARPROT),
+           .ARVALID (net_ARVALID),
+           .ARREADY (S_ARREADY),
+           // Read Data Channel Signals.
+           .RID    (S_RID),
+           .RDATA  (S_RDATA),
+           .RRESP  (S_RRESP),
+           .RLAST  (S_RLAST),
+           .RVALID (S_RVALID),
+           .RREADY (S_RREADY));
+
+  /* Latency type and Debug/Error Control */
+  reg[1:0] latency_type = RANDOM_CASE;
+  reg DEBUG_INFO = 1; 
+  reg STOP_ON_ERROR = 1\'b1; 
+
+  /* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */
+  reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1];
+  reg [int_wr_cntr_width-1:0]    wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
+  wire wr_fifo_empty;
+
+  /* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/
+  reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0;
+  real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received
+  reg  awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received 
+
+  /* Address Write Channel handshake*/
+  reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid
+
+  /* various FIFOs for storing the ADDR channel info */
+  reg [axi_size_width-1:0]  awsize [0:max_wr_outstanding_transactions-1];
+  reg [axi_prot_width-1:0]  awprot [0:max_wr_outstanding_transactions-1];
+  reg [axi_lock_width-1:0]  awlock [0:max_wr_outstanding_transactions-1];
+  reg [axi_cache_width-1:0]  awcache [0:max_wr_outstanding_transactions-1];
+  reg [axi_brst_type_width-1:0]  awbrst [0:max_wr_outstanding_transactions-1];
+  reg [axi_len_width-1:0]  awlen [0:max_wr_outstanding_transactions-1];
+  reg aw_flag [0:max_wr_outstanding_transactions-1];
+  reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1];
+  reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1];
+  reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1];
+  wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
+
+  /* internal fifos to store burst write data, ID & strobes*/
+  reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1];
+  reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
+  reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag  to indicate WLAST received
+  wire wd_fifo_full;
+
+  /* Write Data Channel and Write Response handshake signals*/
+  reg [int_wr_cntr_width-1:0] wd_cnt = 0;
+  reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
+  reg [addr_width-1:0] aligned_wr_addr;
+  reg [max_burst_bytes_width:0] valid_data_bytes;
+  reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0;
+  reg [axi_rsp_width-1:0] bresp;
+  reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response
+  reg enable_write_bresp;
+  reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0;
+  integer wr_latency_count;
+  reg  wr_delayed;
+  wire bresp_fifo_empty;
+
+  /* states for managing read/write to WR_FIFO */ 
+  parameter SEND_DATA = 0,  WAIT_ACK = 1;
+  reg state;
+
+  /* Qos*/
+  reg [axi_qos_width-1:0] ar_qos, aw_qos;
+
+  initial begin
+   if(DEBUG_INFO) begin
+    if(enable_this_port)
+     $display(""[%0d] : %0s : %0s : Port is ENABLED."",$time, DISP_INFO, slave_name);
+    else
+     $display(""[%0d] : %0s : %0s : Port is DISABLED."",$time, DISP_INFO, slave_name);
+   end
+  end
+
+  initial slave.set_disable_reset_value_checks(1); 
+  initial begin
+     repe'b'at(2) @(posedge S_ACLK);
+     if(!enable_this_port) begin
+        slave.set_channel_level_info(0);
+        slave.set_function_level_info(0);
+     end 
+     slave.RESPONSE_TIMEOUT = 0;
+  end
+  /*--------------------------------------------------------------------------------*/
+
+  /* Set Latency type to be used */
+  task set_latency_type;
+    input[1:0] lat;
+  begin
+   if(enable_this_port) 
+    latency_type = lat;
+   else begin
+    if(DEBUG_INFO)
+     $display(""[%0d] : %0s : %0s : Port is disabled. \'Latency Profile\' will not be set..."",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  /* Set ARQoS to be used */
+  task set_arqos;
+    input[axi_qos_width-1:0] qos;
+  begin
+   if(enable_this_port) 
+    ar_qos = qos;
+   else begin
+    if(DEBUG_INFO)
+     $display(""[%0d] : %0s : %0s : Port is disabled. \'ARQOS\' will not be set..."",$time, DISP_WARN, slave_name);
+   end
+
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  /* Set AWQoS to be used */
+  task set_awqos;
+    input[axi_qos_width-1:0] qos;
+  begin
+   if(enable_this_port) 
+    aw_qos = qos;
+   else begin
+    if(DEBUG_INFO)
+     $display(""[%0d] : %0s : %0s : Port is disabled. \'AWQOS\' will not be set..."",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+  /* get the wr latency number */
+  function [31:0] get_wr_lat_number;
+  input dummy;
+  reg[1:0] temp;
+  begin 
+   case(latency_type)
+    BEST_CASE   : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min;            
+    AVG_CASE    : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg;            
+    WORST_CASE  : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max;            
+    default     : begin  // RANDOM_CASE
+                   temp = $random;
+                   case(temp) 
+                    2\'b00   : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min); 
+                    2\'b01   : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg); 
+                    default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max); 
+                   endcase        
+                  end
+   endcase
+  end
+  endfunction
+ /*--------------------------------------------------------------------------------*/
+
+  /* get the rd latency number */
+  function [31:0] get_rd_lat_number;
+  input dummy;
+  reg[1:0] temp;
+  begin 
+   case(latency_type)
+    BEST_CASE   : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min;            
+    AVG_CASE    : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg;            
+    WORST_CASE  : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max;            
+    default     : begin  // RANDOM_CASE
+                   temp = $random;
+                   case(temp) 
+                    2\'b00   : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min); 
+                    2\'b01   : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg); 
+                    default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max); 
+                   endcase        
+                  end
+   endcase
+  end
+  endfunction
+ /*--------------------------------------------------------------------------------*/
+
+  /* Store the Clock cycle time period */
+  always@(S_RESETN)
+  begin
+   if(S_RESETN) begin
+    @(posedge S_ACLK);
+    s_aclk_period = $time;
+    @(posedge S_ACLK);
+    s_aclk_period = $time - s_aclk_period;
+   end
+  end
+ /*--------------------------------------------------------------------------------*/
+
+ /* Check for any WRITE/READs when this port is disabled */
+ always@(S_AWVALID or S_WVALID or S_ARVALID)
+ begin
+  if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
+    $display(""[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\
+Simulation will halt .."",$time, DISP_ERR, slave_name);
+    $stop;
+  end
+ end
+
+ /*--------------------------------------------------------------------------------*/
+
+ 
+  assign net_ARVALID = enable_this_port ? S_ARVALID : 1\'b0;
+  assign net_AWVALID = enable_this_port ? S_AWVALID : 1\'b0;
+  assign net_WVALID  = enable_this_port ? S_WVALID : 1\'b0;
+
+  assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1\'b1: 1\'b0;
+  assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1\'b1 :1\'b0; /// complete this
+  assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1\'b1 :1\'b0; /// complete this
+  assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1\'b1:1\'b0;
+ 
+
+  /* Store the awvalid receive time --- necessary for calculating the bresp latency */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)
+   aw_time_cnt = 0;
+  else begin
+  if(net_AWVALID && S_AWREADY) begin
+     awvalid_receive_time[aw_time_cnt] = $time;
+     awvalid_flag[aw_time_cnt] = 1\'b1;
+     aw_time_cnt = aw_time_cnt + 1;
+     if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0; 
+   end
+  end // else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  always@(posedge S_ACLK)
+  begin
+  if(net_AWVALID && S_AWREADY) begin
+    if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos; 
+    else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS; 
+  end
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  always@(aw_fifo_full)
+  begin
+  if(aw_fifo_full && DEBUG_INFO) 
+    $display(""[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed."",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions);
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  /* Address Write Channel handshake*/
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+    aw_cnt = 0;
+  end else begin
+    if(!aw_fifo_full) begin 
+        slave.RECEIVE_WRITE_ADDRESS(0,
+                                    id_invalid,
+                                    awaddr[aw_cnt[int_wr_cntr_width-2:0]],
+                                    awlen[aw_cnt[int_wr_cntr_width-2:0]],
+                                    awsize[aw_cnt[int_wr_cntr_width-2:0]],
+                                    awbrst[aw_cnt[int_wr_cntr_width-2:0]],
+                                    awlock[aw_cnt[int_wr_cntr_width-2:0]],
+                                    awcache[aw_cnt[int_wr_cntr_width-2:0]],
+                                    awprot[aw_cnt[int_wr_cntr_width-2:0]],
+                                    awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID.
+        aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1;
+        aw_cnt   = aw_cnt + 1;
+        if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
+          aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1];
+          aw_cnt[int_wr_cntr_width-2:0] = 0;
+        end
+    end // if (!aw_fifo_full)
+  end /// if else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  
+  /* Write Data Channel Handshake */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+   wd_cnt = 0;
+  end else begin
+    if(!wd_fifo_full && S_WVALID) begin
+        slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID,
+                                            burst_data[wd_cnt[int_wr_cntr_width-2:0]],
+                                            burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]);
+        wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1\'b1;
+        wd_cnt   = wd_cnt + 1;
+        if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
+          wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1];
+          wd_cnt[int_wr_cntr_width-2:0] = 0;
+        end
+    end /// if
+  end /// else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+
+  /* Align the wrap data for write transaction */
+  task automatic get_wrap_aligned_wr_data;
+  output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
+  output [addr_width-1:0] start_addr; /// aligned start address
+  input  [addr_width-1:0] addr;
+  input  [(data_bus_width*axi_burst_len)-1:0] b_data;
+  input  [max_burst_bytes_width:0] v_bytes;
+  reg    [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
+  integer wrp_bytes;
+  integer i;
+  begin
+    start_addr = (addr/v_bytes) * v_bytes;
+    wrp_bytes = addr - start_addr;
+    wrp_data = b_data;
+    temp_data = 0;
+    wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
+    while(wrp_bytes > 0) begin /// get the data that is wrapped
+      temp_data = temp_data << 8;
+      temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
+      wrp_data = wrp_data << 8;
+      wrp_bytes = wrp_bytes - 1;
+    end
+    wrp_bytes = addr - start_addr;
+    wrp_data = b_data << (wrp_bytes*8);
+    
+    aligned_data = (temp_data | wrp_data);
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+   
+  /* Calculate the Response for each read/write transaction */
+  function [axi_rsp_width-1:0] calculate_resp;
+  input rd_wr; // indicates Read(1) or Write(0) transaction 
+  input [addr_width-1:0] awaddr; 
+  input [axi_prot_width-1:0] awprot;
+  reg [axi_rsp_width-1:0] rsp;
+  begin
+    rsp = AXI_OK;
+    /* Address Decode */
+    if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
+     rsp = AXI_SLV_ERR; //slave error
+     $display(""[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) "",$time, DISP_ERR, slave_name, awaddr);
+    end
+    if(!rd_wr && decode_address(awaddr) === REG_MEM) begin
+     rsp = AXI_SLV_ERR; //slave error
+     $display(""[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported "",$time, DISP_ERR, slave_name, awaddr);
+    end
+    if(secure_access_enabled && awprot[1])
+     rsp = AXI_DEC_ERR; // decode error
+    calculate_resp = rsp;
+  end
+  endfunction
+  /*--------------------------------------------------------------------------------*/
+
+  /* Store the Write response for each write transaction */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+   wr_bresp_cnt = 0;
+   wr_fifo_wr_ptr = 0;
+  end else begin
+   enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]];
+   /* calculate bresp only when AWVALID && WLAST is received */
+   if(enable_write_bresp) begin
+     aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]    = 0;
+     wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
+  
+     bresp = calculate_resp(1\'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
+     fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp};
+     /* Fill WR data FIFO */
+     if(bresp === AXI_OK) begin
+       if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data
+         get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]);      /// gives wrapped start address
+       end else begin
+         aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]]; 
+         aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ;
+       end
+       valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]];
+     end else 
+       valid_data_bytes = 0;  
+
+     wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes};
+     wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; 
+     wr_bresp_cnt = wr_bresp_cnt+1;
+     if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
+       wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1];
+       wr_bresp_cnt[int_wr_cntr_width-2:0] = 0;
+     end
+   end
+  end // else
+  end // always
+  /*--------------------------------------------------------------------------------*/
+
+  /* Send Write Response Channel handshake */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+   rd_bresp_cnt = 0;
+   wr_latency_count = get_wr_lat_number(1);
+   wr_delayed = 0;
+   bresp_time_cnt = 0; 
+  end else begin
+   wr_delayed = 1\'b0;
+   if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
+     wr_delayed = 1;
+   if(!bresp_fifo_empty && wr_delayed) begin
+     slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb],  // ID
+                               fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb]   // Response
+                              );
+     wr_delayed = 0;
+     awvalid_flag[bresp_time_cnt] = 1\'b0;
+     bresp_time_cnt = bresp_time_cnt+1;
+     rd_bresp_cnt = rd_bresp_cnt + 1;
+     if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
+       rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1];
+       rd_bresp_cnt[int_wr_cntr_width-2:0] = 0;
+     end
+     if(bresp_time_cnt === max_wr_outstanding_transactions) begin
+       bresp_time_cnt = 0; 
+     end
+     wr_latency_count = get_wr_lat_number(1);
+   end 
+  end // else
+  end//always
+  /*--------------------------------------------------------------------------------*/
+
+  /* Reading from the wr_fifo */
+  always@(negedge S_RESETN or posedge SW_CLK) begin
+  if(!S_RESETN) begin 
+   WR_DATA_VALID_DDR = 1\'b0;
+   WR_DATA_VALID_OCM = 1\'b0;
+   wr_fifo_rd_ptr = 0;
+   state = SEND_DATA;
+   WR_QOS = 0;
+  end else begin
+   case(state)
+   SEND_DATA :begin
+      state = SEND_DATA;
+      WR_DATA_VALID_OCM = 0;
+      WR_DATA_VALID_DDR = 0;
+      if(!wr_fifo_empty) begin
+        WR_DATA  = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb];
+        WR_ADDR  = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb];
+        WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
+        WR_QOS   = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb];
+        state = WAIT_ACK;
+        case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]))
+         OCM_MEM : WR_DATA_VALID_OCM = 1;
+         DDR_MEM : WR_DATA_VALID_DDR = 1;
+         default : state = SEND_DATA;
+        endcase
+        wr_fifo_rd_ptr = wr_fifo_rd_ptr+1;
+      end
+      end
+   WAIT_ACK :begin
+      state = WAIT_ACK;
+      if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin 
+        WR_DATA_VALID_OCM = 1\'b0;
+        WR_DATA_VALID_DDR = 1\'b0;
+        state = SEND_DATA;
+      end
+      end
+   endcase
+  end
+  end
+  /*--------------------------------------------------------------------------------*/
+/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
+
+/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
+
+  /* READ CHANNELS */
+  /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
+  reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
+  real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
+  reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
+  reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info
+
+  /* various FIFOs for storing the ADDR channel info */
+  reg [axi_size_width-1:0]  arsize [0:max_rd_outstanding_transactions-1];
+  reg [axi_prot_width-1:0]  arprot [0:max_rd_outstanding_transactions-1];
+  reg [axi_brst_type_width-1:0]  arbrst [0:max_rd_outstanding_transactions-1];
+  reg [axi_len_width-1:0]  arlen [0:max_rd_outstanding_transactions-1];
+  reg [axi_cache_width-1:0]  arcache [0:max_rd_outstanding_transactions-1];
+  reg [axi_lock_width-1:0]  arlock [0:max_rd_outstanding_transactions-1];
+  reg ar_flag [0:max_rd_outstanding_transactions-1];
+  reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1];
+  reg [id_bus_width-1:0]  arid [0:max_rd_outstanding_transactions-1];
+  reg [axi_qos_width-1:0]  arqos [0:max_rd_outstanding_transactions-1];
+  wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
+
+  reg [int_rd_cntr_width-1:0] rd_cnt = 0;
+  reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0;
+  reg [axi_rsp_width-1:0] rresp;
+  reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response
+
+  /* Send Read Response  & Data Channel handshake */
+  integer rd_latency_count;
+  reg  rd_delayed;
+
+  reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data ..
+  reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
+  wire read_fifo_full; 
+ 
+  assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1\'b1: 1\'b0;
+  assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1\'b1: 1\'b0;
+  assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1\'b1 :1\'b0; 
+
+  /* Store the arvalid receive time --- necessary for calculating the bresp latency */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)
+   ar_time_cnt = 0;
+  else begin
+  if(net_ARVALID && S_ARREADY) begin
+     arvalid_receive_time[ar_time_cnt] = $time;
+     arvalid_flag[ar_time_cnt] = 1\'b1;
+     ar_time_cnt = ar_time_cnt + 1;
+     if(ar_time_cnt === max_rd_outstanding_transactions)
+       ar_time_cnt = 0; 
+   end 
+  end // else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  always@(posedge S_ACLK)
+  begin
+  if(net_ARVALID && S_ARREADY) begin
+    if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos; 
+    else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS; 
+  end
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  always@(ar_fifo_full)
+  begin
+  if(ar_fifo_full && DEBUG_INFO) 
+    $display(""[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed."",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions);
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  /* Address Read  Channel handshake*/
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+    ar_cnt = 0;
+  end else begin
+    if(!ar_fifo_full) begin
+        slave.RECEIVE_READ_ADDRESS(0,
+                                   id_invalid,
+                                   araddr[ar_cnt[int_rd_cntr_width-2:0]],
+                                   arlen[ar_cnt[int_rd_cntr_width-2:0]],
+                                   arsize[ar_cnt[int_rd_cntr_width-2:0]],
+                                   arbrst[ar_cnt[int_rd_cntr_width-2:0]],
+                                   arlock[ar_cnt[int_rd_cntr_width-2:0]],
+                                   arcache[ar_cnt[int_rd_cntr_width-2:0]],
+                                   arprot[ar_cnt[int_rd_cntr_width-2:0]],
+                                   arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID.
+        ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1\'b1;
+        ar_cnt = ar_cnt+1;
+        if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
+          ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1];
+          ar_cnt[int_rd_cntr_width-2:0] = 0;
+        end 
+    end /// if(!ar_fifo_full)
+  end /// if else
+  end /// always*/
+  /*--------------------------------------------------------------------------------*/
+
+  /* Align Wrap data for read transaction*/
+  task automatic get_wrap_aligned_rd_data;
+  output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
+  input [addr_width-1:0] addr;
+  input [(data_bus_width*axi_burst_len)-1:0] b_data;
+  input [max_burst_bytes_width:0] v_bytes;
+  reg [addr_width-1:0] start_addr;
+  reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
+  integer wrp_bytes;
+  integer i;
+  begin
+    start_addr = (addr/v_bytes) * v_bytes;
+    wrp_bytes = addr - start_addr;
+    wrp_data  = b_data;
+    temp_data = 0;
+    while(wrp_bytes > 0) begin /// get the data that is wrapped
+     temp_data = temp_data >> 8;
+     temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
+     wrp_data = wrp_data >> 8;
+     wrp_bytes = wrp_bytes - 1;
+    end
+    temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
+    wrp_bytes = addr - start_addr;
+    wrp_data = b_data >> (wrp_bytes*8);
+    
+    aligned_data = (temp_data | wrp_data);
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+   
+  parameter RD_DATA_REQ = 1\'b0, WAIT_RD_VALID = 1\'b1;
+  reg [addr_width-1:0] temp_read_address;
+  reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
+  reg rd_fifo_state; 
+  reg invalid_rd_req;
+  /* get the data from memory && also calculate the rresp*/
+  always@(negedge S_RESETN or posedge SW_CLK)
+  begin
+  if(!S_RESETN)begin
+   rd_fifo_wr_ptr = 0; 
+   wr_rresp_cnt =0;
+   rd_fifo_state = RD_DATA_REQ;
+   temp_rd_valid_bytes = 0;
+   temp_read_address = 0;
+   RD_REQ_DDR = 0;
+   RD_REQ_OCM = 0;
+   RD_REQ_REG = 0;
+   RD_QOS  = 0;
+   invalid_rd_req = 0;
+  end else begin
+   case(rd_fifo_state)
+    RD_DATA_REQ : begin
+     rd_fifo_state = RD_DATA_REQ;
+     RD_REQ_DDR = 0;
+     RD_REQ_OCM = 0;
+     RD_REQ_REG = 0;
+     RD_QOS  = 0;
+     if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin
+       ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0;
+       rresp = calculate_resp(1\'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
+       fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp};
+       temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8;
+
+       if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
+        temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
+       else 
+        temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
+       if(rresp === AXI_OK) begin 
+        case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
+          OCM_MEM : RD_REQ_OCM = 1;
+          DDR_MEM : RD_REQ_DDR = 1;
+          REG_MEM : RD_REQ_REG = 1;
+          default : invalid_rd_req = 1;
+        endcase
+       end else
+        invalid_rd_req = 1;
+        
+       RD_QOS     = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]];
+       RD_ADDR    = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
+       RD_BYTES   = temp_rd_valid_bytes;
+       rd_fifo_state = WAIT_RD_VALID;
+       wr_rresp_cnt = wr_rresp_cnt + 1;
+       if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
+         wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1];
+         wr_rresp_cnt[int_rd_cntr_width-2:0] = 0;
+       end
+     end
+    end
+    WAIT_RD_VALID : begin    
+     rd_fifo_state = WAIT_RD_VALID; 
+     if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2\'b11) begin
+       if(RD_DATA_VALID_DDR)
+         read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR;
+       else if(RD_DATA_VALID_OCM)
+         read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM;
+       else if(RD_DATA_VALID_REG)
+         read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG;
+       else
+         read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0;
+       rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
+       RD_REQ_DDR = 0;
+       RD_REQ_OCM = 0;
+       RD_REQ_REG = 0;
+       RD_QOS  = 0;
+       invalid_rd_req = 0;
+       rd_fifo_state = RD_DATA_REQ;
+     end
+    end
+   endcase
+  end /// else
+  end /// always
+
+  /*--------------------------------------------------------------------------------*/
+  reg[max_burst_bytes_width:0] rd_v_b;
+  reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data;
+  reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data;
+  reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
+
+  /* Read Data Channel handshake */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)begin
+   rd_fifo_rd_ptr = 0;
+   rd_cnt = 0;
+   rd_latency_count = get_rd_lat_number(1);
+   rd_delayed = 0;
+   rresp_time_cnt = 0;
+   rd_v_b = 0;
+  end else begin
+     if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) 
+       rd_delayed = 1;
+     if(!read_fifo_empty && rd_delayed)begin
+       rd_delayed = 0;  
+       arvalid_flag[rresp_time_cnt] = 1\'b0;
+       rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]]));
+       temp_read_data =  read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]];
+       rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
+
+       if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin
+         get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b);
+         temp_read_data = temp_wrap_data;
+       end 
+       temp_read_rsp = 0;
+       repeat(axi_burst_len) begin
+         temp_read_rsp = temp_read_rsp >> axi_rsp_width;
+         temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb];
+       end 
+       slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]],
+                                       araddr[rd_cnt[int_rd_cntr_width-2:0]],
+                                       arlen[rd_cnt[int_rd_cntr_width-2:0]],
+                                       arsize[rd_cnt[int_rd_cntr_width-2:0]],
+                                       arbrst[rd_cnt[int_rd_cntr_width-2:0]],
+                                       temp_read_data,
+                                       temp_read_rsp);
+       rd_cnt = rd_cnt + 1; 
+       rresp_time_cnt = rresp_time_cnt+1;
+       if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0;
+       if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin
+         rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1];
+         rd_cnt[int_rd_cntr_width-2:0] = 0;
+       end   
+       rd_latency_count = get_rd_lat_number(1);
+     end
+  end /// else
+  end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_axi_master.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Model that acts as PS AXI Master port interface. 
+ *               It uses AXI3 Master BFM
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_axi_master (
+    M_RESETN,
+    M_ARVALID,
+    M_AWVALID,
+    M_BREADY,
+    M_RREADY,
+    M_WLAST,
+    M_WVALID,
+    M_ARID,
+    M_AWID,
+    M_WID,
+    M_ARBURST,
+    M_ARLOCK,
+    M_ARSIZE,
+    M_AWBURST,
+    M_AWLOCK,
+    M_AWSIZE,
+    M_ARPROT,
+    M_AWPROT,
+    M_ARADDR,
+    M_AWADDR,
+    M_WDATA,
+    M_ARCACHE,
+    M_ARLEN,
+    M_AWCACHE,
+    M_AWLEN,
+    M_ARQOS,  // not connected to AXI BFM
+    M_AWQOS,  // not connected to AXI BFM
+    M_WSTRB,
+    M_ACLK,
+    M_ARREADY,
+    M_AWREADY,
+    M_BVALID,
+    M_RLAST,
+    M_RVALID,
+    M_WREADY,
+    M_BID,
+    M_RID,
+    M_BRESP,
+    M_RRESP,
+    M_RDATA
+
+);
+   parameter enable_this_port = 0;  
+   parameter master_name = ""Master"";
+   parameter data_bus_width = 32;
+   parameter address_bus_width = 32;
+   parameter id_bus_width = 6;
+   parameter max_outstanding_transactions = 8;
+   parameter exclusive_access_supported = 0;
+   parameter ID = 12\'hC00;
+   `include ""processing_system7_bfm_v2_0_5_local_params.v""
+    /* IDs for Masters 
+       // l2m1 (CPU000)
+       12\'b11_000_000_00_00    
+       12\'b11_010_000_00_00     
+       12\'b11_011_000_00_00   
+       12\'b11_100_000_00_00   
+       12\'b11_101_000_00_00   
+       12\'b11_110_000_00_00     
+       12\'b11_111_000_00_00     
+       // l2m1 (CPU001)
+       12\'b11_000_001_00_00    
+       12\'b11_010_001_00_00     
+       12\'b11_011_001_00_00    
+       12\'b11_100_001_00_00    
+       12\'b11_101_001_00_00    
+       12\'b11_110_001_00_00     
+       12\'b11_111_001_00_00    
+   */
+
+   input  M_RESETN;
+
+   output M_ARVALID;
+   output M_AWVALID;
+   output M_BREADY;
+   output M_RREADY;
+   output M_WLAST;
+   output M_WVALID;
+   output [id_bus_width-1:0] M_ARID;
+   output [id_bus_width-1:0] M_AWID;
+   output [id_bus_width-1:0] M_WID;
+   output [axi_brst_type_width-1:0] M_ARBURST;
+   output [axi_lock_width-1:0] M_ARLOCK;
+   output [axi_size_width-1:0] M_ARSIZE;
+   output [axi_brst_type_width-1:0] M_AWBURST;
+   output [axi_lock_width-1:0] M_AWLOCK;
+   output [axi_size_width-1:0] M_AWSIZE;
+   output [axi_prot_width-1:0] M_ARPROT;
+   output [axi_prot_width-1:0] M_AWPROT;
+   output [address_bus_width-1:0] M_ARADDR;
+   output [address_bus_width-1:0] M_AWADDR;
+   output [data_bus_width-1:0] M_WDATA;
+   output [axi_cache_width-1:0] M_ARCACHE;
+   output [axi_len_width-1:0] M_ARLEN;
+   output [axi_qos_width-1:0] M_ARQOS;  // not connected to AXI BFM
+   output [axi_cache_width-1:0] M_AWCACHE;
+   output [axi_len_width-1:0] M_AWLEN;
+   output [axi_qos_width-1:0] M_AWQOS;  // not connected to AXI BFM
+   output [(data_bus_width/8)-1:0] M_WSTRB;
+   input M_ACLK;
+   input M_ARREADY;
+   input M_AWREADY;
+   input M_BVALID;
+   input M_RLAST;
+   input M_RVALID;
+   input M_WREADY;
+   input [id_bus_width-1:0] M_BID;
+   input [id_bus_width-1:0] M_RID;
+   input [axi_rsp_width-1:0] M_BRESP;
+   input [axi_rsp_width-1:0] M_RRESP;
+   input [data_bus_width-1:0] M_RDATA;
+
+   wire net_RESETN;
+   wire net_RVALID;
+   wire net_BVALID;
+   reg DEBUG_INFO = 1\'b1; 
+   reg STOP_ON_ERROR = 1\'b1; 
+
+   integer use_id_no = 0;
+
+   assign M_ARQOS = \'b0;
+   assign M_AWQOS = \'b0;
+   assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1\'b0;
+   assign net_RVALID = enable_this_port ? M_RVALID : 1\'b0;
+   assign net_BVALID = enable_this_port ? M_BVALID : 1\'b0;
+
+  initial begin
+   if(DEBUG_INFO) begin
+    if(enable_this_port)
+     $display(""[%0d] : %0s : %0s : Port is ENABLED."",$time, DISP_INFO, master_name);
+    else
+     $display(""[%0d] : %0s : %0s : Port is DISABLED."",$time, DISP_INFO, master_name);
+   end
+  end
+
+   initial master.set_disable_reset_value_checks(1); 
+   initial begin
+     repeat(2) @(posedge M_ACLK);
+     if(!enable_this_port) begin
+        master.set_channel_level_info(0);
+        master.set_function_level_info(0);
+     end
+     master.RESPONSE_TIMEOUT = 0;
+   end
+
+   cdn_axi3_master_bfm #(master_name,
+                         data_bus_width,
+                         address_bus_width,
+                         id_bus_width,
+                         max_outstanding_transactions,
+                         exclusive_access_supported)
+   
+   master  (.ACLK    (M_ACLK),
+            .ARESETn (net_RESETN), /// confirm this
+            // Write Address Channel
+            .AWID    (M_AWID),
+            .AWADDR  (M_AWADDR),
+            .AWLEN   (M_AWLEN),
+            .AWSIZE  (M_AWSIZE),
+            .AWBURST (M_AWBURST),
+            .AWLOCK  (M_AWLOCK),
+            .AWCACHE (M_AWCACHE),
+            .AWPROT  (M_AWPROT),
+            .AWVALID (M_AWVALID),
+            .AWREADY (M_AWREADY),
+            // Write Data Channel Signals.
+            .WID    (M_WID),
+            .WDATA  (M_WDATA),
+            .WSTRB  (M_WSTRB), 
+            .WLAST  (M_WLAST), 
+            .WVALID (M_WVALID),
+            .WREADY (M_WREADY),
+            // Write Response Channel Signals.
+            .BID    (M_BID),
+            .BRESP  (M_BRESP),
+            .BVALID (net_BVALID),
+            .BREADY (M_BREADY),
+            // Read Address Channel Signals.
+            .ARID    (M_ARID),
+            .ARADDR  (M_ARADDR),
+            .ARLEN   (M_ARLEN),
+            .ARSIZE  (M_ARSIZE),
+            .ARBURST (M_ARBURST),
+            .ARLOCK  (M_ARLOCK),
+            .ARCACHE (M_ARCACHE),
+            .ARPROT  (M_ARPROT),
+            .ARVALID (M_ARVALID),
+            .ARREADY (M_ARREADY),
+            // Read Data Channel Signals.
+            .RID    (M_RID),
+            .RDATA  (M_RDATA),
+            .RRESP  (M_RRESP),
+            .RLAST  (M_RLAST),
+            .RVALID (net_RVALID),
+            .RREADY (M_RREADY));
+
+
+/* Call to BFM APIs */
+task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response);
+ if(enable_this_port)begin
+  if(lck !== AXI_NRML)
+   master.READ_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,response);
+  else
+   master.READ_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,response);
+ end else begin
+   $display(""[%0d] : %0s : %0s : Port is disabled. \'read_burst\' will not be executed..."",$time, DISP_ERR, master_name);
+   if(STOP_ON_ERROR) $stop;
+ end
+endtask 
+
+task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+ if(enable_this_port)begin
+  if(lck !== AXI_NRML)
+   master.WRITE_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+  else
+   master.WRITE_BURST(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+ end else begin
+   $display(""[%0d] : %0s : %0s : Port is disabled. \'write_burst\' will not be executed..."",$time, DISP_ERR, master_name);
+   if(STOP_ON_ERROR) $stop;
+ end
+endtask 
+
+task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+ if(enable_this_port)begin
+  if(lck !== AXI_NRML)
+   master.WRITE_BURST_CONCURRENT(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+  else
+   master.WRITE_BURST_CONCURRENT(ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+ end else begin
+   $display(""[%0d] : %0s : %0s : Port is disabled. \'write_burst_concurrent\' will not be executed..."",$time, DISP_ERR, master_name);
+   if(STOP_ON_ERROR) $stop;
+ end
+endtask 
+
+/* local */
+function automatic[id_bus_width-1:0] get_id;
+input dummy; 
+begin
+ case(use_id_no)
+  // l2m1 (CPU000)
+  0 : get_id = 12\'b11_000_000_00_00;   
+  1 : get_id = 12\'b11_010_000_00_00;    
+  2 : get_id = 12\'b11_011_000_00_00;  
+  3 : get_id = 12\'b11_100_000_00_00;  
+  4 : get_id = 12\'b11_101_000_00_00;  
+  5 : get_id = 12\'b11_110_000_00_00;    
+  6 : get_id = 12\'b11_111_000_00_00;    
+  // l2m1 (CPU001)
+  7 : get_id = 12\'b11_000_001_00_00;   
+  8 : get_id = 12\'b11_010_001_00_00;    
+  9 : get_id = 12\'b11_011_001_00_00;   
+ 10 : get_id = 12\'b11_100_001_00_00;   
+ 11 : get_id = 12\'b11_101_001_00_00;   
+ 12 : get_id = 12\'b11_110_001_00_00;    
+ 13 : get_id = 12\'b11_111_001_00_00;   
+ endcase
+ if(use_id_no == 13)
+  use_id_no = 0;
+ else
+  use_id_no = use_id_no+1;
+end
+endfunction
+
+/* Write data from file */
+task automatic write_from_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] wr_size;
+output [axi_rsp_width-1:0] response;
+reg [axi_rsp_width-1:0] wresp,rwrsp;
+reg [addr_width-1:0] addr;
+reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data;
+integer bytes;
+integer trnsfr_bytes;
+integer wr_fd;
+integer succ;
+integer trnsfr_lngth;
+reg concurrent; 
+
+reg [id_bus_width-1:0] wr_id;
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+begin
+if(!enable_this_port) begin
+ $display(""[%0d] : %0s : %0s : Port is disabled. \'write_from_file\' will not be executed..."",$time, DISP_ERR, master_name);
+ if(STOP_ON_ERROR) $stop;
+end else begin
+ siz =  2; 
+ burst = 1;
+ lck = 0;
+ cache = 0;
+ prot = 0;
+
+ addr = start_addr;
+ bytes = wr_size;
+ wresp = 0;
+ concurrent = 1; 
+ if(bytes > (axi_burst_len * data_bus_width/8))
+  trnsfr_bytes = (axi_burst_len * data_bus_width/8);
+ else
+  trnsfr_bytes = bytes;
+ 
+ if(bytes > (axi_burst_len * data_bus_width/8))
+  trnsfr_lngth = axi_burst_len-1;
+ else if(bytes%(data_bus_width/8) == 0)
+  trnsfr_lngth = bytes/(data_bus_width/8) - 1;
+ else 
+  trnsfr_lngth = bytes/(data_bus_width/8);
+ 
+ wr_id = ID;
+ wr_fd = $fopen(file_name,""r"");
+ 
+ while (bytes > 0) begin
+   repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction
+    wr_data = wr_data >> data_bus_width;
+    succ = $fscanf(wr_fd,""%h"",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) ..
+   end
+   if(concurrent)
+    master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
+   else
+    master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
+   bytes = bytes - trnsfr_bytes;
+   addr = addr + trnsfr_bytes;
+   if(bytes >= (axi_burst_len * data_bus_width/8) )
+    trnsfr_bytes = (axi_burst_len * data_bus_width/8); //
+   else
+    trnsfr_bytes = bytes;
+ 
+   if(bytes > (axi_burst_len * data_bus_width/8))
+    trnsfr_lngth = axi_burst_len-1;
+   else if(bytes%(data_bus_width/8) == 0)
+    trnsfr_lngth = bytes/(data_bus_width/8) - 1;
+   else 
+    trnsfr_lngth = bytes/(data_bus_width/8);
+ 
+   wresp = wresp | rwrsp;
+ end /// while 
+ response = wresp;
+end
+end
+endtask
+
+/* Read data to file */
+task automatic read_to_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] rd_size;
+output [axi_rsp_width-1:0] response;
+reg [axi_rsp_width-1:0] rresp, rrrsp;
+reg [addr_width-1:0] addr;
+integer bytes;
+integer trnsfr_lngth;
+reg [(axi_burst_len*data_bus_width)-1 :0] rd_data;
+integer rd_fd;
+reg [id_bus_width-1:0] rd_id;
+
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+begin
+if(!enable_this_port) begin
+ $display(""[%0d] : %0s : %0s : Port is disabled. \'read_to_file\' will not be executed..."",$time, DISP_ERR, master_name);
+ if(STOP_ON_ERROR) $stop;
+end else begin
+  siz =  2; 
+  burst = 1;
+  lck = 0;
+  cache = 0;
+  prot = 0;
+
+  addr = start_addr;
+  rresp = 0;
+  bytes = rd_size;
+  
+  rd_id = ID;
+  
+  if(bytes > (axi_burst_len * data_bus_width/8))
+   trnsfr_lngth = axi_burst_len-1;
+  else if(bytes%(data_bus_width/8) == 0)
+   trnsfr_lngth = bytes/(data_bus_width/8) - 1;
+  else 
+   trnsfr_lngth = bytes/(data_bus_width/8);
+ 
+  rd_fd = $fopen(file_name,""w"");
+  
+  while (bytes > 0) begin
+    master.READ_BURST(rd_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp);
+    repeat(trnsfr_lngth+1) begin
+     $fdisplayh(rd_fd,rd_data[data_bus_width-1:0]);
+     rd_data = rd_data >> data_bus_width;
+    end
+    
+    addr = addr + (trnsfr_lngth+1)*4;
+
+    if(bytes >= (axi_burst_len * data_bus_width/8) )
+     bytes = bytes - (axi_burst_len * data_bus_width/8); //
+    else
+     bytes = 0;
+ 
+    if(bytes > (axi_burst_len * data_bus_width/8))
+     trnsfr_lngth = axi_burst_len-1;
+    else if(bytes%(data_bus_width/8) == 0)
+     trnsfr_lngth = bytes/(data_bus_width/8) - 1;
+    else 
+     trnsfr_lngth = bytes/(data_bus_width/8);
+
+    rresp = rresp | rrrsp;
+  end /// while 
+  response = rresp;
+end
+end
+endtask
+
+/* Write data (used for transfer size <= 128 Bytes */
+task automatic write_data;
+input [addr_width-1:0] start_addr;
+input [max_transfer_bytes_width:0] wr_size;
+input [(max_transfer_bytes*8)-1:0] w_data;
+output [axi_rsp_width-1:0] response;
+reg [axi_rsp_width-1:0] wresp,rwrsp;
+reg [addr_width-1:0] addr;
+reg [7:0] bytes,tmp_bytes;
+integer trnsfr_bytes;
+reg [(max_transfer_bytes*8)-1:0] wr_data;
+integer trnsfr_lngth;
+reg concurrent; 
+
+reg [id_bus_width-1:0] wr_id;
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+
+integer pad_bytes;
+begin
+if(!enable_this_port) begin
+ $display(""[%0d] : %0s : %0s : Port is disabled. \'write_data\' will not be executed..."",$time, DISP_ERR, master_name);
+ if(STOP_ON_ERROR) $stop;
+end else begin
+ addr = start_addr;
+ bytes = wr_size;
+ wresp = 0;
+ wr_data = w_data;
+ concurrent = 1; 
+ siz =  2; 
+ burst = 1;
+ lck = 0;
+ cache = 0;
+ prot = 0;
+ pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
+ wr_id = ID;
+ if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address
+   trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0]; 
+   trnsfr_lngth = axi_burst_len-1;
+ end else begin 
+   trnsfr_bytes = bytes;
+   tmp_bytes   = bytes + pad_bytes;//start_addr[1:0];
+   if(tmp_bytes%(data_bus_width/8) == 0)
+     trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
+   else 
+     trnsfr_lngth = tmp_bytes/(data_bus_width/8);
+ end
+
+ while (bytes > 0) begin
+   if(concurrent)
+    master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth,  siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
+   else
+    master.WRITE_BURST(wr_id, addr, trnsfr_lngth,  siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
+   wr_data = wr_data >> (trnsfr_bytes*8);
+   bytes = bytes - trnsfr_bytes;
+   addr = addr + trnsfr_bytes;
+   if(bytes  > (axi_burst_len * data_bus_width/8)) begin
+    trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; 
+    trnsfr_lngth = axi_burst_len-1;
+   end else begin 
+     trnsfr_bytes = bytes;
+     tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
+     if(tmp_bytes%(data_bus_width/8) == 0)
+       trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
+     else 
+       trnsfr_lngth = tmp_bytes/(data_bus_width/8);
+   end
+   wresp = wresp | rwrsp;
+ end /// while 
+ response = wresp;
+end
+end
+endtask
+
+/* Read data (used for transfer size <= 128 Bytes */
+task automatic read_data;
+input [addr_width-1:0] start_addr;
+input [max_transfer_bytes_width:0] rd_size;
+output [(max_transfer_bytes*8)-1:0] r_data;
+output [axi_rsp_width-1:0] response;
+reg [axi_rsp_width-1:0] rresp,rdrsp;
+reg [addr_width-1:0] addr;
+reg [max_transfer_bytes_width:0] bytes,tmp_bytes;
+integer trnsfr_bytes;
+reg [(max_transfer_bytes*8)-1 : 0] rd_data;
+reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data;
+integer total_rcvd_bytes;
+integer trnsfr_lngth;
+integer i;
+reg [id_bus_width-1:0] rd_id;
+
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+
+integer pad_bytes;
+
+begin
+if(!enable_this_port) begin
+ $display(""[%0d] : %0s : %0s : Port is disabled. \'read_data\' will not be executed..."",$time, DISP_ERR, master_name);
+ if(STOP_ON_ERROR) $stop;
+end else begin
+ addr = start_addr;
+ bytes = rd_size;
+ rresp = 0;
+ total_rcvd_bytes = 0;
+ rd_data = 0; 
+ rd_id = ID;
+
+ siz =  2; 
+ burst = 1;
+ lck = 0;
+ cache = 0;
+ prot = 0;
+ pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
+
+ if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address
+   trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; 
+   trnsfr_lngth = axi_burst_len-1;
+ end else begin 
+   trnsfr_bytes = bytes;
+   tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
+   if(tmp_bytes%(data_bus_width/8) == 0)
+     trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
+   else 
+     trnsfr_lngth = tmp_bytes/(data_bus_width/8);
+ end
+ while (bytes > 0) begin
+   master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp);
+   for(i = 0; i < trnsfr_bytes; i = i+1) begin
+     rd_data = rd_data >> 8;
+     rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0];
+     rcv_rd_data =  rcv_rd_data >> 8;
+     total_rcvd_bytes = total_rcvd_bytes+1;
+   end
+   bytes = bytes - trnsfr_bytes;
+   addr = addr + trnsfr_bytes;
+   if(bytes  > (axi_burst_len * data_bus_width/8)) begin
+    trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; 
+    trnsfr_lngth = 15;
+   end else begin 
+     trnsfr_bytes = bytes;
+     tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
+     if(tmp_bytes%(data_bus_width/8) == 0)
+       trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
+     else 
+       trnsfr_lngth = tmp_bytes/(data_bus_width/8);
+   end
+   rresp = rresp | rdrsp;
+ end /// while 
+ rd_data =  rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8;
+ r_data = rd_data;
+ response = rresp;
+end
+end
+endtask
+
+
+/* Wait Register Update in PL */
+/* Issue a series of 1 burst length reads until the expected data pattern is received */
+
+task automatic wait_reg_update;
+input [addr_width-1:0] addri;
+input [data_width-1:0] datai;
+input [data_width-1:0] maski;
+input [int_width-1:0] time_interval;
+input [int_width-1:0] time_out;
+output [data_width-1:0] data_o;
+output upd_done;
+
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] data_i;
+reg [data_width-1:0] mask_i;
+integer time_int;
+integer timeout;
+
+reg [axi_rsp_width-1:0] rdrsp;
+reg [id_bus_width-1:0] rd_id;
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+reg [data_width-1:0] rcv_data;
+integer trnsfr_lngth; 
+reg rd_loop;
+reg timed_out; 
+integer i;
+integer cycle_cnt;
+
+begin
+addr = addri;
+data_i = datai;
+mask_i = maski;
+time_int = time_interval;
+timeout = time_out;
+timed_out = 0;
+cycle_cnt = 0;
+
+if(!enable_this_port) begin
+ $display(""[%0d] : %0s : %0s : Port is disabled. \'wait_reg_update\' will not be executed..."",$time, DISP_ERR, master_name);
+ upd_done = 0;
+ if(STOP_ON_ERROR) $stop;
+end else begin
+ rd_id = ID;
+ siz =  2; 
+ burst = 1;
+ lck = 0;
+ cache = 0;
+ prot = 0;
+ trnsfr_lngth = 0;
+ rd_loop = 1;
+ fork 
+  begin
+    while(!timed_out & rd_loop) begin
+      cycle_cnt = cycle_cnt + 1;
+      if(cycle_cnt >= timeout) timed_out = 1;
+      @(posedge M_ACLK);
+    end
+  end
+  begin
+    while (rd_loop) begin 
+     if(DEBUG_INFO)
+       $display(""[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) "",$time, master_name, DISP_INFO, addr); 
+     master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp);
+     if(DEBUG_INFO)
+       $display(""[%0d] : %0s : %0s : Reading Register returned (0x%0h) "",$time, master_name, DISP_INFO, rcv_data); 
+     if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out)
+       rd_loop = 0;
+     else
+       repeat(time_int) @(posedge M_ACLK);
+    end /// while 
+  end 
+ join
+ data_o = rcv_data & ~mask_i; 
+ if(timed_out) begin
+   $display(""[%0d] : %0s : %0s : \'wait_reg_update\' timed out ... Register is not updated "",$time, DISP_ERR, master_name);
+   if(STOP_ON_ERROR) $stop;
+ end else
+   upd_done = 1;
+end
+end
+endtask
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_afi_slave.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
+ *               from Cadence.
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_afi_slave (
+  S_RESETN,
+
+  S_ARREADY,
+  S_AWREADY,
+  S_BVALID,
+  S_RLAST,
+  S_RVALID,
+  S_WREADY,
+  S_BRESP,
+  S_RRESP,
+  S_RDATA,
+  S_BID,
+  S_RID,
+  S_ACLK,
+  S_ARVALID,
+  S_AWVALID,
+  S_BREADY,
+  S_RREADY,
+  S_WLAST,
+  S_WVALID,
+  S_ARBURST,
+  S_ARLOCK,
+  S_ARSIZE,
+  S_AWBURST,
+  S_AWLOCK,
+  S_AWSIZE,
+  S_ARPROT,
+  S_AWPROT,
+  S_ARADDR,
+  S_AWADDR,
+  S_WDATA,
+  S_ARCACHE,
+  S_ARLEN,
+  S_AWCACHE,
+  S_AWLEN,
+  S_WSTRB,
+  S_ARID,
+  S_AWID,
+  S_WID,
+  
+  S_AWQOS,
+  S_ARQOS,
+
+  SW_CLK,
+  WR_DATA_ACK_OCM,
+  WR_DATA_ACK_DDR,
+  WR_ADDR,
+  WR_DATA,
+  WR_BYTES,
+  WR_DATA_VALID_OCM,
+  WR_DATA_VALID_DDR,
+  WR_QOS,
+  
+  RD_REQ_DDR,
+  RD_REQ_OCM,
+  RD_ADDR,
+  RD_DATA_OCM,
+  RD_DATA_DDR,
+  RD_BYTES,
+  RD_QOS,
+  RD_DATA_VALID_OCM,
+  RD_DATA_VALID_DDR,
+  S_RDISSUECAP1_EN,
+  S_WRISSUECAP1_EN,
+  S_RCOUNT,
+  S_WCOUNT,
+  S_RACOUNT,
+  S_WACOUNT
+
+);
+  parameter enable_this_port = 0;  
+  parameter slave_name = ""Slave"";
+  parameter data_bus_width = 32;
+  parameter address_bus_width = 32;
+  parameter id_bus_width = 6;
+  parameter slave_base_address = 0;
+  parameter slave_high_address = 4;
+  parameter max_outstanding_transactions = 8;
+  parameter exclusive_access_supported = 0;
+
+  `include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+  /* Local parameters only for this module */
+  /* Internal counters that are used as Read/Write pointers to the fifo\'s that store all the transaction info on all channles.
+     This parameter is used to 'b'define the width of these pointers --> depending on Maximum outstanding transactions supported.
+     1-bit extra width than the no.of.bits needed to represent the outstanding transactions
+     Extra bit helps in generating the empty and full flags
+  */
+  parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
+
+  /* RESP data */
+  parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; 
+  parameter rsp_lsb = 0;
+  parameter rsp_msb = axi_rsp_width-1;
+  parameter rsp_id_lsb = rsp_msb + 1;  
+  parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;  
+
+  input  S_RESETN;
+
+  output  S_ARREADY;
+  output  S_AWREADY;
+  output  S_BVALID;
+  output  S_RLAST;
+  output  S_RVALID;
+  output  S_WREADY;
+  output  [axi_rsp_width-1:0] S_BRESP;
+  output  [axi_rsp_width-1:0] S_RRESP;
+  output  [data_bus_width-1:0] S_RDATA;
+  output  [id_bus_width-1:0] S_BID;
+  output  [id_bus_width-1:0] S_RID;
+  input S_ACLK;
+  input S_ARVALID;
+  input S_AWVALID;
+  input S_BREADY;
+  input S_RREADY;
+  input S_WLAST;
+  input S_WVALID;
+  input [axi_brst_type_width-1:0] S_ARBURST;
+  input [axi_lock_width-1:0] S_ARLOCK;
+  input [axi_size_width-1:0] S_ARSIZE;
+  input [axi_brst_type_width-1:0] S_AWBURST;
+  input [axi_lock_width-1:0] S_AWLOCK;
+  input [axi_size_width-1:0] S_AWSIZE;
+  input [axi_prot_width-1:0] S_ARPROT;
+  input [axi_prot_width-1:0] S_AWPROT;
+  input [address_bus_width-1:0] S_ARADDR;
+  input [address_bus_width-1:0] S_AWADDR;
+  input [data_bus_width-1:0] S_WDATA;
+  input [axi_cache_width-1:0] S_ARCACHE;
+  input [axi_cache_width-1:0] S_ARLEN;
+  
+  input [axi_qos_width-1:0] S_ARQOS;
+ 
+  input [axi_cache_width-1:0] S_AWCACHE;
+  input [axi_len_width-1:0] S_AWLEN;
+
+  input [axi_qos_width-1:0] S_AWQOS;
+  input [(data_bus_width/8)-1:0] S_WSTRB;
+  input [id_bus_width-1:0] S_ARID;
+  input [id_bus_width-1:0] S_AWID;
+  input [id_bus_width-1:0] S_WID;
+
+  input SW_CLK;
+  input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
+  output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
+  output [max_burst_bits-1:0] WR_DATA;
+  output [addr_width-1:0] WR_ADDR;
+  output [max_transfer_bytes_width:0] WR_BYTES;
+  output reg RD_REQ_OCM, RD_REQ_DDR;
+  output reg [addr_width-1:0] RD_ADDR;
+  input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
+  output reg[max_transfer_bytes_width:0] RD_BYTES;
+  input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
+  output [axi_qos_width-1:0] WR_QOS;
+  output reg [axi_qos_width-1:0] RD_QOS;
+ 
+  input S_RDISSUECAP1_EN;
+  input S_WRISSUECAP1_EN;
+
+  output [7:0] S_RCOUNT;
+  output [7:0] S_WCOUNT;
+  output [2:0] S_RACOUNT;
+  output [5:0] S_WACOUNT;
+
+  wire net_ARVALID;
+  wire net_AWVALID;
+  wire net_WVALID;
+
+  real s_aclk_period;
+
+  cdn_axi3_slave_bfm #(slave_name,
+                       data_bus_width,
+                       address_bus_width,
+                       id_bus_width, 
+                       slave_base_address,
+                       (slave_high_address- slave_base_address),
+                       max_outstanding_transactions,
+                       0, ///MEMORY_MODEL_MODE,
+                       exclusive_access_supported)
+  slave   (.ACLK    (S_ACLK),
+           .ARESETn (S_RESETN), /// confirm this
+           // Write Address Channel
+           .AWID    (S_AWID),
+           .AWADDR  (S_AWADDR),
+           .AWLEN   (S_AWLEN),
+           .AWSIZE  (S_AWSIZE),
+           .AWBURST (S_AWBURST),
+           .AWLOCK  (S_AWLOCK),
+           .AWCACHE (S_AWCACHE),
+           .AWPROT  (S_AWPROT),
+           .AWVALID (net_AWVALID),
+           .AWREADY (S_AWREADY),
+           // Write Data Channel Signals.
+           .WID    (S_WID),
+           .WDATA  (S_WDATA),
+           .WSTRB  (S_WSTRB), 
+           .WLAST  (S_WLAST), 
+           .WVALID (net_WVALID),
+           .WREADY (S_WREADY),
+           // Write Response Channel Signals.
+           .BID    (S_BID),
+           .BRESP  (S_BRESP),
+           .BVALID (S_BVALID),
+           .BREADY (S_BREADY),
+           // Read Address Channel Signals.
+           .ARID    (S_ARID),
+           .ARADDR  (S_ARADDR),
+           .ARLEN   (S_ARLEN),
+           .ARSIZE  (S_ARSIZE),
+           .ARBURST (S_ARBURST),
+           .ARLOCK  (S_ARLOCK),
+           .ARCACHE (S_ARCACHE),
+           .ARPROT  (S_ARPROT),
+           .ARVALID (net_ARVALID),
+           .ARREADY (S_ARREADY),
+           // Read Data Channel Signals.
+           .RID    (S_RID),
+           .RDATA  (S_RDATA),
+           .RRESP  (S_RRESP),
+           .RLAST  (S_RLAST),
+           .RVALID (S_RVALID),
+           .RREADY (S_RREADY));
+
+
+  wire wr_intr_fifo_full;
+  reg temp_wr_intr_fifo_full; 
+
+  /* Interconnect WR_FIFO model instance */
+  processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
+
+  /* Register the async \'full\' signal to S_ACLK clock */
+  always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
+
+  /* Latency type and Debug/Error Control */
+  reg[1:0] latency_type = RANDOM_CASE;
+  reg DEBUG_INFO = 1; 
+  reg STOP_ON_ERROR = 1\'b1; 
+
+  /* Internal nets/regs for calling slave BFM API\'s*/
+  reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
+  reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
+  wire wr_fifo_empty;
+
+  /* Store the awvalid receive time --- necessary for calculating the bresp latency */
+  reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
+  real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
+  reg  awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
+
+  /* Address Write Channel handshake*/
+  reg[int_cntr_width-1:0] aw_cnt = 0;//
+
+  /* various FIFOs for storing the ADDR channel info */
+  reg [axi_size_width-1:0]  awsize [0:max_outstanding_transactions-1];
+  reg [axi_prot_width-1:0]  awprot [0:max_outstanding_transactions-1];
+  reg [axi_lock_width-1:0]  awlock [0:max_outstanding_transactions-1];
+  reg [axi_cache_width-1:0]  awcache [0:max_outstanding_transactions-1];
+  reg [axi_brst_type_width-1:0]  awbrst [0:max_outstanding_transactions-1];
+  reg [axi_len_width-1:0]  awlen [0:max_outstanding_transactions-1];
+  reg aw_flag [0:max_outstanding_transactions-1];
+  reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
+  reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
+  reg [axi_qos_width-1:0]  awqos [0:max_outstanding_transactions-1];
+  wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
+
+  /* internal fifos to store burst write data, ID & strobes*/
+  reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
+  reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
+  reg wlast_flag [0:max_outstanding_transactions-1]; // flag  to indicate WLAST received
+  wire wd_fifo_full;
+
+  /* Write Data Channel and Write Response handshake signals*/
+  reg [int_cntr_width-1:0] wd_cnt = 0;
+  reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
+  reg [addr_width-1:0] aligned_wr_addr;
+  reg [max_burst_bytes_width:0] valid_data_bytes;
+  reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
+  reg [axi_rsp_width-1:0] bresp;
+  reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
+  reg enable_write_bresp;
+  reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
+  integer wr_latency_count;
+  reg  wr_delayed;
+  wire bresp_fifo_empty;
+
+  /* keep track of count values */
+  reg[7:0] wcount;
+  reg[5:0] wacount;
+
+  /* Qos*/
+  reg [axi_qos_width-1:0] ar_qos, aw_qos;
+
+  initial begin
+   if(DEBUG_INFO) begin
+    if(enable_this_port)
+     $display(""[%0d] : %0s : %0s : Port is ENABLED."",$time, DISP_INFO, slave_name);
+    else
+     $display(""[%0d] : %0s : %0s : Port is DISABLED."",$time, DISP_INFO, slave_name);
+   end
+  end
+ /*--------------------------------------------------------------------------------*/
+
+  /* Store the Clock cycle time period */
+          
+  always@(S_RESETN)
+  begin
+   if(S_RESETN) begin
+    @(posedge S_ACLK);
+    s_aclk_period = $time;
+    @(posedge S_ACLK);
+    s_aclk_period = $time - s_aclk_period;
+   end
+  end
+ /*--------------------------------------------------------------------------------*/
+
+  initial slave.set_disable_reset_value_checks(1); 
+  initial begin
+     repeat(2) @(posedge S_ACLK);
+     if(!enable_this_port) begin
+        slave.set_channel_level_info(0);
+        slave.set_function_level_info(0);
+     end 
+     slave.RESPONSE_TIMEOUT = 0;
+  end
+ /*--------------------------------------------------------------------------------*/
+
+  /* Set Latency type to be used */
+  task set_latency_type;
+    input[1:0] lat;
+  begin
+   if(enable_this_port) 
+    latency_type = lat;
+   else begin
+    //if(DEBUG_INFO)
+     $display(""[%0d] : %0s : %0s : Port is disabled. \'Latency Profile\' will not be set..."",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+ /*--------------------------------------------------------------------------------*/
+  /* Set ARQoS to be used */
+  task set_arqos;
+    input[axi_qos_width-1:0] qos;
+  begin
+   if(enable_this_port) 
+    ar_qos = qos;
+   else begin
+    if(DEBUG_INFO)
+     $display(""[%0d] : %0s : %0s : Port is disabled. \'ARQOS\' will not be set..."",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  /* Set AWQoS to be used */
+  task set_awqos;
+    input[axi_qos_width-1:0] qos;
+  begin
+   if(enable_this_port) 
+    aw_qos = qos;
+   else begin
+    if(DEBUG_INFO)
+     $display(""[%0d] : %0s : %0s : Port is disabled. \'AWQOS\' will not be set..."",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  /* get the wr latency number */
+  function [31:0] get_wr_lat_number;
+  input dummy;
+  reg[1:0] temp;
+  begin 
+   case(latency_type)
+    BEST_CASE   : get_wr_lat_number = afi_wr_min;            
+    AVG_CASE    : get_wr_lat_number = afi_wr_avg;            
+    WORST_CASE  : get_wr_lat_number = afi_wr_max;            
+    default     : begin  // RANDOM_CASE
+                   temp = $random;
+                   case(temp) 
+                    2\'b00   : get_wr_lat_number = ($random()%10+ afi_wr_min); 
+                    2\'b01   : get_wr_lat_number = ($random()%40+ afi_wr_avg); 
+                    default : get_wr_lat_number = ($random()%60+ afi_wr_max); 
+                   endcase        
+                  end
+   endcase
+  end
+  endfunction
+ /*--------------------------------------------------------------------------------*/
+
+  /* get the rd latency number */
+  function [31:0] get_rd_lat_number;
+  input dummy;
+  reg[1:0] temp;
+  begin 
+   case(latency_type)
+    BEST_CASE   : get_rd_lat_number = afi_rd_min;            
+    AVG_CASE    : get_rd_lat_number = afi_rd_avg;            
+    WORST_CASE  : get_rd_lat_number = afi_rd_max;            
+    default     : begin  // RANDOM_CASE
+                   temp = $random;
+                   case(temp) 
+                    2\'b00   : get_rd_lat_number = ($random()%10+ afi_rd_min); 
+                    2\'b01   : get_rd_lat_number = ($random()%40+ afi_rd_avg); 
+                    default : get_rd_lat_number = ($random()%60+ afi_rd_max); 
+                   endcase        
+                  end
+   endcase
+  end
+  endfunction
+ /*--------------------------------------------------------------------------------*/
+ /* Check for any WRITE/READs when this port is disabled */
+ always@(S_AWVALID or S_WVALID or S_ARVALID)
+ begin
+  if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
+    $display(""[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\
+Simulation will halt .."",$time, DISP_ERR, slave_name);
+    $stop;
+  end
+ end
+
+ /*--------------------------------------------------------------------------------*/
+
+  assign net_ARVALID = enable_this_port ? S_ARVALID : 1\'b0;
+  assign net_AWVALID = enable_this_port ? S_AWVALID : 1\'b0;
+  assign net_WVALID  = enable_this_port ? S_WVALID : 1\'b0;
+
+  assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1\'b1: 1\'b0;
+  assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1\'b1:1\'b0;
+  assign bresp_fifo_full  = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1\'b1:1\'b0;
+
+  assign S_WCOUNT = wcount;
+  assign S_WACOUNT = wacount;
+
+ // FIFO_STATUS (only if AFI port) 1- full 
+ function automatic wrfifo_full ;
+ input [axi_len_width:0] fifo_space_exp;
+ integer fifo_space_left; 
+ begin
+   fifo_space_left = afi_fifo_locations - wcount;
+   if(fifo_space_left < fifo_space_exp) 
+     wrfifo_full = 1;
+   else
+     wrfifo_full = 0;
+ end
+ endfunction
+ /*--------------------------------------------------------------------------------*/
+
+ /* Store the awvalid receive time --- necessary for calculating the bresp latency */
+ always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
+ begin
+ if(!S_RESETN)
+  aw_time_cnt = 0;
+ else begin
+  if(S_AWVALID) begin
+    awvalid_receive_time[aw_time_cnt] = $time;
+    awvalid_flag[aw_time_cnt] = 1\'b1;
+    aw_time_cnt = aw_time_cnt + 1;
+  end
+ end // else
+ end /// always
+ /*--------------------------------------------------------------------------------*/
+  always@(posedge S_ACLK)
+  begin
+  if(net_AWVALID && S_AWREADY) begin
+    if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos; 
+    else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS; 
+  end
+  end
+
+ /* Address Write Channel handshake*/
+ always@(negedge S_RESETN or posedge S_ACLK)
+ begin
+ if(!S_RESETN) begin
+   aw_cnt = 0;
+   wacount = 0;
+ end else begin
+   if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin 
+       slave.RECEIVE_WRITE_ADDRESS(0,
+                                   id_invalid,
+                                   awaddr[aw_cnt[int_cntr_width-2:0]],
+                                   awlen[aw_cnt[int_cntr_width-2:0]],
+                                   awsize[aw_cnt[int_cntr_width-2:0]],
+                                   awbrst[aw_cnt[int_cntr_width-2:0]],
+                                   awlock[aw_cnt[int_cntr_width-2:0]],
+                                   awcache[aw_cnt[int_cntr_width-2:0]],
+                                   awprot[aw_cnt[int_cntr_width-2:0]],
+                                   awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
+       aw_flag[aw_cnt[int_cntr_width-2:0]] = 1\'b1;
+       aw_cnt                              = aw_cnt + 1;
+       wacount                             = wacount + 1;
+   end // if (!aw_fifo_full)
+ end /// if else
+ end /// always
+ /*--------------------------------------------------------------------------------*/
+ 
+ /* Write Data Channel Handshake */
+ always@(negedge S_RESETN or posedge S_ACLK)
+ begin
+ if(!S_RESETN) begin
+  wd_cnt = 0;
+ end else begin
+  if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
+    if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
+     slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); 
+     wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1\'b1;
+     wd_cnt   = wd_cnt + 1;
+    end
+  end else begin
+    if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
+      slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); 
+      wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1\'b1;
+      wd_cnt   = wd_cnt + 1;
+    end
+  end /// if
+ end /// else
+ end /// always
+ /*--------------------------------------------------------------------------------*/
+ 
+ /* Align the wrap data for write transaction */
+ task automatic get_wrap_aligned_wr_data;
+ output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
+ output [addr_width-1:0] start_addr; /// aligned start address
+ input  [addr_width-1:0] addr;
+ input  [(data_bus_width*axi_burst_len)-1:0] b_data;
+ input  [max_burst_bytes_width:0] v_bytes;
+ reg    [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
+ integer wrp_bytes;
+ integer i;
+ begin
+   start_addr = (addr/v_bytes) * v_bytes;
+   wrp_bytes = addr - start_addr;
+   wrp_data = b_data;
+   temp_data = 0;
+   wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
+   while(wrp_bytes > 0) begin /// get the data that is wrapped
+     temp_data = temp_data << 8;
+     temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
+     wrp_data = wrp_data << 8;
+     wrp_bytes = wrp_bytes - 1;
+   end
+   wrp_bytes = addr - start_addr;
+   wrp_data = b_data << (wrp_bytes*8);
+   
+   aligned_data = (temp_data | wrp_data);
+ end
+ endtask
+ /*--------------------------------------------------------------------------------*/
+  
+ /* Calculate the Response for each read/write transaction */
+ function [axi_rsp_width-1:0] calculate_resp;
+ input [addr_width-1:0] awaddr; 
+ input [axi_prot_width-1:0] awprot;
+ reg [axi_rsp_width-1:0] rsp;
+ begin
+   rsp = AXI_OK;
+   /* Address Decode */
+   if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
+    rsp = AXI_SLV_ERR; //slave error
+    $display(""[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) "",$time, DISP_ERR, slave_name, awaddr);
+   end
+   else if(decode_address(awaddr) === REG_MEM) begin
+    rsp = AXI_SLV_ERR; //slave error
+    $display(""[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port."",$time, DISP_ERR, slave_name, awaddr);
+   end
+   if(secure_access_enabled && awprot[1])
+    rsp = AXI_DEC_ERR; // decode error
+   calculate_resp = rsp;
+ end
+ endfunction
+ /*--------------------------------------------------------------------------------*/
+ reg[max_burst_bits-1:0] temp_wr_data;
+ /* Store the Write response for each write transaction */
+ always@(negedge S_RESETN or posedge S_ACLK)
+ begin
+ if(!S_RESETN) begin
+  wr_fifo_wr_ptr = 0;
+  wcount = 0;
+ end else begin
+  enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
+  /* calculate bresp only when AWVALID && WLAST is received */
+  if(enable_write_bresp) begin
+    aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]]    = 0;
+    wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
+ 
+    bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
+    /* Fill AFI_WR_data FIFO */
+    if(bresp === AXI_OK ) begin
+      if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
+        get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]);      /// gives wrapped start address
+      end else begin
+        aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]]; 
+        aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
+      end
+      valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
+    end else
+      valid_data_bytes = 0;
+    temp_wr_data = aligned_wr_data;
+    wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
+    wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
+    wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
+  end
+ end // else
+ end // always
+ /*--------------------------------------------------------------------------------*/
+ 
+ /* Send Write Response Channel handshake */
+ always@(negedge S_RESETN or posedge S_ACLK)
+ begin
+ if(!S_RESETN) begin
+  rd_bresp_cnt = 0;
+  wr_latency_count = get_wr_lat_number(1);
+  wr_delayed = 0;
+  bresp_time_cnt = 0; 
+ end else begin
+  wr_delayed = 1\'b0;
+  if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
+    wr_delayed = 1;
+  if(!bresp_fifo_empty && wr_delayed) begin
+    slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb],  // ID
+                              fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb]   // Response
+                             );
+    wr_delayed = 0;
+    awvalid_flag[bresp_time_cnt] = 1\'b0;
+    bresp_time_cnt = bresp_time_cnt+1;
+    rd_bresp_cnt   = rd_bresp_cnt + 1;
+    wr_latency_count = get_wr_lat_number(1);
+  end 
+ end // else
+ end//always
+ /*--------------------------------------------------------------------------------*/
+ 
+ /* Write Response Channel handshake */
+ reg wr_int_state;
+ /* Reading from the wr_fifo and sending to Interconnect fifo*/
+ always@(negedge S_RESETN or posedge S_ACLK) 
+ begin
+ if(!S_RESETN) begin
+  wr_int_state = 1\'b0;
+  wr_bresp_cnt = 0;
+  wr_fifo_rd_ptr = 0;
+ end else begin
+  case(wr_int_state)
+  1\'b0 : begin
+    wr_int_state = 1\'b0;
+    if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
+      wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
+      wr_int_state = 1\'b1;
+      /* start filling the write response fifo at the same time */
+      fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
+      wcount  = wcount  - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
+      wacount = wacount - 1;
+      wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
+      wr_bresp_cnt   = wr_bresp_cnt+1;
+    end
+  end
+  1\'b1 : begin
+    wr_int_state = 0;
+  end
+  endcase
+ end
+ end
+  /*--------------------------------------------------------------------------------*/
+/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
+ 
+/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
+
+/* READ CHANNELS */
+/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
+  reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
+  real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
+  reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
+  reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
+
+/* various FIFOs for storing the ADDR channel info */
+  reg [axi_size_width-1:0]  arsize [0:max_outstanding_transactions-1];
+  reg [axi_prot_width-1:0]  arprot [0:max_outstanding_transactions-1];
+  reg [axi_brst_type_width-1:0]  arbrst [0:max_outstanding_transactions-1];
+  reg [axi_len_width-1:0]  arlen [0:max_outstanding_transactions-1];
+  reg [axi_cache_width-1:0]  arcache [0:max_outstanding_transactions-1];
+  reg [axi_lock_width-1:0]  arlock [0:max_outstanding_transactions-1];
+  reg ar_flag [0:max_outstanding_transactions-1];
+  reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
+  reg [id_bus_width-1:0]  arid [0:max_outstanding_transactions-1];
+  reg [axi_qos_width-1:0]  arqos [0:max_outstanding_transactions-1];
+  wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
+
+  reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
+  reg [axi_rsp_width-1:0] rresp;
+  reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
+  reg enable_write_rresp;
+
+  /* Send Read Response & Data Channel handshake */
+  integer rd_latency_count;
+  reg  rd_delayed;
+
+  reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
+  reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
+  wire read_fifo_full; 
+
+  reg [7:0] rcount;
+  reg [2:0] racount;
+  
+  wire rd_intr_fifo_full, rd_intr_fifo_empty;
+  wire read_fifo_empty;
+
+  /* signals to communicate with interconnect RD_FIFO model */
+  reg rd_req, invalid_rd_req;
+  
+  /* REad control Info 
+    56:25 : Address (32)
+    24:22 : Size (3)
+    21:20 : BRST (2)
+    19:16 : LEN (4)
+    15:10 : RID (6)
+    9:8 : RRSP (2)
+    7:0 : byte cnt (8)
+  */
+  reg [rd_info_bits-1:0] read_control_info;   
+  reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
+  reg temp_rd_intr_fifo_empty;
+
+  processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
+
+  assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1\'b1: 1\'b0;
+  assign S_RCOUNT = rcount;
+  assign S_RACOUNT = racount;
+
+  /* Register the asynch signal empty coming from Interconnect READ FIFO */
+  always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
+   
+  // FIFO_STATUS (only if AFI port) 1- full 
+   function automatic rdfifo_full ;
+   input [axi_len_width:0] fifo_space_exp;
+   integer fifo_space_left; 
+   begin
+     fifo_space_left = afi_fifo_locations - rcount;
+     if(fifo_space_left < fifo_space_exp) 
+       rdfifo_full = 1;
+     else
+       rdfifo_full = 0;
+   end
+   endfunction
+
+  /* Store the arvalid receive time --- necessary for calculating the bresp latency */
+  always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
+  begin
+  if(!S_RESETN)
+   ar_time_cnt = 0;
+  else begin
+   if(S_ARVALID) begin
+     arvalid_receive_time[ar_time_cnt] = $time;
+     arvalid_flag[ar_time_cnt] = 1\'b1;
+     ar_time_cnt = ar_time_cnt + 1;
+   end 
+  end // else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  always@(posedge S_ACLK)
+  begin
+  if(net_ARVALID && S_ARREADY) begin
+    if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos; 
+    else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS; 
+  end
+  end
+
+  /* Address Read  Channel handshake*/
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+    ar_cnt = 0;
+    racount = 0;
+  end else begin
+    if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
+        slave.RECEIVE_READ_ADDRESS(0,
+                                   id_invalid,
+                                   araddr[ar_cnt[int_cntr_width-2:0]],
+                                   arlen[ar_cnt[int_cntr_width-2:0]],
+                                   arsize[ar_cnt[int_cntr_width-2:0]],
+                                   arbrst[ar_cnt[int_cntr_width-2:0]],
+                                   arlock[ar_cnt[int_cntr_width-2:0]],
+                                   arcache[ar_cnt[int_cntr_width-2:0]],
+                                   arprot[ar_cnt[int_cntr_width-2:0]],
+                                   arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
+        ar_flag[ar_cnt[int_cntr_width-2:0]] = 1\'b1;
+        ar_cnt    = ar_cnt+1;
+        racount   = racount + 1;
+    end /// if(!ar_fifo_full)
+  end /// if else
+  end /// always*/
+  
+  /*--------------------------------------------------------------------------------*/
+
+  /* Align Wrap data for read transaction*/
+  task automatic get_wrap_aligned_rd_data;
+  output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
+  input [addr_width-1:0] addr;
+  input [(data_bus_width*axi_burst_len)-1:0] b_data;
+  input [max_burst_bytes_width:0] v_bytes;
+  reg [addr_width-1:0] start_addr;
+  reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
+  integer wrp_bytes;
+  integer i;
+  begin
+    start_addr = (addr/v_bytes) * v_bytes;
+    wrp_bytes = addr - start_addr;
+    wrp_data  = b_data;
+    temp_data = 0;
+    while(wrp_bytes > 0) begin /// get the data that is wrapped
+     temp_data = temp_data >> 8;
+     temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
+     wrp_data = wrp_data >> 8;
+     wrp_bytes = wrp_bytes - 1;
+    end
+    temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
+    wrp_bytes = addr - start_addr;
+    wrp_data = b_data >> (wrp_bytes*8);
+    
+    aligned_data = (temp_data | wrp_data);
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  parameter RD_DATA_REQ = 1\'b0, WAIT_RD_VALID = 1\'b1;
+  reg rd_fifo_state; 
+  reg [addr_width-1:0] temp_read_address;
+  reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
+  /* get the data from memory && also calculate the rresp*/
+  always@(negedge S_RESETN or posedge SW_CLK)
+  begin
+  if(!S_RESETN)begin
+   wr_rresp_cnt =0;
+   rd_fifo_state = RD_DATA_REQ;
+   temp_rd_valid_bytes = 0;
+   temp_read_address = 0;
+   RD_REQ_DDR = 1\'b0;
+   RD_REQ_OCM = 1\'b0;
+   rd_req        = 0;
+   invalid_rd_req= 0;
+   RD_QOS  = 0;
+  end else begin
+   case(rd_fifo_state)
+   RD_DATA_REQ : begin
+     rd_fifo_state = RD_DATA_REQ;
+     RD_REQ_DDR = 1\'b0;
+     RD_REQ_OCM = 1\'b0;
+     invalid_rd_req = 0;
+     if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
+       ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
+       rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
+       temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
+
+       if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
+        temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
+       else 
+        temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
+       
+       if(rresp === AXI_OK) begin 
+         case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
+          OCM_MEM : RD_REQ_OCM = 1;
+          DDR_MEM : RD_REQ_DDR = 1;
+          default : invalid_rd_req = 1;
+         endcase
+       end else
+         invalid_rd_req = 1;
+       RD_ADDR    = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
+       RD_BYTES   = temp_rd_valid_bytes;
+       RD_QOS     = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
+       rd_fifo_state = WAIT_RD_VALID; 
+       rd_req     = 1;
+       racount    = racount - 1;
+       read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes  };
+       wr_rresp_cnt = wr_rresp_cnt + 1;
+     end
+   end
+   WAIT_RD_VALID : begin    
+     rd_fifo_state = WAIT_RD_VALID;  
+     rd_req        = 0;
+     if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2\'b11) begin
+       RD_REQ_DDR = 1\'b0;
+       RD_REQ_OCM = 1\'b0;
+       invalid_rd_req = 0;
+       rd_fifo_state = RD_DATA_REQ;
+     end
+   end
+   endcase
+  end /// else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  
+  /* thread to fill in the AFI RD_FIFO */
+  reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
+  reg tmp_state; 
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)begin
+   rd_fifo_wr_ptr = 0; 
+   rcount = 0;
+   tmp_state = 0;
+  end else begin
+   case(tmp_state)
+   0 : begin 
+       tmp_state = 0;
+       if(!temp_rd_intr_fifo_empty) begin
+         rd_intr_fifo.read_mem(temp_rd_data);
+         tmp_state = 1;
+       end
+      end
+   1 : begin  
+       tmp_state = 1;
+       if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
+        read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
+        rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
+        rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
+        tmp_state = 0;
+       end
+      end
+    endcase
+  end
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  reg[max_burst_bytes_width:0] rd_v_b;
+  reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd;  /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
+  reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
+  reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
+
+  /* Read Data Channel handshake */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)begin
+   rd_fifo_rd_ptr = 0;
+   rd_latency_count = get_rd_lat_number(1);
+   rd_delayed = 0;
+   rresp_time_cnt = 0;
+   rd_v_b = 0;
+  end else begin
+     if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
+       rd_delayed = 1;
+     end
+     if(!read_fifo_empty && rd_delayed)begin
+       rd_delayed = 0;  
+       arvalid_flag[rresp_time_cnt] = 1\'b0;
+       tmp_fifo_rd =  read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
+       rd_v_b      = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
+       temp_read_data =  tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
+       if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
+          get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
+          temp_read_data = aligned_rd_data;
+       end
+       temp_read_rsp = 0;
+       repeat(axi_burst_len) begin
+         temp_read_rsp = temp_read_rsp >> axi_rsp_width;
+         temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
+       end 
+       slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
+                                       tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], 
+                                       tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb], 
+                                       tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
+                                       tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb], 
+                                       temp_read_data,
+                                       temp_read_rsp);   
+       rcount = rcount -  (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
+       rresp_time_cnt = rresp_time_cnt+1;
+       rd_latency_count = get_rd_lat_number(1);
+       rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
+     end
+  end /// else
+  end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_bfm_v2_0_5_processing_system7_bfm.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Processing_system7_bfm Top (zynq_bfm top)
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_bfm_v2_0_5_processing_system7_bfm
+  (
+    CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TD_I,
+    PJTAG_TD_T,
+    PJTAG_TD_O,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    USB0_PORT_INDCTL,
+    USB1_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB1_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3'b'_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA1_DRTYPE,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_DRVALID,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG,
+    FTMT_F2P_TRIGACK,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK,
+    FTMT_P2F_TRIG,
+    FTMT_P2F_DEBUG,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FPGA_IDLE_N,
+    DDR_ARB,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    MIO,
+    DDR_Clk,
+    DDR_Clk_n,
+    DDR_CKE,
+    DDR_CS_n,
+    DDR_RAS_n,
+    DDR_CAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_ODT,
+    DDR_DRSTB,
+    DDR_DQ,
+    DDR_DM,
+    DDR_DQS,
+    DDR_DQS_n,
+    DDR_VRN,
+    DDR_VRP,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1
+  );
+
+
+  /* parameters for gen_clk */
+  parameter C_FCLK_CLK0_FREQ = 50;
+  parameter C_FCLK_CLK1_FREQ = 50;
+  parameter C_FCLK_CLK3_FREQ = 50;
+  parameter C_FCLK_CLK2_FREQ = 50;
+
+  parameter C_HIGH_OCM_EN    = 0;
+
+
+  /* parameters for HP ports */
+  parameter C_USE_S_AXI_HP0 = 0;
+  parameter C_USE_S_AXI_HP1 = 0;
+  parameter C_USE_S_AXI_HP2 = 0;
+  parameter C_USE_S_AXI_HP3 = 0;
+
+  parameter C_S_AXI_HP0_DATA_WIDTH = 32;
+  parameter C_S_AXI_HP1_DATA_WIDTH = 32;
+  parameter C_S_AXI_HP2_DATA_WIDTH = 32;
+  parameter C_S_AXI_HP3_DATA_WIDTH = 32;
+  
+  parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
+  parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; 
+  parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
+  parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; 
+  
+/* Do we need these 
+  parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */
+
+  parameter C_S_AXI_HP0_BASEADDR = 32\'h0000_0000;
+  parameter C_S_AXI_HP1_BASEADDR = 32\'h0000_0000;
+  parameter C_S_AXI_HP2_BASEADDR = 32\'h0000_0000;
+  parameter C_S_AXI_HP3_BASEADDR = 32\'h0000_0000;
+  
+  parameter C_S_AXI_HP0_HIGHADDR = 32\'hFFFF_FFFF;
+  parameter C_S_AXI_HP1_HIGHADDR = 32\'hFFFF_FFFF;
+  parameter C_S_AXI_HP2_HIGHADDR = 32\'hFFFF_FFFF;
+  parameter C_S_AXI_HP3_HIGHADDR = 32\'hFFFF_FFFF;
+ 
+  /* parameters for GP and ACP ports */
+  parameter C_USE_M_AXI_GP0 = 0;
+  parameter C_USE_M_AXI_GP1 = 0;
+  parameter C_USE_S_AXI_GP0 = 1;
+  parameter C_USE_S_AXI_GP1 = 1;
+  
+  /* Do we need this?
+  parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0;
+  parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0;
+  
+  parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/
+
+  parameter C_S_AXI_GP0_BASEADDR = 32\'h0000_0000;
+  parameter C_S_AXI_GP1_BASEADDR = 32\'h0000_0000;
+  
+  parameter C_S_AXI_GP0_HIGHADDR = 32\'hFFFF_FFFF;
+  parameter C_S_AXI_GP1_HIGHADDR = 32\'hFFFF_FFFF;
+  
+  parameter C_USE_S_AXI_ACP = 1;
+  parameter C_S_AXI_ACP_BASEADDR = 32\'h0000_0000;
+  parameter C_S_AXI_ACP_HIGHADDR = 32\'hFFFF_FFFF;
+ 
+  `include ""processing_system7_bfm_v2_0_5_local_params.v""
+
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0] ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_EXT_INTIN;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input [7:0] ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0] ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_EXT_INTIN;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input [7:0] ENET1_GMII_RXD;
+  input [63:0] GPIO_I;
+  output [63:0] GPIO_O;
+  output [63:0] GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TD_I;
+  output PJTAG_TD_T;
+  output PJTAG_TD_O;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0] SDIO0_DATA_I;
+  output [3:0] SDIO0_DATA_O;
+  output [3:0] SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0] SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0] SDIO1_DATA_I;
+  output [3:0] SDIO1_DATA_O;
+  output [3:0] SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0] SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [31:0] TRACE_DATA;
+  output [1:0] USB0_PORT_INDCTL;
+  output [1:0] USB1_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  output USB1_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID;
+  output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID;
+  output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID;
+  output [1:0] M_AXI_GP0_ARBURST;
+  output [1:0] M_AXI_GP0_ARLOCK;
+  output [2:0] M_AXI_GP0_ARSIZE;
+  output [1:0] M_AXI_GP0_AWBURST;
+  output [1:0] M_AXI_GP0_AWLOCK;
+  output [2:0] M_AXI_GP0_AWSIZE;
+  output [2:0] M_AXI_GP0_ARPROT;
+  output [2:0] M_AXI_GP0_AWPROT;
+  output [31:0] M_AXI_GP0_ARADDR;
+  output [31:0] M_AXI_GP0_AWADDR;
+  output [31:0] M_AXI_GP0_WDATA;
+  output [3:0] M_AXI_GP0_ARCACHE;
+  output [3:0] M_AXI_GP0_ARLEN;
+  output [3:0] M_AXI_GP0_ARQOS;
+  output [3:0] M_AXI_GP0_AWCACHE;
+  output [3:0] M_AXI_GP0_AWLEN;
+  output [3:0] M_AXI_GP0_AWQOS;
+  output [3:0] M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID;
+  input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID;
+  input [1:0] M_AXI_GP0_BRESP;
+  input [1:0] M_AXI_GP0_RRESP;
+  input [31:0] M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID;
+  output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID;
+  output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID;
+  output [1:0] M_AXI_GP1_ARBURST;
+  output [1:0] M_AXI_GP1_ARLOCK;
+  output [2:0] M_AXI_GP1_ARSIZE;
+  output [1:0] M_AXI_GP1_AWBURST;
+  output [1:0] M_AXI_GP1_AWLOCK;
+  output [2:0] M_AXI_GP1_AWSIZE;
+  output [2:0] M_AXI_GP1_ARPROT;
+  output [2:0] M_AXI_GP1_AWPROT;
+  output [31:0] M_AXI_GP1_ARADDR;
+  output [31:0] M_AXI_GP1_AWADDR;
+  output [31:0] M_AXI_GP1_WDATA;
+  output [3:0] M_AXI_GP1_ARCACHE;
+  output [3:0] M_AXI_GP1_ARLEN;
+  output [3:0] M_AXI_GP1_ARQOS;
+  output [3:0] M_AXI_GP1_AWCACHE;
+  output [3:0] M_AXI_GP1_AWLEN;
+  output [3:0] M_AXI_GP1_AWQOS;
+  output [3:0] M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID;
+  input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID;
+  input [1:0] M_AXI_GP1_BRESP;
+  input [1:0] M_AXI_GP1_RRESP;
+  input [31:0] M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0] S_AXI_GP0_BRESP;
+  output [1:0] S_AXI_GP0_RRESP;
+  output [31:0] S_AXI_GP0_RDATA;
+  output [5:0] S_AXI_GP0_BID;
+  output [5:0] S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0] S_AXI_GP0_ARBURST;
+  input [1:0] S_AXI_GP0_ARLOCK;
+  input [2:0] S_AXI_GP0_ARSIZE;
+  input [1:0] S_AXI_GP0_AWBURST;
+  input [1:0] S_AXI_GP0_AWLOCK;
+  input [2:0] S_AXI_GP0_AWSIZE;
+  input [2:0] S_AXI_GP0_ARPROT;
+  input [2:0] S_AXI_GP0_AWPROT;
+  input [31:0] S_AXI_GP0_ARADDR;
+  input [31:0] S_AXI_GP0_AWADDR;
+  input [31:0] S_AXI_GP0_WDATA;
+  input [3:0] S_AXI_GP0_ARCACHE;
+  input [3:0] S_AXI_GP0_ARLEN;
+  input [3:0] S_AXI_GP0_ARQOS;
+  input [3:0] S_AXI_GP0_AWCACHE;
+  input [3:0] S_AXI_GP0_AWLEN;
+  input [3:0] S_AXI_GP0_AWQOS;
+  input [3:0] S_AXI_GP0_WSTRB;
+  input [5:0] S_AXI_GP0_ARID;
+  input [5:0] S_AXI_GP0_AWID;
+  input [5:0] S_AXI_GP0_WID;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0] S_AXI_GP1_BRESP;
+  output [1:0] S_AXI_GP1_RRESP;
+  output [31:0] S_AXI_GP1_RDATA;
+  output [5:0] S_AXI_GP1_BID;
+  output [5:0] S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0] S_AXI_GP1_ARBURST;
+  input [1:0] S_AXI_GP1_ARLOCK;
+  input [2:0] S_AXI_GP1_ARSIZE;
+  input [1:0] S_AXI_GP1_AWBURST;
+  input [1:0] S_AXI_GP1_AWLOCK;
+  input [2:0] S_AXI_GP1_AWSIZE;
+  input [2:0] S_AXI_GP1_ARPROT;
+  input [2:0] S_AXI_GP1_AWPROT;
+  input [31:0] S_AXI_GP1_ARADDR;
+  input [31:0] S_AXI_GP1_AWADDR;
+  input [31:0] S_AXI_GP1_WDATA;
+  input [3:0] S_AXI_GP1_ARCACHE;
+  input [3:0] S_AXI_GP1_ARLEN;
+  input [3:0] S_AXI_GP1_ARQOS;
+  input [3:0] S_AXI_GP1_AWCACHE;
+  input [3:0] S_AXI_GP1_AWLEN;
+  input [3:0] S_AXI_GP1_AWQOS;
+  input [3:0] S_AXI_GP1_WSTRB;
+  input [5:0] S_AXI_GP1_ARID;
+  input [5:0] S_AXI_GP1_AWID;
+  input [5:0] S_AXI_GP1_WID;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0] S_AXI_ACP_BRESP;
+  output [1:0] S_AXI_ACP_RRESP;
+  output [2:0] S_AXI_ACP_BID;
+  output [2:0] S_AXI_ACP_RID;
+  output [63:0] S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0] S_AXI_ACP_ARID;
+  input [2:0] S_AXI_ACP_ARPROT;
+  input [2:0] S_AXI_ACP_AWID;
+  input [2:0] S_AXI_ACP_AWPROT;
+  input [2:0] S_AXI_ACP_WID;
+  input [31:0] S_AXI_ACP_ARADDR;
+  input [31:0] S_AXI_ACP_AWADDR;
+  input [3:0] S_AXI_ACP_ARCACHE;
+  input [3:0] S_AXI_ACP_ARLEN;
+  input [3:0] S_AXI_ACP_ARQOS;
+  input [3:0] S_AXI_ACP_AWCACHE;
+  input [3:0] S_AXI_ACP_AWLEN;
+  input [3:0] S_AXI_ACP_AWQOS;
+  input [1:0] S_AXI_ACP_ARBURST;
+  input [1:0] S_AXI_ACP_ARLOCK;
+  input [2:0] S_AXI_ACP_ARSIZE;
+  input [1:0] S_AXI_ACP_AWBURST;
+  input [1:0] S_AXI_ACP_AWLOCK;
+  input [2:0] S_AXI_ACP_AWSIZE;
+  input [4:0] S_AXI_ACP_ARUSER;
+  input [4:0] S_AXI_ACP_AWUSER;
+  input [63:0] S_AXI_ACP_WDATA;
+  input [7:0] S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0] S_AXI_HP0_BRESP;
+  output [1:0] S_AXI_HP0_RRESP;
+  output [5:0] S_AXI_HP0_BID;
+  output [5:0] S_AXI_HP0_RID;
+  output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA;
+  output [7:0] S_AXI_HP0_RCOUNT;
+  output [7:0] S_AXI_HP0_WCOUNT;
+  output [2:0] S_AXI_HP0_RACOUNT;
+  output [5:0] S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0] S_AXI_HP0_ARBURST;
+  input [1:0] S_AXI_HP0_ARLOCK;
+  input [2:0] S_AXI_HP0_ARSIZE;
+  input [1:0] S_AXI_HP0_AWBURST;
+  input [1:0] S_AXI_HP0_AWLOCK;
+  input [2:0] S_AXI_HP0_AWSIZE;
+  input [2:0] S_AXI_HP0_ARPROT;
+  input [2:0] S_AXI_HP0_AWPROT;
+  input [31:0] S_AXI_HP0_ARADDR;
+  input [31:0] S_AXI_HP0_AWADDR;
+  input [3:0] S_AXI_HP0_ARCACHE;
+  input [3:0] S_AXI_HP0_ARLEN;
+  input [3:0] S_AXI_HP0_ARQOS;
+  input [3:0] S_AXI_HP0_AWCACHE;
+  input [3:0] S_AXI_HP0_AWLEN;
+  input [3:0] S_AXI_HP0_AWQOS;
+  input [5:0] S_AXI_HP0_ARID;
+  input [5:0] S_AXI_HP0_AWID;
+  input [5:0] S_AXI_HP0_WID;
+  input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA;
+  input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0] S_AXI_HP1_BRESP;
+  output [1:0] S_AXI_HP1_RRESP;
+  output [5:0] S_AXI_HP1_BID;
+  output [5:0] S_AXI_HP1_RID;
+  output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA;
+  output [7:0] S_AXI_HP1_RCOUNT;
+  output [7:0] S_AXI_HP1_WCOUNT;
+  output [2:0] S_AXI_HP1_RACOUNT;
+  output [5:0] S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0] S_AXI_HP1_ARBURST;
+  input [1:0] S_AXI_HP1_ARLOCK;
+  input [2:0] S_AXI_HP1_ARSIZE;
+  input [1:0] S_AXI_HP1_AWBURST;
+  input [1:0] S_AXI_HP1_AWLOCK;
+  input [2:0] S_AXI_HP1_AWSIZE;
+  input [2:0] S_AXI_HP1_ARPROT;
+  input [2:0] S_AXI_HP1_AWPROT;
+  input [31:0] S_AXI_HP1_ARADDR;
+  input [31:0] S_AXI_HP1_AWADDR;
+  input [3:0] S_AXI_HP1_ARCACHE;
+  input [3:0] S_AXI_HP1_ARLEN;
+  input [3:0] S_AXI_HP1_ARQOS;
+  input [3:0] S_AXI_HP1_AWCACHE;
+  input [3:0] S_AXI_HP1_AWLEN;
+  input [3:0] S_AXI_HP1_AWQOS;
+  input [5:0] S_AXI_HP1_ARID;
+  input [5:0] S_AXI_HP1_AWID;
+  input [5:0] S_AXI_HP1_WID;
+  input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA;
+  input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0] S_AXI_HP2_BRESP;
+  output [1:0] S_AXI_HP2_RRESP;
+  output [5:0] S_AXI_HP2_BID;
+  output [5:0] S_AXI_HP2_RID;
+  output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA;
+  output [7:0] S_AXI_HP2_RCOUNT;
+  output [7:0] S_AXI_HP2_WCOUNT;
+  output [2:0] S_AXI_HP2_RACOUNT;
+  output [5:0] S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0] S_AXI_HP2_ARBURST;
+  input [1:0] S_AXI_HP2_ARLOCK;
+  input [2:0] S_AXI_HP2_ARSIZE;
+  input [1:0] S_AXI_HP2_AWBURST;
+  input [1:0] S_AXI_HP2_AWLOCK;
+  input [2:0] S_AXI_HP2_AWSIZE;
+  input [2:0] S_AXI_HP2_ARPROT;
+  input [2:0] S_AXI_HP2_AWPROT;
+  input [31:0] S_AXI_HP2_ARADDR;
+  input [31:0] S_AXI_HP2_AWADDR;
+  input [3:0] S_AXI_HP2_ARCACHE;
+  input [3:0] S_AXI_HP2_ARLEN;
+  input [3:0] S_AXI_HP2_ARQOS;
+  input [3:0] S_AXI_HP2_AWCACHE;
+  input [3:0] S_AXI_HP2_AWLEN;
+  input [3:0] S_AXI_HP2_AWQOS;
+  input [5:0] S_AXI_HP2_ARID;
+  input [5:0] S_AXI_HP2_AWID;
+  input [5:0] S_AXI_HP2_WID;
+  input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA;
+  input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0] S_AXI_HP3_BRESP;
+  output [1:0] S_AXI_HP3_RRESP;
+  output [5:0] S_AXI_HP3_BID;
+  output [5:0] S_AXI_HP3_RID;
+  output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA;
+  output [7:0] S_AXI_HP3_RCOUNT;
+  output [7:0] S_AXI_HP3_WCOUNT;
+  output [2:0] S_AXI_HP3_RACOUNT;
+  output [5:0] S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0] S_AXI_HP3_ARBURST;
+  input [1:0] S_AXI_HP3_ARLOCK;
+  input [2:0] S_AXI_HP3_ARSIZE;
+  input [1:0] S_AXI_HP3_AWBURST;
+  input [1:0] S_AXI_HP3_AWLOCK;
+  input [2:0] S_AXI_HP3_AWSIZE;
+  input [2:0] S_AXI_HP3_ARPROT;
+  input [2:0] S_AXI_HP3_AWPROT;
+  input [31:0] S_AXI_HP3_ARADDR;
+  input [31:0] S_AXI_HP3_AWADDR;
+  input [3:0] S_AXI_HP3_ARCACHE;
+  input [3:0] S_AXI_HP3_ARLEN;
+  input [3:0] S_AXI_HP3_ARQOS;
+  input [3:0] S_AXI_HP3_AWCACHE;
+  input [3:0] S_AXI_HP3_AWLEN;
+  input [3:0] S_AXI_HP3_AWQOS;
+  input [5:0] S_AXI_HP3_ARID;
+  input [5:0] S_AXI_HP3_AWID;
+  input [5:0] S_AXI_HP3_WID;
+  input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA;
+  input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB;
+  output [1:0] DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input [1:0] DMA0_DRTYPE;
+  output [1:0] DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input [1:0] DMA1_DRTYPE;
+  output [1:0] DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_DRVALID;
+  output [1:0] DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input [1:0] DMA2_DRTYPE;
+  input [1:0] DMA3_DRTYPE;
+  input [31:0] FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0] FTMD_TRACEIN_ATID;
+  input [3:0] FTMT_F2P_TRIG;
+  output [3:0] FTMT_F2P_TRIGACK;
+  input [31:0] FTMT_F2P_DEBUG;
+  input [3:0] FTMT_P2F_TRIGACK;
+  output [3:0] FTMT_P2F_TRIG;
+  output [31:0] FTMT_P2F_DEBUG;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input FPGA_IDLE_N;
+  input [3:0] DDR_ARB;
+  input [irq_width-1:0] IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output EVENT_EVENTO;
+  output [1:0] EVENT_STANDBYWFE;
+  output [1:0] EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  inout [53:0] MIO;
+  inout DDR_Clk;
+  inout DDR_Clk_n;
+  inout DDR_CKE;
+  inout DDR_CS_n;
+  inout DDR_RAS_n;
+  inout DDR_CAS_n;
+  output DDR_WEB;
+  inout [2:0] DDR_BankAddr;
+  inout [14:0] DDR_Addr;
+  inout DDR_ODT;
+  inout DDR_DRSTB;
+  inout [31:0] DDR_DQ;
+  inout [3:0] DDR_DM;
+  inout [3:0] DDR_DQS;
+  inout [3:0] DDR_DQS_n;
+  inout DDR_VRN;
+  inout DDR_VRP;
+/* Reset Input & Clock Input */
+  input PS_SRSTB;
+  input PS_CLK;
+  input PS_PORB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+
+
+  /* Internal wires/nets used for connectivity */
+  wire net_rstn;
+  wire net_sw_clk;
+  wire net_ocm_clk;
+  wire net_arbiter_clk;
+
+  wire net_axi_mgp0_rstn;
+  wire net_axi_mgp1_rstn;
+  wire net_axi_gp0_rstn;
+  wire net_axi_gp1_rstn;
+  wire net_axi_hp0_rstn;
+  wire net_axi_hp1_rstn;
+  wire net_axi_hp2_rstn;
+  wire net_axi_hp3_rstn;
+  wire net_axi_acp_rstn;
+  wire [4:0] net_axi_acp_awuser;
+  wire [4:0] net_axi_acp_aruser;
+
+
+  /* Dummy */
+  assign net_axi_acp_awuser = S_AXI_ACP_AWUSER;
+  assign net_axi_acp_aruser = S_AXI_ACP_ARUSER;
+
+  /* Global variables */
+  reg DEBUG_INFO = 1;
+  reg STOP_ON_ERROR = 1;
+  
+  /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ 
+  reg mem_update_key = 1; 
+  reg reg_update_key_0 = 1; 
+  reg reg_update_key_1 = 1; 
+  
+  /* assignments and semantic checks for unused ports */
+  `include ""processing_system7_bfm_v2_0_5_unused_ports.v""
+ 
+  /* include api definition */
+  `include ""processing_system7_bfm_v2_0_5_apis.v""
+ 
+  /* Reset Generator */
+  processing_system7_bfm_v2_0_5_gen_reset gen_rst(.por_rst_n(PS_PORB),
+                    .sys_rst_n(PS_SRSTB),
+                    .rst_out_n(net_rstn),
+
+                    .m_axi_gp0_clk(M_AXI_GP0_ACLK),
+                    .m_axi_gp1_clk(M_AXI_GP1_ACLK),
+                    .s_axi_gp0_clk(S_AXI_GP0_ACLK),
+                    .s_axi_gp1_clk(S_AXI_GP1_ACLK),
+                    .s_axi_hp0_clk(S_AXI_HP0_ACLK),
+                    .s_axi_hp1_clk(S_AXI_HP1_ACLK),
+                    .s_axi_hp2_clk(S_AXI_HP2_ACLK),
+                    .s_axi_hp3_clk(S_AXI_HP3_ACLK),
+                    .s_axi_acp_clk(S_AXI_ACP_ACLK),
+
+                    .m_axi_gp0_rstn(net_axi_mgp0_rstn),
+                    .m_axi_gp1_rstn(net_axi_mgp1_rstn),
+                    .s_axi_gp0_rstn(net_axi_gp0_rstn),
+                    .s_axi_gp1_rstn(net_axi_gp1_rstn),
+                    .s_axi_hp0_rstn(net_axi_hp0_rstn),
+                    .s_axi_hp1_rstn(net_axi_hp1_rstn),
+                    .s_axi_hp2_rstn(net_axi_hp2_rstn),
+                    .s_axi_hp3_rstn(net_axi_hp3_rstn),
+                    .s_axi_acp_rstn(net_axi_acp_rstn),
+
+                    .fclk_reset3_n(FCLK_RESET3_N),
+                    .fclk_reset2_n(FCLK_RESET2_N),
+                    .fclk_reset1_n(FCLK_RESET1_N),
+                    .fclk_reset0_n(FCLK_RESET0_N),
+
+                    .fpga_acp_reset_n(),   ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP)
+                    .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN),
+                    .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN),
+                    .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN),
+                    .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN),
+                    .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN),
+                    .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN),
+                    .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN),
+                    .fpga_hp_s3_reset_n()  ////S_AXI_HP3_ARESETN)
+                   );
+
+  /* Clock Generator */
+  processing_system7_bfm_v2_0_5_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ)
+            gen_clk(.ps_clk(PS_CLK),
+                    .sw_clk(net_sw_clk),
+
+                    .fclk_clk3(FCLK_CLK3),
+                    .fclk_clk2(FCLK_CLK2),
+                    .fclk_clk1(FCLK_CLK1),
+                    .fclk_clk0(FCLK_CLK0)
+                    );
+
+  wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1;
+  wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1;
+  wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1;
+  wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1;
+  wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1;
+  wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1;
+
+  wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1;
+  wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1;
+  wire net_rd_req_reg_gp0, net_rd_req_reg_gp1;
+  wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1;
+  wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1;
+  wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1;
+  wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1;
+  wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1;
+  wire  net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1;
+  wire  net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1;
+  wire  net_rd_dv_reg_gp0, net_rd_dv_reg_gp1;
+  wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1;
+  
+  wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3;
+  wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3;
+  wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3;
+  wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3;
+  wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3;
+  wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3;
+  wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3;
+  wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3;
+  
+  wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3;
+  wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3;
+  wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3;
+  wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3;
+  wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3;
+  wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3;
+  wire  net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3;
+  wire  net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3;
+  wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3;
+
+  wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp;
+  wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp;
+  wire [max_burst_bits-1:0] net_wr_data_acp;
+  wire [addr_width-1:0] net_wr_addr_acp;
+  wire [max_burst_bytes_width:0] net_wr_bytes_acp;
+  wire [axi_qos_width-1:0] net_wr_qos_acp;
+  
+  wire net_rd_req_ddr_acp, net_rd_req_ocm_acp;
+  wire [addr_width-1:0] net_rd_addr_acp;
+  wire [max_burst_bytes_width:0] net_rd_bytes_acp;
+  wire [max_burst_bits-1:0] net_rd_data_ddr_acp;
+  wire [max_burst_bits-1:0] net_rd_data_ocm_acp;
+  wire  net_rd_dv_ddr_acp,net_rd_dv_ocm_acp;
+  wire [axi_qos_width-1:0] net_rd_qos_acp;
+  
+  wire ocm_wr_ack_port0;
+  wire ocm_wr_dv_port0;
+  wire ocm_rd_req_port0;
+  wire ocm_rd_dv_port0;
+  wire [addr_width-1:0] ocm_wr_addr_port0;
+  wire [max_burst_bits-1:0] ocm_wr_data_port0;
+  wire [max_burst_bytes_width:0] ocm_wr_bytes_port0;
+  wire [addr_width-1:0] ocm_rd_addr_port0;
+  wire [max_burst_bits-1:0] ocm_rd_data_port0;
+  wire [max_burst_bytes_width:0] ocm_rd_bytes_port0;
+  wire [axi_qos_width-1:0] ocm_wr_qos_port0;
+  wire [axi_qos_width-1:0] ocm_rd_qos_port0;
+
+  wire ocm_wr_ack_port1;
+  wire ocm_wr_dv_port1;
+  wire ocm_rd_req_port1;
+  wire ocm_rd_dv_port1;
+  wire [addr_width-1:0] ocm_wr_addr_port1;
+  wire [max_burst_bits-1:0] ocm_wr_data_port1;
+  wire [max_burst_bytes_width:0] ocm_wr_bytes_port1;
+  wire [addr_width-1:0] ocm_rd_addr_port1;
+  wire [max_burst_bits-1:0] ocm_rd_data_port1;
+  wire [max_burst_bytes_width:0] ocm_rd_bytes_port1;
+  wire [axi_qos_width-1:0] ocm_wr_qos_port1;
+  wire [axi_qos_width-1:0] ocm_rd_qos_port1;
+
+  wire ddr_wr_ack_port0;
+  wire ddr_wr_dv_port0;
+  wire ddr_rd_req_port0;
+  wire ddr_rd_dv_port0;
+  wire[addr_width-1:0] ddr_wr_addr_port0;
+  wire[max_burst_bits-1:0] ddr_wr_data_port0;
+  wire[max_burst_bytes_width:0] ddr_wr_bytes_port0;
+  wire[addr_width-1:0] ddr_rd_addr_port0;
+  wire[max_burst_bits-1:0] ddr_rd_data_port0;
+  wire[max_burst_bytes_width:0] ddr_rd_bytes_port0;
+  wire [axi_qos_width-1:0] ddr_wr_qos_port0;
+  wire [axi_qos_width-1:0] ddr_rd_qos_port0;
+
+  wire ddr_wr_ack_port1;
+  wire ddr_wr_dv_port1;
+  wire ddr_rd_req_port1;
+  wire ddr_rd_dv_port1;
+  wire[addr_width-1:0] ddr_wr_addr_port1;
+  wire[max_burst_bits-1:0] ddr_wr_data_port1;
+  wire[max_burst_bytes_width:0] ddr_wr_bytes_port1;
+  wire[addr_width-1:0] ddr_rd_addr_port1;
+  wire[max_burst_bits-1:0] ddr_rd_data_port1;
+  wire[max_burst_bytes_width:0] ddr_rd_bytes_port1;
+  wire[axi_qos_width-1:0] ddr_wr_qos_port1;
+  wire[axi_qos_width-1:0] ddr_rd_qos_port1;
+  
+  wire ddr_wr_ack_port2;
+  wire ddr_wr_dv_port2;
+  wire ddr_rd_req_port2;
+  wire ddr_rd_dv_port2;
+  wire[addr_width-1:0] ddr_wr_addr_port2;
+  wire[max_burst_bits-1:0] ddr_wr_data_port2;
+  wire[max_burst_bytes_width:0] ddr_wr_bytes_port2;
+  wire[addr_width-1:0] ddr_rd_addr_port2;
+  wire[max_burst_bits-1:0] ddr_rd_data_port2;
+  wire[max_burst_bytes_width:0] ddr_rd_bytes_port2;
+  wire[axi_qos_width-1:0] ddr_wr_qos_port2;
+  wire[axi_qos_width-1:0] ddr_rd_qos_port2;
+  
+  wire ddr_wr_ack_port3;
+  wire ddr_wr_dv_port3;
+  wire ddr_rd_req_port3;
+  wire ddr_rd_dv_port3;
+  wire[addr_width-1:0] ddr_wr_addr_port3;
+  wire[max_burst_bits-1:0] ddr_wr_data_port3;
+  wire[max_burst_bytes_width:0] ddr_wr_bytes_port3;
+  wire[addr_width-1:0] ddr_rd_addr_port3;
+  wire[max_burst_bits-1:0] ddr_rd_data_port3;
+  wire[max_burst_bytes_width:0] ddr_rd_bytes_port3;
+  wire[axi_qos_width-1:0] ddr_wr_qos_port3;
+  wire[axi_qos_width-1:0] ddr_rd_qos_port3;
+
+  wire reg_rd_req_port0;
+  wire reg_rd_dv_port0;
+  wire[addr_width-1:0] reg_rd_addr_port0;
+  wire[max_burst_bits-1:0] reg_rd_data_port0;
+  wire[max_burst_bytes_width:0] reg_rd_bytes_port0;
+  wire [axi_qos_width-1:0] reg_rd_qos_port0;
+
+  wire reg_rd_req_port1;
+  wire reg_rd_dv_port1;
+  wire[addr_width-1:0] reg_rd_addr_port1;
+  wire[max_burst_bits-1:0] reg_rd_data_port1;
+  wire[max_burst_bytes_width:0] reg_rd_bytes_port1;
+  wire [axi_qos_width-1:0] reg_rd_qos_port1;
+
+  wire [11:0]  M_AXI_GP0_AWID_FULL;
+  wire [11:0]  M_AXI_GP0_WID_FULL;
+  wire [11:0]  M_AXI_GP0_ARID_FULL;
+  
+  wire [11:0]  M_AXI_GP0_BID_FULL;
+  wire [11:0]  M_AXI_GP0_RID_FULL;
+  
+  wire [11:0]  M_AXI_GP1_AWID_FULL;
+  wire [11:0]  M_AXI_GP1_WID_FULL;
+  wire [11:0]  M_AXI_GP1_ARID_FULL;
+  
+  wire [11:0]  M_AXI_GP1_BID_FULL;
+  wire [11:0]  M_AXI_GP1_RID_FULL;
+
+  
+  function [5:0] compress_id; 
+  \tinput [11:0] id; 
+  \t\tbegin 
+  \t\t\tcompress_id = id[5:0]; 
+  \t\tend 
+  endfunction 
+  
+  function [11:0] uncompress_id; 
+  \tinput [5:0] id; 
+  \t\tbegin 
+  \t\t    uncompress_id = {6\'b110000, id[5:0]};
+  \t\tend 
+  endfunction
+
+  assign M_AXI_GP0_AWID        = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
+  assign M_AXI_GP0_WID         = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL)  : M_AXI_GP0_WID_FULL;   
+  assign M_AXI_GP0_ARID        = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;      
+  assign M_AXI_GP0_BID_FULL    = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID)     : M_AXI_GP0_BID;
+  assign M_AXI_GP0_RID_FULL    = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID)     : M_AXI_GP0_RID;      
+
+
+  assign M_AXI_GP1_AWID        = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
+  assign M_AXI_GP1_WID         = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL)  : M_AXI_GP1_WID_FULL;   
+  assign M_AXI_GP1_ARID        = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;      
+  assign M_AXI_GP1_BID_FULL    = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID)     : M_AXI_GP1_BID;
+  assign M_AXI_GP1_RID_FULL    = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID)     : M_AXI_GP1_RID;      
+
+
+
+
+  processing_system7_bfm_v2_0_5_interconnect_model icm (
+                 .rstn(net_rstn),
+                 .sw_clk(net_sw_clk),
+
+                 .w_qos_gp0(net_wr_qos_gp0),
+                 .w_qos_gp1(net_wr_qos_gp1),
+                 .w_qos_hp0(net_wr_qos_hp0),
+                 .w_qos_hp1(net_wr_qos_hp1),
+                 .w_qos_hp2(net_wr_qos_hp2),
+                 .w_qos_hp3(net_wr_qos_hp3),
+                                            
+                 .r_qos_gp0(net_rd_qos_gp0),
+                 .r_qos_gp1(net_rd_qos_gp1),
+                 .r_qos_hp0(net_rd_qos_hp0),
+                 .r_qos_hp1(net_rd_qos_hp1),
+                 .r_qos_hp2(net_rd_qos_hp2),
+                 .r_qos_hp3(net_rd_qos_hp3),
+
+              /* GP Slave ports access */
+                 .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0),
+                 .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0),
+                 .wr_data_gp0(net_wr_data_gp0),
+                 .wr_addr_gp0(net_wr_addr_gp0),
+                 .wr_bytes_gp0(net_wr_bytes_gp0),
+                 .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0),
+                 .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0),
+                 .rd_req_ddr_gp0(net_rd_req_ddr_gp0),
+                 .rd_req_ocm_gp0(net_rd_req_ocm_gp0),
+                 .rd_req_reg_gp0(net_rd_req_reg_gp0),
+                 .rd_addr_gp0(net_rd_addr_gp0),
+                 .rd_bytes_gp0(net_rd_bytes_gp0),
+                 .rd_data_ddr_gp0(net_rd_data_ddr_gp0),
+                 .rd_data_ocm_gp0(net_rd_data_ocm_gp0),
+                 .rd_data_reg_gp0(net_rd_data_reg_gp0),
+                 .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0),
+                 .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0),
+                 .rd_dv_reg_gp0(net_rd_dv_reg_gp0),
+
+                 .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1),
+                 .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1),
+                 .wr_data_gp1(net_wr_data_gp1), 
+                 .wr_addr_gp1(net_wr_addr_gp1),
+                 .wr_bytes_gp1(net_wr_bytes_gp1),
+                 .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1),
+                 .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1),
+                 .rd_req_ddr_gp1(net_rd_req_ddr_gp1),
+                 .rd_req_ocm_gp1(net_rd_req_ocm_gp1),
+                 .rd_req_reg_gp1(net_rd_req_reg_gp1),
+                 .rd_addr_gp1(net_rd_addr_gp1),
+                 .rd_bytes_gp1(net_rd_bytes_gp1),
+                 .rd_data_ddr_gp1(net_rd_data_ddr_gp1),
+                 .rd_data_ocm_gp1(net_rd_data_ocm_gp1),
+                 .rd_data_reg_gp1(net_rd_data_reg_gp1),
+                 .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1),
+                 .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1),
+                 .rd_dv_reg_gp1(net_rd_dv_reg_gp1),
+
+              /* HP Slave ports access */
+                 .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0),
+                 .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0),
+                 .wr_data_hp0(net_wr_data_hp0),
+                 .wr_addr_hp0(net_wr_addr_hp0),
+                 .wr_bytes_hp0(net_wr_bytes_hp0),
+                 .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0),
+                 .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0),
+                 .rd_req_ddr_hp0(net_rd_req_ddr_hp0),
+                 .rd_req_ocm_hp0(net_rd_req_ocm_hp0),
+                 .rd_addr_hp0(net_rd_addr_hp0),
+                 .rd_bytes_hp0(net_rd_bytes_hp0),
+                 .rd_data_ddr_hp0(net_rd_data_ddr_hp0),
+                 .rd_data_ocm_hp0(net_rd_data_ocm_hp0),
+                 .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0),
+                 .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0),
+
+                 .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1),
+                 .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1),
+                 .wr_data_hp1(net_wr_data_hp1),
+                 .wr_addr_hp1(net_wr_addr_hp1),
+                 .wr_bytes_hp1(net_wr_bytes_hp1),
+                 .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1),
+                 .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1),
+                 .rd_req_ddr_hp1(net_rd_req_ddr_hp1),
+                 .rd_req_ocm_hp1(net_rd_req_ocm_hp1),
+                 .rd_addr_hp1(net_rd_addr_hp1),
+                 .rd_bytes_hp1(net_rd_bytes_hp1),
+                 .rd_data_ddr_hp1(net_rd_data_ddr_hp1),
+                 .rd_data_ocm_hp1(net_rd_data_ocm_hp1),
+                 .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1),
+                 .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1),
+
+                 .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2),
+                 .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2),
+                 .wr_data_hp2(net_wr_data_hp2),
+                 .wr_addr_hp2(net_wr_addr_hp2),
+                 .wr_bytes_hp2(net_wr_bytes_hp2),
+                 .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2),
+                 .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2),
+                 .rd_req_ddr_hp2(net_rd_req_ddr_hp2),
+                 .rd_req_ocm_hp2(net_rd_req_ocm_hp2),
+                 .rd_addr_hp2(net_rd_addr_hp2),
+                 .rd_bytes_hp2(net_rd_bytes_hp2),
+                 .rd_data_ddr_hp2(net_rd_data_ddr_hp2),
+                 .rd_data_ocm_hp2(net_rd_data_ocm_hp2),
+                 .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2),
+                 .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2),
+
+                 .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3),
+                 .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3),
+                 .wr_data_hp3(net_wr_data_hp3),
+                 .wr_addr_hp3(net_wr_addr_hp3),
+                 .wr_bytes_hp3(net_wr_bytes_hp3),
+                 .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3),
+                 .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3),
+                 .rd_req_ddr_hp3(net_rd_req_ddr_hp3),
+                 .rd_req_ocm_hp3(net_rd_req_ocm_hp3),
+                 .rd_addr_hp3(net_rd_addr_hp3),
+                 .rd_bytes_hp3(net_rd_bytes_hp3),
+                 .rd_data_ddr_hp3(net_rd_data_ddr_hp3),
+                 .rd_data_ocm_hp3(net_rd_data_ocm_hp3),
+                 .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3),
+                 .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3),
+
+                 /* Goes to port 1 of DDR */
+                 .ddr_wr_ack_port1(ddr_wr_ack_port1),
+                 .ddr_wr_dv_port1(ddr_wr_dv_port1),
+                 .ddr_rd_req_port1(ddr_rd_req_port1),
+                 .ddr_rd_dv_port1 (ddr_rd_dv_port1),
+                 .ddr_wr_addr_port1(ddr_wr_addr_port1),
+                 .ddr_wr_data_port1(ddr_wr_data_port1),
+                 .ddr_wr_bytes_port1(ddr_wr_bytes_port1),
+                 .ddr_rd_addr_port1(ddr_rd_addr_port1),
+                 .ddr_rd_data_port1(ddr_rd_data_port1),
+                 .ddr_rd_bytes_port1(ddr_rd_bytes_port1),
+                 .ddr_wr_qos_port1(ddr_wr_qos_port1),
+                 .ddr_rd_qos_port1(ddr_rd_qos_port1),
+                 
+                /* Goes to port2 of DDR */
+                 .ddr_wr_ack_port2 (ddr_wr_ack_port2),
+                 .ddr_wr_dv_port2  (ddr_wr_dv_port2),
+                 .ddr_rd_req_port2 (ddr_rd_req_port2),
+                 .ddr_rd_dv_port2  (ddr_rd_dv_port2),
+                 .ddr_wr_addr_port2(ddr_wr_addr_port2),
+                 .ddr_wr_data_port2(ddr_wr_data_port2),
+                 .ddr_wr_bytes_port2(ddr_wr_bytes_port2),
+                 .ddr_rd_addr_port2(ddr_rd_addr_port2),
+                 .ddr_rd_data_port2(ddr_rd_data_port2),
+                 .ddr_rd_bytes_port2(ddr_rd_bytes_port2),
+                 .ddr_wr_qos_port2 (ddr_wr_qos_port2),
+                 .ddr_rd_qos_port2 (ddr_rd_qos_port2),
+                
+                /* Goes to port3 of DDR */
+                 .ddr_wr_ack_port3 (ddr_wr_ack_port3),
+                 .ddr_wr_dv_port3  (ddr_wr_dv_port3),
+                 .ddr_rd_req_port3 (ddr_rd_req_port3),
+                 .ddr_rd_dv_port3  (ddr_rd_dv_port3),
+                 .ddr_wr_addr_port3(ddr_wr_addr_port3),
+                 .ddr_wr_data_port3(ddr_wr_data_port3),
+                 .ddr_wr_bytes_port3(ddr_wr_bytes_port3),
+                 .ddr_rd_addr_port3(ddr_rd_addr_port3),
+                 .ddr_rd_data_port3(ddr_rd_data_port3),
+                 .ddr_rd_bytes_port3(ddr_rd_bytes_port3),
+                 .ddr_wr_qos_port3 (ddr_wr_qos_port3),
+                 .ddr_rd_qos_port3 (ddr_rd_qos_port3),
+
+                /* Goes to port 0 of OCM */
+                 .ocm_wr_ack_port1 (ocm_wr_ack_port1),
+                 .ocm_wr_dv_port1  (ocm_wr_dv_port1),
+                 .ocm_rd_req_port1 (ocm_rd_req_port1),
+                 .ocm_rd_dv_port1  (ocm_rd_dv_port1),
+                 .ocm_wr_addr_port1(ocm_wr_addr_port1),
+                 .ocm_wr_data_port1(ocm_wr_data_port1),
+                 .ocm_wr_bytes_port1(ocm_wr_bytes_port1),
+                 .ocm_rd_addr_port1(ocm_rd_addr_port1),
+                 .ocm_rd_data_port1(ocm_rd_data_port1),
+                 .ocm_rd_bytes_port1(ocm_rd_bytes_port1),
+                 .ocm_wr_qos_port1(ocm_wr_qos_port1),
+                 .ocm_rd_qos_port1(ocm_rd_qos_port1), 
+
+                /* Goes to port 0 of REG */
+                 .reg_rd_qos_port1 (reg_rd_qos_port1) ,
+                 .reg_rd_req_port1 (reg_rd_req_port1),
+                 .reg_rd_dv_port1  (reg_rd_dv_port1),
+                 .reg_rd_addr_port1(reg_rd_addr_port1),
+                 .reg_rd_data_port1(reg_rd_data_port1),
+                 .reg_rd_bytes_port1(reg_rd_bytes_port1)
+                 ); 
+
+  processing_system7_bfm_v2_0_5_ddrc ddrc (
+           .rstn(net_rstn),
+           .sw_clk(net_sw_clk),
+          
+          /* Goes to port 0 of DDR */
+           .ddr_wr_ack_port0 (ddr_wr_ack_port0),
+           .ddr_wr_dv_port0  (ddr_wr_dv_port0),
+           .ddr_rd_req_port0 (ddr_rd_req_port0),
+           .ddr_rd_dv_port0  (ddr_rd_dv_port0),
+
+           .ddr_wr_addr_port0(net_wr_addr_acp),
+           .ddr_wr_data_port0(net_wr_data_acp),
+           .ddr_wr_bytes_port0(net_wr_bytes_acp),
+
+           .ddr_rd_addr_port0(net_rd_addr_acp),
+           .ddr_rd_bytes_port0(net_rd_bytes_acp),
+           
+           .ddr_rd_data_port0(ddr_rd_data_port0),
+
+           .ddr_wr_qos_port0 (net_wr_qos_acp),
+           .ddr_rd_qos_port0 (net_rd_qos_acp),
+          
+          
+          /* Goes to port 1 of DDR */
+           .ddr_wr_ack_port1 (ddr_wr_ack_port1),
+           .ddr_wr_dv_port1  (ddr_wr_dv_port1),
+           .ddr_rd_req_port1 (ddr_rd_req_port1),
+           .ddr_rd_dv_port1  (ddr_rd_dv_port1),
+           .ddr_wr_addr_port1(ddr_wr_addr_port1),
+           .ddr_wr_data_port1(ddr_wr_data_port1),
+           .ddr_wr_bytes_port1(ddr_wr_bytes_port1),
+           .ddr_rd_addr_port1(ddr_rd_addr_port1),
+           .ddr_rd_data_port1(ddr_rd_data_port1),
+           .ddr_rd_bytes_port1(ddr_rd_bytes_port1),
+           .ddr_wr_qos_port1 (ddr_wr_qos_port1),
+           .ddr_rd_qos_port1 (ddr_rd_qos_port1),
+          
+          /* Goes to port2 of DDR */
+           .ddr_wr_ack_port2 (ddr_wr_ack_port2),
+           .ddr_wr_dv_port2  (ddr_wr_dv_port2),
+           .ddr_rd_req_port2 (ddr_rd_req_port2),
+           .ddr_rd_dv_port2  (ddr_rd_dv_port2),
+           .ddr_wr_addr_port2(ddr_wr_addr_port2),
+           .ddr_wr_data_port2(ddr_wr_data_port2),
+           .ddr_wr_bytes_port2(ddr_wr_bytes_port2),
+           .ddr_rd_addr_port2(ddr_rd_addr_port2),
+           .ddr_rd_data_port2(ddr_rd_data_port2),
+           .ddr_rd_bytes_port2(ddr_rd_bytes_port2),
+           .ddr_wr_qos_port2 (ddr_wr_qos_port2),
+           .ddr_rd_qos_port2 (ddr_rd_qos_port2),
+          
+          /* Goes to port3 of DDR */
+           .ddr_wr_ack_port3 (ddr_wr_ack_port3),
+           .ddr_wr_dv_port3  (ddr_wr_dv_port3),
+           .ddr_rd_req_port3 (ddr_rd_req_port3),
+           .ddr_rd_dv_port3  (ddr_rd_dv_port3),
+           .ddr_wr_addr_port3(ddr_wr_addr_port3),
+           .ddr_wr_data_port3(ddr_wr_data_port3),
+           .ddr_wr_bytes_port3(ddr_wr_bytes_port3),
+           .ddr_rd_addr_port3(ddr_rd_addr_port3),
+           .ddr_rd_data_port3(ddr_rd_data_port3),
+           .ddr_rd_bytes_port3(ddr_rd_bytes_port3),
+           .ddr_wr_qos_port3 (ddr_wr_qos_port3),
+           .ddr_rd_qos_port3 (ddr_rd_qos_port3)
+          
+            );
+
+  processing_system7_bfm_v2_0_5_ocmc ocmc (
+           .rstn(net_rstn),
+           .sw_clk(net_sw_clk),
+    
+    /* Goes to port 0 of OCM */
+           .ocm_wr_ack_port0 (ocm_wr_ack_port0),
+           .ocm_wr_dv_port0  (ocm_wr_dv_port0),
+           .ocm_rd_req_port0 (ocm_rd_req_port0),
+           .ocm_rd_dv_port0  (ocm_rd_dv_port0),
+
+           .ocm_wr_addr_port0(net_wr_addr_acp),
+           .ocm_wr_data_port0(net_wr_data_acp),
+           .ocm_wr_bytes_port0(net_wr_bytes_acp),
+
+           .ocm_rd_addr_port0(net_rd_addr_acp),
+           .ocm_rd_bytes_port0(net_rd_bytes_acp),
+           
+           .ocm_rd_data_port0(ocm_rd_data_port0),
+
+           .ocm_wr_qos_port0 (net_wr_qos_acp),
+           .ocm_rd_qos_port0 (net_rd_qos_acp),
+          
+            /* Goes to port 1 of OCM */
+           .ocm_wr_ack_port1 (ocm_wr_ack_port1),
+           .ocm_wr_dv_port1  (ocm_wr_dv_port1),
+           .ocm_rd_req_port1 (ocm_rd_req_port1),
+           .ocm_rd_dv_port1  (ocm_rd_dv_port1),
+           .ocm_wr_addr_port1(ocm_wr_addr_port1),
+           .ocm_wr_data_port1(ocm_wr_data_port1),
+           .ocm_wr_bytes_port1(ocm_wr_bytes_port1),
+           .ocm_rd_addr_port1(ocm_rd_addr_port1),
+           .ocm_rd_data_port1(ocm_rd_data_port1),
+           .ocm_rd_bytes_port1(ocm_rd_bytes_port1),
+           .ocm_wr_qos_port1(ocm_wr_qos_port1),
+           .ocm_rd_qos_port1(ocm_rd_qos_port1) 
+    
+  );
+
+  processing_system7_bfm_v2_0_5_regc regc (
+           .rstn(net_rstn),
+           .sw_clk(net_sw_clk),
+    
+            /* Goes to port 0 of REG */
+           .reg_rd_req_port0 (reg_rd_req_port0),
+           .reg_rd_dv_port0  (reg_rd_dv_port0),
+           .reg_rd_addr_port0(net_rd_addr_acp),
+           .reg_rd_bytes_port0(net_rd_bytes_acp),
+           .reg_rd_data_port0(reg_rd_data_port0),
+           .reg_rd_qos_port0 (net_rd_qos_acp),
+          
+            /* Goes to port 1 of REG */
+           .reg_rd_req_port1 (reg_rd_req_port1),
+           .reg_rd_dv_port1  (reg_rd_dv_port1),
+           .reg_rd_addr_port1(reg_rd_addr_port1),
+           .reg_rd_data_port1(reg_rd_data_port1),
+           .reg_rd_bytes_port1(reg_rd_bytes_port1),
+           .reg_rd_qos_port1(reg_rd_qos_port1) 
+    
+  );
+ 
+  /* include axi_gp port instantiations */
+  `include ""processing_system7_bfm_v2_0_5_axi_gp.v""
+
+  /* include axi_hp port instantiations */
+  `include ""processing_system7_bfm_v2_0_5_axi_hp.v""
+
+  /* include axi_acp port instantiations */
+  `include ""processing_system7_bfm_v2_0_5_axi_acp.v""
+
+endmodule
+
+
+"
+"// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
+// Date        : Thu Feb 02 02:37:11 2017
+// Host        : TheMosass-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_stub.v
+// Design      : design_1_axi_gpio_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z010clg400-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""axi_gpio,Vivado 2016.4"" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio2_io_i)
+/* synthesis syn_black_box black_box_pad_pin=""s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[3:0],gpio2_io_i[3:0]"" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output ip2intc_irpt;
+  input [3:0]gpio_io_i;
+  input [3:0]gpio2_io_i;
+endmodule
+"
+"// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, ""Critical
+// Applications""). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
+// IP Revision: 11
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = ""yes"" *)
+module design_1_auto_pc_0 (
+  aclk,
+  aresetn,
+  s_axi_awid,
+  s_axi_awaddr,
+  s_axi_awlen,
+  s_axi_awsize,
+  s_axi_awburst,
+  s_axi_awlock,
+  s_axi_awcache,
+  s_axi_awprot,
+  s_axi_awqos,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wlast,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bid,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_arid,
+  s_axi_araddr,
+  s_axi_arlen,
+  s_axi_arsize,
+  s_axi_arburst,
+  s_axi_arlock,
+  s_axi_arcache,
+  s_axi_arprot,
+  s_axi_arqos,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rid,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rlast,
+  s_axi_rvalid,
+  s_axi_rready,
+  m_axi_awaddr,
+  m_axi_awprot,
+  m_axi_awvalid,
+  m_axi_awready,
+  m_axi_wdata,
+  m_axi_wstrb,
+  m_axi_wvalid,
+  m_axi_wready,
+  m_axi_bresp,
+  m_axi_bvalid,
+  m_axi_bready,
+  m_axi_araddr,
+  m_axi_arprot,
+  m_axi_arvalid,
+  m_axi_arready,
+  m_axi_rdata,
+  m_axi_rresp,
+  m_axi_rvalid,
+  m_axi_rready
+);
+
+(* X_INTERFACE_INFO = ""xilinx.com:signal:clock:1.0 CLK CLK"" *)
+input wire aclk;
+(* X_INTERFACE_INFO = ""xilinx.com:signal:reset:1.0 RST RST"" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWID"" *)
+input wire [11 : 0] s_axi_awid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWADDR"" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWLEN"" *)
+input wire [3 : 0] s_axi_awlen;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"" *)
+input wire [2 : 0] s_axi_awsize;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWBURST"" *)
+input wire [1 : 0] s_axi_awburst;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"" *)
+input wire [1 : 0] s_axi_awlock;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"" *)
+input wire [3 : 0] s_axi_awcache;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWPROT"" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWQOS"" *)
+input wire [3 : 0] s_axi_awqos;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWVALID"" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI AWREADY"" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WID"" *)
+input wire [11 : 0] s_axi_wid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WDATA"" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WSTRB"" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WLAST"" *)
+input wire s_axi_wlast;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WVALID"" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI WREADY"" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BID"" *)
+output wire [11 : 0] s_axi_bid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BRESP"" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BVALID"" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI BREADY"" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARID"" *)
+input wire [11 : 0] s_axi_arid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARADDR"" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARLEN"" *)
+input wire [3 : 0] s_axi_arlen;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"" *)
+input wire [2 : 0] s_axi_arsize;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARBURST"" *)
+input wire [1 : 0] s_axi_arburst;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"" *)
+input wire [1 : 0] s_axi_arlock;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"" *)
+input wire [3 : 0] s_axi_arcache;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARPROT"" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARQOS"" *)
+input wire [3 : 0] s_axi_arqos;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARVALID"" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI ARREADY"" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RID"" *)
+output wire [11 : 0] s_axi_rid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RDATA"" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RRESP"" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RLAST"" *)
+output wire s_axi_rlast;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RVALID"" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 S_AXI RREADY"" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWADDR"" *)
+output wire [31 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWPROT"" *)
+output wire [2 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWVALID"" *)
+output wire m_axi_awvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI AWREADY"" *)
+input wire m_axi_awready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WDATA"" *)
+output wire [31 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WSTRB"" *)
+output wire [3 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WVALID"" *)
+output wire m_axi_wvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI WREADY"" *)
+input wire m_axi_wready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BRESP"" *)
+input wire [1 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BVALID"" *)
+input wire m_axi_bvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI BREADY"" *)
+output wire m_axi_bready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARADDR"" *)
+output wire [31 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARPROT"" *)
+output wire [2 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARVALID"" *)
+output wire m_axi_arvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI ARREADY"" *)
+input wire m_axi_arready;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RDATA"" *)
+input wire [31 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RRESP"" *)
+input wire [1 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RVALID"" *)
+input wire m_axi_rvalid;
+(* X_INTERFACE_INFO = ""xilinx.com:interface:aximm:1.0 M_AXI RREADY"" *)
+output wire m_axi_rready;
+
+  axi_protocol_converter_v2_1_11_axi_protocol_converter #(
+    .C_FAMILY(""zynq""),
+    .C_M_AXI_PROTOCOL(2),
+    .C_S_AXI_PROTOCOL(1),
+    .C_IGNORE_ID(0),
+    .C_AXI_ID_WIDTH(12),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(32),
+    .C_AXI_SUPPORTS_WRITE(1),
+    .C_AXI_SUPPORTS_READ(1),
+    .C_AXI_SUPPORTS_USER_SIGNALS(0),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_TRANSLATION_MODE(2)
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awregion(4\'H0),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(1\'H0),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wid(s_axi_wid),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(1\'H0),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arregion(4\'H0),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(1\'H0),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .m_axi_awid(),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awregion(),
+    .m_axi_awqos(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wid(),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(12\'H000),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(1\'H0),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready),
+    .m_axi_arid(),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arregion(),
+    .m_axi_arqos(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(12\'H000),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(1\'H1),
+    .m_axi_ruser(1\'H0),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+  );
+endmodule
+"
+"// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
+
+// Digital model of a traffic light
+// By Dan Hyde August 10, 1995
+module traffic;
+parameter on = 1, off = 0, red_tics = 35, 
+          amber_tics = 3, green_tics = 20;
+reg clock, red, amber, green;
+
+// will stop the simulation after 1000 time units
+initial begin: stop_at
+   #1000; $stop;    
+end
+
+// initialize the lights and set up monitoring of registers
+initial begin: Init
+    red = off; amber = off; green = off;
+    $display(""                 Time green amber red"");  
+    $monitor(""%3d    %b     %b    %b"", $time, green, amber, red);
+end
+
+// task to wait for \'tics\' positive edge clocks
+// before turning light off
+task light;
+   output color;
+   input [31:0] tics;
+   begin
+      repeat(tics)  // wait to detect tics positive edges on clock
+         @(posedge clock);
+      color = off;
+   end
+endtask
+
+// waveform for clock period of 2 time units
+always begin: clock_wave
+  #1 clock = 0;
+  #1 clock = 1;
+end
+
+always begin: main_process
+   red = on;
+   light(red, red_tics);  // call task to wait 
+   green = on;
+   light(green, green_tics);
+   amber = on;
+   light(amber, amber_tics);
+end
+
+endmodule
+"
+"/*
+ * In Verilog, the following two lines are both valid syntax:
+ *
+ * `define GUEST
+ * `define GUEST <value>
+ *
+ * The first defines ""GUEST"" as existing, but with no assigned 
+ * value.  The second defines ""GUEST"" as existing with an 
+ * assigned value.  Ctags55 correctly handles both cases, but 
+ * Ctags551 - Ctags554 only handles the `define with value 
+ * correctly.  Here is some test code to demonstrate this:
+ */
+`define HOSTA
+`define HOSTB
+`define HOSTC
+`define HOSTD
+
+`define GUESTA 1
+`define GUESTB 2
+`define GUESTC 3
+`define GUESTD 4
+/*
+ * Ctags55 correctly generates a tag for all `defines in the 
+ * code, but Ctags554 does not generate tags for ""HOSTB"" 
+ * or ""HOSTD"".
+ */
+"
+"/**************************************************************************
+****
+* test task one
+* the line below has 53 asteriks
+*****************************************************/
+task pass_task_1;
+begin
+end
+endtask
+
+/**************************************************************************
+****
+* test task one
+* the line below has 54 asteriks
+******************************************************/
+task fail_task_2;
+begin
+end
+endtask
+
+/**************************************************************************
+****
+* test function one
+* the line below has 53 asteriks
+*****************************************************/
+function pass_func_1;
+begin
+end
+endfunction
+
+/**************************************************************************
+****
+* test function two
+* the line below has 54 asteriks
+******************************************************/
+function fail_func_2;
+begin
+end
+endfunction
+
+/**************************************************************************
+****
+* test function one
+* the line below has 53 asteriks
+*****************************************************/
+`define pass_define_1 1'b1;
+
+/**************************************************************************
+****
+* test function two
+* the line below has 54 asteriks
+******************************************************/
+`define fail_define_2 1'b1;
+"
+"/*
+Bugs item #762027, was opened at 2003-06-27 18:32
+Message generated for change (Tracker Item Submitted) made by Item Submitter
+You can respond by visiting: 
+https://sourceforge.net/tracker/?func=detail&atid=106556&aid=762027&group_id=6556
+
+Category: None
+Group: None
+Status: Open
+Resolution: None
+Priority: 5
+Submitted By: cdic (cdic)
+Assigned to: Nobody/Anonymous (nobody)
+Summary: multi-line definition w/o back-slash will be missing
+
+Initial Comment:
+There is a small bug (language verilog):
+*/
+     wire N_84, N_83;     // is ok.
+  
+     wire N_84,
+          N_83;     // then N_83 will be missing in tags.
+/*
+Thanks for fixing it.
+
+cdic
+*/
+"
+"// Include module declaration in a comment
+// module wrong;
+// endmodule
+`define DEFINE
+`define DEF_WITH_EQ = 1'd100
+`define DEF_VALUE   1'd100
+
+module mod#(
+    parameter PARAM1 = 10,
+    parameter PARAM2 = 2.0
+) (
+    input wire a,
+    b,c,
+    d ,
+    output wire e ,
+    output reg f,
+    inout wire g
+);
+
+localparam LOCALPARAM = 2**2;
+
+localparam STATE1 = 4'h0,
+           STATE2 = 4'h1,
+           STATE3 = 4'h2,
+           STATE4 = 4'h5    ,
+           STATE5 = 4'h6    ,
+           STATE6 = 4'h7    ,
+           STATE7 = 4'h8;
+
+real k;
+integer l;
+reg signed [3:0] scounter;
+
+task add (
+    input x, y,
+    output z
+);
+    z = x + y;
+endtask
+
+function integer mult (
+    input x,
+    input y);
+    mult = x * y;
+endfunction
+
+function [1:0] func_with_range (k, l);
+    func_with_range = {k, l};
+endfunction
+
+endmodule // mod
+"
+"// somewhat contrived, but i came across a real-life file that caused this
+// crash.
+value=
+hello/
+world;
+"
+"// Include module declaration in a comment
+// module wrong;
+// endmodule
+`define DEFINE
+
+`define DEF_WITH_EQ = 1'd100
+`define DEF_VALUE   1'd100
+
+parameter PARAM = 1;
+
+localparam LOCALPARAM = 2**2;
+
+localparam STATE1 = 4'h0,
+           STATE2 = 4'h1,
+           STATE3 = 4'h2,
+           STATE4 = 4'h5    ,
+           STATE5 = 4'h6    ,
+           STATE6 = 4'h7    ,
+           STATE7 = 4'h8;
+
+wire a,b,c,d,e;
+reg f;
+wire g;
+real k;
+integer l;
+
+initial begin
+    add(a, b, f);
+end
+
+task add;
+    input x, y;
+    output z;
+begin
+    z = x + y;
+end
+endtask
+
+function mult;
+    input x;
+    input y;
+begin
+    mult = x * y;
+end
+endfunction
+"
+"parameter ramaddr_0 = {1'b1,9'd0};
+"
+"// File example.v
+//
+// Below is an example of a comment that is mis-parsed by exuberant ctags.
+// It uses the multi-line comment format, i.e. /* ... */ except that in
+// this case, the character sequence immediately preceeding the closing
+// delimiter is an asterisk. (Any even number of asterisks would have the
+// same problem.
+// The line immediately afterwards is used to demonstrate the problem.
+// the module name 'wahoo' isn't recognised, because the parser mistakenly
+// thinks we are still in a multi-line comment.
+/*
+ * I am a multi-line comment
+ * I happen to end in a strange
+ * (but legal) way: **/
+module wahoo ()
+begin
+end
+"
+"/*
+*
+**/
+module top(outsig, insig);
+output outsig;
+input insig;
+assign outsig = insig;
+endmodule
+"
+"// Taken from http://www.europa.com/~celiac/fsm_samp.html
+
+// These are the symbolic names for states
+parameter  [1:0]       //synopsys enum state_info
+  S0 = 2'h0,
+  S1 = 2'h1,
+  S2 = 2'h2,
+  S3 = 2'h3;
+
+// These are the current state and next state variables
+reg [1:0] /* synopsys enum state_info */ state;
+reg [1:0] /* synopsys enum state_info */ next_state;
+ 
+ 
+// synopsys state_vector state
+
+always @ (state or y or x)
+begin 
+  next_state = state;
+  case (state)                 // synopsys full_case parallel_case
+    S0: begin 
+      if (x) begin 
+        next_state = S1;
+      end
+      else begin 
+
+        next_state = S2;
+      end
+    end
+    S1: begin 
+      if (y) begin 
+        next_state = S2;
+      end
+      else begin 
+        next_state = S0;
+      end
+    end
+    S2: begin 
+      if (x & y) begin 
+        next_state = S3;
+      end
+      else begin 
+        next_state = S0;
+      end
+    end
+    S3: begin 
+      next_state = S0;
+    end
+  endcase
+end
+
+
+always @ (posedge clk or posedge reset)
+begin 
+  if (reset) begin 
+    state <= S0;
+  end
+  else begin 
+    state <= next_state;
+  end
+end
+"
+"// Include module declaration in a comment
+// module wrong;
+// endmodule
+`define DEFINE
+
+module mod (
+    a,
+    b,c,
+    d , e ,
+    f,
+    g
+);
+
+parameter PARAM = 1;
+
+input a,b, c, d ;
+output e;
+output f;
+inout g;
+
+wire a,b,c,d,e;
+reg f;
+wire g;
+real k;
+integer l;
+
+task add;
+    input x, y;
+"
+"input
+"
+"// Include module declaration in a comment
+// module wrong;
+// endmodule
+`define DEFINE
+`define DEF_WITH_EQ = 1'd100
+`define DEF_VALUE   1'd100
+
+module mod (
+    a,
+    b,c,
+    d , e ,
+    `ifdef DEFINE
+    f,
+    `endif
+    g
+);
+
+parameter PARAM = 1;
+
+parameter STATE1 = 4'h0,
+          STATE2 = 4'h1,
+          STATE3 = 4'h2,
+          STATE4 = 4'h5    ,
+          STATE5 = 4'h6    ,
+          STATE6 = 4'h7    ,
+          STATE7 = 4'h8;
+
+input a,b, c, d ;
+output e;
+output f;
+inout g;
+
+wire a,b,c,d,e;
+reg f;
+wire g;
+real k;
+integer l;
+
+task add;
+    input x, y;
+    output z;
+begin
+    z = x + y;
+end
+endtask
+
+function mult;
+    input x;
+    input y;
+begin
+    mult = x * y;
+end
+endfunction
+
+wire [PARAM1-1:0] mynet;
+
+genvar gencnt;
+generate
+    for (gencnt = 0; gencnt < PARAM1; gencnt = gencnt + 1) begin: array
+        assign mynet[gencnt] = 1'b0;
+    end
+endgenerate
+
+endmodule // mod
+"
+"/******************** (C) COPYRIGHT 2011 e-Design Co.,Ltd. *********************
+
+                          DS203 FIFO main control module  
+
+ Version   : FPGA CFG Ver 2.x                                     Author : bure
+
+********************************************************************************
+\xb0\xe6\xb1\xbe\xd0\xde\xb8\xc4\xcb\xb5\xc3\xf7\xa3\xba
+ FPGA_V2.3: 1. \xd0\xde\xb8\xc4\xc1\xcb\xcd\xac\xb2\xbd\xb4\xa5\xb7\xa2\xc4\xa3\xbf\xe9\xb5\xc4\xc2\xdf\xbc\xad\xbd\xe1\xb9\xb9 
+            2. \xd3\xc5\xbb\xaf\xc1\xcbFIFO\xb6\xc1\xd0\xb4\xb5\xd8\xd6\xb7\xbf\xd8\xd6\xc6\xb5\xc4\xc2\xdf\xbc\xad\xbd\xe1\xb9\xb9
+ FPGA_V2.4: 1. \xd4\xf6\xbc\xd3\xc1\xcb4\xb8\xf6\xcd\xa8\xb5\xc0\xb6\xc0\xc1\xa2\xb5\xc4\xc6\xb5\xc2\xca\xba\xcd\xc2\xf6\xbf\xed\xbc\xc6\xc1\xbf
+            2. \xd0\xde\xb8\xc4\xc1\xcb\xc2\xf6\xbf\xed\xb4\xa5\xb7\xa2\xb5\xc41\xb8\xf6BUG
+ FPGA_V2.5: 1. \xd4\xf6\xbc\xd3\xc1\xcb\xb2\xc9\xd1\xf9\xc9\xee\xb6\xc8\xbf\xc9\xc9\xe8\xd6\xc3\xb5\xc4\xb9\xa6\xc4\xdc
+            2. \xd4\xf6\xbc\xd3\xc1\xcb\xd4\xa4\xb2\xc9\xd1\xf9\xc9\xee\xb6\xc8\xbf\xc9\xc9\xe8\xd6\xc3\xb5\xc4\xb9\xa6\xc4\xdc
+            3. \xd4\xf6\xbc\xd3\xc1\xcb\xd1\xd3\xb3\xd9\xb4\xa5\xb7\xa2\xb2\xc9\xd1\xf9\xbf\xc9\xc9\xe8\xd6\xc3\xb5\xc4\xb9\xa6\xc4\xdc
+*******************************************************************************/
+
+module FIFO( ClrW, MCI, nRD, CE, H_L, C_D, SCK, SDA, Din, 
+             nPD, CKA, CKB, DB);
+
+  input\t  ClrW;               // FIFO status reset       -> Active high 
+  input\t  MCI;                // Main clock input        -> rising edge 
+  input\t  nRD;                // FIFO read clock         -> falling edge
+  input\t  CE;                 // FIFO bus enable         -> Active high
+  input\t  H_L;                // 1 = [17:16]Dout->[ 1:0]DB, 0 = [15:0]Dout->[15:0]DB
+  input\t  C_D;                // 1 = [15:0]Data->[15:0]DB
+  input\t  SCK;                // Serial input clock    -> rising edge 
+  input\t  SDA;                // Serial input data 
+  input\t  [17:0]Din;          // FIFO write data
+
+  output  nPD;                // ADC Power down Output
+  output  CKA;                // Clock_A
+  output  CKB;                // Clock_B
+
+  inout   [15:0]DB;           // FIFO output data bus
+  
+  wire\t  [11:0]R_Addr_Bus;   // current read address
+  wire\t  [11:0]W_Addr_Bus;   // current Writen address 
+  wire\t  [17:0]Dout_Bus;     // Internal data output Bus 
+  wire\t  [17:0]Din_Bus;      // Internal data input Bus 
+  wire\t  [ 7:0]Tm_Link;  
+  wire\t  [ 7:0]Vt_Link;      
+  wire\t  [15:0]Tt_Link;     
+  wire\t  [ 7:0]Ctrl_Link;
+  wire\t  Start_Link;
+  wire\t  Full_Link;
+  wire\t  Empty_Link;
+  wire\t  Sampled_Link;
+  wire\t  Ready_Link;
+  wire\t  [15:0]A_Edge_Link;
+  wire\t  [15:0]A_TL_Link;
+  wire\t  [15:0]A_TH_Link;   
+  wire\t  [15:0]B_Edge_Link;
+  wire\t  [15:0]B_TL_Link;
+  wire\t  [15:0]B_TH_Link;  
+  wire\t  [15:0]C_Edge_Link;
+  wire\t  [15:0]C_TL_Link;
+  wire\t  [15:0]C_TH_Link; 
+  wire\t  [15:0]D_Edge_Link;
+  wire\t  [15:0]D_TL_Link;
+  wire\t  [15:0]D_TH_Link; 
+  wire\t  [11:0]Depth_Link; 
+  wire\t  [11:0]PerCnt_Link; 
+  wire\t  [31:0]Delay_Link;
+
+  assign Din_Bus = { Din[17:16], ~Din[15:8], ~Din[7:0] };
+
+  AddrCtrl\tU1(
+    .ClrW( ClrW ),
+    .Wclk( MCI ),
+    .Start( Start_Link ),
+    .nRclk( nRD ),
+    .RE( CE ),
+    .H_L( H_L ),
+    .Depth( Depth_Link ), 
+    .PerCnt( PerCnt_Link ), 
+    .Delay( Delay_Link ),
+    .Ready( Ready_Link ), 
+    .Sampled(Sampled_Link),
+    .Full( Full_Link ),
+    .Empty( Empty_Link ),
+    .Rptr( R_Addr_Bus ),
+    .Wptr( W_Addr_Bus )
+  );
+  
+  DP_RAM\tU2(
+    .Wclk( MCI ),
+    .nRclk( nRD ),
+    .Din( Din_Bus ),
+    .Raddr( R_Addr_Bus ),
+    .Waddr( W_Addr_Bus ),
+    .Dout( Dout_Bus )
+  );
+                   
+  Signal U3(
+    .Reset( ClrW ),
+    .Mclk( MCI ),         
+    .Trigg_Mode( Tm_Link ), 
+    .Vthreshold( Vt_Link ), 
+    .Tthreshold( Tt_Link ), 
+    .Din( Din_Bus ),
+    .Sampled(Sampled_Link),
+    .CtrlReg( Ctrl_Link ),
+    .Start( Start_Link ),
+    .ClkA( CKA ),
+    .ClkB( CKB ),
+    .A_Edge( A_Edge_Link ),
+    .A_TL( A_TL_Link ),
+    .A_TH( A_TH_Link ),   
+    .B_Edge( B_Edge_Link ),
+    .B_TL( B_TL_Link ),
+    .B_TH( B_TH_Link ),   
+    .C_Edge( C_Edge_Link ),
+    .C_TL( C_TL_Link ),
+    .C_TH( C_TH_Link ),   
+    .D_Edge( D_Edge_Link ),
+    .D_TL( D_TL_Link ),
+    .D_TH( D_TH_Link )   
+  );
+
+  IO_Ctrl U4( 
+    .CE( CE ), 
+    .nRD( nRD ), 
+    .SCK( SCK ), 
+    .SDA( SDA ), 
+    .Dout( Dout_Bus ),  
+    .Start( Start_Link ),
+    .Full( Full_Link ),
+    .Empty( Empty_Link ),
+    .H_L( H_L ), 
+    .C_D( C_D ), 
+    .Ready( Ready_Link ), 
+    .A_Edge( A_Edge_Link ),
+    .A_TL( A_TL_Link ),
+    .A_TH( A_TH_Link ),   
+    .B_Edge( B_Edge_Link ),
+    .B_TL( B_TL_Link ),
+    .B_TH( B_TH_Link ),   
+    .C_Edge( C_Edge_Link ),
+    .C_TL( C_TL_Link ),
+    .C_TH( C_TH_Link ),   
+    .D_Edge( D_Edge_Link ),
+    .D_TL( D_TL_Link ),
+    .D_TH( D_TH_Link ),   
+    .Depth( Depth_Link ), 
+    .PerCnt( PerCnt_Link ), 
+    .Delay( Delay_Link ),
+    .nPD( nPD ),
+    .Trigg_Mode( Tm_Link ), 
+    .Vthreshold( Vt_Link ), 
+    .Tthreshold( Tt_Link ), 
+    .CtrlReg( Ctrl_Link ),
+    .DB( DB ) 
+  );
+  
+endmodule
+ "
+"/********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ********************
+                     Sync signal select and control module  
+ Version   : FPGA CFG Ver 2.x                                     Author : bure
+*******************************************************************************/
+
+module Signal( Reset, Mclk, Trigg_Mode, Vthreshold, Tthreshold, Din, 
+               Sampled, CtrlReg,
+               Start, ClkA, ClkB, 
+               A_Edge, A_TL, A_TH, B_Edge, B_TL, B_TH, 
+               C_Edge, C_TL, C_TH, D_Edge, D_TL, D_TH, );
+
+  input   Reset;              // Trigger status rst    -> Active high 
+  input   Mclk;               // main clock
+  input   [ 7:0]Trigg_Mode;   // Trigger Mode 
+  input   [ 7:0]Vthreshold;   // Trigger voltage threshold 
+  input   [15:0]Tthreshold;   // Trigger time threshold 
+  input   [17:0]Din;          // 0~7:CH_A, 8~15:CH_B, 16:CH_C, 17:CH_D
+  input   Sampled;
+  input   [ 7:0]CtrlReg;      // bit0=nPD, bit1=Mode, 
+
+  output  Start;              // Sync start            -> Active high 
+  output  ClkA;               // Clock_A for ADC CH_A
+  output  ClkB;               // Clock_B for ADC CH_B
+  
+  output  [15:0]A_Edge;       // CH_A edge counter
+  output  [15:0]A_TL;         // CH_A 
+  output  [15:0]A_TH;         // CH_A 
+  
+  output  [15:0]B_Edge;       // CH_B edge counter
+  output  [15:0]B_TL;         // CH_B 
+  output  [15:0]B_TH;         // CH_B 
+  
+  output  [15:0]C_Edge;       // CH_C edge counter
+  output  [15:0]C_TL;         // CH_C 
+  output  [15:0]C_TH;         // CH_C 
+  
+  output  [15:0]D_Edge;       // CH_D edge counter
+  output  [15:0]D_TL;         // CH_D 
+  output  [15:0]D_TH;         // CH_D 
+  
+  reg     Start;
+  wire    [ 8:0]Delta_V1;
+  wire    [ 8:0]Delta_V2;
+  wire    [ 8:0]Delta_V3;
+  wire    [ 8:0]Delta_V4;
+
+  reg     A_Flag;
+  reg     A_Status;
+  reg     A_Dt_L;
+  reg     A_Dt_H;
+  reg     A_Ut_L;
+  reg     A_Ut_H;
+  reg     [11:0]A_Cnt;
+  reg     [15:0]A_Edge;
+  reg     [15:0]A_TL;
+  reg     [15:0]A_TH; 
+   
+  reg     B_Flag;
+  reg     B_Status;
+  reg     B_Dt_L;
+  reg     B_Dt_H;
+  reg     B_Ut_L;
+  reg     B_Ut_H;
+  reg     [11:0]B_Cnt;
+  reg     [15:0]B_Edge;
+  reg     [15:0]B_TL;
+  reg     [15:0]B_TH; 
+  
+  reg     C_Flag;
+  reg     C_Dt_L;
+  reg     C_Dt_H;
+  reg     C_Ut_L;
+  reg     C_Ut_H;
+  reg     [11:0]C_Cnt;
+  reg     [15:0]C_Edge;
+  reg     [15:0]C_TL;
+  reg     [15:0]C_TH; 
+  
+  reg     D_Flag;
+  reg     D_Dt_L;
+  reg     D_Dt_H;
+  reg     D_Ut_L;
+  reg     D_Ut_H;
+  reg     [11:0]D_Cnt;
+  reg     [15:0]D_Edge;
+  reg     [15:0]D_TL;
+  reg     [15:0]D_TH; 
+  
+  assign ClkA = Mclk; 
+  assign ClkB = CtrlReg[1] ? ( ~Mclk ) : ( Mclk );
+  
+  assign  Delta_V1 = Vthreshold + 12;
+  assign  Delta_V2 = Vthreshold - 12;
+  assign  Delta_V3 = Vthreshold + 1;
+  assign  Delta_V4 = Vthreshold - 1;
+  
+  always @( posedge Mclk or posedge Reset ) begin
+
+    if ( Reset ) begin 
+      Start    <= 0;
+      A_Dt_L   <= 0;
+      A_Dt_H   <= 0;
+      A_Ut_L   <= 0;
+      A_Ut_H   <= 0;
+      A_Edge   <= 0;
+      A_TL     <= 0;
+      A_TH     <= 0;
+      B_Dt_L   <= 0;
+      B_Dt_H   <= 0;
+      B_Ut_L   <= 0;
+      B_Ut_H   <= 0;
+      B_Edge   <= 0;
+      B_TL     <= 0;
+      B_TH     <= 0;
+      C_Dt_L   <= 0;
+      C_Dt_H   <= 0;
+      C_Ut_L   <= 0;
+      C_Ut_H   <= 0;
+      C_Edge   <= 0;
+      C_TL     <= 0;
+      C_TH     <= 0;
+      D_Dt_L   <= 0;
+      D_Dt_H   <= 0;
+      D_Ut_L   <= 0;
+      D_Ut_H   <= 0;
+      D_Edge   <= 0;
+      D_TL     <= 0;
+      D_TH     <= 0;
+    end else begin
+      // For CH_A Trigger
+      if ( Din[ 7:0] > Delta_V3 )  A_Status <= 1;
+      if ( Din[ 7:0] < Delta_V4 )  A_Status <= 0;
+      if (( Din[ 7:0] > Delta_V1 )&&( ~A_Flag )) begin
+        if ( A_Cnt < Tthreshold )  A_Dt_L <= Sampled; 
+        else                       A_Ut_L <= Sampled; 
+        A_Flag <= 1;
+        A_Cnt  <= 0;
+        A_Edge <= A_Edge + 1;
+        A_TL   <= A_TL + A_Cnt;
+      end else
+      if (( Din[ 7:0] < Delta_V2 )&&(  A_Flag )) begin
+        if ( A_Cnt < Tthreshold )  A_Dt_H <= Sampled; 
+        else                       A_Ut_H <= Sampled; 
+        A_Flag <= 0;
+        A_Cnt  <= 0;
+        A_Edge <= A_Edge + 1;
+        A_TH   <= A_TH + A_Cnt;
+      end  else  A_Cnt <= A_Cnt + 1; 
+      
+      // For CH_B Trigger
+      if ( Din[15:8] > Delta_V3 )  B_Status <= 1;
+      if ( Din[15:8] < Delta_V4 )  B_Status <= 0;
+      if (( Din[15:8] > Delta_V1 )&&( ~B_Flag )) begin
+        if ( B_Cnt < Tthreshold )  B_Dt_L <= Sampled;
+        else                       B_Ut_L <= Sampled;
+        B_Flag <= 1;
+        B_Cnt  <= 0;
+        B_Edge <= B_Edge + 1;
+        B_TL   <= B_TL + B_Cnt;
+      end else
+      if (( Din[15:8] < Delta_V2 )&&(  B_Flag )) begin
+        if ( B_Cnt < Tthreshold )  B_Dt_H <= Sampled;
+        else                       B_Ut_H <= Sampled;
+        B_Flag <= 0;
+        B_Cnt  <= 0;
+        B_Edge <= B_Edge + 1;
+        B_TH   <= B_TH + B_Cnt;
+      end  else  B_Cnt <= B_Cnt + 1; 
+    
+      // For CH_C Trigger
+      if ( Din[16] != C_Flag ) begin
+        if ( C_Cnt < Tthreshold ) begin
+          if ( Din[16] )  C_Dt_L <= Sampled;
+          else            C_Dt_H <= Sampled;
+        end else begin
+          if ( Din[16] )  C_Ut_L <= Sampled;
+          else            C_Ut_H <= Sampled;
+        end 
+        C_Cnt <= 0;
+        C_Edge <= C_Edge + 1;
+        if ( ~C_Flag )  C_TL <= C_TL + C_Cnt;
+        else            C_TH <= C_TH + C_Cnt;
+      end else  C_Cnt <= C_Cnt + 1; 
+      C_Flag <= Din[16]; 
+       
+      // For CH_D Trigger
+      if ( Din[17] != D_Flag ) begin
+        if ( D_Cnt < Tthreshold ) begin
+          if ( Din[17] )  D_Dt_L <= Sampled;
+          else            D_Dt_H <= Sampled;
+        end else begin
+          if ( Din[17] )  D_Ut_L <= Sampled;
+          else            D_Ut_H <= Sampled;
+        end  
+        D_Cnt <= 0;
+        D_Edge <= D_Edge + 1;
+        if ( ~D_Flag )  D_TL <= D_TL + D_Cnt;
+        else            D_TH <= D_TH + D_Cnt;
+      end else  D_Cnt <= D_Cnt + 1; 
+      D_Flag <= Din[17]; 
+    
+      case( Trigg_Mode )
+        // For CH_A Trigger
+        8'h00: if (( Din[ 7:0] < Vthreshold )&&(  A_Flag ))   Start <= Sampled; // Negedge
+        8'h01: if (( Din[ 7:0] > Vthreshold )&&( ~A_Flag ))   Start <= Sampled; // Posedge
+        8'h02: if (( Din[ 7:0] < Vthreshold )&&(  A_Status )) Start <= Sampled; // L Level
+        8'h03: if (( Din[ 7:0] > Vthreshold )&&( ~A_Status )) Start <= Sampled; // H Level
+        8'h04: Start <= A_Dt_L; // Pusle 0 < ConfigDt
+        8'h05: Start <= A_Ut_L; // Pusle 0 > ConfigDt
+        8'h06: Start <= A_Dt_H; // Pusle 1 < ConfigDt
+        8'h07: Start <= A_Ut_H; // Pusle 1 > ConfigDt
+        // For CH_B Trigger
+        8'h08: if (( Din[15:8] < Vthreshold )&&(  B_Flag ))   Start <= Sampled; // Negedge
+        8'h09: if (( Din[15:8] > Vthreshold )&&( ~B_Flag ))   Start <= Sampled; // Posedge
+        8'h0A: if (( Din[15:8] < Vthreshold )&&(  B_Status )) Start <= Sampled; // L Level
+        8'h0B: if (( Din[15:8] > Vthreshold )&&( ~B_Status )) Start <= Sampled; // H Level
+        8'h0C: Start <= B_Dt_L; // Pusle 0 < ConfigDt
+        8'h0D: Start <= B_Ut_L; // Pusle 0 > ConfigDt
+        8'h0E: Start <= B_Dt_H; // Pusle 1 < ConfigDt
+        8'h0F: Start <= B_Ut_H; // Pusle 1 > ConfigDt
+        // For CH_C Trigger
+        8'h10: if (( ~Din[16] )&&(  C_Flag ))  Start <= Sampled; // Negedge
+        8'h11: if ((  Din[16] )&&( ~C_Flag ))  Start <= Sampled; // Posedge
+        8'h12: if (( ~Din[16] )&&(  C_Flag ))  Start <= Sampled; // L Level
+        8'h13: if ((  Din[16] )&&( ~C_Flag ))  Start <= Sampled; // H Level
+        8'h14: Start <= C_Dt_L; // Pusle 0 < ConfigDt
+        8'h15: Start <= C_Ut_L; // Pusle 0 > ConfigDt
+        8'h16: Start <= C_Dt_H; // Pusle 1 < ConfigDt
+        8'h17: Start <= C_Ut_H; // Pusle 1 > ConfigDt
+        // For CH_D Trigger
+        8'h18: if (( ~Din[17] )&&(  D_Flag ))  Start <= Sampled; // Negedge
+        8'h19: if ((  Din[17] )&&( ~D_Flag ))  Start <= Sampled; // Posedge
+        8'h1A: if (( ~Din[17] )&&(  D_Flag ))  Start <= Sampled; // L Level
+        8'h1B: if ((  Din[17] )&&( ~D_Flag ))  Start <= Sampled; // H Level
+        8'h1C: Start <= D_Dt_L; // Pusle 0 < ConfigDt
+        8'h1D: Start <= D_Ut_L; // Pusle 0 > ConfigDt
+        8'h1E: Start <= D_Dt_H; // Pusle 1 < ConfigDt
+        8'h1F: Start <= D_Ut_H; // Pusle 1 > ConfigDt
+        default:                                          Start <= 1;
+      endcase
+    end
+  end
+endmodule"
+"/********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ********************
+                       4096 * 18Bits dual-port SRAM module  
+ Version   : FPGA CFG Ver 2.x                                     Author : bure
+*******************************************************************************/
+
+module DP_RAM ( Din, Wclk, nRclk, Waddr, Raddr, Dout );
+
+  input  Wclk;                 // Wr clock       -> rising edge
+  input  nRclk;                // Rd clock       -> falling edge
+  
+  input  [11:0]Waddr;          // written address
+  input  [11:0]Raddr;          // read address
+  input  [17:0]Din;            // input dtat
+  
+  output [17:0]Dout;           // output data
+ 
+  reg [17:0] Dout;
+  reg [17:0] Mem_data [4095:0];
+
+  always @( posedge Wclk ) begin
+    Mem_data[Waddr] <= Din;
+  end
+
+  always @( negedge nRclk ) begin
+    Dout <= Mem_data[Raddr];
+  end
+  
+endmodule"
+"/********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ********************
+             Pre-sampling FIFO address counter and control module  
+ Version   : FPGA CFG Ver 2.x                                     Author : bure
+*******************************************************************************/
+
+module AddrCtrl ( ClrW, Wclk, Start, nRclk, RE, H_L, Depth, PerCnt, Delay,
+                  Ready, Sampled, Full, Empty, Wptr, Rptr );
+
+  input\t  ClrW;         // Wr addr cnt rst      -> Active high 
+  input\t  Wclk;         // Wr clock             -> rising edge 
+  input\t  Start;        // Sync start           -> active high 
+  input   nRclk;        // Rd clock             -> falling edge
+  input   RE;           // Rd cnt enable        -> active high
+  input   H_L;          // Data output select   -> 1/0: [17:16]/[15: 0]Dout->[15:0]DB
+  input   [11:0]Depth;  // Sampling depth
+  input   [11:0]PerCnt; // Per-sampling counter                        
+  input   [31:0]Delay;  // Sampling delay
+  
+  output  Sampled;      // Pre-sampling finish  -> active high
+  output  Ready;        // Sampling start       -> active high
+  output  Full;         // FIFO RAM is full     -> active high
+  output  Empty;        // FIFO RAM is empty    -> active high
+  output  [11:0]Wptr;   // written address pointer
+  output  [11:0]Rptr;   // Read address pointer
+
+  reg     Full;
+  reg     Ready; 
+  reg     Loaded;       // marked the Start address loaded ok   
+  reg     [11:0]Wptr;
+  reg     [11:0]Rptr;
+  reg     [12:0]Pcnt;
+  reg     [11:0]Bptr;
+  reg     [31:0]DelayCnt;  
+
+  reg     Sampled;
+
+  always@ ( posedge Wclk or posedge ClrW ) begin
+    if ( ClrW ) begin               
+      Full <= 0;
+      Pcnt <= 0;
+      Sampled  <= 0;
+      DelayCnt <= 0;  
+      Ready    <= 0;              
+    end else begin
+      if ( Start )                      DelayCnt <= DelayCnt + 1;
+      if ( Pcnt >= PerCnt )             Sampled  <= 1;
+      if ( !Full )                      Wptr     <= Wptr + 1;
+      if ( Pcnt >= Depth )              Full     <= Ready; 
+      else                              Pcnt     <= Pcnt +1; // Sampling counter
+      if(( !Start )&&( Pcnt >= PerCnt)) Pcnt     <= PerCnt;
+      if ( DelayCnt == Delay ) begin  
+        Ready <= 1;              
+        Bptr  <= Wptr;                                       // Posedge of Start
+        Pcnt  <= PerCnt;
+      end  
+    end 
+  end
+
+  assign Empty = ( Rptr == Wptr ) ? 1'b1 : 1'b0 ;
+  
+  always @( posedge nRclk or posedge ClrW ) begin
+    if ( ClrW ) begin
+      Loaded <= 0; 
+      Rptr   <= 0;   
+    end else begin 
+      if ( H_L && RE )  Rptr <= Rptr + 1;
+      if (( H_L )&& RE &&( ~Loaded )&& Start ) begin 
+        Loaded <= 1;
+        Rptr   <= Bptr - 151; 
+      end  
+    end   
+  end
+
+endmodule"
+"/********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ********************
+                          Input & output control module  
+ Version   : FPGA CFG Ver 2.x                                     Author : bure
+*******************************************************************************/
+
+module IO_Ctrl( CE, nRD, SCK, SDA, Dout, Start, Full, Empty, H_L, C_D, Ready,  
+                A_Edge, A_TL, A_TH, B_Edge, B_TL, B_TH, 
+                C_Edge, C_TL, C_TH, D_Edge, D_TL, D_TH, 
+                Depth, PerCnt, Delay,
+                nPD, Trigg_Mode, Vthreshold, Tthreshold, CtrlReg, DB ); 
+
+  input     CE;                 // Databus selece enable -> Active high
+  input     nRD;                // Databus read enable   -> Active low
+  input     SCK;                // Serial input clock    -> rising edge 
+  input     SDA;                // Serial input data 
+  input     [17:0]Dout;         // Output data                     
+  input     Start;              // Sync start            -> active high
+  input     Ready;              // Sampling start        -> active high
+  input     Full;               // FIFO RAM is full      -> active high
+  input     Empty;              // FIFO RAM is empty     -> active high
+  input     H_L;                // 0/1 = Status/[15:0]Din -> [15:0]DB
+  input     C_D;                // 1 = [15:0]Data        -> [15:0]DB
+                                
+  input     [15:0]A_Edge;       // CH_A edge counter
+  input     [15:0]A_TL;         // CH_A 
+  input     [15:0]A_TH;         // CH_A 
+  
+  input     [15:0]B_Edge;       // CH_B edge counter
+  input     [15:0]B_TL;         // CH_B 
+  input     [15:0]B_TH;         // CH_B 
+  
+  input     [15:0]C_Edge;       // CH_C edge counter
+  input     [15:0]C_TL;         // CH_C 
+  input     [15:0]C_TH;         // CH_C 
+  
+  input     [15:0]D_Edge;       // CH_D edge counter
+  input     [15:0]D_TL;         // CH_D 
+  input     [15:0]D_TH;         // CH_D 
+  
+  output    [11:0]Depth;        // Sampling depth
+  output    [11:0]PerCnt;       // Per-sampling counter                        
+  output    [31:0]Delay;        // Sampling delay
+
+  output    nPD;                // ADC power down        -> Active low
+  output    [ 7:0]Trigg_Mode;   // Trigger Mode 
+  output    [ 7:0]Vthreshold;   // Trigger voltage threshold 
+  output    [15:0]Tthreshold;   // Trigger time threshold 
+  output    [ 7:0]CtrlReg;      // bit0=nPD, bit1=Mode, 
+
+  inout     [15:0]DB;           // Data bus to MCU
+
+  reg       [ 7:0]Trigg_Mode;   // Trigger Mode 
+  reg       [ 7:0]Vthreshold;   // Trigger voltage threshold 
+  reg       [15:0]Tthreshold;   // Trigger time threshold 
+  reg       [ 7:0]CtrlReg;
+  reg       [ 7:0]RegAddr;
+  reg       [ 7:0]DataBuff;
+  wire      [15:0]DB_Mux ; 
+
+  reg       [15:0]Data;
+  reg       [ 7:0]Select;
+  wire      [15:0]CD_Mux ; 
+
+  reg       [11:0]Depth;       
+  reg       [11:0]PerCnt;                         
+  reg       [31:0]Delay;      
+   
+  assign nPD = CtrlReg[0];
+        
+  assign CD_Mux = C_D ? Data[15:0] : { 10'h000, Start, Empty, Full, Ready, Dout[17:16] };  
+  assign DB_Mux = H_L ? Dout[15:0] : CD_Mux;  
+   
+  assign DB = ( CE && !nRD ) ? DB_Mux : 16'hzzzz ;
+
+  always @(posedge SCK) begin
+      
+    DataBuff <= { DataBuff[6:0], SDA };
+    
+  end
+  
+  always @( negedge nRD ) begin
+   case( Select )
+     4'b0000: Data <= A_Edge;
+     4'b0001: Data <= A_TL;
+     4'b0010: Data <= A_TH;
+     4'b0100: Data <= B_Edge;
+     4'b0101: Data <= B_TL;
+     4'b0110: Data <= B_TH;
+     4'b1000: Data <= C_Edge;
+     4'b1001: Data <= C_TL;
+     4'b1010: Data <= C_TH;
+     4'b1100: Data <= D_Edge;
+     4'b1101: Data <= D_TL;
+     4'b1110: Data <= D_TH;
+     default: Data <= 0;
+   endcase 
+  end
+
+  always @( posedge SDA ) begin
+    if ( !SCK ) begin
+      if ( H_L ) begin
+        RegAddr <= DataBuff;
+      end else begin
+        case( RegAddr )
+          8'h00:  begin 
+            Trigg_Mode <= DataBuff;    
+            Depth      <= 4095;
+            PerCnt     <= 150;
+            Delay      <= 1;
+          end
+          8'h01:  Vthreshold       <= DataBuff;    
+          8'h02:  Tthreshold[ 7:0] <= DataBuff;    
+          8'h03:  Tthreshold[15:8] <= DataBuff;    
+          8'h04:  CtrlReg   [ 7:0] <= DataBuff;    
+          8'h05:  Select    [ 7:0] <= DataBuff;    
+          8'h06:  Depth     [ 7:0] <= DataBuff;       
+          8'h07:  Depth     [11:8] <= DataBuff;      
+          8'h08:  PerCnt    [ 7:0] <= DataBuff;                         
+          8'h09:  PerCnt    [11:8] <= DataBuff;                         
+          8'h0A:  Delay     [ 7:0] <= DataBuff;      
+          8'h0B:  Delay     [15:8] <= DataBuff;      
+          8'h0C:  Delay    [23:16] <= DataBuff;      
+          8'h0D:  Delay    [31:24] <= DataBuff;      
+        endcase 
+      end
+    end 
+  end
+
+endmodule"
+"always @(negedge reset or posedge clk) begin
+  if (reset == 0) begin
+    d_out <= 16'h0000;
+    d_out_mem[resetcount] <= d_out;
+    laststoredvalue <= d_out;
+  end else begin
+    d_out <= d_out + 1'b1; 
+  end
+end
+
+always @(bufreadaddr)
+  bufreadval = d_out_mem[bufreadaddr];"
+"LIBAVDEVICE_$MAJOR {
+        global: avdevice_*;
+        local: *;
+};
+"
+"LIBSWSCALE_$MAJOR {
+        global: swscale_*; sws_*; ff_*;
+        local: *;
+};
+"
+"LIBAVFILTER_$MAJOR {
+        global: avfilter_*; av_*;
+        local: *;
+};
+"
+"LIBSWRESAMPLE_$MAJOR {
+        global: swr_*; ff_*; swresample_*;
+        local: *;
+};
+"
+"LIBPOSTPROC_$MAJOR {
+        global: postproc_*; pp_*;
+        local: *;
+};
+"
+"LIBAVCODEC_$MAJOR {
+        global: av*;
+                audio_resample;
+                audio_resample_close;
+                #deprecated, remove after next bump
+                img_get_alpha_info;
+                dsputil_init;
+                ff_find_pix_fmt;
+                ff_framenum_to_drop_timecode;
+                ff_framenum_to_smtpe_timecode;
+                ff_raw_pix_fmt_tags;
+                ff_init_smtpe_timecode;
+                ff_fft*;
+                ff_mdct*;
+                ff_dct*;
+                ff_rdft*;
+                ff_prores_idct_put_10_sse2;
+                ff_simple_idct*;
+                ff_aanscales;
+                ff_faan*;
+                ff_mmx_idct;
+                ff_fdct*;
+                fdct_ifast;
+                j_rev_dct;
+                ff_mmxext_idct;
+                ff_idct_xvid*;
+                ff_jpeg_fdct*;
+                #XBMC's configure checks for ff_vdpau_vc1_decode_picture()
+                ff_vdpau_vc1_decode_picture;
+        local:  *;
+};
+"
+"LIBAVUTIL_$MAJOR {
+        global: av_*; ff_*; avutil_*;
+        local: *;
+};
+"
+"LIBAVFORMAT_$MAJOR {
+        global: av*;
+                #FIXME those are for ffserver
+                ff_inet_aton;
+                ff_socket_nonblock;
+                ffm_set_write_index;
+                ffm_read_write_index;
+                ffm_write_write_index;
+                ff_rtsp_parse_line;
+                ff_rtp_get_local_rtp_port;
+                ff_rtp_get_local_rtcp_port;
+                ffio_open_dyn_packet_buf;
+                ffurl_close;
+                ffurl_open;
+                ffurl_write;
+                url_open;
+                url_close;
+                url_write;
+                url_get_max_packet_size;
+                #those are deprecated, remove on next bump
+                find_info_tag;
+                parse_date;
+                dump_format;
+                url_*;
+                ff_timefilter_destroy;
+                ff_timefilter_new;
+                ff_timefilter_update;
+                ff_timefilter_reset;
+                get_*;
+                put_*;
+                udp_set_remote_url;
+                udp_get_local_port;
+                init_checksum;
+                init_put_byte;
+        local: *;
+};
+"
+"// the dual-port BRAM Verilog below is adapted from Dan Strother's example:
+// http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
+
+module DualPortBRAM #(
+    parameter DATA = 72,
+    parameter ADDR = 10
+) (
+    input   wire               clk,
+
+    // Port A
+    input   wire                a_wr,
+    input   wire    [ADDR-1:0]  a_addr,
+    input   wire    [DATA-1:0]  a_din,
+    output  reg     [DATA-1:0]  a_dout,
+
+    // Port B
+    input   wire                b_wr,
+    input   wire    [ADDR-1:0]  b_addr,
+    input   wire    [DATA-1:0]  b_din,
+    output  reg     [DATA-1:0]  b_dout
+);
+
+// Shared memory
+reg [DATA-1:0] mem [(2**ADDR)-1:0];
+
+// Port A
+always @(posedge clk) begin
+    a_dout      <= mem[a_addr];
+    if(a_wr) begin
+        a_dout      <= a_din;
+        mem[a_addr] <= a_din;
+    end
+end
+
+// Port B
+always @(posedge clk) begin
+    b_dout      <= mem[b_addr];
+    if(b_wr) begin
+        b_dout      <= b_din;
+        mem[b_addr] <= b_din;
+    end
+end
+
+endmodule
+"
+"// original source:
+// https://github.com/nachiket/tdfc/blob/master/verilog/queues/Q_srl_oreg3_prefull_SIMPLE.v
+
+// changes by Yaman Umuroglu <maltanar@gmail.com>:
+// - added copy of license text at the start of file
+// - changed to synchronous active-high reset
+// - added ""count"" output for monitoring FIFO #elems
+// - added default assignments to comp process to prevent latches
+
+// Copyright (c) 1999 The Regents of the University of California
+// Copyright (c) 2010 The Regents of the University of Pennsylvania
+// Copyright (c) 2011 Department of Electrical and Electronic Engineering, Imperial College London
+//
+// Permission to use, copy, modify, and distribute this software and
+// its documentation for any purpose, without fee, and without a
+// written agreement is hereby granted, provided that the above copyright
+// notice and this paragraph and the following two paragraphs appear in
+// all copies.
+//
+// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+// DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING
+// LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
+// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF
+// SUCH DAMAGE.
+//
+// THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON
+// AN ""AS IS"" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
+// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+//
+
+// Q_srl_oreg3_prefull_SIMPLE.v
+//
+//  - In-page queue with parameterizable depth, bit width
+//  - Stream I/O is triple (data, valid, back-pressure),
+//      with EOS concatenated into the data
+//  - Flow control for input & output is combinationally decoupled
+//  - 2 <= depth <= 256
+//      * (depth >= 2)  is required to decouple I/O flow control,
+//          where empty => no produce,  full => no consume,
+//          and depth 1 would ping-pong between the two at half rate
+//      * (depth <= 256) can be modified
+//           by changing \'\'synthesis loop_limit X\'\' below
+//          and changing \'\'addrwidth\'\' or its log computation
+//  - 1 <= width
+//  - Queue storage is in SRL16E, up to depth 16 per LUT per bit-slice,
+//      plus output register (for fast output)
+//  - Queue addressing is done by \'\'addr\'\' up-down counter
+//  - Queue fullness is checked by comparator (addr==depth)
+//  - Queue fullness                           is pre-computed for next cycle
+//  - Queue input back-pressure                is pre-computed for next cycle
+//  - Queue output valid (state!=state__empty) is pre-computed for next cycle
+//      (necessary since SRL data output reg requires non-boolean state)
+//  - FSM has 3 states (empty, one, more)
+//  - When empty, continue to emit most recently emitted value (for debugging)
+//
+//  - Queue slots used      = / (state==state_empty) ? 0
+//                            | (state==state_one)   ? 1
+//                            \\ (state==state_more)  ? addr+2
+//  - Queue slots used     <=  depth
+//  - Queue slots remaining =  depth - used
+//                          = / (state==state_empty) ? depth
+//                            | (state==state_one)   ? depth-1
+//                            \\ (state==state_more)  ? depth-2-addr
+//
+//  - Synplify 7.1 / 8.0
+//  - Eylon Caspi,  9/11/03, 8/18/04, 3/29/05
+
+
+`ifdef  Q_srl
+`else
+`define Q_srl
+
+
+module Q_srl (clock, reset, i_d, i_v, i_b, o_d, o_v, o_b, count);
+
+   parameter depth = 16;   // - greatest #items in queue  (2 <= depth <= 256)
+   parameter width = 16;   // - width of data (i_d, o_d)
+
+   `define LOG2 (  (((depth))     ==0) ? 0\t/* - depth==0   LOG2=0 */ \\
+\t\t : (((depth-1)>>0)==0) ? 0\t/* - depth<=1   LOG2=0 */ \\
+\t\t : (((depth-1)>>1)==0) ? 1\t/* - depth<=2   LOG2=1 */ \\
+\t\t : (((depth-1)>>2)==0) ? 2\t/* - depth<=4   LOG2=2 */ \\
+\t\t : (((depth-1)>>3)==0) ? 3\t/* - depth<=8   LOG2=3 */ \\
+\t\t : (((depth-1)>>4)==0) ? 4\t/* - depth<=16  LOG2=4 */ \\
+\t\t : (((depth-1)>>5)==0) ? 5\t/* - depth<=32  LOG2=5 */ \\
+\t\t : (((depth-1)>>6)==0) ? 6\t/* - depth<=64  LOG2=6 */ \\
+\t\t : (((depth-1)>>7)==0) ? 7\t/* - depth<=128 LOG2=7 */ \\
+\t\t :                       8)\t/* - depth<=256 LOG2=8 */
+
+// parameter addrwidth = LOG2;\t\t\t// - width of queue addr
+
+   parameter addrwidth =
+\t\t(  (((depth))     ==0) ? 0\t// - depth==0   LOG2=0
+\t\t : (((depth-1)>>0)==0) ? 0\t// - depth<=1   LOG2=0
+\t\t : (((depth-1)>>1)==0) ? 1\t// - depth<=2   LOG2=1
+\t\t : (((depth-1)>>2)==0) ? 2\t// - depth<=4   LOG2=2
+\t\t : (((depth-1)>>3)==0) ? 3\t// - depth<=8   LOG2=3
+\t\t : (((depth-1)>>4)==0) ? 4\t// - depth<=16  LOG2=4
+\t\t : (((depth-1)>>5)==0) ? 5\t// - depth<=32  LOG2=5
+\t\t : (((depth-1)>>6)==0) ? 6\t// - depth<=64  LOG2=6
+\t\t : (((depth-1)>>7)==0) ? 7\t// - depth<=128 LOG2=7
+\t\t :                       8)\t// - depth<=256 LOG2=8
+\t\t ;
+
+   input     clock;
+   input     reset;
+
+   input  [width-1:0] i_d;\t// - input  stream data (concat data + eos)
+   input              i_v;\t// - input  stream valid
+   output             i_b;\t// - input  stream back-pressure
+
+   output [width-1:0] o_d;\t// - output stream data (concat data + eos)
+   output             o_v;\t// - output stream valid
+   input              o_b;\t// - output stream back-pressure
+
+   output [addrwidth:0] count;  // - output number of elems in queue
+
+   reg    [addrwidth-1:0] addr, addr_, a_;\t\t// - SRL16 address
+\t\t\t\t\t\t\t//     for data output
+   reg \t\t\t  shift_en_;\t\t\t// - SRL16 shift enable
+   reg    [width-1:0] \t  srl [depth-2:0];\t\t// - SRL16 memory
+   reg \t\t\t  shift_en_o_;\t\t\t// - SRLO  shift enable
+   reg    [width-1:0] \t  srlo_, srlo\t\t\t// - SRLO  output reg
+\t\t\t  /* synthesis syn_allow_retiming=0 */ ;
+
+   parameter state_empty = 2\'d0;    // - state empty : o_v=0 o_d=UNDEFINED
+   parameter state_one   = 2\'d1;    // - state one   : o_v=1 o_d=srlo
+   parameter state_more  = 2\'d2;    // - state more  : o_v=1 o_d=srlo
+\t\t\t\t    //     #items in srl = addr+2
+
+   reg [1:0] state, state_;\t    // - state register
+
+   wire      addr_full_;\t    // - true iff addr==depth-2 on NEXT cycle
+   reg       addr_full; \t    // - true iff addr==depth-2
+   wire      addr_zero_;\t    // - true iff addr==0
+   wire      o_v_reg_;\t\t    // - true iff state_empty   on NEXT cycle
+   reg       o_v_reg  \t\t    // - true iff state_empty
+\t     /* synthesis syn_allow_retiming=0 */ ;
+   wire      i_b_reg_;\t\t    // - true iff !full         on NEXT cycle
+   reg       i_b_reg  \t\t    // - true iff !full
+\t     /* synthesis syn_allow_retiming=0 */ ;
+
+   assign addr_full_ = (state_==state_more) && (addr_==depth-2);
+\t\t\t\t\t\t// - queue full
+   assign addr_zero_ = (addr==0);\t\t// - queue contains 2 (or 1,0)
+   assign o_v_reg_   = (state_!=state_empty);\t// - output valid if non-empty
+   assign i_b_reg_   = addr_full_;\t\t// - input bp if full
+   assign o_d = srlo;\t\t\t\t// - output data from queue
+   assign o_v = o_v_reg;\t\t\t// - output valid if non-empty
+   assign i_b = i_b_reg;\t\t\t// - input bp if full
+
+   assign count = (state==state_more ? addr+2 : (state==state_one ? 1 : 0));
+
+   // - \'\'always\'\' block with both FFs and SRL16 does not work,
+   //      since FFs need reset but SRL16 does not
+
+   always @(posedge clock) begin\t// - seq always: FFs
+      if (reset) begin
+\t state     <= state_empty;
+\t addr      <= 0;
+         addr_full <= 0;
+\t o_v_reg   <= 0;
+\t i_b_reg   <= 1;
+      end
+      else begin
+\t state     <= state_;
+\t addr      <= addr_;
+         addr_full <= addr_full_;
+\t o_v_reg   <= o_v_reg_;
+\t i_b_reg   <= i_b_reg_;
+      end
+   end // always @ (posedge clock)
+
+   always @(posedge clock) begin\t// - seq always: srlo
+      // - infer enabled output reg at end of shift chain
+      // - input first element from i_d, all subsequent elements from SRL16
+      if (reset) begin
+\t srlo <= 0;
+      end
+      else begin
+\t if (shift_en_o_) begin
+\t    srlo <= srlo_;
+\t end
+      end
+   end // always @ (posedge clock)
+
+   always @(posedge clock) begin\t\t\t// - seq always: srl
+      // - infer enabled SRL16E from shifting srl array
+      // - no reset capability;  srl[] contents undefined on reset
+      if (shift_en_) begin
+\t // synthesis loop_limit 256
+\t for (a_=depth-2; a_>0; a_=a_-1) begin
+\t    srl[a_] <= srl[a_-1];
+\t end
+\t srl[0] <= i_d;
+      end
+   end // always @ (posedge clock or negedge reset)
+
+   always @* begin\t\t\t\t\t// - combi always
+        srlo_       <=  \'bx;
+        shift_en_o_ <= 1\'bx;
+        shift_en_   <= 1\'bx;
+        addr_       <=  \'bx;
+        state_      <= 2\'bx;
+      case (state)
+
+\tstate_empty: begin\t\t    // - (empty, will not produce)
+\t      if (i_v) begin\t\t    // - empty & i_v => consume
+\t\t srlo_       <= i_d;
+\t\t shift_en_o_ <= 1;
+\t\t shift_en_   <= 1\'bx;
+\t\t addr_       <= 0;
+\t\t state_      <= state_one;
+\t      end
+\t      else\tbegin\t\t    // - empty & !i_v => idle
+\t\t srlo_       <= \'bx;
+\t\t shift_en_o_ <= 0;
+\t\t shift_en_   <= 1\'bx;
+\t\t addr_       <= 0;
+\t\t state_      <= state_empty;
+\t      end
+\tend
+
+\tstate_one: begin\t\t    // - (contains one)
+\t      if (i_v && o_b) begin\t    // - one & i_v & o_b => consume
+\t\t srlo_       <= \'bx;
+\t\t shift_en_o_ <= 0;
+\t\t shift_en_   <= 1;
+\t\t addr_       <= 0;
+\t\t state_      <= state_more;
+\t      end
+\t      else if (i_v && !o_b) begin   // - one & i_v & !o_b => cons+prod
+\t\t srlo_       <= i_d;
+\t\t shift_en_o_ <= 1;
+\t\t shift_en_   <= 1;
+\t\t addr_       <= 0;
+\t\t state_      <= state_one;
+\t      end
+\t      else if (!i_v && o_b) begin   // - one & !i_v & o_b => idle
+\t\t srlo_       <= \'bx;
+\t\t shift_en_o_ <= 0;
+\t\t shift_en_   <= 1\'bx;
+\t\t addr_       <= 0;
+\t\t state_      <= state_one;
+\t      end
+\t      else if (!i_v && !o_b) begin  // - one & !i_v & !o_b => produce
+\t\t srlo_       <= \'bx;
+\t\t shift_en_o_ <= 0;
+\t\t shift_en_   <= 1\'bx;
+\t\t addr_       <= 0;
+\t\t state_      <= state_empty;
+\t      end
+\tend // case: state_one
+
+\tstate_more: begin\t\t    // - (contains more than one)
+\t   if (addr_full || (depth==2)) begin
+\t\t\t\t\t    // - (full, will not consume)
+\t\t\t\t\t    // - (full here if depth==2)
+\t      if (o_b) begin\t\t    // - full & o_b => idle
+\t\t srlo_       <= \'bx;
+\t\t shift_en_o_ <= 0;
+\t\t shift_en_   <= 0;
+\t\t addr_       <= addr;
+\t\t state_      <= state_more;
+\t      end
+\t      else begin\t\t    // - full & !o_b => produce
+\t\t srlo_       <= srl[addr];
+\t\t shift_en_o_ <= 1;
+\t\t shift_en_   <= 0;
+//\t\t addr_       <= addr-1;
+//\t\t state_      <= state_more;
+\t\t addr_       <= addr_zero_ ? 0         : addr-1;
+\t\t state_      <= addr_zero_ ? state_one : state_more;
+\t      end
+\t   end
+\t   else begin\t\t\t    // - (mid: neither empty nor full)
+\t      if (i_v && o_b) begin\t    // - mid & i_v & o_b => consume
+\t\t srlo_       <= \'bx;
+\t\t shift_en_o_ <= 0;
+\t\t shift_en_   <= 1;
+\t\t addr_       <= addr+1;
+\t\t state_      <= state_more;
+\t      end
+\t      else if (i_v && !o_b) begin   // - mid & i_v & !o_b => cons+prod
+\t\t srlo_       <= srl[addr];
+\t\t shift_en_o_ <= 1;
+\t\t shift_en_   <= 1;
+\t\t addr_       <= addr;
+\t\t state_      <= state_more;
+\t      end
+\t      else if (!i_v && o_b) begin   // - mid & !i_v & o_b => idle
+\t\t srlo_       <= \'bx;
+\t\t shift_en_o_ <= 0;
+\t\t shift_en_   <= 0;
+\t\t addr_       <= addr;
+\t\t state_      <= state_more;
+\t      end
+\t      else if (!i_v && !o_b) begin  // - mid & !i_v & !o_b => produce
+\t\t srlo_       <= srl[addr];
+\t\t shift_en_o_ <= 1;
+\t\t shift_en_   <= 0;
+\t\t addr_       <= addr_zero_ ? 0         : addr-1;
+\t\t state_      <= addr_zero_ ? state_one : state_more;
+\t      end
+\t   end // else: !if(addr_full)
+\tend // case: state_more
+
+\tdefault: begin
+\t\t srlo_       <=  \'bx;
+\t\t shift_en_o_ <= 1\'bx;
+\t\t shift_en_   <= 1\'bx;
+\t\t addr_       <=  \'bx;
+\t\t state_      <= 2\'bx;
+\tend // case: default
+
+      endcase // case(state)
+   end // always @ *
+
+endmodule // Q_srl
+
+
+`endif  // `ifdef  Q_srl
+"
+"module GenericSDAccelWrapperTop(input ap_clk, input ap_rst_n,
+    output s_axi_control_AWREADY,
+    input  s_axi_control_AWVALID,
+    input [63:0] s_axi_control_AWADDR,
+    input [2:0] s_axi_control_AWPROT,
+    output s_axi_control_WREADY,
+    input  s_axi_control_WVALID,
+    input [31:0] s_axi_control_WDATA,
+    input [3:0] s_axi_control_WSTRB,
+    input  s_axi_control_BREADY,
+    output s_axi_control_BVALID,
+    output[1:0] s_axi_control_BRESP,
+    output s_axi_control_ARREADY,
+    input  s_axi_control_ARVALID,
+    input [63:0] s_axi_control_ARADDR,
+    input [2:0] s_axi_control_ARPROT,
+    input  s_axi_control_RREADY,
+    output s_axi_control_RVALID,
+    output[31:0] s_axi_control_RDATA,
+    output[1:0] s_axi_control_RRESP,
+    input  m_axi_gmem_AWREADY,
+    output m_axi_gmem_AWVALID,
+    output[63:0] m_axi_gmem_AWADDR,
+    output[2:0] m_axi_gmem_AWSIZE,
+    output[7:0] m_axi_gmem_AWLEN,
+    output[1:0] m_axi_gmem_AWBURST,
+    output[0:0] m_axi_gmem_AWID,
+    output m_axi_gmem_AWLOCK,
+    output[3:0] m_axi_gmem_AWCACHE,
+    output[2:0] m_axi_gmem_AWPROT,
+    output[3:0] m_axi_gmem_AWQOS,
+    input  m_axi_gmem_WREADY,
+    output m_axi_gmem_WVALID,
+    output[63:0] m_axi_gmem_WDATA,
+    output[63:0] m_axi_gmem_WSTRB,
+    output m_axi_gmem_WLAST,
+    output m_axi_gmem_BREADY,
+    input  m_axi_gmem_BVALID,
+    input [0:0] m_axi_gmem_BID,
+    input [1:0] m_axi_gmem_BRESP,
+    input  m_axi_gmem_ARREADY,
+    output m_axi_gmem_ARVALID,
+    output[63:0] m_axi_gmem_ARADDR,
+    output[2:0] m_axi_gmem_ARSIZE,
+    output[7:0] m_axi_gmem_ARLEN,
+    output[1:0] m_axi_gmem_ARBURST,
+    output[0:0] m_axi_gmem_ARID,
+    output m_axi_gmem_ARLOCK,
+    output[3:0] m_axi_gmem_ARCACHE,
+    output[2:0] m_axi_gmem_ARPROT,
+    output[3:0] m_axi_gmem_ARQOS,
+    output m_axi_gmem_RREADY,
+    input  m_axi_gmem_RVALID,
+    input [63:0] m_axi_gmem_RDATA,
+    input [0:0] m_axi_gmem_RID,
+    input  m_axi_gmem_RLAST,
+    input [1:0] m_axi_gmem_RRESP
+);
+  GenericSDAccelWrapper GenericSDAccelWrapper(.clk(ap_clk), .reset(!ap_rst_n),
+  \t.csr_AWREADY(s_axi_control_AWREADY),
+\t\t.csr_AWVALID(s_axi_control_AWVALID),
+\t\t.csr_AWADDR(s_axi_control_AWADDR),
+\t\t.csr_AWPROT(s_axi_control_AWPROT),
+\t\t.csr_WREADY(s_axi_control_WREADY),
+\t\t.csr_WVALID(s_axi_control_WVALID),
+\t\t.csr_WDATA(s_axi_control_WDATA),
+\t\t.csr_WSTRB(s_axi_control_WSTRB),
+\t\t.csr_BREADY(s_axi_control_BREADY),
+\t\t.csr_BVALID(s_axi_control_BVALID),
+\t\t.csr_BRESP(s_axi_control_BRESP),
+\t\t.csr_ARREADY(s_axi_control_ARREADY),
+\t\t.csr_ARVALID(s_axi_control_ARVALID),
+\t\t.csr_ARADDR(s_axi_control_ARADDR),
+\t\t.csr_ARPROT(s_axi_control_ARPROT),
+\t\t.csr_RREADY(s_axi_control_RREADY),
+\t\t.csr_RVALID(s_axi_control_RVALID),
+\t\t.csr_RDATA(s_axi_control_RDATA),
+\t\t.csr_RRESP(s_axi_control_RRESP),
+\t\t.mem0_AWREADY(m_axi_gmem_AWREADY),
+\t\t.mem0_AWVALID(m_axi_gmem_AWVALID),
+\t\t.mem0_AWADDR(m_axi_gmem_AWADDR),
+\t\t.mem0_AWSIZE(m_axi_gmem_AWSIZE),
+\t\t.mem0_AWLEN(m_axi_gmem_AWLEN),
+\t\t.mem0_AWBURST(m_axi_gmem_AWBURST),
+\t\t.mem0_AWID(m_axi_gmem_AWID),
+\t\t.mem0_AWLOCK(m_axi_gmem_AWLOCK),
+\t\t.mem0_AWCACHE(m_axi_gmem_AWCACHE),
+\t\t.mem0_AWPROT(m_axi_gmem_AWPROT),
+\t\t.mem0_AWQOS(m_axi_gmem_AWQOS),
+\t\t.mem0_WREADY(m_axi_gmem_WREADY),
+\t\t.mem0_WVALID(m_axi_gmem_WVALID),
+\t\t.mem0_WDATA(m_axi_gmem_WDATA),
+\t\t.mem0_WSTRB(m_axi_gmem_WSTRB),
+\t\t.mem0_WLAST(m_axi_gmem_WLAST),
+\t\t.mem0_BREADY(m_axi_gmem_BREADY),
+\t\t.mem0_BVALID(m_axi_gmem_BVALID),
+\t\t.mem0_BID(m_axi_gmem_BID),
+\t\t.mem0_BRESP(m_axi_gmem_BRESP),
+\t\t.mem0_ARREADY(m_axi_gmem_ARREADY),
+\t\t.mem0_ARVALID(m_axi_gmem_ARVALID),
+\t\t.mem0_ARADDR(m_axi_gmem_ARADDR),
+\t\t.mem0_ARSIZE(m_axi_gmem_ARSIZE),
+\t\t.mem0_ARLEN(m_axi_gmem_ARLEN),
+\t\t.mem0_ARBURST(m_axi_gmem_ARBURST),
+\t\t.mem0_ARID(m_axi_gmem_ARID),
+\t\t.mem0_ARLOCK(m_axi_gmem_ARLOCK),
+\t\t.mem0_ARCACHE(m_axi_gmem_ARCACHE),
+\t\t.mem0_ARPROT(m_axi_gmem_ARPROT),
+\t\t.mem0_ARQOS(m_axi_gmem_ARQOS),
+\t\t.mem0_RREADY(m_axi_gmem_RREADY),
+\t\t.mem0_RVALID(m_axi_gmem_RVALID),
+\t\t.mem0_RDATA(m_axi_gmem_RDATA),
+\t\t.mem0_RID(m_axi_gmem_RID),
+\t\t.mem0_RLAST(m_axi_gmem_RLAST),
+\t\t.mem0_RRESP(m_axi_gmem_RRESP)
+  );
+endmodule
+"
+"module ZedBoardWrapper(input clk, input reset,
+    output csr_AWREADY,
+    input  csr_AWVALID,
+    input [31:0] csr_AWADDR,
+    input [2:0] csr_AWPROT,
+    output csr_WREADY,
+    input  csr_WVALID,
+    input [31:0] csr_WDATA,
+    input [3:0] csr_WSTRB,
+    input  csr_BREADY,
+    output csr_BVALID,
+    output[1:0] csr_BRESP,
+    output csr_ARREADY,
+    input  csr_ARVALID,
+    input [31:0] csr_ARADDR,
+    input [2:0] csr_ARPROT,
+    input  csr_RREADY,
+    output csr_RVALID,
+    output[31:0] csr_RDATA,
+    output[1:0] csr_RRESP,
+    input  mem3_AWREADY,
+    output mem3_AWVALID,
+    output[31:0] mem3_AWADDR,
+    output[2:0] mem3_AWSIZE,
+    output[7:0] mem3_AWLEN,
+    output[1:0] mem3_AWBURST,
+    output[5:0] mem3_AWID,
+    output mem3_AWLOCK,
+    output[3:0] mem3_AWCACHE,
+    output[2:0] mem3_AWPROT,
+    output[3:0] mem3_AWQOS,
+    input  mem3_WREADY,
+    output mem3_WVALID,
+    output[63:0] mem3_WDATA,
+    output[7:0] mem3_WSTRB,
+    output mem3_WLAST,
+    output mem3_BREADY,
+    input  mem3_BVALID,
+    input [5:0] mem3_BID,
+    input [1:0] mem3_BRESP,
+    input  mem3_ARREADY,
+    output mem3_ARVALID,
+    output[31:0] mem3_ARADDR,
+    output[2:0] mem3_ARSIZE,
+    output[7:0] mem3_ARLEN,
+    output[1:0] mem3_ARBURST,
+    output[5:0] mem3_ARID,
+    output mem3_ARLOCK,
+    output[3:0] mem3_ARCACHE,
+    output[2:0] mem3_ARPROT,
+    output[3:0] mem3_ARQOS,
+    output mem3_RREADY,
+    input  mem3_RVALID,
+    input [63:0] mem3_RDATA,
+    input [5:0] mem3_RID,
+    input  mem3_RLAST,
+    input [1:0] mem3_RRESP,
+    input  mem2_AWREADY,
+    output mem2_AWVALID,
+    output[31:0] mem2_AWADDR,
+    output[2:0] mem2_AWSIZE,
+    output[7:0] mem2_AWLEN,
+    output[1:0] mem2_AWBURST,
+    output[5:0] mem2_AWID,
+    output mem2_AWLOCK,
+    output[3:0] mem2_AWCACHE,
+    output[2:0] mem2_AWPROT,
+    output[3:0] mem2_AWQOS,
+    input  mem2_WREADY,
+    output mem2_WVALID,
+    output[63:0] mem2_WDATA,
+    output[7:0] mem2_WSTRB,
+    output mem2_WLAST,
+    output mem2_BREADY,
+    input  mem2_BVALID,
+    input [5:0] mem2_BID,
+    input [1:0] mem2_BRESP,
+    input  mem2_ARREADY,
+    output mem2_ARVALID,
+    output[31:0] mem2_ARADDR,
+    output[2:0] mem2_ARSIZE,
+    output[7:0] mem2_ARLEN,
+    output[1:0] mem2_ARBURST,
+    output[5:0] mem2_ARID,
+    output mem2_ARLOCK,
+    output[3:0] mem2_ARCACHE,
+    output[2:0] mem2_ARPROT,
+    output[3:0] mem2_ARQOS,
+    output mem2_RREADY,
+    input  mem2_RVALID,
+    input [63:0] mem2_RDATA,
+    input [5:0] mem2_RID,
+    input  mem2_RLAST,
+    input [1:0] mem2_RRESP,
+    input  mem1_AWREADY,
+    output mem1_AWVALID,
+    output[31:0] mem1_AWADDR,
+    output[2:0] mem1_AWSIZE,
+    output[7:0] mem1_AWLEN,
+    output[1:0] mem1_AWBURST,
+    output[5:0] mem1_AWID,
+    output mem1_AWLOCK,
+    output[3:0] mem1_AWCACHE,
+    output[2:0] mem1_AWPROT,
+    output[3:0] mem1_AWQOS,
+    input  mem1_WREADY,
+    output mem1_WVALID,
+    output[63:0] mem1_WDATA,
+    output[7:0] mem1_WSTRB,
+    output mem1_WLAST,
+    output mem1_BREADY,
+    input  mem1_BVALID,
+    input [5:0] mem1_BID,
+    input [1:0] mem1_BRESP,
+    input  mem1_ARREADY,
+    output mem1_ARVALID,
+    output[31:0] mem1_ARADDR,
+    output[2:0] mem1_ARSIZE,
+    output[7:0] mem1_ARLEN,
+    output[1:0] mem1_ARBURST,
+    output[5:0] mem1_ARID,
+    output mem1_ARLOCK,
+    output[3:0] mem1_ARCACHE,
+    output[2:0] mem1_ARPROT,
+    output[3:0] mem1_ARQOS,
+    output mem1_RREADY,
+    input  mem1_RVALID,
+    input [63:0] mem1_RDATA,
+    input [5:0] mem1_RID,
+    input  mem1_RLAST,
+    input [1:0] mem1_RRESP,
+    input  mem0_AWREADY,
+    output mem0_AWVALID,
+    output[31:0] mem0_AWADDR,
+    output[2:0] mem0_AWSIZE,
+    output[7:0] mem0_AWLEN,
+    output[1:0] mem0_AWBURST,
+    output[5:0] mem0_AWID,
+    output mem0_AWLOCK,
+    output[3:0] mem0_AWCACHE,
+    output[2:0] mem0_AWPROT,
+    output[3:0] mem0_AWQOS,
+    input  mem0_WREADY,
+    output mem0_WVALID,
+    output[63:0] mem0_WDATA,
+    output[7:0] mem0_WSTRB,
+    output mem0_WLAST,
+    output mem0_BREADY,
+    input  mem0_BVALID,
+    input [5:0] mem0_BID,
+    input [1:0] mem0_BRESP,
+    input  mem0_ARREADY,
+    output mem0_ARVALID,
+    output[31:0] mem0_ARADDR,
+    output[2:0] mem0_ARSIZE,
+    output[7:0] mem0_ARLEN,
+    output[1:0] mem0_ARBURST,
+    output[5:0] mem0_ARID,
+    output mem0_ARLOCK,
+    output[3:0] mem0_ARCACHE,
+    output[2:0] mem0_ARPROT,
+    output[3:0] mem0_ARQOS,
+    output mem0_RREADY,
+    input  mem0_RVALID,
+    input [63:0] mem0_RDATA,
+    input [5:0] mem0_RID,
+    input  mem0_RLAST,
+    input [1:0] mem0_RRESP
+);
+
+
+endmodule
+"
+"/*
+ * Milkymist VJ SoC fjmem flasher
+ * Copyright (C) 2010 Michael Walle <michael@walle.cc>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+module fjmem_jtag (
+\toutput jtag_tck,
+\toutput jtag_rst,
+\toutput jtag_update,
+\toutput jtag_shift,
+\toutput jtag_tdi,
+\tinput jtag_tdo
+);
+
+BSCAN_SPARTAN6 #(
+\t.JTAG_CHAIN(1)
+) bscan (
+\t.CAPTURE(),
+\t.DRCK(jtag_tck),
+\t.RESET(jtag_rst),
+\t.RUNTEST(),
+\t.SEL(),
+\t.SHIFT(jtag_shift),
+\t.TCK(),
+\t.TDI(jtag_tdi),
+\t.TMS(),
+\t.UPDATE(jtag_update),
+\t.TDO(jtag_tdo)
+);
+
+endmodule
+"
+"/*
+ * Milkymist VJ SoC fjmem flasher
+ * Copyright (C) 2010 Michael Walle
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+module system(
+    input clk50,
+    
+    /* flash */
+    output [23:0] flash_adr,
+    inout [15:0] flash_d,
+    output flash_oe_n,
+    output flash_we_n,
+    output flash_ce_n,
+    output flash_rst_n,
+    input flash_sts,
+
+\t/* debug */
+\toutput led1,
+\toutput led2
+);
+
+/* clock and reset */
+wire sys_rst;
+wire sys_clk;
+assign sys_clk = clk50;
+assign sys_rst = 1'b0;
+
+/* flash control pins */
+assign flash_ce_n = 1'b0;
+assign flash_rst_n = 1'b1;
+
+/* debug */
+wire fjmem_update;
+reg [25:0] counter;
+always @(posedge sys_clk)
+\tcounter <= counter + 1'd1;
+
+assign led1 = counter[25];
+assign led2 = fjmem_update;
+
+fjmem #(
+    .adr_width(24)
+) fjmem (
+    .sys_clk(sys_clk),
+    .sys_rst(sys_rst),
+
+    .flash_adr(flash_adr),
+    .flash_d(flash_d),
+    .flash_oe_n(flash_oe_n),
+    .flash_we_n(flash_we_n),
+
+\t.fjmem_update(fjmem_update)
+);
+
+endmodule
+"
+"/*
+ * Milkymist VJ SoC fjmem flasher
+ * Copyright (C) 2010 Michael Walle <michael@walle.cc>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+module fjmem #(
+\tparameter adr_width = 24
+) (
+\tinput sys_clk,
+\tinput sys_rst,
+
+\t/* flash */
+\toutput [adr_width-1:0] flash_adr,
+\tinout [15:0] flash_d,
+\toutput flash_oe_n,
+\toutput flash_we_n,
+
+\t/* debug output */
+\toutput fjmem_update
+);
+
+wire jtag_tck;
+wire jtag_rst;
+wire jtag_update;
+wire jtag_shift;
+wire jtag_tdi;
+wire jtag_tdo;
+
+fjmem_core #(
+\t.adr_width(adr_width)
+) core (
+\t.sys_clk(sys_clk),
+\t.sys_rst(sys_rst),
+
+\t/* jtag */
+\t.jtag_tck(jtag_tck),
+\t.jtag_rst(jtag_rst),
+\t.jtag_update(jtag_update),
+\t.jtag_shift(jtag_shift),
+\t.jtag_tdi(jtag_tdi),
+\t.jtag_tdo(jtag_tdo),
+
+\t/* flash */
+\t.flash_adr(flash_adr),
+\t.flash_d(flash_d),
+\t.flash_oe_n(flash_oe_n),
+\t.flash_we_n(flash_we_n),
+
+\t/* debug */
+\t.fjmem_update(fjmem_update)
+);
+
+fjmem_jtag jtag (
+\t.jtag_tck(jtag_tck),
+\t.jtag_rst(jtag_rst),
+\t.jtag_update(jtag_update),
+\t.jtag_shift(jtag_shift),
+\t.jtag_tdi(jtag_tdi),
+\t.jtag_tdo(jtag_tdo)
+);
+
+endmodule
+"
+"/*
+ * Milkymist VJ SoC fjmem flasher
+ * Copyright (C) 2010 Michael Walle
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns / 1ps
+
+module tb_fjmem();
+
+parameter adr_width = 24;
+
+/* 100MHz system clock */
+reg clk;
+initial clk = 1\'b0;
+always #5 clk = ~clk;
+
+reg rst;
+
+wire [adr_width-1:0] flash_adr;
+wire [15:0] flash_d;
+wire flash_oe_n;
+wire flash_we_n;
+
+reg [15:0] flash_do;
+assign flash_d = (flash_oe_n) ? 16\'bz : flash_do;
+
+reg jtag_tck;
+reg jtag_rst;
+reg jtag_update;
+reg jtag_shift;
+reg jtag_tdi;
+wire jtag_tdo;
+
+fjmem_core #(
+\t.adr_width(adr_width)
+) core (
+\t.sys_clk(clk),
+\t.sys_rst(rst),
+
+\t/* jtag */
+\t.jtag_tck(jtag_tck),
+\t.jtag_rst(jtag_rst),
+\t.jtag_update(jtag_update),
+\t.jtag_shift(jtag_shift),
+\t.jtag_tdi(jtag_tdi),
+\t.jtag_tdo(jtag_tdo),
+
+\t/* flash */
+\t.flash_adr(flash_adr),
+\t.flash_d(flash_d),
+\t.flash_oe_n(flash_oe_n),
+\t.flash_we_n(flash_we_n)
+);
+
+task jtagclock;
+\tinput integer n;
+begin
+\trepeat(n)
+\tbegin
+\t\tjtag_tck = 1\'b0;
+\t\t#50;
+\t\tjtag_tck = 1\'b1;
+\t\t#50;
+\t\tjtag_tck = 1\'b0;
+\tend
+end
+endtask
+
+task jtagshift;
+\tinput integer sw;
+\tinput [63:0] din;
+\toutput [63:0] dout;
+begin
+\trepeat(sw)
+\tbegin 
+\t\tjtag_shift = 1\'b1;
+\t\tjtag_tck = 1\'b0;
+\t\t{din[62:0], jtag_tdi} = din;
+
+\t\t#50;
+\t\tjtag_tck = 1\'b1;
+\t\tdout = {dout[61:0], jtag_tdo};
+
+\t\t#50;
+\t\tjtag_tck = 1\'b0;
+\t\tjtag_shift = 1\'b0;
+\tend
+end
+endtask
+
+task jtagupdate;
+begin
+\tjtag_update = 1\'b0;
+\tjtag_tck = 1\'b0;
+\t#50;
+\tjtag_update = 1\'b1;
+\tjtag_tck = 1\'b1;
+\t#50;
+\tjtag_update = 1\'b0;
+\tjtag_tck = 1\'b0;
+end
+endtask
+
+task jtagreset;
+begin
+\tjtag_rst = 1\'b0;
+\tjtag_tck = 1\'b0;
+\t#50;
+\tjtag_rst = 1\'b1;
+\tjtag_tck = 1\'b1;
+\t#50;
+\tjtag_rst = 1\'b0;
+\tjtag_tck = 1\'b0;
+end
+endtask
+
+parameter IDLE   = 3\'b000;
+parameter DETECT = 3\'b111;
+parameter QUERY  = 3\'b110;
+parameter READ   = 3\'b001;
+parameter WRITE  = 3\'b010;
+
+task fjmemcommand;
+input [2:0] cmd;
+input block;
+input [23:0] adr;
+input data;
+reg [44:0] din;
+reg [44:0] dout;
+begin
+\tdin = { data, adr, block, 1\'b0, cmd};
+\t$display(""din=%x"", din);
+\tjtagshift(45, din, dout);
+\tjtagupdate();
+\t$display(""dout=%x"", dout);
+\t$display(""data=%x adr=%x block=%x ack=%x cmd=%x"",
+\t\tdout[44:29], dout[28:5], dout[4], dout[3], dout[2:0]);
+end
+endtask
+
+always @(negedge flash_oe_n)
+begin
+\t$display(""Flash read access @%x: %x"", flash_adr, flash_adr[15:0]);
+\t#110 flash_do = flash_adr[15:0];
+end
+
+always @(negedge flash_we_n)
+begin
+\t$display(""Flash write access @%x: %x"", flash_adr, flash_d[15:0]);
+end
+
+reg [44:0] data_r;
+always begin
+\t$dumpfile(""fjmem.vcd"");
+\t$dumpvars();
+
+\t/* Reset / Initialize our logic */
+\trst = 1\'b1;
+\t
+\tjtag_tck = 1\'b0;
+\tjtag_rst = 1\'b0;
+\tjtag_update = 1\'b0;
+\tjtag_shift = 1\'b0;
+\tjtag_tdi = 1\'b0;
+\t
+\t#10;
+\trst = 1\'b0;
+
+\tjtagreset();
+
+\tfjmemcommand(DETECT, 0, 0, 0);
+\tfjmemcommand(IDLE, 0, 0, 0);
+
+\t$finish;
+end
+
+endmodule
+
+"
+"/*
+ * Milkymist VJ SoC fjmem flasher
+ * Copyright (C) 2010 Michael Walle
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+module system(
+    input clk50,
+    
+    /* flash */
+    output [23:0] flash_adr,
+    inout [15:0] flash_d,
+    output flash_oe_n,
+    output flash_we_n,
+    output flash_ce_n,
+    output flash_rst_n,
+    input flash_sts,
+
+\t/* debug */
+\toutput led
+);
+
+/* clock and reset */
+wire sys_rst;
+wire sys_clk;
+assign sys_clk = clk50;
+assign sys_rst = 1'b0;
+
+/* flash control pins */
+assign flash_ce_n = 1'b0;
+assign flash_rst_n = 1'b1;
+
+/* debug */
+wire fjmem_update;
+reg [25:0] counter;
+always @(posedge sys_clk)
+\tcounter <= counter + 1'd1;
+
+assign led = counter[25] ^ fjmem_update;
+
+fjmem #(
+    .adr_width(24)
+) fjmem (
+    .sys_clk(sys_clk),
+    .sys_rst(sys_rst),
+
+    .flash_adr(flash_adr),
+    .flash_d(flash_d),
+    .flash_oe_n(flash_oe_n),
+    .flash_we_n(flash_we_n),
+
+\t.fjmem_update(fjmem_update)
+);
+
+endmodule
+"
+"/*
+ * Milkymist VJ SoC fjmem flasher
+ * Copyright (C) 2010 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2008 Arnim Laeuger <arniml@users.sourceforge.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ * This core is derived from the VHDL version supplied with UrJTAG, written
+ * by Arnim Laeuger.
+ *
+ */
+
+module fjmem_core #(
+\tparameter adr_width = 24,
+\tparameter timing = 4'd6
+) (
+\tinput sys_clk,
+\tinput sys_rst,
+
+\t/* jtag */
+\tinput jtag_tck,
+\tinput jtag_rst,
+\tinput jtag_update,
+\tinput jtag_shift,
+\tinput jtag_tdi,
+\toutput jtag_tdo,
+
+\t/* flash */
+\toutput [adr_width-1:0] flash_adr,
+\tinout [15:0] flash_d,
+\toutput reg flash_oe_n,
+\toutput reg flash_we_n,
+
+\t/* debug */
+\toutput fjmem_update
+);
+
+parameter INSTR_IDLE   = 3'b000;
+parameter INSTR_DETECT = 3'b111;
+parameter INSTR_QUERY  = 3'b110;
+parameter INSTR_READ   = 3'b001;
+parameter INSTR_WRITE  = 3'b010;
+
+
+parameter aw = adr_width;
+parameter sw = aw+21;
+
+reg [sw-1:0] shift_r;
+
+assign jtag_tdo = shift_r[0];
+assign read = (instr == INSTR_READ);
+assign write = (instr == INSTR_WRITE);
+
+always @(posedge jtag_tck or posedge jtag_rst)
+begin
+\tif (jtag_rst) begin
+\t\tshift_r <= {(sw){1'b0}};
+\tend
+\telse if (jtag_shift) begin
+\t\t/* shift mode */
+\t\tshift_r[sw-1:0] <= { jtag_tdi, shift_r[sw-1:1] };
+\tend
+\telse begin
+\t\t/* capture mode */
+\t\tshift_r[2:0] <= instr;
+\t\tcase (instr)
+\t\t\tINSTR_READ:
+\t\t\tbegin
+\t\t\t\tshift_r[3] <= ack_q;
+\t\t\t\tshift_r[aw+20:aw+5] <= din;
+\t\t\tend
+\t\t\tINSTR_WRITE:
+\t\t\tbegin
+\t\t\tend
+\t\t\tINSTR_IDLE:
+\t\t\tbegin
+\t\t\t\tshift_r <= {(sw){1'b0}};
+\t\t\tend
+\t\t\tINSTR_DETECT:
+\t\t\tbegin
+\t\t\t\tshift_r[4]           <= 1'b1;
+\t\t\t\tshift_r[aw+4:5]      <= {(aw){1'b0}};
+\t\t\t\tshift_r[aw+20:aw+5]  <= 16'b1111111111111111;
+\t\t\tend
+\t\t\tINSTR_QUERY:
+\t\t\tbegin
+\t\t\t\tif (~block) begin
+\t\t\t\t\tshift_r[aw+4:5]      <= {(aw){1'b1}};
+\t\t\t\t\tshift_r[aw+20:aw+5]  <= 16'b1111111111111111;
+\t\t\t\tend
+\t\t\t\telse begin
+\t\t\t\t\tshift_r[sw-1:3] <= {(sw-3){1'b0}};
+\t\t\t\tend
+\t\t\tend
+\t\t\tdefault:
+\t\t\t\tshift_r[sw-1:3] <= {(sw-3){1'bx}};
+\t\tendcase
+\tend
+end
+
+reg [2:0] instr;
+reg block;
+reg [aw-1:0] addr;
+reg [15:0] dout;
+reg strobe_toggle;
+
+assign flash_d = (flash_oe_n) ? dout : 16'bz;
+assign flash_adr = addr;
+
+/*
+ * 2:0            : instr
+ * 3              : ack
+ * 4              : block
+ * (aw+4):5       : addr
+ * (aw+20):(aw+5) : data
+ */
+
+always @(posedge jtag_update or posedge jtag_rst)
+begin
+\tif (jtag_rst) begin
+\t\tinstr <= INSTR_IDLE;
+\t\tblock <= 1'b0;
+\t\taddr <= {(aw){1'b0}};
+\t\tdout <= 16'h0000;
+\t\tstrobe_toggle <= 1'b0;
+\tend
+\telse begin
+\t\tinstr <= shift_r[2:0];
+\t\tblock <= shift_r[4];
+\t\taddr <= shift_r[aw+4:5];
+\t\tdout <= shift_r[aw+20:aw+5];
+
+\t\tstrobe_toggle <= ~strobe_toggle;
+\tend
+end
+
+wire strobe;
+reg strobe_q;
+reg strobe_qq;
+reg strobe_qqq;
+
+assign strobe = strobe_qq ^ strobe_qqq;
+
+always @(posedge sys_clk)
+begin
+\tif (sys_rst) begin
+\t\tstrobe_q   <= 1'b0;
+\t\tstrobe_qq  <= 1'b0;
+\t\tstrobe_qqq <= 1'b0;
+\tend
+\telse begin
+\t\tstrobe_q   <= strobe_toggle;
+\t\tstrobe_qq  <= strobe_q;
+\t\tstrobe_qqq <= strobe_qq;
+\tend
+end
+
+reg [3:0] counter;
+reg counter_en;
+wire counter_done = (counter == timing);
+
+always @(posedge sys_clk)
+begin
+\tif (sys_rst)
+\t\tcounter <= 4'd0;
+\telse begin
+\t\tif (counter_en & ~counter_done)
+\t\t\tcounter <= counter + 4'd1;
+\t\telse
+\t\t\tcounter <= 4'd0;
+\tend
+end
+
+reg ack_q;
+always @(posedge sys_clk)
+begin
+\tif (sys_rst)
+\t\tack_q <= 1'b0;
+\telse
+\t\tack_q <= ack;
+end
+
+parameter IDLE    = 2'd0;
+parameter DELAYRD = 2'd1;
+parameter DELAYWR = 2'd2;
+parameter RD      = 2'd3;
+
+reg [15:0] din;
+reg [1:0] state;
+reg ack;
+
+always @(posedge sys_clk)
+begin
+\tif (sys_rst) begin
+\t\tflash_oe_n <= 1'b1;
+\t\tflash_we_n <= 1'b1;
+\t\tack <= 1'b0;
+\t\tdin <= 16'h0000;
+\t\tstate <= IDLE;
+\tend
+\telse begin
+\t\tflash_oe_n <= 1'b1;
+\t\tflash_we_n <= 1'b1;
+\t\tcounter_en <= 1'b0;
+\t\tcase (state)
+\t\t\tIDLE: begin
+\t\t\t\tack <= 1;
+\t\t\t\tif (strobe)
+\t\t\t\t\tif (read)
+\t\t\t\t\t\tstate <= DELAYRD;
+\t\t\t\t\telse if (write)
+\t\t\t\t\t\tstate <= DELAYWR;
+\t\t\tend
+\t\t\tDELAYRD: begin
+\t\t\t\tack <= 0;
+\t\t\t\tflash_oe_n <= 1'b0;
+\t\t\t\tcounter_en <= 1'b1;
+\t\t\t\tif (counter_done)
+\t\t\t\t\tstate <= RD;
+\t\t\tend
+\t\t\tDELAYWR: begin
+\t\t\t\tflash_we_n <= 1'b0;
+\t\t\t\tcounter_en <= 1'b1;
+\t\t\t\tif (counter_done)
+\t\t\t\t\tstate <= IDLE;
+\t\t\tend
+\t\t\tRD: begin
+\t\t\t\tcounter_en <= 1'b0;
+\t\t\t\tdin <= flash_d;
+\t\t\t\tstate <= IDLE;
+\t\t\tend
+\t\tendcase
+\tend
+end
+
+assign fjmem_update = strobe_toggle;
+
+endmodule
+"
+"call<call,x>
+------------
+
+foo foo x
+    sfd
+
+
+name
+----
+
+foo
+
+"
+"assign
+    variable
+    command
+        add
+            literal
+            literal
+        add
+            literal
+            literal
+
+$test = echo 1+2, 1+3
+echo (1+2) (1+3)"
+"pass
+
+pass"
+"`timescale 1 ns / 1 ps
+
+`include ""pdk_fpga_defines.vh""
+
+(* keep_hierarchy = ""true"" *)
+module cae_pers #(
+   parameter    NUM_MC_PORTS = 1,
+   parameter    RTNCTL_WIDTH = 32
+) (
+   //
+   // Clocks and Resets
+   //
+   input\t\tclk,\t\t// Personalitycore clock
+   input\t\tclkhx,\t\t// half-rate clock
+   input\t\tclk2x,\t\t// 2x rate clock
+   input\t\ti_reset,\t// global reset synchronized to clk
+
+   //
+   // Dispatch Interface
+   //
+   input                disp_inst_vld,
+   input  [4:0]         disp_inst,
+   input  [17:0]        disp_aeg_idx,
+   input                disp_aeg_rd,
+   input                disp_aeg_wr,
+   input  [63:0]        disp_aeg_wr_data,
+
+   output [17:0]        disp_aeg_cnt,
+   output [15:0]        disp_exception,
+   output               disp_idle,
+   output               disp_rtn_data_vld,
+   output [63:0]        disp_rtn_data,
+   output               disp_stall,
+
+   //
+   // MC Interface(s)
+   //
+   output [NUM_MC_PORTS*1-1 :0]         mc_rq_vld,
+   output [NUM_MC_PORTS*RTNCTL_WIDTH-1:0]         mc_rq_rtnctl,
+   output [NUM_MC_PORTS*64-1:0]         mc_rq_data,
+   output [NUM_MC_PORTS*48-1:0]         mc_rq_vadr,
+   output [NUM_MC_PORTS*2-1 :0]         mc_rq_size,
+   output [NUM_MC_PORTS*3-1 :0]         mc_rq_cmd,
+   output [NUM_MC_PORTS*4-1 :0]         mc_rq_scmd,
+   input  [NUM_MC_PORTS*1-1 :0]         mc_rq_stall,
+
+   input  [NUM_MC_PORTS*1-1 :0]         mc_rs_vld,
+   input  [NUM_MC_PORTS*3-1 :0]         mc_rs_cmd,
+   input  [NUM_MC_PORTS*4-1 :0]         mc_rs_scmd,
+   input  [NUM_MC_PORTS*64-1:0]         mc_rs_data,
+   input  [NUM_MC_PORTS*RTNCTL_WIDTH-1:0]         mc_rs_rtnctl,
+   output [NUM_MC_PORTS*1-1 :0]         mc_rs_stall,
+
+   // Write flush
+   output [NUM_MC_PORTS*1-1 :0]         mc_rq_flush,
+   input  [NUM_MC_PORTS*1-1 :0]         mc_rs_flush_cmplt,
+
+   //
+   // AE-to-AE Interface not used
+   //
+
+   //
+   // Management/Debug Interface
+   //
+   input\t\t\t\tcsr_wr_vld,
+   input\t\t\t\tcsr_rd_vld,
+   input  [15:0]\t\t\tcsr_address,
+   input  [63:0]\t\t\tcsr_wr_data,
+   output\t\t\t\tcsr_rd_ack,
+   output [63:0]\t\t\tcsr_rd_data,
+
+   //
+   // Miscellaneous
+   //
+   input  [3:0]\t\ti_aeid
+);
+
+`include ""pdk_fpga_param.vh""
+
+  // Convey-recommended way of registering the global reset signal
+  wire r_reset;
+  FDSE rst (.C(clk),.S(i_reset),.CE(r_reset),.D(!r_reset),.Q(r_reset));
+
+   WolverinePlatformWrapper pers(
+    .clk(clk),
+    .reset(r_reset),
+    .disp_inst_vld(disp_inst_vld),
+    .disp_inst(disp_inst),
+    .disp_aeg_idx(disp_aeg_idx),
+    .disp_aeg_rd(disp_aeg_rd),
+    .disp_aeg_wr(disp_aeg_wr),
+    .disp_aeg_wr_data(disp_aeg_wr_data),
+    .disp_aeg_cnt(disp_aeg_cnt),
+    .disp_exception(disp_exception),
+    .disp_idle(disp_idle),
+    .disp_rtn_data_vld(disp_rtn_data_vld),
+    .disp_rtn_data(disp_rtn_data),
+    .disp_stall(disp_stall),
+    .mc_rq_vld(mc_rq_vld),
+    .mc_rq_rtnctl(mc_rq_rtnctl),
+    .mc_rq_data(mc_rq_data),
+    .mc_rq_vadr(mc_rq_vadr),
+    .mc_rq_size(mc_rq_size),
+    .mc_rq_cmd(mc_rq_cmd),
+    .mc_rq_scmd(mc_rq_scmd),
+    .mc_rq_stall(mc_rq_stall),
+    .mc_rs_vld(mc_rs_vld),
+    .mc_rs_cmd(mc_rs_cmd),
+    .mc_rs_scmd(mc_rs_scmd),
+    .mc_rs_data(mc_rs_data),
+    .mc_rs_rtnctl(mc_rs_rtnctl),
+    .mc_rs_stall(mc_rs_stall),
+    .mc_rq_flush(mc_rq_flush),
+    .mc_rs_flush_cmplt(mc_rs_flush_cmplt),
+    .csr_wr_vld(csr_wr_vld),
+    .csr_rd_vld(csr_rd_vld),
+    .csr_address(csr_address),
+    .csr_wr_data(csr_wr_data),
+    .csr_rd_ack(csr_rd_ack),
+    .csr_rd_data(csr_rd_data),
+    .i_aeid(i_aeid)
+   );
+
+   /* ---------- debug & synopsys off blocks  ---------- */
+
+   // synopsys translate_off
+
+   // Parameters: 1-Severity: Don\'t Stop, 2-start check only after negedge of reset
+   //assert_never #(1, 2, ""***ERROR ASSERT: unimplemented instruction cracked"") a0 (.clk(clk), .reset_n(!i_reset), .test_expr(r_unimplemented_inst));
+
+   // Parameters: 0-Severity: Stop, 2-start check only after negedge of reset
+   //assert_never #(0, 2, ""***ERROR ASSERT: Number of MC Ports must be a power of 2"") a1 (.clk(clk), .reset_n(!i_reset), .test_expr(|config_err));
+
+    // synopsys translate_on
+
+endmodule // cae_pers
+"
+"always @(negedge reset or posedge clk) begin
+  if (reset == 0) begin
+    d_out <= 16'h0000;
+    d_out_mem[resetcount] <= d_out;
+    laststoredvalue <= d_out;
+  end else begin
+    d_out <= d_out + 1'b1; 
+  end
+end
+
+always @(bufreadaddr)
+  bufreadval = d_out_mem[bufreadaddr];"
+"module ControlFSM (clk, reset, irq, read, write, iack, ir, alu_flags,
+    addr_sel, load_sel, count_sel, count_up, top_enable, alu_enable, alu_op);
+
+input clk, reset;
+
+// 16-bit microcode address
+input irq;              // 1
+input [7:0] ir;         // 8
+input [2:0] alu_flags;  // 3
+reg   [3:0] ustate;     // 4
+
+// 22-bit microinstruction
+output read, write, iack;                   // 3
+output [1:0] addr_sel, load_sel, count_sel; // 6
+output count_up, top_enable, alu_enable;    // 3
+output [5:0] alu_op;                        // 6
+wire   [3:0] nx_ustate;                     // 4
+
+reg [21:0] ucode [0:65535];
+
+assign {read, write, iack, addr_sel, load_sel, count_sel, count_up, top_enable,
+        alu_enable, alu_op, nx_ustate} = ucode[ {ir, ustate, irq, alu_flags} ];
+
+initial begin
+    $readmemh(""microcode.hex"", ucode);
+end
+
+always @(posedge reset) begin
+    if (reset)
+        ustate <= 0;
+end
+
+always @(posedge clk) begin
+    ustate <= nx_ustate;
+end
+
+endmodule"
+"// test-bench for the ALU
+
+`timescale 1 ns / 100 ps
+
+module alu_testbench ();
+
+reg [15:0] A, B;
+reg [4:0] Op;
+reg Swap;
+wire [15:0] Q;
+wire Carry, Zero, Sign;
+
+BitsliceALU DUT (A, B, Op, Q, Flags);
+
+task test_vector;
+    input [4:0] testOp;
+    input [15:0] testA, testB;
+    input [15:0] expectQ;
+    input expectCarry, expectZero, expectMinus1;
+    begin
+        $display($time, ""M=%b, S=%h, Cn=%b, A = %h, B = %h"", testOp, testSwap, testA, testB);
+        A = testA;
+        B = testB;
+        Op = testOp;
+        Swap = testSwap;
+        #10 if ( (Q==expectQ) && (Carry==expectCarry) && (Zero==expectZero) && (Minus1==expectMinus1) )
+            $display($time, ""                                      passed."");
+        else
+            begin
+                if (Q != expectQ)
+                    $display($time, ""   ... FAILED with Q = %h"", Q);
+                if (Carry != expectCarry)
+                    $display($time, ""   ... FAILED with Carry = %h"", Carry);
+                if (Zero != expectZero)
+                    $display($time, ""   ... FAILED with Zero = %h"", Zero);
+                if (Minus1 != expectMinus1)
+                    $display($time, ""   ... FAILED with Minus1 = %h"", Minus1);
+            end
+    end
+endtask
+
+initial
+begin
+    $display($time, "" ##### Testing addition... #####"");
+    //                 MSSSS          AAAA     BBBB     QQQQ    C    Z   M1
+    #10 test_vector(5\'b01001,1\'b1,16\'h4444,16\'h2345,16\'h8967,1\'b0,1\'b0,1\'b0);
+    #10 test_vector(5\'b01001,1\'b0,16\'hf00f,16\'hc7c8,16\'hb7d7,1\'b1,1\'b0,1\'b0);
+    #10 test_vector(5\'b01001,1\'b1,16\'h3cc3,16\'h7cc7,16\'h8ab9,1\'b0,1\'b0,1\'b0);
+    #10 test_vector(5\'b01001,1\'b0,16\'hff00,16\'h0100,16\'h0000,1\'b1,1\'b1,1\'b0);
+    #10 test_vector(5\'b01001,1\'b1,16\'h0000,16\'h0000,16\'h0000,1\'b0,1\'b1,1\'b0);
+    #10 test_vector(5\'b01001,1\'b0,16\'h7777,16\'h8888,16\'hffff,1\'b0,1\'b0,1\'b1);
+end
+
+endmodule"
+"/* a 16-bit ALU built from four 74181\'s
+   Uses behavioral 74181 model from M. Hansen, H. Yalcin, and J. P. Hayes,
+   ""Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering,""
+   IEEE Design and Test, vol. 16, no. 3, pp. 72-80, July-Sept. 1999.
+   http://web.eecs.umich.edu/~jhayes/iscas.restore/
+ */
+   
+
+/* Operations: 
+    00 = A                      A plus 1
+    03 = minus 1                0
+    06 =                        A minus B
+    09 = A plus B
+    0c = A plus A
+    0f = A minus 1              A
+    10 = A\'
+    11 = A nor B
+    14 = A nand B
+    15 = B\'
+    16 = A xor B
+    19 = A xnor B
+    1a = B
+    1b = A and B
+    1c = 1
+    1e = A or B
+*/
+
+module BitsliceALU (A, B, Op, Q, Flags);
+    input  [15:0] A, B;
+    input  [5:0] Op;
+    output [15:0] Q;
+    output [2:0] Flags;
+    
+    wire Sign, Zero, Minus1, Carry, Overflow;
+    wire C3, C7, C11, C15;
+    wire Z3, Z7, Z11, Z15;
+    wire [3:0] X, Y;
+    wire [15:0] result;
+    
+    Circuit74181b slice3
+        (Op[4:1], A[3:0], B[3:0], Op[5], Op[0], result[3:0], X[0], Y[0], C3, Z3);
+    
+    Circuit74181b slice7
+        (Op[4:1], A[7:4], B[7:4], Op[5], C3, result[7:4], X[1], Y[1], C7, Z7);
+    
+    Circuit74181b slice11
+        (Op[4:1], A[11:8], B[11:8], Op[5], C7, result[11:8], X[2], Y[2], C11, Z11);
+    
+    Circuit74181b slice15
+        (Op[4:1], A[15:12], B[15:12], Op[5], C11, result[15:12], X[3],Y[3],C15,Z15);
+
+    assign Q = result;
+
+    assign Sign = result[15];
+
+    // infer single inverter
+    assign Carry = ~C15;
+
+    // assign Overflow = (A[15] == B[15]) && (A[15] ~= Sign);
+    
+    // infer 16-input AND
+    assign Zero = (Q == 16\'h0000);
+
+    // infer 4-input AND
+    // assign Minus1 = Z3 && Z7 && Z11 && Z15;
+
+    assign Flags = { Carry, Sign, Zero };
+endmodule"
+"module Top (clk, reset);
+
+input clk, reset;
+
+Datapath CPU (clk, irq, reset, addr, data, read, write);
+
+endmodule"
+"module Datapath (clk, reset, addr, data, read, write, irq, iack);
+
+input  clk, reset, irq;
+inout  [15:0] data;
+output [15:0] addr;
+output read, write, iack;
+
+reg  [15:0] top, next;
+reg  [15:0] pc, dsp, rsp;
+reg   [7:0] ir;
+
+wire  [1:0] addr_sel, load_sel, count_sel;
+wire        top_enable, alu_enable, count_up;
+wire  [5:0] alu_op;
+
+wire [15:0] alu_q;
+wire  [2:0] alu_flags;
+
+ControlFSM control (clk, reset, irq, read, write, iack, ir, alu_flags,
+    addr_sel, load_sel, count_sel, count_up, top_enable, alu_enable, alu_op);
+
+BitsliceALU alu (top, next, alu_op, alu_q, alu_flags);
+
+// infer two 16-bit tri-state buffers
+assign
+    data = (top_enable == 1) ? top : 16'bZ,
+    data = (alu_enable == 1) ? alu_q : 16'bZ;
+
+// infer 16-bit 4-way mux
+assign addr = (addr_sel == 0) ? top :
+              (addr_sel == 1) ? dsp :
+              (addr_sel == 2) ? rsp :
+              (addr_sel == 3) ? pc  :
+                                16'bX; 
+
+// implement asynchronous reset for all registers
+always @(posedge reset or posedge iack) begin
+    if (reset) begin
+        top  <= 0;
+        next <= 0;
+        dsp  <= 16'h7e00;
+        rsp  <= 16'h7c00;
+        ir   <= 0;
+    end
+    if (reset | iack) begin
+        pc <= 16'h0000;
+    end
+end
+        
+// infer 2 2-to-4 decoders
+// infer 3 16-bit registers with clock enable
+// infer 1 16-bit up counter with clock enable and synchronous load
+// infer 2 16-bit up-down counters with clock enable
+always @(posedge clk) begin
+    case (load_sel)
+        0:       top  <= data;
+        1:       next <= data;
+        2:       ir   <= data[7:0];
+        3:       pc   <= data;
+    endcase
+
+    case (count_sel)
+        1: dsp <= count_up ? dsp + 1 : dsp - 1;
+        2: rsp <= count_up ? rsp + 1 : rsp - 1;
+        3: if (load_sel != 3) pc <= pc + 1;
+    endcase   
+end
+
+endmodule"
+"module ghrd_10m50da_top (
+  //Clock and Reset
+  input  wire       clk_50,
+  //input  wire       clk_ddr3_100_p,
+  input  wire       fpga_reset_n,
+  //QSPI
+  output wire     \t qspi_clk,
+  inout  wire[3:0]    qspi_io,
+  output wire         qspi_csn,
+\t//ddr3
+   //output wire [13:0] mem_a,
+   //output wire [2:0]  mem_ba,
+   //inout  wire [0:0]  mem_ck,
+   //inout  wire [0:0]  mem_ck_n,
+   //output wire [0:0]  mem_cke,
+   //output wire [0:0]  mem_cs_n,
+   //output wire [0:0]  mem_dm,
+   //output wire [0:0]  mem_ras_n,
+   //output wire [0:0]  mem_cas_n,
+   //output wire [0:0]  mem_we_n,
+   //output wire        mem_reset_n,
+   ///inout  wire [7:0]  mem_dq,
+   //inout  wire [0:0]  mem_dqs,
+   //inout  wire [0:0]  mem_dqs_n,
+   //output wire [0:0]  mem_odt,
+   //i2c
+\tinout  wire         i2c_sda,
+   inout  wire         i2c_scl,
+   //spi
+\tinput wire \t\t\tspi_miso,
+\toutput wire\t\t\tspi_mosi,
+\toutput wire \t\tspi_sclk,
+\toutput wire \t\tspi_ssn,
+  //16550 UART
+  input wire\t     uart_rx,
+  output wire \t\t  uart_tx,
+  output wire [4:0] user_led
+);
+//Heart-beat counter
+reg   [25:0]  heart_beat_cnt;
+
+//DDR3 interface assignments
+//wire          local_init_done;
+//wire          local_cal_success;
+//wire          local_cal_fail;
+
+//i2c interface
+wire i2c_serial_sda_in ;
+wire i2c_serial_scl_in ;
+wire i2c_serial_sda_oe ;
+wire i2c_serial_scl_oe ;
+assign i2c_serial_scl_in = i2c_scl;
+assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz;
+
+assign i2c_serial_sda_in = i2c_sda;
+assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz;
+
+//assign system_resetn = fpga_reset_n & local_init_done;
+
+// SoC sub-system module
+ghrd_10m50da ghrd_10m50da_inst (
+\t\t.clk_clk                                                  \t\t(clk_50),
+\t\t//.ref_clock_bridge_in_clk_clk\t\t\t\t\t\t\t\t\t\t\t\t(clk_ddr3_100_p),
+\t\t.reset_reset_n                                           \t\t(fpga_reset_n),
+\t\t//.mem_resetn_in_reset_reset_n                                   (fpga_reset_n               ), //                 mem_resetn_in_reset.reset_n
+\t\t.ext_flash_qspi_pins_data                       \t\t\t\t\t(qspi_io),
+\t\t.ext_flash_qspi_pins_dclk                     \t\t\t\t\t\t(qspi_clk),
+\t\t.ext_flash_qspi_pins_ncs                               \t\t\t(qspi_csn),
+\t\t//.memory_mem_a                                                  (mem_a[12:0]               ), //                              memory.mem_a
+      //.memory_mem_ba                                                 (mem_ba                    ), //                                    .mem_ba
+      //.memory_mem_ck                                                 (mem_ck                    ), //                                    .mem_ck
+      //.memory_mem_ck_n                                               (mem_ck_n                  ), //                                    .mem_ck_n
+      //.memory_mem_cke                                                (mem_cke                   ), //                                    .mem_cke
+      //.memory_mem_cs_n                                               (mem_cs_n                  ), //                                    .mem_cs_n
+      //.memory_mem_dm                                                 (mem_dm                    ), //                                    .mem_dm
+      //.memory_mem_ras_n                                              (mem_ras_n                 ), //                                    .mem_ras_n
+      //.memory_mem_cas_n                                              (mem_cas_n                 ), //                                    .mem_cas_n
+      //.memory_mem_we_n                                               (mem_we_n                  ), //                                    .mem_we_n
+      //.memory_mem_reset_n                                            (mem_reset_n               ), //                                    .mem_reset_n
+      //.memory_mem_dq                                                 (mem_dq                    ), //                                    .mem_dq
+      //.memory_mem_dqs                                                (mem_dqs                   ), //                                    .mem_dqs
+      //.memory_mem_dqs_n                                              (mem_dqs_n                 ), //                                    .mem_dqs_n
+      //.memory_mem_odt                                                (mem_odt                   ), //                                    .mem_odt
+      //.mem_if_ddr3_emif_0_status_local_init_done                     (local_init_done           ), //           mem_if_ddr3_emif_0_status.local_init_done
+      //.mem_if_ddr3_emif_0_status_local_cal_success                   (local_cal_success         ), //                                    .local_cal_success
+      //.mem_if_ddr3_emif_0_status_local_cal_fail                      (local_cal_fail            ),  //                                    .local_cal_fail
+\t\t//i2c
+\t\t.i2c_0_i2c_serial_sda_in\t\t\t\t\t\t\t\t\t\t\t\t\t(i2c_serial_sda_in),
+\t\t.i2c_0_i2c_serial_scl_in\t\t\t\t\t\t\t\t\t\t\t\t\t(i2c_serial_scl_in),
+\t\t.i2c_0_i2c_serial_sda_oe\t\t\t\t\t\t\t\t\t\t\t\t\t(i2c_serial_sda_oe),
+\t\t.i2c_0_i2c_serial_scl_oe\t\t\t\t\t\t\t\t\t\t\t\t\t(i2c_serial_scl_oe),
+\t\t//spi
+\t\t.spi_0_external_MISO                           \t\t\t\t\t\t(spi_miso),\t\t\t\t\t\t\t\t//                           spi_0_external.MISO
+\t\t.spi_0_external_MOSI                          \t\t\t\t\t\t(spi_mosi),\t\t\t\t\t\t\t\t//                                         .MOSI
+\t\t.spi_0_external_SCLK                           \t\t\t\t\t\t(spi_sclk),\t\t\t\t\t\t\t\t//                                         .SCLK
+\t\t.spi_0_external_SS_n                            \t\t\t\t\t(spi_ssn),\t\t\t\t\t\t\t\t//                                         .SS_n
+\t\t//pio
+\t\t.led_external_connection_export\t\t\t\t\t\t\t\t\t\t\t(user_led[3:0]),
+\t\t//16550 UART
+\t\t.a_16550_uart_0_rs_232_serial_sin (uart_rx),                    //           a_16550_uart_0_rs_232_serial.sin
+\t\t.a_16550_uart_0_rs_232_serial_sout (uart_tx),                   //                                       .sout
+\t\t.a_16550_uart_0_rs_232_serial_sout_oe ()                //                                       .sout_oe
+
+);
+
+//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16)
+//assign mem_a[13] = 1'b0;
+
+//Heart beat by 50MHz clock
+always @(posedge clk_50 or negedge fpga_reset_n)
+  if (!fpga_reset_n)
+      heart_beat_cnt <= 26'h0; //0x3FFFFFF
+  else
+      heart_beat_cnt <= heart_beat_cnt + 1'b1;
+
+assign user_led[4] = heart_beat_cnt[25];
+ 
+
+endmodule
+
+
+"
+"// ********************************************************************/ 
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+ //  
+//
+// spi.v -- top level module for spi core
+//
+//
+// Revision Information:
+// Date     Description
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+// Resolved SARs
+// SAR      Date     Who   Description
+//
+// Notes: 
+//
+//
+// *********************************************************************/ 
+
+
+module spi(   //inputs
+//              TESTMODE,
+              PCLK,       //system clock
+              PRESETN,    //system reset
+              PADDR,      //address line
+              PSEL,       //device select
+              PENABLE,    //enable
+              PWRITE,     //write
+              PWDATA,     //write data
+              SPISSI,     //slave select
+              SPISDI,     //serial data in
+              SPICLKI,    //serial clock in
+
+              //outputs
+              PRDDATA,    //data read
+              SPIINT,     //interrupt
+              SPISS,      //slave select
+              SPISCLKO,   //serial clock out
+              SPIRXAVAIL, //data ready to be read (dma mode)
+              SPITXRFM,   //room for more (dma mode)
+              SPIOEN,     //output enable
+              SPISDO,     //serial data out
+              SPIMODE     //1 -> master, 0 -> slave
+              );
+
+// AS: Added Parameters to replace 
+// configuration bits / registers
+parameter               APB_DWIDTH      =   8;
+parameter               CFG_FRAME_SIZE  =   4;
+parameter               FIFO_DEPTH      =   4;
+parameter               CFG_CLK         =   7;
+parameter               CFG_SPO         =   0;
+parameter               CFG_SPH         =   0;
+parameter               CFG_SPS         =   0;
+parameter               CFG_MODE        =   0;
+              
+//input TESTMODE;
+input PCLK;
+input PRESETN;
+input [6:0] PADDR;
+input PSEL;
+input PENABLE;
+input PWRITE;
+input [APB_DWIDTH-1:0] PWDATA;
+input SPISSI;
+input SPISDI;
+input SPICLKI;
+
+
+output [APB_DWIDTH-1:0] PRDDATA;
+
+output SPIINT;
+output [7:0] SPISS;
+output SPISCLKO;
+output SPIRXAVAIL;
+output SPITXRFM;
+output SPIOEN;
+output SPIMODE;
+output SPISDO;
+
+
+// Do not declare single bit block connections unless required
+
+wire [APB_DWIDTH-1:0] prdata_regs;            
+// ---------------------
+// AS: removed features:
+// ---------------------
+//wire [1:0]  cfg_mode;        
+//wire [5:0]  cfg_framesize;        
+//wire [7:0]  cfg_clkrate;        
+//wire [15:0] cfg_framecnt;  
+wire [7:0]  cfg_ssel;             
+//wire [1:0]  cfg_fifosize;             
+wire        cfg_master;
+wire        cfg_enable;
+//wire [5:0]  cfg_pktsize;
+wire [2:0]  cfg_cmdsize;
+//wire [1:0]  cfg_userstatus;
+
+wire [CFG_FRAME_SIZE-1:0] tx_fifo_data_in;      
+wire [CFG_FRAME_SIZE-1:0] tx_fifo_data_out;     
+wire [CFG_FRAME_SIZE-1:0] rx_fifo_data_in;      
+wire [CFG_FRAME_SIZE-1:0] rx_fifo_data_out;     
+
+wire rx_fifo_empty;
+wire tx_fifo_full;
+wire master_ssel_out;
+wire [5:0]   rx_fifo_count;
+wire [5:0]   tx_fifo_count;
+
+
+//##########################################################################################
+//APB Signals 
+
+
+wire  [6:0]  PADDR32 = { PADDR[6:2], 2'b00 };
+
+
+//read data: either from the register file or the fifo.
+// ------------------------
+// AS: adjusted PADDR value, changed to async
+// ------------------------
+assign PRDDATA = ~(PADDR32[6:0]==7'h08) ? prdata_regs :  rx_fifo_data_out;
+
+assign SPIMODE    = cfg_master;
+assign SPIRXAVAIL = ~rx_fifo_empty;
+assign SPITXRFM   = ~tx_fifo_full;
+
+
+// ----------------------------------------------------------------------------------
+// Channel Outputs
+
+//Pass the slave select to the selected devices. If no slave select asserted then everything off
+
+reg [7:0]  master_ssel_all;
+assign SPISS = master_ssel_all;
+
+integer i;
+always @(*)
+   begin
+      if (cfg_enable && cfg_master)
+         begin
+            for (i=0; i<8; i=i+1)
+             begin
+               if (cfg_ssel[i])
+                  master_ssel_all[i] = master_ssel_out;
+               else
+                  master_ssel_all[i] = (CFG_MODE != 1);   //Send low in TIMODE to deselect
+             end
+         end
+      else
+         begin
+            for (i =0; i<8; i=i+1)
+                 master_ssel_all[i] = (CFG_MODE != 1);    //Send low in TIMODE to deselect
+         end
+   end      
+      
+wire  ssel_both = ( cfg_master ? master_ssel_out : SPISSI ); 
+
+
+//-----------------------------------------------------------------------------------------
+
+
+// The Register Set
+spi_rf # (
+          .APB_DWIDTH(APB_DWIDTH)
+)
+URF    ( .pclk                 (PCLK),                           
+                .presetn              (PRESETN),                        
+                .paddr                (PADDR32[6:0]),                   
+                .psel                 (PSEL),
+                .penable              (PENABLE),                             
+                .pwrite               (PWRITE),                         
+                .wrdata               (PWDATA),                         
+                .prdata               (prdata_regs),                    
+                .interrupt            (SPIINT),                         
+              
+                .tx_channel_underflow (tx_channel_underflow),           
+                .rx_channel_overflow  (rx_channel_overflow),           
+                .tx_done              (tx_done),                        
+                .rx_done              (rx_done),                        
+                .rx_fifo_read         (rx_fifo_read),                   
+                .tx_fifo_write        (tx_fifo_write),                  
+                .tx_fifo_read         (tx_fifo_read),                  
+                .rx_fifo_full         (rx_fifo_full),                   
+                .rx_fifo_full_next    (rx_fifo_full_next),              
+                .rx_fifo_empty        (rx_fifo_empty),                  
+                .rx_fifo_empty_next   (rx_fifo_empty_next),             
+                .tx_fifo_full         (tx_fifo_full),                   
+                .tx_fifo_full_next    (tx_fifo_full_next),              
+                .tx_fifo_empty        (tx_fifo_empty), 
+                .tx_fifo_empty_next   (tx_fifo_empty_next), 
+                .first_frame          (first_frame_out), 
+                //.frames_done_fill     (tx_fifo_last_in),                       
+                //.frames_done_empty    (rx_done),
+                .ssel                 (ssel_both),                       
+                //.hw_txbusy            (hw_txbusy),                         
+                //.hw_rxbusy            (hw_rxbusy),                        
+                .rx_pktend            (rx_pktend),
+                .rx_cmdsize           (rx_cmdsize),
+                .active               (active),
+
+                .cfg_enable           (cfg_enable),                    
+                //.cfg_mode             (cfg_mode),                       
+                .cfg_master           (cfg_master),
+// AS: removed a bunch of register bits
+//     (now parameter-driven)
+                //.cfg_spo              (cfg_spo),                       
+                //.cfg_sph              (cfg_sph),                       
+                //.cfg_sps              (cfg_sps),                       
+                //.cfg_framesize        (cfg_framesize),                 
+                //.cfg_clkmode          (cfg_clkmode),                   
+                //.cfg_clkrate          (cfg_clkrate),                   
+                //.cfg_framecnt         (cfg_framecnt),                
+                .cfg_ssel             (cfg_ssel),                      
+                //.cfg_fifosize         (cfg_fifosize),
+                .cfg_cmdsize          (cfg_cmdsize),                    
+                //.cfg_pktsize          (cfg_pktsize),                    
+                //.cfg_userstatus       (cfg_userstatus),
+                .clr_txfifo           (fiforsttx),                     
+                .clr_rxfifo           (fiforstrx),                  
+                //.auto_fill            (auto_fill),
+                //.auto_empty           (auto_empty),
+                //.auto_stall           (auto_stall),
+                //.auto_txnow           (auto_txnow),
+                //.cfg_autopoll         (cfg_autopoll),
+                //.cfg_autostatus       (cfg_autostatus),
+                .cfg_frameurun        (cfg_frameurun),
+                //.clr_framecnt         (clr_framecnt),
+                .cfg_oenoff           (cfg_oenoff)
+              );
+
+
+// APB side of FIFOs Control    
+
+spi_control # (
+                   .CFG_FRAME_SIZE       (CFG_FRAME_SIZE)
+)           UCON ( .pclk                 (PCLK),
+                   .presetn              (PRESETN),
+                   .psel                 (PSEL),
+                   .penable              (PENABLE),
+                   .pwrite               (PWRITE),
+                   .paddr                (PADDR32[6:0]),
+                   .wr_data_in           (PWDATA[CFG_FRAME_SIZE-1:0]),          // AS: use only FRAME_SIZE bits for data
+                   //.auto_fill            (auto_fill),                 
+                   //.auto_empty           (auto_empty),
+                   .cfg_master           (cfg_master),
+                   //.cfg_framecnt         (cfg_framecnt), 
+                   .tx_fifo_data         (tx_fifo_data_in),     
+                   .tx_fifo_write        (tx_fifo_write),       
+                   .tx_fifo_last         (tx_fifo_last_in),        
+                   .tx_fifo_empty        (tx_fifo_empty),
+                   .rx_fifo_read         (rx_fifo_read),
+                   //.clear_frame_count    (clr_framecnt),
+                   //.fill_okay            (fill_okay),
+                   .rx_fifo_empty        (rx_fifo_empty)             
+                   //.rx_fifo_first        (first_frame_out)             
+                   );
+
+
+//Transmit Fifo
+
+spi_fifo # (
+                   .CFG_FRAME_SIZE  (CFG_FRAME_SIZE),
+                   .FIFO_DEPTH      (FIFO_DEPTH)
+) UTXF    (        .pclk            (PCLK), 
+                   .presetn         (PRESETN), 
+                   .fiforst         (fiforsttx),
+                   //.fifosize        (cfg_fifosize),
+                   .data_in         (tx_fifo_data_in),               
+                   .flag_in         (tx_fifo_last_in),                  
+                   .data_out        (tx_fifo_data_out),              
+                   .flag_out        (tx_fifo_last_out),              
+                   .read_in         (tx_fifo_read),                  
+                   .write_in        (tx_fifo_write),                 
+                   .full_out        (tx_fifo_full),                  
+                   .empty_out       (tx_fifo_empty),                 
+                   .full_next_out   (tx_fifo_full_next),             
+                   .empty_next_out  (tx_fifo_empty_next),            
+                   .overflow_out    (not_used1),              
+                   .fifo_count      (tx_fifo_count)
+                   );
+
+
+
+//Receive Fifo
+
+spi_fifo # (
+          .CFG_FRAME_SIZE(CFG_FRAME_SIZE),
+          .FIFO_DEPTH(FIFO_DEPTH)
+          
+) URXF     ( .pclk            (PCLK), 
+                    .presetn         (PRESETN), 
+                    .fiforst         (fiforstrx),
+                    //.fifosize        (cfg_fifosize),
+                    .data_in         (rx_fifo_data_in),             
+                    .write_in        (rx_fifo_write), 
+                    .flag_in         (rx_fifo_first_in),             
+                    .data_out        (rx_fifo_data_out),            
+                    .read_in         (rx_fifo_read),                
+                    .flag_out        (first_frame_out),             
+                    .full_out        (rx_fifo_full),                
+                    .empty_out       (rx_fifo_empty),               
+                    .empty_next_out  (rx_fifo_empty_next),          
+                    .full_next_out   (rx_fifo_full_next),           
+                    .overflow_out    (rx_channel_overflow),         
+                    .fifo_count      (rx_fifo_count)
+                    );
+
+
+//Channel controll
+
+spi_chanctrl # (
+  // parameters (AS)
+  .CFG_SPH            (CFG_SPH),
+  .CFG_SPO            (CFG_SPO),
+  .CFG_SPS            (CFG_SPS),
+  .CFG_MODE           (CFG_MODE),
+  .CFG_CLKRATE        (CFG_CLK),
+  // no clock mode parameter (removed)
+  .CFG_FRAME_SIZE      (CFG_FRAME_SIZE)
+)UCC   (               .pclk               (PCLK),      
+                       .presetn            (PRESETN), 
+//                       .testmode           (TESTMODE),         
+                       .spi_clk_in         (SPICLKI),      
+                       .spi_clk_out        (SPISCLKO),        
+                       .spi_ssel_in        (SPISSI),
+                       .spi_ssel_out       (master_ssel_out),    
+                       .spi_data_in        (SPISDI),
+                       .spi_data_out       (SPISDO), 
+                       .spi_data_oen       (SPIOEN),
+                       .txfifo_count       (tx_fifo_count),
+                       .txfifo_empty       (tx_fifo_empty),       
+                       .txfifo_read        (tx_fifo_read), 
+                       .txfifo_data        (tx_fifo_data_out),
+                       .txfifo_last        (tx_fifo_last_out),
+                       .rxfifo_count       (rx_fifo_count),
+                       .rxfifo_write       (rx_fifo_write),
+                       .rxfifo_data        (rx_fifo_data_in),
+                       .rxfifo_first       (rx_fifo_first_in), 
+                       .cfg_enable         (cfg_enable), 
+                       .cfg_master         (cfg_master), 
+                       //.cfg_mode           (cfg_mode),        
+                       //.cfg_sph            (cfg_sph),        
+                       //.cfg_spo            (cfg_spo),       
+                       //.cfg_sps            (cfg_sps),
+                       //.cfg_autopoll       (cfg_autopoll),
+                       .cfg_frameurun      (cfg_frameurun),
+                       //.cfg_autostatus     (cfg_autostatus), 
+                       //.cfg_clkmode        (cfg_clkmode), 
+                       //.cfg_clkrate        (cfg_clkrate),
+                       //.cfg_fifosize       (cfg_fifosize), 
+                       //.cfg_framesize      (cfg_framesize), 
+                       //.cfg_userstatus     (cfg_userstatus),         
+                       .cfg_cmdsize        (cfg_cmdsize),
+                       //.cfg_pktsize        (cfg_pktsize),
+                       .cfg_oenoff         (cfg_oenoff),
+                       //.auto_stall         (auto_stall),
+                       //.auto_txnow         (auto_txnow),
+                       //.hw_rxbusy          (hw_rxbusy),
+                       //.hw_txbusy          (hw_txbusy),
+                       .tx_alldone         (tx_done), 
+                       .rx_alldone         (rx_done), 
+                       .rx_pktend          (rx_pktend),
+                       .rx_cmdsize         (rx_cmdsize),
+                       .tx_underrun        (tx_channel_underflow),
+                       //.fill_okay          (fill_okay),
+                       .active             (active) 
+                     );                 
+
+
+
+endmodule
+
+
+   "
+"// ********************************************************************/ 
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+//  
+// Description: AMBA BFMs
+//              BFM Support Package  
+//
+// Revision Information:
+// Date     Description
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+//
+// Resolved SARs
+// SAR      Date     Who  Description
+//
+//
+// Notes: 
+//        
+// *********************************************************************/ 
+
+    //-------------------------------------------------------------------------------------------
+    // Constants
+    localparam C_VECTORS_VERSION = 22; 
+    // Command Encodings in Vectors
+    localparam C_NOP = 0; 
+    localparam C_WRITE = 4; 
+    localparam C_READ = 8; 
+    localparam C_RDCHK = 12; 
+    localparam C_RDMSK = 16; 
+    localparam C_POLL = 20; 
+    localparam C_POLLM = 24; 
+    localparam C_POLLB = 28; 
+    localparam C_WRTM = 32; 
+    localparam C_FILL = 36; 
+    localparam C_WRTT = 40; 
+    localparam C_RDM = 44; 
+    localparam C_RDMC = 48; 
+    localparam C_READF = 52; 
+    localparam C_READT = 56; 
+    localparam C_IOTST = 60; 
+    localparam C_IOWAIT = 64; 
+    localparam C_READS = 68;
+    localparam C_AHBC  = 72;
+    localparam C_WRTA  = 76;
+    localparam C_READA = 80;
+     
+    localparam C_IOWR = 100; 
+    localparam C_IORD = 101; 
+    localparam C_IOCHK = 102; 
+    localparam C_IOMSK = 103; 
+    localparam C_IOSET = 104; 
+    localparam C_IOCLR = 105; 
+    localparam C_INTREQ = 106; 
+    localparam C_FIQ = 107; 
+    localparam C_IRQ = 108; 
+    localparam C_HRESP = 109; 
+    localparam C_EXTW = 110; 
+    localparam C_EXTR = 111; 
+    localparam C_EXTRC = 112; 
+    localparam C_EXTMSK = 113; 
+    localparam C_EXTWT = 114; 
+    localparam C_EXTWM = 115; 
+    localparam C_LABEL = 128; 
+    localparam C_JMP = 129; 
+    localparam C_JMPZ = 130; 
+    localparam C_JMPNZ = 131; 
+    localparam C_CALL = 132; 
+    localparam C_CALLP = 133; 
+    localparam C_RET = 134; 
+    localparam C_LOOP = 135; 
+    localparam C_LOOPE = 136; 
+    localparam C_WAIT = 137; 
+    localparam C_STOP = 138; 
+    localparam C_QUIT = 139; 
+    localparam C_TOUT = 140; 
+    localparam C_TABLE = 141; 
+    localparam C_FLUSH = 142; 
+    localparam C_PRINT = 150; 
+    localparam C_HEAD = 151; 
+    localparam C_FILEN = 152; 
+    localparam C_MEMT = 153; 
+    localparam C_MEMT2 = 154; 
+    localparam C_MODE = 160; 
+    localparam C_SETUP = 161; 
+    localparam C_DEBUG = 162; 
+    localparam C_PROT = 163; 
+    localparam C_LOCK = 164; 
+    localparam C_ERROR = 165; 
+    localparam C_BURST = 166; 
+    localparam C_CHKT = 167; 
+    localparam C_SFAIL  = 168;
+    localparam C_STTIM  = 169;
+    localparam C_CKTIM  = 170;
+    localparam C_RAND  = 171;
+    localparam C_CONPU = 172;
+        
+    localparam C_MMAP      = 200;
+    localparam C_SET       = 201;
+    localparam C_CONS      = 202;
+    localparam C_INT       = 203;
+    localparam C_CALC      = 204;
+    localparam C_CMP       = 205;
+    localparam C_RESET     = 206;
+    localparam C_CLKS      = 207;
+    localparam C_IF        = 208;
+    localparam C_IFNOT     = 209;
+    localparam C_WHILE     = 210;
+    localparam C_ELSE      = 211;
+    localparam C_ENDIF     = 212;
+    localparam C_ENDWHILE  = 213;
+    localparam C_CASE      = 214;
+    localparam C_WHEN      = 215;
+    localparam C_ENDCASE   = 216;
+    localparam C_DEFAULT   = 217;
+    localparam C_CMPR      = 218;
+    localparam C_RETV      = 219;
+    localparam C_WAITNS    = 220;
+    localparam C_WAITUS    = 221;
+    localparam C_DRVX      = 222;
+
+    localparam  C_VERS     = 250;
+    localparam  C_LOGF     = 251;
+    localparam  C_LOGS     = 252;
+    localparam  C_LOGE     = 253;
+    localparam  C_ECHO     = 254;
+    localparam  C_FAIL     = 255;
+        
+    
+    
+     
+    localparam OP_NONE = 1001; 
+    localparam OP_ADD = 1002; 
+    localparam OP_SUB = 1003; 
+    localparam OP_MULT = 1004; 
+    localparam OP_DIV = 1005; 
+    localparam OP_MOD = 1006; 
+    localparam OP_POW = 1007; 
+    localparam OP_AND = 1008; 
+    localparam OP_OR = 1009; 
+    localparam OP_XOR = 1010; 
+    localparam OP_CMP = 1011; 
+    localparam OP_SHL = 1012; 
+    localparam OP_SHR = 1013; 
+    localparam OP_EQ = 1014; 
+    localparam OP_NEQ = 1015; 
+    localparam OP_GR = 1016; 
+    localparam OP_LS = 1017; 
+    localparam OP_GRE = 1018; 
+    localparam OP_LSE = 1019; 
+    localparam OP_SETB = 1020; 
+    localparam OP_CLRB = 1021; 
+    localparam OP_INVB = 1022; 
+    localparam OP_TSTB = 1023; 
+
+    localparam  D_RESERVED  = 0;
+    localparam  D_RETVALUE  = 1;
+    localparam  D_TIME      = 2;
+    localparam  D_DEBUG     = 3;
+    localparam  D_LINENO    = 4;
+    localparam  D_ERRORS    = 5;
+    localparam  D_TIMER     = 6;
+    localparam  D_LTIMER    = 7;
+    localparam  D_LICYCLES  = 8;
+
+
+    localparam  D_NORMAL  = 0;
+    localparam  D_ARGVALUE  = 1;
+    localparam  D_RAND      = 2;
+    localparam  D_RANDSET   = 3;
+    localparam  D_RANDRESET = 4;
+ 
+    localparam  E_DATA   = 32\'h00000000;   
+    localparam  E_ADDR   = 32\'h00002000;   
+    localparam  E_STACK  = 32\'h00004000;
+    localparam  E_CONST  = 32\'h00006000;   
+    localparam  E_ARRAY  = 32\'h00008000;   
+     
+   
+    localparam[1:0] B_Tcommand_s = 0; 
+    localparam[1:0] H = 1; 
+    localparam[1:0] W = 2; 
+    localparam[1:0] X = 3; 
+
+    function integer to_int;
+        input [31:0] xlv; 
+        integer X; 
+        begin
+            X = xlv; 
+            to_int = X; 
+        end
+    endfunction
+
+    function integer to_int_unsigned;
+        input [31:0] xlv; 
+        integer xlv;
+        integer X; 
+
+        begin
+            X = xlv; 
+            to_int_unsigned = X; 
+        end
+    endfunction
+
+    function integer to_int_signed;
+        input [31:0] xlv; 
+        integer X; 
+
+        begin
+            X = xlv; 
+            to_int_signed = X; 
+        end
+    endfunction
+
+    function [31:0] to_slv32;
+        input X; 
+        integer X;
+
+        reg[31:0] xlv; 
+
+        begin
+            xlv = X; 
+            to_slv32 = xlv; 
+        end
+    endfunction
+
+
+    function [31:0] align_data;
+        input[2:0] size; 
+        input[1:0] addr10; 
+        input[31:0] datain; 
+        input alignmode; 
+        integer alignmode;
+
+        reg[31:0] adata; 
+        reg addr1; 
+
+        begin
+            adata = {32{1\'b0}}; 
+            case (alignmode)
+                0 :
+                            begin
+                                case (size)
+                                    3\'b000 :
+                                                begin
+                                                    // Normal operation, data is correctly aligned for a 32 bit bus 
+                                                    case (addr10)
+                                                        2\'b00 :
+                                                                    begin
+                                                                        adata[7:0] = datain[7:0]; 
+                                                                    end
+                                                        2\'b01 :
+                                                                    begin
+                                                                        adata[15:8] = datain[7:0]; 
+                                                                    end
+                                                        2\'b10 :
+                                                                    begin
+                                                                        adata[23:16] = datain[7:0]; 
+                                                                    end
+                                                        2\'b11 :
+                                                                    begin
+                                                                        adata[31:24] = datain[7:0]; 
+                                                                    end
+                                                        default :
+                                                                    begin
+                                                                    end
+                                                    endcase 
+                                                end
+                                    3\'b001 :
+                                                begin
+                                                    case (addr10)
+                                                        2\'b00 :
+                                                                    begin
+                                                                        adata[15:0] = datain[15:0]; 
+                                                                    end
+                                                        2\'b01 :
+                                                                    begin
+                                                                        adata[15:0] = datain[15:0]; 
+                                                                        $display(""BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)""); 
+                                                                    end
+                                                        2\'b10 :
+                                                                    begin
+                                                                        adata[31:16] = datain[15:0]; 
+                                                                    end
+                                                        2\'b11 :
+                                                                    begin
+                                                                        adata[31:16] = datain[15:0]; 
+                                                                        $display(""BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)""); 
+                                                                    end
+                                                        default :
+                                                                    begin
+                                                                    end
+                                                    endcase 
+                                                end
+                                    3\'b010 :
+                                                begin
+                                                    adata = datain; 
+                                                    case (addr10)
+                                                        2\'b00 :
+                                                                    begin
+                                                                    end
+                                                        2\'b01 :
+                                                                    begin
+                                                                        $display(""BFM: Missaligned AHB Cycle(Word A10=01) ? (WARNING)""); 
+                                                                    end
+                                                        2\'b10 :
+                                                                    begin
+                                                                        $display(""BFM: Missaligned AHB Cycle(Word A10=10) ? (WARNING)""); 
+                                                                    end
+                                                        2\'b11 :
+                                                                    begin
+                                                                        $display(""BFM: Missaligned AHB Cycle(Word A10=11) ? (WARNING)""); 
+                                                                    end
+                                                        default :
+                                                                    begin
+                                                                    end
+                                                    endcase 
+                                                end
+                                    default :
+                                                begin
+                                                    $display(""Unexpected AHB Size setting (ERROR)""); 
+                                                end
+                                endcase 
+                            end
+                1 :
+                            begin
+                                case (size)
+                                    3\'b000 :
+                                                begin
+                                                    // Normal operation, data is correctly aligned for a 16 bit bus 
+                                                    case (addr10)
+                                                        2\'b00 :
+                                                                    begin
+                                                                        adata[7:0] = datain[7:0]; 
+                                                                    end
+                                                        2\'b01 :
+                                                                    begin
+                                                                        adata[15:8] = datain[7:0]; 
+                                                                    end
+                                                        2\'b10 :
+                                                                    begin
+                                                                        adata[7:0] = datain[7:0]; 
+                                                                    end
+                                                        2\'b11 :
+                                                                    begin
+                                                                        adata[15:8] = datain[7:0]; 
+                                                                    end
+                                                        default :
+                                                                    begin
+                                                                    end
+                                                    endcase 
+                                                end
+                                    3\'b001 :
+                                                begin
+                                                    adata[15:0] = datain[15:0]; 
+                                                    case (addr10)
+                                                        2\'b00 :
+                                                                    begin
+                                                                    end
+                                                        2\'b01 :
+                                                                    begin
+                                                                        $display(""BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)""); 
+                                                                    end
+                                                        2\'b10 :
+                                                                    begin
+                                                                        $display(""BFM: Missaligned AHB Cycle(Half A10=10) ? (WARNING)""); 
+                                                                    end
+                                                        2\'b11 :
+                                                                    begin
+                                                                        $display(""BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)""); 
+                                                                    end
+                                                        default :
+                                                                    begin
+                                                                    end
+                                                    endcase 
+                                                end
+                                    default :
+                                                begin
+                                                    $display(""Unexpected AHB Size setting (ERROR)""); 
+                                                end
+                                endcase 
+                            end
+                2 :
+                            begin
+                                // Normal operation, data is correctly aligned for a 8 bit bus 
+                                case (size)
+                                    3\'b000 :
+                                                begin
+                                                    adata[7:0] = datain[7:0]; 
+                                                end
+                                    default :
+                                                begin
+                                                    $display(""Unexpected AHB Size setting (ERROR)""); 
+                                                end
+                                endcase 
+                            end
+                8 :
+                            begin
+                                // No alignment takes place
+                                adata = datain; 
+                            end
+                default :
+                            begin
+                                $display(""Illegal Alignment mode (ERROR)""); 
+                            end
+            endcase 
+            align_data = adata; 
+        end
+    endfunction
+
+    function [31:0] align_mask;
+        input[2:0] size; 
+        input[1:0] addr10; 
+        input[31:0] datain; 
+        input alignmode; 
+        integer alignmode;
+
+        reg[31:0] adata; 
+
+        begin
+            adata = align_data(size, addr10, datain, alignmode); 
+            align_mask = adata; 
+        end
+    endfunction
+
+    function [31:0] align_read;
+        input[2:0] size; 
+        input[1:0] addr10; 
+        input[31:0] datain; 
+        input alignmode; 
+        integer alignmode;
+
+        reg[31:0] adata; 
+        reg addr1; 
+
+        begin
+            if (alignmode == 8)
+            begin
+                adata = datain; 
+            end
+            else
+            begin
+              adata = 0; 
+              addr1 = addr10[1]; 
+              case (size)
+                  3\'b000 :    begin
+                                  case (addr10)
+                                      2\'b00 :\t adata[7:0] = datain[7:0  ]; 
+                                      2\'b01 :\t adata[7:0] = datain[15:8 ]; 
+                                      2\'b10 :\t adata[7:0] = datain[23:16]; 
+                                      2\'b11 :\t adata[7:0] = datain[31:24]; 
+                                      default : begin
+                                                end
+                                  endcase 
+                              end
+                  3\'b001 :    begin
+                                  case (addr1)
+                                      1\'b0 : adata[15:0] = datain[15:0]; 
+                                      1\'b1 : adata[15:0] = datain[31:16]; 
+                                      default : begin
+                                                end
+                                  endcase 
+                              end
+                  3\'b010 :    begin
+                                  adata = datain; 
+                              end
+                  default :       $display(""Unexpected AHB Size setting (ERROR)""); 
+              endcase 
+            end
+            align_read = adata; 
+        end
+    endfunction
+
+    function  integer to_ascii;
+        input X; 
+        integer X;
+
+        integer  c; 
+
+        begin
+            c = X; 
+            to_ascii = c; 
+        end
+    endfunction
+
+
+    function integer to_char;
+        input size; 
+        integer size;
+
+        integer c; 
+
+        begin
+            case (size)
+                0 :
+                            begin
+                                c = \'h62;  //\'b\'
+                            end
+                1 :
+                            begin
+                                c = \'h68; //\'h\'; 
+                            end
+                2 :
+                            begin
+                                c = \'h77; //\'w\'; 
+                            end
+                3 :
+                            begin
+                                c = \'h78 ; //\'x\';
+                            end
+                default :
+                            begin
+                                c = \'h3f; //\'?\'; 
+                            end
+            endcase 
+            to_char = c; 
+        end
+    endfunction
+
+
+    function integer address_increment;
+        input size; 
+        integer size;
+        input xainc; 
+        integer xainc;
+
+        integer c; 
+
+        begin
+            case (size)
+                0 :
+                            begin
+                                c = 1; 
+                            end
+                1 :
+                            begin
+                                c = 2; 
+                            end
+                2 :
+                            begin
+                                c = 4; 
+                            end
+                3 :
+                            begin
+                                c = xainc; 
+                            end
+                default :
+                            begin
+                                c = 0; 
+                            end
+            endcase 
+            address_increment = c; 
+        end
+    endfunction
+
+    function integer xfer_size;
+        input size; 
+        integer size;
+        input xsize; 
+        integer xsize;
+
+        reg[2:0] c; 
+
+        begin
+            case (size)
+                0 :
+                            begin
+                                c = 3\'b000; 
+                            end
+                1 :
+                            begin
+                                c = 3\'b001; 
+                            end
+                2 :
+                            begin
+                                c = 3\'b010; 
+                            end
+                3 :
+                            begin
+                                c = xsize; 
+                            end
+                default :
+                            begin
+                                c = 3\'bXXX; 
+                            end
+            endcase 
+            xfer_size = c; 
+        end
+    endfunction
+
+    function integer calculate;
+        input op; 
+        integer op;
+        input X; 
+        integer X;
+        input Y; 
+        integer Y;
+        input debug; 
+        integer debug;
+
+        integer Z; 
+        reg[31:0] XS; 
+        reg[31:0] YS; 
+        reg[31:0] ZS; 
+        integer YI; 
+        reg[63:0] ZZS; 
+        localparam[31:0] ZERO = 0; 
+        localparam[31:0] ONE  = 1; 
+
+        begin
+            
+            XS = X; 
+            YS = Y; 
+            YI = Y; 
+            ZS = {32{1\'b0}}; 
+            case (op)
+                OP_NONE :
+                            begin
+                                ZS = 0; 
+                            end
+                OP_ADD :
+                            begin
+                                ZS = XS + YS; 
+                            end
+                OP_SUB :
+                            begin
+                                ZS = XS - YS; 
+                            end
+                OP_MULT :
+                            begin
+                                ZZS = XS * YS; 
+                                ZS = ZZS[31:0]; 
+                            end
+                OP_DIV :
+                            begin
+                                ZS = XS / YS; 
+                            end
+                OP_AND :
+                            begin
+                                ZS = XS & YS; 
+                            end
+                OP_OR :
+                            begin
+                                ZS = XS | YS; 
+                            end
+                OP_XOR :
+                            begin
+                                ZS = XS ^ YS; 
+                            end
+                OP_CMP :
+                            begin
+                                ZS = XS ^ YS; 
+                            end
+                OP_SHR :
+                            begin
+                                if (YI == 0)
+                                begin
+                                    ZS = XS; 
+                                end
+                                else
+                                begin
+                                    ZS = XS >> YI;
+                                end 
+                            end
+                OP_SHL :
+                            begin
+                                if (YI == 0)
+                                begin
+                                    ZS = XS; 
+                                end
+                                else
+                                begin
+                                    ZS = XS << YI;
+                                end 
+                            end
+                OP_POW :
+                            begin
+                                ZZS = {ZERO, ONE}; 
+                                if (YI > 0)
+                                begin
+                                    begin : xhdl_1
+                                        integer i;
+                                        for(i = 1; i <= YI; i = i + 1)
+                                        begin
+                                            ZZS = ZZS[31:0] * XS; 
+                                        end
+                                    end 
+                                end 
+                                ZS = ZZS[31:0]; 
+                            end
+                OP_EQ :
+                            begin
+                                if (XS == YS)
+                                begin
+                                    ZS = ONE; 
+                                end 
+                            end
+                OP_NEQ :
+                            begin
+                                if (XS != YS)
+                                begin
+                                    ZS = ONE; 
+                                end 
+                            end
+                OP_GR :
+                            begin
+                                if (XS > YS)
+                                begin
+                                    ZS = ONE; 
+                                end 
+                            end
+                OP_LS :
+                            begin
+                                if (XS < YS)
+                                begin
+                                    ZS = ONE; 
+                                end 
+                            end
+                OP_GRE :
+                            begin
+                                if (XS >= YS)
+                                begin
+                                    ZS = ONE; 
+                                end 
+                            end
+                OP_LSE :
+                            begin
+                                if (XS <= YS)
+                                begin
+                                    ZS = ONE; 
+                                end 
+                            end
+                OP_MOD :
+                            begin
+                                ZS = XS % YS; 
+                            end
+                OP_SETB :
+                            begin
+                                if (Y <= 31)
+                                begin
+                                    ZS = XS; 
+                                    ZS[Y] = 1\'b1; 
+                                end
+                                else
+                                begin
+                                    $display(""Bit operation on bit >31 (FAILURE)""); 
+                                    $stop;
+                                end 
+                            end
+                OP_CLRB :
+                            begin
+                                if (Y <= 31)
+                                begin
+                                    ZS = XS; 
+                                    ZS[Y] = 1\'b0; 
+                                end
+                                else
+                                begin
+                                    $display(""Bit operation on bit >31 (FAILURE)""); 
+                                    $stop;
+                                end 
+                            end
+                OP_INVB :
+                            begin
+                                if (Y <= 31)
+                                begin
+                                    ZS = XS; 
+                                    ZS[Y] = ~ZS[Y]; 
+                                end
+                                else
+                                begin
+                                    $display(""Bit operation on bit >31 (FAILURE)""); 
+                                    $stop;
+                                end 
+                            end
+                OP_TSTB :
+                            begin
+                                if (Y <= 31)
+                                begin
+                                    ZS = 0; 
+                                    ZS[0] = XS[Y]; 
+                                end
+                                else
+                                begin
+                                    $display(""Bit operation on bit >31 (FAILURE)""); 
+                                    $stop;
+                                end 
+                            end
+                default :
+                            begin
+                                $display(""Illegal Maths Operator (FAILURE)""); 
+                                $stop;
+                            end
+            endcase 
+            Z = ZS; 
+            if (debug >= 4)
+            begin
+                $display(""Calculated %d = %d (%d) %d"", Z, X, op, Y); 
+            end 
+            calculate = Z; 
+        end
+    endfunction
+
+    function [31:0] clean;
+        input [31:0] X; 
+
+        reg[31:0] tmp; 
+
+        begin
+            tmp = X; 
+            tmp = 0; 
+            begin : xhdl_2
+                integer i;
+                for(i =0 ; i <= 31; i = i + 1)
+                begin
+                    if ((X[i]) == 1\'b1)
+                    begin
+                        tmp[i] = 1\'b1; 
+                    end 
+                end
+            end 
+            clean = tmp; 
+        end
+    endfunction
+
+/*
+    function [1:(256)*8] extract_string;
+        input len; 
+        integer len;
+        input vchar; 
+        reg [256*8:0] vchar;
+        reg [1:(256)*8] str; 
+        integer i,j,b,p; 
+
+        begin
+            nchars = vectors(cptr + 1) / 65536; 
+            nparas = vectors(cptr + 1) % 65536; 
+
+            for (i=0; i<256*8; i=i+1) str[i] = 0;
+            p=0;
+            for (i=0; i<(len+3)/4; i=i+1) 
+             begin
+               for (j=3;j>=0;j=j-1)
+                 begin
+                   for (b=1;b<=8;b=b+1)
+                     begin 
+                       str[p*8+b] = vchar[i*32+32-8*(4-j)+8-b];
+                     end
+                   p=p+1;
+                 end
+              end
+            extract_string = str; 
+        end
+    endfunction
+
+*/
+
+
+
+
+    function integer get_line;
+        input lineno; 
+        integer lineno;
+        input X; 
+        integer X;
+
+        integer ln; 
+        integer fn; 
+
+        begin
+            fn = lineno / X; 
+            ln = lineno - fn * X; 
+            get_line = ln; 
+        end
+    endfunction
+
+    function integer get_file;
+        input lineno; 
+        integer lineno;
+        input X; 
+        integer X;
+
+        integer ln; 
+        integer fn; 
+
+        begin
+            fn = lineno / X; 
+            ln = lineno - fn * X; 
+            get_file = fn; 
+        end
+    endfunction
+
+
+
+    function integer to_boolean;
+        input X; 
+        integer X;
+        integer z;
+        begin   
+          z=0;
+          if (X!=0) z=1;
+          to_boolean = z;
+        end
+    endfunction
+
+
+    function integer random;
+    input seed; 
+    integer seed;
+    reg [31:0] regx;  
+    reg [31:0] regy;  
+    reg d;
+    begin
+      regx = seed;
+      d = 1\'b1;
+      regy[0]  = d ^ regx[31];
+      regy[1]  = d ^ regx[31] ^ regx[0];
+      regy[2]  = d ^ regx[31] ^ regx[1];
+      regy[3]  = regx[2];
+      regy[4]  = d ^ regx[31] ^ regx[3];
+      regy[5]  = d ^ regx[31] ^ regx[4];
+      regy[6]  = regx[5];
+      regy[7]  = d ^ regx[31] ^ regx[6];
+      regy[8]  = d ^ regx[31] ^ regx[7];
+      regy[9]  = regx[8];
+      regy[10] = d ^ regx[31] ^ regx[9];
+      regy[11] = d ^ regx[31] ^ regx[10];
+      regy[12] = d ^ regx[31] ^ regx[11];
+      regy[13] = regx[12];
+      regy[14] = regx[13];
+      regy[15] = regx[14];
+      regy[16] = d ^ regx[31] ^ regx[15];
+      regy[17] = regx[16];
+      regy[18] = regx[17];
+      regy[19] = regx[18];
+      regy[20] = regx[19];
+      regy[21] = regx[20];
+      regy[22] = d ^ regx[31] ^ regx[21];
+      regy[23] = d ^ regx[31] ^ regx[22];
+      regy[24] = regx[23];
+      regy[25] = regx[24];
+      regy[26] = d ^ regx[31] ^ regx[25];
+      regy[27] = regx[26];
+      regy[28] = regx[27];
+      regy[29] = regx[28];
+      regy[30] = regx[29];
+      regy[31] = regx[30];
+      random = regy;
+    end
+
+endfunction
+
+
+
+function integer mask_randomN;
+    input seed; 
+    integer seed;
+    input size; 
+    integer size;
+
+    integer xrand; 
+    integer i;
+
+    reg[31:0] regx; 
+
+    begin
+        regx =seed; 
+        for(i=31;i>=size;i=i-1) regx[i] = 0; 
+        xrand = regx; 
+        mask_randomN = xrand; 
+    end
+endfunction
+
+
+
+    function integer mask_randomS;
+        input seed; 
+        integer seed;
+        input size; 
+        integer size;
+
+        integer xrand; 
+        reg[31:0] regx; 
+        integer sn; 
+        integer i;
+        begin
+            case (size)
+                1 :
+                            begin
+                                sn = 0; 
+                            end
+                2 :
+                            begin
+                                sn = 1; 
+                            end
+                4 :
+                            begin
+                                sn = 2; 
+                            end
+                8 :
+                            begin
+                                sn = 3; 
+                            end
+                16 :
+                            begin
+                                sn = 4; 
+                            end
+                32 :
+                            begin
+                                sn = 5; 
+                            end
+                64 :
+                            begin
+                                sn = 6; 
+                            end
+                128 :
+                            begin
+                                sn = 7; 
+                            end
+                256 :
+                            begin
+                                sn = 8; 
+                            end
+                512 :
+                            begin
+                                sn = 9; 
+                            end
+                1024 :
+                            begin
+                                sn = 10; 
+                            end
+                2048 :
+                            begin
+                                sn = 11; 
+                            end
+                4096 :
+                            begin
+                                sn = 12; 
+                            end
+                8192 :
+                            begin
+                                sn = 13; 
+                            end
+                16384 :
+                            begin
+                                sn = 14; 
+                            end
+                32768 :
+                            begin
+                                sn = 15; 
+                            end
+                65536 :
+                            begin
+                                sn = 16; 
+                            end
+                131072     : sn= 17;
+                262144     : sn= 18;
+                524288     : sn= 19;
+                1048576    : sn= 20;
+                2097152    : sn= 21;
+                4194304    : sn= 22;
+                8388608    : sn= 23;
+                16777216   : sn= 24;
+                33554432   : sn= 25;
+                67108864   : sn= 26;
+                134217728  : sn= 27;
+                268435456  : sn= 28;
+                536870912  : sn= 29;
+                1073741824 : sn= 30;
+                default :
+                            begin
+                                $display(""Random function error (FAILURE)""); 
+                                $finish;
+                            end
+            endcase 
+            regx = to_slv32(seed); 
+            if (sn < 31)
+            begin
+                for(i=31;i>=sn;i=i-1) regx[i] = 0; 
+            end 
+            xrand = to_int_signed(regx); 
+            mask_randomS = xrand; 
+        end
+    endfunction
+
+
+
+
+
+    function bound1k;
+        input bmode; 
+        integer bmode;
+        input addr; 
+\t\tinteger addr;
+
+        reg[31:0] address; 
+        reg boundary; 
+
+        begin
+        \taddress = addr;
+            boundary = 0; 
+            case (bmode)
+                0 :
+                            begin
+                                if (address[9:0] == 10\'b0000000000)
+                                begin
+                                    boundary = 1; 
+                                end 
+                            end
+                1 :
+                            begin
+                                boundary = 1; 
+                            end
+                2 :
+                            begin
+                                // return FALSE
+                            end
+                default :
+                            begin
+                                $display(""Illegal Burst Boundary Set (FAILURE)""); 
+                                $finish;
+                            end
+            endcase 
+            bound1k = boundary; 
+        end
+    endfunction
+"
+"//--------------------------------------------------------------------
+// Created by Actel SmartDesign Tue Apr 29 04:30:25 2014
+// Parameters for CoreAPB3
+//--------------------------------------------------------------------
+
+
+parameter APB_DWIDTH = 32;
+parameter APBSLOT0ENABLE = 1;
+parameter APBSLOT1ENABLE = 0;
+parameter APBSLOT2ENABLE = 0;
+parameter APBSLOT3ENABLE = 0;
+parameter APBSLOT4ENABLE = 0;
+parameter APBSLOT5ENABLE = 0;
+parameter APBSLOT6ENABLE = 0;
+parameter APBSLOT7ENABLE = 0;
+parameter APBSLOT8ENABLE = 0;
+parameter APBSLOT9ENABLE = 0;
+parameter APBSLOT10ENABLE = 0;
+parameter APBSLOT11ENABLE = 0;
+parameter APBSLOT12ENABLE = 0;
+parameter APBSLOT13ENABLE = 0;
+parameter APBSLOT14ENABLE = 0;
+parameter APBSLOT15ENABLE = 0;
+parameter HDL_license = ""O"";
+parameter IADDR_OPTION = 0;
+parameter MADDR_BITS = 12;
+parameter SC_0 = 0;
+parameter SC_1 = 0;
+parameter SC_2 = 0;
+parameter SC_3 = 0;
+parameter SC_4 = 0;
+parameter SC_5 = 0;
+parameter SC_6 = 0;
+parameter SC_7 = 0;
+parameter SC_8 = 0;
+parameter SC_9 = 0;
+parameter SC_10 = 0;
+parameter SC_11 = 0;
+parameter SC_12 = 0;
+parameter SC_13 = 0;
+parameter SC_14 = 0;
+parameter SC_15 = 0;
+parameter testbench = ""User"";
+parameter UPR_NIBBLE_POSN = 6;
+"
+"`timescale 1 ns / 100 ps
+// ********************************************************************/ 
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+//  
+// Description: AMBA BFMs
+//              AHB to APB Bridge  
+//
+// Revision Information:
+// Date     Description
+// 01Sep07  Initial Release 
+// 14Sep07  Updated for 1.2 functionality
+// 25Sep07  Updated for 1.3 functionality
+// 09Nov07  Updated for 1.4 functionality
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+//
+// Resolved SARs
+// SAR      Date     Who  Description
+//
+//
+// Notes: 
+// 28Nov07 IPB Updated to increase throughput
+//
+// *********************************************************************/ 
+
+module BFM_AHB2APB (HCLK, HRESETN, HSEL, HWRITE, HADDR, HWDATA, HRDATA, HREADYIN, HREADYOUT, HTRANS, HSIZE, HBURST, HMASTLOCK, HPROT, HRESP, PSEL, PADDR, PWRITE, PENABLE, PWDATA, PRDATA, PREADY, PSLVERR);
+
+    parameter  TPD  = 1;
+
+
+    input HCLK; 
+    input HRESETN; 
+    input HSEL; 
+    input HWRITE; 
+    input[31:0] HADDR; 
+    input[31:0] HWDATA; 
+    output[31:0] HRDATA; 
+    wire[31:0]  HRDATA;
+    input HREADYIN; 
+    output HREADYOUT; 
+    wire  HREADYOUT;
+    input[1:0] HTRANS; 
+    input[2:0] HSIZE; 
+    input[2:0] HBURST; 
+    input HMASTLOCK; 
+    input[3:0] HPROT; 
+    output HRESP; 
+    wire  HRESP;
+    output[15:0] PSEL; 
+    wire[15:0]  PSEL;
+    output[31:0] PADDR; 
+    wire[31:0]  PADDR;
+    output PWRITE; 
+    wire  PWRITE;
+    output PENABLE; 
+    wire  PENABLE;
+    output[31:0] PWDATA; 
+    wire[31:0]  PWDATA;
+    input[31:0] PRDATA; 
+    input PREADY; 
+    input PSLVERR; 
+
+    parameter[1:0] T0 = 0; 
+    parameter[1:0] T2 = 1; 
+    parameter[1:0] T345 = 2; 
+    parameter[1:0] TR0 = 3; 
+    reg[1:0] STATE; 
+    reg HREADYOUT_P0; 
+    reg HRESP_P0; 
+    reg[15:0] PSEL_P0; 
+    reg[31:0] PADDR_P0; 
+    reg PWRITE_P0; 
+    reg PENABLE_P0; 
+    reg[31:0] PWDATA_P0; 
+    wire[31:0] PWDATA_MUX; 
+    reg DMUX; 
+    reg PSELEN; 
+
+    always @(posedge HCLK or negedge HRESETN)
+    begin
+        if (HRESETN == 1'b0)
+        begin
+            STATE  <= T0 ; 
+            HREADYOUT_P0 <= 1'b1 ; 
+            PADDR_P0   <= {32{1'b0}} ; 
+            PWDATA_P0  <= {32{1'b0}} ; 
+            PWRITE_P0  <= 1'b0 ; 
+            PENABLE_P0 <= 1'b0 ; 
+            HRESP_P0   <= 1'b0 ; 
+            DMUX       <= 1'b0 ; 
+            PSELEN     <= 1'b0 ; 
+        end
+        else
+        begin
+            HRESP_P0 <= 1'b0 ; 
+            HREADYOUT_P0 <= 1'b0 ; 
+            DMUX <= 1'b0 ; 
+            case (STATE)
+                T0 :
+                            begin
+                                if (HSEL == 1'b1 & HREADYIN == 1'b1 & (HTRANS[1]) == 1'b1)
+                                begin
+                                    STATE <= T2 ; 
+                                    PADDR_P0 <= HADDR ; 
+                                    PWRITE_P0 <= HWRITE ; 
+                                    PWDATA_P0 <= HWDATA ; 
+                                    PENABLE_P0 <= 1'b0 ; 
+                                    DMUX <= HWRITE ; 
+                                    PSELEN <= 1'b1 ; 
+                                end
+                                else
+                                begin
+                                    HREADYOUT_P0 <= 1'b1 ; 
+                                end 
+                            end
+                T2 :
+                            begin
+                                PENABLE_P0 <= 1'b1 ; 
+                                STATE <= T345 ; 
+                            end
+                T345 :
+                            begin
+                                if (PREADY == 1'b1)
+                                begin
+                                    PENABLE_P0 <= 1'b0 ; 
+                                    PSELEN <= 1'b0 ; 
+                                    if (PSLVERR == 1'b0)
+                                    begin
+                                        STATE <= T0 ; 
+                                        if (HSEL == 1'b1 & HREADYIN == 1'b1 & (HTRANS[1]) == 1'b1)
+                                        begin
+                                            STATE <= T2 ; 
+                                            PADDR_P0 <= HADDR ; 
+                                            PWRITE_P0 <= HWRITE ; 
+                                            DMUX <= HWRITE ; 
+                                            PSELEN <= 1'b1 ; 
+                                        end 
+                                    end
+                                    else
+                                    begin
+                                        HRESP_P0 <= 1'b1 ; 
+                                        STATE <= TR0 ; 
+                                    end 
+                                end 
+                            end
+                TR0 :
+                            begin
+                                HRESP_P0 <= 1'b1 ; 
+                                HREADYOUT_P0 <= 1'b1 ; 
+                                STATE <= T0 ; 
+                            end
+            endcase 
+            if (DMUX == 1'b1)
+            begin
+                PWDATA_P0 <= HWDATA ; 
+            end 
+        end 
+    end 
+
+    always @(PADDR_P0 or PSELEN)
+    begin
+        PSEL_P0 <= {16{1'b0}} ; 
+        if (PSELEN == 1'b1)
+        begin
+            begin : xhdl_3
+                integer i;
+                for(i = 0; i <= 15; i = i + 1)
+                begin
+                    PSEL_P0[i] <= (PADDR_P0[27:24] == i) ; 
+                end
+            end 
+        end 
+    end 
+    \t
+    assign      PWDATA_MUX = (DMUX == 1'b1) ? HWDATA : PWDATA_P0 ;
+    assign #TPD HRDATA     = PRDATA ;
+    assign #TPD HREADYOUT  = HREADYOUT_P0 | (PREADY & PSELEN & PENABLE_P0 & ~PSLVERR) ;
+    assign #TPD HRESP      = HRESP_P0 ;
+    assign #TPD PSEL       = PSEL_P0 ;
+    assign #TPD PADDR      = PADDR_P0 ;
+    assign #TPD PWRITE     = PWRITE_P0 ;
+    assign #TPD PENABLE    = PENABLE_P0 ;
+    assign #TPD PWDATA     = PWDATA_MUX ;
+
+endmodule
+ "
+"`timescale 1ns/1ns
+
+module testbench();
+
+localparam APB_DWIDTH = 32;
+
+reg  SYSCLK;      
+reg  SYSRSTN;     
+wire PCLK;        
+wire PRESETN;     
+wire [31:0] PADDR;      
+wire PENABLE;     
+wire PWRITE;      
+wire [APB_DWIDTH-1:0] PWDATA;     
+wire [APB_DWIDTH-1:0] PRDATA;     
+wire [APB_DWIDTH-1:0] PRDATA_0;     
+wire [APB_DWIDTH-1:0] PRDATA_1;     
+wire [15:0] PSEL;
+         
+wire [255:0] INTERRUPT;   
+wire [31:0]  GP_OUT;      
+wire [31:0]  GP_IN;       
+wire FINISHED;  
+wire FAILED;
+
+wire Logic0 = 1\'b0;
+wire Logic1 = 1\'b1;    
+
+
+// ********************************************************************************
+// Clocks and Reset
+
+
+initial
+ begin
+  SYSRSTN <= 1\'b0;
+  #100;
+  SYSRSTN <= 1\'b1;
+ end
+
+// Clock is 100MHz
+always
+ begin
+   SYSCLK <= 1\'b0;
+   #5;
+   SYSCLK <= 1\'b1;
+   #5;
+ end
+ 
+   
+// ********************************************************************************
+// APB Master  
+
+BFM_APB  #(.VECTFILE     (""user_tb.vec"") )
+     UBFM (.SYSCLK       (SYSCLK), 
+           .SYSRSTN      (SYSRSTN), 
+           .PCLK         (PCLK), 
+           .PRESETN      (PRESETN), 
+           .PADDR        (PADDR), 
+           .PENABLE      (PENABLE), 
+           .PWRITE       (PWRITE), 
+           .PWDATA       (PWDATA), 
+           .PRDATA       (PRDATA), 
+           .PREADY       (Logic1), 
+           .PSLVERR      (Logic0), 
+           .PSEL         (PSEL), 
+           .INTERRUPT    (INTERRUPT),
+           .GP_OUT       (GP_OUT), 
+           .GP_IN        (GP_IN), 
+           .EXT_WR       (), 
+           .EXT_RD       (), 
+           .EXT_ADDR     (), 
+           .EXT_DATA     (), 
+           .EXT_WAIT     (Logic0), 
+           .CON_ADDR     (), 
+           .CON_DATA     (), 
+           .CON_RD       (Logic0), 
+           .CON_WR       (Logic0), 
+           .CON_BUSY     (), 
+           .FINISHED     (FINISHED), 
+           .FAILED       (FAILED)
+        );                       
+                   
+assign PRDATA = ( PSEL[1] ? PRDATA_1 : PRDATA_0) ;                   
+                         
+                         
+/* #############################################################################
+                         
+SPIINT      Output interrupt 
+SPISDO      Output serial data out (generated by SPI as master)
+SPISS[7:0]  Output slave select (generated by SPI as master)
+SPISCLKO    Output shift clock out (generated by SPI as master)
+SPISDI      Input  shift data in (master or slave)
+SPIRXAVAIL  Output request for data to be read - rx data available
+SPITXRFM    Output indicates transmit done - ready for more
+SPISSI      Input  slave select (when SPI in slave mode)
+SPIOEN      Output output enable (when de-asserted output pad for SPISDO tri-stated). This is active when the SPI is writing output data and deactivated when there is not data to write. This signal is active high.
+SPIMode     Output mode:  (when 1,  SPI is master, when 0, SPI is slave)
+
+*/
+
+// ********************************************************************************
+// SPI Core - Master    
+
+wire [7:0] M_SPISS;
+
+CORESPI # (
+  .APB_DWIDTH        (APB_DWIDTH),
+  .CFG_FRAME_SIZE    (4),
+  .FIFO_DEPTH        (4),
+  .CFG_CLK           (2),
+  .CFG_SPO           (1),
+  .CFG_SPH           (1),
+  .CFG_SPS           (0),
+  .CFG_MODE          (0)
+)USPIM ( //.TESTMODE   (1\'b0),
+                  .PCLK       (PCLK),   
+                  .PRESETN    (PRESETN),
+                  .PADDR      (PADDR[6:0]),  
+                  .PSEL       (PSEL[0]),   
+                  .PENABLE    (PENABLE),
+                  .PWRITE     (PWRITE), 
+                  .PWDATA     (PWDATA), 
+                  .PRDATA    (PRDATA_0),
+
+                  .SPISSI     (M_SPISSI), 
+                  .SPISDI     (M_SPISDI), 
+                  .SPICLKI    (M_SPICLKI),
+                  .SPISS      (M_SPISS),  
+                  .SPISCLKO   (M_SPISCLKO),  
+                  .SPIOEN     (M_SPIOEN),    
+                  .SPISDO     (M_SPISDO),    
+
+                  .SPIINT     (GP_IN[0]), 
+                  .SPIRXAVAIL (GP_IN[1]),
+                  .SPITXRFM   (GP_IN[2]),  
+                  .SPIMODE    (GP_IN[3]),
+                  .PREADY     (),
+                  .PSLVERR    ()
+
+                  );
+
+// ********************************************************************************
+// SPI Core - Master    
+
+wire [7:0] S_SPISS;
+
+
+CORESPI # (
+  .APB_DWIDTH        (APB_DWIDTH),
+  .CFG_FRAME_SIZE    (4),
+  .FIFO_DEPTH        (4),
+  .CFG_CLK           (2),
+  .CFG_SPO           (1),
+  .CFG_SPH           (1),
+  .CFG_SPS           (0),
+  .CFG_MODE          (0)
+)  USPIS ( //.TESTMODE   (1\'b0),
+                  .PCLK       (PCLK),   
+                  .PRESETN    (PRESETN),
+                  .PADDR      (PADDR[6:0]),  
+                  .PSEL       (PSEL[1]),   
+                  .PENABLE    (PENABLE),
+                  .PWRITE     (PWRITE), 
+                  .PWDATA     (PWDATA), 
+                  .PRDATA    (PRDATA_1),
+
+                  .SPISSI     (S_SPISSI), 
+                  .SPISDI     (S_SPISDI), 
+                  .SPICLKI    (S_SPICLKI),
+                  .SPISS      (S_SPISS),  
+                  .SPISCLKO   (S_SPISCLKO),  
+                  .SPIOEN     (S_SPIOEN),    
+                  .SPISDO     (S_SPISDO),    
+
+                  .SPIINT     (GP_IN[8]), 
+                  .SPIRXAVAIL (GP_IN[9]),
+                  .SPITXRFM   (GP_IN[10]),  
+                  .SPIMODE    (GP_IN[11]),
+                  .PREADY     (),
+                  .PSLVERR    ()
+
+                  );
+
+
+
+// *************************************************************************************
+// SPI Connectivity
+
+reg [31:0] shiftreg = 32\'b000;
+
+always @(posedge M_SPISCLKO)
+begin
+\tshiftreg <= { shiftreg[30:0] , (M_SPISDO & M_SPIOEN)}; 
+end
+
+reg nscdata;
+always @(negedge M_SPISCLKO)
+begin
+\tnscdata <= shiftreg[8]; 
+end
+\t
+
+reg mux;
+always @(*)
+ begin
+   case (GP_OUT[10:8])
+     3\'b000 :  mux = M_SPISDO & M_SPIOEN;
+     3\'b001 :  mux = M_SPISDO & M_SPIOEN;
+     3\'b010 :  mux = nscdata;\t\t\t  // 9 clock delay
+     3\'b100 :  mux = S_SPISDO & S_SPIOEN;
+     3\'b101 :  mux = S_SPISDO & S_SPIOEN;
+     3\'b110 :  mux = S_SPISDO & S_SPIOEN;
+\tendcase
+ end
+ \t
+assign M_SPISDI  = mux;  
+assign S_SPICLKI = M_SPISCLKO;
+assign S_SPISSI  = M_SPISS[0];
+assign S_SPISDI  = M_SPISDO & M_SPIOEN;
+
+
+// For Waveform trace
+wire SPICLK   =  M_SPISCLKO;
+wire SPISEL   =  M_SPISS[0];
+wire SPIDATAM =  M_SPISDO & M_SPIOEN;
+wire SPIDATAS =  M_SPISDI;
+
+
+// *************************************************************************************
+// Simple Spy Capture Model
+
+// AS: removed
+
+//reg [7:0] capture = 8\'b00;
+//reg [7:0] capnext = 8\'b00;
+//integer bit = 0;
+
+/*
+
+always @(posedge SPICLK)
+begin
+  if (SPISEL==1)
+  \t begin
+  \t   capture <= 8\'b00;
+      bit = 0;
+    end 
+  else
+    begin
+      capnext = { capture[6:0], M_SPISDO };
+      capture <= capnext;
+      bit = bit +1;
+      if (bit==8)
+       begin
+       \t$display(""Captured %02d %02x"",bit,capnext);
+  \t      capture <= 8\'b00;
+         bit = 0;
+ \t\t end
+ \t end\t \t
+end
+    \t  
+*/
+
+// *************************************************************************************
+// PCLK Width Check
+
+// AS: removed, not needed for USER TB
+
+endmodule
+"
+"// ********************************************************************/ 
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+//  
+// Description: AMBA BFMs
+//              AHB Lite BFM     
+//
+// Revision Information:
+// Date     Description
+// 01Sep07  Initial Release 
+// 14Sep07  Updated for 1.2 functionality
+// 25Sep07  Updated for 1.3 functionality
+// 09Nov07  Updated for 1.4 functionality
+// 18Dec08  Updated for 1.5 functionality
+// 18Feb08  Updated for 1.6 functionality
+// 08May08  2.0 for Soft IP Usage
+// 08May08  2.0 for Soft IP Usage
+// 04Feb09  2.1 Created fileset for G4 with CON bus back
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+//
+// Resolved SARs
+// SAR      Date     Who  Description
+//
+//
+// Notes: 
+//
+// Release 2.0
+//   Soft IP Release of Internal Hard IP Models
+// Release 2.1
+//   Added else and case support
+//
+// Requested Enhancements
+//   Ability to do back-to-back single cycle checking of the IO_IN inputs 
+// 
+//
+//
+// *********************************************************************/ 
+
+
+`timescale 1 ns / 100 ps
+
+
+module BFM_MAIN (SYSCLK, SYSRSTN, PCLK, HCLK, HRESETN, 
+                 HADDR, HBURST, HMASTLOCK, HPROT, HSIZE, HTRANS, HWRITE, HWDATA, HRDATA, HREADY, HRESP, HSEL, 
+                 INTERRUPT, GP_OUT, GP_IN, EXT_WR, EXT_RD, EXT_ADDR, EXT_DATA, EXT_WAIT, 
+                 CON_ADDR, CON_DATA, CON_RD, CON_WR, CON_BUSY, 
+                 INSTR_OUT, INSTR_IN, FINISHED, FAILED);
+
+    parameter OPMODE    = 0;
+    parameter VECTFILE  = ""test.vec"";
+    parameter MAX_INSTRUCTIONS  = 16384;
+    parameter MAX_STACK   = 1024;
+    parameter MAX_MEMTEST = 65536;
+    parameter TPD        = 1;
+    parameter DEBUGLEVEL = -1;
+    parameter CON_SPULSE = 0;
+    parameter ARGVALUE0  = 0;
+    parameter ARGVALUE1  = 0;
+    parameter ARGVALUE2  = 0;
+    parameter ARGVALUE3  = 0;
+    parameter ARGVALUE4  = 0;
+    parameter ARGVALUE5  = 0;
+    parameter ARGVALUE6  = 0;
+    parameter ARGVALUE7  = 0;
+    parameter ARGVALUE8  = 0;
+    parameter ARGVALUE9  = 0;
+    parameter ARGVALUE10 = 0;
+    parameter ARGVALUE11 = 0;
+    parameter ARGVALUE12 = 0;
+    parameter ARGVALUE13 = 0;
+    parameter ARGVALUE14 = 0;
+    parameter ARGVALUE15 = 0;
+    parameter ARGVALUE16 = 0;
+    parameter ARGVALUE17 = 0;
+    parameter ARGVALUE18 = 0;
+    parameter ARGVALUE19 = 0;
+    parameter ARGVALUE20 = 0;
+    parameter ARGVALUE21 = 0;
+    parameter ARGVALUE22 = 0;
+    parameter ARGVALUE23 = 0;
+    parameter ARGVALUE24 = 0;
+    parameter ARGVALUE25 = 0;
+    parameter ARGVALUE26 = 0;
+    parameter ARGVALUE27 = 0;
+    parameter ARGVALUE28 = 0;
+    parameter ARGVALUE29 = 0;
+    parameter ARGVALUE30 = 0;
+    parameter ARGVALUE31 = 0;
+    parameter ARGVALUE32 = 0;
+    parameter ARGVALUE33 = 0;
+    parameter ARGVALUE34 = 0;
+    parameter ARGVALUE35 = 0;
+    parameter ARGVALUE36 = 0;
+    parameter ARGVALUE37 = 0;
+    parameter ARGVALUE38 = 0;
+    parameter ARGVALUE39 = 0;
+    parameter ARGVALUE40 = 0;
+    parameter ARGVALUE41 = 0;
+    parameter ARGVALUE42 = 0;
+    parameter ARGVALUE43 = 0;
+    parameter ARGVALUE44 = 0;
+    parameter ARGVALUE45 = 0;
+    parameter ARGVALUE46 = 0;
+    parameter ARGVALUE47 = 0;
+    parameter ARGVALUE48 = 0;
+    parameter ARGVALUE49 = 0;
+    parameter ARGVALUE50 = 0;
+    parameter ARGVALUE51 = 0;
+    parameter ARGVALUE52 = 0;
+    parameter ARGVALUE53 = 0;
+    parameter ARGVALUE54 = 0;
+    parameter ARGVALUE55 = 0;
+    parameter ARGVALUE56 = 0;
+    parameter ARGVALUE57 = 0;
+    parameter ARGVALUE58 = 0;
+    parameter ARGVALUE59 = 0;
+    parameter ARGVALUE60 = 0;
+    parameter ARGVALUE61 = 0;
+    parameter ARGVALUE62 = 0;
+    parameter ARGVALUE63 = 0;
+    parameter ARGVALUE64 = 0;
+    parameter ARGVALUE65 = 0;
+    parameter ARGVALUE66 = 0;
+    parameter ARGVALUE67 = 0;
+    parameter ARGVALUE68 = 0;
+    parameter ARGVALUE69 = 0;
+    parameter ARGVALUE70 = 0;
+    parameter ARGVALUE71 = 0;
+    parameter ARGVALUE72 = 0;
+    parameter ARGVALUE73 = 0;
+    parameter ARGVALUE74 = 0;
+    parameter ARGVALUE75 = 0;
+    parameter ARGVALUE76 = 0;
+    parameter ARGVALUE77 = 0;
+    parameter ARGVALUE78 = 0;
+    parameter ARGVALUE79 = 0;
+    parameter ARGVALUE80 = 0;
+    parameter ARGVALUE81 = 0;
+    parameter ARGVALUE82 = 0;
+    parameter ARGVALUE83 = 0;
+    parameter ARGVALUE84 = 0;
+    parameter ARGVALUE85 = 0;
+    parameter ARGVALUE86 = 0;
+    parameter ARGVALUE87 = 0;
+    parameter ARGVALUE88 = 0;
+    parameter ARGVALUE89 = 0;
+    parameter ARGVALUE90 = 0;
+    parameter ARGVALUE91 = 0;
+    parameter ARGVALUE92 = 0;
+    parameter ARGVALUE93 = 0;
+    parameter ARGVALUE94 = 0;
+    parameter ARGVALUE95 = 0;
+    parameter ARGVALUE96 = 0;
+    parameter ARGVALUE97 = 0;
+    parameter ARGVALUE98 = 0;
+    parameter ARGVALUE99 = 0;
+     
+
+    localparam [1:(3)*8] BFM_VERSION = ""2.1""; 
+    localparam [1:(7)*8] BFM_DATE    = ""04FEB09""; 
+
+    input SYSCLK; 
+    input SYSRSTN; 
+    output PCLK; 
+    wire PCLK;
+    output HCLK; 
+    wire HCLK;
+    output HRESETN; 
+    wire #TPD HRESETN;
+   
+    output[31:0] HADDR; 
+    wire[31:0] #TPD HADDR;
+   
+    output[2:0] HBURST; 
+    wire[2:0] #TPD HBURST;
+    output HMASTLOCK; 
+    wire #TPD HMASTLOCK;
+    output[3:0] HPROT; 
+    wire[3:0] #TPD HPROT;
+    output[2:0] HSIZE; 
+    wire[2:0] #TPD HSIZE;
+    output[1:0] HTRANS; 
+    wire[1:0] #TPD HTRANS;
+    output HWRITE; 
+    wire #TPD HWRITE;
+    output[31:0] HWDATA; 
+    wire[31:0] #TPD HWDATA;
+    input[31:0] HRDATA; 
+    input HREADY; 
+    input HRESP; 
+    output[15:0] HSEL; 
+    wire[15:0] #TPD HSEL;
+    input[255:0] INTERRUPT; 
+    output[31:0] GP_OUT; 
+    wire[31:0] #TPD GP_OUT;
+    input[31:0] GP_IN; 
+    output EXT_WR; 
+    wire #TPD EXT_WR;
+    output EXT_RD; 
+    wire #TPD EXT_RD;
+    output[31:0] EXT_ADDR; 
+    wire[31:0] #TPD EXT_ADDR;
+    inout[31:0] EXT_DATA; 
+    wire[31:0] #TPD EXT_DATA;
+    input EXT_WAIT; 
+   
+    input[15:0] CON_ADDR; 
+    inout[31:0] CON_DATA; 
+    wire[31:0] #TPD CON_DATA;
+    wire[31:0] CON_DATA_xhdl1;
+    input CON_RD; 
+    input CON_WR; 
+    output CON_BUSY; 
+    reg CON_BUSY;
+   
+   
+    output[31:0] INSTR_OUT; 
+    reg[31:0] INSTR_OUT;
+    input[31:0] INSTR_IN; 
+    output FINISHED; 
+    wire #TPD FINISHED;
+    output FAILED; 
+    wire #TPD FAILED;
+
+    localparam NUL = 0;
+
+    wire SCLK; 
+    integer command [0:255]; 
+    integer vectors [0:MAX_INSTRUCTIONS - 1]; 
+    reg HRESETN_P0; 
+    reg[2:0] HBURST_P0; 
+    reg HMASTLOCK_P0; 
+    reg[3:0] HPROT_P0; 
+    reg[1:0] HTRANS_P0; 
+    reg HWRITE_P0; 
+    wire[31:0] HWDATA_P0; 
+    reg[31:0] HADDR_P0; 
+    reg[31:0] HADDR_P1; 
+    reg[2:0] HSIZE_P0; 
+    reg[2:0] HSIZE_P1; 
+    reg[15:0] HSEL_P0; 
+    reg WRITE_P1; 
+    reg WRITE_P0; 
+    reg READ_P0; 
+    reg READ_P1; 
+    reg POLL_P0; 
+    reg POLL_P1; 
+    reg RDCHK_P0; 
+    reg RDCHK_P1; 
+    reg[31:0] RDATA_P0; 
+    reg[31:0] MDATA_P0; 
+    reg[31:0] WDATA_P0; 
+    reg[31:0] RDATA_P1; 
+    reg[31:0] MDATA_P1; 
+    reg[31:0] WDATA_P1; 
+    reg[31:0] EIO_RDATA_P0; 
+    reg[31:0] EIO_MDATA_P0; 
+    integer EIO_LINENO_P0; 
+    reg EIO_RDCHK_P0; 
+    reg EIO_RDCHK_P1; 
+    reg[31:0] EIO_RDATA_P1; 
+    reg[31:0] EIO_MDATA_P1; 
+    integer EIO_LINENO_P1; 
+    reg EXTWR_P0; 
+    reg EXTRD_P0; 
+    reg EXTRD_P1; 
+    reg GPIORD_P0; 
+    reg GPIOWR_P0; 
+    wire[31:0] EXT_DIN; 
+    reg[31:0] EXT_DOUT; 
+    reg[31:0] EXTADDR_P0; 
+    reg[31:0] EXTADDR_P1; 
+    wire[31:0] CON_DIN; 
+    reg[31:0] CON_DOUT; 
+    reg CON_RDP1; 
+    reg CON_WRP1; 
+    integer LINENO_P0; 
+    integer LINENO_P1; 
+    reg HCLK_STOP = 1\'b0; 
+    reg[31:0] GPOUT_P0; 
+    reg[1:(80)*8] FILENAME; 
+    reg FINISHED_P0; 
+    reg FAILED_P0; 
+    reg DRIVEX_CLK; 
+    reg DRIVEX_RST; 
+    reg DRIVEX_ADD; 
+    reg DRIVEX_DAT; 
+
+
+    parameter[31:0]   ZEROLV = {32{1\'b0}}; 
+    parameter[255:0] ZERO256 = {256{1\'b0}}; 
+
+    parameter TPDns = TPD * 1; 
+
+    assign SCLK = SYSCLK ;
+
+    integer stack[0:MAX_STACK - 1]; 
+    integer return_value; 
+    integer stkptr; 
+    integer cmd_lineno; 
+    integer DEBUG; 
+    integer logopen;
+
+    
+    `include ""bfm_package.v""
+
+    function integer len_string;
+        input len; 
+        integer len;
+
+        integer nparas; 
+        integer nchars; 
+        integer n; 
+
+        begin
+            nchars = len / 65536; 
+            nparas = len % 65536; 
+            n = 2 + nparas + 1 + ((nchars - 1) / 4); 
+            len_string = n; 
+        end
+    endfunction
+
+    function [1:(256)*8] extract_string;
+        input cptr; 
+        integer cptr;
+
+        reg[1:(256)*8] pstr; 
+        reg[1:(256)*8] str; 
+        integer i; 
+        integer p; 
+        integer j; 
+        reg[31:0] tmp_un; 
+        integer nparas; 
+        integer nchars; 
+        integer len; 
+\t\tinteger b;
+
+        begin
+            nchars = vectors[cptr + 1] / 65536; 
+            nparas = vectors[cptr + 1] % 65536; 
+            len = 2 + nparas + 1 + ((nchars - 1) / 4); 
+            for(p = 1; p <= 256*8; p = p + 1)  pstr[p]=0;
+
+            i = cptr + 2 + nparas; 
+            j = 3; 
+            begin : xhdl_3
+                integer p;
+                for(p = 1; p <= nchars; p = p + 1)
+                begin
+                    tmp_un = vectors[i]; 
+                    for (b=1;b<=8;b=b+1) 
+                       pstr[(p-1)*8+b] = tmp_un[j * 8 + 8-b]; 
+                    if (j == 0)
+                    begin
+                        i = i + 1; 
+                        j = 4; 
+                    end 
+                    j = j - 1; 
+                end
+            end 
+            case (nparas)
+                0 :
+                            begin
+                                $sformat(str, pstr); 
+                            end
+                1 :
+                            begin
+                                $sformat(str, pstr, command[2]); 
+                            end
+                2 :
+                            begin
+                                $sformat(str, pstr, command[2], command[3]); 
+                            end
+                3 :
+                            begin
+                                $sformat(str, pstr, command[2], command[3], command[4]); 
+                            end
+                4 :
+                            begin
+                                $sformat(str, pstr, command[2], command[3], command[4], command[5]); 
+                            end
+                5 :
+                            begin
+                                $sformat(str, pstr, command[2], command[3], command[4], command[5], command[6]); 
+                            end
+                6 :
+                            begin
+                                $sformat(str, pstr, command[2], command[3], command[4], command[5], command[6], command[7]); 
+                            end
+                7 :
+                            begin
+                                $sformat(str, pstr, command[2], command[3], command[4], command[5], command[6], command[7], command[8]); 
+                            end
+                default :
+                            begin
+                                $display(""String Error (FAILURE)""); 
+                            end
+            endcase 
+
+            extract_string = str; 
+        end
+    endfunction
+
+
+\tinteger lastrandom;
+    integer setrandom;
+    integer ERRORS; 
+    integer reset_pulse; 
+    parameter[2:0] idle = 0; 
+    parameter[2:0] init = 1; 
+    parameter[2:0] active = 2; 
+    parameter[2:0] done = 3; 
+    parameter[2:0] fill = 4; 
+    parameter[2:0] scan = 5; 
+    integer mt_addr; 
+    integer mt_size; 
+    integer mt_align; 
+    integer mt_cycles; 
+    integer mt_seed; 
+    reg[2:0] mt_state; 
+    integer mt_image[0:MAX_MEMTEST-1]; 
+    integer mt_ad; 
+    integer mt_op; 
+    integer mt_base; 
+    integer mt_base2; 
+    reg mt_readok; 
+    integer mt_reads; 
+    integer mt_writes; 
+    integer mt_nops;
+    integer var_ltimer; 
+    integer var_licycles; 
+    integer instructions_timer; 
+    reg mt_dual; 
+    reg mt_fill; 
+    reg mt_scan; 
+    reg mt_restart; 
+    integer mt_fillad; 
+
+    function automatic integer get_para_value;
+        input isvar;
+        input x; 
+        integer x;
+
+        integer y; 
+        integer x30x16; 
+        integer x14x13; 
+        integer x12x0; 
+        integer x12x8; 
+        integer x7x0; 
+        reg[31:0] xlv; 
+        integer offset; 
+
+        begin
+            if (isvar)
+            begin
+                xlv    = x; 
+                x30x16 = xlv[30:16]; 
+                x14x13 = xlv[14:13]; 
+                x12x0  = xlv[12:0]; 
+                x12x8  = xlv[12:8]; 
+                x7x0   = xlv[7:0]; 
+                offset = 0; 
+                if ((xlv[15]) == 1\'b1)
+                begin
+                    // ARRAY offset in upper 16 bits
+                    offset = get_para_value(1, x30x16);
+                end 
+                case (x14x13)
+                    3 :
+                                begin
+                                    case (x12x8)
+                                        D_NORMAL :
+                                                    begin
+                                                        case (x7x0)
+                                                            // E_CONST
+                                                            D_RETVALUE :
+                                                                        begin
+                                                                            y = return_value; 
+                                                                        end
+                                                            D_TIME :
+                                                                        begin
+                                                                            y = ( $time / 1); 
+                                                                        end
+                                                            D_DEBUG :
+                                                                        begin
+                                                                            y = DEBUG; 
+                                                                        end
+                                                            D_LINENO :
+                                                                        begin
+                                                                            y = cmd_lineno; 
+                                                                        end
+                                                            D_ERRORS :
+                                                                        begin
+                                                                            y = ERRORS; 
+                                                                        end
+                                                            D_TIMER :
+                                                                        begin
+                                                                            y = instructions_timer - 1; 
+                                                                        end
+                                                            D_LTIMER :
+                                                                        begin
+                                                                            y = var_ltimer; 
+                                                                        end
+                                                            D_LICYCLES :
+                                                                        begin
+                                                                            y = var_licycles; 
+                                                                        end
+                                                            default :
+                                                                        begin
+                                                                            $display(""Illegal Parameter P0 (FAILURE)""); 
+                                                                        end
+                                                        endcase 
+                                                    end
+                                        D_ARGVALUE :
+                                                    begin
+                                                        case (x7x0)
+                                                            0   :\t  y = ARGVALUE0;  
+                                                            1   :\t  y = ARGVALUE1;  
+                                                            2   :\t  y = ARGVALUE2;  
+                                                            3   :\t  y = ARGVALUE3;  
+                                                            4   :\t  y = ARGVALUE4;  
+                                                            5   :\t  y = ARGVALUE5;  
+                                                            6   :\t  y = ARGVALUE6;  
+                                                            7   :\t  y = ARGVALUE7;  
+                                                            8   :\t  y = ARGVALUE8;  
+                                                            9   :\t  y = ARGVALUE9;  
+                                                            10  :\t  y = ARGVALUE10; 
+                                                            11  :\t  y = ARGVALUE11; 
+                                                            12  :\t  y = ARGVALUE12; 
+                                                            13  :\t  y = ARGVALUE13; 
+                                                            14  :\t  y = ARGVALUE14; 
+                                                            15  :\t  y = ARGVALUE15; 
+                                                            16  :\t  y = ARGVALUE16; 
+                                                            17  :\t  y = ARGVALUE17; 
+                                                            18  :\t  y = ARGVALUE18; 
+                                                            19  :\t  y = ARGVALUE19; 
+                                                            20  :\t  y = ARGVALUE20; 
+                                                            21  :\t  y = ARGVALUE21; 
+                                                            22  :\t  y = ARGVALUE22; 
+                                                            23  :\t  y = ARGVALUE23; 
+                                                            24  :\t  y = ARGVALUE24; 
+                                                            25  :\t  y = ARGVALUE25; 
+                                                            26  :\t  y = ARGVALUE26; 
+                                                            27  :\t  y = ARGVALUE27; 
+                                                            28  :\t  y = ARGVALUE28; 
+                                                            29  :\t  y = ARGVALUE29; 
+                                                            30  :\t  y = ARGVALUE30; 
+                                                            31  :\t  y = ARGVALUE31; 
+                                                            32  :\t  y = ARGVALUE32; 
+                                                            33  :\t  y = ARGVALUE33; 
+                                                            34  :\t  y = ARGVALUE34; 
+                                                            35  :\t  y = ARGVALUE35; 
+                                                            36  :\t  y = ARGVALUE36; 
+                                                            37  :\t  y = ARGVALUE37; 
+                                                            38  :\t  y = ARGVALUE38; 
+                                                            39  :\t  y = ARGVALUE39; 
+                                                            40  :\t  y = ARGVALUE40; 
+                                                            41  :\t  y = ARGVALUE41; 
+                                                            42  :\t  y = ARGVALUE42; 
+                                                            43  :\t  y = ARGVALUE43; 
+                                                            44  :\t  y = ARGVALUE44; 
+                                                            45  :\t  y = ARGVALUE45; 
+                                                            46  :\t  y = ARGVALUE46; 
+                                                            47  :\t  y = ARGVALUE47; 
+                                                            48  :\t  y = ARGVALUE48; 
+                                                            49  :\t  y = ARGVALUE49; 
+                                                            50  :\t  y = ARGVALUE50; 
+                                                            51  :\t  y = ARGVALUE51; 
+                                                            52  :\t  y = ARGVALUE52; 
+                                                            53  :\t  y = ARGVALUE53; 
+                                                            54  :\t  y = ARGVALUE54; 
+                                                            55  :\t  y = ARGVALUE55; 
+                                                            56  :\t  y = ARGVALUE56; 
+                                                            57  :\t  y = ARGVALUE57; 
+                                                            58  :\t  y = ARGVALUE58; 
+                                                            59  :\t  y = ARGVALUE59; 
+                                                            60  :\t  y = ARGVALUE60; 
+                                                            61  :\t  y = ARGVALUE61; 
+                                                            62  :\t  y = ARGVALUE62; 
+                                                            63  :\t  y = ARGVALUE63; 
+                                                            64  :\t  y = ARGVALUE64; 
+                                                            65  :\t  y = ARGVALUE65; 
+                                                            66  :\t  y = ARGVALUE66; 
+                                                            67  :\t  y = ARGVALUE67; 
+                                                            68  :\t  y = ARGVALUE68; 
+                                                            69  :\t  y = ARGVALUE69; 
+                                                            70  :\t  y = ARGVALUE70; 
+                                                            71  :\t  y = ARGVALUE71; 
+                                                            72  :\t  y = ARGVALUE72; 
+                                                            73  :\t  y = ARGVALUE73; 
+                                                            74  :\t  y = ARGVALUE74; 
+                                                            75  :\t  y = ARGVALUE75; 
+                                                            76  :\t  y = ARGVALUE76; 
+                                                            77  :\t  y = ARGVALUE77; 
+                                                            78  :\t  y = ARGVALUE78; 
+                                                            79  :\t  y = ARGVALUE79; 
+                                                            80  :\t  y = ARGVALUE80; 
+                                                            81  :\t  y = ARGVALUE81; 
+                                                            82  :\t  y = ARGVALUE82; 
+                                                            83  :\t  y = ARGVALUE83; 
+                                                            84  :\t  y = ARGVALUE84; 
+                                                            85  :\t  y = ARGVALUE85; 
+                                                            86  :\t  y = ARGVALUE86; 
+                                                            87  :\t  y = ARGVALUE87; 
+                                                            88  :\t  y = ARGVALUE88; 
+                                                            89  :\t  y = ARGVALUE89; 
+                                                            90  :\t  y = ARGVALUE90; 
+                                                            91  :\t  y = ARGVALUE91; 
+                                                            92  :\t  y = ARGVALUE92; 
+                                                            93  :\t  y = ARGVALUE93; 
+                                                            94  :\t  y = ARGVALUE94; 
+                                                            95  :\t  y = ARGVALUE95; 
+                                                            96  :\t  y = ARGVALUE96; 
+                                                            97  :\t  y = ARGVALUE97; 
+                                                            98  :\t  y = ARGVALUE98; 
+                                                            99  :\t  y = ARGVALUE99; 
+                                                            default :
+                                                                        begin
+                                                                            $display(""Illegal Parameter P1 (FAILURE)""); 
+                                                                        end
+                                                        endcase 
+                                                    end
+                                        D_RAND :
+                                                    begin
+                                                        lastrandom = random(lastrandom); 
+                                                        y = mask_randomN(lastrandom, x7x0); 
+                                                    end
+                                        D_RANDSET :
+                                                    begin
+                                                        setrandom = lastrandom; 
+                                                        lastrandom = random(lastrandom); 
+                                                        y = mask_randomN(lastrandom, x7x0); 
+                                                    end
+                                        D_RANDRESET :
+                                                    begin
+                                                        lastrandom = setrandom; 
+                                                        lastrandom = random(lastrandom); 
+                                                        y = mask_randomN(lastrandom, x7x0); 
+                                                    end
+                                        default :
+                                                    begin
+                                                        $display(""Illegal Parameter P2 (FAILURE)""); 
+                                                    end
+                                    endcase 
+                                end
+                    2 :
+                                begin
+                                    y = stack[stkptr - x12x0 + offset]; // E_STACK
+                                end
+                    1 :
+                                begin
+                                    y = stack[x12x0 + offset]; // E_ADDR
+                                end
+                    0 :
+                                begin
+                                    y = x12x0; // E_DATA
+                                end
+                    default :
+                                begin
+                                    $display(""Illegal Parameter P3 (FAILURE)""); 
+                                end
+                endcase 
+            end
+            else
+            begin
+                // immediate data
+                y = x; 
+            end 
+            get_para_value = y; 
+        end
+    endfunction
+
+    function integer get_storeaddr;
+        input x; 
+        integer x;
+        input stkptr;
+        integer stkptr;
+
+        integer sa; 
+        integer x30x16; 
+        integer x14x13; 
+        integer x12x0; 
+        integer x12x8; 
+        integer x7x0; 
+        reg[31:0] xlv; 
+        integer offset; 
+
+        begin
+            xlv    = x; 
+            x30x16 = xlv[30:16]; 
+            x14x13 = xlv[14:13]; 
+            x12x0  = xlv[12:0]; 
+            x12x8  = xlv[12:8]; 
+            x7x0   = xlv[7:0]; 
+            offset = 0; 
+            if ((xlv[15]) == 1\'b1)
+            begin
+                // ARRAY offset in upper 16 bits
+                offset = get_para_value(1, x30x16); 
+            end 
+            case (x14x13)
+                3 :
+                            begin
+                                $display(""$Variables not allowed (FAILURE)""); 
+                            end
+                2 :
+                            begin
+                                sa = stkptr - x12x0 + offset; // E_STACK
+                            end
+                1 :
+                            begin
+                                sa = x12x0 + offset; // E_ADDR
+                            end
+                0 :
+                            begin
+                                $display(""Immediate data not allowed (FAILURE)""); 
+                            end
+                default :
+                            begin
+                                $display(""Illegal Parameter P3 (FAILURE)""); 
+                            end
+            endcase 
+            get_storeaddr = sa; 
+        end
+    endfunction 
+
+
+
+//---------------------------------------------------------------------------------------
+
+    // NOTE THIS IS IN ONE HUGE PROCESS FOR SIMULATION PERFORMANCE REASONS 
+    always @(posedge SCLK or negedge SYSRSTN)
+    begin : BFM
+       
+        parameter[0:0] OK1  = 0; 
+        parameter[0:0] OK2  = 1; 
+
+        integer flog;
+        reg initdone; 
+        integer Loopcmd[0:4]; 
+        reg [31:0] commandLV [0:255]; 
+        integer Nvectors; 
+        integer cptr; 
+        integer lptr; 
+        integer fptr; 
+        integer loopcounter; 
+        reg[31:0] command0; 
+        reg[1:0] cmd_size; 
+        integer cmd_cmd; 
+        integer cmd_cmdx4; 
+        integer cmd_scmd; 
+        integer command_length; 
+        integer command_timeout; 
+        reg[2:0] command_size; 
+        reg[31:0] command_address; 
+        reg[31:0] command_data; 
+        reg[31:0] command_mask; 
+        reg do_case; 
+        reg do_read; 
+        reg do_bwrite; 
+        reg do_bread; 
+        reg do_write; 
+        reg do_poll; 
+        reg do_flush; 
+        reg do_idle;
+        reg do_io;
+        reg cmd_active; 
+        reg last_match; 
+        integer wait_counter; 
+        integer bitn; 
+        integer timer; 
+        integer n; 
+        integer i; 
+        integer j; 
+        integer x; 
+        integer y; 
+        integer v; 
+        reg[1:(256)*8] str; 
+        reg[1:(256)*8] logstr; 
+        reg[1:(256)*8] logfile; 
+        integer burst_address; 
+        integer burst_length; 
+        integer burst_count; 
+        integer burst_addrinc; 
+        integer burst_data[0:8191]; 
+        reg[1:(8)*8] istr; 
+        reg bfm_done; 
+        reg filedone; 
+        reg ch; 
+        integer tableid; 
+        integer characters; 
+        integer int_vector; 
+        integer call_address; 
+        integer return_address; 
+        integer jump_address; 
+        integer nparas; 
+        integer data_start; 
+        integer data_inc; 
+        integer hresp_mode; 
+        integer bfm_mode; 
+        integer instruct_cycles; 
+        integer instuct_count; 
+        integer setvar; 
+        integer newvalue; 
+        reg[31:0] EXP; 
+        reg[31:0] GOT; 
+        reg DATA_MATCH_AHB; 
+        reg DATA_MATCH_EXT; 
+        reg DATA_MATCH_IO; 
+        reg hresp_occured; 
+        reg[0:0] HRESP_STATE; 
+        reg[1:(10)*8] tmpstr; 
+        reg ahb_lock; 
+        reg[3:0] ahb_prot; 
+        reg[2:0] ahb_burst; 
+        integer storeaddr; 
+        reg piped_activity; 
+        reg [1:(256)*8] filenames[0:100]; 
+        integer NFILES; 
+        integer filemult; 
+        reg[1:0] su_xsize; 
+        reg[5:0] su_xainc; 
+        reg[16:0] su_xrate; 
+        reg su_flush; 
+        integer su_noburst; 
+        reg su_align; 
+        reg bfm_run; 
+        reg bfm_single; 
+        reg int_active; 
+        reg su_endsim;
+        integer count_xrate; 
+        reg insert_busy; 
+        reg log_ahb; 
+        reg log_ext; 
+        reg log_gpio; 
+        reg log_bfm; 
+        integer bfmc_version; 
+        integer cmpvalue; 
+        integer vectors_version; 
+        integer wait_time; 
+        reg ahbc_hwrite; 
+        reg[1:0] ahbc_htrans; 
+        reg[3:0] ahbc_prot; 
+        reg[2:0] ahbc_burst; 
+        reg      ahbc_lock; 
+        reg      ahb_activity; 
+       
+        reg [256*8:0] vchar;
+        integer c;
+        integer b;
+        integer ni;
+        reg zerocycle; 
+        integer mt_dual; 
+        integer passed[0:15]; 
+        integer npass; 
+        integer returnstk[0:255]; 
+        reg[8:0] wptr_cstk; 
+        reg[8:0] rptr_cstk; 
+        integer casedone[0:255];
+        integer casedepth;
+
+        if (SYSRSTN == 1\'b0)
+        begin
+            // These are auto initialized in VHDL
+            instruct_cycles = 0;
+            instuct_count   = 0;
+            ERRORS          = 0;
+            NFILES          = 0;
+            filemult        = 65536;
+            HRESP_STATE     = OK1;
+            reset_pulse     = 0;
+            var_ltimer      = 0;
+            var_licycles    = 0;
+
+
+            //
+            HCLK_STOP <= 1\'b0 ; 
+            DEBUG <= DEBUGLEVEL ; 
+            HADDR_P0 <= {32{1\'b0}} ; 
+            HBURST_P0 <= {3{1\'b0}} ; 
+            HMASTLOCK_P0 <= 1\'b0 ; 
+            HPROT_P0 <= {4{1\'b0}} ; 
+            HSIZE_P0 <= {3{1\'b0}} ; 
+            HTRANS_P0 <= {2{1\'b0}} ; 
+            HWRITE_P0 <= 1\'b0 ; 
+            GPOUT_P0 <= {32{1\'b0}} ; 
+            INSTR_OUT <= {32{1\'b0}} ; 
+            WRITE_P0 <= 1\'b0 ; 
+            READ_P0 <= 1\'b0 ; 
+            RDATA_P0 <= {32{1\'b0}} ; 
+            MDATA_P0 <= {32{1\'b0}} ; 
+            WDATA_P0 <= {32{1\'b0}} ; 
+            GPIORD_P0 <= 1\'b0 ; 
+            EXTWR_P0 <= 1\'b0 ; 
+            EXTRD_P0 <= 1\'b0 ; 
+            EXTADDR_P0 <= {32{1\'b0}} ; 
+            EXT_DOUT <= {32{1\'b0}} ; 
+            FINISHED_P0 <= 1\'b0 ; 
+            FILENAME[1:8] <= {""UNKNOWN"", 8\'b0 } ; 
+            READ_P1 <= 1\'b0 ; 
+            RDATA_P1 <= {32{1\'b0}} ; 
+            MDATA_P1 <= {32{1\'b0}} ; 
+            LINENO_P1 <= 0 ; 
+            HADDR_P1 <= {32{1\'b0}} ; 
+            FAILED_P0 <= 1\'b0 ; 
+            HRESETN_P0 <= 1\'b0 ; 
+            CON_BUSY <= 1\'b0 ; 
+            LINENO_P1 <= 0 ; 
+            POLL_P0 <= 1\'b0 ; 
+            POLL_P1 <= 1\'b0 ; 
+            DRIVEX_CLK <= 0 ; 
+            DRIVEX_RST <= 0 ; 
+            DRIVEX_ADD <= 0 ; 
+            DRIVEX_DAT <= 0 ; 
+            initdone = 0; 
+            cptr = 0; 
+            cmd_active = 0; 
+            bfm_mode = 0; 
+            do_case = 0; 
+            do_flush = 0; 
+            do_write = 0; 
+            do_read = 0; 
+            do_bwrite = 0; 
+            do_bread = 0; 
+            do_poll = 0; 
+            do_idle = 0; 
+            stkptr = 0; 
+            hresp_mode = 0; 
+            command_timeout = 512; 
+            piped_activity = 0; 
+            ERRORS = 0; 
+            hresp_occured = 0; 
+            ahb_lock = 1\'b0; 
+            ahb_prot = 4\'b0011; 
+            ahb_burst = 3\'b001; 
+            bfm_done = 0; 
+            su_xsize = 2; 
+            su_xainc = 4; 
+            su_xrate = 0; 
+            su_flush = 0; 
+            su_align = 0;\t                   
+            su_endsim = 0;
+            return_value = 0; 
+            bfm_run = 0; 
+            count_xrate = 0; 
+            log_ahb = 0; 
+            log_ext = 0; 
+            log_gpio = 0; 
+            log_bfm = 0; 
+            logopen = NUL; 
+            insert_busy = 0; 
+            wait_time = 0; 
+            lastrandom =1;
+            setrandom =1;
+            logopen =1;
+            npass = 0;
+            wptr_cstk = 0; 
+            rptr_cstk = 0; 
+            casedepth = 0;
+            su_noburst = 0;
+        end
+        else
+        begin
+            CON_RDP1 <= CON_RD ; 
+            CON_WRP1 <= CON_WR ; 
+            EXTWR_P0 <= 1\'b0 ; 
+            EXTRD_P0 <= 1\'b0 ; 
+            GPIORD_P0 <= 1\'b0 ; 
+            GPIOWR_P0 <= 1\'b0 ;
+            do_io = 0; 
+            if (~initdone)
+            begin
+                $display("" ""); 
+                $display(""###########################################################################""); 
+                $display(""AMBA BFM Model""); 
+                $display(""Version %s %s"",BFM_VERSION,BFM_DATE); 
+                $display("" ""); 
+                $display(""Opening BFM Script file %0s"", VECTFILE); 
+                if (~initdone & OPMODE != 2)
+                begin
+                    $readmemh(VECTFILE,vectors);
+                    v = 3000;
+                    initdone = 1; 
+                    Nvectors        = vectors[4]; 
+                    bfmc_version    = vectors[0] % 65536; 
+                    vectors_version = vectors[0] / 65536; 
+                    $display(""Read %0d Vectors - Compiler Version %0d.%0d"", Nvectors, vectors_version, bfmc_version); 
+                    if (vectors_version != C_VECTORS_VERSION)
+                    begin
+                        $display(""Incorrect vectors file format for this BFM %0s  (FAILURE) == "", VECTFILE); 
+                        $stop;
+                    end 
+                    cptr   = vectors[1]; 
+                    fptr   = vectors[2]; 
+                    stkptr = vectors[3];\t// Start Stack after required global storage area
+                    stack[stkptr] = 0;\t    // put a return address of zero on the stack
+                    stkptr = stkptr +1;
+
+                    if (cptr == 0)
+                    begin
+                        $display(""BFM Compiler reported errors (FAILURE)""); 
+                        $stop;
+                    end 
+                    // extract files names     
+                    $display(""BFM:Filenames referenced in Vectors""); 
+                    command0 = vectors[fptr]; 
+                    cmd_cmd  = vectors[fptr] % 256; 
+                    while (cmd_cmd == C_FILEN)
+                    begin
+                        command_length = len_string(vectors[fptr+1]); 
+                        str = extract_string(fptr); 
+                        $display(""  %0s"", str); 
+                        begin : xhdl_6
+                            integer i,b;
+                            for(i = 0; i<256; i=i+1)
+                              for (b=1;b<=8;b=b+1) filenames[NFILES][i*8+b] = str[i*8+b];  
+                        end 
+                        NFILES = NFILES + 1; 
+                        fptr = fptr + command_length; 
+                        command0 = to_slv32(vectors[fptr]); 
+                        cmd_cmd = vectors[fptr] % 256; 
+                    end 
+                    filemult = 65536; 
+                    if (NFILES > 1)  filemult = 32768; 
+                    if (NFILES > 2)  filemult = 16384; 
+                    if (NFILES > 4)  filemult = 8912; 
+                    if (NFILES > 8)  filemult = 4096; 
+                    if (NFILES > 16) filemult = 2048; 
+                    if (NFILES > 32) filemult = 1024; 
+                    bfm_run = (OPMODE == 0); 
+                end 
+            end 
+            if (OPMODE == 2 & ~initdone)
+            begin
+                filemult = 65536; 
+                initdone = 1; 
+                bfm_run = 0; 
+                stkptr = vectors[3]+1;
+                stack[stkptr] =0;
+                stkptr = stkptr+1;
+            end 
+            //--------------------------------------------------------------------------
+            // see whether reset needs deasserting
+            if (reset_pulse <= 1)
+            begin
+                HRESETN_P0 <= 1\'b1 ; 
+            end
+            else
+            begin
+                reset_pulse = reset_pulse - 1; 
+            end 
+     
+            //----------------------------------------------------------------------------------------------------------
+                
+            case (HRESP_STATE)
+                OK1 :
+                            begin
+                                if (HRESP == 1\'b1 & HREADY == 1\'b1)
+                                begin
+                                    $display(""BFM: HRESP Signaling Protocol Error T2 (ERROR)""); 
+                                    ERRORS = ERRORS + 1; 
+                                end 
+                                if (HRESP == 1\'b1 & HREADY == 1\'b0)
+                                begin
+                                    HRESP_STATE = OK2; 
+                                end 
+                            end
+                OK2 :
+                            begin
+                                if (HRESP == 1\'b0 | HREADY == 1\'b0)
+                                begin
+                                    $display(""BFM: HRESP Signaling Protocol Error T3 (ERROR)""); 
+                                    ERRORS = ERRORS + 1; 
+                                end 
+                                if (HRESP == 1\'b1 & HREADY == 1\'b1)
+                                begin
+                                    HRESP_STATE = OK1; 
+                                end 
+                                case (hresp_mode)
+                                    0 :
+                                                begin
+                                                    // should not have occured
+                                                    $display(""BFM: Unexpected HRESP Signaling Occured (ERROR)""); 
+                                                    ERRORS = ERRORS + 1; 
+                                                end
+                                    1 :
+                                                begin
+                                                    // Ignore
+                                                    hresp_occured = 1; 
+                                                end
+                                    default :
+                                                begin
+                                                    $display(""BFM: HRESP mode is not correctly set (ERROR)""); 
+                                                    ERRORS = ERRORS + 1; 
+                                                end
+                                endcase 
+                            end
+            endcase 
+    
+            //----------------------------------------------------------------------------------------------------------
+         
+            if (OPMODE > 0)
+            begin
+                if ((CON_WR == 1\'b1) && ( CON_WRP1 == 1\'b0 || CON_SPULSE ==1))
+                begin
+                    n = to_int(CON_ADDR); 
+                    case (n)
+                        0 :
+                                    begin
+                                        bfm_run = ((CON_DIN[0]) == 1\'b1); 
+                                        bfm_single = ((CON_DIN[1]) == 1\'b1); 
+                                        bfm_done = 0; 
+                                        if ( bfm_run & ~bfm_single)
+                                       \tbegin
+\t                                      stack[stkptr] = 0;\t\t// null return address
+\t                                      stkptr = stkptr+1;
+\t\t\t\t\t                    end 
+                                        //----------------------------------------------------------------------------------------
+                                        // Handle the external command interface
+                                        if (DEBUG >= 2 & bfm_run & ~bfm_single)
+                                        begin
+                                            $display(""BFM: Starting script at %08x (%0d parameters)"", cptr,npass); 
+                                        end 
+                                        if (DEBUG >= 2 & bfm_run & bfm_single)
+                                        begin
+                                            $display(""BFM: Starting instruction at %08x"", cptr); 
+                                        end 
+                                        if (bfm_run)
+                                        begin
+                                            if (npass > 0)
+                                            begin
+                                                // put the stored parameters on the stack
+                                                begin : xhdl_7
+                                                    integer i;
+                                                    for(i = 0; i <= npass - 1; i = i + 1)
+                                                    begin
+                                                        stack[stkptr] = passed[i]; 
+                                                        stkptr = stkptr + 1; 
+                                                    end
+                                                end 
+                                                npass = 0; 
+                                            end 
+                                            wptr_cstk = 0; 
+                                            rptr_cstk = 0; 
+                                        end 
+                                    end
+                        1 :
+                                    begin
+                                        cptr = CON_DIN; 
+                                    end
+                        2 :
+                                    begin
+                                        passed[npass] = CON_DIN; 
+                                        npass = npass + 1; 
+                                    end
+                        default :
+                                    begin
+                                        vectors[n] = to_int_signed(CON_DIN); 
+                                    end
+                    endcase 
+                end 
+                if ((CON_RD == 1\'b1) && ( CON_RDP1 == 1\'b0 || CON_SPULSE ==1))
+                begin
+                    n = to_int(CON_ADDR); 
+                    case (n)
+                        0 :
+                                    begin
+                                        CON_DOUT <= {32{1\'b0}} ; 
+                                        CON_DOUT[2] <= bfm_run ; 
+                                        CON_DOUT[3] <= (ERRORS > 0) ; 
+                                    end
+                        1 :
+                                    begin
+                                        CON_DOUT <= cptr; 
+                                    end
+                        2 :
+                                    begin
+                                        CON_DOUT <= return_value; 
+                                        npass = 0;
+                                    end
+                        3 :
+                                    begin
+                                        if (wptr_cstk > rptr_cstk)
+                                        begin
+                                            CON_DOUT <= returnstk[rptr_cstk] ; 
+                                            rptr_cstk = rptr_cstk + 1; 
+                                        end
+                                        else
+                                        begin
+                                            $display(""BFM: Overread Control return stack""); 
+                                            CON_DOUT <= {32{1\'b0}} ; 
+                                        end 
+                                    end
+                        default :
+                                    begin
+                                        CON_DOUT <= {32{1\'b0}} ; 
+                                    end
+                    endcase 
+                end 
+            end 
+            //----------------------------------------------------------------------------------------
+            // Decode the Commands and schedule activities
+            // Command Processing no requirement on HREADY
+            instruct_cycles    = instruct_cycles + 1; 
+            instructions_timer = instructions_timer + 1; 
+            zerocycle = 1; 
+            while (zerocycle)
+            begin
+                zerocycle = 0; 
+                if (~cmd_active & bfm_run)
+                begin
+                    for (i=0;i<=7;i=i+1) command[i]=0;
+                    command0   = vectors[cptr]; 
+                    cmd_size   = command0[1:0]; 
+                    cmd_cmd    = command0[7:0]; 
+                    cmd_scmd   = command0[15:8]; 
+                    cmd_lineno = command0[31:16]; 
+                    timer = command_timeout; 
+                    instuct_count = instuct_count + 1; 
+                    command_length = 1; 
+                    storeaddr = -1; 
+                    count_xrate = 0; 
+                    if (DEBUG>=5) $display( ""BFM: Instruction %0d Line Number %0d Command %0d"", cptr, cmd_lineno, cmd_cmd); 
+                    if (log_bfm)
+                    begin
+                      $fdisplay(flog,""%05d BF %4d %4d %3d"", $time, cptr, cmd_lineno, cmd_cmd); 
+                    end 
+                    if (cmd_cmd >= 100)
+                    begin
+                        cmd_cmdx4 = cmd_cmd; 
+                    end
+                    else
+                    begin
+                        cmd_cmdx4 = 4 * (cmd_cmd / 4); 
+                    end 
+                    if (cmd_cmd != C_CHKT)
+                    begin
+                        instruct_cycles = 0; 
+                    end 
+                    // Move command from vectors to stack switching parameters if necessary
+                    case (cmd_cmdx4)
+                        C_PRINT, C_HEAD, C_FILEN, C_LOGF :     n = 8; 
+                        C_WRTM, C_RDMC :  n = 4 + vectors[cptr + 1]; 
+                        C_CALLP :         n = 3 + vectors[cptr + 2]; 
+                        C_CALL :          n = 3; 
+                        C_TABLE :         n = 2 + vectors[cptr + 1]; 
+                        C_CALC :          n = 3 + vectors[cptr + 2]; 
+                        C_ECHO :          n = 2 + vectors[cptr + 1]; 
+                        C_EXTWM :         n = 3 + vectors[cptr + 1]; 
+                        default :         n = 8; 
+                    endcase 
+                    if (n > 0)
+                    begin
+                        begin : xhdl_7aa
+                            integer i;
+                            for(i = 0; i <= n - 1; i = i + 1)
+                            begin
+                                if (i >= 1 & i <= 8)
+                                begin
+                                    command[i] = get_para_value(((command0[7 + i]) == 1\'b1), vectors[cptr + i]); 
+                                end
+                                else
+                                begin
+                                    command[i] = vectors[cptr + i]; 
+                                end 
+                                commandLV[i] = to_slv32(command[i]); 
+                            end
+                        end 
+                    end 
+                    case (cmd_cmdx4)
+                        C_FAIL :
+                                    begin
+                                        $display(""BFM Compiler reported an error (FAILURE)""); 
+                                        ERRORS = ERRORS + 1; 
+                                        $stop;
+                                    end
+                        C_CONPU :
+                                    begin
+                                        command_length = 2; 
+                                        'b'zerocycle = 1; 
+                                        returnstk[wptr_cstk] = command[1]; 
+                                        wptr_cstk = wptr_cstk + 1; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:conifpush %0d"", cmd_lineno,command[1]); 
+                                
+                                    end
+                        C_RESET :
+                                    begin
+                                        command_length = 2; 
+                                        HRESETN_P0 <= 1\'b0 ; 
+                                        reset_pulse = command[1]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:RESET %0d"", cmd_lineno,reset_pulse); 
+                                    end
+                        C_CLKS :
+                                    begin
+                                        command_length = 2; 
+                                        HCLK_STOP <= commandLV[1][0] ; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:STOPCLK %0d "", cmd_lineno, commandLV[1][0]); 
+                                    end
+                        C_MODE :
+                                    begin
+                                        command_length = 2; 
+                                        bfm_mode = command[1]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:mode %0d (No effect in this version)"", cmd_lineno, bfm_mode); 
+                                    end
+                        C_SETUP :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 4; 
+                                        n = command[1]; 
+                                        x = command[2]; 
+                                        y = command[3]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:setup %0d %0d %0d "", cmd_lineno, n, x, y); 
+                                        // Main Command Processing
+                                        case (n)
+                                            1 :
+                                                        begin
+                                                            command_length = 4; 
+                                                            su_xsize = x; 
+                                                            su_xainc = y; 
+                                                            if (DEBUG>=2) $display( ""BFM:%0d:Setup- Memory Cycle Transfer Size %0s %0d"", cmd_lineno, to_char(su_xsize), su_xainc); 
+                                                        end
+                                            2 :
+                                                        begin
+                                                            command_length = 3; 
+                                                            su_flush = to_boolean(x); 
+                                                            if (DEBUG>=2) $display( ""BFM:%0d:Setup- Automatic Flush %0d"", cmd_lineno, su_flush); 
+                                                        end
+                                            3 :
+                                                        begin
+                                                            command_length = 3; 
+                                                            su_xrate = x; 
+                                                            if (DEBUG>=2) $display( ""BFM:%0d:Setup- XRATE %0d"", cmd_lineno, su_xrate); 
+                                                        end
+                                            4 :
+                                                        begin
+                                                            command_length = 3; 
+                                                            su_noburst = x; 
+                                                            if (DEBUG>=2) $display( ""BFM:%0d:Setup- Burst Mode %0d"", cmd_lineno, su_noburst); 
+                                                        end
+                                            5 :
+                                                        begin
+                                                            command_length = 3; 
+                                                            su_align = x; 
+                                                            if (DEBUG >= 2) $display( ""BFM:%0d:Setup- Alignment %0d"", cmd_lineno, su_align); 
+                                                            if (su_align == 1 | su_align == 2)
+                                                            begin
+                                                                $display(""BFM: Untested 8 or 16 Bit alignment selected (WARNING)""); 
+                                                            end 
+                                                        end
+                                            6:          begin
+                                                           command_length = 3;
+                                                           // ignore VHDL endsim command
+                                                        end
+                                            7:          begin
+                                                            command_length = 3; 
+                                                            su_endsim =   x; 
+                                                            if (DEBUG >= 2) $display( ""BFM:%0d:Setup- End Sim Action %0d"", cmd_lineno, su_endsim); 
+                                                            if ( su_endsim > 2)
+                                                            begin
+                                                                $display(""BFM: Unexpected End Simulation value (WARNING)""); 
+                                                            end 
+                                                        end
+                                           
+                                            default :
+                                                        begin
+                                                            $display(""BFM Unknown Setup Command (FAILURE)""); 
+                                                        end
+                                        endcase 
+                                    end
+               
+                        C_DRVX :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        DRIVEX_ADD <= ((commandLV[1][0]) == 1\'b1) ; 
+                                        DRIVEX_DAT <= ((commandLV[1][1]) == 1\'b1) ; 
+                                        DRIVEX_RST <= ((commandLV[1][2]) == 1\'b1) ; 
+                                        DRIVEX_CLK <= ((commandLV[1][3]) == 1\'b1) ; 
+                                        if (DEBUG >= 2) $display( ""BFM:%0d:drivex %0d "", cmd_lineno,command[1]); 
+                                    end
+               
+               
+                        C_ERROR :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 3; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:error %0d %0d (No effect in this version)"", cmd_lineno, command[1], command[2]); 
+                                    end
+                        C_PROT :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        ahb_prot = commandLV[1][3:0]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:prot %0d "", cmd_lineno, ahb_prot); 
+                                    end
+                        C_LOCK :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        ahb_lock = commandLV[1][0]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:lock %0d "", cmd_lineno, ahb_lock); 
+                                    end
+                        C_BURST :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        ahb_burst = commandLV[1][2:0]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:burst %0d "", cmd_lineno, ahb_burst); 
+                                    end
+                        C_WAIT :
+                                    begin
+                                        command_length = 2; 
+                                        wait_counter = command[1]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:wait %0d  starting at %0d ns"", cmd_lineno, wait_counter,$time); 
+                                        do_case = 1; 
+                                    end
+                        C_WAITUS :
+                                    begin
+                                        command_length = 2; 
+                                        wait_time = command[1] * 1000 + ($time / 1); 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:waitus %0d  starting at %0d ns"", cmd_lineno, command[1],$time); 
+                                        do_case = 1; 
+                                    end
+                        C_WAITNS :
+                                    begin
+                                        command_length = 2; 
+                                        wait_time = command[1] * 1 + ($time / 1); 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:waitns %0d  starting at %0d ns"", cmd_lineno, command[1],$time); 
+                                        do_case = 1; 
+                                    end
+                        C_CHKT :
+                                    begin
+                                        command_length = 3; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:checktime %0d %0d at %0d ns"", cmd_lineno, command[1], command[2],$time); 
+                                        do_case = 1;
+                                    end
+                  
+                        C_STTIM :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 1; 
+                                        instructions_timer = 1; 
+                                        if (DEBUG>=2) $display(""BFM:%0d:starttimer at %0d ns"", cmd_lineno,$time); 
+                                    end
+                        C_CKTIM :
+                                    begin
+                                        command_length = 3; 
+                                        if (DEBUG>=2) $display(""BFM:%0d:checktimer %0d %0d at %0d ns "", cmd_lineno, command[1], command[2],$time); 
+                                        do_case = 1; 
+                                    end
+                  
+                        C_NOP :
+                                    begin
+                                        command_length = 1; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:nop"", cmd_lineno); 
+                                    end
+                        C_WRITE :
+                                    begin
+                                        command_length = 4; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = commandLV[3]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:write %c %08x %08x at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, command_data,$time); 
+                                        do_write = 1; 
+                                    end
+      
+                        C_AHBC :
+                                    begin
+                                        command_length = 5; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = commandLV[3]; 
+                                        ahbc_hwrite = commandLV[4][0]; 
+                                        ahbc_htrans = commandLV[4][5:4]; 
+                                        ahbc_burst = commandLV[4][10:8]; 
+                                        ahbc_lock = commandLV[4][12]; 
+                                        ahbc_prot = commandLV[4][19:16]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:idle %c %08x %08x %08x at %0d ns"",cmd_lineno, to_char(cmd_size),
+                                                                                                          command_address,command_data, commandLV[4],$time); 
+                                        do_idle = 1; 
+                                    end
+      
+                        C_READ :
+                                    begin
+                                        command_length = 3; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = {32{1\'b0}}; 
+                                        command_mask = {32{1\'b0}}; 
+                                        if (DEBUG>=2) $display(""BFM:%0d:read %c %08x at %0d ns"", cmd_lineno, to_char(cmd_size), command_address,$time); 
+                                        do_read = 1; 
+                                    end
+                        C_READS :
+                                    begin
+                                        command_length = 4; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = {32{1\'b0}}; 
+                                        command_mask = {32{1\'b0}}; 
+                                        storeaddr = get_storeaddr(vectors[cptr + 3],stkptr); // take pointer from vectors
+                                        if (DEBUG>=2) $display( ""BFM:%0d:readstore %c %08x @%0d at %0d ns "", 
+                                                cmd_lineno, to_char(cmd_size), command_address, storeaddr,$time); 
+                                        do_read = 1; 
+                                        do_flush = 1; 
+                                    end
+                        C_RDCHK :
+                                    begin
+                                        command_length = 4; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = commandLV[3]; 
+                                        command_mask = {32{1\'b1}}; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:readcheck %c %08x %08x at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, command_data,$time); 
+                                        do_read = 1; 
+                                    end
+                        C_RDMSK :
+                                    begin
+                                        command_length = 5; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = commandLV[3]; 
+                                        command_mask = commandLV[4]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:readmask %c %08x %08x %08x at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, command_data, command_mask,$time); 
+                                        do_read = 1; 
+                                    end
+                        C_POLL :
+                                    begin
+                                        command_length = 4; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = commandLV[3]; 
+                                        command_mask = {32{1\'b1}}; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:poll %c %08x %08x at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, command_data,$time); 
+                                        cmd_active = 1; 
+                                        do_poll = 1; 
+                                        do_poll = 1; 
+                                    end
+                        C_POLLM :
+                                    begin
+                                        command_length = 5; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = commandLV[3]; 
+                                        command_mask = commandLV[4]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:pollmask %c %08x %08x %08x at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, command_data, command_mask,$time); 
+                                        do_poll = 1; 
+                                    end
+                        C_POLLB :
+                                    begin
+                                        command_length = 5; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_data = {32{1\'b0}}; 
+                                        command_mask = {32{1\'b0}}; 
+                                        bitn = command[3]; 
+                                        command_mask[bitn] = 1\'b1; 
+                                        command_data[bitn] = commandLV[4][0]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:pollbit %c %08x %0d %0d at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, bitn, command_data[bitn],$time); 
+                                        do_poll = 1; 
+                                    end
+                        C_WRTM :
+                                    begin
+                                        burst_length = command[1]; 
+                                        command_length = 4 + burst_length; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[2] + command[3]); 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        begin : xhdl_8
+                                            integer i;
+                                            for(i = 0; i <= burst_length - 1; i = i + 1)
+                                            begin
+                                                burst_data[i] = command[i + 4]; 
+                                            end
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:writemultiple %c %08x %08x ... at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, burst_data[0],$time); 
+                                        do_bwrite = 1; 
+                                    end
+                        C_FILL :
+                                    begin
+                                        burst_length = command[3]; 
+                                        command_length = 6; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        data_start = command[4]; 
+                                        data_inc = command[5]; 
+                                        begin : xhdl_9
+                                            integer i;
+                                            for(i = 0; i <= burst_length - 1; i = i + 1)
+                                            begin
+                                                burst_data[i] = data_start; 
+                                                data_start = data_start + data_inc; 
+                                            end
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:fill %c %08x %0d %0d %0d at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, burst_length, command[4], command[4],$time); 
+                                        do_bwrite = 1; 
+                                    end
+                        C_WRTT :
+                                    begin
+                                        burst_length = command[4]; 
+                                        command_length = 5; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        tableid = command[3]; 
+                                        begin : xhdl_10
+                                            integer i;
+                                            for(i = 0; i <= burst_length - 1; i = i + 1)
+                                            begin
+                                                burst_data[i] = vectors[2 + tableid + i]; 
+                                            end
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:writetable %c %08x %0d %0d at %0d ns "", cmd_lineno, to_char(cmd_size), command_address, tableid, burst_length,$time); 
+                                        do_bwrite = 1; 
+                                    end
+                      
+                        C_WRTA :
+                                    begin
+                                        burst_length = command[4]; 
+                                        command_length = 5; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        setvar = get_storeaddr(vectors[cptr + 3],stkptr); 
+                                        begin : xhdl_10a
+                                            integer i;
+                                            for(i = 0; i <= burst_length - 1; i = i + 1)
+                                            begin
+                                                burst_data[i] = stack[setvar + i]; 
+                                            end
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:writearray %c %08x %0d %0d at %0d ns "", 
+                                                                 cmd_lineno, to_char(cmd_size), command_address,setvar, burst_length,$time); 
+                                        do_bwrite = 1; 
+                                    end
+                      
+                      
+                        C_RDM :
+                                    begin
+                                        burst_length = command[3]; // note this is a fixed length instruction
+                                        command_length = 4; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_mask = {32{1\'b0}}; 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        command_mask = {32{1\'b0}}; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:readmult %c %08x %0d at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, burst_length,$time); 
+                                        do_bread = 1; 
+                                    end
+                        C_RDMC :
+                                    begin
+                                        burst_length = command[1]; 
+                                        command_length = 4 + burst_length; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[2] + command[3]); 
+                                        command_mask = {32{1\'b1}}; 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        command_mask = {32{1\'b1}}; 
+                                        begin : xhdl_11
+                                            integer i;
+                                            for(i = 0; i <= burst_length - 1; i = i + 1)
+                                            begin
+                                                burst_data[i] = command[i + 4]; 
+                                            end
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:readmultchk %c %08x %08x ... at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, burst_data[0],$time); 
+                                        do_bread = 1; 
+                                    end
+                        C_READF :
+                                    begin
+                                        burst_length = command[3]; 
+                                        command_length = 6; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_mask = {32{1\'b1}}; 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        data_start = command[4]; 
+                                        data_inc = command[5]; 
+                                        begin : xhdl_12
+                                            integer i;
+                                            for(i = 0; i <= burst_length - 1; i = i + 1)
+                                            begin
+                                                burst_data[i] = data_start; 
+                                                data_start = data_start + data_inc; 
+                                            end
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:fillcheck %c %08x %0d %0d %0d at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, burst_length, command[4], command[5],$time); 
+                                        do_bread = 1; 
+                                    end
+                        C_READT :
+                                    begin
+                                        burst_length = command[4]; 
+                                        command_length = 5; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_mask = {32{1\'b1}}; 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        tableid = command[3]; 
+                                        begin : xhdl_13
+                                            integer i;
+                                            for(i = 0; i <= burst_length - 1; i = i + 1)
+                                            begin
+                                                burst_data[i] = vectors[tableid + 2 + i]; 
+                                            end
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:readtable %c %08x %0d %0d at %0d ns"", cmd_lineno, to_char(cmd_size), command_address, tableid, burst_length,$time); 
+                                        do_bread = 1; 
+                                    end
+                        C_READA :
+                                    begin
+                                        burst_length = command[4]; 
+                                        command_length = 5; 
+                                        command_size = xfer_size(cmd_size, su_xsize); 
+                                        command_address = to_slv32(command[1] + command[2]); 
+                                        command_mask = {32{1\'b1}}; 
+                                        burst_count = 0; 
+                                        burst_addrinc = address_increment(cmd_size, su_xainc); 
+                                        setvar = get_storeaddr(vectors[cptr + 3],stkptr); 
+                                        begin : xhdl_13s
+                                            integer i;
+                                            for(i = 0; i <= burst_length - 1; i = i + 1)
+                                            begin
+                                                burst_data[i] = stack[setvar + i];  
+                                            end
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:readtable %c %08x %0d %0d at %0d ns"", 
+                                                                           cmd_lineno, to_char(cmd_size), command_address, setvar, burst_length,$time); 
+                                        do_bread = 1; 
+                                    end
+                        C_MEMT :
+                                    begin
+                                        command_length = 7; 
+                                        do_case = 1; 
+                                        mt_state = init; 
+                                    end
+                        C_MEMT2 :
+                                    begin
+                                        command_length = 7; 
+                                        do_case = 1; 
+                                        mt_state = init; 
+                                    end
+                        C_FIQ :
+                                    begin
+                                        command_length = 1; 
+                                        int_vector = 0; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:waitfiq at %0d ns "", cmd_lineno,$time); 
+                                        do_case = 1; 
+                                    end
+                        C_IRQ :
+                                    begin
+                                        command_length = 1; 
+                                        int_vector = 1; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:waitirq at %0d ns "", cmd_lineno,$time); 
+                                        do_case = 1; 
+                                    end
+                        C_INTREQ :
+                                    begin
+                                        command_length = 2; 
+                                        int_vector = command[1]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:waitint %0d  at %0d ns"", cmd_lineno, int_vector,$time); 
+                                        do_case = 1; 
+                                    end
+                        C_IOWR :
+                                    begin
+                                        command_length = 2; 
+                                        command_data = commandLV[1]; 
+                                        GPOUT_P0 <= command_data ; 
+                                        GPIOWR_P0 <= 1\'b1 ; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:iowrite %08x  at %0d ns "", cmd_lineno, command_data,$time); 
+                                    end                                                                                  
+                        C_IORD :
+                                    begin
+                                        command_length = 2; 
+                                        command_data = {32{1\'b0}}; 
+                                        command_mask = {32{1\'b0}}; 
+                                        storeaddr = get_storeaddr(vectors[cptr + 1],stkptr); // take pointer from vectors
+                                        if (DEBUG>=2) $display( ""BFM:%0d:ioread @%0d at %0d ns"", cmd_lineno, storeaddr,$time); 
+                                        GPIORD_P0 <= 1\'b1 ; 
+                                        do_case = 1; 
+                                        do_flush = 1; 
+                                        do_io = 1;
+                                    end
+                        C_IOCHK :
+                                    begin
+                                        command_length = 2; 
+                                        command_data = commandLV[1]; 
+                                        command_mask = {32{1\'b1}}; 
+                                        GPIORD_P0 <= 1\'b1 ; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:iocheck %08x  at %0d ns "", cmd_lineno, command_data,$time); 
+                                        do_case = 1; 
+                                    end
+                        C_IOMSK :
+                                    begin
+                                        command_length = 3; 
+                                        command_data = commandLV[1]; 
+                                        command_mask = commandLV[2]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:iomask %08x %08x  at %0d ns"", cmd_lineno, command_data, command_mask,$time); 
+                                        GPIORD_P0 <= 1\'b1 ; 
+                                        do_case = 1; 
+                                    end
+                        C_IOTST :
+                                    begin
+                                        command_length = 2; 
+                                        command_data = {32{1\'b0}}; 
+                                        command_mask = {32{1\'b0}}; 
+                                        bitn = command[1]; 
+                                        command_data[bitn] = command0[0]; 
+                                        command_mask[bitn] = 1\'b1; 
+                                        GPIORD_P0 <= 1\'b1 ; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:iotest %0d %0d  at %0d ns"", cmd_lineno, bitn, command0[0],$time); 
+                                        do_case = 1; 
+                                    end
+                        C_IOSET :
+                                    begin
+                                        command_length = 2; 
+                                        bitn = command[1]; 
+                                        GPOUT_P0[bitn] <= 1\'b1 ; 
+                                        GPIOWR_P0 <= 1\'b1 ; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:ioset %0d at %0d ns"", cmd_lineno, bitn,$time); 
+                                    end
+                        C_IOCLR :
+                                    begin
+                                        command_length = 2; 
+                                        bitn = command[1]; 
+                                        GPOUT_P0[bitn] <= 1\'b0 ; 
+                                        GPIOWR_P0 <= 1\'b1 ; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:ioclr %0d at %0d ns"", cmd_lineno, bitn,$time); 
+                                    end
+                        C_IOWAIT :
+                                    begin
+                                        command_length = 2; 
+                                        command_data = {32{1\'b0}}; 
+                                        command_mask = {32{1\'b0}}; 
+                                        bitn = command[1]; 
+                                        command_data[bitn] = command0[0]; 
+                                        command_mask[bitn] = 1\'b1; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:iowait %0d %0d at %0d ns "", cmd_lineno, bitn, command0[0],$time); 
+                                        GPIORD_P0 <= 1\'b1 ; 
+                                        do_case = 1; 
+                                    end
+                        C_EXTW :
+                                    begin
+                                        command_length = 3; 
+                                        command_address = commandLV[1]; 
+                                        command_data = commandLV[2]; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:extwrite %08x %08x at %0d ns"", cmd_lineno, command_address, command_data,$time); 
+                                        do_case = 1; 
+                                    end
+                        C_EXTR :
+                                    begin
+                                        command_length = 3; 
+                                        command_address = commandLV[1]; 
+                                        command_data = {32{1\'b0}}; 
+                                        command_mask = {32{1\'b0}}; 
+                                        storeaddr =get_storeaddr(vectors[cptr + 2],stkptr); // take pointer from vectors
+                                        EXTRD_P0 <= 1\'b1 ; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:extread @%0d %08x at %0d ns "", cmd_lineno, storeaddr, command_address,$time); 
+                                        do_case = 1; 
+                                        do_flush = 1; 
+                                        do_io = 1;
+                                    end
+                       
+                        C_EXTWM :
+                                    begin
+                                        burst_length = command[1]; 
+                                        burst_address = command[2]; 
+                                        command_length = burst_length + 3; 
+                                        begin : xhdl_14
+                                            integer i;
+                                            for(i = 0; i < burst_length ; i = i + 1)
+                                            begin
+                                                burst_data[i] = command[i + 3]; 
+                                            end
+                                        end 
+                                        if (DEBUG >= 2) $display(""BFM:%0d:extwrite %08x %0d Words at %0t ns"", cmd_lineno,command_address, burst_length, $time); 
+                                        burst_count = 0; 
+                                        do_case = 1; 
+                                    end
+                   
+                        C_EXTRC :
+                                    begin
+                                        command_length = 3; 
+                                        command_address = commandLV[1]; 
+                                        command_data = commandLV[2]; 
+                                        command_mask = {32{1\'b1}}; 
+                                        cmd_active = 1; 
+                                        EXTRD_P0 <= 1\'b1 ; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:extcheck %08x %08x at %0d ns"", cmd_lineno, command_address, command_data,$time); 
+                                        do_case = 1; 
+                                    end
+                        C_EXTMSK :
+                                    begin
+                                        command_length = 4; 
+                                        command_address = commandLV[1]; 
+                                        command_data = commandLV[2]; 
+                                        command_mask = commandLV[3]; 
+                                        EXTRD_P0 <= 1\'b1 ; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:extmask %08x %08x %08x at %0d ns"", cmd_lineno, command_address, command_data, command_mask,$time); 
+                                        do_case = 1; 
+                                    end
+                        C_EXTWT :
+                                    begin
+                                        command_length = 1; 
+                                        wait_counter = 1; 
+                                        cmd_active = 1; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:extwait "", cmd_lineno); 
+                                        do_case = 1; 
+                                    end
+                        C_LABEL :
+                                    begin
+                                        $display(""LABEL instructions not allowed in vector files (FAILURE)""); 
+                                    end
+                        C_TABLE :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2 + command[1]; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:table %08x ... (length=%0d)"", cmd_lineno, command[2], command_length - 2); 
+                                    end
+                        C_JMP :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        jump_address = command[1]; 
+                                        command_length = jump_address - cptr; // point at new address
+                                        if (DEBUG>=2) $display( ""BFM:%0d:jump"", cmd_lineno); 
+                                    end
+                        C_JMPZ :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 3; 
+                                        jump_address = command[1]; 
+                                        if (command[2] == 0)
+                                        begin
+                                            command_length = jump_address - cptr; // point at new address
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:jumpz  %08x"", cmd_lineno, command[2]); 
+                                    end
+                        C_IF :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 5; 
+                                        jump_address = command[1]; 
+                                        newvalue = calculate(command[3], command[2], command[4], DEBUG); 
+                                        if (newvalue == 0)
+                                        begin
+                                            command_length = jump_address + 2 - cptr; // point at new address
+                                        end 
+                                        if (DEBUG>=2) $display(""BFM:%0d:if %08x func %08x"", cmd_lineno, command[2], command[4]); 
+                                    end
+                        C_IFNOT :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 5; 
+                                        jump_address = command[1]; 
+                                        newvalue = calculate(command[3], command[2], command[4], DEBUG); 
+                                        if (newvalue != 0)
+                                        begin
+                                            command_length = jump_address + 2 - cptr; // point at new address
+                                        end 
+                                        if (DEBUG>=2) $display(""BFM:%0d:ifnot %08x func %08x"", cmd_lineno, command[2], command[4]); 
+                                    end
+                     
+                        C_ELSE :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        jump_address = command[1]; 
+                                        command_length = jump_address + 2 - cptr; // point at new address
+                                        if (DEBUG>=2) $display(""BFM:%0d:else "",cmd_lineno); 
+                                    end
+                      
+                        C_ENDIF :
+                                    begin
+                                        zerocycle = 1; // do nothing endif is pad instruction stream so +2 works
+                                        command_length = 2; 
+                                        if (DEBUG>=2) $display(""BFM:%0d:endif "",cmd_lineno); 
+                                    end
+                        C_WHILE :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 5; 
+                                        jump_address = command[1] + 2; // after endwhile
+                                        newvalue = calculate(command[3], command[2], command[4], DEBUG); 
+                                        if (newvalue == 0)
+                                        begin
+                                            command_length = jump_address - cptr; // point at new address
+                                        end 
+                                        if (DEBUG>=2) $display(""BFM:%0d:while %08x func %08x"", cmd_lineno, command[2], command[4]); 
+                                    end
+                        C_ENDWHILE :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        jump_address = command[1]; 
+                                        command_length = jump_address - cptr; // point at new address
+                                        if (DEBUG>=2) $display( ""BFM:%0d:endwhile"", cmd_lineno); 
+                                    end
+                  
+                        C_WHEN :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 4; 
+                                        jump_address = command[3]; 
+                                        if (command[1] != command[2])
+                                        begin
+                                            command_length = jump_address - cptr; // point at new address ie next when/endcase
+                                        end 
+                                        else
+                                        begin
+                                            casedone[casedepth] = 1; // doing this branch
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:when %08x=%08x %08x"", cmd_lineno, command[1], command[2], command[3]); 
+                                    end
+                  
+                        C_DEFAULT :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 4; 
+                                        jump_address = command[3]; 
+                                        if (casedone[casedepth])
+                                        begin
+                                            // if already done then branch
+                                            command_length = jump_address - cptr; // point at new address ie next when/endcase
+                                        end
+                                        else
+                                        begin
+                                            casedone[casedepth] = 0; // doing this branch
+                                        end 
+                                        if (DEBUG>=2) $display(""BFM:%0d:default %08x=%08x %08x"", cmd_lineno, command[1], command[2],command[3]); 
+                                    end
+                        C_CASE :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 1; 
+                                        casedepth = casedepth + 1; 
+                                        casedone[casedepth] = 0; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:case"", cmd_lineno); 
+                                    end
+                        C_ENDCASE :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 1; 
+                                        casedepth = casedepth - 1; 
+                                        if (DEBUG>=2) $display(""BFM:%0d:endcase"", cmd_lineno); 
+                                    end
+                  
+                        C_JMPNZ :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 3; 
+                                        jump_address = command[1]; 
+                                        if (command[2] != 0)
+                                        begin
+                                            command_length = jump_address - cptr; // point at new address
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:jumpnz  %08x"", cmd_lineno, command[2]); 
+                                    end
+                        C_CMP :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 4; 
+                                        command_data = commandLV[2]; 
+                                        command_mask = commandLV[3]; 
+                                        cmpvalue = (commandLV[1] ^ command_data) & command_mask; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:compare  %08x==%08x Mask=%08x (RES=%08x) at %0d ns"", cmd_lineno, command[1], command_data, command_mask, cmpvalue,$time); 
+                                        if (cmpvalue != 0)
+                                        begin
+                                            ERRORS = ERRORS + 1; 
+                                            $display(""ERROR:  compare failed %08x==%08x Mask=%08x (RES=%08x) "", command[1], command_data, command_mask, cmpvalue); 
+                                            $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(cmd_lineno, filemult)], get_line(cmd_lineno, filemult)); 
+                                            $display(""BFM Data Compare Error (ERROR)""); 
+                                            $stop;
+                                        end 
+                                    end
+                        C_CMPR :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 4; 
+                                        command_data = commandLV[2]; 
+                                        command_mask = commandLV[3]; 
+                                        if (command[1] >= command[2] & command[1] <= command[3])
+                                        begin
+                                            cmpvalue = 1; 
+                                        end
+                                        else
+                                        begin
+                                            cmpvalue = 0; 
+                                        end 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:cmprange %0d in %0d to %0d at %0d ns"", cmd_lineno, command[1], command[2], command[3],$time); 
+                                        if (cmpvalue == 0)
+                                        begin
+                                            ERRORS = ERRORS + 1; 
+                                            $display(""ERROR: cmprange failed %0d in %0d to %0d"", command[1], command[2], command[3]); 
+                                            $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(cmd_lineno, filemult)], get_line(cmd_lineno, filemult)); 
+                                            $display(""BFM Data Compare Error (ERROR)""); 
+                                            $stop;
+                                        end 
+                                    end
+                        C_INT :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        nparas = command[1]; 
+                                        stkptr = stkptr + nparas; 
+                                        stack[stkptr] = 0; 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:int %0d"", cmd_lineno, command[1]); 
+                                    end
+                                    \t
+                        C_CALL, C_CALLP :
+                                    begin
+                                        zerocycle = 1; 
+                                        if (cmd_cmd == C_CALL)
+                                        begin
+                                            command_length = 2; 
+                                            nparas = 0; 
+                                        end
+                                        else
+                                        begin
+                                            nparas = command[2]; 
+                                            command_length = 3 + nparas; 
+                                        end 
+                                        call_address = command[1]; 
+                                        return_address = cptr + command_length; 
+                                        command_length = call_address - cptr; // point at new address
+                                        stack[stkptr] = return_address; 
+                                        stkptr = stkptr + 1; 
+                                        if (nparas > 0)
+                                        begin
+                                            begin : xhdl_16
+                                                integer i;
+                                                for(i = 0; i <= nparas - 1; i = i + 1)
+                                                begin
+                                                    stack[stkptr] = command[3 + i]; 
+                                                    stkptr = stkptr + 1; 
+                                                end
+                                            end 
+                                        end 
+                                        if (DEBUG >= 2 & cmd_cmd == C_CALL)  $display(""BFM:%0d:call %0d"", cmd_lineno, call_address); 
+                                        if (DEBUG >= 2 & cmd_cmd == C_CALLP) $display(""BFM:%0d:call %0d %08x ..."", cmd_lineno, call_address, command[3]); 
+                                    end
+                        C_RET :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        stkptr = stkptr - command[1]; // no of values pushed
+                                        return_address = 0; 
+                                        if (stkptr > 0)
+                                        begin
+                                            stkptr = stkptr - 1; 
+                                            return_address = stack[stkptr]; 
+                                        end 
+                                        if (return_address == 0)
+                                        begin
+                                            bfm_done = 1; 
+                                            do_flush = 1; 
+                                            zerocycle = 0; 
+                                        end
+                                        else
+                                        begin
+                                            command_length = return_address - cptr; // point at new address
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:return"", cmd_lineno); 
+                                    end
+                        C_RETV :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 3; 
+                                        stkptr = stkptr - command[1]; // no of values pushed
+                                        return_address = 0; 
+                                        if (stkptr > 0)
+                                        begin
+                                            stkptr = stkptr - 1; 
+                                            return_address = stack[stkptr]; 
+                                        end 
+                                        return_value = command[2]; 
+                                        if (return_address == 0)
+                                        begin
+                                            bfm_done = 1; 
+                                            do_flush = 1; 
+                                            zerocycle = 0; 
+                                        end
+                                        else
+                                        begin
+                                            command_length = return_address - cptr; // point at new address
+                                        end 
+                                        if (DEBUG>=2) $display( ""BFM:%0d:return %08x"", cmd_lineno, return_value); 
+                                    end
+                        C_LOOP :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 5; 
+                                        setvar = get_storeaddr(vectors[cptr + 1],stkptr); 
+                                        newvalue = command[2]; 
+                                        stack[setvar] = newvalue; 
+                                        if (DEBUG >= 2)  $display(""BFM:%0d:loop %0d %0d %0d %0d "", cmd_lineno, setvar, command[2], command[3], command[4]); 
+                                    end
+                        C_LOOPE :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        lptr = command[1]; // points at the loop commands
+                                        // Get parameters from the loop command
+                                        begin : xhdl_19a
+                                            integer i;
+                                            for(i = 2; i <= 4; i = i + 1)
+                                            begin
+                                                Loopcmd[i] = get_para_value((to_slv32(vectors[lptr][7 + i]) == 1\'b1), vectors[lptr + i]); 
+                                            end
+                                        end 
+                                        setvar = get_storeaddr(vectors[lptr + 1],stkptr); 
+                                        n = Loopcmd[4]; 
+                                        j = Loopcmd[3]; 
+                                        //$display(""OLD LOOP %0d  INC %0d  LIMIT %0d"",stack(setvar)),n),j);
+                                        loopcounter = stack[setvar]; 
+                                        loopcounter = loopcounter + n; 
+                                        stack[setvar] = loopcounter; 
+                                        jump_address = lptr + 5; 
+                                        if ((n >= 0 & loopcounter <= j) | (n < 0 & loopcounter >= j))
+                                        begin
+                                            command_length = jump_address - cptr; // point at new address
+                                            if ( DEBUG >=2) $display(""BFM:%0d:endloop (Next Loop=%0d)"", cmd_lineno, loopcounter); 
+                                        end
+                                        else
+                                        begin
+                                            if ( DEBUG >=2) $display(""BFM:%0d:endloop (Finished)"", cmd_lineno); 
+                                        end 
+                                    end
+                        C_TOUT :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        command_timeout = command[1]; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:timeout %0d"", cmd_lineno, command_timeout); 
+                                    end
+                     
+                        C_RAND :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        lastrandom = command[1]; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:rand %0d"",cmd_lineno,lastrandom); 
+                                    end
+                     
+                        C_PRINT :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = len_string(vectors[cptr+1]); 
+                                        str = extract_string(cptr); 
+                                        $display(""BFM:%0s"", str); 
+                                    end
+                        C_HEAD :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = len_string(vectors[cptr+1]); 
+                                        str = extract_string(cptr); 
+                                        $display(""################################################################""); 
+                                        $display(""BFM:%0s"", str); 
+                                    end
+                        C_FILEN :
+                                    begin
+                                        zerocycle = 1; 
+                                        characters = to_int(command0[15:8]); 
+                                        command_length = (characters - 1) / 4 + 2; 
+                                    end
+                        C_DEBUG :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        if (DEBUGLEVEL >= 0 & DEBUGLEVEL <= 5)
+                                        begin
+                                            $display(""BFM:%0d: DEBUG - ignored due to DEBUGLEVEL generic setting"", cmd_lineno); 
+                                        end
+                                        else
+                                        begin
+                                            DEBUG <= command[1] ; 
+                                            $display(""BFM:%0d: DEBUG %0d"", cmd_lineno, command[1]); 
+                                        end 
+                                    end
+                        C_HRESP :
+                                    begin
+                                        zerocycle = 0; 
+                                        command_length = 2; 
+                                        hresp_mode = command[1]; 
+                                        tmpstr[1] = NUL; 
+                                        if (hresp_mode == 2)
+                                        begin
+                                            if (hresp_occured)
+                                            begin
+                                                tmpstr[1:9] = {""OCCURRED"", NUL}; 
+                                            end
+                                            else
+                                            begin
+                                                $display(""BFM: HRESP Did Not Occur When Expected (ERROR)""); 
+                                                ERRORS = ERRORS + 1; 
+                                                $stop;
+                                            end 
+                                            hresp_mode = 0; 
+                                        end 
+                                        hresp_occured = 0; 
+                                        if (DEBUG >= 2) $display(""BFM:%0d:hresp %0d %0s"", cmd_lineno, hresp_mode, tmpstr); 
+                                    end
+                        C_STOP :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:stop %0d"", cmd_lineno, command[1]); 
+                                        $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(cmd_lineno, filemult)], get_line(cmd_lineno, filemult)); 
+                                        case (command[1])
+                                            0 :
+                                                        begin
+                                                            $display(""BFM Script Stop Command (NOTE)""); 
+                                                        end
+                                            1 :
+                                                        begin
+                                                            $display(""BFM Script Stop Command (WARNING)""); 
+\t\t\t    \t\t\t\t\t\t\t\t\t\t\t//$stop;
+                                                        end
+                                            3 :
+                                                        begin
+                                                            $display(""BFM Script Stop Command (FAILURE)""); 
+                                                            $stop;
+                                                        end
+                                            default :
+                                                        begin
+                                                            $display(""BFM Script Stop Command (ERROR)""); 
+                                                            $stop;
+                                                        end
+                                        endcase 
+                                    end
+                        C_QUIT :
+                                    begin
+                                        bfm_done = 1; 
+                                    end
+                        C_ECHO :
+                                    begin
+                                        zerocycle = 1; 
+                                        if (DEBUG>=1) $display(""BFM:%0d:echo at %0d ns"", cmd_lineno,$time); 
+                                        command_length = 2 + command[1]; 
+                                        $display(""BFM Parameter values are""); 
+                                        begin : xhdl_21
+                                            integer i;
+                                            for(i = 0; i <= command_length - 3; i = i + 1)
+                                            begin
+                                                $display("" Para %0d=0x%08x (%0d)"", i + 1, commandLV[2 + i], commandLV[2 + i]); 
+                                            end
+                                        end 
+                                    end
+                        C_FLUSH :
+                                    begin
+                                        command_length = 2; 
+                                        wait_counter = command[1]; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:flush %0d at %0d ns"", cmd_lineno, wait_counter,$time); 
+                                        do_flush = 1; 
+                                        do_case = 1; 
+                                    end
+                        C_SFAIL :
+                                    begin
+                                        zerocycle = 1; 
+                                        ERRORS = ERRORS + 1; 
+                                        if ( DEBUG >=2) $display(""BFM:%0d:setfail"", cmd_lineno); 
+                                        $display(""BFM: User Script detected ERROR (ERROR)""); 
+                                        $stop;
+                                    end
+                        C_SET :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 3; 
+                                        setvar = get_storeaddr(vectors[cptr + 1],stkptr); 
+                                        newvalue = command[2]; 
+                                        stack[setvar] = newvalue; 
+                                        if (DEBUG >= 2) $display(""BFM:%0d:set %0d= 0x%08x (%0d)"", cmd_lineno, setvar, newvalue, newvalue); 
+                                    end
+                        C_CALC :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = command[2] + 3; 
+                                        setvar = get_storeaddr(vectors[cptr + 1],stkptr); 
+                                        newvalue = calculate(command[4], command[3], command[5], DEBUG); 
+                                        i = 6; 
+                                        while (i < command_length)
+                                        begin
+                                            newvalue = calculate(command[i], newvalue, command[i + 1], DEBUG); 
+                                            i = i + 2; 
+                                        end 
+                                        stack[setvar] = newvalue; 
+                                        if (DEBUG >= 2) $display(""BFM:%0d:set %0d= 0x%08x (%0d)"", cmd_lineno, setvar, newvalue, newvalue); 
+                                    end
+                        C_LOGF :
+                                    begin
+                                        zerocycle = 1; 
+                                        if (logopen)
+                                        begin
+\t\t\t    \t\t\t\t\t\t   $fflush(flog);
+\t\t\t    \t\t\t\t\t\t   $fclose(flog);
+                                        end 
+                                        command_length = len_string(vectors[cptr+1]); 
+                                        logfile = extract_string(cptr); 
+                                        $display(""BFM:%0d:LOGFILE %0s"", cmd_lineno, logfile); 
+                                        flog = $fopen(logfile,""w""); 
+                                        logopen = 1;
+                                    end
+                        C_LOGS :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 2; 
+                                        $display(""BFM:%0d:LOGSTART %0d"", cmd_lineno, command[1]); 
+                                        if (logopen==0)
+                                        begin
+                                            $display(""Logfile not defined, ignoring command (ERROR)""); 
+                                        end
+                                        else
+                                        begin
+                                            log_ahb  = ((commandLV[1][0]) == 1\'b1); 
+                                            log_ext  = ((commandLV[1][1]) == 1\'b1); 
+                                            log_gpio = ((commandLV[1][2]) == 1\'b1); 
+                                            log_bfm  = ((commandLV[1][3]) == 1\'b1); 
+                                        end 
+                                    end
+                        C_LOGE :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 1; 
+                                        $display(""BFM:%0d:LOGSTOP"", cmd_lineno); 
+                                        log_ahb = 0; 
+                                        log_ext = 0; 
+                                        log_gpio = 0; 
+                                        log_bfm = 0; 
+                                    end
+                        C_VERS :
+                                    begin
+                                        zerocycle = 1; 
+                                        command_length = 1; 
+                                        $display(""BFM:%0d:VERSION"", cmd_lineno); 
+                                        $display(""  BFM Verilog Version %0s"", BFM_VERSION); 
+                                        $display(""  BFM Date %0s"", BFM_DATE); 
+                                        // The two lines below will be autoupdated when file is commited to SubVersion
+                                        $display(""  SVN Revision $Revision: 21608 $"");
+                                        $display(""  SVN Date $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $"");
+                                        $display(""  Compiler Version %0d"", bfmc_version); 
+                                        $display(""  Vectors Version %0d"", vectors_version); 
+                                        $display(""  No of Vectors %0d"", Nvectors); 
+                                        if (logopen != NUL)
+                                        begin
+                                          $fdisplay(flog,""%05d VR %0s %0s %0d %0d %0d"", $time,BFM_VERSION, BFM_DATE, bfmc_version, vectors_version, Nvectors); 
+                                        end 
+                                    end
+                        default :
+                                    begin
+                                        $display(""BFM: Instruction %0d Line Number %0d Command %0d"", cptr, cmd_lineno, cmd_cmd); 
+                                        $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(cmd_lineno, filemult)], get_line(cmd_lineno, filemult)); 
+                                        $display(""Instruction not yet implemented (ERROR)""); 
+                                        $stop;
+                                    end
+                    endcase 
+                end 
+                // zero cycle was set indicating instruction does not require a clock! 
+                if (zerocycle)
+                begin
+                    cmd_active = 0; 
+                    cptr = cptr + command_length; 
+                    command_length = 0; 
+                end 
+\t\t\tend
+\t\t\t\t
+            //----------------------------------------------------------------------------------------------------------
+            //----------------------------------------------------------------------------------------------------------
+            // Data Checker, needs to happen before multi cycle command processing
+            DATA_MATCH_AHB = 0; 
+            DATA_MATCH_EXT = 0; 
+            DATA_MATCH_IO = 0; 
+            if (READ_P1 == 1\'b1)
+            begin
+                EXP = RDATA_P1 & MDATA_P1; 
+                GOT = HRDATA & MDATA_P1; 
+                DATA_MATCH_AHB = (EXP === GOT); 
+            end 
+            if (EXTRD_P1 == 1\'b1)
+            begin
+                EXP = EIO_RDATA_P1 & EIO_MDATA_P1; 
+                GOT = EXT_DIN & EIO_MDATA_P1; 
+                DATA_MATCH_EXT = (EXP === GOT); 
+            end 
+            if (GPIORD_P0 == 1\'b1)
+            begin
+                EXP = EIO_RDATA_P0 & EIO_MDATA_P0; 
+                GOT = GP_IN & EIO_MDATA_P0; 
+                DATA_MATCH_IO = (EXP === GOT); 
+            end 
+
+            //----------------------------------------------------------------------------------------------------------
+            piped_activity = do_read | do_write | do_bwrite | do_bread | do_poll | do_idle | do_io 
+                                          | to_boolean(READ_P1 | READ_P0 | WRITE_P0 | WRITE_P1 | EXTRD_P0 | EXTRD_P1 | GPIORD_P0 ); 
+            if (do_case)
+            begin
+                case (cmd_cmdx4)
+                    C_FLUSH :
+                                begin
+                                    if (~piped_activity)
+                                    begin
+                                        //----------------------------------------------------------------------------------------------------------
+                                        //----------------------------------------------------------------------------------------------------------
+                                        // Command Processing for multi cycle commands etc
+                                        if (wait_counter <= 1)
+                                        begin
+                                            do_case = 0; 
+                                        end
+                                        else
+                                        begin
+                                            wait_counter = wait_counter - 1; 
+                                        end 
+                                    end 
+                                end
+                    C_WAIT :
+                                begin
+                                    if (wait_counter <= 1)
+                                    begin
+                                        do_case = 0; 
+                                    end
+                                    else
+                                    begin
+                                        wait_counter = wait_counter - 1; 
+                                    end 
+                                end
+                    C_WAITNS, C_WAITUS :
+                                begin
+                                    if ($time >= wait_time)
+                                    begin
+                                        do_case = 0; 
+                                    end 
+                                end
+                    C_IRQ, C_FIQ, C_INTREQ :
+                                begin
+                                    if (int_vector == 256)
+                                    begin
+                                        int_active = (INTERRUPT != ZERO256); 
+                                    end
+                                    else
+                                    begin
+                                        int_active = ((INTERRUPT[int_vector]) === 1\'b1); 
+                                    end 
+                                    if (int_active)
+                                    begin
+                                        if (DEBUG>=2) $display( ""BFM:Interrupt Wait Time %0d cycles"", instruct_cycles); 
+                                        do_case = 0; 
+                                    end 
+                                end
+                    C_EXTW :
+                                begin
+                                    EXTADDR_P0 <= command_address ; 
+                                    EXT_DOUT   <= command_data ; 
+                                    EXTWR_P0   <= 1\'b1 ; 
+                                    do_case = 0; 
+                                end
+                                \t
+                    C_EXTWM :
+                                begin
+                                    EXTADDR_P0 <= burst_address + burst_count ; 
+                                    EXT_DOUT   <= burst_data[burst_count] ; 
+                                    EXTWR_P0   <= 1\'b1 ; 
+                                    burst_count = burst_count + 1; 
+                                    if (burst_count >= burst_length)
+                                    begin
+                                        do_case = 0; 
+                                    end 
+                                end
+
+                    C_EXTR, C_EXTRC, C_EXTMSK :
+                                begin
+                                    EXTADDR_P0 <= command_address ; 
+                                    EIO_RDATA_P0 <= command_data ; 
+                                    EIO_MDATA_P0 <= command_mask ; 
+                                    EIO_LINENO_P0 <= cmd_lineno ; 
+                                    EIO_RDCHK_P0 <= 1\'b1 ; 
+                                    if (EXTRD_P1 == 1\'b1)
+                                    begin
+                                        // must wait until data on bus, cannot allow immediate write
+                                        do_case = 0; 
+                                    end 
+                                end
+                    C_EXTWT :
+                                begin
+                                    if (EXT_WAIT == 1\'b0 & wait_counter == 0)
+                                    begin
+                                        if (DEBUG>=2) $display( ""BFM:Exteral Wait Time %0d cycles"", instruct_cycles); 
+                                        do_case = 0; 
+                                    end 
+                                    if (wait_counter >= 1)
+                                    begin
+                                        wait_counter = wait_counter - 1; 
+                                    end 
+                                end
+                    C_IOCHK, C_IOMSK, C_IOTST, C_IORD :
+                                begin
+                                    EIO_RDCHK_P0 <= 1\'b1 ; 
+                                    EIO_RDATA_P0 <= command_data ; 
+                                    EIO_MDATA_P0 <= command_mask ; 
+                                    EIO_LINENO_P0 <= cmd_lineno ; 
+                                    do_case = 0; 
+                                end
+                    C_IOWAIT :
+                                begin
+                                    EIO_RDATA_P0 <= command_data ; 
+                                    EIO_MDATA_P0 <= command_mask ; 
+                                    EIO_LINENO_P0 <= cmd_lineno ; 
+                                    GPIORD_P0 <= 1\'b1 ; 
+                                    EIO_RDCHK_P0 <= 1\'b0 ; 
+                                    if (GPIORD_P0 == 1\'b1 & DATA_MATCH_IO)
+                                    begin
+                                        GPIORD_P0 <= 1\'b0 ; 
+                                        do_case = 0; 
+                                        if (DEBUG>=2) $display( ""BFM:GP IO Wait Time %0d cycles"", instruct_cycles); 
+                                    end 
+                                end
+                    C_MEMT , C_MEMT2 :
+                                begin
+                                    case (mt_state)
+                                        //memtest resource addr size align cycles
+                                        idle :  do_case = 0; 
+                                        init :\t    begin
+                                                        mt_base    = command[1] + command[2]; 
+                                                        mt_size    = command[3]; 
+                                                        mt_align   = command[4] % 65536; 
+                                                        mt_fill    = ((commandLV[4][16]) == 1\'b1); 
+                                                        mt_scan    = ((commandLV[4][17]) == 1\'b1); 
+                                                        mt_restart = ((commandLV[4][18]) == 1\'b1); 
+                                                        mt_cycles  = command[5]; 
+                                                        mt_seed    = command[6]; 
+                                                        if (~mt_restart)
+                                                           for (i=0;i<MAX_MEMTEST;i=i+1) mt_image[i] = 0; 
+                                                        mt_reads = 0; 
+                                                        mt_writes = 0; 
+                                                        mt_nops = 0; 
+                                                        mt_dual = 0; 
+                                                        mt_fillad = 0;
+                                                        if (cmd_cmdx4 == C_MEMT2)
+                                                        begin
+                                                            // if two banks double size
+                                                            mt_base = command[1]; 
+                                                            mt_base2 = command[2] - mt_size; 
+                                                            mt_size = 2 * mt_size; 
+                                                            mt_dual = 1; 
+                                                        end 
+                                                        if (cmd_cmdx4 == C_MEMT)
+                                                        begin
+                                                            $display(""BFM:%0d: memtest Started at %0d ns"", cmd_lineno, $time); 
+                                                            $display(""BFM:  Address %08x Size %0d Cycles %5d"", mt_base, mt_size, mt_cycles); 
+                                                        end
+                                                        else
+                                                        begin
+                                                            $display(""BFM:%0d: dual memtest Started at %0d ns"", cmd_lineno, $time); 
+                                                            $display(""BFM:  Address %08x %08x  Size %0d Cycles %5d"", mt_base,mt_base2 + mt_size/2, mt_size/2, mt_cycles); 
+                                                        end 
+                                                        case (mt_align)
+                                                            0 :\t  begin end
+                                                            1 :\t  $display(""BFM: Transfers are APB Byte aligned""); 
+                                                            2 :\t  $display(""BFM: Transfers are APB Half Word aligned""); 
+                                                            3 :\t  $display(""BFM: Transfers are APB Word aligned""); 
+                                                            4 :\t  $display(""BFM: Byte Writes Suppressed""); 
+                                                            default :   $display(""Illegal Align on memtest (FAILURE)""); 
+                                                        endcase 
+                                                        if (mt_restart)
+                                                        begin
+                                                            $display(""BFM: memtest restarted""); 
+                                                        end 
+                                                        if (mt_fill)
+                                                        begin
+                                                            $display(""BFM: Memtest Filling Memory""); 
+                                                            mt_state = fill; 
+                                                        end
+                                                        else if (mt_cycles > 0)
+                                                        begin
+                                                            $display(""BFM: Memtest Random Read Writes""); 
+                                                            mt_state = active; 
+                                                        end
+                                                        else if (mt_scan)
+                                                        begin
+                                                            $display(""BFM: Memtest Verifying Memory Content""); 
+                                                            mt_state = scan; 
+                                                        end
+                                                        else
+                                                        begin
+                                                            mt_state = done; 
+                                                        end 
+                                                    end
+                                        active, fill, scan :
+                                                    begin
+                                                        if (~(do_write | do_read))
+                                                        begin
+                                                            case (mt_state)
+                                                                active :
+                                                                            begin
+                                                                                mt_seed = random(mt_seed); 
+                                                                                mt_ad = mask_randomS(mt_seed, mt_size); 
+                                                                                mt_seed = random(mt_seed); 
+                                                                                mt_op = mask_randomS(mt_seed, 8); 
+                                                                            end
+                                                                fill :
+                                                                            begin
+                                                                                mt_ad = mt_fillad; 
+                                                                                mt_op = 6; 
+                                                                            end
+                                                                scan :
+                                                                            begin
+                                                                                mt_ad = mt_fillad; 
+                                                                                mt_op = 2; 
+                                                                            end
+                                                                default :
+                                                                            begin
+                                                                            end
+                                                            endcase 
+                                                            case (mt_align)
+                                                                0 :
+                                                                            begin
+                                                                            end
+                                                                1 :
+                                                                            begin
+                                                                                // byte wide APB
+                                                                                mt_ad = 4 * (mt_ad / 4); 
+                                                                                case (mt_op)
+                                                                                    // full AHB operation
+                                                                                    0, 4 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op; // all to op 0 and 4
+                                                                                                end
+                                                                                    1, 5 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op - 1; 
+                                                                                                end
+                                                                                    2, 6 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op - 2; 
+                                                                                                end
+                                                                                    default :
+                                                                                                begin
+                                                                                                end
+                                                                                endcase 
+                                                                            end
+                                                                2 :
+                                                                            begin
+                                                                                // half wide APB
+                                                                                mt_ad = 4 * (mt_ad / 4); 
+                                                                                case (mt_op)
+                                                                                    0, 4 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op + 1; // all to op 1 and 5
+                                                                                                end
+                                                                                    1, 5 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op; 
+                                                                                                end
+                                                                                    2, 6 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op - 1; 
+                                                                                                end
+                                                                                    default :
+                                                                                                begin
+                                                                                                end
+                                                                                endcase 
+                                                                            end
+                                                                3 :
+                                                                            begin
+                                                                                // word wide APB
+                                                                                mt_ad = 4 * (mt_ad / 4); 
+                                                                                case (mt_op)
+                                                                                    0, 4 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op + 2; // all to op 2 and 6
+                                                                                                end
+                                                                                    1, 5 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op + 1; 
+                                                                                                end
+                                                                                    2, 6 :
+                                                                                                begin
+                                                                                                    mt_op = mt_op; 
+                                                                                                end
+                                                                                    default :
+                                                                                                begin
+                                                                                                end
+                                                                                endcase 
+                                                                            end
+                                                                4 :
+                                                                            begin
+                                                                                // Dont allow Byte writes
+                                                                                case (mt_op)
+                                                                                    4 :
+                                                                                                begin
+                                                                                                    mt_ad = 2 * (mt_ad / 2); 
+                                                                                                    mt_op = 5; // stop a byte write, make a half write
+                                                                                                end
+                                                                                    default :
+                                                                                                begin
+                                                                                                end
+                                                                                endcase 
+                                                                            end
+                                                                default :
+                                                                            begin
+                                                                            end
+                                                            endcase 
+                                                            if (mt_op >= 0 & mt_op <= 2)
+                                                            begin
+                                                                // do read
+                                                                case (mt_op)
+                                                                    // see if valid data
+                                                                    0 :
+                                                                                begin
+                                                                                    command_size = 3\'b000; 
+                                                                                    mt_ad = mt_ad; 
+                                                                                    mt_readok = (mt_image[mt_ad + 0] >= 256); 
+                                                                                end
+                                                                    1 :
+                                                                                begin
+                                                                                    command_size = 3\'b001; 
+                                                                                    mt_ad = 2 * (mt_ad / 2); 
+                                                                                    mt_readok = ((mt_image[mt_ad + 0] >= 256) & (mt_image[mt_ad + 1] >= 256)); 
+                                                                                end
+                                                                    2 :
+                                                                                begin
+                                                                                    command_size = 3\'b010; 
+                                                                                    mt_ad = 4 * (mt_ad / 4); 
+                                                                                    mt_readok = ((mt_image[mt_ad + 0] >= 256) & (mt_image[mt_ad + 1] >= 256) & (mt_image[mt_ad + 2] >= 256) & (mt_image[mt_ad + 3] >= 256)); 
+                                                                                end
+                                                                    default :
+                                                                                begin
+                                                                                end
+                                                                endcase 
+                                                                // wait until previous cycle clears
+                                                                if (mt_readok)
+                                                                begin
+                                                                    // do a read
+                                                                    do_read = 1; 
+                                                                    mt_reads = mt_reads + 1; 
+                                                                    if (mt_dual == 1 & mt_ad >= mt_size / 2)
+                                                                    begin
+                                                                        command_address = mt_base2 + mt_ad; 
+                                                                    end
+                                                                    else
+                                                                    begin
+                                                                        command_address = mt_base + mt_ad; 
+                                                                    end 
+                                                                    case (mt_op)
+                                                                        0 :\t        begin
+                                                                                        command_data = {ZEROLV[31:8], mt_image[mt_ad + 0][7:0]}; 
+                                                                                    end
+                                                                        1 :\t        begin
+                                                                                        command_data = {ZEROLV[31:16], mt_image[mt_ad + 1][7:0], mt_image[mt_ad + 0][7:0]}; 
+                                                                                    end
+                                                                        2 :\t        begin
+                                                                                        command_data = {mt_image[mt_ad + 3][7:0], mt_image[mt_ad + 2][7:0], 
+                                                                                                        mt_image[mt_ad + 1][7:0], mt_image[mt_ad + 0][7:0]}; 
+                                                                                    end
+                                                                        default :   begin
+                                                                                        command_data = ZEROLV[31:0]; 
+                                                                                    end
+                                                                    endcase 
+                                                                    command_mask = {32{1\'b1}}; 
+                                                                end
+                                                                else
+                                                                begin
+                                                                    //$display(""Memtest read converted to write"");
+                                                                    mt_op = mt_op + 4; // force a write if not written
+                                                                    // if a byte read converted to byte write and byte writes not allowed make a half word write!
+                                                                    if (mt_op == 4 & mt_align == 4)
+                                                                    begin
+                                                                        mt_op = 5; 
+                                                                    end 
+                                                                'b'end 
+                                                            end 
+                                                            if (mt_op >= 4 & mt_op <= 6)
+                                                            begin
+                                                                // do write
+                                                                do_write = 1; 
+                                                                mt_writes = mt_writes + 1; 
+                                                                mt_seed = random(mt_seed); 
+                                                                command_data = mt_seed; 
+                                                                case (mt_op)
+                                                                    // update image
+                                                                    4 :
+                                                                                begin
+                                                                                    command_size = 3\'b000; 
+                                                                                    mt_ad = mt_ad; 
+                                                                                    mt_image[mt_ad + 0] = 256 + command_data[7:0]; 
+                                                                                end
+                                                                    5 :
+                                                                                begin
+                                                                                    command_size = 3\'b001; 
+                                                                                    mt_ad = 2 * (mt_ad / 2); 
+                                                                                    mt_image[mt_ad + 0] = 256 + command_data[7:0]; 
+                                                                                    mt_image[mt_ad + 1] = 256 + command_data[15:8]; 
+                                                                                end
+                                                                    6 :
+                                                                                begin
+                                                                                    command_size = 3\'b010; 
+                                                                                    mt_ad = 4 * (mt_ad / 4); 
+                                                                                    mt_image[mt_ad + 0] = 256 + command_data[7:0]; 
+                                                                                    mt_image[mt_ad + 1] = 256 + command_data[15:8]; 
+                                                                                    mt_image[mt_ad + 2] = 256 + command_data[23:16]; 
+                                                                                    mt_image[mt_ad + 3] = 256 + command_data[31:24]; 
+                                                                                end
+                                                                    default :
+                                                                                begin
+                                                                                end
+                                                                endcase 
+                                                                if (mt_dual == 1 & mt_ad >= mt_size / 2)
+                                                                begin
+                                                                    command_address = mt_base2 + mt_ad; 
+                                                                end
+                                                                else
+                                                                begin
+                                                                    command_address = mt_base + mt_ad; 
+                                                                end 
+                                                            end 
+                                                            if (mt_op == 3 | mt_op == 7)
+                                                            begin
+                                                                // insert one wait cycle
+                                                                mt_nops = mt_nops + 1; 
+                                                            end 
+                                                            mt_fillad = mt_fillad + 4; 
+                                                            case (mt_state)
+                                                                active :
+                                                                            begin
+                                                                                if (mt_cycles > 0)
+                                                                                begin
+                                                                                    mt_cycles = mt_cycles - 1; 
+                                                                                end
+                                                                                else if (mt_scan)
+                                                                                begin
+                                                                                    mt_fillad = 0; 
+                                                                                    mt_state = scan; 
+                                                                                    $display(""BFM: Memtest Verifying Memory Content""); 
+                                                                                end
+                                                                                else
+                                                                                begin
+                                                                                    mt_state = done; 
+                                                                                end 
+                                                                            end
+                                                                fill :
+                                                                            begin
+                                                                                if (mt_fillad >= mt_size)
+                                                                                begin
+                                                                                    if (mt_cycles == 0)
+                                                                                    begin
+                                                                                        if (mt_scan)
+                                                                                        begin
+                                                                                            mt_fillad = 0; 
+                                                                                            mt_state = scan; 
+                                                                                            $display(""BFM: Memtest Verifying Memory Content""); 
+                                                                                        end
+                                                                                        else
+                                                                                        begin
+                                                                                            mt_state = done; 
+                                                                                        end 
+                                                                                    end
+                                                                                    else
+                                                                                    begin
+                                                                                        mt_state = active; 
+                                                                                        $display(""BFM: Memtest Random Read Writes""); 
+                                                                                    end 
+                                                                                end 
+                                                                            end
+                                                                scan :
+                                                                            begin
+                                                                                if (mt_fillad >= mt_size)
+                                                                                begin
+                                                                                    mt_state = done; 
+                                                                                end 
+                                                                            end
+                                                                default :
+                                                                            begin
+                                                                            end
+                                                            endcase 
+                                                            timer = command_timeout; // also reset the timer as we completed a cycle  
+                                                        end 
+                                                    end
+                                        done :
+                                                    begin
+                                                        if (~piped_activity)
+                                                        begin
+                                                            mt_state = idle; 
+                                                            $display(""BFM: bfmtest complete  Writes %0d  Reads %0d  Nops %0d"", mt_writes, mt_reads, mt_nops); 
+                                                        end 
+                                                    end
+                                    endcase 
+                                end
+                    default :
+                                begin
+                                end
+                endcase 
+            end 
+            //----------------------------------------------------------------------------------------------------------
+            //----------------------------------------------------------------------------------------------------------
+            // AMBA Bus Cycles
+            //- this inserts AHB BUSY cycles
+            if (count_xrate == 0)
+            begin
+                insert_busy = 0; 
+                count_xrate = su_xrate; 
+            end
+            else
+            begin
+                count_xrate = count_xrate - 1; 
+                insert_busy = 1; 
+            end 
+            if (HREADY == 1\'b1)
+            begin
+                HTRANS_P0 <= 2\'b00 ; // IDLE
+                HWRITE_P0 <= 1\'b0 ; 
+                // AMBA Cycles
+                WRITE_P0 <= 1\'b0 ; 
+                READ_P0 <= 1\'b0 ; 
+                POLL_P0 <= 1\'b0 ; 
+                //---------
+                if (WRITE_P0 == 1\'b1 | READ_P0 == 1\'b1)
+                begin
+                    RDCHK_P0 <= 1\'b0 ; 
+                end 
+                if (do_write & HREADY == 1\'b1)
+                begin
+                    HADDR_P0 <= command_address ; 
+                    HWRITE_P0 <= 1\'b1 ; 
+                    HBURST_P0 <= ahb_burst ; 
+                    HTRANS_P0 <= 2\'b10 ; 
+                    HMASTLOCK_P0 <= ahb_lock ; 
+                    HPROT_P0 <= ahb_prot ; 
+                    HSIZE_P0 <= command_size ; 
+                    WDATA_P0 <= align_data(command_size, command_address[1:0], command_data, su_align) ; 
+                    WRITE_P0 <= 1\'b1 ; 
+                    LINENO_P0 <= cmd_lineno ; 
+                    do_write = 0; 
+                end 
+                if (do_read & HREADY == 1\'b1)
+                begin
+                    HADDR_P0 <= command_address ; 
+                    HWRITE_P0 <= 1\'b0 ; 
+                    HBURST_P0 <= ahb_burst ; 
+                    HTRANS_P0 <= 2\'b10 ; 
+                    HMASTLOCK_P0 <= ahb_lock ; 
+                    HPROT_P0 <= ahb_prot ; 
+                    HSIZE_P0 <= command_size ; \t\t\t\t\t\t\t\t\t\t\t 
+                    RDATA_P0 <= align_data(command_size, command_address[1:0], command_data, su_align) ; 
+                    MDATA_P0 <= align_mask(command_size, command_address[1:0], command_mask, su_align) ; 
+                    LINENO_P0 <= cmd_lineno ; 
+                    READ_P0 <= 1\'b1 ; 
+                    RDCHK_P0 <= 1\'b1 ; 
+                    do_read = 0; 
+                end 
+                if (do_idle & HREADY == 1\'b1)
+                begin
+                    HADDR_P0 <= command_address ; 
+                    HWRITE_P0 <= ahbc_hwrite ; 
+                    HBURST_P0 <= ahbc_burst ; 
+                    HTRANS_P0 <= ahbc_htrans ; 
+                    HMASTLOCK_P0 <= ahbc_lock ; 
+                    HPROT_P0 <= ahbc_prot ; 
+                    HSIZE_P0 <= command_size ; 
+                    WDATA_P0 <= align_data(command_size, command_address[1:0], command_data, su_align) ; 
+                    WRITE_P0 <= 1\'b1 ; // use write pipe line to control timing
+                    LINENO_P0 <= cmd_lineno ; 
+                    do_idle = 0; 
+                end 
+                if (do_poll & HREADY == 1\'b1)
+                begin
+                    //$display(""POLL %08x %08x"",RDATA_P0),MDATA_P0));
+                    HADDR_P0 <= command_address ; 
+                    HWRITE_P0 <= 1\'b0 ; 
+                    HBURST_P0 <= ahb_burst ; 
+                    HMASTLOCK_P0 <= ahb_lock ; 
+                    HPROT_P0 <= ahb_prot ; 
+                    HSIZE_P0 <= command_size ; 
+                    RDATA_P0 <= align_data(command_size, command_address[1:0], command_data, su_align) ; 
+                    MDATA_P0 <= align_mask(command_size, command_address[1:0], command_mask, su_align) ; 
+                    LINENO_P0 <= cmd_lineno ; 
+                    if (READ_P0 == 1\'b1 | READ_P1 == 1\'b1)
+                    begin
+                        HTRANS_P0 <= 2\'b00 ; // No cycle, waiting to check data
+                    end
+                    else
+                    begin
+                        HTRANS_P0 <= 2\'b10 ; 
+                        READ_P0 <= 1\'b1 ; 
+                        POLL_P0 <= 1\'b1 ; 
+                    end 
+                    if (POLL_P1 == 1\'b1 & DATA_MATCH_AHB)
+                    begin
+                        do_poll = 0; 
+                    end 
+                end 
+                if (do_bwrite & HREADY == 1\'b1)
+                begin
+                    HADDR_P0 <= command_address ; 
+                    HWRITE_P0 <= 1\'b1 ; 
+                    HBURST_P0 <= ahb_burst ; 
+                    HMASTLOCK_P0 <= ahb_lock ; 
+                    HPROT_P0 <= ahb_prot ; 
+                    HSIZE_P0 <= command_size ; 
+                    LINENO_P0 <= cmd_lineno ; 
+                    if (insert_busy)
+                    begin
+                        HTRANS_P0 <= 2\'b01 ; 
+                    end
+                    else
+                    begin
+                        WDATA_P0 <= align_data(command_size, command_address[1:0], to_slv32(burst_data[burst_count]), su_align) ; 
+                        WRITE_P0 <= 1\'b1 ; 
+                        if (burst_count == 0 | cmd_size == 3 | bound1k(su_noburst, command_address) )
+                        begin
+                            HTRANS_P0 <= 2\'b10 ; 
+                        end
+                        else
+                        begin
+                            HTRANS_P0 <= 2\'b11 ; 
+                        end 
+                        command_address = command_address + burst_addrinc; 
+                        burst_count = burst_count + 1; 
+                        if (burst_count == burst_length)
+                        begin
+                            do_bwrite = 0; 
+                        end 
+                    end 
+                end 
+                if (do_bread & HREADY == 1\'b1)
+                begin
+                    HADDR_P0 <= command_address ; 
+                    HWRITE_P0 <= 1\'b0 ; 
+                    HBURST_P0 <= ahb_burst ; 
+                    HMASTLOCK_P0 <= ahb_lock ; 
+                    HPROT_P0 <= ahb_prot ; 
+                    HSIZE_P0 <= command_size ; 
+                    LINENO_P0 <= cmd_lineno ; 
+                    if (insert_busy)
+                    begin
+                        HTRANS_P0 <= 2\'b01 ; 
+                    end
+                    else
+                    begin
+                        RDATA_P0 <= align_data(command_size, command_address[1:0], to_slv32(burst_data[burst_count]), su_align) ; 
+                        MDATA_P0 <= align_mask(command_size, command_address[1:0], command_mask, su_align) ; 
+                        READ_P0 <= 1\'b1 ; 
+                        RDCHK_P0 <= 1\'b1 ; 
+                        if (burst_count == 0 | cmd_size == 3 | bound1k(su_noburst, command_address) )
+                        begin
+                            HTRANS_P0 <= 2\'b10 ; 
+                        end
+                        else
+                        begin
+                            HTRANS_P0 <= 2\'b11 ; 
+                        end 
+                        command_address = command_address + burst_addrinc; 
+                        burst_count = burst_count + 1; 
+                        if (burst_count == burst_length)
+                        begin
+                            do_bread = 0; 
+                        end 
+                    end 
+                end 
+            end 
+            //----------------------------------------------------------------------------------------------------------
+            if (HREADY == 1\'b1)
+            begin
+                WRITE_P1 <= WRITE_P0 ; 
+                READ_P1 <= READ_P0 ; 
+                POLL_P1 <= POLL_P0 ; 
+                RDCHK_P1 <= RDCHK_P0 ; 
+                RDATA_P1 <= RDATA_P0 ; 
+                MDATA_P1 <= MDATA_P0 ; 
+                LINENO_P1 <= LINENO_P0 ; 
+                HADDR_P1 <= HADDR_P0 ; 
+                HSIZE_P1 <= HSIZE_P0 ; 
+            end 
+            \t
+            EXTRD_P1 <= EXTRD_P0 ; 
+            EXTADDR_P1 <= EXTADDR_P0 ; 
+            //seperate data pipe to AHB!
+            EIO_RDCHK_P1 <= EIO_RDCHK_P0 ; 
+            EIO_RDATA_P1 <= EIO_RDATA_P0 ; 
+            EIO_MDATA_P1 <= EIO_MDATA_P0 ; 
+            EIO_LINENO_P1 <= EIO_LINENO_P0 ; 
+
+
+            if (HREADY == 1\'b1)
+            begin
+                //----------------------------------------------------------------------------------------------------------
+                //----------------------------------------------------------------------------------------------------------
+                // Write Data Pipeline and logger
+                if (WRITE_P0 == 1\'b1)
+                begin
+                    WDATA_P1 <= WDATA_P0 ; 
+                end
+                else
+                begin
+                    WDATA_P1 <= {32{1\'b0}} ; 
+                end 
+                if (WRITE_P1 == 1\'b1 & DEBUG >= 3)
+                begin
+                    $display(""BFM: Data Write %08x %08x"", HADDR_P1, WDATA_P1); 
+                end 
+                if (log_ahb & WRITE_P1 == 1\'b1)
+                begin
+                    $fdisplay(flog,""%05d AW %c %08x %08x"", $time,to_char(HSIZE_P1), HADDR_P1, WDATA_P1); 
+                end 
+            end 
+            if (GPIOWR_P0 == 1\'b1 & log_gpio)
+            begin
+                $fdisplay(flog,""%05d GW   %08x "", $time,GPOUT_P0); 
+            end 
+            if (EXTWR_P0 == 1\'b1 & log_ext)
+            begin
+                $fdisplay(flog,""%05d EW   %08x %08x"", $time,EXTADDR_P0, EXT_DOUT); 
+            end 
+            if (HREADY == 1\'b1)
+            begin
+                if (READ_P1 == 1\'b1)
+                begin
+                    if (DEBUG >= 3)
+                    begin
+                        //----------------------------------------------------------------------------------------------------------
+                        //----------------------------------------------------------------------------------------------------------
+                        // Read Data Pipeline, Checker and logger
+                        // AHB Read Checks
+                        if (MDATA_P1 == ZEROLV)
+                        begin
+                            $display(""BFM: Data Read %08x %08x"", HADDR_P1, HRDATA); 
+                        end
+                        else
+                        begin
+                            $display(""BFM: Data Read %08x %08x MASK:%08x"", HADDR_P1, HRDATA, MDATA_P1); 
+                        end 
+                    end 
+                    if (log_ahb)
+                    begin
+                         $fdisplay(flog,""%05d AR %c %08x %08x"", $time,to_char(HSIZE_P1), HADDR_P1, HRDATA); 
+                    end 
+                    if (storeaddr >= 0)
+                    begin
+                        stack[storeaddr] = to_int(align_read(HSIZE_P1, HADDR_P1[1:0], HRDATA,su_align)); 
+                    end 
+                    if (RDCHK_P1 == 1\'b1 & ~DATA_MATCH_AHB)
+                    begin
+                        ERRORS = ERRORS + 1; 
+                        $display(""ERROR: AHB Data Read Comparison failed Addr:%08x  Got:%08x  EXP:%08x  (MASK:%08x)"", HADDR_P1, HRDATA, RDATA_P1, MDATA_P1); 
+                        $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(LINENO_P1, filemult)], get_line(LINENO_P1, filemult)); 
+                        $display(""BFM Data Compare Error (ERROR)""); 
+                        $stop;
+                        if (log_ahb)
+                        begin
+                            $fdisplay(flog, ""%05d ERROR  Addr:%08x  Got:%08x  EXP:%08x  (MASK:%08x)"", $time,HADDR_P1, HRDATA, RDATA_P1, MDATA_P1); 
+                        end 
+                    end 
+                end 
+            end 
+
+                
+            if (GPIORD_P0 == 1\'b1)
+            begin
+                if (DEBUG >= 3)
+                begin
+                    // IO Port Checker
+                    if (EIO_MDATA_P0 == ZEROLV)
+                    begin
+                        $display(""BFM: GP IO Data Read %08x"", GP_IN); 
+                    end
+                    else
+                    begin
+                        $display(""BFM: GP IO Data Read %08x  MASK:%08x"", GP_IN, EIO_MDATA_P0); 
+                    end 
+                end 
+                if (log_gpio)
+                begin
+                    $fdisplay(flog,""%05d GR   %08x "",$time, EIO_RDATA_P0); 
+                end 
+                if (storeaddr >= 0)
+                begin
+                    stack[storeaddr] = GP_IN; 
+                end 
+                if (EIO_RDCHK_P0 == 1\'b1 & ~DATA_MATCH_IO)
+                begin
+                    ERRORS = ERRORS + 1; 
+                    $display(""GPIO input not as expected  Got:%08x  EXP:%08x  (MASK:%08x)"", GP_IN, EIO_RDATA_P0, EIO_MDATA_P0); 
+                    $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(EIO_LINENO_P0, filemult)], get_line(EIO_LINENO_P0, filemult)); 
+                    $display(""BFM GPIO Compare Error (ERROR)""); 
+                    $stop;
+                    if (log_gpio)
+                    begin
+                        $fdisplay(flog,""ERROR  Got:%08x  EXP:%08x  (MASK:%08x)"", GP_IN, EIO_RDATA_P0, EIO_MDATA_P0); 
+                    end 
+                end 
+            end 
+                
+            if (EXTRD_P1 == 1\'b1)
+            begin
+                if (DEBUG >= 3)
+                begin
+                    // Extention Read Checks
+                    if (EIO_MDATA_P1 == ZEROLV)
+                    begin
+                        $display(""BFM: Extention Data Read %08x %08x"", EXTADDR_P1, EXT_DIN); 
+                    end
+                    else
+                    begin
+                        $display(""BFM: Extention Data Read %08x %08x  MASK:%08x"", EXTADDR_P1, EXT_DIN, EIO_MDATA_P1); 
+                    end 
+                end 
+                if (log_ext)
+                begin
+                    $fdisplay(flog,""%05d ER   %08x %08x"", $time,EXTADDR_P1, EIO_RDATA_P1); 
+                end 
+                if (storeaddr >= 0)
+                begin
+                    stack[storeaddr] = to_int(EXT_DIN); 
+                end 
+                if (EIO_RDCHK_P1 == 1\'b1 & ~DATA_MATCH_EXT)
+                begin
+                    ERRORS = ERRORS + 1; 
+                    $display(""ERROR: Extention Data Read Comparison FAILED  Got:%08x  EXP:%08x  (MASK:%08x)"", EXT_DIN, EIO_RDATA_P1, EIO_MDATA_P1); 
+                    $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(EIO_LINENO_P1, filemult)], get_line(EIO_LINENO_P1, filemult)); 
+                    $display(""BFM Extention Data Compare Error (ERROR)""); 
+                    $stop;
+                    if (log_ext)
+                    begin
+                        $fdisplay(flog,""ERROR  Got:%08x  EXP:%08x  (MASK:%08x)"", EXT_DIN, EIO_RDATA_P1, EIO_MDATA_P1); 
+                    end 
+                end 
+            end 
+            //----------------------------------------------------------------------------------------------------------
+            // routines that require operation after AHB cycle completes
+
+            ahb_activity = do_read | do_write | do_bwrite | do_bread | do_poll | do_idle | to_boolean(READ_P0 | WRITE_P0 | EXTRD_P0 | GPIORD_P0) | (to_boolean((READ_P1 | WRITE_P1) & ~HREADY)); 
+            if (do_case)
+            begin
+                case (cmd_cmdx4)
+                    C_CHKT :
+                                begin
+                                    if (~ahb_activity)
+                                    begin
+                                        if (DEBUG >= 2) $display( ""BFM:%0d:checktime was %0d cycles "", cmd_lineno, instruct_cycles); 
+                                        if (instruct_cycles < command[1] | instruct_cycles > command[2])
+                                        begin
+                                            $display(""BFM: ERROR checktime %0d %0d Actual %0d"", command[1], command[2], instruct_cycles); 
+                                            $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(LINENO_P1, filemult)], get_line(LINENO_P1, filemult)); 
+                                            $display(""BFM checktime failure (ERROR)""); 
+                                            ERRORS = ERRORS + 1; 
+                                            $stop;
+                                        end 
+                                        do_case = 0; 
+                                        var_licycles = instruct_cycles; 
+                                    end 
+                                end
+                    C_CKTIM :
+                                begin
+                                    if (~ahb_activity)
+                                    begin
+                                        instructions_timer = instructions_timer - 1; // need to allow for check instruction
+                                        if (DEBUG >= 2) $display( ""BFM:%0d:checktimer was %0d cycles "", cmd_lineno, instructions_timer); 
+                                        if (instructions_timer < command[1] | instructions_timer > command[2])
+                                        begin
+                                            $display(""BFM: ERROR checktimer %0d %0d Actual %0d"", command[1], command[2], instructions_timer); 
+                                            $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(LINENO_P1, filemult)], get_line(LINENO_P1, filemult)); 
+                                            $display(""BFM checktimer failure (ERROR)""); 
+                                            ERRORS = ERRORS + 1; 
+                                            $stop;
+                                        end 
+                                        do_case = 0; 
+                                        var_ltimer = instructions_timer; 
+                                    end 
+                                end
+                    default :
+                                begin
+                                end
+                endcase 
+            end 
+            //----------------------------------------------------------------------------------------------------------
+
+            if (bfm_run)
+            begin
+                //----------------------------------------------------------------------------------------------------------
+                //----------------------------------------------------------------------------------------------------------
+                // Watchdog timer
+                if (timer > 0)
+                begin
+                    timer = timer - 1; 
+                end
+                else
+                begin
+                    timer = command_timeout; 
+                    $display(""BFM Command Timeout Occured"");
+                    $display(""       Stimulus file %0s  Line No %0d"", filenames[get_file(LINENO_P1, filemult)], get_line(LINENO_P1, filemult)); 
+                    if (~bfm_done) $display(""BFM Command timeout occured (ERROR)""); 
+                    if ( bfm_done) $display(""BFM Completed and timeout occured (ERROR)"");
+                    $stop; 
+                end 
+            end
+            else
+            begin
+                timer = command_timeout; 
+            end 
+            if (ERRORS > 0)
+            begin
+                FAILED_P0 <= 1\'b1 ; 
+            end 
+            if (do_case | do_read | do_write | do_bwrite | do_bread | do_poll | do_idle | ((do_flush | su_flush) & piped_activity))
+            begin
+                cmd_active = 1; 
+            end
+            else
+            begin
+                do_flush = 0; 
+                // See if command done, if so allow next command to be started
+                if (~bfm_done)
+                begin
+                    cmd_active = 0; 
+                end 
+                cptr = cptr + command_length; 
+                command_length = 0; 
+                if (OPMODE > 0)
+                begin
+                    if (bfm_single | bfm_done)
+                    begin
+                        bfm_run = 0; 
+                        cmd_active = 0; 
+                    end 
+                end 
+            end 
+            if (FINISHED_P0 == 1\'b0 & OPMODE == 0 & bfm_done & ~piped_activity)
+            begin
+                $display(""###########################################################""); 
+                $display("" ""); 
+                //----------------------------------------------------------------------------------------------------------
+                //----------------------------------------------------------------------------------------------------------
+                if (ERRORS == 0)
+                begin
+                    $display(""BFM Simulation Complete - %0d Instructions - NO ERRORS"", instuct_count); 
+                end
+                else
+                begin
+                    $display(""BFM Simulation Complete - %0d Instructions - %0d ERRORS OCCURED"", instuct_count, ERRORS); 
+                end 
+                $display("" ""); 
+                $display(""###########################################################""); 
+                $display("" ""); 
+                FINISHED_P0 <= 1\'b1 ; 
+                cmd_active = 1; 
+                bfm_run = 0; 
+                if (logopen)
+                begin
+                    // close log file
+                   $fflush(flog); 
+                   $fclose(flog); 
+                end 
+                if ( su_endsim==1 ) $stop;
+                if ( su_endsim==2 ) $finish;
+            end 
+            CON_BUSY  <= (bfm_run | piped_activity) ; 
+            INSTR_OUT <= to_slv32(cptr) ; 
+        end 
+    end 
+    \t
+    assign #TPD GP_OUT   = GPOUT_P0 ;
+    assign #TPD EXT_WR   = EXTWR_P0 ;
+    assign #TPD EXT_RD   = EXTRD_P0 ;
+    assign #TPD EXT_ADDR = EXTADDR_P0 ;
+    assign #TPD EXT_DATA = (EXTWR_P0 == 1\'b1) ? EXT_DOUT : {32{1\'bz}} ;
+    assign      EXT_DIN  = EXT_DATA ;
+
+    always @(HADDR_P0)
+    begin
+        begin : xhdl_29
+            integer i;
+            for(i = 0; i <= 15; i = i + 1)
+            begin
+                HSEL_P0[i] <= (HADDR_P0[31:28] == i) ; 
+            end
+        end 
+    end 
+    \t
+    assign HCLK      = (DRIVEX_CLK) ? 1\'bx : (SYSCLK | HCLK_STOP) ;
+    assign PCLK      = (DRIVEX_CLK) ? 1\'bx : (SYSCLK | HCLK_STOP) ;
+    assign #TPD HRESETN   = (DRIVEX_RST) ? 1\'bx : HRESETN_P0 ;
+    assign #TPD HADDR     = (DRIVEX_ADD) ? {32{1\'bx}} : HADDR_P0 ;
+    assign #TPD HWDATA    = (DRIVEX_DAT) ? {32{1\'bx}} : WDATA_P1 ;
+    assign #TPD HBURST    = (DRIVEX_ADD) ? {3{1\'bx}} : HBURST_P0 ;
+    assign #TPD HMASTLOCK = (DRIVEX_ADD) ? 1\'bx : HMASTLOCK_P0 ;
+    assign #TPD HPROT     = (DRIVEX_ADD) ? {4{1\'bx}} : HPROT_P0 ;
+    assign #TPD HSIZE     = (DRIVEX_ADD) ? {3{1\'bx}} : HSIZE_P0 ;
+    assign #TPD HTRANS    = (DRIVEX_ADD) ? {2{1\'bx}} : HTRANS_P0 ;
+    assign #TPD HWRITE    = (DRIVEX_ADD) ? 1\'bx : HWRITE_P0 ;
+    assign #TPD HSEL      = (DRIVEX_ADD) ? {16{1\'bx}} : HSEL_P0 ;
+
+    assign #TPD CON_DATA = (CON_RDP1 == 1\'b1) ? CON_DOUT : {32{1\'bz}} ;
+    assign      CON_DIN  = CON_DATA ;
+    assign #TPD FINISHED = FINISHED_P0 ;
+    assign #TPD FAILED   = FAILED_P0 ;
+
+
+
+endmodule
+
+
+
+"
+"// Actel Corporation Proprietary and Confidential
+// Copyright 2008 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+// Revision Information:
+// SVN Revision Information:
+// SVN $Revision: 11864 $
+// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
+`timescale 1ns/100ps
+module
+BFM_APBSLAVE
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+PWRITE
+,
+PSEL
+,
+PADDR
+,
+PWDATA
+,
+PRDATA
+,
+PREADY
+,
+PSLVERR
+)
+;
+parameter
+AWIDTH
+=
+10
+;
+parameter
+DEPTH
+=
+256
+;
+parameter
+DWIDTH
+=
+32
+;
+parameter
+INITFILE
+=
+"" ""
+;
+parameter
+ID
+=
+0
+;
+parameter
+TPD
+=
+1
+;
+parameter
+ENFUNC
+=
+0
+;
+parameter
+DEBUG
+=
+0
+;
+localparam
+EXT_SIZE
+=
+2
+;
+// Actel Corporation Proprietary and Confidential
+// Copyright 2008 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+// Revision Information:
+// SVN Revision Information:
+// SVN $Revision: 11864 $
+// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
+localparam
+BFMA1I11
+=
+22
+;
+localparam
+BFMA1l11
+=
+0
+;
+localparam
+BFMA1OOOI
+=
+4
+;
+localparam
+BFMA1IOOI
+=
+8
+;
+localparam
+BFMA1lOOI
+=
+12
+;
+localparam
+BFMA1OIOI
+=
+16
+;
+localparam
+BFMA1IIOI
+=
+20
+;
+localparam
+BFMA1lIOI
+=
+24
+;
+localparam
+BFMA1OlOI
+=
+28
+;
+localparam
+BFMA1IlOI
+=
+32
+;
+localparam
+BFMA1llOI
+=
+36
+;
+localparam
+BFMA1O0OI
+=
+40
+;
+localparam
+BFMA1I0OI
+=
+44
+;
+localparam
+BFMA1l0OI
+=
+48
+;
+localparam
+BFMA1O1OI
+=
+52
+;
+localparam
+BFMA1I1OI
+=
+56
+;
+localparam
+BFMA1l1OI
+=
+60
+;
+localparam
+BFMA1OOII
+=
+64
+;
+localparam
+BFMA1IOII
+=
+68
+;
+localparam
+BFMA1lOII
+=
+72
+;
+localparam
+BFMA1OIII
+=
+76
+;
+localparam
+BFMA1IIII
+=
+80
+;
+localparam
+BFMA1lIII
+=
+100
+;
+localparam
+BFMA1OlII
+=
+101
+;
+localparam
+BFMA1IlII
+=
+102
+;
+localparam
+BFMA1llII
+=
+103
+;
+localparam
+BFMA1O0II
+=
+104
+;
+localparam
+BFMA1I0II
+=
+105
+;
+localparam
+BFMA1l0II
+=
+106
+;
+localparam
+BFMA1O1II
+=
+107
+;
+localparam
+BFMA1I1II
+=
+108
+;
+localparam
+BFMA1l1II
+=
+109
+;
+localparam
+BFMA1OOlI
+=
+110
+;
+localparam
+BFMA1IOlI
+=
+111
+;
+localparam
+BFMA1lOlI
+=
+112
+;
+localparam
+BFMA1OIlI
+=
+113
+;
+localparam
+BFMA1IIlI
+=
+114
+;
+localparam
+BFMA1lIlI
+=
+115
+;
+localparam
+BFMA1OllI
+=
+128
+;
+localparam
+BFMA1IllI
+=
+129
+;
+localparam
+BFMA1lllI
+=
+130
+;
+localparam
+BFMA1O0lI
+=
+131
+;
+localparam
+BFMA1I0lI
+=
+132
+;
+localparam
+BFMA1l0lI
+=
+133
+;
+localparam
+BFMA1O1lI
+=
+134
+;
+localparam
+BFMA1I1lI
+=
+135
+;
+localparam
+BFMA1l1lI
+=
+136
+;
+localparam
+BFMA1OO0I
+=
+137
+;
+localparam
+BFMA1IO0I
+=
+138
+;
+localparam
+BFMA1lO0I
+=
+139
+;
+localparam
+BFMA1OI0I
+=
+140
+;
+localparam
+BFMA1II0I
+=
+141
+;
+localparam
+BFMA1lI0I
+=
+142
+;
+localparam
+BFMA1Ol0I
+=
+150
+;
+localparam
+BFMA1Il0I
+=
+151
+;
+localparam
+BFMA1ll0I
+=
+152
+;
+localparam
+BFMA1O00I
+=
+153
+;
+localparam
+BFMA1I00I
+=
+154
+;
+localparam
+BFMA1l00I
+=
+160
+;
+localparam
+BFMA1O10I
+=
+161
+;
+localparam
+BFMA1I10I
+=
+162
+;
+localparam
+BFMA1l10I
+=
+163
+;
+localparam
+BFMA1OO1I
+=
+164
+;
+localparam
+BFMA1IO1I
+=
+165
+;
+localparam
+BFMA1lO1I
+=
+166
+;
+localparam
+BFMA1OI1I
+=
+167
+;
+localparam
+BFMA1II1I
+=
+168
+;
+localparam
+BFMA1lI1I
+=
+169
+;
+localparam
+BFMA1Ol1I
+=
+170
+;
+localparam
+BFMA1Il1I
+=
+171
+;
+localparam
+BFMA1ll1I
+=
+172
+;
+localparam
+BFMA1O01I
+=
+200
+;
+localparam
+BFMA1I01I
+=
+201
+;
+localparam
+BFMA1l01I
+=
+202
+;
+localparam
+BFMA1O11I
+=
+203
+;
+localparam
+BFMA1I11I
+=
+204
+;
+localparam
+BFMA1l11I
+=
+205
+;
+localparam
+BFMA1OOOl
+=
+206
+;
+localparam
+BFMA1IOOl
+=
+207
+;
+localparam
+BFMA1lOOl
+=
+208
+;
+localparam
+BFMA1OIOl
+=
+209
+;
+localparam
+BFMA1IIOl
+=
+210
+;
+localparam
+BFMA1lIOl
+=
+211
+;
+localparam
+BFMA1OlOl
+=
+212
+;
+localparam
+BFMA1IlOl
+=
+213
+;
+localparam
+BFMA1llOl
+=
+214
+;
+localparam
+BFMA1O0Ol
+=
+215
+;
+localparam
+BFMA1I0Ol
+=
+216
+;
+localparam
+BFMA1l0Ol
+=
+217
+;
+localparam
+BFMA1O1Ol
+=
+218
+;
+localparam
+BFMA1I1Ol
+=
+219
+;
+localparam
+BFMA1l1Ol
+=
+220
+;
+localparam
+BFMA1OOIl
+=
+221
+;
+localparam
+BFMA1IOIl
+=
+222
+;
+localparam
+BFMA1lOIl
+=
+250
+;
+localparam
+BFMA1OIIl
+=
+251
+;
+localparam
+BFMA1IIIl
+=
+252
+;
+localparam
+BFMA1lIIl
+=
+253
+;
+localparam
+BFMA1OlIl
+=
+254
+;
+localparam
+BFMA1IlIl
+=
+255
+;
+localparam
+BFMA1llIl
+=
+1001
+;
+localparam
+BFMA1O0Il
+=
+1002
+;
+localparam
+BFMA1I0Il
+=
+1003
+;
+localparam
+BFMA1l0Il
+=
+1004
+;
+localparam
+BFMA1O1Il
+=
+1005
+;
+localparam
+BFMA1I1Il
+=
+1006
+;
+localparam
+BFMA1l1Il
+=
+1007
+;
+localparam
+BFMA1OOll
+=
+1008
+;
+localparam
+BFMA1IOll
+=
+1009
+;
+localparam
+BFMA1lOll
+=
+1010
+;
+localparam
+BFMA1OIll
+=
+1011
+;
+localparam
+BFMA1IIll
+=
+1012
+;
+localparam
+BFMA1lIll
+=
+1013
+;
+localparam
+BFMA1Olll
+=
+1014
+;
+localparam
+BFMA1Illl
+=
+1015
+;
+localparam
+BFMA1llll
+=
+1016
+;
+localparam
+BFMA1O0ll
+=
+1017
+;
+localparam
+BFMA1I0ll
+=
+1018
+;
+localparam
+BFMA1l0ll
+=
+1019
+;
+localparam
+BFMA1O1ll
+=
+1020
+;
+localparam
+BFMA1I1ll
+=
+1021
+;
+localparam
+BFMA1l1ll
+=
+1022
+;
+localparam
+BFMA1OO0l
+=
+1023
+;
+localparam
+BFMA1IO0l
+=
+0
+;
+localparam
+BFMA1lO0l
+=
+1
+;
+localparam
+BFMA1OI0l
+=
+2
+;
+localparam
+BFMA1II0l
+=
+3
+;
+localparam
+BFMA1lI0l
+=
+4
+;
+localparam
+BFMA1Ol0l
+=
+5
+;
+localparam
+BFMA1Il0l
+=
+6
+;
+localparam
+BFMA1ll0l
+=
+7
+;
+localparam
+BFMA1O00l
+=
+8
+;
+localparam
+BFMA1I00l
+=
+0
+;
+localparam
+BFMA1l00l
+=
+1
+;
+localparam
+BFMA1O10l
+=
+2
+;
+localparam
+BFMA1I10l
+=
+3
+;
+localparam
+BFMA1l10l
+=
+4
+;
+localparam
+BFMA1OO1l
+=
+32
+\'h
+00000000
+;
+localparam
+BFMA1IO1l
+=
+32
+\'h
+00002000
+;
+localparam
+BFMA1lO1l
+=
+32
+\'h
+00004000
+;
+localparam
+BFMA1OI1l
+=
+32
+\'h
+00006000
+;
+localparam
+BFMA1II1l
+=
+32
+\'h
+00008000
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1lI1l
+=
+0
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1Ol1l
+=
+1
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1Il1l
+=
+2
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1ll1l
+=
+3
+;
+function
+integer
+BFMA1O01l
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+BFMA1O01l
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+integer
+to_int_unsigned
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+to_int_unsigned
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+integer
+to_int_signed
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+to_int_signed
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+to_slv32
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+reg
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+begin
+BFMA1I01l
+=
+BFMA1ll1l
+;
+to_slv32
+=
+BFMA1I01l
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1l01l
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+reg
+BFMA1lOO0
+;
+begin
+BFMA1IOO0
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+case
+(
+BFMA1OOO0
+)
+0
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+23
+:
+16
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+31
+:
+24
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+31
+:
+16
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+31
+:
+16
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+010
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+end
+2
+\'b
+01
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=10) ? (WARNING)""
+)
+;
+end
+2
+\'b
+11
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+1
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+end
+2
+\'b
+01
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=10) ? (WARNING)""
+)
+;
+end
+2
+\'b
+11
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+2
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+8
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+default
+:
+begin
+$display
+(
+""Illegal Alignment mode (ERROR)""
+)
+;
+end
+endcase
+BFMA1l01l
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1OIO0
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+begin
+BFMA1IOO0
+=
+BFMA1l01l
+(
+BFMA1O11l
+,
+BFMA1I11l
+,
+BFMA1l11l
+,
+BFMA1OOO0
+)
+;
+BFMA1OIO0
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1IIO0
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+reg
+BFMA1lOO0
+;
+begin
+if
+(
+BFMA1OOO0
+==
+8
+)
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+else
+begin
+BFMA1IOO0
+=
+0
+;
+BFMA1lOO0
+=
+BFMA1I11l
+[
+1
+]
+;
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+2
+\'b
+01
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+8
+]
+;
+2
+\'b
+10
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+23
+:
+16
+]
+;
+2
+\'b
+11
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+31
+:
+24
+]
+;
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+case
+(
+BFMA1lOO0
+)
+1
+\'b
+0
+:
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+1
+\'b
+1
+:
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+31
+:
+16
+]
+;
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+010
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+default
+:
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+endcase
+end
+BFMA1IIO0
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+integer
+BFMA1lIO0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1OlO0
+;
+begin
+BFMA1OlO0
+=
+BFMA1ll1l
+;
+BFMA1lIO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1IlO0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+\'h
+62
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+\'h
+68
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+\'h
+77
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+\'h
+78
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+\'h
+3f
+;
+end
+endcase
+BFMA1IlO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1llO0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+input
+BFMA1O0O0
+;
+integer
+BFMA1O0O0
+;
+integer
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+1
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+2
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+4
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+BFMA1O0O0
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+0
+;
+end
+endcase
+BFMA1llO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1I0O0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+input
+BFMA1l0O0
+;
+integer
+BFMA1l0O0
+;
+reg
+[
+2
+:
+0
+]
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+000
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+001
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+010
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+BFMA1l0O0
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+XXX
+;
+end
+endcase
+BFMA1I0O0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1O1O0
+;
+input
+BFMA1I1O0
+;
+integer
+BFMA1I1O0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+input
+BFMA1l1O0
+;
+integer
+BFMA1l1O0
+;
+input
+BFMA1OOI0
+;
+integer
+BFMA1OOI0
+;
+integer
+BFMA1IOI0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lOI0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1OII0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1III0
+;
+integer
+BFMA1lII0
+;
+reg
+[
+63
+:
+0
+]
+BFMA1OlI0
+;
+localparam
+[
+31
+:
+0
+]
+BFMA1IlI0
+=
+0
+;
+localparam
+[
+31
+:
+0
+]
+BFMA1llI0
+=
+1
+;
+begin
+BFMA1lOI0
+=
+BFMA1ll1l
+;
+BFMA1OII0
+=
+BFMA1l1O0
+;
+BFMA1lII0
+=
+BFMA1l1O0
+;
+BFMA1III0
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+case
+(
+BFMA1I1O0
+)
+BFMA1llIl
+:
+begin
+BFMA1III0
+=
+0
+;
+end
+BFMA1O0Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
++
+BFMA1OII0
+;
+end
+BFMA1I0Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+-
+BFMA1OII0
+;
+end
+BFMA1l0Il
+:
+begin
+BFMA1OlI0
+=
+BFMA1lOI0
+*
+BFMA1OII0
+;
+BFMA1III0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+;
+end
+BFMA1O1Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+/
+BFMA1OII0
+;
+end
+BFMA1OOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+&
+BFMA1OII0
+;
+end
+BFMA1IOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+|
+BFMA1OII0
+;
+end
+BFMA1lOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+^
+BFMA1OII0
+;
+end
+BFMA1OIll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+^
+BFMA1OII0
+;
+end
+BFMA1lIll
+:
+begin
+if
+(
+BFMA1lII0
+==
+0
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+end
+else
+begin
+BFMA1III0
+=
+BFMA1lOI0
+>>
+BFMA1lII0
+;
+end
+end
+BFMA1IIll
+:
+begin
+if
+(
+BFMA1lII0
+==
+0
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+end
+else
+begin
+BFMA1III0
+=
+BFMA1lOI0
+<<
+BFMA1lII0
+;
+end
+end
+BFMA1l1Il
+:
+begin
+BFMA1OlI0
+=
+{
+BFMA1IlI0
+,
+BFMA1llI0
+}
+;
+if
+(
+BFMA1lII0
+>
+0
+)
+begin
+begin
+:
+BFMA1O0I0
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+1
+;
+BFMA1I0I0
+<=
+BFMA1lII0
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OlI0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+*
+BFMA1lOI0
+;
+end
+end
+end
+BFMA1III0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+;
+end
+BFMA1Olll
+:
+begin
+if
+(
+BFMA1lOI0
+==
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1Illl
+:
+begin
+if
+(
+BFMA1lOI0
+!=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1llll
+:
+begin
+if
+(
+BFMA1lOI0
+>
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1O0ll
+:
+begin
+if
+(
+BFMA1lOI0
+<
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1I0ll
+:
+begin
+if
+(
+BFMA1lOI0
+>=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1l0ll
+:
+begin
+if
+(
+BFMA1lOI0
+<=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1I1Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+%
+BFMA1OII0
+;
+end
+BFMA1O1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+1
+\'b
+1
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1I1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+1
+\'b
+0
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1l1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+~
+BFMA1III0
+[
+BFMA1l1O0
+]
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1OO0l
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+0
+;
+BFMA1III0
+[
+0
+]
+=
+BFMA1lOI0
+[
+BFMA1l1O0
+]
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+default
+:
+begin
+$display
+(
+""Illegal Maths Operator (FAILURE)""
+)
+;
+$stop
+;
+end
+endcase
+BFMA1IOI0
+=
+BFMA1III0
+;
+if
+(
+BFMA1OOI0
+>=
+4
+)
+begin
+$display
+(
+""Calculated %d = %d (%d) %d""
+,
+BFMA1IOI0
+,
+BFMA1ll1l
+,
+BFMA1I1O0
+,
+BFMA1l1O0
+)
+;
+end
+BFMA1O1O0
+=
+BFMA1IOI0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1l0I0
+;
+input
+[
+31
+:
+0
+]
+BFMA1ll1l
+;
+reg
+[
+31
+:
+0
+]
+BFMA1O1I0
+;
+begin
+BFMA1O1I0
+=
+BFMA1ll1l
+;
+BFMA1O1I0
+=
+0
+;
+begin
+:
+BFMA1I1I0
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+31
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+if
+(
+(
+BFMA1ll1l
+[
+BFMA1I0I0
+]
+)
+==
+1
+\'b
+1
+)
+begin
+BFMA1O1I0
+[
+BFMA1I0I0
+]
+=
+1
+\'b
+1
+;
+end
+end
+end
+BFMA1l0I0
+=
+BFMA1O1I0
+;
+end
+endfunction
+function
+integer
+BFMA1l1I0
+;
+input
+BFMA1OOl0
+;
+integer
+BFMA1OOl0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IOl0
+;
+integer
+BFMA1lOl0
+;
+begin
+BFMA1lOl0
+=
+BFMA1OOl0
+/
+BFMA1ll1l
+;
+BFMA1IOl0
+=
+BFMA1OOl0
+-
+BFMA1lOl0
+*
+BFMA1ll1l
+;
+BFMA1l1I0
+=
+BFMA1IOl0
+;
+end
+endfunction
+function
+integer
+BFMA1OIl0
+;
+input
+BFMA1OOl0
+;
+integer
+BFMA1OOl0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IOl0
+;
+integer
+BFMA1lOl0
+;
+begin
+BFMA1lOl0
+=
+BFMA1OOl0
+/
+BFMA1ll1l
+;
+BFMA1IOl0
+=
+BFMA1OOl0
+-
+BFMA1lOl0
+*
+BFMA1ll1l
+;
+BFMA1OIl0
+=
+BFMA1lOl0
+;
+end
+endfunction
+function
+integer
+to_boolean
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IIl0
+;
+begin
+BFMA1IIl0
+=
+0
+;
+if
+(
+BFMA1ll1l
+!=
+0
+)
+BFMA1IIl0
+=
+1
+;
+to_boolean
+=
+BFMA1IIl0
+;
+end
+endfunction
+function
+integer
+BFMA1lIl0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lll0
+;
+reg
+BFMA1O0l0
+;
+begin
+BFMA1Ill0
+=
+BFMA1Oll0
+;
+BFMA1O0l0
+=
+1
+\'b
+1
+;
+BFMA1lll0
+[
+0
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+;
+BFMA1lll0
+[
+1
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+0
+]
+;
+BFMA1lll0
+[
+2
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+1
+]
+;
+BFMA1lll0
+[
+3
+]
+=
+BFMA1Ill0
+[
+2
+]
+;
+BFMA1lll0
+[
+4
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+3
+]
+;
+BFMA1lll0
+[
+5
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+4
+]
+;
+BFMA1lll0
+[
+6
+]
+=
+BFMA1Ill0
+[
+5
+]
+;
+BFMA1lll0
+[
+7
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+6
+]
+;
+BFMA1lll0
+[
+8
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+7
+]
+;
+BFMA1lll0
+[
+9
+]
+=
+BFMA1Ill0
+[
+8
+]
+;
+BFMA1lll0
+[
+10
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+9
+]
+;
+BFMA1lll0
+[
+11
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+10
+]
+;
+BFMA1lll0
+[
+12
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+11
+]
+;
+BFMA1lll0
+[
+13
+]
+=
+BFMA1Ill0
+[
+12
+]
+;
+BFMA1lll0
+[
+14
+]
+=
+BFMA1Ill0
+[
+13
+]
+;
+BFMA1lll0
+[
+15
+]
+=
+BFMA1Ill0
+[
+14
+]
+;
+BFMA1lll0
+[
+16
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+15
+]
+;
+BFMA1lll0
+[
+17
+]
+=
+BFMA1Ill0
+[
+16
+]
+;
+BFMA1lll0
+[
+18
+]
+=
+BFMA1Ill0
+[
+17
+]
+;
+BFMA1lll0
+[
+19
+]
+=
+BFMA1Ill0
+[
+18
+]
+;
+BFMA1lll0
+[
+20
+]
+=
+BFMA1Ill0
+[
+19
+]
+;
+BFMA1lll0
+[
+21
+]
+=
+BFMA1Ill0
+[
+20
+]
+;
+BFMA1lll0
+[
+22
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+21
+]
+;
+BFMA1lll0
+[
+23
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+22
+]
+;
+BFMA1lll0
+[
+24
+]
+=
+BFMA1Ill0
+[
+23
+]
+;
+BFMA1lll0
+[
+25
+]
+=
+BFMA1Ill0
+[
+24
+]
+;
+BFMA1lll0
+[
+26
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+25
+]
+;
+BFMA1lll0
+[
+27
+]
+=
+BFMA1Ill0
+[
+26
+]
+;
+BFMA1lll0
+[
+28
+]
+=
+BFMA1Ill0
+[
+27
+]
+;
+BFMA1lll0
+[
+29
+]
+=
+BFMA1Ill0
+[
+28
+]
+;
+BFMA1lll0
+[
+30
+]
+=
+BFMA1Ill0
+[
+29
+]
+;
+BFMA1lll0
+[
+31
+]
+=
+BFMA1Ill0
+[
+30
+]
+;
+BFMA1lIl0
+=
+BFMA1lll0
+;
+end
+endfunction
+function
+integer
+BFMA1I0l0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1l0l0
+;
+integer
+BFMA1I0I0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+begin
+BFMA1Ill0
+=
+BFMA1Oll0
+;
+for
+(
+BFMA1I0I0
+=
+31
+;
+BFMA1I0I0
+>=
+BFMA1O11l
+;
+BFMA1I0I0
+=
+BFMA1I0I0
+-
+1
+)
+BFMA1Ill0
+[
+BFMA1I0I0
+]
+=
+0
+;
+BFMA1l0l0
+=
+BFMA1Ill0
+;
+BFMA1I0l0
+=
+BFMA1l0l0
+;
+end
+endfunction
+function
+integer
+BFMA1O1l0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1l0l0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+integer
+BFMA1I1l0
+;
+integer
+BFMA1I0I0
+;
+begin
+case
+(
+BFMA1O11l
+)
+1
+:
+begin
+BFMA1I1l0
+=
+0
+;
+end
+2
+:
+begin
+BFMA1I1l0
+=
+1
+;
+end
+4
+:
+begin
+BFMA1I1l0
+=
+2
+;
+end
+8
+:
+begin
+BFMA1I1l0
+=
+3
+;
+end
+16
+:
+begin
+BFMA1I1l0
+=
+4
+;
+end
+32
+:
+begin
+BFMA1I1l0
+=
+5
+;
+end
+64
+:
+begin
+BFMA1I1l0
+=
+6
+;
+end
+128
+:
+begin
+BFMA1I1l0
+=
+7
+;
+end
+256
+:
+begin
+BFMA1I1l0
+=
+8
+;
+end
+512
+:
+begin
+BFMA1I1l0
+=
+9
+;
+end
+1024
+:
+begin
+BFMA1I1l0
+=
+10
+;
+end
+2048
+:
+begin
+BFMA1I1l0
+=
+11
+;
+end
+4096
+:
+begin
+BFMA1I1l0
+=
+12
+;
+end
+8192
+:
+begin
+BFMA1I1l0
+=
+13
+;
+end
+16384
+:
+begin
+BFMA1I1l0
+=
+14
+;
+end
+32768
+:
+begin
+BFMA1I1l0
+=
+15
+;
+end
+65536
+:
+begin
+BFMA1I1l0
+=
+16
+;
+end
+131072
+:
+BFMA1I1l0
+=
+17
+;
+262144
+:
+BFMA1I1l0
+=
+18
+;
+524288
+:
+BFMA1I1l0
+=
+19
+;
+1048576
+:
+BFMA1I1l0
+=
+20
+;
+2097152
+:
+BFMA1I1l0
+=
+21
+;
+4194304
+:
+BFMA1I1l0
+=
+22
+;
+8388608
+:
+BFMA1I1l0
+=
+23
+;
+16777216
+:
+BFMA1I1l0
+=
+24
+;
+33554432
+:
+BFMA1I1l0
+=
+25
+;
+67108864
+:
+BFMA1I1l0
+=
+26
+;
+134217728
+:
+BFMA1I1l0
+=
+27
+;
+268435456
+:
+BFMA1I1l0
+=
+28
+;
+536870912
+:
+BFMA1I1l0
+=
+29
+;
+1073741824
+:
+BFMA1I1l0
+=
+30
+;
+default
+:
+begin
+$display
+(
+""Random function error (FAILURE)""
+)
+;
+$finish
+;
+end
+endcase
+BFMA1Ill0
+=
+to_slv32
+(
+BFMA1Oll0
+)
+;
+if
+(
+BFMA1I1l0
+<
+31
+)
+begin
+for
+(
+BFMA1I0I0
+=
+31
+;
+BFMA1I0I0
+>=
+BFMA1I1l0
+;
+BFMA1I0I0
+=
+BFMA1I0I0
+-
+1
+)
+BFMA1Ill0
+[
+BFMA1I0I0
+]
+=
+0
+;
+end
+BFMA1l0l0
+=
+to_int_signed
+(
+BFMA1Ill0
+)
+;
+BFMA1O1l0
+=
+BFMA1l0l0
+;
+end
+endfunction
+function
+bound1k
+;
+input
+BFMA1l1l0
+;
+integer
+BFMA1l1l0
+;
+input
+BFMA1OO00
+;
+integer
+BFMA1OO00
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IO00
+;
+reg
+BFMA1lO00
+;
+begin
+BFMA1IO00
+=
+BFMA1OO00
+;
+BFMA1lO00
+=
+0
+;
+case
+(
+BFMA1l1l0
+)
+0
+:
+begin
+if
+(
+BFMA1IO00
+[
+9
+:
+0
+]
+==
+10
+\'b
+0000000000
+)
+begin
+BFMA1lO00
+=
+1
+;
+end
+end
+1
+:
+begin
+BFMA1lO00
+=
+1
+;
+end
+2
+:
+begin
+end
+default
+:
+begin
+$display
+(
+""Illegal Burst Boundary Set (FAILURE)""
+)
+;
+$finish
+;
+end
+endcase
+bound1k
+=
+BFMA1lO00
+;
+end
+endfunction
+input
+PCLK
+;
+input
+PRESETN
+;
+input
+PENABLE
+;
+input
+PWRITE
+;
+input
+PSEL
+;
+input
+[
+AWIDTH
+-
+1
+:
+0
+]
+PADDR
+;
+input
+[
+DWIDTH
+-
+1
+:
+0
+]
+PWDATA
+;
+output
+[
+DWIDTH
+-
+1
+:
+0
+]
+PRDATA
+;
+wire
+[
+DWIDTH
+-
+1
+:
+0
+]
+#
+TPD
+PRDATA
+;
+output
+PREADY
+;
+wire
+PREADY
+;
+output
+PSLVERR
+;
+wire
+PSLVERR
+;
+wire
+EXT_EN
+;
+wire
+EXT_WR
+;
+wire
+EXT_RD
+;
+wire
+[
+AWIDTH
+-
+1
+:
+0
+]
+EXT_ADDR
+;
+wire
+[
+DWIDTH
+-
+1
+:
+0
+]
+EXT_DATA
+;
+assign
+EXT_EN
+=
+1
+\'b
+0
+;
+assign
+EXT_WR
+=
+1
+\'b
+0
+;
+assign
+EXT_RD
+=
+1
+\'b
+0
+;
+assign
+EXT_ADDR
+=
+{
+AWIDTH
+-
+1
+-
+(
+0
+)
++
+1
+{
+1
+\'b
+0
+}
+}
+;
+assign
+EXT_DATA
+=
+0
+;
+BFM_APBSLAVEEXT
+#
+(
+.AWIDTH
+(
+AWIDTH
+)
+,
+.DEPTH
+(
+DEPTH
+)
+,
+.DWIDTH
+(
+DWIDTH
+)
+,
+.EXT_SIZE
+(
+EXT_SIZE
+)
+,
+.INITFILE
+(
+INITFILE
+)
+,
+.ID
+(
+ID
+)
+,
+.TPD
+(
+TPD
+)
+,
+.ENFUNC
+(
+ENFUNC
+)
+,
+.DEBUG
+(
+DEBUG
+)
+)
+BFMA1OI1II
+(
+.PCLK
+(
+PCLK
+)
+,
+.PRESETN
+(
+PRESETN
+)
+,
+.PENABLE
+(
+PENABLE
+)
+,
+.PWRITE
+(
+PWRITE
+)
+,
+.PSEL
+(
+PSEL
+)
+,
+.PADDR
+(
+PADDR
+)
+,
+.PWDATA
+(
+PWDATA
+)
+,
+.PRDATA
+(
+PRDATA
+)
+,
+.PREADY
+(
+PREADY
+)
+,
+.PSLVERR
+(
+PSLVERR
+)
+,
+.EXT_EN
+(
+EXT_EN
+)
+,
+.EXT_WR
+(
+EXT_WR
+)
+,
+.EXT_RD
+(
+EXT_RD
+)
+,
+.EXT_ADDR
+(
+EXT_ADDR
+)
+,
+.EXT_DATA
+(
+EXT_DATA
+)
+)
+;
+endmodule
+"
+"// ********************************************************************/
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
+// IN ADVANCE IN WRITING.
+ //
+//
+// corespi.v
+//
+//
+// Revision Information:
+// Date     Description
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+// Resolved SARs
+// SAR      Date     Who   Description
+// 72424       top level name
+// 72425       PADDR 11 bits
+// Notes:
+//
+//
+// *********************************************************************/
+
+module
+CORESPI 
+(\t //inputs
+             PCLK,       //system clock
+             PRESETN,    //system reset
+             PADDR,      //address line
+             PSEL,       //device select
+             PENABLE,    //enable
+             PWRITE,     //write
+             PWDATA,     //write data
+             SPISSI,     //slave select
+             SPISDI,     //serial data in
+             SPICLKI,    //serial clock in
+
+             //outputs
+             PRDATA,     //data read
+             SPIINT,     //interrupt
+             SPISS,      //slave select
+             SPISCLKO,   //serial clock out
+             SPIRXAVAIL, //data ready to be read (dma mode)
+             SPITXRFM,   //room for more (dma mode)
+             SPIOEN,     //output enable
+             SPISDO,     //serial data out
+             SPIMODE,     //1 -> master, 0 -> slave,
+             PREADY,
+             PSLVERR
+             
+             );
+
+// AS: Added Parameters to replace 
+// configuration bits / registers
+parameter               FAMILY          =   15;
+parameter               APB_DWIDTH      =   8;
+parameter               CFG_FRAME_SIZE  =   4;
+parameter               FIFO_DEPTH      =   4;
+parameter               CFG_CLK         =   7;
+parameter               CFG_SPO         =   0;
+parameter               CFG_SPH         =   0;
+parameter               CFG_SPS         =   0;
+parameter               CFG_MODE        =   0;
+
+
+//input TESTMODE;
+input PCLK;
+input PRESETN;
+input [6:0] PADDR;
+input PSEL;
+input PENABLE;
+input PWRITE;
+input [APB_DWIDTH-1:0] PWDATA;
+input SPISSI;
+input SPISDI;
+input SPICLKI;
+
+
+output [APB_DWIDTH-1:0] PRDATA;
+output SPIINT;
+output [7:0] SPISS;
+output SPISCLKO;
+output SPIRXAVAIL;
+output SPITXRFM;
+output SPIOEN;
+output SPIMODE;
+output SPISDO;
+
+// AP3
+output PSLVERR;
+output PREADY;
+
+// tie off AP3 signals
+assign PSLVERR = 1'b0;
+assign PREADY = 1'b1;
+
+spi # (
+          .APB_DWIDTH     (APB_DWIDTH),
+          .CFG_FRAME_SIZE (CFG_FRAME_SIZE),
+          .FIFO_DEPTH     (FIFO_DEPTH),
+          .CFG_CLK        (CFG_CLK),
+          .CFG_SPO        (CFG_SPO),
+          .CFG_SPH        (CFG_SPH),
+          .CFG_SPS        (CFG_SPS),
+          .CFG_MODE       (CFG_MODE)
+) USPI( //inputs
+//         .TESTMODE(TESTMODE),
+         .PCLK(PCLK),      
+         .PRESETN(PRESETN),
+         .PADDR(PADDR),    
+         .PSEL(PSEL),      
+         .PENABLE(PENABLE),
+         .PWRITE(PWRITE),  
+         .PWDATA(PWDATA),  
+         .SPISSI(SPISSI),  
+         .SPISDI(SPISDI),  
+         .SPICLKI(SPICLKI),
+          
+         //outputs
+         .PRDDATA(PRDATA), 
+         .SPIINT(SPIINT),  
+         .SPISS(SPISS),    
+         .SPISCLKO(SPISCLKO), 
+         .SPIRXAVAIL(SPIRXAVAIL),
+         .SPITXRFM(SPITXRFM), 
+         .SPIOEN(SPIOEN), 
+         .SPISDO(SPISDO), 
+         .SPIMODE(SPIMODE)
+         );
+
+endmodule
+"
+"//////////////////////////////////////////////////////////////////////
+// Created by Actel SmartDesign Tue Apr 29 08:58:52 2014
+// Testbench Template
+// This is a basic testbench that instantiates your design with basic 
+// clock and reset pins connected.  If your design has special
+// clock/reset or testbench driver requirements then you should 
+// copy this file and modify it. 
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ns/100ps
+
+module testbench;
+
+parameter SYSCLK_PERIOD = 100; // 10MHz
+
+reg SYSCLK;
+reg NSYSRESET;
+
+initial
+begin
+    SYSCLK = 1'b0;
+    NSYSRESET = 1'b0;
+end
+
+//////////////////////////////////////////////////////////////////////
+// Reset Pulse
+//////////////////////////////////////////////////////////////////////
+initial
+begin
+    #(SYSCLK_PERIOD * 10 )
+        NSYSRESET = 1'b1;
+end
+
+
+//////////////////////////////////////////////////////////////////////
+// 10MHz Clock Driver
+//////////////////////////////////////////////////////////////////////
+always @(SYSCLK)
+    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
+
+
+//////////////////////////////////////////////////////////////////////
+// Instantiate Unit Under Test:  cc3000fpga_MSS
+//////////////////////////////////////////////////////////////////////
+cc3000fpga_MSS cc3000fpga_MSS_0 (
+    // Inputs
+    .MSSPREADY({1{1'b0}}),
+    .MSSPSLVERR({1{1'b0}}),
+    .MSSPRDATA({32{1'b0}}),
+    .UART_0_RXD({1{1'b0}}),
+    .UART_1_RXD({1{1'b0}}),
+    .SPI_1_DI({1{1'b0}}),
+    .GPIO_2_IN({1{1'b0}}),
+    .MSS_RESET_N(NSYSRESET),
+
+    // Outputs
+    .M2F_GPO_1( ),
+    .M2F_GPO_0( ),
+    .FAB_CLK( ),
+    .M2F_RESET_N( ),
+    .MSSPSEL( ),
+    .MSSPENABLE( ),
+    .MSSPWRITE( ),
+    .M2F_GPO_3( ),
+    .M2F_GPO_9( ),
+    .MSSPADDR( ),
+    .MSSPWDATA( ),
+    .UART_0_TXD( ),
+    .UART_1_TXD( ),
+    .SPI_1_DO( ),
+    .GPIO_4_OUT( ),
+
+    // Inouts
+    .SPI_1_CLK( ),
+    .SPI_1_SS( )
+
+);
+
+endmodule
+
+"
+"// ********************************************************************/ 
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+//  
+//
+// SPI Synchronous Fifo
+//
+// Revision Information:
+// Date     Description
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+// Resolved SARs
+// SAR      Date     Who   Description
+//
+// Notes: 
+// Sept 5th. Fix for reading empty fifo.
+//
+// *********************************************************************/ 
+
+
+
+module spi_fifo(   pclk,           
+                   presetn,        
+                   fiforst,
+                   //fifosize,      
+                   data_in,       
+                   flag_in,       
+                   data_out,      
+                   flag_out,      
+
+                   read_in,       
+                   write_in,      
+                   
+                   full_out,      
+                   empty_out,     
+                   full_next_out, 
+                   empty_next_out,
+                   overflow_out,  
+                   fifo_count
+                );
+
+parameter CFG_FRAME_SIZE = 4;       // 4-32
+parameter FIFO_DEPTH = 4;       // 2,4,8,16,32
+
+                
+input pclk;
+input presetn;
+input fiforst;
+//input [1:0] fifosize;       
+input [CFG_FRAME_SIZE-1:0] data_in;
+input read_in;
+input write_in;
+input flag_in;
+
+
+output [CFG_FRAME_SIZE-1:0] data_out;
+output empty_out;
+output full_out;
+output empty_next_out;
+output full_next_out;
+output overflow_out;
+output flag_out;
+output [5:0] fifo_count;
+
+   
+reg [4:0] rd_pointer_d; 
+reg [4:0] rd_pointer_q;        //read pointer address
+reg [4:0] wr_pointer_d;
+reg [4:0] wr_pointer_q;        //write pointer address
+reg [5:0] counter_d;
+reg [5:0] counter_q;           //counter 5 bits
+
+
+reg [CFG_FRAME_SIZE:0] fifo_mem_d[0:FIFO_DEPTH-1];    //FIFO has extra flag bit (CFG_FRAME_SIZE + 1)
+reg [CFG_FRAME_SIZE:0] fifo_mem_q[0:FIFO_DEPTH-1];
+reg [CFG_FRAME_SIZE:0] data_out_dx;
+reg [CFG_FRAME_SIZE:0] data_out_d;
+
+reg full_out;       
+reg empty_out;     
+reg full_next_out;  
+reg empty_next_out; 
+
+// -----------------------------
+// AS: replaced with fixed width
+// -----------------------------
+
+//localparam [1:0] FS4  = 2'b00;
+//localparam [1:0] FS8  = 2'b01;
+//localparam [1:0] FS16 = 2'b10;
+//localparam [1:0] FS32 = 2'b11;
+//
+//
+//// AS: replaced with parameter
+////reg [5:0] FIFO_DEPTH;
+//
+//always @(posedge pclk or negedge presetn)    // Register as this feeds into lots of logic
+//begin
+//   if (~presetn)
+//      FIFO_DEPTH <= 4;
+//   else
+//   begin
+//      case (fifosize)
+//             FS8   : FIFO_DEPTH <= 8;
+//             FS16  : FIFO_DEPTH <= 16;
+//             FS32  : FIFO_DEPTH <= 32;
+//           default : FIFO_DEPTH <= 4;
+//      endcase
+//   end
+//end
+   
+
+wire [CFG_FRAME_SIZE-1:0]  data_out  = data_out_d[CFG_FRAME_SIZE-1:0];
+wire                   flag_out  = data_out_d[CFG_FRAME_SIZE];
+
+
+assign overflow_out = (write_in && (counter_q == FIFO_DEPTH));        /* write and fifo full */
+
+
+integer i;
+
+//------------------------------------------------------------------------------------------------------------
+//infer the FIFO   - no reset required
+
+always @(posedge pclk)
+ begin  
+   for (i=0; i<FIFO_DEPTH; i=i+1)
+      begin
+         fifo_mem_q[i] <= fifo_mem_d[i];
+      end
+ end
+
+
+//infer the registers and register the flags 
+always @(posedge pclk or negedge presetn)
+   begin
+   if (~presetn)
+     begin
+       rd_pointer_q   <= 0;
+       wr_pointer_q   <= 0;
+       counter_q      <= 0;
+       full_out       <= 0;
+       empty_out      <= 1;
+       full_next_out  <= 0;
+       empty_next_out <= 0;
+     end
+   else
+     begin
+       rd_pointer_q   <= rd_pointer_d;
+       wr_pointer_q   <= wr_pointer_d;
+       counter_q      <= counter_d;
+       full_out       <= (counter_d == FIFO_DEPTH); //is next pointer equal to fifo length
+       empty_out      <= (counter_d == 0);
+       full_next_out  <= (counter_q == FIFO_DEPTH-1);
+       empty_next_out <= (counter_q == 1);
+     end
+   end
+
+
+integer j;
+
+always @(*)
+begin  
+   for (j=0; j<FIFO_DEPTH; j=j+1)    // Hold old values
+      begin
+         fifo_mem_d[j] = fifo_mem_q[j];
+      end
+
+   if (write_in)
+      begin
+        if (counter_q != FIFO_DEPTH)
+          begin
+          // -----------------------------------------
+          // AS: replaced with fixed size (CFG_FRAME_SIZE)
+          // -----------------------------------------
+          fifo_mem_d[wr_pointer_q[4:0]][CFG_FRAME_SIZE-1:0] = data_in[CFG_FRAME_SIZE-1:0];
+          fifo_mem_d[wr_pointer_q[4:0]][CFG_FRAME_SIZE] = flag_in;
+          end
+      end
+
+   //Read - data out always available
+   data_out_dx = fifo_mem_q[rd_pointer_q[4:0]];
+end
+
+
+// Perform extra read mux on Byte/Half wide reads
+always @(*)
+  begin
+     // AS: removed Byte/Half wide read option
+     // flag bits are zero if count zero
+     data_out_d = data_out_dx[CFG_FRAME_SIZE:0];
+     
+     if (counter_q == 0) data_out_d[CFG_FRAME_SIZE] = 1'b0;
+
+  end
+   
+
+
+// Pointers and Flags
+
+always @(*)
+   begin
+   
+     if (fiforst==1'b1)
+     begin
+        wr_pointer_d  = 5'b00000;
+        rd_pointer_d  = 5'b00000;
+        counter_d     = 6'b000000;
+     end 
+     else
+     begin
+       //defaults
+       counter_d    = counter_q;
+       rd_pointer_d = rd_pointer_q;
+       wr_pointer_d = wr_pointer_q;
+    
+      if (read_in)
+      begin
+         if (counter_q != 0)   // ignore read when empty
+         begin
+            if (~write_in) //if not writing decrement count of the number of objects in fifo else count stays the same
+               begin 
+                  counter_d = counter_q - 1'b1;
+               end
+            // AS: Added limits for wrap-around
+            if (rd_pointer_q == FIFO_DEPTH - 1)
+              rd_pointer_d = 5'b00000;
+            else   
+              rd_pointer_d = rd_pointer_q + 1'b1; 
+         end
+            
+      end //~read_n
+
+      if (write_in)
+      begin
+         if (counter_q != FIFO_DEPTH) // ignore write when full
+         begin
+           if (~read_in)
+            begin
+               counter_d =  counter_q + 1'b1;
+            end
+            // AS: Added limits for wrap-around
+            if (wr_pointer_q == FIFO_DEPTH-1)
+              wr_pointer_d = 5'b00000;
+            else
+              wr_pointer_d = wr_pointer_q + 1'b1;
+              
+           end //~write_n
+         end
+     end
+   end
+      
+wire [5:0] fifo_count = counter_q;
+
+endmodule
+"
+"//--------------------------------------------------------------------
+// Created by Actel SmartDesign Thu Apr 10 11:13:55 2014
+// Parameters for CORESPI
+//--------------------------------------------------------------------
+
+
+parameter APB_DWIDTH = 8;
+parameter CFG_CLK = 7;
+parameter CFG_FRAME_SIZE = 4;
+parameter CFG_MODE = 1;
+parameter CFG_SPH = 0;
+parameter CFG_SPO = 0;
+parameter CFG_SPS = 0;
+parameter FAMILY = 18;
+parameter FIFO_DEPTH = 4;
+parameter HDL_license = ""U"";
+parameter testbench = ""User"";
+"
+"///////////////////////////////////////////////////////////////////////////////////////////////////
+// Company: <Name>
+//
+// File: pwm.v
+// File history:
+//      <Revision number>: <Date>: <Comments>
+//      <Revision number>: <Date>: <Comments>
+//      <Revision number>: <Date>: <Comments>
+//
+// Description: 
+//
+// <Description here>
+//
+// Targeted device: <Family::SmartFusion> <Die::A2F200M3F> <Package::484 FBGA>
+// Author: <Name>
+//
+/////////////////////////////////////////////////////////////////////////////////////////////////// 
+`timescale <time_units> / <precision>
+
+module pwm( clk, duty_cycle, period, pwm_out );
+input port1, port2;
+output port3;
+inout port4;
+
+<statements>
+
+endmodule
+
+"
+"// Microsemi Corporation Proprietary and Confidential
+// Copyright 2011 Microsemi Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
+// IN ADVANCE IN WRITING.
+// Revision Information:
+// 05Feb10              Production Release Version 3.0
+// SVN Revision Information:
+// SVN $Revision: 19036 $
+// SVN $Date: 2013-01-11 08:25:22 -0800 (Fri, 11 Jan 2013) $
+`timescale 1ns/1ps
+module
+CoreAPB3
+#
+(
+parameter
+[
+5
+:
+0
+]
+APB_DWIDTH
+=
+32
+,
+parameter
+IADDR_OPTION
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT0ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT1ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT2ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT3ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT4ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT5ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT6ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT7ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT8ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT9ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT10ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT11ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT12ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT13ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT14ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+APBSLOT15ENABLE
+=
+1
+,
+parameter
+[
+0
+:
+0
+]
+SC_0
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_1
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_2
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_3
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_4
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_5
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_6
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_7
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_8
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_9
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_10
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_11
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_12
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_13
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_14
+=
+0
+,
+parameter
+[
+0
+:
+0
+]
+SC_15
+=
+0
+,
+parameter
+[
+5
+:
+0
+]
+MADDR_BITS
+=
+32
+,
+parameter
+[
+3
+:
+0
+]
+UPR_NIBBLE_POSN
+=
+7
+)
+(
+input
+[
+31
+:
+0
+]
+IADDR,
+input
+PRESETN,
+input
+PCLK,
+input
+[
+31
+:
+0
+]
+PADDR,
+input
+PWRITE,
+input
+PENABLE,
+input
+PSEL,
+input
+[
+31
+:
+0
+]
+PWDATA,
+output
+wire
+[
+31
+:
+0
+]
+PRDATA,
+output
+wire
+PREADY,
+output
+wire
+PSLVERR,
+output
+reg
+[
+31
+:
+0
+]
+PADDRS,
+output
+wire
+PWRITES,
+output
+wire
+PENABLES,
+output
+wire
+[
+31
+:
+0
+]
+PWDATAS,
+output
+wire
+PSELS0,
+output
+wire
+PSELS1,
+output
+wire
+PSELS2,
+output
+wire
+PSELS3,
+output
+wire
+PSELS4,
+output
+wire
+PSELS5,
+output
+wire
+PSELS6,
+output
+wire
+PSELS7,
+output
+wire
+PSELS8,
+output
+wire
+PSELS9,
+output
+wire
+PSELS10,
+output
+wire
+PSELS11,
+output
+wire
+PSELS12,
+output
+wire
+PSELS13,
+output
+wire
+PSELS14,
+output
+wire
+PSELS15,
+output
+reg
+PSELS16,
+input
+[
+31
+:
+0
+]
+PRDATAS0,
+input
+[
+31
+:
+0
+]
+PRDATAS1,
+input
+[
+31
+:
+0
+]
+PRDATAS2,
+input
+[
+31
+:
+0
+]
+PRDATAS3,
+input
+[
+31
+:
+0
+]
+PRDATAS4,
+input
+[
+31
+:
+0
+]
+PRDATAS5,
+input
+[
+31
+:
+0
+]
+PRDATAS6,
+input
+[
+31
+:
+0
+]
+PRDATAS7,
+input
+[
+31
+:
+0
+]
+PRDATAS8,
+input
+[
+31
+:
+0
+]
+PRDATAS9,
+input
+[
+31
+:
+0
+]
+PRDATAS10,
+input
+[
+31
+:
+0
+]
+PRDATAS11,
+input
+[
+31
+:
+0
+]
+PRDATAS12,
+input
+[
+31
+:
+0
+]
+PRDATAS13,
+input
+[
+31
+:
+0
+]
+PRDATAS14,
+input
+[
+31
+:
+0
+]
+PRDATAS15,
+input
+[
+31
+:
+0
+]
+PRDATAS16,
+input
+PREADYS0,
+input
+PREADYS1,
+input
+PREADYS2,
+input
+PREADYS3,
+input
+PREADYS4,
+input
+PREADYS5,
+input
+PREADYS6,
+input
+PREADYS7,
+input
+PREADYS8,
+input
+PREADYS9,
+input
+PREADYS10,
+input
+PREADYS11,
+input
+PREADYS12,
+input
+PREADYS13,
+input
+PREADYS14,
+input
+PREADYS15,
+input
+PREADYS16,
+input
+PSLVERRS0,
+input
+PSLVERRS1,
+input
+PSLVERRS2,
+input
+PSLVERRS3,
+input
+PSLVERRS4,
+input
+PSLVERRS5,
+input
+PSLVERRS6,
+input
+PSLVERRS7,
+input
+PSLVERRS8,
+input
+PSLVERRS9,
+input
+PSLVERRS10,
+input
+PSLVERRS11,
+input
+PSLVERRS12,
+input
+PSLVERRS13,
+input
+PSLVERRS14,
+input
+PSLVERRS15,
+input
+PSLVERRS16
+)
+;
+localparam
+CAPB3I1I
+=
+0
+;
+localparam
+CAPB3l1I
+=
+1
+;
+localparam
+CAPB3OOl
+=
+2
+;
+localparam
+CAPB3IOl
+=
+3
+;
+localparam
+CAPB3lOl
+=
+4
+;
+localparam
+CAPB3OIl
+=
+5
+;
+localparam
+CAPB3IIl
+=
+6
+;
+localparam
+CAPB3lIl
+=
+7
+;
+localparam
+CAPB3Oll
+=
+8
+;
+localparam
+CAPB3Ill
+=
+9
+;
+localparam
+CAPB3lll
+=
+10
+;
+localparam
+CAPB3O0l
+=
+11
+;
+localparam
+CAPB3I0l
+=
+12
+;
+localparam
+CAPB3l0l
+=
+13
+;
+localparam
+CAPB3O1l
+=
+14
+;
+localparam
+CAPB3I1l
+=
+15
+;
+localparam
+CAPB3l1l
+=
+16
+;
+localparam
+CAPB3OO0
+=
+17
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3IO0
+=
+(
+APBSLOT0ENABLE
+||
+SC_0
+||
+(
+IADDR_OPTION
+==
+CAPB3OOl
+)
+)
+*
+(
+2
+**
+0
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3lO0
+=
+(
+APBSLOT1ENABLE
+||
+SC_1
+||
+(
+IADDR_OPTION
+==
+CAPB3IOl
+)
+)
+*
+(
+2
+**
+1
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3OI0
+=
+(
+APBSLOT2ENABLE
+||
+SC_2
+||
+(
+IADDR_OPTION
+==
+CAPB3lOl
+)
+)
+*
+(
+2
+**
+2
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3II0
+=
+(
+APBSLOT3ENABLE
+||
+SC_3
+||
+(
+IADDR_OPTION
+==
+CAPB3OIl
+)
+)
+*
+(
+2
+**
+3
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3lI0
+=
+(
+APBSLOT4ENABLE
+||
+SC_4
+||
+(
+IADDR_OPTION
+==
+CAPB3IIl
+)
+)
+*
+(
+2
+**
+4
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3Ol0
+=
+(
+APBSLOT5ENABLE
+||
+SC_5
+||
+(
+IADDR_OPTION
+==
+CAPB3lIl
+)
+)
+*
+(
+2
+**
+5
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3Il0
+=
+(
+APBSLOT6ENABLE
+||
+SC_6
+||
+(
+IADDR_OPTION
+==
+CAPB3Oll
+)
+)
+*
+(
+2
+**
+6
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3ll0
+=
+(
+APBSLOT7ENABLE
+||
+SC_7
+||
+(
+IADDR_OPTION
+==
+CAPB3Ill
+)
+)
+*
+(
+2
+**
+7
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3O00
+=
+(
+APBSLOT8ENABLE
+||
+SC_8
+||
+(
+IADDR_OPTION
+==
+CAPB3lll
+)
+)
+*
+(
+2
+**
+8
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3I00
+=
+(
+APBSLOT9ENABLE
+||
+SC_9
+||
+(
+IADDR_OPTION
+==
+CAPB3O0l
+)
+)
+*
+(
+2
+**
+9
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3l00
+=
+(
+APBSLOT10ENABLE
+||
+SC_10
+||
+(
+IADDR_OPTION
+==
+CAPB3I0l
+)
+)
+*
+(
+2
+**
+10
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3O10
+=
+(
+APBSLOT11ENABLE
+||
+SC_11
+||
+(
+IADDR_OPTION
+==
+CAPB3l0l
+)
+)
+*
+(
+2
+**
+11
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3I10
+=
+(
+APBSLOT12ENABLE
+||
+SC_12
+||
+(
+IADDR_OPTION
+==
+CAPB3O1l
+)
+)
+*
+(
+2
+**
+12
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3l10
+=
+(
+APBSLOT13ENABLE
+||
+SC_13
+||
+(
+IADDR_OPTION
+==
+CAPB3I1l
+)
+)
+*
+(
+2
+**
+13
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3OO1
+=
+(
+APBSLOT14ENABLE
+||
+SC_14
+||
+(
+IADDR_OPTION
+==
+CAPB3l1l
+)
+)
+*
+(
+2
+**
+14
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3IO1
+=
+(
+APBSLOT15ENABLE
+||
+SC_15
+||
+(
+IADDR_OPTION
+==
+CAPB3OO0
+)
+)
+*
+(
+2
+**
+15
+)
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3lO1
+=
+{
+SC_15
+,
+SC_14
+,
+SC_13
+,
+SC_12
+,
+SC_11
+,
+SC_10
+,
+SC_9
+,
+SC_8
+,
+SC_7
+,
+SC_6
+,
+SC_5
+,
+SC_4
+,
+SC_3
+,
+SC_2
+,
+SC_1
+,
+SC_0
+}
+;
+localparam
+[
+15
+:
+0
+]
+CAPB3OI1
+=
+CAPB3lO1
+&
+{
+(
+IADDR_OPTION
+!=
+CAPB3OO0
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3l1l
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3I1l
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3O1l
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3l0l
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3I0l
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3O0l
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3lll
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3Ill
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3Oll
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3lIl
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3IIl
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3OIl
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3lOl
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3IOl
+)
+,
+(
+IADDR_OPTION
+!=
+CAPB3OOl
+)
+}
+;
+wire
+[
+31
+:
+0
+]
+CAPB3I0I
+;
+wire
+[
+31
+:
+0
+]
+CAPB3II1
+;
+wire
+[
+31
+:
+0
+]
+CAPB3lI1
+;
+wire
+[
+31
+:
+0
+]
+CAPB3Ol1
+;
+wire
+[
+31
+:
+0
+]
+CAPB3Il1
+;
+wire
+[
+31
+:
+0
+]
+CAPB3ll1
+;
+wire
+[
+31
+:
+0
+]
+CAPB3O01
+;
+wire
+[
+31
+:
+0
+]
+CAPB3I01
+;
+wire
+[
+31
+:
+0
+]
+CAPB3l01
+;
+wire
+[
+31
+:
+0
+]
+CAPB3O11
+;
+wire
+[
+31
+:
+0
+]
+CAPB3I11
+;
+wire
+[
+31
+:
+0
+]
+CAPB3l11
+;
+wire
+[
+31
+:
+0
+]
+CAPB3OOOI
+;
+wire
+[
+31
+:
+0
+]
+CAPB3IOOI
+;
+wire
+[
+31
+:
+0
+]
+CAPB3lOOI
+;
+wire
+[
+31
+:
+0
+]
+CAPB3OIOI
+;
+wire
+[
+31
+:
+0
+]
+CAPB3IIOI
+;
+wire
+[
+31
+:
+0
+]
+CAPB3lIOI
+;
+wire
+[
+15
+:
+0
+]
+CAPB3OlOI
+;
+wire
+[
+15
+:
+0
+]
+CAPB3IlOI
+;
+reg
+[
+15
+:
+0
+]
+CAPB3llOI
+;
+reg
+[
+15
+:
+0
+]
+CAPB3O0OI
+;
+wire
+[
+3
+:
+0
+]
+CAPB3I0OI
+;
+wire
+[
+31
+:
+0
+]
+CAPB3I
+;
+wire
+[
+31
+:
+0
+]
+CAPB3l0OI
+;
+wire
+[
+31
+:
+0
+]
+CAPB3O1OI
+;
+wire
+[
+31
+:
+0
+]
+CAPB3I1OI
+;
+wire
+CAPB3l1OI
+;
+wire
+CAPB3OOII
+;
+assign
+CAPB3I1OI
+=
+32
+'b
+0
+;
+assign
+CAPB3l1OI
+=
+1
+'b
+1
+;
+assign
+CAPB3OOII
+=
+1
+'b
+0
+;
+assign
+PWRITES
+=
+PWRITE
+;
+assign
+PENABLES
+=
+PENABLE
+;
+assign
+PWDATAS
+=
+PWDATA
+[
+31
+:
+0
+]
+;
+assign
+CAPB3I0OI
+=
+PADDR
+[
+MADDR_BITS
+-
+1
+:
+MADDR_BITS
+-
+4
+]
+;
+always
+@(*)
+begin
+if
+(
+PSEL
+==
+1
+'b
+1
+)
+begin
+case
+(
+CAPB3I0OI
+)
+4
+'b
+0000
+:
+CAPB3llOI
+=
+CAPB3IO0
+;
+4
+'b
+0001
+:
+CAPB3llOI
+=
+CAPB3lO0
+;
+4
+'b
+0010
+:
+CAPB3llOI
+=
+CAPB3OI0
+;
+4
+'b
+0011
+:
+CAPB3llOI
+=
+CAPB3II0
+;
+4
+'b
+0100
+:
+CAPB3llOI
+=
+CAPB3lI0
+;
+4
+'b
+0101
+:
+CAPB3llOI
+=
+CAPB3Ol0
+;
+4
+'b
+0110
+:
+CAPB3llOI
+=
+CAPB3Il0
+;
+4
+'b
+0111
+:
+CAPB3llOI
+=
+CAPB3ll0
+;
+4
+'b
+1000
+:
+CAPB3llOI
+=
+CAPB3O00
+;
+4
+'b
+1001
+:
+CAPB3llOI
+=
+CAPB3I00
+;
+4
+'b
+1010
+:
+CAPB3llOI
+=
+CAPB3l00
+;
+4
+'b
+1011
+:
+CAPB3llOI
+=
+CAPB3O10
+;
+4
+'b
+1100
+:
+CAPB3llOI
+=
+CAPB3I10
+;
+4
+'b
+1101
+:
+CAPB3llOI
+=
+CAPB3l10
+;
+4
+'b
+1110
+:
+CAPB3llOI
+=
+CAPB3OO1
+;
+4
+'b
+1111
+:
+CAPB3llOI
+=
+CAPB3IO1
+;
+default
+:
+CAPB3llOI
+=
+16
+'b
+0000000000000000
+;
+endcase
+CAPB3O0OI
+[
+15
+:
+0
+]
+=
+CAPB3llOI
+&
+~
+CAPB3OI1
+;
+PSELS16
+=
+|
+(
+CAPB3llOI
+&
+CAPB3OI1
+)
+;
+end
+else
+begin
+CAPB3O0OI
+=
+16
+'b
+0000000000000000
+;
+PSELS16
+=
+1
+'b
+0
+;
+end
+end
+generate
+begin
+:
+CAPB3IOII
+if
+(
+IADDR_OPTION
+==
+CAPB3OOl
+)
+assign
+CAPB3II1
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT0ENABLE
+)
+assign
+CAPB3II1
+[
+31
+:
+0
+]
+=
+PRDATAS0
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3II1
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IOl
+)
+assign
+CAPB3lI1
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT1ENABLE
+)
+assign
+CAPB3lI1
+[
+31
+:
+0
+]
+=
+PRDATAS1
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3lI1
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lOl
+)
+assign
+CAPB3Ol1
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT2ENABLE
+)
+assign
+CAPB3Ol1
+[
+31
+:
+0
+]
+=
+PRDATAS2
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3Ol1
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OIl
+)
+assign
+CAPB3Il1
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT3ENABLE
+)
+assign
+CAPB3Il1
+[
+31
+:
+0
+]
+=
+PRDATAS3
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3Il1
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IIl
+)
+assign
+CAPB3ll1
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT4ENABLE
+)
+assign
+CAPB3ll1
+[
+31
+:
+0
+]
+=
+PRDATAS4
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3ll1
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lIl
+)
+assign
+CAPB3O01
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT5ENABLE
+)
+assign
+CAPB3O01
+[
+31
+:
+0
+]
+=
+PRDATAS5
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3O01
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Oll
+)
+assign
+CAPB3I01
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT6ENABLE
+)
+assign
+CAPB3I01
+[
+31
+:
+0
+]
+=
+PRDATAS6
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3I01
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Ill
+)
+assign
+CAPB3l01
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT7ENABLE
+)
+assign
+CAPB3l01
+[
+31
+:
+0
+]
+=
+PRDATAS7
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3l01
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lll
+)
+assign
+CAPB3O11
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT8ENABLE
+)
+assign
+CAPB3O11
+[
+31
+:
+0
+]
+=
+PRDATAS8
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3O11
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O0l
+)
+assign
+CAPB3I11
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT9ENABLE
+)
+assign
+CAPB3I11
+[
+31
+:
+0
+]
+=
+PRDATAS9
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3I11
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I0l
+)
+assign
+CAPB3l11
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT10ENABLE
+)
+assign
+CAPB3l11
+[
+31
+:
+0
+]
+=
+PRDATAS10
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3l11
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l0l
+)
+assign
+CAPB3OOOI
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT11ENABLE
+)
+assign
+CAPB3OOOI
+[
+31
+:
+0
+]
+=
+PRDATAS11
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3OOOI
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O1l
+)
+assign
+CAPB3IOOI
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT12ENABLE
+)
+assign
+CAPB3IOOI
+[
+31
+:
+0
+]
+=
+PRDATAS12
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3IOOI
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I1l
+)
+assign
+CAPB3lOOI
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT13ENABLE
+)
+assign
+CAPB3lOOI
+[
+31
+:
+0
+]
+=
+PRDATAS13
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3lOOI
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l1l
+)
+assign
+CAPB3OIOI
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT14ENABLE
+)
+assign
+CAPB3OIOI
+[
+31
+:
+0
+]
+=
+PRDATAS14
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3OIOI
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OO0
+)
+assign
+CAPB3IIOI
+[
+31
+:
+0
+]
+=
+CAPB3lIOI
+[
+31
+:
+0
+]
+;
+else
+if
+(
+APBSLOT15ENABLE
+)
+assign
+CAPB3IIOI
+[
+31
+:
+0
+]
+=
+PRDATAS15
+[
+31
+:
+0
+]
+;
+else
+assign
+CAPB3IIOI
+[
+31
+:
+0
+]
+=
+CAPB3I1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OOl
+)
+assign
+CAPB3OlOI
+[
+0
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT0ENABLE
+)
+assign
+CAPB3OlOI
+[
+0
+]
+=
+PREADYS0
+;
+else
+assign
+CAPB3OlOI
+[
+0
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IOl
+)
+assign
+CAPB3OlOI
+[
+1
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT1ENABLE
+)
+assign
+CAPB3OlOI
+[
+1
+]
+=
+PREADYS1
+;
+else
+assign
+CAPB3OlOI
+[
+1
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lOl
+)
+assign
+CAPB3OlOI
+[
+2
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT2ENABLE
+)
+assign
+CAPB3OlOI
+[
+2
+]
+=
+PREADYS2
+;
+else
+assign
+CAPB3OlOI
+[
+2
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OIl
+)
+assign
+CAPB3OlOI
+[
+3
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT3ENABLE
+)
+assign
+CAPB3OlOI
+[
+3
+]
+=
+PREADYS3
+;
+else
+assign
+CAPB3OlOI
+[
+3
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IIl
+)
+assign
+CAPB3OlOI
+[
+4
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT4ENABLE
+)
+assign
+CAPB3OlOI
+[
+4
+]
+=
+PREADYS4
+;
+else
+assign
+CAPB3OlOI
+[
+4
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lIl
+)
+assign
+CAPB3OlOI
+[
+5
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT5ENABLE
+)
+assign
+CAPB3OlOI
+[
+5
+]
+=
+PREADYS5
+;
+else
+assign
+CAPB3OlOI
+[
+5
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Oll
+)
+assign
+CAPB3OlOI
+[
+6
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT6ENABLE
+)
+assign
+CAPB3OlOI
+[
+6
+]
+=
+PREADYS6
+;
+else
+assign
+CAPB3OlOI
+[
+6
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Ill
+)
+assign
+CAPB3OlOI
+[
+7
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT7ENABLE
+)
+assign
+CAPB3OlOI
+[
+7
+]
+=
+PREADYS7
+;
+else
+assign
+CAPB3OlOI
+[
+7
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lll
+)
+assign
+CAPB3OlOI
+[
+8
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT8ENABLE
+)
+assign
+CAPB3OlOI
+[
+8
+]
+=
+PREADYS8
+;
+else
+assign
+CAPB3OlOI
+[
+8
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O0l
+)
+assign
+CAPB3OlOI
+[
+9
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT9ENABLE
+)
+assign
+CAPB3OlOI
+[
+9
+]
+=
+PREADYS9
+;
+else
+assign
+CAPB3OlOI
+[
+9
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I0l
+)
+assign
+CAPB3OlOI
+[
+10
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT10ENABLE
+)
+assign
+CAPB3OlOI
+[
+10
+]
+=
+PREADYS10
+;
+else
+assign
+CAPB3OlOI
+[
+10
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l0l
+)
+assign
+CAPB3OlOI
+[
+11
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT11ENABLE
+)
+assign
+CAPB3OlOI
+[
+11
+]
+=
+PREADYS11
+;
+else
+assign
+CAPB3OlOI
+[
+11
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O1l
+)
+assign
+CAPB3OlOI
+[
+12
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT12ENABLE
+)
+assign
+CAPB3OlOI
+[
+12
+]
+=
+PREADYS12
+;
+else
+assign
+CAPB3OlOI
+[
+12
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I1l
+)
+assign
+CAPB3OlOI
+[
+13
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT13ENABLE
+)
+assign
+CAPB3OlOI
+[
+13
+]
+=
+PREADYS13
+;
+else
+assign
+CAPB3OlOI
+[
+13
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l1l
+)
+assign
+CAPB3OlOI
+[
+14
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT14ENABLE
+)
+assign
+CAPB3OlOI
+[
+14
+]
+=
+PREADYS14
+;
+else
+assign
+CAPB3OlOI
+[
+14
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OO0
+)
+assign
+CAPB3OlOI
+[
+15
+]
+=
+CAPB3l1OI
+;
+else
+if
+(
+APBSLOT15ENABLE
+)
+assign
+CAPB3OlOI
+[
+15
+]
+=
+PREADYS15
+;
+else
+assign
+CAPB3OlOI
+[
+15
+]
+=
+CAPB3l1OI
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OOl
+)
+assign
+CAPB3IlOI
+[
+0
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT0ENABLE
+)
+assign
+CAPB3IlOI
+[
+0
+]
+=
+PSLVERRS0
+;
+else
+assign
+CAPB3IlOI
+[
+0
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IOl
+)
+assign
+CAPB3IlOI
+[
+1
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT1ENABLE
+)
+assign
+CAPB3IlOI
+[
+1
+]
+=
+PSLVERRS1
+;
+else
+assign
+CAPB3IlOI
+[
+1
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lOl
+)
+assign
+CAPB3IlOI
+[
+2
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT2ENABLE
+)
+assign
+CAPB3IlOI
+[
+2
+]
+=
+PSLVERRS2
+;
+else
+assign
+CAPB3IlOI
+[
+2
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OIl
+)
+assign
+CAPB3IlOI
+[
+3
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT3ENABLE
+)
+assign
+CAPB3IlOI
+[
+3
+]
+=
+PSLVERRS3
+;
+else
+assign
+CAPB3IlOI
+[
+3
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IIl
+)
+assign
+CAPB3IlOI
+[
+4
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT4ENABLE
+)
+assign
+CAPB3IlOI
+[
+4
+]
+=
+PSLVERRS4
+;
+else
+assign
+CAPB3IlOI
+[
+4
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lIl
+)
+assign
+CAPB3IlOI
+[
+5
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT5ENABLE
+)
+assign
+CAPB3IlOI
+[
+5
+]
+=
+PSLVERRS5
+;
+else
+assign
+CAPB3IlOI
+[
+5
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Oll
+)
+assign
+CAPB3IlOI
+[
+6
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT6ENABLE
+)
+assign
+CAPB3IlOI
+[
+6
+]
+=
+PSLVERRS6
+;
+else
+assign
+CAPB3IlOI
+[
+6
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Ill
+)
+assign
+CAPB3IlOI
+[
+7
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT7ENABLE
+)
+assign
+CAPB3IlOI
+[
+7
+]
+=
+PSLVERRS7
+;
+else
+assign
+CAPB3IlOI
+[
+7
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lll
+)
+assign
+CAPB3IlOI
+[
+8
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT8ENABLE
+)
+assign
+CAPB3IlOI
+[
+8
+]
+=
+PSLVERRS8
+;
+else
+assign
+CAPB3IlOI
+[
+8
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O0l
+)
+assign
+CAPB3IlOI
+[
+9
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT9ENABLE
+)
+assign
+CAPB3IlOI
+[
+9
+]
+=
+PSLVERRS9
+;
+else
+assign
+CAPB3IlOI
+[
+9
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I0l
+)
+assign
+CAPB3IlOI
+[
+10
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT10ENABLE
+)
+assign
+CAPB3IlOI
+[
+10
+]
+=
+PSLVERRS10
+;
+else
+assign
+CAPB3IlOI
+[
+10
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l0l
+)
+assign
+CAPB3IlOI
+[
+11
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT11ENABLE
+)
+assign
+CAPB3IlOI
+[
+11
+]
+=
+PSLVERRS11
+;
+else
+assign
+CAPB3IlOI
+[
+11
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O1l
+)
+assign
+CAPB3IlOI
+[
+12
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT12ENABLE
+)
+assign
+CAPB3IlOI
+[
+12
+]
+=
+PSLVERRS12
+;
+else
+assign
+CAPB3IlOI
+[
+12
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I1l
+)
+assign
+CAPB3IlOI
+[
+13
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT13ENABLE
+)
+assign
+CAPB3IlOI
+[
+13
+]
+=
+PSLVERRS13
+;
+else
+assign
+CAPB3IlOI
+[
+13
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l1l
+)
+assign
+CAPB3IlOI
+[
+14
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT14ENABLE
+)
+assign
+CAPB3IlOI
+[
+14
+]
+=
+PSLVERRS14
+;
+else
+assign
+CAPB3IlOI
+[
+14
+]
+=
+CAPB3OOII
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OO0
+)
+assign
+CAPB3IlOI
+[
+15
+]
+=
+CAPB3OOII
+;
+else
+if
+(
+APBSLOT15ENABLE
+)
+assign
+CAPB3IlOI
+[
+15
+]
+=
+PSLVERRS15
+;
+else
+assign
+CAPB3IlOI
+[
+15
+]
+=
+CAPB3OOII
+;
+end
+endgenerate
+CAPB3l
+CAPB3lOII
+(
+.CAPB3OI
+(
+{
+PSELS16
+,
+CAPB3O0OI
+[
+15
+:
+0
+]
+}
+)
+,
+.PRDATAS0
+(
+CAPB3II1
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS1
+(
+CAPB3lI1
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS2
+(
+CAPB3Ol1
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS3
+(
+CAPB3Il1
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS4
+(
+CAPB3ll1
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS5
+(
+CAPB3O01
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS6
+(
+CAPB3I01
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS7
+(
+CAPB3l01
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS8
+(
+CAPB3O11
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS9
+(
+CAPB3I11
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS10
+(
+CAPB3l11
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS11
+(
+CAPB3OOOI
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS12
+(
+CAPB3IOOI
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS13
+(
+CAPB3lOOI
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS14
+(
+CAPB3OIOI
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS15
+(
+CAPB3IIOI
+[
+31
+:
+0
+]
+)
+,
+.PRDATAS16
+(
+PRDATAS16
+[
+31
+:
+0
+]
+)
+,
+.CAPB3II
+(
+{
+PREADYS16
+,
+CAPB3OlOI
+[
+15
+:
+0
+]
+}
+)
+,
+.CAPB3lI
+(
+{
+PSLVERRS16
+,
+CAPB3IlOI
+[
+15
+:
+0
+]
+}
+)
+,
+.PREADY
+(
+PREADY
+)
+,
+.PSLVERR
+(
+PSLVERR
+)
+,
+.PRDATA
+(
+CAPB3I0I
+[
+31
+:
+0
+]
+)
+)
+;
+assign
+PRDATA
+[
+31
+:
+0
+]
+=
+CAPB3I0I
+[
+31
+:
+0
+]
+;
+generate
+begin
+:
+CAPB3OIII
+if
+(
+IADDR_OPTION
+==
+CAPB3OOl
+)
+assign
+PSELS0
+=
+1
+'b
+0
+;
+else
+assign
+PSELS0
+=
+CAPB3O0OI
+[
+0
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IOl
+)
+assign
+PSELS1
+=
+1
+'b
+0
+;
+else
+assign
+PSELS1
+=
+CAPB3O0OI
+[
+1
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lOl
+)
+assign
+PSELS2
+=
+1
+'b
+0
+;
+else
+assign
+PSELS2
+=
+CAPB3O0OI
+[
+2
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OIl
+)
+assign
+PSELS3
+=
+1
+'b
+0
+;
+else
+assign
+PSELS3
+=
+CAPB3O0OI
+[
+3
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IIl
+)
+assign
+PSELS4
+=
+1
+'b
+0
+;
+else
+assign
+PSELS4
+=
+CAPB3O0OI
+[
+4
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lIl
+)
+assign
+PSELS5
+=
+1
+'b
+0
+;
+else
+assign
+PSELS5
+=
+CAPB3O0OI
+[
+5
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Oll
+)
+assign
+PSELS6
+=
+1
+'b
+0
+;
+else
+assign
+PSELS6
+=
+CAPB3O0OI
+[
+6
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Ill
+)
+assign
+PSELS7
+=
+1
+'b
+0
+;
+else
+assign
+PSELS7
+=
+CAPB3O0OI
+[
+7
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lll
+)
+assign
+PSELS8
+=
+1
+'b
+0
+;
+else
+assign
+PSELS8
+=
+CAPB3O0OI
+[
+8
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O0l
+)
+assign
+PSELS9
+=
+1
+'b
+0
+;
+else
+assign
+PSELS9
+=
+CAPB3O0OI
+[
+9
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I0l
+)
+assign
+PSELS10
+=
+1
+'b
+0
+;
+else
+assign
+PSELS10
+=
+CAPB3O0OI
+[
+10
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l0l
+)
+assign
+PSELS11
+=
+1
+'b
+0
+;
+else
+assign
+PSELS11
+=
+CAPB3O0OI
+[
+11
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O1l
+)
+assign
+PSELS12
+=
+1
+'b
+0
+;
+else
+assign
+PSELS12
+=
+CAPB3O0OI
+[
+12
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I1l
+)
+assign
+PSELS13
+=
+1
+'b
+0
+;
+else
+assign
+PSELS13
+=
+CAPB3O0OI
+[
+13
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l1l
+)
+assign
+PSELS14
+=
+1
+'b
+0
+;
+else
+assign
+PSELS14
+=
+CAPB3O0OI
+[
+14
+]
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OO0
+)
+assign
+PSELS15
+=
+1
+'b
+0
+;
+else
+assign
+PSELS15
+=
+CAPB3O0OI
+[
+15
+]
+;
+end
+endgenerate
+generate
+begin
+:
+CAPB3IIII
+if
+(
+IADDR_OPTION
+==
+CAPB3I1I
+)
+assign
+CAPB3I
+=
+32
+'b
+0
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l1I
+)
+assign
+CAPB3I
+=
+32
+'b
+0
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OOl
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+0
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IOl
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+1
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lOl
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+2
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OIl
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+3
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3IIl
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+4
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lIl
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+5
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Oll
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+6
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3Ill
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+7
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3lll
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+8
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O0l
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+9
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I0l
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+10
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l0l
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+11
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3O1l
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+12
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3I1l
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+13
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3l1l
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+14
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+if
+(
+IADDR_OPTION
+==
+CAPB3OO0
+)
+CAPB3O
+#
+(
+APB_DWIDTH
+,
+MADDR_BITS
+)
+CAPB3lIII
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+CAPB3O0OI
+[
+15
+]
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+CAPB3lIOI
+,
+CAPB3I
+)
+;
+end
+endgenerate
+generate
+begin
+if
+(
+IADDR_OPTION
+==
+CAPB3I1I
+)
+begin
+assign
+CAPB3O1OI
+=
+PADDR
+;
+assign
+CAPB3l0OI
+=
+32
+'b
+0
+;
+end
+else
+if
+(
+IADDR_OPTION
+==
+CAPB3l1I
+)
+begin
+assign
+CAPB3O1OI
+=
+IADDR
+;
+assign
+CAPB3l0OI
+=
+IADDR
+;
+end
+else
+begin
+assign
+CAPB3O1OI
+=
+CAPB3I
+;
+assign
+CAPB3l0OI
+=
+CAPB3I
+;
+end
+end
+endgenerate
+generate
+if
+(
+MADDR_BITS
+==
+12
+)
+begin
+always
+@(*)
+case
+(
+UPR_NIBBLE_POSN
+)
+2
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+12
+]
+,
+PADDR
+[
+11
+:
+0
+]
+}
+;
+3
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+16
+]
+,
+PADDR
+[
+11
+:
+8
+]
+,
+CAPB3l0OI
+[
+11
+:
+8
+]
+,
+PADDR
+[
+7
+:
+0
+]
+}
+;
+4
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+20
+]
+,
+PADDR
+[
+11
+:
+8
+]
+,
+CAPB3l0OI
+[
+15
+:
+8
+]
+,
+PADDR
+[
+7
+:
+0
+]
+}
+;
+5
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+24
+]
+,
+PADDR
+[
+11
+:
+8
+]
+,
+CAPB3l0OI
+[
+19
+:
+8
+]
+,
+PADDR
+[
+7
+:
+0
+]
+}
+;
+6
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+11
+:
+8
+]
+,
+CAPB3l0OI
+[
+23
+:
+8
+]
+,
+PADDR
+[
+7
+:
+0
+]
+}
+;
+7
+:
+PADDRS
+=
+{
+PADDR
+[
+11
+:
+8
+]
+,
+CAPB3l0OI
+[
+27
+:
+8
+]
+,
+PADDR
+[
+7
+:
+0
+]
+}
+;
+8
+:
+PADDRS
+=
+{
+CAPB3l0OI
+[
+31
+:
+8
+]
+,
+PADDR
+[
+7
+:
+0
+]
+}
+;
+endcase
+end
+endgenerate
+generate
+if
+(
+MADDR_BITS
+==
+16
+)
+begin
+always
+@(*)
+case
+(
+UPR_NIBBLE_POSN
+)
+2
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+16
+]
+,
+PADDR
+[
+15
+:
+0
+]
+}
+;
+3
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+16
+]
+,
+PADDR
+[
+15
+:
+0
+]
+}
+;
+4
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+20
+]
+,
+PADDR
+[
+15
+:
+12
+]
+,
+CAPB3l0OI
+[
+15
+:
+12
+]
+,
+PADDR
+[
+11
+:
+0
+]
+}
+;
+5
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+24
+]
+,
+PADDR
+[
+15
+:
+12
+]
+,
+CAPB3l0OI
+[
+19
+:
+12
+]
+,
+PADDR
+[
+11
+:
+0
+]
+}
+;
+6
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+15
+:
+12
+]
+,
+CAPB3l0OI
+[
+23
+:
+12
+]
+,
+PADDR
+[
+11
+:
+0
+]
+}
+;
+7
+:
+PADDRS
+=
+{
+PADDR
+[
+15
+:
+12
+]
+,
+CAPB3l0OI
+[
+27
+:
+12
+]
+,
+PADDR
+[
+11
+:
+0
+]
+}
+;
+8
+:
+PADDRS
+=
+{
+CAPB3l0OI
+[
+31
+:
+12
+]
+,
+PADDR
+[
+11
+:
+0
+]
+}
+;
+endcase
+end
+endgenerate
+generate
+if
+(
+MADDR_BITS
+==
+20
+)
+begin
+always
+@(*)
+case
+(
+UPR_NIBBLE_POSN
+)
+2
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+20
+]
+,
+PADDR
+[
+19
+:
+0
+]
+}
+;
+3
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+20
+]
+,
+PADDR
+[
+19
+:
+0
+]
+}
+;
+4
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+20
+]
+,
+PADDR
+[
+19
+:
+0
+]
+}
+;
+5
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+24
+]
+,
+PADDR
+[
+19
+:
+16
+]
+,
+CAPB3l0OI
+[
+19
+:
+16
+]
+,
+PADDR
+[
+15
+:
+0
+]
+}
+;
+6
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+19
+:
+16
+]
+,
+CAPB3l0OI
+[
+23
+:
+16
+]
+,
+PADDR
+[
+15
+:
+0
+]
+}
+;
+7
+:
+PADDRS
+=
+{
+PADDR
+[
+19
+:
+16
+]
+,
+CAPB3l0OI
+[
+27
+:
+16
+]
+,
+PADDR
+[
+15
+:
+0
+]
+}
+;
+8
+:
+PADDRS
+=
+{
+CAPB3l0OI
+[
+31
+:
+16
+]
+,
+PADDR
+[
+15
+:
+0
+]
+}
+;
+endcase
+end
+endgenerate
+generate
+if
+(
+MADDR_BITS
+==
+24
+)
+begin
+always
+@(*)
+case
+(
+UPR_NIBBLE_POSN
+)
+2
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+24
+]
+,
+PADDR
+[
+23
+:
+0
+]
+}
+;
+3
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+24
+]
+,
+PADDR
+[
+23
+:
+0
+]
+}
+;
+4
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+24
+]
+,
+PADDR
+[
+23
+:
+0
+]
+}
+;
+5
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+24
+]
+,
+PADDR
+[
+23
+:
+0
+]
+}
+;
+6
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+23
+:
+20
+]
+,
+CAPB3l0OI
+[
+23
+:
+20
+]
+,
+PADDR
+[
+19
+:
+0
+]
+}
+;
+7
+:
+PADDRS
+=
+{
+PADDR
+[
+23
+:
+20
+]
+,
+CAPB3l0OI
+[
+27
+:
+20
+]
+,
+PADDR
+[
+19
+:
+0
+]
+}
+;
+8
+:
+PADDRS
+=
+{
+CAPB3l0OI
+[
+31
+:
+20
+]
+,
+PADDR
+[
+19
+:
+0
+]
+}
+;
+endcase
+end
+endgenerate
+generate
+if
+(
+MADDR_BITS
+==
+28
+)
+begin
+always
+@(*)
+case
+(
+UPR_NIBBLE_POSN
+)
+2
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+27
+:
+0
+]
+}
+;
+3
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+27
+:
+0
+]
+}
+;
+4
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+27
+:
+0
+]
+}
+;
+5
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+27
+:
+0
+]
+}
+;
+6
+:
+PADDRS
+=
+{
+CAPB3O1OI
+[
+31
+:
+28
+]
+,
+PADDR
+[
+27
+:
+0
+]
+}
+;
+7
+:
+PADDRS
+=
+{
+PADDR
+[
+27
+:
+24
+]
+,
+CAPB3l0OI
+[
+27
+:
+24
+]
+,
+PADDR
+[
+23
+:
+0
+]
+}
+;
+8
+:
+PADDRS
+=
+{
+CAPB3l0OI
+[
+31
+:
+24
+]
+,
+PADDR
+[
+23
+:
+0
+]
+}
+;
+endcase
+end
+endgenerate
+generate
+if
+(
+MADDR_BITS
+==
+32
+)
+begin
+always
+@(*)
+PADDRS
+=
+PADDR
+[
+31
+:
+0
+]
+;
+end
+endgenerate
+endmodule
+"
+"// Microsemi Corporation Proprietary and Confidential
+// Copyright 2011 Microsemi Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
+// IN ADVANCE IN WRITING.
+// SVN Revision Information:
+// SVN $Revision: 17936 $
+// SVN $Date: 2012-10-05 07:28:51 -0700 (Fri, 05 Oct 2012) $
+module
+CAPB3O
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+PSEL
+,
+PADDR
+,
+PWRITE
+,
+PWDATA
+,
+PRDATA
+,
+CAPB3I
+)
+;
+parameter
+[
+5
+:
+0
+]
+APB_DWIDTH
+=
+32
+;
+parameter
+[
+5
+:
+0
+]
+MADDR_BITS
+=
+32
+;
+input
+PCLK
+;
+input
+PRESETN
+;
+input
+PENABLE
+;
+input
+PSEL
+;
+input
+[
+31
+:
+0
+]
+PADDR
+;
+input
+PWRITE
+;
+input
+[
+31
+:
+0
+]
+PWDATA
+;
+output
+[
+31
+:
+0
+]
+PRDATA
+;
+output
+[
+31
+:
+0
+]
+CAPB3I
+;
+reg
+[
+31
+:
+0
+]
+PRDATA
+;
+reg
+[
+31
+:
+0
+]
+CAPB3I
+;
+always
+@
+(
+posedge
+PCLK
+or
+negedge
+PRESETN
+)
+begin
+if
+(
+!
+PRESETN
+)
+begin
+CAPB3I
+<=
+32
+'b
+0
+;
+end
+else
+begin
+if
+(
+PSEL
+&&
+PENABLE
+&&
+PWRITE
+)
+begin
+if
+(
+APB_DWIDTH
+==
+32
+)
+begin
+if
+(
+PADDR
+[
+MADDR_BITS
+-
+4
+-
+1
+:
+0
+]
+==
+{
+MADDR_BITS
+-
+4
+{
+1
+'b
+0
+}
+}
+)
+begin
+CAPB3I
+<=
+PWDATA
+;
+end
+end
+if
+(
+APB_DWIDTH
+==
+16
+)
+begin
+if
+(
+PADDR
+[
+MADDR_BITS
+-
+4
+-
+1
+:
+4
+]
+==
+{
+MADDR_BITS
+-
+4
+-
+4
+{
+1
+'b
+0
+}
+}
+)
+begin
+case
+(
+PADDR
+[
+3
+:
+0
+]
+)
+4
+'b
+0000
+:
+CAPB3I
+[
+15
+:
+0
+]
+<=
+PWDATA
+[
+15
+:
+0
+]
+;
+4
+'b
+0100
+:
+CAPB3I
+[
+31
+:
+16
+]
+<=
+PWDATA
+[
+15
+:
+0
+]
+;
+4
+'b
+1000
+:
+CAPB3I
+<=
+CAPB3I
+;
+4
+'b
+1100
+:
+CAPB3I
+<=
+CAPB3I
+;
+endcase
+end
+end
+if
+(
+APB_DWIDTH
+==
+8
+)
+begin
+if
+(
+PADDR
+[
+MADDR_BITS
+-
+4
+-
+1
+:
+4
+]
+==
+{
+MADDR_BITS
+-
+4
+-
+4
+{
+1
+'b
+0
+}
+}
+)
+begin
+case
+(
+PADDR
+[
+3
+:
+0
+]
+)
+4
+'b
+0000
+:
+CAPB3I
+[
+7
+:
+0
+]
+<=
+PWDATA
+[
+7
+:
+0
+]
+;
+4
+'b
+0100
+:
+CAPB3I
+[
+15
+:
+8
+]
+<=
+PWDATA
+[
+7
+:
+0
+]
+;
+4
+'b
+1000
+:
+CAPB3I
+[
+23
+:
+16
+]
+<=
+PWDATA
+[
+7
+:
+0
+]
+;
+4
+'b
+1100
+:
+CAPB3I
+[
+31
+:
+24
+]
+<=
+PWDATA
+[
+7
+:
+0
+]
+;
+endcase
+end
+end
+end
+end
+end
+always
+@(*)
+begin
+PRDATA
+=
+32
+'b
+0
+;
+if
+(
+APB_DWIDTH
+==
+32
+)
+begin
+if
+(
+PADDR
+[
+MADDR_BITS
+-
+4
+-
+1
+:
+0
+]
+==
+{
+MADDR_BITS
+-
+4
+{
+1
+'b
+0
+}
+}
+)
+begin
+PRDATA
+=
+CAPB3I
+;
+end
+end
+if
+(
+APB_DWIDTH
+==
+16
+)
+begin
+if
+(
+PADDR
+[
+MADDR_BITS
+-
+4
+-
+1
+:
+4
+]
+==
+{
+MADDR_BITS
+-
+4
+-
+4
+{
+1
+'b
+0
+}
+}
+)
+begin
+case
+(
+PADDR
+[
+3
+:
+0
+]
+)
+4
+'b
+0000
+:
+PRDATA
+[
+15
+:
+0
+]
+=
+CAPB3I
+[
+15
+:
+0
+]
+;
+4
+'b
+0100
+:
+PRDATA
+[
+15
+:
+0
+]
+=
+CAPB3I
+[
+31
+:
+16
+]
+;
+4
+'b
+1000
+:
+PRDATA
+=
+32
+'b
+0
+;
+4
+'b
+1100
+:
+PRDATA
+=
+32
+'b
+0
+;
+endcase
+end
+end
+if
+(
+APB_DWIDTH
+==
+8
+)
+begin
+if
+(
+PADDR
+[
+MADDR_BITS
+-
+4
+-
+1
+:
+4
+]
+==
+{
+MADDR_BITS
+-
+4
+-
+4
+{
+1
+'b
+0
+}
+}
+)
+begin
+case
+(
+PADDR
+[
+3
+:
+0
+]
+)
+4
+'b
+0000
+:
+PRDATA
+[
+7
+:
+0
+]
+=
+CAPB3I
+[
+7
+:
+0
+]
+;
+4
+'b
+0100
+:
+PRDATA
+[
+7
+:
+0
+]
+=
+CAPB3I
+[
+15
+:
+8
+]
+;
+4
+'b
+1000
+:
+PRDATA
+[
+7
+:
+0
+]
+=
+CAPB3I
+[
+23
+:
+16
+]
+;
+4
+'b
+1100
+:
+PRDATA
+[
+7
+:
+0
+]
+=
+CAPB3I
+[
+31
+:
+24
+]
+;
+endcase
+end
+end
+end
+endmodule
+"
+"// ********************************************************************/
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
+// IN ADVANCE IN WRITING.
+//
+//
+// SPI Register file
+//
+// Revision Information:
+// Date     Description
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+// Resolved SARs
+// SAR      Date     Who   Description
+//
+// Notes:
+//
+//
+// *********************************************************************/
+
+
+
+
+
+module spi_rf # (
+  parameter APB_DWIDTH = 8
+)(   //APB Access to registers
+                 input             pclk,
+                 input             presetn,
+                 input [6:0]       paddr,
+                 input             psel,
+                 input             pwrite,
+                 input             penable,
+                 input [APB_DWIDTH-1:0]      wrdata,
+                 output [APB_DWIDTH-1:0]     prdata,
+                 output            interrupt,
+
+                 //Hardware Status
+                 input             tx_channel_underflow,  
+                 input             rx_channel_overflow,   
+                 input             tx_done,               
+                 input             rx_done,               
+                 input             rx_fifo_read,
+                 input             tx_fifo_read,
+                 input             tx_fifo_write,
+
+                 input             rx_fifo_full,
+                 input             rx_fifo_full_next,
+                 input             rx_fifo_empty,
+                 input             rx_fifo_empty_next,
+
+                 input             tx_fifo_full,
+                 input             tx_fifo_full_next,
+                 input             tx_fifo_empty,
+                 input             tx_fifo_empty_next,
+                 input             first_frame,
+
+                 //input             frames_done_fill, 
+                 //input             frames_done_empty, 
+                 input             ssel,
+                 //input             hw_txbusy,
+                 //input             hw_rxbusy,
+                 input             active,
+                 input             rx_pktend,
+                 input             rx_cmdsize,
+
+                 // -----------------------------------------------
+                 // AS: removed a bunch of flags
+                 // -----------------------------------------------
+                 
+                 //Static Configuration Outputs
+                 output            cfg_enable,
+                 //output     [1:0]  cfg_mode,
+                 output            cfg_master,
+                 //output            cfg_spo,
+                 //output            cfg_sph,
+                 //output            cfg_sps,
+                 //output reg [5:0]  cfg_framesize,
+                 //output            cfg_clkmode,
+                 //output reg [7:0]  cfg_clkrate,
+                 //output     [15:0] cfg_framecnt,
+                 output reg [7:0]  cfg_ssel,
+                 //output reg [1:0]  cfg_fifosize,
+                 output      [2:0]  cfg_cmdsize, 
+                 //output reg [5:0]  cfg_pktsize, 
+                 output            cfg_oenoff,
+
+                 //Strobe Outputs, will change during operation
+                 output reg        clr_txfifo, 
+                 output reg        clr_rxfifo,
+                 //output reg        auto_fill,
+                 //output reg        auto_empty,
+                 //output reg        auto_stall,
+                 //output reg        auto_txnow,
+                 //output            cfg_autopoll,
+                 //output            cfg_autostatus,
+                 output            cfg_frameurun
+                 //output reg [1:0]  cfg_userstatus,
+                 //output reg        clr_framecnt
+
+);
+
+
+reg   [7:0] control1;        
+reg   [7:0]  control2;       
+wire  [5:0]  command;       
+wire  [7:0]  int_masked;
+reg   [7:0]  int_raw;
+wire  [7:0]  status_byte;
+reg   [1:0]  sticky;
+reg   [APB_DWIDTH-1:0] rdata;        
+//wire  cfg_disfrmcnt;
+//wire  cfg_bigfifo;
+
+// -----------------------------------------------------------------------------------------------------------------------
+// Registers with sticky bits (The interrupt register)
+
+//interrupt generation
+
+// AS: modified Masked Interrupt register (control 2 register)
+//assign  int_masked =    { (1'b0 ),
+//                          (1'b0 ), 
+//                          (int_raw[5] &&  control2[5]), 
+//                          (int_raw[4] &&  control2[4]),                         
+//                          (int_raw[3] &&  control1[7]),
+//                          (int_raw[2] &&  control1[6]), 
+//                          (int_raw[1] &&  control1[4]), 
+//                          (int_raw[0] &&  control1[5]) 
+//                        };
+
+assign  int_masked =    { 
+                          (int_raw[7] &&  control2[7]),         // !tx_fifo_full
+                          (int_raw[6] &&  control2[6]),         // !rx_fifo_empty
+                          (int_raw[5] &&  control2[5]),         // ssend
+                          (int_raw[4] &&  control2[4]),         // cmdint         
+                          (int_raw[3] &&  control1[5]),         // txunderrun
+                          (int_raw[2] &&  control1[4]),         // rxoverflow
+\t\t\t\t\t\t  (1'b0),\t//PL : added
+\t\t\t\t\t\t  // PL: Removed rx_done signal
+                          //(int_raw[1] &&  control1[2]),  
+                          (int_raw[0] &&  control1[3])          // txdone
+                        };
+                                             
+assign interrupt =   int_masked[7] || int_masked[6] || int_masked[5] || int_masked[4] || 
+                     int_masked[3] || int_masked[2] || int_masked[1] || int_masked[0] ;
+ 
+
+// ############################################################################################################
+// Create Register Values 
+
+   
+assign status_byte = { active,
+                       ssel,
+                       int_raw[3],
+                       int_raw[2],
+                       tx_fifo_full,
+                       rx_fifo_empty,\t\t\t\t\t  
+\t\t\t\t\t  (sticky[0] && sticky[1]),
+                       first_frame
+                     };
+
+// AS: command is now write-only
+assign command  = 8'h00;
+
+   
+// ############################################################################################################
+// Writes. 
+
+integer i;
+
+always @(posedge pclk or negedge presetn)
+  begin
+    if (!presetn)
+      begin
+       control1       <= 8'h00;
+       cfg_ssel       <= 8'h00;
+       control2       <= 8'h00;
+       clr_rxfifo     <= 1'b0;  
+       clr_txfifo     <= 1'b0;  
+       int_raw        <= 8'h00; 
+       sticky         <= 2'b00;
+      end
+    else
+      begin
+
+        //------------------------------------------------------------------------
+        // Hardware Events lower priority than CPU activities
+        
+        clr_rxfifo   <= 1'b0;
+        clr_txfifo   <= 1'b0;
+        //clr_framecnt <= cfg_disfrmcnt;
+
+        //-----------------------------------------------------------------------
+        // CPU Writes
+        if (psel & pwrite & penable)
+          begin
+             case (paddr) //synthesis parallel_case
+             7'h00:  begin
+                       control1[7:0] <= wrdata[7:0];    
+                     end
+             7'h04:  begin
+                       for (i=0; i<8; i=i+1) if (wrdata[i]) int_raw[i] <= 1'b0;
+                     end
+             7'h18:  begin
+                       control2      <= wrdata[7:0];
+                     end
+             7'h1c:  begin
+                       clr_rxfifo  <= wrdata[0];
+                       clr_txfifo  <= wrdata[1];
+                     end
+             7'h24:  cfg_ssel       <= wrdata[7:0];  
+             default:  begin end
+           endcase
+           //if we were enabled dont allow various changes
+          end
+        
+        //------------------------------------------------------------------------
+        // Hardware Events higher proirity than CPU activities
+
+        // Clear off the auto bits
+        // AS: removed auto bits
+        // if (frames_done_fill==1'b1)                 auto_fill  <= 1'b0;
+        // if (cfg_master && frames_done_empty==1'b1)  auto_empty <= 1'b0;  
+        // if (!cfg_master && rx_pktend)               auto_empty <= 1'b0;  
+        // if (tx_fifo_read==1'b1)                     auto_stall <= 1'b0;
+        // if (tx_fifo_read==1'b1)                     auto_txnow <= 1'b0;
+     
+        // Sticky Status Bits 
+        if (tx_done)              sticky[0]  <= 1'b1;
+\t\tif (rx_done)              sticky[1]  <= 1'b1;
+        if (tx_fifo_write)        sticky[0]  <= 1'b0; 
+        if (rx_fifo_read)         sticky[1]  <= 1'b0;
+       
+        // Interrupt Settings
+        if (tx_done)              int_raw[0]  <= 1'b1;
+\t\tif (rx_done)              int_raw[1]  <= 1'b1;
+        if (rx_channel_overflow)  int_raw[2]  <= 1'b1;
+        if (tx_channel_underflow) int_raw[3]  <= 1'b1;  
+        if (rx_cmdsize)           int_raw[4]  <= 1'b1;                
+        if (rx_pktend)            int_raw[5]  <= 1'b1;                
+        if (!rx_fifo_empty)       int_raw[6]  <= 1'b1;                
+        if (!tx_fifo_full)        int_raw[7]  <= 1'b1;                
+        
+        //Unused interrupts
+//        int_raw[7:6] <= 2'b00;          
+     
+        //------------------------------------------------------------------------
+        // Unused Control bits
+//        control2[7:6]  <= 2'b00;
+        control2[3]    <= 1'b0;
+      end
+ end
+
+
+// 5:2 are interrupt enables     
+assign cfg_enable     = control1[0];        
+assign cfg_master     = control1[1];       
+assign cfg_frameurun  = control1[6];
+assign cfg_oenoff     = control1[7];
+assign cfg_cmdsize    = control2[2:0];
+
+// ############################################################################################################
+// Reads, purely combinational of the PADDR. 
+
+localparam [APB_DWIDTH-1:0] ZEROS = {(APB_DWIDTH){1'b0}};
+
+always @(*)
+ begin
+     if (psel)    
+       begin   
+         case (paddr) //synthesis parallel_case
+          7'h00:  rdata[7:0] = control1[7:0];     // control register 1
+          7'h04:  rdata[7:0] = 8'h00;             // write-only
+                                                  // 0x08 assigned elsewhere
+          7'h0C:  rdata[7:0] = 8'h00;             // write-only
+          7'h10:  rdata[7:0] = int_masked[7:0];   // masked interrupt register
+          7'h14:  rdata[7:0] = int_raw[7:0];      // raw interrupt register
+          7'h18:  rdata[7:0] = control2[7:0];     // control register 2
+          7'h20:  rdata[7:0] = status_byte[7:0];  // status register
+          7'h24:  rdata[7:0] = cfg_ssel[7:0];     // slave select register
+         default: rdata = ZEROS;
+         endcase
+       end
+     else
+        rdata = ZEROS;    
+ end
+
+assign prdata = ( (psel && penable) ? rdata : ZEROS);
+
+
+
+endmodule
+
+
+"
+"// ********************************************************************/ 
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+//  
+//
+// SPI Top level control.
+//
+// Revision Information:
+// Date     Description
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+// Resolved SARs
+// SAR      Date     Who   Description
+//
+// Notes: 
+//
+//
+// *********************************************************************/ 
+
+// ------------------------------------------------------
+// AS:
+// - remove auto fill and auto empty ports/ function
+// - remove frame count and associated signals
+// - remove tx_fifo_
+// ------------------------------------------------------
+
+module spi_control # (
+  // AS: added parameters
+  parameter     CFG_FRAME_SIZE    = 4
+)(  input         pclk,
+                     input         presetn,
+                     input         psel,
+                     input         penable,
+                     input         pwrite,
+                     input  [6:0]  paddr,
+                     input  [CFG_FRAME_SIZE-1:0] wr_data_in,
+                     //input  [15:0] cfg_framecnt,
+                     //input         auto_fill,
+                     //input         auto_empty, 
+                     input         cfg_master,
+                     //input         rx_fifo_first,               // not really needed anymore
+                     input         rx_fifo_empty,
+                     // -----------------------
+                     // AS: added tx_fifo_empty
+                     // -----------------------
+                     input         tx_fifo_empty,
+                     //input         clear_frame_count,
+                     //input         fill_okay,
+
+                     output [CFG_FRAME_SIZE-1:0] tx_fifo_data,            
+                     output        tx_fifo_write,           
+                     output        tx_fifo_last,             
+                     output        rx_fifo_read            
+                );
+
+
+
+//######################################################################################################
+
+reg tx_fifo_write_sig;
+reg rx_fifo_read_sig;
+
+//reg [15:0] txrx_frame_count_d;   //frame count
+//reg [15:0] txrx_frame_count_q;
+reg tx_last_frame_sig;
+
+//reg auto_write;
+//reg auto_read;
+
+
+// Output assignments.
+// AS: modified tx_fifo_last to be dependent on tx_fifo_empty (undone)
+assign tx_fifo_last   = tx_last_frame_sig;      
+//assign tx_fifo_last   = tx_last_frame_sig && tx_fifo_empty;
+assign tx_fifo_data   = wr_data_in;
+assign tx_fifo_write  = tx_fifo_write_sig;     
+assign rx_fifo_read   = rx_fifo_read_sig;     
+
+// AS: removed counter
+//always @(posedge pclk or negedge presetn)
+//   begin
+//   if (~presetn)
+//      begin 
+//        txrx_frame_count_q <= 16'h0001;
+//      end
+//   else
+//      begin
+//        txrx_frame_count_q <=  txrx_frame_count_d;
+//      end
+//   end
+
+// Note combinational generation of FIFO read and write signals
+
+always @(*)
+   begin
+   //defaults
+   rx_fifo_read_sig  = 1'b0;      //default no read on rx fifo
+   tx_fifo_write_sig = 1'b0;      //default no write on tx fifo
+   tx_last_frame_sig = 1'b0;      //default not last frame
+   //txrx_frame_count_d = txrx_frame_count_q;
+
+   if (penable && psel)
+      begin
+      case (paddr) //synthesis parallel_case
+      6'h0C:\t  //write to transmit fifo
+         begin
+            if (pwrite)
+               begin
+                 tx_fifo_write_sig  = 1'b1;   //write to the fifo
+                 
+                 //txrx_frame_count_d = txrx_frame_count_q + 1'b1;
+                 // *************************************************************
+                 // AS: what to do here? not sure how tx_last_frame_sig should be
+                 // be assigned
+                 // ************************************************************* 
+                 //if (txrx_frame_count_q == cfg_framecnt)
+                 //   begin
+                 //     tx_last_frame_sig  = 1'b1;
+                 //     txrx_frame_count_d = 16'h0001;
+                 //   end
+                 
+                 // Solution: created Aliased TX DATA register to indicate last frame
+                 
+               end            
+         end
+      6'h08:    //read from receive fifo
+         begin 
+            if (~pwrite) 
+            begin
+                rx_fifo_read_sig = 1'b1;
+            end
+         end
+      6'h28:    // aliased transmit data, sets last frame bit
+        begin
+          tx_fifo_write_sig  = 1'b1;   //write to the fifo
+          tx_last_frame_sig  = 1'b1;   //last frame
+        end
+      default:
+         begin
+         end
+      endcase     
+   end
+
+   //if (auto_write)
+   // begin
+   //      tx_fifo_write_sig  = 1'b1;   //write to the fifo
+   //      txrx_frame_count_d = txrx_frame_count_q + 1'b1;
+   //      if (txrx_frame_count_q == cfg_framecnt)
+   //      begin
+   //        tx_last_frame_sig  = 1'b1;
+   //        txrx_frame_count_d = 16'h0001;
+   //      end
+   // end
+   //
+   //if (auto_read)
+   // begin
+   //     rx_fifo_read_sig = 1'b1;
+   // end
+   //  
+   //if (clear_frame_count) txrx_frame_count_d = 16'h0001; 
+   
+
+end
+    
+
+
+
+
+//----------------------------------------------------------------------------------
+
+// AS: removed auto write and auto read features
+//always@(posedge pclk or negedge presetn)
+//begin
+//  if (!presetn)
+//   begin
+//     auto_write <= 1'b0;
+//     auto_read  <= 1'b0;
+//   end
+//  else
+// begin
+//    auto_write <= 1'b0;
+//    auto_read  <= 1'b0;
+//   
+//    if ((auto_fill) & !auto_write & (fill_okay))       // if room in FIFOs write data
+//    begin
+//        auto_write <= 1'b1;
+//    end
+//        
+//    //on master empty until all frames done
+//    if (cfg_master && auto_empty && !auto_read && !rx_fifo_empty)
+//    begin
+//        auto_read <= 1'b1;
+//    end
+//
+//    //On slave empty until start of next packet
+//    if (!cfg_master && auto_empty && !auto_read && !rx_fifo_first && !rx_fifo_empty)
+//    begin
+//        auto_read <= 1'b1;
+//    end
+//
+// end
+//end
+
+
+
+
+
+
+endmodule
+   "
+"// timerInterrupts.v
+module timer(
+\t\t\tpclk,
+\t\t\tnreset,
+\t\t\tbus_write_en, 
+\t\t\tbus_read_en,
+\t\t\tbus_addr,
+\t\t\tbus_write_data,
+\t\t\tbus_read_data,
+            fabint
+            );
+\t
+input pclk, nreset, bus_write_en, bus_read_en;
+input [7:0] bus_addr;
+input [31:0] bus_write_data;
+output reg [31:0] bus_read_data;
+output reg fabint;
+
+
+
+reg [31:0] compareReg;
+reg [31:0] counterReg;
+reg [31:0] controlReg;
+reg [31:0] overflowReg;
+
+reg overflowReset;\t\t//Resets counterReg when new overflow value is written
+
+wire timerEn;        //Timer Enable
+wire interruptEn;    //Interrupt Enable
+wire compareEn;      //Compare Enable
+wire overflowEn;\t //Overflow Enable
+
+assign timerEn \t\t= controlReg[0];
+assign interruptEn \t= controlReg[1];
+assign compareEn \t= controlReg[2];
+assign overflowEn\t= controlReg[3];
+
+reg [1:0] interrupt_status;
+reg reset_interrupt;
+reg timer_interrupt;
+
+reg [31:0] nextCounter;
+
+always@(posedge pclk)
+if(~nreset)
+  fabint   <= 1'b0;
+else
+  begin
+    if(timer_interrupt)
+      fabint   <= 1'b1;
+    else
+      fabint   <= 1'b0;
+end
+
+
+
+
+always@(posedge pclk)
+if(~nreset)
+  begin
+    overflowReset <= 1'b0;
+    compareReg <= 32'h00000000;
+    overflowReg <= 32'h00000000;
+\tcontrolReg <= 32'h00000000;
+    reset_interrupt <= 1'b0;
+  end
+else begin
+\tif(bus_write_en) begin : WRITE
+\t\tcase(bus_addr[4:2])
+\t\t\t3'b000: // Overflow Register
+                begin 
+                overflowReset <= 1'b1;
+\t\t\t\toverflowReg <= bus_write_data;
+                end
+            3'b001: // Timer Value, Read Only
+                begin
+                overflowReset <= 1'b0;
+                end
+            3'b010: // Timer Control
+                begin 
+                overflowReset <= 1'b0;
+                controlReg <= bus_write_data;
+                end
+            3'b011: // Compare Register
+                begin
+                overflowReset <= 1'b0;
+                compareReg <= bus_write_data;
+                end
+            3'b100: //Interrupt Status, Read Only
+                begin
+                overflowReset <= 1'b0;
+                end
+            3'b101: //Spare
+                begin
+                end
+        endcase
+    end
+\telse if(bus_read_en) begin : READ
+        case(bus_addr[4:2])
+\t        3'b000: // Timer Overflow register
+                begin 
+\t\t        bus_read_data <= overflowReg;
+                reset_interrupt <= 1'b0;
+\t\t\t\tend
+            3'b001: // Timer Value, Read Only
+                begin 
+                bus_read_data <= counterReg;
+                reset_interrupt <= 1'b0;
+\t\t\t\tend
+            3'b010: // Timer Control
+                begin 
+                bus_read_data <= controlReg;
+                reset_interrupt <= 1'b0;
+\t\t\t    end
+            3'b011: //Compare Register
+                begin
+                bus_read_data <= compareReg;
+                reset_interrupt <= 1'b0;
+                end
+            3'b100: // Interrupt Status
+                begin 
+                bus_read_data[31:2] <= 30'd0;;
+                bus_read_data[1:0] <= interrupt_status;
+                reset_interrupt <= 1'b1;
+                end
+            3'b101: //Spare
+                begin
+                end
+        endcase
+     end
+     else begin
+\t   overflowReset <= 1'b0;
+       reset_interrupt <= 1'b0;
+     end
+end
+
+always@*
+\tnextCounter = counterReg + 1;
+  
+always@(posedge pclk)
+if(~nreset) begin
+\tcounterReg <= 32'd0;
+    timer_interrupt <= 1'b0;
+    interrupt_status <= 2'b00;
+end
+else begin
+    if(reset_interrupt)begin
+        interrupt_status <= 2'b00;
+        timer_interrupt <= 1'b0;
+    end
+    else begin
+        if(overflowReset) begin
+            counterReg <= 32'd0;
+            timer_interrupt <= 1'b0;
+        end
+        else if(timerEn) begin
+            if(counterReg == overflowReg) begin
+                counterReg <= 32'd0;
+                if(interruptEn && overflowEn) begin
+                    timer_interrupt <= 1'b1;
+                    interrupt_status[0] <= 1'b1;
+                end
+                else
+                    timer_interrupt <= 1'b0;
+            end
+            else begin
+                if(counterReg == compareReg && interruptEn && compareEn) begin
+                    timer_interrupt <= 1'b1;
+                    interrupt_status[1] <= 1'b1;
+                end
+                else
+                    timer_interrupt <= 1'b0;
+                counterReg <= nextCounter;
+            end
+        end
+
+    end
+end
+
+endmodule"
+"module inverter(bus, line);
+  input [7:0] bus;
+  output line;
+  assign line = ~bus[0];
+endmodule
+
+"
+"// ********************************************************************
+// Actel Corporation Proprietary and Confidential
+//  Copyright 2010 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
+// IN ADVANCE IN WRITING.
+//
+// Description:\tUser Testbench for CoreAPB3
+//
+// Revision Information:
+// Date     Description
+// 05Feb10\t\tProduction Release Version 3.0
+//
+// SVN Revision Information:
+// SVN $Revision: 18490 $
+// SVN $Date: 2012-11-21 10:03:55 -0800 (Wed, 21 Nov 2012) $
+//
+// Resolved SARs
+// SAR      Date     Who   Description
+//
+// Notes:
+// 1. best viewed with tabstops set to ""4""
+// 2. Most of the behavior is driven from the BFM script for the APB
+//    master.  Consult the Actel AMBA BFM documentation for more information.
+//
+// History:\t\t1/28/10  - TFB created
+//
+// *********************************************************************
+
+`timescale 1ns/1ps
+
+
+module testbench ();
+
+// location of this can be overridden at compile time (+incdir switch)
+//`include ""../../../../coreparameters.v""
+`include ""coreparameters.v""
+
+//parameter RANGESIZE = 268435456;
+//parameter IADDR_ENABLE = 0;
+
+
+//-----------------------------------------------------------------------------
+// top-level parameters
+//-----------------------------------------------------------------------------
+
+// vector files for driving the APB master BFM
+// NOTE: location of the following files can be overridden at run time
+parameter APB_MASTER_VECTFILE\t= ""coreapb3_usertb_master.vec"";
+
+// APB Master System Clock cycle (in ns)
+parameter APB_MASTER_CLK_CYCLE\t= 30;
+
+// propagation delay in ns
+parameter TPD\t\t\t= 3;
+
+
+// BFM slave constants
+//localparam SLAVE_AWIDTH\t\t= 8;
+localparam SLAVE_AWIDTH\t\t= 8;
+localparam SLAVE_DEPTH\t\t= (2**SLAVE_AWIDTH) ;
+
+
+// System signals
+reg\t\t\t\t\t\t\tSYSRSTN_apb;
+reg\t\t\t\t\t\t\tSYSCLK_apb;
+
+// APB master bfm signals
+wire\t\t\t\t\t\tPCLK;
+wire\t\t\t\t\t\tPRESETN;
+wire\t[31:0]\t\t\t\tPADDR_apb_bfm_wide;
+//wire\t[23:0]\t\t\t\tPADDR;
+wire\t[31:0]\t\t\t\tPADDR;
+wire\t[15:0]\t\t\t\tPSEL_apb_bfm_wide;
+wire\t\t\t\t\t\tPSEL;
+wire\t\t\t\t\t\tPENABLE;
+wire\t\t\t\t\t\tPWRITE;
+wire\t[31:0]\t\t\t\tPWDATA_apb_bfm_wide;
+//wire\t[APB_DWIDTH-1:0]\tPWDATA;
+wire\t[31:0]\t\t\t\tPWDATA;
+
+// input to bfm
+wire\t[31:0]\t\t\t\tPRDATA_apb_bfm_wide;
+//wire\t[APB_DWIDTH-1:0]\tPRDATA;
+wire\t[31:0]\t\t\t\tPRDATA;
+wire\t\t\t\t\t\tPREADY;
+wire\t\t\t\t\t\tPSLVERR;
+
+// input to APB bfm
+//wire\t[31:0]\t\t\t\tGP_IN_apb_bfm=32\'b0;
+//wire\t[31:0]\t\t\t\tGP_OUT_apb_bfm;
+wire\t\t\t\t\t\tFINISHED_apb_bfm;
+wire\t\t\t\t\t\tFAILED_apb_bfm;
+
+
+// misc. signals
+wire\t[255:0]\t\t\t\tGND256=256\'b0;
+wire\t[31:0]\t\t\t\tGND32=32\'b0;
+wire\t\t\t\t\t\tGND1=1\'b0;
+reg\t\t\t\t\t\t\tstopsim=0;
+
+
+//wire\t[23:0]\t\t\t\tPADDRS;
+wire\t[31:0]\t\t\t\tPADDRS;
+//wire\t[(((1-IADDR_ENABLE)*24)+((IADDR_ENABLE)*32))-1:0] PADDRS0;
+wire\t\t\t\t\t\tPWRITES;
+wire\t\t\t\t\t\tPENABLES;
+//wire\t[APB_DWIDTH-1:0]\tPWDATAS;
+wire\t[31:0]\t\t\t\tPWDATAS;
+wire\t\t\t\t\t\tPSELS0;
+wire\t\t\t\t\t\tPSELS1;
+wire\t\t\t\t\t\tPSELS2;
+wire\t\t\t\t\t\tPSELS3;
+wire\t\t\t\t\t\tPSELS4;
+wire\t\t\t\t\t\tPSELS5;
+wire\t\t\t\t\t\tPSELS6;
+wire\t\t\t\t\t\tPSELS7;
+wire\t\t\t\t\t\tPSELS8;
+wire\t\t\t\t\t\tPSELS9;
+wire\t\t\t\t\t\tPSELS10;
+wire\t\t\t\t\t\tPSELS11;
+wire\t\t\t\t\t\tPSELS12;
+wire\t\t\t\t\t\tPSELS13;
+wire\t\t\t\t\t\tPSELS14;
+wire\t\t\t\t\t\tPSELS15;
+wire\t\t\t\t\t\tPSELS16;
+
+/*
+wire\t[APB_DWIDTH-1:0]\tPRDATAS0;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS1;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS2;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS3;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS4;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS5;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS6;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS7;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS8;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS9;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS10;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS11;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS12;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS13;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS14;
+wire\t[APB_DWIDTH-1:0]\tPRDATAS15;
+*/
+wire\t[31:0]\t\t\t\tPRDATAS0;
+wire\t[31:0]\t\t\t\tPRDATAS1;
+wire\t[31:0]\t\t\t\tPRDATAS2;
+wire\t[31:0]\t\t\t\tPRDATAS3;
+wire\t[31:0]\t\t\t\tPRDATAS4;
+wire\t[31:0]\t\t\t\tPRDATAS5;
+wire\t[31:0]\t\t\t\tPRDATAS6;
+wire\t[31:0]\t\t\t\tPRDATAS7;
+wire\t[31:0]\t\t\t\tPRDATAS8;
+wire\t[31:0]\t\t\t\tPRDATAS9;
+wire\t[31:0]\t\t\t\tPRDATAS10;
+wire\t[31:0]\t\t\t\tPRDATAS11;
+wire\t[31:0]\t\t\t\tPRDATAS12;
+wire\t[31:0]\t\t\t\tPRDATAS13;
+wire\t[31:0]\t\t\t\tPRDATAS14;
+wire\t[31:0]\t\t\t\tPRDATAS15;
+wire\t[31:0]\t\t\t\tPRDATAS16;
+
+
+wire\t\t\t\t\t\tPREADYS0;
+wire\t\t\t\t\t\tPREADYS1;
+wire\t\t\t\t\t\tPREADYS2;
+wire\t\t\t\t\t\tPREADYS3;
+wire\t\t\t\t\t\tPREADYS4;
+wire\t\t\t\t\t\tPREADYS5;
+wire\t\t\t\t\t\tPREADYS6;
+wire\t\t\t\t\t\tPREADYS7;
+wire\t\t\t\t\t\tPREADYS8;
+wire\t\t\t\t\t\tPREADYS9;
+wire\t\t\t\t\t\tPREADYS10;
+wire\t\t\t\t\t\tPREADYS11;
+wire\t\t\t\t\t\tPREADYS12;
+wire\t\t\t\t\t\tPREADYS13;
+wire\t\t\t\t\t\tPREADYS14;
+wire\t\t\t\t\t\tPREADYS15;
+wire\t\t\t\t\t\tPREADYS16;
+
+wire\t\t\t\t\t\tPSLVERRS0;
+wire\t\t\t\t\t\tPSLVERRS1;
+wire\t\t\t\t\t\tPSLVERRS2;
+wire\t\t\t\t\t\tPSLVERRS3;
+wire\t\t\t\t\t\tPSLVERRS4;
+wire\t\t\t\t\t\tPSLVERRS5;
+wire\t\t\t\t\t\tPSLVERRS6;
+wire\t\t\t\t\t\tPSLVERRS7;
+wire\t\t\t\t\t\tPSLVERRS8;
+wire\t\t\t\t\t\tPSLVERRS9;
+wire\t\t\t\t\t\tPSLVERRS10;
+wire\t\t\t\t\t\tPSLVERRS11;
+wire\t\t\t\t\t\tPSLVERRS12;
+wire\t\t\t\t\t\tPSLVERRS13;
+wire\t\t\t\t\t\tPSLVERRS14;
+wire\t\t\t\t\t\tPSLVERRS15;
+wire\t\t\t\t\t\tPSLVERRS16;
+
+/*
+wire\t[31:0]\t\t\t\tPWDATAS_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS0_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS1_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS2_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS3_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS4_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS5_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS6_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS7_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS8_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS9_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS10_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS11_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS12_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS13_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS14_apb_slave;
+wire\t[31:0]\t\t\t\tPRDATAS15_apb_slave;
+*/
+
+reg                 s0_write;
+reg                 s1_write;
+reg                 s2_write;
+reg                 s3_write;
+reg                 s4_write;
+reg                 s5_write;
+reg                 s6_write;
+reg                 s7_write;
+reg                 s8_write;
+reg                 s9_write;
+reg                 s10_write;
+reg                 s11_write;
+reg                 s12_write;
+reg                 s13_write;
+reg                 s14_write;
+reg                 s15_write;
+reg                 s16_write;
+
+// BFM GPIO
+wire\t[31:0]\t\tGP_OUT;
+wire\t[31:0]\t\tGP_IN;
+
+
+// instantiate DUT(s)
+CoreAPB3 #(
+\t.APB_DWIDTH(APB_DWIDTH),
+\t.IADDR_OPTION(IADDR_OPTION),
+\t.APBSLOT0ENABLE(APBSLOT0ENABLE),
+\t.APBSLOT1ENABLE(APBSLOT1ENABLE),
+\t.APBSLOT2ENABLE(APBSLOT2ENABLE),
+\t.APBSLOT3ENABLE(APBSLOT3ENABLE),
+\t.APBSLOT4ENABLE(APBSLOT4ENABLE),
+\t.APBSLOT5ENABLE(APBSLOT5ENABLE),
+\t.APBSLOT6ENABLE(APBSLOT6ENABLE),
+\t.APBSLOT7ENABLE(APBSLOT7ENABLE),
+\t.APBSLOT8ENABLE(APBSLOT8ENABLE),
+\t.APBSLOT9ENABLE(APBSLOT9ENABLE),
+\t.APBSLOT10ENABLE(APBSLOT10ENABLE),
+\t.APBSLOT11ENABLE(APBSLOT11ENABLE),
+\t.APBSLOT12ENABLE(APBSLOT12ENABLE),
+\t.APBSLOT13ENABLE(APBSLOT13ENABLE),
+\t.APBSLOT14ENABLE(APBSLOT14ENABLE),
+\t.APBSLOT15ENABLE(APBSLOT15ENABLE),
+\t.MADDR_BITS(MADDR_BITS),
+\t.UPR_NIBBLE_POSN(UPR_NIBBLE_POSN),
+\t.SC_0  (SC_0 ),
+\t.SC_1  (SC_1 ),
+\t.SC_2  (SC_2 ),
+\t.SC_3  (SC_3 ),
+\t.SC_4  (SC_4 ),
+\t.SC_5  (SC_5 ),
+\t.SC_6  (SC_6 ),
+\t.SC_7  (SC_7 ),
+\t.SC_8  (SC_8 ),
+\t.SC_9  (SC_9 ),
+\t.SC_10 (SC_10),
+\t.SC_11 (SC_11),
+\t.SC_12 (SC_12),
+\t.SC_13 (SC_13),
+\t.SC_14 (SC_14),
+\t.SC_15 (SC_15)
+) u_coreapb3 (
+    .IADDR(32\'b0),
+\t.PRESETN(PRESETN),
+\t.PCLK(PCLK),
+\t.PADDR(PADDR),
+\t.PWRITE(PWRITE),
+\t.PENABLE(PENABLE),
+\t.PSEL(PSEL),
+\t.PWDATA(PWDATA),
+\t.PRDATA(PRDATA),
+\t.PREADY(PREADY),
+\t.PSLVERR(PSLVERR),
+\t.PADDRS(PADDRS),
+\t.PWRITES(PWRITES),
+\t.PENABLES(PENABLES),
+\t.PWDATAS(PWDATAS),
+\t.PSELS0(PSELS0),
+\t.PSELS1(PSELS1),
+\t.PSELS2(PSELS2),
+\t.PSELS3(PSELS3),
+\t.PSELS4(PSELS4),
+\t.PSELS5(PSELS5),
+\t.PSELS6(PSELS6),
+\t.PSELS7(PSELS7),
+\t.PSELS8(PSELS8),
+\t.PSELS9(PSELS9),
+\t.PSELS10(PSELS10),
+\t.PSELS11(PSELS11),
+\t.PSELS12(PSELS12),
+\t.PSELS13(PSELS13),
+\t.PSELS14(PSELS14),
+\t.PSELS15(PSELS15),
+\t.PSELS16(PSELS16),
+\t.PRDATAS0(PRDATAS0),
+\t.PRDATAS1(PRDATAS1),
+\t.PRDATAS2(PRDATAS2),
+\t.PRDATAS3(PRDATAS3),
+\t.PRDATAS4(PRDATAS4),
+\t.PRDATAS5(PRDATAS5),
+\t.PRDATAS6(PRDATAS6),
+\t.PRDATAS7(PRDATAS7),
+\t.PRDATAS8(PRDATAS8),
+\t.PRDATAS9(PRDATAS9),
+\t.PRDATAS10(PRDATAS10),
+\t.PRDATAS11(PRDATAS11),
+\t.PRDATAS12(PRDATAS12),
+\t.PRDATAS13(PRDATAS13),
+\t.PRDATAS14(PRDATAS14),
+\t.PRDATAS15(PRDATAS15),
+\t.PRDATAS16(PRDATAS16),
+\t.PREADYS0(PREADYS0),
+\t.PREADYS1(PREADYS1),
+\t.PREADYS2(PREADYS2),
+\t.PREADYS3(PREADYS3),
+\t.PREADYS4(PREADYS4),
+\t.PREADYS5(PREADYS5),
+\t.PREADYS6(PREADYS6),
+\t.PREADYS7(PREADYS7),
+\t.PREADYS8(PREADYS8),
+\t.PREADYS9(PREADYS9),
+\t.PREADYS10(PREADYS10),
+\t.PREADYS11(PREADYS11),
+\t.PREADYS12(PREADYS12),
+\t.PREADYS13(PREADYS13),
+\t.PREADYS14(PREADYS14),
+\t.PREADYS15(PREADYS15),
+\t.PREADYS16(PREADYS16),
+\t.PSLVERRS0(PSLVERRS0),
+\t.PSLVERRS1(PSLVERRS1),
+\t.PSLVERRS2(PSLVERRS2),
+\t.PSLVERRS3(PSLVERRS3),
+\t.PSLVERRS4(PSLVERRS4),
+\t.PSLVERRS5(PSLVERRS5),
+\t.PSLVERRS6(PSLVERRS6),
+\t.PSLVERRS7(PSLVERRS7),
+\t.PSLVERRS8(PSLVERRS8),
+\t.PSLVERRS9(PSLVERRS9),
+\t.PSLVERRS10(PSLVERRS10),
+\t.PSLVERRS11(PSLVERRS11),
+\t.PSLVERRS12(PSLVERRS12),
+\t.PSLVERRS13(PSLVERRS13),
+\t.PSLVERRS14(PSLVERRS14),
+\t.PSLVERRS15(PSLVERRS15),
+\t.PSLVERRS16(PSLVERRS16)
+);
+//assign PRDATA_apb_bfm_wide\t\t= {{32-APB_DWIDTH{1\'b0}},PRDATA};
+assign PRDATA_apb_bfm_wide\t\t= PRDATA;
+
+// BFM monitors various signals
+assign GP_IN = {
+\t15\'b0,              // 31:17
+    s16_write,          // 16
+    s15_write,          // 15
+    s14_write,          // 14
+    s13_write,          // 13
+    s12_write,          // 12
+    s11_write,          // 11
+    s10_write,          // 10
+    s9_write,           //  9
+    s8_write,           //  8
+    s7_write,           //  7
+    s6_write,           //  6
+    s5_write,           //  5
+    s4_write,           //  4
+    s3_write,           //  3
+    s2_write,           //  2
+    s1_write,           //  1
+    s0_write            //  0
+};
+
+
+// instantiate APB Master BFM to drive APB mirrored master port
+BFM_APB #(
+\t.VECTFILE(APB_MASTER_VECTFILE),
+\t.TPD(TPD),
+\t// passing testbench parameters to BFM ARGVALUE* parameters
+\t.ARGVALUE0  (APB_DWIDTH),
+\t.ARGVALUE1  (IADDR_OPTION),
+\t.ARGVALUE2  (APBSLOT0ENABLE),
+\t.ARGVALUE3  (APBSLOT1ENABLE),
+\t.ARGVALUE4  (APBSLOT2ENABLE),
+\t.ARGVALUE5  (APBSLOT3ENABLE),
+\t.ARGVALUE6  (APBSLOT4ENABLE),
+\t.ARGVALUE7  (APBSLOT5ENABLE),
+\t.ARGVALUE8  (APBSLOT6ENABLE),
+\t.ARGVALUE9  (APBSLOT7ENABLE),
+\t.ARGVALUE10 (APBSLOT8ENABLE),
+\t.ARGVALUE11 (APBSLOT9ENABLE),
+\t.ARGVALUE12 (APBSLOT10ENABLE),
+\t.ARGVALUE13 (APBSLOT11ENABLE),
+\t.ARGVALUE14 (APBSLOT12ENABLE),
+\t.ARGVALUE15 (APBSLOT13ENABLE),
+\t.ARGVALUE16 (APBSLOT14ENABLE),
+\t.ARGVALUE17 (APBSLOT15ENABLE),
+\t.ARGVALUE18 (MADDR_BITS),
+\t.ARGVALUE19 (UPR_NIBBLE_POSN),
+\t.ARGVALUE20 (SC_0),
+\t.ARGVALUE21 (SC_1),
+\t.ARGVALUE22 (SC_2),
+\t.ARGVALUE23 (SC_3),
+\t.ARGVALUE24 (SC_4),
+\t.ARGVALUE25 (SC_5),
+\t.ARGVALUE26 (SC_6),
+\t.ARGVALUE27 (SC_7),
+\t.ARGVALUE28 (SC_8),
+\t.ARGVALUE29 (SC_9),
+\t.ARGVALUE30 (SC_10),
+\t.ARGVALUE31 (SC_11),
+\t.ARGVALUE32 (SC_12),
+\t.ARGVALUE33 (SC_13),
+\t.ARGVALUE34 (SC_14),
+\t.ARGVALUE35 (SC_15)
+) u_apb_master (
+\t.SYSCLK(SYSCLK_apb),
+\t.SYSRSTN(SYSRSTN_apb),
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PADDR(PADDR_apb_bfm_wide),
+\t.PSEL(PSEL_apb_bfm_wide),
+\t.PENABLE(PENABLE),
+\t.PWRITE(PWRITE),
+\t.PWDATA(PWDATA_apb_bfm_wide),
+\t.PRDATA(PRDATA_apb_bfm_wide),
+\t.PREADY(PREADY),
+\t.PSLVERR(PSLVERR),
+\t.INTERRUPT(GND256),
+\t.GP_OUT(GP_OUT),
+\t.GP_IN(GP_IN),
+\t.EXT_WR(),
+\t.EXT_RD(),
+\t.EXT_ADDR(),
+\t.EXT_DATA(),
+\t.EXT_WAIT(GND1),
+\t.FINISHED(FINISHED_apb_bfm),
+\t.FAILED(FAILED_apb_bfm)
+);
+//assign PADDR\t\t\t\t= PADDR_apb_bfm_wide[23:0];
+assign PADDR\t\t\t\t= PADDR_apb_bfm_wide[31:0];
+//assign PSEL\t\t\t\t\t= PSEL_apb_bfm_wide[0];
+assign PSEL\t\t\t\t\t= PSEL_apb_bfm_wide[ 0] ||
+                              PSEL_apb_bfm_wide[ 1] ||
+                              PSEL_apb_bfm_wide[ 2] ||
+                              PSEL_apb_bfm_wide[ 3] ||
+                              PSEL_apb_bfm_wide[ 4] ||
+                              PSEL_apb_bfm_wide[ 5] ||
+                              PSEL_apb_bfm_wide[ 6] ||
+                              PSEL_apb_bfm_wide[ 7] ||
+                              PSEL_apb_bfm_wide[ 8] ||
+                              PSEL_apb_bfm_wide[ 9] ||
+                              PSEL_apb_bfm_wide[10] ||
+                              PSEL_apb_bfm_wide[11] ||
+                              PSEL_apb_bfm_wide[12] ||
+                              PSEL_apb_bfm_wide[13] ||
+                              PSEL_apb_bfm_wide[14] ||
+                              PSEL_apb_bfm_wide[15] ;
+//assign PWDATA\t\t\t\t= PWDATA_apb_bfm_wide[APB_DWIDTH-1:0];
+assign PWDATA\t\t\t\t= PWDATA_apb_bfm_wide;
+
+// BFM slave 0
+BFM_APBSLAVE#(
+\t//.AWIDTH(((1-IADDR_ENABLE)*SLAVE_AWIDTH)+((IADDR_ENABLE)*28)),
+\t//.DEPTH(((1-IADDR_ENABLE)*SLAVE_DEPTH)+((IADDR_ENABLE)*(2**28))),
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave0 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS0),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t//.PADDR(PADDRS0[(((1-IADDR_ENABLE)*SLAVE_AWIDTH)+((IADDR_ENABLE)*28)-1):0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS0),
+\t.PREADY(PREADYS0),
+\t.PSLVERR(PSLVERRS0)
+);
+
+// BFM slave 1
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave1 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS1),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS1),
+\t.PREADY(PREADYS1),
+\t.PSLVERR(PSLVERRS1)
+);
+
+// BFM slave 2
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave2 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS2),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS2),
+\t.PREADY(PREADYS2),
+\t.PSLVERR(PSLVERRS2)
+);
+
+// BFM slave 3
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave3 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS3),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS3),
+\t.PREADY(PREADYS3),
+\t.PSLVERR(PSLVERRS3)
+);
+
+// BFM slave 4
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave4 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS4),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS4),
+\t.PREADY(PREADYS4),
+\t.PSLVERR(PSLVERRS4)
+);
+
+// BFM slave 5
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave5 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS5),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS5),
+\t.PREADY(PREADYS5),
+\t.PSLVERR(PSLVERRS5)
+);
+
+// BFM slave 6
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave6 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS6),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS6),
+\t.PREADY(PREADYS6),
+\t.PSLVERR(PSLVERRS6)
+);
+
+// BFM slave 7
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave7 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS7),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS7),
+\t.PREADY(PREADYS7),
+\t.PSLVERR(PSLVERRS7)
+);
+
+// BFM slave 8
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave8 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS8),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS8),
+\t.PREADY(PREADYS8),
+\t.PSLVERR(PSLVERRS8)
+);
+
+// BFM slave 9
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave9 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS9),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS9),
+\t.PREADY(PREADYS9),
+\t.PSLVERR(PSLVERRS9)
+);
+
+// BFM slave 10
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave10 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS10),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS10),
+\t.PREADY(PREADYS10),
+\t.PSLVERR(PSLVERRS10)
+);
+
+// BFM slave 11
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave11 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS11),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS11),
+\t.PREADY(PREADYS11),
+\t.PSLVERR(PSLVERRS11)
+);
+
+// BFM slave 12
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave12 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS12),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS12),
+\t.PREADY(PREADYS12),
+\t.PSLVERR(PSLVERRS12)
+);
+
+// BFM slave 13
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave13 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS13),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS13),
+\t.PREADY(PREADYS13),
+\t.PSLVERR(PSLVERRS13)
+);
+
+// BFM slave 14
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave14 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS14),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS14),
+\t.PREADY(PREADYS14),
+\t.PSLVERR(PSLVERRS14)
+);
+
+// BFM slave 15
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave15 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS15),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS15),
+\t.PREADY(PREADYS15),
+\t.PSLVERR(PSLVERRS15)
+);
+
+// BFM slave 16 (combined region)
+BFM_APBSLAVE #(
+\t.AWIDTH(SLAVE_AWIDTH),
+\t.DEPTH(SLAVE_DEPTH),
+\t.DWIDTH(32),
+\t.TPD(TPD)
+) u_slave16 (
+\t.PCLK(PCLK),
+\t.PRESETN(PRESETN),
+\t.PENABLE(PENABLES),
+\t.PWRITE(PWRITES),
+\t.PSEL(PSELS16),
+\t.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
+\t.PWDATA(PWDATAS),
+\t.PRDATA(PRDATAS16),
+\t.PREADY(PREADYS16),
+\t.PSLVERR(PSLVERRS16)
+);
+
+
+/*
+// adjust busses to widths
+assign PWDATAS_apb_slave = {{32-APB_DWIDTH{1\'b0}},PWDATAS[APB_DWIDTH-1:0]};
+assign PRDATAS0\t\t=\tPRDATAS0_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS1\t\t=\tPRDATAS1_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS2\t\t=\tPRDATAS2_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS3\t\t=\tPRDATAS3_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS4\t\t=\tPRDATAS4_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS5\t\t=\tPRDATAS5_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS6\t\t=\tPRDATAS6_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS7\t\t=\tPRDATAS7_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS8\t\t=\tPRDATAS8_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS9\t\t=\tPRDATAS9_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS10\t=\tPRDATAS10_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS11\t=\tPRDATAS11_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS12\t=\tPRDATAS12_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS13\t=\tPRDATAS13_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS14\t=\tPRDATAS14_apb_slave[APB_DWIDTH-1:0];
+assign PRDATAS15\t=\tPRDATAS15_apb_slave[APB_DWIDTH-1:0];
+*/
+
+    //---------------------------------------------------------------------
+    // Detect writes to individual slots
+    //---------------------------------------------------------------------
+    always @(posedge PCLK or negedge PRESETN)
+    begin
+        if (!PRESETN)
+        begin
+            s0_write  <= 1\'b0;
+            s1_write  <= 1\'b0;
+            s2_write  <= 1\'b0;
+            s3_write  <= 1\'b0;
+            s4_write  <= 1\'b0;
+            s5_write  <= 1\'b0;
+            s6_write  <= 1\'b0;
+            s7_write  <= 1\'b0;
+            s8_write  <= 1\'b0;
+            s9_write  <= 1\'b0;
+            s10_write <= 1\'b0;
+            s11_write <= 1\'b0;
+            s12_write <= 1\'b0;
+            s13_write <= 1\'b0;
+            s14_write <= 1\'b0;
+            s15_write <= 1\'b0;
+            s16_write <= 1\'b0;
+        end
+        else
+        begin
+            // Set write indication bits
+            if (PSELS0  && PWRITES) s0_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS1  && PWRITES) s1_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS2  && PWRITES) s2_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS3  && PWRITES) s3_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS4  && PWRITES) s4_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS5  && PWRITES) s5_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS6  && PWRITES) s6_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS7  && PWRITES) s7_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS8  && PWRITES) s8_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS9  && PWRITES) s9_write  <= 1\'b1;                       // && PENABLES
+            if (PSELS10 && PWRITES) s10_write <= 1\'b1;                       // && PENABLES
+            if (PSELS11 && PWRITES) s11_write <= 1\'b1;                       // && PENABLES
+            if (PSELS12 && PWRITES) s12_write <= 1\'b1;                       // && PENABLES
+            if (PSELS13 && PWRITES) s13_write <= 1\'b1;                       // && PENABLES
+            if (PSELS14 && PWRITES) s14_write <= 1\'b1;                       // && PENABLES
+            if (PSELS15 && PWRITES) s15_write <= 1\'b1;                       // && PENABLES
+            if (PSELS16 && PWRITES) s16_write <= 1\'b1;                       // && PENABLES
+            // Clear write indication bits
+            if (GP_OUT[0])  s0_write  <= 1\'b0;
+            if (GP_OUT[1])  s1_write  <= 1\'b0;
+            if (GP_OUT[2])  s2_write  <= 1\'b0;
+            if (GP_OUT[3])  s3_write  <= 1\'b0;
+            if (GP_OUT[4])  s4_write  <= 1\'b0;
+            if (GP_OUT[5])  s5_write  <= 1\'b0;
+            if (GP_OUT[6])  s6_write  <= 1\'b0;
+            if (GP_OUT[7])  s7_write  <= 1\'b0;
+            if (GP_OUT[8])  s8_write  <= 1\'b0;
+            if (GP_OUT[9])  s9_write  <= 1\'b0;
+            if (GP_OUT[10]) s10_write <= 1\'b0;
+            if (GP_OUT[11]) s11_write <= 1\'b0;
+            if (GP_OUT[12]) s12_write <= 1\'b0;
+            if (GP_OUT[13]) s13_write <= 1\'b0;
+            if (GP_OUT[14]) s14_write <= 1\'b0;
+            if (GP_OUT[15]) s15_write <= 1\'b0;
+            if (GP_OUT[16]) s16_write <= 1\'b0;
+        end
+    end
+
+
+// System Clocks
+initial SYSCLK_apb = 1\'b0;
+always #(APB_MASTER_CLK_CYCLE/2) SYSCLK_apb = ~SYSCLK_apb;
+
+// Main simulation
+initial
+begin: main_sim
+\tSYSRSTN_apb\t= 0;
+\t@ (posedge SYSCLK_apb); #TPD;
+\tSYSRSTN_apb\t= 1;
+
+\t// wait until BFM is finished
+\twhile (!(FINISHED_apb_bfm===1\'b1))
+\tbegin
+\t\t@ (posedge SYSCLK_apb); #TPD;
+\tend
+\tstopsim=1;
+\t#1;
+\t$stop;
+end
+
+endmodule // testbench
+"
+"
+module rgb_led
+(
+\tpclk,
+\tnreset,
+\tbus_write_en, 
+\tbus_read_en,
+\tbus_addr,
+\tbus_write_data,
+\tbus_read_data,
+    pwm_r, pwm_g, pwm_b
+);
+
+
+`define HZ_PER_COLOR_DIVISION 16\'d3921
+
+// 100Hz pwm
+`define PWM_PERIOD 32\'d1000000
+
+// bus lines\t
+input pclk, nreset, bus_write_en, bus_read_en;
+input [7:0] bus_addr;
+input [31:0] bus_write_data;
+output reg [31:0] bus_read_data;
+output reg pwm_r, pwm_g, pwm_b;
+
+// counts to PWM_PERIOD
+reg [31:0] duty_cycle_counter;
+
+reg [31:0] brightness;
+reg [31:0] brightness_factor;
+reg [7:0]  delta_brightness;
+
+// led state registers
+// the led toggles between state 1 and state 2
+
+reg [31:0] led_control;
+
+// 0x En (Enabled bit) P (pulse_rate) RR GG BB
+reg [31:0] pending_led_state_1;
+reg [31:0] pending_led_state_2;
+
+reg [31:0] led_state_1;
+reg [31:0] led_state_2;
+
+// which led state are we in?
+reg [31:0] current_state;
+
+reg enabled;
+reg pulse;
+reg red;
+reg green;
+reg blue;
+
+always@(posedge pclk)
+if(~nreset)
+  begin
+\tpending_led_state_1 <= 32\'h00000000;
+    pending_led_state_2 <= 32\'h00000000;
+  end
+else begin
+\tif(bus_write_en) begin : WRITE
+\t\tcase(bus_addr[3:2])
+\t\t\t2\'b00: // led_control
+                begin 
+\t\t\t\tled_control <= bus_write_data;
+                end
+            2\'b01: // pending_led_state_1
+                begin
+                pending_led_state_1 <= bus_write_data;
+                end
+            2\'b10: // pending_led_state_2
+                begin 
+                pending_led_state_2 <= bus_write_data;
+                end
+        endcase
+    end
+\telse if(bus_read_en) begin : READ
+        case(bus_addr[3:2])
+\t        2\'b00: // led_control
+                begin 
+\t\t        bus_read_data <= led_control;
+\t\t\t\tend
+            2\'b01: // pending_led_state_1
+                begin 
+                bus_read_data <= pending_led_state_1;
+\t\t\t\tend
+            2\'b10: // pending_led_state_2
+                begin 
+                bus_read_data <= pending_led_state_2;
+\t\t\t    end
+        endcase
+     end
+end
+
+always@(posedge pclk) begin
+    enabled <= current_state[31];
+    pulse   <= current_state[30:24];
+    red \t<= current_state[23:16];
+    green \t<= current_state[15:8];
+    blue\t<= current_state[7:0];
+end
+
+// changing global brightness
+always@(posedge pclk) begin
+\tif(brightness == 32\'d100000000) begin
+    \tdelta_brightness = -1;
+    end
+    else begin
+\t\tif(brightness == 32\'d0) begin
+\t\t\tdelta_brightness = 1;
+\t\tend
+\t\telse begin
+\t\t\tbrightness = brightness + delta_brightness;
+\t\tend
+    end
+\tbrightness_factor <= ((`HZ_PER_COLOR_DIVISION * brightness) / 32\'d100000000);
+end
+
+// pulsing colors based on global brightness
+always@(posedge pclk) begin
+if(~nreset)begin
+    led_state_1 <= 32\'h00000000;
+    led_state_2 <= 32\'h00000000;
+\tpwm_r <= 0;
+    pwm_g <= 0;
+    pwm_b <= 0;
+end
+else begin
+\tduty_cycle_counter <= duty_cycle_counter + 1;
+\tif(duty_cycle_counter == `PWM_PERIOD) begin
+    \tduty_cycle_counter <= 0;
+    end
+    else begin
+       //turn off signals that have reached their duty cycle
+\t\tif(red * brightness_factor == duty_cycle_counter) begin
+\t\t\tpwm_r <= 0;
+\t\tend
+\t\tif(blue * brightness_factor == duty_cycle_counter) begin
+\t\t\tpwm_b <= 0;
+\t\tend
+\t\tif(green * brightness_factor == duty_cycle_counter) begin
+\t\t\tpwm_g <= 0;
+\t\tend
+    end
+
+\t// ""overflow"" of the pwm counter, so start a new duty cycle
+    if(duty_cycle_counter == 0)begin
+\t\t// toggle state
+\t\tif(current_state == led_state_1)begin
+\t\t\tcurrent_state <= led_state_2;
+\t\tend
+\t\telse begin
+\t\t\tcurrent_state <= led_state_1;
+\t\tend
+
+\t\tled_state_1 <= pending_led_state_1;
+\t\tled_state_2 <= pending_led_state_2;
+
+    \t//turn on all pwm signals
+\t\t//TODO only if they are non-zero values
+\t\tpwm_r <= 1;
+        pwm_g <= 1;
+        pwm_b <= 1;
+    end
+end
+end
+
+endmodule"
+"//////////////////////////////////////////////////////////////////////
+// Created by SmartDesign Tue Apr 29 08:58:52 2014
+// Version: 10.1 SP3 10.1.3.1
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/100 ps
+
+// cc3000fpga_MSS
+module cc3000fpga_MSS(
+    // Inputs
+    GPIO_2_IN,
+    MSSPRDATA,
+    MSSPREADY,
+    MSSPSLVERR,
+    MSS_RESET_N,
+    SPI_1_DI,
+    UART_0_RXD,
+    UART_1_RXD,
+    // Outputs
+    FAB_CLK,
+    GPIO_4_OUT,
+    M2F_GPO_0,
+    M2F_GPO_1,
+    M2F_GPO_3,
+    M2F_GPO_9,
+    M2F_RESET_N,
+    MSSPADDR,
+    MSSPENABLE,
+    MSSPSEL,
+    MSSPWDATA,
+    MSSPWRITE,
+    SPI_1_DO,
+    UART_0_TXD,
+    UART_1_TXD,
+    // Inouts
+    SPI_1_CLK,
+    SPI_1_SS
+);
+
+//--------------------------------------------------------------------
+// Input
+//--------------------------------------------------------------------
+input         GPIO_2_IN;
+input  [31:0] MSSPRDATA;
+input         MSSPREADY;
+input         MSSPSLVERR;
+input         MSS_RESET_N;
+input         SPI_1_DI;
+input         UART_0_RXD;
+input         UART_1_RXD;
+//--------------------------------------------------------------------
+// Output
+//--------------------------------------------------------------------
+output        FAB_CLK;
+output        GPIO_4_OUT;
+output        M2F_GPO_0;
+output        M2F_GPO_1;
+output        M2F_GPO_3;
+output        M2F_GPO_9;
+output        M2F_RESET_N;
+output [19:0] MSSPADDR;
+output        MSSPENABLE;
+output        MSSPSEL;
+output [31:0] MSSPWDATA;
+output        MSSPWRITE;
+output        SPI_1_DO;
+output        UART_0_TXD;
+output        UART_1_TXD;
+//--------------------------------------------------------------------
+// Inout
+//--------------------------------------------------------------------
+inout         SPI_1_CLK;
+inout         SPI_1_SS;
+//--------------------------------------------------------------------
+// Nets
+//--------------------------------------------------------------------
+wire          GPIO_2_IN;
+wire          MSS_ADLIB_INST_EMCCLK;
+wire          MSS_ADLIB_INST_FCLK;
+wire          MSS_ADLIB_INST_MACCLK;
+wire          MSS_ADLIB_INST_MACCLKCCC;
+wire          MSS_ADLIB_INST_PLLLOCK;
+wire          MSS_ADLIB_INST_SYNCCLKFDBK;
+wire          MSS_GPIO_0_GPIO_2_IN_Y;
+wire   [4:4]  MSS_GPIO_0_GPIO_4_OUT_D;
+wire          MSS_RESET_0_MSS_RESET_N_Y;
+wire          MSS_RESET_N;
+wire          MSS_SPI_1_CLK_D;
+wire          MSS_SPI_1_CLK_Y;
+wire          MSS_SPI_1_DI_Y;
+wire          MSS_SPI_1_DO_D;
+wire          MSS_SPI_1_DO_E;
+wire   [0:0]  MSS_SPI_1_SS_D;
+wire          MSS_SPI_1_SS_E;
+wire          MSS_SPI_1_SS_Y;
+wire          MSS_UART_0_RXD_Y;
+wire          MSS_UART_0_TXD_D;
+wire          MSS_UART_1_RXD_Y;
+wire          MSS_UART_1_TXD_D;
+wire   [0:0]  MSSINT_GPO_0_A;
+wire   [1:1]  MSSINT_GPO_1_A;
+wire   [3:3]  MSSINT_GPO_3_A;
+wire   [9:9]  MSSINT_GPO_9_A;
+wire          net_71;
+wire          net_72;
+wire          net_73;
+wire          net_74;
+wire          net_75;
+wire   [19:0] net_76_PADDR;
+wire          net_76_PENABLE;
+wire   [31:0] MSSPRDATA;
+wire          MSSPREADY;
+wire          net_76_PSELx;
+wire          MSSPSLVERR;
+wire   [31:0] net_76_PWDATA;
+wire          net_76_PWRITE;
+wire          PAD;
+wire          SPI_1_CLK;
+wire          SPI_1_DI;
+wire          SPI_1_DO_net_0;
+wire          SPI_1_SS;
+wire          UART_0_RXD;
+wire          UART_0_TXD_net_0;
+wire          UART_1_RXD;
+wire          UART_1_TXD_net_0;
+wire          net_72_net_0;
+wire          net_71_net_0;
+wire          MSS_ADLIB_INST_SYNCCLKFDBK_net_0;
+wire          net_75_net_0;
+wire          net_76_PSELx_net_0;
+wire          net_76_PENABLE_net_0;
+wire          net_76_PWRITE_net_0;
+wire          net_73_net_0;
+wire          net_74_net_0;
+wire   [19:0] net_76_PADDR_net_0;
+wire   [31:0] net_76_PWDATA_net_0;
+wire          UART_0_TXD_net_1;
+wire          UART_1_TXD_net_1;
+wire          SPI_1_DO_net_1;
+wire          PAD_net_0;
+wire   [31:0] GPI_net_0;
+wire   [31:0] GPO_net_0;
+wire   [7:0]  SPI1SSO_net_0;
+//--------------------------------------------------------------------
+// TiedOff Nets
+//--------------------------------------------------------------------
+wire          GND_net;
+wire          VCC_net;
+wire   [1:0]  DMAREADY_const_net_0;
+wire   [1:0]  MACF2MRXD_const_net_0;
+wire   [1:0]  MACRXD_const_net_0;
+wire   [15:0] EMCRDB_const_net_0;
+wire   [31:0] FABPADDR_const_net_0;
+wire   [31:0] FABPWDATA_const_net_0;
+//--------------------------------------------------------------------
+// Constant assignments
+//--------------------------------------------------------------------
+assign GND_net               = 1\'b0;
+assign VCC_net               = 1\'b1;
+assign DMAREADY_const_net_0  = 2\'h0;
+assign MACF2MRXD_const_net_0 = 2\'h0;
+assign MACRXD_const_net_0    = 2\'h0;
+assign EMCRDB_const_net_0    = 16\'h0000;
+assign FABPADDR_const_net_0  = 32\'h00000000;
+assign FABPWDATA_const_net_0 = 32\'h00000000;
+//--------------------------------------------------------------------
+// Top level output port assignments
+//--------------------------------------------------------------------
+assign net_72_net_0                     = net_72;
+assign M2F_GPO_1                        = net_72_net_0;
+assign net_71_net_0                     = net_71;
+assign M2F_GPO_0                        = net_71_net_0;
+assign MSS_ADLIB_INST_SYNCCLKFDBK_net_0 = MSS_ADLIB_INST_SYNCCLKFDBK;
+assign FAB_CLK                          = MSS_ADLIB_INST_SYNCCLKFDBK_net_0;
+assign net_75_net_0                     = net_75;
+assign M2F_RESET_N                      = net_75_net_0;
+assign net_76_PSELx_net_0               = net_76_PSELx;
+assign MSSPSEL                          = net_76_PSELx_net_0;
+assign net_76_PENABLE_net_0             = net_76_PENABLE;
+assign MSSPENABLE                       = net_76_PENABLE_net_0;
+assign net_76_PWRITE_net_0              = net_76_PWRITE;
+assign MSSPWRITE                        = net_76_PWRITE_net_0;
+assign net_73_net_0                     = net_73;
+assign M2F_GPO_3                        = net_73_net_0;
+assign net_74_net_0                     = net_74;
+assign M2F_GPO_9                        = net_74_net_0;
+assign net_76_PADDR_net_0               = net_76_PADDR;
+assign MSSPADDR[19:0]                   = net_76_PADDR_net_0;
+assign net_76_PWDATA_net_0              = net_76_PWDATA;
+assign MSSPWDATA[31:0]                  = net_76_PWDATA_net_0;
+assign UART_0_TXD_net_1                 = UART_0_TXD_net_0;
+assign UART_0_TXD                       = UART_0_TXD_net_1;
+assign UART_1_TXD_net_1                 = UART_1_TXD_net_0;
+assign UART_1_TXD                       = UART_1_TXD_net_1;
+assign SPI_1_DO_net_1                   = SPI_1_DO_net_0;
+assign SPI_1_DO                         = SPI_1_DO_net_1;
+assign PAD_net_0                        = PAD;
+assign GPIO_4_OUT                       = PAD_net_0;
+//--------------------------------------------------------------------
+// Slices assignments
+//--------------------------------------------------------------------
+assign MSS_GPIO_0_GPIO_4_OUT_D[4] = GPO_net_0[4:4];
+assign MSS_SPI_1_SS_D[0]          = SPI1SSO_net_0[0:0];
+assign MSSINT_GPO_0_A[0]          = GPO_net_0[0:0];
+assign MSSINT_GPO_1_A[1]          = GPO_net_0[1:1];
+assign MSSINT_GPO_3_A[3]          = GPO_net_0[3:3];
+assign MSSINT_GPO_9_A[9]          = GPO_net_0[9:9];
+//--------------------------------------------------------------------
+// Concatenation assignments
+//--------------------------------------------------------------------
+assign GPI_net_0 = { 29\'h00000000 , MSS_GPIO_0_GPIO_2_IN_Y , 2\'h0 };
+//--------------------------------------------------------------------
+// Component instances
+//--------------------------------------------------------------------
+//--------MSS_APB
+MSS_APB #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_DIE    ( ""IP4X3M1"" ),
+        .ACT_FCLK   ( 100000000 ),
+        .ACT_PKG    ( ""fg484"" ) )
+MSS_ADLIB_INST(
+        // Inputs
+        .MSSPRDATA      ( MSSPRDATA ),
+        .MSSPREADY      ( MSSPREADY ),
+        .MSSPSLVERR     ( MSSPSLVERR ),
+        .FABPADDR       ( FABPADDR_const_net_0 ), // tied to 32\'h00000000 from definition
+        .FABPWDATA      ( FABPWDATA_const_net_0 ), // tied to 32\'h00000000 from definition
+        .FABPWRITE      ( GND_net ), // tied to 1\'b0 from definition
+        .FABPSEL        ( GND_net ), // tied to 1\'b0 from definition
+        .FABPENABLE     ( GND_net ), // tied to 1\'b0 from definition
+        .SYNCCLKFDBK    ( MSS_ADLIB_INST_SYNCCLKFDBK ),
+        .CALIBIN        ( GND_net ), // tied to 1\'b0 from definition
+        .FABINT         ( GND_net ), // tied to 1\'b0 from definition
+        .F2MRESETn      ( VCC_net ), // tied to 1\'b1 from definition
+        .DMAREADY       ( DMAREADY_const_net_0 ), // tied to 2\'h0 from definition
+        .RXEV           ( GND_net ), // tied to 1\'b0 from definition
+        .VRON           ( GND_net ), // tied to 1\'b0 from definition
+        .GPI            ( GPI_net_0 ),
+        .UART0CTSn      ( GND_net ), // tied to 1\'b0 from definition
+        .UART0DSRn      ( GND_net ), // tied to 1\'b0 from definition
+        .UART0RIn       ( GND_net ), // tied to 1\'b0 from definition
+        .UART0DCDn      ( GND_net ), // tied to 1\'b0 from definition
+        .UART1CTSn      ( GND_net ), // tied to 1\'b0 from definition
+        .UART1DSRn      ( GND_net ), // tied to 1\'b0 from definition
+        .UART1RIn       ( GND_net ), // tied to 1\'b0 from definition
+        .UART1DCDn      ( GND_net ), // tied to 1\'b0 from definition
+        .I2C0SMBUSNI    ( GND_net ), // tied to 1\'b0 from definition
+        .I2C0SMBALERTNI ( GND_net ), // tied to 1\'b0 from definition
+        .I2C0BCLK       ( GND_net ), // tied to 1\'b0 from definition
+        .I2C1SMBUSNI    ( GND_net ), // tied to 1\'b0 from definition
+        .I2C1SMBALERTNI ( GND_net ), // tied to 1\'b0 from definition
+        .I2C1BCLK       ( GND_net ), // tied to 1\'b0 from definition
+        .MACF2MRXD      ( MACF2MRXD_const_net_0 ), // tied to 2\'h0 from definition
+        .MACF2MCRSDV    ( GND_net ), // tied to 1\'b0 from definition
+        .MACF2MRXER     ( GND_net ), // tied to 1\'b0 from definition
+        .MACF2MMDI      ( GND_net ), // tied to 1\'b0 from definition
+        .FABSDD0D       ( GND_net ), // tied to 1\'b0 from definition
+        .FABSDD1D       ( GND_net ), // tied to 1\'b0 from definition
+        .FABSDD2D       ( GND_net ), // tied to 1\'b0 from definition
+        .FABSDD0CLK     ( GND_net ), // tied to 1\'b0 from definition
+        .FABSDD1CLK     ( GND_net ), // tied to 1\'b0 from definition
+        .FABSDD2CLK     ( GND_net ), // tied to 1\'b0 from definition
+        .FABACETRIG     ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL0EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL1EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL2EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL3EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL4EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL5EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL6EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL7EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL8EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL9EN       ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL10EN      ( GND_net ), // tied to 1\'b0 from definition
+        .LVTTL11EN      ( GND_net ), // tied to 1\'b0 from definition
+        .FCLK           ( MSS_ADLIB_INST_FCLK ),
+        .MACCLKCCC      ( MSS_ADLIB_INST_MACCLKCCC ),
+        .RCOSC          ( GND_net ), // tied to 1\'b0 from definition
+        .MACCLK         ( MSS_ADLIB_INST_MACCLK ),
+        .PLLLOCK        ( MSS_ADLIB_INST_PLLLOCK ),
+        .MSSRESETn      ( MSS_RESET_0_MSS_RESET_N_Y ),
+        .SPI0DI         ( GND_net ), // tied to 1\'b0 from definition
+        .SPI0CLKI       ( GND_net ), // tied to 1\'b0 from definition
+        .SPI0SSI        ( GND_net ), // tied to 1\'b0 from definition
+        .UART0RXD       ( MSS_UART_0_RXD_Y ),
+        .I2C0SDAI       ( GND_net ), // tied to 1\'b0 from definition
+        .I2C0SCLI       ( GND_net ), // tied to 1\'b0 from definition
+        .SPI1DI         ( MSS_SPI_1_DI_Y ),
+        .SPI1CLKI       ( MSS_SPI_1_CLK_Y ),
+        .SPI1SSI        ( MSS_SPI_1_SS_Y ),
+        .UART1RXD       ( MSS_UART_1_RXD_Y ),
+        .I2C1SDAI       ( GND_net ), // tied to 1\'b0 from definition
+        .I2C1SCLI       ( GND_net ), // tied to 1\'b0 from definition
+        .MACRXD         ( MACRXD_const_net_0 ), // tied to 2\'h0 from definition
+        .MACCRSDV       ( GND_net ), // tied to 1\'b0 from definition
+        .MACRXER        ( GND_net ), // tied to 1\'b0 from definition
+        .MACMDI         ( GND_net ), // tied to 1\'b0 from definition
+        .EMCCLKRTN      ( MSS_ADLIB_INST_EMCCLK ),
+        .EMCRDB         ( EMCRDB_const_net_0 ), // tied to 16\'h0000 from definition
+        .ADC0           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC1           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC2           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC3           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC4           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC5           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC6           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC7           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC8           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC9           ( GND_net ), // tied to 1\'b0 from definition
+        .ADC10          ( GND_net ), // tied to 1\'b0 from definition
+        .ADC11          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS0          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS1          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS2          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS3          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS4          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS5          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS6          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS7          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS8          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS9          ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS10         ( GND_net ), // tied to 1\'b0 from definition
+        .ABPS11         ( GND_net ), // tied to 1\'b0 from definition
+        .TM0            ( GND_net ), // tied to 1\'b0 from definition
+        .TM1            ( GND_net ), // tied to 1\'b0 from definition
+        .TM2            ( GND_net ), // tied to 1\'b0 from definition
+        .TM3            ( GND_net ), // tied to 1\'b0 from definition
+        .TM4            ( GND_net ), // tied to 1\'b0 from definition
+        .TM5            ( GND_net ), // tied to 1\'b0 from definition
+        .CM0            ( GND_net ), // tied to 1\'b0 from definition
+        .CM1            ( GND_net ), // tied to 1\'b0 from definition
+        .CM2            ( GND_net ), // tied to 1\'b0 from definition
+        .CM3            ( GND_net ), // tied to 1\'b0 from definition
+        .CM4            ( GND_net ), // tied to 1\'b0 from definition
+        .CM5            ( GND_net ), // tied to 1\'b0 from definition
+        .GNDTM0         ( GND_net ), // tied to 1\'b0 from definition
+        .GNDTM1         ( GND_net ), // tied to 1\'b0 from definition
+        .GNDTM2         ( GND_net ), // tied to 1\'b0 from definition
+        .VAREF0         ( GND_net ), // tied to 1\'b0 from definition
+        .VAREF1         ( GND_net ), // tied to 1\'b0 from definition
+        .VAREF2         ( GND_net ), // tied to 1\'b0 from definition
+        .GNDVAREF       ( GND_net ), // tied to 1\'b0 from definition
+        .PUn            ( GND_net ), // tied to 1\'b0 from definition
+        // Outputs
+        .MSSPADDR       ( net_76_PADDR ),
+        .MSSPWDATA      ( net_76_PWDATA ),
+        .MSSPWRITE      ( net_76_PWRITE ),
+        .MSSPSEL        ( net_76_PSELx ),
+        .MSSPENABLE     ( net_76_PENABLE ),
+        .FABPRDATA      (  ),
+        .FABPREADY      (  ),
+        .FABPSLVERR     (  ),
+        .CALIBOUT       (  ),
+        .MSSINT         (  ),
+        .WDINT          (  ),
+        .M2FRESETn      ( net_75 ),
+        .DEEPSLEEP      (  ),
+        .SLEEP          (  ),
+        .TXEV           (  ),
+        .GPO            ( GPO_net_0 ),
+        .UART0RTSn      (  ),
+        .UART0DTRn      (  ),
+        .UART1RTSn      (  ),
+        .UART1DTRn      (  ),
+        .I2C0SMBUSNO    (  ),
+        .I2C0SMBALERTNO (  ),
+        .I2C1SMBUSNO    (  ),
+        .I2C1SMBALERTNO (  ),
+        .MACM2FTXD      (  ),
+        .MACM2FTXEN     (  ),
+        .MACM2FMDO      (  ),
+        .MACM2FMDEN     (  ),
+        .MACM2FMDC      (  ),
+        .ACEFLAGS       (  ),
+        .CMP0           (  ),
+        .CMP1           (  ),
+        .CMP2           (  ),
+        .CMP3           (  ),
+        .CMP4           (  ),
+        .CMP5           (  ),
+        .CMP6           (  ),
+        .CMP7           (  ),
+        .CMP8           (  ),
+        .CMP9           (  ),
+        .CMP10          (  ),
+        .CMP11          (  ),
+        .LVTTL0         (  ),
+        .LVTTL1         (  ),
+        .LVTTL2         (  ),
+        .LVTTL3         (  ),
+        .LVTTL4         (  ),
+        .LVTTL5         (  ),
+        .LVTTL6         (  ),
+        .LVTTL7         (  ),
+        .LVTTL8         (  ),
+        .LVTTL9         (  ),
+        .LVTTL10        (  ),
+        .LVTTL11        (  ),
+        .PUFABn         (  ),
+        .VCC15GOOD      (  ),
+        .VCC33GOOD      (  ),
+        .GPOE           (  ),
+        .SPI0DO         (  ),
+        .SPI0DOE        (  ),
+        .SPI0CLKO       (  ),
+        .SPI0MODE       (  ),
+        .SPI0SSO        (  ),
+        .UART0TXD       ( MSS_UART_0_TXD_D ),
+        .I2C0SDAO       (  ),
+        .I2C0SCLO       (  ),
+        .SPI1DO         ( MSS_SPI_1_DO_D ),
+        .SPI1DOE        ( MSS_SPI_1_DO_E ),
+        .SPI1CLKO       ( MSS_SPI_1_CLK_D ),
+        .SPI1MODE       ( MSS_SPI_1_SS_E ),
+        .SPI1SSO        ( SPI1SSO_net_0 ),
+        .UART1TXD       ( MSS_UART_1_TXD_D ),
+        .I2C1SDAO       (  ),
+        .I2C1SCLO       (  ),
+        .MACTXD         (  ),
+        .MACTXEN        (  ),
+        .MACMDO         (  ),
+        .MACMDEN        (  ),
+        .MACMDC         (  ),
+        .EMCCLK         ( MSS_ADLIB_INST_EMCCLK ),
+        .EMCAB          (  ),
+        .EMCWDB         (  ),
+        .EMCRWn         (  ),
+        .EMCCS0n        (  ),
+        .EMCCS1n        (  ),
+        .EMCOEN0n       (  ),
+        .EMCOEN1n       (  ),
+        .EMCBYTEN       (  ),
+        .EMCDBOE        (  ),
+        .SDD0           (  ),
+        .SDD1           (  ),
+        .SDD2           (  ),
+        .VAREFOUT       (  ) 
+        );
+
+//--------cc3000fpga_MSS_tmp_MSS_CCC_0_MSS_CCC   -   Actel:SmartFusionMSS:MSS_CCC:2.0.106
+cc3000fpga_MSS_tmp_MSS_CCC_0_MSS_CCC MSS_CCC_0(
+        // Inputs
+        .CLKA           ( GND_net ), // tied to 1\'b0 from definition
+        .CLKA_PAD       ( GND_net ), // tied to 1\'b0 from definition
+        .CLKA_PADP      ( GND_net ), // tied to 1\'b0 from definition
+        .CLKA_PADN      ( GND_net ), // tied to 1\'b0 from definition
+        .CLKB           ( GND_net ), // tied to 1\'b0 from definition
+        .CLKB_PAD       ( GND_net ), // tied to 1\'b0 from definition
+        .CLKB_PADP      ( GND_net ), // tied to 1\'b0 from definition
+        .CLKB_PADN      ( GND_net ), // tied to 1\'b0 from definition
+        .CLKC           ( GND_net ), // tied to 1\'b0 from definition
+        .CLKC_PAD       ( GND_net ), // tied to 1\'b0 from definition
+        .CLKC_PADP      ( GND_net ), // tied to 1\'b0 from definition
+        .CLKC_PADN      ( GND_net ), // tied to 1\'b0 from definition
+        .MAINXIN        ( GND_net ), // tied to 1\'b0 from definition
+        .LPXIN          ( GND_net ), // tied to 1\'b0 from definition
+        .MAC_CLK        ( GND_net ), // tied to 1\'b0 from definition
+        // Outputs
+        .GLA            (  ),
+        .GLB            (  ),
+        .GLC            (  ),
+        .FAB_CLK        ( MSS_ADLIB_INST_SYNCCLKFDBK ),
+        .YB             (  ),
+        .YC             (  ),
+        .FAB_LOCK       (  ),
+        .RCOSC_CLKOUT   (  ),
+        .MAINXIN_CLKOUT (  ),
+        .LPXIN_CLKOUT   (  ),
+        .GLA0           ( MSS_ADLIB_INST_FCLK ),
+        .MSS_LOCK       ( MSS_ADLIB_INST_PLLLOCK ),
+        .MAC_CLK_CCC    ( MSS_ADLIB_INST_MACCLKCCC ),
+        .MAC_CLK_IO     ( MSS_ADLIB_INST_MACCLK ) 
+        );
+
+//--------INBUF_MSS
+INBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""W1"" ) )
+MSS_GPIO_0_GPIO_2_IN(
+        // Inputs
+        .PAD ( GPIO_2_IN ),
+        // Outputs
+        .Y   ( MSS_GPIO_0_GPIO_2_IN_Y ) 
+        );
+
+//--------OUTBUF_MSS
+OUTBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""AA1"" ) )
+MSS_GPIO_0_GPIO_4_OUT(
+        // Inputs
+        .D   ( MSS_GPIO_0_GPIO_4_OUT_D ),
+        // Outputs
+        .PAD ( PAD ) 
+        );
+
+//--------INBUF_MSS
+INBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""R1"" ) )
+MSS_RESET_0_MSS_RESET_N(
+        // Inputs
+        .PAD ( MSS_RESET_N ),
+        // Outputs
+        .Y   ( MSS_RESET_0_MSS_RESET_N_Y ) 
+        );
+
+//--------BIBUF_MSS
+BIBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""AA22"" ) )
+MSS_SPI_1_CLK(
+        // Inputs
+        .D   ( MSS_SPI_1_CLK_D ),
+        .E   ( MSS_SPI_1_SS_E ),
+        // Outputs
+        .Y   ( MSS_SPI_1_CLK_Y ),
+        // Inouts
+        .PAD ( SPI_1_CLK ) 
+        );
+
+//--------INBUF_MSS
+INBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""V19"" ) )
+MSS_SPI_1_DI(
+        // Inputs
+        .PAD ( SPI_1_DI ),
+        // Outputs
+        .Y   ( MSS_SPI_1_DI_Y ) 
+        );
+
+//--------TRIBUFF_MSS
+TRIBUFF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""T17"" ) )
+MSS_SPI_1_DO(
+        // Inputs
+        .D   ( MSS_SPI_1_DO_D ),
+        .E   ( MSS_SPI_1_DO_E ),
+        // Outputs
+        .PAD ( SPI_1_DO_net_0 ) 
+        );
+
+//--------BIBUF_MSS
+BIBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""W21"" ) )
+MSS_SPI_1_SS(
+        // Inputs
+        .D   ( MSS_SPI_1_SS_D ),
+        .E   ( MSS_SPI_1_SS_E ),
+        // Outputs
+        .Y   ( MSS_SPI_1_SS_Y ),
+        // Inouts
+        .PAD ( SPI_1_SS ) 
+        );
+
+//--------INBUF_MSS
+INBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""U18"" ) )
+MSS_UART_0_RXD(
+        // Inputs
+        .PAD ( UART_0_RXD ),
+        // Outputs
+        .Y   ( MSS_UART_0_RXD_Y ) 
+        );
+
+//--------OUTBUF_MSS
+OUTBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""Y22"" ) )
+MSS_UART_0_TXD(
+        // Inputs
+        .D   ( MSS_UART_0_TXD_D ),
+        // Outputs
+        .PAD ( UART_0_TXD_net_0 ) 
+        );
+
+//--------INBUF_MSS
+INBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""W22"" ) )
+MSS_UART_1_RXD(
+        // Inputs
+        .PAD ( UART_1_RXD ),
+        // Outputs
+        .Y   ( MSS_UART_1_RXD_Y ) 
+        );
+
+//--------OUTBUF_MSS
+OUTBUF_MSS #( 
+        .ACT_CONFIG ( 0 ),
+        .ACT_PIN    ( ""V20"" ) )
+MSS_UART_1_TXD(
+        // Inputs
+        .D   ( MSS_UART_1_TXD_D ),
+        // Outputs
+        .PAD ( UART_1_TXD_net_0 ) 
+        );
+
+//--------MSSINT
+MSSINT MSSINT_GPO_0(
+        // Inputs
+        .A ( MSSINT_GPO_0_A ),
+        // Outputs
+        .Y ( net_71 ) 
+        );
+
+//--------MSSINT
+MSSINT MSSINT_GPO_1(
+        // Inputs
+        .A ( MSSINT_GPO_1_A ),
+        // Outputs
+        .Y ( net_72 ) 
+        );
+
+//--------MSSINT
+MSSINT MSSINT_GPO_3(
+        // Inputs
+        .A ( MSSINT_GPO_3_A ),
+        // Outputs
+        .Y ( net_73 ) 
+        );
+
+//--------MSSINT
+MSSINT MSSINT_GPO_9(
+        // Inputs
+        .A ( MSSINT_GPO_9_A ),
+        // Outputs
+        .Y ( net_74 ) 
+        );
+
+
+endmodule
+"
+"
+module spi2fabric(in_from_fabric_di, out_to_spi_di, in_from_spi_do, out_to_fabric_do, in_from_spi_clk, out_to_fabric_clk, in_from_spi_ss, out_to_fabric_ss);
+
+input in_from_fabric_di, in_from_spi_do, in_from_spi_clk, in_from_spi_ss;
+output out_to_spi_di, out_to_fabric_do, out_to_fabric_clk, out_to_fabric_ss;
+
+assign out_to_spi_di = in_from_fabric_di;
+assign out_to_fabric_do = in_from_spi_do;
+assign out_to_fabric_clk = in_from_spi_clk;
+assign out_to_fabric_ss = in_from_spi_ss;
+
+endmodule
+
+"
+"// Actel Corporation Proprietary and Confidential
+// Copyright 2008 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+// Revision Information:
+// SVN Revision Information:
+// SVN $Revision: 11864 $
+// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
+`timescale 1ns/100ps
+module
+BFM_APB
+(
+SYSCLK
+,
+SYSRSTN
+,
+PCLK
+,
+PRESETN
+,
+PADDR
+,
+PENABLE
+,
+PWRITE
+,
+PWDATA
+,
+PRDATA
+,
+PREADY
+,
+PSLVERR
+,
+PSEL
+,
+INTERRUPT
+,
+GP_OUT
+,
+GP_IN
+,
+EXT_WR
+,
+EXT_RD
+,
+EXT_ADDR
+,
+EXT_DATA
+,
+EXT_WAIT
+,
+FINISHED
+,
+FAILED
+)
+;
+parameter
+VECTFILE
+=
+""test.vec""
+;
+parameter
+MAX_INSTRUCTIONS
+=
+16384
+;
+parameter
+MAX_STACK
+=
+1024
+;
+parameter
+MAX_MEMTEST
+=
+65536
+;
+parameter
+TPD
+=
+1
+;
+parameter
+DEBUGLEVEL
+=
+-
+1
+;
+parameter
+ARGVALUE0
+=
+0
+;
+parameter
+ARGVALUE1
+=
+0
+;
+parameter
+ARGVALUE2
+=
+0
+;
+parameter
+ARGVALUE3
+=
+0
+;
+parameter
+ARGVALUE4
+=
+0
+;
+parameter
+ARGVALUE5
+=
+0
+;
+parameter
+ARGVALUE6
+=
+0
+;
+parameter
+ARGVALUE7
+=
+0
+;
+parameter
+ARGVALUE8
+=
+0
+;
+parameter
+ARGVALUE9
+=
+0
+;
+parameter
+ARGVALUE10
+=
+0
+;
+parameter
+ARGVALUE11
+=
+0
+;
+parameter
+ARGVALUE12
+=
+0
+;
+parameter
+ARGVALUE13
+=
+0
+;
+parameter
+ARGVALUE14
+=
+0
+;
+parameter
+ARGVALUE15
+=
+0
+;
+parameter
+ARGVALUE16
+=
+0
+;
+parameter
+ARGVALUE17
+=
+0
+;
+parameter
+ARGVALUE18
+=
+0
+;
+parameter
+ARGVALUE19
+=
+0
+;
+parameter
+ARGVALUE20
+=
+0
+;
+parameter
+ARGVALUE21
+=
+0
+;
+parameter
+ARGVALUE22
+=
+0
+;
+parameter
+ARGVALUE23
+=
+0
+;
+parameter
+ARGVALUE24
+=
+0
+;
+parameter
+ARGVALUE25
+=
+0
+;
+parameter
+ARGVALUE26
+=
+0
+;
+parameter
+ARGVALUE27
+=
+0
+;
+parameter
+ARGVALUE28
+=
+0
+;
+parameter
+ARGVALUE29
+=
+0
+;
+parameter
+ARGVALUE30
+=
+0
+;
+parameter
+ARGVALUE31
+=
+0
+;
+parameter
+ARGVALUE32
+=
+0
+;
+parameter
+ARGVALUE33
+=
+0
+;
+parameter
+ARGVALUE34
+=
+0
+;
+parameter
+ARGVALUE35
+=
+0
+;
+parameter
+ARGVALUE36
+=
+0
+;
+parameter
+ARGVALUE37
+=
+0
+;
+parameter
+ARGVALUE38
+=
+0
+;
+parameter
+ARGVALUE39
+=
+0
+;
+parameter
+ARGVALUE40
+=
+0
+;
+parameter
+ARGVALUE41
+=
+0
+;
+parameter
+ARGVALUE42
+=
+0
+;
+parameter
+ARGVALUE43
+=
+0
+;
+parameter
+ARGVALUE44
+=
+0
+;
+parameter
+ARGVALUE45
+=
+0
+;
+parameter
+ARGVALUE46
+=
+0
+;
+parameter
+ARGVALUE47
+=
+0
+;
+parameter
+ARGVALUE48
+=
+0
+;
+parameter
+ARGVALUE49
+=
+0
+;
+parameter
+ARGVALUE50
+=
+0
+;
+parameter
+ARGVALUE51
+=
+0
+;
+parameter
+ARGVALUE52
+=
+0
+;
+parameter
+ARGVALUE53
+=
+0
+;
+parameter
+ARGVALUE54
+=
+0
+;
+parameter
+ARGVALUE55
+=
+0
+;
+parameter
+ARGVALUE56
+=
+0
+;
+parameter
+ARGVALUE57
+=
+0
+;
+parameter
+ARGVALUE58
+=
+0
+;
+parameter
+ARGVALUE59
+=
+0
+;
+parameter
+ARGVALUE60
+=
+0
+;
+parameter
+ARGVALUE61
+=
+0
+;
+parameter
+ARGVALUE62
+=
+0
+;
+parameter
+ARGVALUE63
+=
+0
+;
+parameter
+ARGVALUE64
+=
+0
+;
+parameter
+ARGVALUE65
+=
+0
+;
+parameter
+ARGVALUE66
+=
+0
+;
+parameter
+ARGVALUE67
+=
+0
+;
+parameter
+ARGVALUE68
+=
+0
+;
+parameter
+ARGVALUE69
+=
+0
+;
+parameter
+ARGVALUE70
+=
+0
+;
+parameter
+ARGVALUE71
+=
+0
+;
+parameter
+ARGVALUE72
+=
+0
+;
+parameter
+ARGVALUE73
+=
+0
+;
+parameter
+ARGVALUE74
+=
+0
+;
+parameter
+ARGVALUE75
+=
+0
+;
+parameter
+ARGVALUE76
+=
+0
+;
+parameter
+ARGVALUE77
+=
+0
+;
+parameter
+ARGVALUE78
+=
+0
+;
+parameter
+ARGVALUE79
+=
+0
+;
+parameter
+ARGVALUE80
+=
+0
+;
+parameter
+ARGVALUE81
+=
+0
+;
+parameter
+ARGVALUE82
+=
+0
+;
+parameter
+ARGVALUE83
+=
+0
+;
+parameter
+ARGVALUE84
+=
+0
+;
+parameter
+ARGVALUE85
+=
+0
+;
+parameter
+ARGVALUE86
+=
+0
+;
+parameter
+ARGVALUE87
+=
+0
+;
+parameter
+ARGVALUE88
+=
+0
+;
+parameter
+ARGVALUE89
+=
+0
+;
+parameter
+ARGVALUE90
+=
+0
+;
+parameter
+ARGVALUE91
+=
+0
+;
+parameter
+ARGVALUE92
+=
+0
+;
+parameter
+ARGVALUE93
+=
+0
+;
+parameter
+ARGVALUE94
+=
+0
+;
+parameter
+ARGVALUE95
+=
+0
+;
+parameter
+ARGVALUE96
+=
+0
+;
+parameter
+ARGVALUE97
+=
+0
+;
+parameter
+ARGVALUE98
+=
+0
+;
+parameter
+ARGVALUE99
+=
+0
+;
+localparam
+OPMODE
+=
+0
+;
+localparam
+CON_SPULSE
+=
+0
+;
+input
+SYSCLK
+;
+input
+SYSRSTN
+;
+output
+PCLK
+;
+wire
+PCLK
+;
+output
+PRESETN
+;
+wire
+PRESETN
+;
+output
+[
+31
+:
+0
+]
+PADDR
+;
+wire
+[
+31
+:
+0
+]
+PADDR
+;
+output
+PENABLE
+;
+wire
+PENABLE
+;
+output
+PWRITE
+;
+wire
+PWRITE
+;
+output
+[
+31
+:
+0
+]
+PWDATA
+;
+wire
+[
+31
+:
+0
+]
+PWDATA
+;
+input
+[
+31
+:
+0
+]
+PRDATA
+;
+input
+PREADY
+;
+input
+PSLVERR
+;
+output
+[
+15
+:
+0
+]
+PSEL
+;
+wire
+[
+15
+:
+0
+]
+PSEL
+;
+input
+[
+255
+:
+0
+]
+INTERRUPT
+;
+output
+[
+31
+:
+0
+]
+GP_OUT
+;
+wire
+[
+31
+:
+0
+]
+GP_OUT
+;
+input
+[
+31
+:
+0
+]
+GP_IN
+;
+output
+EXT_WR
+;
+wire
+EXT_WR
+;
+output
+EXT_RD
+;
+wire
+EXT_RD
+;
+output
+[
+31
+:
+0
+]
+EXT_ADDR
+;
+wire
+[
+31
+:
+0
+]
+EXT_ADDR
+;
+inout
+[
+31
+:
+0
+]
+EXT_DATA
+;
+wire
+[
+31
+:
+0
+]
+EXT_DATA
+;
+wire
+[
+31
+:
+0
+]
+BFMA1O1OII
+;
+input
+EXT_WAIT
+;
+output
+FINISHED
+;
+wire
+FINISHED
+;
+output
+FAILED
+;
+wire
+FAILED
+;
+wire
+BFMA1l0lII
+;
+wire
+BFMA1O1lII
+;
+wire
+BFMA1I1lII
+;
+wire
+[
+31
+:
+0
+]
+BFMA1l1lII
+;
+wire
+[
+2
+:
+0
+]
+BFMA1OO0II
+;
+wire
+BFMA1IO0II
+;
+wire
+[
+3
+:
+0
+]
+BFMA1lO0II
+;
+wire
+[
+2
+:
+0
+]
+BFMA1OI0II
+;
+wire
+[
+1
+:
+0
+]
+BFMA1II0II
+;
+wire
+BFMA1lI0II
+;
+wire
+[
+31
+:
+0
+]
+BFMA1Ol0II
+;
+wire
+[
+31
+:
+0
+]
+BFMA1Il0II
+;
+wire
+BFMA1ll0II
+;
+wire
+BFMA1O00II
+;
+wire
+BFMA1I00II
+;
+wire
+BFMA1l00II
+;
+wire
+[
+15
+:
+0
+]
+BFMA1O10II
+;
+wire
+[
+31
+:
+0
+]
+INSTR_IN
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+assign
+EXT_DATA
+=
+BFMA1O1OII
+;
+BFM_MAIN
+#
+(
+OPMODE
+,
+VECTFILE
+,
+MAX_INSTRUCTIONS
+,
+MAX_STACK
+,
+MAX_MEMTEST
+,
+TPD
+,
+DEBUGLEVEL
+,
+CON_SPULSE
+,
+ARGVALUE0
+,
+ARGVALUE1
+,
+ARGVALUE2
+,
+ARGVALUE3
+,
+ARGVALUE4
+,
+ARGVALUE5
+,
+ARGVALUE6
+,
+ARGVALUE7
+,
+ARGVALUE8
+,
+ARGVALUE9
+,
+ARGVALUE10
+,
+ARGVALUE11
+,
+ARGVALUE12
+,
+ARGVALUE13
+,
+ARGVALUE14
+,
+ARGVALUE15
+,
+ARGVALUE16
+,
+ARGVALUE17
+,
+ARGVALUE18
+,
+ARGVALUE19
+,
+ARGVALUE20
+,
+ARGVALUE21
+,
+ARGVALUE22
+,
+ARGVALUE23
+,
+ARGVALUE24
+,
+ARGVALUE25
+,
+ARGVALUE26
+,
+ARGVALUE27
+,
+ARGVALUE28
+,
+ARGVALUE29
+,
+ARGVALUE30
+,
+ARGVALUE31
+,
+ARGVALUE32
+,
+ARGVALUE33
+,
+ARGVALUE34
+,
+ARGVALUE35
+,
+ARGVALUE36
+,
+ARGVALUE37
+,
+ARGVALUE38
+,
+ARGVALUE39
+,
+ARGVALUE40
+,
+ARGVALUE41
+,
+ARGVALUE42
+,
+ARGVALUE43
+,
+ARGVALUE44
+,
+ARGVALUE45
+,
+ARGVALUE46
+,
+ARGVALUE47
+,
+ARGVALUE48
+,
+ARGVALUE49
+,
+ARGVALUE50
+,
+ARGVALUE51
+,
+ARGVALUE52
+,
+ARGVALUE53
+,
+ARGVALUE54
+,
+ARGVALUE55
+,
+ARGVALUE56
+,
+ARGVALUE57
+,
+ARGVALUE58
+,
+ARGVALUE59
+,
+ARGVALUE60
+,
+ARGVALUE61
+,
+ARGVALUE62
+,
+ARGVALUE63
+,
+ARGVALUE64
+,
+ARGVALUE65
+,
+ARGVALUE66
+,
+ARGVALUE67
+,
+ARGVALUE68
+,
+ARGVALUE69
+,
+ARGVALUE70
+,
+ARGVALUE71
+,
+ARGVALUE72
+,
+ARGVALUE73
+,
+ARGVALUE74
+,
+ARGVALUE75
+,
+ARGVALUE76
+,
+ARGVALUE77
+,
+ARGVALUE78
+,
+ARGVALUE79
+,
+ARGVALUE80
+,
+ARGVALUE81
+,
+ARGVALUE82
+,
+ARGVALUE83
+,
+ARGVALUE84
+,
+ARGVALUE85
+,
+ARGVALUE86
+,
+ARGVALUE87
+,
+ARGVALUE88
+,
+ARGVALUE89
+,
+ARGVALUE90
+,
+ARGVALUE91
+,
+ARGVALUE92
+,
+ARGVALUE93
+,
+ARGVALUE94
+,
+ARGVALUE95
+,
+ARGVALUE96
+,
+ARGVALUE97
+,
+ARGVALUE98
+,
+ARGVALUE99
+)
+BFMA1I1OII
+(
+.SYSCLK
+(
+SYSCLK
+)
+,
+.SYSRSTN
+(
+SYSRSTN
+)
+,
+.HADDR
+(
+BFMA1l1lII
+)
+,
+.HCLK
+(
+BFMA1O1lII
+)
+,
+.PCLK
+(
+BFMA1l0lII
+)
+,
+.HRESETN
+(
+BFMA1I1lII
+)
+,
+.HBURST
+(
+BFMA1OO0II
+)
+,
+.HMASTLOCK
+(
+BFMA1IO0II
+)
+,
+.HPROT
+(
+BFMA1lO0II
+)
+,
+.HSIZE
+(
+BFMA1OI0II
+)
+,
+.HTRANS
+(
+BFMA1II0II
+)
+,
+.HWRITE
+(
+BFMA1lI0II
+)
+,
+.HWDATA
+(
+BFMA1Il0II
+)
+,
+.HRDATA
+(
+BFMA1Ol0II
+)
+,
+.HREADY
+(
+BFMA1ll0II
+)
+,
+.HRESP
+(
+BFMA1l00II
+)
+,
+.HSEL
+(
+BFMA1O10II
+)
+,
+.INTERRUPT
+(
+INTERRUPT
+)
+,
+.GP_OUT
+(
+GP_OUT
+)
+,
+.GP_IN
+(
+GP_IN
+)
+,
+.EXT_WR
+(
+EXT_WR
+)
+,
+.EXT_RD
+(
+EXT_RD
+)
+,
+.EXT_ADDR
+(
+EXT_ADDR
+)
+,
+.EXT_DATA
+(
+EXT_DATA
+)
+,
+.EXT_WAIT
+(
+EXT_WAIT
+)
+,
+.CON_ADDR
+(
+16
+\'b
+0
+)
+,
+.CON_DATA
+(
+)
+,
+.CON_RD
+(
+1
+\'b
+0
+)
+,
+.CON_WR
+(
+1
+\'b
+0
+)
+,
+.CON_BUSY
+(
+)
+,
+.INSTR_OUT
+(
+)
+,
+.INSTR_IN
+(
+INSTR_IN
+)
+,
+.FINISHED
+(
+FINISHED
+)
+,
+.FAILED
+(
+FAILED
+)
+)
+;
+assign
+PCLK
+=
+BFMA1l0lII
+;
+assign
+PRESETN
+=
+BFMA1I1lII
+;
+BFMA1l1OII
+#
+(
+TPD
+)
+BFMA1lO1II
+(
+.HCLK
+(
+BFMA1O1lII
+)
+,
+.HRESETN
+(
+BFMA1I1lII
+)
+,
+.HSEL
+(
+1
+\'b
+1
+)
+,
+.HWRITE
+(
+BFMA1lI0II
+)
+,
+.HADDR
+(
+BFMA1l1lII
+)
+,
+.HWDATA
+(
+BFMA1Il0II
+)
+,
+.HRDATA
+(
+BFMA1Ol0II
+)
+,
+.HREADYIN
+(
+BFMA1ll0II
+)
+,
+.HREADYOUT
+(
+BFMA1ll0II
+)
+,
+.HTRANS
+(
+BFMA1II0II
+)
+,
+.HSIZE
+(
+BFMA1OI0II
+)
+,
+.HBURST
+(
+BFMA1OO0II
+)
+,
+.HMASTLOCK
+(
+BFMA1IO0II
+)
+,
+.HPROT
+(
+BFMA1lO0II
+)
+,
+.HRESP
+(
+BFMA1l00II
+)
+,
+.PSEL
+(
+PSEL
+)
+,
+.PADDR
+(
+PADDR
+)
+,
+.PWRITE
+(
+PWRITE
+)
+,
+.PENABLE
+(
+PENABLE
+)
+,
+.PWDATA
+(
+PWDATA
+)
+,
+.PRDATA
+(
+PRDATA
+)
+,
+.PREADY
+(
+PREADY
+)
+,
+.PSLVERR
+(
+PSLVERR
+)
+)
+;
+endmodule
+"
+"// ********************************************************************/ 
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+//  
+// Description: AMBA BFMs
+//              APB Master Wrapper  
+//
+// Revision Information:
+// Date     Description
+// 01Sep07  Initial Release 
+// 14Sep07  Updated for 1.2 functionality
+// 25Sep07  Updated for 1.3 functionality
+// 09Nov07  Updated for 1.4 functionality
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+//
+// Resolved SARs
+// SAR      Date     Who  Description
+//
+//
+// Notes: 
+//        
+// *********************************************************************/ 
+
+`timescale 1 ns / 100 ps
+
+module BFM_APB (SYSCLK, SYSRSTN, PCLK, PRESETN, PADDR, PENABLE, PWRITE, PWDATA, PRDATA, PREADY, PSLVERR, PSEL, INTERRUPT, GP_OUT, GP_IN, EXT_WR, EXT_RD, EXT_ADDR, EXT_DATA, EXT_WAIT, CON_ADDR, CON_DATA, CON_RD, CON_WR, CON_BUSY, FINISHED, FAILED);
+
+    parameter OPMODE     = 0;
+    parameter VECTFILE    = ""test.vec"";
+    parameter MAX_INSTRUCTIONS  = 16384;
+    parameter MAX_STACK  = 1024;
+    parameter MAX_MEMTEST = 65536;
+    parameter TPD        = 1;
+    parameter DEBUGLEVEL = -1;
+    parameter CON_SPULSE = 0;
+    parameter ARGVALUE0  = 0;
+    parameter ARGVALUE1  = 0;
+    parameter ARGVALUE2  = 0;
+    parameter ARGVALUE3  = 0;
+    parameter ARGVALUE4  = 0;
+    parameter ARGVALUE5  = 0;
+    parameter ARGVALUE6  = 0;
+    parameter ARGVALUE7  = 0;
+    parameter ARGVALUE8  = 0;
+    parameter ARGVALUE9  = 0;
+    parameter ARGVALUE10 = 0;
+    parameter ARGVALUE11 = 0;
+    parameter ARGVALUE12 = 0;
+    parameter ARGVALUE13 = 0;
+    parameter ARGVALUE14 = 0;
+    parameter ARGVALUE15 = 0;
+    parameter ARGVALUE16 = 0;
+    parameter ARGVALUE17 = 0;
+    parameter ARGVALUE18 = 0;
+    parameter ARGVALUE19 = 0;
+    parameter ARGVALUE20 = 0;
+    parameter ARGVALUE21 = 0;
+    parameter ARGVALUE22 = 0;
+    parameter ARGVALUE23 = 0;
+    parameter ARGVALUE24 = 0;
+    parameter ARGVALUE25 = 0;
+    parameter ARGVALUE26 = 0;
+    parameter ARGVALUE27 = 0;
+    parameter ARGVALUE28 = 0;
+    parameter ARGVALUE29 = 0;
+    parameter ARGVALUE30 = 0;
+    parameter ARGVALUE31 = 0;
+    parameter ARGVALUE32 = 0;
+    parameter ARGVALUE33 = 0;
+    parameter ARGVALUE34 = 0;
+    parameter ARGVALUE35 = 0;
+    parameter ARGVALUE36 = 0;
+    parameter ARGVALUE37 = 0;
+    parameter ARGVALUE38 = 0;
+    parameter ARGVALUE39 = 0;
+    parameter ARGVALUE40 = 0;
+    parameter ARGVALUE41 = 0;
+    parameter ARGVALUE42 = 0;
+    parameter ARGVALUE43 = 0;
+    parameter ARGVALUE44 = 0;
+    parameter ARGVALUE45 = 0;
+    parameter ARGVALUE46 = 0;
+    parameter ARGVALUE47 = 0;
+    parameter ARGVALUE48 = 0;
+    parameter ARGVALUE49 = 0;
+    parameter ARGVALUE50 = 0;
+    parameter ARGVALUE51 = 0;
+    parameter ARGVALUE52 = 0;
+    parameter ARGVALUE53 = 0;
+    parameter ARGVALUE54 = 0;
+    parameter ARGVALUE55 = 0;
+    parameter ARGVALUE56 = 0;
+    parameter ARGVALUE57 = 0;
+    parameter ARGVALUE58 = 0;
+    parameter ARGVALUE59 = 0;
+    parameter ARGVALUE60 = 0;
+    parameter ARGVALUE61 = 0;
+    parameter ARGVALUE62 = 0;
+    parameter ARGVALUE63 = 0;
+    parameter ARGVALUE64 = 0;
+    parameter ARGVALUE65 = 0;
+    parameter ARGVALUE66 = 0;
+    parameter ARGVALUE67 = 0;
+    parameter ARGVALUE68 = 0;
+    parameter ARGVALUE69 = 0;
+    parameter ARGVALUE70 = 0;
+    parameter ARGVALUE71 = 0;
+    parameter ARGVALUE72 = 0;
+    parameter ARGVALUE73 = 0;
+    parameter ARGVALUE74 = 0;
+    parameter ARGVALUE75 = 0;
+    parameter ARGVALUE76 = 0;
+    parameter ARGVALUE77 = 0;
+    parameter ARGVALUE78 = 0;
+    parameter ARGVALUE79 = 0;
+    parameter ARGVALUE80 = 0;
+    parameter ARGVALUE81 = 0;
+    parameter ARGVALUE82 = 0;
+    parameter ARGVALUE83 = 0;
+    parameter ARGVALUE84 = 0;
+    parameter ARGVALUE85 = 0;
+    parameter ARGVALUE86 = 0;
+    parameter ARGVALUE87 = 0;
+    parameter ARGVALUE88 = 0;
+    parameter ARGVALUE89 = 0;
+    parameter ARGVALUE90 = 0;
+    parameter ARGVALUE91 = 0;
+    parameter ARGVALUE92 = 0;
+    parameter ARGVALUE93 = 0;
+    parameter ARGVALUE94 = 0;
+    parameter ARGVALUE95 = 0;
+    parameter ARGVALUE96 = 0;
+    parameter ARGVALUE97 = 0;
+    parameter ARGVALUE98 = 0;
+    parameter ARGVALUE99 = 0;
+
+    input SYSCLK; 
+    input SYSRSTN; 
+    output PCLK; 
+    wire PCLK;
+    output PRESETN; 
+    wire PRESETN;
+    output[31:0] PADDR; 
+    wire[31:0] PADDR;
+    output PENABLE; 
+    wire PENABLE;
+    output PWRITE; 
+    wire PWRITE;
+    output[31:0] PWDATA; 
+    wire[31:0] PWDATA;
+    input[31:0] PRDATA; 
+    input PREADY; 
+    input PSLVERR; 
+    output[15:0] PSEL; 
+    wire[15:0] PSEL;
+    input[255:0] INTERRUPT; 
+    output[31:0] GP_OUT; 
+    wire[31:0] GP_OUT;
+    input[31:0] GP_IN; 
+    output EXT_WR; 
+    wire EXT_WR;
+    output EXT_RD; 
+    wire EXT_RD;
+    output[31:0] EXT_ADDR; 
+    wire[31:0] EXT_ADDR;
+    inout[31:0] EXT_DATA; 
+    wire[31:0] EXT_DATA;
+    input EXT_WAIT; 
+    input[15:0] CON_ADDR; 
+    inout[31:0] CON_DATA; 
+    wire[31:0] CON_DATA;
+    input CON_RD; 
+    input CON_WR; 
+    output CON_BUSY; 
+    wire CON_BUSY;
+    output FINISHED; 
+    wire FINISHED;
+    output FAILED; 
+    wire FAILED;
+
+    wire iPCLk; 
+    wire iHCLk; 
+    wire iHRESETN; 
+    wire[31:0] iHADDR; 
+    wire[2:0] iHBURST; 
+    wire iHMASTLOCK; 
+    wire[3:0] iHPROT; 
+    wire[2:0] iHSIZE; 
+    wire[1:0] iHTRANS; 
+    wire iHWRITE; 
+    wire[31:0] iHRDATA; 
+    wire[31:0] iHWDATA; 
+    wire iHREADY; 
+    wire iHREADYIN; 
+    wire iHREADYOUT; 
+    wire iHRESP; 
+    wire[15:0] iHSEL; 
+    wire[31:0] INSTR_IN = {32{1\'b0}}; 
+
+
+    BFM_MAIN #( OPMODE, VECTFILE, MAX_INSTRUCTIONS, MAX_STACK, MAX_MEMTEST, TPD, DEBUGLEVEL, CON_SPULSE,
+                ARGVALUE0,  ARGVALUE1,  ARGVALUE2,  ARGVALUE3,  ARGVALUE4,  ARGVALUE5,  ARGVALUE6,  ARGVALUE7,  ARGVALUE8,  ARGVALUE9,
+                ARGVALUE10, ARGVALUE11, ARGVALUE12, ARGVALUE13, ARGVALUE14, ARGVALUE15, ARGVALUE16, ARGVALUE17, ARGVALUE18, ARGVALUE19,
+                ARGVALUE20, ARGVALUE21, ARGVALUE22, ARGVALUE23, ARGVALUE24, ARGVALUE25, ARGVALUE26, ARGVALUE27, ARGVALUE28, ARGVALUE29,
+                ARGVALUE30, ARGVALUE31, ARGVALUE32, ARGVALUE33, ARGVALUE34, ARGVALUE35, ARGVALUE36, ARGVALUE37, ARGVALUE38, ARGVALUE39,
+                ARGVALUE40, ARGVALUE41, ARGVALUE42, ARGVALUE43, ARGVALUE44, ARGVALUE45, ARGVALUE46, ARGVALUE47, ARGVALUE48, ARGVALUE49,
+                ARGVALUE50, ARGVALUE51, ARGVALUE52, ARGVALUE53, ARGVALUE54, ARGVALUE55, ARGVALUE56, ARGVALUE57, ARGVALUE58, ARGVALUE59,
+                ARGVALUE60, ARGVALUE61, ARGVALUE62, ARGVALUE63, ARGVALUE64, ARGVALUE65, ARGVALUE66, ARGVALUE67, ARGVALUE68, ARGVALUE69,
+                ARGVALUE70, ARGVALUE71, ARGVALUE72, ARGVALUE73, ARGVALUE74, ARGVALUE75, ARGVALUE76, ARGVALUE77, ARGVALUE78, ARGVALUE79,
+                ARGVALUE80, ARGVALUE81, ARGVALUE82, ARGVALUE83, ARGVALUE84, ARGVALUE85, ARGVALUE86, ARGVALUE87, ARGVALUE88, ARGVALUE89,
+                ARGVALUE90, ARGVALUE91, ARGVALUE92, ARGVALUE93, ARGVALUE94, ARGVALUE95, ARGVALUE96, ARGVALUE97, ARGVALUE98, ARGVALUE99
+     ) UBFM(
+        .SYSCLK(SYSCLK), 
+        .SYSRSTN(SYSRSTN), 
+        .HADDR(iHADDR), 
+        .HCLK(iHCLk), 
+        .PCLK(iPCLk), 
+        .HRESETN(iHRESETN), 
+        .HBURST(iHBURST), 
+        .HMASTLOCK(iHMASTLOCK), 
+        .HPROT(iHPROT), 
+        .HSIZE(iHSIZE), 
+        .HTRANS(iHTRANS), 
+        .HWRITE(iHWRITE), 
+        .HWDATA(iHWDATA), 
+        .HRDATA(iHRDATA), 
+        .HREADY(iHREADY), 
+        .HRESP(iHRESP), 
+        .HSEL(iHSEL), 
+        .INTERRUPT(INTERRUPT), 
+        .GP_OUT(GP_OUT), 
+        .GP_IN(GP_IN), 
+        .EXT_WR(EXT_WR), 
+        .EXT_RD(EXT_RD), 
+        .EXT_ADDR(EXT_ADDR), 
+        .EXT_DATA(EXT_DATA), 
+        .EXT_WAIT(EXT_WAIT), 
+        .CON_ADDR(CON_ADDR), 
+        .CON_DATA(CON_DATA), 
+        .CON_RD(CON_RD), 
+        .CON_WR(CON_WR), 
+        .CON_BUSY(CON_BUSY), 
+        .INSTR_OUT(), 
+        .INSTR_IN(INSTR_IN), 
+        .FINISHED(FINISHED), 
+        .FAILED(FAILED)
+    ); 
+    assign PCLK = iPCLk ;
+    assign PRESETN = iHRESETN ;
+
+    BFM_AHB2APB #(TPD) UBRIDGE(
+        .HCLK(iHCLk), 
+        .HRESETN(iHRESETN), 
+        .HSEL(1\'b1), 
+        .HWRITE(iHWRITE), 
+        .HADDR(iHADDR), 
+        .HWDATA(iHWDATA), 
+        .HRDATA(iHRDATA), 
+        .HREADYIN(iHREADY), 
+        .HREADYOUT(iHREADY), 
+        .HTRANS(iHTRANS), 
+        .HSIZE(iHSIZE), 
+        .HBURST(iHBURST), 
+        .HMASTLOCK(iHMASTLOCK), 
+        .HPROT(iHPROT), 
+        .HRESP(iHRESP), 
+        .PSEL(PSEL), 
+        .PADDR(PADDR), 
+        .PWRITE(PWRITE), 
+        .PENABLE(PENABLE), 
+        .PWDATA(PWDATA), 
+        .PRDATA(PRDATA), 
+        .PREADY(PREADY), 
+        .PSLVERR(PSLVERR)
+    ); 
+endmodule
+"
+"module MSS_XTLOSC( 
+    XTL, 
+    CLKOUT );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""XTL"" */
+
+    output CLKOUT;
+    input  XTL;
+endmodule
+
+module MSS_LPXTLOSC( 
+    LPXIN, 
+    CLKOUT );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""LPXIN"" */
+
+    output CLKOUT;
+    input  LPXIN;
+endmodule
+
+module INBUF_MSS( 
+    PAD, 
+    Y );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""PAD"" */
+
+    input  PAD;
+    output Y;
+
+parameter ACT_PIN    = """";
+parameter ACT_CONFIG = 1\'b0;
+endmodule
+
+module OUTBUF_MSS( 
+    D, 
+    PAD );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""PAD"" */
+
+    input  D;
+    output PAD;
+
+parameter ACT_PIN    = """";
+parameter ACT_CONFIG = 1\'b0;
+endmodule
+
+module TRIBUFF_MSS( 
+    D, 
+    E, 
+    PAD );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""PAD"" */
+
+    input  D;
+    input  E;
+    output PAD;
+
+parameter ACT_PIN    = """";
+parameter ACT_CONFIG = 1\'b0;
+endmodule
+
+module BIBUF_MSS(
+    PAD,
+    D, 
+    E, 
+    Y );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""PAD"" */
+
+    inout  PAD;
+    input  D;
+    input  E;
+    output Y;
+
+parameter ACT_PIN    = """";
+parameter ACT_CONFIG = 1\'b0;
+endmodule
+
+module BIBUF_OPEND_MSS(
+    PAD, 
+    E, 
+    Y );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""PAD"" */
+
+    inout PAD;
+    input E;
+    output Y;
+
+parameter ACT_PIN    = """";
+parameter ACT_CONFIG = 1\'b0;
+endmodule
+
+module INBUF_MCCC( 
+    PAD, 
+    Y );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""PAD"" */
+
+    input  PAD;
+    output Y;
+
+parameter ACT_PIN    = """";
+parameter ACT_CONFIG = 1\'b0;
+endmodule
+
+module INBUF_LVPECL_MCCC( 
+    PADP, 
+    PADN, 
+    Y );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""PADP, PADN"" */
+
+    input  PADP;
+    input  PADN;
+    output Y;
+
+parameter ACT_PIN    = """";
+endmodule
+
+module INBUF_LVDS_MCCC( 
+    PADP, 
+    PADN, 
+    Y );
+
+/* synthesis syn_black_box */
+/* synthesis black_box_pad_pin =""PADP, PADN"" */
+
+    input  PADP;
+    input  PADN;
+    output Y;
+
+parameter ACT_PIN    = """";
+endmodule
+
+module MSSINT(Y,A);
+/* synthesis syn_black_box */
+   input A;
+   output Y;
+endmodule
+
+module MSS_CCC(
+       CLKA,
+       EXTFB,
+       GLA,
+       GLAMSS,
+       LOCK,
+       LOCKMSS,
+       CLKB,
+       GLB,
+       YB,
+       CLKC,
+       GLC,
+       YC,
+       MACCLK,
+       OADIV,
+       OADIVHALF,
+       OAMUX,
+       BYPASSA,
+       DLYGLA,
+       DLYGLAMSS,
+       DLYGLAFAB,
+       OBDIV,
+       OBDIVHALF,
+       OBMUX,
+       BYPASSB,
+       DLYGLB,
+       OCDIV,
+       OCDIVHALF,
+       OCMUX,
+       BYPASSC,
+       DLYGLC,
+       FINDIV,
+       FBDIV,
+       FBDLY,
+       FBSEL,
+       XDLYSEL,
+       GLMUXSEL,
+       GLMUXCFG
+    );
+/* synthesis syn_black_box */
+input  CLKA;
+input  EXTFB;
+output GLA;
+output GLAMSS;
+output LOCK;
+output LOCKMSS;
+input  CLKB;
+output GLB;
+output YB;
+input  CLKC;
+output GLC;
+output YC;
+output MACCLK;
+input  [4:0] OADIV;
+input  OADIVHALF;
+input  [2:0] OAMUX;
+input  BYPASSA;
+input  [4:0] DLYGLA;
+input  [4:0] DLYGLAMSS;
+input  [4:0] DLYGLAFAB;
+input  [4:0] OBDIV;
+input  OBDIVHALF;
+input  [2:0] OBMUX;
+input  BYPASSB;
+input  [4:0] DLYGLB;
+input  [4:0] OCDIV;
+input  OCDIVHALF;
+input  [2:0] OCMUX;
+input  BYPASSC;
+input  [4:0] DLYGLC;
+input  [6:0] FINDIV;
+input  [6:0] FBDIV;
+input  [4:0] FBDLY;
+input  [1:0] FBSEL;
+input  XDLYSEL;
+input  [1:0] GLMUXSEL;
+input  [1:0] GLMUXCFG;
+
+    parameter VCOFREQUENCY = 0.0;
+
+endmodule
+
+module MSS_ALL(
+       HMADDR,
+       HMWDATA,
+       HMTRANS,
+       HMSIZE,
+       HMMASTLOCK,
+       HMAHBWRITE,
+       HMRDATA,
+       HMAHBREADY,
+       HMRESP,
+       FMADDR,
+       FMWDATA,
+       FMTRANS,
+       FMSIZE,
+       FMMASTLOCK,
+       FMAHBWRITE,
+       FMAHBSEL,
+       FMAHBREADY,
+       FMRDATA,
+       FMREADYOUT,
+       FMRESP,
+       HMPSEL,
+       HMPENABLE,
+       HMPWRITE,
+       FMPSLVERR,
+       HMPREADY,
+       HMPSLVERR,
+       FMPSEL,
+       FMPENABLE,
+       FMPWRITE,
+       FMPREADY,
+
+       SYNCCLKFDBK,
+       CALIBOUT,
+       CALIBIN,
+       FABINT,
+       MSSINT,
+       WDINT,
+       F2MRESETn,
+       DMAREADY,
+       RXEV,
+       VRON,
+       M2FRESETn,
+       DEEPSLEEP,
+       SLEEP,
+       TXEV,
+       UART0CTSn,
+       UART0DSRn,
+       UART0RIn,
+       UART0DCDn,
+       UART0RTSn,
+       UART0DTRn,
+       UART1CTSn,
+       UART1DSRn,
+       UART1RIn,
+       UART1DCDn,
+       UART1RTSn,
+       UART1DTRn,
+       I2C0SMBUSNI,
+       I2C0SMBALERTNI,
+       I2C0BCLK,
+       I2C0SMBUSNO,
+       I2C0SMBALERTNO,
+       I2C1SMBUSNI,
+       I2C1SMBALERTNI,
+       I2C1BCLK,
+       I2C1SMBUSNO,
+       I2C1SMBALERTNO,
+       MACM2FTXD,
+       MACF2MRXD,
+       MACM2FTXEN,
+       MACF2MCRSDV,
+       MACF2MRXER,
+       MACF2MMDI,
+       MACM2FMDO,
+       MACM2FMDEN,
+       MACM2FMDC,
+       FABSDD0D,
+       FABSDD1D,
+       FABSDD2D,
+       FABSDD0CLK,
+       FABSDD1CLK,
+       FABSDD2CLK,
+       FABACETRIG,
+       ACEFLAGS,
+       CMP0,
+       CMP1,
+       CMP2,
+       CMP3,
+       CMP4,
+       CMP5,
+       CMP6,
+       CMP7,
+       CMP8,
+       CMP9,
+       CMP10,
+       CMP11,
+       LVTTL0EN,
+       LVTTL1EN,
+       LVTTL2EN,
+       LVTTL3EN,
+       LVTTL4EN,
+       LVTTL5EN,
+       LVTTL6EN,
+       LVTTL7EN,
+       LVTTL8EN,
+       LVTTL9EN,
+       LVTTL10EN,
+       LVTTL11EN,
+       LVTTL0,
+       LVTTL1,
+       LVTTL2,
+       LVTTL3,
+       LVTTL4,
+       LVTTL5,
+       LVTTL6,
+       LVTTL7,
+       LVTTL8,
+       LVTTL9,
+       LVTTL10,
+       LVTTL11,
+       PUFABn,
+       VCC15GOOD,
+       VCC33GOOD,
+       FCLK,
+       MACCLKCCC,
+       RCOSC,
+       MACCLK,
+       PLLLOCK,
+       MSSRESETn,
+       GPI,
+       GPO,
+       GPOE,
+       SPI0DO,
+       SPI0DOE,
+       SPI0DI,
+       SPI0CLKI,
+       SPI0CLKO,
+       SPI0MODE,
+       SPI0SSI,
+       SPI0SSO,
+       UART0TXD,
+       UART0RXD,
+       I2C0SDAI,
+       I2C0SDAO,
+       I2C0SCLI,
+       I2C0SCLO,
+       SPI1DO,
+       SPI1DOE,
+       SPI1DI,
+       SPI1CLKI,
+       SPI1CLKO,
+       SPI1MODE,
+       SPI1SSI,
+       SPI1SSO,
+       UART1TXD,
+       UART1RXD,
+       I2C1SDAI,
+       I2C1SDAO,
+       I2C1SCLI,
+       I2C1SCLO,
+       MACTXD,
+       MACRXD,
+       MACTXEN,
+       MACCRSDV,
+       MACRXER,
+       MACMDI,
+       MACMDO,
+       MACMDEN,
+       MACMDC,
+       EMCCLK,
+       EMCCLKRTN,
+       EMCRDB,
+       EMCAB,
+       EMCWDB,
+       EMCRWn,
+       EMCCS0n,
+       EMCCS1n,
+       EMCOEN0n,
+       EMCOEN1n,
+       EMCBYTEN,
+       EMCDBOE,
+       ADC0,
+       ADC1,
+       ADC2,
+       ADC3,
+       ADC4,
+       ADC5,
+       ADC6,
+       ADC7,
+       ADC8,
+       ADC9,
+       ADC10,
+       ADC11,
+       SDD0,
+       SDD1,
+       SDD2,
+       ABPS0,
+       ABPS1,
+       ABPS2,
+       ABPS3,
+       ABPS4,
+       ABPS5,
+       ABPS6,
+       ABPS7,
+       ABPS8,
+       ABPS9,
+       ABPS10,
+       ABPS11,
+       TM0,
+       TM1,
+       TM2,
+       TM3,
+       TM4,
+       TM5,
+       CM0,
+       CM1,
+       CM2,
+       CM3,
+       CM4,
+       CM5,
+       GNDTM0,
+       GNDTM1,
+       GNDTM2,
+       VAREF0,
+       VAREF1,
+       VAREF2,
+       VAREFOUT,
+       GNDVAREF,
+       PUn
+    );
+/* synthesis syn_black_box */
+output [19:0] HMADDR;
+output [31:0] HMWDATA;
+output        HMTRANS;
+output [1:0]  HMSIZE;
+output        HMMASTLOCK;
+output        HMAHBWRITE;
+input  [31:0] HMRDATA;
+input         HMAHBREADY;
+input         HMRESP;
+input  [31:0] FMADDR;
+input  [31:0] FMWDATA;
+input         FMTRANS;
+input  [1:0]  FMSIZE;
+input         FMMASTLOCK;
+input         FMAHBWRITE;
+input         FMAHBSEL;
+input         FMAHBREADY;
+output [31:0] FMRDATA;
+output        FMREADYOUT;
+output        FMRESP;
+output        HMPSEL;
+output        HMPENABLE;
+output        HMPWRITE;
+output        FMPSLVERR;
+input         HMPREADY;
+input         HMPSLVERR;
+input         FMPSEL;
+input         FMPENABLE;
+input         FMPWRITE;
+output        FMPREADY;
+input  SYNCCLKFDBK;
+output CALIBOUT;
+input  CALIBIN;
+input  FABINT;
+output [7:0] MSSINT;
+output WDINT;
+input  F2MRESETn;
+input  [1:0] DMAREADY;
+input  RXEV;
+input  VRON;
+output M2FRESETn;
+output DEEPSLEEP;
+output SLEEP;
+output TXEV;
+input  UART0CTSn;
+input  UART0DSRn;
+input  UART0RIn;
+input  UART0DCDn;
+output UART0RTSn;
+output UART0DTRn;
+input  UART1CTSn;
+input  UART1DSRn;
+input  UART1RIn;
+input  UART1DCDn;
+output UART1RTSn;
+output UART1DTRn;
+input  I2C0SMBUSNI;
+input  I2C0SMBALERTNI;
+input  I2C0BCLK;
+output I2C0SMBUSNO;
+output I2C0SMBALERTNO;
+input  I2C1SMBUSNI;
+input  I2C1SMBALERTNI;
+input  I2C1BCLK;
+output I2C1SMBUSNO;
+output I2C1SMBALERTNO;
+output [1:0] MACM2FTXD;
+input  [1:0] MACF2MRXD;
+output MACM2FTXEN;
+input  MACF2MCRSDV;
+input  MACF2MRXER;
+input  MACF2MMDI;
+output MACM2FMDO;
+output MACM2FMDEN;
+output MACM2FMDC;
+input  FABSDD0D;
+input  FABSDD1D;
+input  FABSDD2D;
+input  FABSDD0CLK;
+input  FABSDD1CLK;
+input  FABSDD2CLK;
+input  FABACETRIG;
+output [31:0] ACEFLAGS;
+output CMP0;
+output CMP1;
+output CMP2;
+output CMP3;
+output CMP4;
+output CMP5;
+output CMP6;
+output CMP7;
+output CMP8;
+output CMP9;
+output CMP10;
+output CMP11;
+input  LVTTL0EN;
+input  LVTTL1EN;
+input  LVTTL2EN;
+input  LVTTL3EN;
+input  LVTTL4EN;
+input  LVTTL5EN;
+input  LVTTL6EN;
+input  LVTTL7EN;
+input  LVTTL8EN;
+input  LVTTL9EN;
+input  LVTTL10EN;
+input  LVTTL11EN;
+output LVTTL0;
+output LVTTL1;
+output LVTTL2;
+output LVTTL3;
+output LVTTL4;
+output LVTTL5;
+output LVTTL6;
+output LVTTL7;
+output LVTTL8;
+output LVTTL9;
+output LVTTL10;
+output LVTTL11;
+output PUFABn;
+output VCC15GOOD;
+output VCC33GOOD;
+input  FCLK;
+input  MACCLKCCC;
+input  RCOSC;
+input  MACCLK;
+input  PLLLOCK;
+input  MSSRESETn;
+input  [31:0] GPI;
+output [31:0] GPO;
+output [31:0] GPOE;
+output SPI0DO;
+output SPI0DOE;
+input  SPI0DI;
+input  SPI0CLKI;
+output SPI0CLKO;
+output SPI0MODE;
+input  SPI0SSI;
+output [7:0] SPI0SSO;
+output UART0TXD;
+input  UART0RXD;
+input  I2C0SDAI;
+output I2C0SDAO;
+input  I2C0SCLI;
+output I2C0SCLO;
+output SPI1DO;
+output SPI1DOE;
+input  SPI1DI;
+input  SPI1CLKI;
+output SPI1CLKO;
+output SPI1MODE;
+input  SPI1SSI;
+output [7:0] SPI1SSO;
+output UART1TXD;
+input  UART1RXD;
+input  I2C1SDAI;
+output I2C1SDAO;
+input  I2C1SCLI;
+output I2C1SCLO;
+output [1:0] MACTXD;
+input  [1:0] MACRXD;
+output MACTXEN;
+input  MACCRSDV;
+input  MACRXER;
+input  MACMDI;
+output MACMDO;
+output MACMDEN;
+output MACMDC;
+output EMCCLK;
+input  EMCCLKRTN;
+input  [15:0] EMCRDB;
+output [25:0] EMCAB;
+output [15:0] EMCWDB;
+output EMCRWn;
+output EMCCS0n;
+output EMCCS1n;
+output EMCOEN0n;
+output EMCOEN1n;
+output [1:0] EMCBYTEN;
+output EMCDBOE;
+input  ADC0;
+input  ADC1;
+input  ADC2;
+input  ADC3;
+input  ADC4;
+input  ADC5;
+input  ADC6;
+input  ADC7;
+input  ADC8;
+input  ADC9;
+input  ADC10;
+input  ADC11;
+output SDD0;
+output SDD1;
+output SDD2;
+input  ABPS0;
+input  ABPS1;
+input  ABPS2;
+input  ABPS3;
+input  ABPS4;
+input  ABPS5;
+input  ABPS6;
+input  ABPS7;
+input  ABPS8;
+input  ABPS9;
+input  ABPS10;
+input  ABPS11;
+input  TM0;
+input  TM1;
+input  TM2;
+input  TM3;
+input  TM4;
+input  TM5;
+input  CM0;
+input  CM1;
+input  CM2;
+input  CM3;
+input  CM4;
+input  CM5;
+input  GNDTM0;
+input  GNDTM1;
+input  GNDTM2;
+input  VAREF0;
+input  VAREF1;
+input  VAREF2;
+output VAREFOUT;
+input  GNDVAREF;
+input  PUn;
+
+parameter ACT_CONFIG = 1\'b0;
+parameter ACT_FCLK   = 0;
+parameter ACT_DIE    = """";
+parameter ACT_PKG    = """";
+
+endmodule
+"
+"module rgb_led_wrapper(
+\t\t\t\t\tPCLK,
+\t\t\t\t\tPENABLE,
+\t\t\t\t\tPSEL,
+\t\t\t\t\tPRESETN,
+\t\t\t\t\tPWRITE,
+\t\t\t\t\tPREADY,
+\t\t\t\t\tPSLVERR,
+\t\t\t\t\tPADDR,
+\t\t\t\t\tPWDATA,
+\t\t\t\t\tPRDATA,
+\t\t\t\t\tPWM_R, PWM_G, PWM_B,
+\t\t\t\t\tTPS);
+
+// APB Bus Interface
+input PCLK,PENABLE, PSEL, PRESETN, PWRITE;
+input  [31:0] PWDATA;
+input  [7:0] PADDR;
+output [31:0] PRDATA;
+output PREADY, PSLVERR, PWM_R, PWM_G, PWM_B;
+
+
+// Test Interface
+output [4:0] TPS; // Use for your debugging
+ 
+assign BUS_WRITE_EN = (PENABLE && PWRITE && PSEL);
+assign BUS_READ_EN = (!PWRITE && PSEL); //Data is ready during first cycle to make it availble on the bus when PENABLE is asserted
+
+assign PREADY = 1'b1;
+assign PSLVERR = 1'b0;
+
+rgb_led led_0(\t.pclk(PCLK),
+\t\t\t    .nreset(PRESETN), 
+\t\t\t    .bus_write_en(BUS_WRITE_EN),
+\t\t\t    .bus_read_en(BUS_READ_EN),
+\t\t\t    .bus_addr(PADDR),
+\t\t\t    .bus_write_data(PWDATA),
+\t\t\t    .bus_read_data(PRDATA),
+                .pwm_r(PWM_R), .pwm_g(PWM_G), .pwm_b(PWM_B)
+\t\t\t);
+
+endmodule"
+"// Actel Corporation Proprietary and Confidential
+// Copyright 2010 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
+// IN ADVANCE IN WRITING.
+// Revision Information:
+// 05Feb10              Production Release Version 3.0
+// SVN Revision Information:
+// SVN $Revision: 16159 $
+// SVN $Date: 2012-01-13 12:15:19 -0800 (Fri, 13 Jan 2012) $
+`timescale 1ns/1ps
+module
+CAPB3l
+(
+input
+[
+16
+:
+0
+]
+CAPB3OI,
+input
+[
+31
+:
+0
+]
+PRDATAS0,
+input
+[
+31
+:
+0
+]
+PRDATAS1,
+input
+[
+31
+:
+0
+]
+PRDATAS2,
+input
+[
+31
+:
+0
+]
+PRDATAS3,
+input
+[
+31
+:
+0
+]
+PRDATAS4,
+input
+[
+31
+:
+0
+]
+PRDATAS5,
+input
+[
+31
+:
+0
+]
+PRDATAS6,
+input
+[
+31
+:
+0
+]
+PRDATAS7,
+input
+[
+31
+:
+0
+]
+PRDATAS8,
+input
+[
+31
+:
+0
+]
+PRDATAS9,
+input
+[
+31
+:
+0
+]
+PRDATAS10,
+input
+[
+31
+:
+0
+]
+PRDATAS11,
+input
+[
+31
+:
+0
+]
+PRDATAS12,
+input
+[
+31
+:
+0
+]
+PRDATAS13,
+input
+[
+31
+:
+0
+]
+PRDATAS14,
+input
+[
+31
+:
+0
+]
+PRDATAS15,
+input
+[
+31
+:
+0
+]
+PRDATAS16,
+input
+[
+16
+:
+0
+]
+CAPB3II,
+input
+[
+16
+:
+0
+]
+CAPB3lI,
+output
+wire
+PREADY,
+output
+wire
+PSLVERR,
+output
+wire
+[
+31
+:
+0
+]
+PRDATA
+)
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3Ol
+=
+5
+'b
+00000
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3Il
+=
+5
+'b
+00001
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3ll
+=
+5
+'b
+00010
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3O0
+=
+5
+'b
+00011
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3I0
+=
+5
+'b
+00100
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3l0
+=
+5
+'b
+00101
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3O1
+=
+5
+'b
+00110
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3I1
+=
+5
+'b
+00111
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3l1
+=
+5
+'b
+01000
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3OOI
+=
+5
+'b
+01001
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3IOI
+=
+5
+'b
+01010
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3lOI
+=
+5
+'b
+01011
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3OII
+=
+5
+'b
+01100
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3III
+=
+5
+'b
+01101
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3lII
+=
+5
+'b
+01110
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3OlI
+=
+5
+'b
+01111
+;
+localparam
+[
+4
+:
+0
+]
+CAPB3IlI
+=
+5
+'b
+10000
+;
+reg
+CAPB3llI
+;
+reg
+CAPB3O0I
+;
+reg
+[
+31
+:
+0
+]
+CAPB3I0I
+;
+wire
+[
+4
+:
+0
+]
+CAPB3l0I
+;
+wire
+[
+31
+:
+0
+]
+CAPB3O1I
+;
+assign
+CAPB3O1I
+=
+32
+'b
+0
+;
+assign
+CAPB3l0I
+[
+4
+]
+=
+CAPB3OI
+[
+16
+]
+;
+assign
+CAPB3l0I
+[
+3
+]
+=
+CAPB3OI
+[
+15
+]
+|
+CAPB3OI
+[
+14
+]
+|
+CAPB3OI
+[
+13
+]
+|
+CAPB3OI
+[
+12
+]
+|
+CAPB3OI
+[
+11
+]
+|
+CAPB3OI
+[
+10
+]
+|
+CAPB3OI
+[
+9
+]
+|
+CAPB3OI
+[
+8
+]
+;
+assign
+CAPB3l0I
+[
+2
+]
+=
+CAPB3OI
+[
+15
+]
+|
+CAPB3OI
+[
+14
+]
+|
+CAPB3OI
+[
+13
+]
+|
+CAPB3OI
+[
+12
+]
+|
+CAPB3OI
+[
+7
+]
+|
+CAPB3OI
+[
+6
+]
+|
+CAPB3OI
+[
+5
+]
+|
+CAPB3OI
+[
+4
+]
+;
+assign
+CAPB3l0I
+[
+1
+]
+=
+CAPB3OI
+[
+15
+]
+|
+CAPB3OI
+[
+14
+]
+|
+CAPB3OI
+[
+11
+]
+|
+CAPB3OI
+[
+10
+]
+|
+CAPB3OI
+[
+7
+]
+|
+CAPB3OI
+[
+6
+]
+|
+CAPB3OI
+[
+3
+]
+|
+CAPB3OI
+[
+2
+]
+;
+assign
+CAPB3l0I
+[
+0
+]
+=
+CAPB3OI
+[
+15
+]
+|
+CAPB3OI
+[
+13
+]
+|
+CAPB3OI
+[
+11
+]
+|
+CAPB3OI
+[
+9
+]
+|
+CAPB3OI
+[
+7
+]
+|
+CAPB3OI
+[
+5
+]
+|
+CAPB3OI
+[
+3
+]
+|
+CAPB3OI
+[
+1
+]
+;
+always
+@(*)
+begin
+case
+(
+CAPB3l0I
+)
+CAPB3Ol
+:
+if
+(
+CAPB3OI
+[
+0
+]
+)
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS0
+[
+31
+:
+0
+]
+;
+else
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+CAPB3O1I
+[
+31
+:
+0
+]
+;
+CAPB3Il
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS1
+[
+31
+:
+0
+]
+;
+CAPB3ll
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS2
+[
+31
+:
+0
+]
+;
+CAPB3O0
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS3
+[
+31
+:
+0
+]
+;
+CAPB3I0
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS4
+[
+31
+:
+0
+]
+;
+CAPB3l0
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS5
+[
+31
+:
+0
+]
+;
+CAPB3O1
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS6
+[
+31
+:
+0
+]
+;
+CAPB3I1
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS7
+[
+31
+:
+0
+]
+;
+CAPB3l1
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS8
+[
+31
+:
+0
+]
+;
+CAPB3OOI
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS9
+[
+31
+:
+0
+]
+;
+CAPB3IOI
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS10
+[
+31
+:
+0
+]
+;
+CAPB3lOI
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS11
+[
+31
+:
+0
+]
+;
+CAPB3OII
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS12
+[
+31
+:
+0
+]
+;
+CAPB3III
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS13
+[
+31
+:
+0
+]
+;
+CAPB3lII
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS14
+[
+31
+:
+0
+]
+;
+CAPB3OlI
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS15
+[
+31
+:
+0
+]
+;
+CAPB3IlI
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+PRDATAS16
+[
+31
+:
+0
+]
+;
+default
+:
+CAPB3I0I
+[
+31
+:
+0
+]
+=
+CAPB3O1I
+[
+31
+:
+0
+]
+;
+endcase
+end
+always
+@(*)
+begin
+case
+(
+CAPB3l0I
+)
+CAPB3Ol
+:
+if
+(
+CAPB3OI
+[
+0
+]
+)
+CAPB3llI
+=
+CAPB3II
+[
+0
+]
+;
+else
+CAPB3llI
+=
+1
+'b
+1
+;
+CAPB3Il
+:
+CAPB3llI
+=
+CAPB3II
+[
+1
+]
+;
+CAPB3ll
+:
+CAPB3llI
+=
+CAPB3II
+[
+2
+]
+;
+CAPB3O0
+:
+CAPB3llI
+=
+CAPB3II
+[
+3
+]
+;
+CAPB3I0
+:
+CAPB3llI
+=
+CAPB3II
+[
+4
+]
+;
+CAPB3l0
+:
+CAPB3llI
+=
+CAPB3II
+[
+5
+]
+;
+CAPB3O1
+:
+CAPB3llI
+=
+CAPB3II
+[
+6
+]
+;
+CAPB3I1
+:
+CAPB3llI
+=
+CAPB3II
+[
+7
+]
+;
+CAPB3l1
+:
+CAPB3llI
+=
+CAPB3II
+[
+8
+]
+;
+CAPB3OOI
+:
+CAPB3llI
+=
+CAPB3II
+[
+9
+]
+;
+CAPB3IOI
+:
+CAPB3llI
+=
+CAPB3II
+[
+10
+]
+;
+CAPB3lOI
+:
+CAPB3llI
+=
+CAPB3II
+[
+11
+]
+;
+CAPB3OII
+:
+CAPB3llI
+=
+CAPB3II
+[
+12
+]
+;
+CAPB3III
+:
+CAPB3llI
+=
+CAPB3II
+[
+13
+]
+;
+CAPB3lII
+:
+CAPB3llI
+=
+CAPB3II
+[
+14
+]
+;
+CAPB3OlI
+:
+CAPB3llI
+=
+CAPB3II
+[
+15
+]
+;
+CAPB3IlI
+:
+CAPB3llI
+=
+CAPB3II
+[
+16
+]
+;
+default
+:
+CAPB3llI
+=
+1
+'b
+1
+;
+endcase
+end
+always
+@(*)
+begin
+case
+(
+CAPB3l0I
+)
+CAPB3Ol
+:
+if
+(
+CAPB3OI
+[
+0
+]
+)
+CAPB3O0I
+=
+CAPB3lI
+[
+0
+]
+;
+else
+CAPB3O0I
+=
+1
+'b
+0
+;
+CAPB3Il
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+1
+]
+;
+CAPB3ll
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+2
+]
+;
+CAPB3O0
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+3
+]
+;
+CAPB3I0
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+4
+]
+;
+CAPB3l0
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+5
+]
+;
+CAPB3O1
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+6
+]
+;
+CAPB3I1
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+7
+]
+;
+CAPB3l1
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+8
+]
+;
+CAPB3OOI
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+9
+]
+;
+CAPB3IOI
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+10
+]
+;
+CAPB3lOI
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+11
+]
+;
+CAPB3OII
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+12
+]
+;
+CAPB3III
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+13
+]
+;
+CAPB3lII
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+14
+]
+;
+CAPB3OlI
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+15
+]
+;
+CAPB3IlI
+:
+CAPB3O0I
+=
+CAPB3lI
+[
+16
+]
+;
+default
+:
+CAPB3O0I
+=
+1
+'b
+0
+;
+endcase
+end
+assign
+PREADY
+=
+CAPB3llI
+;
+assign
+PSLVERR
+=
+CAPB3O0I
+;
+assign
+PRDATA
+=
+CAPB3I0I
+[
+31
+:
+0
+]
+;
+endmodule
+"
+"// Actel Corporation Proprietary and Confidential
+// Copyright 2008 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+// Revision Information:
+// SVN Revision Information:
+// SVN $Revision: 11864 $
+// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
+`timescale 1ns/100ps
+module
+BFM_MAIN
+(
+SYSCLK
+,
+SYSRSTN
+,
+PCLK
+,
+HCLK
+,
+HRESETN
+,
+HADDR
+,
+HBURST
+,
+HMASTLOCK
+,
+HPROT
+,
+HSIZE
+,
+HTRANS
+,
+HWRITE
+,
+HWDATA
+,
+HRDATA
+,
+HREADY
+,
+HRESP
+,
+HSEL
+,
+INTERRUPT
+,
+GP_OUT
+,
+GP_IN
+,
+EXT_WR
+,
+EXT_RD
+,
+EXT_ADDR
+,
+EXT_DATA
+,
+EXT_WAIT
+,
+CON_ADDR
+,
+CON_DATA
+,
+CON_RD
+,
+CON_WR
+,
+CON_BUSY
+,
+INSTR_OUT
+,
+INSTR_IN
+,
+FINISHED
+,
+FAILED
+)
+;
+parameter
+OPMODE
+=
+0
+;
+parameter
+VECTFILE
+=
+""test.vec""
+;
+parameter
+MAX_INSTRUCTIONS
+=
+16384
+;
+parameter
+MAX_STACK
+=
+1024
+;
+parameter
+MAX_MEMTEST
+=
+65536
+;
+parameter
+TPD
+=
+1
+;
+parameter
+DEBUGLEVEL
+=
+-
+1
+;
+parameter
+CON_SPULSE
+=
+0
+;
+parameter
+ARGVALUE0
+=
+0
+;
+parameter
+ARGVALUE1
+=
+0
+;
+parameter
+ARGVALUE2
+=
+0
+;
+parameter
+ARGVALUE3
+=
+0
+;
+parameter
+ARGVALUE4
+=
+0
+;
+parameter
+ARGVALUE5
+=
+0
+;
+parameter
+ARGVALUE6
+=
+0
+;
+parameter
+ARGVALUE7
+=
+0
+;
+parameter
+ARGVALUE8
+=
+0
+;
+parameter
+ARGVALUE9
+=
+0
+;
+parameter
+ARGVALUE10
+=
+0
+;
+parameter
+ARGVALUE11
+=
+0
+;
+parameter
+ARGVALUE12
+=
+0
+;
+parameter
+ARGVALUE13
+=
+0
+;
+parameter
+ARGVALUE14
+=
+0
+;
+parameter
+ARGVALUE15
+=
+0
+;
+parameter
+ARGVALUE16
+=
+0
+;
+parameter
+ARGVALUE17
+=
+0
+;
+parameter
+ARGVALUE18
+=
+0
+;
+parameter
+ARGVALUE19
+=
+0
+;
+parameter
+ARGVALUE20
+=
+0
+;
+parameter
+ARGVALUE21
+=
+0
+;
+parameter
+ARGVALUE22
+=
+0
+;
+parameter
+ARGVALUE23
+=
+0
+;
+parameter
+ARGVALUE24
+=
+0
+;
+parameter
+ARGVALUE25
+=
+0
+;
+parameter
+ARGVALUE26
+=
+0
+;
+parameter
+ARGVALUE27
+=
+0
+;
+parameter
+ARGVALUE28
+=
+0
+;
+parameter
+ARGVALUE29
+=
+0
+;
+parameter
+ARGVALUE30
+=
+0
+;
+parameter
+ARGVALUE31
+=
+0
+;
+parameter
+ARGVALUE32
+=
+0
+;
+parameter
+ARGVALUE33
+=
+0
+;
+parameter
+ARGVALUE34
+=
+0
+;
+parameter
+ARGVALUE35
+=
+0
+;
+parameter
+ARGVALUE36
+=
+0
+;
+parameter
+ARGVALUE37
+=
+0
+;
+parameter
+ARGVALUE38
+=
+0
+;
+parameter
+ARGVALUE39
+=
+0
+;
+parameter
+ARGVALUE40
+=
+0
+;
+parameter
+ARGVALUE41
+=
+0
+;
+parameter
+ARGVALUE42
+=
+0
+;
+parameter
+ARGVALUE43
+=
+0
+;
+parameter
+ARGVALUE44
+=
+0
+;
+parameter
+ARGVALUE45
+=
+0
+;
+parameter
+ARGVALUE46
+=
+0
+;
+parameter
+ARGVALUE47
+=
+0
+;
+parameter
+ARGVALUE48
+=
+0
+;
+parameter
+ARGVALUE49
+=
+0
+;
+parameter
+ARGVALUE50
+=
+0
+;
+parameter
+ARGVALUE51
+=
+0
+;
+parameter
+ARGVALUE52
+=
+0
+;
+parameter
+ARGVALUE53
+=
+0
+;
+parameter
+ARGVALUE54
+=
+0
+;
+parameter
+ARGVALUE55
+=
+0
+;
+parameter
+ARGVALUE56
+=
+0
+;
+parameter
+ARGVALUE57
+=
+0
+;
+parameter
+ARGVALUE58
+=
+0
+;
+parameter
+ARGVALUE59
+=
+0
+;
+parameter
+ARGVALUE60
+=
+0
+;
+parameter
+ARGVALUE61
+=
+0
+;
+parameter
+ARGVALUE62
+=
+0
+;
+parameter
+ARGVALUE63
+=
+0
+;
+parameter
+ARGVALUE64
+=
+0
+;
+parameter
+ARGVALUE65
+=
+0
+;
+parameter
+ARGVALUE66
+=
+0
+;
+parameter
+ARGVALUE67
+=
+0
+;
+parameter
+ARGVALUE68
+=
+0
+;
+parameter
+ARGVALUE69
+=
+0
+;
+parameter
+ARGVALUE70
+=
+0
+;
+parameter
+ARGVALUE71
+=
+0
+;
+parameter
+ARGVALUE72
+=
+0
+;
+parameter
+ARGVALUE73
+=
+0
+;
+parameter
+ARGVALUE74
+=
+0
+;
+parameter
+ARGVALUE75
+=
+0
+;
+parameter
+ARGVALUE76
+=
+0
+;
+parameter
+ARGVALUE77
+=
+0
+;
+parameter
+ARGVALUE78
+=
+0
+;
+parameter
+ARGVALUE79
+=
+0
+;
+parameter
+ARGVALUE80
+=
+0
+;
+parameter
+ARGVALUE81
+=
+0
+;
+parameter
+ARGVALUE82
+=
+0
+;
+parameter
+ARGVALUE83
+=
+0
+;
+parameter
+ARGVALUE84
+=
+0
+;
+parameter
+ARGVALUE85
+=
+0
+;
+parameter
+ARGVALUE86
+=
+0
+;
+parameter
+ARGVALUE87
+=
+0
+;
+parameter
+ARGVALUE88
+=
+0
+;
+parameter
+ARGVALUE89
+=
+0
+;
+parameter
+ARGVALUE90
+=
+0
+;
+parameter
+ARGVALUE91
+=
+0
+;
+parameter
+ARGVALUE92
+=
+0
+;
+parameter
+ARGVALUE93
+=
+0
+;
+parameter
+ARGVALUE94
+=
+0
+;
+parameter
+ARGVALUE95
+=
+0
+;
+parameter
+ARGVALUE96
+=
+0
+;
+parameter
+ARGVALUE97
+=
+0
+;
+parameter
+ARGVALUE98
+=
+0
+;
+parameter
+ARGVALUE99
+=
+0
+;
+localparam
+[
+1
+:
+(
+3
+)
+*
+8
+]
+BFMA1O
+=
+""2.1""
+;
+localparam
+[
+1
+:
+(
+7
+)
+*
+8
+]
+BFMA1I
+=
+""22Dec08""
+;
+input
+SYSCLK
+;
+input
+SYSRSTN
+;
+output
+PCLK
+;
+wire
+PCLK
+;
+output
+HCLK
+;
+wire
+HCLK
+;
+output
+HRESETN
+;
+wire
+#
+TPD
+HRESETN
+;
+output
+[
+31
+:
+0
+]
+HADDR
+;
+wire
+[
+31
+:
+0
+]
+#
+TPD
+HADDR
+;
+output
+[
+2
+:
+0
+]
+HBURST
+;
+wire
+[
+2
+:
+0
+]
+#
+TPD
+HBURST
+;
+output
+HMASTLOCK
+;
+wire
+#
+TPD
+HMASTLOCK
+;
+output
+[
+3
+:
+0
+]
+HPROT
+;
+wire
+[
+3
+:
+0
+]
+#
+TPD
+HPROT
+;
+output
+[
+2
+:
+0
+]
+HSIZE
+;
+wire
+[
+2
+:
+0
+]
+#
+TPD
+HSIZE
+;
+output
+[
+1
+:
+0
+]
+HTRANS
+;
+wire
+[
+1
+:
+0
+]
+#
+TPD
+HTRANS
+;
+output
+HWRITE
+;
+wire
+#
+TPD
+HWRITE
+;
+output
+[
+31
+:
+0
+]
+HWDATA
+;
+wire
+[
+31
+:
+0
+]
+#
+TPD
+HWDATA
+;
+input
+[
+31
+:
+0
+]
+HRDATA
+;
+input
+HREADY
+;
+input
+HRESP
+;
+output
+[
+15
+:
+0
+]
+HSEL
+;
+wire
+[
+15
+:
+0
+]
+#
+TPD
+HSEL
+;
+input
+[
+255
+:
+0
+]
+INTERRUPT
+;
+output
+[
+31
+:
+0
+]
+GP_OUT
+;
+wire
+[
+31
+:
+0
+]
+#
+TPD
+GP_OUT
+;
+input
+[
+31
+:
+0
+]
+GP_IN
+;
+output
+EXT_WR
+;
+wire
+#
+TPD
+EXT_WR
+;
+output
+EXT_RD
+;
+wire
+#
+TPD
+EXT_RD
+;
+output
+[
+31
+:
+0
+]
+EXT_ADDR
+;
+wire
+[
+31
+:
+0
+]
+#
+TPD
+EXT_ADDR
+;
+inout
+[
+31
+:
+0
+]
+EXT_DATA
+;
+wire
+[
+31
+:
+0
+]
+#
+TPD
+EXT_DATA
+;
+input
+EXT_WAIT
+;
+input
+[
+15
+:
+0
+]
+CON_ADDR
+;
+inout
+[
+31
+:
+0
+]
+CON_DATA
+;
+wire
+[
+31
+:
+0
+]
+#
+TPD
+CON_DATA
+;
+wire
+[
+31
+:
+0
+]
+BFMA1l
+;
+input
+CON_RD
+;
+input
+CON_WR
+;
+output
+CON_BUSY
+;
+reg
+CON_BUSY
+;
+output
+[
+31
+:
+0
+]
+INSTR_OUT
+;
+reg
+[
+31
+:
+0
+]
+INSTR_OUT
+;
+input
+[
+31
+:
+0
+]
+INSTR_IN
+;
+output
+FINISHED
+;
+wire
+#
+TPD
+FINISHED
+;
+output
+FAILED
+;
+wire
+#
+TPD
+FAILED
+;
+localparam
+BFMA1OI
+=
+0
+;
+wire
+BFMA1II
+;
+integer
+BFMA1lI
+[
+0
+:
+255
+]
+;
+integer
+BFMA1Ol
+[
+0
+:
+MAX_INSTRUCTIONS
+-
+1
+]
+;
+reg
+BFMA1Il
+;
+reg
+[
+2
+:
+0
+]
+BFMA1ll
+;
+reg
+BFMA1O0
+;
+reg
+[
+3
+:
+0
+]
+BFMA1I0
+;
+reg
+[
+1
+:
+0
+]
+BFMA1l0
+;
+reg
+BFMA1O1
+;
+wire
+[
+31
+:
+0
+]
+BFMA1I1
+;
+reg
+[
+31
+:
+0
+]
+BFMA1l1
+;
+reg
+[
+31
+:
+0
+]
+BFMA1OOI
+;
+reg
+[
+2
+:
+0
+]
+BFMA1IOI
+;
+reg
+[
+2
+:
+0
+]
+BFMA1lOI
+;
+reg
+[
+15
+:
+0
+]
+BFMA1OII
+;
+reg
+BFMA1III
+;
+reg
+BFMA1lII
+;
+reg
+BFMA1OlI
+;
+reg
+BFMA1IlI
+;
+reg
+BFMA1llI
+;
+reg
+BFMA1O0I
+;
+reg
+BFMA1I0I
+;
+reg
+BFMA1l0I
+;
+reg
+[
+31
+:
+0
+]
+BFMA1O1I
+;
+reg
+[
+31
+:
+0
+]
+BFMA1I1I
+;
+reg
+[
+31
+:
+0
+]
+BFMA1l1I
+;
+reg
+[
+31
+:
+0
+]
+BFMA1OOl
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOl
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lOl
+;
+reg
+[
+31
+:
+0
+]
+BFMA1OIl
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IIl
+;
+integer
+BFMA1lIl
+;
+reg
+BFMA1Oll
+;
+reg
+BFMA1Ill
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lll
+;
+reg
+[
+31
+:
+0
+]
+BFMA1O0l
+;
+integer
+BFMA1I0l
+;
+reg
+BFMA1l0l
+;
+reg
+BFMA1O1l
+;
+reg
+BFMA1I1l
+;
+reg
+BFMA1l1l
+;
+reg
+BFMA1OO0
+;
+wire
+[
+31
+:
+0
+]
+BFMA1IO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1OI0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1II0
+;
+wire
+[
+31
+:
+0
+]
+BFMA1lI0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ol0
+;
+reg
+BFMA1Il0
+;
+reg
+BFMA1ll0
+;
+integer
+BFMA1O00
+;
+integer
+BFMA1I00
+;
+reg
+BFMA1l00
+=
+1
+\'b
+0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1O10
+;
+reg
+[
+1
+:
+(
+80
+)
+*
+8
+]
+BFMA1I10
+;
+reg
+BFMA1l10
+;
+reg
+BFMA1OO1
+;
+reg
+BFMA1IO1
+;
+reg
+BFMA1lO1
+;
+reg
+BFMA1OI1
+;
+reg
+BFMA1II1
+;
+parameter
+[
+31
+:
+0
+]
+BFMA1lI1
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+parameter
+[
+255
+:
+0
+]
+BFMA1Ol1
+=
+{
+256
+{
+1
+\'b
+0
+}
+}
+;
+parameter
+BFMA1Il1
+=
+TPD
+*
+1
+;
+assign
+BFMA1II
+=
+SYSCLK
+;
+integer
+BFMA1ll1
+[
+0
+:
+MAX_STACK
+-
+1
+]
+;
+integer
+BFMA1O01
+;
+integer
+BFMA1I01
+;
+integer
+BFMA1l01
+;
+integer
+DEBUG
+;
+integer
+BFMA1O11
+;
+// Actel Corporation Proprietary and Confidential
+// Copyright 2008 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+// Revision Information:
+// SVN Revision Information:
+// SVN $Revision: 11864 $
+// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
+localparam
+BFMA1I11
+=
+22
+;
+localparam
+BFMA1l11
+=
+0
+;
+localparam
+BFMA1OOOI
+=
+4
+;
+localparam
+BFMA1IOOI
+=
+8
+;
+localparam
+BFMA1lOOI
+=
+12
+;
+localparam
+BFMA1OIOI
+=
+16
+;
+localparam
+BFMA1IIOI
+=
+20
+;
+localparam
+BFMA1lIOI
+=
+24
+;
+localparam
+BFMA1OlOI
+=
+28
+;
+localparam
+BFMA1IlOI
+=
+32
+;
+localparam
+BFMA1llOI
+=
+36
+;
+localparam
+BFMA1O0OI
+=
+40
+;
+localparam
+BFMA1I0OI
+=
+44
+;
+localparam
+BFMA1l0OI
+=
+48
+;
+localparam
+BFMA1O1OI
+=
+52
+;
+localparam
+BFMA1I1OI
+=
+56
+;
+localparam
+BFMA1l1OI
+=
+60
+;
+localparam
+BFMA1OOII
+=
+64
+;
+localparam
+BFMA1IOII
+=
+68
+;
+localparam
+BFMA1lOII
+=
+72
+;
+localparam
+BFMA1OIII
+=
+76
+;
+localparam
+BFMA1IIII
+=
+80
+;
+localparam
+BFMA1lIII
+=
+100
+;
+localparam
+BFMA1OlII
+=
+101
+;
+localparam
+BFMA1IlII
+=
+102
+;
+localparam
+BFMA1llII
+=
+103
+;
+localparam
+BFMA1O0II
+=
+104
+;
+localparam
+BFMA1I0II
+=
+105
+;
+localparam
+BFMA1l0II
+=
+106
+;
+localparam
+BFMA1O1II
+=
+107
+;
+localparam
+BFMA1I1II
+=
+108
+;
+localparam
+BFMA1l1II
+=
+109
+;
+localparam
+BFMA1OOlI
+=
+110
+;
+localparam
+BFMA1IOlI
+=
+111
+;
+localparam
+BFMA1lOlI
+=
+112
+;
+localparam
+BFMA1OIlI
+=
+113
+;
+localparam
+BFMA1IIlI
+=
+114
+;
+localparam
+BFMA1lIlI
+=
+115
+;
+localparam
+BFMA1OllI
+=
+128
+;
+localparam
+BFMA1IllI
+=
+129
+;
+localparam
+BFMA1lllI
+=
+130
+;
+localparam
+BFMA1O0lI
+=
+131
+;
+localparam
+BFMA1I0lI
+=
+132
+;
+localparam
+BFMA1l0lI
+=
+133
+;
+localparam
+BFMA1O1lI
+=
+134
+;
+localparam
+BFMA1I1lI
+=
+135
+;
+localparam
+BFMA1l1lI
+=
+136
+;
+localparam
+BFMA1OO0I
+=
+137
+;
+localparam
+BFMA1IO0I
+=
+138
+;
+localparam
+BFMA1lO0I
+=
+139
+;
+localparam
+BFMA1OI0I
+=
+140
+;
+localparam
+BFMA1II0I
+=
+141
+;
+localparam
+BFMA1lI0I
+=
+142
+;
+localparam
+BFMA1Ol0I
+=
+150
+;
+localparam
+BFMA1Il0I
+=
+151
+;
+localparam
+BFMA1ll0I
+=
+152
+;
+localparam
+BFMA1O00I
+=
+153
+;
+localparam
+BFMA1I00I
+=
+154
+;
+localparam
+BFMA1l00I
+=
+160
+;
+localparam
+BFMA1O10I
+=
+161
+;
+localparam
+BFMA1I10I
+=
+162
+;
+localparam
+BFMA1l10I
+=
+163
+;
+localparam
+BFMA1OO1I
+=
+164
+;
+localparam
+BFMA1IO1I
+=
+165
+;
+localparam
+BFMA1lO1I
+=
+166
+;
+localparam
+BFMA1OI1I
+=
+167
+;
+localparam
+BFMA1II1I
+=
+168
+;
+localparam
+BFMA1lI1I
+=
+169
+;
+localparam
+BFMA1Ol1I
+=
+170
+;
+localparam
+BFMA1Il1I
+=
+171
+;
+localparam
+BFMA1ll1I
+=
+172
+;
+localparam
+BFMA1O01I
+=
+200
+;
+localparam
+BFMA1I01I
+=
+201
+;
+localparam
+BFMA1l01I
+=
+202
+;
+localparam
+BFMA1O11I
+=
+203
+;
+localparam
+BFMA1I11I
+=
+204
+;
+localparam
+BFMA1l11I
+=
+205
+;
+localparam
+BFMA1OOOl
+=
+206
+;
+localparam
+BFMA1IOOl
+=
+207
+;
+localparam
+BFMA1lOOl
+=
+208
+;
+localparam
+BFMA1OIOl
+=
+209
+;
+localparam
+BFMA1IIOl
+=
+210
+;
+localparam
+BFMA1lIOl
+=
+211
+;
+localparam
+BFMA1OlOl
+=
+212
+;
+localparam
+BFMA1IlOl
+=
+213
+;
+localparam
+BFMA1llOl
+=
+214
+;
+localparam
+BFMA1O0Ol
+=
+215
+;
+localparam
+BFMA1I0Ol
+=
+216
+;
+localparam
+BFMA1l0Ol
+=
+217
+;
+localparam
+BFMA1O1Ol
+=
+218
+;
+localparam
+BFMA1I1Ol
+=
+219
+;
+localparam
+BFMA1l1Ol
+=
+220
+;
+localparam
+BFMA1OOIl
+=
+221
+;
+localparam
+BFMA1IOIl
+=
+222
+;
+localparam
+BFMA1lOIl
+=
+250
+;
+localparam
+BFMA1OIIl
+=
+251
+;
+localparam
+BFMA1IIIl
+=
+252
+;
+localparam
+BFMA1lIIl
+=
+253
+;
+localparam
+BFMA1OlIl
+=
+254
+;
+localparam
+BFMA1IlIl
+=
+255
+;
+localparam
+BFMA1llIl
+=
+1001
+;
+localparam
+BFMA1O0Il
+=
+1002
+;
+localparam
+BFMA1I0Il
+=
+1003
+;
+localparam
+BFMA1l0Il
+=
+1004
+;
+localparam
+BFMA1O1Il
+=
+1005
+;
+localparam
+BFMA1I1Il
+=
+1006
+;
+localparam
+BFMA1l1Il
+=
+1007
+;
+localparam
+BFMA1OOll
+=
+1008
+;
+localparam
+BFMA1IOll
+=
+1009
+;
+localparam
+BFMA1lOll
+=
+1010
+;
+localparam
+BFMA1OIll
+=
+1011
+;
+localparam
+BFMA1IIll
+=
+1012
+;
+localparam
+BFMA1lIll
+=
+1013
+;
+localparam
+BFMA1Olll
+=
+1014
+;
+localparam
+BFMA1Illl
+=
+1015
+;
+localparam
+BFMA1llll
+=
+1016
+;
+localparam
+BFMA1O0ll
+=
+1017
+;
+localparam
+BFMA1I0ll
+=
+1018
+;
+localparam
+BFMA1l0ll
+=
+1019
+;
+localparam
+BFMA1O1ll
+=
+1020
+;
+localparam
+BFMA1I1ll
+=
+1021
+;
+localparam
+BFMA1l1ll
+=
+1022
+;
+localparam
+BFMA1OO0l
+=
+1023
+;
+localparam
+BFMA1IO0l
+=
+0
+;
+localparam
+BFMA1lO0l
+=
+1
+;
+localparam
+BFMA1OI0l
+=
+2
+;
+localparam
+BFMA1II0l
+=
+3
+;
+localparam
+BFMA1lI0l
+=
+4
+;
+localparam
+BFMA1Ol0l
+=
+5
+;
+localparam
+BFMA1Il0l
+=
+6
+;
+localparam
+BFMA1ll0l
+=
+7
+;
+localparam
+BFMA1O00l
+=
+8
+;
+localparam
+BFMA1I00l
+=
+0
+;
+localparam
+BFMA1l00l
+=
+1
+;
+localparam
+BFMA1O10l
+=
+2
+;
+localparam
+BFMA1I10l
+=
+3
+;
+localparam
+BFMA1l10l
+=
+4
+;
+localparam
+BFMA1OO1l
+=
+32
+\'h
+00000000
+;
+localparam
+BFMA1IO1l
+=
+32
+\'h
+00002000
+;
+localparam
+BFMA1lO1l
+=
+32
+\'h
+00004000
+;
+localparam
+BFMA1OI1l
+=
+32
+\'h
+00006000
+;
+localparam
+BFMA1II1l
+=
+32
+\'h
+00008000
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1lI1l
+=
+0
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1Ol1l
+=
+1
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1Il1l
+=
+2
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1ll1l
+=
+3
+;
+function
+integer
+BFMA1O01l
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+BFMA1O01l
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+integer
+to_int_unsigned
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+to_int_unsigned
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+integer
+to_int_signed
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+to_int_signed
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+to_slv32
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+reg
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+begin
+BFMA1I01l
+=
+BFMA1ll1l
+;
+to_slv32
+=
+BFMA1I01l
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1l01l
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+reg
+BFMA1lOO0
+;
+begin
+BFMA1IOO0
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+case
+(
+BFMA1OOO0
+)
+0
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+23
+:
+16
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+31
+:
+24
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+31
+:
+16
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+31
+:
+16
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+010
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+end
+2
+\'b
+01
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=10) ? (WARNING)""
+)
+;
+end
+2
+\'b
+11
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+1
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+end
+2
+\'b
+01
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=10) ? (WARNING)""
+)
+;
+end
+2
+\'b
+11
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+2
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+8
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+default
+:
+begin
+$display
+(
+""Illegal Alignment mode (ERROR)""
+)
+;
+end
+endcase
+BFMA1l01l
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1OIO0
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+begin
+BFMA1IOO0
+=
+BFMA1l01l
+(
+BFMA1O11l
+,
+BFMA1I11l
+,
+BFMA1l11l
+,
+BFMA1OOO0
+)
+;
+BFMA1OIO0
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1IIO0
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+reg
+BFMA1lOO0
+;
+begin
+if
+(
+BFMA1OOO0
+==
+8
+)
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+else
+begin
+BFMA1IOO0
+=
+0
+;
+BFMA1lOO0
+=
+BFMA1I11l
+[
+1
+]
+;
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+2
+\'b
+01
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+8
+]
+;
+2
+\'b
+10
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+23
+:
+16
+]
+;
+2
+\'b
+11
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+31
+:
+24
+]
+;
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+case
+(
+BFMA1lOO0
+)
+1
+\'b
+0
+:
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+1
+\'b
+1
+:
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+31
+:
+16
+]
+;
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+010
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+default
+:
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+endcase
+end
+BFMA1IIO0
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+integer
+BFMA1lIO0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1OlO0
+;
+begin
+BFMA1OlO0
+=
+BFMA1ll1l
+;
+BFMA1lIO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1IlO0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+\'h
+62
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+\'h
+68
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+\'h
+77
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+\'h
+78
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+\'h
+3f
+;
+end
+endcase
+BFMA1IlO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1llO0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+input
+BFMA1O0O0
+;
+integer
+BFMA1O0O0
+;
+integer
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+1
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+2
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+4
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+BFMA1O0O0
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+0
+;
+end
+endcase
+BFMA1llO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1I0O0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+input
+BFMA1l0O0
+;
+integer
+BFMA1l0O0
+;
+reg
+[
+2
+:
+0
+]
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+000
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+001
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+010
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+BFMA1l0O0
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+XXX
+;
+end
+endcase
+BFMA1I0O0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1O1O0
+;
+input
+BFMA1I1O0
+;
+integer
+BFMA1I1O0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+input
+BFMA1l1O0
+;
+integer
+BFMA1l1O0
+;
+input
+BFMA1OOI0
+;
+integer
+BFMA1OOI0
+;
+integer
+BFMA1IOI0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lOI0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1OII0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1III0
+;
+integer
+BFMA1lII0
+;
+reg
+[
+63
+:
+0
+]
+BFMA1OlI0
+;
+localparam
+[
+31
+:
+0
+]
+BFMA1IlI0
+=
+0
+;
+localparam
+[
+31
+:
+0
+]
+BFMA1llI0
+=
+1
+;
+begin
+BFMA1lOI0
+=
+BFMA1ll1l
+;
+BFMA1OII0
+=
+BFMA1l1O0
+;
+BFMA1lII0
+=
+BFMA1l1O0
+;
+BFMA1III0
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+case
+(
+BFMA1I1O0
+)
+BFMA1llIl
+:
+begin
+BFMA1III0
+=
+0
+;
+end
+BFMA1O0Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
++
+BFMA1OII0
+;
+end
+BFMA1I0Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+-
+BFMA1OII0
+;
+end
+BFMA1l0Il
+:
+begin
+BFMA1OlI0
+=
+BFMA1lOI0
+*
+BFMA1OII0
+;
+BFMA1III0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+;
+end
+BFMA1O1Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+/
+BFMA1OII0
+;
+end
+BFMA1OOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+&
+BFMA1OII0
+;
+end
+BFMA1IOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+|
+BFMA1OII0
+;
+end
+BFMA1lOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+^
+BFMA1OII0
+;
+end
+BFMA1OIll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+^
+BFMA1OII0
+;
+end
+BFMA1lIll
+:
+begin
+if
+(
+BFMA1lII0
+==
+0
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+end
+else
+begin
+BFMA1III0
+=
+BFMA1lOI0
+>>
+BFMA1lII0
+;
+end
+end
+BFMA1IIll
+:
+begin
+if
+(
+BFMA1lII0
+==
+0
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+end
+else
+begin
+BFMA1III0
+=
+BFMA1lOI0
+<<
+BFMA1lII0
+;
+end
+end
+BFMA1l1Il
+:
+begin
+BFMA1OlI0
+=
+{
+BFMA1IlI0
+,
+BFMA1llI0
+}
+;
+if
+(
+BFMA1lII0
+>
+0
+)
+begin
+begin
+:
+BFMA1O0I0
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+1
+;
+BFMA1I0I0
+<=
+BFMA1lII0
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OlI0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+*
+BFMA1lOI0
+;
+end
+end
+end
+BFMA1III0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+;
+end
+BFMA1Olll
+:
+begin
+if
+(
+BFMA1lOI0
+==
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1Illl
+:
+begin
+if
+(
+BFMA1lOI0
+!=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1llll
+:
+begin
+if
+(
+BFMA1lOI0
+>
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1O0ll
+:
+begin
+if
+(
+BFMA1lOI0
+<
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1I0ll
+:
+begin
+if
+(
+BFMA1lOI0
+>=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1l0ll
+:
+begin
+if
+(
+BFMA1lOI0
+<=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1I1Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+%
+BFMA1OII0
+;
+end
+BFMA1O1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+1
+\'b
+1
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1I1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+1
+\'b
+0
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1l1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+~
+BFMA1III0
+[
+BFMA1l1O0
+]
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1OO0l
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+0
+;
+BFMA1III0
+[
+0
+]
+=
+BFMA1lOI0
+[
+BFMA1l1O0
+]
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+default
+:
+begin
+$display
+(
+""Illegal Maths Operator (FAILURE)""
+)
+;
+$stop
+;
+end
+endcase
+BFMA1IOI0
+=
+BFMA1III0
+;
+if
+(
+BFMA1OOI0
+>=
+4
+)
+begin
+$display
+(
+""Calculated %d = %d (%d) %d""
+,
+BFMA1IOI0
+,
+BFMA1ll1l
+,
+BFMA1I1O0
+,
+BFMA1l1O0
+)
+;
+end
+BFMA1O1O0
+=
+BFMA1IOI0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1l0I0
+;
+input
+[
+31
+:
+0
+]
+BFMA1ll1l
+;
+reg
+[
+31
+:
+0
+]
+BFMA1O1I0
+;
+begin
+BFMA1O1I0
+=
+BFMA1ll1l
+;
+BFMA1O1I0
+=
+0
+;
+begin
+:
+BFMA1I1I0
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+31
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+if
+(
+(
+BFMA1ll1l
+[
+BFMA1I0I0
+]
+)
+==
+1
+\'b
+1
+)
+begin
+BFMA1O1I0
+[
+BFMA1I0I0
+]
+=
+1
+\'b
+1
+;
+end
+end
+end
+BFMA1l0I0
+=
+BFMA1O1I0
+;
+end
+endfunction
+function
+integer
+BFMA1l1I0
+;
+input
+BFMA1OOl0
+;
+integer
+BFMA1OOl0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IOl0
+;
+integer
+BFMA1lOl0
+;
+begin
+BFMA1lOl0
+=
+BFMA1OOl0
+/
+BFMA1ll1l
+;
+BFMA1IOl0
+=
+BFMA1OOl0
+-
+BFMA1lOl0
+*
+BFMA1ll1l
+;
+BFMA1l1I0
+=
+BFMA1IOl0
+;
+end
+endfunction
+function
+integer
+BFMA1OIl0
+;
+input
+BFMA1OOl0
+;
+integer
+BFMA1OOl0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IOl0
+;
+integer
+BFMA1lOl0
+;
+begin
+BFMA1lOl0
+=
+BFMA1OOl0
+/
+BFMA1ll1l
+;
+BFMA1IOl0
+=
+BFMA1OOl0
+-
+BFMA1lOl0
+*
+BFMA1ll1l
+;
+BFMA1OIl0
+=
+BFMA1lOl0
+;
+end
+endfunction
+function
+integer
+to_boolean
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IIl0
+;
+begin
+BFMA1IIl0
+=
+0
+;
+if
+(
+BFMA1ll1l
+!=
+0
+)
+BFMA1IIl0
+=
+1
+;
+to_boolean
+=
+BFMA1IIl0
+;
+end
+endfunction
+function
+integer
+BFMA1lIl0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lll0
+;
+reg
+BFMA1O0l0
+;
+begin
+BFMA1Ill0
+=
+BFMA1Oll0
+;
+BFMA1O0l0
+=
+1
+\'b
+1
+;
+BFMA1lll0
+[
+0
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+;
+BFMA1lll0
+[
+1
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+0
+]
+;
+BFMA1lll0
+[
+2
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+1
+]
+;
+BFMA1lll0
+[
+3
+]
+=
+BFMA1Ill0
+[
+2
+]
+;
+BFMA1lll0
+[
+4
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+3
+]
+;
+BFMA1lll0
+[
+5
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+4
+]
+;
+BFMA1lll0
+[
+6
+]
+=
+BFMA1Ill0
+[
+5
+]
+;
+BFMA1lll0
+[
+7
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+6
+]
+;
+BFMA1lll0
+[
+8
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+7
+]
+;
+BFMA1lll0
+[
+9
+]
+=
+BFMA1Ill0
+[
+8
+]
+;
+BFMA1lll0
+[
+10
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+9
+]
+;
+BFMA1lll0
+[
+11
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+10
+]
+;
+BFMA1lll0
+[
+12
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+11
+]
+;
+BFMA1lll0
+[
+13
+]
+=
+BFMA1Ill0
+[
+12
+]
+;
+BFMA1lll0
+[
+14
+]
+=
+BFMA1Ill0
+[
+13
+]
+;
+BFMA1lll0
+[
+15
+]
+=
+BFMA1Ill0
+[
+14
+]
+;
+BFMA1lll0
+[
+16
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+15
+]
+;
+BFMA1lll0
+[
+17
+]
+=
+BFMA1Ill0
+[
+16
+]
+;
+BFMA1lll0
+[
+18
+]
+=
+BFMA1Ill0
+[
+17
+]
+;
+BFMA1lll0
+[
+19
+]
+=
+BFMA1Ill0
+[
+18
+]
+;
+BFMA1lll0
+[
+20
+]
+=
+BFMA1Ill0
+[
+19
+]
+;
+BFMA1lll0
+[
+21
+]
+=
+BFMA1Ill0
+[
+20
+]
+;
+BFMA1lll0
+[
+22
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+21
+]
+;
+BFMA1lll0
+[
+23
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+22
+]
+;
+BFMA1lll0
+[
+24
+]
+=
+BFMA1Ill0
+[
+23
+]
+;
+BFMA1lll0
+[
+25
+]
+=
+BFMA1Ill0
+[
+24
+]
+;
+BFMA1lll0
+[
+26
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+25
+]
+;
+BFMA1lll0
+[
+27
+]
+=
+BFMA1Ill0
+[
+26
+]
+;
+BFMA1lll0
+[
+28
+]
+=
+BFMA1Ill0
+[
+27
+]
+;
+BFMA1lll0
+[
+29
+]
+=
+BFMA1Ill0
+[
+28
+]
+;
+BFMA1lll0
+[
+30
+]
+=
+BFMA1Ill0
+[
+29
+]
+;
+BFMA1lll0
+[
+31
+]
+=
+BFMA1Ill0
+[
+30
+]
+;
+BFMA1lIl0
+=
+BFMA1lll0
+;
+end
+endfunction
+function
+integer
+BFMA1I0l0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1l0l0
+;
+integer
+BFMA1I0I0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+begin
+BFMA1Ill0
+=
+BFMA1Oll0
+;
+for
+(
+BFMA1I0I0
+=
+31
+;
+BFMA1I0I0
+>=
+BFMA1O11l
+;
+BFMA1I0I0
+=
+BFMA1I0I0
+-
+1
+)
+BFMA1Ill0
+[
+BFMA1I0I0
+]
+=
+0
+;
+BFMA1l0l0
+=
+BFMA1Ill0
+;
+BFMA1I0l0
+=
+BFMA1l0l0
+;
+end
+endfunction
+function
+integer
+BFMA1O1l0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1l0l0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+integer
+BFMA1I1l0
+;
+integer
+BFMA1I0I0
+;
+begin
+case
+(
+BFMA1O11l
+)
+1
+:
+begin
+BFMA1I1l0
+=
+0
+;
+end
+2
+:
+begin
+BFMA1I1l0
+=
+1
+;
+end
+4
+:
+begin
+BFMA1I1l0
+=
+2
+;
+end
+8
+:
+begin
+BFMA1I1l0
+=
+3
+;
+end
+16
+:
+begin
+BFMA1I1l0
+=
+4
+;
+end
+32
+:
+begin
+BFMA1I1l0
+=
+5
+;
+end
+64
+:
+begin
+BFMA1I1l0
+=
+6
+;
+end
+128
+:
+begin
+BFMA1I1l0
+=
+7
+;
+end
+256
+:
+begin
+BFMA1I1l0
+=
+8
+;
+end
+512
+:
+begin
+BFMA1I1l0
+=
+9
+;
+end
+1024
+:
+begin
+BFMA1I1l0
+=
+10
+;
+end
+2048
+:
+begin
+BFMA1I1l0
+=
+11
+;
+end
+4096
+:
+begin
+BFMA1I1l0
+=
+12
+;
+end
+8192
+:
+begin
+BFMA1I1l0
+=
+13
+;
+end
+16384
+:
+begin
+BFMA1I1l0
+=
+14
+;
+end
+32768
+:
+begin
+BFMA1I1l0
+=
+15
+;
+end
+65536
+:
+begin
+BFMA1I1l0
+=
+16
+;
+end
+131072
+:
+BFMA1I1l0
+=
+17
+;
+262144
+:
+BFMA1I1l0
+=
+18
+;
+524288
+:
+BFMA1I1l0
+=
+19
+;
+1048576
+:
+BFMA1I1l0
+=
+20
+;
+2097152
+:
+BFMA1I1l0
+=
+21
+;
+4194304
+:
+BFMA1I1l0
+=
+22
+;
+8388608
+:
+BFMA1I1l0
+=
+23
+;
+16777216
+:
+BFMA1I1l0
+=
+24
+;
+33554432
+:
+BFMA1I1l0
+=
+25
+;
+67108864
+:
+BFMA1I1l0
+=
+26
+;
+134217728
+:
+BFMA1I1l0
+=
+27
+;
+268435456
+:
+BFMA1I1l0
+=
+28
+;
+536870912
+:
+BFMA1I1l0
+=
+29
+;
+1073741824
+:
+BFMA1I1l0
+=
+30
+;
+default
+:
+begin
+$display
+(
+""Random function error (FAILURE)""
+)
+;
+$finish
+;
+end
+endcase
+BFMA1Ill0
+=
+to_slv32
+(
+BFMA1Oll0
+)
+;
+if
+(
+BFMA1I1l0
+<
+31
+)
+begin
+for
+(
+BFMA1I0I0
+=
+31
+;
+BFMA1I0I0
+>=
+BFMA1I1l0
+;
+BFMA1I0I0
+=
+BFMA1I0I0
+-
+1
+)
+BFMA1Ill0
+[
+BFMA1I0I0
+]
+=
+0
+;
+end
+BFMA1l0l0
+=
+to_int_signed
+(
+BFMA1Ill0
+)
+;
+BFMA1O1l0
+=
+BFMA1l0l0
+;
+end
+endfunction
+function
+bound1k
+;
+input
+BFMA1l1l0
+;
+integer
+BFMA1l1l0
+;
+input
+BFMA1OO00
+;
+integer
+BFMA1OO00
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IO00
+;
+reg
+BFMA1lO00
+;
+begin
+BFMA1IO00
+=
+BFMA1OO00
+;
+BFMA1lO00
+=
+0
+;
+case
+(
+BFMA1l1l0
+)
+0
+:
+begin
+if
+(
+BFMA1IO00
+[
+9
+:
+0
+]
+==
+10
+\'b
+0000000000
+)
+begin
+BFMA1lO00
+=
+1
+;
+end
+end
+1
+:
+begin
+BFMA1lO00
+=
+1
+;
+end
+2
+:
+begin
+end
+default
+:
+begin
+$display
+(
+""Illegal Burst Boundary Set (FAILURE)""
+)
+;
+$finish
+;
+end
+endcase
+bound1k
+=
+BFMA1lO00
+;
+end
+endfunction
+function
+integer
+BFMA1OI00
+;
+input
+BFMA1II00
+;
+integer
+BFMA1II00
+;
+integer
+BFMA1lI00
+;
+integer
+BFMA1Ol00
+;
+integer
+BFMA1Il00
+;
+begin
+BFMA1Ol00
+=
+BFMA1II00
+/
+65536
+;
+BFMA1lI00
+=
+BFMA1II00
+%
+65536
+;
+BFMA1Il00
+=
+2
++
+BFMA1lI00
++
+1
++
+(
+(
+BFMA1Ol00
+-
+1
+)
+/
+4
+)
+;
+BFMA1OI00
+=
+BFMA1Il00
+;
+end
+endfunction
+function
+[
+1
+:
+(
+256
+)
+*
+8
+]
+BFMA1ll00
+;
+input
+BFMA1O000
+;
+integer
+BFMA1O000
+;
+reg
+[
+1
+:
+(
+256
+)
+*
+8
+]
+BFMA1I000
+;
+reg
+[
+1
+:
+(
+256
+)
+*
+8
+]
+BFMA1l000
+;
+integer
+BFMA1I0I0
+;
+integer
+BFMA1O100
+;
+integer
+BFMA1I100
+;
+reg
+[
+31
+:
+0
+]
+BFMA1l100
+;
+integer
+BFMA1lI00
+;
+integer
+BFMA1Ol00
+;
+integer
+BFMA1II00
+;
+integer
+BFMA1OO10
+;
+begin
+BFMA1Ol00
+=
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+/
+65536
+;
+BFMA1lI00
+=
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+%
+65536
+;
+BFMA1II00
+=
+2
++
+BFMA1lI00
++
+1
++
+(
+(
+BFMA1Ol00
+-
+1
+)
+/
+4
+)
+;
+for
+(
+BFMA1O100
+=
+1
+;
+BFMA1O100
+<=
+256
+*
+8
+;
+BFMA1O100
+=
+BFMA1O100
++
+1
+)
+BFMA1I000
+[
+BFMA1O100
+]
+=
+0
+;
+BFMA1I0I0
+=
+BFMA1O000
++
+2
++
+BFMA1lI00
+;
+BFMA1I100
+=
+3
+;
+begin
+:
+BFMA1IO10
+integer
+BFMA1O100
+;
+for
+(
+BFMA1O100
+=
+1
+;
+BFMA1O100
+<=
+BFMA1Ol00
+;
+BFMA1O100
+=
+BFMA1O100
++
+1
+)
+begin
+BFMA1l100
+=
+BFMA1Ol
+[
+BFMA1I0I0
+]
+;
+for
+(
+BFMA1OO10
+=
+1
+;
+BFMA1OO10
+<=
+8
+;
+BFMA1OO10
+=
+BFMA1OO10
++
+1
+)
+BFMA1I000
+[
+(
+BFMA1O100
+-
+1
+)
+*
+8
++
+BFMA1OO10
+]
+=
+BFMA1l100
+[
+BFMA1I100
+*
+8
++
+8
+-
+BFMA1OO10
+]
+;
+if
+(
+BFMA1I100
+==
+0
+)
+begin
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+;
+BFMA1I100
+=
+4
+;
+end
+BFMA1I100
+=
+BFMA1I100
+-
+1
+;
+end
+end
+case
+(
+BFMA1lI00
+)
+0
+:
+begin
+$sformat
+(
+BFMA1l000
+,
+BFMA1I000
+)
+;
+end
+1
+:
+begin
+$sformat
+(
+BFMA1l000
+,
+BFMA1I000
+,
+BFMA1lI
+[
+2
+]
+)
+;
+end
+2
+:
+begin
+$sformat
+(
+BFMA1l000
+,
+BFMA1I000
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+)
+;
+end
+3
+:
+begin
+$sformat
+(
+BFMA1l000
+,
+BFMA1I000
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+4
+]
+)
+;
+end
+4
+:
+begin
+$sformat
+(
+BFMA1l000
+,
+BFMA1I000
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+4
+]
+,
+BFMA1lI
+[
+5
+]
+)
+;
+end
+5
+:
+begin
+$sformat
+(
+BFMA1l000
+,
+BFMA1I000
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+4
+]
+,
+BFMA1lI
+[
+5
+]
+,
+BFMA1lI
+[
+6
+]
+)
+;
+end
+6
+:
+begin
+$sformat
+(
+BFMA1l000
+,
+BFMA1I000
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+4
+]
+,
+BFMA1lI
+[
+5
+]
+,
+BFMA1lI
+[
+6
+]
+,
+BFMA1lI
+[
+7
+]
+)
+;
+end
+7
+:
+begin
+$sformat
+(
+BFMA1l000
+,
+BFMA1I000
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+4
+]
+,
+BFMA1lI
+[
+5
+]
+,
+BFMA1lI
+[
+6
+]
+,
+BFMA1lI
+[
+7
+]
+,
+BFMA1lI
+[
+8
+]
+)
+;
+end
+default
+:
+begin
+$display
+(
+""String Error (FAILURE)""
+)
+;
+end
+endcase
+BFMA1ll00
+=
+BFMA1l000
+;
+end
+endfunction
+integer
+BFMA1lO10
+;
+integer
+BFMA1OI10
+;
+integer
+BFMA1II10
+;
+integer
+BFMA1lI10
+;
+parameter
+[
+2
+:
+0
+]
+BFMA1Ol10
+=
+0
+;
+parameter
+[
+2
+:
+0
+]
+BFMA1Il10
+=
+1
+;
+parameter
+[
+2
+:
+0
+]
+BFMA1ll10
+=
+2
+;
+parameter
+[
+2
+:
+0
+]
+BFMA1O010
+=
+3
+;
+parameter
+[
+2
+:
+0
+]
+BFMA1I010
+=
+4
+;
+parameter
+[
+2
+:
+0
+]
+BFMA1l010
+=
+5
+;
+integer
+BFMA1O110
+;
+integer
+BFMA1I110
+;
+integer
+BFMA1l110
+;
+integer
+BFMA1OOO1
+;
+integer
+BFMA1IOO1
+;
+reg
+[
+2
+:
+0
+]
+BFMA1lOO1
+;
+integer
+BFMA1OIO1
+[
+0
+:
+MAX_MEMTEST
+-
+1
+]
+;
+integer
+BFMA1IIO1
+;
+integer
+BFMA1lIO1
+;
+integer
+BFMA1OlO1
+;
+integer
+BFMA1IlO1
+;
+reg
+BFMA1llO1
+;
+integer
+BFMA1O0O1
+;
+integer
+BFMA1I0O1
+;
+integer
+BFMA1l0O1
+;
+integer
+BFMA1O1O1
+;
+integer
+BFMA1I1O1
+;
+integer
+BFMA1l1O1
+;
+reg
+BFMA1OOI1
+;
+reg
+BFMA1IOI1
+;
+reg
+BFMA1lOI1
+;
+reg
+BFMA1OII1
+;
+integer
+BFMA1III1
+;
+function
+automatic
+integer
+BFMA1lII1
+;
+input
+BFMA1OlI1
+;
+input
+BFMA1IlI1
+;
+integer
+BFMA1IlI1
+;
+integer
+BFMA1llI1
+;
+integer
+BFMA1O0I1
+;
+integer
+BFMA1I0I1
+;
+integer
+BFMA1l0I1
+;
+integer
+BFMA1O1I1
+;
+integer
+BFMA1I1I1
+;
+reg
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1l1I1
+;
+begin
+if
+(
+BFMA1OlI1
+)
+begin
+BFMA1I01l
+=
+BFMA1IlI1
+;
+BFMA1O0I1
+=
+BFMA1I01l
+[
+30
+:
+16
+]
+;
+BFMA1I0I1
+=
+BFMA1I01l
+[
+14
+:
+13
+]
+;
+BFMA1l0I1
+=
+BFMA1I01l
+[
+12
+:
+0
+]
+;
+BFMA1O1I1
+=
+BFMA1I01l
+[
+12
+:
+8
+]
+;
+BFMA1I1I1
+=
+BFMA1I01l
+[
+7
+:
+0
+]
+;
+BFMA1l1I1
+=
+0
+;
+if
+(
+(
+BFMA1I01l
+[
+15
+]
+)
+==
+1
+\'b
+1
+)
+begin
+BFMA1l1I1
+=
+BFMA1lII1
+(
+1
+,
+BFMA1O0I1
+)
+;
+end
+case
+(
+BFMA1I0I1
+)
+3
+:
+begin
+case
+(
+BFMA1O1I1
+)
+BFMA1I00l
+:
+begin
+case
+(
+BFMA1I1I1
+)
+BFMA1lO0l
+:
+begin
+BFMA1llI1
+=
+BFMA1O01
+;
+end
+BFMA1OI0l
+:
+begin
+BFMA1llI1
+=
+(
+$time
+/
+1
+)
+;
+end
+BFMA1II0l
+:
+begin
+BFMA1llI1
+=
+DEBUG
+;
+end
+BFMA1lI0l
+:
+begin
+BFMA1llI1
+=
+BFMA1l01
+;
+end
+BFMA1Ol0l
+:
+begin
+BFMA1llI1
+=
+BFMA1II10
+;
+end
+BFMA1Il0l
+:
+begin
+BFMA1llI1
+=
+BFMA1l1O1
+-
+1
+;
+end
+BFMA1ll0l
+:
+begin
+BFMA1llI1
+=
+BFMA1O1O1
+;
+end
+BFMA1O00l
+:
+begin
+BFMA1llI1
+=
+BFMA1I1O1
+;
+end
+default
+:
+begin
+$display
+(
+""Illegal Parameter P0 (FAILURE)""
+)
+;
+end
+endcase
+end
+BFMA1l00l
+:
+begin
+case
+(
+BFMA1I1I1
+)
+0
+:
+BFMA1llI1
+=
+ARGVALUE0
+;
+1
+:
+BFMA1llI1
+=
+ARGVALUE1
+;
+2
+:
+BFMA1llI1
+=
+ARGVALUE2
+;
+3
+:
+BFMA1llI1
+=
+ARGVALUE3
+;
+4
+:
+BFMA1llI1
+=
+ARGVALUE4
+;
+5
+:
+BFMA1llI1
+=
+ARGVALUE5
+;
+6
+:
+BFMA1llI1
+=
+ARGVALUE6
+;
+7
+:
+BFMA1llI1
+=
+ARGVALUE7
+;
+8
+:
+BFMA1llI1
+=
+ARGVALUE8
+;
+9
+:
+BFMA1llI1
+=
+ARGVALUE9
+;
+10
+:
+BFMA1llI1
+=
+ARGVALUE10
+;
+11
+:
+BFMA1llI1
+=
+ARGVALUE11
+;
+12
+:
+BFMA1llI1
+=
+ARGVALUE12
+;
+13
+:
+BFMA1llI1
+=
+ARGVALUE13
+;
+14
+:
+BFMA1llI1
+=
+ARGVALUE14
+;
+15
+:
+BFMA1llI1
+=
+ARGVALUE15
+;
+16
+:
+BFMA1llI1
+=
+ARGVALUE16
+;
+17
+:
+BFMA1llI1
+=
+ARGVALUE17
+;
+18
+:
+BFMA1llI1
+=
+ARGVALUE18
+;
+19
+:
+BFMA1llI1
+=
+ARGVALUE19
+;
+20
+:
+BFMA1llI1
+=
+ARGVALUE20
+;
+21
+:
+BFMA1llI1
+=
+ARGVALUE21
+;
+22
+:
+BFMA1llI1
+=
+ARGVALUE22
+;
+23
+:
+BFMA1llI1
+=
+ARGVALUE23
+;
+24
+:
+BFMA1llI1
+=
+ARGVALUE24
+;
+25
+:
+BFMA1llI1
+=
+ARGVALUE25
+;
+26
+:
+BFMA1llI1
+=
+ARGVALUE26
+;
+27
+:
+BFMA1llI1
+=
+ARGVALUE27
+;
+28
+:
+BFMA1llI1
+=
+ARGVALUE28
+;
+29
+:
+BFMA1llI1
+=
+ARGVALUE29
+;
+30
+:
+BFMA1llI1
+=
+ARGVALUE30
+;
+31
+:
+BFMA1llI1
+=
+ARGVALUE31
+;
+32
+:
+BFMA1llI1
+=
+ARGVALUE32
+;
+33
+:
+BFMA1llI1
+=
+ARGVALUE33
+;
+34
+:
+BFMA1llI1
+=
+ARGVALUE34
+;
+35
+:
+BFMA1llI1
+=
+ARGVALUE35
+;
+36
+:
+BFMA1llI1
+=
+ARGVALUE36
+;
+37
+:
+BFMA1llI1
+=
+ARGVALUE37
+;
+38
+:
+BFMA1llI1
+=
+ARGVALUE38
+;
+39
+:
+BFMA1llI1
+=
+ARGVALUE39
+;
+40
+:
+BFMA1llI1
+=
+ARGVALUE40
+;
+41
+:
+BFMA1llI1
+=
+ARGVALUE41
+;
+42
+:
+BFMA1llI1
+=
+ARGVALUE42
+;
+43
+:
+BFMA1llI1
+=
+ARGVALUE43
+;
+44
+:
+BFMA1llI1
+=
+ARGVALUE44
+;
+45
+:
+BFMA1llI1
+=
+ARGVALUE45
+;
+46
+:
+BFMA1llI1
+=
+ARGVALUE46
+;
+47
+:
+BFMA1llI1
+=
+ARGVALUE47
+;
+48
+:
+BFMA1llI1
+=
+ARGVALUE48
+;
+49
+:
+BFMA1llI1
+=
+ARGVALUE49
+;
+50
+:
+BFMA1llI1
+=
+ARGVALUE50
+;
+51
+:
+BFMA1llI1
+=
+ARGVALUE51
+;
+52
+:
+BFMA1llI1
+=
+ARGVALUE52
+;
+53
+:
+BFMA1llI1
+=
+ARGVALUE53
+;
+54
+:
+BFMA1llI1
+=
+ARGVALUE54
+;
+55
+:
+BFMA1llI1
+=
+ARGVALUE55
+;
+56
+:
+BFMA1llI1
+=
+ARGVALUE56
+;
+57
+:
+BFMA1llI1
+=
+ARGVALUE57
+;
+58
+:
+BFMA1llI1
+=
+ARGVALUE58
+;
+59
+:
+BFMA1llI1
+=
+ARGVALUE59
+;
+60
+:
+BFMA1llI1
+=
+ARGVALUE60
+;
+61
+:
+BFMA1llI1
+=
+ARGVALUE61
+;
+62
+:
+BFMA1llI1
+=
+ARGVALUE62
+;
+63
+:
+BFMA1llI1
+=
+ARGVALUE63
+;
+64
+:
+BFMA1llI1
+=
+ARGVALUE64
+;
+65
+:
+BFMA1llI1
+=
+ARGVALUE65
+;
+66
+:
+BFMA1llI1
+=
+ARGVALUE66
+;
+67
+:
+BFMA1llI1
+=
+ARGVALUE67
+;
+68
+:
+BFMA1llI1
+=
+ARGVALUE68
+;
+69
+:
+BFMA1llI1
+=
+ARGVALUE69
+;
+70
+:
+BFMA1llI1
+=
+ARGVALUE70
+;
+71
+:
+BFMA1llI1
+=
+ARGVALUE71
+;
+72
+:
+BFMA1llI1
+=
+ARGVALUE72
+;
+73
+:
+BFMA1llI1
+=
+ARGVALUE73
+;
+74
+:
+BFMA1llI1
+=
+ARGVALUE74
+;
+75
+:
+BFMA1llI1
+=
+ARGVALUE75
+;
+76
+:
+BFMA1llI1
+=
+ARGVALUE76
+;
+77
+:
+BFMA1llI1
+=
+ARGVALUE77
+;
+78
+:
+BFMA1llI1
+=
+ARGVALUE78
+;
+79
+:
+BFMA1llI1
+=
+ARGVALUE79
+;
+80
+:
+BFMA1llI1
+=
+ARGVALUE80
+;
+81
+:
+BFMA1llI1
+=
+ARGVALUE81
+;
+82
+:
+BFMA1llI1
+=
+ARGVALUE82
+;
+83
+:
+BFMA1llI1
+=
+ARGVALUE83
+;
+84
+:
+BFMA1llI1
+=
+ARGVALUE84
+;
+85
+:
+BFMA1llI1
+=
+ARGVALUE85
+;
+86
+:
+BFMA1llI1
+=
+ARGVALUE86
+;
+87
+:
+BFMA1llI1
+=
+ARGVALUE87
+;
+88
+:
+BFMA1llI1
+=
+ARGVALUE88
+;
+89
+:
+BFMA1llI1
+=
+ARGVALUE89
+;
+90
+:
+BFMA1llI1
+=
+ARGVALUE90
+;
+91
+:
+BFMA1llI1
+=
+ARGVALUE91
+;
+92
+:
+BFMA1llI1
+=
+ARGVALUE92
+;
+93
+:
+BFMA1llI1
+=
+ARGVALUE93
+;
+94
+:
+BFMA1llI1
+=
+ARGVALUE94
+;
+95
+:
+BFMA1llI1
+=
+ARGVALUE95
+;
+96
+:
+BFMA1llI1
+=
+ARGVALUE96
+;
+97
+:
+BFMA1llI1
+=
+ARGVALUE97
+;
+98
+:
+BFMA1llI1
+=
+ARGVALUE98
+;
+99
+:
+BFMA1llI1
+=
+ARGVALUE99
+;
+default
+:
+begin
+$display
+(
+""Illegal Parameter P1 (FAILURE)""
+)
+;
+end
+endcase
+end
+BFMA1O10l
+:
+begin
+BFMA1lO10
+=
+BFMA1lIl0
+(
+BFMA1lO10
+)
+;
+BFMA1llI1
+=
+BFMA1I0l0
+(
+BFMA1lO10
+,
+BFMA1I1I1
+)
+;
+end
+BFMA1I10l
+:
+begin
+BFMA1OI10
+=
+BFMA1lO10
+;
+BFMA1lO10
+=
+BFMA1lIl0
+(
+BFMA1lO10
+)
+;
+BFMA1llI1
+=
+BFMA1I0l0
+(
+BFMA1lO10
+,
+BFMA1I1I1
+)
+;
+end
+BFMA1l10l
+:
+begin
+BFMA1lO10
+=
+BFMA1OI10
+;
+BFMA1lO10
+=
+BFMA1lIl0
+(
+BFMA1lO10
+)
+;
+BFMA1llI1
+=
+BFMA1I0l0
+(
+BFMA1lO10
+,
+BFMA1I1I1
+)
+;
+end
+default
+:
+begin
+$display
+(
+""Illegal Parameter P2 (FAILURE)""
+)
+;
+end
+endcase
+end
+2
+:
+begin
+BFMA1llI1
+=
+BFMA1ll1
+[
+BFMA1I01
+-
+BFMA1l0I1
++
+BFMA1l1I1
+]
+;
+end
+1
+:
+begin
+BFMA1llI1
+=
+BFMA1ll1
+[
+BFMA1l0I1
++
+BFMA1l1I1
+]
+;
+end
+0
+:
+begin
+BFMA1llI1
+=
+BFMA1l0I1
+;
+end
+default
+:
+begin
+$display
+(
+""Illegal Parameter P3 (FAILURE)""
+)
+;
+end
+endcase
+end
+else
+begin
+BFMA1llI1
+=
+BFMA1IlI1
+;
+end
+BFMA1lII1
+=
+BFMA1llI1
+;
+end
+endfunction
+function
+integer
+BFMA1OOl1
+;
+input
+BFMA1IlI1
+;
+integer
+BFMA1IlI1
+;
+input
+BFMA1I01
+;
+integer
+BFMA1I01
+;
+integer
+BFMA1IOl1
+;
+integer
+BFMA1O0I1
+;
+integer
+BFMA1I0I1
+;
+integer
+BFMA1l0I1
+;
+integer
+BFMA1O1I1
+;
+integer
+BFMA1I1I1
+;
+reg
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1l1I1
+;
+begin
+BFMA1I01l
+=
+BFMA1IlI1
+;
+BFMA1O0I1
+=
+BFMA1I01l
+[
+30
+:
+16
+]
+;
+BFMA1I0I1
+=
+BFMA1I01l
+[
+14
+:
+13
+]
+;
+BFMA1l0I1
+=
+BFMA1I01l
+[
+12
+:
+0
+]
+;
+BFMA1O1I1
+=
+BFMA1I01l
+[
+12
+:
+8
+]
+;
+BFMA1I1I1
+=
+BFMA1I01l
+[
+7
+:
+0
+]
+;
+BFMA1l1I1
+=
+0
+;
+if
+(
+(
+BFMA1I01l
+[
+15
+]
+)
+==
+1
+\'b
+1
+)
+begin
+BFMA1l1I1
+=
+BFMA1lII1
+(
+1
+,
+BFMA1O0I1
+)
+;
+end
+case
+(
+BFMA1I0I1
+)
+3
+:
+begin
+$display
+(
+""$Variables not allowed (FAILURE)""
+)
+;
+end
+2
+:
+begin
+BFMA1IOl1
+=
+BFMA1I01
+-
+BFMA1l0I1
++
+BFMA1l1I1
+;
+end
+1
+:
+begin
+BFMA1IOl1
+=
+BFMA1l0I1
++
+BFMA1l1I1
+;
+end
+0
+:
+begin
+$display
+(
+""Immediate data not allowed (FAILURE)""
+)
+;
+end
+default
+:
+begin
+$display
+(
+""Illegal Parameter P3 (FAILURE)""
+)
+;
+end
+endcase
+BFMA1OOl1
+=
+BFMA1IOl1
+;
+end
+endfunction
+always
+@
+(
+posedge
+BFMA1II
+or
+negedge
+SYSRSTN
+)
+begin
+:
+BFMA1lOl1
+parameter
+[
+0
+:
+0
+]
+BFMA1OIl1
+=
+0
+;
+parameter
+[
+0
+:
+0
+]
+BFMA1IIl1
+=
+1
+;
+integer
+BFMA1lIl1
+;
+reg
+BFMA1Oll1
+;
+integer
+BFMA1Ill1
+[
+0
+:
+4
+]
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lll1
+[
+0
+:
+255
+]
+;
+integer
+BFMA1O0l1
+;
+integer
+BFMA1O000
+;
+integer
+BFMA1I0l1
+;
+integer
+BFMA1l0l1
+;
+integer
+BFMA1O1l1
+;
+reg
+[
+31
+:
+0
+]
+BFMA1I1l1
+;
+reg
+[
+1
+:
+0
+]
+BFMA1l1l1
+;
+integer
+BFMA1OO01
+;
+integer
+BFMA1IO01
+;
+integer
+BFMA1lO01
+;
+integer
+BFMA1OI01
+;
+integer
+BFMA1II01
+;
+reg
+[
+2
+:
+0
+]
+BFMA1lI01
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ol01
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Il01
+;
+reg
+[
+31
+:
+0
+]
+BFMA1ll01
+;
+reg
+BFMA1O001
+;
+reg
+BFMA1I001
+;
+reg
+BFMA1l001
+;
+reg
+BFMA1O101
+;
+reg
+BFMA1I101
+;
+reg
+BFMA1l101
+;
+reg
+BFMA1OO11
+;
+reg
+BFMA1IO11
+;
+reg
+BFMA1lO11
+;
+reg
+BFMA1OI11
+;
+reg
+BFMA1II11
+;
+integer
+BFMA1lI11
+;
+integer
+BFMA1Ol11
+;
+integer
+BFMA1Il11
+;
+integer
+BFMA1Il00
+;
+integer
+BFMA1I0I0
+;
+integer
+BFMA1I100
+;
+integer
+BFMA1IlI1
+;
+integer
+BFMA1llI1
+;
+integer
+BFMA1ll11
+;
+reg
+[
+1
+:
+(
+256
+)
+*
+8
+]
+BFMA1l000
+;
+reg
+[
+1
+:
+(
+256
+)
+*
+8
+]
+BFMA1O011
+;
+reg
+[
+1
+:
+(
+256
+)
+*
+8
+]
+BFMA1I011
+;
+integer
+BFMA1l011
+;
+integer
+BFMA1O111
+;
+integer
+BFMA1I111
+;
+integer
+BFMA1l111
+;
+integer
+BFMA1OOOOI
+[
+0
+:
+8191
+]
+;
+reg
+[
+1
+:
+(
+8
+)
+*
+8
+]
+BFMA1IOOOI
+;
+reg
+BFMA1lOOOI
+;
+reg
+BFMA1OIOOI
+;
+reg
+BFMA1IIOOI
+;
+integer
+BFMA1lIOOI
+;
+integer
+BFMA1OlOOI
+;
+integer
+BFMA1IlOOI
+;
+integer
+BFMA1llOOI
+;
+integer
+BFMA1O0OOI
+;
+integer
+BFMA1I0OOI
+;
+integer
+BFMA1lI00
+;
+integer
+BFMA1l0OOI
+;
+integer
+BFMA1O1OOI
+;
+integer
+BFMA1I1OOI
+;
+integer
+BFMA1l1OOI
+;
+integer
+BFMA1OOIOI
+;
+integer
+BFMA1IOIOI
+;
+integer
+BFMA1lOIOI
+;
+integer
+BFMA1OIIOI
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IIIOI
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lIIOI
+;
+reg
+BFMA1OlIOI
+;
+reg
+BFMA1IlIOI
+;
+reg
+BFMA1llIOI
+;
+reg
+BFMA1O0IOI
+;
+reg
+[
+0
+:
+0
+]
+BFMA1I0IOI
+;
+reg
+[
+1
+:
+(
+10
+)
+*
+8
+]
+BFMA1l0IOI
+;
+reg
+BFMA1O1IOI
+;
+reg
+[
+3
+:
+0
+]
+BFMA1I1IOI
+;
+reg
+[
+2
+:
+0
+]
+BFMA1l1IOI
+;
+integer
+BFMA1OOlOI
+;
+reg
+BFMA1IOlOI
+;
+reg
+[
+1
+:
+(
+256
+)
+*
+8
+]
+BFMA1lOlOI
+[
+0
+:
+100
+]
+;
+integer
+BFMA1OIlOI
+;
+integer
+BFMA1IIlOI
+;
+reg
+[
+1
+:
+0
+]
+BFMA1lIlOI
+;
+reg
+[
+5
+:
+0
+]
+BFMA1OllOI
+;
+reg
+[
+16
+:
+0
+]
+BFMA1IllOI
+;
+reg
+BFMA1lllOI
+;
+integer
+BFMA1O0lOI
+;
+reg
+BFMA1I0lOI
+;
+reg
+BFMA1l0lOI
+;
+reg
+BFMA1O1lOI
+;
+reg
+BFMA1I1lOI
+;
+reg
+BFMA1l1lOI
+;
+integer
+BFMA1OO0OI
+;
+reg
+BFMA1IO0OI
+;
+reg
+BFMA1lO0OI
+;
+reg
+BFMA1OI0OI
+;
+reg
+BFMA1II0OI
+;
+reg
+BFMA1lI0OI
+;
+integer
+BFMA1Ol0OI
+;
+integer
+BFMA1Il0OI
+;
+integer
+BFMA1ll0OI
+;
+integer
+BFMA1O00OI
+;
+reg
+BFMA1I00OI
+;
+reg
+[
+1
+:
+0
+]
+BFMA1l00OI
+;
+reg
+[
+3
+:
+0
+]
+BFMA1O10OI
+;
+reg
+[
+2
+:
+0
+]
+BFMA1I10OI
+;
+reg
+BFMA1l10OI
+;
+reg
+BFMA1OO1OI
+;
+reg
+[
+256
+*
+8
+:
+0
+]
+BFMA1IO1OI
+;
+integer
+BFMA1OlO0
+;
+integer
+BFMA1OO10
+;
+integer
+BFMA1lO1OI
+;
+reg
+BFMA1OI1OI
+;
+integer
+BFMA1OOI1
+;
+integer
+BFMA1II1OI
+[
+0
+:
+15
+]
+;
+integer
+BFMA1lI1OI
+;
+integer
+BFMA1Ol1OI
+[
+0
+:
+255
+]
+;
+reg
+[
+8
+:
+0
+]
+BFMA1Il1OI
+;
+reg
+[
+8
+:
+0
+]
+BFMA1ll1OI
+;
+integer
+BFMA1O01OI
+[
+0
+:
+255
+]
+;
+integer
+BFMA1I01OI
+;
+if
+(
+SYSRSTN
+==
+1
+\'b
+0
+)
+begin
+BFMA1OOIOI
+=
+0
+;
+BFMA1IOIOI
+=
+0
+;
+BFMA1II10
+=
+0
+;
+BFMA1OIlOI
+=
+0
+;
+BFMA1IIlOI
+=
+65536
+;
+BFMA1I0IOI
+=
+BFMA1OIl1
+;
+BFMA1lI10
+=
+0
+;
+BFMA1O1O1
+=
+0
+;
+BFMA1I1O1
+=
+0
+;
+BFMA1l00
+<=
+1
+\'b
+0
+;
+DEBUG
+<=
+DEBUGLEVEL
+;
+BFMA1l1
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1ll
+<=
+{
+3
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1O0
+<=
+1
+\'b
+0
+;
+BFMA1I0
+<=
+{
+4
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1IOI
+<=
+{
+3
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1l0
+<=
+{
+2
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1O1
+<=
+1
+\'b
+0
+;
+BFMA1O10
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+INSTR_OUT
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1lII
+<=
+1
+\'b
+0
+;
+BFMA1OlI
+<=
+1
+\'b
+0
+;
+BFMA1O1I
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1I1I
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1l1I
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1l1l
+<=
+1
+\'b
+0
+;
+BFMA1l0l
+<=
+1
+\'b
+0
+;
+BFMA1O1l
+<=
+1
+\'b
+0
+;
+BFMA1OI0
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1lO0
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1l10
+<=
+1
+\'b
+0
+;
+BFMA1I10
+[
+1
+:
+8
+]
+<=
+{
+""UNKNOWN""
+,
+8
+\'b
+0
+}
+;
+BFMA1IlI
+<=
+1
+\'b
+0
+;
+BFMA1OOl
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1IOl
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1I00
+<=
+0
+;
+BFMA1OOI
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1OO1
+<=
+1
+\'b
+0
+;
+BFMA1Il
+<=
+1
+\'b
+0
+;
+CON_BUSY
+<=
+1
+\'b
+0
+;
+BFMA1I00
+<=
+0
+;
+BFMA1llI
+<=
+1
+\'b
+0
+;
+BFMA1O0I
+<=
+1
+\'b
+0
+;
+BFMA1IO1
+<=
+0
+;
+BFMA1lO1
+<=
+0
+;
+BFMA1OI1
+<=
+0
+;
+BFMA1II1
+<=
+0
+;
+BFMA1Oll1
+=
+0
+;
+BFMA1O000
+=
+0
+;
+BFMA1OI11
+=
+0
+;
+BFMA1l1OOI
+=
+0
+;
+BFMA1O001
+=
+0
+;
+BFMA1OO11
+=
+0
+;
+BFMA1I101
+=
+0
+;
+BFMA1I001
+=
+0
+;
+BFMA1l001
+=
+0
+;
+BFMA1O101
+=
+0
+;
+BFMA1l101
+=
+0
+;
+BFMA1IO11
+=
+0
+;
+BFMA1I01
+=
+0
+;
+BFMA1I1OOI
+=
+0
+;
+BFMA1II01
+=
+512
+;
+BFMA1IOlOI
+=
+0
+;
+BFMA1II10
+=
+0
+;
+BFMA1O0IOI
+=
+0
+;
+BFMA1O1IOI
+=
+1
+\'b
+0
+;
+BFMA1I1IOI
+=
+4
+\'b
+0011
+;
+BFMA1l1IOI
+=
+3
+\'b
+001
+;
+BFMA1lOOOI
+=
+0
+;
+BFMA1lIlOI
+=
+2
+;
+BFMA1OllOI
+=
+4
+;
+BFMA1IllOI
+=
+0
+;
+BFMA1lllOI
+=
+0
+;
+BFMA1I0lOI
+=
+0
+;
+BFMA1l1lOI
+=
+0
+;
+BFMA1O01
+=
+0
+;
+BFMA1l0lOI
+=
+0
+;
+BFMA1OO0OI
+=
+0
+;
+BFMA1lO0OI
+=
+0
+;
+BFMA1OI0OI
+=
+0
+;
+BFMA1II0OI
+=
+0
+;
+BFMA1lI0OI
+=
+0
+;
+BFMA1O11
+=
+BFMA1OI
+;
+BFMA1IO0OI
+=
+0
+;
+BFMA1O00OI
+=
+0
+;
+BFMA1lO10
+=
+1
+;
+BFMA1OI10
+=
+1
+;
+BFMA1O11
+=
+1
+;
+BFMA1lI1OI
+=
+0
+;
+BFMA1Il1OI
+=
+0
+;
+BFMA1ll1OI
+=
+0
+;
+BFMA1I01OI
+=
+0
+;
+BFMA1O0lOI
+=
+0
+;
+end
+else
+begin
+BFMA1Il0
+<=
+CON_RD
+;
+BFMA1ll0
+<=
+CON_WR
+;
+BFMA1l0l
+<=
+1
+\'b
+0
+;
+BFMA1O1l
+<=
+1
+\'b
+0
+;
+BFMA1l1l
+<=
+1
+\'b
+0
+;
+BFMA1OO0
+<=
+1
+\'b
+0
+;
+BFMA1lO11
+=
+0
+;
+if
+(
+~
+BFMA1Oll1
+)
+begin
+$display
+(
+"" ""
+)
+;
+$display
+(
+""###########################################################################""
+)
+;
+$display
+(
+""AMBA BFM Model""
+)
+;
+$display
+(
+""Version %s %s""
+,
+BFMA1O
+,
+BFMA1I
+)
+;
+$display
+(
+"" ""
+)
+;
+$display
+(
+""Opening BFM Script file %0s""
+,
+VECTFILE
+)
+;
+if
+(
+~
+BFMA1Oll1
+&
+OPMODE
+!=
+2
+)
+begin
+$readmemh
+(
+VECTFILE
+,
+BFMA1Ol
+)
+;
+BFMA1ll11
+=
+3000
+;
+BFMA1Oll1
+=
+1
+;
+BFMA1O0l1
+=
+BFMA1Ol
+[
+4
+]
+;
+BFMA1Ol0OI
+=
+BFMA1Ol
+[
+0
+]
+%
+65536
+;
+BFMA1ll0OI
+=
+BFMA1Ol
+[
+0
+]
+/
+65536
+;
+$display
+(
+""Read %0d Vectors - Compiler Version %0d.%0d""
+,
+BFMA1O0l1
+,
+BFMA1ll0OI
+,
+BFMA1Ol0OI
+)
+;
+if
+(
+BFMA1ll0OI
+!=
+BFMA1I11
+)
+begin
+$display
+(
+""Incorrect vectors file format for this BFM %0s  (FAILURE) == ""
+,
+VECTFILE
+)
+;
+$stop
+;
+end
+BFMA1O000
+=
+BFMA1Ol
+[
+1
+]
+;
+BFMA1l0l1
+=
+BFMA1Ol
+[
+2
+]
+;
+BFMA1I01
+=
+BFMA1Ol
+[
+3
+]
+;
+BFMA1ll1
+[
+BFMA1I01
+]
+=
+0
+;
+BFMA1I01
+=
+BFMA1I01
++
+1
+;
+if
+(
+BFMA1O000
+==
+0
+)
+begin
+$display
+(
+""BFM Compiler reported errors (FAILURE)""
+)
+;
+$stop
+;
+end
+$display
+(
+""BFM:Filenames referenced in Vectors""
+)
+;
+BFMA1I1l1
+=
+BFMA1Ol
+[
+BFMA1l0l1
+]
+;
+BFMA1OO01
+=
+BFMA1Ol
+[
+BFMA1l0l1
+]
+%
+256
+;
+while
+(
+BFMA1OO01
+==
+BFMA1ll0I
+)
+begin
+BFMA1OI01
+=
+BFMA1OI00
+(
+BFMA1Ol
+[
+BFMA1l0l1
++
+1
+]
+)
+;
+BFMA1l000
+=
+BFMA1ll00
+(
+BFMA1l0l1
+)
+;
+$display
+(
+""  %0s""
+,
+BFMA1l000
+)
+;
+begin
+:
+BFMA1l01OI
+integer
+BFMA1I0I0
+,
+BFMA1OO10
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<
+256
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+for
+(
+BFMA1OO10
+=
+1
+;
+BFMA1OO10
+<=
+8
+;
+BFMA1OO10
+=
+BFMA1OO10
++
+1
+)
+BFMA1lOlOI
+[
+BFMA1OIlOI
+]
+[
+BFMA1I0I0
+*
+8
++
+BFMA1OO10
+]
+=
+BFMA1l000
+[
+BFMA1I0I0
+*
+8
++
+BFMA1OO10
+]
+;
+end
+BFMA1OIlOI
+=
+BFMA1OIlOI
++
+1
+;
+BFMA1l0l1
+=
+BFMA1l0l1
++
+BFMA1OI01
+;
+BFMA1I1l1
+=
+to_slv32
+(
+BFMA1Ol
+[
+BFMA1l0l1
+]
+)
+;
+BFMA1OO01
+=
+BFMA1Ol
+[
+BFMA1l0l1
+]
+%
+256
+;
+end
+BFMA1IIlOI
+=
+65536
+;
+if
+(
+BFMA1OIlOI
+>
+1
+)
+BFMA1IIlOI
+=
+32768
+;
+if
+(
+BFMA1OIlOI
+>
+2
+)
+BFMA1IIlOI
+=
+16384
+;
+if
+(
+BFMA1OIlOI
+>
+4
+)
+BFMA1IIlOI
+=
+8912
+;
+if
+(
+BFMA1OIlOI
+>
+8
+)
+BFMA1IIlOI
+=
+4096
+;
+if
+(
+BFMA1OIlOI
+>
+16
+)
+BFMA1IIlOI
+=
+2048
+;
+if
+(
+BFMA1OIlOI
+>
+32
+)
+BFMA1IIlOI
+=
+1024
+;
+BFMA1l0lOI
+=
+(
+OPMODE
+==
+0
+)
+;
+end
+end
+if
+(
+OPMODE
+==
+2
+&
+~
+BFMA1Oll1
+)
+begin
+BFMA1IIlOI
+=
+65536
+;
+BFMA1Oll1
+=
+1
+;
+BFMA1l0lOI
+=
+0
+;
+BFMA1I01
+=
+BFMA1Ol
+[
+3
+]
++
+1
+;
+BFMA1ll1
+[
+BFMA1I01
+]
+=
+0
+;
+BFMA1I01
+=
+BFMA1I01
++
+1
+;
+end
+if
+(
+BFMA1lI10
+<=
+1
+)
+begin
+BFMA1Il
+<=
+1
+\'b
+1
+;
+end
+else
+begin
+BFMA1lI10
+=
+BFMA1lI10
+-
+1
+;
+end
+case
+(
+BFMA1I0IOI
+)
+BFMA1OIl1
+:
+begin
+if
+(
+HRESP
+==
+1
+\'b
+1
+&
+HREADY
+==
+1
+\'b
+1
+)
+begin
+$display
+(
+""BFM: HRESP Signaling Protocol Error T2 (ERROR)""
+)
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+end
+if
+(
+HRESP
+==
+1
+\'b
+1
+&
+HREADY
+==
+1
+\'b
+0
+)
+begin
+BFMA1I0IOI
+=
+BFMA1IIl1
+;
+end
+end
+BFMA1IIl1
+:
+begin
+if
+(
+HRESP
+==
+1
+\'b
+0
+|
+HREADY
+==
+1
+\'b
+0
+)
+begin
+$display
+(
+""BFM: HRESP Signaling Protocol Error T3 (ERROR)""
+)
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+end
+if
+(
+HRESP
+==
+1
+\'b
+1
+&
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1I0IOI
+=
+BFMA1OIl1
+;
+end
+case
+(
+BFMA1I1OOI
+)
+0
+:
+begin
+$display
+(
+""BFM: Unexpected HRESP Signaling Occured (ERROR)""
+)
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+end
+1
+:
+begin
+BFMA1O0IOI
+=
+1
+;
+end
+default
+:
+begin
+$display
+(
+""BFM: HRESP mode is not correctly set (ERROR)""
+)
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+end
+endcase
+end
+endcase
+if
+(
+OPMODE
+>
+0
+)
+begin
+if
+(
+(
+CON_WR
+==
+1
+\'b
+1
+)
+&&
+(
+BFMA1ll0
+==
+1
+\'b
+0
+||
+CON_SPULSE
+==
+1
+)
+)
+begin
+BFMA1Il00
+=
+BFMA1O01l
+(
+CON_ADDR
+)
+;
+case
+(
+BFMA1Il00
+)
+0
+:
+begin
+BFMA1l0lOI
+=
+(
+(
+BFMA1lI0
+[
+0
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1O1lOI
+=
+(
+(
+BFMA1lI0
+[
+1
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1lOOOI
+=
+0
+;
+if
+(
+BFMA1l0lOI
+&
+~
+BFMA1O1lOI
+)
+begin
+BFMA1ll1
+[
+BFMA1I01
+]
+=
+0
+;
+BFMA1I01
+=
+BFMA1I01
++
+1
+;
+end
+if
+(
+DEBUG
+>=
+2
+&
+BFMA1l0lOI
+&
+~
+BFMA1O1lOI
+)
+begin
+$display
+(
+""BFM: Starting script at %08x (%0d parameters)""
+,
+BFMA1O000
+,
+BFMA1lI1OI
+)
+;
+end
+if
+(
+DEBUG
+>=
+2
+&
+BFMA1l0lOI
+&
+BFMA1O1lOI
+)
+begin
+$display
+(
+""BFM: Starting instruction at %08x""
+,
+BFMA1O000
+)
+;
+end
+if
+(
+BFMA1l0lOI
+)
+begin
+if
+(
+BFMA1lI1OI
+>
+0
+)
+begin
+begin
+:
+BFMA1O11OI
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1lI1OI
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1ll1
+[
+BFMA1I01
+]
+=
+BFMA1II1OI
+[
+BFMA1I0I0
+]
+;
+BFMA1I01
+=
+BFMA1I01
++
+1
+;
+end
+end
+BFMA1lI1OI
+=
+0
+;
+end
+BFMA1Il1OI
+=
+0
+;
+BFMA1ll1OI
+=
+0
+;
+end
+end
+1
+:
+begin
+BFMA1O000
+=
+BFMA1lI0
+;
+end
+2
+:
+begin
+BFMA1II1OI
+[
+BFMA1lI1OI
+]
+=
+BFMA1lI0
+;
+BFMA1lI1OI
+=
+BFMA1lI1OI
++
+1
+;
+end
+default
+:
+begin
+BFMA1Ol
+[
+BFMA1Il00
+]
+=
+to_int_signed
+(
+BFMA1lI0
+)
+;
+end
+endcase
+end
+if
+(
+(
+CON_RD
+==
+1
+\'b
+1
+)
+&&
+(
+BFMA1Il0
+==
+1
+\'b
+0
+||
+CON_SPULSE
+==
+1
+)
+)
+begin
+BFMA1Il00
+=
+BFMA1O01l
+(
+CON_ADDR
+)
+;
+case
+(
+BFMA1Il00
+)
+0
+:
+begin
+BFMA1Ol0
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1Ol0
+[
+2
+]
+<=
+BFMA1l0lOI
+;
+BFMA1Ol0
+[
+3
+]
+<=
+(
+BFMA1II10
+>
+0
+)
+;
+end
+1
+:
+begin
+BFMA1Ol0
+<=
+BFMA1O000
+;
+end
+2
+:
+begin
+BFMA1Ol0
+<=
+BFMA1O01
+;
+BFMA1lI1OI
+=
+0
+;
+end
+3
+:
+begin
+if
+(
+BFMA1Il1OI
+>
+BFMA1ll1OI
+)
+begin
+BFMA1Ol0
+<=
+BFMA1Ol1OI
+[
+BFMA1ll1OI
+]
+;
+BFMA1ll1OI
+=
+BFMA1ll1OI
++
+1
+;
+end
+else
+begin
+$display
+(
+""BFM: Overread Control return stack""
+)
+;
+BFMA1Ol0
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+end
+end
+default
+:
+begin
+BFMA1Ol0
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+end
+endcase
+end
+end
+BFMA1OOIOI
+=
+BFMA1OOIOI
++
+1
+;
+BFMA1l1O1
+=
+BFMA1l1O1
++
+1
+;
+BFMA1OI1OI
+=
+1
+;
+while
+(
+BFMA1OI1OI
+)
+begin
+BFMA1OI1OI
+=
+0
+;
+if
+(
+~
+BFMA1OI11
+&
+BFMA1l0lOI
+)
+begin
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+7
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+BFMA1lI
+[
+BFMA1I0I0
+]
+=
+0
+;
+BFMA1I1l1
+=
+BFMA1Ol
+[
+BFMA1O000
+]
+;
+BFMA1l1l1
+=
+BFMA1I1l1
+[
+1
+:
+0
+]
+;
+BFMA1OO01
+=
+BFMA1I1l1
+[
+7
+:
+0
+]
+;
+BFMA1lO01
+=
+BFMA1I1l1
+[
+15
+:
+8
+]
+;
+BFMA1l01
+=
+BFMA1I1l1
+[
+31
+:
+16
+]
+;
+BFMA1Il11
+=
+BFMA1II01
+;
+BFMA1IOIOI
+=
+BFMA1IOIOI
++
+1
+;
+BFMA1OI01
+=
+1
+;
+BFMA1OOlOI
+=
+-
+1
+;
+BFMA1OO0OI
+=
+0
+;
+if
+(
+DEBUG
+>=
+5
+)
+$display
+(
+""BFM: Instruction %0d Line Number %0d Command %0d""
+,
+BFMA1O000
+,
+BFMA1l01
+,
+BFMA1OO01
+)
+;
+if
+(
+BFMA1lI0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d BF %4d %4d %3d""
+,
+$time
+,
+BFMA1O000
+,
+BFMA1l01
+,
+BFMA1OO01
+)
+;
+end
+if
+(
+BFMA1OO01
+>=
+100
+)
+begin
+BFMA1IO01
+=
+BFMA1OO01
+;
+end
+else
+begin
+BFMA1IO01
+=
+4
+*
+(
+BFMA1OO01
+/
+4
+)
+;
+end
+if
+(
+BFMA1OO01
+!=
+BFMA1OI1I
+)
+begin
+BFMA1OOIOI
+=
+0
+;
+end
+case
+(
+BFMA1IO01
+)
+BFMA1Ol0I
+,
+BFMA1Il0I
+,
+BFMA1ll0I
+,
+BFMA1OIIl
+:
+BFMA1Il00
+=
+8
+;
+BFMA1IlOI
+,
+BFMA1l0OI
+:
+BFMA1Il00
+=
+4
++
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+;
+BFMA1l0lI
+:
+BFMA1Il00
+=
+3
++
+BFMA1Ol
+[
+BFMA1O000
++
+2
+]
+;
+BFMA1I0lI
+:
+BFMA1Il00
+=
+3
+;
+BFMA1II0I
+:
+BFMA1Il00
+=
+2
++
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+;
+BFMA1I11I
+:
+BFMA1Il00
+=
+3
++
+BFMA1Ol
+[
+BFMA1O000
++
+2
+]
+;
+BFMA1OlIl
+:
+BFMA1Il00
+=
+2
++
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+;
+BFMA1lIlI
+:
+BFMA1Il00
+=
+3
++
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+;
+default
+:
+BFMA1Il00
+=
+8
+;
+endcase
+if
+(
+BFMA1Il00
+>
+0
+)
+begin
+begin
+:
+BFMA1I11OI
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1Il00
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+if
+(
+BFMA1I0I0
+>=
+1
+&
+BFMA1I0I0
+<=
+8
+)
+begin
+BFMA1lI
+[
+BFMA1I0I0
+]
+=
+BFMA1lII1
+(
+(
+(
+BFMA1I1l1
+[
+7
++
+BFMA1I0I0
+]
+)
+==
+1
+\'b
+1
+)
+,
+BFMA1Ol
+[
+BFMA1O000
++
+BFMA1I0I0
+]
+)
+;
+end
+else
+begin
+BFMA1lI
+[
+BFMA1I0I0
+]
+=
+BFMA1Ol
+[
+BFMA1O000
++
+BFMA1I0I0
+]
+;
+end
+BFMA1lll1
+[
+BFMA1I0I0
+]
+=
+to_slv32
+(
+BFMA1lI
+[
+BFMA1I0I0
+]
+)
+;
+end
+end
+end
+case
+(
+BFMA1IO01
+)
+BFMA1IlIl
+:
+begin
+$display
+(
+""BFM Compiler reported a'b'n error (FAILURE)""
+)
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$stop
+;
+end
+BFMA1ll1I
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1OI1OI
+=
+1
+;
+BFMA1Ol1OI
+[
+BFMA1Il1OI
+]
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1Il1OI
+=
+BFMA1Il1OI
++
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:conifpush %0d""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+)
+;
+end
+BFMA1OOOl
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1Il
+<=
+1
+\'b
+0
+;
+BFMA1lI10
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:RESET %0d""
+,
+BFMA1l01
+,
+BFMA1lI10
+)
+;
+end
+BFMA1IOOl
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1l00
+<=
+BFMA1lll1
+[
+1
+]
+[
+0
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:STOPCLK %0d ""
+,
+BFMA1l01
+,
+BFMA1lll1
+[
+1
+]
+[
+0
+]
+)
+;
+end
+BFMA1l00I
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1l1OOI
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:mode %0d (No effect in this version)""
+,
+BFMA1l01
+,
+BFMA1l1OOI
+)
+;
+end
+BFMA1O10I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+4
+;
+BFMA1Il00
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1IlI1
+=
+BFMA1lI
+[
+2
+]
+;
+BFMA1llI1
+=
+BFMA1lI
+[
+3
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:setup %0d %0d %0d ""
+,
+BFMA1l01
+,
+BFMA1Il00
+,
+BFMA1IlI1
+,
+BFMA1llI1
+)
+;
+case
+(
+BFMA1Il00
+)
+1
+:
+begin
+BFMA1OI01
+=
+4
+;
+BFMA1lIlOI
+=
+BFMA1IlI1
+;
+BFMA1OllOI
+=
+BFMA1llI1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:Setup- Memory Cycle Transfer Size %0s %0d""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1lIlOI
+)
+,
+BFMA1OllOI
+)
+;
+end
+2
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1lllOI
+=
+to_boolean
+(
+BFMA1IlI1
+)
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:Setup- Automatic Flush %0d""
+,
+BFMA1l01
+,
+BFMA1lllOI
+)
+;
+end
+3
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1IllOI
+=
+BFMA1IlI1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:Setup- XRATE %0d""
+,
+BFMA1l01
+,
+BFMA1IllOI
+)
+;
+end
+4
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1O0lOI
+=
+BFMA1IlI1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:Setup- Burst Mode %0d""
+,
+BFMA1l01
+,
+BFMA1O0lOI
+)
+;
+end
+5
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1I0lOI
+=
+BFMA1IlI1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:Setup- Alignment %0d""
+,
+BFMA1l01
+,
+BFMA1I0lOI
+)
+;
+if
+(
+BFMA1I0lOI
+==
+1
+|
+BFMA1I0lOI
+==
+2
+)
+begin
+$display
+(
+""BFM: Untested 8 or 16 Bit alignment selected (WARNING)""
+)
+;
+end
+end
+6
+:
+begin
+BFMA1OI01
+=
+3
+;
+end
+7
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1l1lOI
+=
+BFMA1IlI1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:Setup- End Sim Action %0d""
+,
+BFMA1l01
+,
+BFMA1l1lOI
+)
+;
+if
+(
+BFMA1l1lOI
+>
+2
+)
+begin
+$display
+(
+""BFM: Unexpected End Simulation value (WARNING)""
+)
+;
+end
+end
+default
+:
+begin
+$display
+(
+""BFM Unknown Setup Command (FAILURE)""
+)
+;
+end
+endcase
+end
+BFMA1IOIl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1OI1
+<=
+(
+(
+BFMA1lll1
+[
+1
+]
+[
+0
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1II1
+<=
+(
+(
+BFMA1lll1
+[
+1
+]
+[
+1
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1lO1
+<=
+(
+(
+BFMA1lll1
+[
+1
+]
+[
+2
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1IO1
+<=
+(
+(
+BFMA1lll1
+[
+1
+]
+[
+3
+]
+)
+==
+1
+\'b
+1
+)
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:drivex %0d ""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+)
+;
+end
+BFMA1IO1I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+3
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:error %0d %0d (No effect in this version)""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+)
+;
+end
+BFMA1l10I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1I1IOI
+=
+BFMA1lll1
+[
+1
+]
+[
+3
+:
+0
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:prot %0d ""
+,
+BFMA1l01
+,
+BFMA1I1IOI
+)
+;
+end
+BFMA1OO1I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1O1IOI
+=
+BFMA1lll1
+[
+1
+]
+[
+0
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:lock %0d ""
+,
+BFMA1l01
+,
+BFMA1O1IOI
+)
+;
+end
+BFMA1lO1I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1l1IOI
+=
+BFMA1lll1
+[
+1
+]
+[
+2
+:
+0
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:burst %0d ""
+,
+BFMA1l01
+,
+BFMA1l1IOI
+)
+;
+end
+BFMA1OO0I
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1lI11
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:wait %0d  starting at %0d ns""
+,
+BFMA1l01
+,
+BFMA1lI11
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1OOIl
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1O00OI
+=
+BFMA1lI
+[
+1
+]
+*
+1000
++
+(
+$time
+/
+1
+)
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:waitus %0d  starting at %0d ns""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1l1Ol
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1O00OI
+=
+BFMA1lI
+[
+1
+]
+*
+1
++
+(
+$time
+/
+1
+)
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:waitns %0d  starting at %0d ns""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1OI1I
+:
+begin
+BFMA1OI01
+=
+3
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:checktime %0d %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1lI1I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+1
+;
+BFMA1l1O1
+=
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:starttimer at %0d ns""
+,
+BFMA1l01
+,
+$time
+)
+;
+end
+BFMA1Ol1I
+:
+begin
+BFMA1OI01
+=
+3
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:checktimer %0d %0d at %0d ns ""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1l11
+:
+begin
+BFMA1OI01
+=
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:nop""
+,
+BFMA1l01
+)
+;
+end
+BFMA1OOOI
+:
+begin
+BFMA1OI01
+=
+4
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+3
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:write %c %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+$time
+)
+;
+BFMA1I101
+=
+1
+;
+end
+BFMA1lOII
+:
+begin
+BFMA1OI01
+=
+5
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+3
+]
+;
+BFMA1I00OI
+=
+BFMA1lll1
+[
+4
+]
+[
+0
+]
+;
+BFMA1l00OI
+=
+BFMA1lll1
+[
+4
+]
+[
+5
+:
+4
+]
+;
+BFMA1I10OI
+=
+BFMA1lll1
+[
+4
+]
+[
+10
+:
+8
+]
+;
+BFMA1l10OI
+=
+BFMA1lll1
+[
+4
+]
+[
+12
+]
+;
+BFMA1O10OI
+=
+BFMA1lll1
+[
+4
+]
+[
+19
+:
+16
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:idle %c %08x %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+BFMA1lll1
+[
+4
+]
+,
+$time
+)
+;
+BFMA1IO11
+=
+1
+;
+end
+BFMA1IOOI
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:read %c %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+$time
+)
+;
+BFMA1I001
+=
+1
+;
+end
+BFMA1IOII
+:
+begin
+BFMA1OI01
+=
+4
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1OOlOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1O000
++
+3
+]
+,
+BFMA1I01
+)
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:readstore %c %08x @%0d at %0d ns ""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1OOlOI
+,
+$time
+)
+;
+BFMA1I001
+=
+1
+;
+BFMA1OO11
+=
+1
+;
+end
+BFMA1lOOI
+:
+begin
+BFMA1OI01
+=
+4
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+3
+]
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:readcheck %c %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+$time
+)
+;
+BFMA1I001
+=
+1
+;
+end
+BFMA1OIOI
+:
+begin
+BFMA1OI01
+=
+5
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+3
+]
+;
+BFMA1ll01
+=
+BFMA1lll1
+[
+4
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:readmask %c %08x %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+BFMA1ll01
+,
+$time
+)
+;
+BFMA1I001
+=
+1
+;
+end
+BFMA1IIOI
+:
+begin
+BFMA1OI01
+=
+4
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+3
+]
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:poll %c %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+$time
+)
+;
+BFMA1OI11
+=
+1
+;
+BFMA1l101
+=
+1
+;
+BFMA1l101
+=
+1
+;
+end
+BFMA1lIOI
+:
+begin
+BFMA1OI01
+=
+5
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+3
+]
+;
+BFMA1ll01
+=
+BFMA1lll1
+[
+4
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:pollmask %c %08x %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+BFMA1ll01
+,
+$time
+)
+;
+BFMA1l101
+=
+1
+;
+end
+BFMA1OlOI
+:
+begin
+BFMA1OI01
+=
+5
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1Il01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1Ol11
+=
+BFMA1lI
+[
+3
+]
+;
+BFMA1ll01
+[
+BFMA1Ol11
+]
+=
+1
+\'b
+1
+;
+BFMA1Il01
+[
+BFMA1Ol11
+]
+=
+BFMA1lll1
+[
+4
+]
+[
+0
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:pollbit %c %08x %0d %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1Ol11
+,
+BFMA1Il01
+[
+BFMA1Ol11
+]
+,
+$time
+)
+;
+BFMA1l101
+=
+1
+;
+end
+BFMA1IlOI
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1OI01
+=
+4
++
+BFMA1O111
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+2
+]
++
+BFMA1lI
+[
+3
+]
+)
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+begin
+:
+BFMA1l11OI
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1O111
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1lI
+[
+BFMA1I0I0
++
+4
+]
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:writemultiple %c %08x %08x ... at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1OOOOI
+[
+0
+]
+,
+$time
+)
+;
+BFMA1l001
+=
+1
+;
+end
+BFMA1llOI
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+3
+]
+;
+BFMA1OI01
+=
+6
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+BFMA1l0OOI
+=
+BFMA1lI
+[
+4
+]
+;
+BFMA1O1OOI
+=
+BFMA1lI
+[
+5
+]
+;
+begin
+:
+BFMA1OOOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1O111
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1l0OOI
+;
+BFMA1l0OOI
+=
+BFMA1l0OOI
++
+BFMA1O1OOI
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:fill %c %08x %0d %0d %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1O111
+,
+BFMA1lI
+[
+4
+]
+,
+BFMA1lI
+[
+4
+]
+,
+$time
+)
+;
+BFMA1l001
+=
+1
+;
+end
+BFMA1O0OI
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+4
+]
+;
+BFMA1OI01
+=
+5
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+BFMA1lIOOI
+=
+BFMA1lI
+[
+3
+]
+;
+begin
+:
+BFMA1IOOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1O111
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1Ol
+[
+2
++
+BFMA1lIOOI
++
+BFMA1I0I0
+]
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:writetable %c %08x %0d %0d at %0d ns ""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1lIOOI
+,
+BFMA1O111
+,
+$time
+)
+;
+BFMA1l001
+=
+1
+;
+end
+BFMA1OIII
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+4
+]
+;
+BFMA1OI01
+=
+5
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+BFMA1lOIOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1O000
++
+3
+]
+,
+BFMA1I01
+)
+;
+begin
+:
+BFMA1lOOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1O111
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1ll1
+[
+BFMA1lOIOI
++
+BFMA1I0I0
+]
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:writearray %c %08x %0d %0d at %0d ns ""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1lOIOI
+,
+BFMA1O111
+,
+$time
+)
+;
+BFMA1l001
+=
+1
+;
+end
+BFMA1I0OI
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+3
+]
+;
+BFMA1OI01
+=
+4
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:readmult %c %08x %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1O111
+,
+$time
+)
+;
+BFMA1O101
+=
+1
+;
+end
+BFMA1l0OI
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1OI01
+=
+4
++
+BFMA1O111
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+2
+]
++
+BFMA1lI
+[
+3
+]
+)
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+begin
+:
+BFMA1OIOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1O111
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1lI
+[
+BFMA1I0I0
++
+4
+]
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:readmultchk %c %08x %08x ... at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1OOOOI
+[
+0
+]
+,
+$time
+)
+;
+BFMA1O101
+=
+1
+;
+end
+BFMA1O1OI
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+3
+]
+;
+BFMA1OI01
+=
+6
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+BFMA1l0OOI
+=
+BFMA1lI
+[
+4
+]
+;
+BFMA1O1OOI
+=
+BFMA1lI
+[
+5
+]
+;
+begin
+:
+BFMA1IIOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1O111
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1l0OOI
+;
+BFMA1l0OOI
+=
+BFMA1l0OOI
++
+BFMA1O1OOI
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:fillcheck %c %08x %0d %0d %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1O111
+,
+BFMA1lI
+[
+4
+]
+,
+BFMA1lI
+[
+5
+]
+,
+$time
+)
+;
+BFMA1O101
+=
+1
+;
+end
+BFMA1I1OI
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+4
+]
+;
+BFMA1OI01
+=
+5
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+BFMA1lIOOI
+=
+BFMA1lI
+[
+3
+]
+;
+begin
+:
+BFMA1lIOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1O111
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1Ol
+[
+BFMA1lIOOI
++
+2
++
+BFMA1I0I0
+]
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:readtable %c %08x %0d %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1lIOOI
+,
+BFMA1O111
+,
+$time
+)
+;
+BFMA1O101
+=
+1
+;
+end
+BFMA1IIII
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+4
+]
+;
+BFMA1OI01
+=
+5
+;
+BFMA1lI01
+=
+BFMA1I0O0
+(
+BFMA1l1l1
+,
+BFMA1lIlOI
+)
+;
+BFMA1Ol01
+=
+to_slv32
+(
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+)
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+BFMA1I111
+=
+0
+;
+BFMA1l111
+=
+BFMA1llO0
+(
+BFMA1l1l1
+,
+BFMA1OllOI
+)
+;
+BFMA1lOIOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1O000
++
+3
+]
+,
+BFMA1I01
+)
+;
+begin
+:
+BFMA1OlOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1O111
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1ll1
+[
+BFMA1lOIOI
++
+BFMA1I0I0
+]
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:readtable %c %08x %0d %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlO0
+(
+BFMA1l1l1
+)
+,
+BFMA1Ol01
+,
+BFMA1lOIOI
+,
+BFMA1O111
+,
+$time
+)
+;
+BFMA1O101
+=
+1
+;
+end
+BFMA1O00I
+:
+begin
+BFMA1OI01
+=
+7
+;
+BFMA1O001
+=
+1
+;
+BFMA1lOO1
+=
+BFMA1Il10
+;
+end
+BFMA1I00I
+:
+begin
+BFMA1OI01
+=
+7
+;
+BFMA1O001
+=
+1
+;
+BFMA1lOO1
+=
+BFMA1Il10
+;
+end
+BFMA1O1II
+:
+begin
+BFMA1OI01
+=
+1
+;
+BFMA1IlOOI
+=
+0
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:waitfiq at %0d ns ""
+,
+BFMA1l01
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1I1II
+:
+begin
+BFMA1OI01
+=
+1
+;
+BFMA1IlOOI
+=
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:waitirq at %0d ns ""
+,
+BFMA1l01
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1l0II
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1IlOOI
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:waitint %0d  at %0d ns""
+,
+BFMA1l01
+,
+BFMA1IlOOI
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1lIII
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+1
+]
+;
+BFMA1O10
+<=
+BFMA1Il01
+;
+BFMA1OO0
+<=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:iowrite %08x  at %0d ns ""
+,
+BFMA1l01
+,
+BFMA1Il01
+,
+$time
+)
+;
+end
+BFMA1OlII
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1Il01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1OOlOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+,
+BFMA1I01
+)
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:ioread @%0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1OOlOI
+,
+$time
+)
+;
+BFMA1l1l
+<=
+1
+\'b
+1
+;
+BFMA1O001
+=
+1
+;
+BFMA1OO11
+=
+1
+;
+BFMA1lO11
+=
+1
+;
+end
+BFMA1IlII
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+1
+]
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+BFMA1l1l
+<=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:iocheck %08x  at %0d ns ""
+,
+BFMA1l01
+,
+BFMA1Il01
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1llII
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+1
+]
+;
+BFMA1ll01
+=
+BFMA1lll1
+[
+2
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:iomask %08x %08x  at %0d ns""
+,
+BFMA1l01
+,
+BFMA1Il01
+,
+BFMA1ll01
+,
+$time
+)
+;
+BFMA1l1l
+<=
+1
+\'b
+1
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1l1OI
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1Il01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1Ol11
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1Il01
+[
+BFMA1Ol11
+]
+=
+BFMA1I1l1
+[
+0
+]
+;
+BFMA1ll01
+[
+BFMA1Ol11
+]
+=
+1
+\'b
+1
+;
+BFMA1l1l
+<=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:iotest %0d %0d  at %0d ns""
+,
+BFMA1l01
+,
+BFMA1Ol11
+,
+BFMA1I1l1
+[
+0
+]
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1O0II
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1Ol11
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1O10
+[
+BFMA1Ol11
+]
+<=
+1
+\'b
+1
+;
+BFMA1OO0
+<=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:ioset %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1Ol11
+,
+$time
+)
+;
+end
+BFMA1I0II
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1Ol11
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1O10
+[
+BFMA1Ol11
+]
+<=
+1
+\'b
+0
+;
+BFMA1OO0
+<=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:ioclr %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1Ol11
+,
+$time
+)
+;
+end
+BFMA1OOII
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1Il01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1Ol11
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1Il01
+[
+BFMA1Ol11
+]
+=
+BFMA1I1l1
+[
+0
+]
+;
+BFMA1ll01
+[
+BFMA1Ol11
+]
+=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:iowait %0d %0d at %0d ns ""
+,
+BFMA1l01
+,
+BFMA1Ol11
+,
+BFMA1I1l1
+[
+0
+]
+,
+$time
+)
+;
+BFMA1l1l
+<=
+1
+\'b
+1
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1OOlI
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1Ol01
+=
+BFMA1lll1
+[
+1
+]
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+2
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:extwrite %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1IOlI
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1Ol01
+=
+BFMA1lll1
+[
+1
+]
+;
+BFMA1Il01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1OOlOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1O000
++
+2
+]
+,
+BFMA1I01
+)
+;
+BFMA1O1l
+<=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:extread @%0d %08x at %0d ns ""
+,
+BFMA1l01
+,
+BFMA1OOlOI
+,
+BFMA1Ol01
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+BFMA1OO11
+=
+1
+;
+BFMA1lO11
+=
+1
+;
+end
+BFMA1lIlI
+:
+begin
+BFMA1O111
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1l011
+=
+BFMA1lI
+[
+2
+]
+;
+BFMA1OI01
+=
+BFMA1O111
++
+3
+;
+begin
+:
+BFMA1IlOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<
+BFMA1O111
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OOOOI
+[
+BFMA1I0I0
+]
+=
+BFMA1lI
+[
+BFMA1I0I0
++
+3
+]
+;
+end
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:extwrite %08x %0d Words at %0t ns""
+,
+BFMA1l01
+,
+BFMA1Ol01
+,
+BFMA1O111
+,
+$time
+)
+;
+BFMA1I111
+=
+0
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1lOlI
+:
+begin
+BFMA1OI01
+=
+3
+;
+BFMA1Ol01
+=
+BFMA1lll1
+[
+1
+]
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+2
+]
+;
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+BFMA1OI11
+=
+1
+;
+BFMA1O1l
+<=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:extcheck %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1OIlI
+:
+begin
+BFMA1OI01
+=
+4
+;
+BFMA1Ol01
+=
+BFMA1lll1
+[
+1
+]
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+2
+]
+;
+BFMA1ll01
+=
+BFMA1lll1
+[
+3
+]
+;
+BFMA1O1l
+<=
+1
+\'b
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:extmask %08x %08x %08x at %0d ns""
+,
+BFMA1l01
+,
+BFMA1Ol01
+,
+BFMA1Il01
+,
+BFMA1ll01
+,
+$time
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1IIlI
+:
+begin
+BFMA1OI01
+=
+1
+;
+BFMA1lI11
+=
+1
+;
+BFMA1OI11
+=
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:extwait ""
+,
+BFMA1l01
+)
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1OllI
+:
+begin
+$display
+(
+""LABEL instructions not allowed in vector files (FAILURE)""
+)
+;
+end
+BFMA1II0I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
++
+BFMA1lI
+[
+1
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:table %08x ... (length=%0d)""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1OI01
+-
+2
+)
+;
+end
+BFMA1IllI
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1OI01
+=
+BFMA1I0OOI
+-
+BFMA1O000
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:jump""
+,
+BFMA1l01
+)
+;
+end
+BFMA1lllI
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+3
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+BFMA1lI
+[
+2
+]
+==
+0
+)
+begin
+BFMA1OI01
+=
+BFMA1I0OOI
+-
+BFMA1O000
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:jumpz  %08x""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+2
+]
+)
+;
+end
+BFMA1lOOl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+5
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1OIIOI
+=
+BFMA1O1O0
+(
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+4
+]
+,
+DEBUG
+)
+;
+if
+(
+BFMA1OIIOI
+==
+0
+)
+begin
+BFMA1OI01
+=
+BFMA1I0OOI
++
+2
+-
+BFMA1O000
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:if %08x func %08x""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+4
+]
+)
+;
+end
+BFMA1OIOl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+5
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1OIIOI
+=
+BFMA1O1O0
+(
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+4
+]
+,
+DEBUG
+)
+;
+if
+(
+BFMA1OIIOI
+!=
+0
+)
+begin
+BFMA1OI01
+=
+BFMA1I0OOI
++
+2
+-
+BFMA1O000
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:ifnot %08x func %08x""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+4
+]
+)
+;
+end
+BFMA1lIOl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1OI01
+=
+BFMA1I0OOI
++
+2
+-
+BFMA1O000
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:else ""
+,
+BFMA1l01
+)
+;
+end
+BFMA1OlOl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:endif ""
+,
+BFMA1l01
+)
+;
+end
+BFMA1IIOl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+5
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+1
+]
++
+2
+;
+BFMA1OIIOI
+=
+BFMA1O1O0
+(
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+4
+]
+,
+DEBUG
+)
+;
+if
+(
+BFMA1OIIOI
+==
+0
+)
+begin
+BFMA1OI01
+=
+BFMA1I0OOI
+-
+BFMA1O000
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:while %08x func %08x""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+4
+]
+)
+;
+end
+BFMA1IlOl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1OI01
+=
+BFMA1I0OOI
+-
+BFMA1O000
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:endwhile""
+,
+BFMA1l01
+)
+;
+end
+BFMA1O0Ol
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+4
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+3
+]
+;
+if
+(
+BFMA1lI
+[
+1
+]
+!=
+BFMA1lI
+[
+2
+]
+)
+begin
+BFMA1OI01
+=
+BFMA1I0OOI
+-
+BFMA1O000
+;
+end
+else
+begin
+BFMA1O01OI
+[
+BFMA1I01OI
+]
+=
+1
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:when %08x=%08x %08x""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+)
+;
+end
+BFMA1l0Ol
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+4
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+3
+]
+;
+if
+(
+BFMA1O01OI
+[
+BFMA1I01OI
+]
+)
+begin
+BFMA1OI01
+=
+BFMA1I0OOI
+-
+BFMA1O000
+;
+end
+else
+begin
+BFMA1O01OI
+[
+BFMA1I01OI
+]
+=
+0
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:default %08x=%08x %08x""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+)
+;
+end
+BFMA1llOl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+1
+;
+BFMA1I01OI
+=
+BFMA1I01OI
++
+1
+;
+BFMA1O01OI
+[
+BFMA1I01OI
+]
+=
+0
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:case""
+,
+BFMA1l01
+)
+;
+end
+BFMA1I0Ol
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+1
+;
+BFMA1I01OI
+=
+BFMA1I01OI
+-
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:endcase""
+,
+BFMA1l01
+)
+;
+end
+BFMA1O0lI
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+3
+;
+BFMA1I0OOI
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+BFMA1lI
+[
+2
+]
+!=
+0
+)
+begin
+BFMA1OI01
+=
+BFMA1I0OOI
+-
+BFMA1O000
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:jumpnz  %08x""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+2
+]
+)
+;
+end
+BFMA1l11I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+4
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+2
+]
+;
+BFMA1ll01
+=
+BFMA1lll1
+[
+3
+]
+;
+BFMA1Il0OI
+=
+(
+BFMA1lll1
+[
+1
+]
+^
+BFMA1Il01
+)
+&
+BFMA1ll01
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:compare  %08x==%08x Mask=%08x (RES=%08x) at %0d ns""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1Il01
+,
+BFMA1ll01
+,
+BFMA1Il0OI
+,
+$time
+)
+;
+if
+(
+BFMA1Il0OI
+!=
+0
+)
+begin
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$display
+(
+""ERROR:  compare failed %08x==%08x Mask=%08x (RES=%08x) ""
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1Il01
+,
+BFMA1ll01
+,
+BFMA1Il0OI
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1l01
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1l01
+,
+BFMA1IIlOI
+)
+)
+;
+$display
+(
+""BFM Data Compare Error (ERROR)""
+)
+;
+$stop
+;
+end
+end
+BFMA1O1Ol
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+4
+;
+BFMA1Il01
+=
+BFMA1lll1
+[
+2
+]
+;
+BFMA1ll01
+=
+BFMA1lll1
+[
+3
+]
+;
+if
+(
+BFMA1lI
+[
+1
+]
+>=
+BFMA1lI
+[
+2
+]
+&
+BFMA1lI
+[
+1
+]
+<=
+BFMA1lI
+[
+3
+]
+)
+begin
+BFMA1Il0OI
+=
+1
+;
+end
+else
+begin
+BFMA1Il0OI
+=
+0
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:cmprange %0d in %0d to %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+,
+$time
+)
+;
+if
+(
+BFMA1Il0OI
+==
+0
+)
+begin
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$display
+(
+""ERROR: cmprange failed %0d in %0d to %0d""
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1l01
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1l01
+,
+BFMA1IIlOI
+)
+)
+;
+$display
+(
+""BFM Data Compare Error (ERROR)""
+)
+;
+$stop
+;
+end
+end
+BFMA1O11I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1lI00
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1I01
+=
+BFMA1I01
++
+BFMA1lI00
+;
+BFMA1ll1
+[
+BFMA1I01
+]
+=
+0
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:int %0d""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+)
+;
+end
+BFMA1I0lI
+,
+BFMA1l0lI
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+if
+(
+BFMA1OO01
+==
+BFMA1I0lI
+)
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1lI00
+=
+0
+;
+end
+else
+begin
+BFMA1lI00
+=
+BFMA1lI
+[
+2
+]
+;
+BFMA1OI01
+=
+3
++
+BFMA1lI00
+;
+end
+BFMA1llOOI
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1O0OOI
+=
+BFMA1O000
++
+BFMA1OI01
+;
+BFMA1OI01
+=
+BFMA1llOOI
+-
+BFMA1O000
+;
+BFMA1ll1
+[
+BFMA1I01
+]
+=
+BFMA1O0OOI
+;
+BFMA1I01
+=
+BFMA1I01
++
+1
+;
+if
+(
+BFMA1lI00
+>
+0
+)
+begin
+begin
+:
+BFMA1llOII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1lI00
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1ll1
+[
+BFMA1I01
+]
+=
+BFMA1lI
+[
+3
++
+BFMA1I0I0
+]
+;
+BFMA1I01
+=
+BFMA1I01
++
+1
+;
+end
+end
+end
+if
+(
+DEBUG
+>=
+2
+&
+BFMA1OO01
+==
+BFMA1I0lI
+)
+$display
+(
+""BFM:%0d:call %0d""
+,
+BFMA1l01
+,
+BFMA1llOOI
+)
+;
+if
+(
+DEBUG
+>=
+2
+&
+BFMA1OO01
+==
+BFMA1l0lI
+)
+$display
+(
+""BFM:%0d:call %0d %08x ...""
+,
+BFMA1l01
+,
+BFMA1llOOI
+,
+BFMA1lI
+[
+3
+]
+)
+;
+end
+BFMA1O1lI
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1I01
+=
+BFMA1I01
+-
+BFMA1lI
+[
+1
+]
+;
+BFMA1O0OOI
+=
+0
+;
+if
+(
+BFMA1I01
+>
+0
+)
+begin
+BFMA1I01
+=
+BFMA1I01
+-
+1
+;
+BFMA1O0OOI
+=
+BFMA1ll1
+[
+BFMA1I01
+]
+;
+end
+if
+(
+BFMA1O0OOI
+==
+0
+)
+begin
+BFMA1lOOOI
+=
+1
+;
+BFMA1OO11
+=
+1
+;
+BFMA1OI1OI
+=
+0
+;
+end
+else
+begin
+BFMA1OI01
+=
+BFMA1O0OOI
+-
+BFMA1O000
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:return""
+,
+BFMA1l01
+)
+;
+end
+BFMA1I1Ol
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+3
+;
+BFMA1I01
+=
+BFMA1I01
+-
+BFMA1lI
+[
+1
+]
+;
+BFMA1O0OOI
+=
+0
+;
+if
+(
+BFMA1I01
+>
+0
+)
+begin
+BFMA1I01
+=
+BFMA1I01
+-
+1
+;
+BFMA1O0OOI
+=
+BFMA1ll1
+[
+BFMA1I01
+]
+;
+end
+BFMA1O01
+=
+BFMA1lI
+[
+2
+]
+;
+if
+(
+BFMA1O0OOI
+==
+0
+)
+begin
+BFMA1lOOOI
+=
+1
+;
+BFMA1OO11
+=
+1
+;
+BFMA1OI1OI
+=
+0
+;
+end
+else
+begin
+BFMA1OI01
+=
+BFMA1O0OOI
+-
+BFMA1O000
+;
+end
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:return %08x""
+,
+BFMA1l01
+,
+BFMA1O01
+)
+;
+end
+BFMA1I1lI
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+5
+;
+BFMA1lOIOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+,
+BFMA1I01
+)
+;
+BFMA1OIIOI
+=
+BFMA1lI
+[
+2
+]
+;
+BFMA1ll1
+[
+BFMA1lOIOI
+]
+=
+BFMA1OIIOI
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:loop %0d %0d %0d %0d ""
+,
+BFMA1l01
+,
+BFMA1lOIOI
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+4
+]
+)
+;
+end
+BFMA1l1lI
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1I0l1
+=
+BFMA1lI
+[
+1
+]
+;
+begin
+:
+BFMA1O0OII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+2
+;
+BFMA1I0I0
+<=
+4
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1Ill1
+[
+BFMA1I0I0
+]
+=
+BFMA1lII1
+(
+(
+to_slv32
+(
+BFMA1Ol
+[
+BFMA1I0l1
+]
+[
+7
++
+BFMA1I0I0
+]
+)
+==
+1
+\'b
+1
+)
+,
+BFMA1Ol
+[
+BFMA1I0l1
++
+BFMA1I0I0
+]
+)
+;
+end
+end
+BFMA1lOIOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1I0l1
++
+1
+]
+,
+BFMA1I01
+)
+;
+BFMA1Il00
+=
+BFMA1Ill1
+[
+4
+]
+;
+BFMA1I100
+=
+BFMA1Ill1
+[
+3
+]
+;
+BFMA1O1l1
+=
+BFMA1ll1
+[
+BFMA1lOIOI
+]
+;
+BFMA1O1l1
+=
+BFMA1O1l1
++
+BFMA1Il00
+;
+BFMA1ll1
+[
+BFMA1lOIOI
+]
+=
+BFMA1O1l1
+;
+BFMA1I0OOI
+=
+BFMA1I0l1
++
+5
+;
+if
+(
+(
+BFMA1Il00
+>=
+0
+&
+BFMA1O1l1
+<=
+BFMA1I100
+)
+|
+(
+BFMA1Il00
+<
+0
+&
+BFMA1O1l1
+>=
+BFMA1I100
+)
+)
+begin
+BFMA1OI01
+=
+BFMA1I0OOI
+-
+BFMA1O000
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:endloop (Next Loop=%0d)""
+,
+BFMA1l01
+,
+BFMA1O1l1
+)
+;
+end
+else
+begin
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:endloop (Finished)""
+,
+BFMA1l01
+)
+;
+end
+end
+BFMA1OI0I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1II01
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:timeout %0d""
+,
+BFMA1l01
+,
+BFMA1II01
+)
+;
+end
+BFMA1Il1I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+BFMA1lO10
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:rand %0d""
+,
+BFMA1l01
+,
+BFMA1lO10
+)
+;
+end
+BFMA1Ol0I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+BFMA1OI00
+(
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+)
+;
+BFMA1l000
+=
+BFMA1ll00
+(
+BFMA1O000
+)
+;
+$display
+(
+""BFM:%0s""
+,
+BFMA1l000
+)
+;
+end
+BFMA1Il0I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+BFMA1OI00
+(
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+)
+;
+BFMA1l000
+=
+BFMA1ll00
+(
+BFMA1O000
+)
+;
+$display
+(
+""################################################################""
+)
+;
+$display
+(
+""BFM:%0s""
+,
+BFMA1l000
+)
+;
+end
+BFMA1ll0I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OlOOI
+=
+BFMA1O01l
+(
+BFMA1I1l1
+[
+15
+:
+8
+]
+)
+;
+BFMA1OI01
+=
+(
+BFMA1OlOOI
+-
+1
+)
+/
+4
++
+2
+;
+end
+BFMA1I10I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+if
+(
+DEBUGLEVEL
+>=
+0
+&
+DEBUGLEVEL
+<=
+5
+)
+begin
+$display
+(
+""BFM:%0d: DEBUG - ignored due to DEBUGLEVEL generic setting""
+,
+BFMA1l01
+)
+;
+end
+else
+begin
+DEBUG
+<=
+BFMA1lI
+[
+1
+]
+;
+$display
+(
+""BFM:%0d: DEBUG %0d""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+)
+;
+end
+end
+BFMA1l1II
+:
+begin
+BFMA1OI1OI
+=
+0
+;
+BFMA1OI01
+=
+2
+;
+BFMA1I1OOI
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1l0IOI
+[
+1
+]
+=
+BFMA1OI
+;
+if
+(
+BFMA1I1OOI
+==
+2
+)
+begin
+if
+(
+BFMA1O0IOI
+)
+begin
+BFMA1l0IOI
+[
+1
+:
+9
+]
+=
+{
+""OCCURRED""
+,
+BFMA1OI
+}
+;
+end
+else
+begin
+$display
+(
+""BFM: HRESP Did Not Occur When Expected (ERROR)""
+)
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$stop
+;
+end
+BFMA1I1OOI
+=
+0
+;
+end
+BFMA1O0IOI
+=
+0
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:hresp %0d %0s""
+,
+BFMA1l01
+,
+BFMA1I1OOI
+,
+BFMA1l0IOI
+)
+;
+end
+BFMA1IO0I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:stop %0d""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1l01
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1l01
+,
+BFMA1IIlOI
+)
+)
+;
+case
+(
+BFMA1lI
+[
+1
+]
+)
+0
+:
+begin
+$display
+(
+""BFM Script Stop Command (NOTE)""
+)
+;
+end
+1
+:
+begin
+$display
+(
+""BFM Script Stop Command (WARNING)""
+)
+;
+end
+3
+:
+begin
+$display
+(
+""BFM Script Stop Command (FAILURE)""
+)
+;
+$stop
+;
+end
+default
+:
+begin
+$display
+(
+""BFM Script Stop Command (ERROR)""
+)
+;
+$stop
+;
+end
+endcase
+end
+BFMA1lO0I
+:
+begin
+BFMA1lOOOI
+=
+1
+;
+end
+BFMA1OlIl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+if
+(
+DEBUG
+>=
+1
+)
+$display
+(
+""BFM:%0d:echo at %0d ns""
+,
+BFMA1l01
+,
+$time
+)
+;
+BFMA1OI01
+=
+2
++
+BFMA1lI
+[
+1
+]
+;
+$display
+(
+""BFM Parameter values are""
+)
+;
+begin
+:
+BFMA1I0OII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+BFMA1OI01
+-
+3
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+$display
+(
+"" Para %0d=0x%08x (%0d)""
+,
+BFMA1I0I0
++
+1
+,
+BFMA1lll1
+[
+2
++
+BFMA1I0I0
+]
+,
+BFMA1lll1
+[
+2
++
+BFMA1I0I0
+]
+)
+;
+end
+end
+end
+BFMA1lI0I
+:
+begin
+BFMA1OI01
+=
+2
+;
+BFMA1lI11
+=
+BFMA1lI
+[
+1
+]
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:flush %0d at %0d ns""
+,
+BFMA1l01
+,
+BFMA1lI11
+,
+$time
+)
+;
+BFMA1OO11
+=
+1
+;
+BFMA1O001
+=
+1
+;
+end
+BFMA1II1I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:setfail""
+,
+BFMA1l01
+)
+;
+$display
+(
+""BFM: User Script detected ERROR (ERROR)""
+)
+;
+$stop
+;
+end
+BFMA1I01I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+3
+;
+BFMA1lOIOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+,
+BFMA1I01
+)
+;
+BFMA1OIIOI
+=
+BFMA1lI
+[
+2
+]
+;
+BFMA1ll1
+[
+BFMA1lOIOI
+]
+=
+BFMA1OIIOI
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:set %0d= 0x%08x (%0d)""
+,
+BFMA1l01
+,
+BFMA1lOIOI
+,
+BFMA1OIIOI
+,
+BFMA1OIIOI
+)
+;
+end
+BFMA1I11I
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+BFMA1lI
+[
+2
+]
++
+3
+;
+BFMA1lOIOI
+=
+BFMA1OOl1
+(
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+,
+BFMA1I01
+)
+;
+BFMA1OIIOI
+=
+BFMA1O1O0
+(
+BFMA1lI
+[
+4
+]
+,
+BFMA1lI
+[
+3
+]
+,
+BFMA1lI
+[
+5
+]
+,
+DEBUG
+)
+;
+BFMA1I0I0
+=
+6
+;
+while
+(
+BFMA1I0I0
+<
+BFMA1OI01
+)
+begin
+BFMA1OIIOI
+=
+BFMA1O1O0
+(
+BFMA1lI
+[
+BFMA1I0I0
+]
+,
+BFMA1OIIOI
+,
+BFMA1lI
+[
+BFMA1I0I0
++
+1
+]
+,
+DEBUG
+)
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+2
+;
+end
+BFMA1ll1
+[
+BFMA1lOIOI
+]
+=
+BFMA1OIIOI
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:set %0d= 0x%08x (%0d)""
+,
+BFMA1l01
+,
+BFMA1lOIOI
+,
+BFMA1OIIOI
+,
+BFMA1OIIOI
+)
+;
+end
+BFMA1OIIl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+if
+(
+BFMA1O11
+)
+begin
+$fflush
+(
+BFMA1lIl1
+)
+;
+$fclose
+(
+BFMA1lIl1
+)
+;
+end
+BFMA1OI01
+=
+BFMA1OI00
+(
+BFMA1Ol
+[
+BFMA1O000
++
+1
+]
+)
+;
+BFMA1I011
+=
+BFMA1ll00
+(
+BFMA1O000
+)
+;
+$display
+(
+""BFM:%0d:LOGFILE %0s""
+,
+BFMA1l01
+,
+BFMA1I011
+)
+;
+BFMA1lIl1
+=
+$fopen
+(
+BFMA1I011
+,
+""w""
+)
+;
+BFMA1O11
+=
+1
+;
+end
+BFMA1IIIl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+2
+;
+$display
+(
+""BFM:%0d:LOGSTART %0d""
+,
+BFMA1l01
+,
+BFMA1lI
+[
+1
+]
+)
+;
+if
+(
+BFMA1O11
+==
+0
+)
+begin
+$display
+(
+""Logfile not defined, ignoring command (ERROR)""
+)
+;
+end
+else
+begin
+BFMA1lO0OI
+=
+(
+(
+BFMA1lll1
+[
+1
+]
+[
+0
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1OI0OI
+=
+(
+(
+BFMA1lll1
+[
+1
+]
+[
+1
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1II0OI
+=
+(
+(
+BFMA1lll1
+[
+1
+]
+[
+2
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1lI0OI
+=
+(
+(
+BFMA1lll1
+[
+1
+]
+[
+3
+]
+)
+==
+1
+\'b
+1
+)
+;
+end
+end
+BFMA1lIIl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+1
+;
+$display
+(
+""BFM:%0d:LOGSTOP""
+,
+BFMA1l01
+)
+;
+BFMA1lO0OI
+=
+0
+;
+BFMA1OI0OI
+=
+0
+;
+BFMA1II0OI
+=
+0
+;
+BFMA1lI0OI
+=
+0
+;
+end
+BFMA1lOIl
+:
+begin
+BFMA1OI1OI
+=
+1
+;
+BFMA1OI01
+=
+1
+;
+$display
+(
+""BFM:%0d:VERSION""
+,
+BFMA1l01
+)
+;
+$display
+(
+""  BFM Verilog Version %0s""
+,
+BFMA1O
+)
+;
+$display
+(
+""  BFM Date %0s""
+,
+BFMA1I
+)
+;
+$display
+(
+""  SVN Revision $Revision: 11864 $""
+)
+;
+$display
+(
+""  SVN Date $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $""
+)
+;
+$display
+(
+""  Compiler Version %0d""
+,
+BFMA1Ol0OI
+)
+;
+$display
+(
+""  Vectors Version %0d""
+,
+BFMA1ll0OI
+)
+;
+$display
+(
+""  No of Vectors %0d""
+,
+BFMA1O0l1
+)
+;
+if
+(
+BFMA1O11
+!=
+BFMA1OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d VR %0s %0s %0d %0d %0d""
+,
+$time
+,
+BFMA1O
+,
+BFMA1I
+,
+BFMA1Ol0OI
+,
+BFMA1ll0OI
+,
+BFMA1O0l1
+)
+;
+end
+end
+default
+:
+begin
+$display
+(
+""BFM: Instruction %0d Line Number %0d Command %0d""
+,
+BFMA1O000
+,
+BFMA1l01
+,
+BFMA1OO01
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1l01
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1l01
+,
+BFMA1IIlOI
+)
+)
+;
+$display
+(
+""Instruction not yet implemented (ERROR)""
+)
+;
+$stop
+;
+end
+endcase
+end
+if
+(
+BFMA1OI1OI
+)
+begin
+BFMA1OI11
+=
+0
+;
+BFMA1O000
+=
+BFMA1O000
++
+BFMA1OI01
+;
+BFMA1OI01
+=
+0
+;
+end
+end
+BFMA1OlIOI
+=
+0
+;
+BFMA1IlIOI
+=
+0
+;
+BFMA1llIOI
+=
+0
+;
+if
+(
+BFMA1IlI
+==
+1
+\'b
+1
+)
+begin
+BFMA1IIIOI
+=
+BFMA1OOl
+&
+BFMA1IOl
+;
+BFMA1lIIOI
+=
+HRDATA
+&
+BFMA1IOl
+;
+BFMA1OlIOI
+=
+(
+BFMA1IIIOI
+===
+BFMA1lIIOI
+)
+;
+end
+if
+(
+BFMA1I1l
+==
+1
+\'b
+1
+)
+begin
+BFMA1IIIOI
+=
+BFMA1lll
+&
+BFMA1O0l
+;
+BFMA1lIIOI
+=
+BFMA1IO0
+&
+BFMA1O0l
+;
+BFMA1IlIOI
+=
+(
+BFMA1IIIOI
+===
+BFMA1lIIOI
+)
+;
+end
+if
+(
+BFMA1l1l
+==
+1
+\'b
+1
+)
+begin
+BFMA1IIIOI
+=
+BFMA1OIl
+&
+BFMA1IIl
+;
+BFMA1lIIOI
+=
+GP_IN
+&
+BFMA1IIl
+;
+BFMA1llIOI
+=
+(
+BFMA1IIIOI
+===
+BFMA1lIIOI
+)
+;
+end
+BFMA1IOlOI
+=
+BFMA1I001
+|
+BFMA1I101
+|
+BFMA1l001
+|
+BFMA1O101
+|
+BFMA1l101
+|
+BFMA1IO11
+|
+BFMA1lO11
+|
+to_boolean
+(
+BFMA1IlI
+|
+BFMA1OlI
+|
+BFMA1lII
+|
+BFMA1III
+|
+BFMA1O1l
+|
+BFMA1I1l
+|
+BFMA1l1l
+)
+;
+if
+(
+BFMA1O001
+)
+begin
+case
+(
+BFMA1IO01
+)
+BFMA1lI0I
+:
+begin
+if
+(
+~
+BFMA1IOlOI
+)
+begin
+if
+(
+BFMA1lI11
+<=
+1
+)
+begin
+BFMA1O001
+=
+0
+;
+end
+else
+begin
+BFMA1lI11
+=
+BFMA1lI11
+-
+1
+;
+end
+end
+end
+BFMA1OO0I
+:
+begin
+if
+(
+BFMA1lI11
+<=
+1
+)
+begin
+BFMA1O001
+=
+0
+;
+end
+else
+begin
+BFMA1lI11
+=
+BFMA1lI11
+-
+1
+;
+end
+end
+BFMA1l1Ol
+,
+BFMA1OOIl
+:
+begin
+if
+(
+$time
+>=
+BFMA1O00OI
+)
+begin
+BFMA1O001
+=
+0
+;
+end
+end
+BFMA1I1II
+,
+BFMA1O1II
+,
+BFMA1l0II
+:
+begin
+if
+(
+BFMA1IlOOI
+==
+256
+)
+begin
+BFMA1I1lOI
+=
+(
+INTERRUPT
+!=
+BFMA1Ol1
+)
+;
+end
+else
+begin
+BFMA1I1lOI
+=
+(
+(
+INTERRUPT
+[
+BFMA1IlOOI
+]
+)
+===
+1
+\'b
+1
+)
+;
+end
+if
+(
+BFMA1I1lOI
+)
+begin
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:Interrupt Wait Time %0d cycles""
+,
+BFMA1OOIOI
+)
+;
+BFMA1O001
+=
+0
+;
+end
+end
+BFMA1OOlI
+:
+begin
+BFMA1OI0
+<=
+BFMA1Ol01
+;
+BFMA1lO0
+<=
+BFMA1Il01
+;
+BFMA1l0l
+<=
+1
+\'b
+1
+;
+BFMA1O001
+=
+0
+;
+end
+BFMA1lIlI
+:
+begin
+BFMA1OI0
+<=
+BFMA1l011
++
+BFMA1I111
+;
+BFMA1lO0
+<=
+BFMA1OOOOI
+[
+BFMA1I111
+]
+;
+BFMA1l0l
+<=
+1
+\'b
+1
+;
+BFMA1I111
+=
+BFMA1I111
++
+1
+;
+if
+(
+BFMA1I111
+>=
+BFMA1O111
+)
+begin
+BFMA1O001
+=
+0
+;
+end
+end
+BFMA1IOlI
+,
+BFMA1lOlI
+,
+BFMA1OIlI
+:
+begin
+BFMA1OI0
+<=
+BFMA1Ol01
+;
+BFMA1OIl
+<=
+BFMA1Il01
+;
+BFMA1IIl
+<=
+BFMA1ll01
+;
+BFMA1lIl
+<=
+BFMA1l01
+;
+BFMA1Oll
+<=
+1
+\'b
+1
+;
+if
+(
+BFMA1I1l
+==
+1
+\'b
+1
+)
+begin
+BFMA1O001
+=
+0
+;
+end
+end
+BFMA1IIlI
+:
+begin
+if
+(
+EXT_WAIT
+==
+1
+\'b
+0
+&
+BFMA1lI11
+==
+0
+)
+begin
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:Exteral Wait Time %0d cycles""
+,
+BFMA1OOIOI
+)
+;
+BFMA1O001
+=
+0
+;
+end
+if
+(
+BFMA1lI11
+>=
+1
+)
+begin
+BFMA1lI11
+=
+BFMA1lI11
+-
+1
+;
+end
+end
+BFMA1IlII
+,
+BFMA1llII
+,
+BFMA1l1OI
+,
+BFMA1OlII
+:
+begin
+BFMA1Oll
+<=
+1
+\'b
+1
+;
+BFMA1OIl
+<=
+BFMA1Il01
+;
+BFMA1IIl
+<=
+BFMA1ll01
+;
+BFMA1lIl
+<=
+BFMA1l01
+;
+BFMA1O001
+=
+0
+;
+end
+BFMA1OOII
+:
+begin
+BFMA1OIl
+<=
+BFMA1Il01
+;
+BFMA1IIl
+<=
+BFMA1ll01
+;
+BFMA1lIl
+<=
+BFMA1l01
+;
+BFMA1l1l
+<=
+1
+\'b
+1
+;
+BFMA1Oll
+<=
+1
+\'b
+0
+;
+if
+(
+BFMA1l1l
+==
+1
+\'b
+1
+&
+BFMA1llIOI
+)
+begin
+BFMA1l1l
+<=
+1
+\'b
+0
+;
+BFMA1O001
+=
+0
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:GP IO Wait Time %0d cycles""
+,
+BFMA1OOIOI
+)
+;
+end
+end
+BFMA1O00I
+,
+BFMA1I00I
+:
+begin
+case
+(
+BFMA1lOO1
+)
+BFMA1Ol10
+:
+BFMA1O001
+=
+0
+;
+BFMA1Il10
+:
+begin
+BFMA1OlO1
+=
+BFMA1lI
+[
+1
+]
++
+BFMA1lI
+[
+2
+]
+;
+BFMA1I110
+=
+BFMA1lI
+[
+3
+]
+;
+BFMA1l110
+=
+BFMA1lI
+[
+4
+]
+%
+65536
+;
+BFMA1IOI1
+=
+(
+(
+BFMA1lll1
+[
+4
+]
+[
+16
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1lOI1
+=
+(
+(
+BFMA1lll1
+[
+4
+]
+[
+17
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1OII1
+=
+(
+(
+BFMA1lll1
+[
+4
+]
+[
+18
+]
+)
+==
+1
+\'b
+1
+)
+;
+BFMA1OOO1
+=
+BFMA1lI
+[
+5
+]
+;
+BFMA1IOO1
+=
+BFMA1lI
+[
+6
+]
+;
+if
+(
+~
+BFMA1OII1
+)
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<
+MAX_MEMTEST
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+BFMA1OIO1
+[
+BFMA1I0I0
+]
+=
+0
+;
+BFMA1O0O1
+=
+0
+;
+BFMA1I0O1
+=
+0
+;
+BFMA1l0O1
+=
+0
+;
+BFMA1OOI1
+=
+0
+;
+BFMA1III1
+=
+0
+;
+if
+(
+BFMA1IO01
+==
+BFMA1I00I
+)
+begin
+BFMA1OlO1
+=
+BFMA1lI
+[
+1
+]
+;
+BFMA1IlO1
+=
+BFMA1lI
+[
+2
+]
+-
+BFMA1I110
+;
+BFMA1I110
+=
+2
+*
+BFMA1I110
+;
+BFMA1OOI1
+=
+1
+;
+end
+if
+(
+BFMA1IO01
+==
+BFMA1O00I
+)
+begin
+$display
+(
+""BFM:%0d: memtest Started at %0d ns""
+,
+BFMA1l01
+,
+$time
+)
+;
+$display
+(
+""BFM:  Address %08x Size %0d Cycles %5d""
+,
+BFMA1OlO1
+,
+BFMA1I110
+,
+BFMA1OOO1
+)
+;
+end
+else
+begin
+$display
+(
+""BFM:%0d: dual memtest Started at %0d ns""
+,
+BFMA1l01
+,
+$time
+)
+;
+$display
+(
+""BFM:  Address %08x %08x  Size %0d Cycles %5d""
+,
+BFMA1OlO1
+,
+BFMA1IlO1
++
+BFMA1I110
+/
+2
+,
+BFMA1I110
+/
+2
+,
+BFMA1OOO1
+)
+;
+end
+case
+(
+BFMA1l110
+)
+0
+:
+begin
+end
+1
+:
+$display
+(
+""BFM: Transfers are APB Byte aligned""
+)
+;
+2
+:
+$display
+(
+""BFM: Transfers are APB Half Word aligned""
+)
+;
+3
+:
+$display
+(
+""BFM: Transfers are APB Word aligned""
+)
+;
+4
+:
+$display
+(
+""BFM: Byte Writes Suppressed""
+)
+;
+default
+:
+$display
+(
+""Illegal Align on memtest (FAILURE)""
+)
+;
+endcase
+if
+(
+BFMA1OII1
+)
+begin
+$display
+(
+""BFM: memtest restarted""
+)
+;
+end
+if
+(
+BFMA1IOI1
+)
+begin
+$display
+(
+""BFM: Memtest Filling Memory""
+)
+;
+BFMA1lOO1
+=
+BFMA1I010
+;
+end
+else
+if
+(
+BFMA1OOO1
+>
+0
+)
+begin
+$display
+(
+""BFM: Memtest Random Read Writes""
+)
+;
+BFMA1lOO1
+=
+BFMA1ll10
+;
+end
+else
+if
+(
+BFMA1lOI1
+)
+begin
+$display
+(
+""BFM: Memtest Verifying Memory Content""
+)
+;
+BFMA1lOO1
+=
+BFMA1l010
+;
+end
+else
+begin
+BFMA1lOO1
+=
+BFMA1O010
+;
+end
+end
+BFMA1ll10
+,
+BFMA1I010
+,
+BFMA1l010
+:
+begin
+if
+(
+~
+(
+BFMA1I101
+|
+BFMA1I001
+)
+)
+begin
+case
+(
+BFMA1lOO1
+)
+BFMA1ll10
+:
+begin
+BFMA1IOO1
+=
+BFMA1lIl0
+(
+BFMA1IOO1
+)
+;
+BFMA1IIO1
+=
+BFMA1O1l0
+(
+BFMA1IOO1
+,
+BFMA1I110
+)
+;
+BFMA1IOO1
+=
+BFMA1lIl0
+(
+BFMA1IOO1
+)
+;
+BFMA1lIO1
+=
+BFMA1O1l0
+(
+BFMA1IOO1
+,
+8
+)
+;
+end
+BFMA1I010
+:
+begin
+BFMA1IIO1
+=
+BFMA1III1
+;
+BFMA1lIO1
+=
+6
+;
+end
+BFMA1l010
+:
+begin
+BFMA1IIO1
+=
+BFMA1III1
+;
+BFMA1lIO1
+=
+2
+;
+end
+default
+:
+begin
+end
+endcase
+case
+(
+BFMA1l110
+)
+0
+:
+begin
+end
+1
+:
+begin
+BFMA1IIO1
+=
+4
+*
+(
+BFMA1IIO1
+/
+4
+)
+;
+case
+(
+BFMA1lIO1
+)
+0
+,
+4
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
+;
+end
+1
+,
+5
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
+-
+1
+;
+end
+2
+,
+6
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
+-
+2
+;
+end
+default
+:
+begin
+end
+endcase
+end
+2
+:
+begin
+BFMA1IIO1
+=
+4
+*
+(
+BFMA1IIO1
+/
+4
+)
+;
+case
+(
+BFMA1lIO1
+)
+0
+,
+4
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
++
+1
+;
+end
+1
+,
+5
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
+;
+end
+2
+,
+6
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
+-
+1
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+:
+begin
+BFMA1IIO1
+=
+4
+*
+(
+BFMA1IIO1
+/
+4
+)
+;
+case
+(
+BFMA1lIO1
+)
+0
+,
+4
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
++
+2
+;
+end
+1
+,
+5
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
++
+1
+;
+end
+2
+,
+6
+:
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
+;
+end
+default
+:
+begin
+end
+endcase
+end
+4
+:
+begin
+case
+(
+BFMA1lIO1
+)
+4
+:
+begin
+BFMA1IIO1
+=
+2
+*
+(
+BFMA1IIO1
+/
+2
+)
+;
+BFMA1lIO1
+=
+5
+;
+end
+default
+:
+begin
+end
+endcase
+end
+default
+:
+begin
+end
+endcase
+if
+(
+BFMA1lIO1
+>=
+0
+&
+BFMA1lIO1
+<=
+2
+)
+begin
+case
+(
+BFMA1lIO1
+)
+0
+:
+begin
+BFMA1lI01
+=
+3
+\'b
+000
+;
+BFMA1IIO1
+=
+BFMA1IIO1
+;
+BFMA1llO1
+=
+(
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+>=
+256
+)
+;
+end
+1
+:
+begin
+BFMA1lI01
+=
+3
+\'b
+001
+;
+BFMA1IIO1
+=
+2
+*
+(
+BFMA1IIO1
+/
+2
+)
+;
+BFMA1llO1
+=
+(
+(
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+>=
+256
+)
+&
+(
+BFMA1OIO1
+[
+BFMA1IIO1
++
+1
+]
+>=
+256
+)
+)
+;
+end
+2
+:
+begin
+BFMA1lI01
+=
+3
+\'b
+010
+;
+BFMA1IIO1
+=
+4
+*
+(
+BFMA1IIO1
+/
+4
+)
+;
+BFMA1llO1
+=
+(
+(
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+>=
+256
+)
+&
+(
+BFMA1OIO1
+[
+BFMA1IIO1
++
+1
+]
+>=
+256
+)
+&
+(
+BFMA1OIO1
+[
+BFMA1IIO1
++
+2
+]
+>=
+256
+)
+&
+(
+BFMA1OIO1
+[
+BFMA1IIO1
++
+3
+]
+>=
+256
+)
+)
+;
+end
+default
+:
+begin
+end
+endcase
+if
+(
+BFMA1llO1
+)
+begin
+BFMA1I001
+=
+1
+;
+BFMA1O0O1
+=
+BFMA1O0O1
++
+1
+;
+if
+(
+BFMA1OOI1
+==
+1
+&
+BFMA1IIO1
+>=
+BFMA1I110
+/
+2
+)
+begin
+BFMA1Ol01
+=
+BFMA1IlO1
++
+BFMA1IIO1
+;
+end
+else
+begin
+BFMA1Ol01
+=
+BFMA1OlO1
++
+BFMA1IIO1
+;
+end
+case
+(
+BFMA1lIO1
+)
+0
+:
+begin
+BFMA1Il01
+=
+{
+BFMA1lI1
+[
+31
+:
+8
+]
+,
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+[
+7
+:
+0
+]
+}
+;
+end
+1
+:
+begin
+BFMA1Il01
+=
+{
+BFMA1lI1
+[
+31
+:
+16
+]
+,
+BFMA1OIO1
+[
+BFMA1IIO1
++
+1
+]
+[
+7
+:
+0
+]
+,
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+[
+7
+:
+0
+]
+}
+;
+end
+2
+:
+begin
+BFMA1Il01
+=
+{
+BFMA1OIO1
+[
+BFMA1IIO1
++
+3
+]
+[
+7
+:
+0
+]
+,
+BFMA1OIO1
+[
+BFMA1IIO1
++
+2
+]
+[
+7
+:
+0
+]
+,
+BFMA1OIO1
+[
+BFMA1IIO1
++
+1
+]
+[
+7
+:
+0
+]
+,
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+[
+7
+:
+0
+]
+}
+;
+end
+default
+:
+begin
+BFMA1Il01
+=
+BFMA1lI1
+[
+31
+:
+0
+]
+;
+end
+endcase
+BFMA1ll01
+=
+{
+32
+{
+1
+\'b
+1
+}
+}
+;
+end
+else
+begin
+BFMA1lIO1
+=
+BFMA1lIO1
++
+4
+;
+if
+(
+BFMA1lIO1
+==
+4
+&
+BFMA1l110
+==
+4
+)
+begin
+BFMA1lIO1
+=
+5
+;
+end
+end
+end
+if
+(
+BFMA1lIO1
+>=
+4
+&
+BFMA1lIO1
+<=
+6
+)
+begin
+BFMA1I101
+=
+1
+;
+BFMA1I0O1
+=
+BFMA1I0O1
++
+1
+;
+BFMA1IOO1
+=
+BFMA1lIl0
+(
+BFMA1IOO1
+)
+;
+BFMA1Il01
+=
+BFMA1IOO1
+;
+case
+(
+BFMA1lIO1
+)
+4
+:
+begin
+BFMA1lI01
+=
+3
+\'b
+000
+;
+BFMA1IIO1
+=
+BFMA1IIO1
+;
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+=
+256
++
+BFMA1Il01
+[
+7
+:
+0
+]
+;
+end
+5
+:
+begin
+BFMA1lI01
+=
+3
+\'b
+001
+;
+BFMA1IIO1
+=
+2
+*
+(
+BFMA1IIO1
+/
+2
+)
+;
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+=
+256
++
+BFMA1Il01
+[
+7
+:
+0
+]
+;
+BFMA1OIO1
+[
+BFMA1IIO1
++
+1
+]
+=
+256
++
+BFMA1Il01
+[
+15
+:
+8
+]
+;
+end
+6
+:
+begin
+BFMA1lI01
+=
+3
+\'b
+010
+;
+BFMA1IIO1
+=
+4
+*
+(
+BFMA1IIO1
+/
+4
+)
+;
+BFMA1OIO1
+[
+BFMA1IIO1
++
+0
+]
+=
+256
++
+BFMA1Il01
+[
+7
+:
+0
+]
+;
+BFMA1OIO1
+[
+BFMA1IIO1
++
+1
+]
+=
+256
++
+BFMA1Il01
+[
+15
+:
+8
+]
+;
+BFMA1OIO1
+[
+BFMA1IIO1
++
+2
+]
+=
+256
++
+BFMA1Il01
+[
+23
+:
+16
+]
+;
+BFMA1OIO1
+[
+BFMA1IIO1
++
+3
+]
+=
+256
++
+BFMA1Il01
+[
+31
+:
+24
+]
+;
+end
+default
+:
+begin
+end
+endcase
+if
+(
+BFMA1OOI1
+==
+1
+&
+BFMA1IIO1
+>=
+BFMA1I110
+/
+2
+)
+begin
+BFMA1Ol01
+=
+BFMA1IlO1
++
+BFMA1IIO1
+;
+end
+else
+begin
+BFMA1Ol01
+=
+BFMA1OlO1
++
+BFMA1IIO1
+;
+end
+end
+if
+(
+BFMA1lIO1
+==
+3
+|
+BFMA1lIO1
+==
+7
+)
+begin
+BFMA1l0O1
+=
+BFMA1l0O1
++
+1
+;
+end
+BFMA1III1
+=
+BFMA1III1
++
+4
+;
+case
+(
+BFMA1lOO1
+)
+BFMA1ll10
+:
+begin
+if
+(
+BFMA1OOO1
+>
+0
+)
+begin
+BFMA1OOO1
+=
+BFMA1OOO1
+-
+1
+;
+end
+else
+if
+(
+BFMA1lOI1
+)
+begin
+BFMA1III1
+=
+0
+;
+BFMA1lOO1
+=
+BFMA1l010
+;
+$display
+(
+""BFM: Memtest Verifying Memory Content""
+)
+;
+end
+else
+begin
+BFMA1lOO1
+=
+BFMA1O010
+;
+end
+end
+BFMA1I010
+:
+begin
+if
+(
+BFMA1III1
+>=
+BFMA1I110
+)
+begin
+if
+(
+BFMA1OOO1
+==
+0
+)
+begin
+if
+(
+BFMA1lOI1
+)
+begin
+BFMA1III1
+=
+0
+;
+BFMA1lOO1
+=
+BFMA1l010
+;
+$display
+(
+""BFM: Memtest Verifying Memory Content""
+)
+;
+end
+else
+begin
+BFMA1lOO1
+=
+BFMA1O010
+;
+end
+end
+else
+begin
+BFMA1lOO1
+=
+BFMA1ll10
+;
+$display
+(
+""BFM: Memtest Random Read Writes""
+)
+;
+end
+end
+end
+BFMA1l010
+:
+begin
+if
+(
+BFMA1III1
+>=
+BFMA1I110
+)
+begin
+BFMA1lOO1
+=
+BFMA1O010
+;
+end
+end
+default
+:
+begin
+end
+endcase
+BFMA1Il11
+=
+BFMA1II01
+;
+end
+end
+BFMA1O010
+:
+begin
+if
+(
+~
+BFMA1IOlOI
+)
+begin
+BFMA1lOO1
+=
+BFMA1Ol10
+;
+$display
+(
+""BFM: bfmtest complete  Writes %0d  Reads %0d  Nops %0d""
+,
+BFMA1I0O1
+,
+BFMA1O0O1
+,
+BFMA1l0O1
+)
+;
+end
+end
+endcase
+end
+default
+:
+begin
+end
+endcase
+end
+if
+(
+BFMA1OO0OI
+==
+0
+)
+begin
+BFMA1IO0OI
+=
+0
+;
+BFMA1OO0OI
+=
+BFMA1IllOI
+;
+end
+else
+begin
+BFMA1OO0OI
+=
+BFMA1OO0OI
+-
+1
+;
+BFMA1IO0OI
+=
+1
+;
+end
+if
+(
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1l0
+<=
+2
+\'b
+00
+;
+BFMA1O1
+<=
+1
+\'b
+0
+;
+BFMA1lII
+<=
+1
+\'b
+0
+;
+BFMA1OlI
+<=
+1
+\'b
+0
+;
+BFMA1llI
+<=
+1
+\'b
+0
+;
+if
+(
+BFMA1lII
+==
+1
+\'b
+1
+|
+BFMA1OlI
+==
+1
+\'b
+1
+)
+begin
+BFMA1I0I
+<=
+1
+\'b
+0
+;
+end
+if
+(
+BFMA1I101
+&
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1l1
+<=
+BFMA1Ol01
+;
+BFMA1O1
+<=
+1
+\'b
+1
+;
+BFMA1ll
+<=
+BFMA1l1IOI
+;
+BFMA1l0
+<=
+2
+\'b
+10
+;
+BFMA1O0
+<=
+BFMA1O1IOI
+;
+BFMA1I0
+<=
+BFMA1I1IOI
+;
+BFMA1IOI
+<=
+BFMA1lI01
+;
+BFMA1l1I
+<=
+BFMA1l01l
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+BFMA1Il01
+,
+BFMA1I0lOI
+)
+;
+BFMA1lII
+<=
+1
+\'b
+1
+;
+BFMA1O00
+<=
+BFMA1l01
+;
+BFMA1I101
+=
+0
+;
+end
+if
+(
+BFMA1I001
+&
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1l1
+<=
+BFMA1Ol01
+;
+BFMA1O1
+<=
+1
+\'b
+0
+;
+BFMA1ll
+<=
+BFMA1l1IOI
+;
+BFMA1l0
+<=
+2
+\'b
+10
+;
+BFMA1O0
+<=
+BFMA1O1IOI
+;
+BFMA1I0
+<=
+BFMA1I1IOI
+;
+BFMA1IOI
+<=
+BFMA1lI01
+;
+BFMA1O1I
+<=
+BFMA1l01l
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+BFMA1Il01
+,
+BFMA1I0lOI
+)
+;
+BFMA1I1I
+<=
+BFMA1OIO0
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+BFMA1ll01
+,
+BFMA1I0lOI
+)
+;
+BFMA1O00
+<=
+BFMA1l01
+;
+BFMA1OlI
+<=
+1
+\'b
+1
+;
+BFMA1I0I
+<=
+1
+\'b
+1
+;
+BFMA1I001
+=
+0
+;
+end
+if
+(
+BFMA1IO11
+&
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1l1
+<=
+BFMA1Ol01
+;
+BFMA1O1
+<=
+BFMA1I00OI
+;
+BFMA1ll
+<=
+BFMA1I10OI
+;
+BFMA1l0
+<=
+BFMA1l00OI
+;
+BFMA1O0
+<=
+BFMA1l10OI
+;
+BFMA1I0
+<=
+BFMA1O10OI
+;
+BFMA1IOI
+<=
+BFMA1lI01
+;
+BFMA1l1I
+<=
+BFMA1l01l
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+BFMA1Il01
+,
+BFMA1I0lOI
+)
+;
+BFMA1lII
+<=
+1
+\'b
+1
+;
+BFMA1O00
+<=
+BFMA1l01
+;
+BFMA1IO11
+=
+0
+;
+end
+if
+(
+BFMA1l101
+&
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1l1
+<=
+BFMA1Ol01
+;
+BFMA1O1
+<=
+1
+\'b
+0
+;
+BFMA1ll
+<=
+BFMA1l1IOI
+;
+BFMA1O0
+<=
+BFMA1O1IOI
+;
+BFMA1I0
+<=
+BFMA1I1IOI
+;
+BFMA1IOI
+<=
+BFMA1lI01
+;
+BFMA1O1I
+<=
+BFMA1l01l
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+BFMA1Il01
+,
+BFMA1I0lOI
+)
+;
+BFMA1I1I
+<=
+BFMA1OIO0
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+BFMA1ll01
+,
+BFMA1I0lOI
+)
+;
+BFMA1O00
+<=
+BFMA1l01
+;
+if
+(
+BFMA1OlI
+==
+1
+\'b
+1
+|
+BFMA1IlI
+==
+1
+\'b
+1
+)
+begin
+BFMA1l0
+<=
+2
+\'b
+00
+;
+end
+else
+begin
+BFMA1l0
+<=
+2
+\'b
+10
+;
+BFMA1OlI
+<=
+1
+\'b
+1
+;
+BFMA1llI
+<=
+1
+\'b
+1
+;
+end
+if
+(
+BFMA1O0I
+==
+1
+\'b
+1
+&
+BFMA1OlIOI
+)
+begin
+BFMA1l101
+=
+0
+;
+end
+end
+if
+(
+BFMA1l001
+&
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1l1
+<=
+BFMA1Ol01
+;
+BFMA1O1
+<=
+1
+\'b
+1
+;
+BFMA1ll
+<=
+BFMA1l1IOI
+;
+BFMA1O0
+<=
+BFMA1O1IOI
+;
+BFMA1I0
+<=
+BFMA1I1IOI
+;
+BFMA1IOI
+<=
+BFMA1lI01
+;
+BFMA1O00
+<=
+BFMA1l01
+;
+if
+(
+BFMA1IO0OI
+)
+begin
+BFMA1l0
+<=
+2
+\'b
+01
+;
+end
+else
+begin
+BFMA1l1I
+<=
+BFMA1l01l
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+to_slv32
+(
+BFMA1OOOOI
+[
+BFMA1I111
+]
+)
+,
+BFMA1I0lOI
+)
+;
+BFMA1lII
+<=
+1
+\'b
+1
+;
+if
+(
+BFMA1I111
+==
+0
+|
+BFMA1l1l1
+==
+3
+|
+bound1k
+(
+BFMA1O0lOI
+,
+BFMA1Ol01
+)
+)
+begin
+BFMA1l0
+<=
+2
+\'b
+10
+;
+end
+else
+begin
+BFMA1l0
+<=
+2
+\'b
+11
+;
+end
+BFMA1Ol01
+=
+BFMA1Ol01
++
+BFMA1l111
+;
+BFMA1I111
+=
+BFMA1I111
++
+1
+;
+if
+(
+BFMA1I111
+==
+BFMA1O111
+)
+begin
+BFMA1l001
+=
+0
+;
+end
+end
+end
+if
+(
+BFMA1O101
+&
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1l1
+<=
+BFMA1Ol01
+;
+BFMA1O1
+<=
+1
+\'b
+0
+;
+BFMA1ll
+<=
+BFMA1l1IOI
+;
+BFMA1O0
+<=
+BFMA1O1IOI
+;
+BFMA1I0
+<=
+BFMA1I1IOI
+;
+BFMA1IOI
+<=
+BFMA1lI01
+;
+BFMA1O00
+<=
+BFMA1l01
+;
+if
+(
+BFMA1IO0OI
+)
+begin
+BFMA1l0
+<=
+2
+\'b
+01
+;
+end
+else
+begin
+BFMA1O1I
+<=
+BFMA1l01l
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+to_slv32
+(
+BFMA1OOOOI
+[
+BFMA1I111
+]
+)
+,
+BFMA1I0lOI
+)
+;
+BFMA1I1I
+<=
+BFMA1OIO0
+(
+BFMA1lI01
+,
+BFMA1Ol01
+[
+1
+:
+0
+]
+,
+BFMA1ll01
+,
+BFMA1I0lOI
+)
+;
+BFMA1OlI
+<=
+1
+\'b
+1
+;
+BFMA1I0I
+<=
+1
+\'b
+1
+;
+if
+(
+BFMA1I111
+==
+0
+|
+BFMA1l1l1
+==
+3
+|
+bound1k
+(
+BFMA1O0lOI
+,
+BFMA1Ol01
+)
+)
+begin
+BFMA1l0
+<=
+2
+\'b
+10
+;
+end
+else
+begin
+BFMA1l0
+<=
+2
+\'b
+11
+;
+end
+BFMA1Ol01
+=
+BFMA1Ol01
++
+BFMA1l111
+;
+BFMA1I111
+=
+BFMA1I111
++
+1
+;
+if
+(
+BFMA1I111
+==
+BFMA1O111
+)
+begin
+BFMA1O101
+=
+0
+;
+end
+end
+end
+end
+if
+(
+HREADY
+==
+1
+\'b
+1
+)
+begin
+BFMA1III
+<=
+BFMA1lII
+;
+BFMA1IlI
+<=
+BFMA1OlI
+;
+BFMA1O0I
+<=
+BFMA1llI
+;
+BFMA1l0I
+<=
+BFMA1I0I
+;
+BFMA1OOl
+<=
+BFMA1O1I
+;
+BFMA1IOl
+<=
+BFMA1I1I
+;
+BFMA1I00
+<=
+BFMA1O00
+;
+BFMA1OOI
+<=
+BFMA1l1
+;
+BFMA1lOI
+<=
+BFMA1IOI
+;
+end
+BFMA1I1l
+<=
+BFMA1O1l
+;
+BFMA1II0
+<=
+BFMA1OI0
+;
+BFMA1Ill
+<=
+BFMA1Oll
+;
+BFMA1lll
+<=
+BFMA1OIl
+;
+BFMA1O0l
+<=
+BFMA1IIl
+;
+BFMA1I0l
+<=
+BFMA1lIl
+;
+if
+(
+HREADY
+==
+1
+\'b
+1
+)
+begin
+if
+(
+BFMA1lII
+==
+1
+\'b
+1
+)
+begin
+BFMA1lOl
+<=
+BFMA1l1I
+;
+end
+else
+begin
+BFMA1lOl
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+end
+if
+(
+BFMA1III
+==
+1
+\'b
+1
+&
+DEBUG
+>=
+3
+)
+begin
+$display
+(
+""BFM: Data Write %08x %08x""
+,
+BFMA1OOI
+,
+BFMA1lOl
+)
+;
+end
+if
+(
+BFMA1lO0OI
+&
+BFMA1III
+==
+1
+\'b
+1
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d AW %c %08x %08x""
+,
+$time
+,
+BFMA1IlO0
+(
+BFMA1lOI
+)
+,
+BFMA1OOI
+,
+BFMA1lOl
+)
+;
+end
+end
+if
+(
+BFMA1OO0
+==
+1
+\'b
+1
+&
+BFMA1II0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d GW   %08x ""
+,
+$time
+,
+BFMA1O10
+)
+;
+end
+if
+(
+BFMA1l0l
+==
+1
+\'b
+1
+&
+BFMA1OI0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d EW   %08x %08x""
+,
+$time
+,
+BFMA1OI0
+,
+BFMA1lO0
+)
+;
+end
+if
+(
+HREADY
+==
+1
+\'b
+1
+)
+begin
+if
+(
+BFMA1IlI
+==
+1
+\'b
+1
+)
+begin
+if
+(
+DEBUG
+>=
+3
+)
+begin
+if
+(
+BFMA1IOl
+==
+BFMA1lI1
+)
+begin
+$display
+(
+""BFM: Data Read %08x %08x""
+,
+BFMA1OOI
+,
+HRDATA
+)
+;
+end
+else
+begin
+$display
+(
+""BFM: Data Read %08x %08x MASK:%08x""
+,
+BFMA1OOI
+,
+HRDATA
+,
+BFMA1IOl
+)
+;
+end
+end
+if
+(
+BFMA1lO0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d AR %c %08x %08x""
+,
+$time
+,
+BFMA1IlO0
+(
+BFMA1lOI
+)
+,
+BFMA1OOI
+,
+HRDATA
+)
+;
+end
+if
+(
+BFMA1OOlOI
+>=
+0
+)
+begin
+BFMA1ll1
+[
+BFMA1OOlOI
+]
+=
+BFMA1O01l
+(
+BFMA1IIO0
+(
+BFMA1lOI
+,
+BFMA1OOI
+[
+1
+:
+0
+]
+,
+HRDATA
+,
+BFMA1I0lOI
+)
+)
+;
+end
+if
+(
+BFMA1l0I
+==
+1
+\'b
+1
+&
+~
+BFMA1OlIOI
+)
+begin
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$display
+(
+""ERROR: AHB Data Read Comparison failed Addr:%08x  Got:%08x  EXP:%08x  (MASK:%08x)""
+,
+BFMA1OOI
+,
+HRDATA
+,
+BFMA1OOl
+,
+BFMA1IOl
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1I00
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1I00
+,
+BFMA1IIlOI
+)
+)
+;
+$display
+(
+""BFM Data Compare Error (ERROR)""
+)
+;
+$stop
+;
+if
+(
+BFMA1lO0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d ERROR  Addr:%08x  Got:%08x  EXP:%08x  (MASK:%08x)""
+,
+$time
+,
+BFMA1OOI
+,
+HRDATA
+,
+BFMA1OOl
+,
+BFMA1IOl
+)
+;
+end
+end
+end
+end
+if
+(
+BFMA1l1l
+==
+1
+\'b
+1
+)
+begin
+if
+(
+DEBUG
+>=
+3
+)
+begin
+if
+(
+BFMA1IIl
+==
+BFMA1lI1
+)
+begin
+$display
+(
+""BFM: GP IO Data Read %08x""
+,
+GP_IN
+)
+;
+end
+else
+begin
+$display
+(
+""BFM: GP IO Data Read %08x  MASK:%08x""
+,
+GP_IN
+,
+BFMA1IIl
+)
+;
+end
+end
+if
+(
+BFMA1II0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d GR   %08x ""
+,
+$time
+,
+BFMA1OIl
+)
+;
+end
+if
+(
+BFMA1OOlOI
+>=
+0
+)
+begin
+BFMA1ll1
+[
+BFMA1OOlOI
+]
+=
+GP_IN
+;
+end
+if
+(
+BFMA1Oll
+==
+1
+\'b
+1
+&
+~
+BFMA1llIOI
+)
+begin
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$display
+(
+""GPIO input not as expected  Got:%08x  EXP:%08x  (MASK:%08x)""
+,
+GP_IN
+,
+BFMA1OIl
+,
+BFMA1IIl
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1lIl
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1lIl
+,
+BFMA1IIlOI
+)
+)
+;
+$display
+(
+""BFM GPIO Compare Error (ERROR)""
+)
+;
+$stop
+;
+if
+(
+BFMA1II0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""ERROR  Got:%08x  EXP:%08x  (MASK:%08x)""
+,
+GP_IN
+,
+BFMA1OIl
+,
+BFMA1IIl
+)
+;
+end
+end
+end
+if
+(
+BFMA1I1l
+==
+1
+\'b
+1
+)
+begin
+if
+(
+DEBUG
+>=
+3
+)
+begin
+if
+(
+BFMA1O0l
+==
+BFMA1lI1
+)
+begin
+$display
+(
+""BFM: Extention Data Read %08x %08x""
+,
+BFMA1II0
+,
+BFMA1IO0
+)
+;
+end
+else
+begin
+$display
+(
+""BFM: Extention Data Read %08x %08x  MASK:%08x""
+,
+BFMA1II0
+,
+BFMA1IO0
+,
+BFMA1O0l
+)
+;
+end
+end
+if
+(
+BFMA1OI0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""%05d ER   %08x %08x""
+,
+$time
+,
+BFMA1II0
+,
+BFMA1lll
+)
+;
+end
+if
+(
+BFMA1OOlOI
+>=
+0
+)
+begin
+BFMA1ll1
+[
+BFMA1OOlOI
+]
+=
+BFMA1O01l
+(
+BFMA1IO0
+)
+;
+end
+if
+(
+BFMA1Ill
+==
+1
+\'b
+1
+&
+~
+BFMA1IlIOI
+)
+begin
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$display
+(
+""ERROR: Extention Data Read Comparison FAILED  Got:%08x  EXP:%08x  (MASK:%08x)""
+,
+BFMA1IO0
+,
+BFMA1lll
+,
+BFMA1O0l
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1I0l
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1I0l
+,
+BFMA1IIlOI
+)
+)
+;
+$display
+(
+""BFM Extention Data Compare Error (ERROR)""
+)
+;
+$stop
+;
+if
+(
+BFMA1OI0OI
+)
+begin
+$fdisplay
+(
+BFMA1lIl1
+,
+""ERROR  Got:%08x  EXP:%08x  (MASK:%08x)""
+,
+BFMA1IO0
+,
+BFMA1lll
+,
+BFMA1O0l
+)
+;
+end
+end
+end
+BFMA1OO1OI
+=
+BFMA1I001
+|
+BFMA1I101
+|
+BFMA1l001
+|
+BFMA1O101
+|
+BFMA1l101
+|
+BFMA1IO11
+|
+to_boolean
+(
+BFMA1OlI
+|
+BFMA1lII
+|
+BFMA1O1l
+|
+BFMA1l1l
+)
+|
+(
+to_boolean
+(
+(
+BFMA1IlI
+|
+BFMA1III
+)
+&
+~
+HREADY
+)
+)
+;
+if
+(
+BFMA1O001
+)
+begin
+case
+(
+BFMA1IO01
+)
+BFMA1OI1I
+:
+begin
+if
+(
+~
+BFMA1OO1OI
+)
+begin
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:checktime was %0d cycles ""
+,
+BFMA1l01
+,
+BFMA1OOIOI
+)
+;
+if
+(
+BFMA1OOIOI
+<
+BFMA1lI
+[
+1
+]
+|
+BFMA1OOIOI
+>
+BFMA1lI
+[
+2
+]
+)
+begin
+$display
+(
+""BFM: ERROR checktime %0d %0d Actual %0d""
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1OOIOI
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1I00
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1I00
+,
+BFMA1IIlOI
+)
+)
+;
+$display
+(
+""BFM checktime failure (ERROR)""
+)
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$stop
+;
+end
+BFMA1O001
+=
+0
+;
+BFMA1I1O1
+=
+BFMA1OOIOI
+;
+end
+end
+BFMA1Ol1I
+:
+begin
+if
+(
+~
+BFMA1OO1OI
+)
+begin
+BFMA1l1O1
+=
+BFMA1l1O1
+-
+1
+;
+if
+(
+DEBUG
+>=
+2
+)
+$display
+(
+""BFM:%0d:checktimer was %0d cycles ""
+,
+BFMA1l01
+,
+BFMA1l1O1
+)
+;
+if
+(
+BFMA1l1O1
+<
+BFMA1lI
+[
+1
+]
+|
+BFMA1l1O1
+>
+BFMA1lI
+[
+2
+]
+)
+begin
+$display
+(
+""BFM: ERROR checktimer %0d %0d Actual %0d""
+,
+BFMA1lI
+[
+1
+]
+,
+BFMA1lI
+[
+2
+]
+,
+BFMA1l1O1
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1I00
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1I00
+,
+BFMA1IIlOI
+)
+)
+;
+$display
+(
+""BFM checktimer failure (ERROR)""
+)
+;
+BFMA1II10
+=
+BFMA1II10
++
+1
+;
+$stop
+;
+end
+BFMA1O001
+=
+0
+;
+BFMA1O1O1
+=
+BFMA1l1O1
+;
+end
+end
+default
+:
+begin
+end
+endcase
+end
+if
+(
+BFMA1l0lOI
+)
+begin
+if
+(
+BFMA1Il11
+>
+0
+)
+begin
+BFMA1Il11
+=
+BFMA1Il11
+-
+1
+;
+end
+else
+begin
+BFMA1Il11
+=
+BFMA1II01
+;
+$display
+(
+""BFM Command Timeout Occured""
+)
+;
+$display
+(
+""       Stimulus file %0s  Line No %0d""
+,
+BFMA1lOlOI
+[
+BFMA1OIl0
+(
+BFMA1I00
+,
+BFMA1IIlOI
+)
+]
+,
+BFMA1l1I0
+(
+BFMA1I00
+,
+BFMA1IIlOI
+)
+)
+;
+if
+(
+~
+BFMA1lOOOI
+)
+$display
+(
+""BFM Command timeout occured (ERROR)""
+)
+;
+if
+(
+BFMA1lOOOI
+)
+$display
+(
+""BFM Completed and timeout occured (ERROR)""
+)
+;
+$stop
+;
+end
+end
+else
+begin
+BFMA1Il11
+=
+BFMA1II01
+;
+end
+if
+(
+BFMA1II10
+>
+0
+)
+begin
+BFMA1OO1
+<=
+1
+\'b
+1
+;
+end
+if
+(
+BFMA1O001
+|
+BFMA1I001
+|
+BFMA1I101
+|
+BFMA1l001
+|
+BFMA1O101
+|
+BFMA1l101
+|
+BFMA1IO11
+|
+(
+(
+BFMA1OO11
+|
+BFMA1lllOI
+)
+&
+BFMA1IOlOI
+)
+)
+begin
+BFMA1OI11
+=
+1
+;
+end
+else
+begin
+BFMA1OO11
+=
+0
+;
+if
+(
+~
+BFMA1lOOOI
+)
+begin
+BFMA1OI11
+=
+0
+;
+end
+BFMA1O000
+=
+BFMA1O000
++
+BFMA1OI01
+;
+BFMA1OI01
+=
+0
+;
+if
+(
+OPMODE
+>
+0
+)
+begin
+if
+(
+BFMA1O1lOI
+|
+BFMA1lOOOI
+)
+begin
+BFMA1l0lOI
+=
+0
+;
+BFMA1OI11
+=
+0
+;
+end
+end
+end
+if
+(
+BFMA1l10
+==
+1
+\'b
+0
+&
+OPMODE
+==
+0
+&
+BFMA1lOOOI
+&
+~
+BFMA1IOlOI
+)
+begin
+$display
+(
+""###########################################################""
+)
+;
+$display
+(
+"" ""
+)
+;
+if
+(
+BFMA1II10
+==
+0
+)
+begin
+$display
+(
+""BFM Simulation Complete - %0d Instructions - NO ERRORS""
+,
+BFMA1IOIOI
+)
+;
+end
+else
+begin
+$display
+(
+""BFM Simulation Complete - %0d Instructions - %0d ERRORS OCCURED""
+,
+BFMA1IOIOI
+,
+BFMA1II10
+)
+;
+end
+$display
+(
+"" ""
+)
+;
+$display
+(
+""###########################################################""
+)
+;
+$display
+(
+"" ""
+)
+;
+BFMA1l10
+<=
+1
+\'b
+1
+;
+BFMA1OI11
+=
+1
+;
+BFMA1l0lOI
+=
+0
+;
+if
+(
+BFMA1O11
+)
+begin
+$fflush
+(
+BFMA1lIl1
+)
+;
+$fclose
+(
+BFMA1lIl1
+)
+;
+end
+if
+(
+BFMA1l1lOI
+==
+1
+)
+$stop
+;
+if
+(
+BFMA1l1lOI
+==
+2
+)
+$finish
+;
+end
+CON_BUSY
+<=
+(
+BFMA1l0lOI
+|
+BFMA1IOlOI
+)
+;
+INSTR_OUT
+<=
+to_slv32
+(
+BFMA1O000
+)
+;
+end
+end
+assign
+#
+TPD
+GP_OUT
+=
+BFMA1O10
+;
+assign
+#
+TPD
+EXT_WR
+=
+BFMA1l0l
+;
+assign
+#
+TPD
+EXT_RD
+=
+BFMA1O1l
+;
+assign
+#
+TPD
+EXT_ADDR
+=
+BFMA1OI0
+;
+assign
+#
+TPD
+EXT_DATA
+=
+(
+BFMA1l0l
+==
+1
+\'b
+1
+)
+?
+BFMA1lO0
+:
+{
+32
+{
+1
+\'b
+z
+}
+}
+;
+assign
+BFMA1IO0
+=
+EXT_DATA
+;
+always
+@
+(
+BFMA1l1
+)
+begin
+begin
+:
+BFMA1l0OII
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+15
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OII
+[
+BFMA1I0I0
+]
+<=
+(
+BFMA1l1
+[
+31
+:
+28
+]
+==
+BFMA1I0I0
+)
+;
+end
+end
+end
+assign
+HCLK
+=
+(
+BFMA1IO1
+)
+?
+1
+\'b
+x
+:
+(
+SYSCLK
+|
+BFMA1l00
+)
+;
+assign
+PCLK
+=
+(
+BFMA1IO1
+)
+?
+1
+\'b
+x
+:
+(
+SYSCLK
+|
+BFMA1l00
+)
+;
+assign
+#
+TPD
+HRESETN
+=
+(
+BFMA1lO1
+)
+?
+1
+\'b
+x
+:
+BFMA1Il
+;
+assign
+#
+TPD
+HADDR
+=
+(
+BFMA1OI1
+)
+?
+{
+32
+{
+1
+\'b
+x
+}
+}
+:
+BFMA1l1
+;
+assign
+#
+TPD
+HWDATA
+=
+(
+BFMA1II1
+)
+?
+{
+32
+{
+1
+\'b
+x
+}
+}
+:
+BFMA1lOl
+;
+assign
+#
+TPD
+HBURST
+=
+(
+BFMA1OI1
+)
+?
+{
+3
+{
+1
+\'b
+x
+}
+}
+:
+BFMA1ll
+;
+assign
+#
+TPD
+HMASTLOCK
+=
+(
+BFMA1OI1
+)
+?
+1
+\'b
+x
+:
+BFMA1O0
+;
+assign
+#
+TPD
+HPROT
+=
+(
+BFMA1OI1
+)
+?
+{
+4
+{
+1
+\'b
+x
+}
+}
+:
+BFMA1I0
+;
+assign
+#
+TPD
+HSIZE
+=
+(
+BFMA1OI1
+)
+?
+{
+3
+{
+1
+\'b
+x
+}
+}
+:
+BFMA1IOI
+;
+assign
+#
+TPD
+HTRANS
+=
+(
+BFMA1OI1
+)
+?
+{
+2
+{
+1
+\'b
+x
+}
+}
+:
+BFMA1l0
+;
+assign
+#
+TPD
+HWRITE
+=
+(
+BFMA1OI1
+)
+?
+1
+\'b
+x
+:
+BFMA1O1
+;
+assign
+#
+TPD
+HSEL
+=
+(
+BFMA1OI1
+)
+?
+{
+16
+{
+1
+\'b
+x
+}
+}
+:
+BFMA1OII
+;
+assign
+#
+TPD
+CON_DATA
+=
+(
+BFMA1Il0
+==
+1
+\'b
+1
+)
+?
+BFMA1Ol0
+:
+{
+32
+{
+1
+\'b
+z
+}
+}
+;
+assign
+BFMA1lI0
+=
+CON_DATA
+;
+assign
+#
+TPD
+FINISHED
+=
+BFMA1l10
+;
+assign
+#
+TPD
+FAILED
+=
+BFMA1OO1
+;
+endmodule
+"
+"`timescale 1 ns / 100 ps
+// ********************************************************************/ 
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+//  
+// Description: AMBA BFMs
+//              AHB Lite BFM  
+//
+// Revision Information:
+// Date     Description
+// 01Sep07  Initial Release 
+// 14Sep07  Updated for 1.2 functionality
+// 25Sep07  Updated for 1.3 functionality
+// 09Nov07  Updated for 1.4 functionality
+// 08May08  2.0 for Soft IP Usage
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+//
+// Resolved SARs
+// SAR      Date     Who  Description
+//
+//
+// Notes: 
+// 28Nov07 IPB Updated to increase throughput
+//       
+// *********************************************************************/ 
+module BFM_APB2APB ( PCLK_PM, PRESETN_PM, PADDR_PM, PWRITE_PM, PENABLE_PM, PWDATA_PM, PRDATA_PM, PREADY_PM, PSLVERR_PM,
+                     PCLK_SC, PSEL_SC, PADDR_SC, PWRITE_SC, PENABLE_SC, PWDATA_SC, PRDATA_SC, PREADY_SC, PSLVERR_SC);
+
+    parameter[9:0] TPD  = 1;
+   
+   
+    localparam TPDns  = TPD * 1;
+
+    input PCLK_PM; 
+    input PRESETN_PM; 
+    input[31:0] PADDR_PM; 
+    input PWRITE_PM; 
+    input PENABLE_PM; 
+    input[31:0] PWDATA_PM; 
+    output[31:0] PRDATA_PM; 
+    reg[31:0] PRDATA_PM;
+    output PREADY_PM; 
+    reg PREADY_PM;
+    output PSLVERR_PM; 
+    reg PSLVERR_PM;
+    input PCLK_SC; 
+    output[15:0] PSEL_SC; 
+    wire[15:0] #TPDns PSEL_SC;
+    output[31:0] PADDR_SC; 
+    wire[31:0] #TPDns PADDR_SC;
+    output PWRITE_SC; 
+    wire #TPDns PWRITE_SC;
+    output PENABLE_SC; 
+    wire #TPDns PENABLE_SC;
+    output[31:0] PWDATA_SC; 
+    wire[31:0] #TPDns PWDATA_SC;
+    input[31:0] PRDATA_SC; 
+    input PREADY_SC; 
+    input PSLVERR_SC; 
+
+    parameter[0:0] IDLE = 0; 
+    parameter[0:0] ACTIVE = 1; 
+    reg[0:0] STATE_PM; 
+    parameter[1:0] T0 = 0; 
+    parameter[1:0] T1 = 1; 
+    parameter[1:0] T2 = 2; 
+    reg[1:0] STATE_SC; 
+
+    reg[15:0] PSEL_P0; 
+    reg[31:0] PADDR_P0; 
+    reg PWRITE_P0; 
+    reg PENABLE_P0; 
+    reg[31:0] PWDATA_P0; 
+    reg PSELEN; 
+    reg[31:0] PRDATA_HD; 
+    reg PSLVERR_HD; 
+    reg PENABLE_PM_P0; 
+    reg TRIGGER; 
+    reg DONE; 
+
+    always @(posedge PCLK_PM or negedge PRESETN_PM)
+    begin
+        if (PRESETN_PM == 1'b0)
+        begin
+            STATE_PM <= IDLE ; 
+            TRIGGER <= 1'b0 ; 
+            PREADY_PM <= 1'b0 ; 
+            PSLVERR_PM <= 1'b0 ; 
+            PRDATA_PM <= {32{1'b0}} ; 
+            PENABLE_PM_P0 <= 1'b0 ; 
+        end
+        else
+        begin
+            PREADY_PM <= 1'b0 ; 
+            PENABLE_PM_P0 <= PENABLE_PM ; 
+            case (STATE_PM)
+                IDLE :
+                            begin
+                                if (PENABLE_PM == 1'b1 & PENABLE_PM_P0 == 1'b0)
+                                begin
+                                    TRIGGER <= 1'b1 ; 
+                                    STATE_PM <= ACTIVE ; 
+                                end 
+                            end
+                ACTIVE :
+                            begin
+                                if (DONE == 1'b1)
+                                begin
+                                    STATE_PM <= IDLE ; 
+                                    TRIGGER <= 1'b0 ; 
+                                    PREADY_PM <= 1'b1 ; 
+                                    PSLVERR_PM <= PSLVERR_HD ; 
+                                    PRDATA_PM <= PRDATA_HD ; 
+                                end 
+                            end
+            endcase 
+        end 
+    end 
+
+    always @(posedge PCLK_SC or negedge TRIGGER)
+    begin
+        if (TRIGGER == 1'b0)
+        begin
+            STATE_SC <= T0 ; 
+            DONE <= 1'b0 ; 
+            PRDATA_HD <= {32{1'b0}} ; 
+            PSLVERR_HD <= 1'b0 ; 
+            PSELEN <= 1'b0 ; 
+            PENABLE_P0 <= 1'b0 ; 
+            PADDR_P0 <= {32{1'b0}} ; 
+            PWDATA_P0 <= {32{1'b0}} ; 
+            PWRITE_P0 <= 1'b0 ; 
+        end
+        else
+        begin
+            case (STATE_SC)
+                T0 :
+                            begin
+                                STATE_SC <= T1 ; 
+                                PADDR_P0 <= PADDR_PM ; 
+                                PWDATA_P0 <= PWDATA_PM ; 
+                                PWRITE_P0 <= PWRITE_PM ; 
+                                PSELEN <= 1'b1 ; 
+                                PENABLE_P0 <= 1'b0 ; 
+                                DONE <= 1'b0 ; 
+                            end
+                T1 :
+                            begin
+                                STATE_SC <= T2 ; 
+                                PENABLE_P0 <= 1'b1 ; 
+                            end
+                T2 :
+                            begin
+                                if (PREADY_SC == 1'b1)
+                                begin
+                                    DONE <= 1'b1 ; 
+                                    PRDATA_HD <= PRDATA_SC ; 
+                                    PSLVERR_HD <= PSLVERR_SC ; 
+                                    PSELEN <= 1'b0 ; 
+                                    PENABLE_P0 <= 1'b0 ; 
+                                    PADDR_P0 <= {32{1'b0}} ; 
+                                    PWDATA_P0 <= {32{1'b0}} ; 
+                                    PWRITE_P0 <= 1'b0 ; 
+                                end 
+                            end
+            endcase 
+        end 
+    end 
+
+    always @(PADDR_P0 or PSELEN)
+    begin
+        PSEL_P0 <= {16{1'b0}} ; 
+        if (PSELEN == 1'b1)
+        begin
+            begin : xhdl_5
+                integer i;
+                for(i = 0; i <= 15; i = i + 1)
+                begin
+                    PSEL_P0[i] <= (PADDR_P0[27:24] == i); 
+                end
+            end 
+        end 
+    end 
+
+    assign PSEL_SC    = PSEL_P0 ;
+    assign PADDR_SC   = PADDR_P0 ;
+    assign PWRITE_SC  = PWRITE_P0 ;
+    assign PENABLE_SC = PENABLE_P0 ;
+    assign PWDATA_SC  = PWDATA_P0 ;
+
+
+endmodule
+"
+"module timerWrapper(
+\t\t\t\t\tPCLK,
+\t\t\t\t\tPENABLE,
+\t\t\t\t\tPSEL,
+\t\t\t\t\tPRESETN,
+\t\t\t\t\tPWRITE,
+\t\t\t\t\tPREADY,
+\t\t\t\t\tPSLVERR,
+\t\t\t\t\tPADDR,
+\t\t\t\t\tPWDATA,
+\t\t\t\t\tPRDATA,
+\t\t\t\t\tTPS,
+                    FABINT);
+
+// APB Bus Interface
+input PCLK,PENABLE, PSEL, PRESETN, PWRITE;
+input  [31:0] PWDATA;
+input  [7:0] PADDR;
+output [31:0] PRDATA;
+output PREADY, PSLVERR;
+output FABINT;
+
+
+// Test Interface
+output [4:0] TPS; // Use for your debugging
+
+ 
+assign BUS_WRITE_EN = (PENABLE && PWRITE && PSEL);
+assign BUS_READ_EN = (!PWRITE && PSEL); //Data is ready during first cycle to make it availble on the bus when PENABLE is asserted
+
+assign PREADY = 1'b1;
+assign PSLVERR = 1'b0;
+
+timer timer_0(\t.pclk(PCLK),
+\t\t\t    .nreset(PRESETN), 
+\t\t\t    .bus_write_en(BUS_WRITE_EN),
+\t\t\t    .bus_read_en(BUS_READ_EN),
+\t\t\t    .bus_addr(PADDR),
+\t\t\t    .bus_write_data(PWDATA),
+\t\t\t    .bus_read_data(PRDATA),
+                .fabint(FABINT)
+\t\t\t);
+
+
+endmodule"
+"`timescale 1 ns/100 ps\r
+// Version: 10.1 SP3 10.1.3.1\r
+\r
+\r
+module cc3000fpga_MSS_tmp_MSS_CCC_0_MSS_CCC(\r
+       CLKA,\r
+       CLKA_PAD,\r
+       CLKA_PADP,\r
+       CLKA_PADN,\r
+       CLKB,\r
+       CLKB_PAD,\r
+       CLKB_PADP,\r
+       CLKB_PADN,\r
+       CLKC,\r
+       CLKC_PAD,\r
+       CLKC_PADP,\r
+       CLKC_PADN,\r
+       MAINXIN,\r
+       LPXIN,\r
+       MAC_CLK,\r
+       GLA0,\r
+       GLA,\r
+       FAB_CLK,\r
+       FAB_LOCK,\r
+       MSS_LOCK,\r
+       GLB,\r
+       YB,\r
+       GLC,\r
+       YC,\r
+       MAC_CLK_CCC,\r
+       MAC_CLK_IO,\r
+       RCOSC_CLKOUT,\r
+       MAINXIN_CLKOUT,\r
+       LPXIN_CLKOUT\r
+    );\r
+input  CLKA;\r
+input  CLKA_PAD;\r
+input  CLKA_PADP;\r
+input  CLKA_PADN;\r
+input  CLKB;\r
+input  CLKB_PAD;\r
+input  CLKB_PADP;\r
+input  CLKB_PADN;\r
+input  CLKC;\r
+input  CLKC_PAD;\r
+input  CLKC_PADP;\r
+input  CLKC_PADN;\r
+input  MAINXIN;\r
+input  LPXIN;\r
+input  MAC_CLK;\r
+output GLA0;\r
+output GLA;\r
+output FAB_CLK;\r
+output FAB_LOCK;\r
+output MSS_LOCK;\r
+output GLB;\r
+output YB;\r
+output GLC;\r
+output YC;\r
+output MAC_CLK_CCC;\r
+output MAC_CLK_IO;\r
+output RCOSC_CLKOUT;\r
+output MAINXIN_CLKOUT;\r
+output LPXIN_CLKOUT;\r
+\r
+    wire N_CLKA_RCOSC, N_GND, N_VCC;\r
+    wire GND_power_net1;\r
+    wire VCC_power_net1;\r
+    assign GLA = N_GND;\r
+    assign FAB_LOCK = N_GND;\r
+    assign MSS_LOCK = N_GND;\r
+    assign GLB = N_GND;\r
+    assign YB = N_GND;\r
+    assign GLC = N_GND;\r
+    assign YC = N_GND;\r
+    assign MAC_CLK_CCC = N_GND;\r
+    assign MAC_CLK_IO = N_GND;\r
+    assign N_GND = GND_power_net1;\r
+    assign N_VCC = VCC_power_net1;\r
+    \r
+    MSS_CCC #( .VCOFREQUENCY(-1.000) )  I_MSSCCC (.CLKA(N_CLKA_RCOSC), \r
+        .EXTFB(N_GND), .GLA(FAB_CLK), .GLAMSS(GLA0), .LOCK(), .LOCKMSS(\r
+        ), .CLKB(N_GND), .GLB(), .YB(), .CLKC(N_GND), .GLC(), .YC(), \r
+        .MACCLK(), .OADIV({N_GND, N_GND, N_GND, N_GND, N_GND}), \r
+        .OADIVHALF(N_GND), .OAMUX({N_GND, N_GND, N_GND}), .BYPASSA(\r
+        N_VCC), .DLYGLA({N_GND, N_GND, N_GND, N_GND, N_GND}), \r
+        .DLYGLAMSS({N_GND, N_GND, N_GND, N_GND, N_GND}), .DLYGLAFAB({\r
+        N_GND, N_GND, N_GND, N_GND, N_GND}), .OBDIV({N_GND, N_GND, \r
+        N_GND, N_VCC, N_VCC}), .OBDIVHALF(N_GND), .OBMUX({N_GND, N_GND, \r
+        N_GND}), .BYPASSB(N_VCC), .DLYGLB({N_GND, N_GND, N_GND, N_GND, \r
+        N_GND}), .OCDIV({N_GND, N_GND, N_GND, N_VCC, N_VCC}), \r
+        .OCDIVHALF(N_GND), .OCMUX({N_GND, N_GND, N_GND}), .BYPASSC(\r
+        N_VCC), .DLYGLC({N_GND, N_GND, N_GND, N_GND, N_GND}), .FINDIV({\r
+        N_GND, N_GND, N_GND, N_GND, N_VCC, N_VCC, N_GND}), .FBDIV({\r
+        N_GND, N_GND, N_GND, N_GND, N_VCC, N_VCC, N_GND}), .FBDLY({\r
+        N_GND, N_GND, N_GND, N_GND, N_VCC}), .FBSEL({N_GND, N_VCC}), \r
+        .XDLYSEL(N_GND), .GLMUXSEL({N_GND, N_GND}), .GLMUXCFG({N_GND, \r
+        N_GND}));\r
+    RCOSC I_RCOSC (.CLKOUT(N_CLKA_RCOSC));\r
+    GND GND_power_inst1 (.Y(GND_power_net1));\r
+    VCC VCC_power_inst1 (.Y(VCC_power_net1));\r
+    \r
+endmodule\r
+"
+"`timescale 1ns/100ps
+// Actel Corporation Proprietary and Confidential
+// Copyright 2008 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+// Revision Information:
+// SVN Revision Information:
+// SVN $Revision: 11864 $
+// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
+module
+BFMA1l1OII
+(
+HCLK
+,
+HRESETN
+,
+HSEL
+,
+HWRITE
+,
+HADDR
+,
+HWDATA
+,
+HRDATA
+,
+HREADYIN
+,
+HREADYOUT
+,
+HTRANS
+,
+HSIZE
+,
+HBURST
+,
+HMASTLOCK
+,
+HPROT
+,
+HRESP
+,
+PSEL
+,
+PADDR
+,
+PWRITE
+,
+PENABLE
+,
+PWDATA
+,
+PRDATA
+,
+PREADY
+,
+PSLVERR
+)
+;
+parameter
+TPD
+=
+1
+;
+input
+HCLK
+;
+input
+HRESETN
+;
+input
+HSEL
+;
+input
+HWRITE
+;
+input
+[
+31
+:
+0
+]
+HADDR
+;
+input
+[
+31
+:
+0
+]
+HWDATA
+;
+output
+[
+31
+:
+0
+]
+HRDATA
+;
+wire
+[
+31
+:
+0
+]
+HRDATA
+;
+input
+HREADYIN
+;
+output
+HREADYOUT
+;
+wire
+HREADYOUT
+;
+input
+[
+1
+:
+0
+]
+HTRANS
+;
+input
+[
+2
+:
+0
+]
+HSIZE
+;
+input
+[
+2
+:
+0
+]
+HBURST
+;
+input
+HMASTLOCK
+;
+input
+[
+3
+:
+0
+]
+HPROT
+;
+output
+HRESP
+;
+wire
+HRESP
+;
+output
+[
+15
+:
+0
+]
+PSEL
+;
+wire
+[
+15
+:
+0
+]
+PSEL
+;
+output
+[
+31
+:
+0
+]
+PADDR
+;
+wire
+[
+31
+:
+0
+]
+PADDR
+;
+output
+PWRITE
+;
+wire
+PWRITE
+;
+output
+PENABLE
+;
+wire
+PENABLE
+;
+output
+[
+31
+:
+0
+]
+PWDATA
+;
+wire
+[
+31
+:
+0
+]
+PWDATA
+;
+input
+[
+31
+:
+0
+]
+PRDATA
+;
+input
+PREADY
+;
+input
+PSLVERR
+;
+parameter
+[
+1
+:
+0
+]
+BFMA1OOIII
+=
+0
+;
+parameter
+[
+1
+:
+0
+]
+BFMA1IOIII
+=
+1
+;
+parameter
+[
+1
+:
+0
+]
+BFMA1lOIII
+=
+2
+;
+parameter
+[
+1
+:
+0
+]
+BFMA1OIIII
+=
+3
+;
+reg
+[
+1
+:
+0
+]
+BFMA1IIIII
+;
+reg
+BFMA1lIIII
+;
+reg
+BFMA1OlIII
+;
+reg
+[
+15
+:
+0
+]
+BFMA1IlIII
+;
+reg
+[
+31
+:
+0
+]
+BFMA1llIII
+;
+reg
+BFMA1O0III
+;
+reg
+BFMA1I0III
+;
+reg
+[
+31
+:
+0
+]
+BFMA1l0III
+;
+wire
+[
+31
+:
+0
+]
+BFMA1O1III
+;
+reg
+BFMA1I1III
+;
+reg
+BFMA1l1III
+;
+always
+@
+(
+posedge
+HCLK
+or
+negedge
+HRESETN
+)
+begin
+if
+(
+HRESETN
+==
+1
+'b
+0
+)
+begin
+BFMA1IIIII
+<=
+BFMA1OOIII
+;
+BFMA1lIIII
+<=
+1
+'b
+1
+;
+BFMA1llIII
+<=
+{
+32
+{
+1
+'b
+0
+}
+}
+;
+BFMA1l0III
+<=
+{
+32
+{
+1
+'b
+0
+}
+}
+;
+BFMA1O0III
+<=
+1
+'b
+0
+;
+BFMA1I0III
+<=
+1
+'b
+0
+;
+BFMA1OlIII
+<=
+1
+'b
+0
+;
+BFMA1I1III
+<=
+1
+'b
+0
+;
+BFMA1l1III
+<=
+1
+'b
+0
+;
+end
+else
+begin
+BFMA1OlIII
+<=
+1
+'b
+0
+;
+BFMA1lIIII
+<=
+1
+'b
+0
+;
+BFMA1I1III
+<=
+1
+'b
+0
+;
+case
+(
+BFMA1IIIII
+)
+BFMA1OOIII
+:
+begin
+if
+(
+HSEL
+==
+1
+'b
+1
+&
+HREADYIN
+==
+1
+'b
+1
+&
+(
+HTRANS
+[
+1
+]
+)
+==
+1
+'b
+1
+)
+begin
+BFMA1IIIII
+<=
+BFMA1IOIII
+;
+BFMA1llIII
+<=
+HADDR
+;
+BFMA1O0III
+<=
+HWRITE
+;
+BFMA1l0III
+<=
+HWDATA
+;
+BFMA1I0III
+<=
+1
+'b
+0
+;
+BFMA1I1III
+<=
+HWRITE
+;
+BFMA1l1III
+<=
+1
+'b
+1
+;
+end
+else
+begin
+BFMA1lIIII
+<=
+1
+'b
+1
+;
+end
+end
+BFMA1IOIII
+:
+begin
+BFMA1I0III
+<=
+1
+'b
+1
+;
+BFMA1IIIII
+<=
+BFMA1lOIII
+;
+end
+BFMA1lOIII
+:
+begin
+if
+(
+PREADY
+==
+1
+'b
+1
+)
+begin
+BFMA1I0III
+<=
+1
+'b
+0
+;
+BFMA1l1III
+<=
+1
+'b
+0
+;
+if
+(
+PSLVERR
+==
+1
+'b
+0
+)
+begin
+BFMA1IIIII
+<=
+BFMA1OOIII
+;
+if
+(
+HSEL
+==
+1
+'b
+1
+&
+HREADYIN
+==
+1
+'b
+1
+&
+(
+HTRANS
+[
+1
+]
+)
+==
+1
+'b
+1
+)
+begin
+BFMA1IIIII
+<=
+BFMA1IOIII
+;
+BFMA1llIII
+<=
+HADDR
+;
+BFMA1O0III
+<=
+HWRITE
+;
+BFMA1I1III
+<=
+HWRITE
+;
+BFMA1l1III
+<=
+1
+'b
+1
+;
+end
+end
+else
+begin
+BFMA1OlIII
+<=
+1
+'b
+1
+;
+BFMA1IIIII
+<=
+BFMA1OIIII
+;
+end
+end
+end
+BFMA1OIIII
+:
+begin
+BFMA1OlIII
+<=
+1
+'b
+1
+;
+BFMA1lIIII
+<=
+1
+'b
+1
+;
+BFMA1IIIII
+<=
+BFMA1OOIII
+;
+end
+endcase
+if
+(
+BFMA1I1III
+==
+1
+'b
+1
+)
+begin
+BFMA1l0III
+<=
+HWDATA
+;
+end
+end
+end
+always
+@
+(
+BFMA1llIII
+or
+BFMA1l1III
+)
+begin
+BFMA1IlIII
+<=
+{
+16
+{
+1
+'b
+0
+}
+}
+;
+if
+(
+BFMA1l1III
+==
+1
+'b
+1
+)
+begin
+begin
+:
+BFMA1IO10
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+15
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1IlIII
+[
+BFMA1I0I0
+]
+<=
+(
+BFMA1llIII
+[
+27
+:
+24
+]
+==
+BFMA1I0I0
+)
+;
+end
+end
+end
+end
+assign
+BFMA1O1III
+=
+(
+BFMA1I1III
+==
+1
+'b
+1
+)
+?
+HWDATA
+:
+BFMA1l0III
+;
+assign
+#
+TPD
+HRDATA
+=
+PRDATA
+;
+assign
+#
+TPD
+HREADYOUT
+=
+BFMA1lIIII
+|
+(
+PREADY
+&
+BFMA1l1III
+&
+BFMA1I0III
+&
+~
+PSLVERR
+)
+;
+assign
+#
+TPD
+HRESP
+=
+BFMA1OlIII
+;
+assign
+#
+TPD
+PSEL
+=
+BFMA1IlIII
+;
+assign
+#
+TPD
+PADDR
+=
+BFMA1llIII
+;
+assign
+#
+TPD
+PWRITE
+=
+BFMA1O0III
+;
+assign
+#
+TPD
+PENABLE
+=
+BFMA1I0III
+;
+assign
+#
+TPD
+PWDATA
+=
+BFMA1O1III
+;
+endmodule
+"
+"module MSS_APB
+    (
+    ABPS0,
+    ABPS1,
+    ABPS10,
+    ABPS11,
+    ABPS2,
+    ABPS3,
+    ABPS4,
+    ABPS5,
+    ABPS6,
+    ABPS7,
+    ABPS8,
+    ABPS9,
+    ACEFLAGS,
+    ADC0,
+    ADC1,
+    ADC10,
+    ADC11,
+    ADC2,
+    ADC3,
+    ADC4,
+    ADC5,
+    ADC6,
+    ADC7,
+    ADC8,
+    ADC9,
+    CALIBIN,
+    CALIBOUT,
+    CM0,
+    CM1,
+    CM2,
+    CM3,
+    CM4,
+    CM5,
+    CMP0,
+    CMP1,
+    CMP10,
+    CMP11,
+    CMP2,
+    CMP3,
+    CMP4,
+    CMP5,
+    CMP6,
+    CMP7,
+    CMP8,
+    CMP9,
+    DEEPSLEEP,
+    DMAREADY,
+    EMCAB,
+    EMCBYTEN,
+    EMCCLK,
+    EMCCLKRTN,
+    EMCCS0n,
+    EMCCS1n,
+    EMCDBOE,
+    EMCOEN0n,
+    EMCOEN1n,
+    EMCRDB,
+    EMCRWn,
+    EMCWDB,
+    F2MRESETn,
+    FABACETRIG,
+    FABINT,
+    FABPADDR,
+    FABPENABLE,
+    FABPRDATA,
+    FABPREADY,
+    FABPSEL,
+    FABPSLVERR,
+    FABPWDATA,
+    FABPWRITE,
+    FABSDD0CLK,
+    FABSDD0D,
+    FABSDD1CLK,
+    FABSDD1D,
+    FABSDD2CLK,
+    FABSDD2D,
+    FCLK,
+    GNDTM0,
+    GNDTM1,
+    GNDTM2,
+    GNDVAREF,
+    GPI,
+    GPO,
+    GPOE,
+    I2C0BCLK,
+    I2C0SCLI,
+    I2C0SCLO,
+    I2C0SDAI,
+    I2C0SDAO,
+    I2C0SMBALERTNI,
+    I2C0SMBALERTNO,
+    I2C0SMBUSNI,
+    I2C0SMBUSNO,
+    I2C1BCLK,
+    I2C1SCLI,
+    I2C1SCLO,
+    I2C1SDAI,
+    I2C1SDAO,
+    I2C1SMBALERTNI,
+    I2C1SMBALERTNO,
+    I2C1SMBUSNI,
+    I2C1SMBUSNO,
+    LVTTL0,
+    LVTTL0EN,
+    LVTTL1,
+    LVTTL10,
+    LVTTL10EN,
+    LVTTL11,
+    LVTTL11EN,
+    LVTTL1EN,
+    LVTTL2,
+    LVTTL2EN,
+    LVTTL3,
+    LVTTL3EN,
+    LVTTL4,
+    LVTTL4EN,
+    LVTTL5,
+    LVTTL5EN,
+    LVTTL6,
+    LVTTL6EN,
+    LVTTL7,
+    LVTTL7EN,
+    LVTTL8,
+    LVTTL8EN,
+    LVTTL9,
+    LVTTL9EN,
+    M2FRESETn,
+    MACCLK,
+    MACCLKCCC,
+    MACCRSDV,
+    MACF2MCRSDV,
+    MACF2MMDI,
+    MACF2MRXD,
+    MACF2MRXER,
+    MACM2FMDC,
+    MACM2FMDEN,
+    MACM2FMDO,
+    MACM2FTXD,
+    MACM2FTXEN,
+    MACMDC,
+    MACMDEN,
+    MACMDI,
+    MACMDO,
+    MACRXD,
+    MACRXER,
+    MACTXD,
+    MACTXEN,
+    MSSINT,
+    MSSPADDR,
+    MSSPENABLE,
+    MSSPRDATA,
+    MSSPREADY,
+    MSSPSEL,
+    MSSPSLVERR,
+    MSSPWDATA,
+    MSSPWRITE,
+    MSSRESETn,
+    PLLLOCK,
+    PUFABn,
+    PUn,
+    RCOSC,
+    RXEV,
+    SDD0,
+    SDD1,
+    SDD2,
+    SLEEP,
+    SPI0CLKI,
+    SPI0CLKO,
+    SPI0DI,
+    SPI0DO,
+    SPI0DOE,
+    SPI0MODE,
+    SPI0SSI,
+    SPI0SSO,
+    SPI1CLKI,
+    SPI1CLKO,
+    SPI1DI,
+    SPI1DO,
+    SPI1DOE,
+    SPI1MODE,
+    SPI1SSI,
+    SPI1SSO,
+    SYNCCLKFDBK,
+    TM0,
+    TM1,
+    TM2,
+    TM3,
+    TM4,
+    TM5,
+    TXEV,
+    UART0CTSn,
+    UART0DCDn,
+    UART0DSRn,
+    UART0DTRn,
+    UART0RIn,
+    UART0RTSn,
+    UART0RXD,
+    UART0TXD,
+    UART1CTSn,
+    UART1DCDn,
+    UART1DSRn,
+    UART1DTRn,
+    UART1RIn,
+    UART1RTSn,
+    UART1RXD,
+    UART1TXD,
+    VAREF0,
+    VAREF1,
+    VAREF2,
+    VAREFOUT,
+    VCC15GOOD,
+    VCC33GOOD,
+    VRON,
+    WDINT
+    );
+
+    /*
+    synthesis syn_black_box
+    syn_tco1=""FCLK->ACEFLAGS[31:0]=5.641""
+    syn_tco2=""FCLK->DEEPSLEEP=3.492""
+    syn_tsu1=""DMAREADY[1:0]->FCLK=1.468""
+    syn_tco3=""FCLK->EMCAB[25:0]=2.672""
+    syn_tco4=""FCLK->EMCBYTEN[1:0]=4.324""
+    syn_tco5=""FCLK->EMCCS0n=4.522""
+    syn_tco6=""FCLK->EMCCS1n=4.554""
+    syn_tco7=""FCLK->EMCDBOE=2.672""
+    syn_tco8=""FCLK->EMCOEN0n=4.303""
+    syn_tco9=""FCLK->EMCOEN1n=4.314""
+    syn_tsu2=""EMCRDB[15:0]->EMCCLKRTN=0.003""
+    syn_tco10=""FCLK->EMCRWn=2.924""
+    syn_tco11=""FCLK->EMCWDB[15:0]=6.91""
+    syn_tsu3=""FABACETRIG->FCLK=0""
+    syn_tsu4=""FABINT->FCLK=0.321""
+    syn_tsu5=""FABPADDR[31:0]->FCLK=0""
+    syn_tsu6=""FABPENABLE->FCLK=0""
+    syn_tco12=""FCLK->FABPRDATA[31:0]=3.926""
+    syn_tco13=""FCLK->FABPREADY=2.712""
+    syn_tsu7=""FABPSEL->FCLK=0""
+    syn_tco14=""FCLK->FABPSLVERR=2.859""
+    syn_tsu8=""FABPWDATA[31:0]->FCLK=0""
+    syn_tsu9=""FABPWRITE->FCLK=0""
+    syn_tsu10=""GPI[31:0]->FCLK=0.516""
+    syn_tco15=""FCLK->GPO[31:0]=4.132""
+    syn_tco16=""FCLK->GPOE[31:0]=3.908""
+    syn_tsu11=""I2C0BCLK->FCLK=0""
+    syn_tsu12=""I2C0SCLI->FCLK=0""
+    syn_tco17=""FCLK->I2C0SCLO=3.465""
+    syn_tsu13=""I2C0SDAI->FCLK=0""
+    syn_tco18=""FCLK->I2C0SDAO=3.368""
+    syn_tsu14=""I2C0SMBALERTNI->FCLK=0""
+    syn_tco19=""FCLK->I2C0SMBALERTNO=2.855""
+    syn_tsu15=""I2C0SMBUSNI->FCLK=0""
+    syn_tco20=""FCLK->I2C0SMBUSNO=2.916""
+    syn_tsu16=""I2C1BCLK->FCLK=0""
+    syn_tsu17=""I2C1SCLI->FCLK=0""
+    syn_tco21=""FCLK->I2C1SCLO=3.762""
+    syn_tsu18=""I2C1SDAI->FCLK=0.045""
+    syn_tco22=""FCLK->I2C1SDAO=3.712""
+    syn_tsu19=""I2C1SMBALERTNI->FCLK=0""
+    syn_tco23=""FCLK->I2C1SMBALERTNO=2.5""
+    syn_tsu20=""I2C1SMBUSNI->FCLK=0""
+    syn_tco24=""FCLK->I2C1SMBUSNO=2.501""
+    syn_tco25=""FCLK->M2FRESETn=2.957""
+    syn_tsu21=""MACCRSDV->MACCLK=0""
+    syn_tsu22=""MACCRSDV->MACCLKCCC=0""
+    syn_tsu23=""MACF2MCRSDV->MACCLK=0""
+    syn_tsu24=""MACF2MCRSDV->MACCLKCCC=0""
+    syn_tsu25=""MACF2MMDI->FCLK=0""
+    syn_tsu26=""MACF2MRXD[1:0]->MACCLK=0""
+    syn_tsu27=""MACF2MRXD[1:0]->MACCLKCCC=0""
+    syn_tsu28=""MACF2MRXER->MACCLK=0""
+    syn_tsu29=""MACF2MRXER->MACCLKCCC=0""
+    syn_tco26=""FCLK->MACM2FMDC=3.861""
+    syn_tco27=""FCLK->MACM2FMDEN=4.061""
+    syn_tco28=""FCLK->MACM2FMDO=4.261""
+    syn_tco29=""FCLK->MACM2FTXD[1:0]=3.912""
+    syn_tco30=""MACCLK->MACM2FTXD[1:0]=2.855""
+    syn_tco31=""FCLK->MACM2FTXEN=4.167""
+    syn_tco32=""MACCLK->MACM2FTXEN=2.843""
+    syn_tco33=""FCLK->MACMDC=3.198""
+    syn_tco34=""FCLK->MACMDEN=3.664""
+    syn_tsu30=""MACMDI->FCLK=0""
+    syn_tco35=""FCLK->MACMDO=3.524""
+    syn_tsu31=""MACRXD[1:0]->MACCLK=0""
+    syn_tsu32=""MACRXD[1:0]->MACCLKCCC=0""
+    syn_tsu33=""MACRXER->MACCLK=0""
+    syn_tsu34=""MACRXER->MACCLKCCC=0""
+    syn_tco36=""FCLK->MACTXD[1:0]=3.24""
+    syn_tco37=""MACCLK->MACTXD[1:0]=2.596""
+    syn_tco38=""FCLK->MACTXEN=3.601""
+    syn_tco39=""MACCLK->MACTXEN=2.745""
+    syn_tco40=""FCLK->MSSINT[7:0]=5.637""
+    syn_tco41=""FCLK->MSSPADDR[19:0]=2.679""
+    syn_tco42=""FCLK->MSSPENABLE=2.474""
+    syn_tsu35=""MSSPRDATA[31:0]->FCLK=0""
+    syn_tsu36=""MSSPREADY->FCLK=0""
+    syn_tco43=""FCLK->MSSPSEL=2.49""
+    syn_tsu37=""MSSPSLVERR->FCLK=0""
+    syn_tco44=""FCLK->MSSPWDATA[31:0]=2.71""
+    syn_tco45=""FCLK->MSSPWRITE=2.456""
+    syn_tsu38=""MSSRESETn->FCLK=0""
+    syn_tsu39=""PUn->FCLK=0""
+    syn_tsu40=""RXEV->FCLK=0""
+    syn_tco46=""FCLK->SLEEP=3.304""
+    syn_tsu41=""SPI0CLKI->FCLK=0""
+    syn_tco47=""FCLK->SPI0CLKO=3.407""
+    syn_tsu42=""SPI0DI->FCLK=0""
+    syn_tco48=""FCLK->SPI0DO=4.35""
+    syn_tco49=""FCLK->SPI0DOE=4.947""
+    syn_tco50=""FCLK->SPI0MODE=3.423""
+    syn_tsu43=""SPI0SSI->FCLK=0.858""
+    syn_tco51=""FCLK->SPI0SSO[7:0]=4.117""
+    syn_tsu44=""SPI1CLKI->FCLK=0""
+    syn_tco52=""FCLK->SPI1CLKO=3.548""
+    syn_tsu45=""SPI1DI->FCLK=0""
+    syn_tco53=""FCLK->SPI1DO=4.643""
+    syn_tco54=""FCLK->SPI1DOE=4.318""
+    syn_tco55=""FCLK->SPI1MODE=4.136""
+    syn_tsu46=""SPI1SSI->FCLK=0.271""
+    syn_tco56=""FCLK->SPI1SSO[7:0]=4.904""
+    syn_tco57=""FCLK->TXEV=4.597""
+    syn_tsu47=""UART0CTSn->FCLK=0""
+    syn_tsu48=""UART0DCDn->FCLK=0""
+    syn_tsu49=""UART0DSRn->FCLK=0""
+    syn_tco58=""FCLK->UART0DTRn=3.299""
+    syn_tsu50=""UART0RIn->FCLK=0""
+    syn_tco59=""FCLK->UART0RTSn=3.349""
+    syn_tsu51=""UART0RXD->FCLK=0.076""
+    syn_tco60=""FCLK->UART0TXD=3.571""
+    syn_tsu52=""UART1CTSn->FCLK=0""
+    syn_tsu53=""UART1DCDn->FCLK=0""
+    syn_tsu54=""UART1DSRn->FCLK=0""
+    syn_tco61=""FCLK->UART1DTRn=3.407""
+    syn_tsu55=""UART1RIn->FCLK=0""
+    syn_tco62=""FCLK->UART1RTSn=3.714""
+    syn_tsu56=""UART1RXD->FCLK=0""
+    syn_tco63=""FCLK->UART1TXD=3.585""
+    syn_tco64=""FCLK->WDINT=2.749""
+    */
+
+    input ABPS0;
+    input ABPS1;
+    input ABPS10;
+    input ABPS11;
+    input ABPS2;
+    input ABPS3;
+    input ABPS4;
+    input ABPS5;
+    input ABPS6;
+    input ABPS7;
+    input ABPS8;
+    input ABPS9;
+    output [31:0]ACEFLAGS;
+    input ADC0;
+    input ADC1;
+    input ADC10;
+    input ADC11;
+    input ADC2;
+    input ADC3;
+    input ADC4;
+    input ADC5;
+    input ADC6;
+    input ADC7;
+    input ADC8;
+    input ADC9;
+    input CALIBIN;
+    output CALIBOUT;
+    input CM0;
+    input CM1;
+    input CM2;
+    input CM3;
+    input CM4;
+    input CM5;
+    output CMP0;
+    output CMP1;
+    output CMP10;
+    output CMP11;
+    output CMP2;
+    output CMP3;
+    output CMP4;
+    output CMP5;
+    output CMP6;
+    output CMP7;
+    output CMP8;
+    output CMP9;
+    output DEEPSLEEP;
+    input [1:0]DMAREADY;
+    output [25:0]EMCAB;
+    output [1:0]EMCBYTEN;
+    output EMCCLK;
+    input EMCCLKRTN;
+    output EMCCS0n;
+    output EMCCS1n;
+    output EMCDBOE;
+    output EMCOEN0n;
+    output EMCOEN1n;
+    input [15:0]EMCRDB;
+    output EMCRWn;
+    output [15:0]EMCWDB;
+    input F2MRESETn;
+    input FABACETRIG;
+    input FABINT;
+    input [31:0]FABPADDR;
+    input FABPENABLE;
+    output [31:0]FABPRDATA;
+    output FABPREADY;
+    input FABPSEL;
+    output FABPSLVERR;
+    input [31:0]FABPWDATA;
+    input FABPWRITE;
+    input FABSDD0CLK;
+    input FABSDD0D;
+    input FABSDD1CLK;
+    input FABSDD1D;
+    input FABSDD2CLK;
+    input FABSDD2D;
+    input FCLK;
+    input GNDTM0;
+    input GNDTM1;
+    input GNDTM2;
+    input GNDVAREF;
+    input [31:0]GPI;
+    output [31:0]GPO;
+    output [31:0]GPOE;
+    input I2C0BCLK;
+    input I2C0SCLI;
+    output I2C0SCLO;
+    input I2C0SDAI;
+    output I2C0SDAO;
+    input I2C0SMBALERTNI;
+    output I2C0SMBALERTNO;
+    input I2C0SMBUSNI;
+    output I2C0SMBUSNO;
+    input I2C1BCLK;
+    input I2C1SCLI;
+    output I2C1SCLO;
+    input I2C1SDAI;
+    output I2C1SDAO;
+    input I2C1SMBALERTNI;
+    output I2C1SMBALERTNO;
+    input I2C1SMBUSNI;
+    output I2C1SMBUSNO;
+    output LVTTL0;
+    input LVTTL0EN;
+    output LVTTL1;
+    output LVTTL10;
+    input LVTTL10EN;
+    output LVTTL11;
+    input LVTTL11EN;
+    input LVTTL1EN;
+    output LVTTL2;
+    input LVTTL2EN;
+    output LVTTL3;
+    input LVTTL3EN;
+    output LVTTL4;
+    input LVTTL4EN;
+    output LVTTL5;
+    input LVTTL5EN;
+    output LVTTL6;
+    input LVTTL6EN;
+    output LVTTL7;
+    input LVTTL7EN;
+    output LVTTL8;
+    input LVTTL8EN;
+    output LVTTL9;
+    input LVTTL9EN;
+    output M2FRESETn;
+    input MACCLK;
+    input MACCLKCCC;
+    input MACCRSDV;
+    input MACF2MCRSDV;
+    input MACF2MMDI;
+    input [1:0]MACF2MRXD;
+    input MACF2MRXER;
+    output MACM2FMDC;
+    output MACM2FMDEN;
+    output MACM2FMDO;
+    output [1:0]MACM2FTXD;
+    output MACM2FTXEN;
+    output MACMDC;
+    output MACMDEN;
+    input MACMDI;
+    output MACMDO;
+    input [1:0]MACRXD;
+    input MACRXER;
+    output [1:0]MACTXD;
+    output MACTXEN;
+    output [7:0]MSSINT;
+    output [19:0]MSSPADDR;
+    output MSSPENABLE;
+    input [31:0]MSSPRDATA;
+    input MSSPREADY;
+    output MSSPSEL;
+    input MSSPSLVERR;
+    output [31:0]MSSPWDATA;
+    output MSSPWRITE;
+    input MSSRESETn;
+    input PLLLOCK;
+    output PUFABn;
+    input PUn;
+    input RCOSC;
+    input RXEV;
+    output SDD0;
+    output SDD1;
+    output SDD2;
+    output SLEEP;
+    input SPI0CLKI;
+    output SPI0CLKO;
+    input SPI0DI;
+    output SPI0DO;
+    output SPI0DOE;
+    output SPI0MODE;
+    input SPI0SSI;
+    output [7:0]SPI0SSO;
+    input SPI1CLKI;
+    output SPI1CLKO;
+    input SPI1DI;
+    output SPI1DO;
+    output SPI1DOE;
+    output SPI1MODE;
+    input SPI1SSI;
+    output [7:0]SPI1SSO;
+    input SYNCCLKFDBK;
+    input TM0;
+    input TM1;
+    input TM2;
+    input TM3;
+    input TM4;
+    input TM5;
+    output TXEV;
+    input UART0CTSn;
+    input UART0DCDn;
+    input UART0DSRn;
+    output UART0DTRn;
+    input UART0RIn;
+    output UART0RTSn;
+    input UART0RXD;
+    output UART0TXD;
+    input UART1CTSn;
+    input UART1DCDn;
+    input UART1DSRn;
+    output UART1DTRn;
+    input UART1RIn;
+    output UART1RTSn;
+    input UART1RXD;
+    output UART1TXD;
+    input VAREF0;
+    input VAREF1;
+    input VAREF2;
+    output VAREFOUT;
+    output VCC15GOOD;
+    output VCC33GOOD;
+    input VRON;
+    output WDINT;
+
+    parameter ACT_CONFIG = 1\'b0;
+    parameter ACT_FCLK   = 0;
+    parameter ACT_DIE    = """";
+    parameter ACT_PKG    = """";
+
+endmodule
+"
+"// Actel Corporation Proprietary and Confidential
+// Copyright 2008 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+// Revision Information:
+// SVN Revision Information:
+// SVN $Revision: 11864 $
+// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
+`timescale 1ns/100ps
+module
+BFM_APBSLAVEEXT
+(
+PCLK
+,
+PRESETN
+,
+PENABLE
+,
+PWRITE
+,
+PSEL
+,
+PADDR
+,
+PWDATA
+,
+PRDATA
+,
+PREADY
+,
+PSLVERR
+,
+EXT_EN
+,
+EXT_WR
+,
+EXT_RD
+,
+EXT_ADDR
+,
+EXT_DATA
+)
+;
+parameter
+AWIDTH
+=
+10
+;
+parameter
+DEPTH
+=
+256
+;
+parameter
+DWIDTH
+=
+32
+;
+parameter
+EXT_SIZE
+=
+2
+;
+parameter
+INITFILE
+=
+"" ""
+;
+parameter
+ID
+=
+0
+;
+parameter
+TPD
+=
+1
+;
+parameter
+ENFUNC
+=
+0
+;
+parameter
+DEBUG
+=
+0
+;
+// Actel Corporation Proprietary and Confidential
+// Copyright 2008 Actel Corporation.  All rights reserved.
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
+// IN ADVANCE IN WRITING.  
+// Revision Information:
+// SVN Revision Information:
+// SVN $Revision: 11864 $
+// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
+localparam
+BFMA1I11
+=
+22
+;
+localparam
+BFMA1l11
+=
+0
+;
+localparam
+BFMA1OOOI
+=
+4
+;
+localparam
+BFMA1IOOI
+=
+8
+;
+localparam
+BFMA1lOOI
+=
+12
+;
+localparam
+BFMA1OIOI
+=
+16
+;
+localparam
+BFMA1IIOI
+=
+20
+;
+localparam
+BFMA1lIOI
+=
+24
+;
+localparam
+BFMA1OlOI
+=
+28
+;
+localparam
+BFMA1IlOI
+=
+32
+;
+localparam
+BFMA1llOI
+=
+36
+;
+localparam
+BFMA1O0OI
+=
+40
+;
+localparam
+BFMA1I0OI
+=
+44
+;
+localparam
+BFMA1l0OI
+=
+48
+;
+localparam
+BFMA1O1OI
+=
+52
+;
+localparam
+BFMA1I1OI
+=
+56
+;
+localparam
+BFMA1l1OI
+=
+60
+;
+localparam
+BFMA1OOII
+=
+64
+;
+localparam
+BFMA1IOII
+=
+68
+;
+localparam
+BFMA1lOII
+=
+72
+;
+localparam
+BFMA1OIII
+=
+76
+;
+localparam
+BFMA1IIII
+=
+80
+;
+localparam
+BFMA1lIII
+=
+100
+;
+localparam
+BFMA1OlII
+=
+101
+;
+localparam
+BFMA1IlII
+=
+102
+;
+localparam
+BFMA1llII
+=
+103
+;
+localparam
+BFMA1O0II
+=
+104
+;
+localparam
+BFMA1I0II
+=
+105
+;
+localparam
+BFMA1l0II
+=
+106
+;
+localparam
+BFMA1O1II
+=
+107
+;
+localparam
+BFMA1I1II
+=
+108
+;
+localparam
+BFMA1l1II
+=
+109
+;
+localparam
+BFMA1OOlI
+=
+110
+;
+localparam
+BFMA1IOlI
+=
+111
+;
+localparam
+BFMA1lOlI
+=
+112
+;
+localparam
+BFMA1OIlI
+=
+113
+;
+localparam
+BFMA1IIlI
+=
+114
+;
+localparam
+BFMA1lIlI
+=
+115
+;
+localparam
+BFMA1OllI
+=
+128
+;
+localparam
+BFMA1IllI
+=
+129
+;
+localparam
+BFMA1lllI
+=
+130
+;
+localparam
+BFMA1O0lI
+=
+131
+;
+localparam
+BFMA1I0lI
+=
+132
+;
+localparam
+BFMA1l0lI
+=
+133
+;
+localparam
+BFMA1O1lI
+=
+134
+;
+localparam
+BFMA1I1lI
+=
+135
+;
+localparam
+BFMA1l1lI
+=
+136
+;
+localparam
+BFMA1OO0I
+=
+137
+;
+localparam
+BFMA1IO0I
+=
+138
+;
+localparam
+BFMA1lO0I
+=
+139
+;
+localparam
+BFMA1OI0I
+=
+140
+;
+localparam
+BFMA1II0I
+=
+141
+;
+localparam
+BFMA1lI0I
+=
+142
+;
+localparam
+BFMA1Ol0I
+=
+150
+;
+localparam
+BFMA1Il0I
+=
+151
+;
+localparam
+BFMA1ll0I
+=
+152
+;
+localparam
+BFMA1O00I
+=
+153
+;
+localparam
+BFMA1I00I
+=
+154
+;
+localparam
+BFMA1l00I
+=
+160
+;
+localparam
+BFMA1O10I
+=
+161
+;
+localparam
+BFMA1I10I
+=
+162
+;
+localparam
+BFMA1l10I
+=
+163
+;
+localparam
+BFMA1OO1I
+=
+164
+;
+localparam
+BFMA1IO1I
+=
+165
+;
+localparam
+BFMA1lO1I
+=
+166
+;
+localparam
+BFMA1OI1I
+=
+167
+;
+localparam
+BFMA1II1I
+=
+168
+;
+localparam
+BFMA1lI1I
+=
+169
+;
+localparam
+BFMA1Ol1I
+=
+170
+;
+localparam
+BFMA1Il1I
+=
+171
+;
+localparam
+BFMA1ll1I
+=
+172
+;
+localparam
+BFMA1O01I
+=
+200
+;
+localparam
+BFMA1I01I
+=
+201
+;
+localparam
+BFMA1l01I
+=
+202
+;
+localparam
+BFMA1O11I
+=
+203
+;
+localparam
+BFMA1I11I
+=
+204
+;
+localparam
+BFMA1l11I
+=
+205
+;
+localparam
+BFMA1OOOl
+=
+206
+;
+localparam
+BFMA1IOOl
+=
+207
+;
+localparam
+BFMA1lOOl
+=
+208
+;
+localparam
+BFMA1OIOl
+=
+209
+;
+localparam
+BFMA1IIOl
+=
+210
+;
+localparam
+BFMA1lIOl
+=
+211
+;
+localparam
+BFMA1OlOl
+=
+212
+;
+localparam
+BFMA1IlOl
+=
+213
+;
+localparam
+BFMA1llOl
+=
+214
+;
+localparam
+BFMA1O0Ol
+=
+215
+;
+localparam
+BFMA1I0Ol
+=
+216
+;
+localparam
+BFMA1l0Ol
+=
+217
+;
+localparam
+BFMA1O1Ol
+=
+218
+;
+localparam
+BFMA1I1Ol
+=
+219
+;
+localparam
+BFMA1l1Ol
+=
+220
+;
+localparam
+BFMA1OOIl
+=
+221
+;
+localparam
+BFMA1IOIl
+=
+222
+;
+localparam
+BFMA1lOIl
+=
+250
+;
+localparam
+BFMA1OIIl
+=
+251
+;
+localparam
+BFMA1IIIl
+=
+252
+;
+localparam
+BFMA1lIIl
+=
+253
+;
+localparam
+BFMA1OlIl
+=
+254
+;
+localparam
+BFMA1IlIl
+=
+255
+;
+localparam
+BFMA1llIl
+=
+1001
+;
+localparam
+BFMA1O0Il
+=
+1002
+;
+localparam
+BFMA1I0Il
+=
+1003
+;
+localparam
+BFMA1l0Il
+=
+1004
+;
+localparam
+BFMA1O1Il
+=
+1005
+;
+localparam
+BFMA1I1Il
+=
+1006
+;
+localparam
+BFMA1l1Il
+=
+1007
+;
+localparam
+BFMA1OOll
+=
+1008
+;
+localparam
+BFMA1IOll
+=
+1009
+;
+localparam
+BFMA1lOll
+=
+1010
+;
+localparam
+BFMA1OIll
+=
+1011
+;
+localparam
+BFMA1IIll
+=
+1012
+;
+localparam
+BFMA1lIll
+=
+1013
+;
+localparam
+BFMA1Olll
+=
+1014
+;
+localparam
+BFMA1Illl
+=
+1015
+;
+localparam
+BFMA1llll
+=
+1016
+;
+localparam
+BFMA1O0ll
+=
+1017
+;
+localparam
+BFMA1I0ll
+=
+1018
+;
+localparam
+BFMA1l0ll
+=
+1019
+;
+localparam
+BFMA1O1ll
+=
+1020
+;
+localparam
+BFMA1I1ll
+=
+1021
+;
+localparam
+BFMA1l1ll
+=
+1022
+;
+localparam
+BFMA1OO0l
+=
+1023
+;
+localparam
+BFMA1IO0l
+=
+0
+;
+localparam
+BFMA1lO0l
+=
+1
+;
+localparam
+BFMA1OI0l
+=
+2
+;
+localparam
+BFMA1II0l
+=
+3
+;
+localparam
+BFMA1lI0l
+=
+4
+;
+localparam
+BFMA1Ol0l
+=
+5
+;
+localparam
+BFMA1Il0l
+=
+6
+;
+localparam
+BFMA1ll0l
+=
+7
+;
+localparam
+BFMA1O00l
+=
+8
+;
+localparam
+BFMA1I00l
+=
+0
+;
+localparam
+BFMA1l00l
+=
+1
+;
+localparam
+BFMA1O10l
+=
+2
+;
+localparam
+BFMA1I10l
+=
+3
+;
+localparam
+BFMA1l10l
+=
+4
+;
+localparam
+BFMA1OO1l
+=
+32
+\'h
+00000000
+;
+localparam
+BFMA1IO1l
+=
+32
+\'h
+00002000
+;
+localparam
+BFMA1lO1l
+=
+32
+\'h
+00004000
+;
+localparam
+BFMA1OI1l
+=
+32
+\'h
+00006000
+;
+localparam
+BFMA1II1l
+=
+32
+\'h
+00008000
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1lI1l
+=
+0
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1Ol1l
+=
+1
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1Il1l
+=
+2
+;
+localparam
+[
+1
+:
+0
+]
+BFMA1ll1l
+=
+3
+;
+function
+integer
+BFMA1O01l
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+BFMA1O01l
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+integer
+to_int_unsigned
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+to_int_unsigned
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+integer
+to_int_signed
+;
+input
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+integer
+BFMA1ll1l
+;
+begin
+BFMA1ll1l
+=
+BFMA1I01l
+;
+to_int_signed
+=
+BFMA1ll1l
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+to_slv32
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+reg
+[
+31
+:
+0
+]
+BFMA1I01l
+;
+begin
+BFMA1I01l
+=
+BFMA1ll1l
+;
+to_slv32
+=
+BFMA1I01l
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1l01l
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+reg
+BFMA1lOO0
+;
+begin
+BFMA1IOO0
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+case
+(
+BFMA1OOO0
+)
+0
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+23
+:
+16
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+31
+:
+24
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+31
+:
+16
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+31
+:
+16
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+010
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+end
+2
+\'b
+01
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=10) ? (WARNING)""
+)
+;
+end
+2
+\'b
+11
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Word A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+1
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+01
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+10
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+2
+\'b
+11
+:
+begin
+BFMA1IOO0
+[
+15
+:
+8
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+begin
+end
+2
+\'b
+01
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)""
+)
+;
+end
+2
+\'b
+10
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=10) ? (WARNING)""
+)
+;
+end
+2
+\'b
+11
+:
+begin
+$display
+(
+""BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)""
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+2
+:
+begin
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+end
+default
+:
+begin
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+end
+endcase
+end
+8
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+default
+:
+begin
+$display
+(
+""Illegal Alignment mode (ERROR)""
+)
+;
+end
+endcase
+BFMA1l01l
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1OIO0
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+begin
+BFMA1IOO0
+=
+BFMA1l01l
+(
+BFMA1O11l
+,
+BFMA1I11l
+,
+BFMA1l11l
+,
+BFMA1OOO0
+)
+;
+BFMA1OIO0
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1IIO0
+;
+input
+[
+2
+:
+0
+]
+BFMA1O11l
+;
+input
+[
+1
+:
+0
+]
+BFMA1I11l
+;
+input
+[
+31
+:
+0
+]
+BFMA1l11l
+;
+input
+BFMA1OOO0
+;
+integer
+BFMA1OOO0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOO0
+;
+reg
+BFMA1lOO0
+;
+begin
+if
+(
+BFMA1OOO0
+==
+8
+)
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+else
+begin
+BFMA1IOO0
+=
+0
+;
+BFMA1lOO0
+=
+BFMA1I11l
+[
+1
+]
+;
+case
+(
+BFMA1O11l
+)
+3
+\'b
+000
+:
+begin
+case
+(
+BFMA1I11l
+)
+2
+\'b
+00
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+7
+:
+0
+]
+;
+2
+\'b
+01
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+8
+]
+;
+2
+\'b
+10
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+23
+:
+16
+]
+;
+2
+\'b
+11
+:
+BFMA1IOO0
+[
+7
+:
+0
+]
+=
+BFMA1l11l
+[
+31
+:
+24
+]
+;
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+001
+:
+begin
+case
+(
+BFMA1lOO0
+)
+1
+\'b
+0
+:
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+15
+:
+0
+]
+;
+1
+\'b
+1
+:
+BFMA1IOO0
+[
+15
+:
+0
+]
+=
+BFMA1l11l
+[
+31
+:
+16
+]
+;
+default
+:
+begin
+end
+endcase
+end
+3
+\'b
+010
+:
+begin
+BFMA1IOO0
+=
+BFMA1l11l
+;
+end
+default
+:
+$display
+(
+""Unexpected AHB Size setting (ERROR)""
+)
+;
+endcase
+end
+BFMA1IIO0
+=
+BFMA1IOO0
+;
+end
+endfunction
+function
+integer
+BFMA1lIO0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1OlO0
+;
+begin
+BFMA1OlO0
+=
+BFMA1ll1l
+;
+BFMA1lIO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1IlO0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+\'h
+62
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+\'h
+68
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+\'h
+77
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+\'h
+78
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+\'h
+3f
+;
+end
+endcase
+BFMA1IlO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1llO0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+input
+BFMA1O0O0
+;
+integer
+BFMA1O0O0
+;
+integer
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+1
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+2
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+4
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+BFMA1O0O0
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+0
+;
+end
+endcase
+BFMA1llO0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1I0O0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+input
+BFMA1l0O0
+;
+integer
+BFMA1l0O0
+;
+reg
+[
+2
+:
+0
+]
+BFMA1OlO0
+;
+begin
+case
+(
+BFMA1O11l
+)
+0
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+000
+;
+end
+1
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+001
+;
+end
+2
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+010
+;
+end
+3
+:
+begin
+BFMA1OlO0
+=
+BFMA1l0O0
+;
+end
+default
+:
+begin
+BFMA1OlO0
+=
+3
+\'b
+XXX
+;
+end
+endcase
+BFMA1I0O0
+=
+BFMA1OlO0
+;
+end
+endfunction
+function
+integer
+BFMA1O1O0
+;
+input
+BFMA1I1O0
+;
+integer
+BFMA1I1O0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+input
+BFMA1l1O0
+;
+integer
+BFMA1l1O0
+;
+input
+BFMA1OOI0
+;
+integer
+BFMA1OOI0
+;
+integer
+BFMA1IOI0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lOI0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1OII0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1III0
+;
+integer
+BFMA1lII0
+;
+reg
+[
+63
+:
+0
+]
+BFMA1OlI0
+;
+localparam
+[
+31
+:
+0
+]
+BFMA1IlI0
+=
+0
+;
+localparam
+[
+31
+:
+0
+]
+BFMA1llI0
+=
+1
+;
+begin
+BFMA1lOI0
+=
+BFMA1ll1l
+;
+BFMA1OII0
+=
+BFMA1l1O0
+;
+BFMA1lII0
+=
+BFMA1l1O0
+;
+BFMA1III0
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+case
+(
+BFMA1I1O0
+)
+BFMA1llIl
+:
+begin
+BFMA1III0
+=
+0
+;
+end
+BFMA1O0Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
++
+BFMA1OII0
+;
+end
+BFMA1I0Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+-
+BFMA1OII0
+;
+end
+BFMA1l0Il
+:
+begin
+BFMA1OlI0
+=
+BFMA1lOI0
+*
+BFMA1OII0
+;
+BFMA1III0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+;
+end
+BFMA1O1Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+/
+BFMA1OII0
+;
+end
+BFMA1OOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+&
+BFMA1OII0
+;
+end
+BFMA1IOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+|
+BFMA1OII0
+;
+end
+BFMA1lOll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+^
+BFMA1OII0
+;
+end
+BFMA1OIll
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+^
+BFMA1OII0
+;
+end
+BFMA1lIll
+:
+begin
+if
+(
+BFMA1lII0
+==
+0
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+end
+else
+begin
+BFMA1III0
+=
+BFMA1lOI0
+>>
+BFMA1lII0
+;
+end
+end
+BFMA1IIll
+:
+begin
+if
+(
+BFMA1lII0
+==
+0
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+end
+else
+begin
+BFMA1III0
+=
+BFMA1lOI0
+<<
+BFMA1lII0
+;
+end
+end
+BFMA1l1Il
+:
+begin
+BFMA1OlI0
+=
+{
+BFMA1IlI0
+,
+BFMA1llI0
+}
+;
+if
+(
+BFMA1lII0
+>
+0
+)
+begin
+begin
+:
+BFMA1O0I0
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+1
+;
+BFMA1I0I0
+<=
+BFMA1lII0
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1OlI0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+*
+BFMA1lOI0
+;
+end
+end
+end
+BFMA1III0
+=
+BFMA1OlI0
+[
+31
+:
+0
+]
+;
+end
+BFMA1Olll
+:
+begin
+if
+(
+BFMA1lOI0
+==
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1Illl
+:
+begin
+if
+(
+BFMA1lOI0
+!=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1llll
+:
+begin
+if
+(
+BFMA1lOI0
+>
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1O0ll
+:
+begin
+if
+(
+BFMA1lOI0
+<
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1I0ll
+:
+begin
+if
+(
+BFMA1lOI0
+>=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1l0ll
+:
+begin
+if
+(
+BFMA1lOI0
+<=
+BFMA1OII0
+)
+begin
+BFMA1III0
+=
+BFMA1llI0
+;
+end
+end
+BFMA1I1Il
+:
+begin
+BFMA1III0
+=
+BFMA1lOI0
+%
+BFMA1OII0
+;
+end
+BFMA1O1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+1
+\'b
+1
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1I1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+1
+\'b
+0
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1l1ll
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+BFMA1lOI0
+;
+BFMA1III0
+[
+BFMA1l1O0
+]
+=
+~
+BFMA1III0
+[
+BFMA1l1O0
+]
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+BFMA1OO0l
+:
+begin
+if
+(
+BFMA1l1O0
+<=
+31
+)
+begin
+BFMA1III0
+=
+0
+;
+BFMA1III0
+[
+0
+]
+=
+BFMA1lOI0
+[
+BFMA1l1O0
+]
+;
+end
+else
+begin
+$display
+(
+""Bit operation on bit >31 (FAILURE)""
+)
+;
+$stop
+;
+end
+end
+default
+:
+begin
+$display
+(
+""Illegal Maths Operator (FAILURE)""
+)
+;
+$stop
+;
+end
+endcase
+BFMA1IOI0
+=
+BFMA1III0
+;
+if
+(
+BFMA1OOI0
+>=
+4
+)
+begin
+$display
+(
+""Calculated %d = %d (%d) %d""
+,
+BFMA1IOI0
+,
+BFMA1ll1l
+,
+BFMA1I1O0
+,
+BFMA1l1O0
+)
+;
+end
+BFMA1O1O0
+=
+BFMA1IOI0
+;
+end
+endfunction
+function
+[
+31
+:
+0
+]
+BFMA1l0I0
+;
+input
+[
+31
+:
+0
+]
+BFMA1ll1l
+;
+reg
+[
+31
+:
+0
+]
+BFMA1O1I0
+;
+begin
+BFMA1O1I0
+=
+BFMA1ll1l
+;
+BFMA1O1I0
+=
+0
+;
+begin
+:
+BFMA1I1I0
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+31
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+if
+(
+(
+BFMA1ll1l
+[
+BFMA1I0I0
+]
+)
+==
+1
+\'b
+1
+)
+begin
+BFMA1O1I0
+[
+BFMA1I0I0
+]
+=
+1
+\'b
+1
+;
+end
+end
+end
+BFMA1l0I0
+=
+BFMA1O1I0
+;
+end
+endfunction
+function
+integer
+BFMA1l1I0
+;
+input
+BFMA1OOl0
+;
+integer
+BFMA1OOl0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IOl0
+;
+integer
+BFMA1lOl0
+;
+begin
+BFMA1lOl0
+=
+BFMA1OOl0
+/
+BFMA1ll1l
+;
+BFMA1IOl0
+=
+BFMA1OOl0
+-
+BFMA1lOl0
+*
+BFMA1ll1l
+;
+BFMA1l1I0
+=
+BFMA1IOl0
+;
+end
+endfunction
+function
+integer
+BFMA1OIl0
+;
+input
+BFMA1OOl0
+;
+integer
+BFMA1OOl0
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IOl0
+;
+integer
+BFMA1lOl0
+;
+begin
+BFMA1lOl0
+=
+BFMA1OOl0
+/
+BFMA1ll1l
+;
+BFMA1IOl0
+=
+BFMA1OOl0
+-
+BFMA1lOl0
+*
+BFMA1ll1l
+;
+BFMA1OIl0
+=
+BFMA1lOl0
+;
+end
+endfunction
+function
+integer
+to_boolean
+;
+input
+BFMA1ll1l
+;
+integer
+BFMA1ll1l
+;
+integer
+BFMA1IIl0
+;
+begin
+BFMA1IIl0
+=
+0
+;
+if
+(
+BFMA1ll1l
+!=
+0
+)
+BFMA1IIl0
+=
+1
+;
+to_boolean
+=
+BFMA1IIl0
+;
+end
+endfunction
+function
+integer
+BFMA1lIl0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1lll0
+;
+reg
+BFMA1O0l0
+;
+begin
+BFMA1Ill0
+=
+BFMA1Oll0
+;
+BFMA1O0l0
+=
+1
+\'b
+1
+;
+BFMA1lll0
+[
+0
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+;
+BFMA1lll0
+[
+1
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+0
+]
+;
+BFMA1lll0
+[
+2
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+1
+]
+;
+BFMA1lll0
+[
+3
+]
+=
+BFMA1Ill0
+[
+2
+]
+;
+BFMA1lll0
+[
+4
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+3
+]
+;
+BFMA1lll0
+[
+5
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+4
+]
+;
+BFMA1lll0
+[
+6
+]
+=
+BFMA1Ill0
+[
+5
+]
+;
+BFMA1lll0
+[
+7
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+6
+]
+;
+BFMA1lll0
+[
+8
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+7
+]
+;
+BFMA1lll0
+[
+9
+]
+=
+BFMA1Ill0
+[
+8
+]
+;
+BFMA1lll0
+[
+10
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+9
+]
+;
+BFMA1lll0
+[
+11
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+10
+]
+;
+BFMA1lll0
+[
+12
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+11
+]
+;
+BFMA1lll0
+[
+13
+]
+=
+BFMA1Ill0
+[
+12
+]
+;
+BFMA1lll0
+[
+14
+]
+=
+BFMA1Ill0
+[
+13
+]
+;
+BFMA1lll0
+[
+15
+]
+=
+BFMA1Ill0
+[
+14
+]
+;
+BFMA1lll0
+[
+16
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+15
+]
+;
+BFMA1lll0
+[
+17
+]
+=
+BFMA1Ill0
+[
+16
+]
+;
+BFMA1lll0
+[
+18
+]
+=
+BFMA1Ill0
+[
+17
+]
+;
+BFMA1lll0
+[
+19
+]
+=
+BFMA1Ill0
+[
+18
+]
+;
+BFMA1lll0
+[
+20
+]
+=
+BFMA1Ill0
+[
+19
+]
+;
+BFMA1lll0
+[
+21
+]
+=
+BFMA1Ill0
+[
+20
+]
+;
+BFMA1lll0
+[
+22
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+21
+]
+;
+BFMA1lll0
+[
+23
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+22
+]
+;
+BFMA1lll0
+[
+24
+]
+=
+BFMA1Ill0
+[
+23
+]
+;
+BFMA1lll0
+[
+25
+]
+=
+BFMA1Ill0
+[
+24
+]
+;
+BFMA1lll0
+[
+26
+]
+=
+BFMA1O0l0
+^
+BFMA1Ill0
+[
+31
+]
+^
+BFMA1Ill0
+[
+25
+]
+;
+BFMA1lll0
+[
+27
+]
+=
+BFMA1Ill0
+[
+26
+]
+;
+BFMA1lll0
+[
+28
+]
+=
+BFMA1Ill0
+[
+27
+]
+;
+BFMA1lll0
+[
+29
+]
+=
+BFMA1Ill0
+[
+28
+]
+;
+BFMA1lll0
+[
+30
+]
+=
+BFMA1Ill0
+[
+29
+]
+;
+BFMA1lll0
+[
+31
+]
+=
+BFMA1Ill0
+[
+30
+]
+;
+BFMA1lIl0
+=
+BFMA1lll0
+;
+end
+endfunction
+function
+integer
+BFMA1I0l0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1l0l0
+;
+integer
+BFMA1I0I0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+begin
+BFMA1Ill0
+=
+BFMA1Oll0
+;
+for
+(
+BFMA1I0I0
+=
+31
+;
+BFMA1I0I0
+>=
+BFMA1O11l
+;
+BFMA1I0I0
+=
+BFMA1I0I0
+-
+1
+)
+BFMA1Ill0
+[
+BFMA1I0I0
+]
+=
+0
+;
+BFMA1l0l0
+=
+BFMA1Ill0
+;
+BFMA1I0l0
+=
+BFMA1l0l0
+;
+end
+endfunction
+function
+integer
+BFMA1O1l0
+;
+input
+BFMA1Oll0
+;
+integer
+BFMA1Oll0
+;
+input
+BFMA1O11l
+;
+integer
+BFMA1O11l
+;
+integer
+BFMA1l0l0
+;
+reg
+[
+31
+:
+0
+]
+BFMA1Ill0
+;
+integer
+BFMA1I1l0
+;
+integer
+BFMA1I0I0
+;
+begin
+case
+(
+BFMA1O11l
+)
+1
+:
+begin
+BFMA1I1l0
+=
+0
+;
+end
+2
+:
+begin
+BFMA1I1l0
+=
+1
+;
+end
+4
+:
+begin
+BFMA1I1l0
+=
+2
+;
+end
+8
+:
+begin
+BFMA1I1l0
+=
+3
+;
+end
+16
+:
+begin
+BFMA1I1l0
+=
+4
+;
+end
+32
+:
+begin
+BFMA1I1l0
+=
+5
+;
+end
+64
+:
+begin
+BFMA1I1l0
+=
+6
+;
+end
+128
+:
+begin
+BFMA1I1l0
+=
+7
+;
+end
+256
+:
+begin
+BFMA1I1l0
+=
+8
+;
+end
+512
+:
+begin
+BFMA1I1l0
+=
+9
+;
+end
+1024
+:
+begin
+BFMA1I1l0
+=
+10
+;
+end
+2048
+:
+begin
+BFMA1I1l0
+=
+11
+;
+end
+4096
+:
+begin
+BFMA1I1l0
+=
+12
+;
+end
+8192
+:
+begin
+BFMA1I1l0
+=
+13
+;
+end
+16384
+:
+begin
+BFMA1I1l0
+=
+14
+;
+end
+32768
+:
+begin
+BFMA1I1l0
+=
+15
+;
+end
+65536
+:
+begin
+BFMA1I1l0
+=
+16
+;
+end
+131072
+:
+BFMA1I1l0
+=
+17
+;
+262144
+:
+BFMA1I1l0
+=
+18
+;
+524288
+:
+BFMA1I1l0
+=
+19
+;
+1048576
+:
+BFMA1I1l0
+=
+20
+;
+2097152
+:
+BFMA1I1l0
+=
+21
+;
+4194304
+:
+BFMA1I1l0
+=
+22
+;
+8388608
+:
+BFMA1I1l0
+=
+23
+;
+16777216
+:
+BFMA1I1l0
+=
+24
+;
+33554432
+:
+BFMA1I1l0
+=
+25
+;
+67108864
+:
+BFMA1I1l0
+=
+26
+;
+134217728
+:
+BFMA1I1l0
+=
+27
+;
+268435456
+:
+BFMA1I1l0
+=
+28
+;
+536870912
+:
+BFMA1I1l0
+=
+29
+;
+1073741824
+:
+BFMA1I1l0
+=
+30
+;
+default
+:
+begin
+$display
+(
+""Random function error (FAILURE)""
+)
+;
+$finish
+;
+end
+endcase
+BFMA1Ill0
+=
+to_slv32
+(
+BFMA1Oll0
+)
+;
+if
+(
+BFMA1I1l0
+<
+31
+)
+begin
+for
+(
+BFMA1I0I0
+=
+31
+;
+BFMA1I0I0
+>=
+BFMA1I1l0
+;
+BFMA1I0I0
+=
+BFMA1I0I0
+-
+1
+)
+BFMA1Ill0
+[
+BFMA1I0I0
+]
+=
+0
+;
+end
+BFMA1l0l0
+=
+to_int_signed
+(
+BFMA1Ill0
+)
+;
+BFMA1O1l0
+=
+BFMA1l0l0
+;
+end
+endfunction
+function
+bound1k
+;
+input
+BFMA1l1l0
+;
+integer
+BFMA1l1l0
+;
+input
+BFMA1OO00
+;
+integer
+BFMA1OO00
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IO00
+;
+reg
+BFMA1lO00
+;
+begin
+BFMA1IO00
+=
+BFMA1OO00
+;
+BFMA1lO00
+=
+0
+;
+case
+(
+BFMA1l1l0
+)
+0
+:
+begin
+if
+(
+BFMA1IO00
+[
+9
+:
+0
+]
+==
+10
+\'b
+0000000000
+)
+begin
+BFMA1lO00
+=
+1
+;
+end
+end
+1
+:
+begin
+BFMA1lO00
+=
+1
+;
+end
+2
+:
+begin
+end
+default
+:
+begin
+$display
+(
+""Illegal Burst Boundary Set (FAILURE)""
+)
+;
+$finish
+;
+end
+endcase
+bound1k
+=
+BFMA1lO00
+;
+end
+endfunction
+input
+PCLK
+;
+input
+PRESETN
+;
+input
+PENABLE
+;
+input
+PWRITE
+;
+input
+PSEL
+;
+input
+[
+AWIDTH
+-
+1
+:
+0
+]
+PADDR
+;
+input
+[
+DWIDTH
+-
+1
+:
+0
+]
+PWDATA
+;
+output
+[
+DWIDTH
+-
+1
+:
+0
+]
+PRDATA
+;
+wire
+[
+DWIDTH
+-
+1
+:
+0
+]
+PRDATA
+;
+output
+PREADY
+;
+wire
+PREADY
+;
+output
+PSLVERR
+;
+wire
+PSLVERR
+;
+input
+EXT_EN
+;
+input
+EXT_WR
+;
+input
+EXT_RD
+;
+input
+[
+AWIDTH
+-
+1
+:
+0
+]
+EXT_ADDR
+;
+inout
+[
+DWIDTH
+-
+1
+:
+0
+]
+EXT_DATA
+;
+reg
+[
+DWIDTH
+-
+1
+:
+0
+]
+BFMA1lI1II
+;
+integer
+BFMA1Ol1II
+=
+DEBUG
+;
+wire
+BFMA1O11lI
+;
+reg
+BFMA1I11lI
+;
+reg
+BFMA1l11lI
+;
+wire
+BFMA1OOO0I
+;
+reg
+BFMA1IOO0I
+;
+reg
+BFMA1lOO0I
+;
+wire
+BFMA1OIO0I
+;
+reg
+BFMA1IIO0I
+;
+reg
+BFMA1lIO0I
+;
+wire
+[
+AWIDTH
+-
+1
+:
+0
+]
+BFMA1OlO0I
+;
+reg
+[
+AWIDTH
+-
+1
+:
+0
+]
+BFMA1IlO0I
+;
+reg
+[
+AWIDTH
+-
+1
+:
+0
+]
+BFMA1llO0I
+;
+wire
+[
+DWIDTH
+-
+1
+:
+0
+]
+BFMA1O0O0I
+;
+reg
+[
+DWIDTH
+-
+1
+:
+0
+]
+BFMA1I0O0I
+;
+reg
+[
+DWIDTH
+-
+1
+:
+0
+]
+BFMA1l0O0I
+;
+reg
+[
+31
+:
+0
+]
+BFMA1l0III
+;
+reg
+[
+31
+:
+0
+]
+BFMA1O1O0I
+;
+reg
+BFMA1I1O0I
+;
+reg
+BFMA1l1O0I
+;
+parameter
+BFMA1Il1
+=
+TPD
+*
+1
+;
+reg
+[
+31
+:
+0
+]
+BFMA1OOI0I
+;
+wire
+[
+31
+:
+0
+]
+BFMA1IlI0
+;
+assign
+BFMA1IlI0
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+reg
+BFMA1OlOlI
+;
+initial
+begin
+BFMA1OlOlI
+<=
+1
+\'b
+0
+;
+#
+1
+;
+BFMA1OlOlI
+<=
+1
+\'b
+1
+;
+end
+always
+@
+(
+posedge
+PCLK
+or
+negedge
+PRESETN
+or
+negedge
+BFMA1OlOlI
+)
+begin
+:
+BFMA1I0OlI
+integer
+BFMA1l0OlI
+;
+reg
+[
+7
+:
+0
+]
+BFMA1l1OlI
+[
+0
+:
+DEPTH
+-
+1
+]
+;
+integer
+BFMA1OOIlI
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOIlI
+;
+reg
+BFMA1lIIlI
+;
+integer
+BFMA1l1IlI
+;
+integer
+BFMA1OOllI
+;
+reg
+[
+31
+:
+0
+]
+BFMA1IOllI
+;
+reg
+BFMA1OIllI
+;
+integer
+BFMA1IIllI
+;
+integer
+BFMA1IIIlI
+;
+integer
+BFMA1IOI0I
+;
+reg
+[
+7
+:
+0
+]
+BFMA1O1I0
+;
+reg
+BFMA1OIOOI
+;
+reg
+BFMA1lIllI
+;
+reg
+BFMA1OlllI
+;
+reg
+BFMA1Oll1
+;
+reg
+BFMA1IIOOI
+;
+integer
+BFMA1ll11
+;
+integer
+BFMA1IlllI
+;
+integer
+BFMA1llllI
+;
+reg
+[
+1
+:
+(
+80
+)
+*
+8
+]
+BFMA1I011
+;
+reg
+[
+1
+:
+(
+80
+)
+*
+8
+]
+BFMA1O011
+;
+integer
+BFMA1OO0lI
+;
+integer
+BFMA1lOI0I
+;
+integer
+BFMA1IO0lI
+;
+if
+(
+INITFILE
+!=
+8
+\'h
+20
+&&
+BFMA1Oll1
+==
+0
+&&
+BFMA1OlOlI
+==
+1
+\'b
+1
+)
+begin
+$display
+(
+""Opening BFM APB Slave %0d Initialisation file %s""
+,
+ID
+,
+INITFILE
+)
+;
+$readmemb
+(
+INITFILE
+,
+BFMA1l1OlI
+)
+;
+BFMA1Oll1
+=
+1
+;
+end
+if
+(
+BFMA1OlOlI
+==
+1
+\'b
+0
+)
+begin
+BFMA1IIIlI
+=
+0
+;
+BFMA1Oll1
+=
+0
+;
+BFMA1OIllI
+=
+0
+;
+end
+else
+if
+(
+PRESETN
+==
+1
+\'b
+0
+)
+begin
+BFMA1l1IlI
+=
+0
+;
+BFMA1OOllI
+=
+256
+;
+BFMA1OIllI
+=
+0
+;
+BFMA1IIllI
+=
+0
+;
+BFMA1IIIlI
+=
+0
+;
+BFMA1lIIlI
+=
+1
+\'b
+0
+;
+BFMA1I1O0I
+<=
+1
+\'b
+0
+;
+BFMA1l1O0I
+<=
+1
+\'b
+0
+;
+BFMA1lI1II
+<=
+{
+DWIDTH
+{
+1
+\'b
+z
+}
+}
+;
+BFMA1OO0lI
+=
+69
+;
+BFMA1IO0lI
+=
+0
+;
+BFMA1OOI0I
+=
+0
+;
+end
+else
+begin
+BFMA1lIIlI
+=
+1
+\'b
+0
+;
+BFMA1l1O0I
+<=
+1
+\'b
+0
+;
+if
+(
+PSEL
+==
+1
+\'b
+1
+)
+begin
+BFMA1OOIlI
+=
+{
+PADDR
+[
+AWIDTH
+-
+1
+:
+2
+]
+,
+2
+\'b
+00
+}
+;
+if
+(
+PSEL
+==
+1
+\'b
+1
+&
+PENABLE
+==
+1
+\'b
+0
+)
+begin
+if
+(
+BFMA1IIIlI
+>=
+256
+)
+begin
+BFMA1OO0lI
+=
+BFMA1lIl0
+(
+BFMA1OO0lI
+)
+;
+BFMA1lOI0I
+=
+BFMA1O1l0
+(
+BFMA1OO0lI
+,
+BFMA1IIIlI
+%
+256
+)
+;
+end
+else
+begin
+BFMA1lOI0I
+=
+BFMA1IIIlI
+;
+end
+BFMA1IOI0I
+=
+BFMA1lOI0I
+-
+1
+;
+if
+(
+BFMA1lOI0I
+==
+0
+)
+begin
+BFMA1lIIlI
+=
+1
+\'b
+1
+;
+BFMA1IOI0I
+=
+0
+;
+end
+end
+if
+(
+PSEL
+==
+1
+\'b
+1
+&
+PENABLE
+==
+1
+\'b
+1
+&
+BFMA1IIIlI
+>
+0
+)
+begin
+if
+(
+BFMA1IOI0I
+>
+0
+)
+begin
+BFMA1IOI0I
+=
+BFMA1IOI0I
+-
+1
+;
+end
+else
+if
+(
+BFMA1I1O0I
+==
+1
+\'b
+0
+)
+begin
+BFMA1lIIlI
+=
+1
+\'b
+1
+;
+if
+(
+BFMA1IIIlI
+>=
+256
+)
+begin
+BFMA1OO0lI
+=
+BFMA1lIl0
+(
+BFMA1OO0lI
+)
+;
+BFMA1IOI0I
+=
+BFMA1O1l0
+(
+BFMA1OO0lI
+,
+BFMA1IIIlI
+%
+256
+)
+;
+end
+else
+begin
+BFMA1IOI0I
+=
+BFMA1IIIlI
+;
+end
+end
+else
+begin
+BFMA1lIIlI
+=
+1
+\'b
+0
+;
+end
+end
+if
+(
+PSEL
+==
+1
+\'b
+1
+&
+BFMA1lIIlI
+==
+1
+\'b
+1
+)
+begin
+if
+(
+BFMA1OIllI
+)
+begin
+if
+(
+BFMA1IIllI
+>
+1
+)
+begin
+BFMA1IIllI
+=
+BFMA1IIllI
+-
+1
+;
+end
+else
+begin
+BFMA1OIllI
+=
+0
+;
+BFMA1l1O0I
+<=
+1
+\'b
+1
+;
+end
+end
+end
+if
+(
+PENABLE
+==
+1
+\'b
+1
+&
+PWRITE
+==
+1
+\'b
+1
+&
+BFMA1I1O0I
+==
+1
+\'b
+1
+)
+begin
+if
+(
+~
+(
+ENFUNC
+>
+0
+&
+BFMA1OOIlI
+>=
+ENFUNC
+&
+BFMA1OOIlI
+<
+ENFUNC
++
+256
+)
+)
+begin
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+0
+]
+=
+BFMA1l0III
+[
+7
+:
+0
+]
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+1
+]
+=
+BFMA1l0III
+[
+15
+:
+8
+]
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+2
+]
+=
+BFMA1l0III
+[
+23
+:
+16
+]
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+3
+]
+=
+BFMA1l0III
+[
+31
+:
+24
+]
+;
+if
+(
+BFMA1Ol1II
+>=
+1
+)
+$display
+(
+""APBS: Slot %0d Write %04x=%04x ""
+,
+ID
+,
+BFMA1OOIlI
+,
+PWDATA
+)
+;
+BFMA1IlllI
+=
+BFMA1OOIlI
+;
+BFMA1llllI
+=
+BFMA1O01l
+(
+PWDATA
+)
+;
+end
+else
+begin
+if
+(
+ENFUNC
+>
+0
+&
+BFMA1OOIlI
+>=
+ENFUNC
+&
+BFMA1OOIlI
+<
+ENFUNC
++
+256
+)
+begin
+$display
+(
+""APBS:%0d Setting ENFUNC %0d %0d""
+,
+ID
+,
+BFMA1OOIlI
+-
+ENFUNC
+,
+PWDATA
+)
+;
+case
+(
+BFMA1OOIlI
+-
+ENFUNC
+)
+0
+:
+begin
+BFMA1OIllI
+=
+1
+;
+BFMA1IIllI
+=
+BFMA1O01l
+(
+PWDATA
+[
+7
+:
+0
+]
+)
+;
+$display
+(
+""APBS: PSLVERR  will be set on the %0d access""
+,
+BFMA1IIllI
+)
+;
+end
+4
+:
+begin
+BFMA1IIIlI
+=
+BFMA1O01l
+(
+PWDATA
+[
+9
+:
+0
+]
+)
+;
+if
+(
+BFMA1IIIlI
+>=
+256
+)
+begin
+$display
+(
+""APBS:PREADY timing random 0 to %0d cycles""
+,
+(
+BFMA1IIIlI
+%
+256
+)
+)
+;
+end
+else
+begin
+$display
+(
+""APBS:PREADY timing %0d cycles ""
+,
+BFMA1IIIlI
+)
+;
+end
+end
+8
+:
+begin
+BFMA1Ol1II
+<=
+BFMA1O01l
+(
+PWDATA
+[
+7
+:
+0
+]
+)
+;
+end
+12
+:
+begin
+begin
+:
+BFMA1OII0I
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+DEPTH
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1l1OlI
+[
+BFMA1I0I0
+]
+=
+0
+;
+end
+end
+end
+16
+:
+begin
+begin
+:
+BFMA1III0I
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+DEPTH
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+begin
+BFMA1l1OlI
+[
+BFMA1I0I0
+]
+=
+~
+BFMA1I0I0
+;
+end
+end
+end
+28
+:
+begin
+BFMA1IOllI
+=
+BFMA1l0III
+;
+BFMA1l1IlI
+=
+BFMA1OOllI
+;
+end
+32
+:
+begin
+BFMA1OOllI
+=
+BFMA1O01l
+(
+PWDATA
+)
+;
+end
+36
+:
+begin
+BFMA1Oll1
+=
+0
+;
+end
+40
+:
+begin
+$swrite
+(
+BFMA1I011
+,
+""image%0d.txt""
+,
+ID
+)
+;
+$display
+(
+""APBS:%0d: Dumping to %0s""
+,
+ID
+,
+BFMA1I011
+)
+;
+BFMA1l0OlI
+=
+$fopen
+(
+BFMA1I011
+,
+""w""
+)
+;
+begin
+:
+BFMA1l01OI
+integer
+BFMA1I0I0
+;
+for
+(
+BFMA1I0I0
+=
+0
+;
+BFMA1I0I0
+<=
+DEPTH
+-
+1
+;
+BFMA1I0I0
+=
+BFMA1I0I0
++
+1
+)
+$fdisplay
+(
+BFMA1l0OlI
+,
+""%08b""
+,
+BFMA1l1OlI
+[
+BFMA1I0I0
+]
+)
+;
+end
+$fflush
+(
+BFMA1l0OlI
+)
+;
+$fclose
+(
+BFMA1l0OlI
+)
+;
+end
+52
+:
+begin
+BFMA1IO0lI
+=
+(
+PWDATA
+[
+0
+]
+==
+1
+\'b
+1
+)
+;
+$display
+(
+""APBS: Special Mode Enables set to %d""
+,
+PWDATA
+[
+2
+:
+0
+]
+)
+;
+if
+(
+BFMA1IO0lI
+==
+1
+\'b
+1
+)
+BFMA1OOI0I
+=
+{
+32
+{
+1
+\'b
+X
+}
+}
+;
+else
+BFMA1OOI0I
+=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+end
+default
+:
+begin
+end
+endcase
+end
+end
+end
+if
+(
+PSEL
+==
+1
+\'b
+1
+&
+PWRITE
+==
+1
+\'b
+0
+&
+BFMA1lIIlI
+==
+1
+\'b
+1
+)
+begin
+BFMA1IOIlI
+=
+{
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+3
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+2
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+1
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+0
+]
+}
+;
+if
+(
+~
+(
+ENFUNC
+>
+0
+&
+BFMA1OOIlI
+>=
+ENFUNC
+&
+BFMA1OOIlI
+<
+ENFUNC
++
+256
+)
+)
+begin
+BFMA1IlllI
+=
+BFMA1OOIlI
+;
+BFMA1llllI
+=
+BFMA1O01l
+(
+BFMA1IOIlI
+)
+;
+end
+else
+begin
+case
+(
+BFMA1OOIlI
+-
+ENFUNC
+)
+44
+:
+begin
+BFMA1IOIlI
+=
+to_slv32
+(
+BFMA1IlllI
+)
+;
+end
+48
+:
+begin
+BFMA1IOIlI
+=
+to_slv32
+(
+BFMA1llllI
+)
+;
+end
+default
+:
+begin
+end
+endcase
+end
+BFMA1O1O0I
+<=
+BFMA1IOIlI
+;
+end
+if
+(
+PSEL
+==
+1
+\'b
+1
+&
+PWRITE
+==
+1
+\'b
+0
+&
+PENABLE
+==
+1
+\'b
+1
+&
+BFMA1I1O0I
+==
+1
+\'b
+1
+)
+begin
+if
+(
+BFMA1Ol1II
+>=
+1
+)
+$display
+(
+""APBS: Slot %0d Read %04x=%04x ""
+,
+ID
+,
+BFMA1OOIlI
+,
+BFMA1IOIlI
+)
+;
+end
+end
+BFMA1I1O0I
+<=
+BFMA1lIIlI
+;
+if
+(
+BFMA1l1IlI
+>
+1
+)
+begin
+BFMA1l1IlI
+=
+BFMA1l1IlI
+-
+1
+;
+end
+else
+if
+(
+BFMA1l1IlI
+==
+1
+)
+begin
+BFMA1l1OlI
+[
+ENFUNC
++
+28
++
+0
+]
+=
+BFMA1IOllI
+[
+7
+:
+0
+]
+;
+BFMA1l1OlI
+[
+ENFUNC
++
+28
++
+1
+]
+=
+BFMA1IOllI
+[
+15
+:
+8
+]
+;
+BFMA1l1OlI
+[
+ENFUNC
++
+28
++
+2
+]
+=
+BFMA1IOllI
+[
+23
+:
+16
+]
+;
+BFMA1l1OlI
+[
+ENFUNC
++
+28
++
+3
+]
+=
+BFMA1IOllI
+[
+31
+:
+24
+]
+;
+BFMA1l1IlI
+=
+0
+;
+end
+BFMA1lI1II
+<=
+{
+DWIDTH
+{
+1
+\'b
+z
+}
+}
+;
+if
+(
+EXT_EN
+==
+1
+\'b
+1
+&
+EXT_RD
+==
+1
+\'b
+1
+)
+begin
+case
+(
+EXT_SIZE
+)
+0
+:
+begin
+BFMA1OOIlI
+=
+EXT_ADDR
+[
+AWIDTH
+-
+1
+:
+0
+]
+;
+BFMA1IOIlI
+=
+{
+BFMA1IlI0
+[
+31
+:
+8
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+0
+]
+}
+;
+end
+1
+:
+begin
+BFMA1OOIlI
+=
+{
+EXT_ADDR
+[
+AWIDTH
+-
+1
+:
+1
+]
+,
+1
+\'b
+0
+}
+;
+BFMA1IOIlI
+=
+{
+BFMA1IlI0
+[
+31
+:
+16
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+1
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+0
+]
+}
+;
+end
+2
+:
+begin
+BFMA1OOIlI
+=
+{
+EXT_ADDR
+[
+AWIDTH
+-
+1
+:
+2
+]
+,
+2
+\'b
+00
+}
+;
+BFMA1IOIlI
+=
+{
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+3
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+2
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+1
+]
+,
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+0
+]
+}
+;
+end
+endcase
+if
+(
+BFMA1Ol1II
+>=
+1
+)
+$display
+(
+""APBS:%0d Extension Read %04x=%04x ""
+,
+ID
+,
+BFMA1OOIlI
+,
+BFMA1IOIlI
+)
+;
+BFMA1lI1II
+<=
+BFMA1IOIlI
+;
+end
+if
+(
+EXT_EN
+==
+1
+\'b
+1
+&
+EXT_WR
+==
+1
+\'b
+1
+)
+begin
+case
+(
+EXT_SIZE
+)
+0
+:
+begin
+BFMA1OOIlI
+=
+EXT_ADDR
+[
+AWIDTH
+-
+1
+:
+0
+]
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+0
+]
+=
+EXT_DATA
+[
+7
+:
+0
+]
+;
+end
+1
+:
+begin
+BFMA1OOIlI
+=
+{
+EXT_ADDR
+[
+AWIDTH
+-
+1
+:
+1
+]
+,
+1
+\'b
+0
+}
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+0
+]
+=
+EXT_DATA
+[
+7
+:
+0
+]
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+1
+]
+=
+EXT_DATA
+[
+15
+:
+8
+]
+;
+end
+2
+:
+begin
+BFMA1OOIlI
+=
+{
+EXT_ADDR
+[
+AWIDTH
+-
+1
+:
+2
+]
+,
+2
+\'b
+00
+}
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+0
+]
+=
+EXT_DATA
+[
+7
+:
+0
+]
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+1
+]
+=
+EXT_DATA
+[
+15
+:
+8
+]
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+2
+]
+=
+EXT_DATA
+[
+23
+:
+16
+]
+;
+BFMA1l1OlI
+[
+BFMA1OOIlI
++
+3
+]
+=
+EXT_DATA
+[
+31
+:
+24
+]
+;
+end
+endcase
+if
+(
+BFMA1Ol1II
+>=
+1
+)
+$display
+(
+""APBS:%0d Extension Write %04x=%04x ""
+,
+ID
+,
+BFMA1OOIlI
+,
+EXT_DATA
+)
+;
+end
+end
+end
+assign
+#
+TPD
+PRDATA
+=
+(
+PENABLE
+==
+1
+\'b
+1
+)
+?
+BFMA1O1O0I
+[
+DWIDTH
+-
+1
+:
+0
+]
+:
+BFMA1OOI0I
+[
+DWIDTH
+-
+1
+:
+0
+]
+;
+assign
+#
+TPD
+PREADY
+=
+BFMA1I1O0I
+;
+assign
+#
+TPD
+PSLVERR
+=
+BFMA1l1O0I
+;
+wire
+[
+DWIDTH
+-
+1
+:
+0
+]
+EXT_DATA
+=
+BFMA1lI1II
+;
+always
+@
+(
+PWDATA
+)
+begin
+BFMA1l0III
+<=
+{
+32
+{
+1
+\'b
+0
+}
+}
+;
+BFMA1l0III
+[
+DWIDTH
+-
+1
+:
+0
+]
+<=
+PWDATA
+;
+end
+assign
+BFMA1O11lI
+=
+PENABLE
+;
+assign
+BFMA1OOO0I
+=
+PWRITE
+;
+assign
+BFMA1OIO0I
+=
+PSEL
+;
+assign
+BFMA1OlO0I
+=
+BFMA1l0I0
+(
+PADDR
+)
+;
+assign
+BFMA1O0O0I
+=
+BFMA1l0I0
+(
+PWDATA
+)
+;
+always
+@
+(
+posedge
+PCLK
+)
+begin
+:
+BFMA1lII0I
+reg
+BFMA1l01lI
+;
+BFMA1I11lI
+<=
+BFMA1O11lI
+;
+BFMA1l11lI
+<=
+BFMA1I11lI
+;
+BFMA1IOO0I
+<=
+BFMA1OOO0I
+;
+BFMA1lOO0I
+<=
+BFMA1IOO0I
+;
+BFMA1IIO0I
+<=
+BFMA1OIO0I
+;
+BFMA1lIO0I
+<=
+BFMA1IIO0I
+;
+BFMA1IlO0I
+<=
+BFMA1OlO0I
+;
+BFMA1llO0I
+<=
+BFMA1IlO0I
+;
+BFMA1I0O0I
+<=
+BFMA1O0O0I
+;
+BFMA1l0O0I
+<=
+BFMA1I0O0I
+;
+BFMA1l01lI
+=
+0
+;
+if
+(
+BFMA1O11lI
+==
+1
+\'b
+1
+&
+BFMA1OIO0I
+==
+1
+\'b
+1
+)
+begin
+if
+(
+BFMA1OlO0I
+!=
+BFMA1IlO0I
+)
+begin
+$display
+(
+""APBS:%0d Address not stable in both cycles""
+,
+ID
+)
+;
+BFMA1l01lI
+=
+1
+;
+end
+if
+(
+BFMA1OOO0I
+!=
+BFMA1IOO0I
+)
+begin
+$display
+(
+""APBS:%0d PWRITE not stable in both cycles""
+,
+ID
+)
+;
+BFMA1l01lI
+=
+1
+;
+end
+if
+(
+BFMA1OIO0I
+!=
+BFMA1IIO0I
+)
+begin
+$display
+(
+""APBS:%0d PSEL not stable in both cycles""
+,
+ID
+)
+;
+BFMA1l01lI
+=
+1
+;
+end
+if
+(
+BFMA1O0O0I
+!=
+BFMA1I0O0I
+&
+BFMA1OOO0I
+==
+1
+\'b
+1
+)
+begin
+$display
+(
+""APBS:%0d PWDATA not stable in both cycles""
+,
+ID
+)
+;
+BFMA1l01lI
+=
+1
+;
+end
+if
+(
+BFMA1IIO0I
+!=
+1
+\'b
+1
+)
+begin
+$display
+(
+""APBS:%0d PSEL was not active in cycle before PENABLE""
+,
+ID
+)
+;
+BFMA1l01lI
+=
+1
+;
+end
+end
+if
+(
+BFMA1l01lI
+)
+begin
+$display
+(
+""APB Protocol violation (ERROR)""
+)
+;
+end
+end
+endmodule
+"
+"// ********************************************************************/
+// Actel Corporation Proprietary and Confidential
+// Copyright 2009 Actel Corporation.  All rights reserved.
+//
+// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
+// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
+// IN ADVANCE IN WRITING.
+//
+//
+// SPI Transmit/Receive control logic for channel
+// This was totally rewritten in Sept 09 for G4i
+//
+// Revision Information:
+// Date     Description
+//
+//
+// SVN Revision Information:
+// SVN $Revision: 21608 $
+// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
+//
+// Resolved SARs
+// SAR      Date     Who   Description
+//
+// Notes:
+// -----
+//
+// ********************************************************************/
+
+
+module spi_chanctrl # (
+  parameter CFG_SPH          = 0,
+  parameter CFG_SPO          = 0,
+  parameter CFG_SPS          = 0,
+  parameter CFG_MODE         = 0,
+  parameter CFG_CLKRATE      = 7,
+  parameter CFG_FRAME_SIZE   = 4,
+  parameter FIFO_DEPTH       = 4
+)
+(
+                       input         pclk,
+                       input         presetn,
+                       // SPI Interface
+                       input         spi_clk_in,
+                       output  reg   spi_clk_out,
+                       input         spi_ssel_in,
+                       output        spi_ssel_out,
+                       input         spi_data_in,
+                       output        spi_data_out,
+                       output        spi_data_oen,
+
+                       //FIFOs
+                       input  [5:0]  txfifo_count,
+                       input         txfifo_empty,
+                       output        txfifo_read,
+                       input [CFG_FRAME_SIZE-1:0]  txfifo_data,
+                       input         txfifo_last,
+                       input  [5:0]  rxfifo_count,
+                       output        rxfifo_write,
+                       output [CFG_FRAME_SIZE-1:0] rxfifo_data,
+                       output        rxfifo_first,
+
+                       //Configuration
+                       input         cfg_enable,
+                       input         cfg_master,
+                       input         cfg_frameurun,
+                       input         cfg_oenoff,
+                       input  [2:0]  cfg_cmdsize,
+
+                       //Status
+                       output        tx_alldone,
+                       output reg    rx_alldone,
+                       output        tx_underrun,
+                       output        rx_pktend,
+                       output reg    rx_cmdsize,
+                       output        active
+                     );
+
+
+
+localparam [3:0] MTX_IDLE1     = 4\'d0;
+localparam [3:0] MTX_IDLE2     = 4\'d1;
+localparam [3:0] MTX_MOTSTART  = 4\'d2;
+localparam [3:0] MTX_TISTART1  = 4\'d3;
+localparam [3:0] MTX_TISTART2  = 4\'d4;
+localparam [3:0] MTX_NSCSTART1 = 4\'d5;
+localparam [3:0] MTX_NSCSTART2 = 4\'d6;
+localparam [3:0] MTX_SHIFT1    = 4\'d7;
+localparam [3:0] MTX_SHIFT2    = 4\'d8;
+localparam [3:0] MTX_END       = 4\'d9;
+
+localparam       STXS_IDLE     = 1\'b0;
+localparam       STXS_SHIFT    = 1\'b1;
+
+
+//------------------------------------------------------------------------------------------------------
+// Simple Stuff
+
+localparam MOTMODE = ( CFG_MODE == 2\'b00);
+localparam TIMODE  = ( CFG_MODE == 2\'b01);
+localparam NSCMODE = ( CFG_MODE == 2\'b10);
+localparam MOTNOSSEL  = MOTMODE && ( CFG_SPH || CFG_SPS);
+localparam NSCNOSSEL  = NSCMODE && !CFG_SPH;
+
+localparam cfg_framesizeM1   = CFG_FRAME_SIZE - 1;
+
+//######################################################################################################
+// NEW BIT CONTROL ASSIGNMENTS
+//  NSC SPH force idle cycle
+//  NSC SPO free running clock
+//  NSC SPS Concatenate
+//  TI  SPH suppress SSEL
+//  TI  SPO free running clock
+
+
+//######################################################################################################
+// Declarations
+
+
+reg [15:0]  spi_clk_count;
+reg         spi_clk_next;
+reg         spi_clk_nextd;
+reg         spi_clk_tick;
+
+reg         cfg_enable_P1;
+wire        cfg_enableON;
+
+
+reg [4:0]   mtx_bitsel;
+reg         mtx_fiforead;
+reg [4:0]   mtx_bitcnt;
+reg         mtx_ssel;
+reg         mtx_lastframe;
+reg         mtx_consecutive;
+reg [2:0]   mtx_datahold;
+reg         mtx_oen;
+reg         mtx_spi_data_out;
+reg         mtx_spi_data_oen;
+reg         mtx_busy;
+reg         mtx_rxbusy;
+reg         mtx_holdsel;
+reg         mtx_first;
+reg         mtx_pktsel;
+reg         mtx_lastbit;
+reg         mtx_firstrx;
+reg         mtx_midbit;
+reg         mtx_alldone;
+
+reg         mtx_re;
+reg         mtx_re_q1;
+reg         mtx_re_q2;
+wire        mtx_re_d = mtx_re_q1 && !mtx_re_q2;
+
+reg         msrxs_strobe;
+reg [CFG_FRAME_SIZE-2:0]  msrxs_shiftreg;
+reg [CFG_FRAME_SIZE-1:0]  msrxs_datain;
+wire        msrxs_pktsel;
+reg         msrxs_ssel;
+reg         msrxp_strobe;
+reg [5:0]   msrxp_frames;
+reg         msrxs_first;
+reg         msrxp_pktend;
+reg         msrxp_alldone;
+
+reg         SYNC1_msrxp_strobe;
+reg         SYNC2_msrxp_strobe;
+reg         SYNC3_msrxp_strobe;
+reg         SYNC1_msrxp_pktsel;
+reg         SYNC2_msrxp_pktsel;
+reg         SYNC3_msrxp_pktsel;
+
+// AS: changed to wires (fixed)
+wire        cfg_clk_idle1;
+wire        cfg_clk_idle2;
+wire        cfg_clk_ph1;
+wire        cfg_clk_ph2;
+wire        cfg_clk_cap;
+wire        cfg_clk_end1;
+
+wire        clock_rx;
+wire        resetn_rx;
+wire        resetn_tx;
+
+reg         stxs_strobetx;
+reg         stxs_midbit;
+reg         stxs_direct;
+reg [CFG_FRAME_SIZE-1:0]  stxs_datareg;
+reg [4:0]   stxs_bitsel;
+reg [4:0]   stxs_bitcnt;
+wire        stxp_fiforead;
+reg         stxs_dataerr;
+reg         stxs_checkorun;
+reg         stxs_oen;
+reg         stxs_spi_data_out;
+reg         stxs_spi_data_oen;
+wire        stxp_strobe;
+wire        stxp_underrun;
+reg         stxp_lastframe;
+reg         stxs_txzeros;
+reg         stxs_first;
+reg         stxs_pktsel;
+wire        stxs_txready;
+reg         stxs_txready_at_ssel;
+reg         stxs_lastbit;
+
+
+reg         txfifo_davailable;
+reg         SYNC1_stxp_strobetx;
+reg         SYNC1_stxp_dataerr;
+reg         SYNC2_stxp_strobetx;
+reg         SYNC2_stxp_dataerr;
+reg         SYNC3_stxp_strobetx;
+reg         SYNC3_stxp_dataerr;
+reg         SYNC1_stxs_txready;
+reg         SYNC2_stxs_txready;
+
+wire        stxs_txready_re = txfifo_davailable && !SYNC1_stxs_txready;
+
+reg         spi_ssel_pos;
+reg         spi_ssel_neg;
+
+reg [CFG_FRAME_SIZE-1:0]  txfifo_datadelay;
+
+
+wire [CFG_FRAME_SIZE-1:0] txfifo_dhold;
+wire        busy;
+
+reg         msrx_async_reset_ok;
+reg         stx_async_reset_ok;
+
+reg [3:0]   mtx_state;
+reg         stxs_state;
+
+wire cfg_slave = ~cfg_master;
+
+reg         clock_rx_q1;
+reg         clock_rx_q2;
+reg         clock_rx_q3;
+reg         data_rx_q1;
+reg         data_rx_q2;
+reg         ssel_rx_q1;
+reg         ssel_rx_q2;
+
+wire spi_ssel_mux = ( cfg_master ? spi_ssel_out : ssel_rx_q2);
+
+wire spi_di_mux = (cfg_master ? spi_data_in : data_rx_q2); 
+
+wire clock_rx_re_slave = clock_rx_q2 && !clock_rx_q3;
+wire clock_rx_re       = (cfg_master ? mtx_re_d : clock_rx_re_slave);
+wire clock_rx_fe       = !clock_rx_q2 &&  clock_rx_q3;
+
+//######################################################################################################
+// Clock Generation
+
+// AS: added process to remove blocking assignments from synchronous process below
+always@ *
+begin
+  if (spi_clk_count[7:0] ==  CFG_CLKRATE)
+  begin
+    spi_clk_nextd =  (!spi_clk_next);
+  end
+  else
+  begin
+    spi_clk_nextd =  spi_clk_next;
+  end
+end
+
+always @(posedge pclk or negedge presetn)
+   begin
+   if (~presetn)
+      begin
+        spi_clk_count      <= 16\'b0;
+        spi_clk_next       <= 1\'b0;
+        spi_clk_tick       <= 1\'b0;
+      end
+   else
+      begin
+        //Not in Use
+        if ( !(cfg_enable && cfg_master))
+        begin
+            spi_clk_tick  <= 1\'b0;
+            spi_clk_count <= 16\'b0;
+        end
+        else
+        begin
+          if (spi_clk_count[7:0] ==  CFG_CLKRATE)
+          begin
+            spi_clk_count <= 16\'b0;
+          end
+          else
+          begin
+            // Default inc count
+            spi_clk_count <= spi_clk_count + 1;
+          end
+
+          // Edge Detects
+          spi_clk_next    <= spi_clk_nextd;
+          spi_clk_tick    <= spi_clk_nextd  ^ spi_clk_next;
+        end
+      end
+   end
+
+
+//######################################################################################################
+// Support features in both modes
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (~presetn)
+      begin
+        cfg_enable_P1 <= 1\'b0;
+      end
+   else
+      begin
+        cfg_enable_P1 <= cfg_enable;
+      end
+ end
+
+assign cfg_enableON = cfg_enable && cfg_enable_P1;   // delayed assertion of enable, to gate critical stuff
+
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (~presetn)
+      begin
+        mtx_re_q1 <= 1\'b0;
+        mtx_re_q2 <= 1\'b0;
+      end
+   else
+      begin
+\t\tmtx_re_q1 <= mtx_re;
+\t\tmtx_re_q2 <= mtx_re_q1;
+\t  end
+ end
+
+
+//######################################################################################################
+// Master Transmit Engine  runs of PCLK, max rate is PCLK/2
+
+
+generate
+    if(CFG_MODE == 0)  // MOTMODE
+      begin: mode_0
+        assign cfg_clk_end1  = CFG_SPO;
+        assign cfg_clk_idle1 = CFG_SPO;
+        assign cfg_clk_idle2 = CFG_SPO;
+        assign cfg_clk_ph1   = CFG_SPO ^ CFG_SPH;
+        assign cfg_clk_ph2   = !(CFG_SPO ^ CFG_SPH);
+        assign cfg_clk_cap   = CFG_SPO ^ CFG_SPH;
+      end
+    else if(CFG_MODE == 1)  // TIMODE
+      begin: mode_1
+        assign cfg_clk_end1  = 1\'b1;
+        assign cfg_clk_idle1 = CFG_SPO;
+        assign cfg_clk_idle2 = 1\'b0;
+        assign cfg_clk_ph1   = 1\'b1;
+        assign cfg_clk_ph2   = 1\'b0;
+        assign cfg_clk_cap   = 1\'b1;
+      end
+    else if(CFG_MODE == 2)  // NSCMODE
+      begin: mode_2
+        assign cfg_clk_end1  = 1\'b0;
+        assign cfg_clk_idle1 = 1\'b0;
+        assign cfg_clk_idle2 = CFG_SPO;
+        assign cfg_clk_ph1   = 1\'b0;
+        assign cfg_clk_ph2   = 1\'b1;
+        assign cfg_clk_cap   = 1\'b0;
+      end
+    else
+      begin: mode_default   // invalid!
+        assign cfg_clk_end1  = 1\'b0;
+        assign cfg_clk_idle1 = 1\'b0;
+        assign cfg_clk_idle2 = 1\'b0;
+        assign cfg_clk_ph1   = 1\'b0;
+        assign cfg_clk_ph2   = 1\'b0;
+        assign cfg_clk_cap   = 1\'b0;
+      end
+endgenerate
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+    begin
+      mtx_bitsel       <= cfg_framesizeM1;
+      mtx_state        <= MTX_IDLE1;
+      mtx_bitcnt       <= 5\'b00000;
+      mtx_fiforead     <= 1\'b0;
+      mtx_lastframe    <= 1\'b0;
+      mtx_consecutive  <= 1\'b0;
+      mtx_datahold     <= 3\'b000;
+      mtx_oen          <= 1\'b0;
+      mtx_busy         <= 1\'b0;
+      mtx_rxbusy       <= 1\'b0;
+      mtx_holdsel      <= 1\'b0;
+      mtx_ssel         <= 1\'b0;
+      mtx_first        <= 1\'b1;
+      mtx_pktsel       <= 1\'b0;
+      mtx_alldone      <= 1\'b0;
+      mtx_re           <= 1\'b0;
+    end
+    else
+    begin
+      //------------------------------------------------------
+      //This runs every clock
+      mtx_fiforead  <= 1\'b0;
+      mtx_alldone   <= 1\'b0;
+      mtx_re        <= 1\'b0;
+
+      //------------------------------------------------------
+      //Master Disabled so hold key signals inactive
+      if (!cfg_master || !cfg_enable)
+       begin
+         mtx_state  <= MTX_IDLE1;
+         mtx_pktsel <= 1\'b0;
+         mtx_first  <= 1\'b0;
+       end
+      //-----------------------------------------------------
+      //This runs at SPICLK rising and falling edges
+      // FSM has two phases aligned with data
+      //  Phase 1: first clock cycle that data is valid
+      //  Phase 2: second clock cycle that data is valid
+      //-----------------------------------------------------
+      else if (spi_clk_tick)
+       begin
+         mtx_ssel <= 1\'b0;
+         case (mtx_state)
+          MTX_IDLE1,MTX_IDLE2:
+                        begin
+                            // state assign
+                            if (mtx_state==MTX_IDLE1) mtx_state <= MTX_IDLE2;
+                            else mtx_state <= MTX_IDLE1;
+
+                            if (!txfifo_empty && cfg_master && cfg_enableON)            // AS: removed autostall check
+                            begin
+                              mtx_bitsel   <= cfg_framesizeM1;
+                              mtx_bitcnt   <= 5\'b00000;
+                              mtx_pktsel   <= 1\'b1;
+                              mtx_first    <= !mtx_holdsel;
+                                case (CFG_MODE)
+                                  0   : mtx_state <= MTX_MOTSTART;
+                                  1   : if (mtx_state==MTX_IDLE2)  mtx_state <= MTX_TISTART1;     // make sure stays aligned
+                                  2   : if (mtx_state==MTX_IDLE2)  mtx_state <= MTX_NSCSTART1;
+                                  default : begin end
+                                endcase
+                            end
+                            else
+                             begin
+                               mtx_oen <= 1\'b0;
+                               if (mtx_state==MTX_IDLE1) mtx_busy <= 1\'b0;                         // hold busy until we get to IDLE1
+                               if ((mtx_state==MTX_IDLE1) && (mtx_busy==1\'b0)) mtx_rxbusy <= 1\'b0; // Allows time for RX activity to complete
+                               mtx_pktsel <= mtx_holdsel;
+                               mtx_first  <= !mtx_holdsel;
+                             end
+                        end
+          MTX_MOTSTART: begin
+                          mtx_state  <= MTX_SHIFT1;
+                          mtx_oen    <= 1\'b1;
+                          mtx_busy   <= 1\'b1;
+                          mtx_rxbusy <= 1\'b1;
+                        end
+          MTX_TISTART1: begin
+                          mtx_state  <= MTX_TISTART2;
+                          mtx_oen    <= 1\'b1;
+                          mtx_rxbusy <= 1\'b1;
+                          mtx_busy   <= 1\'b1;
+                        end
+          MTX_TISTART2: begin
+                          mtx_state  <= MTX_SHIFT1;
+                          mtx_ssel   <= 1\'b0;
+                        end
+          MTX_NSCSTART1:begin
+                          mtx_state  <= MTX_NSCSTART2;
+                          mtx_oen    <= 1\'b1;
+                          mtx_busy   <= 1\'b1;
+                          mtx_rxbusy <= 1\'b1;
+                        end
+          MTX_NSCSTART2:begin
+                          mtx_state <= MTX_SHIFT1;
+                        end
+          MTX_SHIFT1 :  begin
+                         mtx_state  <= MTX_SHIFT2;
+                         mtx_ssel   <= mtx_ssel;
+\t\t\t\t\t\t mtx_re     <= 1\'b1;
+                         case (mtx_bitsel)
+                           3: begin
+                                mtx_datahold  <= txfifo_data[2:0];        // Hold data for last bits
+                              end
+                           2: begin
+                                mtx_fiforead  <= 1\'b1;                    // Advance read, since we are here not empty
+                                mtx_lastframe <= txfifo_last;
+                              end
+                           1: begin
+
+                                if (!txfifo_empty && !mtx_lastframe )      // more data - get ready to do back to back
+                                  begin
+                                    mtx_consecutive <= 1\'b1;
+                                  end
+                                 else
+                                  begin
+                                    mtx_consecutive <= 1\'b0;
+                                  end
+                              end
+
+                           default:
+                              begin
+                                 // Simply decrement the count until zero
+                              end
+                         endcase
+                       end
+          MTX_SHIFT2 : begin
+                          // if set at shift 1 hold value
+                          mtx_ssel    <= mtx_ssel;
+                          mtx_state   <= MTX_SHIFT1;
+                          // AS: added condition to avoid wraparound
+                          if (mtx_bitsel == 5\'b00000)
+                            mtx_bitsel <= cfg_framesizeM1;
+                          else
+                          begin
+                            mtx_bitsel  <= mtx_bitsel -1;
+                          end
+                          mtx_bitcnt  <= mtx_bitcnt +1;
+                          mtx_oen     <= 1\'b1;
+                          mtx_holdsel <= 1\'b0;
+
+                          if (NSCMODE && (mtx_bitcnt[3] || mtx_bitcnt[4] )) mtx_oen <= 1\'b0;
+
+                          case (mtx_bitsel)
+                           1: begin
+                                if (mtx_consecutive && TIMODE) mtx_ssel <= !CFG_SPH;
+                              end
+                           0: begin
+                                mtx_ssel      <= 1\'b0;
+                                mtx_first     <= 1\'b0;
+                                if (mtx_lastframe)
+                                   begin  // last frame so go through IDLE to END state
+                                     mtx_state   <= MTX_END;
+                                     mtx_oen     <= 1\'b0;    //not continuous so remove OEN
+                                     mtx_alldone <= 1\'b1;
+                                   end
+                                else
+                                   begin
+                                     if (mtx_consecutive)
+                                       begin  // Next data was available so lets output it
+                                         mtx_consecutive <= 1\'b0;
+                                         if ((TIMODE) || (MOTNOSSEL) || (NSCNOSSEL))
+                                           begin   // back to back frames
+                                             mtx_bitsel <= cfg_framesizeM1;
+                                             mtx_state  <= MTX_SHIFT1;
+                                             mtx_bitcnt <= 5\'b00000;
+                                             if (CFG_SPS && NSCMODE)
+                                              begin // Restart at receive phase
+                                                 mtx_bitsel <= cfg_framesizeM1-9;
+                                                 mtx_bitcnt <= 5\'b01000;
+                                              end
+                                           end
+                                         else
+                                           begin   // go through SSEL must be in MOT/NSC mode
+                                             mtx_state  <= MTX_END;
+                                             mtx_oen    <= MOTMODE;                   //make sure OEN stays on in MOT
+                                           end
+                                       end
+                                     else  //data was not ready do go back to IDLE  through END
+                                       begin
+                                         mtx_state   <= MTX_END;
+                                         mtx_oen     <= 1\'b0;      // turn off OEN as we dont have data
+                                         mtx_holdsel <= MOTMODE && CFG_SPS;  // see whether need to hold SSEL
+                                       end
+                                   end
+                              end
+                           endcase
+                        end
+          MTX_END    : begin
+                         mtx_state   <= MTX_IDLE2;        // Got to IDLE2 so TI/NSC mode alignment occurs
+                         mtx_pktsel  <= mtx_holdsel;      // unless we are holding SSEL must be end of packet
+                       end
+          default:     begin
+                         mtx_state <= MTX_IDLE1;
+                       end
+          endcase
+       end
+    end
+ end
+
+//-----------------------------------------------------------------------------------------------------
+// Based on the STATE value drive out the signals 1 PCLK cycle later
+//
+
+assign txfifo_dhold =  {txfifo_data[CFG_FRAME_SIZE-1:3] , mtx_datahold };
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+    begin
+      spi_clk_out      <= cfg_clk_idle1;
+      spi_ssel_pos     <= 1\'b1;
+      mtx_spi_data_oen <= 1\'b0;
+      mtx_spi_data_out <= 1\'b0;
+      mtx_lastbit      <= 1\'b0;
+      mtx_firstrx      <= 1\'b0;
+      mtx_midbit       <= 1\'b0;
+    end
+   else
+    begin
+       // Control Lines
+       case (mtx_state)
+        MTX_IDLE1   : begin
+                        spi_clk_out      <= cfg_clk_idle1;
+                        spi_ssel_pos     <= !(TIMODE || mtx_holdsel);
+                        mtx_spi_data_oen <= mtx_oen;
+                      end
+        MTX_IDLE2   : begin
+                        spi_clk_out      <= cfg_clk_idle2;
+                        spi_ssel_pos     <= !(TIMODE || mtx_holdsel);
+                        mtx_spi_data_oen <= mtx_oen;
+                      end
+        MTX_MOTSTART :begin
+                        spi_clk_out      <= cfg_clk_idle1;
+                        spi_ssel_pos     <= 1\'b0;
+                        mtx_spi_data_oen <= 1\'b0;
+                      end
+        MTX_TISTART1: begin
+                        spi_clk_out      <= cfg_clk_ph1;
+                        spi_ssel_pos     <= 1\'b1;
+                        mtx_spi_data_oen <= 1\'b0;
+                      end
+        MTX_TISTART2: begin
+                        spi_clk_out      <= cfg_clk_ph2;
+                        spi_ssel_pos     <= 1\'b1;
+                        mtx_spi_data_oen <= 1\'b1;
+                      end
+        MTX_NSCSTART1:begin
+                        spi_clk_out      <= cfg_clk_ph1;
+                        spi_ssel_pos     <= 1\'b1;
+                        mtx_spi_data_oen <= 1\'b0;
+                      end
+        MTX_NSCSTART2:begin
+                        spi_clk_out      <= cfg_clk_ph2;
+                        spi_ssel_pos     <= 1\'b0;
+                        mtx_spi_data_oen <= 1\'b1;
+                      end
+        MTX_SHIFT1  : begin
+                        spi_clk_out      <= cfg_clk_ph1;
+                        spi_ssel_pos     <= (TIMODE && mtx_ssel);
+                        mtx_spi_data_oen <= 1\'b1 && mtx_oen;
+                      end
+        MTX_SHIFT2  : begin
+                        spi_clk_out      <= cfg_clk_ph2;
+                        spi_ssel_pos     <= (TIMODE && mtx_ssel);
+                        mtx_spi_data_oen <= 1\'b1 && mtx_oen;
+                      end
+        MTX_END     : begin
+                        spi_clk_out      <= cfg_clk_end1;
+                        spi_ssel_pos     <= 1\'b0;
+                        mtx_spi_data_oen <= MOTMODE || TIMODE;   // should be held on here
+                      end
+        default :     begin //Unused states
+                        // AS: replaced with 0\'s for consistency
+                        spi_clk_out      <= 1\'b0;
+                        spi_ssel_pos     <= 1\'b0;
+                        mtx_spi_data_oen <= 1\'b0;
+                      end
+       endcase
+
+       // Data Lines
+       //$display(""mtx_bitsel %0d"", mtx_bitsel);
+       mtx_spi_data_out <= txfifo_dhold[mtx_bitsel] ;
+       if (NSCMODE && (mtx_bitcnt[4] || mtx_bitcnt[3]) ) mtx_spi_data_out <= 1\'b0;
+
+       // RX capture
+       mtx_lastbit <= (mtx_bitsel == 5\'b00000);  // Used to assert RX strobe
+       mtx_midbit  <= (mtx_bitsel == 5\'b00010);  // Used to deassert RX strobe
+       mtx_firstrx <= mtx_first;
+
+
+  end
+ end
+
+assign tx_alldone = mtx_alldone || (cfg_slave && msrxp_alldone);
+
+
+always @(negedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+    begin
+      spi_ssel_neg <= 1\'b1;
+    end
+   else
+    begin
+      spi_ssel_neg <= spi_ssel_pos;
+    end
+ end
+
+assign  spi_ssel_out = (NSCMODE ? spi_ssel_neg :  spi_ssel_pos);
+
+
+
+
+//######################################################################################################
+// Slave Transmitter logic
+// Always clocks on oppoisite edge to recieve logic
+
+// NOTE THERE IS ONLY A CLOCK WHEN DATA IS MOVING SYNCRONISING ACCROSS CLOCK DOMAINS IS HARD
+// THIS CLOCKS ON OPPOSITE EDGE TO THE MASTER/SLAVE RECEIVER
+
+// Internally we have two counters
+//   bitcnt counts up from 0 when shifting
+//   bitsel counts down from framesize-1
+
+
+// Synchroniser
+//always @(negedge clock_rx or negedge resetn_tx)
+//always @(posedge pclk or negedge resetn_tx)
+// begin
+//   if (!resetn_tx)
+//    begin
+//       SYNC1_stxs_txready <= 1\'b0;
+//       SYNC2_stxs_txready <= 1\'b0;
+//    end
+//   else
+//    begin
+//     if (clock_rx_fe)
+//     begin
+//       SYNC1_stxs_txready <= txfifo_davailable;
+//       SYNC2_stxs_txready <= SYNC1_stxs_txready;
+//     end
+//    end
+// end
+
+//assign stxs_txready = SYNC2_stxs_txready;
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+    begin
+       SYNC1_stxs_txready <= 1\'b0;
+    end
+   else
+    begin
+       SYNC1_stxs_txready <= txfifo_davailable;
+   end
+ end
+
+ //assign stxs_txready = SYNC2_stxs_txready;
+assign stxs_txready = txfifo_davailable;
+
+// Handle case that no initial shift clock
+// This is clocks as SEL is released
+always @(posedge resetn_rx)
+ begin
+   stxs_txready_at_ssel <= txfifo_davailable;
+ end
+
+
+// The FSM  only needed in slaves
+//always @(negedge clock_rx or negedge resetn_tx)
+always @(posedge pclk or negedge resetn_tx)
+ begin
+  if (!resetn_tx)
+   begin
+      stxs_state      <= STXS_IDLE;
+      stxs_strobetx   <= 1\'b0;
+      stxs_midbit     <= 1\'b0;
+      stxs_direct     <= 1\'b1;
+      stxs_datareg    <= {(CFG_FRAME_SIZE-1){1\'b0}};
+      stxs_bitsel     <= 5\'b00000;
+      stxs_bitcnt     <= 5\'b00000;
+      stxs_dataerr    <= 1\'b0;
+      stxs_checkorun  <= 1\'b0;
+      stxs_oen        <= 1\'b0;
+      stxs_first      <= 1\'b0;
+      stxs_txzeros    <= 1\'b0;
+      stxs_pktsel     <= 1\'b0;
+      stxs_lastbit    <= 1\'b0;
+   end
+  else
+   begin
+\tif (stxs_txready_re && (stxs_bitcnt == 5\'b00000)) // data now available in tx FIFO and still on first bit
+\tbegin
+\t\tstxs_datareg   <= txfifo_data[CFG_FRAME_SIZE-1:0]; // reload with valid data
+\tend
+    if (clock_rx_fe)
+    begin
+      stxs_strobetx  <= 1\'b0;
+      stxs_midbit    <= 1\'b0;
+      stxs_lastbit   <= 1\'b0;
+      case (stxs_state)
+         STXS_IDLE:
+           begin
+             stxs_bitcnt    <= 5\'b00000;
+             stxs_datareg   <= {txfifo_datadelay[CFG_FRAME_SIZE-2:0] , 1\'b0};         //Sample the Data, check ready flag in two clocks time
+             stxs_dataerr   <= 1\'b0;
+             stxs_checkorun <= !cfg_frameurun;                          //if auo mode not enabled check for orun conditions
+             stxs_dataerr   <= 1\'b0;
+             stxs_first     <= 1\'b1;
+             stxs_txzeros   <= 1\'b0;
+             stxs_direct    <= 1\'b1;  //  !NSCMODE;
+             stxs_oen       <= TIMODE && msrxs_ssel;
+             if ((cfg_slave && cfg_enableON && ( MOTMODE || NSCMODE ||  (TIMODE && msrxs_ssel==1\'b1))))
+               begin //About to transmit, but not sure until we see next clock edge
+                  stxs_state   <= STXS_SHIFT;
+                  stxs_bitsel  <= cfg_framesizeM1;
+                  stxs_oen     <= !NSCMODE;
+                  stxs_pktsel  <= 1\'b1;
+                  if (MOTMODE && !CFG_SPH)   // no initial shift edge
+                    begin
+                      stxs_bitsel  <= cfg_framesizeM1-1;
+                      stxs_bitcnt  <= 5\'b00001;
+                      stxs_direct  <= 1\'b0;
+                    end
+               end
+           end
+         STXS_SHIFT:
+           begin
+             stxs_bitcnt  <= stxs_bitcnt +1;
+             stxs_bitsel  <= stxs_bitsel -1;
+             if (!stxs_direct) stxs_datareg <= {stxs_datareg, 1\'b0};     // Shift
+             stxs_direct  <= 1\'b0;
+             //----------------------------------------------------------------------
+             case (stxs_bitcnt)
+               1 : begin                    // At this point we can see whether we actually sampled valid data from the FIFO
+                     stxs_midbit  <= 1\'b1;  // clear the RX strobe, stays in S clock domain
+\t\t\t\t\t   // If no initial shift then we need to check value at SSEL going inactive
+                       if (       ( (MOTMODE && CFG_SPH==1\'b0 && stxs_first) && stxs_txready_at_ssel && !stxs_dataerr )
+                               || (!(MOTMODE && CFG_SPH==1\'b0 && stxs_first) && stxs_txready && !stxs_dataerr)  ) // Got good data and not failed before
+                       begin
+                         stxs_strobetx  <= 1\'b1;
+                         stxs_checkorun <= 1\'b1;              // Check for overrun from now on
+                       end
+                     else
+                       begin                               // Data was not available, see if checking report
+                         stxs_dataerr <= stxs_checkorun;
+                         stxs_txzeros <= 1\'b1;
+                       end
+                   end
+               2 : begin
+                    stxs_strobetx <= stxs_strobetx;      // if asserted hold strobe for second cycle
+                   end
+               7: begin
+                   stxs_oen <= 1\'b1; //Turn on OEN slave TXT in NSC mode, on in other modes anyway
+                  end
+             endcase
+             //-----------------------------------------------------------------------
+
+
+             case (stxs_bitsel)
+                1: begin
+                    stxs_lastbit <= 1\'b1;
+                   end
+                0: begin
+                     stxs_oen    <= !NSCMODE;
+                     stxs_first  <= 1\'b0;
+                     stxs_direct <= 1\'b1;
+                     stxs_oen    <= 1\'b0;
+                     if (  (TIMODE && msrxs_ssel==1\'b1)                 // If TI Mode and SSEL start again
+                         || (MOTMODE)                                  // Start again unless reset
+                         || (NSCMODE)                                  // Start again unless reset
+                        )
+                       begin // CLOCK EDGE OF NEXT FRAME TRANSMIT AGAIN
+                         stxs_bitsel    <= cfg_framesizeM1;
+                         stxs_bitcnt    <= 5\'b00000;
+                         stxs_direct    <= 1\'b0;
+                         stxs_datareg   <= txfifo_data[CFG_FRAME_SIZE-1:0];           //Next frame, This time no need for direct operation
+                         stxs_oen       <= TIMODE && msrxs_ssel;
+                         stxs_pktsel    <= 1\'b1;
+                       end
+                     else
+                       begin
+                         stxs_pktsel <= 1\'b0;
+                         stxs_state  <= STXS_IDLE;
+                         stxs_oen    <= 1\'b0;
+                       end
+                   end
+                default:
+                   begin
+                   end
+             endcase
+           end
+      endcase
+    end
+   end
+ end
+
+// Work out that to output
+always @(*)
+ begin
+    if (stxs_txzeros)     stxs_spi_data_out = 1\'b0;
+    else if (stxs_direct) stxs_spi_data_out = txfifo_datadelay[cfg_framesizeM1];
+    else                  stxs_spi_data_out = stxs_datareg[cfg_framesizeM1];
+
+    //OEN is little complicated
+    case (CFG_MODE)
+      0 : begin //MOT
+                stxs_spi_data_oen = !ssel_rx_q2;
+              end
+      1 : begin //TI
+                stxs_spi_data_oen = stxs_oen;
+              end
+      2 : begin //NSC
+                stxs_spi_data_oen = (!ssel_rx_q2 && stxs_oen);
+              end
+      default :
+              begin
+                stxs_spi_data_oen = 1\'bx;
+              end
+    endcase
+    if (!cfg_slave || !cfg_enableON) stxs_spi_data_oen = 1\'b0;
+
+ end
+
+
+
+// SYNC the Strobes back to PCLK
+always @(posedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+    begin
+       SYNC1_stxp_strobetx   <= 1\'b0;
+       SYNC1_stxp_dataerr    <= 1\'b0;
+       SYNC2_stxp_strobetx   <= 1\'b0;
+       SYNC2_stxp_dataerr    <= 1\'b0;
+       SYNC3_stxp_strobetx   <= 1\'b0;
+       SYNC3_stxp_dataerr    <= 1\'b0;
+    end
+   else
+    begin
+       SYNC1_stxp_strobetx   <= stxs_strobetx;
+       SYNC1_stxp_dataerr    <= stxs_dataerr;
+       SYNC2_stxp_strobetx   <= SYNC1_stxp_strobetx;
+       SYNC2_stxp_dataerr    <= SYNC1_stxp_dataerr;
+       SYNC3_stxp_strobetx   <= SYNC2_stxp_strobetx;
+       SYNC3_stxp_dataerr    <= SYNC2_stxp_dataerr;
+    end
+ end
+
+
+assign stxp_strobe   =  SYNC2_stxp_strobetx && ~SYNC3_stxp_strobetx;
+assign stxp_fiforead =  stxp_strobe;
+assign stxp_underrun =  SYNC2_stxp_dataerr && ~SYNC3_stxp_dataerr;
+
+
+
+// The HW Status Register is effectivly sampled at the start of a transfer
+// The SPICLK domain will sample after this time
+// The TXDATA is also delayed by a clock cycle to make sure its on Q of register, FIFO\'s have muxes on outputs
+
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+    begin
+       txfifo_davailable <= 1\'b0;
+       txfifo_datadelay  <= {CFG_FRAME_SIZE{1\'b0}};
+       stxp_lastframe    <= 1\'b0;
+    end
+   else
+    begin
+       // AS: removed userstatus
+       txfifo_davailable <= !txfifo_empty;
+       txfifo_datadelay  <= txfifo_data;
+       if (stxp_strobe) stxp_lastframe <= txfifo_last;      //remember that we are doing last bit
+\t   if (!cfg_slave)  stxp_lastframe <= 1\'b0;\t\t\t\t//make sure off in if not in slave mode
+    end
+ end
+
+
+//######################################################################################################
+// Select Outputs based on mode
+
+assign  txfifo_read  = ( cfg_master ? mtx_fiforead : stxp_fiforead);
+
+
+assign  spi_data_out = ( cfg_slave ? stxs_spi_data_out :  mtx_spi_data_out);
+wire    spi_data_oex = ( cfg_slave ? stxs_spi_data_oen :  mtx_spi_data_oen);
+assign  spi_data_oen = spi_data_oex && !cfg_oenoff;
+
+
+assign  busy        = (mtx_busy || mtx_rxbusy || (stxs_state != STXS_IDLE) || (cfg_master && !txfifo_empty) );
+assign  active      = busy;
+assign  tx_underrun = stxp_underrun;
+
+
+//######################################################################################################
+//Receive logic
+
+//Reduce the combinational logic clock driving the ASYNC resets
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+   begin
+      msrx_async_reset_ok <= 1\'b0;
+      stx_async_reset_ok <= 1\'b0;
+   end
+   else
+   begin
+      msrx_async_reset_ok <= cfg_enable && !TIMODE;
+       stx_async_reset_ok <= cfg_enable && !TIMODE && cfg_slave;
+   end
+end
+
+// AS: removed testmode
+assign resetn_rx = ~(!presetn || (spi_ssel_mux && msrx_async_reset_ok) );
+assign resetn_tx = ~(!presetn || (ssel_rx_q2  && stx_async_reset_ok)) ;
+
+//Instantiate the clock mux for synthesis etc
+
+spi_clockmux UCLKMUX1 (
+                   .sel     (cfg_master),
+                   .clka    (spi_clk_in),
+                   .clkb    (spi_clk_out),
+                   .clkout  (clock_rx_mux1)
+                  );
+
+wire  clock_rx_mux2 = (cfg_clk_cap ^ clock_rx_mux1);\t\t// Clock inversion when needed
+
+
+assign clock_rx = clock_rx_mux2;
+
+//-------------------------------------------------------------------------
+always @(posedge pclk or negedge presetn)
+begin
+    if (!presetn)
+    begin
+        clock_rx_q1 <= 1\'b0;
+        clock_rx_q2 <= 1\'b0;
+        clock_rx_q3 <= 1\'b0;
+
+        data_rx_q1 <= 1\'b0;
+        data_rx_q2 <= 1\'b0;
+
+        ssel_rx_q1 <= 1\'b0;
+        ssel_rx_q2 <= 1\'b0;
+\tend
+    else
+    begin
+        clock_rx_q1 <= clock_rx;
+        clock_rx_q2 <= clock_rx_q1;
+        clock_rx_q3 <= clock_rx_q2;
+\t\t
+        data_rx_q1 <= spi_data_in;
+        data_rx_q2 <= data_rx_q1;
+\t\t
+        ssel_rx_q1 <= spi_ssel_in;
+        ssel_rx_q2 <= ssel_rx_q1;
+    end
+end
+
+//-------------------------------------------------------------------------
+
+// The msrxs_datain register must not be reset by the next frame select,
+
+//always @(posedge clock_rx or negedge presetn)
+always @(posedge pclk or negedge presetn)
+begin
+  if (!presetn)
+    begin
+      msrxs_strobe    <= 1\'b0;
+      msrxs_datain    <= {(CFG_FRAME_SIZE){1\'b0}};
+      msrxs_shiftreg  <= {(CFG_FRAME_SIZE-1){1\'b0}};
+      msrxs_first     <= 1\'b0;
+      msrxs_ssel      <= 1\'b0;
+    end
+  else
+    begin
+    if (clock_rx_re)
+    begin
+       msrxs_ssel      <= ssel_rx_q2 & cfg_enableON;
+\t   msrxs_shiftreg  <=  { msrxs_shiftreg[CFG_FRAME_SIZE-3:0], spi_di_mux};//spi_di_mux};
+       if (stxs_midbit || mtx_midbit )  msrxs_strobe <= 1\'b0;
+       if (TIMODE && spi_ssel_mux) msrxs_shiftreg  <= 31\'b00000; \t // Start of Cycle clear shift reg, no data at SSEL
+       if (stxs_lastbit ||  mtx_lastbit )
+         begin
+            msrxs_first     <= mtx_firstrx || (cfg_slave && stxs_first);
+            msrxs_shiftreg  <= {(CFG_FRAME_SIZE-1){1\'b0}};
+            msrxs_datain    <= { msrxs_shiftreg[CFG_FRAME_SIZE-2:0], spi_di_mux};
+            msrxs_strobe    <= 1\'b1;
+         end
+    end
+    end
+end
+
+// Note mrsx_ssel samples ssel for TI mode at the -ve clock edge for the stx FSM to use on +ve clock edge
+
+// msrxs_strobe pulse high every frame whether good or bad!
+
+assign msrxs_pktsel = stxs_pktsel || mtx_pktsel;
+
+// Data is held valid accross FIFO write pulse by design
+assign rxfifo_data   = msrxs_datain;
+assign rxfifo_first  = msrxs_first;
+
+// SYNC the Strobe back to PCLK  and write to FIFO
+// Used in both master and slave modes to write data to FIFO
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+    begin
+      SYNC1_msrxp_strobe <= 1\'b1;
+      SYNC2_msrxp_strobe <= 1\'b1;
+      SYNC3_msrxp_strobe <= 1\'b1;
+      SYNC1_msrxp_pktsel <= 1\'b0;
+      SYNC2_msrxp_pktsel <= 1\'b0;
+      SYNC3_msrxp_pktsel <= 1\'b0;
+    end
+   else
+    begin
+      SYNC1_msrxp_strobe <= msrxs_strobe;
+      SYNC2_msrxp_strobe <= SYNC1_msrxp_strobe;
+      SYNC3_msrxp_strobe <= SYNC2_msrxp_strobe;
+      SYNC1_msrxp_pktsel <= msrxs_pktsel;
+      SYNC2_msrxp_pktsel <= SYNC1_msrxp_pktsel;
+      SYNC3_msrxp_pktsel <= SYNC2_msrxp_pktsel;
+    end
+end
+
+always @(posedge pclk or negedge presetn)
+ begin
+   if (!presetn)
+    begin
+      msrxp_strobe    <= 1\'b0;
+      msrxp_pktend    <= 1\'b0;
+      msrxp_alldone\t  <= 1\'b0;
+      rx_alldone      <= 1\'b0;
+    end
+   else
+    begin
+      msrxp_strobe  <= 1\'b0;
+      msrxp_pktend  <= 1\'b0;
+      msrxp_alldone <= 1\'b0;
+      if ( SYNC2_msrxp_strobe && ~SYNC3_msrxp_strobe )
+       begin
+              msrxp_strobe  <= 1\'b1;
+              msrxp_alldone <= mtx_lastframe || stxp_lastframe;    // consistent with write strobe
+       end
+
+      if  (~SYNC2_msrxp_pktsel && SYNC3_msrxp_pktsel)       //
+       begin
+            msrxp_pktend <= 1\'b1;
+       end
+
+       rx_alldone <=  msrxp_alldone ;   // let write to FIFO complete before setting done
+
+    end
+end
+
+assign rxfifo_write =  msrxp_strobe;
+wire   msrxp_pktsel =  SYNC2_msrxp_pktsel;
+
+
+//######################################################################################################
+// FIFO Level Checkers
+
+reg [2:0] tmp;
+always@*
+begin
+  tmp = msrxp_frames+1;
+end
+
+
+always @(posedge pclk or negedge presetn)  // Register as this feeds into lots of logic
+begin
+  if (~presetn)
+  begin
+    msrxp_frames <= 6\'b000000;
+    rx_cmdsize   <= 1\'b0;
+  end
+  else
+  begin
+    rx_cmdsize   <= 1\'b0;
+    if (msrxp_pktsel==1\'b0)
+    begin
+      msrxp_frames <= 6\'b00000;
+    end
+    else if (msrxp_strobe)
+    begin
+      msrxp_frames <= {3\'b000, tmp};
+      rx_cmdsize   <= (tmp == cfg_cmdsize);
+    end
+  end
+end
+
+
+assign  rx_pktend  = msrxp_pktend;
+
+endmodule
+"
+"module spi_clockmux ( input      sel,
+                  input      clka,
+                  input      clkb,
+                  output reg clkout
+                );
+
+
+ always @(*)
+ begin
+     case (sel) //synopsys infer_mux
+         1'b0    : clkout = clka;
+         1'b1    : clkout = clkb;
+         default : clkout = clka;
+     endcase
+ end
+
+endmodule"
+"\xb6\xa6\xf2\x08F\x00\x00\x00<\x00\x00\x00\x03\x00\x00\x00\x08\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x16\x00\x00\x00\xd6j5@\xd6j5@\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00mPBnQAmN<lK8tS@\x82aN\x85fT\x81bP\x80aM|]IxYEuVBtS@sR?wVC{ZGzVFvUDtUCoTAnS@rWDvYGtUCrUClO=jM;oR@uXFvYGsVDqTBoS>jO<gL9fM9jP?mRAkP?jM=oRDnQCkOCiNCfNDfPEfRIgSJeRKdRHbNCbL?bJ>dM?hQClUGlUGpVGoUFnRDqTDwZJyZHvWEy\\Lz]M{`Oz_NrWFiN=jM?kN>mN<pO<{ZG\x87fS\x87hV\x81bP\x81bN\x7f`L{\\HvWCsT@sT@uVBxYEtSBnO=kN<jM;gL9iN;mP>mN<hK9dG5bE3eH6hK9gJ8dG5bE3cF4`E2^C0[B.[A0[@/Z?.Y<,X;-X;-X<0W<1V>2V@5T@7UA8M<4O=3SA7XD9]G<^H;bL?gOChQClUGoUFnTEqVEwZJ|\\M{\\Jz]M|_O|aPy^MuZIsXGjM?jM=nO=xWD\x85dQ\x8ckX\x87hV\x80aOz[I|]Kz[IuVDtUCwXFxYGwXFkL:`A/Y<*Y<*V;(V9\'Y<*Y<*V9\'U8&V9\'Y<*\\?-\\?-[>,[>,X;)Z=+Z?,X=*U:\'P5""N1!L/\x1fK.\x1eL/!L0""L2%J2&I3(G3(G3*@/\'A0(G6.Q@6WE;WE;[G<_K@gQDlVIqZLsYLvZL}`P\x82eU\x85eV|_O~aQ{`Ow\\Kw\\K|aPmPBmP@uVD\x81`M\x8aiV\x8bjW\x84eS~_MtUCvWEuVDsTBsVDx[IvYGqTB_B2P3#G*\x1aG*\x18E(\x16D\'\x15H+\x19K.\x1cO2 Q4""U8&Z=+]@.`C1bE3dG5^A/aD2bG4cH5`E2Z?,V9\'S6$Q4$P3#M1#K1$H1#H2%G3(H4)D3+@2)C5,L=6PA:Q@8TC9[I?eQFjVKpZMt]Oy_R\x80dV\x87jZ\x89l\\~aQ|_Ow\\KuZIx]L|aPpSEsVF|]K\x86eR\x8aiV\x86eR\x80aO|]KtTEuUFqTDpSCtWGv[JpUDeJ9U:)E*\x19?""\x12A$\x14B%\x13D\'\x15K.\x1cP3!Z=-^A1cF6fI9iL<lO?qTDtWGtUCqTBpSAoTAoTAnQ?jN9iJ6^A/Z=-S8\'M3$I2$H2%H5\'J6+F5+C2*C4-G:4K>8K>6OA8TF=`NDcQGiUJoYLu^P~dW\x84hZ\x87j\\\x7fbRwZJrWFv[Jy^Mx]LqTFwZJ\x81bP\x87fS\x87fS\x82aN}^L{\\JsSDqTDpSCrUEuZItYHhN=[A0K1""A%\x17?#\x15G*\x1aL/\x1fR5#[>,`E2eH8iL<lO?nQApSCuXH{^N~aQ\x84eS|_MvYGsXCuZEy]Hx\\GxYEnQ?iL:aF5X>/O8(I3%E2$C0""C1%A0&@3+C82G<6J?9NA9RD;ZIA]LDcQGiUJs[O{aT\x80dV\x82fX\x81dTvYIqVEw\\Kz_Nv[JrUGz]M\x83dR\x86eR\x84cP\x7f^K{\\JxYGpSEpSEqTFsWItXJmSD_E6R;+D-\x1fB(\x19I-\x1fU8([>.bE3hM:kP=iL<lO?nQAnQAoRBuXH|_O\x7fbR\x82cQ|]KsVDrVAuYDy]H|]H|]Hy]Hx[ItYFmSBbK;V@2J7(D1#B/!B0$@2)?4.C:3J?9OB:QC:UF?YJCaPHiULoYNu]Q}cV\x82fX\x83fV{^NuZIw\\Ky^Mx]LtWI|_O\x84eS\x85dQ\x82aN~]JyZHuVDsVHrUGtWIuYKpVGcI:R;+H1!E. H.!S7)`C5gJ:kN<nS@nS@oRBqTDqTDnQAmP@rUEx[K{^NxYGtUCoR@pT?tXCw[Fz[FyZEx\\G|_M\x7fdQ~dSu^NgQCVC4M:+G1#E3\'@2):/)=4-G<6M@8N@7PC=WHA`OGgUKmWLrZN{aT\x82fZ\x86iY\x80cSx]Lv[Jw\\Ky^M{^N\x83dR\x87fS\x84cP\x80_L~]Jz[IsVFrUEtWGw\\Kv[JmRA^C2R8\'N4#I2""S9*]C4gL;nSBsVFrUCpQ?oRBoRBoRBmP@lO?nQArUEvYIpUDmRAkN>lO=nQ?rUCuVDuVBuYDx\\G|_M\x7fdQ\x80eRz`OlRA`F5R;+K5\'A/#=/&D7/L?9M@:I<6K@<TIC\\OIaRKiXPp\\Qw`R~dU\x83hU~cRz^Px\\Nx\\Nx\\N\x7fbR\x86gU\x89hU\x85dQ\x80_L|[HwXFpSCqTDtWGwZJsXGgL;Y>-Q6%N4#V<-]C4gM>pUDv[JwZJrUEoP>mP@nQAnQAmP@kN>kN>mP@nQAjM=jM=iL<iL:lM;nO=oP>pQ?sT@tXCz^I\x81eP\x85hV\x81fSz_LtYF`F5R;+D1#B1\'E7.H;3I<4H;3K>8RE?VIC\\MFfTJlXMu^P\x7feV\x82gT\x82gV|`RtXJsWIx\\N\x83dR\x86gU\x88gT\x84cP\x7f^K{\\HwXFqTBrUEuXHwZJoTCaF5T9(P5$S8\'`F7gM>pTFw\\K|_Oz]MsVFmM>lO?mP@mP@mP@lO?jM=iL<hK;jJ;kK<lL=kK<jK9kJ9kJ9lK:nO:pQ<vWB~_K\x83dP\x82fQ\x85iT\x88lWx]JdJ9P9)H5\'F6)E7,H:1M?6L=6O@9RC<ZIAcQGkUHt]O\x81gX\x87lY\x8bp]\x84iXuYKqUGx\\N\x86eT\x87fU\x86eT\x80_N{\\JyZHwXFsVDtWEwZHvYGkN<[@-Q6#S8%Y>+fK:jO>pUDv[Jz]My\\LqTDjM=lO?lO?mP@nQAnQAmP@kN>iL<oO@pPApPAqPAoN?mL;lK:kJ9nN9mM8pP;wWBzZE}]H\x87gR\x91q\\\x8cmYw[F_F2M6&B/ @. G7*P@3M>7O@9QB;ZIAbPFiSFr[M\x82hY\x87lY\x8cq`\x88m\\z^PtXJy]Q\x89hW\x87fU\x83bQ{\\JwXFvWEvWEuVDxYGwZHrUCfI7Y<*S8%Y>+`E2jO>lQ@pSCrUEtWGtWGpSCkN>kN>kN>lO?nQAoRBpSCoRBoRBsSFrRErRCtSDtSDsRCoN=lK:oO:nN9pP;uU@uU@vVA\x7f_J\x8djT\x94t_\x8clWx\\G`E2J3!E/!H6(O?2M>7O@9QB;YH@aOEeQFpYK}fV\x80eT\x83hW\x84iX\x80dV|`Rz^R\x88eR\x84aN}\\KwXFsVDtWEvZEz[G{\\Jz[IsTBfI7^A/^A/dG5iN;oRBpSCqTDpSCpSCqTFoRDmPBjM?kN@lOAnQCoRDqTFrUGsVHsSFrREqQDsSDtTEuTErQBoN?nN9oO:qQ<tT?sS>tQ=yV@\x7f\\F\x8ejT\x94q[\x8foZyZF\\A.J3#F3$H6(J;4M>7O@9TE>\\KCaOEjTGu_R~dW~dW\x82hY\x85k\\\x81gX{aR\x85`N\x80]JyXGuUFrUEsVDvZEz[G{\\JxYGpQ?fI7dG5hK9lO=nQ?pSArUErUEoRBnQAnQCnQCmPBkN@lOAnQCoRDoRDpSErUGtWIqTFpSEpSEqTFsSDsSDqQBpPApQ=pQ=qP=pO<oO:qN:tQ=vS?\x81[F\x8fkU\x9av`\x8flXoP<O5$A+\x1d@-\x1fE82J=7L?9NA;UF?\\KCcQEmYN~cZ~cX\x82h[\x86l]\x84jY}cR\x88cQ\x83`M{ZIsVFqTDpSAqU@tUAwXDsT@kL8fG3eI4kO:mQ<mQ<oP>rSAsSDoRBlO?lOAlOAlOAlOAnQCpSEqTFpSEpSEqTFsVHrVHrVHtWIsVHqTDoRBqQBqQBwXFuVDqR>mL9kJ7oO:tQ=vS?\x85_J\x96p[\xa8\x82m\xa4\x81m\x83dP]B1H2$G4&C60I<6J=7K>8PC;ZIAbPFjVKv[Tx]T}cV\x82hY\x83iX\x80fU\x81`M|]IxYGsVFqTDpSCpSAsTBrVAlO=eH6dG5iL:oRBpSCoRBpSCoRBnQAoRBoRDmPBnQCoRDpSEpSEoRDoRDnRDoSEpTFpTFqUGrVHsWIrVHqUGpTFoSEoSEpVGsXGrWFmR?kO:nO:pQ<qS;|\\E\x8cgT\xa8~n\xb5\x8cz\xa1{fyZEW@.E3%C6.I>:H=;F;7PC;VH=ZIAaNHoTYw]\\|c\\~gW\x82hW\x81gV~]Jz[GuVDqTDpSCpSCqTBsTBkO:eH6`C1cF4jM;oRBrUEtWGrUEoRBnQAoRBoRDoRDoRDpSEpSEpSEoRDoRDnRDoSEpTFqUGpTFrVHsWIsWIrVHqUGpTFoSErXIuYKsXGoTAlP;nO:oP;nP8{[D\x88cP\xa4{i\xba\x91}\xb4\x8ew\x94v^mT@P=.D7/K>8J<;G<8OB9SE:VE;[JBjQTtZYyaW{dT\x80fU\x7ffR}\\IyZFuVDpSCpSCqTDqTBsTBgK6`C1^A/dG5kN<oRBsVFwZJtWGpSCmP@nQAoRDpSEpSEqTFpSEoRDoRDoRDoSEoSEpTFqUGpTFrVHsWItXJsWIrVHqUGqUGsYJuYKtYHpUBmP>nO;nO:nO:uU>\x7f[E\x97q\\\xb5\x8cv\xbd\x98~\xa9\x8an\x7ffP[F3F8-I:3G96G:4L?6QC6RD7XG=dONoWSt^Sw`P|cO{bN\x80_L{\\HvWEqTDrUEsVFqTBpQ?gK6aD2`C1hK9nQ?nQAqTDwZJwZJqTDmP@mP@oRDpSEpSEqTFpSEpSEpSEpSEoSEpTFqUGqUGqUGrVHsWIsWIrVHrVHrVHsWIrXIsWIqVEoTCnQ?oP>pQ=pQ=qQ:yU?\x8dgR\xa8\x80g\xb8\x93v\xb1\x92u\x8fu\\iS>TB6N=5G83G83K>5QC6SE8VH=_LHiUNpZOt]My_NzaM\x82aN}^JvWEqTDrUEtWGpSAlM;eI4`C1cF4lO=pSAnQApSCvYIwZJrUEmP@mP@oRDoRDpSEpSEpSEpSEpSEpSEpTFpTFpTFqUGrVHrVHqUGqUGqUGqUGsWItXJqWHpTFoSEmRAmP@oP>qR@rSAtT=xU?\x84^G\x9auZ\xb6\x92r\xc0\x9f\x80\xa7\x89o\x81fQkUH\\HAO<8J;8L=6OC7SE8TF;[JCdQJjVKqZLx^O{aP\x80_L{\\HuVDoRBqTDsVFmP>fG5_C._B0eH6mP>qTBpSCqTDuXHvYIrUEnQAnQAoRDoRDoRDpSEqTFqTFqTFqTFpTFpTFpTFpTFqUGqUGqUGpTFpTFpTFrVHsWIqWHpTFnRDmQCnQAoO@pPArRCsS>sP<xT>\x8cgL\xb2\x8el\xce\xad\x8c\xbe\x9e\x85\x98|gzbVgPJWBAP><K<7L?6PD8RF:UH@`OGfRInVJx^Q|bS\x81`M{\\HtUCnQApSCqTDhK9`A/^B-bE3iL:pSArUCqTDqTDsVFtWGqTDpSCpSCqTFpSEpSErUGrUGrUGrUGqTFpTFpTFoSEoSEoSEpTFpTFpTFpTFpTFpTFqUGpVIoSGnRDoSEpSEqQDqQDrRCpO>pM:qM7\x81\\A\xa9\x85c\xd2\xaf\x8f\xcf\xaf\x96\xb2\x93\x7f\x8bpev]XgNQ\\HIM>;H;3M@7OB9QG>ZKD`NDiSHw\\Q}cV\x83bO~_KvWEoRBpSCoRBeH6[<*`D/gJ8oR@sVDtWErUEpSCoRBrUEqTDqTDrUErUGqTFrUGsVHrUGrUGrUGrUGpTFpTFoSEoSEnRDoSEpTFqUGpTFoSEoSEoSEnTGmQEnRDqUGsVHsSFrRErREqP?uQAuQ;}X=\xa1}[\xd0\xad\x8d\xdd\xbb\xa2\xc8\xa7\x94\x9e\x82w\x8anjzadjVXSDAG:2I<3K>5OD>WHA]JCgPHv[R}bW\x87gR\x81bNyZHqTBoRBjM;_B0W8&[?*gJ8nQ?qTBtWEsVFoRBnQAqTFqTFqTFqTFpSEqTFrUGsVHsVHtWItWIsVHpTFoSEnRDoSEmRAmQCpTHsWKtXMqUIpTHqUIuYNmQFqUIqTFoRDrUEqTBsVDqU?qP=xSA~UA\xa1y`\xc8\xa3\x88\xdf\xbd\xa4\xcf\xaf\x9a\xa6\x8a\x7f\x95yv\x93z~\x88szhX[N@?D63I;8MB>TGA[JBcOFq[NycV\x8ajU\x82cOz[IrUClO?dG5Z=+U6$Z>)fI7mP>oR@rUCsVFpSCpSCqTFqTFpSEpSEpSEpSErUGsVHuXJvYKvYKuXJqUGoSEoSEoSEqVErVHuYMx\\Pw[PsWKrVJsWKuYNmQFpTHpSEoRBrUErUCtWErS>qP=yTB}T@\x9bsZ\xc2\x9f\x83\xdb\xbb\xa2\xd2\xb3\x9e\xb0\x95\x8c\x9c\x83\x7f\x9e\x87\x8d\x9b\x88\x8e}mpYKJF85G:4LA=RE?WF?^LBjVKt^Q\x8bkV\x83dPz[IqTBhK;]@.U8&U6$\\@+gJ8lO=mP>qTBrUEqTDrUEqTFpSEoRDoRDoRDqTFrUGsVHuXJvYKvYKuXJqUGnRDmQCmQCnSBqUGtXLw[OvZOsWKrVJtXLtXMnRFrVJsVHrUEtWEsVDtWErR=tQ>yRA{R>\x90kQ\xb5\x93w\xd1\xb3\x99\xcc\xb2\x9b\xad\x96\x8e\x94\x7f|\x99\x84\x89\x9f\x8e\x96\x8a{~eWVJ=7F93F;7K>8M>7UC9aMBiUJ\x87gR\x80aMyZHpSAdG7W:(T7%Y:(bF1kN<nQ?mP>oR@rUEsVFuXHqTFpSEoRDoRDpSEqTFsVHtWIuXJvYKvYKtWIqUGoSEnRDnRDqVEuYKy]Q{_Sz^Sx\\Px\\Py]QuYMpTHvZNx[MvYIvYGrUCqU@rO;tO=wP?yP<\x89dJ\xae\x8cp\xc7\xac\x91\xc7\xaf\x97\xa4\x92\x88\x87us\x86vy\x93\x84\x8b\x8a{~oa^RE?I:5>3-C60D5.J91WE;_MA\x84dO~_KyZHoR@`C3T7%S6$[<*eI4mP>oR@mP>pSAtWGvYIz]MuXJsVHqTFpSEpSEqTFrUGrUGtWIuXJuXJtWIqUGpTFpTFqUGtYHx\\N|`T}aU}aV}aU}aU~bVy]QsWKx\\Ny\\NvYIvYGsWBrVArO;sN<tM<yP<\x86aG\xa7\x88k\xbe\xa4\x89\xbc\xa6\x8e\xa2\x92\x85\x84rn}mp\x87x}\x87yyvhe[NHK<7>1+@3-?2*E6/PB9YH>\x84dO\x81bN{\\JnQ?]@0Q4""Q4""Y:(dH3lO=oR@nQ?rUCvYIy\\L}`Px[MuXJrUGpSEpSEpSEpSEpSEqTFrUGrUGqTFoSEoSEqUGsWIsXGw[M{_S}aU\x80dY\x84h\\\x86j^\x86j^}aUuYMw[MvYIsVDvYGuYDvZEvVAuR?tM<wQ<\x7f[A\x9e\x7fb\xad\x93x\xac\x94|\x98\x87w|kcwgg\x80qt\x7fqqqc`ZMGL=8C6.D7/B5-F91QD<XJA\x86fQ\x85fR\x7f`NmP>Z=-O2 O2 U6$`D/jM;nQ?oR@tWEwZJx[K{^Nx[MtWIqTFoRDpSEqTFqTFpSEqTFqTFqTFpSEoSEpTFsWIuYKx]Lz^P|`T}aU\x81eZ\x86j^\x87k_\x86j^z^RrVHuYKtWGsVDvZEvZEx\\GxYDxUBtO=xR=|X>\x97x[\xa4\x89n\xa2\x8ar\x8axdtbVvd`~notfe`SMOB<K>8I<4I<4E:4H=7UH@^PG\x87gR\x87hT\x81bPmP>Y<,N1\x1fN1\x1fS4""^B-hK9oR@qTBuXFwZJvYIwZJuXJrUGoRDnQCpSErUGsVHrUGuXJuXJuXJtWIrVHtXJw[Mz^Px]Lx\\NvZNtXLuYNx\\PvZNsWKuYMoSEtXJvYIuXFx\\GvZEx\\FwXCvUBtO={U@~Z@\x9a{^\xa7\x8cq\xa7\x8fw\x88t\\taR{hb\x81qql^[QD>D71K>8K>6K>6F;5J?9VLCaTK\x80cQ\x85hV}bOjO<X=*M0\x1eJ-\x1bP1\x1f_C.hL7lO=nQ?tWGvYIsVHrUGqTDrUEqTDmP@nQArUEsVFqTDqTDsVFuXHvYIx[K{^N|_O{^NwZLtXJqWHrXItZKv\\Mw[MwZLv[JtYHqVEqTDrUCtWEvYGwZHtYDrV@rR;sS:\x82bI\x9c~f\xa7\x8cw\xa1\x88t\x8ap_w`P{hZxg]^PGI<4C60E:4D:8J?;LA;OB:[JBgTM\x80aO\x81dR}bOqVC_D1M0\x1eH+\x19P1\x1f^B-gK6mP>nQ?rUEsVFpSEpSEpSCrUEpSCmP@nQArUEsVFqTDqTDuXHx[Ky\\Lz]M|_O|_O{^NsVHqUGnTEoUFrXItZKvZLwZLuZIsXGqVEqTDqTBsVDtWEtWErVAsT?sS<wU<\x83cJ\x9b|g\xa4\x88s\x9d\x82o\x83iXu^PxeWq`VVH?E80F93OB<LB@PEARE?SE<\\KChVL\x80aO\x80aO}`Nv[HfK8O2 G*\x18R3![?*fJ5lO=mP>pSCpSCoRDpSEqTDrUEpSCmP@nQAqTDrUEqTDqTDvYIz]Mz]Mz]Mz]Mz]My\\LrUGpTFoSEoUFqWHtXJuYKvYKsXGrWFpUDqTDqTBrUCrUCrUCrS?rR=vS=|ZA\x8bhR\x9e~i\xa0\x84o\x96{j{aRmVHlXMaPFK<5B5-F93OB<MB>OD>RE=UG>`OEkYO\x81`O\x7f`N{^LwZHjO<W:(L/\x1dR3!W:(cF4kN<lO=oRBpSCpSCsVFrUErUEpSCnQAnQApSCqTDpSCpSCtWGx[KwZJuXHtWGtWGtWGsVHsVHrVHqWHrXIsWItWIsVHqVEpUDpUDqTDrUCrUCrUCrUCrSAqP=wT@\x82^H\x91mW\x9d}h\x99zh\x89l\\qZLaK>ZF;O>6E6/E80D71F93H=7K>8OA8ZI?hVJuaV~]L\x7f^M{\\JuXFpSAcF4T7%O0\x1eU8&bE3jM;kN<nQApSCrUEuXHtWGsVFqTDnQAnQAoRBoRBnQAoRBsVFuXHrUEoRBnQAoRBpSCsVHsVHsWItXJtXJsWIsVHqTFoTCnSBoTCqTDrUCsVDrUCrUCsTBqP=xUA\x85`M\x94o\\\x99xe\x8dm^wZLgPBYC6Q=2I80F70K<5G81G81M@:K>6OA8^NAq_Q\x7fl^zVF}\\K{\\JvYGuXFnQ?Z=+J-\x1bS6$_B0gJ8iL:mP@pSCrUEvYIuXHsVFpSCnQAnQAnQAnQAnQApSCrUErUEoRBmP@mP@oRBoRBrREqTFrVHtXJtXJsWIrUGsSFnSBnSBnSBpSCqTBrUCqTBqTBpPAoN=yVC\x88eQ\x96s_\x97vc\x85hXnRD[E8U?4P>4K:2J;4M>7L=6PA:UH@RD;UD:dRFxeW\x86pbwSC}YI{ZIxYGx[IrUC_B0N1\x1fP3#[>.bE5eH8jM;oR@sVDwZHtWGrUEpSCnQAnQAnQAoRBoRBpSCqTDqTDoRBnQAoRBqTDqTDqQDpSErUGsWIsWItWIsVHuUHpUDoTCoTCpSCpSAoR@nQ?mP>kN>n'b'O={ZG\x8ciU\x92q^\x8fp^|_OhL@S=0M9.M;1I81I:3K<7K<5TE>WI@TF;[K>lZL~k\\\x89seyTD|XHyXGwXFx[IrUCaD2T7%L/\x1fW:*^A1aD4iL:oR@sVDx[IsVFqTDoRBnQAnQAoRBoRBpSCnQAoRBoRBnQAoRBqTDrUEqTDsSFrUGsVHrVHrVHtWItWIwWJrWFqVEoTCoRBnQ?mP>kN<jM;kP?oR@~]J\x8aiV\x8ckX\x82cQmQCY?2O9.H4)E3)C2+F70H94F70O@9SE<UG<bREucU\x86sd\x8exj{VC~[H~]N{[Nx[MtYHiN9[A*S6$S6$[>,cF4gJ8mP>rUCrUCqTDoRBnQAnQAmP@lO?oRBsVFoRBpSCpSCpSCqTDqTDqTDqTDpUDpUDpUDrUEsVFsVFsVFuUFtWGpSClO?kN>mP@mP@lO?jM=pSAwXF\x80_L\x85dS\x83bStWIaG:R</E1*F3,D3,D5.G81G81H92P?7TF;WG:eSE}gY\x8ase\x8dsf}XF\x82^N\x84cT~aS|_Qw\\KmR?bG2U8&S6$X;)`C1eH6jM;oR@oR@pSCnQAnQAnQAmP@lO?nQAqTDpSCpSCpSCpSCpSCpSCpSCqTDqVEqVEqTDrUEsVFsVFsVFtTEsVFqTDnQAlO?kN>lO?nQAoRBtWEx[I~_M\x80_NxXIhL>U>0J4\'C/(D1*C2+C4-H92I:3K=4SB:UG<ZJ=gUG|fX\x85n`\x86l_\x7fZJ\x85aS\x87eY\x81cX}_Ty]OsVFkN<]@.U8&U8&]@.bE3gJ8mP>oR@qTDpSCpSCpSCoRBmP@mP@nQAoRBoRBoRBoRBpSCpSCqTDqTDqVEqTDqTDqTDqTDrUEsSDsSDpSCpSCpSCnQAlO?lO?oRBrUEy^K}`N\x81bP}^LoRB^D5M7*D1#D1*D3+C2+D5.I:3K<5N=5SB:YH>_OBmZL{eW\x7fhZ}cV~ZL\x83_Q\x83cV~`U{]Rz]OvYIqTDfI7Y<*T7%Y<*]@.bE3jM;nQ?tWGtWGtWGtWGrUEoRBmP@lO?mP@mP@nQAoRBpSCpSCqTDqTDpSCpSCoRBoRBrRCrRCqQBqQBoO@qQBpSCoRBmP@nQApSCsVFx]L{`O|_OtYHeK<S<.E2$?-!B1)B3,B3,E82L=6M>7Q@8VE;_NDhVJtaS}fX}cVw]P\x7f[M\x7f^O~^Qy\\Nx[My\\Nx[KuXHoR@`C1V9\'U8&V9\'\\?-fI7lO=rUCtWEuXFvYGuXFsVDpSAmP>lO?mP@nQAoRBpSCpSCoRBoRBpSCoRBoRBoRBqQBqQBqQBpPAnN?nN?mM>kN>mP@pSCsXGv[Jw\\Kv[JpVEeK:U>.E2#=+\x1f:)\x1f;,%?0)A4,E82M>7OA8TC;[I?gUKr^S}gZ\x7fhZ{aTu[N\x80\\N~]N|\\MwZJwZJx[K{[L{[Lx[IjM;^A/V9\'R5#X;)cF4iL:lO=oR@rUCtWEvYGvYGsVDpSAoRBoRBoRBoRBoRBoRBoRBoRBqTDpSCrRCqQBqQBqQBpPAqPAnN?lL=iI:hK;mP@rWFw\\Kz_Nz^PsYJgM>VA0G4%?-\x1f<,\x1f;-""</\'@3+A60F93K>6P?7UC9]KAo]Szf[\x82l_~gYw]PtZM}\\M\x7f^O~_My\\JvYGvYG{[L|\\M|_MsVDgJ8X;)N1\x1fS6$^A/cF4fI7kN<oR@sVDvYGx[IvYGrUCrUEpSCoRBnQAnQApSCqTDsVFrUEsSDrRCqQBpPAoO@oN?nM>nM>lL=lL=lO?pSCsXGv[Jx]LrVHiO@ZC3K8\'B1!>.\x1f=/$=1%>4+C82D93F;5J=5P?7XF<dPEuaX\x81k`\x85ma}cVrXKpVI|[J\x80_N\x80aOz]KuXFtWEyZH|]K{^LuXFiL:W:(I,\x1aL/\x1dW:(Z=+eH6jM;oR@sVDwZHy\\JwZHsVDrUEpSCnQAmP@nQAqTDuXHx[KrUErRCqQBoO@nN?mL=kJ;jI:lK<nM>qQBsVFtWGsXGrWFpVEaG8Y?0K6%B/ <,\x1c:,\x1f:."":-$=3*B71E:4G<6L?7TC;`NDo[Pxd[\x83mb\x84l`z`SnTGmSFvYI{^L\x80aM~^IzZExYDxYEtWEsXGw[MmQC]A3T9(M0\x1eL0\x1bU9#aE/cG1hL6mQ;tU@vWBvWBtU@sWBsWBqTBnQ?pSAtWGx[Kz]MuXHqTDpPAqP?qM=mL;mL9nM:oN;qP=sTBsVFsXGrXIkTFfOAUB3M:+E5&A3&=1%9-!8+"";.%;2+?6/D:1H;3M?6ZIAgUKo]Sr\\QycV{eXu]QpUJnTGuXF}^L\x81bN\x81aL~^I{\\HxYGrUCqVEsWInRDgK=]B1M2\x1fD)\x14K1\x1aZ?*]A,`D/dH3hL7nO;pQ=qR>rVArVAqTBoR@pSAtWGwZJwZJvYIrUEqQBrQ@qP?pO>pO<pQ=qP=sR?sTBqTDoSEkQBcL>]G9J7(D3#?/ =/"";/#8, 9,#;.%<3,B71F<3J=5P?7ZG@gUKp\\SpZOs]Pt^QqYMoTImSFxYD}^I\x82bM\x81aL\x81`M\x80aM~_Mx[KsYHoUFmSDoUFgM<P7#A(\x12C*\x14L1\x1cO4\x1fT9$Z>)^B-cG2iM8mQ<oR@pSAqTBoR@pSAsVDuXHuXHrUEoRBoP>pO>pO>oN=nO=oP>pQ?rSAoR@jO>dJ;]F8V@2Q;.C0!>,\x1e;+\x1c9+\x1e8, 8, :-$>1(A60F<3M@8O@9UD<_LEkWNr^Us]Rq[NpXLoWKoTImSFwYA|\\E\x7f_H~^I\x7f^K\x83bQ\x85eV\x83fVw]LpVGmSDqWHmSDZ@/G1\x1cB,\x15@%\x10E*\x15K0\x1bR7""V;&[?*aE0fJ5jM;lO=nQ?mP>nQ?pSArUCsVDsVDtUCsTBtSBtSBrSApQ?mP>mN<kN<gL;_E6V?1P:,K5(E2$D1#@. ;+\x1e8*\x1d7+\x1f8+""=0\'C5,G:2K>6QC:XG?aNGlXQu^VxaYw_UqYMnVJpUJpUJmSFtT;yY@}ZD|YE{ZG\x82aP\x87gX\x88k[y^MqVElRCoUFoUFeN<T=+F0\x1b?&\x12@\'\x13D+\x17J/\x1cM2\x1fP5""U:\'Z?,cF4fI7hK9hK9iL:lO=nQ?oR@oR@rSArSAsRArQ@nO=hK9eH6cF6`E4[@/S9*J3%F0#A. >, D2&B0$?/"";-""9-!:-$@2)D6-H;2L>5TC;`MFo[T|e]\x7ff_}d]s[QpUJmRGoTIpUJoUHoP4vT;yV@yVB{XE\x80_N\x84eS\x83fTwZJqVEoSEpTFpVGoUF`I7L5#C)\x18?%\x14=#\x12?%\x14C)\x18H-\x1cM2!R7&X;+\\?/`C1`C1aD2dG5gJ8hK9gJ8kL:lM;kL:iJ8cF4^A1X=,V;*T9(N4%E. A+\x1e>+\x1d=+\x1f=+\x1f@.""@0#@2\'?1&=1%=0\'A3*E7.J<3O>6WF>gUKzf]\x86mf\x83jc}b[oTKmRGmRGoTIqVKrXKrP5tR9uR<vS@|YF\x81`M\x82cO~bMy\\LtWGtWIsWKpTHpVGiO@V?-H1\x1f?(\x168!\x0f<""\x11@&\x15B(\x17E+\x1aH-\x1cM0 R5%W:*X;)Y<*[>,\\@+]A,aE0eF2eF4cD2`A/[>.U:)P5$J/\x1eG-\x1eA*\x1a=\'\x19;(\x1a<*\x1e<,\x1f<+!>,""@/%?1&?1&<0$?1(D6-K:2RA7UD:`NDp\\S\x82kc\x88oh\x81f_uZSmPHpTIqUJpUJpUJrXKuS:tR9sN;tQ>|YF\x83bO\x84eP~bL\x7f_PyYJx[MvXMoSGpTFmSDbH7Q:(F/\x1d<%\x13<%\x13@&\x15?%\x14;!\x10: \x0fF)\x19L/\x1fR5%T7%T7%T7%U9$U9$U9$X9%W8&T5#R3!M0 H-\x1cB(\x17B(\x19A\'\x18<%\x17:$\x16:\'\x19=+\x1f=,""<+!A/%A0&?1&<.#:-$?1(G90P?7YH>]LBhVLwcZ\x85nf\x86mf{`YnQKlOGqUJsWLpTImQFmSF{[DuU>qQ:rO;vS?\x7f\\H\x85bN\x83`M\x7f`N}^L{\\JwZJvZLtZKpVGjSE]C2T:)F,\x1b: \x0f6\x1c\x0b7\x1d\x0c9\x1f\x0e8\x1e\r>""\x14B\'\x16E*\x19H-\x1cK0\x1dI.\x1bH-\x1aL1\x1eN3""M0 K.\x1eJ-\x1dH+\x1bC(\x17@&\x15?%\x14: \x119""\x12<%\x17=\'\x19<&\x198%\x17:&\x1b<*\x1e=,""=- :*\x1d9)\x1a>.\x1fB2#H8)RB5_K@hTIr\\QzdY\x86nd\x86kby^UnSJnSHmRGoTIrXKfOA\\E5\x7f_HwW@qQ:oL8pM9zWC\x83`L\x84aM\x80_L~]Lz[IuXFvYIv[JrXIoUFlRAdJ9V<+G-\x1c?%\x14?%\x14B(\x17D*\x19@%\x14C(\x17D)\x18E*\x19F+\x18D)\x16C(\x15G,\x19F+\x1aC(\x17B%\x15B%\x15A$\x14>#\x12<""\x11<""\x11: \x119""\x12:#\x15:$\x169#\x167$\x169%\x1a<*\x1e9\'\x1d<*\x1e>, B0""I7)M;-R@2ZH<iVHs]PwaTzbV\x7fg[\x7fdYuZOnSHoTInSHnSHlRE]F8R;+\x81aJzZCsS<nK5lI5uR>\x80]I\x83`L\x84aM\x81^K{ZGwXFuXFvYItYHrWFlRAhN=]C2N4#D*\x19B(\x17E+\x1aH.\x1dD)\x18F+\x1aD)\x18C(\x17C(\x17@%\x14?$\x11C(\x15D)\x18A&\x15A$\x14B%\x15B%\x15@%\x14@&\x15A\'\x16<%\x15;$\x14;$\x14;%\x17:$\x168%\x17<)\x1b@,!G3*M9.R?1XE7^K<_L>_L>dQCs]PzdWzdWw_Sv^Rv[PqVKoTIlQFkPEiNC_E8Q:,L5%\x7f_H{[DvV?rO9mJ4sP<|YE\x7f\\H\x86aN\x83`L\x7f\\HyXEwXDvYGtWEqVCrWFqVElQ@aF5X=,U:)W<+Y>-Z?.Z?.W<+V;*U:)R7&P5$T9(R7&P5$P5$S6&S8\'S8\'S9(R;)S<*R;+Q<+Q;-Q;-Q;.S@2XE7[D<aK@fPCkUGoYKlVHiSFkUHv_Q|eWybTs\\NsYLqWJoUHoUHkPEgLAcI<T:-G0 L5%<?xml version=""1.0""?>
+<root xmlns=""http://www.vips.ecs.soton.ac.uk/vips/8.3.1"">
+  <header>
+    <field type=""VipsRefString"" name=""Hist""/>
+  </header>
+  <meta>
+    <field type=""VipsRefString"" name=""vips-loader"">jpegload</field>
+    <field type=""gint"" name=""jpeg-multiscan"">1</field>
+  </meta>
+</root>
+"
+"always @(negedge reset or posedge clk) begin
+  if (reset == 0) begin
+    d_out <= 16'h0000;
+    d_out_mem[resetcount] <= d_out;
+    laststoredvalue <= d_out;
+  end else begin
+    d_out <= d_out + 1'b1; 
+  end
+end
+
+always @(bufreadaddr)
+  bufreadval = d_out_mem[bufreadaddr];"
+"module axi_elink(/*AUTOARG*/
+   // Outputs
+   rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
+   txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
+   txo_data_n, e_chipid, e_resetb, e_cclk_p, e_cclk_n,
+   mailbox_not_empty, mailbox_full, m_axi_awid, m_axi_awaddr,
+   m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock,
+   m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid,
+   m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready,
+   m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst,
+   m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
+   m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready,
+   s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata,
+   s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
+   // Inputs
+   reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
+   rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
+   txi_rd_wait_p, txi_rd_wait_n, m_axi_aresetn, m_axi_awready,
+   m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_arready,
+   m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
+   s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
+   s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
+   s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
+   s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
+   s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
+   s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
+   s_axi_wstrb, s_axi_wvalid
+   );
+   
+    parameter AW          = 32;
+   parameter DW          = 32; 
+   parameter PW          = 104;      //packet width   
+   parameter ID          = 12\'h810;
+   parameter S_IDW       = 12;       //ID width for S_AXI
+   parameter M_IDW       = 6;        //ID width for M_AXI
+   parameter IOSTD_ELINK = ""LVDS_25"";
+   parameter ETYPE       = 1;
+   
+   /****************************/
+   /*CLK AND RESET             */
+   /****************************/
+   input        reset;            // active high async reset
+   input \tsys_clk;          // system clock for AXI
+
+   /********************************/
+   /*ELINK I/O PINS                */
+   /********************************/          
+   //Receiver
+   input        rxi_lclk_p,   rxi_lclk_n;    //link rx clock input
+   input        rxi_frame_p,  rxi_frame_n;   //link rx frame signal
+   input [7:0] \trxi_data_p,   rxi_data_n;    //link rx data
+   output       rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
+   output       rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
+   
+   //Transmitter
+   output       txo_lclk_p,   txo_lclk_n;    //link tx clock output
+   output       txo_frame_p,  txo_frame_n;   //link tx frame signal
+   output [7:0] txo_data_p,   txo_data_n;    //link tx data
+   input \ttxi_wr_wait_p,txi_wr_wait_n; //link tx write pushback input
+   input \ttxi_rd_wait_p,txi_rd_wait_n; //link tx read pushback input
+
+   /********************************/
+   /*EPIPHANY INTERFACE (I/O PINS) */
+   /********************************/          
+   output [11:0] e_chipid;\t        //chip id strap pins for Epiphany
+   output \t e_resetb;              //chip reset for Epiphany (active low)
+   output \t e_cclk_p,e_cclk_n;     //high speed clock (up to 1GHz) to Epiphany
+   
+   /*****************************/
+   /*MAILBOX (interrupts)       */
+   /*****************************/
+   output        mailbox_not_empty;   
+   output        mailbox_full;
+
+   //########################
+   //AXI MASTER INTERFACE
+   //########################
+   input  \t       m_axi_aresetn; // global reset singal.
+
+   //Write address channel
+   output [M_IDW-1:0]  m_axi_awid;    // write address ID
+   output [31 : 0]     m_axi_awaddr;  // master interface write address   
+   output [7 : 0]      m_axi_awlen;   // burst length.
+   output [2 : 0]      m_axi_awsize;  // burst size.
+   output [1 : 0]      m_axi_awburst; // burst type.
+   output [1 : 0]      m_axi_awlock;  // lock type   
+   output [3 : 0]      m_axi_awcache; // memory type.
+   output [2 : 0]      m_axi_awprot;  // protection type.
+   output [3 : 0]      m_axi_awqos;   // quality of service
+   output \t       m_axi_awvalid; // write address valid
+   input \t       m_axi_awready; // write address ready
+
+   //Write data channel
+   output [M_IDW-1:0]    m_axi_wid;     
+   output [63 : 0]     m_axi_wdata;   // master interface write data.
+   output [7 : 0]      m_axi_wstrb;   // byte write strobes
+   output \t       m_axi_wlast;   // last transfer in a write burst.
+   output \t       m_axi_wvalid;  // indicates data is ready to go
+   input \t       m_axi_wready;  // slave is ready for data
+
+   //Write response channel
+   input [M_IDW-1:0]   m_axi_bid;
+   input [1 : 0]       m_axi_bresp;   // status of the write transaction.
+   input \t       m_axi_bvalid;  // valid write response
+   output \t       m_axi_bready;  // master can accept write response.
+
+   //Read address channel
+   output [M_IDW-1:0]  m_axi_arid;    // read address ID
+   output [31 : 0]     m_axi_araddr;  // initial address of a read burst
+   output [7 : 0]      m_axi_arlen;   // burst length
+   output [2 : 0]      m_axi_arsize;  // burst size
+   output [1 : 0]      m_axi_arburst; // burst type
+   output [1 : 0]      m_axi_arlock;  // lock type   
+   output [3 : 0]      m_axi_arcache; // memory type
+   output [2 : 0]      m_axi_arprot;  // protection type
+   output [3 : 0]      m_axi_arqos;   // --
+   output \t       m_axi_arvalid; // read address and control is valid
+   input \t       m_axi_arready; // slave is ready to accept an address
+
+   //Read data channel   
+   input [M_IDW-1:0]     m_axi_rid; 
+   input [63 : 0]      m_axi_rdata;   // master read data
+   input [1 : 0]       m_axi_rresp;   // status of the read transfer
+   input \t       m_axi_rlast;   // signals last transfer in a read burst
+   input \t       m_axi_rvalid;  // signaling the required read data
+   output \t       m_axi_rready;  // master can accept the readback data
+
+   /*****************************/
+   /*AXI slave interface        */
+   /*****************************/  
+   //Clock and reset
+   input \t   s_axi_aresetn;
+   
+   //Read address channel
+   input [S_IDW-1:0] s_axi_arid;    //write address ID
+   input [31:0]    s_axi_araddr;
+   input [1:0] \t   s_axi_arburst;
+   input [3:0] \t   s_axi_arcache;
+   input [1:0] \t   s_axi_arlock;
+   input [7:0] \t   s_axi_arlen;
+   input [2:0] \t   s_axi_arprot;
+   input [3:0] \t   s_axi_arqos;
+   output \t   s_axi_arready;
+   input [2:0] \t   s_axi_arsize;
+   input \t   s_axi_arvalid;
+   
+   //Write address channel
+   input [S_IDW-1:0] s_axi_awid;    //write address ID
+   input [31:0]    s_axi_awaddr;
+   input [1:0] \t   s_axi_awburst;
+   input [3:0] \t   s_axi_awcache;
+   input [1:0] \t   s_axi_awlock;
+   input [7:0] \t   s_axi_awlen;
+   input [2:0] \t   s_axi_awprot;
+   input [3:0] \t   s_axi_awqos;   
+   input [2:0] \t   s_axi_awsize;
+   input \t   s_axi_awvalid;
+   output \t   s_axi_awready;
+   
+   //Buffered write response channel
+   output [S_IDW-1:0] s_axi_bid;    //write address ID
+   output [1:0]     s_axi_bresp;
+   output \t    s_axi_bvalid;
+   input \t    s_axi_bready;
+   
+   //Read channel
+   output [S_IDW-1:0] s_axi_rid;    //write address ID
+   output [31:0]    s_axi_rdata;
+   output \t    s_axi_rlast;   
+   output [1:0]     s_axi_rresp;
+   output \t    s_axi_rvalid;
+   input \t    s_axi_rready;
+
+   //Write channel
+   input [S_IDW-1:0]  s_axi_wid;    //write address ID
+   input [31:0]     s_axi_wdata;
+   input \t    s_axi_wlast;   
+   input [3:0] \t    s_axi_wstrb;
+   input \t    s_axi_wvalid;
+   output \t    s_axi_wready;
+   
+   /*#############################################*/
+   /*  END OF BLOCK INTERFACE                     */
+   /*#############################################*/
+   
+   /*AUTOINPUT*/
+
+  
+   // End of automatics
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\telink_en;\t\t// From elink of elink.v
+   wire\t\t\telink_reset;\t\t// From eclocks of eclocks.v
+   wire\t\t\trx_lclk;\t\t// From eclocks of eclocks.v
+   wire\t\t\trx_lclk_div4;\t\t// From eclocks of eclocks.v
+   wire\t\t\trx_lclk_pll;\t\t// From elink of elink.v
+   wire\t\t\trxrd_access;\t\t// From elink of elink.v
+   wire [PW-1:0]\trxrd_packet;\t\t// From elink of elink.v
+   wire\t\t\trxrd_wait;\t\t// From emaxi of emaxi.v
+   wire\t\t\trxrr_access;\t\t// From elink of elink.v
+   wire [PW-1:0]\trxrr_packet;\t\t// From elink of elink.v
+   wire\t\t\trxrr_wait;\t\t// From esaxi of esaxi.v
+   wire\t\t\trxwr_access;\t\t// From elink of elink.v
+   wire [PW-1:0]\trxwr_packet;\t\t// From elink of elink.v
+   wire\t\t\trxwr_wait;\t\t// From emaxi of emaxi.v
+   wire\t\t\ttimeout;\t\t// From elink of elink.v
+   wire\t\t\ttx_lclk;\t\t// From eclocks of eclocks.v
+   wire\t\t\ttx_lclk90;\t\t// From eclocks of eclocks.v
+   wire\t\t\ttx_lclk_div4;\t\t// From eclocks of eclocks.v
+   wire\t\t\ttxrd_access;\t\t// From esaxi of esaxi.v
+   wire [PW-1:0]\ttxrd_packet;\t\t// From esaxi of esaxi.v
+   wire\t\t\ttxrd_wait;\t\t// From elink of elink.v
+   wire\t\t\ttxrr_access;\t\t// From emaxi of emaxi.v
+   wire [PW-1:0]\ttxrr_packet;\t\t// From emaxi of emaxi.v
+   wire\t\t\ttxrr_wait;\t\t// From elink of elink.v
+   wire\t\t\ttxwr_access;\t\t// From esaxi of esaxi.v
+   wire [PW-1:0]\ttxwr_packet;\t\t// From esaxi of esaxi.v
+   wire\t\t\ttxwr_wait;\t\t// From elink of elink.v
+   // End of automatics
+
+     
+   //########################################################
+   //ELINK
+   //########################################################
+    
+   defparam elink.IOSTD_ELINK = IOSTD_ELINK;
+   defparam elink.ETYPE       = ETYPE;
+
+   elink elink(.reset\t\t\t(elink_reset),
+\t       /*AUTOINST*/
+\t       // Outputs
+\t       .rx_lclk_pll\t\t(rx_lclk_pll),
+\t       .rxo_wr_wait_p\t\t(rxo_wr_wait_p),
+\t       .rxo_wr_wait_n\t\t(rxo_wr_wait_n),
+\t       .rxo_rd_wait_p\t\t(rxo_rd_wait_p),
+\t       .rxo_rd_wait_n\t\t(rxo_rd_wait_n),
+\t       .txo_lclk_p\t\t(txo_lclk_p),
+\t       .txo_lclk_n\t\t(txo_lclk_n),
+\t       .txo_frame_p\t\t(txo_frame_p),
+\t       .txo_frame_n\t\t(txo_frame_n),
+\t       .txo_data_p\t\t(txo_data_p[7:0]),
+\t       .txo_data_n\t\t(txo_data_n[7:0]),
+\t       .e_chipid\t\t(e_chipid[11:0]),
+\t       .elink_en\t\t(elink_en),
+\t       .rxwr_access\t\t(rxwr_access),
+\t       .rxwr_packet\t\t(rxwr_packet[PW-1:0]),
+\t       .rxrd_access\t\t(rxrd_access),
+\t       .rxrd_packet\t\t(rxrd_packet[PW-1:0]),
+\t       .rxrr_access\t\t(rxrr_access),
+\t       .rxrr_packet\t\t(rxrr_packet[PW-1:0]),
+\t       .txwr_wait\t\t(txwr_wait),
+\t       .txrd_wait\t\t(txrd_wait),
+\t       .txrr_wait\t\t(txrr_wait),
+\t       .mailbox_not_empty\t(mailbox_not_empty),
+\t       .mailbox_full\t\t(mailbox_full),
+\t       .timeout\t\t\t(timeout),
+\t       // Inputs
+\t       .sys_clk\t\t\t(sys_clk),
+\t       .tx_lclk\t\t\t(tx_lclk),
+\t       .tx_lclk90\t\t(tx_lclk90),
+\t       .tx_lclk_div4\t\t(tx_lclk_div4),
+\t       .rx_lclk\t\t\t(rx_lclk),
+\t       .rx_lclk_div4\t\t(rx_lclk_div4),
+\t       .rxi_lclk_p\t\t(rxi_lclk_p),
+\t       .rxi_lclk_n\t\t(rxi_lclk_n),
+\t       .rxi_frame_p\t\t(rxi_frame_p),
+\t       .rxi_frame_n\t\t(rxi_frame_n),
+\t       .rxi_data_p\t\t(rxi_data_p[7:0]),
+\t       .rxi_data_n\t\t(rxi_data_n[7:0]),
+\t       .txi_wr_wait_p\t\t(txi_wr_wait_p),
+\t       .txi_wr_wait_n\t\t(txi_wr_wait_n),
+\t       .txi_rd_wait_p\t\t(txi_rd_wait_p),
+\t       .txi_rd_wait_n\t\t(txi_rd_wait_n),
+\t       .rxwr_wait\t\t(rxwr_wait),
+\t       .rxrd_wait\t\t(rxrd_wait),
+\t       .rxrr_wait\t\t(rxrr_wait),
+\t       .txwr_access\t\t(txwr_access),
+\t       .txwr_packet\t\t(txwr_packet[PW-1:0]),
+\t       .txrd_access\t\t(txrd_access),
+\t       .txrd_packet\t\t(txrd_packet[PW-1:0]),
+\t       .txrr_access\t\t(txrr_access),
+\t       .txrr_packet\t\t(txrr_packet[PW-1:0]));
+
+   //########################################################
+   //CLOCK AND RESET
+   //########################################################
+
+   eclocks eclocks (.rx_clkin\t\t(rx_lclk_pll),
+\t\t    /*AUTOINST*/
+\t\t    // Outputs
+\t\t    .tx_lclk\t\t(tx_lclk),
+\t\t    .tx_lclk90\t\t(tx_lclk90),
+\t\t    .tx_lclk_div4\t(tx_lclk_div4),
+\t\t    .rx_lclk\t\t(rx_lclk),
+\t\t    .rx_lclk_div4\t(rx_lclk_div4),
+\t\t    .e_cclk_p\t\t(e_cclk_p),
+\t\t    .e_cclk_n\t\t(e_cclk_n),
+\t\t    .elink_reset\t(elink_reset),
+\t\t    .e_resetb\t\t(e_resetb),
+\t\t    // Inputs
+\t\t    .reset\t\t(reset),
+\t\t    .elink_en\t\t(elink_en),
+\t\t    .sys_clk\t\t(sys_clk));
+   
+   
+   //########################################################
+   //AXI SLAVE
+   //########################################################
+   
+   defparam esaxi.IDW=S_IDW;
+   esaxi esaxi (.s_axi_aclk\t\t(sys_clk),
+\t\t/*AUTOINST*/
+\t\t// Outputs
+\t\t.txwr_access\t\t(txwr_access),
+\t\t.txwr_packet\t\t(txwr_packet[PW-1:0]),
+\t\t.txrd_access\t\t(txrd_access),
+\t\t.txrd_packet\t\t(txrd_packet[PW-1:0]),
+\t\t.rxrr_wait\t\t(rxrr_wait),
+\t\t.s_axi_arready\t\t(s_axi_arready),
+\t\t.s_axi_awready\t\t(s_axi_awready),
+\t\t.s_axi_bid\t\t(s_axi_bid[S_IDW-1:0]),
+\t\t.s_axi_bresp\t\t(s_axi_bresp[1:0]),
+\t\t.s_axi_bvalid\t\t(s_axi_bvalid),
+\t\t.s_axi_rid\t\t(s_axi_rid[S_IDW-1:0]),
+\t\t.s_axi_rdata\t\t(s_axi_rdata[31:0]),
+\t\t.s_axi_rlast\t\t(s_axi_rlast),
+\t\t.s_axi_rresp\t\t(s_axi_rresp[1:0]),
+\t\t.s_axi_rvalid\t\t(s_axi_rvalid),
+\t\t.s_axi_wready\t\t(s_axi_wready),
+\t\t// Inputs
+\t\t.txwr_wait\t\t(txwr_wait),
+\t\t.txrd_wait\t\t(txrd_wait),
+\t\t.rxrr_access\t\t(rxrr_access),
+\t\t.rxrr_packet\t\t(rxrr_packet[PW-1:0]),
+\t\t.s_axi_aresetn\t\t(s_axi_aresetn),
+\t\t.s_axi_arid\t\t(s_axi_arid[S_IDW-1:0]),
+\t\t.s_axi_araddr\t\t(s_axi_araddr[31:0]),
+\t\t.s_axi_arburst\t\t(s_axi_arburst[1:0]),
+\t\t.s_axi_arcache\t\t(s_axi_arcache[3:0]),
+\t\t.s_axi_arlock\t\t(s_axi_arlock[1:0]),
+\t\t.s_axi_arlen\t\t(s_axi_arlen[7:0]),
+\t\t.s_axi_arprot\t\t(s_axi_arprot[2:0]),
+\t\t.s_axi_arqos\t\t(s_axi_arqos[3:0]),
+\t\t.s_axi_arsize\t\t(s_axi_arsize[2:0]),
+\t\t.s_axi_arvalid\t\t(s_axi_arvalid),
+\t\t.s_axi_awid\t\t(s_axi_awid[S_IDW-1:0]),
+\t\t.s_axi_awaddr\t\t(s_axi_awaddr[31:0]),
+\t\t.s_axi_awburst\t\t(s_axi_awburst[1:0]),
+\t\t.s_axi_awcache\t\t(s_axi_awcache[3:0]),
+\t\t.s_axi_awlock\t\t(s_axi_awlock[1:0]),
+\t\t.s_axi_awlen\t\t(s_axi_awlen[7:0]),
+\t\t.s_axi_awprot\t\t(s_axi_awprot[2:0]),
+\t\t.s_axi_awqos\t\t(s_axi_awqos[3:0]),
+\t\t.s_axi_awsize\t\t(s_axi_awsize[2:0]),
+\t\t.s_axi_awvalid\t\t(s_axi_awvalid),
+\t\t.s_axi_bready\t\t(s_axi_bready),
+\t\t.s_axi_rready\t\t(s_axi_rready),
+\t\t.s_axi_wid\t\t(s_axi_wid[S_IDW-1:0]),
+\t\t.s_axi_wdata\t\t(s_axi_wdata[31:0]),
+\t\t.s_axi_wlast\t\t(s_axi_wlast),
+\t\t.s_axi_wstrb\t\t(s_axi_wstrb[3:0]),
+\t\t.s_axi_wvalid\t\t(s_axi_wvalid));
+
+   //########################################################
+   //AXI MASTER INTERFACE
+   //########################################################
+
+   defparam emaxi.IDW=M_IDW;
+   emaxi emaxi (.m_axi_aclk\t\t(sys_clk),
+\t\t/*AUTOINST*/
+\t\t// Outputs
+\t\t.rxwr_wait\t\t(rxwr_wait),
+\t\t.rxrd_wait\t\t(rxrd_wait),
+\t\t.txrr_access\t\t(txrr_access),
+\t\t.txrr_packet\t\t(txrr_packet[PW-1:0]),
+\t\t.m_axi_awid\t\t(m_axi_awid[M_IDW-1:0]),
+\t\t.m_axi_awaddr\t\t(m_axi_awaddr[31:0]),
+\t\t.m_axi_awlen\t\t(m_axi_awlen[7:0]),
+\t\t.m_axi_awsize\t\t(m_axi_awsize[2:0]),
+\t\t.m_axi_awburst\t\t(m_axi_awburst[1:0]),
+\t\t.m_axi_awlock\t\t(m_axi_awlock[1:0]),
+\t\t.m_axi_awcache\t\t(m_axi_awcache[3:0]),
+\t\t.m_axi_awprot\t\t(m_axi_awprot[2:0]),
+\t\t.m_axi_awqos\t\t(m_axi_awqos[3:0]),
+\t\t.m_axi_awvalid\t\t(m_axi_awvalid),
+\t\t.m_axi_wid\t\t(m_axi_wid[M_IDW-1:0]),
+\t\t.m_axi_wdata\t\t(m_axi_wdata[63:0]),
+\t\t.m_axi_wstrb\t\t(m_axi_wstrb[7:0]),
+\t\t.m_axi_wlast\t\t(m_axi_wlast),
+\t\t.m_axi_wvalid\t\t(m_axi_wvalid),
+\t\t.m_axi_bready\t\t(m_axi_bready),
+\t\t.m_axi_arid\t\t(m_axi_arid[M_IDW-1:0]),
+\t\t.m_axi_araddr\t\t(m_axi_araddr[31:0]),
+\t\t.m_axi_arlen\t\t(m_axi_arlen[7:0]),
+\t\t.m_axi_arsize\t\t(m_axi_arsize[2:0]),
+\t\t.m_axi_arburst\t\t(m_axi_arburst[1:0]),
+\t\t.m_axi_arlock\t\t(m_axi_arlock[1:0]),
+\t\t.m_axi_arcache\t\t(m_axi_arcache[3:0]),
+\t\t.m_axi_arprot\t\t(m_axi_arprot[2:0]),
+\t\t.m_axi_arqos\t\t(m_axi_arqos[3:0]),
+\t\t.m_axi_arvalid\t\t(m_axi_arvalid),
+\t\t.m_axi_rready\t\t(m_axi_rready),
+\t\t// Inputs
+\t\t.rxwr_access\t\t(rxwr_access),
+\t\t.rxwr_packet\t\t(rxwr_packet[PW-1:0]),
+\t\t.rxrd_access\t\t(rxrd_access),
+\t\t.rxrd_packet\t\t(rxrd_packet[PW-1:0]),
+\t\t.txrr_wait\t\t(txrr_wait),
+\t\t.m_axi_aresetn\t\t(m_axi_aresetn),
+\t\t.m_axi_awready\t\t(m_axi_awready),
+\t\t.m_axi_wready\t\t(m_axi_wready),
+\t\t.m_axi_bid\t\t(m_axi_bid[M_IDW-1:0]),
+\t\t.m_axi_bresp\t\t(m_axi_bresp[1:0]),
+\t\t.m_axi_bvalid\t\t(m_axi_bvalid),
+\t\t.m_axi_arready\t\t(m_axi_arready),
+\t\t.m_axi_rid\t\t(m_axi_rid[M_IDW-1:0]),
+\t\t.m_axi_rdata\t\t(m_axi_rdata[63:0]),
+\t\t.m_axi_rresp\t\t(m_axi_rresp[1:0]),
+\t\t.m_axi_rlast\t\t(m_axi_rlast),
+\t\t.m_axi_rvalid\t\t(m_axi_rvalid));
+
+      
+endmodule // elink
+// Local Variables:
+// verilog-library-directories:(""."" ""../../erx/hdl"" ""../../etx/hdl""  ""../../memory/hdl"")
+// End:
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+ 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"/* Simple combinatorial priority arbiter
+ * (lowest position has highest priority)
+ *
+ */
+
+module arbiter_priority(/*AUTOARG*/
+   // Outputs
+   grant, await,
+   // Inputs
+   request
+   );
+   
+   parameter ARW=99;
+       
+   input  [ARW-1:0] request;  //request vector
+   output [ARW-1:0] grant;    //grant (one hot)
+   output [ARW-1:0] await;    //grant mask
+   
+   genvar j;
+   assign await[0]   = 1'b0;   
+   generate for (j=ARW-1; j>=1; j=j-1) begin : gen_arbiter     
+      assign await[j] = |request[j-1:0];
+   end
+   endgenerate
+
+   //grant circuit
+   assign grant[ARW-1:0] = request[ARW-1:0] & ~await[ARW-1:0];
+
+   
+endmodule // arbiter_priority
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"/*
+ ########################################################################
+ ELINK CONFIGURATION REGISTER FILE
+ ########################################################################
+ 
+ */
+`include ""elink_regmap.v""
+
+module erx_cfg (/*AUTOARG*/
+   // Outputs
+   mi_dout, rx_enable, mmu_enable, remap_mode, remap_base,
+   remap_pattern, remap_sel, timer_cfg,
+   // Inputs
+   reset, clk, mi_en, mi_we, mi_addr, mi_din, gpio_datain, rx_status
+   );
+
+   /******************************/
+   /*Compile Time Parameters     */
+   /******************************/
+   parameter RFAW            = 6;         // 32 registers for now
+   parameter GROUP           = 4\'h0;
+   
+   /******************************/
+   /*HARDWARE RESET (EXTERNAL)   */
+   /******************************/
+   input \treset;       // ecfg registers reset only by ""hard reset""
+   input \tclk;
+   /*****************************/
+   /*SIMPLE MEMORY INTERFACE    */
+   /*****************************/    
+   input \t mi_en;         
+   input \t mi_we;            // single we, must write 32 bit words
+   input [14:0]  mi_addr;          // complete physical address (no shifting!)
+   input [31:0]  mi_din;
+   output [31:0] mi_dout;   
+   
+   /*****************************/
+   /*CONFIG SIGNALS             */
+   /*****************************/
+   //rx
+   output \t rx_enable;      // enable signal for rx  
+   output \t mmu_enable;     // enables MMU on rx path (static)  
+   input [8:0] \t gpio_datain;    // frame and data inputs (static)        
+   input [15:0]  rx_status;      // etx status signals
+   output [1:0]  remap_mode;     // remap mode (static)       
+   output [31:0] remap_base;     // base for dynamic remap (static) 
+   output [11:0] remap_pattern;  // patter for static remap (static)
+   output [11:0] remap_sel;      // selects for static remap (static)
+   output [1:0]  timer_cfg;      // timeout config (00=off) (static)
+   
+   /*------------------------CODE BODY---------------------------------------*/
+   
+   //registers
+   reg [31:0] \tecfg_rx_reg;
+   reg [31:0] \tecfg_offset_reg;
+   reg [8:0] \tecfg_gpio_reg;
+   reg [2:0] \tecfg_rx_status_reg;
+   reg [31:0] \tmi_dout;
+   
+   //wires
+   wire \tecfg_read;
+   wire \tecfg_write;
+   wire \tecfg_rx_write;
+   wire  \tecfg_base_write;
+   wire  \tecfg_remap_write;
+   
+   /*****************************/
+   /*ADDRESS DECODE LOGIC       */
+   /*****************************/
+
+   //read/write decode
+   assign ecfg_write  = mi_en &  mi_we;
+   assign ecfg_read   = mi_en & ~mi_we;   
+
+   //Config write enables
+   assign ecfg_rx_write      = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_CFG);
+   assign ecfg_base_write    = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_OFFSET);
+   
+   //###########################
+   //# RXCFG
+   //###########################
+   always @ (posedge clk)
+     if(reset)
+       ecfg_rx_reg[31:0] <= \'b0;
+     else if (ecfg_rx_write)
+       ecfg_rx_reg[31:0] <= mi_din[31:0];
+
+   assign rx_enable           = 1\'b1;//is there any good reason turn RX off?
+   assign mmu_enable          = ecfg_rx_reg[1];
+   assign remap_mode[1:0]     = ecfg_rx_reg[3:2];
+   assign remap_sel[11:0]     = ecfg_rx_reg[15:4];
+   assign remap_pattern[11:0] = ecfg_rx_reg[27:16];
+   assign timer_cfg[1:0]      = ecfg_rx_reg[29:28];
+      
+   //###########################
+   //# DATAIN
+   //###########################
+   always @ (posedge clk)
+     ecfg_gpio_reg[8:0] <= gpio_datain[8:0];
+   
+   //###########################1
+   //# DEBUG
+   //###########################   
+   always @ (posedge clk)
+     if(reset)
+       ecfg_rx_status_reg[2:0] <= \'b0;   
+     else
+       ecfg_rx_status_reg[2:0] <= ecfg_rx_status_reg[2:0] | rx_status[2:0];
+
+   //###########################1
+   //# DYNAMIC REMAP BASE
+   //###########################
+   always @ (posedge clk)   
+     if (ecfg_base_write)
+       ecfg_offset_reg[31:0] <= mi_din[31:0];
+
+   assign remap_base[31:0] = ecfg_offset_reg[31:0];
+   
+   //###############################
+   //# DATA READBACK MUX
+   //###############################
+
+   //Pipelineing readback
+   always @ (posedge clk)
+     if(ecfg_read)
+       case(mi_addr[RFAW+1:2])
+         `ERX_CFG:     mi_dout[31:0] <= {ecfg_rx_reg[31:0]};
+         `ERX_GPIO:    mi_dout[31:0] <= {23\'b0, ecfg_gpio_reg[8:0]};
+\t `ERX_STATUS:  mi_dout[31:0] <= {16\'b0, rx_status[15:3],ecfg_rx_status_reg[2:0]};
+\t `ERX_OFFSET:  mi_dout[31:0] <= {ecfg_offset_reg[31:0]};
+         default:      mi_dout[31:0] <= 32\'d0;
+       endcase // case (mi_addr[RFAW+1:2])
+     else
+       mi_dout[31:0] <= 32\'d0;
+   
+endmodule // ecfg_rx
+
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+"
+"module etx(/*AUTOARG*/
+   // Outputs
+   txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
+   txo_data_n, txrd_wait, txwr_wait, txrr_wait, etx_cfg_access,
+   etx_cfg_packet,
+   // Inputs
+   etx_reset, sys_reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4,
+   txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n,
+   txrd_access, txrd_packet, txwr_access, txwr_packet, txrr_access,
+   txrr_packet, etx_cfg_wait, etx90_reset
+   );
+   parameter AW          = 32;
+   parameter DW          = 32;
+   parameter PW          = 104;
+   parameter RFAW        = 6;
+   parameter ID          = 12\'h000;
+   parameter IOSTD_ELINK = ""LVDS_25"";
+   parameter ETYPE       = 1;   
+   //Synched resets
+   input          etx_reset;                   // reset for core logic 
+   input \t  sys_reset;                   // reset for fifos   
+
+   //Clocks
+   input \t  sys_clk;                     // clock for fifos   
+   input \t  tx_lclk;\t               // fast clock for io
+   input \t  tx_lclk90;                   // 90 deg shifted lclk   
+   input \t  tx_lclk_div4;\t\t       // slow clock for core logic   
+
+   //Transmit signals for IO
+   output \t  txo_lclk_p,   txo_lclk_n;     // tx clock output
+   output \t  txo_frame_p, txo_frame_n;     // tx frame signal
+   output [7:0]   txo_data_p, txo_data_n;       // tx data (dual data rate)
+   input \t  txi_wr_wait_p,txi_wr_wait_n;  // tx async write pushback
+   input \t  txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback
+      
+   //Read Request Channel Input
+   input \t  txrd_access;
+   input [PW-1:0] txrd_packet;
+   output \t  txrd_wait;
+   
+   //Write Channel Input
+   input \t  txwr_access;
+   input [PW-1:0] txwr_packet;
+   output \t  txwr_wait;
+   
+   //Read Response Channel Input
+   input \t  txrr_access;
+   input [PW-1:0] txrr_packet;
+   output \t  txrr_wait;
+
+   //Configuration Interface (for ERX)
+   output \t   etx_cfg_access;
+   output [PW-1:0] etx_cfg_packet;
+   input \t   etx_cfg_wait;
+
+   input \t   etx90_reset;
+   
+         
+   /*AUTOOUTPUT*/
+   /*AUTOINPUT*/
+        
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\ttx_access;\t\t// From etx_core of etx_core.v
+   wire\t\t\ttx_burst;\t\t// From etx_core of etx_core.v
+   wire\t\t\ttx_io_wait;\t\t// From etx_io of etx_io.v
+   wire [PW-1:0]\ttx_packet;\t\t// From etx_core of etx_core.v
+   wire\t\t\ttx_rd_wait;\t\t// From etx_io of etx_io.v
+   wire\t\t\ttx_wr_wait;\t\t// From etx_io of etx_io.v
+   wire\t\t\ttxrd_fifo_access;\t// From etx_fifo of etx_fifo.v
+   wire [PW-1:0]\ttxrd_fifo_packet;\t// From etx_fifo of etx_fifo.v
+   wire\t\t\ttxrd_fifo_wait;\t\t// From etx_core of etx_core.v
+   wire\t\t\ttxrr_fifo_access;\t// From etx_fifo of etx_fifo.v
+   wire [PW-1:0]\ttxrr_fifo_packet;\t// From etx_fifo of etx_fifo.v
+   wire\t\t\ttxrr_fifo_wait;\t\t// From etx_core of etx_core.v
+   wire\t\t\ttxwr_fifo_access;\t// From etx_fifo of etx_fifo.v
+   wire [PW-1:0]\ttxwr_fifo_packet;\t// From etx_fifo of etx_fifo.v
+   wire\t\t\ttxwr_fifo_wait;\t\t// From etx_core of etx_core.v
+  
+   
+   /************************************************************/
+   /*FIFOs                                                     */
+   /************************************************************/
+   etx_fifo etx_fifo (/*AUTOINST*/
+\t\t      // Outputs
+\t\t      .txrd_wait\t(txrd_wait),
+\t\t      .txwr_wait\t(txwr_wait),
+\t\t      .txrr_wait\t(txrr_wait),
+\t\t      //.etx_cfg_access\t(etx_cfg_access),
+\t\t      //.etx_cfg_packet\t(etx_cfg_packet[PW-1:0]),
+\t\t      .txrd_fifo_access\t(txrd_fifo_access),
+\t\t      .txrd_fifo_packet\t(txrd_fifo_packet[PW-1:0]),
+\t\t      .txrr_fifo_access\t(txrr_fifo_access),
+\t\t      .txrr_fifo_packet\t(txrr_fifo_packet[PW-1:0]),
+\t\t      .txwr_fifo_access\t(txwr_fifo_access),
+\t\t      .txwr_fifo_packet\t(txwr_fifo_packet[PW-1:0]),
+\t\t      // Inputs
+\t\t      .etx_reset\t(etx_reset),
+\t\t      .sys_reset\t(sys_reset),
+\t\t      .sys_clk\t\t(sys_clk),
+\t\t      .tx_lclk_div4\t(tx_lclk_div4),
+\t\t      .txrd_access\t(txrd_access),
+\t\t      .txrd_packet\t(txrd_packet[PW-1:0]),
+\t\t      .txwr_access\t(txwr_access),
+\t\t      .txwr_packet\t(txwr_packet[PW-1:0]),
+\t\t      .txrr_access\t(txrr_access),
+\t\t      .txrr_packet\t(txrr_packet[PW-1:0]),
+\t\t      .etx_cfg_wait\t(etx_cfg_wait),
+\t\t      .txrd_fifo_wait\t(txrd_fifo_wait),
+\t\t      .txrr_fifo_wait\t(txrr_fifo_wait),
+\t\t      .txwr_fifo_wait\t(txwr_fifo_wait));
+
+   /***********************************************************/
+   /*ELINK CORE LOGIC                                         */
+   /***********************************************************/
+   /*etx_core   AUTO_TEMPLATE ( .tx_access\t(tx_access),
+\t\t                .tx_burst\t(tx_burst),
+    \t\t                .tx_io_wait\t(tx_io_wait), 
+                                .tx_rd_wait\t(tx_rd_wait),
+\t\t                .tx_wr_wait\t(tx_wr_wait),
+\t\t                .tx_packet\t(tx_packet[PW-1:0]),
+                                .etx_cfg_access\t(etx_cfg_access),
+\t\t                .etx_cfg_packet\t(etx_cfg_packet[PW-1:0]),
+                                .etx_cfg_wait\t(etx_cfg_wait),
+                               
+    \t\t\t        .\\(.*\\)_packet   (\\1_fifo_packet[PW-1:0]),
+    \t\t\t        .\\(.*\\)_access   (\\1_fifo_access),
+       \t\t\t        .\\(.*\\)_wait     (\\1_fifo_wait),
+    );
+    */
+   
+   defparam etx_core.ID=ID;   
+   etx_core etx_core (.clk\t\t(tx_lclk_div4),
+\t\t      .reset\t\t(etx_reset),
+\t\t      /*AUTOINST*/
+\t\t      // Outputs
+\t\t      .tx_access\t(tx_access),\t\t // Templated
+\t\t      .tx_burst\t\t(tx_burst),\t\t // Templated
+\t\t      .tx_packet\t(tx_packet[PW-1:0]),\t // Templated
+\t\t      .txrd_wait\t(txrd_fifo_wait),\t // Templated
+\t\t      .txrr_wait\t(txrr_fifo_wait),\t // Templated
+\t\t      .txwr_wait\t(txwr_fifo_wait),\t // Templated
+\t\t      .etx_cfg_access\t(etx_cfg_access),\t // Templated
+\t\t      .etx_cfg_packet\t(etx_cfg_packet[PW-1:0]), // Templated
+\t\t      // Inputs
+\t\t      .tx_io_wait\t(tx_io_wait),\t\t // Templated
+\t\t      .tx_rd_wait\t(tx_rd_wait),\t\t // Templated
+\t\t      .tx_wr_wait\t(tx_wr_wait),\t\t // Templated
+\t\t      .txrd_access\t(txrd_fifo_access),\t // Templated
+\t\t      .txrd_packet\t(txrd_fifo_packet[PW-1:0]), // Templated
+\t\t      .txrr_access\t(txrr_fifo_access),\t // Templated
+\t\t      .txrr_packet\t(txrr_fifo_packet[PW-1:0]), // Templated
+\t\t      .txwr_access\t(txwr_fifo_access),\t // Templated
+\t\t      .txwr_packet\t(txwr_fifo_packet[PW-1:0]), // Templated
+\t\t      .etx_cfg_wait\t(etx_cfg_wait));\t\t // Templated
+   
+   
+   /***********************************************************/
+   /*TRANSMIT I/O LOGIC                                       */
+   /***********************************************************/
+
+   defparam etx_io.IOSTD_ELINK=IOSTD_ELINK;
+   etx_io etx_io (.reset\t\t(etx_reset),
+\t\t  .etx90_reset (etx90_reset),
+\t\t  
+\t\t  /*AUTOINST*/
+\t\t  // Outputs
+\t\t  .txo_lclk_p\t\t(txo_lclk_p),
+\t\t  .txo_lclk_n\t\t(txo_lclk_n),
+\t\t  .txo_frame_p\t\t(txo_frame_p),
+\t\t  .txo_frame_n\t\t(txo_frame_n),
+\t\t  .txo_data_p\t\t(txo_data_p[7:0]),
+\t\t  .txo_data_n\t\t(txo_data_n[7:0]),
+\t\t  .tx_io_wait\t\t(tx_io_wait),
+\t\t  .tx_wr_wait\t\t(tx_wr_wait),
+\t\t  .tx_rd_wait\t\t(tx_rd_wait),
+\t\t  // Inputs
+\t\t  .tx_lclk\t\t(tx_lclk),
+\t\t  .tx_lclk90\t\t(tx_lclk90),
+\t\t  .txi_wr_wait_p\t(txi_wr_wait_p),
+\t\t  .txi_wr_wait_n\t(txi_wr_wait_n),
+\t\t  .txi_rd_wait_p\t(txi_rd_wait_p),
+\t\t  .txi_rd_wait_n\t(txi_rd_wait_n),
+\t\t  .tx_packet\t\t(tx_packet[PW-1:0]),
+\t\t  .tx_access\t\t(tx_access),
+\t\t  .tx_burst\t\t(tx_burst));
+   
+   
+endmodule // elink
+// Local Variables:
+// verilog-library-directories:(""."" ""../../emmu/hdl"" ""../../memory/hdl"" ""../../edma/hdl/"")
+// End:
+
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+ 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"module OBUF (/*AUTOARG*/
+   // Outputs
+   O,
+   // Inputs
+   I
+   );
+
+    parameter CAPACITANCE   = ""DONT_CARE"";
+    parameter integer DRIVE = 12;
+    parameter IOSTANDARD    = ""DEFAULT"";
+`ifdef XIL_TIMING
+    parameter LOC = "" UNPLACED"";
+`endif
+    parameter SLEW = ""SLOW"";
+   
+   output \t      O;
+   input \t      I;
+   
+   wire \t      GTS = 1\'b0;  //Note, uses globals, ugly! 
+
+   bufif0 B1 (O, I, GTS);
+    
+endmodule
+
+
+
+
+
+
+"
+"
+/*###########################################################################
+ # Function: Dual port memory wrapper (one read/ one write port)
+ #           To run without hardware platform dependancy, `define:
+ #           ""TARGET_CLEAN""
+ ############################################################################
+ */
+
+module memory_dp(/*AUTOARG*/
+   // Outputs
+   rd_data,
+   // Inputs
+   wr_clk, wr_en, wr_addr, wr_data, rd_clk, rd_en, rd_addr
+   );
+
+   parameter AW      = 14;   
+   parameter DW      = 32;
+   parameter WED     = DW/8; //one per byte  
+   parameter MD      = 1<<AW;//memory depth
+
+   //write-port
+   input               wr_clk; //write clock
+   input [WED-1:0]     wr_en;  //write enable vector
+   input [AW-1:0]      wr_addr;//write address
+   input [DW-1:0]      wr_data;//write data
+
+   //read-port   
+   input \t       rd_clk; //read clock
+   input \t       rd_en;  //read enable
+   input [AW-1:0]      rd_addr;//read address
+   output[DW-1:0]      rd_data;//read output data
+   
+   //////////////////////
+   //SIMPLE MEMORY MODEL 
+   //////////////////////   
+
+   reg [DW-1:0]        ram    [MD-1:0];  
+   reg [DW-1:0]        rd_data;
+   
+   //read port
+   always @ (posedge rd_clk)
+     if(rd_en)       
+       rd_data[DW-1:0] <= ram[rd_addr[AW-1:0]];
+   
+   //write port
+   generate
+      genvar \t     i;
+      for (i = 0; i < WED; i = i+1) begin: gen_ram
+\t always @(posedge wr_clk)
+           begin  
+              if (wr_en[i]) 
+                ram[wr_addr[AW-1:0]][(i+1)*8-1:i*8] <= wr_data[(i+1)*8-1:i*8];
+           end
+      end
+   endgenerate
+   
+endmodule // memory_dp
+
+
+/*
+  Copyright (C) 2014 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+  
+     
+
+"
+"
+/*###########################################################################
+ # Function: Single port memory wrapper
+ #           To run without hardware platform dependancy use:
+ #           `define TARGET_CLEAN""
+ ############################################################################
+ */
+
+module memory_sp(/*AUTOARG*/
+   // Outputs
+   dout,
+   // Inputs
+   clk, en, wen, addr, din
+   );
+
+   parameter AW      = 14;   
+   parameter DW      = 32;
+   parameter WED     = DW/8; //one write enable per byte  
+   parameter MD      = 1<<AW;//memory depth
+
+   //write-port
+   input               clk; //clock
+   input               en;  //memory access   
+   input [WED-1:0]     wen; //write enable vector
+   input [AW-1:0]      addr;//address
+   input [DW-1:0]      din; //data input
+   output [DW-1:0]     dout;//data output
+      
+   reg [DW-1:0]        ram    [MD-1:0];  
+   reg [DW-1:0]        rd_data;
+   reg [DW-1:0]        dout;
+   
+   //read port
+   always @ (posedge clk)
+     if(en)       
+       dout[DW-1:0] <= ram[addr[AW-1:0]];
+
+   //write port
+   generate
+      genvar \t     i;
+      for (i = 0; i < WED; i = i+1) begin: gen_ram
+\t always @(posedge clk)
+           begin  
+              if (wen[i] & en) 
+                ram[addr[AW-1:0]][(i+1)*8-1:i*8] <= din[(i+1)*8-1:i*8];
+           end
+      end
+   endgenerate
+   
+endmodule // memory_dp
+
+
+/*
+  Copyright (C) 2014 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+  
+     
+
+"
+"/*
+ ########################################################################
+ Generic Clock Domain Crossing Block
+ ########################################################################
+ */
+
+module fifo_cdc (/*AUTOARG*/
+   // Outputs
+   wait_out, access_out, packet_out,
+   // Inputs
+   clk_in, reset_in, access_in, packet_in, clk_out, reset_out,
+   wait_in
+   );
+
+   parameter DW    = 104;
+   parameter DEPTH     = 16;
+
+   /********************************/
+   /*Incoming Packet               */
+   /********************************/
+   input              clk_in;   
+   input              reset_in;
+   input \t      access_in;   
+   input [DW-1:0]     packet_in;   
+   output \t      wait_out;   
+
+   /********************************/
+   /*Outgoing Packet               */
+   /********************************/  
+   input              clk_out;   
+   input              reset_out;
+   output \t      access_out;   
+   output [DW-1:0]    packet_out;   
+   input \t      wait_in;   
+   
+   //Local wires
+   wire \t      wr_en;
+   wire \t      rd_en;   
+   wire \t      empty;
+   wire \t      full;
+   wire \t      valid;   
+   reg \t\t      access_out;
+      
+   assign wr_en    = access_in;//&~full
+   assign rd_en    = ~empty & ~wait_in;
+   assign wait_out =  full;
+
+   //Keep access high until ""acknowledge""
+   always @ (posedge clk_out)
+     if(reset_out)
+       access_out <=1\'b0;   
+     else if(~wait_in)
+       access_out <=rd_en;
+
+   //Read response fifo (from master)
+   defparam fifo.DW=DW;
+   defparam fifo.DEPTH=DEPTH;
+
+   fifo_async  fifo (.prog_full\t\t(full),//stay safe for now
+\t\t     .full\t\t(),
+\t\t    // Outputs
+\t\t    .dout\t\t(packet_out[DW-1:0]),
+\t\t    .empty\t\t(empty),
+\t\t    .valid\t\t(valid), 
+\t\t    // Inputs
+\t\t    .wr_rst\t\t(reset_in),
+\t\t    .rd_rst\t\t(reset_out),
+\t\t    .wr_clk\t\t(clk_in),
+\t\t    .rd_clk\t\t(clk_out),
+\t\t    .wr_en\t\t(wr_en),
+\t\t    .din\t\t(packet_in[DW-1:0]),
+\t\t    .rd_en\t\t(rd_en)
+\t\t    );
+      
+endmodule // fifo_cdc
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+"
+"/*
+ ########################################################################
+ Generic small FIFO using distributed memory
+ 
+ Caution:  There is no protection against overflow or underflow,
+           driving logic should avoid wen on full or ren on empty.
+ ########################################################################
+ */
+
+module fifo_sync
+  #(
+    // Address width (must be 5 => 32-deep FIFO)
+    parameter AW = 5,
+    // Data width
+    parameter DW = 16
+    )
+   (
+    input                clk,
+    input                reset,
+    input [DW-1:0]       wr_data,
+    input                wr_en,
+    input                rd_en,
+    output wire [DW-1:0] rd_data,
+    output reg           rd_empty,
+    output reg           wr_full
+    );
+   
+   reg [AW-1:0]          wr_addr;
+   reg [AW-1:0]          rd_addr;
+   reg [AW-1:0]          count;
+   
+   always @ ( posedge clk or posedge reset ) begin
+      if( reset ) 
+\tbegin\t   
+           wr_addr[AW-1:0] <= \'d0;
+           rd_addr[AW-1:0] <= \'b0;
+           count[AW-1:0] <= \'b0;
+           rd_empty      <= 1\'b1;
+           wr_full       <= 1\'b0;         
+      end else 
+\tbegin
+           if( wr_en & rd_en ) 
+\t     begin
+\t\twr_addr <= wr_addr + \'d1;
+\t\trd_addr <= rd_addr + \'d1;\t      
+             end 
+\t   else if( wr_en ) 
+\t     begin
+\t\twr_addr <= wr_addr + \'d1;
+\t\tcount <= count + \'d1;
+\t\trd_empty <= 1\'b0;
+\t\tif( & count )
+\t\t  wr_full <= 1\'b1;\t\t
+         end 
+\t   else if( rd_en ) 
+\t   begin\t      
+              rd_addr <= rd_addr + \'d1;
+              count <= count - \'d1;
+              wr_full <= 1\'b0;
+              if( count == \'d1 )
+\t\trd_empty <= 1\'b1;\t      
+           end
+\tend // else: !if( reset )
+   end // always @ ( posedge clk )
+      
+
+   defparam mem.DW=DW;
+   defparam mem.AW=AW;   
+   memory_dp mem (
+\t\t\t// Outputs
+\t\t\t.rd_data\t(rd_data[DW-1:0]),
+\t\t\t// Inputs
+\t\t\t.wr_clk\t\t(clk),
+\t\t\t.wr_en\t\t({(DW/8){wr_en}}),
+\t\t\t.wr_addr\t(wr_addr[AW-1:0]),
+\t\t\t.wr_data\t(wr_data[DW-1:0]),
+\t\t\t.rd_clk\t\t(clk),
+\t\t\t.rd_en\t\t(rd_en),
+\t\t\t.rd_addr\t(rd_addr[AW-1:0]));
+
+   
+endmodule // fifo_sync
+
+// Local Variables:
+// verilog-library-directories:(""."")
+// End:
+
+/*
+ Copyright (C) 2014 Adapteva, Inc.
+ Contributed by Fred Huettig <fred@adapteva.com>
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+ 
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+ 
+ You should have received a copy of the GNU General Public License
+ along with this program (see the file COPYING).  If not, see
+ <http://www.gnu.org/licenses/>.
+ */
+"
+"/* Model for xilinx async fifo*/
+module fifo_async_104x16 
+   (/*AUTOARG*/
+   // Outputs
+   full, prog_full, almost_full, dout, empty, valid,
+   // Inputs
+   wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
+   );
+   
+   parameter DW     = 104;//104 wide
+   parameter DEPTH  = 16; //
+   
+   //##########
+   //# RESET/CLOCK
+   //##########
+   input           wr_rst;     //asynchronous reset
+   input           rd_rst;     //asynchronous reset
+   input           wr_clk;    //write clock   
+   input           rd_clk;    //read clock   
+
+   //##########
+   //# FIFO WRITE
+   //##########
+   input           wr_en;   
+   input  [DW-1:0] din;
+   output          full;
+   output \t   prog_full;
+   output \t   almost_full;
+   
+   //###########
+   //# FIFO READ
+   //###########
+   input \t   rd_en;
+   output [DW-1:0] dout;
+   output          empty;
+   output          valid;
+
+   defparam fifo_model.DW=104;   
+   defparam fifo_model.DEPTH=16;   
+
+   fifo_async_model fifo_model (/*AUTOINST*/
+\t\t\t\t// Outputs
+\t\t\t\t.full\t\t(full),
+\t\t\t\t.prog_full\t(prog_full),
+\t\t\t\t.almost_full\t(almost_full),
+\t\t\t\t.dout\t\t(dout[DW-1:0]),
+\t\t\t\t.empty\t\t(empty),
+\t\t\t\t.valid\t\t(valid),
+\t\t\t\t// Inputs
+\t\t\t\t.wr_rst\t\t(wr_rst),
+\t\t\t\t.rd_rst\t\t(rd_rst),
+\t\t\t\t.wr_clk\t\t(wr_clk),
+\t\t\t\t.rd_clk\t\t(rd_clk),
+\t\t\t\t.wr_en\t\t(wr_en),
+\t\t\t\t.din\t\t(din[DW-1:0]),
+\t\t\t\t.rd_en\t\t(rd_en));
+      
+      
+endmodule // fifo_async
+// Local Variables:
+// verilog-library-directories:(""."" ""../../memory/hdl"")
+// End:
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"
+/*
+ Emesh interface wrapper for asynchronous fifo
+ 
+ */
+
+module fifo_async_emesh (/*AUTOARG*/
+   // Outputs
+   emesh_access_out, emesh_write_out, emesh_datamode_out,
+   emesh_ctrlmode_out, emesh_dstaddr_out, emesh_data_out,
+   emesh_srcaddr_out, fifo_full, fifo_progfull,
+   // Inputs
+   rd_clk, wr_clk, reset, emesh_access_in, emesh_write_in,
+   emesh_datamode_in, emesh_ctrlmode_in, emesh_dstaddr_in,
+   emesh_data_in, emesh_srcaddr_in, fifo_read
+   );
+
+   //Clocks
+   input         rd_clk;
+   input         wr_clk;
+   input \t reset;
+   
+   //input-data
+   input \t emesh_access_in;
+   input \t emesh_write_in;
+   input [1:0] \t emesh_datamode_in;
+   input [3:0] \t emesh_ctrlmode_in;
+   input [31:0]  emesh_dstaddr_in;
+   input [31:0]  emesh_data_in;
+   input [31:0]  emesh_srcaddr_in;
+
+   //output-data
+   output        emesh_access_out;
+   output        emesh_write_out;
+   output [1:0]  emesh_datamode_out;
+   output [3:0]  emesh_ctrlmode_out;
+   output [31:0] emesh_dstaddr_out;
+   output [31:0] emesh_data_out;
+   output [31:0] emesh_srcaddr_out;
+
+   //FIFO controls
+   input         fifo_read;
+   
+   output \t fifo_full;
+   output \t fifo_progfull;
+   
+   //wires
+   wire [103:0]  fifo_din;
+   wire [103:0]  fifo_dout;
+   wire \t fifo_empty;
+   
+   //Inputs to FIFO
+   assign fifo_din[103:0]={emesh_srcaddr_in[31:0],
+\t\t\t   emesh_data_in[31:0],
+\t\t\t   emesh_dstaddr_in[31:0],
+\t\t\t   emesh_ctrlmode_in[3:0],
+\t\t\t   emesh_datamode_in[1:0],
+\t\t\t   emesh_write_in,
+\t\t\t   1\'b0
+\t\t\t   };
+   
+   //Outputs
+   assign emesh_access_out         = ~fifo_empty;
+   assign emesh_write_out          =  fifo_dout[1];
+   assign emesh_datamode_out[1:0]  =  fifo_dout[3:2];
+   assign emesh_ctrlmode_out[3:0]  =  fifo_dout[7:4];
+   assign emesh_dstaddr_out[31:0]  =  fifo_dout[39:8];
+   assign emesh_data_out[31:0]     =  fifo_dout[71:40];
+   assign emesh_srcaddr_out[31:0]  =  fifo_dout[103:72];
+
+`ifdef TARGET_XILINX   
+   fifo_async_104x32 fifo_async_104x32 (.dout\t\t(fifo_dout[103:0]),
+\t\t\t\t\t.full\t\t(fifo_full),
+\t\t\t\t\t.empty\t\t(fifo_empty),
+\t\t\t\t\t.prog_full\t(fifo_progfull),
+\t\t\t\t\t//inputs
+\t\t\t\t\t.rst\t\t(reset),
+\t\t\t\t\t.wr_clk\t\t(wr_clk),
+\t\t\t\t\t.rd_clk\t\t(rd_clk),
+\t\t\t\t\t.din\t\t(fifo_din[103:0]),
+\t\t\t\t\t.wr_en\t\t(emesh_access_in),
+\t\t\t\t\t.rd_en\t\t(fifo_read)
+\t\t\t\t\t);
+   
+`elsif TARGET_CLEAN
+
+   wire \t tmp_progfull;    
+   assign fifo_progfull = tmp_progfull | fifo_full;//HACK, need to fix this
+   
+
+  fifo_async #(.DW(104), .AW(5))  fifo_async (
+\t\t\t\t\t.rd_data\t  (fifo_dout[103:0]),
+\t\t\t\t\t.wr_fifo_progfull (tmp_progfull),
+\t\t\t\t\t.wr_fifo_full\t  (fifo_full),
+\t\t\t\t\t.rd_fifo_empty\t  (fifo_empty),
+\t\t\t\t\t//inputs
+\t\t\t\t\t.reset\t\t(reset),
+\t\t\t\t\t.wr_clk\t\t(wr_clk),
+\t\t\t\t\t.rd_clk\t\t(rd_clk),
+\t\t\t\t\t.wr_data\t(fifo_din[103:0]),
+\t\t\t\t\t.wr_write\t(emesh_access_in),
+\t\t\t\t\t.rd_read\t(fifo_read)
+\t\t\t\t\t);
+`elsif TARGET_ALTERA
+  //SOMETHING
+`endif
+
+   
+endmodule // fifo_sync
+// Local Variables:
+// verilog-library-directories:(""."" ""../../stubs/hdl"")
+// End:
+
+/*
+ Copyright (C) 2014 Adapteva, Inc.
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+ 
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+ 
+ You should have received a copy of the GNU General Public License
+ along with this program (see the file COPYING).  If not, see
+ <http://www.gnu.org/licenses/>.
+ */
+"
+"module PLLE2_BASE (/*AUTOARG*/
+   // Outputs
+   LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5,
+   CLKFBOUT,
+   // Inputs
+   CLKIN1, RST, PWRDWN, CLKFBIN
+   );
+
+   parameter BANDWIDTH          = 0;
+   parameter CLKFBOUT_MULT      = 1;
+   parameter CLKFBOUT_PHASE     = 0;
+   parameter CLKIN1_PERIOD      = 10;
+   parameter DIVCLK_DIVIDE      = 1;
+   parameter REF_JITTER1        = 0;
+   parameter STARTUP_WAIT       = 0;
+
+   parameter CLKOUT0_DIVIDE     = 1;
+   parameter CLKOUT0_DUTY_CYCLE = 0.5;
+   parameter CLKOUT0_PHASE      = 0;
+
+   parameter CLKOUT1_DIVIDE     = 1;
+   parameter CLKOUT1_DUTY_CYCLE = 0.5;
+   parameter CLKOUT1_PHASE      = 0;
+
+   parameter CLKOUT2_DIVIDE     = 1;
+   parameter CLKOUT2_DUTY_CYCLE = 0.5;
+   parameter CLKOUT2_PHASE      = 0;
+   
+   parameter CLKOUT3_DIVIDE     = 1;
+   parameter CLKOUT3_DUTY_CYCLE = 0.5;
+   parameter CLKOUT3_PHASE      = 0;
+
+   parameter CLKOUT4_DIVIDE     = 1;   
+   parameter CLKOUT4_DUTY_CYCLE = 0.5;
+   parameter CLKOUT4_PHASE      = 0;
+
+   parameter CLKOUT5_DIVIDE     = 1;
+   parameter CLKOUT5_DUTY_CYCLE = 0.5;
+   parameter CLKOUT5_PHASE      = 0;
+
+   //#LOCAL DERIVED PARAMETERS
+   parameter VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT;
+   parameter CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE * (CLKOUT0_PHASE/360);
+   parameter CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
+   parameter CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
+   parameter CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
+   parameter CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
+   parameter CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
+      
+   //inputs
+   input CLKIN1;
+   input RST;
+   input PWRDWN;
+   input CLKFBIN;
+   
+   //outputs
+   output LOCKED;
+   output CLKOUT0;
+   output CLKOUT1;
+   output CLKOUT2;
+   output CLKOUT3;
+   output CLKOUT4;
+   output CLKOUT5;
+   output CLKFBOUT;
+  
+   //##############
+   //#VCO 
+   //##############
+   reg \t  vco_clk;
+   initial
+     begin
+\tvco_clk = 1\'b0;\t
+     end
+   
+   always
+     #(VCO_PERIOD/2) vco_clk = ~vco_clk;
+
+   //##############
+   //#DIVIDERS
+   //##############
+   wire [3:0] DIVCFG[5:0]; 
+   wire [5:0] CLKOUT_DIV;
+      
+   assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE);
+   assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
+   assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
+   assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
+   assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
+   assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
+
+
+   //ugly POR reset
+   reg \t      POR;
+   initial
+     begin
+\tPOR=1\'b1;
+\t#1
+\tPOR=1\'b0;\t
+     end
+
+   genvar i;
+   generate for(i=0; i<6; i=i+1)
+     begin : gen_clkdiv
+\tclock_divider clkdiv (/*AUTOINST*/
+\t\t\t      // Outputs
+\t\t\t      .clkout\t\t(CLKOUT_DIV[i]),
+\t\t\t      // Inputs
+\t\t\t      .clkin\t\t(vco_clk),
+\t\t\t      .divcfg\t\t(DIVCFG[i]),
+\t\t\t      .reset\t\t(RST | POR)
+\t\t\t      );\t\t
+     end      
+   endgenerate
+
+   //##############
+   //#PHASE DELAY
+   //##############
+   reg CLKOUT0;
+   reg CLKOUT1;
+   reg CLKOUT2;
+   reg CLKOUT3;
+   reg CLKOUT4;
+   reg CLKOUT5;
+   
+   always @ (CLKOUT_DIV)
+     begin\t
+\tCLKOUT0 <= #(CLK0_DELAY) CLKOUT_DIV[0];
+\tCLKOUT1 <= #(CLK1_DELAY) CLKOUT_DIV[1];
+\tCLKOUT2 <= #(CLK2_DELAY) CLKOUT_DIV[2];
+\tCLKOUT3 <= #(CLK3_DELAY) CLKOUT_DIV[3];
+\tCLKOUT4 <= #(CLK4_DELAY) CLKOUT_DIV[4];
+\tCLKOUT5 <= #(CLK5_DELAY) CLKOUT_DIV[5];
+     end
+
+   //##############
+   //#DUMMY DRIVES
+   //##############
+   assign CLKFBOUT=CLKIN1;
+   assign LOCKED=1\'b0;
+  
+   
+endmodule // PLLE2_BASE
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+"
+"module RAM32X1D (/*AUTOARG*/
+   // Outputs
+   DPO, SPO,
+   // Inputs
+   A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE
+   );
+
+   //inputs
+   input A0;
+   input A1;
+   input A2;
+   input A3;
+   input A4;
+   input D;
+   input DPRA0;
+   input DPRA1;
+   input DPRA2;
+   input DPRA3;
+   input DPRA4;
+   input WCLK;
+   input WE;
+   
+   //outputs
+   output DPO;
+   output SPO;
+
+   assign DPO=1'b0;
+   assign SPO=1'b0;
+   
+  
+endmodule // RAM32X1D
+
+"
+"module erx (/*AUTOARG*/
+   // Outputs
+   rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
+   rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
+   rxrr_access, rxrr_packet, erx_cfg_wait, timeout, mailbox_full,
+   mailbox_not_empty,
+   // Inputs
+   erx_reset,erx_ioreset, sys_reset, sys_clk, rx_lclk, rx_lclk_div4,
+   rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
+   rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait, erx_cfg_access,
+   erx_cfg_packet
+   );
+
+   parameter AW          = 32;
+   parameter DW          = 32;
+   parameter PW          = 104;
+   parameter RFAW        = 6;
+   parameter ID          = 12\'h800;
+   parameter IOSTD_ELINK = ""LVDS_25"";
+   parameter ETYPE       = 1;   
+
+   //Synched resets
+   input          erx_reset;                   // reset for core logic
+   input          sys_reset;                   // reset for fifos
+   input \t  erx_ioreset;
+   
+
+   //Clocks
+   input \t  sys_clk;\t               // system clock for rx fifos
+   input \t  rx_lclk;\t               // fast clock for io
+   input \t  rx_lclk_div4;\t\t       // slow clock for rest of logic
+   output \t  rx_lclk_pll;                 // clock output for pll
+   
+   //FROM IO Pins
+   input \t  rxi_lclk_p,   rxi_lclk_n;     // rx clock input
+   input \t  rxi_frame_p,  rxi_frame_n;    // rx frame signal
+   input [7:0] \t  rxi_data_p,   rxi_data_n;     // rx data
+   output \t  rxo_wr_wait_p,rxo_wr_wait_n;  // rx write pushback output
+   output \t  rxo_rd_wait_p,rxo_rd_wait_n;  // rx read pushback output
+
+   //Master write
+   output \t   rxwr_access;\t\t
+   output [PW-1:0] rxwr_packet;
+   input \t   rxwr_wait;
+
+   //Master read request
+   output \t   rxrd_access;\t\t
+   output [PW-1:0] rxrd_packet;
+   input \t   rxrd_wait;
+
+   //Slave read response
+   output \t   rxrr_access;\t\t
+   output [PW-1:0] rxrr_packet;
+   input \t   rxrr_wait;
+  
+   //Configuration Interface (from ETX)
+   input \t   erx_cfg_access;
+   input [PW-1:0]  erx_cfg_packet;
+   output \t   erx_cfg_wait;
+   
+   //Readback timeout (synchronized to sys_c
+   output \t   timeout;
+   output \t   mailbox_full;
+   output \t   mailbox_not_empty;
+   
+   /*AUTOOUTPUT*/
+   /*AUTOINPUT*/
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\trx_access;\t\t// From erx_io of erx_io.v
+   wire\t\t\trx_burst;\t\t// From erx_io of erx_io.v
+   wire [PW-1:0]\trx_packet;\t\t// From erx_io of erx_io.v
+   wire\t\t\trx_rd_wait;\t\t// From erx_core of erx_core.v
+   wire\t\t\trx_wr_wait;\t\t// From erx_core of erx_core.v
+   wire\t\t\trxrd_fifo_access;\t// From erx_core of erx_core.v
+   wire [PW-1:0]\trxrd_fifo_packet;\t// From erx_core of erx_core.v
+   wire\t\t\trxrd_fifo_wait;\t\t// From erx_fifo of erx_fifo.v
+   wire\t\t\trxrr_fifo_access;\t// From erx_core of erx_core.v
+   wire [PW-1:0]\trxrr_fifo_packet;\t// From erx_core of erx_core.v
+   wire\t\t\trxrr_fifo_wait;\t\t// From erx_fifo of erx_fifo.v
+   wire\t\t\trxwr_fifo_access;\t// From erx_core of erx_core.v
+   wire [PW-1:0]\trxwr_fifo_packet;\t// From erx_core of erx_core.v
+   wire\t\t\trxwr_fifo_wait;\t\t// From erx_fifo of erx_fifo.v
+   // End of automatics
+
+   /***********************************************************/
+   /*RECEIVER  I/O LOGIC                                      */
+   /***********************************************************/
+   defparam erx_io.IOSTD_ELINK=IOSTD_ELINK;
+   defparam erx_io.ETYPE=ETYPE;   
+   erx_io erx_io (.reset\t\t(erx_ioreset),
+\t\t  /*AUTOINST*/
+\t\t  // Outputs
+\t\t  .rx_lclk_pll\t\t(rx_lclk_pll),
+\t\t  .rxo_wr_wait_p\t(rxo_wr_wait_p),
+\t\t  .rxo_wr_wait_n\t(rxo_wr_wait_n),
+\t\t  .rxo_rd_wait_p\t(rxo_rd_wait_p),
+\t\t  .rxo_rd_wait_n\t(rxo_rd_wait_n),
+\t\t  .rx_access\t\t(rx_access),
+\t\t  .rx_burst\t\t(rx_burst),
+\t\t  .rx_packet\t\t(rx_packet[PW-1:0]),
+\t\t  // Inputs
+\t\t  .rx_lclk\t\t(rx_lclk),
+\t\t  .rx_lclk_div4\t\t(rx_lclk_div4),
+\t\t  .rxi_lclk_p\t\t(rxi_lclk_p),
+\t\t  .rxi_lclk_n\t\t(rxi_lclk_n),
+\t\t  .rxi_frame_p\t\t(rxi_frame_p),
+\t\t  .rxi_frame_n\t\t(rxi_frame_n),
+\t\t  .rxi_data_p\t\t(rxi_data_p[7:0]),
+\t\t  .rxi_data_n\t\t(rxi_data_n[7:0]),
+\t\t  .rx_wr_wait\t\t(rx_wr_wait),
+\t\t  .rx_rd_wait\t\t(rx_rd_wait));
+   
+   /**************************************************************/
+   /*ELINK CORE LOGIC                                            */
+   /**************************************************************/
+   /*erx_core   AUTO_TEMPLATE ( .rx_packet\t(rx_packet[PW-1:0]),
+\t\t                .rx_access\t(rx_access),
+                                .erx_cfg_access\t(erx_cfg_access),
+\t\t                .erx_cfg_packet\t(erx_cfg_packet[PW-1:0]),
+                                .erx_cfg_wait\t(erx_cfg_wait),
+                                .rx_rd_wait\t(rx_rd_wait),
+\t\t                .rx_wr_wait\t(rx_wr_wait),
+    \t\t\t       .\\(.*\\)_packet   (\\1_fifo_packet[PW-1:0]),
+    \t\t\t       .\\(.*\\)_access   (\\1_fifo_access),
+       \t\t\t       .\\(.*\\)_wait     (\\1_fifo_wait),
+    );
+    */
+   
+   defparam erx_core.ID=ID;   
+   erx_core erx_core ( .clk\t\t(rx_lclk_div4),
+\t\t       .reset           (erx_reset),
+\t\t      /*AUTOINST*/
+\t\t      // Outputs
+\t\t      .rx_rd_wait\t(rx_rd_wait),\t\t // Templated
+\t\t      .rx_wr_wait\t(rx_wr_wait),\t\t // Templated
+\t\t      .rxrd_access\t(rxrd_fifo_access),\t // Templated
+\t\t      .rxrd_packet\t(rxrd_fifo_packet[PW-1:0]), // Templated
+\t\t      .rxrr_access\t(rxrr_fifo_access),\t // Templated
+\t\t      .rxrr_packet\t(rxrr_fifo_packet[PW-1:0]), // Templated
+\t\t      .rxwr_access\t(rxwr_fifo_access),\t // Templated
+\t\t      .rxwr_packet\t(rxwr_fifo_packet[PW-1:0]), // Templated
+\t\t      .erx_cfg_wait\t(erx_cfg_wait),\t\t // Templated
+\t\t      .mailbox_full\t(mailbox_full),
+\t\t      .mailbox_not_empty(mailbox_not_empty),
+\t\t      // Inputs
+\t\t      .rx_packet\t(rx_packet[PW-1:0]),\t // Templated
+\t\t      .rx_access\t(rx_access),\t\t // Templated
+\t\t      .rx_burst\t\t(rx_burst),
+\t\t      .rxrd_wait\t(rxrd_fifo_wait),\t // Templated
+\t\t      .rxrr_wait\t(rxrr_fifo_wait),\t // Templated
+\t\t      .rxwr_wait\t(rxwr_fifo_wait),\t // Templated
+\t\t      .erx_cfg_access\t(erx_cfg_access),\t // Templated
+\t\t      .erx_cfg_packet\t(erx_cfg_packet[PW-1:0])); // Templated
+
+   /************************************************************/
+   /*FIFOs                                                     */
+   /************************************************************/      
+   erx_fifo erx_fifo   (
+\t\t/*AUTOINST*/
+\t\t\t// Outputs
+\t\t\t.rxwr_access\t(rxwr_access),
+\t\t\t.rxwr_packet\t(rxwr_packet[PW-1:0]),
+\t\t\t.rxrd_access\t(rxrd_access),
+\t\t\t.rxrd_packet\t(rxrd_packet[PW-1:0]),
+\t\t\t.rxrr_access\t(rxrr_access),
+\t\t\t.rxrr_packet\t(rxrr_packet[PW-1:0]),
+\t\t\t.rxrd_fifo_wait\t(rxrd_fifo_wait),
+\t\t\t.rxrr_fifo_wait\t(rxrr_fifo_wait),
+\t\t\t.rxwr_fifo_wait\t(rxwr_fifo_wait),
+\t\t\t// Inputs
+\t\t\t.erx_reset\t(erx_reset),
+\t\t\t.sys_reset\t(sys_reset),
+\t\t\t.rx_lclk_div4\t(rx_lclk_div4),
+\t\t\t.sys_clk\t(sys_clk),
+\t\t\t.rxwr_wait\t(rxwr_wait),
+\t\t\t.rxrd_wait\t(rxrd_wait),
+\t\t\t.rxrr_wait\t(rxrr_wait),
+\t\t\t.rxrd_fifo_access(rxrd_fifo_access),
+\t\t\t.rxrd_fifo_packet(rxrd_fifo_packet[PW-1:0]),
+\t\t\t.rxrr_fifo_access(rxrr_fifo_access),
+\t\t\t.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
+\t\t\t.rxwr_fifo_access(rxwr_fifo_access),
+\t\t\t.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]));
+   
+endmodule // erx
+// Local Variables:
+// verilog-library-directories:(""."")
+// End:
+
+/*
+ Copyright (C) 2014 Adapteva, Inc.
+  
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+"
+"module erx_remap (/*AUTOARG*/
+   // Outputs
+   emesh_access_out, emesh_packet_out,
+   // Inputs
+   clk, reset, emesh_access_in, emesh_packet_in, remap_mode,
+   remap_sel, remap_pattern, remap_base
+   );
+
+   parameter AW = 32;
+   parameter DW = 32;
+   parameter PW = 104;
+   parameter ID = 12'h808;
+   
+   //Clock/reset
+   input clk;
+   input reset;
+   
+   //Input from arbiter
+   input          emesh_access_in;
+   input [PW-1:0] emesh_packet_in;
+   
+   //Configuration
+   input [1:0] \t  remap_mode;    //00=none,01=static,02=continuity
+   input [11:0]   remap_sel;     //number of bits to remap
+   input [11:0]   remap_pattern; //static pattern to map to
+   input [31:0]   remap_base;    //remap offset
+   
+   //Output to TX IO   
+   output \t   emesh_access_out;
+   output [PW-1:0] emesh_packet_out;
+
+   wire [31:0] \t   static_remap;
+   wire [31:0] \t   dynamic_remap;
+   wire [31:0] \t   remap_mux;
+   wire \t   write_in;
+   wire \t   read_in;
+   wire [31:0] \t   addr_in;
+   wire [31:0] \t   addr_out;
+   wire \t   remap_en;
+   
+   reg \t\t   emesh_access_out;
+   reg [PW-1:0]    emesh_packet_out;
+
+   //TODO:FIX!??
+   parameter[5:0]  colid = ID[5:0];
+   
+   //parsing packet
+   assign addr_in[31:0]  =  emesh_packet_in[39:8];
+   assign write_in       =  emesh_packet_in[1];
+   assign read_in        =  ~emesh_packet_in[1];
+   
+   //simple static remap
+   assign static_remap[31:20] = (remap_sel[11:0] & remap_pattern[11:0]) |
+\t\t\t        (~remap_sel[11:0] & addr_in[31:20]);
+
+   assign static_remap[19:0]  = addr_in[19:0];
+    
+   //more complex compresssed map
+   assign dynamic_remap[31:0] = addr_in[31:0]    //input
+\t\t\t     - (colid << 20)     //subtracing elink (start at 0)
+\t\t\t     + remap_base[31:0]  //adding back base
+                             - (addr_in[31:26]<<$clog2(colid));
+     \t\t\t     
+
+   //Static, dynamic, or no remap
+   assign remap_mux[31:0]  = (remap_mode[1:0]==2'b00) ? addr_in[31:0] :
+\t\t\t     (remap_mode[1:0]==2'b01) ? static_remap[31:0] :
+\t  \t\t                                dynamic_remap[31:0];
+
+
+   //Access
+   always @ (posedge clk)
+     if (reset)
+       emesh_access_out         <= 1'b0;
+     else
+       emesh_access_out         <= emesh_access_in;
+
+   //Packet
+   always @ (posedge clk)    
+       emesh_packet_out[PW-1:0] <= {emesh_packet_in[103:40],
+                                    remap_mux[31:0],
+                                    emesh_packet_in[7:0]
+\t\t\t\t    };
+   
+endmodule // etx_mux
+
+"
+"//`timescale 1 ns / 100 ps
+module dv_emmu
+  (input clk,
+   input reset,
+   input go);
+
+   parameter DW   = 32;        //data width of
+   parameter AW   = 32;        //data width of 
+   parameter IW   = 12;        //index size of table
+   parameter PAW  = 64;        //physical address width of output
+   parameter MW   = PAW-AW+IW; //table data width
+   parameter MD   = 1<<IW;     //memory depth
+
+   
+   //Stimulus to drive
+   reg \t      mmu_en;
+   
+   //Reg interface
+   reg        mi_en;
+   reg [12:0] mi_addr;
+   reg [31:0] mi_din;
+   reg [3:0]  mi_we;
+   
+   
+   //emesh interface
+   reg              emesh_access_in;
+   reg              emesh_write_in;
+   reg [1:0]        emesh_datamode_in;
+   reg [3:0]        emesh_ctrlmode_in;
+   reg [AW-1:0]     emesh_dstaddr_in;
+   reg [AW-1:0]     emesh_srcaddr_in;
+   reg [DW-1:0]     emesh_data_in;
+   
+   //Test junk
+   reg [1:0]  test_state;
+  
+   //Pattern generator
+   //1.) Write some patterns through mi_interface
+   //2.) Write some patterns from emesh interface
+      
+   always @ (negedge clk) begin
+     if(go)
+       begin
+\t  case(test_state[1:0])
+\t    2\'b00://write entries
+\t      if(mi_addr[12:0]<13\'h16)
+\t\tbegin
+\t\t   mi_en            <= 1\'b1;
+\t\t   mi_we[3:0]       <= 4\'b1111;
+\t\t   mi_addr[12:0]    <= mi_addr[12:0] + 1\'b1;\t  
+\t\t   /* verilator lint_off WIDTH */
+\t\t   mi_din[31:0]     <= mi_addr[0] ? (mi_addr[12:0]+32\'hFFFFF000) : 32\'hFFFFFFFF;
+\t\t   /* verilator lint_on WIDTH */
+\t\tend
+\t      else
+\t\tbegin
+\t\t   test_state       <= 2\'b01;
+\t\t   mi_en            <= 1\'b0;
+\t\tend
+\t    2\'b01://
+\t      if(emesh_dstaddr_in[31:0]<32\'h00800000)
+\t\tbegin\t    
+\t\t   emesh_access_in        <= 1\'b1;
+\t\t   emesh_write_in         <= 1\'b1;
+\t\t   emesh_dstaddr_in[31:0] <= emesh_dstaddr_in[31:0] + 32\'h00100001;
+\t\t   emesh_ctrlmode_in[3:0] <= 4\'b1111;
+\t\t   emesh_datamode_in[1:0] <= 2\'b11;
+\t\t   emesh_data_in[31:0]    <= 32\'h12345678;
+\t\t   emesh_srcaddr_in[31:0] <= 32\'h55555555;
+\t\tend
+\t      else
+\t\tbegin
+\t\t   test_state       <= 2\'b10;
+\t\t   emesh_access_in <= 1\'b0;
+\t\tend // else: !if(~done)
+\t    2\'b10://init array
+\t      begin
+\t\t mi_addr[5:0]     <= mi_addr[5:0]-1\'b1;
+\t      end
+\t    default : test_state <= test_state;
+\t  endcase // case (test_state[1:0])
+       end // if (go)
+      if (reset) begin
+\t mi_we[3:0]             <= 4\'b0;
+\t mi_en                  <= 1\'b0;
+\t mi_addr[12:0]          <= 13\'b0;
+\t mi_din[31:0]           <= 32\'h55555000;
+\t test_state[1:0]        <= 2\'b00;
+         emesh_access_in        <= 1\'b0;
+\t emesh_write_in         <= 1\'b0;
+\t emesh_ctrlmode_in[3:0] <= 4\'b0;
+\t emesh_datamode_in[1:0] <= 2\'b0;
+\t emesh_dstaddr_in[31:0] <= 32\'b0;
+\t emesh_srcaddr_in[31:0] <= 32\'b0;
+\t emesh_data_in[31:0]    <= 32\'b0;
+\t mmu_en                 <= 1\'b1;
+     end
+   end
+   wire done =  (mi_addr[5:0]==6\'b001101);
+  
+   
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\temmu_access_out;\t// From emmu of emmu.v
+   wire [3:0]\t\temmu_ctrlmode_out;\t// From emmu of emmu.v
+   wire [DW-1:0]\temmu_data_out;\t\t// From emmu of emmu.v
+   wire [1:0]\t\temmu_datamode_out;\t// From emmu of emmu.v
+   wire [63:0]\t\temmu_dstaddr_out;\t// From emmu of emmu.v
+   wire [AW-1:0]\temmu_srcaddr_out;\t// From emmu of emmu.v
+   wire\t\t\temmu_write_out;\t\t// From emmu of emmu.v
+   wire [31:0]\t\tmi_dout;\t\t// From emmu of emmu.v
+   // End of automatics
+   /*AUTOWIRE*/
+   
+   //DUT
+   emmu emmu(.mi_clk\t\t\t(clk),
+\t     /*AUTOINST*/
+\t     // Outputs
+\t     .mi_dout\t\t\t(mi_dout[31:0]),
+\t     .emmu_access_out\t\t(emmu_access_out),
+\t     .emmu_write_out\t\t(emmu_write_out),
+\t     .emmu_datamode_out\t\t(emmu_datamode_out[1:0]),
+\t     .emmu_ctrlmode_out\t\t(emmu_ctrlmode_out[3:0]),
+\t     .emmu_dstaddr_out\t\t(emmu_dstaddr_out[63:0]),
+\t     .emmu_srcaddr_out\t\t(emmu_srcaddr_out[AW-1:0]),
+\t     .emmu_data_out\t\t(emmu_data_out[DW-1:0]),
+\t     // Inputs
+\t     .clk\t\t\t(clk),
+\t     .mmu_en\t\t\t(mmu_en),
+\t     .mi_en\t\t\t(mi_en),
+\t     .mi_we\t\t\t(mi_we[3:0]),
+\t     .mi_addr\t\t\t({3\'b000,mi_addr[12:0]}),
+\t     .mi_din\t\t\t(mi_din[31:0]),
+\t     .emesh_access_in\t\t(emesh_access_in),
+\t     .emesh_write_in\t\t(emesh_write_in),
+\t     .emesh_datamode_in\t\t(emesh_datamode_in[1:0]),
+\t     .emesh_ctrlmode_in\t\t(emesh_ctrlmode_in[3:0]),
+\t     .emesh_dstaddr_in\t\t(emesh_dstaddr_in[AW-1:0]),
+\t     .emesh_srcaddr_in\t\t(emesh_srcaddr_in[AW-1:0]),
+\t     .emesh_data_in\t\t(emesh_data_in[DW-1:0]));
+
+   
+endmodule // dv_emmu
+// Local Variables:
+// verilog-library-directories:(""."" ""../hdl"")
+// End:
+
+
+
+"
+"module BUFG (/*AUTOARG*/
+   // Outputs
+   O,
+   // Inputs
+   I
+   );
+   input I;
+   output O;
+
+   assign O = I;
+   
+endmodule // IBUFDS
+"
+"`include ""elink_regmap.v""
+module erx_arbiter (/*AUTOARG*/
+   // Outputs
+   rx_rd_wait, rx_wr_wait, edma_wait, ecfg_wait, rxwr_access,
+   rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet,
+   // Inputs
+   erx_rr_access, erx_packet, emmu_access, emmu_packet, edma_access,
+   edma_packet, ecfg_access, ecfg_packet, timeout, rxwr_wait,
+   rxrd_wait, rxrr_wait
+   );
+
+   parameter AW   = 32;
+   parameter DW   = 32;
+   parameter PW   = 104;
+   parameter ID   = 12\'h800; //link id
+   parameter RFAW = 6;
+   
+   
+   //From IO (for rr)   
+   input           erx_rr_access;
+   input [PW-1:0]  erx_packet;
+   output          rx_rd_wait; //for IO
+   output          rx_wr_wait; //for IO
+
+   //From EMMU (writes)  
+   input           emmu_access;
+   input [PW-1:0]  emmu_packet;
+
+   //From DMA
+   input           edma_access;
+   input [PW-1:0]  edma_packet;
+   output \t   edma_wait;
+
+   //From ETX
+   input           ecfg_access;
+   input [PW-1:0]  ecfg_packet;
+   output \t   ecfg_wait;
+
+   //From timeout circuit
+   input \t   timeout;
+   
+   //To Master Write FIFO
+   output \t   rxwr_access;
+   output [PW-1:0] rxwr_packet;   
+   input           rxwr_wait;
+   
+   //To Master Read FIFO
+   output \t   rxrd_access;
+   output [PW-1:0] rxrd_packet;   
+   input           rxrd_wait;
+   
+   //To Slave Read Response FIFO
+   output \t   rxrr_access;
+   output [PW-1:0] rxrr_packet;   
+   input           rxrr_wait;
+
+   //wires
+   wire            emmu_write;
+   wire \t   emmu_read;
+   
+   wire [11:0] \t   myid;
+
+   //####################################
+   //Splicing pakets
+   //####################################
+   assign \t myid[11:0] = ID;   
+   
+   //####################################
+   //Read response path (from IO or cfg)
+   //####################################
+   
+   assign rxrr_access         = erx_rr_access   |
+\t\t\t        ecfg_access;
+   
+   assign rxrr_packet[PW-1:0] = erx_rr_access ?  erx_packet[PW-1:0] :
+\t\t\t \t                 ecfg_packet[PW-1:0];
+
+   assign ecfg_wait           = erx_rr_access;
+
+   //####################################
+   //Write Path (direct)
+   //####################################
+   assign emmu_write          = emmu_packet[1];
+
+   assign rxwr_access         = emmu_access & emmu_write;
+   
+   assign rxwr_packet[PW-1:0] = emmu_packet[PW-1:0];
+         
+   //####################################
+   //Read Request Path 
+   //####################################
+
+   assign emmu_read           = emmu_access & ~emmu_write;
+   
+   assign rxrd_access         = emmu_read | edma_access;
+   
+   assign rxrd_packet[PW-1:0] = emmu_read ? emmu_packet[PW-1:0] : 
+\t\t\t\t            edma_packet[PW-1:0];
+   
+   //####################################
+   //Wait Signals
+   //####################################   
+   
+   assign rx_rd_wait    = rxrd_wait;
+   assign rx_wr_wait    = rxwr_wait | rxrr_wait;
+   assign edma_wait     = rxrd_wait | emmu_read;
+   assign erx_cfg_wait  = rxwr_wait | rxrr_wait;   
+   
+endmodule // erx_arbiter
+
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"" ""../../emmu/hdl"")
+// End:
+
+//#############################################################################
+/*
+  This file is part of the Parallella Project.
+
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"`define CFG_FAKECLK   1      /*stupid verilator doesn\'t get clock gating*/
+`define CFG_MDW       32     /*Width of mesh network*/
+`define CFG_DW        32     /*Width of datapath*/
+`define CFG_AW        32     /*Width of address space*/
+`define CFG_LW        8      /*Link port width*/
+`define CFG_NW        13     /*Number of bytes in the transmission*/
+
+
+module e16_arbiter_priority(/*AUTOARG*/
+   // Outputs
+   grant, arb_wait,
+   // Inputs
+   clk, clk_en, reset, hold, request
+   );
+   
+   parameter ARW=99;
+   
+   input            clk;
+   input            clk_en;
+   input            reset;
+
+   input            hold;      
+   input  [ARW-1:0] request;
+
+   output [ARW-1:0] grant;
+   output [ARW-1:0] arb_wait;
+
+
+   //wires
+   wire [ARW-1:0] grant_mask;
+   wire [ARW-1:0] request_mask;
+   
+   //regs
+   reg [ARW-1:0]  grant_hold;
+
+   //hold circuit
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       grant_hold[ARW-1:0] <= {(ARW){1\'b0}};
+     else if(clk_en)       
+       grant_hold[ARW-1:0] <= grant[ARW-1:0] & {(ARW){hold}};
+
+   //request blocking based on held previous requests
+   genvar i;
+   generate              
+      for(i=0;i<ARW-1;i=i+1) begin : gen_block
+         assign request_mask[i]=request[i] & ~(|grant_hold[ARW-1:i+1]);\t 
+      end
+      assign request_mask[ARW-1]=request[ARW-1];//awlays on, loses on priority 
+   endgenerate
+   
+   genvar j;
+   assign grant_mask[0]   = 1\'b0;   
+   generate for (j=ARW-1; j>=1; j=j-1) begin : gen_arbiter     
+      assign grant_mask[j] = |request_mask[j-1:0];
+   end
+   endgenerate
+        
+   //grant circuit
+   assign grant[ARW-1:0] = request_mask[ARW-1:0] & ~grant_mask[ARW-1:0];
+
+   //wait circuit  
+   assign arb_wait[ARW-1:0] = request[ARW-1:0] & ({(ARW){hold}} | ~grant[ARW-1:0]);
+
+
+   //makes sure we hold request one cycle after wait is gone!!!
+   // synthesis translate_off
+   always @*
+     if((|(grant_hold[ARW-1:0] & ~request[ARW-1:0])) & ~reset  & $time> 0)
+       begin
+\t  $display(""ERROR>>Request not held steady in cell %m at time %0d"", $time);
+       end
+   // synthesis translate_on
+   
+endmodule // arbiter_priority
+
+   
+     
+module e16_arbiter_roundrobin(/*AUTOARG*/
+   // Outputs
+   grants,
+   // Inputs
+   clk, clk_en, reset, en_rotate, requests
+   );
+
+   /************************************************************/
+   /*PARAMETERS                                                */
+   /************************************************************/   
+   parameter ARW  = 5;
+
+
+   /************************************************************/
+   /*BASIC INTERFACE                                           */
+   /****I*******************************************************/
+   input            clk;
+   input            clk_en;  //2nd level manual clock gater   
+   input            reset;
+
+   /************************************************************/
+   /*ARBITRATION INTERFACE                                     */
+   /****I*******************************************************/
+   input            en_rotate;//enable mask rotation, makes arbiter more flexible
+                              //in mesh there should be a way to control freq of rotation 
+
+   input  [ARW-1:0] requests; 
+   output [ARW-1:0] grants;   
+
+   //loop variable
+   integer m;    
+
+   //Masks
+   reg  [ARW-1:0]   request_mask; //rotating mask
+
+
+   //Wires
+   reg [2*ARW-1:0]  grants_rotate_buffer;   
+   reg [ARW-1:0]    grants;         //output grants      
+   wire [ARW-1:0]   shifted_requests[ARW-1:0];
+   wire [ARW-1:0]   shifted_grants[ARW-1:0];
+   wire [2*ARW-1:0] requests_rotate_buffer;
+   
+   /********************************************************************/
+   /*Rotating Mask Pointer On Every Clock Cycle                        */
+   /********************************************************************/
+   //request vector[7:0]-->regular
+   //hold vector[7:0]   -->sets the priority to the request when it wins
+   //                      there can be multiple bits set
+   //                      the only one active is the one where the
+   //                      mask is currently located.
+   //                      en_rotate=~(hold_vec[7:0] & requeste_mask[7:0])
+
+   //every request should also be able to send a ""start/stop"" signal
+   //instead of having an en_rotate signal, we have
+   //if then en-rotate signal is low
+  
+   always @ ( posedge clk or posedge reset)
+     if(reset)
+       request_mask[ARW-1:0] <= {{(ARW-1){1\'b0}},1\'b1};   
+     else if(clk_en)
+       if(en_rotate)
+\t request_mask[ARW-1:0] <= {request_mask[ARW-2:0],request_mask[ARW-1]};
+   
+   /********************************************************************/
+   /*Creating Shifted Request Vectors                                  */
+   /********************************************************************/
+   assign requests_rotate_buffer[2*ARW-1:0]={requests[ARW-1:0],requests[ARW-1:0]};
+
+   genvar i;
+   generate
+      for (i=0;i<ARW;i=i+1) begin: gen_requests\t
+\t assign shifted_requests[i]=requests_rotate_buffer[ARW-1+i:i];      
+      end
+   endgenerate
+
+   /********************************************************************/
+   /*Priority Encoders For Each Vector                                 */
+   /********************************************************************/
+   //Priority Encoders For Each Vector   
+   genvar k;   
+   generate
+      for (k=0;k<ARW;k=k+1) begin: gen_arbiter
+\t   e16_arbiter_priority #(.ARW(ARW)) simple_arbiter(
+                                                        .clk       (clk),
+\t\t\t\t\t                .clk_en    (clk_en),
+\t\t\t\t\t                .reset     (reset),                                     
+\t\t\t\t\t                .hold      (1\'b0),\t\t\t\t 
+\t\t\t\t\t                .request   (shifted_requests[k]),                         
+                                                        .arb_wait  (),
+\t\t\t\t\t                .grant     (shifted_grants[k])
+\t\t\t\t\t                );      
+      end
+   endgenerate   
+
+   /********************************************************************/
+   /*One Hot Mux                                                       */
+   /********************************************************************/
+   //Note that grants have to be rotate back to their right positiona again.
+   always @*
+     begin\t
+\tgrants[ARW-1:0]      = {(ARW){1\'b0}};
+\tfor(m=0;m<ARW;m=m+1)
+\t  begin
+\t     grants_rotate_buffer[2*ARW-1:0]={shifted_grants[m],shifted_grants[m]};\t
+\t     grants[ARW-1:0]                =grants[ARW-1:0] |
+\t                                     ({(ARW){request_mask[m]}} & 
+\t\t\t\t\t      grants_rotate_buffer[2*ARW-1-m-:ARW]
+\t\t\t\t\t      );
+\t  end
+     end
+     
+   /********************************************************************/
+   /*Checkers                                                          */
+   /********************************************************************/
+/*
+   
+   // synthesis translate_off
+   always @*     
+     begin
+\tif((|(grants[ARW-1:0]&~requests[ARW-1:0])) & $time>0)
+\t  $display(""ERROR>>Grant granted with out request in cell %m at time %0d"",$time);
+\tif((~(|grants[ARW-1:0]) & (|requests[ARW-1:0])) & $time>0)
+\t  $display(""ERROR>>Zero granted when there was a request in cell %m at time %0d"",$time);\t
+     end   
+   // synthesis translate_on
+*/
+   \t    
+endmodule // arbiter_roundrobin
+// ###############################################################
+// # FUNCTION: Synchronous clock divider that divides by integer
+// #  NOTE:     Combinatorial output becomes new clock
+// ############################################################### 
+
+module e16_clock_divider(/*AUTOARG*/
+   // Outputs
+   clk_out, clk_out90,
+   // Inputs
+   clk_in, reset, div_cfg
+   );
+
+
+   input       clk_in;    // Input clock
+   input       reset;
+   input [3:0] div_cfg;   // Divide factor
+   
+   output      clk_out;   // Divided clock phase aligned with clk_in 
+   output      clk_out90; // Divided clock with 90deg phase shift with clk_out
+
+
+   reg        clk_out_reg;
+   //reg        clk_out90_reg;
+   //reg        clk90_div2_reg;
+   reg [5:0]  counter;   
+   reg [5:0]  div_cfg_dec;
+
+   wire div2_sel;   
+   wire posedge_match;
+   wire negedge_match;  
+   wire posedge90_match;
+   wire negedge90_match; 
+    
+   wire clk_out90_div2;
+   wire clk_out90_div4;
+   wire clk_out90_div2_in;
+   wire clk_out90_div4_in;
+   // ###################
+   // # Decode div_cfg
+   // ###################
+
+   always @ (div_cfg[3:0])
+     begin
+\tcasez (div_cfg[3:0])
+\t  4\'b0000 : div_cfg_dec[5:0] = 6\'b000010;  // Divide by 2
+\t  4\'b0001 : div_cfg_dec[5:0] = 6\'b000100;  // Divide by 4
+\t  4\'b0010 : div_cfg_dec[5:0] = 6\'b001000;  // Divide by 8
+\t  4\'b0011 : div_cfg_dec[5:0] = 6\'b010000;  // Divide by 16
+\t  4\'b01?? : div_cfg_dec[5:0] = 6\'b100000;  // A lof of different ratios
+          4\'b1??? : div_cfg_dec[5:0] = 6\'b100000;  // Divide by 32
+\t  default : div_cfg_dec[5:0] = 6\'b000000;
+\tendcase // casez (div_cfg[3:0])
+     end // always @ (div_cfg[3:0])
+
+   assign div2_sel = div_cfg[3:0]==4\'b0;
+    
+
+   //Counter For Generating Toggling Edges
+   //always @ (posedge clk_in or posedge reset)
+   //if(reset)
+   //counter[5:0] <= 6\'b000001;// Reset value
+
+   always @ (posedge clk_in or posedge reset)
+     if (reset)
+       counter[5:0] <= 6\'b000001;   
+     else if(posedge_match)
+       counter[5:0] <= 6\'b000001;// Self resetting
+     else
+       counter[5:0] <= (counter[5:0]+6\'b000001);
+   
+   assign posedge_match    = (counter[5:0]==div_cfg_dec[5:0]);
+   assign negedge_match    = (counter[5:0]=={1\'b0,div_cfg_dec[5:1]}); 
+   assign posedge90_match  = (counter[5:0]==({2\'b00,div_cfg_dec[5:2]}));
+   assign negedge90_match  = (counter[5:0]==({2\'b00,div_cfg_dec[5:2]}+{1\'b0,div_cfg_dec[5:1]})); 
+\t\t\t      
+   //Divided clock
+   //always @ (posedge clk_in or posedge reset)
+   //if(reset)
+   //clk_out_reg <= 1\'b0;   
+   always @ (posedge clk_in)
+     if(posedge_match)
+       clk_out_reg <= 1\'b1;
+     else if(negedge_match)
+       clk_out_reg <= 1\'b0;
+  
+   assign clk_out    = clk_out_reg;
+
+   /**********************************************************************/
+   /*Divide by 2 Clock
+   /**********************************************************************/
+   //always @ (posedge clk_in or posedge reset)     
+   //if(reset)
+   //clk_out90_reg <= 1\'b0;   
+   //always @ (posedge clk_in)     
+   //  if(posedge90_match)
+   //    clk_out90_reg <= 1\'b1;
+   //  else if(negedge90_match)
+   //    clk_out90_reg <= 1\'b0;
+
+   assign clk_out90_div4_in = posedge90_match ? 1\'b1 :
+                              negedge90_match ? 1\'b0 :
+\t\t\t                        clk_out90_div4;
+
+   DFFQX4A12TR clk90_flop     (.CK(clk_in), 
+\t\t\t       .D(clk_out90_div4_in), 
+\t\t\t       .Q(clk_out90_div4) 
+\t\t\t       );
+   
+   //always @ (negedge clk_in)
+   //  if(negedge_match)
+   //    clk90_div2_reg <= 1\'b1;
+   //  else if(posedge_match)
+   //    clk90_div2_reg <= 1\'b0;
+
+   assign clk_out90_div2_in = negedge_match ? 1\'b1 :
+                              posedge_match ? 1\'b0 :
+\t\t\t                      clk_out90_div2;
+   
+  
+   
+   DFFNQX3A12TR clk90_div2_flop (.CKN(clk_in), 
+\t \t\t\t .D(clk_out90_div2_in), 
+\t\t\t\t .Q(clk_out90_div2) 
+\t\t\t\t);
+   
+
+   //assign clk_out90  = div2_sel ? clk90_div2_reg : clk_out90_reg;
+   MX2X4A12TR clk90_mux2      (.A(clk_out90_div4), 
+\t\t\t       .B(clk_out90_div2), 
+\t\t\t       .S0(div2_sel),
+\t\t\t       .Y(clk_out90)
+\t\t\t       );
+
+
+   
+   
+endmodule // clock_divider
+
+
+
+     
+module e16_mesh_interface(/*AUTOARG*/
+   // Outputs
+   wait_out, access_out, write_out, datamode_out, ctrlmode_out,
+   data_out, dstaddr_out, srcaddr_out, access_reg, write_reg,
+   datamode_reg, ctrlmode_reg, data_reg, dstaddr_reg, srcaddr_reg,
+   // Inputs
+   clk, clk_en, reset, wait_in, access_in, write_in, datamode_in,
+   ctrlmode_in, data_in, dstaddr_in, srcaddr_in, wait_int, access,
+   write, datamode, ctrlmode, data, dstaddr, srcaddr
+   );
+
+   parameter DW = `CFG_DW;
+   parameter AW = `CFG_AW;
+   
+   //###########
+   //# INPUTS
+   //###########
+   input            clk;
+   input            clk_en;  //2nd level manual clock gater   
+   input \t    reset;  
+
+   //# from the mesh
+   input \t    wait_in;
+   input \t    access_in;
+   input \t    write_in;
+   input [1:0]      datamode_in;
+   input [3:0]      ctrlmode_in;   \t\t    
+   input [DW-1:0]   data_in;
+   input [AW-1:0]   dstaddr_in;
+   input [AW-1:0]   srcaddr_in;   
+
+   //# from the internal control
+   input \t    wait_int;
+   input \t    access;
+   input \t    write;
+   input [1:0]      datamode;
+   input [3:0]      ctrlmode;   \t\t    
+   input [DW-1:0]   data;
+   input [AW-1:0]   dstaddr;
+   input [AW-1:0]   srcaddr;   
+
+   //###########
+   //# OUTPUTS
+   //###########
+
+   //# to the mesh
+   output \t    wait_out;
+   output \t    access_out;
+   output \t    write_out;
+   output [1:0]     datamode_out;
+   output [3:0]     ctrlmode_out;   \t\t    
+   output [DW-1:0]  data_out;
+   output [AW-1:0]  dstaddr_out;
+   output [AW-1:0]  srcaddr_out;  
+
+   //# to the internal control
+   output \t    access_reg;
+   output \t    write_reg;
+   output [1:0]     datamode_reg;
+   output [3:0]     ctrlmode_reg;   \t\t    
+   output [DW-1:0]  data_reg;
+   output [AW-1:0]  dstaddr_reg;
+   output [AW-1:0]  srcaddr_reg;  
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   //#########
+   //# REGS
+   //#########
+   reg          wait_out;
+   reg \t\taccess_out;
+   reg \t\twrite_out;
+   reg [1:0] \tdatamode_out;
+   reg [3:0] \tctrlmode_out;   \t\t    
+   reg [DW-1:0] data_out;
+   reg [AW-1:0] dstaddr_out;
+   reg [AW-1:0] srcaddr_out;  
+
+   reg \t\taccess_reg;
+   reg \t\twrite_reg;
+   reg [1:0] \tdatamode_reg;
+   reg [3:0] \tctrlmode_reg;   \t\t    
+   reg [DW-1:0] data_reg;
+   reg [AW-1:0] dstaddr_reg;
+   reg [AW-1:0] srcaddr_reg;  
+
+   //#########
+   //# WIRES
+   //#########
+
+   //##########################
+   //# mesh input busses
+   //##########################
+
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       access_reg <= 1\'b0;
+     else if(clk_en)
+       if(~wait_int)
+\t access_reg <= access_in;
+      
+   always @ (posedge clk)
+     if(clk_en)
+       if(~wait_int & access_in)
+\t begin
+\t    write_reg           <= write_in;
+\t    datamode_reg[1:0]   <= datamode_in[1:0];
+\t    ctrlmode_reg[3:0]   <= ctrlmode_in[3:0];
+\t    data_reg[DW-1:0]    <= data_in[DW-1:0];
+\t    dstaddr_reg[AW-1:0] <= dstaddr_in[AW-1:0];
+\t    srcaddr_reg[AW-1:0] <= srcaddr_in[AW-1:0];
+\t end
+
+   //##########################
+   //# mesh output busses  
+   //##########################
+
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       access_out <= 1\'b0;
+     else if(clk_en)
+       if(!wait_in)
+\t access_out <= access;
+
+   always @ (posedge clk)
+     if (clk_en)
+       if(!wait_in & access)
+\t begin
+\t    srcaddr_out[AW-1:0] <= srcaddr[AW-1:0];
+\t    data_out[DW-1:0]    <= data[DW-1:0];
+\t    write_out           <= write;
+\t    datamode_out[1:0]   <= datamode[1:0]; 
+\t    dstaddr_out[AW-1:0] <= dstaddr[AW-1:0];
+\t    ctrlmode_out[3:0]   <= ctrlmode[3:0];
+\t end
+ 
+   //#####################
+   //# Wait out control
+   //#####################
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       wait_out <= 1\'b0;
+     else if(clk_en)
+       wait_out <= wait_int;
+   
+endmodule // mesh_interface
+
+
+
+module e16_mux7(/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   in0, in1, in2, in3, in4, in5, in6, sel0, sel1, sel2, sel3, sel4,
+   sel5, sel6
+   );
+
+   parameter DW=99;
+   
+
+   //data inputs
+   input [DW-1:0]  in0;
+   input [DW-1:0]  in1;
+   input [DW-1:0]  in2;
+   input [DW-1:0]  in3;
+   input [DW-1:0]  in4;
+   input [DW-1:0]  in5;
+   input [DW-1:0]  in6;
+   
+   //select inputs
+   input \t   sel0;
+   input \t   sel1;
+   input \t   sel2;
+   input \t   sel3;
+   input \t   sel4;
+   input \t   sel5;
+   input \t   sel6;
+
+
+   output [DW-1:0] out;
+   
+  
+   assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
+\t\t\t {(DW){sel1}} & in1[DW-1:0] |
+\t\t\t {(DW){sel2}} & in2[DW-1:0] |
+\t\t\t {(DW){sel3}} & in3[DW-1:0] |
+\t\t\t {(DW){sel4}} & in4[DW-1:0] |
+\t\t\t {(DW){sel5}} & in5[DW-1:0] |
+\t\t\t {(DW){sel6}} & in6[DW-1:0]);
+   
+
+   // synthesis translate_off
+   always @*
+     if((sel0+sel1+sel2+sel3+sel4+sel5+sel6>1) & $time>0)
+       $display(""ERROR>>Arbitration failure in cell %m"");
+   // synthesis translate_on
+   
+   
+endmodule // mux7
+
+module e16_pulse2pulse(/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   inclk, outclk, in, reset
+   );
+
+   
+   //clocks
+   input  inclk; 
+   input  outclk;  
+
+   
+   input  in;   
+   output out;
+
+   //reset
+   input  reset;  //do we need this???
+
+
+
+   wire   intoggle;
+   wire   insync;
+   
+   
+   //pulse to toggle
+   pulse2toggle    pulse2toggle(
+\t\t\t\t// Outputs
+\t\t\t\t.out\t\t(intoggle),
+\t\t\t\t// Inputs
+\t\t\t\t.clk\t\t(inclk),
+\t\t\t\t.in\t\t(in),
+\t\t\t\t.reset\t\t(reset));
+   
+   //metastability synchronizer
+   synchronizer #(1) synchronizer(
+\t\t\t\t  // Outputs
+\t\t\t\t  .out\t\t\t(insync),
+\t\t\t\t  // Inputs
+\t\t\t\t  .in\t\t\t(intoggle),
+\t\t\t\t  .clk\t\t\t(outclk),
+\t\t\t\t  .reset\t\t(reset));
+   
+   
+   //toogle to pulse
+   toggle2pulse toggle2pulse(
+\t\t\t     // Outputs
+\t\t\t     .out\t\t(out),
+\t\t\t     // Inputs
+\t\t\t     .clk\t\t(outclk),
+\t\t\t     .in\t\t(insync),
+\t\t\t     .reset\t\t(reset));
+   
+
+   
+endmodule // pulse2pulse
+
+
+
+module e16_pulse2toggle(/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in, reset
+   );
+
+   
+   //clocks
+   input  clk; 
+   
+   input  in;   
+   output out;
+
+   //reset
+   input  reset;  //do we need this???
+
+
+   reg \t  out;
+   wire   toggle;
+   
+   //if input goes high, toggle output
+   //note1: input can only be high for one clock cycle
+   //note2: be careful with clock gating
+
+   assign toggle = in ? ~out :
+\t\t         out;
+   
+
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       out <= 1\'b0;
+     else
+       out <= toggle;
+   
+endmodule // pulse2toggle
+
+
+
+
+module e16_synchronizer #(parameter DW=32) (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   in, clk, reset
+   );
+
+
+   //Input Side   
+   input  [DW-1:0] in;   
+   input           clk;      
+   input           reset;//asynchronous signal
+   
+   
+   //Output Side
+   output [DW-1:0] out;
+
+   reg [DW-1:0] sync_reg0;
+   reg [DW-1:0] sync_reg1;
+   reg [DW-1:0] out;
+     
+   //Synchronization between clock domain
+   //We use two flip-flops for metastability improvement
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       begin
+\t  sync_reg0[DW-1:0] <= {(DW){1\'b0}};
+\t  sync_reg1[DW-1:0] <= {(DW){1\'b0}};
+\t  out[DW-1:0]       <= {(DW){1\'b0}};
+       end
+     else
+       begin
+\t  sync_reg0[DW-1:0] <= in[DW-1:0];
+\t  sync_reg1[DW-1:0] <= sync_reg0[DW-1:0];
+\t  out[DW-1:0]       <= sync_reg1[DW-1:0];
+       end
+   
+
+
+   
+   
+     
+
+endmodule // clock_synchronizer
+
+//goes high for one clock cycle on every input transition
+module e16_toggle2pulse(/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in, reset
+   );
+
+   
+   //clocks
+   input  clk; 
+   
+   input  in;   
+   output out;
+
+   //reset
+   input  reset;
+   reg \t  out_reg;
+         
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       out_reg <= 1\'b0;
+     else
+       out_reg <= in;
+      
+   assign out = in ^ out_reg;
+
+endmodule 
+
+
+
+
+
+module elink_e16 (/*AUTOARG*/
+   // Outputs
+   rxi_rd_wait, rxi_wr_wait, txo_data, txo_lclk, txo_frame,
+   c0_mesh_access_out, c0_mesh_write_out, c0_mesh_dstaddr_out,
+   c0_mesh_srcaddr_out, c0_mesh_data_out, c0_mesh_datamode_out,
+   c0_mesh_ctrlmode_out, c0_emesh_wait_out, c0_mesh_wait_out,
+   // Inputs
+   reset, c0_clk_in, c1_clk_in, c2_clk_in, c3_clk_in, rxi_data,
+   rxi_lclk, rxi_frame, txo_rd_wait, txo_wr_wait, c0_mesh_access_in,
+   c0_mesh_write_in, c0_mesh_dstaddr_in, c0_mesh_srcaddr_in,
+   c0_mesh_data_in, c0_mesh_datamode_in, c0_mesh_ctrlmode_in,
+   c0_mesh_wait_in
+   );
+   
+   parameter DW   = `CFG_DW  ;//data width  
+   parameter AW   = `CFG_AW  ;//address width
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+
+ 
+   
+   //Reset/core clock
+   input             reset; 
+   input \t     c0_clk_in;
+   input \t     c1_clk_in;
+   input \t     c2_clk_in;
+   input \t     c3_clk_in;
+   
+
+   // # IO Signals
+   input   [LW-1:0]  rxi_data;      // Byte word
+   input             rxi_lclk;      // receive clock (adjusted)
+   input             rxi_frame;     // indicates new transmission
+   input             txo_rd_wait;   // wait indicator on read transactions   
+   input             txo_wr_wait;   // wait indicator on write transactions  
+   output \t     rxi_rd_wait;   // wait indicator on read transaction  
+   output \t     rxi_wr_wait;   // wait indicator on write transaction  
+   output  [LW-1:0]  txo_data;      // Byte word
+   output            txo_lclk;      // transmit clock
+   output            txo_frame;     // indicates new transmission 
+
+   
+
+   // # MESH 
+   // # core0 (external corners and multicast)
+   input \t    c0_mesh_access_in;  // access control from the mesh
+   input \t    c0_mesh_write_in;   // write control from the mesh
+   input [AW-1:0]   c0_mesh_dstaddr_in; // destination address from the mesh
+   input [AW-1:0]   c0_mesh_srcaddr_in; // source address from the mesh
+   input [DW-1:0]   c0_mesh_data_in;    // data from the mesh
+   input [1:0] \t    c0_mesh_datamode_in;// data mode from the mesh 
+   input [3:0] \t    c0_mesh_ctrlmode_in;// ctrl mode from the mesh
+   input \t    c0_mesh_wait_in;   // wait
+
+
+
+   // ##############
+   // # Outputs
+   // ##############
+
+   
+   // # MESH (write transactions internal and external corners)
+   // # core0 
+   output \t     c0_mesh_access_out;  // access control to the mesh
+   output \t     c0_mesh_write_out;   // write control to the mesh
+   output [AW-1:0]   c0_mesh_dstaddr_out; // destination address to the mesh
+   output [AW-1:0]   c0_mesh_srcaddr_out; // source address to the mesh
+   output [DW-1:0]   c0_mesh_data_out;    // data to the mesh
+   output [1:0]      c0_mesh_datamode_out;// data mode to the mesh 
+   output [3:0]      c0_mesh_ctrlmode_out;// ctrl mode to the mesh
+  
+
+   // # Waits
+   output \t     c0_emesh_wait_out; // wait to the emesh   
+   output \t     c0_mesh_wait_out;  // wait to the mesh 
+
+   wire [3:0] \t     ext_yid_k=4\'h8;   
+   wire [3:0] \t     ext_xid_k=4\'h4;   
+   wire \t     vertical_k=1\'b1; // specifies if block is vertical or horizontal
+   wire [3:0] \t     who_am_i=4\'b0100;   // (north,east,south,west)
+   wire \t     cfg_extcomp_dis=1\'b0;// Disable external coordinates comparison
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\tc0_emesh_frame_out;\t// From link_port of link_port.v
+   wire [2*LW-1:0]\tc0_emesh_tran_out;\t// From link_port of link_port.v
+   wire\t\t\tc0_rdmesh_frame_out;\t// From link_port of link_port.v
+   wire [2*LW-1:0]\tc0_rdmesh_tran_out;\t// From link_port of link_port.v
+   wire\t\t\tc0_rdmesh_wait_out;\t// From link_port of link_port.v
+   wire\t\t\tc1_emesh_wait_out;\t// From link_port of link_port.v
+   wire\t\t\tc1_rdmesh_frame_out;\t// From link_port of link_port.v
+   wire [2*LW-1:0]\tc1_rdmesh_tran_out;\t// From link_port of link_port.v
+   wire\t\t\tc1_rdmesh_wait_out;\t// From link_port of link_port.v
+   wire\t\t\tc2_emesh_wait_out;\t// From link_port of link_port.v
+   wire\t\t\tc2_rdmesh_frame_out;\t// From link_port of link_port.v
+   wire [2*LW-1:0]\tc2_rdmesh_tran_out;\t// From link_port of link_port.v
+   wire\t\t\tc2_rdmesh_wait_out;\t// From link_port of link_port.v
+   wire\t\t\tc3_emesh_frame_out;\t// From link_port of link_port.v
+   wire [2*LW-1:0]\tc3_emesh_tran_out;\t// From link_port of link_port.v
+   wire\t\t\tc3_emesh_wait_out;\t// From link_port of link_port.v
+   wire\t\t\tc3_mesh_access_out;\t// From link_port of link_port.v
+   wire [3:0]\t\tc3_mesh_ctrlmode_out;\t// From link_port of link_port.v
+   wire [DW-1:0]\tc3_mesh_data_out;\t// From link_port of link_port.v
+   wire [1:0]\t\tc3_mesh_datamode_out;\t// From link_port of link_port.v
+   wire [AW-1:0]\tc3_mesh_dstaddr_out;\t// From link_port of link_port.v
+   wire [AW-1:0]\tc3_mesh_srcaddr_out;\t// From link_port of link_port.v
+   wire\t\t\tc3_mesh_wait_out;\t// From link_port of link_port.v
+   wire\t\t\tc3_mesh_write_out;\t// From link_port of link_port.v
+   wire\t\t\tc3_rdmesh_frame_out;\t// From link_port of link_port.v
+   wire [2*LW-1:0]\tc3_rdmesh_tran_out;\t// From link_port of link_port.v
+   wire\t\t\tc3_rdmesh_wait_out;\t// From link_port of link_port.v
+   // End of automatics
+
+   /* link_port AUTO_TEMPLATE  (.\\(.*\\)_rdmesh_tran_in (16\'b0),
+                                .\\(.*\\)_rdmesh_frame_in (1\'b0),
+                                .\\(.*\\)_emesh_tran_in (16\'b0),
+                                .\\(.*\\)_emesh_frame_in (1\'b0),
+    );
+    */
+   
+
+   wire\t\tc0_emesh_wait_in=1\'b0;
+   wire\t\tc0_rdmesh_wait_in=1\'b0;
+   wire\t\tc1_rdmesh_wait_in=1\'b0;
+   wire\t\tc2_rdmesh_wait_in=1\'b0;
+   wire\t\tc3_emesh_wait_in=1\'b0;
+   wire\t\tc3_mesh_wait_in=1\'b0;
+   wire\t\tc3_rdmesh_wait_in=1\'b0;
+   wire [5:0] \ttxo_cfg_reg=6\'b0;
+   
+
+   link_port link_port (.c3_mesh_access_in(1\'b0),
+\t\t\t.c3_mesh_write_in(1\'b0),
+\t\t\t.c3_mesh_dstaddr_in(32\'b0),
+\t\t\t.c3_mesh_srcaddr_in(32\'b0),
+\t\t\t.c3_mesh_data_in(32\'b0),
+\t\t\t.c3_mesh_datamode_in(2\'b0),
+\t\t\t.c3_mesh_ctrlmode_in(4\'b0),
+\t\t\t/*AUTOINST*/
+\t\t\t// Outputs
+\t\t\t.rxi_rd_wait\t(rxi_rd_wait),
+\t\t\t.rxi_wr_wait\t(rxi_wr_wait),
+\t\t\t.txo_data\t(txo_data[LW-1:0]),
+\t\t\t.txo_lclk\t(txo_lclk),
+\t\t\t.txo_frame\t(txo_frame),
+\t\t\t.c0_emesh_frame_out(c0_emesh_frame_out),
+\t\t\t.c0_emesh_tran_out(c0_emesh_tran_out[2*LW-1:0]),
+\t\t\t.c3_emesh_frame_out(c3_emesh_frame_out),
+\t\t\t.c3_emesh_tran_out(c3_emesh_tran_out[2*LW-1:0]),
+\t\t\t.c0_rdmesh_frame_out(c0_rdmesh_frame_out),
+\t\t\t.c0_rdmesh_tran_out(c0_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t.c1_rdmesh_frame_out(c1_rdmesh_frame_out),
+\t\t\t.c1_rdmesh_tran_out(c1_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t.c2_rdmesh_frame_out(c2_rdmesh_frame_out),
+\t\t\t.c2_rdmesh_tran_out(c2_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t.c3_rdmesh_frame_out(c3_rdmesh_frame_out),
+\t\t\t.c3_rdmesh_tran_out(c3_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t.c0_mesh_access_out(c0_mesh_access_out),
+\t\t\t.c0_mesh_write_out(c0_mesh_write_out),
+\t\t\t.c0_mesh_dstaddr_out(c0_mesh_dstaddr_out[AW-1:0]),
+\t\t\t.c0_mesh_srcaddr_out(c0_mesh_srcaddr_out[AW-1:0]),
+\t\t\t.c0_mesh_data_out(c0_mesh_data_out[DW-1:0]),
+\t\t\t.c0_mesh_datamode_out(c0_mesh_datamode_out[1:0]),
+\t\t\t.c0_mesh_ctrlmode_out(c0_mesh_ctrlmode_out[3:0]),
+\t\t\t.c3_mesh_access_out(c3_mesh_access_out),
+\t\t\t.c3_mesh_write_out(c3_mesh_write_out),
+\t\t\t.c3_mesh_dstaddr_out(c3_mesh_dstaddr_out[AW-1:0]),
+\t\t\t.c3_mesh_srcaddr_out(c3_mesh_srcaddr_out[AW-1:0]),
+\t\t\t.c3_mesh_data_out(c3_mesh_data_out[DW-1:0]),
+\t\t\t.c3_mesh_datamode_out(c3_mesh_datamode_out[1:0]),
+\t\t\t.c3_mesh_ctrlmode_out(c3_mesh_ctrlmode_out[3:0]),
+\t\t\t.c0_emesh_wait_out(c0_emesh_wait_out),
+\t\t\t.c1_emesh_wait_out(c1_emesh_wait_out),
+\t\t\t.c2_emesh_wait_out(c2_emesh_wait_out),
+\t\t\t.c3_emesh_wait_out(c3_emesh_wait_out),
+\t\t\t.c0_rdmesh_wait_out(c0_rdmesh_wait_out),
+\t\t\t.c1_rdmesh_wait_out(c1_rdmesh_wait_out),
+\t\t\t.c2_rdmesh_wait_out(c2_rdmesh_wait_out),
+\t\t\t.c3_rdmesh_wait_out(c3_rdmesh_wait_out),
+\t\t\t.c0_mesh_wait_out(c0_mesh_wait_out),
+\t\t\t.c3_mesh_wait_out(c3_mesh_wait_out),
+\t\t\t// Inputs
+\t\t\t.reset\t\t(reset),
+\t\t\t.ext_yid_k\t(ext_yid_k[3:0]),
+\t\t\t.ext_xid_k\t(ext_xid_k[3:0]),
+\t\t\t.txo_cfg_reg\t(txo_cfg_reg[5:0]),
+\t\t\t.vertical_k\t(vertical_k),
+\t\t\t.who_am_i\t(who_am_i[3:0]),
+\t\t\t.cfg_extcomp_dis(cfg_extcomp_dis),
+\t\t\t.rxi_data\t(rxi_data[LW-1:0]),
+\t\t\t.rxi_lclk\t(rxi_lclk),
+\t\t\t.rxi_frame\t(rxi_frame),
+\t\t\t.txo_rd_wait\t(txo_rd_wait),
+\t\t\t.txo_wr_wait\t(txo_wr_wait),
+\t\t\t.c0_clk_in\t(c0_clk_in),
+\t\t\t.c1_clk_in\t(c1_clk_in),
+\t\t\t.c2_clk_in\t(c2_clk_in),
+\t\t\t.c3_clk_in\t(c3_clk_in),
+\t\t\t.c0_emesh_tran_in(16\'b0),\t\t // Templated
+\t\t\t.c0_emesh_frame_in(1\'b0),\t\t // Templated
+\t\t\t.c1_emesh_tran_in(16\'b0),\t\t // Templated
+\t\t\t.c1_emesh_frame_in(1\'b0),\t\t // Templated
+\t\t\t.c2_emesh_tran_in(16\'b0),\t\t // Templated
+\t\t\t.c2_emesh_frame_in(1\'b0),\t\t // Templated
+\t\t\t.c3_emesh_tran_in(16\'b0),\t\t // Templated
+\t\t\t.c3_emesh_frame_in(1\'b0),\t\t // Templated
+\t\t\t.c0_rdmesh_tran_in(16\'b0),\t\t // Templated
+\t\t\t.c0_rdmesh_frame_in(1\'b0),\t\t // Templated
+\t\t\t.c1_rdmesh_tran_in(16\'b0),\t\t // Templated
+\t\t\t.c1_rdmesh_frame_in(1\'b0),\t\t // Templated
+\t\t\t.c2_rdmesh_tran_in(16\'b0),\t\t // Templated
+\t\t\t.c2_rdmesh_frame_in(1\'b0),\t\t // Templated
+\t\t\t.c3_rdmesh_tran_in(16\'b0),\t\t // Templated
+\t\t\t.c3_rdmesh_frame_in(1\'b0),\t\t // Templated
+\t\t\t.c0_mesh_access_in(c0_mesh_access_in),
+\t\t\t.c0_mesh_write_in(c0_mesh_write_in),
+\t\t\t.c0_mesh_dstaddr_in(c0_mesh_dstaddr_in[AW-1:0]),
+\t\t\t.c0_mesh_srcaddr_in(c0_mesh_srcaddr_in[AW-1:0]),
+\t\t\t.c0_mesh_data_in(c0_mesh_data_in[DW-1:0]),
+\t\t\t.c0_mesh_datamode_in(c0_mesh_datamode_in[1:0]),
+\t\t\t.c0_mesh_ctrlmode_in(c0_mesh_ctrlmode_in[3:0]),
+\t\t\t.c0_emesh_wait_in(c0_emesh_wait_in),
+\t\t\t.c3_emesh_wait_in(c3_emesh_wait_in),
+\t\t\t.c0_mesh_wait_in(c0_mesh_wait_in),
+\t\t\t.c3_mesh_wait_in(c3_mesh_wait_in),
+\t\t\t.c0_rdmesh_wait_in(c0_rdmesh_wait_in),
+\t\t\t.c1_rdmesh_wait_in(c1_rdmesh_wait_in),
+\t\t\t.c2_rdmesh_wait_in(c2_rdmesh_wait_in),
+\t\t\t.c3_rdmesh_wait_in(c3_rdmesh_wait_in));
+      
+endmodule // elink_e16
+
+module link_port(/*AUTOARG*/
+   // Outputs
+   rxi_rd_wait, rxi_wr_wait, txo_data, txo_lclk, txo_frame,
+   c0_emesh_frame_out, c0_emesh_tran_out, c3_emesh_frame_out,
+   c3_emesh_tran_out, c0_rdmesh_frame_out, c0_rdmesh_tran_out,
+   c1_rdmesh_frame_out, c1_rdmesh_tran_out, c2_rdmesh_frame_out,
+   c2_rdmesh_tran_out, c3_rdmesh_frame_out, c3_rdmesh_tran_out,
+   c0_mesh_access_out, c0_mesh_write_out, c0_mesh_dstaddr_out,
+   c0_mesh_srcaddr_out, c0_mesh_data_out, c0_mesh_datamode_out,
+   c0_mesh_ctrlmode_out, c3_mesh_access_out, c3_mesh_write_out,
+   c3_mesh_dstaddr_out, c3_mesh_srcaddr_out, c3_mesh_data_out,
+   c3_mesh_datamode_out, c3_mesh_ctrlmode_out, c0_emesh_wait_out,
+   c1_emesh_wait_out, c2_emesh_wait_out, c3_emesh_wait_out,
+   c0_rdmesh_wait_out, c1_rdmesh_wait_out, c2_rdmesh_wait_out,
+   c3_rdmesh_wait_out, c0_mesh_wait_out, c3_mesh_wait_out,
+   // Inputs
+   reset, ext_yid_k, ext_xid_k, txo_cfg_reg, vertical_k, who_am_i,
+   cfg_extcomp_dis, rxi_data, rxi_lclk, rxi_frame, txo_rd_wait,
+   txo_wr_wait, c0_clk_in, c1_clk_in, c2_clk_in, c3_clk_in,
+   c0_emesh_tran_in, c0_emesh_frame_in, c1_emesh_tran_in,
+   c1_emesh_frame_in, c2_emesh_tran_in, c2_emesh_frame_in,
+   c3_emesh_tran_in, c3_emesh_frame_in, c0_rdmesh_tran_in,
+   c0_rdmesh_frame_in, c1_rdmesh_tran_in, c1_rdmesh_frame_in,
+   c2_rdmesh_tran_in, c2_rdmesh_frame_in, c3_rdmesh_tran_in,
+   c3_rdmesh_frame_in, c0_mesh_access_in, c0_mesh_write_in,
+   c0_mesh_dstaddr_in, c0_mesh_srcaddr_in, c0_mesh_data_in,
+   c0_mesh_datamode_in, c0_mesh_ctrlmode_in, c3_mesh_access_in,
+   c3_mesh_write_in, c3_mesh_dstaddr_in, c3_mesh_srcaddr_in,
+   c3_mesh_data_in, c3_mesh_datamode_in, c3_mesh_ctrlmode_in,
+   c0_emesh_wait_in, c3_emesh_wait_in, c0_mesh_wait_in,
+   c3_mesh_wait_in, c0_rdmesh_wait_in, c1_rdmesh_wait_in,
+   c2_rdmesh_wait_in, c3_rdmesh_wait_in
+   );
+
+   parameter DW   = `CFG_DW  ;//data width  
+   parameter AW   = `CFG_AW  ;//address width
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+
+   // #########
+   // # Inputs
+   // #########
+   
+   input             reset;     //reset input
+   input [3:0] \t     ext_yid_k; //external y-id 
+   input [3:0] \t     ext_xid_k; //external x-id
+
+   input [5:0] \t     txo_cfg_reg;// Link configuration register
+   input             vertical_k; // specifies if block is vertical or horizontal
+   input [3:0] \t     who_am_i;   // specifies what link is that (north,east,south,west)
+   input \t     cfg_extcomp_dis;// Disable external coordinates comparison
+                                     // Every input transaction is received by the chip
+   // # Vertical_k usage:
+   // # West/East link port is ""vertical"", i.e. sends transactions to the cores
+   // # horizontally, according to the row_k[2:0] index
+   // # North/South link port is ""horizontal"", i.e. sends transactions to the cores
+   // # vertically, according to the col_k[2:0] index
+   // # In order to distinguish between West/East and North/South,
+   // # vertical_k index is used.
+
+   // # Receiver
+   input   [LW-1:0]  rxi_data;        // Byte word
+   input             rxi_lclk;        // receive clock (adjusted to the frame/data)
+   input             rxi_frame;       // indicates new transmission
+
+   // # Transmitter
+   input             txo_rd_wait;     // wait indicator on read transactions   
+   input             txo_wr_wait;     // wait indicator on write transactions  
+
+   // # Clocks
+   input \t    c0_clk_in;         // clock of the core  
+   input \t    c1_clk_in;         // clock of the core  
+   input \t    c2_clk_in;         // clock of the core  
+   input \t    c3_clk_in;         // clock of the core  
+
+   // # EMESH
+   input [2*LW-1:0] c0_emesh_tran_in;  // serialized transaction
+   input \t    c0_emesh_frame_in; // transaction frame
+   input [2*LW-1:0] c1_emesh_tran_in;  // serialized transaction
+   input \t    c1_emesh_frame_in; // transaction frame
+   input [2*LW-1:0] c2_emesh_tran_in;  // serialized transaction
+   input \t    c2_emesh_frame_in; // transaction frame
+   input [2*LW-1:0] c3_emesh_tran_in;  // serialized transaction
+   input \t    c3_emesh_frame_in; // transaction frame
+   // # RDMESH
+   input [2*LW-1:0] c0_rdmesh_tran_in;  // serialized transaction
+   input \t    c0_rdmesh_frame_in; // transaction frame
+   input [2*LW-1:0] c1_rdmesh_tran_in;  // serialized transaction
+   input \t    c1_rdmesh_frame_in; // transaction frame
+   input [2*LW-1:0] c2_rdmesh_tran_in;  // serialized transaction
+   input \t    c2_rdmesh_frame_in; // transaction frame
+   input [2*LW-1:0] c3_rdmesh_tran_in;  // serialized transaction
+   input \t    c3_rdmesh_frame_in; // transaction frame
+   // # MESH 
+   // # core0 (external corners and multicast)
+   input \t    c0_mesh_access_in;  // access control from the mesh
+   input \t    c0_mesh_write_in;   // write control from the mesh
+   input [AW-1:0]   c0_mesh_dstaddr_in; // destination address from the mesh
+   input [AW-1:0]   c0_mesh_srcaddr_in; // source address from the mesh
+   input [DW-1:0]   c0_mesh_data_in;    // data from the mesh
+   input [1:0] \t    c0_mesh_datamode_in;// data mode from the mesh 
+   input [3:0] \t    c0_mesh_ctrlmode_in;// ctrl mode from the mesh
+   // # core3 (external corners only)
+   input \t    c3_mesh_access_in;  // access control from the mesh
+   input \t    c3_mesh_write_in;   // write control from the mesh
+   input [AW-1:0]   c3_mesh_dstaddr_in; // destination address from the mesh
+   input [AW-1:0]   c3_mesh_srcaddr_in; // source address from the mesh
+   input [DW-1:0]   c3_mesh_data_in;    // data from the mesh
+   input [1:0] \t    c3_mesh_datamode_in;// data mode from the mesh 
+   input [3:0] \t    c3_mesh_ctrlmode_in;// ctrl mode from the mesh
+
+   //# Waits
+   input \t    c0_emesh_wait_in;  // wait
+   input \t    c3_emesh_wait_in;  // wait
+   input \t    c0_mesh_wait_in;   // wait
+   input \t    c3_mesh_wait_in;   // wait
+   input \t    c0_rdmesh_wait_in; // wait
+   input \t    c1_rdmesh_wait_in; // wait
+   input \t    c2_rdmesh_wait_in; // wait
+   input \t    c3_rdmesh_wait_in; // wait
+
+   // ##############
+   // # Outputs
+   // ##############
+
+   // # Receiver
+   output \t     rxi_rd_wait;      // wait indicator on read transaction  
+   output \t     rxi_wr_wait;      // wait indicator on write transaction  
+
+   // # Transmitter
+   output  [LW-1:0]  txo_data;      // Byte word
+   output            txo_lclk;      // transmit clock (adjusted to the frame/data)
+   output            txo_frame;     // indicates new transmission 
+
+   //# EMESH (write transactions with the off chip destination)
+   output            c0_emesh_frame_out; // transaction frame
+   output [2*LW-1:0] c0_emesh_tran_out;  // serialized transaction
+   output            c3_emesh_frame_out; // transaction frame
+   output [2*LW-1:0] c3_emesh_tran_out;  // serialized transaction
+   // # RDMESH (any read transaction)
+   output            c0_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c0_rdmesh_tran_out;  // serialized transaction
+   output            c1_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c1_rdmesh_tran_out;  // serialized transaction
+   output            c2_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c2_rdmesh_tran_out;  // serialized transaction
+   output            c3_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c3_rdmesh_tran_out;  // serialized transaction
+   // # MESH (write transactions internal and external corners)
+   // # core0 
+   output \t     c0_mesh_access_out;  // access control to the mesh
+   output \t     c0_mesh_write_out;   // write control to the mesh
+   output [AW-1:0]   c0_mesh_dstaddr_out; // destination address to the mesh
+   output [AW-1:0]   c0_mesh_srcaddr_out; // source address to the mesh
+   output [DW-1:0]   c0_mesh_data_out;    // data to the mesh
+   output [1:0]      c0_mesh_datamode_out;// data mode to the mesh 
+   output [3:0]      c0_mesh_ctrlmode_out;// ctrl mode to the mesh
+   // # core3 
+   output \t     c3_mesh_access_out;  // access control to the mesh
+   output \t     c3_mesh_write_out;   // write control to the mesh
+   output [AW-1:0]   c3_mesh_dstaddr_out; // destination address to the mesh
+   output [AW-1:0]   c3_mesh_srcaddr_out; // source address to the mesh
+   output [DW-1:0]   c3_mesh_data_out;    // data to the mesh
+   output [1:0]      c3_mesh_datamode_out;// data mode to the mesh 
+   output [3:0]      c3_mesh_ctrlmode_out;// ctrl mode to the mesh
+
+   // # Waits
+   output \t     c0_emesh_wait_out; // wait to the emesh   
+   output \t     c1_emesh_wait_out; // wait to the emesh   
+   output \t     c2_emesh_wait_out; // wait to the emesh   
+   output \t     c3_emesh_wait_out; // wait to the emesh   
+
+   output \t     c0_rdmesh_wait_out; // wait to the rdmesh   
+   output \t     c1_rdmesh_wait_out; // wait to the rdmesh   
+   output \t     c2_rdmesh_wait_out; // wait to the rdmesh   
+   output \t     c3_rdmesh_wait_out; // wait to the rdmesh   
+
+   output \t     c0_mesh_wait_out;  // wait to the mesh 
+   output \t     c3_mesh_wait_out;  // wait to the mesh 
+     
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+ 
+   // #########################
+   // # Receiver instantiation
+   // #########################
+  
+   link_receiver  link_receiver(/*AUTOINST*/
+\t\t\t\t// Outputs
+\t\t\t\t.rxi_wr_wait\t(rxi_wr_wait),
+\t\t\t\t.rxi_rd_wait\t(rxi_rd_wait),
+\t\t\t\t.c0_emesh_frame_out(c0_emesh_frame_out),
+\t\t\t\t.c0_emesh_tran_out(c0_emesh_tran_out[2*LW-1:0]),
+\t\t\t\t.c3_emesh_frame_out(c3_emesh_frame_out),
+\t\t\t\t.c3_emesh_tran_out(c3_emesh_tran_out[2*LW-1:0]),
+\t\t\t\t.c0_rdmesh_frame_out(c0_rdmesh_frame_out),
+\t\t\t\t.c0_rdmesh_tran_out(c0_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t\t.c1_rdmesh_frame_out(c1_rdmesh_frame_out),
+\t\t\t\t.c1_rdmesh_tran_out(c1_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t\t.c2_rdmesh_frame_out(c2_rdmesh_frame_out),
+\t\t\t\t.c2_rdmesh_tran_out(c2_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t\t.c3_rdmesh_frame_out(c3_rdmesh_frame_out),
+\t\t\t\t.c3_rdmesh_tran_out(c3_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t\t.c0_mesh_access_out(c0_mesh_access_out),
+\t\t\t\t.c0_mesh_write_out(c0_mesh_write_out),
+\t\t\t\t.c0_mesh_dstaddr_out(c0_mesh_dstaddr_out[AW-1:0]),
+\t\t\t\t.c0_mesh_srcaddr_out(c0_mesh_srcaddr_out[AW-1:0]),
+\t\t\t\t.c0_mesh_data_out(c0_mesh_data_out[DW-1:0]),
+\t\t\t\t.c0_mesh_datamode_out(c0_mesh_datamode_out[1:0]),
+\t\t\t\t.c0_mesh_ctrlmode_out(c0_mesh_ctrlmode_out[3:0]),
+\t\t\t\t.c3_mesh_access_out(c3_mesh_access_out),
+\t\t\t\t.c3_mesh_write_out(c3_mesh_write_out),
+\t\t\t\t.c3_mesh_dstaddr_out(c3_mesh_dstaddr_out[AW-1:0]),
+\t\t\t\t.c3_mesh_srcaddr_out(c3_mesh_srcaddr_out[AW-1:0]),
+\t\t\t\t.c3_mesh_data_out(c3_mesh_data_out[DW-1:0]),
+\t\t\t\t.c3_mesh_datamode_out(c3_mesh_datamode_out[1:0]),
+\t\t\t\t.c3_mesh_ctrlmode_out(c3_mesh_ctrlmode_out[3:0]),
+\t\t\t\t// Inputs
+\t\t\t\t.reset\t\t(reset),
+\t\t\t\t.ext_yid_k\t(ext_yid_k[3:0]),
+\t\t\t\t.ext_xid_k\t(ext_xid_k[3:0]),
+\t\t\t\t.vertical_k\t(vertical_k),
+\t\t\t\t.who_am_i\t(who_am_i[3:0]),
+\t\t\t\t.cfg_extcomp_dis(cfg_extcomp_dis),
+\t\t\t\t.rxi_data\t(rxi_data[LW-1:0]),
+\t\t\t\t.rxi_lclk\t(rxi_lclk),
+\t\t\t\t.rxi_frame\t(rxi_frame),
+\t\t\t\t.c0_clk_in\t(c0_clk_in),
+\t\t\t\t.c1_clk_in\t(c1_clk_in),
+\t\t\t\t.c2_clk_in\t(c2_clk_in),
+\t\t\t\t.c3_clk_in\t(c3_clk_in),
+\t\t\t\t.c0_emesh_wait_in(c0_emesh_wait_in),
+\t\t\t\t.c3_emesh_wait_in(c3_emesh_wait_in),
+\t\t\t\t.c0_mesh_wait_in(c0_mesh_wait_in),
+\t\t\t\t.c3_mesh_wait_in(c3_mesh_wait_in),
+\t\t\t\t.c0_rdmesh_wait_in(c0_rdmesh_wait_in),
+\t\t\t\t.c1_rdmesh_wait_in(c1_rdmesh_wait_in),
+\t\t\t\t.c2_rdmesh_wait_in(c2_rdmesh_wait_in),
+\t\t\t\t.c3_rdmesh_wait_in(c3_rdmesh_wait_in));
+   
+
+   // ############################
+   // # Transmitter instantiation
+   // ############################
+
+   link_transmitter  link_transmitter(.txo_lclk90\t(txo_lclk),
+\t\t\t\t      /*AUTOINST*/
+\t\t\t\t      // Outputs
+\t\t\t\t      .txo_data\t\t(txo_data[LW-1:0]),
+\t\t\t\t      .txo_frame\t(txo_frame),
+\t\t\t\t      .c0_emesh_wait_out(c0_emesh_wait_out),
+\t\t\t\t      .c1_emesh_wait_out(c1_emesh_wait_out),
+\t\t\t\t      .c2_emesh_wait_out(c2_emesh_wait_out),
+\t\t\t\t      .c3_emesh_wait_out(c3_emesh_wait_out),
+\t\t\t\t      .c0_rdmesh_wait_out(c0_rdmesh_wait_out),
+\t\t\t\t      .c1_rdmesh_wait_out(c1_rdmesh_wait_out),
+\t\t\t\t      .c2_rdmesh_wait_out(c2_rdmesh_wait_out),
+\t\t\t\t      .c3_rdmesh_wait_out(c3_rdmesh_wait_out),
+\t\t\t\t      .c0_mesh_wait_out\t(c0_mesh_wait_out),
+\t\t\t\t      .c3_mesh_wait_out\t(c3_mesh_wait_out),
+\t\t\t\t      // Inputs
+\t\t\t\t      .reset\t\t(reset),
+\t\t\t\t      .ext_yid_k\t(ext_yid_k[3:0]),
+\t\t\t\t      .ext_xid_k\t(ext_xid_k[3:0]),
+\t\t\t\t      .who_am_i\t\t(who_am_i[3:0]),
+\t\t\t\t      .txo_cfg_reg\t(txo_cfg_reg[5:0]),
+\t\t\t\t      .txo_wr_wait\t(txo_wr_wait),
+\t\t\t\t      .txo_rd_wait\t(txo_rd_wait),
+\t\t\t\t      .c0_clk_in\t(c0_clk_in),
+\t\t\t\t      .c1_clk_in\t(c1_clk_in),
+\t\t\t\t      .c2_clk_in\t(c2_clk_in),
+\t\t\t\t      .c3_clk_in\t(c3_clk_in),
+\t\t\t\t      .c0_mesh_access_in(c0_mesh_access_in),
+\t\t\t\t      .c0_mesh_write_in\t(c0_mesh_write_in),
+\t\t\t\t      .c0_mesh_dstaddr_in(c0_mesh_dstaddr_in[AW-1:0]),
+\t\t\t\t      .c0_mesh_srcaddr_in(c0_mesh_srcaddr_in[AW-1:0]),
+\t\t\t\t      .c0_mesh_data_in\t(c0_mesh_data_in[DW-1:0]),
+\t\t\t\t      .c0_mesh_datamode_in(c0_mesh_datamode_in[1:0]),
+\t\t\t\t      .c0_mesh_ctrlmode_in(c0_mesh_ctrlmode_in[3:0]),
+\t\t\t\t      .c3_mesh_access_in(c3_mesh_access_in),
+\t\t\t\t      .c3_mesh_write_in\t(c3_mesh_write_in),
+\t\t\t\t      .c3_mesh_dstaddr_in(c3_mesh_dstaddr_in[AW-1:0]),
+\t\t\t\t      .c3_mesh_srcaddr_in(c3_mesh_srcaddr_in[AW-1:0]),
+\t\t\t\t      .c3_mesh_data_in\t(c3_mesh_data_in[DW-1:0]),
+\t\t\t\t      .c3_mesh_datamode_in(c3_mesh_datamode_in[1:0]),
+\t\t\t\t      .c3_mesh_ctrlmode_in(c3_mesh_ctrlmode_in[3:0]),
+\t\t\t\t      .c0_emesh_frame_in(c0_emesh_frame_in),
+\t\t\t\t      .c0_emesh_tran_in\t(c0_emesh_tran_in[2*LW-1:0]),
+\t\t\t\t      .c1_emesh_frame_in(c1_emesh_frame_in),
+\t\t\t\t      .c1_emesh_tran_in\t(c1_emesh_tran_in[2*LW-1:0]),
+\t\t\t\t      .c2_emesh_frame_in(c2_emesh_frame_in),
+\t\t\t\t      .c2_emesh_tran_in\t(c2_emesh_tran_in[2*LW-1:0]),
+\t\t\t\t      .c3_emesh_frame_in(c3_emesh_frame_in),
+\t\t\t\t      .c3_emesh_tran_in\t(c3_emesh_tran_in[2*LW-1:0]));
+      
+endmodule // link_port
+
+
+module link_receiver(/*AUTOARG*/
+   // Outputs
+   rxi_wr_wait, rxi_rd_wait, c0_emesh_frame_out, c0_emesh_tran_out,
+   c3_emesh_frame_out, c3_emesh_tran_out, c0_rdmesh_frame_out,
+   c0_rdmesh_tran_out, c1_rdmesh_frame_out, c1_rdmesh_tran_out,
+   c2_rdmesh_frame_out, c2_rdmesh_tran_out, c3_rdmesh_frame_out,
+   c3_rdmesh_tran_out, c0_mesh_access_out, c0_mesh_write_out,
+   c0_mesh_dstaddr_out, c0_mesh_srcaddr_out, c0_mesh_data_out,
+   c0_mesh_datamode_out, c0_mesh_ctrlmode_out, c3_mesh_access_out,
+   c3_mesh_write_out, c3_mesh_dstaddr_out, c3_mesh_srcaddr_out,
+   c3_mesh_data_out, c3_mesh_datamode_out, c3_mesh_ctrlmode_out,
+   // Inputs
+   reset, ext_yid_k, ext_xid_k, vertical_k, who_am_i, cfg_extcomp_dis,
+   rxi_data, rxi_lclk, rxi_frame, c0_clk_in, c1_clk_in, c2_clk_in,
+   c3_clk_in, c0_emesh_wait_in, c3_emesh_wait_in, c0_mesh_wait_in,
+   c3_mesh_wait_in, c0_rdmesh_wait_in, c1_rdmesh_wait_in,
+   c2_rdmesh_wait_in, c3_rdmesh_wait_in
+   );
+
+   parameter LW   = `CFG_LW;//lvds tranceiver pairs per side
+   parameter DW   = `CFG_DW;//data width  
+   parameter AW   = `CFG_AW;//address width
+\t\t     
+   // #########
+   // # Inputs
+   // #########
+
+   input             reset;     // reset input
+   input [3:0] \t     ext_yid_k; // external y-id 
+   input [3:0] \t     ext_xid_k; // external x-id
+   input             vertical_k;// specifies if block is vertical or horizontal
+   input [3:0] \t     who_am_i;  // specifies what link is that (north,east,south,west)
+   input \t     cfg_extcomp_dis;// Disable external coordinates comparison
+                                     // Every input transaction is received by the chip
+  
+   input [LW-1:0]    rxi_data;  // Byte word
+   input             rxi_lclk;  // receive clock (adjusted to the frame/data)
+   input             rxi_frame; // indicates new transmission
+
+   // # Sync clocks
+   input             c0_clk_in; // clock of the core
+   input             c1_clk_in; // clock of the core
+   input             c2_clk_in; // clock of the core
+   input             c3_clk_in; // clock of the core
+
+   // # Wait indicators
+   input             c0_emesh_wait_in;  // wait
+   input             c3_emesh_wait_in;  // wait
+   input \t     c0_mesh_wait_in;   // wait
+   input \t    'b' c3_mesh_wait_in;   // wait
+   input             c0_rdmesh_wait_in; // wait
+   input             c1_rdmesh_wait_in; // wait
+   input             c2_rdmesh_wait_in; // wait
+   input             c3_rdmesh_wait_in; // wait
+
+   // ##########
+   // # Outputs
+   // ##########
+
+   output \t     rxi_wr_wait;  //wait indicator for write transactions
+   output \t     rxi_rd_wait;  //wait indicator for read transactions 
+
+   //# EMESH (write transactions with the off chip destination)
+   output            c0_emesh_frame_out; // transaction frame
+   output [2*LW-1:0] c0_emesh_tran_out;  // serialized transaction
+   output            c3_emesh_frame_out; // transaction frame
+   output [2*LW-1:0] c3_emesh_tran_out;  // serialized transaction
+   // # RDMESH (any read transaction)
+   output            c0_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c0_rdmesh_tran_out;  // serialized transaction
+   output            c1_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c1_rdmesh_tran_out;  // serialized transaction
+   output            c2_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c2_rdmesh_tran_out;  // serialized transaction
+   output            c3_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c3_rdmesh_tran_out;  // serialized transaction
+   // # MESH (write transactions internal and external corners)
+   // # core0 
+   output \t     c0_mesh_access_out;  // access control to the mesh
+   output \t     c0_mesh_write_out;   // write control to the mesh
+   output [AW-1:0]   c0_mesh_dstaddr_out; // destination address to the mesh
+   output [AW-1:0]   c0_mesh_srcaddr_out; // source address to the mesh
+   output [DW-1:0]   c0_mesh_data_out;    // data to the mesh
+   output [1:0]      c0_mesh_datamode_out;// data mode to the mesh 
+   output [3:0]      c0_mesh_ctrlmode_out;// ctrl mode to the mesh
+   // # core3 
+   output \t     c3_mesh_access_out;  // access control to the mesh
+   output \t     c3_mesh_write_out;   // write control to the mesh
+   output [AW-1:0]   c3_mesh_dstaddr_out; // destination address to the mesh
+   output [AW-1:0]   c3_mesh_srcaddr_out; // source address to the mesh
+   output [DW-1:0]   c3_mesh_data_out;    // data to the mesh
+   output [1:0]      c3_mesh_datamode_out;// data mode to the mesh 
+   output [3:0]      c3_mesh_ctrlmode_out;// ctrl mode to the mesh
+  
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   //#################################
+   //# Write Transactions Receiver
+   //#################################
+
+   link_rxi_wr link_rxi_wr(/*AUTOINST*/
+\t\t\t   // Outputs
+\t\t\t   .rxi_wr_wait\t\t(rxi_wr_wait),
+\t\t\t   .c0_emesh_frame_out\t(c0_emesh_frame_out),
+\t\t\t   .c0_emesh_tran_out\t(c0_emesh_tran_out[2*LW-1:0]),
+\t\t\t   .c3_emesh_frame_out\t(c3_emesh_frame_out),
+\t\t\t   .c3_emesh_tran_out\t(c3_emesh_tran_out[2*LW-1:0]),
+\t\t\t   .c0_mesh_access_out\t(c0_mesh_access_out),
+\t\t\t   .c0_mesh_write_out\t(c0_mesh_write_out),
+\t\t\t   .c0_mesh_dstaddr_out\t(c0_mesh_dstaddr_out[AW-1:0]),
+\t\t\t   .c0_mesh_srcaddr_out\t(c0_mesh_srcaddr_out[AW-1:0]),
+\t\t\t   .c0_mesh_data_out\t(c0_mesh_data_out[DW-1:0]),
+\t\t\t   .c0_mesh_datamode_out(c0_mesh_datamode_out[1:0]),
+\t\t\t   .c0_mesh_ctrlmode_out(c0_mesh_ctrlmode_out[3:0]),
+\t\t\t   .c3_mesh_access_out\t(c3_mesh_access_out),
+\t\t\t   .c3_mesh_write_out\t(c3_mesh_write_out),
+\t\t\t   .c3_mesh_dstaddr_out\t(c3_mesh_dstaddr_out[AW-1:0]),
+\t\t\t   .c3_mesh_srcaddr_out\t(c3_mesh_srcaddr_out[AW-1:0]),
+\t\t\t   .c3_mesh_data_out\t(c3_mesh_data_out[DW-1:0]),
+\t\t\t   .c3_mesh_datamode_out(c3_mesh_datamode_out[1:0]),
+\t\t\t   .c3_mesh_ctrlmode_out(c3_mesh_ctrlmode_out[3:0]),
+\t\t\t   // Inputs
+\t\t\t   .reset\t\t(reset),
+\t\t\t   .ext_yid_k\t\t(ext_yid_k[3:0]),
+\t\t\t   .ext_xid_k\t\t(ext_xid_k[3:0]),
+\t\t\t   .vertical_k\t\t(vertical_k),
+\t\t\t   .who_am_i\t\t(who_am_i[3:0]),
+\t\t\t   .cfg_extcomp_dis\t(cfg_extcomp_dis),
+\t\t\t   .rxi_data\t\t(rxi_data[LW-1:0]),
+\t\t\t   .rxi_lclk\t\t(rxi_lclk),
+\t\t\t   .rxi_frame\t\t(rxi_frame),
+\t\t\t   .c0_clk_in\t\t(c0_clk_in),
+\t\t\t   .c3_clk_in\t\t(c3_clk_in),
+\t\t\t   .c0_emesh_wait_in\t(c0_emesh_wait_in),
+\t\t\t   .c3_emesh_wait_in\t(c3_emesh_wait_in),
+\t\t\t   .c0_mesh_wait_in\t(c0_mesh_wait_in),
+\t\t\t   .c3_mesh_wait_in\t(c3_mesh_wait_in));
+
+   //#################################
+   //# Read Transactions Receiver
+   //#################################
+
+   link_rxi_rd link_rxi_rd(/*AUTOINST*/
+\t\t\t   // Outputs
+\t\t\t   .rxi_rd_wait\t\t(rxi_rd_wait),
+\t\t\t   .c0_rdmesh_frame_out\t(c0_rdmesh_frame_out),
+\t\t\t   .c0_rdmesh_tran_out\t(c0_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t   .c1_rdmesh_frame_out\t(c1_rdmesh_frame_out),
+\t\t\t   .c1_rdmesh_tran_out\t(c1_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t   .c2_rdmesh_frame_out\t(c2_rdmesh_frame_out),
+\t\t\t   .c2_rdmesh_tran_out\t(c2_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t   .c3_rdmesh_frame_out\t(c3_rdmesh_frame_out),
+\t\t\t   .c3_rdmesh_tran_out\t(c3_rdmesh_tran_out[2*LW-1:0]),
+\t\t\t   // Inputs
+\t\t\t   .reset\t\t(reset),
+\t\t\t   .ext_yid_k\t\t(ext_yid_k[3:0]),
+\t\t\t   .ext_xid_k\t\t(ext_xid_k[3:0]),
+\t\t\t   .vertical_k\t\t(vertical_k),
+\t\t\t   .who_am_i\t\t(who_am_i[3:0]),
+\t\t\t   .cfg_extcomp_dis\t(cfg_extcomp_dis),
+\t\t\t   .rxi_data\t\t(rxi_data[LW-1:0]),
+\t\t\t   .rxi_lclk\t\t(rxi_lclk),
+\t\t\t   .rxi_frame\t\t(rxi_frame),
+\t\t\t   .c0_clk_in\t\t(c0_clk_in),
+\t\t\t   .c1_clk_in\t\t(c1_clk_in),
+\t\t\t   .c2_clk_in\t\t(c2_clk_in),
+\t\t\t   .c3_clk_in\t\t(c3_clk_in),
+\t\t\t   .c0_rdmesh_wait_in\t(c0_rdmesh_wait_in),
+\t\t\t   .c1_rdmesh_wait_in\t(c1_rdmesh_wait_in),
+\t\t\t   .c2_rdmesh_wait_in\t(c2_rdmesh_wait_in),
+\t\t\t   .c3_rdmesh_wait_in\t(c3_rdmesh_wait_in));
+
+
+ 
+endmodule // link_receiver
+
+     //############################################################################
+//# The input data stream is of the following structure:
+//#
+//#        ---     ---     ---     ---     ---     ---
+//# lclk _|   |___|   |___|   |___|   |___|   |___|   |_
+//#
+//#              -------------------------------
+//# frame ______/
+//#              --- --- --- --- ---
+//# data  XXXXXXX 0 X 1 X 2 X 3 X 4 X .....
+//#              --- --- --- --- ---
+//#
+//# byte0 (the byte received on the rising edge of the clock the 
+//# same cycle the frame\'s rising edge is detected) holds the 
+//# information of the transmitted transaction.
+//#
+//#      byte0          | transaction type
+//#   ----------------- | ----------------
+//#  8\'b??_??_?0_<cid>  | New transaction with incremental bursting address
+//#  8\'b??_??_?1_<cid>  | New transaction with the same bursting address
+//#
+//#  cid[1:0] - channel id (for now for debugging usage only) 
+//#
+//#  New transaction structure:
+//#  -------------------------
+//#   byte1  -> ctrlmode[3:0],dstaddr[31:28]
+//#   byte2  -> dstaddr[27:20]
+//#   byte3  -> dstaddr[19:12]
+//#   byte4  -> dstaddr[11:4]
+//#   byte5  -> dstaddr[3:0],datamode[1:0],write,access
+//#   byte6  -> data[31:24] (or srcaddr[31:24] if read transaction)
+//#   byte7  -> data[23:16] (or srcaddr[23:16] if read transaction)
+//#   byte8  -> data[15:8]  (or srcaddr[15:8]  if read transaction)
+//#  *byte9  -> data[7:0]   (or srcaddr[7:0]   if read transaction)
+//#   byte10 -> data[63:56]  
+//#   byte11 -> data[55:48]  
+//#   byte12 -> data[47:40]  
+//#   byte13 -> data[39:32]  
+//# **byte14 -> data[31:24]  
+//#    ...
+//#    ...
+//#    ...
+//#
+//#  * byte9 is the last byte of 32 bit write or read transaction 
+//#   
+//# ** if 64 bit write transaction, data of byte14 is the first data byte of
+//#    bursting transaction
+//# 
+//# -- The data is transmitted MSB first but in 32bits resolution. If we want
+//#    to transmit 64 bits it will be [31:0] (msb first) and then [63:32] (msb first)
+//#
+//# !!!
+//# !!! According to the above scheme, any new transaction (burst or not)
+//# !!! will take at least four cycles to be transmitted.
+//# !!! There are some internal mechanisms in the transmitter-receiver logic
+//# !!! which are implemented considering this assumption true.
+//# !!! Any change to this assumption (transaction takes at least four cycles)
+//# !!! should be carefully reviewed with its implications on the internal
+//# !!! implementation
+//# !!!
+//# 
+//#####################################################################
+module link_rxi_assembler (/*AUTOARG*/
+   // Outputs
+   rxi_assembled_tran, rxi_c0_access, rxi_c1_access, rxi_c2_access,
+   rxi_c3_access,
+   // Inputs
+   reset, rxi_lclk, vertical_k, ext_yid_k, ext_xid_k, fifo_data_reg,
+   fifo_data_val, start_tran, cfg_extcomp_dis
+   );
+
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+   parameter DW   = `CFG_DW  ;//data width
+   parameter AW   = `CFG_AW  ;//address width
+
+   // #########
+   // # INPUTS
+   // #########
+   input            reset;       //reset input
+   input \t    rxi_lclk;    //receive clock (adjusted to the frame/data)
+
+   input            vertical_k;  //specifies if block is vertical or horizontal
+   input [3:0] \t    ext_yid_k;   //external y-id 
+   input [3:0] \t    ext_xid_k;   //external x-id
+
+   input [2*LW-1:0] fifo_data_reg;// output of the input receiver fifo
+   input \t    fifo_data_val;// fifo_data_reg is valid
+   input \t    start_tran;   // Start transaction bit
+
+   input \t    cfg_extcomp_dis;// Disable external coordinates comparison
+                                    // Every input transaction is received by the chip
+   // ##########
+   // # OUTPUTS
+   // ##########
+   output [14*LW-1:0] rxi_assembled_tran; // data to be transferred to secondary fifos
+   output             rxi_c0_access; //transfering to c0_fifo
+   output \t      rxi_c1_access; //transfering to c1_fifo
+   output \t      rxi_c2_access; //transfering to c2_fifo
+   output \t      rxi_c3_access; //transfering to c3_fifo  
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   // #########
+   // # REGS
+   // #########
+   reg [LW-1:0] tran_byte0;
+   reg [2:0] \trxi_assemble_cnt;
+   reg [3:0] \tctrlmode;
+   reg [AW-1:0] dstaddr_int;
+   reg [1:0] \tdatamode;
+   reg \t\twrite;
+   reg \t\taccess;
+   reg [DW-1:0] data;
+   reg [AW-1:0] srcaddr;
+   reg \t\trxi_cx_access;
+
+   // #########
+   // # WIRES
+   // #########
+   wire          byte0_inc8; // Address of the burst transaction should be incremented
+   wire \t dstaddr_2712_en;
+   wire \t dstaddr_1100_en;
+   wire \t datamode_en;    
+   wire \t write_en;       
+   wire \t access_en;      
+   wire \t data_3116_en;   
+   wire \t data_1500_en;   
+   wire \t srcaddr_3116_en;
+   wire \t srcaddr_1500_en;
+   wire [2:0] \t rxi_assemble_cnt_next; // Next value of the assembly counter
+   wire [2:0] \t rxi_assemble_cnt_inc;  // Incremented value of the assembly counter
+   wire \t rxi_assemble_cnt_max;  // Maximum value of the counter 
+   wire \t burst_tran;            // detected burst transaction
+   wire [AW-1:0] dstaddr_inc;           // Incremented value of burst transaction dstaddr
+   wire [AW-1:0] dstaddr_in;            // Input to the next destination address FF
+   wire \t single_write;          // single write transaction
+   wire \t single_write_complete; // single write transaction is complete
+   wire \t read_jump;             // read transaction ""jumps"" over data part
+   wire \t tran_assembled;        // transaction is assembled
+   wire [5:0] \t comp_addr;
+   wire [5:0] \t chip_addr;
+   wire [5:0] \t comp_low;
+   wire \t carry_low;
+   wire \t zero_low;
+   wire [5:0] \t comp_high;
+   wire \t carry_high;
+   wire \t c0_match;
+   wire \t c1_match;
+   wire \t c2_match;
+   wire \t c3_match;
+   wire \t multicast_match;
+   wire [AW-1:0] dstaddr;
+
+   //##############################
+   //# Assembled data and controls
+   //##############################
+
+   assign rxi_assembled_tran[14*LW-1:0]={
+                                         srcaddr[7:0],{(LW){1\'b0}},
+\t\t\t\t               srcaddr[23:8],
+\t\t\t                 data[7:0],srcaddr[31:24],
+\t\t\t\t                 data[23:8],
+\t                    dstaddr[3:0],datamode[1:0],write,access,data[31:24],
+\t\t\t\t                dstaddr[19:4],
+\t\t\t                 ctrlmode[3:0],dstaddr[31:20]
+                                        };
+ 
+   //####################
+   //# Byte0 detection
+   //####################
+
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & start_tran)
+       begin
+\t  tran_byte0[LW-1:0]  <= fifo_data_reg[2*LW-1:LW]; 
+\t  ctrlmode[3:0]       <= fifo_data_reg[7:4];
+       end
+
+   //# byte0 decode
+   //# bit[2] is the only one in use for now
+   assign byte0_inc8   = ~tran_byte0[2];
+
+   //##########################
+   //# Transaction assembly
+   //##########################
+
+   //# destination address
+   //# There is a special mode set in the Link Bypass Configuration Register
+   //# which forces the chip to receive all of the transactions entering the chip
+   //# In this case we just replace the external coordinates of the destination 
+   //# address with the chip coordinates.
+//   assign dstaddr[31:29] = cfg_extcomp_dis ? ext_yid_k[2:0] : dstaddr_int[31:29];
+//   assign dstaddr[28:26] = cfg_extcomp_dis ? ext_xid_k[2:0] : dstaddr_int[28:26];
+//   assign dstaddr[25:0]  = dstaddr_int[25:0];
+   assign dstaddr[31:28] = cfg_extcomp_dis ? ext_yid_k[3:0] : dstaddr_int[31:28];
+   assign dstaddr[25:22] = cfg_extcomp_dis ? ext_xid_k[3:0] : dstaddr_int[25:22];
+   assign dstaddr[27:26] = dstaddr_int[27:26];
+   assign dstaddr[21:0]  = dstaddr_int[21:0];
+
+//   assign comp_addr[5:0]  = vertical_k ? {dstaddr[31:29],dstaddr[25:23]} : 
+//                                         {dstaddr[28:26],dstaddr[22:20]} ;   
+
+//   assign chip_addr[2:0]   = vertical_k ?  ext_yid_k[2:0] : ext_xid_k[2:0];
+ 
+   //# destination address is updated on the beginning of burst transaction
+   //# while datamode, write, access and control mode are unchanged
+   assign dstaddr_inc[AW-1:0] = dstaddr[AW-1:0] + {{(AW-4){1\'b0}},byte0_inc8,3\'b000};
+
+   assign dstaddr_in[31:28] = burst_tran ? dstaddr_inc[31:28] : fifo_data_reg[3:0];
+   assign dstaddr_in[27:12] = burst_tran ? dstaddr_inc[27:12] : fifo_data_reg[2*LW-1:0];
+   assign dstaddr_in[11:0]  = burst_tran ? dstaddr_inc[11:0]  : fifo_data_reg[2*LW-1:4];
+
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & (start_tran | burst_tran))
+       dstaddr_int[31:28] <= dstaddr_in[31:28];
+
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & (dstaddr_2712_en | burst_tran))
+       dstaddr_int[27:12] <= dstaddr_in[27:12];
+
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & (dstaddr_1100_en | burst_tran))
+       dstaddr_int[11:0] <= dstaddr_in[11:0];
+       
+   //# data mode
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & datamode_en)
+       datamode[1:0] <= fifo_data_reg[3:2];
+
+   //# write
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & write_en)
+       write <= fifo_data_reg[1];
+
+   //# access
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & access_en)
+       access <= fifo_data_reg[0];
+
+   //# data
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & (data_3116_en | burst_tran))
+       data[31:16] <= fifo_data_reg[2*LW-1:0];
+
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & data_1500_en)
+       data[15:0] <= fifo_data_reg[2*LW-1:0];
+
+   //# srcaddr
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & srcaddr_3116_en)
+        srcaddr[31:16] <= fifo_data_reg[2*LW-1:0];
+
+   always @ (posedge rxi_lclk)
+     if(fifo_data_val & srcaddr_1500_en)
+       srcaddr[15:0] <= fifo_data_reg[2*LW-1:0];
+       
+
+   //###################################################################
+   //#            Order of the transaction fields in the fifo
+   //#            -------------------------------------------
+   //# Entry ""n+6""                 srcaddr[15:0]
+   //# Entry ""n+5""\t\t  srcaddr[31:16],
+   //# Entry ""n+4""                  data[15:0],
+   //# Entry ""n+3""                 data[31:16],
+   //# Entry ""n+2""  dstaddr[11:0],datamode[1:0],write,access,
+   //# Entry ""n+1""\t          dstaddr[27:12],
+   //# Entry ""n""         byte0[7:0],ctrlmode[3:0],dstaddr[31:28],
+   //#            --------------------------------------------
+   //####################################################################
+
+   assign dstaddr_2712_en  = (rxi_assemble_cnt[2:0] == 3\'b001);
+   assign dstaddr_1100_en  = (rxi_assemble_cnt[2:0] == 3\'b010);
+   assign datamode_en      = (rxi_assemble_cnt[2:0] == 3\'b010);
+   assign write_en         = (rxi_assemble_cnt[2:0] == 3\'b010);
+   assign access_en        = (rxi_assemble_cnt[2:0] == 3\'b010);
+   assign data_3116_en     = (rxi_assemble_cnt[2:0] == 3\'b011);
+   assign data_1500_en     = (rxi_assemble_cnt[2:0] == 3\'b100);
+   assign srcaddr_3116_en  = (rxi_assemble_cnt[2:0] == 3\'b101);
+   assign srcaddr_1500_en  = (rxi_assemble_cnt[2:0] == 3\'b110);
+
+   //# Assemble counter
+   assign rxi_assemble_cnt_inc[2:0]  = rxi_assemble_cnt[2:0] + 3\'b001;
+
+   assign rxi_assemble_cnt_next[2:0] = burst_tran           ? 3\'b100 :
+\t\t\t\t       tran_assembled       ? 3\'b000 :
+\t\t\t\t       read_jump            ? 3\'b101 :
+\t\t\t\t                              rxi_assemble_cnt_inc[2:0];
+   always @ (posedge rxi_lclk or posedge reset)
+     if (reset)
+       rxi_assemble_cnt[2:0] <= 3\'b000;
+     else if(fifo_data_val)
+       rxi_assemble_cnt[2:0] <= rxi_assemble_cnt_next[2:0];
+
+   //# single write transaction completion
+//   assign single_write = access & write & ~(&(datamode[1:0]));
+   assign single_write = 1\'b0; // no special treatment for single writes
+   assign single_write_complete = single_write & (rxi_assemble_cnt[2:0] == 3\'b100);
+
+   //# read transaction ""jumps"" over data part of the counter
+   //assign read_jump = ~fifo_data_reg[1] & (rxi_assemble_cnt[2:0] == 3\'b010);
+   //# read transaction ""jump"" feature is disabled because of the test-and-set inst
+   assign read_jump = 1\'b0;
+
+   //# transaction completion
+   assign rxi_assemble_cnt_max = (rxi_assemble_cnt[2:0] == 3\'b110);
+   assign tran_assembled = fifo_data_val & (single_write_complete | rxi_assemble_cnt_max);
+
+   //# burst transaction detection
+   assign burst_tran = (rxi_assemble_cnt[2:0] == 3\'b000) & ~start_tran;
+
+   //###########################################
+   //# Secondary-FIFOs transaction distribution
+   //###########################################
+
+   always @ (posedge rxi_lclk or posedge reset)
+     if(reset)
+       rxi_cx_access <= 1\'b0;
+     else
+       rxi_cx_access <= tran_assembled;
+
+   assign rxi_c0_access   = (c0_match |  multicast_match) & rxi_cx_access;
+   assign rxi_c1_access   = (c1_match & ~multicast_match) & rxi_cx_access;   
+   assign rxi_c2_access   = (c2_match & ~multicast_match) & rxi_cx_access;   
+   assign rxi_c3_access   = (c3_match & ~multicast_match) & rxi_cx_access;
+
+   //# address preparation for comparison based on the links position (horiz or vert)
+//   assign comp_addr[5:0]  = vertical_k ? {dstaddr[31:29],dstaddr[25:23]} : 
+//                                         {dstaddr[28:26],dstaddr[22:20]} ;   
+   assign comp_addr[5:0]  = vertical_k ? dstaddr[31:26] : dstaddr[25:20];   
+
+//   assign chip_addr[2:0]   = vertical_k ?  ext_yid_k[2:0] : ext_xid_k[2:0];
+   assign chip_addr[5:2] = vertical_k ?  ext_yid_k[3:0] : ext_xid_k[3:0];
+   assign chip_addr[1:0] = 2\'b11;
+//   assign chip_addr_n[3:0] =~chip_addr[3:0];
+   //# high comparison
+//   assign {carry_high,comp_high[5:0]} = comp_addr[5:0] + {chip_addr_n[2:0],3\'b101};
+   assign {carry_high,comp_high[5:0]} = {1\'b0,comp_addr[5:0]} - {1\'b0,chip_addr[5:0]};
+   //# channels matching
+   assign c0_match =  carry_high; // chip addr is bigger
+   assign c1_match =  (comp_addr[5:0] == {chip_addr[5:2],3\'b01});//EQ   
+   assign c2_match =  (comp_addr[5:0] == {chip_addr[5:2],3\'b10});//EQ  
+   assign c3_match = ~(c0_match | c1_match | c2_match);
+   //# multicast tran detection
+   assign multicast_match = write & 
+\t\t\t    (ctrlmode[1:0]==2\'b11) & ~(datamode[1:0] == 2\'b11);
+
+
+
+
+endmodule // link_rxi_assembler
+module link_rxi_buffer (/*AUTOARG*/
+   // Outputs
+   rxi_wait, rxi_assembled_tran, rxi_c0_access, rxi_c1_access,
+   rxi_c2_access, rxi_c3_access,
+   // Inputs
+   reset, vertical_k, ext_yid_k, ext_xid_k, rxi_data, rxi_lclk,
+   rxi_frame, rxi_rd, cfg_extcomp_dis, c0_fifo_full, c1_fifo_full,
+   c2_fifo_full, c3_fifo_full
+   );
+
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+   parameter NC   = 32;// Number of cycles for save TXO-RXI ""transaction interface""
+   parameter FAD  = 5; // Number of bits to access all the entries (2^FAD + 1) > NC
+   localparam MD = 1<<FAD;
+
+   // #########
+   // # INPUTS
+   // #########
+
+   input          reset;       //reset input
+   input \t  vertical_k;  //specifies if block is vertical or horizontal
+   input [3:0] \t  ext_yid_k;   //external y-id 
+   input [3:0] \t  ext_xid_k;   //external x-id
+   
+   input [LW-1:0] rxi_data;      //Byte word
+   input \t  rxi_lclk;      //receive clock (adjusted to the frame/data)
+   input \t  rxi_frame;     //indicates new transmission
+   
+   input \t  rxi_rd;         // this is read transactions rxi_buffer
+   input \t  cfg_extcomp_dis;// Disable external coordinates comparison
+                                  // Every input transaction is received by the chip
+
+   input \t  c0_fifo_full;
+   input \t  c1_fifo_full;
+   input \t  c2_fifo_full;
+   input \t  c3_fifo_full;
+
+   // ##########
+   // # OUTPUTS
+   // ##########
+
+   output \t      rxi_wait;          //wait indicator   
+
+   output [14*LW-1:0] rxi_assembled_tran; // data to be transferred to secondary fifos
+   output             rxi_c0_access; //transfering to c0_fifo
+   output \t      rxi_c1_access; //transfering to c1_fifo
+   output \t      rxi_c2_access; //transfering to c2_fifo
+   output \t      rxi_c3_access; //transfering to c3_fifo  
+ 
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   // #########
+   // # Regs
+   // #########
+
+   reg \t\t   rd_tran;
+   reg [2*LW:0]    fifo_mem[MD-1:0];
+   reg \t\t   frame_reg;
+   reg \t\t   frame_reg_del;
+   reg [LW-1:0]    data_even_reg;
+   reg [LW-1:0]    data_odd_reg;
+   reg [FAD:0] \t   wr_binary_pointer;
+   reg [FAD:0] \t   rd_binary_pointer;
+   reg \t\t   fifo_read;
+   reg \t\t   rxi_wait;
+   reg \t\t   start_tran;
+   reg \t\t   fifo_data_val;
+   reg [2*LW-1:0]  fifo_data_reg;
+
+   // #########
+   // # Wires
+   // #########
+
+   wire \t   my_tran;      // this transaction is dedicated to current rxi_buffer
+   wire \t   new_tran;     // first cycle of the new transaction
+   wire [2*LW:0]   fifo_data_in; // even and odd bytes combined into short words for fifo 
+   wire [2*LW:0]   fifo_data_out;// output of the fifo
+   wire [FAD:0]\t   wr_binary_next; // next value of the write pointer
+   wire [FAD:0]    rd_binary_next; // next value of the read pointer
+   wire \t   fifo_write; // write into the fifo
+   wire [FAD-1:0]  wr_addr; // write address of the fifo
+   wire [FAD-1:0]  rd_addr; // read address of the fifo
+   wire \t   fifo_empty; // indication of the empty fifo
+   wire \t   stop_fifo_read; //one of the secondary fifos is full (stop reading)
+   
+   // ####################################################
+   // #        Sample input transaction
+   // # The positive edge FFs work all the time
+   // # while the negative edge FFs can be disabled
+   // # by the state of the detected frame (to save power)  
+   // ####################################################     
+
+   //# frame
+   always @ (posedge rxi_lclk or posedge reset)
+     if(reset)
+       begin
+\t  frame_reg     <= 1\'b0;
+\t  frame_reg_del <= 1\'b0;
+       end
+     else
+       begin
+\t  frame_reg     <= rxi_frame;
+\t  frame_reg_del <= frame_reg;
+       end
+
+   //# even bytes
+   always @ (posedge rxi_lclk)
+     data_even_reg[LW-1:0] <= rxi_data[LW-1:0];
+
+   //# odd bytes
+   always @ (negedge rxi_lclk)
+     data_odd_reg[LW-1:0] <= rxi_data[LW-1:0];
+
+   //##################################################
+   //# We should differentiate between read and write
+   //# transactions since link_rxi_buffer can accept
+   //# the transactions of one type only.
+   //# The indication of the type of the transaction
+   //# is sent in the byte0 of the transaction.
+   //##################################################
+
+   assign my_tran = ~(rd_tran ^ rxi_rd);
+   always @ (posedge rxi_lclk)
+     if(~frame_reg)            //will stop sampling when byte0 is received
+       rd_tran <= rxi_data[7];
+
+   //# frame rising edge detection
+   assign new_tran = my_tran & frame_reg & ~frame_reg_del;
+
+   //# bytes packaging into short words + new transaction indication
+   assign fifo_data_in[2*LW:0] = {new_tran,data_even_reg[LW-1:0],data_odd_reg[LW-1:0]};
+
+   //###############################################################################
+   //#          Wait indication to the transmitter
+   //# When one of the secondary fifos becomes full we send wait indication 
+   //# to the transmitter.
+   //# There is some uncertainty regarding how long it will take for the wait 
+   //# control to stop the transmitter (we have synchronization on the way, 
+   //# which may cause +/-1 cycle of uncertainty).
+   //# Our main fifo on the input port of the receiver is robust enough
+   //# (has enough entries) to receive all of the transactions sent during the
+   //# time of ""wait traveling"" without loosing any information.
+   //# But the uncertainty mentioned above forces us to start from empty fifo
+   //# every time after wait indication is raised in order to ensure that 
+   //# the number of available entries won\'t be reduced.            
+   //###############################################################################
+
+   assign stop_fifo_read = c0_fifo_full | c1_fifo_full | c2_fifo_full | c3_fifo_full;
+
+   always @ (posedge rxi_lclk or posedge reset)
+     if(reset)
+       rxi_wait <= 1\'b0;
+     else if(stop_fifo_read)
+       rxi_wait <= 1\'b1;
+     else if(fifo_empty)
+       rxi_wait <= 1\'b0;
+
+   //##################################
+   //#   Input FIFO of the receiver
+   //##################################
+
+   always @ (posedge rxi_lclk)
+     if (fifo_write)
+       fifo_mem[wr_addr[FAD-1:0]] <= fifo_data_in[2*LW:0];
+
+   //# Read from fifo
+   assign fifo_data_out[2*LW:0] = fifo_mem[rd_addr[FAD-1:0]];
+
+   //# Since the size of the FIFO is parametrized I prefer to sample the output
+   //# data to prevent timing issues for the big number of entries (big mux on read)
+   //# This shouldn\'t add any performance loss just latency increase
+
+   always @ (posedge rxi_lclk or posedge reset)
+     if(reset)
+       start_tran  <= 1\'b0;
+     else if(fifo_read)
+       start_tran  <= fifo_data_out[2*LW];
+ 
+   always @ (posedge rxi_lclk)
+     if(fifo_read)
+       fifo_data_reg[2*LW-1:0] <= fifo_data_out[2*LW-1:0];
+
+   always @ (posedge rxi_lclk or posedge reset)
+     if(reset)
+       fifo_data_val <= 1\'b0;
+     else
+       fifo_data_val <= fifo_read;
+
+   //#####################################################################
+   //#                  FIFO Write State Machine
+   //# !!!
+   //# This FIFO will write the data in every time the FRAME IS HIGH and
+   //# INDEPENDENT of the read out of the FIFO ""frequency""
+   //# !!!
+   //# When the data cannot be read out of the FIFO, the indication will
+   //# be sent to the transmitter to stop sending new transactions and the
+   //# frame signal will be deasserted.
+   //# The number of entries in the FIFO sould be big enough to receive
+   //# all of the transactions sent by the transmitter in that case.
+   //######################################################################
+
+   assign fifo_write = my_tran & frame_reg;
+   
+   always @(posedge rxi_lclk or posedge reset)
+     if(reset)
+       wr_binary_pointer[FAD:0]     <= {(FAD+1){1\'b0}};
+     else if(fifo_write)
+       wr_binary_pointer[FAD:0]     <= wr_binary_next[FAD:0];\t  
+
+   assign wr_addr[FAD-1:0]       = wr_binary_pointer[FAD-1:0];
+   assign wr_binary_next[FAD:0]  = wr_binary_pointer[FAD:0] + {{(FAD){1\'b0}},fifo_write};
+
+   //#############################
+   //# FIFO Read State Machine
+   //#############################
+   
+   always @(posedge rxi_lclk or posedge reset)
+     if(reset)
+       fifo_read <= 1\'b0;
+     else
+       fifo_read <= ~(fifo_empty | stop_fifo_read);
+
+   always @(posedge rxi_lclk or posedge reset)
+     if(reset)
+       rd_binary_pointer[FAD:0]  <= {(FAD+1){1\'b0}};
+     else if(fifo_read)
+       rd_binary_pointer[FAD:0]  <= rd_binary_next[FAD:0];\t  
+
+   assign rd_addr[FAD-1:0]       = rd_binary_pointer[FAD-1:0];
+   assign rd_binary_next[FAD:0]  = rd_binary_pointer[FAD:0] + {{(FAD){1\'b0}},fifo_read};
+
+   assign fifo_empty = (rd_binary_next[FAD:0] == wr_binary_next[FAD:0]);
+
+   //########################################
+   //# Transaction assembly and distribution
+   //########################################
+
+   link_rxi_assembler link_rxi_assembler(/*AUTOINST*/
+\t\t\t\t\t // Outputs
+\t\t\t\t\t .rxi_assembled_tran\t(rxi_assembled_tran[14*LW-1:0]),
+\t\t\t\t\t .rxi_c0_access\t\t(rxi_c0_access),
+\t\t\t\t\t .rxi_c1_access\t\t(rxi_c1_access),
+\t\t\t\t\t .rxi_c2_access\t\t(rxi_c2_access),
+\t\t\t\t\t .rxi_c3_access\t\t(rxi_c3_access),
+\t\t\t\t\t // Inputs
+\t\t\t\t\t .reset\t\t\t(reset),
+\t\t\t\t\t .rxi_lclk\t\t(rxi_lclk),
+\t\t\t\t\t .vertical_k\t\t(vertical_k),
+\t\t\t\t\t .ext_yid_k\t\t(ext_yid_k[3:0]),
+\t\t\t\t\t .ext_xid_k\t\t(ext_xid_k[3:0]),
+\t\t\t\t\t .fifo_data_reg\t\t(fifo_data_reg[2*LW-1:0]),
+\t\t\t\t\t .fifo_data_val\t\t(fifo_data_val),
+\t\t\t\t\t .start_tran\t\t(start_tran),
+\t\t\t\t\t .cfg_extcomp_dis\t(cfg_extcomp_dis));
+
+   
+endmodule // link_rxi_buffer
+module link_rxi_channel (/*AUTOARG*/
+   // Outputs
+   fifo_full_rlc, rdmesh_tran_out, rdmesh_frame_out,
+   // Inputs
+   reset, cclk, cclk_en, rxi_lclk, cfg_extcomp_dis,
+   rxi_assembled_tran_rlc, fifo_access_rlc, rdmesh_wait_in
+   );
+
+   parameter LW    = `CFG_LW;//lvds tranceiver pairs per side
+   
+   //#########
+   //# INPUTS
+   //#########
+
+   input             reset;   //reset input
+   input \t     cclk;    //core clock
+   input \t     cclk_en; // clock enable 
+   input \t     rxi_lclk;//receiver link clock
+   input \t     cfg_extcomp_dis;// Disable external coordinates comparison
+                                     // Every input transaction is received by the chip
+
+   input [14*LW-1:0] rxi_assembled_tran_rlc; // assembled data from the main fifo
+   input \t     fifo_access_rlc;        // fifo is accessed
+
+   input \t     rdmesh_wait_in; //wait indication from rdmesh
+  
+   //##########
+   //# OUTPUTS
+   //##########
+   output \t  fifo_full_rlc;//fifo full push back indicator
+
+   //# transaction to rdmesh
+   output [2*LW-1:0] rdmesh_tran_out;  // transaction data
+   output \t     rdmesh_frame_out; // core frame
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\tfifo_empty;\t\t// From link_rxi_fifo of link_rxi_fifo.v
+   wire\t\t\tfifo_read;\t\t// From link_rxi_launcher of link_rxi_launcher.v
+   wire [14*LW-1:0]\tfifo_tran_out;\t\t// From link_rxi_fifo of link_rxi_fifo.v
+   wire\t\t\trdmesh_frame;\t\t// From link_rxi_launcher of link_rxi_launcher.v
+   wire [2*LW-1:0]\trdmesh_tran;\t\t// From link_rxi_launcher of link_rxi_launcher.v
+   // End of automatics
+
+  
+
+endmodule // link_rxi_channel
+module link_rxi_ctrl(/*AUTOARG*/
+   // Outputs
+   lclk, 
+   // Inputs
+   io_lclk, rxi_cfg_reg
+   );
+
+   parameter DW = `CFG_DW;
+   
+   
+   //Input clock
+   input           io_lclk;    //link clock from IO
+   input [DW-1:0]  rxi_cfg_reg;//used to deskew clock input
+
+   //Should we have a monitor pin for locking the timing?
+   
+   
+   //Delay Control word
+   //1 for rise
+   //1 for fall
+   
+   ///Output clocks to reciever block
+  
+   output  lclk;   //buffered clock without delay
+   
+
+
+   //Need to insert delay elements here
+   //How to insert delay with cts?
+   
+   assign lclk   =  io_lclk;
+  
+   
+   
+endmodule // link_clock
+
+
+//#############################################
+//# This block is a ""common"" channel for both
+//# mesh (multicast) and emesh transactions
+//#############################################
+module link_rxi_double_channel (/*AUTOARG*/
+   // Outputs
+   fifo_full_rlc, emesh_tran_out, emesh_frame_out, mesh_access_out,
+   mesh_write_out, mesh_dstaddr_out, mesh_srcaddr_out, mesh_data_out,
+   mesh_datamode_out, mesh_ctrlmode_out,
+   // Inputs
+   reset, cclk, cclk_en, ext_yid_k, ext_xid_k, rxi_lclk, who_am_i,
+   cfg_extcomp_dis, rxi_assembled_tran_rlc, fifo_access_rlc,
+   emesh_wait_in, mesh_wait_in
+   );
+
+   parameter LW   = `CFG_LW;//lvds tranceiver pairs per side
+   parameter DW   = `CFG_DW;//data width  
+   parameter AW   = `CFG_AW;//address width
+  
+   //#########
+   //# INPUTS
+   //#########
+
+   input             reset;   //reset input
+   input \t     cclk;    //core clock
+   input \t     cclk_en; // clock enable 
+   input [3:0] \t     ext_yid_k;//external y-id 
+   input [3:0] \t     ext_xid_k;//external x-id
+   input \t     rxi_lclk;//receiver link clock
+   input [3:0] \t     who_am_i;// specifies what link is that (north,east,south,west)
+   input \t     cfg_extcomp_dis;// Disable external coordinates comparison
+                                     // Every input transaction is received by the chip
+
+   input [14*LW-1:0] rxi_assembled_tran_rlc; // assembled data from the main fifo
+   input \t     fifo_access_rlc;  // fifo is accessed 
+
+   input \t     emesh_wait_in; //wait indication from emesh
+   input \t     mesh_wait_in;  //wait indication from mesh
+
+   //##########
+   //# OUTPUTS
+   //##########
+   output \t     fifo_full_rlc;//fifo full push back indicator
+
+   //# transaction to the emesh (transactions coming out off the chip)
+   output [2*LW-1:0] emesh_tran_out;  // transaction data
+   output \t     emesh_frame_out; // core frame
+
+   //# transaction to the mesh 
+   output \t     mesh_access_out;  // access control to the mesh
+   output \t     mesh_write_out;   // write control to the mesh
+   output [AW-1:0]   mesh_dstaddr_out; // destination address to the mesh
+   output [AW-1:0]   mesh_srcaddr_out; // source address to the mesh
+   output [DW-1:0]   mesh_data_out;    // data to the mesh
+   output [1:0]      mesh_datamode_out;// data mode to the mesh 
+   output [3:0]      mesh_ctrlmode_out;// ctrl mode to the mesh
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\taccess;\t\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   wire [3:0]\t\tctrlmode;\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   wire [DW-1:0]\tdata;\t\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   wire [1:0]\t\tdatamode;\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   wire [AW-1:0]\tdstaddr;\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   wire\t\t\temesh_fifo_read;\t// From link_rxi_launcher of link_rxi_launcher.v
+   wire\t\t\temesh_frame;\t\t// From link_rxi_launcher of link_rxi_launcher.v
+   wire [2*LW-1:0]\temesh_tran;\t\t// From link_rxi_launcher of link_rxi_launcher.v
+   wire\t\t\temesh_tran_dis;\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   wire\t\t\tfifo_empty;\t\t// From link_rxi_fifo of link_rxi_fifo.v
+   wire [14*LW-1:0]\tfifo_tran_out;\t\t// From link_rxi_fifo of link_rxi_fifo.v
+   wire\t\t\tmesh_fifo_read;\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   wire [AW-1:0]\tsrcaddr;\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   wire\t\t\twrite;\t\t\t// From link_rxi_mesh_launcher of link_rxi_mesh_launcher.v
+   // End of automatics
+
+   // #########
+   // # WIRES
+   // #########
+   wire     fifo_read;
+   wire     emesh_fifo_empty;
+
+   //#########
+   //# FIFO
+   //#########
+   assign fifo_read       = mesh_fifo_read;
+                         
+   link_rxi_fifo link_rxi_fifo (/*AUTOINST*/
+\t\t\t\t// Outputs
+\t\t\t\t.fifo_full_rlc\t(fifo_full_rlc),
+\t\t\t\t.fifo_tran_out\t(fifo_tran_out[14*LW-1:0]),
+\t\t\t\t.fifo_empty\t(fifo_empty),
+\t\t\t\t// Inputs
+\t\t\t\t.reset\t\t(reset),
+\t\t\t\t.cclk\t\t(cclk),
+\t\t\t\t.cclk_en\t(cclk_en),
+\t\t\t\t.rxi_lclk\t(rxi_lclk),
+\t\t\t\t.rxi_assembled_tran_rlc(rxi_assembled_tran_rlc[14*LW-1:0]),
+\t\t\t\t.fifo_access_rlc(fifo_access_rlc),
+\t\t\t\t.fifo_read\t(fifo_read));
+
+  
+   //###################################
+   //# Transaction Launcher to Mesh
+   //###################################
+
+   link_rxi_mesh_launcher link_rxi_mesh_launcher(/*AUTOINST*/
+\t\t\t\t\t\t // Outputs
+\t\t\t\t\t\t .mesh_fifo_read\t(mesh_fifo_read),
+\t\t\t\t\t\t .emesh_tran_dis\t(emesh_tran_dis),
+\t\t\t\t\t\t .access\t\t(access),
+\t\t\t\t\t\t .write\t\t\t(write),
+\t\t\t\t\t\t .datamode\t\t(datamode[1:0]),
+\t\t\t\t\t\t .ctrlmode\t\t(ctrlmode[3:0]),
+\t\t\t\t\t\t .data\t\t\t(data[DW-1:0]),
+\t\t\t\t\t\t .dstaddr\t\t(dstaddr[AW-1:0]),
+\t\t\t\t\t\t .srcaddr\t\t(srcaddr[AW-1:0]),
+\t\t\t\t\t\t // Inputs
+\t\t\t\t\t\t .ext_yid_k\t\t(ext_yid_k[3:0]),
+\t\t\t\t\t\t .ext_xid_k\t\t(ext_xid_k[3:0]),
+\t\t\t\t\t\t .who_am_i\t\t(who_am_i[3:0]),
+\t\t\t\t\t\t .cfg_extcomp_dis\t(cfg_extcomp_dis),
+\t\t\t\t\t\t .fifo_tran_out\t\t(fifo_tran_out[14*LW-1:0]),
+\t\t\t\t\t\t .fifo_empty\t\t(fifo_empty),
+\t\t\t\t\t\t .mesh_wait_in\t\t(mesh_wait_in));
+
+ 
+
+   //##################################
+   //#    Interface with mesh
+   //# on output transactions only
+   //# * input from the mesh is driven
+   //# by a diferent block
+   //##################################
+
+   /* e16_mesh_interface AUTO_TEMPLATE (
+                                    .clk               (cclk),
+                                    .clk_en            (cclk_en),
+ \t\t\t\t    .access_in\t       (1\'b0),
+\t\t\t\t    .write_in\t       (1\'b0),
+\t\t\t\t    .datamode_in       (2\'b00),
+\t\t\t\t    .ctrlmode_in       (4\'b0000),
+\t\t\t\t    .data_in\t       ({(DW){1\'b0}}),
+\t\t\t\t    .dstaddr_in\t       ({(AW){1\'b0}}),
+\t\t\t\t    .srcaddr_in\t       ({(AW){1\'b0}}),
+                                    .wait_int          (1\'b0),
+\t\t\t\t    .emesh_core_wait   (1\'b0),
+\t\t\t\t    .emesh_core_clk_en ({(11){1\'b1}}),
+\t\t\t\t    .emesh_tran_sel    (1\'b0),
+                                    .wait_in           (mesh_wait_in),
+                                    .\\(.*\\)_reg        (),
+                                    .wait_out          (),
+                                    .\\(.*\\)_out        (mesh_\\1_out[]),
+                                );
+    */
+   e16_mesh_interface mesh_interface(/*AUTOINST*/
+\t\t\t\t // Outputs
+\t\t\t\t .wait_out\t\t(),\t\t // Templated
+\t\t\t\t .access_out\t\t(mesh_access_out), // Templated
+\t\t\t\t .write_out\t\t(mesh_write_out), // Templated
+\t\t\t\t .datamode_out\t\t(mesh_datamode_out[1:0]), // Templated
+\t\t\t\t .ctrlmode_out\t\t(mesh_ctrlmode_out[3:0]), // Templated
+\t\t\t\t .data_out\t\t(mesh_data_out[DW-1:0]), // Templated
+\t\t\t\t .dstaddr_out\t\t(mesh_dstaddr_out[AW-1:0]), // Templated
+\t\t\t\t .srcaddr_out\t\t(mesh_srcaddr_out[AW-1:0]), // Templated
+\t\t\t\t .access_reg\t\t(),\t\t // Templated
+\t\t\t\t .write_reg\t\t(),\t\t // Templated
+\t\t\t\t .datamode_reg\t\t(),\t\t // Templated
+\t\t\t\t .ctrlmode_reg\t\t(),\t\t // Templated
+\t\t\t\t .data_reg\t\t(),\t\t // Templated
+\t\t\t\t .dstaddr_reg\t\t(),\t\t // Templated
+\t\t\t\t .srcaddr_reg\t\t(),\t\t // Templated
+\t\t\t\t // Inputs
+\t\t\t\t .clk\t\t\t(cclk),\t\t // Templated
+\t\t\t\t .clk_en\t\t(cclk_en),\t // Templated
+\t\t\t\t .reset\t\t\t(reset),
+\t\t\t\t .wait_in\t\t(mesh_wait_in),\t // Templated
+\t\t\t\t .access_in\t\t(1\'b0),\t\t // Templated
+\t\t\t\t .write_in\t\t(1\'b0),\t\t // Templated
+\t\t\t\t .datamode_in\t\t(2\'b00),\t // Templated
+\t\t\t\t .ctrlmode_in\t\t(4\'b0000),\t // Templated
+\t\t\t\t .data_in\t\t({(DW){1\'b0}}),\t // Templated
+\t\t\t\t .dstaddr_in\t\t({(AW){1\'b0}}),\t // Templated
+\t\t\t\t .srcaddr_in\t\t({(AW){1\'b0}}),\t // Templated
+\t\t\t\t .wait_int\t\t(1\'b0),\t\t // Templated
+\t\t\t\t .access\t\t(access),
+\t\t\t\t .write\t\t\t(write),
+\t\t\t\t .datamode\t\t(datamode[1:0]),
+\t\t\t\t .ctrlmode\t\t(ctrlmode[3:0]),
+\t\t\t\t .data\t\t\t(data[DW-1:0]),
+\t\t\t\t .dstaddr\t\t(dstaddr[AW-1:0]),
+\t\t\t\t .srcaddr\t\t(srcaddr[AW-1:0]));
+
+
+endmodule // link_rxi_double_channel
+
+//##############################################################################
+//# 
+//# This is a FOUR entries (FAD=2) receiver FIFO with the main function of
+//# synchronization between RXI link clock domain and core clock domain
+//# It seems that for the FIFO to function without ""build in"" push back
+//# we will need at least THREE entries, so choosing FOUR entries puts us
+//# in a safer position.
+//#
+//# * This FIFO will function even with a single entry (with some modifications)
+//#   but if the number of entries is not sufficient for the synchronization
+//#   the ""build in"" push back will be driven on every new write control.
+//#
+//################################################################################
+ 
+module link_rxi_fifo (/*AUTOARG*/
+   // Outputs
+   fifo_full_rlc, fifo_tran_out, fifo_empty,
+   // Inputs
+   reset, cclk, cclk_en, rxi_lclk, rxi_assembled_tran_rlc,
+   fifo_access_rlc, fifo_read
+   );
+
+   parameter LW    = `CFG_LW;//lvds tranceiver pairs per side
+   parameter FAD   = 2; // Number of bits to access all the entries 
+   localparam MD = 1<<FAD;
+   
+   //#########
+   //# INPUTS
+   //#########
+
+   input          reset;   //reset input
+   input \t  cclk;    //core clock
+   input \t  cclk_en; // clock enable 
+   input \t  rxi_lclk;//receiver link clock
+
+   input [14*LW-1:0] rxi_assembled_tran_rlc; // assembled data from the main fifo
+   input \t     fifo_access_rlc;        // fifo is accessed
+   //# from the launcher
+   input \t     fifo_read;
+   //##########
+   //# OUTPUTS
+   //##########
+
+   output \t     fifo_full_rlc;//fifo full push back indicator
+   //# to the launcher
+   output [14*LW-1:0] fifo_tran_out;
+   output \t      fifo_empty;
+
+   //##########
+   //# REGS
+   //##########
+
+   reg [14*LW-1:0] fifo_mem[MD-1:0];
+   reg [FAD:0] \t   wr_binary_pointer_rlc;
+   reg [FAD:0] \t   wr_gray_pointer_rlc;
+   reg \t\t   fifo_full_rlc;
+
+   reg [FAD:0] \t   rd_binary_pointer;
+   reg [FAD:0] \t   rd_gray_pointer;
+   reg \t\t   fifo_empty;
+
+   //#########
+   //# WIRES
+   //#########
+
+   wire \t      wr_write_rlc; // FIFO write control
+   wire [FAD-1:0]     wr_addr_rlc;
+   wire [FAD:0]       wr_binary_next_rlc;
+   wire [FAD:0]       wr_gray_next_rlc;
+   wire \t      fifo_full_next_rlc;
+   wire [FAD:0]       rd_gray_pointer_rlc;
+
+   wire [FAD-1:0]     rd_addr;
+   wire [FAD:0]       rd_binary_next;
+   wire [FAD:0]       rd_gray_next;
+   wire \t      fifo_empty_next;
+   wire [FAD:0]       wr_gray_pointer;
+
+   /*AUTOWIRE*/
+   /*AUTOINPUT*/
+  
+   //##################################################################
+   //#              Write control generation:
+   //#
+   //# FIFO is being written according to the state of fifo_access_rlc
+   //# control driven by main fifo and independent on the current
+   //# state of the FIFO.
+   //# We do mask this control with fifo full signal but this mask
+   //# is really redundant.
+   //# The reason for that is the following:
+   //# The FASTEST THROUGHPUT the transaction can be dispatched from
+   //# the main fifo here is ONE TRANSACTION IN EVERY FOUR CYCLES.
+   //# FIFO full indication is sent back on the first cycle after
+   //# receiving the transaction causing the fifo to be full.
+   //# This indication is sampled two more times in the main fifo
+   //# and then prevents new transaction to be dispatched.
+   //# So it takes THREE CYCLES to stop new transaction versus
+   //# 'b'FOUR CYCLES to dispatch new one and therefore we are save.
+   //####################################################################
+   
+   assign wr_write_rlc = fifo_access_rlc & ~fifo_full_rlc;
+
+   //#################################
+   //# FIFO data
+   //#################################
+ 
+   //# Write
+   always @ (posedge rxi_lclk)
+     if (wr_write_rlc)
+       fifo_mem[wr_addr_rlc[FAD-1:0]] <= rxi_assembled_tran_rlc[14*LW-1:0];
+   
+   //# Read (for dispatch)
+   assign fifo_tran_out[14*LW-1:0] = fifo_mem[rd_addr[FAD-1:0]];
+
+   //#####################################
+   //# FIFO Write State Machine
+   //#####################################
+
+   //# While for the actual address calculation we use [FAD-1:0] bits only,
+   //# the bit FAD of the counter is needed in order to distinguish
+   //# between the fifo entry currently being written and the one
+   //# written in the previous ""round"" (FAD is a carry-out bit and is
+   //# switched every ""round"")
+   always @(posedge rxi_lclk or posedge reset)
+     if(reset)
+       begin
+\t  wr_binary_pointer_rlc[FAD:0] <= {(FAD+1){1\'b0}};
+\t  wr_gray_pointer_rlc[FAD:0]   <= {(FAD+1){1\'b0}};
+       end
+     else if(wr_write_rlc)
+       begin
+\t  wr_binary_pointer_rlc[FAD:0] <= wr_binary_next_rlc[FAD:0];\t  
+\t  wr_gray_pointer_rlc[FAD:0]   <= wr_gray_next_rlc[FAD:0];\t  
+       end\t  
+
+   assign wr_addr_rlc[FAD-1:0]       = wr_binary_pointer_rlc[FAD-1:0];
+   assign wr_binary_next_rlc[FAD:0]  = wr_binary_pointer_rlc[FAD:0] + 
+\t\t\t\t       {{(FAD){1\'b0}},wr_write_rlc};
+
+   //# Gray Pointer Conversion (for more reliable synchronization)!
+   assign wr_gray_next_rlc[FAD:0] = {1\'b0,wr_binary_next_rlc[FAD:1]} ^ 
+\t\t\t\t    wr_binary_next_rlc[FAD:0];
+
+   //# FIFO full indication
+   assign fifo_full_next_rlc = 
+\t\t\t   (wr_gray_next_rlc[FAD-2:0] == rd_gray_pointer_rlc[FAD-2:0]) &
+                           (wr_gray_next_rlc[FAD]     ^  rd_gray_pointer_rlc[FAD])     &
+                           (wr_gray_next_rlc[FAD-1]   ^  rd_gray_pointer_rlc[FAD-1]);
+\t\t\t      
+   always @ (posedge rxi_lclk or posedge reset)
+     if(reset)
+       fifo_full_rlc <= 1\'b0;
+     else 
+       fifo_full_rlc <= fifo_full_next_rlc;
+
+   //#############################
+   //# FIFO Read State Machine
+   //#############################
+    
+   always @(posedge cclk or posedge reset)
+     if(reset)
+       begin
+\t  rd_binary_pointer[FAD:0]  <= {(FAD+1){1\'b0}};
+\t  rd_gray_pointer[FAD:0]    <= {(FAD+1){1\'b0}};
+       end
+     else if(cclk_en)
+       if(fifo_read)
+\t begin
+\t    rd_binary_pointer[FAD:0]  <= rd_binary_next[FAD:0];\t  
+\t    rd_gray_pointer[FAD:0]    <= rd_gray_next[FAD:0];\t  
+\t end
+
+   assign rd_addr[FAD-1:0]       = rd_binary_pointer[FAD-1:0];
+   assign rd_binary_next[FAD:0]  = rd_binary_pointer[FAD:0] + {{(FAD){1\'b0}},fifo_read};
+
+   //# Gray Pointer Conversion (for more reliable synchronization)!
+   assign rd_gray_next[FAD:0]  = {1\'b0,rd_binary_next[FAD:1]} ^ rd_binary_next[FAD:0];
+
+   //# FIFO empty indication
+   assign fifo_empty_next = (rd_gray_next[FAD:0]==wr_gray_pointer[FAD:0]);
+
+   always @ (posedge cclk or posedge reset)
+     if(reset)
+       fifo_empty <= 1\'b1;
+     else if(cclk_en)
+       fifo_empty <= fifo_empty_next;
+
+   //####################################################
+   //# Synchronization between rd/wr domains
+   //####################################################
+
+   e16_synchronizer #(.DW(FAD+1)) sync_rd2wr (.out\t (rd_gray_pointer_rlc[FAD:0]), 
+                                          .in\t (rd_gray_pointer[FAD:0]), 
+\t\t\t\t\t  .clk\t (rxi_lclk),
+\t\t\t\t\t  .reset (reset));
+   
+   e16_synchronizer #(.DW(FAD+1)) sync_wr2rd (.out\t (wr_gray_pointer[FAD:0]), 
+                                          .in\t (wr_gray_pointer_rlc[FAD:0]), 
+\t\t\t\t\t  .clk\t (cclk),
+\t\t\t\t\t  .reset (reset));
+ 
+
+
+endmodule // link_rxi_fifo
+module link_rxi_launcher (/*AUTOARG*/
+   // Outputs
+   fifo_read, emesh_tran, emesh_frame,
+   // Inputs
+   reset, cclk, cclk_en, fifo_tran_out, fifo_empty, emesh_wait_in
+   );
+
+   parameter LW   = `CFG_LW;//lvds tranceiver pairs per side
+   
+   //#########
+   //# INPUTS
+   //#########
+
+   input             reset;   // reset input
+   input \t     cclk;    // core clock
+   input \t     cclk_en; // clock enable 
+
+   //# from the fifo
+   input [14*LW-1:0] fifo_tran_out; // transaction out of the fifo
+   input \t     fifo_empty;    // fifo is empty
+   //# from the emesh
+   input \t     emesh_wait_in; // emesh wait indication 
+ 
+   //##########
+   //# OUTPUTS
+   //##########
+   //# to the fifo
+   output \t     fifo_read; // read next entry
+   //# to the emesh
+   output [2*LW-1:0] emesh_tran;  // transaction data
+   output \t     emesh_frame; // emesh frame 
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   // #########
+   // # REGS
+   // #########
+
+   reg [2:0]  launch_pointer;
+
+   // #########
+   // # WIRES
+   // #########
+
+   wire       last_tran;
+   wire [2:0] launch_pointer_incr;
+   wire [6:0] launch_sel;
+
+   //################################
+   //# next transaction read control
+   //################################
+
+   assign fifo_read = last_tran & ~emesh_wait_in;
+
+   //############################################
+   //# transaction launcher state machine
+   //############################################
+   assign last_tran = (launch_pointer[2:0] == 3\'b110);
+                        
+   assign launch_pointer_incr[2:0] = last_tran ? 3\'b000 : (launch_pointer[2:0] + 3\'b001);
+
+   always @ (posedge cclk or posedge reset)
+     if(reset)
+       launch_pointer[2:0] <= 3\'b000;
+     else if(cclk_en)
+       if (~(fifo_empty | emesh_wait_in))
+\t launch_pointer[2:0] <= launch_pointer_incr[2:0];
+
+   assign launch_sel[0] = (launch_pointer[2:0] == 3\'b000);
+   assign launch_sel[1] = (launch_pointer[2:0] == 3\'b001);
+   assign launch_sel[2] = (launch_pointer[2:0] == 3\'b010);
+   assign launch_sel[3] = (launch_pointer[2:0] == 3\'b011);
+   assign launch_sel[4] = (launch_pointer[2:0] == 3\'b100);
+   assign launch_sel[5] = (launch_pointer[2:0] == 3\'b101);
+   assign launch_sel[6] = (launch_pointer[2:0] == 3\'b110);
+
+   //###########################
+   //# frame and data selection
+   //###########################
+   
+   assign emesh_frame  =  ~(fifo_empty | last_tran);
+
+   e16_mux7 #(2*LW) mux7(// Outputs
+\t\t     .out (emesh_tran[2*LW-1:0]),
+\t\t     // Inputs
+\t\t     .in0 (fifo_tran_out[2*LW-1:0]),      .sel0 (launch_sel[0]),
+\t\t     .in1 (fifo_tran_out[4*LW-1:2*LW]),   .sel1 (launch_sel[1]),
+\t\t     .in2 (fifo_tran_out[6*LW-1:4*LW]),   .sel2 (launch_sel[2]),
+\t\t     .in3 (fifo_tran_out[8*LW-1:6*LW]),   .sel3 (launch_sel[3]),
+\t\t     .in4 (fifo_tran_out[10*LW-1:8*LW]),  .sel4 (launch_sel[4]),
+\t\t     .in5 (fifo_tran_out[12*LW-1:10*LW]), .sel5 (launch_sel[5]),
+\t\t     .in6 (fifo_tran_out[14*LW-1:12*LW]), .sel6 (launch_sel[6]));
+
+endmodule // link_rxi_launcher
+module link_rxi_mesh_launcher (/*AUTOARG*/
+   // Outputs
+   mesh_fifo_read, emesh_tran_dis, access, write, datamode, ctrlmode,
+   data, dstaddr, srcaddr,
+   // Inputs
+   ext_yid_k, ext_xid_k, who_am_i, cfg_extcomp_dis, fifo_tran_out,
+   fifo_empty, mesh_wait_in
+   );
+
+   parameter AW   = `CFG_AW  ;//address width
+   parameter DW   = `CFG_DW  ;//data width  
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+
+   //#########
+   //# INPUTS
+   //#########
+
+   input [3:0] \t     ext_yid_k;//external y-id 
+   input [3:0] \t     ext_xid_k;//external x-id
+   input [3:0] \t     who_am_i;// specifies what link is that (north,east,south,west)
+   input \t     cfg_extcomp_dis;// Disable external coordinates comparison
+                                     // Every input transaction is received by the chip
+   //# from the fifo
+   input [14*LW-1:0] fifo_tran_out; // transaction out of the fifo
+   input \t     fifo_empty;    // fifo is empty
+   //# from the mesh
+   input \t     mesh_wait_in; // wait indication from mesh
+
+   //##########
+   //# OUTPUTS
+   //##########
+   //# to the fifo
+   output \t     mesh_fifo_read; // read next entry
+   //# to prevent emesh launch
+   output \t     emesh_tran_dis;
+   //# to the mesh
+   output \t     access;
+   output \t     write;
+   output [1:0]      datamode;
+   output [3:0]      ctrlmode;   \t\t    
+   output [DW-1:0]   data;
+   output [AW-1:0]   dstaddr;
+   output [AW-1:0]   srcaddr;   
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   // #########
+   // # WIRES
+   // #########
+   wire [AW-1:0] srcaddr_int;
+   wire [AW-1:0] srcaddr_multicast;
+   wire \t access_int;
+   wire \t multicast_match;
+
+   wire [1:0] \t srcaddr_int_ycoord;
+   wire [1:0] \t srcaddr_int_xcoord;
+
+   wire [1:0] \t north_srcaddr_int_ycoord;
+   wire [1:0] \t north_srcaddr_int_xcoord;
+   wire [1:0] \t east_srcaddr_int_ycoord;
+   wire [1:0] \t east_srcaddr_int_xcoord;
+   wire [1:0] \t south_srcaddr_int_ycoord;
+   wire [1:0] \t south_srcaddr_int_xcoord;
+   wire [1:0] \t west_srcaddr_int_ycoord;
+   wire [1:0] \t west_srcaddr_int_xcoord;
+
+   wire [3:0] \t dst_y_k;
+   wire [3:0] \t dst_x_k;
+   wire \t west_east_corner_tran;
+   wire \t north_south_corner_tran;
+   wire [3:0] \t corner_tran;
+   wire \t corner_tran_match;
+   wire \t mesh_tran_match;
+
+   //# If valid mesh transaction is detected we should prevent the launch
+   //# of this transaction on the emesh
+   assign emesh_tran_dis = access;
+
+   //# Valid mesh (multicast or not) transaction
+   assign access = ~fifo_empty & access_int & 
+\t\t   (corner_tran_match | multicast_match | mesh_tran_match);
+
+   //# Read next entry
+   assign mesh_fifo_read = access & ~mesh_wait_in;
+
+   //# Mesh transaction fields extraction
+   assign ctrlmode[3:0]   =  fifo_tran_out[2*LW-1:2*LW-4];
+
+   assign dstaddr[AW-1:0] = {fifo_tran_out[2*LW-5:0],
+                             fifo_tran_out[4*LW-1:2*LW],
+                             fifo_tran_out[6*LW-1:6*LW-4]};
+
+   assign datamode[1:0]   =  fifo_tran_out[6*LW-5:6*LW-6];
+   assign write           =  fifo_tran_out[6*LW-7]; 
+   assign access_int      =  fifo_tran_out[5*LW]; 
+
+   assign data[DW-1:0]    = {fifo_tran_out[5*LW-1:4*LW],
+                             fifo_tran_out[8*LW-1:6*LW],
+                             fifo_tran_out[10*LW-1:9*LW]};
+
+   assign srcaddr_int[AW-1:0] = {fifo_tran_out[9*LW-1:8*LW],
+                                 fifo_tran_out[12*LW-1:10*LW],
+                                 fifo_tran_out[14*LW-1:13*LW]};
+
+   //# Multicast transaction (there is no multicast transaction when no external compare)
+   assign multicast_match = write & ~cfg_extcomp_dis &
+\t\t\t    (ctrlmode[1:0]==2\'b11) & ~(datamode[1:0] == 2\'b11);
+
+   //# We rewrite the internal coordinates of every multicast transaction
+   //# in the way it will propagate through all the scores in the system
+   //# The new internal coordinates will be those of the attached to the
+   //# current link score and are constant and different for every link
+   //# !!! Since the transaction will propagate in all directions out of the
+   //# !!! attached score, it will try to get out of the chip on the same
+   //# !!! link, but it won\'t happen due to the external coordinate comparison
+   //# !!! of the link transmitter.
+
+   assign north_srcaddr_int_ycoord[1:0] = 2\'b00;
+   assign east_srcaddr_int_ycoord[1:0]  = 2\'b00;
+   assign south_srcaddr_int_ycoord[1:0] = 2\'b11;
+   assign west_srcaddr_int_ycoord[1:0]  = 2\'b00;
+
+   assign north_srcaddr_int_xcoord[1:0] = 2\'b00;
+   assign east_srcaddr_int_xcoord[1:0]  = 2\'b11;
+   assign south_srcaddr_int_xcoord[1:0] = 2\'b00;
+   assign west_srcaddr_int_xcoord[1:0]  = 2\'b00;
+
+   assign srcaddr_int_ycoord[1:0] = {(2){who_am_i[3]}} & north_srcaddr_int_ycoord[1:0]|
+\t\t\t\t    {(2){who_am_i[2]}} & east_srcaddr_int_ycoord[1:0] |
+\t\t\t\t    {(2){who_am_i[1]}} & south_srcaddr_int_ycoord[1:0]|
+\t\t\t\t    {(2){who_am_i[0]}} & west_srcaddr_int_ycoord[1:0];
+
+   assign srcaddr_int_xcoord[1:0] = {(2){who_am_i[3]}} & north_srcaddr_int_xcoord[1:0]|
+\t\t\t\t    {(2){who_am_i[2]}} & east_srcaddr_int_xcoord[1:0] |
+\t\t\t\t    {(2){who_am_i[1]}} & south_srcaddr_int_xcoord[1:0]|
+\t\t\t\t    {(2){who_am_i[0]}} & west_srcaddr_int_xcoord[1:0];
+
+   //# Modified source address
+   //assign srcaddr_multicast[AW-1:0] = {srcaddr_int[31:26],1\'b0,srcaddr_int_ycoord[1:0],
+   //\t\t\t\t                1\'b0,srcaddr_int_xcoord[1:0],
+   //                                    srcaddr_int[19:0]};
+
+   assign srcaddr_multicast[AW-1:0] = {srcaddr_int[31:28],srcaddr_int_ycoord[1:0],
+             \t\t               srcaddr_int[25:22],srcaddr_int_xcoord[1:0],
+                                       srcaddr_int[19:0]};
+
+   assign srcaddr[AW-1:0] = multicast_match ? srcaddr_multicast[AW-1:0] : 
+\t\t\t                      srcaddr_int[AW-1:0];
+
+   //# Mesh transaction for external corners detection
+//   assign dst_y_k[2:0] = dstaddr[31:29];
+//   assign dst_x_k[2:0] = dstaddr[28:26];
+   assign dst_y_k[3:0] = dstaddr[31:28];
+   assign dst_x_k[3:0] = dstaddr[25:22];
+
+   assign west_east_corner_tran = ((dst_x_k[3:0] == ext_xid_k[3:0]) &
+\t\t\t\t  ~(dst_y_k[3:0] == ext_yid_k[3:0]));
+
+   assign north_south_corner_tran = (~(dst_x_k[3:0] == ext_xid_k[3:0]) &
+\t\t\t\t      (dst_y_k[3:0] == ext_yid_k[3:0]));
+
+   assign corner_tran[3:0] = {north_south_corner_tran, west_east_corner_tran,
+                              north_south_corner_tran, west_east_corner_tran};
+
+   assign corner_tran_match = ~cfg_extcomp_dis & (|(corner_tran[3:0] & who_am_i[3:0]));
+   //# Regular Mesh transaction
+   assign mesh_tran_match = cfg_extcomp_dis | 
+\t\t\t    (~multicast_match & ((dst_x_k[3:0] == ext_xid_k[3:0]) &
+\t\t\t                         (dst_y_k[3:0] == ext_yid_k[3:0])));
+
+endmodule // link_rxi_mesh_launcher
+//#############################################################
+//# This block is a receiver of the read transactions only
+//# Read transactions will enter the chip on rdmesh only
+//#############################################################
+module link_rxi_rd (/*AUTOARG*/
+   // Outputs
+   rxi_rd_wait, c0_rdmesh_frame_out, c0_rdmesh_tran_out,
+   c1_rdmesh_frame_out, c1_rdmesh_tran_out, c2_rdmesh_frame_out,
+   c2_rdmesh_tran_out, c3_rdmesh_frame_out, c3_rdmesh_tran_out,
+   // Inputs
+   reset, ext_yid_k, ext_xid_k, vertical_k, who_am_i, cfg_extcomp_dis,
+   rxi_data, rxi_lclk, rxi_frame, c0_clk_in, c1_clk_in, c2_clk_in,
+   c3_clk_in, c0_rdmesh_wait_in, c1_rdmesh_wait_in, c2_rdmesh_wait_in,
+   c3_rdmesh_wait_in
+   );
+
+   parameter LW   = `CFG_LW;//lvds tranceiver pairs per side
+\t\t     
+   // #########
+   // # Inputs
+   // #########
+
+   input             reset;     // reset input
+   input [3:0] \t     ext_yid_k; // external y-id 
+   input [3:0] \t     ext_xid_k; // external x-id
+   input             vertical_k;// specifies if block is vertical or horizontal
+   input [3:0] \t     who_am_i;  // specifies what link is that (north,east,south,west)
+   input \t     cfg_extcomp_dis;// Disable external coordinates comparison
+                                     // Every input transaction is received by the chip
+  
+   input [LW-1:0]    rxi_data;  // Byte word
+   input             rxi_lclk;  // receive clock (adjusted to the frame/data)
+   input             rxi_frame; // indicates new transmission
+
+   // # Sync clocks
+   input             c0_clk_in; // clock of the core
+   input             c1_clk_in; // clock of the core
+   input             c2_clk_in; // clock of the core
+   input             c3_clk_in; // clock of the core
+
+   // # Wait indicators
+   input             c0_rdmesh_wait_in; // wait
+   input             c1_rdmesh_wait_in; // wait
+   input             c2_rdmesh_wait_in; // wait
+   input             c3_rdmesh_wait_in; // wait
+
+   // ##########
+   // # Outputs
+   // ##########
+
+   output \t     rxi_rd_wait;  //wait indicator for read transactions 
+
+   // # RDMESH (any read transaction)
+   output            c0_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c0_rdmesh_tran_out;  // serialized transaction
+   output            c1_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c1_rdmesh_tran_out;  // serialized transaction
+   output            c2_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c2_rdmesh_tran_out;  // serialized transaction
+   output            c3_rdmesh_frame_out; // transaction frame
+   output [2*LW-1:0] c3_rdmesh_tran_out;  // serialized transaction
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\tc0_fifo_access_rlc;\t// From link_rxi_buffer of link_rxi_buffer.v
+   wire\t\t\tc0_fifo_full_rlc;\t// From c0_link_rxi_channel of link_rxi_channel.v
+   wire\t\t\tc1_fifo_access_rlc;\t// From link_rxi_buffer of link_rxi_buffer.v
+   wire\t\t\tc1_fifo_full_rlc;\t// From c1_link_rxi_channel of link_rxi_channel.v
+   wire\t\t\tc2_fifo_access_rlc;\t// From link_rxi_buffer of link_rxi_buffer.v
+   wire\t\t\tc2_fifo_full_rlc;\t// From c2_link_rxi_channel of link_rxi_channel.v
+   wire\t\t\tc3_fifo_access_rlc;\t// From link_rxi_buffer of link_rxi_buffer.v
+   wire\t\t\tc3_fifo_full_rlc;\t// From c3_link_rxi_channel of link_rxi_channel.v
+   wire [14*LW-1:0]\trxi_assembled_tran_rlc;\t// From link_rxi_buffer of link_rxi_buffer.v
+   // End of automatics
+
+   // ################################
+   // # Receiver buffer instantiation
+   // ################################
+
+   /*link_rxi_buffer AUTO_TEMPLATE (.rxi_rd             (1\'b1),
+                                    .rxi_wait\t\t(rxi_rd_wait),
+                                    .reset\t\t(reset),
+                                    .vertical_k\t\t(vertical_k),
+                                    .ext_yid_k\t\t(ext_yid_k[3:0]),
+                                    .ext_xid_k\t\t(ext_xid_k[3:0]),
+                                    .rxi_data\t\t(rxi_data[LW-1:0]),
+\t\t\t\t    .rxi_lclk\t\t(rxi_lclk),
+\t\t\t\t    .rxi_frame\t\t(rxi_frame),
+                                    .rxi_\\(.*\\)_access  (\\1_fifo_access_rlc),
+                                    .\\(.*\\)             (\\1_rlc[]),
+\t\t\t\t    .cfg_extcomp_dis\t(cfg_extcomp_dis), 
+                                        );
+    */
+   link_rxi_buffer link_rxi_buffer(/*AUTOINST*/
+\t\t\t\t   // Outputs
+\t\t\t\t   .rxi_wait\t\t(rxi_rd_wait),\t // Templated
+\t\t\t\t   .rxi_assembled_tran\t(rxi_assembled_tran_rlc[14*LW-1:0]), // Templated
+\t\t\t\t   .rxi_c0_access\t(c0_fifo_access_rlc), // Templated
+\t\t\t\t   .rxi_c1_access\t(c1_fifo_access_rlc), // Templated
+\t\t\t\t   .rxi_c2_access\t(c2_fifo_access_rlc), // Templated
+\t\t\t\t   .rxi_c3_access\t(c3_fifo_access_rlc), // Templated
+\t\t\t\t   // Inputs
+\t\t\t\t   .reset\t\t(reset),\t // Templated
+\t\t\t\t   .vertical_k\t\t(vertical_k),\t // Templated
+\t\t\t\t   .ext_yid_k\t\t(ext_yid_k[3:0]), // Templated
+\t\t\t\t   .ext_xid_k\t\t(ext_xid_k[3:0]), // Templated
+\t\t\t\t   .rxi_data\t\t(rxi_data[LW-1:0]), // Templated
+\t\t\t\t   .rxi_lclk\t\t(rxi_lclk),\t // Templated
+\t\t\t\t   .rxi_frame\t\t(rxi_frame),\t // Templated
+\t\t\t\t   .rxi_rd\t\t(1\'b1),\t\t // Templated
+\t\t\t\t   .cfg_extcomp_dis\t(cfg_extcomp_dis), // Templated
+\t\t\t\t   .c0_fifo_full\t(c0_fifo_full_rlc), // Templated
+\t\t\t\t   .c1_fifo_full\t(c1_fifo_full_rlc), // Templated
+\t\t\t\t   .c2_fifo_full\t(c2_fifo_full_rlc), // Templated
+\t\t\t\t   .c3_fifo_full\t(c3_fifo_full_rlc)); // Templated
+
+
+endmodule // link_rxi_rd
+module link_rxi_router (/*AUTOARG*/
+   // Outputs
+   fifo_read_cvre, read_out, write_out, dst_addr_out, src_addr_out,
+   data_out, datamode_out, ctrlmode_out,
+   // Inputs
+   fifo_data_out_cvre, fifo_empty_cvre, wait_in
+   );
+
+   parameter AW  = 32;
+   parameter MDW = 32;
+   parameter FW  = 112;
+   parameter XW  = 6;
+   parameter YW  = 6;
+   parameter ZW  = 6;
+   parameter IAW = 20;//internal address width=20 bits=1MB
+   
+   /********************************************/
+   /*FIFO Interface                            */
+   /********************************************/
+   input [FW-1:0]   fifo_data_out_cvre;
+   input            fifo_empty_cvre;
+   output           fifo_read_cvre;     //depends on empty and grants
+   
+   /********************************************/
+   /*Transaction                               */
+   /********************************************/
+   //Mesh wait indicators
+   input             wait_in;
+   output            read_out;
+   output            write_out;
+   output [AW-1:0]   dst_addr_out;
+   output [AW-1:0]   src_addr_out;
+   output [MDW-1:0]  data_out;    
+   output [1:0]      datamode_out;
+   output [3:0]      ctrlmode_out;
+
+
+ 
+   /********************************************/
+   /*Wires                                     */
+   /********************************************/
+   wire           mesh_write_cvre;
+   wire           mesh_read_cvre;
+   wire [1:0]     mesh_datamode_cvre;
+   wire [3:0]     mesh_ctrlmode_cvre;
+   wire [7:0]     mesh_reserved_cvre;
+   wire [MDW-1:0] mesh_data_cvre;
+   wire [AW-1:0]  mesh_src_addr_cvre;
+   wire [AW-1:0]  mesh_dst_addr_cvre;
+   wire [1:0]     compare_addr;
+   
+   wire           request_cvre;
+   
+   /********************************************/
+   /*Splitting Vector Into Components          */
+   /********************************************/
+   assign mesh_write_cvre           = fifo_data_out_cvre[0];
+   assign mesh_read_cvre            = fifo_data_out_cvre[1];
+   assign mesh_datamode_cvre[1:0]   = fifo_data_out_cvre[3:2];
+   assign mesh_ctrlmode_cvre[3:0]   = fifo_data_out_cvre[7:4];
+   assign mesh_reserved_cvre[7:0]   = fifo_data_out_cvre[15:8];
+   assign mesh_data_cvre[MDW-1:0]   = fifo_data_out_cvre[47:16];
+   assign mesh_dst_addr_cvre[AW-1:0]= fifo_data_out_cvre[79:48];
+   assign mesh_src_addr_cvre[AW-1:0]= fifo_data_out_cvre[111:80];
+
+
+   /********************************************/
+   /*Address Decoding                          */
+   /********************************************/
+
+   /********************************************/
+   /*Address Decoding                          */
+   /********************************************/
+   //Requests
+   //How to 
+   assign request_cvre         = ~fifo_empty_cvre;
+   
+   /********************************************/
+   /*Only Doing FIFO read when granted         */
+   /********************************************/
+   assign fifo_read_cvre       = (request_cvre  & ~wait_in);
+   
+   
+   /********************************************/
+   /*DISTRIBUTING TO ALL AGENTS                */
+   /********************************************/
+   //turn on directions with read/write
+
+   //READ
+   assign read_out             = request_cvre & mesh_read_cvre;
+   
+   //WRITE
+   assign write_out            = request_cvre & mesh_write_cvre;
+   
+   //Mesh transaction
+   assign dst_addr_out[AW-1:0] = mesh_dst_addr_cvre[AW-1:0];
+   assign src_addr_out[AW-1:0] = mesh_src_addr_cvre[AW-1:0];
+   assign data_out[MDW-1:0]    = mesh_data_cvre[MDW-1:0];   
+   assign datamode_out[1:0]    = mesh_datamode_cvre[1:0];
+   assign ctrlmode_out[3:0]    = mesh_ctrlmode_cvre[3:0];
+
+
+endmodule // link_rxi_router
+
+     //#############################################################
+//# This block is a receiver of the write transactions only
+//# Write transactions will enter the chip on emesh and mesh
+//# only but not on the rdmesh
+//#############################################################
+module link_rxi_wr(/*AUTOARG*/
+   // Outputs
+   rxi_wr_wait, c0_emesh_frame_out, c0_emesh_tran_out,
+   c3_emesh_frame_out, c3_emesh_tran_out, c0_mesh_access_out,
+   c0_mesh_write_out, c0_mesh_dstaddr_out, c0_mesh_srcaddr_out,
+   c0_mesh_data_out, c0_mesh_datamode_out, c0_mesh_ctrlmode_out,
+   c3_mesh_access_out, c3_mesh_write_out, c3_mesh_dstaddr_out,
+   c3_mesh_srcaddr_out, c3_mesh_data_out, c3_mesh_datamode_out,
+   c3_mesh_ctrlmode_out,
+   // Inputs
+   reset, ext_yid_k, ext_xid_k, vertical_k, who_am_i, cfg_extcomp_dis,
+   rxi_data, rxi_lclk, rxi_frame, c0_clk_in, c3_clk_in,
+   c0_emesh_wait_in, c3_emesh_wait_in, c0_mesh_wait_in,
+   c3_mesh_wait_in
+   );
+
+   parameter LW   = `CFG_LW;//lvds tranceiver pairs per side
+   parameter DW   = `CFG_DW;//data width  
+   parameter AW   = `CFG_AW;//address width
+\t\t     
+   // #########
+   // # Inputs
+   // #########
+
+   input             reset;     // reset input
+   input [3:0] \t     ext_yid_k; // external y-id 
+   input [3:0] \t     ext_xid_k; // external x-id
+   input             vertical_k;// specifies if block is vertical or horizontal
+   input [3:0] \t     who_am_i;  // specifies what link is that (north,east,south,west)
+   input \t     cfg_extcomp_dis;// Disable external coordinates comparison
+                                     // Every input transaction is received by the chip
+   input [LW-1:0]    rxi_data;  // Byte word
+   input             rxi_lclk;  // receive clock (adjusted to the frame/data)
+   input             rxi_frame; // indicates new transmission
+
+   // # Sync clocks
+   input             c0_clk_in; // clock of the core
+   input             c3_clk_in; // clock of the core
+
+   // # Wait indicators
+   input             c0_emesh_wait_in;  // wait
+   input             c3_emesh_wait_in;  // wait
+   input \t     c0_mesh_wait_in;   // wait
+   input \t     c3_mesh_wait_in;   // wait
+
+   // ##########
+   // # Outputs
+   // ##########
+
+   output \t     rxi_wr_wait;  //wait indicator for write transactions
+
+   //# EMESH (write transactions with the off chip destination)
+   output            c0_emesh_frame_out; // transaction frame
+   output [2*LW-1:0] c0_emesh_tran_out;  // serialized transaction
+   output            c3_emesh_frame_out; // transaction frame
+   output [2*LW-1:0] c3_emesh_tran_out;  // serialized transaction
+   // # MESH (write transactions internal and external corners)
+   // # core0 
+   output \t     c0_mesh_access_out;  // access control to the mesh
+   output \t     c0_mesh_write_out;   // write control to the mesh
+   output [AW-1:0]   c0_mesh_dstaddr_out; // destination address to the mesh
+   output [AW-1:0]   c0_mesh_srcaddr_out; // source address to the mesh
+   output [DW-1:0]   c0_mesh_data_out;    // data to the mesh
+   output [1:0]      c0_mesh_datamode_out;// data mode to the mesh 
+   output [3:0]      c0_mesh_ctrlmode_out;// ctrl mode to the mesh
+   // # core3 
+   output \t     c3_mesh_access_out;  // access control to the mesh
+   output \t     c3_mesh_write_out;   // write control to the mesh
+   output [AW-1:0]   c3_mesh_dstaddr_out; // destination address to the mesh
+   output [AW-1:0]   c3_mesh_srcaddr_out; // source address to the mesh
+   output [DW-1:0]   c3_mesh_data_out;    // data to the mesh
+   output [1:0]      c3_mesh_datamode_out;// data mode to the mesh 
+   output [3:0]      c3_mesh_ctrlmode_out;// ctrl mode to the mesh
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\tc0_fifo_access;\t\t// From link_rxi_buffer of link_rxi_buffer.v
+   wire\t\t\tc0_fifo_full_rlc;\t// From c0_link_rxi_double_channel of link_rxi_double_channel.v
+   wire\t\t\tc1_fifo_access;\t\t// From link_rxi_buffer of link_rxi_buffer.v
+   wire\t\t\tc2_fifo_access;\t\t// From link_rxi_buffer of link_rxi_buffer.v
+   wire\t\t\tc3_fifo_access;\t\t// From link_rxi_buffer of link_rxi_buffer.v
+   wire\t\t\tc3_fifo_full_rlc;\t// From c3_link_rxi_double_channel of link_rxi_double_channel.v
+   wire [14*LW-1:0]\trxi_assembled_tran_rlc;\t// From link_rxi_buffer of link_rxi_buffer.v
+   // End of automatics
+
+   //##########
+   //# WIRES
+   //##########
+
+   wire    c0_fifo_access_rlc;
+   wire    c3_fifo_access_rlc;
+
+
+   // ################################
+   // # Receiver buffer instantiation
+   // ################################
+
+   /*link_rxi_buffer AUTO_TEMPLATE (.rxi_rd             (1\'b0),
+                                    .rxi_wait\t\t(rxi_wr_wait),
+                                    .reset\t\t(reset),
+                                    .vertical_k\t\t(vertical_k),
+                                    .ext_yid_k\t\t(ext_yid_k[3:0]),
+                                    .ext_xid_k\t\t(ext_xid_k[3:0]),
+                                    .rxi_data\t\t(rxi_data[LW-1:0]),
+\t\t\t\t    .rxi_lclk\t\t(rxi_lclk),
+\t\t\t\t    .rxi_frame\t\t(rxi_frame),
+                                    .rxi_\\(.*\\)_access  (\\1_fifo_access),
+                                    .\\(.*\\)             (\\1_rlc[]),
+\t\t\t\t    .cfg_extcomp_dis\t(cfg_extcomp_dis), 
+\t\t\t\t    .c1_fifo_full\t(1\'b0), 
+\t\t\t\t    .c2_fifo_full\t(1\'b0), 
+                                        );
+    */
+   link_rxi_buffer link_rxi_buffer(/*AUTOINST*/
+\t\t\t\t   // Outputs
+\t\t\t\t   .rxi_wait\t\t(rxi_wr_wait),\t // Templated
+\t\t\t\t   .rxi_assembled_tran\t(rxi_assembled_tran_rlc[14*LW-1:0]), // Templated
+\t\t\t\t   .rxi_c0_access\t(c0_fifo_access), // Templated
+\t\t\t\t   .rxi_c1_access\t(c1_fifo_access), // Templated
+\t\t\t\t   .rxi_c2_access\t(c2_fifo_access), // Templated
+\t\t\t\t   .rxi_c3_access\t(c3_fifo_access), // Templated
+\t\t\t\t   // Inputs
+\t\t\t\t   .reset\t\t(reset),\t // Templated
+\t\t\t\t   .vertical_k\t\t(vertical_k),\t // Templated
+\t\t\t\t   .ext_yid_k\t\t(ext_yid_k[3:0]), // Templated
+\t\t\t\t   .ext_xid_k\t\t(ext_xid_k[3:0]), // Templated
+\t\t\t\t   .rxi_data\t\t(rxi_data[LW-1:0]), // Templated
+\t\t\t\t   .rxi_lclk\t\t(rxi_lclk),\t // Templated
+\t\t\t\t   .rxi_frame\t\t(rxi_frame),\t // Templated
+\t\t\t\t   .rxi_rd\t\t(1\'b0),\t\t // Templated
+\t\t\t\t   .cfg_extcomp_dis\t(cfg_extcomp_dis), // Templated
+\t\t\t\t   .c0_fifo_full\t(c0_fifo_full_rlc), // Templated
+\t\t\t\t   .c1_fifo_full\t(1\'b0),\t\t // Templated
+\t\t\t\t   .c2_fifo_full\t(1\'b0),\t\t // Templated
+\t\t\t\t   .c3_fifo_full\t(c3_fifo_full_rlc)); // Templated
+
+   // ################################################
+   // # Receiver channels instantiation  
+   // ################################################
+
+   //# All the received transactions will be issued on channel0 or channel3 only
+   assign c0_fifo_access_rlc = c0_fifo_access | c1_fifo_access;
+   assign c3_fifo_access_rlc = c2_fifo_access | c3_fifo_access;
+
+   /*link_rxi_double_channel AUTO_TEMPLATE (
+                       .fifo_full_rlc   (@""(substring vl-cell-name 0 2)""_fifo_full_rlc),
+                       .\\(.*\\)_out      (@""(substring vl-cell-name 0 2)""_\\1_out[]),
+                       .emesh_wait_in   (@""(substring vl-cell-name 0 2)""_emesh_wait_in),
+                       .mesh_\\(.*\\)     (@""(substring vl-cell-name 0 2)""_mesh_\\1[]),
+\t\t       .cclk\t        (@""(substring vl-cell-name 0 2)""_clk_in),
+                       .cclk_en         (1\'b1),
+                       .fifo_access_rlc (@""(substring vl-cell-name 0 2)""_fifo_access_rlc),
+                       .mesh_fifo_access_rlc (mesh_fifo_access_rlc),
+                                   );
+    */
+
+   //# channel 0 (emesh + mesh + mesh for multicast)
+   link_rxi_double_channel c0_link_rxi_double_channel(/*AUTOINST*/
+\t\t\t\t\t\t      // Outputs
+\t\t\t\t\t\t      .fifo_full_rlc\t(c0_fifo_full_rlc), // Templated
+\t\t\t\t\t\t      .emesh_tran_out\t(c0_emesh_tran_out[2*LW-1:0]), // Templated
+\t\t\t\t\t\t      .emesh_frame_out\t(c0_emesh_frame_out), // Templated
+\t\t\t\t\t\t      .mesh_access_out\t(c0_mesh_access_out), // Templated
+\t\t\t\t\t\t      .mesh_write_out\t(c0_mesh_write_out), // Templated
+\t\t\t\t\t\t      .mesh_dstaddr_out\t(c0_mesh_dstaddr_out[AW-1:0]), // Templated
+\t\t\t\t\t\t      .mesh_srcaddr_out\t(c0_mesh_srcaddr_out[AW-1:0]), // Templated
+\t\t\t\t\t\t      .mesh_data_out\t(c0_mesh_data_out[DW-1:0]), // Templated
+\t\t\t\t\t\t      .mesh_datamode_out(c0_mesh_datamode_out[1:0]), // Templated
+\t\t\t\t\t\t      .mesh_ctrlmode_out(c0_mesh_ctrlmode_out[3:0]), // Templated
+\t\t\t\t\t\t      // Inputs
+\t\t\t\t\t\t      .reset\t\t(reset),
+\t\t\t\t\t\t      .cclk\t\t(c0_clk_in),\t // Templated
+\t\t\t\t\t\t      .cclk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t      .ext_yid_k\t(ext_yid_k[3:0]),
+\t\t\t\t\t\t      .ext_xid_k\t(ext_xid_k[3:0]),
+\t\t\t\t\t\t      .rxi_lclk\t\t(rxi_lclk),
+\t\t\t\t\t\t      .who_am_i\t\t(who_am_i[3:0]),
+\t\t\t\t\t\t      .cfg_extcomp_dis\t(cfg_extcomp_dis),
+\t\t\t\t\t\t      .rxi_assembled_tran_rlc(rxi_assembled_tran_rlc[14*LW-1:0]),
+\t\t\t\t\t\t      .fifo_access_rlc\t(c0_fifo_access_rlc), // Templated
+\t\t\t\t\t\t      .emesh_wait_in\t(c0_emesh_wait_in), // Templated
+\t\t\t\t\t\t      .mesh_wait_in\t(c0_mesh_wait_in)); // Templated
+
+   //# channel 3 (emesh + mesh)
+   link_rxi_double_channel c3_link_rxi_double_channel(/*AUTOINST*/
+\t\t\t\t\t\t      // Outputs
+\t\t\t\t\t\t      .fifo_full_rlc\t(c3_fifo_full_rlc), // Templated
+\t\t\t\t\t\t      .emesh_tran_out\t(c3_emesh_tran_out[2*LW-1:0]), // Templated
+\t\t\t\t\t\t      .emesh_frame_out\t(c3_emesh_frame_out), // Templated
+\t\t\t\t\t\t      .mesh_access_out\t(c3_mesh_access_out), // Templated
+\t\t\t\t\t\t      .mesh_write_out\t(c3_mesh_write_out), // Templated
+\t\t\t\t\t\t      .mesh_dstaddr_out\t(c3_mesh_dstaddr_out[AW-1:0]), // Templated
+\t\t\t\t\t\t      .mesh_srcaddr_out\t(c3_mesh_srcaddr_out[AW-1:0]), // Templated
+\t\t\t\t\t\t      .mesh_data_out\t(c3_mesh_data_out[DW-1:0]), // Templated
+\t\t\t\t\t\t      .mesh_datamode_out(c3_mesh_datamode_out[1:0]), // Templated
+\t\t\t\t\t\t      .mesh_ctrlmode_out(c3_mesh_ctrlmode_out[3:0]), // Templated
+\t\t\t\t\t\t      // Inputs
+\t\t\t\t\t\t      .reset\t\t(reset),
+\t\t\t\t\t\t      .cclk\t\t(c3_clk_in),\t // Templated
+\t\t\t\t\t\t      .cclk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t      .ext_yid_k\t(ext_yid_k[3:0]),
+\t\t\t\t\t\t      .ext_xid_k\t(ext_xid_k[3:0]),
+\t\t\t\t\t\t      .rxi_lclk\t\t(rxi_lclk),
+\t\t\t\t\t\t      .who_am_i\t\t(who_am_i[3:0]),
+\t\t\t\t\t\t      .cfg_extcomp_dis\t(cfg_extcomp_dis),
+\t\t\t\t\t\t      .rxi_assembled_tran_rlc(rxi_assembled_tran_rlc[14*LW-1:0]),
+\t\t\t\t\t\t      .fifo_access_rlc\t(c3_fifo_access_rlc), // Templated
+\t\t\t\t\t\t      .emesh_wait_in\t(c3_emesh_wait_in), // Templated
+\t\t\t\t\t\t      .mesh_wait_in\t(c3_mesh_wait_in)); // Templated
+
+
+endmodule // link_rxi_wr
+module link_transmitter (/*AUTOARG*/
+   // Outputs
+   txo_data, txo_lclk90, txo_frame, c0_emesh_wait_out,
+   c1_emesh_wait_out, c2_emesh_wait_out, c3_emesh_wait_out,
+   c0_rdmesh_wait_out, c1_rdmesh_wait_out, c2_rdmesh_wait_out,
+   c3_rdmesh_wait_out, c0_mesh_wait_out, c3_mesh_wait_out,
+   // Inputs
+   c3_emesh_tran_in, c3_emesh_frame_in, c2_emesh_tran_in,
+   c2_emesh_frame_in, c1_emesh_tran_in, c1_emesh_frame_in,
+   c0_emesh_tran_in, c0_emesh_frame_in, reset, ext_yid_k, ext_xid_k,
+   who_am_i, txo_cfg_reg, txo_wr_wait, txo_rd_wait, c0_clk_in,
+   c1_clk_in, c2_clk_in, c3_clk_in, c0_mesh_access_in,
+   c0_mesh_write_in, c0_mesh_dstaddr_in, c0_mesh_srcaddr_in,
+   c0_mesh_data_in, c0_mesh_datamode_in, c0_mesh_ctrlmode_in,
+   c3_mesh_access_in, c3_mesh_write_in, c3_mesh_dstaddr_in,
+   c3_mesh_srcaddr_in, c3_mesh_data_in, c3_mesh_datamode_in,
+   c3_mesh_ctrlmode_in
+   );
+
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+   parameter AW   = `CFG_AW  ;//address width
+   parameter DW   = `CFG_DW  ;//data width  
+   
+   // #########
+   // # Inputs
+   // #########
+
+   input            reset;
+   input [3:0] \t    ext_yid_k; //external y-id 
+   input [3:0] \t    ext_xid_k; //external x-id
+   input [3:0] \t    who_am_i;  // specifies what link is that (north,east,south,west)
+   
+   // # Configuration registers
+   input [5:0] \t    txo_cfg_reg; //Clock divider configuration on bits 3-0,
+                                  //Bursting disable control on bit 4
+                                  //Multicast disable control on bit 5
+   // # from io
+   input \t    txo_wr_wait; //wait indicator for write transactions
+   input \t    txo_rd_wait; //wait indicator for read transactions
+
+   // # Clocks
+   input \t    c0_clk_in;         // clock of the core  
+   input \t    c1_clk_in;         // clock of the core  
+   input \t    c2_clk_in;         // clock of the core  
+   input \t    c3_clk_in;         // clock of the core  
+  
+   // # MESH 
+   // # core0 (external corners and multicast)
+   input \t    c0_mesh_access_in;  // access control from the mesh
+   input \t    c0_mesh_write_in;   // write control from the mesh
+   input [AW-1:0]   c0_mesh_dstaddr_in; // destination address from the mesh
+   input [AW-1:0]   c0_mesh_srcaddr_in; // source address from the mesh
+   input [DW-1:0]   c0_mesh_data_in;    // data from the mesh
+   input [1:0] \t    c0_mesh_datamode_in;// data mode from the mesh 
+   input [3:0] \t    c0_mesh_ctrlmode_in;// ctrl mode from the mesh
+   // # core3 (external corners only)
+   input \t    c3_mesh_access_in;  // access control from the mesh
+   input \t    c3_mesh_write_in;   // write control from the mesh
+   input [AW-1:0]   c3_mesh_dstaddr_in; // destination address from the mesh
+   input [AW-1:0]   c3_mesh_srcaddr_in; // source address from the mesh
+   input [DW-1:0]   c3_mesh_data_in;    // data from the mesh
+   input [1:0] \t    c3_mesh_datamode_in;// data mode from the mesh 
+   input [3:0] \t    c3_mesh_ctrlmode_in;// ctrl mode from the mesh
+
+   // ##############
+   // # Outputs
+   // ##############
+
+   output  [LW-1:0]  txo_data;      //Byte word
+   output            txo_lclk90;    //transmit clock (adjusted to the frame/data)
+   output            txo_frame;     //indicates new transmission 
+  
+   output \t     c0_emesh_wait_out; // wait to the emesh   
+   output \t     c1_emesh_wait_out; // wait to the emesh   
+   output \t     c2_emesh_wait_out; // wait to the emesh   
+   output \t     c3_emesh_wait_out; // wait to the emesh   
+
+   output \t     c0_rdmesh_wait_out; // wait to the rdmesh   
+   output \t     c1_rdmesh_wait_out; // wait to the rdmesh   
+   output \t     c2_rdmesh_wait_out; // wait to the rdmesh   
+   output \t     c3_rdmesh_wait_out; // wait to the rdmesh   
+
+   output \t     c0_mesh_wait_out;  // wait to the mesh 
+   output \t     c3_mesh_wait_out;  // wait to the mesh 
+
+   // ##########
+   // # WIRES
+   // ##########
+
+   wire \t     txo_lclk;  //transmit clock to be used internally
+   wire \t     txo_lclk90;//transmit clock (adjusted to the frame/data)
+
+   /*AUTOINPUT*/
+   // Beginning of automatic inputs (from unused autoinst inputs)
+   input\t\tc0_emesh_frame_in;\t// To link_txo_wr of link_txo_wr.v
+   input [2*LW-1:0]\tc0_emesh_tran_in;\t// To link_txo_wr of link_txo_wr.v
+   input\t\tc1_emesh_frame_in;\t// To link_txo_wr of link_txo_wr.v
+   input [2*LW-1:0]\tc1_emesh_tran_in;\t// To link_txo_wr of link_txo_wr.v
+   input\t\tc2_emesh_frame_in;\t// To link_txo_wr of link_txo_wr.v
+   input [2*LW-1:0]\tc2_emesh_tran_in;\t// To link_txo_wr of link_txo_wr.v
+   input\t\tc3_emesh_frame_in;\t// To link_txo_wr of link_txo_wr.v
+   input [2*LW-1:0]\tc3_emesh_tran_in;\t// To link_txo_wr of link_txo_wr.v
+   // End of automatics
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [LW-1:0]\ttxo_wr_data_even;\t// From link_txo_wr of link_txo_wr.v
+   wire [LW-1:0]\ttxo_wr_data_odd;\t// From link_txo_wr of link_txo_wr.v
+   wire\t\t\ttxo_wr_frame;\t\t// From link_txo_wr of link_txo_wr.v
+   wire\t\t\ttxo_wr_launch_req_tlc;\t// From link_txo_wr of link_txo_wr.v
+   wire\t\t\ttxo_wr_rotate_dis;\t// From link_txo_wr of link_txo_wr.v
+   // End of automatics
+   
+
+   // ##############################
+   // # Clock divider instantiation
+   // ##############################
+
+   //# Since the logic of the fifo of the transmitter\'s channel 
+   //# assumes txo_lck and cclk to be asynchronous clocks, we don\'t
+   //# mind to have txo_lclk be generated out of any of the clk_in
+   //# clocks even though they are inverted relative to each other.
+   //# c1_clk_in is selected because of the physical implementation
+   //# considerations.
+   e16_clock_divider clock_divider (.clk_out\t(txo_lclk),
+\t\t\t\t.clk_out90      (txo_lclk90),
+\t\t\t\t.clk_in\t\t(c1_clk_in),
+\t\t\t\t.reset\t\t(reset),
+\t\t\t\t.div_cfg\t(4\'b0)
+\t\t\t\t);
+
+   //########################
+   //# Transmitter interface 
+   //########################
+
+   link_txo_interface link_txo_interface(
+\t\t\t\t\t // Outputs
+\t\t\t\t\t .txo_data\t\t(txo_data[LW-1:0]),
+\t\t\t\t\t .txo_frame\t\t(txo_frame),
+\t\t\t\t\t .txo_wr_wait_int\t(txo_wr_wait_int),
+\t\t\t\t\t .txo_rd_wait_int\t(txo_rd_wait_int),
+\t\t\t\t\t // Inputs
+\t\t\t\t\t .txo_lclk\t\t(txo_lclk),
+\t\t\t\t\t .reset\t\t\t(reset),
+\t\t\t\t\t .txo_wr_data_even\t(txo_wr_data_even[LW-1:0]),
+\t\t\t\t\t .txo_wr_data_odd\t(txo_wr_data_odd[LW-1:0]),
+\t\t\t\t\t .txo_wr_frame\t\t(txo_wr_frame),
+\t\t\t\t\t .txo_wr_launch_req_tlc\t(txo_wr_launch_req_tlc),
+\t\t\t\t\t .txo_wr_rotate_dis\t(txo_wr_rotate_dis),
+\t\t\t\t\t .txo_rd_data_even\t(8\'d0),
+\t\t\t\t\t .txo_rd_data_odd\t(8\'d0),
+\t\t\t\t\t .txo_rd_frame\t\t(1\'d0),
+\t\t\t\t\t .txo_rd_launch_req_tlc\t(1\'d0),
+\t\t\t\t\t .txo_rd_rotate_dis\t(1\'d0)
+\t\t\t\t\t ); 
+   
+   //#################################
+   //# Write Transactions Transmitter
+   //#################################
+
+   link_txo_wr link_txo_wr(.cfg_burst_dis\t(txo_cfg_reg[4]),
+\t\t\t   .cfg_multicast_dis\t(txo_cfg_reg[5]),
+\t\t\t   .txo_wr_wait_int\t(txo_wr_wait_int),
+\t\t\t   /*AUTOINST*/
+\t\t\t   // Outputs
+\t\t\t   .txo_wr_data_even\t(txo_wr_data_even[LW-1:0]),
+\t\t\t   .txo_wr_data_odd\t(txo_wr_data_odd[LW-1:0]),
+\t\t\t   .txo_wr_frame\t(txo_wr_frame),
+\t\t\t   .txo_wr_launch_req_tlc(txo_wr_launch_req_tlc),
+\t\t\t   .txo_wr_rotate_dis\t(txo_wr_rotate_dis),
+\t\t\t   .c0_emesh_wait_out\t(c0_emesh_wait_out),
+\t\t\t   .c1_emesh_wait_out\t(c1_emesh_wait_out),
+\t\t\t   .c2_emesh_wait_out\t(c2_emesh_wait_out),
+\t\t\t   .c3_emesh_wait_out\t(c3_emesh_wait_out),
+\t\t\t   .c0_mesh_wait_out\t(c0_mesh_wait_out),
+\t\t\t   .c3_mesh_wait_out\t(c3_mesh_wait_out),
+\t\t\t   // Inputs
+\t\t\t   .txo_lclk\t\t(txo_lclk),
+\t\t\t   .reset\t\t(reset),
+\t\t\t   .ext_yid_k\t\t(ext_yid_k[3:0]),
+\t\t\t   .ext_xid_k\t\t(ext_xid_k[3:0]),
+\t\t\t   .who_am_i\t\t(who_am_i[3:0]),
+\t\t\t   .txo_wr_wait\t\t(txo_wr_wait),
+\t\t\t   .c0_clk_in\t\t(c0_clk_in),
+\t\t\t   .c1_clk_in\t\t(c1_clk_in),
+\t\t\t   .c2_clk_in\t\t(c2_clk_in),
+\t\t\t   .c3_clk_in\t\t(c3_clk_in),
+\t\t\t   .c0_emesh_tran_in\t(c0_emesh_tran_in[2*LW-1:0]),
+\t\t\t   .c0_emesh_frame_in\t(c0_emesh_frame_in),
+\t\t\t   .c1_emesh_tran_in\t(c1_emesh_tran_in[2*LW-1:0]),
+\t\t\t   .c1_emesh_frame_in\t(c1_emesh_frame_in),
+\t\t\t   .c2_emesh_tran_in\t(c2_emesh_tran_in[2*LW-1:0]),
+\t\t\t   .c2_emesh_frame_in\t(c2_emesh_frame_in),
+\t\t\t   .c3_emesh_tran_in\t(c3_emesh_tran_in[2*LW-1:0]),
+\t\t\t   .c3_emesh_frame_in\t(c3_emesh_frame_in),
+\t\t\t   .c0_mesh_access_in\t(c0_mesh_access_in),
+\t\t\t   .c0_mesh_write_in\t(c0_mesh_write_in),
+\t\t\t   .c0_mesh_dstaddr_in\t(c0_mesh_dstaddr_in[AW-1:0]),
+\t\t\t   .c0_mesh_srcaddr_in\t(c0_mesh_srcaddr_in[AW-1:0]),
+\t\t\t   .c0_mesh_data_in\t(c0_mesh_data_in[DW-1:0]),
+\t\t\t   .c0_mesh_datamode_in\t(c0_mesh_datamode_in[1:0]),
+\t\t\t   .c0_mesh_ctrlmode_in\t(c0_mesh_ctrlmode_in[3:0]),
+\t\t\t   .c3_mesh_access_in\t(c3_mesh_access_in),
+\t\t\t   .c3_mesh_write_in\t(c3_mesh_write_in),
+\t\t\t   .c3_mesh_dstaddr_in\t(c3_mesh_dstaddr_in[AW-1:0]),
+\t\t\t   .c3_mesh_srcaddr_in\t(c3_mesh_srcaddr_in[AW-1:0]),
+\t\t\t   .c3_mesh_data_in\t(c3_mesh_data_in[DW-1:0]),
+\t\t\t   .c3_mesh_datamode_in\t(c3_mesh_datamode_in[1:0]),
+\t\t\t   .c3_mesh_ctrlmode_in\t(c3_mesh_ctrlmode_in[3:0]));
+
+
+endmodule // link_transmitter
+module link_txo_arbiter(/*AUTOARG*/
+   // Outputs
+   txo_launch_req_tlc, txo_rotate_dis_tlc, c0_txo_launch_ack_tlc,
+   c1_txo_launch_ack_tlc, c2_txo_launch_ack_tlc,
+   c3_txo_launch_ack_tlc,
+   // Inputs
+   txo_lclk, reset, txo_wait, txo_wait_int, c0_txo_launch_req_tlc,
+   c0_txo_rotate_dis, c1_txo_launch_req_tlc, c1_txo_rotate_dis,
+   c2_txo_launch_req_tlc, c2_txo_rotate_dis, c3_txo_launch_req_tlc,
+   c3_txo_rotate_dis
+   );
+
+
+   // ##########
+   // # Inputs
+   // ##########
+
+   input       txo_lclk;   
+   input       reset;
+   input       txo_wait; // Wait from the receiver (we have to finish current transmission)
+   input       txo_wait_int; // Wait from the txo_interface (have to stall immediately)
+
+   //Channel 0
+   input       c0_txo_launch_req_tlc; // Launch request
+   input       c0_txo_rotate_dis;     // Arbiter\'s rotate disable 
+   //Channel 1
+   input       c1_txo_launch_req_tlc; // Launch request
+   input       c1_txo_rotate_dis;     // Arbiter\'s rotate disable 
+   //Channel 2
+   input       c2_txo_launch_req_tlc; // Launch request
+   input       c2_txo_rotate_dis;     // Arbiter\'s rotate disable 
+   //Channel 3
+   input       c3_txo_launch_req_tlc; // Launch request
+   input       c3_txo_rotate_dis;     // Arbiter\'s rotate disable 
+
+   // ##########
+   // # Outputs
+   // ##########
+   // to the txo_interface
+   output      txo_launch_req_tlc;
+   output      txo_rotate_dis_tlc;
+   // to the channels
+   output      c0_txo_launch_ack_tlc;
+   output      c1_txo_launch_ack_tlc;
+   output      c2_txo_launch_ack_tlc;
+   output      c3_txo_launch_ack_tlc;
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   // #######
+   // # REGS
+   // #######
+
+   reg [3:0]   grants_reg;
+
+   // ############
+   // # WIRES
+   // ############
+
+   wire [3:0]  txo_rotate_dis;
+   wire        en_arbitration;
+   wire        en_rotate;
+
+   wire [3:0]   grants;             //one-hot grants signals
+   wire [3:0] \trequests_unmasked;  //unmasked (original) requests
+   wire [3:0]   requests;           //requests
+   wire \ttxo_wait_tlc;
+
+   //############################
+   //# txo_wait synchronization
+   //############################
+   e16_synchronizer #(.DW(1)) synchronizer(.out\t(txo_wait_tlc),
+\t\t\t               .in\t(txo_wait),
+\t\t\t\t       .clk\t(txo_lclk),
+\t\t\t\t       .reset\t(reset));
+
+   //#############################################################
+   //# creating requests information for the additional
+   //# arbitration which is performed in the txo_interface
+   //#############################################################
+   assign txo_launch_req_tlc = c0_txo_launch_req_tlc | c1_txo_launch_req_tlc |
+\t\t\t       c2_txo_launch_req_tlc | c3_txo_launch_req_tlc;
+
+   assign txo_rotate_dis_tlc = c0_txo_rotate_dis | c1_txo_rotate_dis |
+\t\t\t       c2_txo_rotate_dis | c3_txo_rotate_dis;
+
+   //###########################################
+   //# Rotation mechanism and requests creation
+   //###########################################
+   always @ (posedge txo_lclk or posedge reset)
+     if(reset)
+       grants_reg[3:0] <= 4\'b0000;
+     else
+       grants_reg[3:0] <= grants[3:0];
+
+   assign txo_rotate_dis[3:0] = {c3_txo_rotate_dis,
+\t\t\t\t c2_txo_rotate_dis,
+\t\t\t\t c1_txo_rotate_dis,
+\t\t\t\t c0_txo_rotate_dis};
+
+   assign en_rotate = ~(|(grants_reg[3:0] & txo_rotate_dis[3:0]));
+
+   assign en_arbitration = ~txo_wait_tlc | (|(txo_rotate_dis[3:0]));
+
+   assign requests_unmasked[3:0] = {c3_txo_launch_req_tlc,
+                                    c2_txo_launch_req_tlc,
+                                    c1_txo_launch_req_tlc,
+                                    c0_txo_launch_req_tlc};
+   
+   assign requests[3:0] = {(4){en_arbitration}} & 
+\t\t\t  requests_unmasked[3:0] & (grants_reg[3:0] | {(4){en_rotate}});
+
+   //############
+   //# Grants
+   //############
+   assign c3_txo_launch_ack_tlc   = grants[3] & ~txo_wait_int;
+   assign c2_txo_launch_ack_tlc   = grants[2] & ~txo_wait_int;
+   assign c1_txo_launch_ack_tlc   = grants[1] & ~txo_wait_int;
+   assign c0_txo_launch_ack_tlc   = grants[0] & ~txo_wait_int;
+
+   //######################################
+   //# Round-Robin Arbiter Instantiation
+   //######################################
+   /*e16_arbiter_roundrobin AUTO_TEMPLATE (.clk\t   (txo_lclk),
+                                       .clk_en\t   (1\'b1),
+                                       .grants\t   (grants[3:0]),
+                                       .requests   (requests[3:0]),
+                                       );
+    */ 
+   e16_arbiter_roundrobin #(.ARW(4)) arbiter_roundrobin(/*AUTOINST*/
+\t\t\t\t\t\t    // Outputs
+\t\t\t\t\t\t    .grants\t\t(grants[3:0]),\t // Templated
+\t\t\t\t\t\t    // Inputs
+\t\t\t\t\t\t    .clk\t\t(txo_lclk),\t // Templated
+\t\t\t\t\t\t    .clk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .reset\t\t(reset),
+\t\t\t\t\t\t    .en_rotate\t\t(en_rotate),
+\t\t\t\t\t\t    .requests\t\t(requests[3:0])); // Templated
+
+endmodule // link_txo_arbiter
+module link_txo_buffer(/*AUTOARG*/
+   // Outputs
+   txo_data_even, txo_data_odd, txo_frame,
+   // Inputs
+   c0_tran_frame_tlc, c0_tran_byte_even_tlc, c0_tran_byte_odd_tlc,
+   c1_tran_frame_tlc, c1_tran_byte_even_tlc, c1_tran_byte_odd_tlc,
+   c2_tran_frame_tlc, c2_tran_byte_even_tlc, c2_tran_byte_odd_tlc,
+   c3_tran_frame_tlc, c3_tran_byte_even_tlc, c3_tran_byte_odd_tlc
+   );
+
+   parameter LW  = `CFG_LW;
+   
+   // #########
+   // # Inputs
+   // #########
+
+   //# from channel 0
+   input          c0_tran_frame_tlc;      // Frame of the transaction
+   input [LW-1:0] c0_tran_byte_even_tlc;  // Even byte of the transaction
+   input [LW-1:0] c0_tran_byte_odd_tlc;   // Odd byte of the transaction
+   //# from channel 1
+   input          c1_tran_frame_tlc;      // Frame of the transaction
+   input [LW-1:0] c1_tran_byte_even_tlc;  // Even byte of the transaction
+   input [LW-1:0] c1_tran_byte_odd_tlc;   // Odd byte of the transaction
+   //# from channel 2
+   input          c2_tran_frame_tlc;      // Frame of the transaction
+   input [LW-1:0] c2_tran_byte_even_tlc;  // Even byte of the transaction
+   input [LW-1:0] c2_tran_byte_odd_tlc;   // Odd byte of the transaction
+   //# from channel 3
+   input          c3_tran_frame_tlc;      // Frame of the transaction
+   input [LW-1:0] c3_tran_byte_even_tlc;  // Even byte of the transaction
+   input [LW-1:0] c3_tran_byte_odd_tlc;   // Odd byte of the transaction
+
+   // ##########
+   // # Outputs
+   // ##########
+ 
+   output [LW-1:0]  txo_data_even; //Even byte word
+   output [LW-1:0]  txo_data_odd;  //Odd byte word
+   output \t    txo_frame;     //indicates new transmission 
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   // ##########
+   // # Regs
+   // ##########
+   
+   // ##########
+   // # Wires
+   // ##########
+
+   wire \t txo_frame;     // selected frame of the transmission
+   wire [LW-1:0] txo_data_even; // selected even bytes of the transmission
+   wire [LW-1:0] txo_data_odd;  // selected odd bytes of the transmission
+
+   //###########################################
+   //#           Transaction mux
+   //# The ""and"" part of the ""and-or"" mux is
+   //# implemented in the link channels blocks  
+   //# therefore here we are good with ""or"" only
+   //###########################################
+
+   assign txo_frame = c0_tran_frame_tlc;
+ 
+   assign txo_data_even[LW-1:0] = c0_tran_byte_even_tlc[LW-1:0];
+   
+   assign txo_data_odd[LW-1:0] = c0_tran_byte_odd_tlc[LW-1:0];
+   
+
+endmodule // link_txo_buffer
+
+
+
+\t\t\t
+//#########################################################
+//# This block is a single channel of the link transmitter
+//# mechanism.
+//#
+//# The input transaction of this block is of the fixed size,  
+//# while the output transaction has an option
+//# of the bursting where data of the new transaction
+//# is sent without the address. In such a case the
+//# address of the transaction will be determined in
+//# the receiver according to the address of the
+//# previous transaction.
+//#
+//#          TXO-RXI TRANSMISSION PROTOCOL
+//#         ###############################
+//#        ----      ----      ----      ----      ----      --
+//# LCLK _|    |____|    |____|    |____|    |____|    |____| 
+//#
+//#              -------------------------------------
+//# FRAME ______/
+//#              ----- ----- ----- ----- -----
+//# DATA  XXXXXXX  0  X  1  X  2  X  3  X  4  X .....
+//#              ----- ----- ----- ----- -----
+//#
+//# The byte sampled on the first rising edge of the LCLK following 
+//# the ""low-to-high"" change of the FRAME signal (byte0) will determine 
+//# the type of the transmitted data according to the following
+//# encoding scheme:
+//#    
+//#      byte0          | transaction type
+//#   ----------------- | ----------------
+//#  8\'b??_??_?0_<cid>  | New transaction with incremental bursting address
+//#  8\'b??_??_?1_<cid>  | New transaction with the same bursting address
+//#
+//#  cid[1:0] - channel id (for debugging usage only for now)
+//#
+//#  New transaction structure:
+//#  'b'-------------------------
+//#   byte1  -> ctrlmode[3:0],dstaddr[31:28]
+//#   byte2  -> dstaddr[27:20]
+//#   byte3  -> dstaddr[19:12]
+//#   byte4  -> dstaddr[11:4]
+//#   byte5  -> dstaddr[3:0],datamode[1:0],write,access
+//#   byte6  -> data[31:24] (or srcaddr[31:24] if read transaction)
+//#   byte7  -> data[23:16] (or srcaddr[23:16] if read transaction)
+//#   byte8  -> data[15:8]  (or srcaddr[15:8]  if read transaction)
+//#  *byte9  -> data[7:0]   (or srcaddr[7:0]   if read transaction)
+//#   byte10 -> data[63:56]  
+//#   byte11 -> data[55:48]  
+//#   byte12 -> data[47:40]  
+//#   byte13 -> data[39:32]  
+//# **byte14 -> data[31:24]  
+//#    ...
+//#    ...
+//#    ...
+//#
+//#  * byte9 is the last byte of 32 bit write or read transaction 
+//#   
+//# ** if 64 bit write transaction, data of byte14 is the first data byte of
+//#    bursting transaction
+//# 
+//# -- The data is transmitted MSB first but in 32bits resolution. If we want
+//#    to transmit 64 bits it will be [31:0] (msb first) and then [63:32] (msb first)
+//#
+//# !!!
+//# !!! According to the above scheme, any new transaction (burst or not)
+//# !!! will take at least four cycles to be transmitted.
+//# !!! There are some internal mechanisms in the transmitter-receiver logic
+//# !!! which are implemented considering this assumption true.
+//# !!! Any change to this assumption (transaction takes at least four cycles)
+//# !!! should be carefully reviewed with its implications on the internal
+//# !!! implementation
+//# !!!
+//#      
+//#####################################################################
+
+module link_txo_channel (/*AUTOARG*/
+   // Outputs
+   emesh_wait_out, txo_launch_req_tlc, txo_rotate_dis, tran_frame_tlc,
+   tran_byte_even_tlc, tran_byte_odd_tlc,
+   // Inputs
+   cclk, cclk_en, txo_lclk, reset, txo_rd, txo_cid, cfg_burst_dis,
+   emesh_tran_in, emesh_frame_in, txo_launch_ack_tlc
+   );
+
+   parameter AW   = `CFG_AW  ;//address width
+   parameter DW   = `CFG_DW  ;//data width  
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+   parameter FW   = `CFG_NW*`CFG_LW;
+   parameter FAD  = 5; // Number of bits to access all the entries (2^FAD + 1) > AE*PE
+
+   //##########
+   //# INPUTS
+   //##########
+
+   input \t  cclk;     // clock of the score the emesh comes from
+   input \t  cclk_en;  // clock enable 
+   input \t  txo_lclk; // clock of the link transmitter
+   input          reset;
+
+   input \t  txo_rd;  // this is read transactions channel
+   input [1:0] \t  txo_cid; // transmitter channel ID
+   input \t  cfg_burst_dis; // control register bursting disable
+
+   //# from the EMESH
+   input [2*LW-1:0] emesh_tran_in;  // serialized transaction
+   input \t    emesh_frame_in; // transaction frame
+
+   //# from the arbiter
+   input \t    txo_launch_ack_tlc;
+
+   //###########
+   //# OUTPUTS
+   //###########
+   //# to emesh
+   output \t    emesh_wait_out; // wait to the emesh   
+
+   //# to the arbiter
+   output \t    txo_launch_req_tlc; // Launch request
+   output \t    txo_rotate_dis; // Arbiter\'s rotate disable 
+
+   //# to the output mux/buffer
+   output \t    tran_frame_tlc;       // Frame of the transaction
+   output [LW-1:0]  tran_byte_even_tlc;  // Even byte of the transaction
+   output [LW-1:0]  tran_byte_odd_tlc;   // Odd byte of the transaction
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\tcheck_next_dstaddr_tlc;\t// From link_txo_launcher of link_txo_launcher.v
+   wire [2*LW-1:0]\tfifo_out_tlc;\t\t// From link_txo_fifo of link_txo_fifo.v
+   wire\t\t\tframe_in;\t\t// From emesh_interface of emesh_interface.v
+   wire\t\t\tnext_access_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire [3:0]\t\tnext_ctrlmode_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire [1:0]\t\tnext_datamode_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire [AW-1:0]\tnext_dstaddr_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire\t\t\tnext_write_tlc;\t\t// From link_txo_fifo of link_txo_fifo.v
+   wire [FAD:0]\t\trd_read_tlc;\t\t// From link_txo_launcher of link_txo_launcher.v
+   wire [2*LW-1:0]\ttran_in;\t\t// From emesh_interface of emesh_interface.v
+   wire\t\t\ttran_written_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire\t\t\twr_fifo_full;\t\t// From link_txo_fifo of link_txo_fifo.v
+   // End of automatics
+
+
+
+
+endmodule // link_txo_channel
+
+//#############################################################################
+//# This block is a custom fifo for the link single channel
+//# transmitter.
+//# The fifo has a following structure:
+//# - 4  ""architectural"" entries to contain 4 full-size transactions. 
+//#    Every architectural entry has 7 ""sub-entries"" of 16bit each
+//#    112 bits in total (104 bits of actual transaction + 8 bits of zerros)
+//# - 28 ""physical"" entries in total (4*7)
+//# 
+//# The fifo is written in the ""regular"" manner - i.e. whenever there is an
+//# empty ""physical"" entry to write in.
+//# The fifo is read ""freely"" from within every ""architectural"" entry 
+//# (7 ""physical"" entries in a raw) once the ""architectural"" entry is written 
+//# in full.
+//# 
+//# For this purpose, the ""fifo write"" domain indicates to the ""fifo-read""
+//# domain every ""architectural"" entry being written,
+//# While the ""fifo read"" domain indicates to the ""fifo-write"" domain
+//# every ""physical"" entry being read.          
+//#############################################################################
+
+module link_txo_fifo (/*AUTOARG*/
+   // Outputs
+   wr_fifo_full, fifo_out_tlc, tran_written_tlc, next_ctrlmode_tlc,
+   next_dstaddr_tlc, next_datamode_tlc, next_write_tlc,
+   next_access_tlc,
+   // Inputs
+   reset, cclk, cclk_en, txo_lclk, tran_in, frame_in, rd_read_tlc,
+   check_next_dstaddr_tlc
+   );
+
+   parameter AW   = `CFG_AW  ;//address width
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+   parameter AE   = 4; // Number of ""architectural"" entries
+   parameter PE   = 7; // Number of ""physical"" entries in the ""architectural"" one
+   parameter FAD  = 5; // Number of bits to access all the entries (2^FAD + 1) > AE*PE
+   localparam MD = 1<<FAD;
+
+   // #########
+   // # Inputs
+   // #########
+   
+   input          reset;
+
+   input \t  cclk;      // core clock
+   input \t  cclk_en;   // core clock enable
+   input \t  txo_lclk;  // link transmitter clock   
+
+   //# from the emesh/mesh selection logic
+   input [2*LW-1:0] tran_in;  // serialized transaction
+   input \t    frame_in; // transaction frame
+
+   //# from the control
+   input [FAD:0]    rd_read_tlc; // Read containing potential jump for bursting
+   input \t    check_next_dstaddr_tlc; // Next transaction dstaddr can be checked
+
+   // ##########
+   // # Outputs
+   // ##########
+
+   //# to the emesh/mesh selection logic
+   output \t   wr_fifo_full;    
+
+   //# to the control
+   output [2*LW-1:0] fifo_out_tlc;      
+   output \t   tran_written_tlc;
+   output [3:0]    next_ctrlmode_tlc;
+   output [AW-1:0] next_dstaddr_tlc;
+   output [1:0]    next_datamode_tlc;
+   output \t   next_write_tlc;
+   output \t   next_access_tlc;
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+  
+   // ##########
+   // # REGS
+   // #########
+   reg [LW-1:0]    even_byte;
+   reg [2*LW-1:0] fifo_mem[MD-1:0];
+ 
+   reg [FAD:0]   rd_gray_pointer_tlc;
+   reg [FAD:0]   rd_binary_pointer_tlc;
+   reg [FAD:0]   rd_addr_traninfo0_tlc;
+
+   reg \t\t frame_del;
+   reg [FAD:0] \t wr_binary_pointer;
+   reg \t\t wr_fifo_full;
+
+   // #########
+   // # WIRES
+   // #########
+   wire [FAD-1:0]  rd_addr_tlc;
+   wire [FAD:0]    rd_binary_next_tlc;
+   wire [FAD:0]    rd_gray_next_tlc;
+   wire [FAD:0]    rd_addr_traninfo0_next_tlc;
+   wire [FAD-1:0]  rd_addr_traninfo1_tlc;
+   wire [FAD-1:0]  rd_addr_traninfo2_tlc;
+   wire [2*LW-1:0] traninfo0_tlc;
+   wire [2*LW-1:0] traninfo1_tlc;
+   wire [2*LW-1:0] traninfo2_tlc;
+
+   wire [FAD-1:0] wr_addr;\t
+   wire \t  wr_write;
+   wire \t  tran_written;
+   wire [FAD:0]   rd_gray_pointer;\t
+   wire \t  wr_fifo_full_next;
+   wire [FAD:0]   wr_gray_next;
+   wire [FAD:0]   wr_binary_next;
+
+   //###########################
+   //# Write control generation
+   //###########################
+   always @ (posedge cclk or posedge reset)
+     if(reset)
+       frame_del <= 1\'b0;
+     else if(cclk_en)
+       if(!wr_fifo_full)
+\t frame_del <= frame_in;
+
+   assign wr_write = (frame_in | frame_del) & ~wr_fifo_full;
+
+   //###################################
+   //# Full transaction write completed
+   //###################################
+   assign tran_written = ~frame_in & frame_del & ~wr_fifo_full;
+
+   //#################################
+   //# FIFO data
+   //#################################
+ 
+   //# Write
+   //# two bytes of the tran short word should enter different fifo entries
+   //# in order to get 32 bit of data, dstaddr and srcaddr each ""sitting"" in two
+   //# entries only.
+   //# In this case byte0 of the first entry of the transaction
+   //# ({byte0,ctrlmode[3:0],dstaddr[31:28]}) will be a ""zevel"" but we don\'t care
+   //# since this byte is replaced later anyway.
+   
+   always @ (posedge cclk)
+     if (cclk_en)
+       if(!wr_fifo_full)
+\t even_byte[LW-1:0] <= tran_in[LW-1:0];
+
+   always @ (posedge cclk)
+     if (cclk_en)
+       if (wr_write)
+\t fifo_mem[wr_addr[FAD-1:0]] <= {even_byte[LW-1:0],tran_in[2*LW-1:LW]};
+   
+   //# Read (for dispatch)
+   assign fifo_out_tlc[2*LW-1:0] = fifo_mem[rd_addr_tlc[FAD-1:0]];
+
+   //# Read (first short word of the next transaction to dispatch)
+   assign traninfo0_tlc[2*LW-1:0] = fifo_mem[rd_addr_traninfo0_tlc[FAD-1:0]];
+
+   //# Read (second short word of the next transaction to dispatch)
+   assign traninfo1_tlc[2*LW-1:0] = fifo_mem[rd_addr_traninfo1_tlc[FAD-1:0]];
+
+   //# Read (third short word of the next transaction to dispatch)
+   assign traninfo2_tlc[2*LW-1:0] = fifo_mem[rd_addr_traninfo2_tlc[FAD-1:0]];
+
+   assign next_ctrlmode_tlc[3:0]   = traninfo0_tlc[LW-1:LW-4];
+
+   assign next_dstaddr_tlc[AW-1:0] = {traninfo0_tlc[3:0],
+                                      traninfo1_tlc[2*LW-1:0],
+                                      traninfo2_tlc[2*LW-1:4]};
+
+   assign next_datamode_tlc[1:0] = traninfo2_tlc[3:2];
+
+   assign next_write_tlc  = traninfo2_tlc[1];
+   assign next_access_tlc = traninfo2_tlc[0];
+
+   //#####################################
+   //# FIFO Write State Machine
+   //#####################################
+
+   //# While for the actual address calculation we use [FAD-1:0] bits only,
+   //# the bit FAD of the counter is needed in order to distinguish
+   //# between the fifo entry currently being written and the one
+   //# written in the previous ""round"" (FAD is a carry-out bit and is
+   //# switched every ""round"")
+   always @(posedge cclk or posedge reset)
+     if(reset)
+       wr_binary_pointer[FAD:0]     <= {(FAD+1){1\'b0}};
+     else if(cclk_en)
+       if(wr_write)
+\t wr_binary_pointer[FAD:0]     <= wr_binary_next[FAD:0];\t  
+   
+   assign wr_addr[FAD-1:0]       = wr_binary_pointer[FAD-1:0];
+   assign wr_binary_next[FAD:0]  = wr_binary_pointer[FAD:0] + {{(FAD){1\'b0}},wr_write};
+
+   //# Gray Pointer Conversion (for more reliable synchronization)!
+   assign wr_gray_next[FAD:0] = {1\'b0,wr_binary_next[FAD:1]} ^ wr_binary_next[FAD:0];
+
+   //# FIFO full indication
+   assign wr_fifo_full_next = (wr_gray_next[FAD-2:0] == rd_gray_pointer[FAD-2:0]) &
+                              (wr_gray_next[FAD]     ^  rd_gray_pointer[FAD])     &
+                              (wr_gray_next[FAD-1]   ^  rd_gray_pointer[FAD-1]);
+\t\t\t      
+   always @ (posedge cclk or posedge reset)
+     if(reset)
+       wr_fifo_full <= 1\'b0;
+     else if(cclk_en)
+       wr_fifo_full <=wr_fifo_full_next;
+
+   //#############################
+   //# FIFO Read State Machine
+   //#############################
+    
+   always @(posedge txo_lclk or posedge reset)
+     if(reset)
+       begin
+\t  rd_binary_pointer_tlc[FAD:0]  <= {(FAD+1){1\'b0}};
+\t  rd_gray_pointer_tlc[FAD:0]    <= {(FAD+1){1\'b0}};
+       end
+     else if(|(rd_read_tlc[FAD:0]))
+       begin\t  rd_binary_pointer_tlc[FAD:0]  <= rd_binary_next_tlc[FAD:0];\t  
+\t  rd_gray_pointer_tlc[FAD:0]    <= rd_gray_next_tlc[FAD:0];\t  
+       end
+
+   assign rd_addr_tlc[FAD-1:0]       = rd_binary_pointer_tlc[FAD-1:0];
+   assign rd_binary_next_tlc[FAD:0]  = rd_binary_pointer_tlc[FAD:0] + rd_read_tlc[FAD:0];
+
+   //# Gray Pointer Conversion (for more reliable synchronization)!
+   assign rd_gray_next_tlc[FAD:0]  = {1\'b0,rd_binary_next_tlc[FAD:1]} ^ 
+                                           rd_binary_next_tlc[FAD:0];
+
+   //#
+   //# address and controls of the next transaction to be dispatch
+   //# * the size is actually FAD-1:0 but since FAD=3 causes syntax
+   //#   error for (FAD-3){1\'b0} expression, we use a biger range
+   //#   FAD:0 and (FAD-2){1\'b0}
+   //assign rd_addr_traninfo0_next_tlc[FAD-1:0] = rd_addr_traninfo0_tlc[FAD-1:0] + 
+   //                                             {{(FAD-3){1\'b0}},3\'b111};
+   assign rd_addr_traninfo0_next_tlc[FAD:0] = rd_addr_traninfo0_tlc[FAD:0] + 
+                                                {{(FAD-2){1\'b0}},3\'b111};
+
+   always @(posedge txo_lclk or posedge reset)
+     if(reset)
+       rd_addr_traninfo0_tlc[FAD:0]   <= {(FAD){1\'b0}};
+     else if(check_next_dstaddr_tlc)
+       rd_addr_traninfo0_tlc[FAD-1:0] <= rd_addr_traninfo0_next_tlc[FAD-1:0];
+
+   assign rd_addr_traninfo1_tlc[FAD-1:0] = rd_addr_traninfo0_tlc[FAD-1:0] +
+                                           {{(FAD-2){1\'b0}},2\'b01};
+
+   assign rd_addr_traninfo2_tlc[FAD-1:0] = rd_addr_traninfo0_tlc[FAD-1:0] +
+                                           {{(FAD-2){1\'b0}},2\'b10};
+
+   //####################################################
+   //# Synchronization between rd/wr domains
+   //####################################################
+
+   e16_pulse2pulse pulse_wr2rd  (.out         (tran_written_tlc),
+                             .outclk      (txo_lclk),
+                             .in          (tran_written),
+                             .inclk       (cclk),
+                             .reset       (reset));
+
+   e16_synchronizer #(.DW(FAD+1)) sync_rd2wr (.out\t (rd_gray_pointer[FAD:0]), 
+                                          .in\t (rd_gray_pointer_tlc[FAD:0]), 
+\t\t\t\t\t  .clk\t (cclk),
+\t\t\t\t\t  .reset (reset));
+   
+
+endmodule // link_txo_fifo
+
+module link_txo_interface (/*AUTOARG*/
+   // Outputs
+   txo_data, txo_frame, txo_wr_wait_int, txo_rd_wait_int,
+   // Inputs
+   txo_lclk, reset, txo_wr_data_even, txo_wr_data_odd, txo_wr_frame,
+   txo_wr_launch_req_tlc, txo_wr_rotate_dis, txo_rd_data_even,
+   txo_rd_data_odd, txo_rd_frame, txo_rd_launch_req_tlc,
+   txo_rd_rotate_dis
+   );
+
+   parameter LW  = `CFG_LW;
+   
+   //#########
+   //# Inputs
+   //#########
+
+   input          txo_lclk;
+   input \t  reset;
+
+   //# write transactions
+   input [LW-1:0]  txo_wr_data_even; //Even byte word
+   input [LW-1:0]  txo_wr_data_odd;  //Odd byte word
+   input \t   txo_wr_frame;     //indicates new transmission 
+   input \t   txo_wr_launch_req_tlc;
+   input \t   txo_wr_rotate_dis;
+   //# read transactions
+   input [LW-1:0]  txo_rd_data_even; //Even byte word
+   input [LW-1:0]  txo_rd_data_odd;  //Odd byte word
+   input \t   txo_rd_frame;     //indicates new transmission 
+   input \t   txo_rd_launch_req_tlc;
+   input \t   txo_rd_rotate_dis;
+
+   //############
+   //# Outputs
+   //############
+
+   output [LW-1:0]  txo_data;      //Byte word
+   output \t    txo_frame;     //indicates new transmission 
+   
+   output \t    txo_wr_wait_int; // Wait to txo_wr (have to stall immediately)
+   output \t    txo_rd_wait_int; // Wait to txo_rd (have to stall immediately)
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   //##########
+   //# REGS
+   //##########
+   reg [LW-1:0]   data_even_lsl;// Even bytes of the transmission
+   reg [LW-1:0]   data_even_lsh;// Even bytes of the transmission
+   reg [LW-1:0]   data_odd_lsl; // Odd bytes of the transmission
+   reg \t\t  txo_frame; //indicates transmission of new package
+
+   //###########
+   //# WIRES
+   //###########
+   wire \t txo_frame_in;   // selected frame of the transmission
+   wire [LW-1:0] data_even_in;   // selected even bytes of the transmission
+   wire [LW-1:0] data_odd_in;    // selected odd bytes of the transmission
+   wire [LW-1:0] txo_data;       // ddr data
+
+   //###########################
+   //# Priority arbitration
+   //###########################
+
+   assign txo_wr_wait_int = txo_rd_rotate_dis;
+   assign txo_rd_wait_int = txo_wr_launch_req_tlc & ~txo_rd_rotate_dis;
+
+   //###########################################
+   //#           Transaction mux
+   //# The ""and"" part of the ""and-or"" mux is
+   //# implemented in the link channels blocks  
+   //# therefore here we are good with ""or"" only
+   //###########################################
+
+   assign txo_frame_in = txo_wr_frame | txo_rd_frame;
+
+   assign data_even_in[LW-1:0] = txo_wr_data_even[LW-1:0] |
+\t\t\t\t txo_rd_data_even[LW-1:0];
+
+   assign data_odd_in[LW-1:0] = txo_wr_data_odd[LW-1:0] |
+\t\t\t\ttxo_rd_data_odd[LW-1:0];
+
+   // ################################
+   // # Transaction output
+   // ################################
+   
+   always @ (posedge txo_lclk or posedge reset)
+     if (reset)
+       begin
+\t  txo_frame             <= 1\'b0;
+\t  data_even_lsl[LW-1:0] <= {(LW){1\'b0}};
+\t  data_odd_lsl[LW-1:0]  <= {(LW){1\'b0}};
+       end
+     else 
+       begin
+\t  txo_frame              <= txo_frame_in;
+ \t  data_even_lsl[LW-1:0]  <= data_even_in[LW-1:0];
+\t  data_odd_lsl[LW-1:0]   <= data_odd_in[LW-1:0];
+       end
+
+   // # Creating data that is stable high
+   always @ (negedge txo_lclk or posedge reset)
+     if (reset)
+       data_even_lsh[LW-1:0] <= {(LW){1\'b0}};
+     else
+       data_even_lsh[LW-1:0]  <= data_even_lsl[LW-1:0];
+
+   // #################################
+   // # Dual data rate implementation
+   // #################################
+
+   assign txo_data[LW-1:0] = txo_lclk ? data_even_lsh[LW-1:0]://stable high data
+                                        data_odd_lsl[LW-1:0]; //stable low data
+
+
+endmodule // link_txo_interface
+module link_txo_launcher (/*AUTOARG*/
+   // Outputs
+   rd_read, check_next_dstaddr, txo_launch_req, txo_rotate_dis,
+   tran_frame, tran_byte_even, tran_byte_odd,
+   // Inputs
+   reset, txo_lclk, txo_rd, txo_cid, cfg_burst_dis, fifo_out,
+   tran_written, next_ctrlmode, next_dstaddr, next_datamode,
+   next_write, next_access, txo_launch_ack
+   );
+
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+   parameter AW   = `CFG_AW  ;//address width
+   parameter AE   = 4; // Number of ""architectural"" entries
+   parameter PE   = 7; // Number of ""physical"" entries in the ""architectural"" one
+   parameter FAD  = 5; // Number of bits to access all the entries (2^FAD + 1) > AE*PE
+
+   //##########
+   //# INPUTS
+   //##########
+   input          reset;
+   input \t  txo_lclk;  // link transmitter clock   
+
+   input \t  txo_rd;  // this is read transactions channel
+   input [1:0] \t  txo_cid; // transmitter channel ID
+   //# from configuration register
+   input \t  cfg_burst_dis; // control register bursting disable
+
+   //# from the fifo
+   input [2*LW-1:0] fifo_out;      
+   input \t  tran_written;
+   input [3:0] \t  next_ctrlmode;
+   input [AW-1:0] next_dstaddr;
+   input [1:0] \t  next_datamode;
+   input \t  next_write;
+   input \t  next_access;
+
+   //# from the arbiter
+   input \t  txo_launch_ack;
+
+   //############
+   //# OUTPUTS
+   //############
+
+   //# to the fifo
+   output [FAD:0] rd_read; // Read containing potential jump for bursting
+   output \t  check_next_dstaddr; // Next transaction dstaddr can be checked
+
+   //# to the arbiter
+   output \t  txo_launch_req; // Launch request
+   output \t  txo_rotate_dis; // Arbiter\'s rotate disable 
+
+   //# to the output mux/buffer
+   output \t  tran_frame;       // Frame of the transaction
+   output [LW-1:0] tran_byte_even;  // Even byte of the transaction
+   output [LW-1:0] tran_byte_odd;   // Odd byte of the transaction
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   //#############
+   //# REGS
+   //#############
+   reg [AE+1:0]   fifo_trans;
+   reg [3:0] \t  ref_ctrlmode;
+   reg [AW-1:0]   ref_dstaddr;
+   reg [1:0] \t  ref_datamode;
+   reg \t\t  ref_write;
+   reg \t\t  ref_access;
+   reg \t\t  byte0_inc0;
+   reg \t\t  txo_launch_init_req; 
+   reg \t\t  txo_launch_ack_del1;
+   reg \t\t  txo_launch_ack_del2;
+   reg \t\t  tran_frame;
+   reg [LW-1:0]   byte_odd_del;
+   reg [LW-1:0]   tran_byte_even;
+   reg [LW-1:0]   tran_byte_odd;
+   reg [2:0] \t  txo_launch_cnt;
+   reg \t\t  burst_req;
+   reg [1:0] \t  burst_backup_cnt;
+
+   //#############
+   //# WIRES
+   //#############
+   wire \t  start_new_read;
+   wire [AW-1:0]  ref_dstaddr_inc8; //Refernce address incremented by 8
+   wire \t  next_inc8_match; // Next address match (incremented by 8)
+   wire \t  next_inc0_match; // Next address match (un-incremented)
+   wire [7:0] \t  ref_ctrl; // Control type of reference transaction
+   wire [7:0] \t  next_ctrl;// Control type of next transaction
+   wire \t  type_match; // Reference and next transactions are of the same type
+   wire [7:0]\t  tran_byte0; // Byte0 of the transaction
+   wire \t  burst_tran; // Burst transaction
+   wire [2:0] \t  txo_launch_cnt_inc; // Incremented value of the counter
+   wire [2:0]\t  txo_launch_cnt_next;// Next value of the counter
+   wire \t  txo_launch_cnt_max; // The counter reached its maximum value
+   wire \t  tran_read;  // Transaction is read (last cycle of the transmission)
+   wire \t  jump_4entries;  // Jump forward four entries
+   wire \t  jump_3entries;  // Jump forward three entries
+   wire \t  jump_3entries_write; // jump over srcaddr part of the tran on write
+   wire \t  jump_3entries_read;  // jump over data part of the transaction on read
+   wire \t  jump_1entry; // single entry ""jump""
+   wire [2:0] \t  jump_value;  // value of the jump for read pointer
+   wire \t  txo_op_ack;       // ""operation"" acknowledge
+   wire \t  txo_op_ack_first; // first ""operation"" acknowledge cycle
+   wire [LW-1:0]  byte_even_mux;
+   wire [LW-1:0]  byte_odd_mux;
+   wire [LW-1:0]  byte_even;
+   wire [LW-1:0]  byte_odd;
+   wire \t  make_gap;     // make gap in the transaction frame
+   wire \t  single_write; // single write transaction
+   wire \t  double_write; // double write transaction
+   wire \t  burst_req_denied; // request of burst transaction is not acknowledged
+   wire \t  burst_backup_inc; // burst transaction backup counter increment
+   wire [1:0] \t  burst_backup_inc_cnt;  // Incremented burst backup counter
+   wire [1:0] \t  burst_backup_next_cnt; // Next burst backup counter value
+   wire \t  freeze_fifo;           // FIFO and main counter advance should stoped
+   wire sel_ref_byte0; // select byte0 from the reference information of the transaction 
+   wire sel_ref_byte1; // select byte1 from the reference information of the transaction 
+   wire sel_ref_byte2; // select byte2 from the reference information of the transaction 
+   wire sel_ref_byte3; // select byte3 from the reference information of the transaction 
+   wire sel_ref_byte4; // select byte4 from the reference information of the transaction 
+   wire sel_ref_byte5; // select byte5 from the reference information of the transaction 
+
+   //####################################################
+   //#               Interface to the arbiter
+   //#
+   //#####################################################
+
+   //# When the acknowledge is received on the last cycle of the transaction
+   //# and if the next transaction is not a burst transaction then we should  
+   //# create an ""artificial gap"" in the frame signal.
+   //# If burst request was denied we should de-assert frame signal 
+   
+   assign make_gap = tran_read & ~burst_tran;
+
+   always @ (posedge txo_lclk or posedge reset)
+     if(reset)
+       begin
+\t  txo_launch_ack_del1 <= 1\'b0;
+\t  txo_launch_ack_del2 <= 1\'b0;
+       end
+     else
+       begin
+\t  txo_launch_ack_del1 <= txo_launch_ack      & ~make_gap;
+\t  txo_launch_ack_del2 <= txo_launch_ack_del1 & ~burst_req_denied;
+       end
+
+   assign txo_op_ack       = txo_launch_ack      &  txo_launch_ack_del1;
+   assign txo_op_ack_first = txo_launch_ack_del1 & ~txo_launch_ack_del2;
+
+   //# Request and rotate disable
+   //# On the first cycle of the acknowledge the launch count is not incremented
+   //# yet, therefore we have to force request and rotate disable ""artificially""
+   always @ (posedge txo_lclk or posedge reset)
+     if (reset)
+       txo_launch_init_req <= 1\'b0;
+     else if(start_new_read)
+       txo_launch_init_req <= 1\'b1;
+     else if(txo_launch_ack)
+       txo_launch_init_req <= 1\'b0;
+
+   assign txo_launch_req = txo_launch_init_req | 
+\t\t\t    txo_op_ack_first | (|(txo_launch_cnt[2:0]));
+
+   assign txo_rotate_dis = ~txo_launch_init_req & 
+\t\t\t   (txo_op_ack_first | (|(txo_launch_cnt[2:0])));
+
+   //#######################################
+   //# Architectural entries state tracking
+   //# (written/read transactions tracking)
+   //#######################################
+
+   always @ (posedge txo_lclk or posedge reset)
+     if(reset)
+       fifo_trans[AE+1:0] <= {{(AE+1){1\'b0}},1\'b1};
+     else if(tran_written & ~tran_read)
+       fifo_trans[AE+1:0] <= {fifo_trans[AE:0],1\'b0};
+     else if(tran_read & ~tran_written)
+       fifo_trans[AE+1:0] <= {1\'b0,fifo_trans[AE+1:1]};
+
+   //# we start new read if:
+   //# 1. there is an indication of the first written transaction
+   //# 2. transaction is read and the new one is written at the same cycle
+   //# 3. transaction is read but there are more already written indicated by fifo_trans
+   assign start_new_read = (fifo_trans[0]           & tran_written) |
+\t\t\t   (tran_read               & tran_written) |
+\t\t\t   ((|(fifo_trans[AE+1:2])) & tran_read );
+
+   assign check_next_dstaddr = start_new_read;
+
+   //#####################
+   //# Bursting logic
+   //#####################
+
+   //# keeping track of the address increment mode of burst transaction
+   always @ (posedge txo_lclk or posedge reset)
+     if(reset)
+       byte0_inc0     <= 1\'b0;
+     else if(start_new_read)
+       byte0_inc0     <= next_inc0_match;
+   
+   //# reference destination address and controls
+   always @(posedge txo_lclk)
+     if(start_new_read)
+       begin
+\t  ref_ctrlmode[3:0]   <= next_ctrlmode[3:0];
+\t  ref_dstaddr[AW-1:0] <= next_dstaddr[AW-1:0];
+\t  ref_datamode[1:0]   <= next_datamode[1:0];
+\t  ref_write           <= next_write;
+\t  ref_access          <= next_access;
+       end
+
+   //# transaction type (double write should be known in advance for burst determination)
+//   assign single_write = ref_access  & ref_write  & ~(&(ref_datamode[1:0]));
+   assign single_write = 1\'b0; // No special treatment for single write
+   assign double_write = next_access & next_write &  (&(next_datamode[1:0]));
+
+   //# compare address
+   assign ref_dstaddr_inc8[AW-1:0] = ref_dstaddr[AW-1:0]+{{(AW-4){1\'b0}},4\'b1000};
+
+   assign next_inc8_match = (ref_dstaddr_inc8[AW-1:0] == next_dstaddr[AW-1:0]);
+   assign next_inc0_match = (ref_dstaddr[AW-1:0]      == next_dstaddr[AW-1:0]);
+
+   assign ref_ctrl[7:0]  = {ref_ctrlmode[3:0], ref_datamode[1:0], ref_write, ref_access};
+   assign next_ctrl[7:0] = {next_ctrlmode[3:0],next_datamode[1:0],next_write,next_access};
+
+   assign type_match = (ref_ctrl[7:0] == next_ctrl[7:0]);
+
+   //# burst mode determination
+   assign burst_tran = ~cfg_burst_dis  & // bursting is enabled by user
+\t\t        start_new_read & // valid cycle
+\t\t        tran_read      & // only continuous burst is supported
+\t\t        type_match     & // type match
+\t\t        double_write   & // double write transaction
+\t\t        ((next_inc8_match  & ~byte0_inc0) |  // address match
+\t\t\t (next_inc0_match  &  byte0_inc0));
+
+   always @ (posedge txo_lclk or posedge reset)
+     if (reset)
+       burst_req    <= 1\'b0;
+     else
+       burst_req    <= burst_tran;
+
+  //####################################################################################
+   //# Composing byte0 of the transaction
+   //# 
+   //# Byte0 has the following encoding scheme:
+   //#
+   //#  8\'b1?_??_??_<cid>  | New READ transaction 
+   //#  8\'b0?_??_?0_<cid>  | New WRITE transaction with incremental bursting address 
+   //#  8\'b0?_??_?1_<cid>  | New WRITE transaction with the same bursting address
+   //#
+   //#  cid[1:0] - channel id (for debugging usage only in the current version of design)
+   //####################################################################################
+
+   assign tran_byte0[7:0] = {txo_rd,4\'b0000, byte0_inc0, txo_cid[1:0]};
+
+   //###################################################################
+   //#            Order of the transaction fields in the fifo
+   //#            -------------------------------------------
+   //# Entry ""n+6""                 srcaddr[15:0]
+   //# Entry ""n+5""\t\t  srcaddr[31:16],
+   //# Entry ""n+4""                  data[15:0],
+   //# Entry ""n+3""                 data[31:16],
+   //# Entry ""n+2""  dstaddr[11:0],datamode[1:0],write,access,
+   //# Entry ""n+1""\t          dstaddr[27:12],
+   //# Entry ""n""          ""zevel"",ctrlmode[3:0],dstaddr[31:28],
+   //#            --------------------------------------------
+   //####################################################################
+
+   //# 4 entries jump on burst transaction (counter comparison is redundant but used
+   //# here to underline the mutex between different jumps)
+   assign jump_4entries = burst_tran & (txo_launch_cnt[2:0] == 3\'b110);
+   //# 3 entries jump on single write or read
+   assign jump_3entries = jump_3entries_write | 
+\t\t\t  jump_3entries_read;
+   //# single write will jump 3 entries to the end of the transaction
+   assign jump_3entries_write = single_write & (txo_launch_cnt[2:0] == 3\'b100); 
+   //# read transaction will jump 3 entries over the data part of that transaction
+   //assign jump_3entries_read = ~ref_write & (txo_launch_cnt[2:0] == 3\'b010);
+   //# read jump over data feature is disabled because of the test-and-set instr.
+   assign jump_3entries_read = 1\'b0;
+   //# single jump when acknowledged and no other jumps and no freeze control
+   assign jump_1entry = ~(jump_4entries | jump_3entries | freeze_fifo) & txo_op_ack;
+
+   //###########################################################
+   //# Counter/FIFO Read Pointer increment prevention mechanism
+   //# when bursting is not acknowledged.
+   //# When burst_backup_cnt[1:0] is not zero, the counter and
+   //# FIFO read pointers won\'t advance and the data out
+   //# will be selected from the reference controls and address
+   //###########################################################
+
+   assign burst_req_denied = burst_req   & ~txo_op_ack;
+   assign burst_backup_inc = freeze_fifo &  txo_op_ack;
+
+   assign burst_backup_inc_cnt[1:0]  = burst_backup_cnt[1:0] + 2\'b01;
+
+   assign burst_backup_next_cnt[1:0] = burst_req_denied ? 2\'b01 :
+\t\t\t\t       burst_backup_inc ? burst_backup_inc_cnt[1:0] :
+\t\t\t\t                          burst_backup_cnt[1:0];
+
+   always @ (posedge txo_lclk or posedge reset)
+     if(reset)
+       burst_backup_cnt[1:0] <= 2\'b00;
+     else
+       burst_backup_cnt[1:0] <= burst_backup_next_cnt[1:0];
+
+   assign freeze_fifo = |(burst_backup_cnt[1:0]);
+
+   //###################################################################
+   //#       Launch Counter vs. FIFO Read Pointer:
+   //# FIFO Read Pointer is incremented in the range 0-6
+   //# relative to any particular entry pointed out in a particular
+   //# cycle.
+   //# Launch Counter on the other hand is incremented in the same 
+   //# range of 0-6 but relative to a specific counter state.
+   //# For example, FIFO Read Pointer can have a jump of 4 from any
+   //# entry, while Launch Counter will have a jump of 4 only if
+   //# the current state of the counter is 3\'b110 (+ some conditions)
+   //#
+   //# This difference in behavior is caused by the fact that 
+   //# for every transaction in the counter we have to go through all
+   //# the eight existing states of the counter, while it will take
+   //# only six entriest of the FIFO.
+   //###################################################################         
+
+   //# FIFO Read Pointer Jump Value
+   assign jump_value[2:0] = ({(3){jump_4entries}} & 3\'b100) |
+\t\t\t    ({(3){jump_3entries}} & 3\'b011) |
+\t\t\t    ({(3){jump_1entry}}   & 3\'b001);
+
+   assign rd_read[FAD:0] = {{(FAD-2){1\'b0}},jump_value[2:0]};
+
+   //# Counter Next Cycle Value
+   assign txo_launch_cnt_max = (txo_launch_cnt[2:0] == 3\'b110);
+
+   assign txo_launch_cnt_inc[2:0] = txo_launch_cnt[2:0] + {2\'b00,jump_1entry};
+
+   assign txo_launch_cnt_next[2:0] =  jump_4entries ? 3\'b011 :
+\t (jump_3entries_write | txo_launch_cnt_max) ? 3\'b000 :
+\t\t\t         jump_3entries_read ? 3\'b101 : txo_launch_cnt_inc[2:0];
+
+   //# Launch counter
+   always @ (posedge txo_lclk or posedge reset)
+     if (reset)
+       txo_launch_cnt[2:0] <= 3\'b000;
+     else if(txo_op_ack)
+       txo_launch_cnt[2:0] <= txo_launch_cnt_next[2:0];
+
+   //#############################################
+   //# Completion of the transaction transmission 
+   //#############################################
+
+   assign tran_read = (~single_write & (txo_launch_cnt[2:0] == 3\'b110)) |
+\t\t      ( single_write & (txo_launch_cnt[2:0] == 3\'b100));
+
+   //##################################################
+   //# Even/Odd bytes construction + tran out sampling
+   //##################################################
+
+   assign sel_ref_byte0 = txo_op_ack_first;
+   assign sel_ref_byte2 = (burst_backup_cnt[1:0] == 2\'b10);
+   assign sel_ref_byte4 = (burst_backup_cnt[1:0] == 2\'b11);
+
+   assign sel_ref_byte1 = (burst_backup_cnt[1:0] == 2\'b01);
+   assign sel_ref_byte3 = (burst_backup_cnt[1:0] == 2\'b10);
+   assign sel_ref_byte5 = (burst_backup_cnt[1:0] == 2\'b11);
+
+   assign byte_even_mux[LW-1:0] = sel_ref_byte0 ? tran_byte0[7:0]    :
+\t\t\t\t  sel_ref_byte2 ? ref_dstaddr[27:20] :
+\t\t\t\t  sel_ref_byte4 ? ref_dstaddr[11:4]  :
+\t\t\t\t                  fifo_out[2*LW-1:LW];
+
+   assign byte_odd_mux[LW-1:0] = sel_ref_byte1 ? {ref_ctrlmode[3:0],ref_dstaddr[31:28]} :
+\t\t\t\t sel_ref_byte3 ? ref_dstaddr[19:12] :
+\t      sel_ref_byte5 ? {ref_dstaddr[3:0],ref_datamode[1:0],ref_write,ref_access} :
+\t\t\t\t                 fifo_out[LW-1:0];
+
+   assign byte_even[LW-1:0] = {(LW){txo_op_ack}} & byte_even_mux[LW-1:0];
+   assign byte_odd[LW-1:0]  = {(LW){txo_op_ack}} & byte_odd_mux[LW-1:0];
+
+   always @ (posedge txo_lclk or posedge reset)
+     if(reset)
+       tran_frame <= 1\'b0;
+     else
+       tran_frame <= txo_launch_ack_del2;
+
+   always @ (posedge txo_lclk)
+     begin
+\tbyte_odd_del[LW-1:0]   <= byte_odd[LW-1:0];
+\ttran_byte_odd[LW-1:0]  <= byte_odd_del[LW-1:0];
+\ttran_byte_even[LW-1:0] <= byte_even[LW-1:0];
+     end
+
+   //###################
+   //# ERROR CHECKERS 
+   //###################
+   // synthesis translate_off
+   always @*
+     if(~(|(fifo_trans[AE+1:0])) & $time>0)
+       $display(""ERROR>>link launcher mechanism is broken in cell %m"");
+
+   always @*
+     if(((jump_4entries       & (jump_3entries_read | jump_3entries_write | jump_1entry))|
+\t (jump_3entries_read  & (                     jump_3entries_write | jump_1entry))|
+\t (jump_3entries_write & (                                           jump_1entry)))
+\t& $time>0)
+       $display(""ERROR>>detected more than one jump for launcher mechanism in cell %m"");
+   // synthesis translate_on
+
+
+endmodule // link_txo_launcher
+module link_txo_mesh_channel (/*AUTOARG*/
+   // Outputs
+   emesh_wait_out, mesh_wait_out, txo_launch_req_tlc,
+   txo_rotate_dis_tlc, tran_frame_tlc, tran_byte_even_tlc,
+   tran_byte_odd_tlc,
+   // Inputs
+   cclk, cclk_en, txo_lclk, reset, ext_yid_k, ext_xid_k, who_am_i,
+   txo_rd, txo_cid, cfg_multicast_dis, cfg_burst_dis, emesh_tran_in,
+   emesh_frame_in, mesh_access_in, mesh_write_in, mesh_dstaddr_in,
+   mesh_srcaddr_in, mesh_data_in, mesh_datamode_in, mesh_ctrlmode_in,
+   txo_launch_ack_tlc
+   );
+
+   parameter AW   = `CFG_AW  ;//address width
+   parameter DW   = `CFG_DW  ;//data width  
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+   parameter FW   = `CFG_NW*`CFG_LW;
+   parameter FAD  = 5; // Number of bits to access all the entries (2^FAD + 1) > AE*PE
+
+   //##########
+   //# INPUTS
+   //##########
+
+   input \t  cclk;     // clock of the score the emesh comes from
+   input \t  cclk_en;  // clock enable 
+   input \t  txo_lclk; // clock of the link transmitter
+   input          reset;
+   input [3:0] \t  ext_yid_k; //external y-id 
+   input [3:0] \t  ext_xid_k; //external x-id
+   input [3:0]\t  who_am_i;  // specifies what link is that (north,east,south,west)
+
+   input \t  txo_rd;  // this is read transactions channel
+   input [1:0] \t  txo_cid; // transmitter channel ID
+   input \t  cfg_multicast_dis; // control register multicast disable
+   input \t  cfg_burst_dis; // control register bursting disable
+
+   //# from the EMESH
+   input [2*LW-1:0] emesh_tran_in;  // serialized transaction
+   input \t    emesh_frame_in; // transaction frame
+
+   //# from the MESH
+   input \t  mesh_access_in;  // access control from the mesh
+   input \t  mesh_write_in;   // write control from the mesh
+   input [AW-1:0] mesh_dstaddr_in; // destination address from the mesh
+   input [AW-1:0] mesh_srcaddr_in; // source address from the mesh
+   input [DW-1:0] mesh_data_in;    // data from the mesh
+   input [1:0] \t  mesh_datamode_in;// data mode from the mesh 
+   input [3:0] \t  mesh_ctrlmode_in;// ctrl mode from the mesh
+
+   //# from the arbiter
+   input \t  txo_launch_ack_tlc;
+
+   //###########
+   //# OUTPUTS
+   //###########
+   //# to emesh
+   output \t  emesh_wait_out; // wait to the emesh   
+
+   //# to mesh
+   output \t  mesh_wait_out; // wait to the mesh   
+
+   //# to the arbiter
+   output \t  txo_launch_req_tlc; // Launch request
+   output \t  txo_rotate_dis_tlc; // Arbiter\'s rotate disable 
+
+   //# to the output mux/buffer
+   output \t   tran_frame_tlc;      // Frame of the transaction
+   output [LW-1:0] tran_byte_even_tlc;  // Even byte of the transaction
+   output [LW-1:0] tran_byte_odd_tlc;   // Odd byte of the transaction
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\taccess_reg;\t\t// From mesh_interface of e16_mesh_interface.v
+   wire\t\t\tcheck_next_dstaddr_tlc;\t// From link_txo_launcher of link_txo_launcher.v
+   wire [3:0]\t\tctrlmode_reg;\t\t// From mesh_interface of e16_mesh_interface.v
+   wire [DW-1:0]\tdata_reg;\t\t// From mesh_interface of e16_mesh_interface.v
+   wire [1:0]\t\tdatamode_reg;\t\t// From mesh_interface of e16_mesh_interface.v
+   wire [AW-1:0]\tdstaddr_reg;\t\t// From mesh_interface of e16_mesh_interface.v
+   wire [2*LW-1:0]\tfifo_out_tlc;\t\t// From link_txo_fifo of link_txo_fifo.v
+   wire\t\t\tmesh_frame;\t\t// From link_txo_mesh_launcher of link_txo_mesh_launcher.v
+   wire\t\t\tmesh_req;\t\t// From link_txo_mesh_launcher of link_txo_mesh_launcher.v
+   wire\t\t\tmesh_rotate_dis;\t// From link_txo_mesh_launcher of link_txo_mesh_launcher.v
+   wire [2*LW-1:0]\tmesh_tran;\t\t// From link_txo_mesh_launcher of link_txo_mesh_launcher.v
+   wire\t\t\tmesh_wait_int;\t\t// From link_txo_mesh_launcher of link_txo_mesh_launcher.v
+   wire\t\t\tnext_access_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire [3:0]\t\tnext_ctrlmode_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire [1:0]\t\tnext_datamode_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire [AW-1:0]\tnext_dstaddr_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire\t\t\tnext_write_tlc;\t\t// From link_txo_fifo of link_txo_fifo.v
+   wire [FAD:0]\t\trd_read_tlc;\t\t// From link_txo_launcher of link_txo_launcher.v
+   wire [AW-1:0]\tsrcaddr_reg;\t\t// From mesh_interface of e16_mesh_interface.v
+   wire\t\t\ttran_written_tlc;\t// From link_txo_fifo of link_txo_fifo.v
+   wire\t\t\twr_fifo_full;\t\t// From link_txo_fifo of link_txo_fifo.v
+   wire\t\t\twrite_reg;\t\t// From mesh_interface of e16_mesh_interface.v
+   // End of automatics
+
+   //#######################
+   //# Transaction Launcher
+   //#######################
+
+   /* link_txo_launcher AUTO_TEMPLATE (
+                                       .txo_rotate_dis\t(txo_rotate_dis_tlc), 
+                                       .reset\t\t(reset),
+                                       .txo_lclk\t(txo_lclk),
+                                       .txo_rd          (txo_rd),
+                                       .txo_cid\t\t(txo_cid[1:0]),
+                                       .cfg_burst_dis\t(cfg_burst_dis),
+                                       .\\(.*\\)          (\\1_tlc[]),
+                                      );
+    */
+
+   link_txo_launcher #(.FAD(FAD)) link_txo_launcher(/*AUTOINST*/
+\t\t\t\t\t\t    // Outputs
+\t\t\t\t\t\t    .rd_read\t\t(rd_read_tlc[FAD:0]), // Templated
+\t\t\t\t\t\t    .check_next_dstaddr\t(check_next_dstaddr_tlc), // Templated
+\t\t\t\t\t\t    .txo_launch_req\t(txo_launch_req_tlc), // Templated
+\t\t\t\t\t\t    .txo_rotate_dis\t(txo_rotate_dis_tlc), // Templated
+\t\t\t\t\t\t    .tran_frame\t\t(tran_frame_tlc), // Templated
+\t\t\t\t\t\t    .tran_'b'byte_even\t(tran_byte_even_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    .tran_byte_odd\t(tran_byte_odd_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    // Inputs
+\t\t\t\t\t\t    .reset\t\t(reset),\t // Templated
+\t\t\t\t\t\t    .txo_lclk\t\t(txo_lclk),\t // Templated
+\t\t\t\t\t\t    .txo_rd\t\t(txo_rd),\t // Templated
+\t\t\t\t\t\t    .txo_cid\t\t(txo_cid[1:0]),\t // Templated
+\t\t\t\t\t\t    .cfg_burst_dis\t(cfg_burst_dis), // Templated
+\t\t\t\t\t\t    .fifo_out\t\t(fifo_out_tlc[2*LW-1:0]), // Templated
+\t\t\t\t\t\t    .tran_written\t(tran_written_tlc), // Templated
+\t\t\t\t\t\t    .next_ctrlmode\t(next_ctrlmode_tlc[3:0]), // Templated
+\t\t\t\t\t\t    .next_dstaddr\t(next_dstaddr_tlc[AW-1:0]), // Templated
+\t\t\t\t\t\t    .next_datamode\t(next_datamode_tlc[1:0]), // Templated
+\t\t\t\t\t\t    .next_write\t\t(next_write_tlc), // Templated
+\t\t\t\t\t\t    .next_access\t(next_access_tlc), // Templated
+\t\t\t\t\t\t    .txo_launch_ack\t(txo_launch_ack_tlc)); // Templated
+
+   //########
+   //# FIFO
+   //########
+   
+   link_txo_fifo #(.FAD(FAD)) link_txo_fifo(.tran_in\t\t(mesh_tran[2*LW-1:0]),
+\t\t\t\t\t    .frame_in\t\t(mesh_frame),
+\t\t\t\t\t    /*AUTOINST*/
+\t\t\t\t\t    // Outputs
+\t\t\t\t\t    .wr_fifo_full\t(wr_fifo_full),
+\t\t\t\t\t    .fifo_out_tlc\t(fifo_out_tlc[2*LW-1:0]),
+\t\t\t\t\t    .tran_written_tlc\t(tran_written_tlc),
+\t\t\t\t\t    .next_ctrlmode_tlc\t(next_ctrlmode_tlc[3:0]),
+\t\t\t\t\t    .next_dstaddr_tlc\t(next_dstaddr_tlc[AW-1:0]),
+\t\t\t\t\t    .next_datamode_tlc\t(next_datamode_tlc[1:0]),
+\t\t\t\t\t    .next_write_tlc\t(next_write_tlc),
+\t\t\t\t\t    .next_access_tlc\t(next_access_tlc),
+\t\t\t\t\t    // Inputs
+\t\t\t\t\t    .reset\t\t(reset),
+\t\t\t\t\t    .cclk\t\t(cclk),
+\t\t\t\t\t    .cclk_en\t\t(cclk_en),
+\t\t\t\t\t    .txo_lclk\t\t(txo_lclk),
+\t\t\t\t\t    .rd_read_tlc\t(rd_read_tlc[FAD:0]),
+\t\t\t\t\t    .check_next_dstaddr_tlc(check_next_dstaddr_tlc));
+
+  
+   //##################################
+   //#    Interface with mesh
+   //# on input transactions only
+   //# * output to the mesh is driven
+   //# by a diferent block
+   //##################################
+
+   /*e16_mesh_interface AUTO_TEMPLATE (
+                                    .clk               (cclk),
+                                    .clk_en            (cclk_en),
+                                    .wait_int          (mesh_wait_int),
+\t\t\t\t    .wait_out\t       (mesh_wait_out),\t
+                                    .\\(.*\\)_out        (),
+                                    .wait_in           (1\'b0),
+                                    .\\(.*\\)_in         (mesh_\\1_in[]),
+    \t\t\t\t    .access\t       (1\'b0),
+\t\t\t\t    .write \t       (1\'b0),
+\t\t\t\t    .datamode\t       (2\'b00),
+\t\t\t\t    .ctrlmode\t       (4\'b0000),
+\t\t\t\t    .data\t       ({(DW){1\'b0}}),
+\t\t\t\t    .dstaddr\t       ({(AW){1\'b0}}),
+\t\t\t\t    .srcaddr\t       ({(AW){1\'b0}}),
+                                   );
+    */
+   e16_mesh_interface mesh_interface(/*AUTOINST*/
+\t\t\t\t     // Outputs
+\t\t\t\t     .wait_out\t\t(mesh_wait_out), // Templated
+\t\t\t\t     .access_out\t(),\t\t // Templated
+\t\t\t\t     .write_out\t\t(),\t\t // Templated
+\t\t\t\t     .datamode_out\t(),\t\t // Templated
+\t\t\t\t     .ctrlmode_out\t(),\t\t // Templated
+\t\t\t\t     .data_out\t\t(),\t\t // Templated
+\t\t\t\t     .dstaddr_out\t(),\t\t // Templated
+\t\t\t\t     .srcaddr_out\t(),\t\t // Templated
+\t\t\t\t     .access_reg\t(access_reg),
+\t\t\t\t     .write_reg\t\t(write_reg),
+\t\t\t\t     .datamode_reg\t(datamode_reg[1:0]),
+\t\t\t\t     .ctrlmode_reg\t(ctrlmode_reg[3:0]),
+\t\t\t\t     .data_reg\t\t(data_reg[DW-1:0]),
+\t\t\t\t     .dstaddr_reg\t(dstaddr_reg[AW-1:0]),
+\t\t\t\t     .srcaddr_reg\t(srcaddr_reg[AW-1:0]),
+\t\t\t\t     // Inputs
+\t\t\t\t     .clk\t\t(cclk),\t\t // Templated
+\t\t\t\t     .clk_en\t\t(cclk_en),\t // Templated
+\t\t\t\t     .reset\t\t(reset),
+\t\t\t\t     .wait_in\t\t(1\'b0),\t\t // Templated
+\t\t\t\t     .access_in\t\t(mesh_access_in), // Templated
+\t\t\t\t     .write_in\t\t(mesh_write_in), // Templated
+\t\t\t\t     .datamode_in\t(mesh_datamode_in[1:0]), // Templated
+\t\t\t\t     .ctrlmode_in\t(mesh_ctrlmode_in[3:0]), // Templated
+\t\t\t\t     .data_in\t\t(mesh_data_in[DW-1:0]), // Templated
+\t\t\t\t     .dstaddr_in\t(mesh_dstaddr_in[AW-1:0]), // Templated
+\t\t\t\t     .srcaddr_in\t(mesh_srcaddr_in[AW-1:0]), // Templated
+\t\t\t\t     .wait_int\t\t(mesh_wait_int), // Templated
+\t\t\t\t     .access\t\t(1\'b0),\t\t // Templated
+\t\t\t\t     .write\t\t(1\'b0),\t\t // Templated
+\t\t\t\t     .datamode\t\t(2\'b00),\t // Templated
+\t\t\t\t     .ctrlmode\t\t(4\'b0000),\t // Templated
+\t\t\t\t     .data\t\t({(DW){1\'b0}}),\t // Templated
+\t\t\t\t     .dstaddr\t\t({(AW){1\'b0}}),\t // Templated
+\t\t\t\t     .srcaddr\t\t({(AW){1\'b0}}));\t // Templated
+
+
+   //#################################
+   //# MESH Transaction Launcher
+   //#################################
+   
+   link_txo_mesh_launcher link_txo_mesh_launcher(.mesh_grant\t\t(~wr_fifo_full),
+\t\t\t\t\t\t /*AUTOINST*/
+\t\t\t\t\t\t // Outputs
+\t\t\t\t\t\t .mesh_wait_int\t\t(mesh_wait_int),
+\t\t\t\t\t\t .mesh_req\t\t(mesh_req),
+\t\t\t\t\t\t .mesh_rotate_dis\t(mesh_rotate_dis),
+\t\t\t\t\t\t .mesh_tran\t\t(mesh_tran[2*LW-1:0]),
+\t\t\t\t\t\t .mesh_frame\t\t(mesh_frame),
+\t\t\t\t\t\t // Inputs
+\t\t\t\t\t\t .cclk\t\t\t(cclk),
+\t\t\t\t\t\t .cclk_en\t\t(cclk_en),
+\t\t\t\t\t\t .reset\t\t\t(reset),
+\t\t\t\t\t\t .ext_yid_k\t\t(ext_yid_k[3:0]),
+\t\t\t\t\t\t .ext_xid_k\t\t(ext_xid_k[3:0]),
+\t\t\t\t\t\t .who_am_i\t\t(who_am_i[3:0]),
+\t\t\t\t\t\t .cfg_multicast_dis\t(cfg_multicast_dis),
+\t\t\t\t\t\t .access_reg\t\t(access_reg),
+\t\t\t\t\t\t .write_reg\t\t(write_reg),
+\t\t\t\t\t\t .datamode_reg\t\t(datamode_reg[1:0]),
+\t\t\t\t\t\t .ctrlmode_reg\t\t(ctrlmode_reg[3:0]),
+\t\t\t\t\t\t .data_reg\t\t(data_reg[DW-1:0]),
+\t\t\t\t\t\t .dstaddr_reg\t\t(dstaddr_reg[AW-1:0]),
+\t\t\t\t\t\t .srcaddr_reg\t\t(srcaddr_reg[AW-1:0]));
+
+endmodule // link_txo_mesh_channel
+module link_txo_mesh_launcher(/*AUTOARG*/
+   // Outputs
+   mesh_wait_int, mesh_req, mesh_rotate_dis, mesh_tran, mesh_frame,
+   // Inputs
+   cclk, cclk_en, reset, ext_yid_k, ext_xid_k, who_am_i,
+   cfg_multicast_dis, access_reg, write_reg, datamode_reg,
+   ctrlmode_reg, data_reg, dstaddr_reg, srcaddr_reg, mesh_grant
+   );
+
+   parameter AW   = `CFG_AW  ;//address width
+   parameter DW   = `CFG_DW  ;//data width  
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+
+   //##########
+   //# INPUTS
+   //##########
+   input \t  cclk;      // clock of the score the emesh comes from
+   input \t  cclk_en;   // clock enable 
+   input          reset;
+   input [3:0] \t  ext_yid_k; // external y-id 
+   input [3:0] \t  ext_xid_k; // external x-id
+   input [3:0]\t  who_am_i;  // specifies what link is that (north,east,south,west)
+
+   input \t  cfg_multicast_dis; // control register multicast disable
+
+   //# input transaction (after mesh interface)
+   input \t  access_reg;
+   input \t  write_reg;
+   input [1:0] \t  datamode_reg;
+   input [3:0] \t  ctrlmode_reg;   \t\t    
+   input [DW-1:0] data_reg;
+   input [AW-1:0] dstaddr_reg;
+   input [AW-1:0] srcaddr_reg;  
+
+   //# from the mesh/emesh arbiter
+   input \t  mesh_grant;
+
+   //############
+   //# OUTPUTS
+   //############
+
+   //# to the mesh interface
+   output \t  mesh_wait_int; // Wait indication
+
+   //# to the arbiter
+   output \t  mesh_req; // Launch request to the arbiter
+   output \t  mesh_rotate_dis; // Arbiter\'s rotate disable 
+
+   //# to the output mux/buffer
+   output [2*LW-1:0] mesh_tran;  // transaction data
+   output \t     mesh_frame; // mesh frame
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   //#############
+   //# REGS
+   //#############
+   reg [2:0]   mesh_pointer;
+
+   //#############
+   //# WIRES
+   //#############
+   wire        multicast_tran_valid; // Valid multicast transaction
+   wire        multicast_tran; // transaction is of the multicast type
+   wire [3:0]  ycoord_k_n; // inverted external y coordinates
+   wire [3:0]  xcoord_k_n; // inverted external x coordinates
+   wire [3:0]  addr_y; // external y coordinates of the source address
+   wire [3:0]  addr_x; // external x coordinates of the source address
+   wire        ext_yzero;
+   wire        ext_xzero;
+   wire [4:0]  ext_xdiff;
+   wire [4:0]  ext_ydiff;
+   wire        ext_xcarry;   
+   wire        ext_ycarry;   
+   wire        ext_xgt;   
+   wire        ext_xlt;   
+   wire        ext_ygt;   
+   wire        ext_ylt;   
+   wire        route_east;   
+   wire        route_west;   
+   wire        route_north;   
+   wire        route_south;   
+   wire        route_east_normal;   
+   wire        route_west_normal;   
+   wire        route_north_normal;   
+   wire        route_south_normal;   
+   wire        route_east_multicast;   
+   wire        route_west_multicast;   
+   wire        route_north_multicast;   
+   wire        route_south_multicast;   
+   wire [3:0]  route_sides; // where to route {north,east,south,west}
+   wire        route_out;   // Route out of this link was detected
+   wire        mesh_ack;
+   wire        mesh_ack_n;
+   wire        mesh_last_tran;
+   wire [2:0]  mesh_pointer_incr;
+   wire [6:0]  launcher_sel;
+   wire [14*LW-1:0] mesh_tran_in;
+
+   //###########################################
+   //# Valid MESH-to-LINK transaction detection
+   //###########################################
+
+   //# Multicast transaction detection
+   assign multicast_tran = write_reg & 
+\t\t\t   (ctrlmode_reg[1:0]==2\'b11) & ~(datamode_reg[1:0] == 2\'b11);
+
+   //# External source or destination address of the transaction for the comparison
+//   assign addr_y[2:0] = multicast_tran ? srcaddr_reg[31:29] : dstaddr_reg[31:29];
+//   assign addr_x[2:0] = multicast_tran ? srcaddr_reg[28:26] : dstaddr_reg[28:26];
+   assign addr_y[3:0] = multicast_tran ? srcaddr_reg[31:28] : dstaddr_reg[31:28];
+   assign addr_x[3:0] = multicast_tran ? srcaddr_reg[25:22] : dstaddr_reg[25:22];
+
+   //# External address based router
+   assign ycoord_k_n[3:0] = ~ext_yid_k[3:0];
+   assign xcoord_k_n[3:0] = ~ext_xid_k[3:0];
+
+   //# External address comparison 
+   assign ext_yzero      = addr_y[3:0]==ext_yid_k[3:0];
+   assign ext_xzero      = addr_x[3:0]==ext_xid_k[3:0];   
+   assign ext_ydiff[4:0] = addr_y[3:0] + ycoord_k_n[3:0] + 1\'b1 ; 
+   assign ext_xdiff[4:0] = addr_x[3:0] + xcoord_k_n[3:0] + 1\'b1 ;
+   assign ext_xcarry     = ext_xdiff[4]; //result is positive or zero
+   assign ext_ycarry     = ext_ydiff[4]; //result is positive or zero    
+   assign ext_xgt        = ext_xcarry & ~ext_xzero;// src/dst X-address is greater than
+   assign ext_xlt        = ~ext_xcarry;  // src/dst X-address is less than
+   assign ext_ygt        = ext_ycarry & ~ext_yzero;// src/dst Y-address is greater than
+   assign ext_ylt        = ~ext_ycarry;  // src/dst Y-address is less than 
+
+   //# NON-MULTICAST ROUTING
+   assign route_east_normal   =  ext_xgt;   
+   assign route_west_normal   =  ext_xlt;
+   assign route_south_normal  =  ext_ygt & ext_xzero;
+   assign route_north_normal  =  ext_ylt & ext_xzero;
+
+   //# MULTICAST ROUTING
+   assign route_east_multicast  = (ext_xlt | ext_xzero) & ext_yzero;
+   assign route_west_multicast  = (ext_xgt | ext_xzero) & ext_yzero;
+   assign route_south_multicast =  ext_ylt | ext_yzero;
+   assign route_north_multicast =  ext_ygt | ext_yzero;
+
+   //# normal-multicast selection
+   assign route_east  = multicast_tran ? route_east_multicast  : route_east_normal;
+   assign route_west  = multicast_tran ? route_west_multicast  : route_west_normal;
+   assign route_south = multicast_tran ? route_south_multicast : route_south_normal;
+   assign route_north = multicast_tran ? route_north_multicast : route_north_normal;
+
+   assign route_sides[3:0] = 4\'b1111;//{route_north,route_east,route_south,route_west};
+   assign route_out = |(who_am_i[3:0] & route_sides[3:0]);
+
+   //# Request
+   assign mesh_req = access_reg & route_out & ((multicast_tran & ~cfg_multicast_dis) |
+\t\t\t\t\t       ~multicast_tran);
+
+   //# Wait
+   assign mesh_ack_n    = mesh_req & ~mesh_grant;
+   assign mesh_ack      = mesh_req &  mesh_grant;
+   assign mesh_wait_int = mesh_req & ~mesh_last_tran | mesh_ack_n;
+
+   //############################################
+   //# Transaction launcher state machine
+   //############################################
+
+   assign mesh_last_tran = mesh_pointer[2] & mesh_pointer[1] & ~mesh_pointer[0];
+                        
+   assign mesh_pointer_incr[2:0] = mesh_last_tran ? 3\'b000 :
+\t\t\t\t   (mesh_pointer[2:0] + 3\'b001);
+
+   always @ (posedge cclk or posedge reset)
+     if(reset)
+       mesh_pointer[2:0] <= 3\'b000;
+     else if(cclk_en)
+       if (mesh_ack)
+\t mesh_pointer[2:0] <= mesh_pointer_incr[2:0];
+
+   assign launcher_sel[0] = (mesh_pointer[2:0] == 3\'b000);
+   assign launcher_sel[1] = (mesh_pointer[2:0] == 3\'b001);
+   assign launcher_sel[2] = (mesh_pointer[2:0] == 3\'b010);
+   assign launcher_sel[3] = (mesh_pointer[2:0] == 3\'b011);
+   assign launcher_sel[4] = (mesh_pointer[2:0] == 3\'b100);
+   assign launcher_sel[5] = (mesh_pointer[2:0] == 3\'b101);
+   assign launcher_sel[6] = (mesh_pointer[2:0] == 3\'b110);
+
+   assign mesh_frame      =   mesh_req & ~mesh_last_tran;
+   assign mesh_rotate_dis = |(mesh_pointer[2:0]);
+
+   //#############################
+   //# mesh transaction 7:1 mux
+   //#############################
+
+   //# We are launching in the following order (MSBs first):
+   assign mesh_tran_in[14*LW-1:0]={
+                                srcaddr_reg[7:0],{(LW){1\'b0}},
+\t\t\t\t   srcaddr_reg[23:8],
+\t\t\t    data_reg[7:0],srcaddr_reg[31:24],
+\t\t\t\t   data_reg[23:8],
+\t dstaddr_reg[3:0],datamode_reg[1:0],write_reg,access_reg,data_reg[31:24],
+\t\t\t\t   dstaddr_reg[19:4],
+\t\t\t  ctrlmode_reg[3:0],dstaddr_reg[31:20]
+                                   };
+
+   e16_mux7 #(2*LW) mux7(// Outputs
+\t\t     .out (mesh_tran[2*LW-1:0]),
+\t\t     // Inputs
+\t\t     .in0 (mesh_tran_in[2*LW-1:0]),      .sel0 (launcher_sel[0]),
+\t\t     .in1 (mesh_tran_in[4*LW-1:2*LW]),   .sel1 (launcher_sel[1]),
+\t\t     .in2 (mesh_tran_in[6*LW-1:4*LW]),   .sel2 (launcher_sel[2]),
+\t\t     .in3 (mesh_tran_in[8*LW-1:6*LW]),   .sel3 (launcher_sel[3]),
+\t\t     .in4 (mesh_tran_in[10*LW-1:8*LW]),  .sel4 (launcher_sel[4]),
+\t\t     .in5 (mesh_tran_in[12*LW-1:10*LW]), .sel5 (launcher_sel[5]),
+\t\t     .in6 (mesh_tran_in[14*LW-1:12*LW]), .sel6 (launcher_sel[6]));
+
+
+endmodule // link_txo_mesh_launcher
+//#############################################################
+//# This block is a transmitter of the read transactions only
+//# Read transactions can be sent out off the chip from
+//# rdmesh only
+//#############################################################
+
+module link_txo_rd (/*AUTOARG*/
+   // Outputs
+   txo_rd_data_even, txo_rd_data_odd, txo_rd_frame,
+   txo_rd_launch_req_tlc, txo_rd_rotate_dis, c0_rdmesh_wait_out,
+   c1_rdmesh_wait_out, c2_rdmesh_wait_out, c3_rdmesh_wait_out,
+   // Inputs
+   txo_lclk, reset, txo_rd_wait, txo_rd_wait_int, c0_clk_in,
+   c1_clk_in, c2_clk_in, c3_clk_in, c0_rdmesh_tran_in,
+   c0_rdmesh_frame_in, c1_rdmesh_tran_in, c1_rdmesh_frame_in,
+   c2_rdmesh_tran_in, c2_rdmesh_frame_in, c3_rdmesh_tran_in,
+   c3_rdmesh_frame_in
+   );
+
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+
+   // #########
+   // # Inputs
+   // #########
+
+   input \ttxo_lclk;  //transmit clock to be used internally
+   input        reset;
+
+   // # from io
+   input \ttxo_rd_wait; // Wait from the receiver
+   input \ttxo_rd_wait_int;  //wait indicator for read transactions
+   // # Clocks
+   input \tc0_clk_in;   //clock of the core  
+   input \tc1_clk_in;   //clock of the core  
+   input \tc2_clk_in;   //clock of the core  
+   input \tc3_clk_in;   //clock of the core  
+
+   // # RDMESH
+   input [2*LW-1:0] c0_rdmesh_tran_in;  // serialized transaction
+   input \t    c0_rdmesh_frame_in; // transaction frame
+   input [2*LW-1:0] c1_rdmesh_tran_in;  // serialized transaction
+   input \t    c1_rdmesh_frame_in; // transaction frame
+   input [2*LW-1:0] c2_rdmesh_tran_in;  // serialized transaction
+   input \t    c2_rdmesh_frame_in; // transaction frame
+   input [2*LW-1:0] c3_rdmesh_tran_in;  // serialized transaction
+   input \t    c3_rdmesh_frame_in; // transaction frame
+
+   // ##############
+   // # Outputs
+   // ##############
+
+   // to the txo_interface
+   output [LW-1:0] txo_rd_data_even; //Even byte word
+   output [LW-1:0] txo_rd_data_odd;  //Odd byte word
+   output \t   txo_rd_frame; //indicates new transmission 
+   output \t   txo_rd_launch_req_tlc;
+   output \t   txo_rd_rotate_dis;
+
+   output \t   c0_rdmesh_wait_out; // wait to the rdmesh   
+   output \t   c1_rdmesh_wait_out; // wait to the rdmesh   
+   output \t   c2_rdmesh_wait_out; // wait to the rdmesh   
+   output \t   c3_rdmesh_wait_out; // wait to the rdmesh   
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [LW-1:0]\tc0_tran_byte_even_tlc;\t// From c0_link_txo_channel of link_txo_channel.v
+   wire [LW-1:0]\tc0_tran_byte_odd_tlc;\t// From c0_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc0_tran_frame_tlc;\t// From c0_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc0_txo_launch_ack_tlc;\t// From link_txo_arbiter of link_txo_arbiter.v
+   wire\t\t\tc0_txo_launch_req_tlc;\t// From c0_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc0_txo_rotate_dis;\t// From c0_link_txo_channel of link_txo_channel.v
+   wire [LW-1:0]\tc1_tran_byte_even_tlc;\t// From c1_link_txo_channel of link_txo_channel.v
+   wire [LW-1:0]\tc1_tran_byte_odd_tlc;\t// From c1_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc1_tran_frame_tlc;\t// From c1_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc1_txo_launch_ack_tlc;\t// From link_txo_arbiter of link_txo_arbiter.v
+   wire\t\t\tc1_txo_launch_req_tlc;\t// From c1_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc1_txo_rotate_dis;\t// From c1_link_txo_channel of link_txo_channel.v
+   wire [LW-1:0]\tc2_tran_byte_even_tlc;\t// From c2_link_txo_channel of link_txo_channel.v
+   wire [LW-1:0]\tc2_tran_byte_odd_tlc;\t// From c2_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc2_tran_frame_tlc;\t// From c2_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc2_txo_launch_ack_tlc;\t// From link_txo_arbiter of link_txo_arbiter.v
+   wire\t\t\tc2_txo_launch_req_tlc;\t// From c2_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc2_txo_rotate_dis;\t// From c2_link_txo_channel of link_txo_channel.v
+   wire [LW-1:0]\tc3_tran_byte_even_tlc;\t// From c3_link_txo_channel of link_txo_channel.v
+   wire [LW-1:0]\tc3_tran_byte_odd_tlc;\t// From c3_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc3_tran_frame_tlc;\t// From c3_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc3_txo_launch_ack_tlc;\t// From link_txo_arbiter of link_txo_arbiter.v
+   wire\t\t\tc3_txo_launch_req_tlc;\t// From c3_link_txo_channel of link_txo_channel.v
+   wire\t\t\tc3_txo_rotate_dis;\t// From c3_link_txo_channel of link_txo_channel.v
+   // End of automatics
+
+   // ##########
+   // # WIRES
+   // ##########
+
+   wire [1:0] \t     c0_txo_cid;//channel 0 ID
+   wire [1:0] \t     c1_txo_cid;//channel 1 ID
+   wire [1:0] \t     c2_txo_cid;//channel 2 ID
+   wire [1:0] \t     c3_txo_cid;//channel 3 ID
+
+   // ################################
+   // # Transmit buffer instantiation
+   // ################################
+
+   /*link_txo_buffer AUTO_TEMPLATE(
+                                  .txo_data_even (txo_rd_data_even[]),
+                                  .txo_data_odd  (txo_rd_data_odd[]),
+                                  .txo_frame     (txo_rd_frame),
+                                   );
+    */
+   link_txo_buffer link_txo_buffer(/*AUTOINST*/
+\t\t\t\t   // Outputs
+\t\t\t\t   .txo_data_even\t(txo_rd_data_even[LW-1:0]), // Templated
+\t\t\t\t   .txo_data_odd\t(txo_rd_data_odd[LW-1:0]), // Templated
+\t\t\t\t   .txo_frame\t\t(txo_rd_frame),\t // Templated
+\t\t\t\t   // Inputs
+\t\t\t\t   .c0_tran_frame_tlc\t(c0_tran_frame_tlc),
+\t\t\t\t   .c0_tran_byte_even_tlc(c0_tran_byte_even_tlc[LW-1:0]),
+\t\t\t\t   .c0_tran_byte_odd_tlc(c0_tran_byte_odd_tlc[LW-1:0]),
+\t\t\t\t   .c1_tran_frame_tlc\t(c1_tran_frame_tlc),
+\t\t\t\t   .c1_tran_byte_even_tlc(c1_tran_byte_even_tlc[LW-1:0]),
+\t\t\t\t   .c1_tran_byte_odd_tlc(c1_tran_byte_odd_tlc[LW-1:0]),
+\t\t\t\t   .c2_tran_frame_tlc\t(c2_tran_frame_tlc),
+\t\t\t\t   .c2_tran_byte_even_tlc(c2_tran_byte_even_tlc[LW-1:0]),
+\t\t\t\t   .c2_tran_byte_odd_tlc(c2_tran_byte_odd_tlc[LW-1:0]),
+\t\t\t\t   .c3_tran_frame_tlc\t(c3_tran_frame_tlc),
+\t\t\t\t   .c3_tran_byte_even_tlc(c3_tran_byte_even_tlc[LW-1:0]),
+\t\t\t\t   .c3_tran_byte_odd_tlc(c3_tran_byte_odd_tlc[LW-1:0]));
+
+   // #########################
+   // # Arbiter instantiation
+   // #########################
+
+   /*link_txo_arbiter AUTO_TEMPLATE(
+                                  .txo_wait            (txo_rd_wait),
+                                  .txo_wait_int        (txo_rd_wait_int),
+                                  .txo_launch_req_tlc  (txo_rd_launch_req_tlc),
+                                  .txo_rotate_dis_tlc  (txo_rd_rotate_dis),
+                                   );
+    */
+   link_txo_arbiter link_txo_arbiter (/*AUTOINST*/
+\t\t\t\t      // Outputs
+\t\t\t\t      .txo_launch_req_tlc(txo_rd_launch_req_tlc), // Templated
+\t\t\t\t      .txo_rotate_dis_tlc(txo_rd_rotate_dis), // Templated
+\t\t\t\t      .c0_txo_launch_ack_tlc(c0_txo_launch_ack_tlc),
+\t\t\t\t      .c1_txo_launch_ack_tlc(c1_txo_launch_ack_tlc),
+\t\t\t\t      .c2_txo_launch_ack_tlc(c2_txo_launch_ack_tlc),
+\t\t\t\t      .c3_txo_launch_ack_tlc(c3_txo_launch_ack_tlc),
+\t\t\t\t      // Inputs
+\t\t\t\t      .txo_lclk\t\t(txo_lclk),
+\t\t\t\t      .reset\t\t(reset),
+\t\t\t\t      .txo_wait\t\t(txo_rd_wait),\t // Templated
+\t\t\t\t      .txo_wait_int\t(txo_rd_wait_int), // Templated
+\t\t\t\t      .c0_txo_launch_req_tlc(c0_txo_launch_req_tlc),
+\t\t\t\t      .c0_txo_rotate_dis(c0_txo_rotate_dis),
+\t\t\t\t      .c1_txo_launch_req_tlc(c1_txo_launch_req_tlc),
+\t\t\t\t      .c1_txo_rotate_dis(c1_txo_rotate_dis),
+\t\t\t\t      .c2_txo_launch_req_tlc(c2_txo_launch_req_tlc),
+\t\t\t\t      .c2_txo_rotate_dis(c2_txo_rotate_dis),
+\t\t\t\t      .c3_txo_launch_req_tlc(c3_txo_launch_req_tlc),
+\t\t\t\t      .c3_txo_rotate_dis(c3_txo_rotate_dis));
+
+   // #########################
+   // # Channels instantiation
+   // #########################
+
+   /*link_txo_channel AUTO_TEMPLATE (
+                   .cclk       (@""(substring vl-cell-name  0 2)""_clk_in),
+                   .cclk_en    (1\'b1),
+                   .txo_rd     (1\'b1),
+\t\t   .txo_lclk   (txo_lclk),
+\t\t   .reset      (reset),
+                   .cfg_burst_dis (1\'b1),
+                   .emesh_\\(.*\\) (@""(substring vl-cell-name  0 2)""_rdmesh_\\1[]),
+                   .\\(.*\\)       (@""(substring vl-cell-name  0 2)""_\\1[]),
+                                     );
+    */
+
+   //# channel 0
+   link_txo_channel #(.FAD(3)) c0_link_txo_channel (/*AUTOINST*/
+\t\t\t\t\t\t    // Outputs
+\t\t\t\t\t\t    .emesh_wait_out\t(c0_rdmesh_wait_out), // Templated
+\t\t\t\t\t\t    .txo_launch_req_tlc\t(c0_txo_launch_req_tlc), // Templated
+\t\t\t\t\t\t    .txo_rotate_dis\t(c0_txo_rotate_dis), // Templated
+\t\t\t\t\t\t    .tran_frame_tlc\t(c0_tran_frame_tlc), // Templated
+\t\t\t\t\t\t    .tran_byte_even_tlc\t(c0_tran_byte_even_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    .tran_byte_odd_tlc\t(c0_tran_byte_odd_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    // Inputs
+\t\t\t\t\t\t    .cclk\t\t(c0_clk_in),\t // Templated
+\t\t\t\t\t\t    .cclk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .txo_lclk\t\t(txo_lclk),\t // Templated
+\t\t\t\t\t\t    .reset\t\t(reset),\t // Templated
+\t\t\t\t\t\t    .txo_rd\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .txo_cid\t\t(c0_txo_cid[1:0]), // Templated
+\t\t\t\t\t\t    .cfg_burst_dis\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .emesh_tran_in\t(c0_rdmesh_tran_in[2*LW-1:0]), // Templated
+\t\t\t\t\t\t    .emesh_frame_in\t(c0_rdmesh_frame_in), // Templated
+\t\t\t\t\t\t    .txo_launch_ack_tlc\t(c0_txo_launch_ack_tlc)); // Templated
+
+   //# channel 1
+   link_txo_channel #(.FAD(3)) c1_link_txo_channel (/*AUTOINST*/
+\t\t\t\t\t\t    // Outputs
+\t\t\t\t\t\t    .emesh_wait_out\t(c1_rdmesh_wait_out), // Templated
+\t\t\t\t\t\t    .txo_launch_req_tlc\t(c1_txo_launch_req_tlc), // Templated
+\t\t\t\t\t\t    .txo_rotate_dis\t(c1_txo_rotate_dis), // Templated
+\t\t\t\t\t\t    .tran_frame_tlc\t(c1_tran_frame_tlc), // Templated
+\t\t\t\t\t\t    .tran_byte_even_tlc\t(c1_tran_byte_even_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    .tran_byte_odd_tlc\t(c1_tran_byte_odd_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    // Inputs
+\t\t\t\t\t\t    .cclk\t\t(c1_clk_in),\t // Templated
+\t\t\t\t\t\t    .cclk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .txo_lclk\t\t(txo_lclk),\t // Templated
+\t\t\t\t\t\t    .reset\t\t(reset),\t // Templated
+\t\t\t\t\t\t    .txo_rd\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .txo_cid\t\t(c1_txo_cid[1:0]), // Templated
+\t\t\t\t\t\t    .cfg_burst_dis\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .emesh_tran_in\t(c1_rdmesh_tran_in[2*LW-1:0]), // Templated
+\t\t\t\t\t\t    .emesh_frame_in\t(c1_rdmesh_frame_in), // Templated
+\t\t\t\t\t\t    .txo_launch_ack_tlc\t(c1_txo_launch_ack_tlc)); // Templated
+
+   //# channel 2
+   link_txo_channel #(.FAD(3)) c2_link_txo_channel (/*AUTOINST*/
+\t\t\t\t\t\t    // Outputs
+\t\t\t\t\t\t    .emesh_wait_out\t(c2_rdmesh_wait_out), // Templated
+\t\t\t\t\t\t    .txo_launch_req_tlc\t(c2_txo_launch_req_tlc), // Templated
+\t\t\t\t\t\t    .txo_rotate_dis\t(c2_txo_rotate_dis), // Templated
+\t\t\t\t\t\t    .tran_frame_tlc\t(c2_tran_frame_tlc), // Templated
+\t\t\t\t\t\t    .tran_byte_even_tlc\t(c2_tran_byte_even_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    .tran_byte_odd_tlc\t(c2_tran_byte_odd_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    // Inputs
+\t\t\t\t\t\t    .cclk\t\t(c2_clk_in),\t // Templated
+\t\t\t\t\t\t    .cclk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .txo_lclk\t\t(txo_lclk),\t // Templated
+\t\t\t\t\t\t    .reset\t\t(reset),\t // Templated
+\t\t\t\t\t\t    .txo_rd\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .txo_cid\t\t(c2_txo_cid[1:0]), // Templated
+\t\t\t\t\t\t    .cfg_burst_dis\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .emesh_tran_in\t(c2_rdmesh_tran_in[2*LW-1:0]), // Templated
+\t\t\t\t\t\t    .emesh_frame_in\t(c2_rdmesh_frame_in), // Templated
+\t\t\t\t\t\t    .txo_launch_ack_tlc\t(c2_txo_launch_ack_tlc)); // Templated
+
+   //# channel 3
+   link_txo_channel #(.FAD(3)) c3_link_txo_channel (/*AUTOINST*/
+\t\t\t\t\t\t    // Outputs
+\t\t\t\t\t\t    .emesh_wait_out\t(c3_rdmesh_wait_out), // Templated
+\t\t\t\t\t\t    .txo_launch_req_tlc\t(c3_txo_launch_req_tlc), // Templated
+\t\t\t\t\t\t    .txo_rotate_dis\t(c3_txo_rotate_dis), // Templated
+\t\t\t\t\t\t    .tran_frame_tlc\t(c3_tran_frame_tlc), // Templated
+\t\t\t\t\t\t    .tran_byte_even_tlc\t(c3_tran_byte_even_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    .tran_byte_odd_tlc\t(c3_tran_byte_odd_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t    // Inputs
+\t\t\t\t\t\t    .cclk\t\t(c3_clk_in),\t // Templated
+\t\t\t\t\t\t    .cclk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .txo_lclk\t\t(txo_lclk),\t // Templated
+\t\t\t\t\t\t    .reset\t\t(reset),\t // Templated
+\t\t\t\t\t\t    .txo_rd\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .txo_cid\t\t(c3_txo_cid[1:0]), // Templated
+\t\t\t\t\t\t    .cfg_burst_dis\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t    .emesh_tran_in\t(c3_rdmesh_tran_in[2*LW-1:0]), // Templated
+\t\t\t\t\t\t    .emesh_frame_in\t(c3_rdmesh_frame_in), // Templated
+\t\t\t\t\t\t    .txo_launch_ack_tlc\t(c3_txo_launch_ack_tlc)); // Templated
+
+endmodule // link_txo_rd
+//#############################################################
+//# This block is a transmitter of the write transactions only
+//# Write transactions can be sent out off the chip from
+//# emesh and mesh but not from rdmesh
+//#############################################################
+
+module link_txo_wr (/*AUTOARG*/
+   // Outputs
+   txo_wr_data_even, txo_wr_data_odd, txo_wr_frame,
+   txo_wr_launch_req_tlc, txo_wr_rotate_dis, c0_emesh_wait_out,
+   c1_emesh_wait_out, c2_emesh_wait_out, c3_emesh_wait_out,
+   c0_mesh_wait_out, c3_mesh_wait_out,
+   // Inputs
+   c2_tran_frame_tlc, c2_tran_byte_odd_tlc, c2_tran_byte_even_tlc,
+   c1_tran_frame_tlc, c1_tran_byte_odd_tlc, c1_tran_byte_even_tlc,
+   txo_lclk, reset, ext_yid_k, ext_xid_k, who_am_i, cfg_burst_dis,
+   cfg_multicast_dis, txo_wr_wait, txo_wr_wait_int, c0_clk_in,
+   c1_clk_in, c2_clk_in, c3_clk_in, c0_emesh_tran_in,
+   c0_emesh_frame_in, c1_emesh_tran_in, c1_emesh_frame_in,
+   c2_emesh_tran_in, c2_emesh_frame_in, c3_emesh_tran_in,
+   c3_emesh_frame_in, c0_mesh_access_in, c0_mesh_write_in,
+   c0_mesh_dstaddr_in, c0_mesh_srcaddr_in, c0_mesh_data_in,
+   c0_mesh_datamode_in, c0_mesh_ctrlmode_in, c3_mesh_access_in,
+   c3_mesh_write_in, c3_mesh_dstaddr_in, c3_mesh_srcaddr_in,
+   c3_mesh_data_in, c3_mesh_datamode_in, c3_mesh_ctrlmode_in
+   );
+
+   parameter LW   = `CFG_LW  ;//lvds tranceiver pairs per side
+   parameter AW   = `CFG_AW  ;//address width
+   parameter DW   = `CFG_DW  ;//data width  
+   
+   // #########
+   // # Inputs
+   // #########
+
+   input \ttxo_lclk;  //transmit clock to be used internally
+   input        reset;
+   input [3:0] \text_yid_k; //external y-id 
+   input [3:0] \text_xid_k; //external x-id
+   input [3:0] \twho_am_i;  //specifies what link is that (north,east,south,west)
+   input \tcfg_burst_dis; //control register bursting disable
+   input \tcfg_multicast_dis;//control register multicast disable
+   // # from io
+   input \ttxo_wr_wait; // Wait from the receiver
+   input \ttxo_wr_wait_int; // Wait from the txo_interface (have to stall immediately)
+   // # Clocks
+   input \tc0_clk_in;   //clock of the core  
+   input \tc1_clk_in;   //clock of the core  
+   input \tc2_clk_in;   //clock of the core  
+   input \tc3_clk_in;   //clock of the core  
+  
+   // # EMESH
+   input [2*LW-1:0] c0_emesh_tran_in;  // serialized transaction
+   input \t    c0_emesh_frame_in; // transaction frame
+   input [2*LW-1:0] c1_emesh_tran_in;  // serialized transaction
+   input \t    c1_emesh_frame_in; // transaction frame
+   input [2*LW-1:0] c2_emesh_tran_in;  // serialized transaction
+   input \t    c2_emesh_frame_in; // transaction frame
+   input [2*LW-1:0] c3_emesh_tran_in;  // serialized transaction
+   input \t    c3_emesh_frame_in; // transaction frame
+
+   // # MESH 
+   // # core0 (external corners and multicast)
+   input \t    c0_mesh_access_in;  // access control from the mesh
+   input \t    c0_mesh_write_in;   // write control from the mesh
+   input [AW-1:0]   c0_mesh_dstaddr_in; // destination address from the mesh
+   input [AW-1:0]   c0_mesh_srcaddr_in; // source address from the mesh
+   input [DW-1:0]   c0_mesh_data_in;    // data from the mesh
+   input [1:0] \t    c0_mesh_datamode_in;// data mode from the mesh 
+   input [3:0] \t    c0_mesh_ctrlmode_in;// ctrl mode from the mesh
+   // # core3 (external corners only)
+   input \t    c3_mesh_access_in;  // access control from the mesh
+   input \t    c3_mesh_write_in;   // write control from the mesh
+   input [AW-1:0]   c3_mesh_dstaddr_in; // destination address from the mesh
+   input [AW-1:0]   c3_mesh_srcaddr_in; // source address from the mesh
+   input [DW-1:0]   c3_mesh_data_in;    // data from the mesh
+   input [1:0] \t    c3_mesh_datamode_in;// data mode from the mesh 
+   input [3:0] \t    c3_mesh_ctrlmode_in;// ctrl mode from the mesh
+
+   // ##############
+   // # Outputs
+   // ##############
+
+   // to the txo_interface
+   output [LW-1:0] txo_wr_data_even; //Even byte word
+   output [LW-1:0] txo_wr_data_odd;  //Odd byte word
+   output \t   txo_wr_frame; //indicates new transmission 
+   output \t   txo_wr_launch_req_tlc;
+   output \t   txo_wr_rotate_dis;
+
+   output \t   c0_emesh_wait_out; //wait to the emesh   
+   output \t   c1_emesh_wait_out; //wait to the emesh   
+   output \t   c2_emesh_wait_out; //wait to the emesh   
+   output \t   c3_emesh_wait_out; //wait to the emesh   
+
+   output \t   c0_mesh_wait_out;  //wait to the mesh 
+   output \t   c3_mesh_wait_out;  //wait to the mesh 
+
+   /*AUTOINPUT*/
+   // Beginning of automatic inputs (from unused autoinst inputs)
+   input [LW-1:0]\tc1_tran_byte_even_tlc;\t// To link_txo_buffer of link_txo_buffer.v
+   input [LW-1:0]\tc1_tran_byte_odd_tlc;\t// To link_txo_buffer of link_txo_buffer.v
+   input\t\tc1_tran_frame_tlc;\t// To link_txo_buffer of link_txo_buffer.v
+   input [LW-1:0]\tc2_tran_byte_even_tlc;\t// To link_txo_buffer of link_txo_buffer.v
+   input [LW-1:0]\tc2_tran_byte_odd_tlc;\t// To link_txo_buffer of link_txo_buffer.v
+   input\t\tc2_tran_frame_tlc;\t// To link_txo_buffer of link_txo_buffer.v
+   // End of automatics
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [LW-1:0]\tc0_tran_byte_even_tlc;\t// From c0_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire [LW-1:0]\tc0_tran_byte_odd_tlc;\t// From c0_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire\t\t\tc0_tran_frame_tlc;\t// From c0_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire\t\t\tc0_txo_launch_ack_tlc;\t// From link_txo_arbiter of link_txo_arbiter.v
+   wire\t\t\tc0_txo_launch_req_tlc;\t// From c0_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire\t\t\tc0_txo_rotate_dis;\t// From c0_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire\t\t\tc1_txo_launch_ack_tlc;\t// From link_txo_arbiter of link_txo_arbiter.v
+   wire\t\t\tc2_txo_launch_ack_tlc;\t// From link_txo_arbiter of link_txo_arbiter.v
+   wire [LW-1:0]\tc3_tran_byte_even_tlc;\t// From c3_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire [LW-1:0]\tc3_tran_byte_odd_tlc;\t// From c3_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire\t\t\tc3_tran_frame_tlc;\t// From c3_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire\t\t\tc3_txo_launch_ack_tlc;\t// From link_txo_arbiter of link_txo_arbiter.v
+   wire\t\t\tc3_txo_launch_req_tlc;\t// From c3_link_txo_mesh_channel of link_txo_mesh_channel.v
+   wire\t\t\tc3_txo_rotate_dis;\t// From c3_link_txo_mesh_channel of link_txo_mesh_channel.v
+   // End of automatics
+
+   // ##########
+   // # WIRES
+   // ##########
+
+   wire [1:0] \t     c0_txo_cid;//channel 0 ID
+   wire [1:0] \t     c1_txo_cid;//channel 1 ID
+   wire [1:0] \t     c2_txo_cid;//channel 2 ID
+   wire [1:0] \t     c3_txo_cid;//channel 3 ID
+
+   // #####################################
+   // # Transmitter channels instantiation
+   // #####################################
+
+   assign c0_txo_cid[1:0] = 2\'b00;
+   assign c1_txo_cid[1:0] = 2\'b01;
+   assign c2_txo_cid[1:0] = 2\'b10;
+   assign c3_txo_cid[1:0] = 2\'b11;
+
+   // ################################
+   // # Transmit buffer instantiation
+   // ################################
+
+   /*link_txo_buffer AUTO_TEMPLATE(
+                                  .txo_data_even (txo_wr_data_even[]),
+                                  .txo_data_odd  (txo_wr_data_odd[]),
+                                  .txo_frame     (txo_wr_frame),
+                                   );
+    */
+   link_txo_buffer link_txo_buffer(/*AUTOINST*/
+\t\t\t\t   // Outputs
+\t\t\t\t   .txo_data_even\t(txo_wr_data_even[LW-1:0]), // Templated
+\t\t\t\t   .txo_data_odd\t(txo_wr_data_odd[LW-1:0]), // Templated
+\t\t\t\t   .txo_frame\t\t(txo_wr_frame),\t // Templated
+\t\t\t\t   // Inputs
+\t\t\t\t   .c0_tran_frame_tlc\t(c0_tran_frame_tlc),
+\t\t\t\t   .c0_tran_byte_even_tlc(c0_tran_byte_even_tlc[LW-1:0]),
+\t\t\t\t   .c0_tran_byte_odd_tlc(c0_tran_byte_odd_tlc[LW-1:0]),
+\t\t\t\t   .c1_tran_frame_tlc\t(c1_tran_frame_tlc),
+\t\t\t\t   .c1_tran_byte_even_tlc(c1_tran_byte_even_tlc[LW-1:0]),
+\t\t\t\t   .c1_tran_byte_odd_tlc(c1_tran_byte_odd_tlc[LW-1:0]),
+\t\t\t\t   .c2_tran_frame_tlc\t(c2_tran_frame_tlc),
+\t\t\t\t   .c2_tran_byte_even_tlc(c2_tran_byte_even_tlc[LW-1:0]),
+\t\t\t\t   .c2_tran_byte_odd_tlc(c2_tran_byte_odd_tlc[LW-1:0]),
+\t\t\t\t   .c3_tran_frame_tlc\t(c3_tran_frame_tlc),
+\t\t\t\t   .c3_tran_byte_even_tlc(c3_tran_byte_even_tlc[LW-1:0]),
+\t\t\t\t   .c3_tran_byte_odd_tlc(c3_tran_byte_odd_tlc[LW-1:0])); 
+
+   // #########################
+   // # Arbiter instantiation
+   // #########################
+
+   /*link_txo_arbiter AUTO_TEMPLATE(
+                                  .txo_wait            (txo_wr_wait),
+                                  .txo_wait_int        (txo_wr_wait_int),
+                                  .txo_launch_req_tlc  (txo_wr_launch_req_tlc),
+                                  .txo_rotate_dis_tlc  (txo_wr_rotate_dis),
+                                   );
+    */
+   link_txo_arbiter link_txo_arbiter (.c1_txo_launch_req_tlc(1\'b0),
+\t\t\t\t      .c1_txo_rotate_dis(1\'b0),
+\t\t\t\t      .c2_txo_launch_req_tlc(1\'b0),
+\t\t\t\t      .c2_txo_rotate_dis(1\'b0),
+\t\t\t\t      .c3_txo_launch_req_tlc(1\'b0),
+\t\t\t\t      .c3_txo_rotate_dis(1\'b0),
+\t\t\t\t      /*AUTOINST*/
+\t\t\t\t      // Outputs
+\t\t\t\t      .txo_launch_req_tlc(txo_wr_launch_req_tlc), // Templated
+\t\t\t\t      .txo_rotate_dis_tlc(txo_wr_rotate_dis), // Templated
+\t\t\t\t      .c0_txo_launch_ack_tlc(c0_txo_launch_ack_tlc),
+\t\t\t\t      .c1_txo_launch_ack_tlc(c1_txo_launch_ack_tlc),
+\t\t\t\t      .c2_txo_launch_ack_tlc(c2_txo_launch_ack_tlc),
+\t\t\t\t      .c3_txo_launch_ack_tlc(c3_txo_launch_ack_tlc),
+\t\t\t\t      // Inputs
+\t\t\t\t      .txo_lclk\t\t(txo_lclk),
+\t\t\t\t      .reset\t\t(reset),
+\t\t\t\t      .txo_wait\t\t(txo_wr_wait),\t // Templated
+\t\t\t\t      .txo_wait_int\t(txo_wr_wait_int), // Templated
+\t\t\t\t      .c0_txo_launch_req_tlc(c0_txo_launch_req_tlc),
+\t\t\t\t      .c0_txo_rotate_dis(c0_txo_rotate_dis));
+
+   // #########################
+   // # Channels instantiation
+   // #########################
+
+   /*link_txo_mesh_channel AUTO_TEMPLATE (
+          .cclk\t         (@""(substring vl-cell-name  0 2)""_clk_in),
+          .cclk_en       (1\'b1),
+          .txo_rd\t (1\'b0),
+\t  .txo_lclk      (txo_lclk),
+\t  .reset         (reset),
+          .cfg_burst_dis (cfg_burst_dis),
+          .txo_rotate_dis_tlc (@""(substring vl-cell-name  0 2)""_txo_rotate_dis),
+          .emesh_\\(.*\\)  (@""(substring vl-cell-name  0 2)""_emesh_\\1[]),
+          .\\(.*\\)        (@""(substring vl-cell-name  0 2)""_\\1[]),
+          .ext_yid_k     (ext_yid_k[]),
+\t  .ext_xid_k     (ext_xid_k[]),
+          .who_am_i      (who_am_i[]),
+                                     );
+    */
+
+   //# channel 0 (emesh + mesh for external corners + mesh for multicast)
+   link_txo_mesh_channel c0_link_txo_mesh_channel(.cfg_multicast_dis (cfg_multicast_dis),
+\t\t\t\t\t\t  /*AUTOINST*/
+\t\t\t\t\t\t  // Outputs
+\t\t\t\t\t\t  .emesh_wait_out\t(c0_emesh_wait_out), // Templated
+\t\t\t\t\t\t  .mesh_wait_out\t(c0_mesh_wait_out), // Templated
+\t\t\t\t\t\t  .txo_launch_req_tlc\t(c0_txo_launch_req_tlc), // Templated
+\t\t\t\t\t\t  .txo_rotate_dis_tlc\t(c0_txo_rotate_dis), // Templated
+\t\t\t\t\t\t  .tran_frame_tlc\t(c0_tran_frame_tlc), // Templated
+\t\t\t\t\t\t  .tran_byte_even_tlc\t(c0_tran_byte_even_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t  .tran_byte_odd_tlc\t(c0_tran_byte_odd_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t  // Inputs
+\t\t\t\t\t\t  .cclk\t\t\t(c0_clk_in),\t // Templated
+\t\t\t\t\t\t  .cclk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t  .txo_lclk\t\t(txo_lclk),\t // Templated
+\t\t\t\t\t\t  .reset\t\t(reset),\t // Templated
+\t\t\t\t\t\t  .ext_yid_k\t\t(ext_yid_k[3:0]), // Templated
+\t\t\t\t\t\t  .ext_xid_k\t\t(ext_xid_k[3:0]), // Templated
+\t\t\t\t\t\t  .who_am_i\t\t(who_am_i[3:0]), // Templated
+\t\t\t\t\t\t  .txo_rd\t\t(1\'b0),\t\t // Templated
+\t\t\t\t\t\t  .txo_cid\t\t(c0_txo_cid[1:0]), // Templated
+\t\t\t\t\t\t  .cfg_burst_dis\t(cfg_burst_dis), // Templated
+\t\t\t\t\t\t  .emesh_tran_in\t(c0_emesh_tran_in[2*LW-1:0]), // Templated
+\t\t\t\t\t\t  .emesh_frame_in\t(c0_emesh_frame_in), // Templated
+\t\t\t\t\t\t  .mesh_access_in\t(c0_mesh_access_in), // Templated
+\t\t\t\t\t\t  .mesh_write_in\t(c0_mesh_write_in), // Templated
+\t\t\t\t\t\t  .mesh_dstaddr_in\t(c0_mesh_dstaddr_in[AW-1:0]), // Templated
+\t\t\t\t\t\t  .mesh_srcaddr_in\t(c0_mesh_srcaddr_in[AW-1:0]), // Templated
+\t\t\t\t\t\t  .mesh_data_in\t\t(c0_mesh_data_in[DW-1:0]), // Templated
+\t\t\t\t\t\t  .mesh_datamode_in\t(c0_mesh_datamode_in[1:0]), // Templated
+\t\t\t\t\t\t  .mesh_ctrlmode_in\t(c0_mesh_ctrlmode_in[3:0]), // Templated
+\t\t\t\t\t\t  .txo_launch_ack_tlc\t(c0_txo_launch_ack_tlc)); // Templated
+
+   //# channel 3 (emesh + mesh for external corners)
+   link_txo_mesh_channel c3_link_txo_mesh_channel(.cfg_multicast_dis (1\'b1),
+\t\t\t\t\t\t  /*AUTOINST*/
+\t\t\t\t\t\t  // Outputs
+\t\t\t\t\t\t  .emesh_wait_out\t(c3_emesh_wait_out), // Templated
+\t\t\t\t\t\t  .mesh_wait_out\t(c3_mesh_wait_out), // Templated
+\t\t\t\t\t\t  .txo_launch_req_tlc\t(c3_txo_launch_req_tlc), // Templated
+\t\t\t\t\t\t  .txo_rotate_dis_tlc\t(c3_txo_rotate_dis), // Templated
+\t\t\t\t\t\t  .tran_frame_tlc\t(c3_tran_frame_tlc), // Templated
+\t\t\t\t\t\t  .tran_byte_even_tlc\t(c3_tran_byte_even_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t  .tran_byte_odd_tlc\t(c3_tran_byte_odd_tlc[LW-1:0]), // Templated
+\t\t\t\t\t\t  // Inputs
+\t\t\t\t\t\t  .cclk\t\t\t(c3_clk_in),\t // Templated
+\t\t\t\t\t\t  .cclk_en\t\t(1\'b1),\t\t // Templated
+\t\t\t\t\t\t  .txo_lclk\t\t(txo_lclk),\t // Templated
+\t\t\t\t\t\t  .reset\t\t(reset),\t // Templated
+\t\t\t\t\t\t  .ext_yid_k\t\t(ext_yid_k[3:0]), // Templated
+\t\t\t\t\t\t  .ext_xid_k\t\t(ext_xid_k[3:0]), // Templated
+\t\t\t\t\t\t  .who_am_i\t\t(who_am_i[3:0]), // Templated
+\t\t\t\t\t\t  .txo_rd\t\t(1\'b0),\t\t // Templated
+\t\t\t\t\t\t  .txo_cid\t\t(c3_txo_cid[1:0]), // Templated
+\t\t\t\t\t\t  .cfg_burst_dis\t(cfg_burst_dis), // Templated
+\t\t\t\t\t\t  .emesh_tran_in\t(c3_emesh_tran_in[2*LW-1:0]), // Templated
+\t\t\t\t\t\t  .emesh_frame_in\t(c3_emesh_frame_in), // Templated
+\t\t\t\t\t\t  .mesh_access_in\t(c3_mesh_access_in), // Templated
+\t\t\t\t\t\t  .mesh_write_in\t(c3_mesh_write_in), // Templated
+\t\t\t\t\t\t  .mesh_dstaddr_in\t(c3_mesh_dstaddr_in[AW-1:0]), // Templated
+\t\t\t\t\t\t  .mesh_srcaddr_in\t(c3_mesh_srcaddr_in[AW-1:0]), // Templated
+\t\t\t\t\t\t  .mesh_data_in\t\t(c3_mesh_data_in[DW-1:0]), // Templated
+\t\t\t\t\t\t  .mesh_datamode_in\t(c3_mesh_datamode_in[1:0]), // Templated
+\t\t\t\t\t\t  .mesh_ctrlmode_in\t(c3_mesh_ctrlmode_in[3:0]), // Templated
+\t\t\t\t\t\t  .txo_launch_ack_tlc\t(c3_txo_launch_ack_tlc)); // Templated
+
+ 
+endmodule // link_txo_wr
+module _MAGMA_CELL_FF_ (DATA, CLOCK, CLEAR, PRESET, SLAVE_CLOCK, OUT);
+
+   input DATA;
+   input CLOCK;
+   input CLEAR;
+   input PRESET;
+   input SLAVE_CLOCK;
+   output OUT;
+   reg    OUT;
+
+   // synopsys one_hot ""PRESET, CLEAR""
+   always @(posedge CLOCK or posedge PRESET or posedge CLEAR)
+   if (CLEAR)
+     OUT <= 1\'b0;
+   else
+     if (PRESET)
+       OUT <= 1\'b1;
+     else
+       OUT <= DATA;
+endmodule
+
+// Entity:dffnq Model:DFFNQX3A12TR Library:cmos10sf_5_20_02_scadv12
+module DFFNQX3A12TR (CKN, D, Q);
+  input CKN, D;
+  output Q;
+  supply0 N7;
+  _MAGMA_CELL_FF_ C1 (.DATA(D), .CLOCK(CKN__br_in_not), .CLEAR(N7), .PRESET(N7), .SLAVE_CLOCK(N7), .OUT(Q));
+  not (CKN__br_in_not, CKN);
+endmodule // DFFNQX3A12TR
+
+module DFFQX4A12TR (CK, D, Q);
+  input CK, D;
+  output Q;
+  supply0 N6;
+  _MAGMA_CELL_FF_ C1 (.DATA(D), .CLOCK(CK), .CLEAR(N6), .PRESET(N6), .SLAVE_CLOCK(N6), .OUT(Q));
+endmodule
+
+module MX2X4A12TR (A, B, S0, Y);
+  input A, B, S0;
+  output Y;
+  wire N3, N6;
+  and C1 (N3, S0, B);
+  and C3 (N6, S0__br_in_not, A);
+  not (S0__br_in_not, S0);
+  or C4 (Y, N3, N6);
+endmodule
+
+
+
+
+
+
+
+/*
+ Copyright (C) 2014 Adapteva, Inc.
+ 
+ Contributed by Roman Trogan <roman@adapteva.com>
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"
+module IBUFGDS (/*AUTOARG*/
+   // Outputs
+   O,
+   // Inputs
+   I, IB
+   );
+
+   parameter DIFF_TERM=0;
+   parameter IOSTANDARD=0;
+
+   input I;
+   input IB;
+   output O;
+
+   assign O = I & ~IB;
+   
+   
+endmodule // IBUFGDS
+
+"
+"/*Converts an emesh bundle into a 104 bit packet*/
+module packet2emesh(/*AUTOARG*/
+   // Outputs
+   access_out, write_out, datamode_out, ctrlmode_out, dstaddr_out,
+   data_out, srcaddr_out,
+   // Inputs
+   packet_in
+   );
+
+   parameter AW=32;
+   parameter DW=32;
+   parameter PW=104;
+   
+   //Emesh signal bundle
+   output \t    access_out;
+   output \t    write_out;   
+   output [1:0]     datamode_out;
+   output [3:0]     ctrlmode_out;   
+   output [AW-1:0]  dstaddr_out;
+   output [DW-1:0]  data_out;   
+   output [AW-1:0]  srcaddr_out;   
+   
+   //Output packet
+   input [PW-1:0]   packet_in;
+
+   assign access_out          = packet_in[0];
+   assign write_out           = packet_in[1];
+   assign datamode_out[1:0]   = packet_in[3:2];
+   assign ctrlmode_out[3:0]   = packet_in[7:4];
+   assign dstaddr_out[AW-1:0] = packet_in[39:8];
+   assign data_out[AW-1:0]    = packet_in[71:40];
+   assign srcaddr_out[AW-1:0] = packet_in[103:72];
+     
+endmodule // emesh2packet
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"module fifo_full_block (/*AUTOARG*/
+   // Outputs
+   wr_fifo_full, wr_fifo_almost_full, wr_addr, wr_gray_pointer,
+   // Inputs
+   reset, wr_clk, wr_rd_gray_pointer, wr_write
+   );
+
+   parameter AW   = 2; // Number of bits to access all the entries 
+
+   //##########
+   //# INPUTS
+   //##########
+   input           reset;
+   input           wr_clk;
+
+   input [AW:0]    wr_rd_gray_pointer;//synced from read domain
+   input           wr_write;
+   
+   //###########
+   //# OUTPUTS
+   //###########
+   output           wr_fifo_full;
+   output           wr_fifo_almost_full;
+   
+   output [AW-1:0]  wr_addr;
+   output [AW:0]    wr_gray_pointer;//for read domain
+
+   //#########
+   //# REGS
+   //#########
+   reg [AW:0]      wr_gray_pointer;
+   reg [AW:0]      wr_binary_pointer;
+   reg             wr_fifo_full;
+
+   //##########
+   //# WIRES
+   //##########
+   wire            wr_fifo_full_next;
+   wire [AW:0]     wr_gray_next;
+   wire [AW:0]     wr_binary_next;
+   
+   wire \t   wr_fifo_almost_full_next;
+   reg \t\t   wr_fifo_almost_full;
+   
+   //Counter States
+   always @(posedge wr_clk or posedge reset)
+     if(reset)
+       begin
+\t  wr_binary_pointer[AW:0]     <= {(AW+1){1'b0}};
+\t  wr_gray_pointer[AW:0]       <= {(AW+1){1'b0}};
+       end
+     else if(wr_write)
+       begin
+\t  wr_binary_pointer[AW:0]     <= wr_binary_next[AW:0];\t  
+\t  wr_gray_pointer[AW:0]       <= wr_gray_next[AW:0];\t  
+       end
+
+   //Write Address
+   assign wr_addr[AW-1:0]       = wr_binary_pointer[AW-1:0];
+
+   //Updating binary pointer
+   assign wr_binary_next[AW:0]  = wr_binary_pointer[AW:0] + 
+\t\t\t\t  {{(AW){1'b0}},wr_write};
+
+   //Gray Pointer Conversion (for more reliable synchronization)!
+   assign wr_gray_next[AW:0]    = {1'b0,wr_binary_next[AW:1]} ^ 
+\t\t\t\t  wr_binary_next[AW:0];
+
+   //FIFO full indication
+   assign wr_fifo_full_next =
+\t\t\t (wr_gray_next[AW-2:0] == wr_rd_gray_pointer[AW-2:0]) &
+\t\t\t (wr_gray_next[AW]     ^  wr_rd_gray_pointer[AW])     &
+\t\t\t (wr_gray_next[AW-1]   ^  wr_rd_gray_pointer[AW-1]);
+
+ 
+   always @ (posedge wr_clk or posedge reset)
+     if(reset)
+       wr_fifo_full <= 1'b0;
+     else
+       wr_fifo_full <=wr_fifo_full_next;
+
+
+   //FIFO almost full
+   assign wr_fifo_almost_full_next =
+\t\t\t (wr_gray_next[AW-3:0] == wr_rd_gray_pointer[AW-3:0]) &
+\t\t\t (wr_gray_next[AW]     ^  wr_rd_gray_pointer[AW])     &
+\t\t\t (wr_gray_next[AW-1]   ^  wr_rd_gray_pointer[AW-1])   &
+\t\t\t (wr_gray_next[AW-2]   ^  wr_rd_gray_pointer[AW-2]);
+  
+   always @ (posedge wr_clk or posedge reset)
+     if(reset)
+       wr_fifo_almost_full <= 1'b0;
+     else
+       wr_fifo_almost_full <=wr_fifo_almost_full_next;
+
+endmodule // fifo_full_block
+
+   
+\t\t 
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"`include ""../../elink/hdl/elink_constants.v""
+module fifo_async 
+   (/*AUTOARG*/
+   // Outputs
+   full, prog_full, dout, empty, valid,
+   // Inputs
+   wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
+   );
+   
+   parameter DW    = 104;        //FIFO width
+   parameter DEPTH = 16;          //FIFO depth
+     
+   //##########
+   //# RESET/CLOCK
+   //##########
+   input \t   wr_rst;    //write reset
+   input \t   rd_rst;    //read reset 
+   input           wr_clk;    //write clock   
+   input           rd_clk;    //read clock   
+
+   //##########
+   //# FIFO WRITE
+   //##########
+   input             wr_en;   
+   input [DW-1:0] din;
+   output            full;
+   output            prog_full;
+
+   //###########
+   //# FIFO READ
+   //###########
+   input \t      rd_en;
+   output [DW-1:0] dout;
+   output \t      empty;
+   output \t      valid;
+
+   
+`ifdef TARGET_CLEAN
+
+   fifo_async_model fifo_model (.full\t\t(),
+\t\t\t\t.prog_full\t(prog_full),
+\t\t\t\t.almost_full\t(full),
+\t\t\t\t/*AUTOINST*/
+\t\t\t\t// Outputs
+\t\t\t\t.dout\t\t(dout[DW-1:0]),
+\t\t\t\t.empty\t\t(empty),
+\t\t\t\t.valid\t\t(valid),
+\t\t\t\t// Inputs
+\t\t\t\t.wr_rst\t\t(wr_rst),
+\t\t\t\t.rd_rst\t\t(rd_rst),
+\t\t\t\t.wr_clk\t\t(wr_clk),
+\t\t\t\t.rd_clk\t\t(rd_clk),
+\t\t\t\t.wr_en\t\t(wr_en),
+\t\t\t\t.din\t\t(din[DW-1:0]),
+\t\t\t\t.rd_en\t\t(rd_en));
+   
+`elsif TARGET_XILINX   
+   generate
+      if((DW==104) & (DEPTH==16))
+\tbegin
+\t   fifo_async_104x16 fifo_async_104x16 (.full\t\t(),
+\t\t\t\t\t\t.prog_full\t(prog_full),
+\t\t\t\t\t\t.almost_full\t(full),
+\t\t\t\t\t\t/*AUTOINST*/
+\t\t\t\t\t\t// Outputs
+\t\t\t\t\t\t.dout\t\t(dout[DW-1:0]),
+\t\t\t\t\t\t.empty\t\t(empty),
+\t\t\t\t\t\t.valid\t\t(valid),
+\t\t\t\t\t\t// Inputs
+\t\t\t\t\t\t.wr_rst\t\t(wr_rst),
+\t\t\t\t\t\t.rd_rst\t\t(rd_rst),
+\t\t\t\t\t\t.wr_clk\t\t(wr_clk),
+\t\t\t\t\t\t.rd_clk\t\t(rd_clk),
+\t\t\t\t\t\t.wr_en\t\t(wr_en),
+\t\t\t\t\t\t.din\t\t(din[DW-1:0]),
+\t\t\t\t\t\t.rd_en\t\t(rd_en));\t   
+\tend
+      else if((DW==104) & (DEPTH==32))
+\tbegin
+\t   fifo_async_104x32 fifo_async_104x32 (.full\t\t(),
+\t\t\t\t\t\t.prog_full\t(prog_full),
+\t\t\t\t\t\t.almost_full\t(full),
+\t\t\t\t\t\t/*AUTOINST*/
+\t\t\t\t\t\t// Outputs
+\t\t\t\t\t\t.dout\t\t(dout[DW-1:0]),
+\t\t\t\t\t\t.empty\t\t(empty),
+\t\t\t\t\t\t.valid\t\t(valid),
+\t\t\t\t\t\t// Inputs
+\t\t\t\t\t\t.wr_rst\t\t(wr_rst),
+\t\t\t\t\t\t.rd_rst\t\t(rd_rst),
+\t\t\t\t\t\t.wr_clk\t\t(wr_clk),
+\t\t\t\t\t\t.rd_clk\t\t(rd_clk),
+\t\t\t\t\t\t.wr_en\t\t(wr_en),
+\t\t\t\t\t\t.din\t\t(din[DW-1:0]),
+\t\t\t\t\t\t.rd_en\t\t(rd_en));
+\t   
+\tend   
+\t      
+   endgenerate
+   
+      
+`endif // !`elsif TARGET_XILINX
+   
+   
+endmodule // fifo_async
+// Local Variables:
+// verilog-library-directories:(""."" ""../../xilibs/hdl"")
+// End:
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"
+module toggle2pulse(/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in, reset
+   );
+   
+   //clocks
+   input  clk; 
+   
+   input  in;   
+   output out;
+
+   //reset
+   input  reset;
+   reg \t  out_reg;
+         
+   always @ (posedge clk)
+     if(reset)
+       out_reg <= 1'b0;
+     else
+       out_reg <= in;
+      
+   assign out = in ^ out_reg;
+
+endmodule 
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"//`timescale 1 ns / 100 ps
+module dv_ecfg();
+
+   //Stimulus to drive
+   reg        clk;
+   reg        reset;
+   reg        mi_access;
+   reg [19:0]  mi_addr;
+   reg [31:0] mi_data_in;
+   reg \t      mi_write;
+   reg [1:0]  test_state;
+   
+   //Reset
+   initial
+     begin
+\t$display($time, "" << Starting the Simulation >>"");\t
+\t#0
+        clk              = 1\'b0;    // at time 0
+\treset            = 1\'b1;    // reset is active
+\tmi_write         = 1\'b0;
+\tmi_access        = 1\'b0;
+\tmi_addr[19:0]    = 20\'hf0340;
+\tmi_data_in[31:0] = 32\'h0;
+\ttest_state[1:0]  = 2\'b00;
+\t#100 
+\treset    = 1\'b0;    // at time 100 release reset
+\t#100
+\tmi_write   = 1\'b1;
+\tmi_access  = 1\'b1;
+\t#10000\t  
+\t  $finish;
+     end
+   
+   //Clock
+   always
+     #10 clk = ~clk;
+
+   //Pattern generator
+   always @ (posedge clk)
+     if(mi_access)
+       case(test_state[1:0])
+\t 2\'b00:
+\t   if(~done)
+\t     begin
+\t\tmi_addr[19:0]    <= mi_addr[19:0]+20\'h4;
+\t\tmi_data_in[5:0] <= mi_data_in[5:0]+1\'b1;
+\t     end
+\t   else
+\t     begin
+\t\ttest_state      <= 2\'b01;\t    
+\t\tmi_addr[19:0]   <= 20\'hf0340;
+\t\tmi_write        <= 1\'b0;
+\t     end
+\t 2\'b01:
+\t   if(~done)
+\t     begin
+\t\tmi_addr[19:0]    <= mi_addr[19:0]+20\'h4;
+\t\tmi_data_in[5:0]  <= 32\'hffffffff;
+\t     end
+\t   else
+\t     test_state <= 2\'b01;\t    
+       endcase// case (test_state[1:0])
+   
+   wire done =  (mi_addr[19:0]==20\'hf0360);
+   
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [3:0]\t\tecfg_cclk_div;\t\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_cclk_en;\t\t// From ecfg of ecfg.v
+   wire [3:0]\t\tecfg_cclk_pllcfg;\t// From ecfg of ecfg.v
+   wire [11:0]\t\tecfg_coreid;\t\t// From ecfg of ecfg.v
+   wire [11:0]\t\tecfg_dataout;\t\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_rx_enable;\t\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_rx_gpio_mode;\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_rx_loopback_mode;\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_rx_mmu_mode;\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_sw_reset;\t\t// From ecfg of ecfg.v
+   wire [3:0]\t\tecfg_tx_clkdiv;\t\t// From ecfg of ecfg.v
+   wire [3:0]\t\tecfg_tx_ctrl_mode;\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_tx_enable;\t\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_tx_gpio_mode;\t// From ecfg of ecfg.v
+   wire\t\t\tecfg_tx_mmu_mode;\t// From ecfg of ecfg.v
+   wire [31:0]\t\tmi_data_out;\t\t// From ecfg of ecfg.v
+   // End of automatics
+   
+   //DUT
+   ecfg ecfg(.param_coreid\t\t(12\'h808),
+\t     /*AUTOINST*/
+\t     // Outputs
+\t     .mi_data_out\t\t(mi_data_out[31:0]),
+\t     .ecfg_sw_reset\t\t(ecfg_sw_reset),
+\t     .ecfg_tx_enable\t\t(ecfg_tx_enable),
+\t     .ecfg_tx_mmu_mode\t\t(ecfg_tx_mmu_mode),
+\t     .ecfg_tx_gpio_mode\t\t(ecfg_tx_gpio_mode),
+\t     .ecfg_tx_ctrl_mode\t\t(ecfg_tx_ctrl_mode[3:0]),
+\t     .ecfg_tx_clkdiv\t\t(ecfg_tx_clkdiv[3:0]),
+\t     .ecfg_rx_enable\t\t(ecfg_rx_enable),
+\t     .ecfg_rx_mmu_mode\t\t(ecfg_rx_mmu_mode),
+\t     .ecfg_rx_gpio_mode\t\t(ecfg_rx_gpio_mode),
+\t     .ecfg_rx_loopback_mode\t(ecfg_rx_loopback_mode),
+\t     .ecfg_cclk_en\t\t(ecfg_cclk_en),
+\t     .ecfg_cclk_div\t\t(ecfg_cclk_div[3:0]),
+\t     .ecfg_cclk_pllcfg\t\t(ecfg_cclk_pllcfg[3:0]),
+\t     .ecfg_coreid\t\t(ecfg_coreid[11:0]),
+\t     .ecfg_dataout\t\t(ecfg_dataout[11:0]),
+\t     // Inputs
+\t     .clk\t\t\t(clk),
+\t     .reset\t\t\t(reset),
+\t     .mi_access\t\t\t(mi_access),
+\t     .mi_write\t\t\t(mi_write),
+\t     .mi_addr\t\t\t(mi_addr[19:0]),
+\t     .mi_data_in\t\t(mi_data_in[31:0]));
+
+
+   //Waveform dump
+   initial
+     begin
+\t$dumpfile(""test.vcd"");
+\t$dumpvars(0, dv_ecfg);
+     end
+
+   
+endmodule // dv_ecfg
+// Local Variables:
+// verilog-library-directories:(""."" ""../hdl"" ""../../memory/hdl "")
+// End:
+
+"
+"module etx_fifo(/*AUTOARG*/
+   // Outputs
+   txrd_wait, txwr_wait, txrr_wait, etx_cfg_access, etx_cfg_packet,
+   txrd_fifo_access, txrd_fifo_packet, txrr_fifo_access,
+   txrr_fifo_packet, txwr_fifo_access, txwr_fifo_packet,
+   // Inputs
+   etx_reset, sys_reset, sys_clk, tx_lclk_div4, txrd_access,
+   txrd_packet, txwr_access, txwr_packet, txrr_access, txrr_packet,
+   etx_cfg_wait, txrd_fifo_wait, txrr_fifo_wait, txwr_fifo_wait
+   );
+
+   parameter AW      = 32;
+   parameter DW      = 32;
+   parameter PW      = 104;
+   parameter RFAW    = 6;
+   parameter ID      = 12\'h000;
+   
+   //Clocks,reset,config
+   input          etx_reset;
+   input          sys_reset;
+   input \t  sys_clk;   
+   input \t  tx_lclk_div4;\t  // slow speed parallel clock
+      
+   //Read Request Channel Input
+   input \t  txrd_access;
+   input [PW-1:0] txrd_packet;
+   output \t  txrd_wait;
+   
+   //Write Channel Input
+   input \t  txwr_access;
+   input [PW-1:0] txwr_packet;
+   output \t  txwr_wait;
+   
+   //Read Response Channel Input
+   input \t  txrr_access;
+   input [PW-1:0] txrr_packet;
+   output \t  txrr_wait;
+
+   //Configuration Interface (for ERX)
+   output \t   etx_cfg_access;
+   output [PW-1:0] etx_cfg_packet;
+   input \t   etx_cfg_wait;
+   
+   output \t   txrd_fifo_access;
+   output [PW-1:0] txrd_fifo_packet;
+   input \t   txrd_fifo_wait;
+   
+   output \t   txrr_fifo_access;
+   output [PW-1:0] txrr_fifo_packet;
+   input \t   txrr_fifo_wait;
+   
+   output \t   txwr_fifo_access;
+   output [PW-1:0] txwr_fifo_packet;
+   input \t   txwr_fifo_wait;
+
+
+   
+   /*AUTOOUTPUT*/
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+
+   
+   /************************************************************/
+   /*FIFOs                                                     */
+   /************************************************************/
+   //TODO: Minimize depth and width
+
+   /*fifo_cdc  AUTO_TEMPLATE (
+\t\t\t       // Outputs
+                               .access_out (@""(substring vl-cell-name  0 4)""_fifo_access),
+\t\t\t       .packet_out (@""(substring vl-cell-name  0 4)""_fifo_packet[PW-1:0]),
+                               .wait_out   (@""(substring vl-cell-name  0 4)""_wait),
+                               .wait_in   (@""(substring vl-cell-name  0 4)""_fifo_wait),
+    \t\t\t       .clk_out\t   (tx_lclk_div4),
+                               .clk_in\t   (sys_clk),
+                               .access_in  (@""(substring vl-cell-name  0 4)""_access),
+                               .rd_en      (@""(substring vl-cell-name  0 4)""_fifo_read),
+\t\t\t       .reset_in   (sys_reset),
+                               .reset_out  (etx_reset),
+                               .packet_in  (@""(substring vl-cell-name  0 4)""_packet[PW-1:0]),
+    );
+    */
+
+   //Write fifo (from slave)
+   fifo_cdc #(.DW(104), .DEPTH(32)) txwr_fifo(
+\t\t\t                  /*AUTOINST*/
+\t\t\t\t\t\t // Outputs
+\t\t\t\t\t\t .wait_out\t\t(txwr_wait),\t // Templated
+\t\t\t\t\t\t .access_out\t\t(txwr_fifo_access), // Templated
+\t\t\t\t\t\t .packet_out\t\t(txwr_fifo_packet[PW-1:0]), // Templated
+\t\t\t\t\t\t // Inputs
+\t\t\t\t\t\t .clk_in\t\t(sys_clk),\t // Templated
+\t\t\t\t\t\t .reset_in\t\t(sys_reset),\t // Templated
+\t\t\t\t\t\t .access_in\t\t(txwr_access),\t // Templated
+\t\t\t\t\t\t .packet_in\t\t(txwr_packet[PW-1:0]), // Templated
+\t\t\t\t\t\t .clk_out\t\t(tx_lclk_div4),\t // Templated
+\t\t\t\t\t\t .reset_out\t\t(etx_reset),\t // Templated
+\t\t\t\t\t\t .wait_in\t\t(txwr_fifo_wait)); // Templated
+   
+   //Read request fifo (from slave)
+   fifo_cdc  #(.DW(104), .DEPTH(32)) txrd_fifo(
+\t\t\t\t             /*AUTOINST*/
+\t\t\t\t\t\t  // Outputs
+\t\t\t\t\t\t  .wait_out\t\t(txrd_wait),\t // Templated
+\t\t\t\t\t\t  .access_out\t\t(txrd_fifo_access), // Templated
+\t\t\t\t\t\t  .packet_out\t\t(txrd_fifo_packet[PW-1:0]), // Templated
+\t\t\t\t\t\t  // Inputs
+\t\t\t\t\t\t  .clk_in\t\t(sys_clk),\t // Templated
+\t\t\t\t\t\t  .reset_in\t\t(sys_reset),\t // Templated
+\t\t\t\t\t\t  .access_in\t\t(txrd_access),\t // Templated
+\t\t\t\t\t\t  .packet_in\t\t(txrd_packet[PW-1:0]), // Templated
+\t\t\t\t\t\t  .clk_out\t\t(tx_lclk_div4),\t // Templated
+\t\t\t\t\t\t  .reset_out\t\t(etx_reset),\t // Templated
+\t\t\t\t\t\t  .wait_in\t\t(txrd_fifo_wait)); // Templated
+   
+
+  
+   //Read response fifo (from master)
+   fifo_cdc  #(.DW(104), .DEPTH(32)) txrr_fifo(
+\t\t\t\t\t    
+\t\t\t\t\t     /*AUTOINST*/
+\t\t\t\t\t\t // Outputs
+\t\t\t\t\t\t .wait_out\t\t(txrr_wait),\t // Templated
+\t\t\t\t\t\t .access_out\t\t(txrr_fifo_access), // Templated
+\t\t\t\t\t\t .packet_out\t\t(txrr_fifo_packet[PW-1:0]), // Templated
+\t\t\t\t\t\t // Inputs
+\t\t\t\t\t\t .clk_in\t\t(sys_clk),\t // Templated
+\t\t\t\t\t\t .reset_in\t\t(sys_reset),\t // Templated
+\t\t\t\t\t\t .access_in\t\t(txrr_access),\t // Templated
+\t\t\t\t\t\t .packet_in\t\t(txrr_packet[PW-1:0]), // Templated
+\t\t\t\t\t\t .clk_out\t\t(tx_lclk_div4),\t // Templated
+\t\t\t\t\t\t .reset_out\t\t(etx_reset),\t // Templated
+\t\t\t\t\t\t .wait_in\t\t(txrr_fifo_wait)); // Templated
+  
+
+   
+endmodule // elink
+// Local Variables:
+// verilog-library-directories:(""."" ""../../emmu/hdl"" ""../../memory/hdl"" ""../../edma/hdl/"")
+// End:
+
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+ 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"// ###############################################################
+// # FUNCTION: Synchronous clock divider that divides by integer
+// ############################################################### 
+
+module clock_divider(/*AUTOARG*/
+   // Outputs
+   clkout,
+   // Inputs
+   clkin, divcfg, reset
+   );
+
+   input       clkin;    // Input clock
+   input [3:0] divcfg;   // Divide factor (1-128)
+   input       reset;    // Counter init
+   output      clkout;   // Divided clock phase aligned with clkin 
+
+   reg        clkout_reg;
+   reg [7:0]  counter;   
+   reg [7:0]  divcfg_dec;
+   reg [3:0]  divcfg_reg;
+   
+   wire       div_bp;   
+   wire       posedge_match;
+   wire       negedge_match;  
+   
+   // ###################
+   // # Decode divcfg
+   // ###################
+
+   always @ (divcfg[3:0])
+     casez (divcfg[3:0])
+\t  4'b0001 : divcfg_dec[7:0] = 8'b00000010;  // Divide by 2
+\t  4'b0010 : divcfg_dec[7:0] = 8'b00000100;  // Divide by 4
+\t  4'b0011 : divcfg_dec[7:0] = 8'b00001000;  // Divide by 8
+\t  4'b0100 : divcfg_dec[7:0] = 8'b00010000;  // Divide by 16
+          4'b0101 : divcfg_dec[7:0] = 8'b00100000;  // Divide by 32
+          4'b0110 : divcfg_dec[7:0] = 8'b01000000;  // Divide by 64
+          4'b0111 : divcfg_dec[7:0] = 8'b10000000;  // Divide by 128
+\t  default : divcfg_dec[7:0] = 8'b00000000;   // others
+\tendcase
+   
+   always @ (posedge clkin or posedge reset)
+     if(reset)
+       counter[7:0] <= 8'b00000001;
+     else if(posedge_match)
+       counter[7:0] <= 8'b00000001;// Self resetting
+     else
+       counter[7:0] <= (counter[7:0] + 8'b00000001);
+   
+   assign posedge_match    = (counter[7:0]==divcfg_dec[7:0]);
+   assign negedge_match    = (counter[7:0]=={1'b0,divcfg_dec[7:1]}); 
+   
+   always @ (posedge clkin or posedge reset)
+     if(reset)
+       clkout_reg <= 1'b0;   
+     else if(posedge_match)
+       clkout_reg <= 1'b1;
+     else if(negedge_match)
+       clkout_reg <= 1'b0;
+
+   //Divide by one bypass
+   assign div_bp  = (divcfg[3:0]==4'b0000);
+   assign clkout  = div_bp ? clkin : clkout_reg;
+ 
+endmodule // clock_divider
+    
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"module OBUFTDS (/*AUTOARG*/
+   // Outputs
+   O, OB,
+   // Inputs
+   I, T
+   );
+
+   parameter IOSTANDARD=0;
+   parameter SLEW=0;
+   
+   input I;    //input
+   input T;    //tristate signal
+   output O;   //output
+   output OB;  //output_bar
+
+   assign O  = T ? 1'bz : I;
+   assign OB = T ? 1'bz : ~I;
+   
+   
+endmodule // OBUFTDS
+
+"
+"module etx_remap (/*AUTOARG*/
+   // Outputs
+   emesh_access_out, emesh_packet_out,
+   // Inputs
+   clk, reset, emesh_access_in, emesh_packet_in, remap_en,
+   remap_bypass, etx_rd_wait, etx_wr_wait
+   );
+
+   parameter AW = 32;
+   parameter DW = 32;
+   parameter PW = 104;
+   parameter ID = 12'h808;
+   
+   //Clock/reset
+   input clk;
+   input reset;
+
+   //Input from arbiter
+   input          emesh_access_in;
+   input [PW-1:0] emesh_packet_in;
+   input \t  remap_en;             //enable tx remap (static)
+   input \t  remap_bypass;         //dynamic control (read request)
+   
+   //Output to TX IO   
+   output \t   emesh_access_out;
+   output [PW-1:0] emesh_packet_out;
+
+   //Wait signals from protocol block
+   input \t   etx_rd_wait;
+   input \t   etx_wr_wait;
+
+   wire [31:0] \t   addr_in;
+   wire [31:0] \t   addr_remap;
+   wire [31:0] \t   addr_out;
+   wire \t   write_in;
+   
+   reg \t\t   emesh_access_out;
+   reg [PW-1:0]    emesh_packet_out;
+
+   
+   assign addr_in[31:0]   =  emesh_packet_in[39:8];
+   assign write_in        =  emesh_packet_in[1];
+      
+   assign addr_remap[31:0] = {addr_in[29:18],//ID
+\t\t\t      addr_in[17:16],//SPECIAL GROUP
+                             {(2){(|addr_in[17:16])}},//ZERO IF NOT SPECIAL
+\t\t\t     addr_in[15:0]
+\t\t\t     };
+   \t\t\t     
+   assign addr_out[31:0] = (remap_en & ~remap_bypass) ? addr_remap[31:0] :
+                \t                                addr_in[31:0];
+        \t\t
+
+   //stall read/write access appropriately
+   always @ (posedge clk)     
+     if((write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
+       begin
+\t  emesh_access_out         <= emesh_access_in;
+\t  emesh_packet_out[PW-1:0] <= {emesh_packet_in[PW-1:40],
+\t\t\t\t       addr_out[31:0],
+\t\t\t\t       emesh_packet_in[7:0]
+\t\t\t\t       };\t
+       end
+   
+endmodule // etx_mux
+
+"
+"module erx_fifo (/*AUTOARG*/
+   // Outputs
+   rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
+   rxrr_packet, rxrd_fifo_wait, rxrr_fifo_wait, rxwr_fifo_wait,
+   // Inputs
+   erx_reset, sys_reset, rx_lclk_div4, sys_clk, rxwr_wait, rxrd_wait,
+   rxrr_wait, rxrd_fifo_access, rxrd_fifo_packet, rxrr_fifo_access,
+   rxrr_fifo_packet, rxwr_fifo_access, rxwr_fifo_packet
+   );
+
+   parameter AW      = 32;
+   parameter DW      = 32;
+   parameter PW      = 104;
+   parameter RFAW    = 6;
+   parameter ID      = 12\'h800;
+
+   //reset & clocks
+   input           erx_reset;
+   input           sys_reset;
+   input \t   rx_lclk_div4;
+   input \t   sys_clk;
+
+   //WR to AXI master
+   output \t   rxwr_access;\t\t
+   output [PW-1:0] rxwr_packet;
+   input \t   rxwr_wait;
+
+   //RD to AXI master
+   output \t   rxrd_access;\t\t
+   output [PW-1:0] rxrd_packet;
+   input \t   rxrd_wait;
+
+   //RR to AXI slave
+   output \t   rxrr_access;\t\t
+   output [PW-1:0] rxrr_packet;
+   input \t   rxrr_wait;
+
+   //RD from IO
+   input \t   rxrd_fifo_access;\t// To rxrd_fifo of fifo_cdc.v
+   input [PW-1:0]  rxrd_fifo_packet;\t// To rxrd_fifo of fifo_cdc.v
+   output \t   rxrd_fifo_wait;\t\t// From rxrd_fifo of fifo_cdc.v
+
+   //RR from IO
+   input \t   rxrr_fifo_access;\t// To rxrr_fifo of fifo_cdc.v
+   input [PW-1:0]  rxrr_fifo_packet;\t// To rxrr_fifo of fifo_cdc.v
+   output \t   rxrr_fifo_wait;\t\t// From rxrr_fifo of fifo_cdc.v
+   
+   //WR from IO
+   input \t   rxwr_fifo_access;\t// To rxwr_fifo of fifo_cdc.v
+   input [PW-1:0]  rxwr_fifo_packet;\t// To rxwr_fifo of fifo_cdc.v
+   output \t   rxwr_fifo_wait;\t// From rxwr_fifo of fifo_cdc.v
+
+   /*AUTOOUTPUT*/
+   /*AUTOINPUT*/
+
+   /*AUTOWIRE*/
+
+
+   /************************************************************/
+   /*FIFOs                                                     */
+   /*(for AXI 1. read request, 2. write, and 3. read response) */
+   /************************************************************/
+
+   /*fifo_cdc   AUTO_TEMPLATE ( 
+ \t\t\t       // Outputs
+\t\t\t       .packet_out (@""(substring vl-cell-name  0 4)""_packet[PW-1:0]),
+    \t\t\t       .access_out (@""(substring vl-cell-name  0 4)""_access),
+                               .wait_out   (@""(substring vl-cell-name  0 4)""_fifo_wait),
+    \t\t\t       // Inputs
+\t\t\t       .clk_out\t   (sys_clk),
+                               .clk_in\t   (rx_lclk_div4),
+                               .access_in  (@""(substring vl-cell-name  0 4)""_fifo_access),
+                               .wait_in    (@""(substring vl-cell-name  0 4)""_wait),
+\t\t\t       .reset_in   (erx_reset),
+                               .reset_out  (sys_reset),
+                               .packet_in  (@""(substring vl-cell-name  0 4)""_fifo_packet[PW-1:0]),
+    );
+   */
+
+      
+   //Read request fifo (from Epiphany)
+   fifo_cdc #(.DW(104), .DEPTH(32)) 
+   rxrd_fifo   (
+\t\t/*AUTOINST*/
+\t\t// Outputs
+\t\t.wait_out\t\t(rxrd_fifo_wait),\t // Templated
+\t\t.access_out\t\t(rxrd_access),\t\t // Templated
+\t\t.packet_out\t\t(rxrd_packet[PW-1:0]),\t // Templated
+\t\t// Inputs
+\t\t.clk_in\t\t\t(rx_lclk_div4),\t\t // Templated
+\t\t.reset_in\t\t(erx_reset),\t\t // Templated
+\t\t.access_in\t\t(rxrd_fifo_access),\t // Templated
+\t\t.packet_in\t\t(rxrd_fifo_packet[PW-1:0]), // Templated
+\t\t.clk_out\t\t(sys_clk),\t\t // Templated
+\t\t.reset_out\t\t(sys_reset),\t\t // Templated
+\t\t.wait_in\t\t(rxrd_wait));\t\t // Templated
+
+ 
+
+   //Write fifo (from Epiphany)
+   fifo_cdc #(.DW(104), .DEPTH(32)) 
+   rxwr_fifo(
+\t     /*AUTOINST*/
+\t     // Outputs
+\t     .wait_out\t\t\t(rxwr_fifo_wait),\t // Templated
+\t     .access_out\t\t(rxwr_access),\t\t // Templated
+\t     .packet_out\t\t(rxwr_packet[PW-1:0]),\t // Templated
+\t     // Inputs
+\t     .clk_in\t\t\t(rx_lclk_div4),\t\t // Templated
+\t     .reset_in\t\t\t(erx_reset),\t\t // Templated
+\t     .access_in\t\t\t(rxwr_fifo_access),\t // Templated
+\t     .packet_in\t\t\t(rxwr_fifo_packet[PW-1:0]), // Templated
+\t     .clk_out\t\t\t(sys_clk),\t\t // Templated
+\t     .reset_out\t\t\t(sys_reset),\t\t // Templated
+\t     .wait_in\t\t\t(rxwr_wait));\t\t // Templated
+   
+ 
+
+   //Read response fifo (for host)
+   fifo_cdc #(.DW(104), .DEPTH(32))  
+   rxrr_fifo(
+\t     /*AUTOINST*/
+\t     // Outputs
+\t     .wait_out\t\t\t(rxrr_fifo_wait),\t // Templated
+\t     .access_out\t\t(rxrr_access),\t\t // Templated
+\t     .packet_out\t\t(rxrr_packet[PW-1:0]),\t // Templated
+\t     // Inputs
+\t     .clk_in\t\t\t(rx_lclk_div4),\t\t // Templated
+\t     .reset_in\t\t\t(erx_reset),\t\t // Templated
+\t     .access_in\t\t\t(rxrr_fifo_access),\t // Templated
+\t     .packet_in\t\t\t(rxrr_fifo_packet[PW-1:0]), // Templated
+\t     .clk_out\t\t\t(sys_clk),\t\t // Templated
+\t     .reset_out\t\t\t(sys_reset),\t\t // Templated
+\t     .wait_in\t\t\t(rxrr_wait));\t\t // Templated
+           
+endmodule // erx
+// Local Variables:
+// verilog-library-directories:(""."" ""../../emmu/hdl"" ""../../edma/hdl"" ""../../memory/hdl"" ""../../emailbox/hdl"")
+// End:
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+  
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+"
+"/*WARNING: INCOMPLETE MODEL, DON\'T USE. I RECOMMEND AGAINST USING THIS
+ *BLOCK ALL TOGETHER. NOT OPEN SOURCE FRIENDLY /AO
+ */
+
+module ISERDESE2 (/*AUTOARG*/
+   // Outputs
+   O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2,
+   // Inputs
+   BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, CLKDIVP, D, DDLY,
+   DYNCLKDIVSEL, DYNCLKSEL, OCLK, OCLKB, OFB, RST, SHIFTIN1, SHIFTIN2
+   );
+
+   parameter DATA_RATE         = 0; // ""DDR"" or ""SDR""
+   parameter DATA_WIDTH        = 0; // 4,2,3,5,6,7,8,10,14
+   parameter DYN_CLK_INV_EN    = 0; // ""FALSE"", ""TRUE""
+   parameter DYN_CLKDIV_INV_EN = 0; // ""FALSE"", ""TRUE""
+   parameter INIT_Q1           = 0; // 1\'b0 to 1\'b1
+   parameter INIT_Q2           = 0; // 1\'b0 to 1\'b1
+   parameter INIT_Q3           = 0; // 1\'b0 to 1\'b1
+   parameter INIT_Q4           = 0; // 1\'b0 to 1\'b1
+   parameter INTERFACE_TYPE    = 0; // ""MEMORY"",""MEMORY_DDR3"", ""MEMORY_QDR"", 
+                                    // ""NETWORKING"", ""OVERSAMPLE""
+   parameter IOBDELAY          = 0; // ""NONE"", ""BOTH"", ""IBUF"", ""IFD""  
+   parameter NUM_CE            = 0; // 2,1
+   parameter OFB_USED          = 0; // ""FALSE"", ""TRUE""
+   parameter SERDES_MODE       = 0; // ""MASTER"" or ""SLAVE""
+   parameter SRVAL_Q1          = 0; // 1\'b0 or 1\'b1 
+   parameter SRVAL_Q2          = 0; // 1\'b0 or 1\'b1 
+   parameter SRVAL_Q3          = 0; // 1\'b0 or 1\'b1 
+   parameter SRVAL_Q4          = 0; // 1\'b0 or 1\'b1 
+  
+   input  BITSLIP;        // performs bitslip operation
+   input  CE1;            // clock enable 
+   input  CE2;            // clock enable
+   input  CLK;            // high speed clock input
+   input  CLKB;           // high speed clock input (inverted)
+   input  CLKDIV;         // divided clock (for bitslip and CE module)
+   input  CLKDIVP;        // for MIG only
+   input  D;              // serial input data pin
+   input  DDLY;           // serial input data from IDELAYE2
+   input  DYNCLKDIVSEL;   // dynamically select CLKDIV inversion
+   input  DYNCLKSEL;      // dynamically select CLK and CLKB inversion.
+   input  OCLK;           // clock for strobe based memory interfaces  
+   input  OCLKB;          // clock for strobe based memory interfaces 
+   input  OFB;            // data feebdack from OSERDESE2?
+   input  RST;            // asynchronous reset
+   input  SHIFTIN1;       // slave of multie serdes
+   input  SHIFTIN2;       // slave of multie serdes
+     
+   //outputs
+   output O;              // pass through from D or DDLY
+   output Q1;             // parallel data out (last bit)
+   output Q2;
+   output Q3;
+   output Q4;   
+   output Q5;
+   output Q6;
+   output Q7;
+   output Q8;             // first bit of D appears here
+   output SHIFTOUT1;      // master of multi serdes
+   output SHIFTOUT2;      // master of multi serdes
+
+
+   reg [3:0] even_samples;
+   reg [3:0] odd_samples;
+   reg \t     Q1; 
+   reg \t     Q2;
+   reg \t     Q3;
+   reg \t     Q4;   
+   reg \t     Q5;
+   reg \t     Q6;
+   reg \t     Q7;
+   reg \t     Q8;           
+   always @ (posedge CLK)
+     odd_samples[3:0] <=   {odd_samples[2:0],D};//#0.1
+
+   always @ (negedge CLK)
+     even_samples[3:0] <=  {even_samples[2:0],D};//#0.1
+
+   always @ (posedge CLKDIV)
+     begin
+\t Q1 <=  odd_samples[0];
+\t Q2 <=  even_samples[0];
+\t Q3 <=  odd_samples[1];
+\t Q4 <=  even_samples[1];
+\t Q5 <=  odd_samples[2];
+\t Q6 <=  even_samples[2];
+\t Q7 <=  odd_samples[3];
+\t Q8 <=  even_samples[3];
+     end
+   
+
+   //pass through
+   assign O=D;
+
+   //not implemented
+   assign SHIFTOUT1=1\'b0;
+   assign SHIFTOUT2=1\'b0;
+   \t
+endmodule // ISERDESE2
+
+
+"
+"module pulse2toggle(/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in, reset
+   );
+
+   
+   //clocks
+   input  clk; 
+   
+   input  in;   
+   output out;
+
+   //reset
+   input  reset;  //do we need this???
+
+
+   reg \t  out;
+   wire   toggle;
+   
+   //if input goes high, toggle output
+   //note1: input can only be high for one clock cycle
+   //note2: be careful with clock gating
+
+   assign toggle = in ? ~out :
+\t\t         out;
+   
+
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       out <= 1'b0;
+     else
+       out <= toggle;
+   
+endmodule // pulse2toggle
+
+/*
+ Copyright (C) 2015 Adapteva, Inc. 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"module dv_emmu_tb;
+
+   reg clk;
+   
+   reg reset;
+   
+   reg \t      go;
+
+   //Clock
+   always
+     #10 clk = ~clk;
+   
+   initial
+     begin
+\t$display($time, "" << Starting the Simulation >>"");
+\t#0
+        clk                    = 1\'b0;    // at time 0
+\treset                  = 1\'b1;    // reset is active
+\t#100 
+\t  reset    = 1\'b0;    // at time 100 release reset
+\t#100
+\t  go       = 1\'b1;\t
+\t#10000\t  
+\t  $finish;
+     end\t
+
+   //Waveform dump
+   initial
+     begin
+\t$dumpfile(""test.vcd"");
+\t$dumpvars(0, dv_emmu);
+     end
+
+
+dv_emmu dv_emmu
+  (.clk (clk),
+   .reset (reset),
+   .go (go));
+endmodule
+"
+"//`timescale 1 ns / 100 ps
+module dv_emmu
+  (input clk,
+   input reset,
+   input go);
+
+   parameter DW   = 32;        //data width of
+   parameter AW   = 32;        //data width of 
+   parameter IW   = 12;        //index size of table
+   parameter PAW  = 64;        //physical address width of output
+   parameter MW   = PAW-AW+IW; //table data width
+   parameter MD   = 1<<IW;     //memory depth
+
+   
+   //Stimulus to drive
+   reg \t      mmu_en;
+   
+   //Reg interface
+   reg        mi_en;
+   reg [12:0] mi_addr;
+   reg [31:0] mi_din;
+   reg [3:0]  mi_we;
+   
+   
+   //emesh interface
+   reg              emesh_access_in;
+   reg              emesh_write_in;
+   reg [1:0]        emesh_datamode_in;
+   reg [3:0]        emesh_ctrlmode_in;
+   reg [AW-1:0]     emesh_dstaddr_in;
+   reg [AW-1:0]     emesh_srcaddr_in;
+   reg [DW-1:0]     emesh_data_in;
+   
+   //Test junk
+   reg [1:0]  test_state;
+  
+   //Pattern generator
+   //1.) Write some patterns through mi_interface
+   //2.) Write some patterns from emesh interface
+      
+   always @ (negedge clk) begin
+     if(go)
+       begin
+\t  case(test_state[1:0])
+\t    2\'b00://write entries
+\t      if(mi_addr[12:0]<13\'h16)
+\t\tbegin
+\t\t   mi_en            <= 1\'b1;
+\t\t   mi_we[3:0]       <= 4\'b1111;
+\t\t   mi_addr[12:0]    <= mi_addr[12:0] + 1\'b1;\t  
+\t\t   /* verilator lint_off WIDTH */
+\t\t   mi_din[31:0]     <= mi_addr[0] ? (mi_addr[12:0]+32\'hFFFFF000) : 32\'hFFFFFFFF;
+\t\t   /* verilator lint_on WIDTH */
+\t\tend
+\t      else
+\t\tbegin
+\t\t   test_state       <= 2\'b01;
+\t\t   mi_en            <= 1\'b0;
+\t\tend
+\t    2\'b01://
+\t      if(emesh_dstaddr_in[31:0]<32\'h00800000)
+\t\tbegin\t    
+\t\t   emesh_access_in        <= 1\'b1;
+\t\t   emesh_write_in         <= 1\'b1;
+\t\t   emesh_dstaddr_in[31:0] <= emesh_dstaddr_in[31:0] + 32\'h00100001;
+\t\t   emesh_ctrlmode_in[3:0] <= 4\'b1111;
+\t\t   emesh_datamode_in[1:0] <= 2\'b11;
+\t\t   emesh_data_in[31:0]    <= 32\'h12345678;
+\t\t   emesh_srcaddr_in[31:0] <= 32\'h55555555;
+\t\tend
+\t      else
+\t\tbegin
+\t\t   test_state       <= 2\'b10;
+\t\t   emesh_access_in <= 1\'b0;
+\t\tend // else: !if(~done)
+\t    2\'b10://init array
+\t      begin
+\t\t mi_addr[5:0]     <= mi_addr[5:0]-1\'b1;
+\t      end
+\t    default : test_state <= test_state;
+\t  endcase // case (test_state[1:0])
+       end // if (go)
+      if (reset) begin
+\t mi_we[3:0]             <= 4\'b0;
+\t mi_en                  <= 1\'b0;
+\t mi_addr[12:0]          <= 13\'b0;
+\t mi_din[31:0]           <= 32\'h55555000;
+\t test_state[1:0]        <= 2\'b00;
+         emesh_access_in        <= 1\'b0;
+\t emesh_write_in         <= 1\'b0;
+\t emesh_ctrlmode_in[3:0] <= 4\'b0;
+\t emesh_datamode_in[1:0] <= 2\'b0;
+\t emesh_dstaddr_in[31:0] <= 32\'b0;
+\t emesh_srcaddr_in[31:0] <= 32\'b0;
+\t emesh_data_in[31:0]    <= 32\'b0;
+\t mmu_en                 <= 1\'b1;
+     end
+   end
+   wire done =  (mi_addr[5:0]==6\'b001101);
+  
+   
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\temmu_access_out;\t// From emmu of emmu.v
+   wire [3:0]\t\temmu_ctrlmode_out;\t// From emmu of emmu.v
+   wire [DW-1:0]\temmu_data_out;\t\t// From emmu of emmu.v
+   wire [1:0]\t\temmu_datamode_out;\t// From emmu of emmu.v
+   wire [63:0]\t\temmu_dstaddr_out;\t// From emmu of emmu.v
+   wire [AW-1:0]\temmu_srcaddr_out;\t// From emmu of emmu.v
+   wire\t\t\temmu_write_out;\t\t// From emmu of emmu.v
+   wire [31:0]\t\tmi_dout;\t\t// From emmu of emmu.v
+   // End of automatics
+   /*AUTOWIRE*/
+   
+   //DUT
+   emmu emmu(.mi_clk\t\t\t(clk),
+\t     /*AUTOINST*/
+\t     // Outputs
+\t     .mi_dout\t\t\t(mi_dout[31:0]),
+\t     .emmu_access_out\t\t(emmu_access_out),
+\t     .emmu_write_out\t\t(emmu_write_out),
+\t     .emmu_datamode_out\t\t(emmu_datamode_out[1:0]),
+\t     .emmu_ctrlmode_out\t\t(emmu_ctrlmode_out[3:0]),
+\t     .emmu_dstaddr_out\t\t(emmu_dstaddr_out[63:0]),
+\t     .emmu_srcaddr_out\t\t(emmu_srcaddr_out[AW-1:0]),
+\t     .emmu_data_out\t\t(emmu_data_out[DW-1:0]),
+\t     // Inputs
+\t     .clk\t\t\t(clk),
+\t     .mmu_en\t\t\t(mmu_en),
+\t     .mi_en\t\t\t(mi_en),
+\t     .mi_we\t\t\t(mi_we[3:0]),
+\t     .mi_addr\t\t\t({3\'b000,mi_addr[12:0]}),
+\t     .mi_din\t\t\t(mi_din[31:0]),
+\t     .emesh_access_in\t\t(emesh_access_in),
+\t     .emesh_write_in\t\t(emesh_write_in),
+\t     .emesh_datamode_in\t\t(emesh_datamode_in[1:0]),
+\t     .emesh_ctrlmode_in\t\t(emesh_ctrlmode_in[3:0]),
+\t     .emesh_dstaddr_in\t\t(emesh_dstaddr_in[AW-1:0]),
+\t     .emesh_srcaddr_in\t\t(emesh_srcaddr_in[AW-1:0]),
+\t     .emesh_data_in\t\t(emesh_data_in[DW-1:0]));
+
+   
+endmodule // dv_emmu
+// Local Variables:
+// verilog-library-directories:(""."" ""../hdl"")
+// End:
+
+
+
+"
+"module IDELAYE2 (/*AUTOARG*/
+   // Outputs
+   CNTVALUEOUT, DATAOUT,
+   // Inputs
+   C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN,
+   REGRST
+   );
+
+   parameter CINVCTRL_SEL = ""FALSE"";           // Enable dynamic clock inversion
+   parameter DELAY_SRC = ""IDATAIN"";            // Delay input 
+   parameter HIGH_PERFORMANCE_MODE  = ""FALSE""; // Reduced jitter
+   parameter IDELAY_TYPE  = ""FIXED"";           // Type of delay line
+   parameter integer IDELAY_VALUE = 0;         // Input delay tap setting
+   parameter [0:0] IS_C_INVERTED = 1\'b0;       // 
+   parameter [0:0] IS_DATAIN_INVERTED = 1\'b0;  //
+   parameter [0:0] IS_IDATAIN_INVERTED = 1\'b0; //
+   parameter PIPE_SEL = ""FALSE"";               // Select pipelined mode
+   parameter real    REFCLK_FREQUENCY = 200.0; // Ref clock frequency
+   parameter SIGNAL_PATTERN    = ""DATA"";       // Input signal type
+
+`ifdef XIL_TIMING
+    parameter LOC = ""UNPLACED"";
+    parameter integer SIM_DELAY_D = 0;
+    localparam DELAY_D = (IDELAY_TYPE == ""VARIABLE"") ? SIM_DELAY_D : 0;
+`endif // ifdef XIL_TIMING
+
+`ifndef XIL_TIMING
+    integer DELAY_D=0;
+`endif // ifndef XIL_TIMING
+
+   output [4:0] CNTVALUEOUT; // count value for monitoring tap value
+   output \tDATAOUT;     // delayed data
+   input \tC;           // clock input for variable mode
+   input \tCE;          // enable increment/decrement function
+   input \tCINVCTRL;    // dynamically inverts clock polarity
+   input [4:0] \tCNTVALUEIN;  // counter value for tap delay
+   input \tDATAIN;      // data input from FGPA logic
+   input \tIDATAIN;     // data input from IBUF
+   input \tINC;         // increment tap delay
+   input \tLD;          // loads the delay primitive
+   input \tLDPIPEEN;    // enables the pipeline register delay 
+   input \tREGRST;      // reset for pipeline register
+
+   assign DATAOUT = IDATAIN;
+
+   initial
+     begin
+\t$display(""Delay %d %m"",IDELAY_VALUE);\t
+     end
+endmodule // IDELAYE2
+
+
+
+"
+"module IDDR (/*AUTOARG*/
+   // Outputs
+   Q1, Q2,
+   // Inputs
+   C, CE, D, R, S
+   );
+
+   //Default parameters
+    parameter DDR_CLK_EDGE        = ""OPPOSITE_EDGE"";    
+    parameter INIT_Q1             = 1\'b0;
+    parameter INIT_Q2             = 1\'b0;
+    parameter [0:0] IS_C_INVERTED = 1\'b0;
+    parameter [0:0] IS_D_INVERTED = 1\'b0;
+    parameter SRTYPE              = ""SYNC"";
+   
+   output   Q1;   // IDDR registered output (first) 
+   output   Q2;   // IDDR registered output (second)    
+   input    C;    // clock
+   input    CE;   // clock enable, set to high to clock in data
+   input    D;    // data input from IOB
+   input    R;    // sync or async reset
+   input    S;    // syn/async ""set to 1""
+
+   //trick for string comparison
+   localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE;
+
+   reg \t    Q1_pos;
+   reg \t    Q1_reg;
+
+   reg \t    Q2_pos;
+   reg \t    Q2_neg;
+   
+   always @ (posedge C)
+     if(CE)
+       Q1_pos <= D;
+
+   always @ (posedge C)
+     if(CE)
+       Q1_reg <= Q1_pos;
+         
+   always @ (negedge C)
+     if(CE)
+       Q2_neg <= D;
+   
+   always @ (posedge C)
+     if(CE)
+      Q2_pos <= Q2_neg;
+
+   //Select behavior based on parameters
+   assign Q1 = (DDR_CLK_EDGE_REG == ""SAME_EDGE_PIPELINED"") ? Q1_reg :
+\t       (DDR_CLK_EDGE_REG == ""SAME_EDGE"")           ? Q1_pos :
+\t                                                     1\'b0;
+   
+   assign Q2 = (DDR_CLK_EDGE_REG == ""SAME_EDGE_PIPELINED"") ? Q2_pos :
+\t       (DDR_CLK_EDGE_REG == ""SAME_EDGE"")           ? Q2_pos :
+\t                                                     1\'b0;
+            
+endmodule // IDDR
+
+"
+"//Version v5_5
+module processing_system7 (
+  #(
+  parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
+  parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
+  parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
+  parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
+  parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12, 
+  parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
+  parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1, 
+  parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
+  parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
+  parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
+  parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
+  parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
+  parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
+  parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
+  parameter integer C_NUM_F2P_INTR_INPUTS = 1,
+  parameter         C_FCLK_CLK0_BUF = ""TRUE"",
+  parameter         C_FCLK_CLK1_BUF = ""TRUE"",
+  parameter         C_FCLK_CLK2_BUF = ""TRUE"",
+  parameter         C_FCLK_CLK3_BUF = ""TRUE"",
+  parameter integer C_EMIO_GPIO_WIDTH = 64,
+  parameter integer C_INCLUDE_TRACE_BUFFER = 0,
+  parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
+  parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
+  parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
+  parameter integer C_TRACE_PIPELINE_WIDTH = 8,
+  parameter         C_PS7_SI_REV = ""PRODUCTION"",
+  parameter integer C_EN_EMIO_ENET0 = 0,
+  parameter integer C_EN_EMIO_ENET1 = 0,
+  parameter integer C_EN_EMIO_TRACE = 0,
+  parameter integer C_DQ_WIDTH = 32,
+  parameter integer C_DQS_WIDTH = 4,
+  parameter integer C_DM_WIDTH = 4,
+  parameter integer C_MIO_PRIMITIVE = 54,
+  parameter\t    C_PACKAGE_NAME = ""clg484"",
+  parameter         C_IRQ_F2P_MODE = ""DIRECT"",
+  parameter         C_TRACE_INTERNAL_WIDTH = 32,
+  parameter integer C_EN_EMIO_PJTAG = 0
+) 
+  //FMIO CAN0
+  output \t\t\t\t       CAN0_PHY_TX,
+  input \t\t\t\t       CAN0_PHY_RX,
+
+  //FMIO CAN1
+  output \t\t\t\t       CAN1_PHY_TX, 
+  input \t\t\t\t       CAN1_PHY_RX,
+  
+  //FMIO ENET0
+  output reg \t\t\t\t       ENET0_GMII_TX_EN,
+  output reg \t\t\t\t       ENET0_GMII_TX_ER,
+  output \t\t\t\t       ENET0_MDIO_MDC,
+  output \t\t\t\t       ENET0_MDIO_O,
+  output \t\t\t\t       ENET0_MDIO_T,
+  output \t\t\t\t       ENET0_PTP_DELAY_REQ_RX,
+  output \t\t\t\t       ENET0_PTP_DELAY_REQ_TX,
+  output \t\t\t\t       ENET0_PTP_PDELAY_REQ_RX,
+  output \t\t\t\t       ENET0_PTP_PDELAY_REQ_TX,
+  output \t\t\t\t       ENET0_PTP_PDELAY_RESP_RX,
+  output \t\t\t\t       ENET0_PTP_PDELAY_RESP_TX,
+  output \t\t\t\t       ENET0_PTP_SYNC_FRAME_RX,
+  output \t\t\t\t       ENET0_PTP_SYNC_FRAME_TX,
+  output \t\t\t\t       ENET0_SOF_RX,
+  output \t\t\t\t       ENET0_SOF_TX,
+  
+  
+  output reg [7:0] \t\t\t       ENET0_GMII_TXD, 
+
+  
+  input \t\t\t\t       ENET0_GMII_COL,
+  input \t\t\t\t       ENET0_GMII_CRS,
+  input \t\t\t\t       ENET0_GMII_RX_CLK,
+  input \t\t\t\t       ENET0_GMII_RX_DV,
+  input \t\t\t\t       ENET0_GMII_RX_ER,
+  input \t\t\t\t       ENET0_GMII_TX_CLK,
+  input \t\t\t\t       ENET0_MDIO_I,
+  input \t\t\t\t       ENET0_EXT_INTIN,
+  input [7:0] \t\t\t\t       ENET0_GMII_RXD, 
+
+  //FMIO ENET1
+  output reg \t\t\t\t       ENET1_GMII_TX_EN,
+  output reg \t\t\t\t       ENET1_GMII_TX_ER,
+  output \t\t\t\t       ENET1_MDIO_MDC,
+  output \t\t\t\t       ENET1_MDIO_O,
+  output \t\t\t\t       ENET1_MDIO_T,
+  output \t\t\t\t       ENET1_PTP_DELAY_REQ_RX,
+  output \t\t\t\t       ENET1_PTP_DELAY_REQ_TX,
+  output \t\t\t\t       ENET1_PTP_PDELAY_REQ_RX,
+  output \t\t\t\t       ENET1_PTP_PDELAY_REQ_TX,
+  output \t\t\t\t       ENET1_PTP_PDELAY_RESP_RX,
+  output \t\t\t\t       ENET1_PTP_PDELAY_RESP_TX,
+  output \t\t\t\t       ENET1_PTP_SYNC_FRAME_RX,
+  output \t\t\t\t       ENET1_PTP_SYNC_FRAME_TX,
+  output \t\t\t\t       ENET1_SOF_RX,
+  output \t\t\t\t       ENET1_SOF_TX,
+  output reg [7:0] \t\t\t       ENET1_GMII_TXD, 
+
+  input \t\t\t\t       ENET1_GMII_COL,
+  input \t\t\t\t       ENET1_GMII_CRS,
+  input \t\t\t\t       ENET1_GMII_RX_CLK,
+  input \t\t\t\t       ENET1_GMII_RX_DV,
+  input \t\t\t\t       ENET1_GMII_RX_ER,
+  input \t\t\t\t       ENET1_GMII_TX_CLK,
+  input \t\t\t\t       ENET1_MDIO_I,
+  input \t\t\t\t       ENET1_EXT_INTIN, 
+  input [7:0] \t\t\t\t       ENET1_GMII_RXD,
+  
+  //FMIO GPIO
+  input [(C_EMIO_GPIO_WIDTH-1):0] \t       GPIO_I,
+  output [(C_EMIO_GPIO_WIDTH-1):0] \t       GPIO_O,
+  output [(C_EMIO_GPIO_WIDTH-1):0] \t       GPIO_T, 
+  
+  //FMIO I2C0
+  input \t\t\t\t       I2C0_SDA_I,
+  output \t\t\t\t       I2C0_SDA_O,
+  output \t\t\t\t       I2C0_SDA_T,
+  input \t\t\t\t       I2C0_SCL_I,
+  output \t\t\t\t       I2C0_SCL_O,
+  output \t\t\t\t       I2C0_SCL_T,
+
+  //FMIO I2C1
+  input \t\t\t\t       I2C1_SDA_I,
+  output \t\t\t\t       I2C1_SDA_O,
+  output \t\t\t\t       I2C1_SDA_T,
+  input \t\t\t\t       I2C1_SCL_I,
+  output \t\t\t\t       I2C1_SCL_O,
+  output \t\t\t\t       I2C1_SCL_T,
+  
+  //FMIO PJTAG
+  input \t\t\t\t       PJTAG_TCK,
+  input \t\t\t\t       PJTAG_TMS,
+  input \t\t\t\t       PJTAG_TDI,
+  output \t\t\t\t       PJTAG_TDO,
+
+  
+  //FMIO SDIO0
+  output \t\t\t\t       SDIO0_CLK,
+  input \t\t\t\t       SDIO0_CLK_FB,
+  output \t\t\t\t       SDIO0_CMD_O,
+  input \t\t\t\t       SDIO0_CMD_I,
+  output \t\t\t\t       SDIO0_CMD_T,
+  input [3:0] \t\t\t\t       SDIO0_DATA_I,
+  output [3:0] \t\t\t\t       SDIO0_DATA_O,
+  output [3:0] \t\t\t\t       SDIO0_DATA_T,
+  output \t\t\t\t       SDIO0_LED,
+  input \t\t\t\t       SDIO0_CDN,
+  input \t\t\t\t       SDIO0_WP, 
+  output \t\t\t\t       SDIO0_BUSPOW,
+  output [2:0] \t\t\t\t       SDIO0_BUSVOLT,
+
+  //FMIO SDIO1
+  output \t\t\t\t       SDIO1_CLK,
+  input \t\t\t\t       SDIO1_CLK_FB,
+  output \t\t\t\t       SDIO1_CMD_O,
+  input \t\t\t\t       SDIO1_CMD_I,
+  output \t\t\t\t       SDIO1_CMD_T,
+  input [3:0] \t\t\t\t       SDIO1_DATA_I,
+  output [3:0] \t\t\t\t       SDIO1_DATA_O,
+  output [3:0] \t\t\t\t       SDIO1_DATA_T, 
+  output \t\t\t\t       SDIO1_LED,
+  input \t\t\t\t       SDIO1_CDN, 
+  input \t\t\t\t       SDIO1_WP,
+  output \t\t\t\t       SDIO1_BUSPOW, 
+  output [2:0] \t\t\t\t       SDIO1_BUSVOLT,
+
+  //FMIO SPI0
+  input \t\t\t\t       SPI0_SCLK_I,
+  output \t\t\t\t       SPI0_SCLK_O,
+  output \t\t\t\t       SPI0_SCLK_T,
+  input \t\t\t\t       SPI0_MOSI_I,
+  output \t\t\t\t       SPI0_MOSI_O,
+  output \t\t\t\t       SPI0_MOSI_T,
+  input \t\t\t\t       SPI0_MISO_I,
+  output \t\t\t\t       SPI0_MISO_O,
+  output \t\t\t\t       SPI0_MISO_T,
+  input \t\t\t\t       SPI0_SS_I,
+  output \t\t\t\t       SPI0_SS_O,
+  output \t\t\t\t       SPI0_SS1_O,
+  output \t\t\t\t       SPI0_SS2_O,
+  output \t\t\t\t       SPI0_SS_T,
+
+  //FMIO SPI1
+  input \t\t\t\t       SPI1_SCLK_I,
+  output \t\t\t\t       SPI1_SCLK_O,
+  output \t\t\t\t       SPI1_SCLK_T,
+  input \t\t\t\t       SPI1_MOSI_I,
+  output \t\t\t\t       SPI1_MOSI_O,
+  output \t\t\t\t       SPI1_MOSI_T,
+  input \t\t\t\t       SPI1_MISO_I,
+  output \t\t\t\t       SPI1_MISO_O,
+  output \t\t\t\t       SPI1_MISO_T,
+  input \t\t\t\t       SPI1_SS_I,
+  output \t\t\t\t       SPI1_SS_O,
+  output \t\t\t\t       SPI1_SS1_O,
+  output \t\t\t\t       SPI1_SS2_O, 
+  output \t\t\t\t       SPI1_SS_T,
+
+  //FMIO UART0
+  output \t\t\t\t       UART0_DTRN,
+  output \t\t\t\t       UART0_RTSN, 
+  output \t\t\t\t       UART0_TX,
+  input \t\t\t\t       UART0_CTSN,
+  input \t\t\t\t       UART0_DCDN,
+  input \t\t\t\t       UART0_DSRN,
+  input \t\t\t\t       UART0_RIN, 
+  input \t\t\t\t       UART0_RX,
+
+  //FMIO UART1
+  output \t\t\t\t       UART1_DTRN,
+  output \t\t\t\t       UART1_RTSN, 
+  output \t\t\t\t       UART1_TX,
+  input \t\t\t\t       UART1_CTSN,
+  input \t\t\t\t       UART1_DCDN,
+  input \t\t\t\t       UART1_DSRN,
+  input \t\t\t\t       UART1_RIN, 
+  input \t\t\t\t       UART1_RX,
+
+  //FMIO TTC0
+  output \t\t\t\t       TTC0_WAVE0_OUT,
+  output \t\t\t\t       TTC0_WAVE1_OUT,
+  output \t\t\t\t       TTC0_WAVE2_OUT,
+  input \t\t\t\t       TTC0_CLK0_IN,
+  input \t\t\t\t       TTC0_CLK1_IN,
+  input \t\t\t\t       TTC0_CLK2_IN,
+
+  //FMIO TTC1
+  output \t\t\t\t       TTC1_WAVE0_OUT,
+  output \t\t\t\t       TTC1_WAVE1_OUT,
+  output \t\t\t\t       TTC1_WAVE2_OUT,
+  input \t\t\t\t       TTC1_CLK0_IN,
+  input \t\t\t\t       TTC1_CLK1_IN,
+  input \t\t\t\t       TTC1_CLK2_IN,
+
+  //WDT
+  input \t\t\t\t       WDT_CLK_IN,
+  output \t\t\t\t       WDT_RST_OUT,
+
+  //FTPORT
+  input \t\t\t\t       TRACE_CLK,
+  output \t\t\t\t       TRACE_CTL,
+  output [(C_TRACE_INTERNAL_WIDTH)-1:0]        TRACE_DATA,
+  output reg \t\t\t\t       TRACE_CLK_OUT,
+  
+  // USB
+  output [1:0] \t\t\t\t       USB0_PORT_INDCTL,
+  output \t\t\t\t       USB0_VBUS_PWRSELECT,
+  input \t\t\t\t       USB0_VBUS_PWRFAULT,
+
+  output [1:0] \t\t\t\t       USB1_PORT_INDCTL,
+  output \t\t\t\t       USB1_VBUS_PWRSELECT,
+  input \t\t\t\t       USB1_VBUS_PWRFAULT,
+  
+  input \t\t\t\t       SRAM_INTIN,
+
+  //AIO ===================================================
+
+  //M_AXI_GP0
+  
+  // -- Output
+  
+  output \t\t\t\t       M_AXI_GP0_ARESETN,
+  output \t\t\t\t       M_AXI_GP0_ARVALID,
+  output \t\t\t\t       M_AXI_GP0_AWVALID,
+  output \t\t\t\t       M_AXI_GP0_BREADY,
+  output \t\t\t\t       M_AXI_GP0_RREADY,
+  output \t\t\t\t       M_AXI_GP0_WLAST,
+  output \t\t\t\t       M_AXI_GP0_WVALID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
+  output [1:0] \t\t\t\t       M_AXI_GP0_ARBURST,
+  output [1:0] \t\t\t\t       M_AXI_GP0_ARLOCK,
+  output [2:0] \t\t\t\t       M_AXI_GP0_ARSIZE,
+  output [1:0] \t\t\t\t       M_AXI_GP0_AWBURST,
+  output [1:0] \t\t\t\t       M_AXI_GP0_AWLOCK,
+  output [2:0] \t\t\t\t       M_AXI_GP0_AWSIZE,
+  output [2:0] \t\t\t\t       M_AXI_GP0_ARPROT,
+  output [2:0] \t\t\t\t       M_AXI_GP0_AWPROT,
+  output [31:0] \t\t\t       M_AXI_GP0_ARADDR,
+  output [31:0] \t\t\t       M_AXI_GP0_AWADDR,
+  output [31:0] \t\t\t       M_AXI_GP0_WDATA,
+  output [3:0] \t\t\t\t       M_AXI_GP0_ARCACHE,
+  output [3:0] \t\t\t\t       M_AXI_GP0_ARLEN,
+  output [3:0] \t\t\t\t       M_AXI_GP0_ARQOS,
+  output [3:0] \t\t\t\t       M_AXI_GP0_AWCACHE,
+  output [3:0] \t\t\t\t       M_AXI_GP0_AWLEN,
+  output [3:0] \t\t\t\t       M_AXI_GP0_AWQOS,
+  output [3:0] \t\t\t\t       M_AXI_GP0_WSTRB, 
+  
+  // -- Input  
+  
+  input \t\t\t\t       M_AXI_GP0_ACLK,
+  input \t\t\t\t       M_AXI_GP0_ARREADY,
+  input \t\t\t\t       M_AXI_GP0_AWREADY,
+  input \t\t\t\t       M_AXI_GP0_BVALID,
+  input \t\t\t\t       M_AXI_GP0_RLAST,
+  input \t\t\t\t       M_AXI_GP0_RVALID,
+  input \t\t\t\t       M_AXI_GP0_WREADY,
+  input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0]  M_AXI_GP0_BID,
+  input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0]  M_AXI_GP0_RID,
+  input [1:0] \t\t\t\t       M_AXI_GP0_BRESP,
+  input [1:0] \t\t\t\t       M_AXI_GP0_RRESP,
+  input [31:0] \t\t\t\t       M_AXI_GP0_RDATA, 
+
+
+  //M_AXI_GP1
+  
+  // -- Output
+
+  output \t\t\t\t       M_AXI_GP1_ARESETN,
+  output \t\t\t\t       M_AXI_GP1_ARVALID,
+  output \t\t\t\t       M_AXI_GP1_AWVALID,
+  output \t\t\t\t       M_AXI_GP1_BREADY,
+  output \t\t\t\t       M_AXI_GP1_RREADY,
+  output \t\t\t\t       M_AXI_GP1_WLAST,
+  output \t\t\t\t       M_AXI_GP1_WVALID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
+  output [1:0] \t\t\t\t       M_AXI_GP1_ARBURST,
+  output [1:0] \t\t\t\t       M_AXI_GP1_ARLOCK,
+  output [2:0] \t\t\t\t       M_AXI_GP1_ARSIZE,
+  output [1:0] \t\t\t\t       M_AXI_GP1_AWBURST,
+  output [1:0] \t\t\t\t       M_AXI_GP1_AWLOCK,
+  output [2:0] \t\t\t\t       M_AXI_GP1_AWSIZE,
+  output [2:0] \t\t\t\t       M_AXI_GP1_ARPROT,
+  output [2:0] \t\t\t\t       M_AXI_GP1_AWPROT,
+  output [31:0] \t\t\t       M_AXI_GP1_ARADDR,
+  output [31:0] \t\t\t       M_AXI_GP1_AWADDR,
+  output [31:0] \t\t\t       M_AXI_GP1_WDATA,
+  output [3:0] \t\t\t\t       M_AXI_GP1_ARCACHE,
+  output [3:0] \t\t\t\t       M_AXI_GP1_ARLEN,
+  output [3:0] \t\t\t\t       M_AXI_GP1_ARQOS,
+  output [3:0] \t\t\t\t       M_AXI_GP1_AWCACHE,
+  output [3:0] \t\t\t\t       M_AXI_GP1_AWLEN,
+  output [3:0] \t\t\t\t       M_AXI_GP1_AWQOS,
+  output [3:0] \t\t\t\t       M_AXI_GP1_WSTRB,
+  
+  // -- Input
+  
+  input \t\t\t\t       M_AXI_GP1_ACLK,
+  input \t\t\t\t       M_AXI_GP1_ARREADY,
+  input \t\t\t\t       M_AXI_GP1_AWREADY,
+  input \t\t\t\t       M_AXI_GP1_BVALID,
+  input \t\t\t\t       M_AXI_GP1_RLAST,
+  input \t\t\t\t       M_AXI_GP1_RVALID,
+  input \t\t\t\t       M_AXI_GP1_WREADY, 
+  input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0]  M_AXI_GP1_BID,
+  input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0]  M_AXI_GP1_RID,
+  input [1:0] \t\t\t\t       M_AXI_GP1_BRESP,
+  input [1:0] \t\t\t\t       M_AXI_GP1_RRESP,
+  input [31:0] \t\t\t\t       M_AXI_GP1_RDATA, 
+  
+
+  // S_AXI_GP0
+  
+  // -- Output
+  
+  output \t\t\t\t       S_AXI_GP0_ARESETN,
+  output \t\t\t\t       S_AXI_GP0_ARREADY,
+  output \t\t\t\t       S_AXI_GP0_AWREADY,
+  output \t\t\t\t       S_AXI_GP0_BVALID,
+  output \t\t\t\t       S_AXI_GP0_RLAST,
+  output \t\t\t\t       S_AXI_GP0_RVALID,
+  output \t\t\t\t       S_AXI_GP0_WREADY, 
+  output [1:0] \t\t\t\t       S_AXI_GP0_BRESP,
+  output [1:0] \t\t\t\t       S_AXI_GP0_RRESP,
+  output [31:0] \t\t\t       S_AXI_GP0_RDATA,
+  output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0]      S_AXI_GP0_BID,
+  output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0]      S_AXI_GP0_RID,
+  
+  // -- Input
+  input \t\t\t\t       S_AXI_GP0_ACLK,
+  input \t\t\t\t       S_AXI_GP0_ARVALID,
+  input \t\t\t\t       S_AXI_GP0_AWVALID,
+  input \t\t\t\t       S_AXI_GP0_BREADY,
+  input \t\t\t\t       S_AXI_GP0_RREADY,
+  input \t\t\t\t       S_AXI_GP0_WLAST,
+  input \t\t\t\t       S_AXI_GP0_WVALID,
+  input [1:0] \t\t\t\t       S_AXI_GP0_ARBURST,
+  input [1:0] \t\t\t\t       S_AXI_GP0_ARLOCK,
+  input [2:0] \t\t\t\t       S_AXI_GP0_ARSIZE,
+  input [1:0] \t\t\t\t       S_AXI_GP0_AWBURST,
+  input [1:0] \t\t\t\t       S_AXI_GP0_AWLOCK,
+  input [2:0] \t\t\t\t       S_AXI_GP0_AWSIZE,
+  input [2:0] \t\t\t\t       S_AXI_GP0_ARPROT,
+  input [2:0] \t\t\t\t       S_AXI_GP0_AWPROT,
+  input [31:0] \t\t\t\t       S_AXI_GP0_ARADDR,
+  input [31:0] \t\t\t\t       S_AXI_GP0_AWADDR,
+  input [31:0] \t\t\t\t       S_AXI_GP0_WDATA,
+  input [3:0] \t\t\t\t       S_AXI_GP0_ARCACHE,
+  input [3:0] \t\t\t\t       S_AXI_GP0_ARLEN,
+  input [3:0] \t\t\t\t       S_AXI_GP0_ARQOS,
+  input [3:0] \t\t\t\t       S_AXI_GP0_AWCACHE,
+  input [3:0] \t\t\t\t       S_AXI_GP0_AWLEN,
+  input [3:0] \t\t\t\t       S_AXI_GP0_AWQOS,
+  input [3:0] \t\t\t\t       S_AXI_GP0_WSTRB,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0]       S_AXI_GP0_ARID,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0]       S_AXI_GP0_AWID,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0]       S_AXI_GP0_WID, 
+
+  // S_AXI_GP1
+  
+  // -- Output  
+  output \t\t\t\t       S_AXI_GP1_ARESETN,
+  output \t\t\t\t       S_AXI_GP1_ARREADY,
+  output \t\t\t\t       S_AXI_GP1_AWREADY,
+  output \t\t\t\t       S_AXI_GP1_BVALID,
+  output \t\t\t\t       S_AXI_GP1_RLAST,
+  output \t\t\t\t       S_AXI_GP1_RVALID,
+  output \t\t\t\t       S_AXI_GP1_WREADY, 
+  output [1:0] \t\t\t\t       S_AXI_GP1_BRESP,
+  output [1:0] \t\t\t\t       S_AXI_GP1_RRESP,
+  output [31:0] \t\t\t       S_AXI_GP1_RDATA,
+  output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0]      S_AXI_GP1_BID,
+  output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0]      S_AXI_GP1_RID,
+  
+  // -- Input
+  input \t\t\t\t       S_AXI_GP1_ACLK,
+  input \t\t\t\t       S_AXI_GP1_ARVALID,
+  input \t\t\t\t       S_AXI_GP1_AWVALID,
+  input \t\t\t\t       S_AXI_GP1_BREADY,
+  input \t\t\t\t       S_AXI_GP1_RREADY,
+  input \t\t\t\t       S_AXI_GP1_WLAST,
+  input \t\t\t\t       S_AXI_GP1_WVALID,
+  input [1:0] \t\t\t\t       S_AXI_GP1_ARBURST,
+  input [1:0] \t\t\t\t       S_AXI_GP1_ARLOCK,
+  input [2:0] \t\t\t\t       S_AXI_GP1_ARSIZE,
+  input [1:0] \t\t\t\t       S_AXI_GP1_AWBURST,
+  input [1:0] \t\t\t\t       S_AXI_GP1_AWLOCK,
+  input [2:0] \t\t\t\t       S_AXI_GP1_AWSIZE,
+  input [2:0] \t\t\t\t       S_AXI_GP1_ARPROT,
+  input [2:0] \t\t\t\t       S_AXI_GP1_AWPROT,
+  input [31:0] \t\t\t\t       S_AXI_GP1_ARADDR,
+  input [31:0] \t\t\t\t       S_AXI_GP1_AWADDR,
+  input [31:0] \t\t\t\t       S_AXI_GP1_WDATA,
+  input [3:0] \t\t\t\t       S_AXI_GP1_ARCACHE,
+  input [3:0] \t\t\t\t       S_AXI_GP1_ARLEN,
+  input [3:0] \t\t\t\t       S_AXI_GP1_ARQOS,
+  input [3:0] \t\t\t\t       S_AXI_GP1_AWCACHE,
+  input [3:0] \t\t\t\t       S_AXI_GP1_AWLEN,
+  input [3:0] \t\t\t\t       S_AXI_GP1_AWQOS,
+  input [3:0] \t\t\t\t       S_AXI_GP1_WSTRB,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0]       S_AXI_GP1_ARID,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0]       S_AXI_GP1_AWID,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0]       S_AXI_GP1_WID, 
+
+  //S_AXI_ACP
+  
+  // -- Output  
+  
+  output \t\t\t\t       S_AXI_ACP_ARESETN,
+  output \t\t\t\t       S_AXI_ACP_ARREADY,
+  output \t\t\t\t       S_AXI_ACP_AWREADY,
+  output \t\t\t\t       S_AXI_ACP_BVALID,
+  output \t\t\t\t       S_AXI_ACP_RLAST,
+  output \t\t\t\t       S_AXI_ACP_RVALID,
+  output \t\t\t\t       S_AXI_ACP_WREADY, 
+  output [1:0] \t\t\t\t       S_AXI_ACP_BRESP,
+  output [1:0] \t\t\t\t       S_AXI_ACP_RRESP,
+  output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]      S_AXI_ACP_BID,
+  output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]      S_AXI_ACP_RID,
+  output [63:0] \t\t\t       S_AXI_ACP_RDATA,
+  
+  // -- Input
+  
+  input \t\t\t\t       S_AXI_ACP_ACLK,
+  input \t\t\t\t       S_AXI_ACP_ARVALID,
+  input \t\t\t\t       S_AXI_ACP_AWVALID,
+  input \t\t\t\t       S_AXI_ACP_BREADY,
+  input \t\t\t\t       S_AXI_ACP_RREADY,
+  input \t\t\t\t       S_AXI_ACP_WLAST,
+  input \t\t\t\t       S_AXI_ACP_WVALID,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]       S_AXI_ACP_ARID,
+  input [2:0] \t\t\t\t       S_AXI_ACP_ARPROT,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]       S_AXI_ACP_AWID,
+  input [2:0] \t\t\t\t       S_AXI_ACP_AWPROT,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]       S_AXI_ACP_WID,
+  input [31:0] \t\t\t\t       S_AXI_ACP_ARADDR,
+  input [31:0] \t\t\t\t       S_AXI_ACP_AWADDR,
+  input [3:0] \t\t\t\t       S_AXI_ACP_ARCACHE,
+  input [3:0] \t\t\t\t       S_AXI_ACP_ARLEN,
+  input [3:0] \t\t\t\t       S_AXI_ACP_ARQOS,
+  input [3:0] \t\t\t\t       S_AXI_ACP_AWCACHE,
+  input [3:0] \t\t\t\t       S_AXI_ACP_AWLEN,
+  input [3:0] \t\t\t\t       S_AXI_ACP_AWQOS, 
+  input [1:0] \t\t\t\t       S_AXI_ACP_ARBURST,
+  input [1:0] \t\t\t\t       S_AXI_ACP_ARLOCK,
+  input [2:0] \t\t\t\t       S_AXI_ACP_ARSIZE,
+  input [1:0] \t\t\t\t       S_AXI_ACP_AWBURST,
+  input [1:0] \t\t\t\t       S_AXI_ACP_AWLOCK,
+  input [2:0] \t\t\t\t       S_AXI_ACP_AWSIZE,
+  input [4:0] \t\t\t\t       S_AXI_ACP_ARUSER,
+  input [4:0] \t\t\t\t       S_AXI_ACP_AWUSER,
+  input [63:0] \t\t\t\t       S_AXI_ACP_WDATA,
+  input [7:0] \t\t\t\t       S_AXI_ACP_WSTRB, 
+  
+  // S_AXI_HP_0
+  
+  // -- Output
+  output \t\t\t\t       S_AXI_HP0_ARESETN,
+  output \t\t\t\t       S_AXI_HP0_ARREADY,
+  output \t\t\t\t       S_AXI_HP0_AWREADY,
+  output \t\t\t\t       S_AXI_HP0_BVALID,
+  output \t\t\t\t       S_AXI_HP0_RLAST,
+  output \t\t\t\t       S_AXI_HP0_RVALID,
+  output \t\t\t\t       S_AXI_HP0_WREADY, 
+  output [1:0] \t\t\t\t       S_AXI_HP0_BRESP,
+  output [1:0] \t\t\t\t       S_AXI_HP0_RRESP,
+  output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0]      S_AXI_HP0_BID,
+  output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0]      S_AXI_HP0_RID,
+  output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0]     S_AXI_HP0_RDATA,
+  output [7:0] \t\t\t\t       S_AXI_HP0_RCOUNT,
+  output [7:0] \t\t\t\t       S_AXI_HP0_WCOUNT,
+  output [2:0] \t\t\t\t       S_AXI_HP0_RACOUNT,
+  output [5:0] \t\t\t\t       S_AXI_HP0_WACOUNT,
+  
+  // -- Input  
+  input \t\t\t\t       S_AXI_HP0_ACLK,
+  input \t\t\t\t       S_AXI_HP0_ARVALID,
+  input \t\t\t\t       S_AXI_HP0_AWVALID,
+  input \t\t\t\t       S_AXI_HP0_BREADY,
+  input \t\t\t\t       S_AXI_HP0_RDISSUECAP1_EN,
+  input \t\t\t\t       S_AXI_HP0_RREADY,
+  input \t\t\t\t       S_AXI_HP0_WLAST,
+  input \t\t\t\t       S_AXI_HP0_WRISSUECAP1_EN,
+  input \t\t\t\t       S_AXI_HP0_WVALID,
+  input [1:0] \t\t\t\t       S_AXI_HP0_ARBURST,
+  input [1:0] \t\t\t\t       S_AXI_HP0_ARLOCK,
+  input [2:0] \t\t\t\t       S_AXI_HP0_ARSIZE,
+  input [1:0] \t\t\t\t       S_AXI_HP0_AWBURST,
+  input [1:0] \t\t\t\t       S_AXI_HP0_AWLOCK,
+  input [2:0] \t\t\t\t       S_AXI_HP0_AWSIZE,
+  input [2:0] \t\t\t\t       S_AXI_HP0_ARPROT,
+  input [2:0] \t\t\t\t       S_AXI_HP0_AWPROT,
+  input [31:0] \t\t\t\t       S_AXI_HP0_ARADDR,
+  input [31:0] \t\t\t\t       S_AXI_HP0_AWADDR,
+  input [3:0] \t\t\t\t       S_AXI_HP0_ARCACHE,
+  input [3:0] \t\t\t\t       S_AXI_HP0_ARLEN,
+  input [3:0] \t\t\t\t       S_AXI_HP0_ARQOS,
+  input [3:0] \t\t\t\t       S_AXI_HP0_AWCACHE,
+  input [3:0] \t\t\t\t       S_AXI_HP0_AWLEN,
+  input [3:0] \t\t\t\t       S_AXI_HP0_AWQOS,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0]       S_AXI_HP0_ARID,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0]       S_AXI_HP0_AWID,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0]       S_AXI_HP0_WID,
+  input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0]      S_AXI_HP0_WDATA,
+  input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0]     S_AXI_HP0_WSTRB, 
+
+  // S_AXI_HP1
+  // -- Output
+  output \t\t\t\t       S_AXI_HP1_ARESETN,
+  output \t\t\t\t       S_AXI_HP1_ARREADY,
+  output \t\t\t\t       S_AXI_HP1_AWREADY,
+  output \t\t\t\t       S_AXI_HP1_BVALID,
+  output \t\t\t\t       S_AXI_HP1_RLAST,
+  output \t\t\t\t       S_AXI_HP1_RVALID,
+  output \t\t\t\t       S_AXI_HP1_WREADY, 
+  output [1:0] \t\t\t\t       S_AXI_HP1_BRESP,
+  output [1:0] \t\t\t\t       S_AXI_HP1_RRESP,
+  output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0]      S_AXI_HP1_BID,
+  output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0]      S_AXI_HP1_RID,
+  output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0]     S_AXI_HP1_RDATA,
+  output [7:0] \t\t\t\t       S_AXI_HP1_RCOUNT,
+  output [7:0] \t\t\t\t       S_AXI_HP1_WCOUNT,
+  output [2:0] \t\t\t\t       S_AXI_HP1_RACOUNT,
+  output [5:0] \t\t\t\t       S_AXI_HP1_WACOUNT,
+  
+  
+  // -- Input  
+  input \t\t\t\t       S_AXI_HP1_ACLK,
+  input \t\t\t\t       S_AXI_HP1_ARVALID,
+  input \t\t\t\t       S_AXI_HP1_AWVALID,
+  input \t\t\t\t       S_AXI_HP1_BREADY,
+  input \t\t\t\t       S_AXI_HP1_RDISSUECAP1_EN,
+  input \t\t\t\t       S_AXI_HP1_RREADY,
+  input \t\t\t\t       S_AXI_HP1_WLAST,
+  input \t\t\t\t       S_AXI_HP1_WRISSUECAP1_EN,
+  input \t\t\t\t       S_AXI_HP1_WVALID,
+  input [1:0] \t\t\t\t       S_AXI_HP1_ARBURST,
+  input [1:0] \t\t\t\t       S_AXI_HP1_ARLOCK,
+  input [2:0] \t\t\t\t       S_AXI_HP1_ARSIZE,
+  input [1:0] \t\t\t\t       S_AXI_HP1_AWBURST,
+  input [1:0] \t\t\t\t       S_AXI_HP1_AWLOCK,
+  input [2:0] \t\t\t\t       S_AXI_HP1_AWSIZE,
+  input [2:0] \t\t\t\t       S_AXI_HP1_ARPROT,
+  input [2:0] \t\t\t\t       S_AXI_HP1_AWPROT,
+  input [31:0] \t\t\t\t       S_AXI_HP1_ARADDR,
+  input [31:0] \t\t\t\t       S_AXI_HP1_AWADDR,
+  input [3:0] \t\t\t\t       S_AXI_HP1_ARCACHE,
+  input [3:0] \t\t\t\t       S_AXI_HP1_ARLEN,
+  input [3:0] \t\t\t\t       S_AXI_HP1_ARQOS,
+  input [3:0] \t\t\t\t       S_AXI_HP1_AWCACHE,
+  input [3:0] \t\t\t\t       S_AXI_HP1_AWLEN,
+  input [3:0] \t\t\t\t       S_AXI_HP1_AWQOS,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0]       S_AXI_HP1_ARID,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0]       S_AXI_HP1_AWID,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0]       S_AXI_HP1_WID,
+  input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0]      S_AXI_HP1_WDATA,
+  input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0]     S_AXI_HP1_WSTRB, 
+
+  // S_AXI_HP2
+  // -- Output
+  output \t\t\t\t       S_AXI_HP2_ARESETN,
+  output \t\t\t\t       S_AXI_HP2_ARREADY,
+  output \t\t\t\t       S_AXI_HP2_AWREADY,
+  output \t\t\t\t       S_AXI_HP2_BVALID,
+  output \t\t\t\t       S_AXI_HP2_RLAST,
+  output \t\t\t\t       S_AXI_HP2_RVALID,
+  output \t\t\t\t       S_AXI_HP2_WREADY, 
+  output [1:0] \t\t\t\t       S_AXI_HP2_BRESP,
+  output [1:0] \t\t\t\t       S_AXI_HP2_RRESP,
+  output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0]      S_AXI_HP2_BID,
+  output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0]      S_AXI_HP2_RID,
+  output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0]     S_AXI_HP2_RDATA,
+  output [7:0] \t\t\t\t       S_AXI_HP2_RCOUNT,
+  output [7:0] \t\t\t\t       S_AXI_HP2_WCOUNT,
+  output [2:0] \t\t\t\t       S_AXI_HP2_RACOUNT,
+  output [5:0] \t\t\t\t       S_AXI_HP2_WACOUNT,
+  
+  
+  // -- Input  
+  input \t\t\t\t       S_AXI_HP2_ACLK,
+  input \t\t\t\t       S_AXI_HP2_ARVALID,
+  input \t\t\t\t       S_AXI_HP2_AWVALID,
+  input \t\t\t\t       S_AXI_HP2_BREADY,
+  input \t\t\t\t       S_AXI_HP2_RDISSUECAP1_EN,
+  input \t\t\t\t       S_AXI_HP2_RREADY,
+  input \t\t\t\t       S_AXI_HP2_WLAST,
+  input \t\t\t\t       S_AXI_HP2_WRISSUECAP1_EN,
+  input \t\t\t\t       S_AXI_HP2_WVALID,
+  input [1:0] \t\t\t\t       S_AXI_HP2_ARBURST,
+  input [1:0] \t\t\t\t       S_AXI_HP2_ARLOCK,
+  input [2:0] \t\t\t\t       S_AXI_HP2_ARSIZE,
+  input [1:0] \t\t\t\t       S_AXI_HP2_AWBURST,
+  input [1:0] \t\t\t\t       S_AXI_HP2_AWLOCK,
+  input [2:0] \t\t\t\t       S_AXI_HP2_AWSIZE,
+  input [2:0] \t\t\t\t       S_AXI_HP2_ARPROT,
+  input [2:0] \t\t\t\t       S_AXI_HP2_AWPROT,
+  input [31:0] \t\t\t\t       S_AXI_HP2_ARADDR,
+  input [31:0] \t\t\t\t       S_AXI_HP2_AWADDR,
+  input [3:0] \t\t\t\t       S_AXI_HP2_ARCACHE,
+  input [3:0] \t\t\t\t       S_AXI_HP2_ARLEN,
+  input [3:0] \t\t\t\t       S_AXI_HP2_ARQOS,
+  input [3:0] \t\t\t\t       S_AXI_HP2_AWCACHE,
+  input [3:0] \t\t\t\t       S_AXI_HP2_AWLEN,
+  input [3:0] \t\t\t\t       S_AXI_HP2_AWQOS,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0]       S_AXI_HP2_ARID,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0]       S_AXI_HP2_AWID,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0]       S_AXI_HP2_WID,
+  input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0]      S_AXI_HP2_WDATA,
+  input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0]     S_AXI_HP2_WSTRB, 
+
+  // S_AXI_HP_3
+  
+  // -- Output
+  output \t\t\t\t       S_AXI_HP3_ARESETN,
+  output \t\t\t\t       S_AXI_HP3_ARREADY,
+  output \t\t\t\t       S_AXI_HP3_AWREADY,
+  output \t\t\t\t       S_AXI_HP3_BVALID,
+  output \t\t\t\t       S_AXI_HP3_RLAST,
+  output \t\t\t\t       S_AXI_HP3_RVALID,
+  output \t\t\t\t       S_AXI_HP3_WREADY, 
+  output [1:0] \t\t\t\t       S_AXI_HP3_BRESP,
+  output [1:0] \t\t\t\t       S_AXI_HP3_RRESP,
+  output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0]      S_AXI_HP3_BID,
+  output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0]      S_AXI_HP3_RID,
+  output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0]     S_AXI_HP3_RDATA,
+  output [7:0] \t\t\t\t       S_AXI_HP3_RCOUNT,
+  output [7:0] \t\t\t\t       S_AXI_HP3_WCOUNT,
+  output [2:0] \t\t\t\t       S_AXI_HP3_RACOUNT,
+  output [5:0] \t\t\t\t       S_AXI_HP3_WACOUNT,
+  
+  
+  // -- Input  
+  input \t\t\t\t       S_AXI_HP3_ACLK,
+  input \t\t\t\t       S_AXI_HP3_ARVALID,
+  input \t\t\t\t       S_AXI_HP3_AWVALID,
+  input \t\t\t\t       S_AXI_HP3_BREADY,
+  input \t\t\t\t       S_AXI_HP3_RDISSUECAP1_EN,
+  input \t\t\t\t       S_AXI_HP3_RREADY,
+  input \t\t\t\t       S_AXI_HP3_WLAST,
+  input \t\t\t\t       S_AXI_HP3_WRISSUECAP1_EN,
+  input \t\t\t\t       S_AXI_HP3_WVALID,
+  input [1:0] \t\t\t\t       S_AXI_HP3_ARBURST,
+  input [1:0] \t\t\t\t       S_AXI_HP3_ARLOCK,
+  input [2:0] \t\t\t\t       S_AXI_HP3_ARSIZE,
+  input [1:0] \t\t\t\t       S_AXI_HP3_AWBURST,
+  input [1:0] \t\t\t\t       S_AXI_HP3_AWLOCK,
+  input [2:0] \t\t\t\t       S_AXI_HP3_AWSIZE,
+  input [2:0] \t\t\t\t       S_AXI_HP3_ARPROT,
+  input [2:0] \t\t\t\t       S_AXI_HP3_AWPROT,
+  input [31:0] \t\t\t\t       S_AXI_HP3_ARADDR,
+  input [31:0] \t\t\t\t       S_AXI_HP3_AWADDR,
+  input [3:0] \t\t\t\t       S_AXI_HP3_ARCACHE,
+  input [3:0] \t\t\t\t       S_AXI_HP3_ARLEN,
+  input [3:0] \t\t\t\t       S_AXI_HP3_ARQOS,
+  input [3:0] \t\t\t\t       S_AXI_HP3_AWCACHE,
+  input [3:0] \t\t\t\t       S_AXI_HP3_AWLEN,
+  input [3:0] \t\t\t\t       S_AXI_HP3_AWQOS,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0]       S_AXI_HP3_ARID,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0]       S_AXI_HP3_AWID,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0]       S_AXI_HP3_WID,
+  input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0]      S_AXI_HP3_WDATA,
+  input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0]     S_AXI_HP3_WSTRB, 
+  
+  //FIO ========================================
+
+  //IRQ
+  output \t\t\t\t       IRQ_P2F_DMAC_ABORT ,
+  output \t\t\t\t       IRQ_P2F_DMAC0,
+  output \t\t\t\t       IRQ_P2F_DMAC1,
+  output \t\t\t\t       IRQ_P2F_DMAC2,
+  output \t\t\t\t       IRQ_P2F_DMAC3,
+  output \t\t\t\t       IRQ_P2F_DMAC4,
+  output \t\t\t\t       IRQ_P2F_DMAC5,
+  output \t\t\t\t       IRQ_P2F_DMAC6,
+  output \t\t\t\t       IRQ_P2F_DMAC7,
+  output \t\t\t\t       IRQ_P2F_SMC,
+  output \t\t\t\t       IRQ_P2F_QSPI,
+  output \t\t\t\t       IRQ_P2F_CTI,
+  output \t\t\t\t       IRQ_P2F_GPIO,
+  output \t\t\t\t       IRQ_P2F_USB0,
+  output \t\t\t\t       IRQ_P2F_ENET0,
+  output \t\t\t\t       IRQ_P2F_ENET_WAKE0,
+  output \t\t\t\t       IRQ_P2F_SDIO0,
+  output \t\t\t\t       IRQ_P2F_I2C0,
+  output \t\t\t\t       IRQ_P2F_SPI0,
+  output \t\t\t\t       IRQ_P2F_UART0,
+  output \t\t\t\t       IRQ_P2F_CAN0,
+  output \t\t\t\t       IRQ_P2F_USB1,
+  output \t\t\t\t       IRQ_P2F_ENET1,
+  output \t\t\t\t       IRQ_P2F_ENET_WAKE1,
+  output \t\t\t\t       IRQ_P2F_SDIO1,
+  output \t\t\t\t       IRQ_P2F_I2C1,
+  output \t\t\t\t       IRQ_P2F_SPI1,
+  output \t\t\t\t       IRQ_P2F_UART1,
+  output \t\t\t\t       IRQ_P2F_CAN1,
+  input [(C_NUM_F2P_INTR_INPUTS-1):0] \t       IRQ_F2P,
+  input \t\t\t\t       Core0_nFIQ,
+  input \t\t\t\t       Core0_nIRQ,
+  input \t\t\t\t       Core1_nFIQ,
+  input \t\t\t\t       Core1_nIRQ,
+
+  //DMA
+
+  output [1:0] \t\t\t\t       DMA0_DATYPE, 
+  output \t\t\t\t       DMA0_DAVALID,
+  output \t\t\t\t       DMA0_DRREADY,
+  output \t\t\t\t       DMA0_RSTN, 
+  output [1:0] \t\t\t\t       DMA1_DATYPE, 
+  output \t\t\t\t       DMA1_DAVALID,
+  output \t\t\t\t       DMA1_DRREADY,
+  output \t\t\t\t       DMA1_RSTN, 
+  output [1:0] \t\t\t\t       DMA2_DATYPE, 
+  output \t\t\t\t       DMA2_DAVALID,
+  output \t\t\t\t       DMA2_DRREADY,
+  output \t\t\t\t       DMA2_RSTN, 
+  output [1:0] \t\t\t\t       DMA3_DATYPE, 
+  output \t\t\t\t       DMA3_DAVALID,
+  output \t\t\t\t       DMA3_DRREADY,
+  output \t\t\t\t       DMA3_RSTN, 
+  input \t\t\t\t       DMA0_ACLK,
+  input \t\t\t\t       DMA0_DAREADY,
+  input \t\t\t\t       DMA0_DRLAST,
+  input \t\t\t\t       DMA0_DRVALID,
+  input \t\t\t\t       DMA1_ACLK,
+  input \t\t\t\t       DMA1_DAREADY,
+  input \t\t\t\t       DMA1_DRLAST,
+  input \t\t\t\t       DMA1_DRVALID,
+  input \t\t\t\t       DMA2_ACLK,
+  input \t\t\t\t       DMA2_DAREADY,
+  input \t\t\t\t       DMA2_DRLAST,
+  input \t\t\t\t       DMA2_DRVALID,
+  input \t\t\t\t       DMA3_ACLK,
+  input \t\t\t\t       DMA3_DAREADY,
+  input \t\t\t\t       DMA3_DRLAST,
+  input \t\t\t\t       DMA3_DRVALID, 
+  input [1:0] \t\t\t\t       DMA0_DRTYPE,
+  input [1:0] \t\t\t\t       DMA1_DRTYPE,
+  input [1:0] \t\t\t\t       DMA2_DRTYPE,
+  input [1:0] \t\t\t\t       DMA3_DRTYPE,
+  
+  //FCLK
+  output \t\t\t\t       FCLK_CLK3,
+  output \t\t\t\t       FCLK_CLK2,
+  output \t\t\t\t       FCLK_CLK1,
+  output \t\t\t\t       FCLK_CLK0,
+ 
+  input \t\t\t\t       FCLK_CLKTRIG3_N,
+  input \t\t\t\t       FCLK_CLKTRIG2_N,
+  input \t\t\t\t       FCLK_CLKTRIG1_N,
+  input \t\t\t\t       FCLK_CLKTRIG0_N,
+ 
+  output \t\t\t\t       FCLK_RESET3_N,
+  output \t\t\t\t       FCLK_RESET2_N,
+  output \t\t\t\t       FCLK_RESET1_N,
+  output \t\t\t\t       FCLK_RESET0_N,
+
+  //FTMD
+  input [31:0] \t\t\t\t       FTMD_TRACEIN_DATA,
+  input \t\t\t\t       FTMD_TRACEIN_VALID,
+  input \t\t\t\t       FTMD_TRACEIN_CLK,
+  input [3:0] \t\t\t\t       FTMD_TRACEIN_ATID,
+
+  //FTMT
+  input \t\t\t\t       FTMT_F2P_TRIG_0,
+  output \t\t\t\t       FTMT_F2P_TRIGACK_0,
+  input \t\t\t\t       FTMT_F2P_TRIG_1,
+  output \t\t\t\t       FTMT_F2P_TRIGACK_1,
+  input \t\t\t\t       FTMT_F2P_TRIG_2,
+  output \t\t\t\t       FTMT_F2P_TRIGACK_2,
+  input \t\t\t\t       FTMT_F2P_TRIG_3,
+  output \t\t\t\t       FTMT_F2P_TRIGACK_3,
+  input [31:0] \t\t\t\t       FTMT_F2P_DEBUG, 
+  input \t\t\t\t       FTMT_P2F_TRIGACK_0,
+  output \t\t\t\t       FTMT_P2F_TRIG_0,
+  input \t\t\t\t       FTMT_P2F_TRIGACK_1,
+  output \t\t\t\t       FTMT_P2F_TRIG_1,
+  input \t\t\t\t       FTMT_P2F_TRIGACK_2,
+  output \t\t\t\t       FTMT_P2F_TRIG_2,
+  input \t\t\t\t       FTMT_P2F_TRIGACK_3,
+  output \t\t\t\t       FTMT_P2F_TRIG_3,
+  output [31:0] \t\t\t       FTMT_P2F_DEBUG,
+
+  //FIDLE
+  input \t\t\t\t       FPGA_IDLE_N,
+  
+  //EVENT
+
+  output \t\t\t\t       EVENT_EVENTO,
+  output [1:0] \t\t\t\t       EVENT_STANDBYWFE,
+  output [1:0] \t\t\t\t       EVENT_STANDBYWFI, 
+  input \t\t\t\t       EVENT_EVENTI, 
+  
+
+  //DARB
+  input [3:0] \t\t\t\t       DDR_ARB,
+  inout [C_MIO_PRIMITIVE - 1:0] \t       MIO, 
+  
+  //DDR
+  inout \t\t\t\t       DDR_CAS_n, // CASB
+  inout \t\t\t\t       DDR_CKE, // CKE
+  inout \t\t\t\t       DDR_Clk_n, // CKN
+  inout \t\t\t\t       DDR_Clk, // CKP
+  inout \t\t\t\t       DDR_CS_n, // CSB 
+  inout \t\t\t\t       DDR_DRSTB, // DDR_DRSTB  
+  inout \t\t\t\t       DDR_ODT, // ODT
+  inout \t\t\t\t       DDR_RAS_n, // RASB
+  inout \t\t\t\t       DDR_WEB,
+  inout [2:0] \t\t\t\t       DDR_BankAddr, // BA  
+  inout [14:0] \t\t\t\t       DDR_Addr, // A
+  
+  inout \t\t\t\t       DDR_VRN,
+  inout \t\t\t\t       DDR_VRP,
+  inout [C_DM_WIDTH - 1:0] \t\t       DDR_DM, // DM  
+  inout [C_DQ_WIDTH - 1:0] \t\t       DDR_DQ, // DQ
+  inout [C_DQS_WIDTH -1:0] \t\t       DDR_DQS_n, // DQSN
+  inout [C_DQS_WIDTH - 1:0] \t\t       DDR_DQS, // DQSP
+  
+  inout \t\t\t\t       PS_SRSTB, // SRSTB    
+  inout \t\t\t\t       PS_CLK, // CLK
+  inout \t\t\t\t       PS_PORB         // PORB 
+
+);
+
+endmodule // processing_system7
+
+
+
+"
+"`ifndef ELINK_CONSTANTS_V_
+`define ELINK_CONSTANTS_V_
+
+//These constants are mutually exclusive
+`define TARGET_XILINX
+`define CFG_AW 32
+`define CFG_DW 32
+`define CFG_LW 8
+`define CFG_NW        13     /*Number of bytes in the transmission*/
+
+`endif
+"
+"module erx_timer (/*AUTOARG*/
+   // Outputs
+   timeout,
+   // Inputs
+   clk, reset, timer_cfg, stop_count, start_count
+   );
+
+   parameter DW = 32;
+   parameter AW = 32;
+   
+   input          clk;
+   input \t  reset;   
+   input [1:0] \t  timer_cfg; //masks MSB of each byte (all zero is off) 
+   input \t  stop_count; 
+   input \t  start_count;
+   
+   output \t  timeout;
+
+   reg [31:0] \t  timeout_reg;
+   reg \t\t  do_count;
+   wire \t  timer_en;
+   wire \t  start_count_sync;
+   
+
+
+   //Synchronize the start count
+   synchronizer #(.DW(1)) sync(
+\t\t\t       // Outputs
+\t\t\t       .out\t\t(start_count_sync),
+\t\t\t       // Inputs
+\t\t\t       .in\t\t(start_count),
+\t\t\t       .clk\t\t(clk),
+\t\t\t       .reset\t\t(reset)
+\t\t\t       );
+   
+   
+   assign timer_en = |(timer_cfg[1:0]);
+   
+  
+   always @ (posedge clk)
+     if(reset)
+       begin
+\t  do_count <=1\'b0;\t  
+\t  timeout_reg[31:0] <= 32\'hffffffff;
+       end
+     else if(start_count_sync & timer_en)
+       begin
+\t  do_count <=1\'b1;\t  
+\t  timeout_reg[31:0] <= (timer_cfg[1:0]==2\'b01) ? 32\'h000000ff :
+\t\t\t       (timer_cfg[1:0]==2\'b10) ? 32\'h0000ffff :
+\t\t\t                                 32\'hffffffff;
+       end
+     else if(stop_count)
+       begin
+\t  do_count <=1\'b0;
+       end
+     else if(timer_expired)
+       begin
+\t  do_count <=1\'b0;
+\t  timeout_reg[31:0] <= 32\'hffffffff;
+       end
+     else if(do_count)
+       begin
+\t  timeout_reg[31:0] <= timeout_reg[31:0]-1\'b1;\t  
+       end
+   
+\t     
+   assign timer_expired = ~(|timeout_reg[31:0]);
+   
+   assign timeout = timer_en & timer_expired;
+   
+endmodule // erx_timeout
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"" )
+// End:
+"
+"/*Converts an emesh bundle into a 104 bit packet*/
+module emesh2packet(/*AUTOARG*/
+   // Outputs
+   packet_out,
+   // Inputs
+   access_in, write_in, datamode_in, ctrlmode_in, dstaddr_in, data_in,
+   srcaddr_in
+   );
+
+   parameter AW=32;
+   parameter DW=32;
+   parameter PW=104;
+   
+   //Emesh signal bundle
+   input \t    access_in;
+   input \t    write_in;   
+   input [1:0] \t    datamode_in;
+   input [3:0] \t    ctrlmode_in;
+   input [AW-1:0]   dstaddr_in;
+   input [DW-1:0]   data_in;   
+   input [AW-1:0]   srcaddr_in;   
+   
+   //Output packet
+   output [PW-1:0]  packet_out;
+
+   assign packet_out[0]       = access_in;
+   assign packet_out[1]       = write_in;
+   assign packet_out[3:2]     = datamode_in[1:0];
+   assign packet_out[7:4]     = ctrlmode_in[3:0];
+   assign packet_out[39:8]    = dstaddr_in[AW-1:0];
+   assign packet_out[71:40]   = data_in[AW-1:0];
+   assign packet_out[103:72]  = srcaddr_in[AW-1:0];
+     
+endmodule // emesh2packet
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"module pulse2pulse(/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   inclk, outclk, in, reset
+   );
+
+   input  in;      //input pulse (one clock cycle)
+   input  inclk;   //input clock
+   output out;     //one cycle wide pulse
+   input  outclk;      
+
+
+   //reset
+   input  reset;
+
+   wire   intoggle;
+   wire   insync;
+   
+   
+   //pulse to toggle
+   pulse2toggle    pulse2toggle(
+\t\t\t\t// Outputs
+\t\t\t\t.out\t\t(intoggle),
+\t\t\t\t// Inputs
+\t\t\t\t.clk\t\t(inclk),
+\t\t\t\t.in\t\t(in),
+\t\t\t\t.reset\t\t(reset));
+   
+   //metastability synchronizer
+   synchronizer #(1) synchronizer(
+\t\t\t\t  // Outputs
+\t\t\t\t  .out\t\t(insync),
+\t\t\t\t  // Inputs
+\t\t\t\t  .in\t\t(intoggle),
+\t\t\t\t  .clk\t\t(outclk),
+\t\t\t\t  .reset\t(reset));
+   
+   
+   //toogle to pulse
+   toggle2pulse toggle2pulse(
+\t\t\t     // Outputs
+\t\t\t     .out\t\t(out),
+\t\t\t     // Inputs
+\t\t\t     .clk\t\t(outclk),
+\t\t\t     .in\t\t(insync),
+\t\t\t     .reset\t\t(reset));
+   
+
+   
+endmodule // pulse2pulse
+
+
+/*
+ Copyright (C) 2015 Adapteva, Inc. 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+"
+"`ifndef ELINK_REGMAP_V_
+`define ELINK_REGMAP_V_
+
+//MEMORY MAP
+
+//[31:20] = LINKID
+//[19:16] = GROUP SELECT
+//[15]    = MMU SELECT (for RX/TX)
+//[14:11]  = USED BY MMU ONLY
+//[10:8]  = register group
+//[7:2]   = REGISTER ADDRESS (0..63)
+//[1:0]   = IGNORED (no byte access)
+
+//Link register groups addr[19:16]
+`define EGROUP_MMR     4'hF // reserved for registers
+`define EGROUP_MMU     4'hE // RX & TX MMU
+`define EGROUP_RR      4'hD // read response block
+
+//ETX-REGS
+`define E_RESET        6'd0 //F0200-reset
+`define E_CLK          6'd1 //F0204-clock configuration
+`define E_CHIPID       6'd2 //F0208-Epiphany chip id for colid/rowid pins 
+`define E_VERSION      6'd3 //F020C-version #
+`define ETX_CFG        6'd4 //F0210-config
+`define ETX_STATUS     6'd5 //F0214-tx status
+`define ETX_GPIO       6'd6 //F0218-direct data for tx pins
+
+//ERX-REGS
+`define ERX_CFG        6'd0 //F0300-config
+`define ERX_STATUS     6'd1 //F0304-status register
+`define ERX_GPIO       6'd2 //F0308-sampled data
+`define ERX_OFFSET     6'd3 //F030C-memory base for remap
+`define E_MAILBOXLO    6'd4 //F0314-reserved-->move?
+`define E_MAILBOXHI    6'd5 //F0318-reserved
+
+//DMA (same numbering as in Epiphany, limit to 4 channels)
+`define DMACFG         5'd0 //F0500/F0520
+`define DMACOUNT       5'd1 //F0504/F0524
+`define DMASTRIDE      5'd2 //F0508/F0528
+`define DMASRCADDR     5'd3 //F050C/F052c
+`define DMADSTADDR     5'd4 //F0510/F0530
+`define DMAAUTO0       5'd5 //F0514/F0534
+`define DMAAUTO1       5'd6 //F0518/F0538
+`define DMASTATUS      5'd7 //F051C/F053c
+
+`endif
+"
+"/*
+ ###########################################################################
+ # **EMMU**
+ # 
+ # This block uses the upper 12 bits [31:20] of a memory address as an index
+ # to read an entry from a table.
+ #
+ # The table is written from the mi_* configuration interface.
+ #
+ # The table can be configured as 12 bits wide or 44 bits wide.
+ #
+ # 32bit address output = {table_data[11:0],dstaddr[19:0]}
+ # 64bit address output = {table_data[43:0],dstaddr[19:0]}
+ #
+ ############################################################################
+ */
+ 
+module emmu (/*AUTOARG*/
+   // Outputs
+   mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out,
+   // Inputs
+   reset, rd_clk, wr_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr,
+   mi_din, emesh_access_in, emesh_packet_in, emesh_rd_wait,
+   emesh_wr_wait
+   );
+   parameter DW     = 32;         //data width
+   parameter AW     = 32;         //address width 
+   parameter PW     = 104;
+   parameter EPW    = 136;        //extended by 32 bits
+   parameter MW     = 48;         //width of table
+   parameter MAW    = 12;         //memory addres width (entries = 1<<MAW)   
+   parameter GROUP  = 0;
+   
+   /*****************************/
+   /*DATAPATH CLOCk             */
+   /*****************************/  
+   input \t     reset;
+   input \t     rd_clk;
+   input \t     wr_clk;
+
+   /*****************************/
+   /*MMU LOOKUP DATA            */
+   /*****************************/
+   input \t     mmu_en;              //enables mmu (static)
+   input \t     mmu_bp;              //bypass mmu on read response
+
+   /*****************************/
+   /*Register Access Interface  */
+   /*****************************/  
+   input \t     mi_en;               //memory access 
+   input  \t     mi_we;               //byte wise write enable
+   input [14:0]      mi_addr;             //address
+   input [DW-1:0]    mi_din;              //input data  
+   output [DW-1:0]   mi_dout;             //read back (TODO?? not implemented)
+  
+   /*****************************/
+   /*EMESH INPUTS               */
+   /*****************************/  
+   input \t     emesh_access_in;
+   input [PW-1:0]    emesh_packet_in;
+   input \t     emesh_rd_wait;
+   input \t     emesh_wr_wait;
+
+   /*****************************/
+   /*EMESH OUTPUTS              */
+   /*****************************/
+   output \t     emesh_access_out;
+   output [PW-1:0]   emesh_packet_out;   
+   output [31:0]     emesh_packet_hi_out;
+   
+   /*****************************/
+   /*REGISTERS                  */
+   /*****************************/
+   reg \t\t      emesh_access_out;
+   reg [PW-1:0]       emesh_packet_reg;
+
+   wire [63:0] \t      emesh_dstaddr_out;   
+   wire [MW-1:0]      emmu_lookup_data;
+   wire [63:0] \t      mi_wr_data;
+   wire [5:0] \t      mi_wr_vec;
+   wire \t      mi_match;
+   wire [MW-1:0]      emmu_rd_addr;
+   wire \t      write_in;
+
+   /*****************************/
+   /*MMU WRITE LOGIC            */
+   /*****************************/
+
+   //write controls
+   assign mi_wr_vec[5:0] = (mi_en & mi_we & ~mi_addr[2]) ? 6\'b001111 :
+\t                   (mi_en & mi_we & mi_addr[2])  ? 6\'b110000 :
+\t\t\t                                   6\'b000000 ;
+
+   //write data
+   assign mi_wr_data[63:0] = {mi_din[31:0], mi_din[31:0]};
+
+   //todo: implement readback? worth it?
+   assign mi_dout[DW-1:0] = \'b0;
+
+   /*****************************/
+   /*MMU READ  LOGIC            */
+   /*****************************/
+   //TODO: could we do with less entries?
+   
+   assign write_in              = emesh_packet_in[1];
+   assign emmu_rd_addr[MAW-1:0] = emesh_packet_in[39:28];
+   
+   memory_dp #(.DW(MW),.AW(MAW)) memory_dp (
+\t\t\t\t\t   // Outputs
+\t\t\t\t\t   .rd_data\t\t(emmu_lookup_data[MW-1:0]),
+\t\t\t\t\t   // Inputs
+\t\t\t\t\t   .wr_clk\t\t(wr_clk),
+\t\t\t\t\t   .wr_en\t\t(mi_wr_vec[5:0]),
+\t\t\t\t\t   .wr_addr\t\t(mi_addr[14:3]),
+\t\t\t\t\t   .wr_data\t\t(mi_wr_data[MW-1:0]),
+\t\t\t\t\t   .rd_clk\t\t(rd_clk),
+\t\t\t\t\t   .rd_en\t\t(emesh_access_in),
+\t\t\t\t\t   .rd_addr\t\t(emmu_rd_addr[MAW-1:0])
+\t\t\t\t\t   );
+   \t\t       
+   /*****************************/
+   /*EMESH OUTPUT TRANSACTION   */
+   /*****************************/   
+   //pipeline to compensate for table lookup pipeline 
+   //assumes one cycle memory access!     
+
+
+    always @ (posedge  rd_clk)     
+     if (reset)
+       begin
+\t  emesh_access_out         <= 1\'b0;\t  
+       end
+     else if((write_in & ~emesh_wr_wait) | (~write_in & ~emesh_rd_wait))
+       begin
+\t  emesh_access_out         <= emesh_access_in;
+\t  emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];\t  
+       end
+     \t 
+   assign emesh_dstaddr_out[63:0] = (mmu_en & ~mmu_bp) ? {emmu_lookup_data[43:0], emesh_packet_reg[27:8]} :
+\t\t\t\t                         {32\'b0,emesh_packet_reg[39:8]}; 
+      
+   //Concatenating output packet
+   assign emesh_packet_out[PW-1:0] = {emesh_packet_reg[PW-1:40],
+                                     emesh_dstaddr_out[31:0],
+                                     emesh_packet_reg[7:0]
+\t\t\t\t    };
+   
+
+   assign emesh_packet_hi_out[31:0] = emesh_dstaddr_out[63:32];
+      
+endmodule // emmu
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"" ""../../memory/hdl"")
+// End:
+
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+
+
+   
+"
+"/*WARNING: INCOMPLETE MODEL, DON'T USE. I RECOMMEND AGAINST USING THIS
+ *BLOCK ALL TOGETHER. NOT OPEN SOURCE FRIENDLY /AO
+ */
+
+module OSERDESE2 ( /*AUTOARG*/
+   // Outputs
+   OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ,
+   // Inputs
+   CLK, CLKDIV, D1, D2, D3, D4, D5, D6, D7, D8, OCE, RST, SHIFTIN1,
+   SHIFTIN2, T1, T2, T3, T4, TBYTEIN, TCE
+   );
+
+   parameter DATA_RATE_OQ=0;
+   parameter DATA_RATE_TQ=0;
+   parameter DATA_WIDTH=0;
+   parameter INIT_OQ=0;
+   parameter INIT_TQ=0;
+   parameter SERDES_MODE=0;
+   parameter SRVAL_OQ=0;
+   parameter SRVAL_TQ=0;
+   parameter TBYTE_CTL=0;
+   parameter TBYTE_SRC=0;
+   parameter TRISTATE_WIDTH=0;
+
+     
+   output OFB;                    // output feedback port
+   output OQ;                     // data output port, D1 appears first
+   output SHIFTOUT1;              // connect to shift in of master
+   output SHIFTOUT2;              // connect to shift in of master
+   output TBYTEOUT;               // byte group tristate output to IOB
+   output TFB;                    // 3-state control output for ODELAYE2
+   output TQ;                     // 3-state control output
+   input  CLK;                    // high speed shift out clock
+   input  CLKDIV;                 // low speed clock (/4 for example)
+   input  D1;                     // first bit to shift out
+   input  D2;                     //
+   input  D3;                     //
+   input  D4;                     //
+   input  D5;                     //
+   input  D6;                     //
+   input  D7;                     //
+   input  D8;                     //
+   input  OCE;                    // active high clock enable for datapath
+   input  RST;                    // async reset, all output flops driven low
+   input  SHIFTIN1;               // connect to shift out of other
+   input  SHIFTIN2;               // connect to shift out of other
+   input  T1;                     // parallel 3-state signals
+   input  T2;                     // ??why 4??
+   input  T3;                     //
+   input  T4;                     //
+   input  TBYTEIN;                // byte group tristate input
+   input  TCE;                    // active high clock enable for 3-state
+
+   //Statemachine
+   reg [2:0] state;
+
+
+   reg [7:0] buffer;
+   reg [1:0] clkdiv_sample;
+   reg [3:0] even;
+   reg [3:0] odd;
+   
+   //parallel sample
+   always @ (posedge CLKDIV)
+     buffer[7:0]<={D8,D7,D6,D5,D4,D3,D2,D1};
+   
+   //sample clkdiv
+   always @ (negedge CLK)
+     clkdiv_sample[1:0] <= {clkdiv_sample[0],CLKDIV};
+
+   //shift on second consective clk rising edge that clkdi_sample==0
+
+   wire      load_parallel = (clkdiv_sample[1:0]==2'b00);
+
+   always @ (posedge CLK)
+     if(load_parallel)
+       even[3:0]<={buffer[6],buffer[4],buffer[2],buffer[0]};
+     else
+       even[3:0]<={1'b0,even[3:1]};
+
+   always @ (posedge CLK)
+     if(load_parallel)
+       odd[3:0]<={buffer[7],buffer[5],buffer[3],buffer[1]};
+     else
+       odd[3:0]<={1'b0,odd[3:1]};
+     
+   assign OQ = CLK ? even[0] : odd[0];
+   
+   //setting other outputs
+   assign OFB       = 1'b0;
+   assign TQ        = 1'b0;
+   assign TBYTEOUT  = 1'b0;
+   assign SHIFTOUT1 = 1'b0;   \t\t      
+   assign SHIFTOUT2 = 1'b0;   
+   assign TFB       = 1'b0;
+   
+endmodule // OSERDESE2
+
+"
+"/*
+ #######################################################
+ # Synchronizer circuit
+ #######################################################
+  */
+module synchronizer (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   in, clk, reset
+   );
+
+   parameter DW = 1;
+   
+   //Input Side   
+   input  [DW-1:0] in;   
+   input           clk;
+   input \t   reset;
+   
+   //Output Side
+   output [DW-1:0] out;
+
+   //Three stages
+   reg [DW-1:0] sync_reg0;
+   reg [DW-1:0] out;
+     
+   //We use two flip-flops for metastability improvement
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       begin
+\t  sync_reg0[DW-1:0] <= {(DW){1'b0}};
+\t  out[DW-1:0]       <= {(DW){1'b0}};
+\t end
+     else
+       begin
+\t  sync_reg0[DW-1:0] <= in[DW-1:0];
+\t  out[DW-1:0]       <= sync_reg0[DW-1:0];
+       end
+   
+
+endmodule // synchronizer
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"/*###########################################################################
+ *#An I/O clock buffer
+ *########################################################################### 
+ * 
+ * BUIOs can drive:
+ * -a single I/O clock network in the same region/bank
+ * 
+ * BUIOs can be driven by:
+ * -SRCCs and MRCCs in the same clock region
+ * -MRCCs in an adjacent clock region using BUFMRs
+ * -MMCMs clock outputs 0-3 driving the HPC in the same clock region
+ *
+ * 
+ * Input to Output Delay (Zynq7010/7020): 1.61/1.32/1.16 (-1/-2/-3 grade) 
+ * 
+ * 
+ */ 
+
+
+module BUFIO (/*AUTOARG*/
+   // Outputs
+   O,
+   // Inputs
+   I
+   );
+
+   output O;
+   input  I;
+    
+   assign O=I;
+     
+endmodule
+"
+"/*###########################################################################
+ # Function:  Clock and reset generator
+ #      
+ #  tx_lclk_div4 - Parallel data clock (125Mhz)
+ #
+ #  tx_lclk      - DDR data clock (500MHz)
+ #
+ #  tx_lclk90    - DDR ""Clock"" for IO (500MHz)
+ #
+ #  rx_lclk      - High speed RX clock for IO (300MHz phase shifted)
+ #
+ #  rx_lclk_div4 - Low speed RX clock for logic (75MHz)
+ ############################################################################
+ 
+ */
+
+`include ""elink_constants.v""
+
+module eclocks (/*AUTOARG*/
+   // Outputs
+   tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4, e_cclk_p,
+   e_cclk_n, elink_reset, e_resetb,
+   // Inputs
+   reset, elink_en, sys_clk, rx_clkin
+   );
+
+//TODO: change to parameter 
+`ifdef SIM
+   parameter RCW                 = 4;          // reset counter width
+`else
+   parameter RCW                 = 8;          // reset counter width
+`endif
+
+   //Frequency Settings (Mhz)
+   parameter FREQ_SYSCLK     = 100;
+   parameter FREQ_RXCLK      = 300;
+   parameter FREQ_TXCLK      = 300;
+   parameter FREQ_IDELAY     = 200;   
+   parameter FREQ_CCLK       = 600;  
+   parameter TXCLK_PHASE     = 90;  //txclk phase shift
+   parameter RXCLK_PHASE     = 0;   //rxclk phase shift
+   
+   //VCO multiplers
+   parameter MMCM_VCO_MULT   = 12;  //TX + CCLK
+   parameter PLL_VCO_MULT    = 4;   //RX
+      
+   //Input clock, reset, config interface
+   input      reset;             // async input reset
+   input      elink_en;          // elink enable (from pin or register)
+   
+   //Main input clocks
+   input      sys_clk;            // always on input clk cclk/TX MMCM
+   input      rx_clkin;           // input clk for RX only PLL
+   
+   //TX Clocks
+   output     tx_lclk;           // tx clock for DDR IO
+   output     tx_lclk90;         // tx output clock shifted by 90 degrees
+   output     tx_lclk_div4;      // tx slow clock for logic
+   
+   //RX Clocks
+   output     rx_lclk;           // rx high speed clock for DDR IO
+   output     rx_lclk_div4;      // rx slow clock for logic
+ 
+   //Epiphany ""free running"" clock
+   output     e_cclk_p, e_cclk_n;
+
+   //Reset
+   output     elink_reset;       // reset for elink logic & IO   
+   output     e_resetb;          // reset fpr Epiphany chip
+
+
+   //Don\'t touch these! (derived parameters)
+   localparam real    SYSCLK_PERIOD = 1000.000000/FREQ_SYSCLK;
+   localparam real    RXCLK_PERIOD  = 1000.000000/FREQ_RXCLK;
+   localparam integer TXCLK_DIVIDE  = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_TXCLK;
+   localparam integer CCLK_DIVIDE   = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_CCLK;
+   localparam integer IREF_DIVIDE   = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_IDELAY;
+   localparam integer RXCLK_DIVIDE  = PLL_VCO_MULT;
+   
+   //############
+   //# WIRES
+   //############
+
+   //CCLK
+   wire       cclk_reset;
+   wire       cclk_i;
+   wire       cclk_bufio;
+   wire       cclk_oddr;
+   
+   //Idelay controller
+   wire       idelay_reset;
+   wire       idelay_ready; //ignore this?
+   wire       idelay_ref_clk_i;
+   wire       idelay_ref_clk;
+   
+   //RX
+   wire       rx_lclk_i;
+   wire       rx_lclk_div4_i;
+   
+   //TX
+   wire       tx_lclk_i;
+   wire       tx_lclk90_i;
+   wire       tx_lckl_div4_i;
+
+   //MMCM & PLL
+   wire       cclk_fb_in;
+   wire       cclk_fb_out;
+   wire       lclk_fb_i;
+   wire       pll_reset;
+   wire       cclk_locked;
+   wire       lclk_fb_in;
+   wire       lclk_fb_out;
+   reg \t      cclk_locked_reg;
+   reg \t      cclk_locked_sync;
+   reg \t      rx_locked_reg;
+   reg \t      rx_locked_sync;
+   wire       lclk_locked;   
+   
+   //###########################
+   // RESET STATE MACHINE
+   //###########################
+  
+   reg [RCW:0] reset_counter = \'b0; //works b/c of free running counter!
+   reg \t       heartbeat;   
+   reg \t       reset_in;
+   reg \t       reset_sync;
+
+   reg [2:0]   reset_state;
+
+   
+   //wrap around counter that generates a 1 cycle heartbeat       
+   //free running counter...
+   always @ (posedge sys_clk)
+     begin
+\treset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1\'b1;
+\theartbeat              <= ~(|reset_counter[RCW-1:0]);
+     end
+   
+   //two clock synchronizer
+   always @ (posedge sys_clk)
+     begin
+\t//TODO: Does rx_lclk always run when cclk does? Restb ?
+        rx_locked_reg     <= lclk_locked;\t
+        rx_locked_sync    <=  rx_locked_reg;\t
+\tcclk_locked_reg    <= cclk_locked; // & clk_locked 
+\tcclk_locked_sync   <= cclk_locked_reg;\t
+\treset_sync        <= (reset | ~elink_en);
+\treset_in          <= reset_sync;
+     end
+   
+`define RESET_ALL        3\'b000
+`define START_CCLK       3\'b001
+`define STOP_CCLK        3\'b010
+`define START_EPIPHANY   3\'b011
+`define HOLD_IT          3\'b100
+`define TX_ACTIVE        3\'b101
+`define ACTIVE           3\'b110
+
+   //Reset sequence state machine
+   
+   always @ (posedge sys_clk)
+     if(reset_in)
+       reset_state[2:0]          <= `RESET_ALL;   
+     else if(heartbeat)
+       case(reset_state[2:0])
+\t `RESET_ALL :
+\t   reset_state[2:0]      <= `START_CCLK;\t 
+\t `START_CCLK :
+\t   if(cclk_locked_sync)
+\t     reset_state[2:0]  <= `STOP_CCLK; 
+\t `STOP_CCLK :
+\t   reset_state[2:0]    <= `START_EPIPHANY;
+\t `START_EPIPHANY :
+\t   reset_state[2:0]    <= `HOLD_IT;
+\t `HOLD_IT :
+\t   if(cclk_locked_sync)
+\t     reset_state[2:0]  <= `TX_ACTIVE;
+\t `TX_ACTIVE :
+\t   reset_state[2:0]    <= `ACTIVE;
+\t `ACTIVE:
+\t   reset_state[2:0]    <= `ACTIVE; //stay there until nex reset
+
+       endcase // case (reset_state[2:0])
+
+   
+   //reset PLL during \'reset\' and during quiet time around reset edge
+
+   //TODO: this is a bug if the RX gets a clock that is not a turnaround from TX
+   assign pll_reset   =  (reset_state[2:0] != `ACTIVE);
+    
+   assign idelay_reset =  (reset_state[2:0]==`RESET_ALL) |
+\t\t\t  (reset_state[2:0]==`START_CCLK);
+   
+   assign cclk_reset =  (reset_state[2:0]==`RESET_ALL) |
+\t\t\t(reset_state[2:0]==`STOP_CCLK) | 
+\t\t\t(reset_state[2:0]==`START_EPIPHANY);
+   
+   assign e_resetb    =  (reset_state[2:0]==`START_EPIPHANY) |
+\t\t         (reset_state[2:0]==`HOLD_IT) |
+\t\t         (reset_state[2:0]==`ACTIVE) |
+   \t\t         (reset_state[2:0]==`TX_ACTIVE);
+   
+
+   assign elink_reset  =  (reset_state[2:0] != `TX_ACTIVE) &
+\t\t\t  (reset_state[2:0] != `ACTIVE);
+   
+\t\t\t     
+`ifdef TARGET_XILINX\t
+
+   //###########################
+   // MMCM FOR TXCLK + CCLK
+   //###########################
+   MMCME2_ADV
+     #(
+       .BANDWIDTH(""OPTIMIZED""),          
+       .CLKFBOUT_MULT_F(MMCM_VCO_MULT),
+       .CLKFBOUT_PHASE(0.0),
+       .CLKIN1_PERIOD(SYSCLK_PERIOD),   
+       .CLKOUT0_DIVIDE_F(CCLK_DIVIDE),   //cclk_c
+       .CLKOUT1_DIVIDE(TXCLK_DIVIDE),    //tx_lclk
+       .CLKOUT2_DIVIDE(TXCLK_DIVIDE),    //tx_lclk90
+       .CLKOUT3_DIVIDE(TXCLK_DIVIDE*4),  //tx_lclk_div4
+       .CLKOUT4_DIVIDE(IREF_DIVIDE),     //idelay_refclk
+       .CLKOUT5_DIVIDE(128),             //
+       .CLKOUT6_DIVIDE(128),             //
+       .CLKOUT0_DUTY_CYCLE(0.5),         
+       .CLKOUT1_DUTY_CYCLE(0.5),
+       .CLKOUT2_DUTY_CYCLE(0.5),
+       .CLKOUT3_DUTY_CYCLE(0.5),
+       .CLKOUT4_DUTY_CYCLE(0.5),
+       .CLKOUT5_DUTY_CYCLE(0.5),
+       .CLKOUT6_DUTY_CYCLE(0.5),
+       .CLKOUT0_PHASE(0.0),
+       .CLKOUT1_PHASE(0.0),
+       .CLKOUT2_PHASE(TXCLK_PHASE),
+       .CLKOUT3_PHASE(0.0),
+       .CLKOUT4_PHASE(0.0),
+       .CLKOUT5_PHASE(0.0),
+       .CLKOUT6_PHASE(0.0),
+       .DIVCLK_DIVIDE(1.0), 
+       .REF_JITTER1(0.01), 
+       .STARTUP_WAIT(""FALSE"") 
+       ) mmcm_cclk
+       (
+        .CLKOUT0(cclk_i),
+\t.CLKOUT0B(),
+        .CLKOUT1(tx_lclk_i),
+\t.CLKOUT1B(),
+        .CLKOUT2(tx_lclk90_i),
+\t.CLKOUT2B(),
+        .CLKOUT3(tx_lclk_div4_i),
+\t.CLKOUT3B(),
+        .CLKOUT4(idelay_ref_clk_i),
+        .CLKOUT5(),
+\t.CLKOUT6(),
+\t.PWRDWN(1\'b0),
+        .RST(cclk_reset),     //reset
+        .CLKFBIN(cclk_fb_in),
+        .CLKFBOUT(cclk_fb_out),  //feedback clock     
+        .CLKIN1(sys_clk),    //input clock
+\t.CLKIN2(1\'b0),
+\t.CLKINSEL(1\'b1),      
+\t.DADDR(7\'b0),
+        .DCLK(1\'b0),
+\t.DEN(1\'b0),
+\t.DI(16\'b0),
+\t.DWE(1\'b0),
+\t.DRDY(),
+\t.DO(), 
+\t.LOCKED(cclk_locked), //locked indicator
+\t.PSCLK(1\'b0),
+\t.PSEN(1\'b0),
+\t.PSDONE(),
+\t.PSINCDEC(1\'b0),
+\t.CLKFBSTOPPED(),
+\t.CLKINSTOPPED()
+        );
+   
+
+   //Idelay ref clock buffer
+   BUFG idelay_ref_bufg_i(.I(idelay_ref_clk_i), .O(idelay_ref_clk));
+   
+   //Feedback buffer
+   BUFG cclk_fb_bufg_i(.I(cclk_fb_out), .O(cclk_fb_in));
+
+   //Tx clock buffers
+   BUFG tx_lclk_bufg_i      (.I(tx_lclk_i),      .O(tx_lclk));
+   BUFG tx_lclk_div4_bufg_i (.I(tx_lclk_div4_i), .O(tx_lclk_div4));
+   BUFG tx_lclk90_bufg_i    (.I(tx_lclk90_i),    .O(tx_lclk90));
+
+   //###########################
+   // PLL RX
+   //###########################  
+   
+   PLLE2_ADV
+     #(
+       .BANDWIDTH(""OPTIMIZED""),          
+       .CLKFBOUT_MULT(PLL_VCO_MULT),              
+       .CLKFBOUT_PHASE(0.0),
+       .CLKIN1_PERIOD(RXCLK_PERIOD),
+       .CLKOUT0_DIVIDE(128),
+       .CLKOUT1_DIVIDE(128),
+       .CLKOUT2_DIVIDE(128),
+       .CLKOUT3_DIVIDE(128),
+       .CLKOUT4_DIVIDE(RXCLK_DIVIDE),   // rx_lclk
+       .CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
+       .CLKOUT0_DUTY_CYCLE(0.5),         
+       .CLKOUT1_DUTY_CYCLE(0.5),
+       .CLKOUT2_DUTY_CYCLE(0.5),
+       .CLKOUT3_DUTY_CYCLE(0.5),
+       .CLKOUT4_DUTY_CYCLE(0.5),
+       .CLKOUT5_DUTY_CYCLE(0.5),
+       .CLKOUT0_PHASE(0.0),
+       .CLKOUT1_PHASE(0.0),
+       .CLKOUT2_PHASE(0.0),
+       .CLKOUT3_PHASE(0.0),
+       .CLKOUT4_PHASE(0.0),
+       .CLKOUT5_PHASE(0.0),
+       .DIVCLK_DIVIDE(1.0), 
+       .REF_JITTER1(0.01), 
+       .STARTUP_WAIT(""FALSE"") 
+       ) pll_rx
+       (
+        .CLKOUT0(),
+        .CLKOUT1(),
+        .CLKOUT2(),
+        .CLKOUT3(),
+        .CLKOUT4(rx_lclk_i),
+        .CLKOUT5(rx_lclk_div4_i),
+\t.PWRDWN(1\'b0),
+        .RST(pll_reset),
+        .CLKFBIN(lclk_fb_in),//lclk_fb_in
+        .CLKFBOUT(lclk_fb_out),       
+        .CLKIN1(rx_clkin),
+\t.CLKIN2(1\'b0),
+\t.CLKINSEL(1\'b1),      
+\t.DADDR(7\'b0),
+        .DCLK(1\'b0),
+\t.DEN(1\'b0),
+\t.DI(16\'b0),
+\t.DWE(1\'b0),
+\t.DRDY(),
+\t.DO(), 
+\t.LOCKED(lclk_locked)
+        );
+   
+   //Rx clock buffers
+   BUFG rx_lclk_bufg_i(.I(rx_lclk_i), .O(rx_lclk));                 //goes to erx_io
+   BUFG rx_lclk_div4_bufg_i(.I(rx_lclk_div4_i), .O(rx_lclk_div4));  //goes to erx_io
+
+    
+   //Feedback buffers
+   BUFG lclk_fb_bufg_i0(.I(rx_lclk), .O(lclk_fb_in)); //.I(lclk_fb_in),
+   
+ //###########################
+   // CCLK
+   //###########################
+
+   //CCLK differential buffer
+   OBUFDS  cclk_obuf (.O   (e_cclk_p),
+\t\t      .OB  (e_cclk_n),
+\t\t      .I   (cclk_oddr)
+\t\t      );
+
+   //CCLK oddr 
+   ODDR #(.DDR_CLK_EDGE  (""SAME_EDGE""),
+\t  .SRTYPE(""ASYNC""))
+   oddr_lclk (
+              .Q  (cclk_oddr),
+              .C  (cclk_bufio),
+              .CE (1\'b1),
+              .D1 (1\'b1),
+              .D2 (1\'b0),
+              .R  (1\'b0),
+              .S  (1\'b0));
+
+   //CCLK bufio
+   BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_i));
+   
+   //###########################
+   // Idelay controller
+   //###########################
+   
+   (* IODELAY_GROUP = ""IDELAY_GROUP"" *) // Group name for IDELAYCTRL
+   IDELAYCTRL idelayctrl_inst 
+     (
+      .RDY(idelay_ready), // check ready flag in reset sequence?
+      .REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
+      .RST(idelay_reset));
+   
+`endif //  `ifdef TARGET_XILINX
+
+
+endmodule // eclocks
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+  Contributed by Gunnar Hillerstrom 
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+"
+"/*
+ ###########################################################################
+ # Function: A mailbox FIFO with a FIFO empty/full flags that can be used as   
+ #           interrupts.
+ #
+ #           E_MAILBOXLO    = lower 32 bits of FIFO entry
+ #           E_MAILBOXHI    = upper 32 bits of FIFO entry
+ #
+ # Notes:    1.) System should take care of not overflowing the FIFO
+ #           2.) Reading the E_MAILBOXHI causes a fifo rd pointer update
+ #           3.) The ""embox_not_empty"" is a ""level"" interrupt signal.
+ #
+ # How to use: 1.) Connect ""embox_not_empty"" to interrupt input line
+ #             2.) Write an ISR to respond to interrupt line::
+ #                 -reads E_MAILBOXLO, then
+ #                 -reads E_MAILBOXHI, then
+ #                 -finishes ISR
+ #
+ ###########################################################################
+ */
+`include ""../../elink/hdl/elink_regmap.v"" // is there a better way?
+
+module emailbox (/*AUTOARG*/
+   // Outputs
+   mi_dout, mailbox_full, mailbox_not_empty,
+   // Inputs
+   reset, wr_clk, rd_clk, emesh_access, emesh_packet, mi_en, mi_we,
+   mi_addr, mi_din
+   );
+
+   parameter DW     = 32;        //data width of fifo
+   parameter AW     = 32;        //data width of fifo
+   parameter PW     = 104;       //packet size
+   parameter RFAW   = 6;         //address bus width
+   parameter ID     = 12\'h000;   //link id
+
+   parameter WIDTH  = 104;
+   parameter DEPTH  = 16;
+   
+   /*****************************/
+   /*RESET                      */
+   /*****************************/
+   input           reset;       //asynchronous reset
+   input \t   wr_clk;      //write clock
+   input \t   rd_clk;      //read clock
+
+
+   /*****************************/
+   /*WRITE INTERFACE            */
+   /*****************************/
+   input \t   emesh_access;
+   input [PW-1:0]  emesh_packet;
+   
+   /*****************************/
+   /*READ INTERFACE             */
+   /*****************************/   
+   input \t    mi_en;
+   input  \t    mi_we;      
+   input [RFAW+1:0] mi_addr;
+   input [63:0]     mi_din;  //assumes write interface is 64 bits
+   output [63:0]    mi_dout;   
+   
+   /*****************************/
+   /*MAILBOX OUTPUTS            */
+   /*****************************/
+   output \t   mailbox_full;
+   output \t   mailbox_not_empty;   
+   
+   /*****************************/
+   /*REGISTERS                  */
+   /*****************************/
+   reg [63:0]     mi_dout;
+
+   /*****************************/
+   /*WIRES                      */
+   /*****************************/
+   wire \t    mailbox_read;
+   wire \t    mi_rd;
+   wire [WIDTH-1:0] mailbox_fifo_data;
+   wire \t    mailbox_empty; 
+   wire \t    mailbox_pop;
+   wire [31:0] \t    emesh_addr;
+   wire [63:0] \t    emesh_din;
+   wire \t    emesh__write;
+   
+   /*****************************/
+   /*WRITE TO FIFO              */
+   /*****************************/  
+
+   assign emesh_addr[31:0]  = emesh_packet[39:8];
+
+   assign emesh_din[63:0]   = emesh_packet[103:40];
+  
+   assign emesh_write       = emesh_access &
+\t\t\t      emesh_packet[1] &
+\t\t\t      (emesh_addr[31:20]==ID) & 
+\t\t\t      (emesh_addr[10:8]==3\'h3) & 
+                              (emesh_addr[RFAW+1:2]==`E_MAILBOXLO); 
+   
+   /*****************************/
+   /*READ BACK DATA             */
+   /*****************************/  
+
+   assign mi_rd =  mi_en & ~mi_we;
+   
+   assign mailbox_pop  = mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXHI); //fifo read
+
+   always @ (posedge rd_clk)
+     if(mi_rd)
+       case(mi_addr[RFAW+1:2])\t 
+\t `E_MAILBOXLO:   mi_dout[63:0] <= mailbox_fifo_data[63:0];\t 
+\t `E_MAILBOXHI:   mi_dout[63:0] <= {mailbox_fifo_data[2*DW-1:DW],
+\t\t\t\t\t   mailbox_fifo_data[2*DW-1:DW]};\t 
+\t default:        mi_dout[63:0] <= 64\'d0;
+       endcase // case (mi_addr[RFAW-1:2])
+     else
+       mi_dout[63:0] <= 64\'d0;
+
+   /*****************************/
+   /*FIFO (64bit wide)          */
+   /*****************************/
+
+   assign mailbox_not_empty         = ~mailbox_empty;
+
+   //BUG! This fifo is currently hard coded to 16 entries
+   //Should be parametrized to up to 4096 entries
+
+   defparam fifo.DW    = WIDTH;
+   defparam fifo.DEPTH = DEPTH;
+   
+   fifo_async fifo(// Outputs
+\t\t   .dout      (mailbox_fifo_data[WIDTH-1:0]),
+\t\t   .empty     (mailbox_empty),
+\t\t   .full      (mailbox_full),
+     \t\t   .prog_full (),
+\t\t   .valid(),
+\t\t   //Read Port
+\t\t   .rd_en    (mailbox_pop), 
+\t\t   .rd_clk   (rd_clk),  
+\t\t   //Write Port 
+\t\t   .din      ({40\'b0,emesh_din[63:0]}),
+\t\t   .wr_en    (emesh_write),
+\t\t   .wr_clk   (wr_clk),  \t\t\t     
+\t\t   .wr_rst   (reset),
+  \t\t   .rd_rst   (reset)      
+\t\t   ); 
+   
+endmodule // emailbox
+
+/*
+  Copyright (C) 2014 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+"
+"module PLLE2_ADV #(
+ 
+  parameter BANDWIDTH = ""OPTIMIZED"",
+  parameter integer CLKFBOUT_MULT = 5,
+  parameter real CLKFBOUT_PHASE = 0.000,
+  parameter real CLKIN1_PERIOD = 0.000,
+  parameter real CLKIN2_PERIOD = 0.000,
+  parameter integer CLKOUT0_DIVIDE = 1,
+  parameter real CLKOUT0_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT0_PHASE = 0.000,
+  parameter integer CLKOUT1_DIVIDE = 1,
+  parameter real CLKOUT1_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT1_PHASE = 0.000,
+  parameter integer CLKOUT2_DIVIDE = 1,
+  parameter real CLKOUT2_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT2_PHASE = 0.000,
+  parameter integer CLKOUT3_DIVIDE = 1,
+  parameter real CLKOUT3_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT3_PHASE = 0.000,
+  parameter integer CLKOUT4_DIVIDE = 1,
+  parameter real CLKOUT4_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT4_PHASE = 0.000,
+  parameter integer CLKOUT5_DIVIDE = 1,
+  parameter real CLKOUT5_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT5_PHASE = 0.000,
+  parameter COMPENSATION = ""ZHOLD"",
+  parameter integer DIVCLK_DIVIDE = 1,
+  parameter [0:0] IS_CLKINSEL_INVERTED = 1\'b0,
+  parameter [0:0] IS_PWRDWN_INVERTED = 1\'b0,
+  parameter [0:0] IS_RST_INVERTED = 1\'b0,
+  parameter real REF_JITTER1 = 0.010,
+  parameter real REF_JITTER2 = 0.010,
+  parameter STARTUP_WAIT = ""FALSE""
+)(
+  
+  output \tCLKOUT0,
+  output \tCLKOUT1,
+  output \tCLKOUT2,
+  output \tCLKOUT3,
+  output \tCLKOUT4,
+  output \tCLKOUT5,
+  output [15:0] DO,
+  output \tDRDY,
+  output \tLOCKED,
+  output \tCLKFBOUT,
+  input \tCLKFBIN,
+  input \tCLKIN1,
+  input \tCLKIN2,
+  input \tCLKINSEL,
+  input [6:0] \tDADDR,
+  input \tDCLK,
+  input \tDEN,
+  input [15:0] \tDI,
+  input \tDWE,
+  input \tPWRDWN,
+  input \tRST
+);
+
+  //#LOCAL DERIVED PARAMETERS
+   localparam real VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT;
+   localparam real CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE * (CLKOUT0_PHASE/360);
+   localparam real CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
+   localparam real CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
+   localparam real CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
+   localparam real CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
+   localparam real CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
+
+   localparam phases = CLKFBOUT_MULT / DIVCLK_DIVIDE;
+   
+   //########################################################################
+   //# POR
+   //########################################################################
+   //ugly POR reset
+   reg \t      POR;
+   initial
+     begin
+\tPOR=1\'b1;
+\t#1
+\tPOR=1\'b0;\t
+     end
+
+   reg reset;
+   always @ (posedge CLKIN1)
+     reset <= POR | RST;
+   
+   //########################################################################
+   //# CLOCK MULTIPLIER
+   //########################################################################
+
+   //TODO: implement  DIVCLK_DIVIDE
+   //   
+   integer \tj;   
+   reg [2*phases-1:0] \tdelay;
+   always @ (CLKIN1)
+     begin\t
+\tfor(j=0; j<(2*phases); j=j+1)
+\t  delay[j] <= #(CLKIN1_PERIOD*j/(2*phases)) CLKIN1;
+     end
+   
+   reg [(phases)-1:0] \tclk_comb;
+    always @ (delay)
+      begin
+\t for(j=0; j<(phases); j=j+1)
+\t   clk_comb[j] <= ~reset & delay[2*j] & ~delay[2*j+1];\t 
+      end
+   
+   reg vco_clk;   
+   integer k;   
+   always @*
+     begin
+\tvco_clk = 1\'b0;
+\tfor(k=0; k<(phases); k=k+1)
+\t  vco_clk = vco_clk | clk_comb[k];
+     end
+   
+   //##############
+   //#DIVIDERS
+   //##############
+   wire [3:0] \t DIVCFG[5:0]; 
+   wire [5:0] \t CLKOUT_DIV;
+      
+   assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE);
+   assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
+   assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
+   assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
+   assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
+   assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
+ 
+   genvar i;
+   generate for(i=0; i<6; i=i+1)
+     begin : gen_clkdiv
+\tclock_divider clkdiv (/*AUTOINST*/
+\t\t\t      // Outputs
+\t\t\t      .clkout\t\t(CLKOUT_DIV[i]),
+\t\t\t      // Inputs
+\t\t\t      .clkin\t\t(vco_clk),
+\t\t\t      .divcfg\t\t(DIVCFG[i]),
+\t\t\t      .reset\t\t(reset));\t\t
+     end      
+   endgenerate
+
+   reg [5:0] CLKOUT_DIV_LOCK;   
+   always @ (posedge (CLKIN1&vco_clk) or negedge (CLKIN1&~vco_clk))
+     begin
+\tCLKOUT_DIV_LOCK[5:0] <= CLKOUT_DIV[5:0];\t
+     end
+
+   
+   //##############
+   //#SUB PHASE DELAY
+   //##############
+   reg CLKOUT0;
+   reg CLKOUT1;
+   reg CLKOUT2;
+   reg CLKOUT3;
+   reg CLKOUT4;
+   reg CLKOUT5;
+   
+   always @ (CLKOUT_DIV_LOCK)
+     begin\t
+\tCLKOUT0 <= #(CLK0_DELAY) ~reset & CLKOUT_DIV_LOCK[0];
+\tCLKOUT1 <= #(CLK1_DELAY) ~reset & CLKOUT_DIV_LOCK[1];
+\tCLKOUT2 <= #(CLK2_DELAY) ~reset & CLKOUT_DIV_LOCK[2];
+\tCLKOUT3 <= #(CLK3_DELAY) ~reset & CLKOUT_DIV_LOCK[3];
+\tCLKOUT4 <= #(CLK4_DELAY) ~reset & CLKOUT_DIV_LOCK[4];
+\tCLKOUT5 <= #(CLK5_DELAY) ~reset & CLKOUT_DIV_LOCK[5];
+     end
+
+   //##############
+   //#DUMMY DRIVES
+   //##############
+   assign CLKFBOUT=CLKIN1;
+
+   //###########################
+   //#SANITY CHECK LOCK COUNTER
+   //############################
+   localparam LCW=4;   
+   reg [LCW-1:0] lock_counter;
+ 
+   
+   always @ (posedge CLKIN1 or posedge reset)
+     if(reset)
+       lock_counter[LCW-1:0]  <= {(LCW){1\'b1}};
+     else if(~LOCKED)
+       lock_counter[LCW-1:0] <= lock_counter[LCW-1:0] - 1\'b1;
+
+   assign LOCKED = ~(|lock_counter[LCW-1:0]);
+      
+endmodule // PLLE2_ADV
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+"
+"/* Model for xilinx async fifo*/
+module fifo_async_104x32 
+   (/*AUTOARG*/
+   // Outputs
+   full, prog_full, almost_full, dout, empty, valid,
+   // Inputs
+   wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
+   );
+   
+   parameter DW     = 104;//104 wide
+   parameter DEPTH  = 16; //
+   
+   //##########
+   //# RESET/CLOCK
+   //##########
+   input           wr_rst;     //asynchronous reset
+   input           rd_rst;     //asynchronous reset
+   input           wr_clk;    //write clock   
+   input           rd_clk;    //read clock   
+
+   //##########
+   //# FIFO WRITE
+   //##########
+   input           wr_en;   
+   input  [DW-1:0] din;
+   output          full;
+   output \t   prog_full;
+   output \t   almost_full;
+   
+   //###########
+   //# FIFO READ
+   //###########
+   input \t   rd_en;
+   output [DW-1:0] dout;
+   output          empty;
+   output          valid;
+
+   defparam fifo_model.DW=104;   
+   defparam fifo_model.DEPTH=32;   
+
+   fifo_async_model fifo_model (/*AUTOINST*/
+\t\t\t\t// Outputs
+\t\t\t\t.full\t\t(full),
+\t\t\t\t.prog_full\t(prog_full),
+\t\t\t\t.almost_full\t(almost_full),
+\t\t\t\t.dout\t\t(dout[DW-1:0]),
+\t\t\t\t.empty\t\t(empty),
+\t\t\t\t.valid\t\t(valid),
+\t\t\t\t// Inputs
+\t\t\t\t.wr_rst\t\t(wr_rst),
+\t\t\t\t.rd_rst\t\t(rd_rst),
+\t\t\t\t.wr_clk\t\t(wr_clk),
+\t\t\t\t.rd_clk\t\t(rd_clk),
+\t\t\t\t.wr_en\t\t(wr_en),
+\t\t\t\t.din\t\t(din[DW-1:0]),
+\t\t\t\t.rd_en\t\t(rd_en));
+      
+      
+endmodule // fifo_async
+// Local Variables:
+// verilog-library-directories:(""."" ""../../memory/hdl"")
+// End:
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"/*
+ This block receives the IO transaction and converts to a 104 bit packet. 
+ */
+
+`include ""elink_constants.v""
+module erx_io (/*AUTOARG*/
+   // Outputs
+   rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
+   rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
+   // Inputs
+   reset, rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
+   rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait
+   );
+   parameter IOSTD_ELINK = ""LVDS_25"";  
+   parameter PW          = 104;
+   parameter ETYPE       = 1;//0=parallella
+                             //1=ephycard     
+   
+   // Can we do this in a better way?
+   //parameter [3:0] RX_TAP_DELAY [8:0]=;
+   //parameter  RX_TAP_DELAY = 1;
+
+   parameter [5*10:0] RX_TAP_DELAY ={5\'d0,  //clk
+\t\t\t\t     5\'d12, //frame
+\t\t\t\t     5\'d12, //d7
+\t\t\t\t     5\'d12, //d6
+\t\t\t\t     5\'d12, //d5
+\t\t\t\t     5\'d12, //d4
+\t\t\t\t     5\'d12, //d3
+\t\t\t\t     5\'d12, //d2
+\t\t\t\t     5\'d12, //d1
+\t\t\t\t     5\'d12  //d0
+\t\t\t\t   };
+   
+   
+   //#########################
+   //# reset, clocks
+   //#########################
+   input       reset;                       // reset
+   input       rx_lclk;                     // fast I/O clock
+   input       rx_lclk_div4;                // slow clock
+   output      rx_lclk_pll;                 // clock output for pll
+   
+   //##########################
+   //# elink pins
+   //##########################
+   input       rxi_lclk_p,   rxi_lclk_n;    // rx clock input
+   input       rxi_frame_p,  rxi_frame_n;   // rx frame signal
+   input [7:0] rxi_data_p,   rxi_data_n;    // rx data
+   output      rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
+   output      rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
+  
+   //##########################
+   //# erx logic interface
+   //##########################
+   output \t   rx_access;
+   output \t   rx_burst;
+   output [PW-1:0] rx_packet;
+   input           rx_wr_wait;
+   input           rx_rd_wait;
+
+   //############
+   //# WIRES
+   //############
+   wire [7:0]    rxi_data;
+   wire          rxi_frame;
+   wire \t rxi_lclk;
+   wire \t access_wide;
+   reg \t\t valid_packet;
+   reg [15:0]   rx_word;
+   wire [15:0] \t rx_word_i;
+   
+   //############
+   //# REGS
+   //############
+   reg [7:0] \t data_even_reg;   
+   reg [7:0] \t data_odd_reg;
+   reg  \t rx_frame;
+   wire \t rx_frame_i;
+   reg [111:0] \t rx_sample; 
+   reg [6:0] \t rx_pointer;
+   reg \t\t access;  
+   reg \t\t burst;
+   reg [PW-1:0]  rx_packet_lclk;
+   reg \t\t rx_access;
+   reg [PW-1:0]  rx_packet;
+   reg \t\t rx_burst;
+   wire \t rx_lclk_iddr;
+   wire [9:0] \t rxi_delay_in;
+   wire [9:0] \t rxi_delay_out;
+
+   
+   
+
+    //#####################
+   //#CREATE 112 BIT PACKET 
+   //#####################
+   
+   //write Pointer   
+   always @ (posedge rx_lclk)
+     if (~rx_frame)
+       rx_pointer[6:0] <= 7\'b0000001; //new frame
+     else if (rx_pointer[6])
+       rx_pointer[6:0] <= 7\'b0001000; //anticipate burst
+     else if(rx_frame)
+       rx_pointer[6:0] <= {rx_pointer[5:0],1\'b0};//middle of frame
+      
+   //convert to 112 bit packet
+   always @ (posedge rx_lclk)
+     if(rx_frame)   
+       begin
+\t  if(rx_pointer[0])
+\t    rx_sample[15:0]    <= rx_word[15:0];
+\t  if(rx_pointer[1])
+\t    rx_sample[31:16]   <= rx_word[15:0];
+\t  if(rx_pointer[2])
+\t    rx_sample[47:32]   <= rx_word[15:0];
+\t  if(rx_pointer[3])
+\t    rx_sample[63:48]   <= rx_word[15:0];
+\t  if(rx_pointer[4])
+\t    rx_sample[79:64]   <= rx_word[15:0];
+\t  if(rx_pointer[5])
+\t    rx_sample[95:80]   <= rx_word[15:0];
+\t  if(rx_pointer[6])
+\t    rx_sample[111:96]  <= rx_word[15:0];\t  
+       end // if (rx_frame)
+   
+   //#####################  
+   //#DATA VALID SIGNAL 
+   //####################
+
+
+   always @ (posedge rx_lclk)
+     begin     
+\taccess       <= rx_pointer[6];
+\tvalid_packet <= access;//data pipeline
+     end
+
+   reg burst_detect;   
+   always @ (posedge rx_lclk)
+     if(access & rx_frame)
+       burst_detect <= 1\'b1;
+     else if(~rx_frame)
+       burst_detect <= 1\'b0;
+      
+   //###################################
+   //#SAMPLE AND HOLD DATA
+   //###################################
+
+   //(..and shuffle data for 104 bit packet)
+   always @ (posedge rx_lclk)
+     if(access)   
+       begin
+\t  //pipelin burst (delay by one frame)
+\t  burst                 <= burst_detect;\t  
+
+\t  //access
+\t  rx_packet_lclk[0]     <= rx_sample[40];
+
+\t  //write
+\t  rx_packet_lclk[1]     <= rx_sample[41];
+
+\t  //datamode
+\t  rx_packet_lclk[3:2]   <= rx_sample[43:42];
+
+\t  //ctrlmode
+\t  rx_packet_lclk[7:4]   <= rx_sample[15:12];
+
+\t  //dstaddr
+\t  rx_packet_lclk[39:8]  <= {rx_sample[11:8],
+\t\t\t             rx_sample[23:16],
+\t\t\t             rx_sample[31:24],
+\t\t\t             rx_sample[39:32],
+\t\t\t             rx_sample[47:44]};
+\t  //data
+\t  rx_packet_lclk[71:40] <= {rx_sample[55:48],
+\t\t\t              rx_sample[63:56],
+\t\t\t              rx_sample[71:64],
+\t\t\t              rx_sample[79:72]};\t
+\t  //srcaddr
+\t  rx_packet_lclk[103:72]<= {rx_sample[87:80],
+\t\t\t              rx_sample[95:88],
+\t\t\t              rx_sample[103:96],
+\t\t\t              rx_sample[111:104]
+\t\t\t\t      };\t
+     end
+   
+   //###################################
+   //#SYNCHRONIZE TO SLOW CLK
+   //###################################
+ 
+   //stretch access pulse to 4 cycles
+   pulse_stretcher #(.DW(3)) 
+   ps0 (
+\t.out(access_wide),
+\t.in(valid_packet),
+\t.clk(rx_lclk),
+\t.reset(reset));
+
+   
+   always @ (posedge rx_lclk_div4)
+     rx_access <= access_wide;
+   
+   always @ (posedge rx_lclk_div4)
+     if(access_wide)
+       begin
+\t  rx_packet[PW-1:0] <= rx_packet_lclk[PW-1:0];
+\t  rx_burst          <= burst;\t  
+       end
+
+
+   //################################
+   //# I/O Buffers Instantiation
+   //################################
+
+   IBUFDS  #(.DIFF_TERM  (""TRUE""),.IOSTANDARD (IOSTD_ELINK))
+   ibuf_data[7:0] 
+     (.I     (rxi_data_p[7:0]),
+      .IB    (rxi_data_n[7:0]),
+      .O     (rxi_data[7:0]));
+   
+   IBUFDS #(.DIFF_TERM  (""TRUE""), .IOSTANDARD (IOSTD_ELINK))
+   ibuf_frame
+     (.I     (rxi_frame_p),
+      .IB    (rxi_frame_n),
+      .O     (rxi_frame));
+
+
+   IBUFGDS #(.DIFF_TERM  (""TRUE""),.IOSTANDARD (IOSTD_ELINK))
+   ibuf_lclk (.I     (rxi_lclk_p),
+\t      .IB    (rxi_lclk_n),
+\t      .O     (rxi_lclk)
+\t      );
+ 
+   generate
+      if(ETYPE==1)
+\tbegin\t   
+\t   OBUFT #(.IOSTANDARD(""LVCMOS18""), .SLEW(""SLOW""))
+\t   obuft_wrwait (
+\t\t\t .O(rxo_wr_wait_p),
+\t\t\t .T(rx_wr_wait),
+\t\t\t .I(1\'b0)
+\t\t\t );
+\t   
+\t   OBUFT #(.IOSTANDARD(""LVCMOS18""), .SLEW(""SLOW""))
+\t   obuft_rdwait (
+\t\t\t .O(rxo_rd_wait_p),
+\t\t\t .T(rx_rd_wait),
+\t\t\t .I(1\'b0)
+\t\t\t );\t   \t   
+
+\t   assign rxo_wr_wait_n = 1\'b0;
+\t   assign rxo_rd_wait_n = 1\'b0;\t   
+\tend      
+      else if(ETYPE==0)
+\tbegin
+\t   OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW(""SLOW"")) 
+\t   obufds_wrwait (
+\t\t\t  .O(rxo_wr_wait_p),
+\t\t\t  .OB(rxo_wr_wait_n),
+\t\t\t  .I(rx_wr_wait)
+\t\t\t  );
+\t   
+\t   OBUFDS  #(.IOSTANDARD(IOSTD_ELINK),.SLEW(""SLOW"")) 
+\t   obufds_rdwait  (.O(rxo_rd_wait_p),
+\t\t\t   .OB(rxo_rd_wait_n),
+\t\t\t   .I(rx_rd_wait)
+\t\t\t   );
+\tend
+   endgenerate
+   
+   //###################################
+   //#RX CLOCK
+   //###################################   
+   BUFG rxi_lclk_bufg_i(.I(rxi_lclk), .O(rx_lclk_pll));  //for mmcm
+   
+   BUFIO rx_lclk_bufio_i(.I(rxi_delay_out[9]), .O(rx_lclk_iddr));//for iddr (NOT USED!)
+
+   //###################################
+   //#IDELAY CIRCUIT
+   //###################################
+
+   assign  rxi_delay_in[9:0] ={rxi_lclk,rxi_frame,rxi_data[7:0]};
+   
+   genvar        j;
+   generate for(j=0; j<10; j=j+1)
+     begin : gen_idelay
+\t(* IODELAY_GROUP = ""IDELAY_GROUP"" *) // Group name for IDELAYCTRL
+\t
+\tIDELAYE2 #(.CINVCTRL_SEL(""FALSE""),
+\t\t   .DELAY_SRC(""IDATAIN""), 
+\t\t   .HIGH_PERFORMANCE_MODE(""FALSE""),
+\t\t   .IDELAY_TYPE(""FIXED""),
+\t\t   .IDELAY_VALUE(RX_TAP_DELAY[(j+1)*5-1:j*5]),
+\t\t   .PIPE_SEL(""FALSE""),
+\t\t   .REFCLK_FREQUENCY(200.0),
+\t\t   .SIGNAL_PATTERN(""DATA""))
+\tidelay_inst (.CNTVALUEOUT(),                   
+\t\t     .DATAOUT(rxi_delay_out[j]),
+\t\t     .C(1\'b0),
+\t\t     .CE(1\'b0),
+\t\t     .CINVCTRL(1\'b0),
+\t\t     .CNTVALUEIN(5\'b0),
+\t\t     .DATAIN(1\'b0),
+\t\t     .IDATAIN(rxi_delay_in[j]),
+\t\t     .INC(1\'b0),
+\t\t     .LD(1\'b0),
+\t\t     .LDPIPEEN(1\'b0),
+\t\t     .REGRST(1\'b0)
+\t\t     );
+     end // block: gen_idelay
+   endgenerate
+
+   
+   //#############################
+   //# IDDR SAMPLERS
+   //#############################  
+ 
+   //DATA
+   genvar        i;
+   generate for(i=0; i<8; i=i+1)
+     begin : gen_iddr           
+\tIDDR #(.DDR_CLK_EDGE  (""SAME_EDGE_PIPELINED""), .SRTYPE(""SYNC""))
+\tiddr_data (
+\t\t   .Q1 (rx_word_i[i]),
+\t\t   .Q2 (rx_word_i[i+8]),
+\t\t   .C  (rx_lclk),//rx_lclk_iddr
+\t\t   .CE (1\'b1),
+\t\t   .D  (rxi_delay_out[i]),
+\t\t   .R  (reset),
+\t\t   .S  (1\'b0)
+\t\t   );
+     end
+     endgenerate
+
+   //FRAME
+   IDDR #(.DDR_CLK_EDGE  (""SAME_EDGE_PIPELINED""), .SRTYPE(""SYNC""))
+\tiddr_frame (
+\t\t   .Q1 (rx_frame_i),
+\t\t   .Q2 (),    
+\t\t   .C  (rx_lclk),//rx_lclk_iddr
+\t\t   .CE (1\'b1),
+\t\t   .D  (rxi_delay_out[8]),
+\t\t   .R  (reset),
+\t\t   .S  (1\'b0)
+\t\t   );
+
+   always @ ( posedge rx_lclk )
+     rx_frame <= rx_frame_i;
+
+   always @ ( posedge rx_lclk )
+     rx_word <= rx_word_i;
+   
+   
+endmodule // erx_io
+// Local Variables:
+// verilog-library-directories:(""."" ""../../emesh/hdl"" ""../../common/hdl"")
+// End:
+
+/*
+ Copyright (C) 2014 Adapteva, Inc.
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+ Contributed by Gunnar Hillerstrom
+ 
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+ 
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+ 
+ You should have received a copy of the GNU General Public License
+ along with this program (see the file COPYING).  If not, see
+ <http://www.gnu.org/licenses/>.
+*/
+"
+"`define CFG_FAKECLK   1      /*stupid verilator doesn\'t get clock gating*/
+`define CFG_MDW       32     /*Width of mesh network*/
+`define CFG_DW        32     /*Width of datapath*/
+`define CFG_AW        32     /*Width of address space*/
+`define CFG_LW        8      /*Link port width*/
+
+module dv_elink(/*AUTOARG*/
+   // Outputs
+   dut_passed, dut_failed, dut_rd_wait, dut_wr_wait, dut_access,
+   dut_packet,
+   // Inputs
+   clk, reset, ext_access, ext_packet, ext_rd_wait, ext_wr_wait
+   );
+
+   parameter AW    = 32;
+   parameter DW    = 32;
+   parameter CW    = 2;             //number of clocks to send int
+   parameter IDW   = 12;
+   parameter M_IDW = 6;
+   parameter S_IDW = 12;
+   parameter PW    = 104;
+   
+   
+   //Basic
+   input           clk;        // system clock
+   input           reset;      // Reset
+   output          dut_passed; // Indicates passing test
+   output          dut_failed; // Indicates failing test
+
+   //Input Transaction
+   input           ext_access;
+   input [PW-1:0]  ext_packet; 
+   output          dut_rd_wait;
+   output          dut_wr_wait;
+
+   //Output Transaction
+   output          dut_access;
+   output [PW-1:0] dut_packet; 
+   input \t   ext_rd_wait;
+   input \t   ext_wr_wait;
+
+   /*AUTOINPUT*/
+  
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [11:0]\t\te_chipid;\t\t// From elink2 of axi_elink.v
+   wire [11:0]\t\telink0_e_chipid;\t// From elink0 of elink.v
+   wire\t\t\telink0_e_resetb;\t// From elink0_eclocks of eclocks.v
+   wire\t\t\telink0_elink_en;\t// From elink0 of elink.v
+   wire\t\t\telink0_mailbox_full;\t// From elink0 of elink.v
+   wire\t\t\telink0_mailbox_not_empty;// From elink0 of elink.v
+   wire\t\t\telink0_reset;\t\t// From elink0_eclocks of eclocks.v
+   wire\t\t\telink0_rx_lclk;\t\t// From elink0_eclocks of eclocks.v
+   wire\t\t\telink0_rx_lclk_div4;\t// From elink0_eclocks of eclocks.v
+   wire\t\t\telink0_rx_lclk_pll;\t// From elink0 of elink.v
+   wire\t\t\telink0_rxo_rd_wait_n;\t// From elink0 of elink.v
+   wire\t\t\telink0_rxo_rd_wait_p;\t// From elink0 of elink.v
+   wire\t\t\telink0_rxo_wr_wait_n;\t// From elink0 of elink.v
+   wire\t\t\telink0_rxo_wr_wait_p;\t// From elink0 of elink.v
+   wire\t\t\telink0_rxrd_access;\t// From elink0 of elink.v
+   wire [PW-1:0]\telink0_rxrd_packet;\t// From elink0 of elink.v
+   wire\t\t\telink0_rxrr_access;\t// From elink0 of elink.v
+   wire [PW-1:0]\telink0_rxrr_packet;\t// From elink0 of elink.v
+   wire\t\t\telink0_rxwr_access;\t// From elink0 of elink.v
+   wire [PW-1:0]\telink0_rxwr_packet;\t// From elink0 of elink.v
+   wire\t\t\telink0_timeout;\t\t// From elink0 of elink.v
+   wire\t\t\telink0_tx_lclk;\t\t// From elink0_eclocks of eclocks.v
+   wire\t\t\telink0_tx_lclk90;\t// From elink0_eclocks of eclocks.v
+   wire\t\t\telink0_tx_lclk_div4;\t// From elink0_eclocks of eclocks.v
+   wire [7:0]\t\telink0_txo_data_n;\t// From elink0 of elink.v
+   wire [7:0]\t\telink0_txo_data_p;\t// From elink0 of elink.v
+   wire\t\t\telink0_txo_frame_n;\t// From elink0 of elink.v
+   wire\t\t\telink0_txo_frame_p;\t// From elink0 of elink.v
+   wire\t\t\telink0_txo_lclk_n;\t// From elink0 of elink.v
+   wire\t\t\telink0_txo_lclk_p;\t// From elink0 of elink.v
+   wire\t\t\telink0_txrd_wait;\t// From elink0 of elink.v
+   wire\t\t\telink0_txrr_wait;\t// From elink0 of elink.v
+   wire\t\t\telink0_txwr_wait;\t// From elink0 of elink.v
+   wire [11:0]\t\telink1_e_chipid;\t// From elink1 of elink.v
+   wire\t\t\telink1_e_resetb;\t// From elink1_eclocks of eclocks.v
+   wire\t\t\telink1_elink_en;\t// From elink1 of elink.v
+   wire\t\t\telink1_mailbox_full;\t// From elink1 of elink.v
+   wire\t\t\telink1_mailbox_not_empty;// From elink1 of elink.v
+   wire\t\t\telink1_reset;\t\t// From elink1_eclocks of eclocks.v
+   wire\t\t\telink1_rx_lclk;\t\t// From elink1_eclocks of eclocks.v
+   wire\t\t\telink1_rx_lclk_div4;\t// From elink1_eclocks of eclocks.v
+   wire\t\t\telink1_rx_lclk_pll;\t// From elink1 of elink.v
+   wire\t\t\telink1_rxo_rd_wait_n;\t// From elink1 of elink.v
+   wire\t\t\telink1_rxo_rd_wait_p;\t// From elink1 of elink.v
+   wire\t\t\telink1_rxo_wr_wait_n;\t// From elink1 of elink.v
+   wire\t\t\telink1_rxo_wr_wait_p;\t// From elink1 of elink.v
+   wire\t\t\telink1_rxrd_access;\t// From elink1 of elink.v
+   wire [PW-1:0]\telink1_rxrd_packet;\t// From elink1 of elink.v
+   wire\t\t\telink1_rxrr_access;\t// From elink1 of elink.v
+   wire [PW-1:0]\telink1_rxrr_packet;\t// From elink1 of elink.v
+   wire\t\t\telink1_rxwr_access;\t// From elink1 of elink.v
+   wire [PW-1:0]\telink1_rxwr_packet;\t// From elink1 of elink.v
+   wire\t\t\telink1_timeout;\t\t// From elink1 of elink.v
+   wire\t\t\telink1_tx_lclk;\t\t// From elink1_eclocks of eclocks.v
+   wire\t\t\telink1_tx_lclk90;\t// From elink1_eclocks of eclocks.v
+   wire\t\t\telink1_tx_lclk_div4;\t// From elink1_eclocks of eclocks.v
+   wire [7:0]\t\telink1_txo_data_n;\t// From elink1 of elink.v
+   wire [7:0]\t\telink1_txo_data_p;\t// From elink1 of elink.v
+   wire\t\t\telink1_txo_frame_n;\t// From elink1 of elink.v
+   wire\t\t\telink1_txo_frame_p;\t// From elink1 of elink.v
+   wire\t\t\telink1_txo_lclk_n;\t// From elink1 of elink.v
+   wire\t\t\telink1_txo_lclk_p;\t// From elink1 of elink.v
+   wire\t\t\telink1_txrd_wait;\t// From elink1 of elink.v
+   wire\t\t\telink1_txrr_access;\t// From emem of ememory.v
+   wire [PW-1:0]\telink1_txrr_packet;\t// From emem of ememory.v
+   wire\t\t\telink1_txrr_wait;\t// From elink1 of elink.v
+   wire\t\t\telink1_txwr_wait;\t// From elink1 of elink.v
+   wire [31:0]\t\tm_axi_araddr;\t\t// From tx_emaxi of emaxi.v
+   wire [1:0]\t\tm_axi_arburst;\t\t// From tx_emaxi of emaxi.v
+   wire [3:0]\t\tm_axi_arcache;\t\t// From tx_emaxi of emaxi.v
+   wire [IDW-1:0]\tm_axi_arid;\t\t// From tx_emaxi of emaxi.v
+   wire [7:0]\t\tm_axi_arlen;\t\t// From tx_emaxi of emaxi.v
+   wire [1:0]\t\tm_axi_arlock;\t\t// From tx_emaxi of emaxi.v
+   wire [2:0]\t\tm_axi_arprot;\t\t// From tx_emaxi of emaxi.v
+   wire [3:0]\t\tm_axi_arqos;\t\t// From tx_emaxi of emaxi.v
+   wire\t\t\tm_axi_arready;\t\t// From elink2 of axi_elink.v
+   wire [2:0]\t\tm_axi_arsize;\t\t// From tx_emaxi of emaxi.v
+   wire\t\t\tm_axi_arvalid;\t\t// From tx_emaxi of emaxi.v
+   wire [31:0]\t\tm_axi_awaddr;\t\t// From tx_emaxi of emaxi.v
+   wire [1:0]\t\tm_axi_awburst;\t\t// From tx_emaxi of emaxi.v
+   wire [3:0]\t\tm_axi_awcache;\t\t// From tx_emaxi of emaxi.v
+   wire [IDW-1:0]\tm_axi_awid;\t\t// From tx_emaxi of emaxi.v
+   wire [7:0]\t\tm_axi_awlen;\t\t// From tx_emaxi of emaxi.v
+   wire [1:0]\t\tm_axi_awlock;\t\t// From tx_emaxi of emaxi.v
+   wire [2:0]\t\tm_axi_awprot;\t\t// From tx_emaxi of emaxi.v
+   wire [3:0]\t\tm_axi_awqos;\t\t// From tx_emaxi of emaxi.v
+   wire\t\t\tm_axi_awready;\t\t// From elink2 of axi_elink.v
+   wire [2:0]\t\tm_axi_awsize;\t\t// From tx_emaxi of emaxi.v
+   wire\t\t\tm_axi_awvalid;\t\t// From tx_emaxi of emaxi.v
+   wire [S_IDW-1:0]\tm_axi_bid;\t\t// From elink2 of axi_elink.v
+   wire\t\t\tm_axi_bready;\t\t// From tx_emaxi of emaxi.v
+   wire [1:0]\t\tm_axi_bresp;\t\t// From elink2 of axi_elink.v
+   wire\t\t\tm_axi_bvalid;\t\t// From elink2 of axi_elink.v
+   wire [31:0]\t\tm_axi_rdata;\t\t// From elink2 of axi_elink.v
+   wire [S_IDW-1:0]\tm_axi_rid;\t\t// From elink2 of axi_elink.v
+   wire\t\t\tm_axi_rlast;\t\t// From elink2 of axi_elink.v
+   wire\t\t\tm_axi_rready;\t\t// From tx_emaxi of emaxi.v
+   wire [1:0]\t\tm_axi_rresp;\t\t// From elink2 of axi_elink.v
+   wire\t\t\tm_axi_rvalid;\t\t// From elink2 of axi_elink.v
+   wire [63:0]\t\tm_axi_wdata;\t\t// From tx_emaxi of emaxi.v
+   wire [IDW-1:0]\tm_axi_wid;\t\t// From tx_emaxi of emaxi.v
+   wire\t\t\tm_axi_wlast;\t\t// From tx_emaxi of emaxi.v
+   wire\t\t\tm_axi_wready;\t\t// From elink2 of axi_elink.v
+   wire [7:0]\t\tm_axi_wstrb;\t\t// From tx_emaxi of emaxi.v
+   wire\t\t\tm_axi_wvalid;\t\t// From tx_emaxi of emaxi.v
+   wire\t\t\trxo_rd_wait_n;\t\t// From elink2 of axi_elink.v
+   wire\t\t\trxo_rd_wait_p;\t\t// From elink2 of axi_elink.v
+   wire\t\t\trxo_wr_wait_n;\t\t// From elink2 of axi_elink.v
+   wire\t\t\trxo_wr_wait_p;\t\t// From elink2 of axi_elink.v
+   wire [31:0]\t\ts_axi_araddr;\t\t// From elink2 of axi_elink.v
+   wire [1:0]\t\ts_axi_arburst;\t\t// From elink2 of axi_elink.v
+   wire [3:0]\t\ts_axi_arcache;\t\t// From elink2 of axi_elink.v
+   wire [M_IDW-1:0]\ts_axi_arid;\t\t// From elink2 of axi_elink.v
+   wire [7:0]\t\ts_axi_arlen;\t\t// From elink2 of axi_elink.v
+   wire [1:0]\t\ts_axi_arlock;\t\t// From elink2 of axi_elink.v
+   wire [2:0]\t\ts_axi_arprot;\t\t// From elink2 of axi_elink.v
+   wire [3:0]\t\ts_axi_arqos;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ts_axi_arready;\t\t// From rx_esaxi of esaxi.v
+   wire [2:0]\t\ts_axi_arsize;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ts_axi_arvalid;\t\t// From elink2 of axi_elink.v
+   wire [31:0]\t\ts_axi_awaddr;\t\t// From elink2 of axi_elink.v
+   wire [1:0]\t\ts_axi_awburst;\t\t// From elink2 of axi_elink.v
+   wire [3:0]\t\ts_axi_awcache;\t\t// From elink2 of axi_elink.v
+   wire [M_IDW-1:0]\ts_axi_awid;\t\t// From elink2 of axi_elink.v
+   wire [7:0]\t\ts_axi_awlen;\t\t// From elink2 of axi_elink.v
+   wire [1:0]\t\ts_axi_awlock;\t\t// From elink2 of axi_elink.v
+   wire [2:0]\t\ts_axi_awprot;\t\t// From elink2 of axi_elink.v
+   wire [3:0]\t\ts_axi_awqos;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ts_axi_awready;\t\t// From rx_esaxi of esaxi.v
+   wire [2:0]\t\ts_axi_awsize;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ts_axi_awvalid;\t\t// From elink2 of axi_elink.v
+   wire [IDW-1:0]\ts_axi_bid;\t\t// From rx_esaxi of esaxi.v
+   wire\t\t\ts_axi_bready;\t\t// From elink2 of axi_elink.v
+   wire [1:0]\t\ts_axi_bresp;\t\t// From rx_esaxi of esaxi.v
+   wire\t\t\ts_axi_bvalid;\t\t// From rx_esaxi of esaxi.v
+   wire [31:0]\t\ts_axi_rdata;\t\t// From rx_esaxi of esaxi.v
+   wire [IDW-1:0]\ts_axi_rid;\t\t// From rx_esaxi of esaxi.v
+   wire\t\t\ts_axi_rlast;\t\t// From rx_esaxi of esaxi.v
+   wire\t\t\ts_axi_rready;\t\t// From elink2 of axi_elink.v
+   wire [1:0]\t\ts_axi_rresp;\t\t// From rx_esaxi of esaxi.v
+   wire\t\t\ts_axi_rvalid;\t\t// From rx_esaxi of esaxi.v
+   wire [63:0]\t\ts_axi_wdata;\t\t// From elink2 of axi_elink.v
+   wire [M_IDW-1:0]\ts_axi_wid;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ts_axi_wlast;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ts_axi_wready;\t\t// From rx_esaxi of esaxi.v
+   wire [7:0]\t\ts_axi_wstrb;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ts_axi_wvalid;\t\t// From elink2 of axi_elink.v
+   wire [7:0]\t\ttxo_data_n;\t\t// From elink2 of axi_elink.v
+   wire [7:0]\t\ttxo_data_p;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ttxo_frame_n;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ttxo_frame_p;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ttxo_lclk_n;\t\t// From elink2 of axi_elink.v
+   wire\t\t\ttxo_lclk_p;\t\t// From elink2 of axi_elink.v
+   // End of automatics
+   wire\t\telink0_rxrd_wait;\t// To elink0 of elink.v
+   wire\t\telink0_rxrr_wait;\t// To elink0 of elink.v
+   wire\t\telink0_rxwr_wait;\t// To elink0 of elink.v
+   wire\t\telink1_rxrd_wait;\t// To elink1 of elink.v
+   wire\t\telink1_rxrr_wait;\t// To elink1 of elink.v
+   wire\t\telink1_rxwr_wait;\t// To elink1 of elink.v
+   wire [3:0] \t\tcolid;
+   wire [3:0] \t\trowid;
+   wire \t\tmailbox_full;
+   wire \t\tmailbox_not_empty;
+   wire \t\tcclk_p, cclk_n;
+   wire \t\tchip_resetb;
+   wire \t\trx_lclk_pll;
+   wire \t\temem_access;
+   wire [PW-1:0]\temem_packet;
+   wire \t\tdut_access;
+   wire [PW-1:0]\tdut_packet;
+   wire \t\trxrr_access;
+   wire [PW-1:0] \trxrr_packet;
+   wire \t\trxwr_access;
+   wire [PW-1:0] \trxwr_packet;
+   wire \t\trxrd_access;
+   wire [PW-1:0] \trxrd_packet;
+
+   wire \t\telink0_txrr_access;
+   wire [PW-1:0] \telink0_txrr_packet;
+   wire \t\telink0_txwr_access;
+   wire [PW-1:0] \telink0_txwr_packet;
+   wire \t\telink0_txrd_access;
+   wire [PW-1:0] \telink0_txrd_packet;
+  
+   wire \t\telink1_txwr_access;
+   wire [PW-1:0] \telink1_txwr_packet;
+   wire \t\telink1_txrd_access;
+   wire [PW-1:0] \telink1_txrd_packet;
+
+   wire [7:0]           elink2_txo_data_p;
+   wire \t        elink2_txo_frame_p;
+   wire                 elink2_txo_lclk_p;
+
+   
+   wire                 emem_wait;
+
+   
+   reg [31:0] \t\t etime;  
+   wire \t itrace = 1\'b1;
+ 
+   
+   //Clocks
+   wire clkin         = clk; //for pll-->cclk, rxclk, txclk
+
+   //######
+   //CLOCKS for all
+   //######
+   /*eclocks AUTO_TEMPLATE (
+                            .\\(.*\\)             (@""(substring vl-cell-name  0 6)""_\\1[]),
+                            .reset\t\t(reset),
+                            .elink_reset\t(@""(substring vl-cell-name  0 6)""_reset),
+                            .rx_clkin\t\t(@""(substring vl-cell-name  0 6)""_rx_lclk_pll),
+                               );
+  */
+      
+   eclocks elink0_eclocks (.sys_clk\t\t(clk),\t\t\t   
+\t\t\t   .e_cclk_p\t\t(),
+\t\t\t   .e_cclk_n\t\t(),
+\t\t\t   /*AUTOINST*/
+\t\t\t   // Outputs
+\t\t\t   .tx_lclk\t\t(elink0_tx_lclk), // Templated
+\t\t\t   .tx_lclk90\t\t(elink0_tx_lclk90), // Templated
+\t\t\t   .tx_lclk_div4\t(elink0_tx_lclk_div4), // Templated
+\t\t\t   .rx_lclk\t\t(elink0_rx_lclk), // Templated
+\t\t\t   .rx_lclk_div4\t(elink0_rx_lclk_div4), // Templated
+\t\t\t   .elink_reset\t\t(elink0_reset),\t // Templated
+\t\t\t   .e_resetb\t\t(elink0_e_resetb), // Templated
+\t\t\t   // Inputs
+\t\t\t   .reset\t\t(reset),\t // Templated
+\t\t\t   .elink_en\t\t(elink0_elink_en), // Templated
+\t\t\t   .rx_clkin\t\t(elink0_rx_lclk_pll)); // Templated
+   
+   eclocks elink1_eclocks (.sys_clk\t\t(clk),\t\t\t   
+\t\t\t   .e_cclk_p\t\t(),
+\t\t\t   .e_cclk_n\t\t(),
+\t\t\t   /*AUTOINST*/
+\t\t\t   // Outputs
+\t\t\t   .tx_lclk\t\t(elink1_tx_lclk), // Templated
+\t\t\t   .tx_lclk90\t\t(elink1_tx_lclk90), // Templated
+\t\t\t   .tx_lclk_div4\t(elink1_tx_lclk_div4), // Templated
+\t\t\t   .rx_lclk\t\t(elink1_rx_lclk), // Templated
+\t\t\t   .rx_lclk_div4\t(elink1_rx_lclk_div4), // Templated
+\t\t\t   .elink_reset\t\t(elink1_reset),\t // Templated
+\t\t\t   .e_resetb\t\t(elink1_e_resetb), // Templated
+\t\t\t   // Inputs
+\t\t\t   .reset\t\t(reset),\t // Templated
+\t\t\t   .elink_en\t\t(elink1_elink_en), // Templated
+\t\t\t   .rx_clkin\t\t(elink1_rx_lclk_pll)); // Templated
+   
+
+   //Read path
+   assign elink0_txrd_access         = ext_access & ~ext_packet[1];
+   assign elink0_txrd_packet[PW-1:0] = ext_packet[PW-1:0];
+        
+   //Write path
+   assign elink0_txwr_access         = ext_access & ext_packet[1];
+   assign elink0_txwr_packet[PW-1:0] = ext_packet[PW-1:0];
+
+   //TX Pushback
+   assign dut_rd_wait                = elink0_txrd_wait;// | elink2_wait_out;   
+   assign dut_wr_wait                = elink0_txwr_wait;// | elink2_wait_out ;
+      
+   //Getting results back
+   assign dut_access                 = elink0_rxrr_access;
+   assign dut_packet[PW-1:0]         = elink0_rxrr_packet[PW-1:0];
+   
+   //No pushback testing on elink0
+   assign elink0_rxrd_wait = 1\'b0;
+   assign elink0_rxwr_wait = 1\'b0;
+   assign elink0_rxrr_wait = 1\'b0;
+
+   //not connected
+   assign elink0_txrr_access         =  1\'b0;
+   assign elink0_txrr_packet[PW-1:0] =  \'b0;
+
+
+   //######################################################################
+   //1ST ELINK
+   //######################################################################
+
+   /*elink AUTO_TEMPLATE (
+                         // Outputs                        
+                         .sys_clk            (clk),
+                         .\\(.*\\)             (@""(substring vl-cell-name  0 6)""_\\1[]),
+                         );
+  */
+
+   defparam elink0.ID    = 12\'h810;   
+   defparam elink0.ETYPE = 0; 
+   elink elink0 (
+\t\t .rxi_lclk_p\t\t(elink1_txo_lclk_p),
+\t\t .rxi_lclk_n\t\t(elink1_txo_lclk_n),
+\t\t .rxi_frame_p\t\t(elink1_txo_frame_p),
+\t\t .rxi_frame_n\t\t(elink1_txo_frame_n),
+\t\t .rxi_data_p\t\t(elink1_txo_data_p[7:0]),
+\t\t .rxi_data_n\t\t(elink1_txo_data_n[7:0]),
+\t\t .txi_wr_wait_p\t\t(elink1_rxo_wr_wait_p),
+\t\t .txi_wr_wait_n\t\t(elink1_rxo_wr_wait_n),
+\t\t .txi_rd_wait_p\t\t(elink1_rxo_rd_wait_p),
+\t\t .txi_rd_wait_n\t\t(elink1_rxo_rd_wait_n),
+\t\t /*AUTOINST*/
+\t\t // Outputs
+\t\t .rx_lclk_pll\t\t(elink0_rx_lclk_pll),\t // Templated
+\t\t .rxo_wr_wait_p\t\t(elink0_rxo_wr_wait_p),\t // Templated
+\t\t .rxo_wr_wait_n\t\t(elink0_rxo_wr_wait_n),\t // Templated
+\t\t .rxo_rd_wait_p\t\t(elink0_rxo_rd_wait_p),\t // Templated
+\t\t .rxo_rd_wait_n\t\t(elink0_rxo_rd_wait_n),\t // Templated
+\t\t .txo_lclk_p\t\t(elink0_txo_lclk_p),\t // Templated
+\t\t .txo_lclk_n\t\t(elink0_txo_lclk_n),\t // Templated
+\t\t .txo_frame_p\t\t(elink0_txo_frame_p),\t // Templated
+\t\t .txo_frame_n\t\t(elink0_txo_frame_n),\t // Templated
+\t\t .txo_data_p\t\t(elink0_txo_data_p[7:0]), // Templated
+\t\t .txo_data_n\t\t(elink0_txo_data_n[7:0]), // Templated
+\t\t .e_chipid\t\t(elink0_e_chipid[11:0]), // Templated
+\t\t .elink_en\t\t(elink0_elink_en),\t // Templated
+\t\t .mailbox_not_empty\t(elink0_mailbox_not_empty), // Templated
+\t\t .mailbox_full\t\t(elink0_mailbox_full),\t // Templated
+\t\t .timeout\t\t(elink0_timeout),\t // Templated
+\t\t .rxwr_access\t\t(elink0_rxwr_access),\t // Templated
+\t\t .rxwr_packet\t\t(elink0_rxwr_packet[PW-1:0]), // Templated
+\t\t .rxrd_access\t\t(elink0_rxrd_access),\t // Templated
+\t\t .rxrd_packet\t\t(elink0_rxrd_packet[PW-1:0]), // Templated
+\t\t .rxrr_access\t\t(elink0_rxrr_access),\t // Templated
+\t\t .rxrr_packet\t\t(elink0_rxrr_packet[PW-1:0]), // Templated
+\t\t .txwr_wait\t\t(elink0_txwr_wait),\t // Templated
+\t\t .txrd_wait\t\t(elink0_txrd_wait),\t // Templated
+\t\t .txrr_wait\t\t(elink0_txrr_wait),\t // Templated
+\t\t // Inputs
+\t\t .reset\t\t\t(elink0_reset),\t\t // Templated
+\t\t .sys_clk\t\t(clk),\t\t\t // Templated
+\t\t .tx_lclk\t\t(elink0_tx_lclk),\t // Templated
+\t\t .tx_lclk90\t\t(elink0_tx_lclk90),\t // Templated
+\t\t .tx_lclk_div4\t\t(elink0_tx_lclk_div4),\t // Templated
+\t\t .rx_lclk\t\t(elink0_rx_lclk),\t // Templated
+\t\t .rx_lclk_div4\t\t(elink0_rx_lclk_div4),\t // Templated
+\t\t .rxwr_wait\t\t(elink0_rxwr_wait),\t // Templated
+\t\t .rxrd_wait\t\t(elink0_rxrd_wait),\t // Templated
+\t\t .rxrr_wait\t\t(elink0_rxrr_wait),\t // Templated
+\t\t .txwr_access\t\t(elink0_txwr_access),\t // Templated
+\t\t .txwr_packet\t\t(elink0_txwr_packet[PW-1:0]), // Templated
+\t\t .txrd_access\t\t(elink0_txrd_access),\t // Templated
+\t\t .txrd_packet\t\t(elink0_txrd_packet[PW-1:0]), // Templated
+\t\t .txrr_access\t\t(elink0_txrr_access),\t // Templated
+\t\t .txrr_packet\t\t(elink0_txrr_packet[PW-1:0])); // Templated
+
+
+   //######################################################################
+   //2ND ELINK (WITH EPIPHANY MEMORY)
+   //######################################################################
+
+   //No read/write from elink1 (for now)
+   assign elink1_txrd_access = 1\'b0;
+   assign elink1_txrd_packet = \'b0;
+   assign elink1_txwr_access = 1\'b0;
+   assign elink1_txwr_packet = \'b0;
+   assign elink1_rxrr_wait   = 1\'b0;
+   
+   defparam elink1.ID = 12\'h820;   
+   defparam elink1.ETYPE = 0; 
+
+   elink elink1 (
+\t\t .rxi_lclk_p\t\t(elink0_txo_lclk_p),
+\t\t .rxi_lclk_n\t\t(elink0_txo_lclk_n),
+\t\t .rxi_frame_p\t\t(elink0_txo_frame_p),
+\t\t .rxi_frame_n\t\t(elink0_txo_frame_n),
+\t\t .rxi_data_p\t\t(elink0_txo_data_p[7:0]),
+\t\t .rxi_data_n\t\t(elink0_txo_data_n[7:0]),
+\t\t .txi_wr_wait_p\t\t(elink0_rxo_wr_wait_p),
+\t\t .txi_wr_wait_n\t\t(elink0_rxo_wr_wait_n),
+\t\t .txi_rd_wait_p\t\t(elink0_rxo_rd_wait_p),
+\t\t .txi_rd_wait_n\t\t(elink0_rxo_rd_wait_n),\t
+\t\t /*AUTOINST*/
+\t\t // Outputs
+\t\t .rx_lclk_pll\t\t(elink1_rx_lclk_pll),\t // Templated
+\t\t .rxo_wr_wait_p\t\t(elink1_rxo_wr_wait_p),\t // Templated
+\t\t .rxo_wr_wait_n\t\t(elink1_rxo_wr_wait_n),\t // Templated
+\t\t .rxo_rd_wait_p\t\t(elink1_rxo_rd_wait_p),\t // Templated
+\t\t .rxo_rd_wait_n\t\t(elink1_rxo_rd_wait_n),\t // Templated
+\t\t .txo_lclk_p\t\t(elink1_txo_lclk_p),\t // Templated
+\t\t .txo_lclk_n\t\t(elink1_txo_lclk_n),\t // Templated
+\t\t .txo_frame_p\t\t(elink1_txo_frame_p),\t // Templated
+\t\t .txo_frame_n\t\t(elink1_txo_frame_n),\t // Templated
+\t\t .txo_data_p\t\t(elink1_txo_data_p[7:0]), // Templated
+\t\t .txo_data_n\t\t(elink1_txo_data_n[7:0]), // Templated
+\t\t .e_chipid\t\t(elink1_e_chipid[11:0]), // Templated
+\t\t .elink_en\t\t(elink1_elink_en),\t // Templated
+\t\t .mailbox_not_empty\t(elink1_mailbox_not_empty), // Templated
+\t\t .mailbox_full\t\t(elink1_mailbox_full),\t // Templated
+\t\t .timeout\t\t(elink1_timeout),\t // Templated
+\t\t .rxwr_access\t\t(elink1_rxwr_access),\t // Templated
+\t\t .rxwr_packet\t\t(elink1_rxwr_packet[PW-1:0]), // Templated
+\t\t .rxrd_access\t\t(elink1_rxrd_access),\t // Templated
+\t\t .rxrd_packet\t\t(elink1_rxrd_packet[PW-1:0]), // Templated
+\t\t .rxrr_access\t\t(elink1_rxrr_access),\t // Templated
+\t\t .rxrr_packet\t\t(elink1_rxrr_packet[PW-1:0]), // Templated
+\t\t .txwr_wait\t\t(elink1_txwr_wait),\t // Templated
+\t\t .txrd_wait\t\t(elink1_txrd_wait),\t // Templated
+\t\t .txrr_wait\t\t(elink1_txrr_wait),\t // Templated
+\t\t // Inputs
+\t\t .reset\t\t\t(elink1_reset),\t\t // Templated
+\t\t .sys_clk\t\t(clk),\t\t\t // Templated
+\t\t .tx_lclk\t\t(elink1_tx_lclk),\t // Templated
+\t\t .tx_lclk90\t\t(elink1_tx_lclk90),\t // Templated
+\t\t .tx_lclk_div4\t\t(elink1_tx_lclk_div4),\t // Templated
+\t\t .rx_lclk\t\t(elink1_rx_lclk),\t // Templated
+\t\t .rx_lclk_div4\t\t(elink1_rx_lclk_div4),\t // Templated
+\t\t .rxwr_wait\t\t(elink1_rxwr_wait),\t // Templated
+\t\t .rxrd_wait\t\t(elink1_rxrd_wait),\t // Templated
+\t\t .rxrr_wait\t\t(elink1_rxrr_wait),\t // Templated
+\t\t .txwr_access\t\t(elink1_txwr_access),\t // Templated
+\t\t .txwr_packet\t\t(elink1_txwr_packet[PW-1:0]), // Templated
+\t\t .txrd_access\t\t(elink1_txrd_access),\t // Templated
+\t\t .txrd_packet\t\t(elink1_txrd_packet[PW-1:0]), // Templated
+\t\t .txrr_access\t\t(elink1_txrr_access),\t // Templated
+\t\t .txrr_packet\t\t(elink1_txrr_packet[PW-1:0])); // Templated
+   
+
+
+
+   reg [8:0] counter;
+   wire      elink1_random_wait;
+   
+   always @ (posedge clk)
+     if(reset)
+       counter <= \'b0;
+     else
+       counter <= counter+1;
+
+   assign elink1_random_wait = counter > 256;
+   
+   assign  emem_access           = (elink1_rxwr_access & ~(elink1_rxwr_packet[39:28]==elink1.ID)) |
+\t\t\t\t   (elink1_rxrd_access & ~(elink1_rxrd_packet[39:28]==elink1.ID));
+   
+   assign  emem_packet[PW-1:0]   = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
+                                                        elink1_rxrd_packet[PW-1:0];
+
+   assign elink1_rxrd_wait = emem_wait | elink1_rxwr_access;
+   assign elink1_rxwr_wait = 1\'b0;//elink1_random_wait
+   
+   /*ememory AUTO_TEMPLATE ( 
+                        // Outputs
+                        .\\(.*\\)_out       (elink1_txrr_\\1[]),
+                        .\\(.*\\)_in        (emem_\\1[]),
+                        .wait_out\t  (emem_wait),
+                         );
+   */
+
+   ememory emem (.wait_in\t        (1\'b0),       //only one read at a time, set to zero for no1
+\t\t .clk\t\t        (clk),
+\t\t .wait_out\t\t(emem_wait),
+\t\t /*AUTOINST*/
+\t\t // Outputs
+\t\t .access_out\t\t(elink1_txrr_access),\t // Templated
+\t\t .packet_out\t\t(elink1_txrr_packet[PW-1:0]), // Templated
+\t\t // Inputs
+\t\t .reset\t\t\t(reset),
+\t\t .access_in\t\t(emem_access),\t\t // Templated
+\t\t .packet_in\t\t(emem_packet[PW-1:0]));\t // Templated
+
+   
+   //######################################################################
+   //3rd ELINK (LOOPBACK), WITH EMAXI,ESAXI
+   //######################################################################
+   /*axi_elink AUTO_TEMPLATE (.m_\\(.*\\)      (s_\\1[]),
+                              .s_\\(.*\\)      (m_\\1[]),
+                         );
+  */
+
+   defparam elink2.ID    = 12\'h810;   
+   defparam elink2.ETYPE = 0; 
+
+   axi_elink elink2 (.sys_clk\t\t(clk),
+\t\t     .m_axi_aresetn\t(~reset),
+\t\t     .s_axi_aresetn\t(~reset),
+\t\t     .rxi_lclk_p\t(txo_lclk_p),
+\t\t     .rxi_lclk_n\t(txo_lclk_n),
+\t\t     .rxi_frame_p\t(txo_frame_p),
+\t\t     .rxi_frame_n\t(txo_frame_n),
+\t\t     .rxi_data_p\t(txo_data_p[7:0]),
+\t\t     .rxi_data_n\t(txo_data_n[7:0]),
+\t\t     .txi_wr_wait_p\t(rxo_wr_wait_p),
+\t\t     .txi_wr_wait_n\t(rxo_wr_wait_n),
+\t\t     .txi_rd_wait_p\t(rxo_rd_wait_p),
+\t\t     .txi_rd_wait_n\t(rxo_rd_wait_n),
+\t\t     .e_resetb   \t(chip_resetb), 
+\t\t     .e_cclk_p\t\t(cclk_p),
+\t\t     .e_cclk_n\t\t(cclk_n),
+\t\t     /*AUTOINST*/
+\t\t     // Outputs
+\t\t     .rxo_wr_wait_p\t(rxo_wr_wait_p),
+\t\t     .rxo_wr_wait_n\t(rxo_wr_wait_n),
+\t\t     .rxo_rd_wait_p\t(rxo_rd_wait_p),
+\t\t     .rxo_rd_wait_n\t(rxo_rd_wait_n),
+\t\t     .txo_lclk_p\t(txo_lclk_p),
+\t\t     .txo_lclk_n\t(txo_lclk_n),
+\t\t     .txo_frame_p\t(txo_frame_p),
+\t\t     .txo_frame_n\t(txo_frame_n),
+\t\t     .txo_data_p\t(txo_data_p[7:0]),
+\t\t     .txo_data_n\t(txo_data_n[7:0]),
+\t\t     .e_chipid\t\t(e_chipid[11:0]),
+\t\t     .mailbox_not_empty\t(mailbox_not_empty),
+\t\t     .mailbox_full\t(mailbox_full),
+\t\t     .m_axi_awid\t(s_axi_awid[M_IDW-1:0]), // Templated
+\t\t     .m_axi_awaddr\t(s_axi_awaddr[31:0]),\t // Templated
+\t\t     .m_axi_awlen\t(s_axi_awlen[7:0]),\t // Templated
+\t\t     .m_axi_awsize\t(s_axi_awsize[2:0]),\t // Templated
+\t\t     .m_axi_awburst\t(s_axi_awburst[1:0]),\t // Templated
+\t\t     .m_axi_awlock\t(s_axi_awlock[1:0]),\t // Templated
+\t\t     .m_axi_awcache\t(s_axi_awcache[3:0]),\t // Templated
+\t\t     .m_axi_awprot\t(s_axi_awprot[2:0]),\t // Templated
+\t\t     .m_axi_awqos\t(s_axi_awqos[3:0]),\t // Templated
+\t\t     .m_axi_awvalid\t(s_axi_awvalid),\t // Templated
+\t\t     .m_axi_wid\t\t(s_axi_wid[M_IDW-1:0]),\t // Templated
+\t\t     .m_axi_wdata\t(s_axi_wdata[63:0]),\t // Templated
+\t\t     .m_axi_wstrb\t(s_axi_wstrb[7:0]),\t // Templated
+\t\t     .m_axi_wlast\t(s_axi_wlast),\t\t // Templated
+\t\t     .m_axi_wvalid\t(s_axi_wvalid),\t\t // Templated
+\t\t     .m_axi_bready\t(s_axi_bready),\t\t // Templated
+\t\t     .m_axi_arid\t(s_axi_arid[M_IDW-1:0]), // Templated
+\t\t     .m_axi_araddr\t(s_axi_araddr[31:0]),\t // Templated
+\t\t     .m_axi_arlen\t(s_axi_arlen[7:0]),\t // Templated
+\t\t     .m_axi_arsize\t(s_axi_arsize[2:0]),\t // Templated
+\t\t     .m_axi_arburst\t(s_axi_arburst[1:0]),\t // Templated
+\t\t     .m_axi_arlock\t(s_axi_arlock[1:0]),\t // Templated
+\t\t     .m_axi_arcache\t(s_axi_arcache[3:0]),\t // Templated
+\t\t     .m_axi_arprot\t(s_axi_arprot[2:0]),\t // Templated
+\t\t     .m_axi_arqos\t(s_axi_arqos[3:0]),\t // Templated
+\t\t     .m_axi_arvalid\t(s_axi_arvalid),\t // Templated
+\t\t     .m_axi_rready\t(s_axi_rready),\t\t // Templated
+\t\t     .s_axi_arready\t(m_axi_arready),\t // Templated
+\t\t     .s_axi_awready\t(m_axi_awready),\t // Templated
+\t\t     .s_axi_bid\t\t(m_axi_bid[S_IDW-1:0]),\t // Templated
+\t\t     .s_axi_bresp\t(m_axi_bresp[1:0]),\t // Templated
+\t\t     .s_axi_bvalid\t(m_axi_bvalid),\t\t // Templated
+\t\t     .s_axi_rid\t\t(m_axi_rid[S_IDW-1:0]),\t // Templated
+\t\t     .s_axi_rdata\t(m_axi_rdata[31:0]),\t // Templated
+\t\t     .s_axi_rlast\t(m_axi_rlast),\t\t // Templated
+\t\t     .s_axi_rresp\t(m_axi_rresp[1:0]),\t // Templated
+\t\t     .s_axi_rvalid\t(m_axi_rvalid),\t\t // Templated
+\t\t     .s_axi_wready\t(m_axi_wready),\t\t // Templated
+\t\t     // Inputs
+\t\t     .reset\t\t(reset),
+\t\t     .m_axi_awready\t(s_axi_awready),\t // Templated
+\t\t     .m_axi_wready\t(s_axi_wready),\t\t // Templated
+\t\t     .m_axi_bid\t\t(s_axi_bid[M_IDW-1:0]),\t // Templated
+\t\t     .m_axi_bresp\t(s_axi_bresp[1:0]),\t // Templated
+\t\t     .m_axi_bvalid\t(s_axi_bvalid),\t\t // Templated
+\t\t     .m_axi_arready\t(s_axi_arready),\t // Templated
+\t\t     .m_axi_rid\t\t(s_axi_rid[M_IDW-1:0]),\t // Templated
+\t\t     .m_axi_rdata\t(s_axi_rdata[63:0]),\t // Templated
+\t\t     .m_axi_rresp\t(s_axi_rresp[1:0]),\t // Templated
+\t\t     .m_axi_rlast\t(s_axi_rlast),\t\t // Templated
+\t\t     .m_axi_rvalid\t(s_axi_rvalid),\t\t // Templated
+\t\t     .s_axi_arid\t(m_axi_arid[S_IDW-1:0]), // Templated
+\t\t     .s_axi_araddr\t(m_axi_araddr[31:0]),\t // Templated
+\t\t     .s_axi_arburst\t(m_axi_arburst[1:0]),\t // Templated
+\t\t     .s_axi_arcache\t(m_axi_arcache[3:0]),\t // Templated
+\t\t     .s_axi_arlock\t(m_axi_arlock[1:0]),\t // Templated
+\t\t     .s_axi_arlen\t(m_axi_arlen[7:0]),\t // Templated
+\t\t     .s_axi_arprot\t(m_axi_arprot[2:0]),\t // Templated
+\t\t     .s_axi_arqos\t(m_axi_arqos[3:0]),\t // Templated
+\t\t     .s_axi_arsize\t(m_axi_arsize[2:0]),\t // Templated
+\t\t     .s_axi_arvalid\t(m_axi_arvalid),\t // Templated
+\t\t     .s_axi_awid\t(m_axi_awid[S_IDW-1:0]), // Templated
+\t\t     .s_axi_awaddr\t(m_axi_awaddr[31:0]),\t // Templated
+\t\t     .s_axi_awburst\t(m_axi_awburst[1:0]),\t // Templated
+\t\t     .s_axi_awcache\t(m_axi_awcache[3:0]),\t // Templated
+\t\t     .s_axi_awlock\t(m_axi_awlock[1:0]),\t // Templated
+\t\t     .s_axi_awlen\t(m_axi_awlen[7:0]),\t // Templated
+\t\t     .s_axi_awprot\t(m_axi_awprot[2:0]),\t // Templated
+\t\t     .s_axi_awqos\t(m_axi_awqos[3:0]),\t // Templated
+\t\t     .s_axi_awsize\t(m_axi_awsize[2:0]),\t // Templated
+\t\t     .s_axi_awvalid\t(m_axi_awvalid),\t // Templated
+\t\t     .s_axi_bready\t(m_axi_bready),\t\t // Templated
+\t\t     .s_axi_rready\t(m_axi_rready),\t\t // Templated
+\t\t     .s_axi_wid\t\t(m_axi_wid[S_IDW-1:0]),\t // Templated
+\t\t     .s_axi_wdata\t(m_axi_wdata[31:0]),\t // Templated
+\t\t     .s_axi_wlast\t(m_axi_wlast),\t\t // Templated
+\t\t     .s_axi_wstrb\t(m_axi_wstrb[3:0]),\t // Templated
+\t\t     .s_axi_wvalid\t(m_axi_wvalid));\t\t // Templated
+   
+
+   //HACK!!!!!
+   wire          txrr_access;
+   wire [PW-1:0] txrr_packet;
+
+   //Read path
+   assign rxrd_access         = elink_axi_access & ~elink_axi_packet[1];
+   assign rxrd_packet[PW-1:0] = elink_axi_packet[PW-1:0];
+        
+   //Write path
+   assign rxwr_access         = elink_axi_access & elink_axi_packet[1];
+   assign rxwr_packet[PW-1:0] = elink_axi_packet[PW-1:0];
+
+   wire \t elink_axi_access;
+   wire [PW-1:0] elink_axi_packet;
+   
+   defparam axi_fifo.DW    = 104;
+   defparam axi_fifo.DEPTH = 32;  //TODO: fix the model, only 16/32 allowed!  
+   fifo_cdc  axi_fifo(
+\t\t\t// Outputs
+\t\t\t.wait_out\t(),
+\t\t\t.access_out\t(elink_axi_access),
+\t\t\t.packet_out\t(elink_axi_packet[PW-1:0]),
+\t\t\t// Inputs
+\t\t\t.clk_in\t\t(clk),
+\t\t\t.clk_out\t(clk),
+\t\t\t.reset_in\t(reset),
+\t\t\t.reset_out\t(reset),
+\t\t\t.access_in\t(ext_access),
+\t\t\t.packet_in\t(ext_packet[PW-1:0]),
+\t\t\t.wait_in\t((rxwr_access & rxwr_wait) |
+\t\t\t\t\t (rxrd_access & rxrd_wait)
+\t\t\t\t\t )
+\t\t\t);   
+   
+   //master interface (driving stimulus to TX path)
+   emaxi tx_emaxi (.m_axi_aclk\t\t(clk),
+                   .m_axi_aresetn\t(~reset),
+\t\t   .txrr_access\t\t(),        //output for monitoring
+\t\t   .txrr_packet\t\t(),//output for monitoring 
+\t\t   .rxwr_wait\t\t(rxwr_wait),          //ignore for now?
+\t\t   .rxrd_wait\t\t(rxrd_wait),          //ignore for now?\t\t   
+\t\t   .rxwr_access\t\t(rxwr_access),
+\t\t   .rxwr_packet\t\t(rxwr_packet[PW-1:0]),
+\t\t   .rxrd_access\t\t(rxrd_access),
+\t\t   .rxrd_packet\t\t(rxrd_packet[PW-1:0]),
+\t\t   .txrr_wait\t\t(1\'b0),
+\t\t   /*AUTOINST*/
+\t\t   // Outputs
+\t\t   .m_axi_awid\t\t(m_axi_awid[IDW-1:0]),
+\t\t   .m_axi_awaddr\t(m_axi_awaddr[31:0]),
+\t\t   .m_axi_awlen\t\t(m_axi_awlen[7:0]),
+\t\t   .m_axi_awsize\t(m_axi_awsize[2:0]),
+\t\t   .m_axi_awburst\t(m_axi_awburst[1:0]),
+\t\t   .m_axi_awlock\t(m_axi_awlock[1:0]),
+\t\t   .m_axi_awcache\t(m_axi_awcache[3:0]),
+\t\t   .m_axi_awprot\t(m_axi_awprot[2:0]),
+\t\t   .m_axi_awqos\t\t(m_axi_awqos[3:0]),
+\t\t   .m_axi_awvalid\t(m_axi_awvalid),
+\t\t   .m_axi_wid\t\t(m_axi_wid[IDW-1:0]),
+\t\t   .m_axi_wdata\t\t(m_axi_wdata[63:0]),
+\t\t   .m_axi_wstrb\t\t(m_axi_wstrb[7:0]),
+\t\t   .m_axi_wlast\t\t(m_axi_wlast),
+\t\t   .m_axi_wvalid\t(m_axi_wvalid),
+\t\t   .m_axi_bready\t(m_axi_bready),
+\t\t   .m_axi_arid\t\t(m_axi_arid[IDW-1:0]),
+\t\t   .m_axi_araddr\t(m_axi_araddr[31:0]),
+\t\t   .m_axi_arlen\t\t(m_axi_arlen[7:0]),
+\t\t   .m_axi_arsize\t(m_axi_arsize[2:0]),
+\t\t   .m_axi_arburst\t(m_axi_arburst[1:0]),
+\t\t   .m_axi_arlock\t(m_axi_arlock[1:0]),
+\t\t   .m_axi_arcache\t(m_axi_arcache[3:0]),
+\t\t   .m_axi_arprot\t(m_axi_arprot[2:0]),
+\t\t   .m_axi_arqos\t\t(m_axi_arqos[3:0]),
+\t\t   .m_axi_arvalid\t(m_axi_arvalid),
+\t\t   .m_axi_rready\t(m_axi_rready),
+\t\t   // Inputs
+\t\t   .m_axi_awready\t(m_axi_awready),
+\t\t   .m_axi_wready\t(m_axi_wready),
+\t\t   .m_axi_bid\t\t(m_axi_bid[IDW-1:0]),
+\t\t   .m_axi_bresp\t\t(m_axi_bresp[1:0]),
+\t\t   .m_axi_bvalid\t(m_axi_bvalid),
+\t\t   .m_axi_arready\t(m_axi_arready),
+\t\t   .m_axi_rid\t\t(m_axi_rid[IDW-1:0]),
+\t\t   .m_axi_rdata\t\t(m_axi_rdata[63:0]),
+\t\t   .m_axi_rresp\t\t(m_axi_rresp[1:0]),
+\t\t   .m_axi_rlast\t\t(m_axi_rlast),
+\t\t   .m_axi_rvalid\t(m_axi_rvalid));
+   
+   wire [PW-1:0] txwr_packet;
+   wire \t txwr_access;
+   wire [PW-1:0] txrd_packet;
+   wire \t txrd_access;
+   wire \t esaxi_rd_wait;
+   wire \t esaxi_wr_wait;
+   
+   //slave interface (receiving from 
+   esaxi rx_esaxi (.s_axi_aclk\t\t(clk),
+                   .s_axi_aresetn\t(~reset),
+\t\t   .txwr_access\t\t(txwr_access),//output to emem2
+\t\t   .txwr_packet\t\t(txwr_packet[PW-1:0]),
+\t\t   .txrd_access\t\t(txrd_access),
+\t\t   .txrd_packet\t\t(txrd_packet[PW-1:0]),
+\t\t   .rxrr_wait\t\t(),
+\t\t   .txwr_wait\t\t(esaxi_wr_wait),
+\t\t   .txrd_wait\t\t(esaxi_rd_wait),
+\t\t   .rxrr_access\t\t(rxrr_access),
+\t\t   .rxrr_packet\t\t(rxrr_packet[PW-1:0]),
+                   /*AUTOINST*/
+\t\t   // Outputs
+\t\t   .s_axi_arready\t(s_axi_arready),
+\t\t   .s_axi_awready\t(s_axi_awready),
+\t\t   .s_axi_bid\t\t(s_axi_bid[IDW-1:0]),
+\t\t   .s_axi_bresp\t\t(s_axi_bresp[1:0]),
+\t\t   .s_axi_bvalid\t(s_axi_bvalid),
+\t\t   .s_axi_rid\t\t(s_axi_rid[IDW-1:0]),
+\t\t   .s_axi_rdata\t\t(s_axi_rdata[31:0]),
+\t\t   .s_axi_rlast\t\t(s_axi_rlast),
+\t\t   .s_axi_rresp\t\t(s_axi_rresp[1:0]),
+\t\t   .s_axi_rvalid\t(s_axi_rvalid),
+\t\t   .s_axi_wready\t(s_axi_wready),
+\t\t   // Inputs
+\t\t   .s_axi_arid\t\t(s_axi_arid[IDW-1:0]),
+\t\t   .s_axi_araddr\t(s_axi_araddr[31:0]),
+\t\t   .s_axi_arburst\t(s_axi_arburst[1:0]),
+\t\t   .s_axi_arcache\t(s_axi_arcache[3:0]),
+\t\t   .s_axi_arlock\t(s_axi_arlock[1:0]),
+\t\t   .s_axi_arlen\t\t(s_axi_arlen[7:0]),
+\t\t   .s_axi_arprot\t(s_axi_arprot[2:0]),
+\t\t   .s_axi_arqos\t\t(s_axi_arqos[3:0]),
+\t\t   .s_axi_arsize\t(s_axi_arsize[2:0]),
+\t\t   .s_axi_arvalid\t(s_axi_arvalid),
+\t\t   .s_axi_awid\t\t(s_axi_awid[IDW-1:0]),
+\t\t   .s_axi_awaddr\t(s_axi_awaddr[31:0]),
+\t\t   .s_axi_awburst\t(s_axi_awburst[1:0]),
+\t\t   .s_axi_awcache\t(s_axi_awcache[3:0]),
+\t\t   .s_axi_awlock\t(s_axi_awlock[1:0]),
+\t\t   .s_axi_awlen\t\t(s_axi_awlen[7:0]),
+\t\t   .s_axi_awprot\t(s_axi_awprot[2:0]),
+\t\t   .s_axi_awqos\t\t(s_axi_awqos[3:0]),
+\t\t   .s_axi_awsize\t(s_axi_awsize[2:0]),
+\t\t   .s_axi_awvalid\t(s_axi_awvalid),
+\t\t   .s_axi_bready\t(s_axi_bready),
+\t\t   .s_axi_rready\t(s_axi_rready),
+\t\t   .s_axi_wid\t\t(s_axi_wid[IDW-1:0]),
+\t\t   .s_axi_wdata\t\t(s_axi_wdata[31:0]),
+\t\t   .s_axi_wlast\t\t(s_axi_wlast),
+\t\t   .s_axi_wstrb\t\t(s_axi_wstrb[3:0]),
+\t\t   .s_axi_wvalid\t(s_axi_wvalid));
+
+
+   wire \t emem2_access;
+   wire [PW-1:0] emem2_packet;
+ 
+   assign  emem2_access           = (txwr_access & ~(txwr_packet[39:28]==elink2.ID)) |
+\t\t\t\t    (txrd_access & ~(txrd_packet[39:28]==elink2.ID));
+   
+   assign  emem2_packet[PW-1:0]   = txwr_access ? txwr_packet[PW-1:0]:
+                                                  txrd_packet[PW-1:0];
+
+   assign esaxi_rd_wait = emem2_wait | txwr_access;
+   assign esaxi_wr_wait = 1\'b0; //no wait on write
+   
+   /*ememory AUTO_TEMPLATE ( 
+                        // Outputs
+                        .\\(.*\\)_out       (elink1_txrr_\\1[]),
+                        .\\(.*\\)_in        (emem_\\1[]),
+                        .wait_out\t  (emem_wait),
+                         );
+   */
+
+   ememory emem2 (.wait_in\t        (1\'b0),       //only one read at a time, set to zero for no1
+\t\t .clk\t\t        (clk),
+\t\t .wait_out\t\t(emem2_wait),
+\t\t .access_out\t\t(rxrr_access),
+\t\t .packet_out\t\t(rxrr_packet[PW-1:0]),
+\t\t  // Inputs
+\t\t  .reset\t\t(reset),
+\t\t  .access_in\t\t(emem2_access),
+\t\t  .packet_in\t\t(emem2_packet[PW-1:0]));
+
+
+   //######################################################################
+   //4th ELINK (chip reference model)
+   //######################################################################
+   wire elink2_access;
+   wire [PW-1:0] elink2_packet;
+   
+   defparam model_fifo.DW    = 104;
+   defparam model_fifo.DEPTH = 32;   
+   fifo_cdc  model_fifo(
+\t\t\t// Outputs
+\t\t\t.wait_out\t(),
+\t\t\t.access_out\t(elink2_access),
+\t\t\t.packet_out\t(elink2_packet[PW-1:0]),
+\t\t\t// Inputs
+\t\t\t.clk_in\t\t(clk),
+\t\t\t.clk_out\t(clk),
+\t\t\t.reset_in\t(reset),
+\t\t\t.reset_out\t(reset),
+\t\t\t.access_in\t(ext_access),
+\t\t\t.packet_in\t(ext_packet[PW-1:0]),
+\t\t\t.wait_in\t(1\'b0)//elink2_wait_out
+\t\t\t);   
+
+   elink_e16 elink_ref (
+\t\t     // Outputs
+\t\t     .rxi_rd_wait\t(),
+\t\t     .rxi_wr_wait\t(),
+\t\t     .txo_data\t\t(elink2_txo_data_p[7:0]),
+\t\t     .txo_lclk\t\t(elink2_txo_lclk_p),
+\t\t     .txo_frame\t\t(elink2_txo_frame_p),
+\t\t     .c0_mesh_access_out(),
+\t\t     .c0_mesh_write_out\t(),
+\t\t     .c0_mesh_dstaddr_out(),
+\t\t     .c0_mesh_srcaddr_out(),
+\t\t     .c0_mesh_data_out\t(),
+\t\t     .c0_mesh_datamode_out(),
+\t\t     .c0_mesh_ctrlmode_out(),
+\t\t     .c0_emesh_wait_out\t(),
+\t\t     .c0_mesh_wait_out\t(elink2_wait_out),
+\t\t     // Inputs
+\t\t     .reset\t\t(reset),
+\t\t     .c0_clk_in\t\t(clk),
+\t\t     .c1_clk_in\t\t(clk),
+\t\t     .c2_clk_in\t\t(clk),
+\t\t     .c3_clk_in\t\t(clk),
+\t\t     .rxi_data\t\t(8\'b0),
+\t\t     .rxi_lclk\t\t(1\'b0),
+\t\t     .rxi_frame\t\t(1\'b0),
+\t\t     .txo_rd_wait\t(1\'b0),
+\t\t     .txo_wr_wait\t(1\'b0),
+\t\t     .c0_mesh_access_in\t(elink2_access),
+\t\t     .c0_mesh_write_in\t(elink2_packet[1]),
+\t\t     .c0_mesh_dstaddr_in(elink2_packet[39:8]),
+\t\t     .c0_mesh_srcaddr_in(elink2_packet[103:72]),
+\t\t     .c0_mesh_data_in\t(elink2_packet[71:40]),
+\t\t     .c0_mesh_datamode_in(elink2_packet[3:2]),
+\t\t     .c0_mesh_ctrlmode_in(elink2_packet[7:4])\t\t     
+\t\t     );
+   
+
+  
+ 
+   
+   //######################################################################
+   //TRANSACTION MONITORS
+   //######################################################################
+   always @ (posedge clkin or posedge reset)
+     if(reset)
+       etime[31:0] <= 32\'b0;
+     else
+       etime[31:0] <= etime[31:0]+1\'b1;
+
+  /*emesh_monitor AUTO_TEMPLATE ( 
+                        // Outputs
+                        .emesh_\\(.*\\)     (@""(substring vl-cell-name  0 3)""_\\1[]),
+                        );
+   */
+
+
+   emesh_monitor #(.NAME(""stimulus"")) ext_monitor (.emesh_wait\t\t((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
+\t\t\t\t\t\t   .clk\t\t\t(clk),
+\t\t\t\t\t\t   /*AUTOINST*/
+\t\t\t\t\t\t   // Inputs
+\t\t\t\t\t\t   .reset\t\t(reset),
+\t\t\t\t\t\t   .itrace\t\t(itrace),
+\t\t\t\t\t\t   .etime\t\t(etime[31:0]),
+\t\t\t\t\t\t   .emesh_access\t(ext_access),\t // Templated
+\t\t\t\t\t\t   .emesh_packet\t(ext_packet[PW-1:0])); // Templated
+   
+   emesh_monitor #(.NAME(""dut"")) dut_monitor (.emesh_wait\t(1\'b0),
+\t\t\t\t\t      .clk\t\t(clk),
+\t\t\t\t\t      /*AUTOINST*/
+\t\t\t\t\t      // Inputs
+\t\t\t\t\t      .reset\t\t(reset),
+\t\t\t\t\t      .itrace\t\t(itrace),
+\t\t\t\t\t      .etime\t\t(etime[31:0]),
+\t\t\t\t\t      .emesh_access\t(dut_access),\t // Templated
+\t\t\t\t\t      .emesh_packet\t(dut_packet[PW-1:0])); // Templated
+
+   emesh_monitor #(.NAME(""emem"")) mem_monitor (.emesh_wait\t(1\'b0),
+\t\t\t\t\t\t.clk\t\t(clk),
+\t\t\t\t\t       .emesh_access\t(emem_access),
+\t\t\t\t\t       .emesh_packet\t(emem_packet[PW-1:0]),
+\t\t\t\t\t\t/*AUTOINST*/
+\t\t\t\t\t       // Inputs
+\t\t\t\t\t       .reset\t\t(reset),
+\t\t\t\t\t       .itrace\t\t(itrace),
+\t\t\t\t\t       .etime\t\t(etime[31:0]));
+   
+
+  
+     
+endmodule // dv_elink
+// Local Variables:
+// verilog-library-directories:(""."" ""../hdl"" ""../../memory/hdl"" ""../../emesh/hdl"")
+// End:
+
+/*
+ Copyright (C) 2014 Adapteva, Inc. 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+"
+"module elink(/*AUTOARG*/
+   // Outputs
+   rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
+   rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
+   txo_data_p, txo_data_n, e_chipid, elink_en, rxwr_access,
+   rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet,
+   txwr_wait, txrd_wait, txrr_wait, mailbox_not_empty, mailbox_full,
+   timeout,
+   // Inputs
+   reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk,
+   rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
+   rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
+   txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait, rxrr_wait,
+   txwr_access, txwr_packet, txrd_access, txrd_packet, txrr_access,
+   txrr_packet
+   );
+   
+   parameter AW          = 32;       //native address width
+   parameter DW          = 32;       //native data width
+   parameter PW          = 104;      //packet width   
+   parameter ID          = 12\'h810;  //epiphany ID for elink (ie addr[31:20])
+   parameter IOSTD_ELINK = ""LVDS_25"";
+   parameter ETYPE       = 1;
+   
+   /****************************/
+   /*CLOCK AND RESET           */
+   /****************************/
+   input        reset;         // hardware reset
+   input \tsys_clk;       // a single system clock for master/slave FIFOs
+   input \ttx_lclk;       // fast tx clock for IO
+   input \ttx_lclk90;     // fast 90deg shifted lclk   
+   input \ttx_lclk_div4;  // slow tx clock for core logic
+   input \trx_lclk;       // rx input clock tweaked by pll for IO
+   input \trx_lclk_div4;  // slow clock for rx logic 
+   output \trx_lclk_pll;   // rx_lclk pass through input for pll
+
+   /********************************/
+   /*ELINK RECEIVER                */
+   /********************************/          
+   input \trxi_lclk_p,   rxi_lclk_n;    // rx clock input
+   input        rxi_frame_p,  rxi_frame_n;   // rx frame signal
+   input [7:0] \trxi_data_p,   rxi_data_n;    // rx data
+   output       rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
+   output       rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
+
+   /********************************/
+   /*ELINK TRANSMITTER             */
+   /********************************/          
+   output \ttxo_lclk_p,   txo_lclk_n;    // tx clock output
+   output       txo_frame_p,  txo_frame_n;   // tx frame signal
+   output [7:0] txo_data_p,   txo_data_n;    // tx data
+   input \ttxi_wr_wait_p,txi_wr_wait_n; // tx write pushback input
+   input \ttxi_rd_wait_p,txi_rd_wait_n; // tx read pushback input
+
+   /*************************************/
+   /*EPIPHANY MISC INTERFACE (I/O PINS) */
+   /*************************************/          
+   output [11:0]   e_chipid;\t// chip id strap pins for epiphany
+   output \t   elink_en;    // master enable (reset) for elink/epiphany 
+   
+   /*****************************/
+   /*MAILBOX INTERRUPTS         */
+   /*****************************/
+   output       mailbox_not_empty;   
+   output       mailbox_full;
+
+   /*****************************/
+   /*READBACK TIMEOUT (TBD)     */
+   /*****************************/
+   output \ttimeout;
+
+   /*****************************/
+   /*SYSTEM SIDE INTERFACE      */
+   /*****************************/   
+   
+   //Master Write (from RX)
+   output \t   rxwr_access;
+   output [PW-1:0] rxwr_packet;
+   input \t   rxwr_wait;
+      
+   //Master Read Request (from RX)
+   output \t   rxrd_access;
+   output [PW-1:0] rxrd_packet;
+   input \t   rxrd_wait;
+   
+   //Slave Read Response (from RX)
+   output \t   rxrr_access;
+   output [PW-1:0] rxrr_packet;
+   input \t   rxrr_wait;
+   
+   //Slave Write (to TX)
+   input \t   txwr_access;
+   input [PW-1:0]  txwr_packet;
+   output \t   txwr_wait;
+
+   //Slave Read Request (to TX) 
+   input \t   txrd_access;
+   input [PW-1:0]  txrd_packet;
+   output \t   txrd_wait;
+   
+   //Master Read Response (to TX)
+   input \t   txrr_access;
+   input [PW-1:0]  txrr_packet;
+   output \t   txrr_wait;
+
+   /*#############################################*/
+   /*  END OF BLOCK INTERFACE                     */
+   /*#############################################*/
+   
+   /*AUTOINPUT*/
+
+   //wire
+   wire \t\terx_cfg_access;\t\t// To erx of erx.v
+   wire [PW-1:0] \terx_cfg_packet;\t\t// To erx of erx.v
+   wire \t\tetx_cfg_wait;\t\t// To etx of etx.v
+   wire [31:0] \t\tmi_rd_data;
+   wire [31:0] \t\tmi_dout_ecfg;
+   wire [31:0] \t\tmi_dout_embox;
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [15:0]\t\tclk_config;\t\t// From ecfg_elink of ecfg_elink.v
+   wire\t\t\terx_cfg_wait;\t\t// From erx of erx.v
+   wire\t\t\terx_reset;\t\t// From ereset of ereset.v
+   wire\t\t\tetx_cfg_access;\t\t// From etx of etx.v
+   wire [PW-1:0]\tetx_cfg_packet;\t\t// From etx of etx.v
+   wire\t\t\tetx_reset;\t\t// From ereset of ereset.v
+   wire\t\t\tsys_reset;\t\t// From ereset of ereset.v
+   wire\t\t\ttxwr_gated_access;\t// From ecfg_elink of ecfg_elink.v
+   wire \t\tetx90_reset;
+   wire \t\terx_ioreset;
+   
+   
+   // End of automatics
+   
+   /***********************************************************/
+   /*CLOCK AND RESET CONFIG                                   */
+   /***********************************************************/
+
+   defparam ecfg_elink.ID=ID;
+   
+   ecfg_elink ecfg_elink (.clk\t\t        (sys_clk),
+\t\t\t  /*AUTOINST*/
+\t\t\t  // Outputs
+\t\t\t  .txwr_gated_access\t(txwr_gated_access),
+\t\t\t  .elink_en\t\t(elink_en),
+\t\t\t  .clk_config\t\t(clk_config[15:0]),
+\t\t\t  .e_chipid\t\t(e_chipid[11:0]),
+\t\t\t  // Inputs
+\t\t\t  .txwr_access\t\t(txwr_access),
+\t\t\t  .txwr_packet\t\t(txwr_packet[PW-1:0]),
+\t\t\t  .reset\t\t(reset));
+
+   /***********************************************************/
+   /*RESET CIRCUITRY                                          */
+   /***********************************************************/
+   //Synchronize with each clock domain
+
+   ereset ereset (
+\t\t  /*AUTOINST*/
+\t\t  // Outputs
+\t\t  .etx_reset\t\t(etx_reset),
+\t\t  .erx_reset\t\t(erx_reset),
+\t\t  .sys_reset\t\t(sys_reset),
+\t\t  .etx90_reset         (etx90_reset),
+\t\t  .erx_ioreset(erx_ioreset),
+\t\t  // Inputs
+\t\t  .reset\t\t(reset),
+\t\t  .sys_clk\t\t(sys_clk),
+\t\t  .tx_lclk90(tx_lclk90),
+\t\t  .rx_lclk(rx_lclk),
+\t\t  .tx_lclk_div4\t\t(tx_lclk_div4),
+\t\t  .rx_lclk_div4\t\t(rx_lclk_div4));
+   
+   /***********************************************************/
+   /*RECEIVER                                                 */
+   /***********************************************************/
+   /*erx AUTO_TEMPLATE ( 
+\t                .mi_dout      (mi_rx_dout[]),
+                        .reset        (erx_reset),
+                       );
+   */
+   
+   defparam erx.ID          = ID;
+   defparam erx.IOSTD_ELINK = IOSTD_ELINK;
+   defparam erx.ETYPE       = ETYPE;
+   
+   erx erx(
+\t   /*AUTOINST*/
+\t   // Outputs
+\t   .rx_lclk_pll\t\t\t(rx_lclk_pll),
+\t   .rxo_wr_wait_p\t\t(rxo_wr_wait_p),
+\t   .rxo_wr_wait_n\t\t(rxo_wr_wait_n),
+\t   .rxo_rd_wait_p\t\t(rxo_rd_wait_p),
+\t   .rxo_rd_wait_n\t\t(rxo_rd_wait_n),
+\t   .rxwr_access\t\t\t(rxwr_access),
+\t   .rxwr_packet\t\t\t(rxwr_packet[PW-1:0]),
+\t   .rxrd_access\t\t\t(rxrd_access),
+\t   .rxrd_packet\t\t\t(rxrd_packet[PW-1:0]),
+\t   .rxrr_access\t\t\t(rxrr_access),
+\t   .rxrr_packet\t\t\t(rxrr_packet[PW-1:0]),
+\t   .erx_cfg_wait\t\t(erx_cfg_wait),
+\t   .timeout\t\t\t(timeout),
+\t   .mailbox_full\t\t(mailbox_full),
+\t   .mailbox_not_empty\t\t(mailbox_not_empty),
+\t   // Inputs
+\t   .erx_reset\t\t\t(erx_reset),
+\t   .erx_ioreset                 (erx_ioreset),
+\t   .sys_reset\t\t\t(sys_reset),
+\t   .sys_clk\t\t\t(sys_clk),
+\t   .rx_lclk\t\t\t(rx_lclk),
+\t   .rx_lclk_div4\t\t(rx_lclk_div4),
+\t   .rxi_lclk_p\t\t\t(rxi_lclk_p),
+\t   .rxi_lclk_n\t\t\t(rxi_lclk_n),
+\t   .rxi_frame_p\t\t\t(rxi_frame_p),
+\t   .rxi_frame_n\t\t\t(rxi_frame_n),
+\t   .rxi_data_p\t\t\t(rxi_data_p[7:0]),
+\t   .rxi_data_n\t\t\t(rxi_data_n[7:0]),
+\t   .rxwr_wait\t\t\t(rxwr_wait),
+\t   .rxrd_wait\t\t\t(rxrd_wait),
+\t   .rxrr_wait\t\t\t(rxrr_wait),
+\t   .erx_cfg_access\t\t(erx_cfg_access),
+\t   .erx_cfg_packet\t\t(erx_cfg_packet[PW-1:0]));
+
+   /***********************************************************/
+   /*TRANSMITTER                                              */
+   /***********************************************************/
+   /*etx AUTO_TEMPLATE (.mi_dout      (mi_tx_dout[]),
+                        .emwr_\\(.*\\)  (esaxi_emwr_\\1[]),
+                        .emrq_\\(.*\\)  (esaxi_emrq_\\1[]),
+                        .emrr_\\(.*\\)  (emaxi_emrr_\\1[]),
+                        .reset        (etx_reset),
+                        
+                       );
+   */
+
+   defparam etx.ID          = ID;
+   defparam etx.IOSTD_ELINK = IOSTD_ELINK;
+   defparam etx.ETYPE       = ETYPE;
+
+   etx etx(.txwr_access  (txwr_gated_access),
+\t   /*AUTOINST*/
+\t   // Outputs
+\t   .txo_lclk_p\t\t\t(txo_lclk_p),
+\t   .txo_lclk_n\t\t\t(txo_lclk_n),
+\t   .txo_frame_p\t\t\t(txo_frame_p),
+\t   .txo_frame_n\t\t\t(txo_frame_n),
+\t   .txo_data_p\t\t\t(txo_data_p[7:0]),
+\t   .txo_data_n\t\t\t(txo_data_n[7:0]),
+\t   .txrd_wait\t\t\t(txrd_wait),
+\t   .txwr_wait\t\t\t(txwr_wait),
+\t   .txrr_wait\t\t\t(txrr_wait),
+\t   .etx_cfg_access\t\t(etx_cfg_access),
+\t   .etx_cfg_packet\t\t(etx_cfg_packet[PW-1:0]),
+\t   // Inputs
+\t   .etx90_reset                 (etx90_reset),
+\t   .etx_reset\t\t\t(etx_reset),
+\t   .sys_reset\t\t\t(sys_reset),
+\t   .sys_clk\t\t\t(sys_clk),
+\t   .tx_lclk\t\t\t(tx_lclk),
+\t   .tx_lclk90\t\t\t(tx_lclk90),
+\t   .tx_lclk_div4\t\t(tx_lclk_div4),
+\t   .txi_wr_wait_p\t\t(txi_wr_wait_p),
+\t   .txi_wr_wait_n\t\t(txi_wr_wait_n),
+\t   .txi_rd_wait_p\t\t(txi_rd_wait_p),
+\t   .txi_rd_wait_n\t\t(txi_rd_wait_n),
+\t   .txrd_access\t\t\t(txrd_access),
+\t   .txrd_packet\t\t\t(txrd_packet[PW-1:0]),
+\t   .txwr_packet\t\t\t(txwr_packet[PW-1:0]),
+\t   .txrr_access\t\t\t(txrr_access),
+\t   .txrr_packet\t\t\t(txrr_packet[PW-1:0]),
+\t   .etx_cfg_wait\t\t(etx_cfg_wait));
+   
+   /***********************************************************/
+   /*TX-->RX REGISTER INTERFACE CONNECTION                    */
+   /***********************************************************/
+   defparam ecfg_cdc.DW=104;
+   defparam ecfg_cdc.DEPTH=32;
+   
+   fifo_cdc ecfg_cdc (// Outputs
+\t\t      .wait_out\t\t(etx_cfg_wait),\t
+\t\t      .access_out\t(erx_cfg_access),\t
+\t\t      .packet_out\t(erx_cfg_packet[PW-1:0]),
+\t\t      // Inputs
+\t\t      .clk_in\t\t(tx_lclk_div4),\t
+\t\t      .reset_in\t\t(etx_reset),
+\t\t      .access_in\t(etx_cfg_access),
+\t\t      .packet_in\t(etx_cfg_packet[PW-1:0]),
+\t\t      .clk_out\t\t(rx_lclk_div4),\t
+\t\t      .reset_out\t(erx_reset),
+\t\t      .wait_in\t\t(erx_cfg_wait)
+\t\t      );
+   
+   
+endmodule // elink
+// Local Variables:
+// verilog-library-directories:(""."" ""../../erx/hdl"" ""../../etx/hdl""  ""../../memory/hdl"")
+// End:
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+ 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
+// Date        : Thu Jul  2 14:31:27 2015
+// Host        : parallella running 64-bit Ubuntu 14.04.2 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/aolofsson/Work_all/oh/elink/scripts/xilinx/temp/temp.srcs/sources_1/ip/fifo_async_104x16/fifo_async_104x16_stub.v
+// Design      : fifo_async_104x16
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z020clg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = ""fifo_generator_v12_0,Vivado 2014.3.1"" *)
+module fifo_async_104x16(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, almost_full, empty, valid, prog_full)
+/* synthesis syn_black_box black_box_pad_pin=""wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full"" */;
+  input wr_clk;
+  input wr_rst;
+  input rd_clk;
+  input rd_rst;
+  input [103:0]din;
+  input wr_en;
+  input rd_en;
+  output [103:0]dout;
+  output full;
+
+  output almost_full;
+
+  output empty;
+
+  output valid;
+
+  output prog_full;
+endmodule
+"
+"/*
+ This block handles the autoincrement needed for bursting and detects 
+ read responses
+ */
+`include ""elink_regmap.v""
+module erx_protocol (/*AUTOARG*/
+   // Outputs
+   erx_rdwr_access, erx_rr_access, erx_packet,
+   // Inputs
+   reset, rx_enable, clk, rx_packet, rx_burst, rx_access
+   );
+
+   parameter AW   = 32;
+   parameter DW   = 32;
+   parameter PW   = 104;
+   parameter ID   = 12\'h800; //link id
+
+   
+   // System reset input
+   input           reset;
+   input \t   rx_enable;//Enables receiver
+
+   // Parallel interface, 8 eLink bytes at a time
+   input           clk;
+   input [PW-1:0]  rx_packet;
+   input \t   rx_burst;
+   input \t   rx_access;
+   
+   // Output to MMU / filter
+   output          erx_rdwr_access;
+   output          erx_rr_access;
+   output [PW-1:0] erx_packet;
+
+
+   //wires
+   reg [31:0] \t   dstaddr_reg;   
+   wire [31:0] \t   dstaddr_next;
+   wire [31:0] \t   dstaddr_mux;
+   reg \t\t   erx_rdwr_access;
+   reg \t\t   erx_rr_access;
+   reg [PW-1:0]    erx_packet;
+   wire [11:0] \t   myid;
+   wire [31:0] \t   rx_addr;
+   wire \t   read_response;
+
+   //parsing inputs
+   assign \t myid[11:0]     = ID;   
+   assign        rx_addr[31:0]  = rx_packet[39:8];
+   
+   //Address generator for bursting
+   always @ (posedge clk)
+     if(rx_access)
+       dstaddr_reg[31:0]     <= dstaddr_mux[31:0];
+
+   assign dstaddr_next[31:0] = dstaddr_reg[31:0] + 4\'b1000;
+   
+   assign dstaddr_mux[31:0] =  rx_burst ? dstaddr_next[31:0] :
+\t\t\t                  rx_addr[31:0];
+      
+   
+   //Read response detector
+   assign read_response = (rx_addr[31:20] == myid[11:0]) & 
+\t\t\t  (rx_addr[19:16] == `EGROUP_RR);
+      
+   
+   //Pipeline stage and decode  
+   always @ (posedge clk)
+     begin
+\t//Write/read request
+\terx_rdwr_access     <= rx_access & ~read_response;      
+\t//Read response
+\terx_rr_access       <= rx_access & read_response;
+\t//Common packet
+\terx_packet[PW-1:0]  <= {rx_packet[PW-1:40],
+\t\t\t\tdstaddr_mux[31:0],
+\t\t\t\trx_packet[7:0]
+\t\t\t      };
+     end
+  
+endmodule // erx_protocol
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"`timescale 1ns/1ps\r
+module dv_elink_tb();\r
+   parameter AW=32;\r
+   parameter DW=32;\r
+   parameter PW=104;\r
+   parameter CW=2;    //number of clocks to send int\r
+   parameter MW=104;\r
+   parameter MAW=10;    \r
+   parameter MD=1<<MAW;//limit test to 1K transactions\r
+   //TODO:generealize\r
+   \r
+\r
+/* verilator lint_off STMTDLY */\r
+/* verilator lint_off UNOPTFLAT */\r
+   //REGS\r
+   reg           clk;\r
+   reg \t\t reset;   \r
+   reg \t\t go;\r
+   reg [1:0] \t datamode;\r
+   reg \t\t ext_access;\r
+   reg \t\t ext_write;\r
+   reg [1:0] \t ext_datamode;\r
+   reg [3:0]     ext_ctrlmode;            \r
+   reg [31:0]    ext_dstaddr;\r
+   reg [31:0]    ext_data;\r
+   reg [31:0]    ext_srcaddr;   \r
+   reg           ext_wr_wait;\r
+   reg           ext_rd_wait;\r
+   wire [PW-1:0] ext_packet;\r
+\r
+   reg \t\t init;\r
+   reg [MW-1:0]  stimarray[MD-1:0];\r
+   reg [MW-1:0]  transaction;\r
+   reg [MAW-1:0] stim_addr;\r
+   reg [1:0] \t state;\r
+   reg [31:0] \t count;\r
+   reg \t start;\r
+   \r
+   integer \t i;\r
+   \r
+`ifdef MANUAL   \r
+   //TODO: make test name a parameter, fancify,...   \r
+   initial\r
+     begin\r
+\tfor(i=0;i<MD;i++)\r
+\t  stimarray[i]=\'d0;\r
+\t//$readmemh(`TESTNAME,stimarray,0,`TRANS-1);//How to?\r
+\t$readmemh(""test.memh"",stimarray,0,`TRANS-1);\r
+     end\r
+`endif\r
+\r
+   //Forever clock\r
+   always\r
+     #5  clk = ~clk; //system clock (100MHz)\r
+   \r
+   wire clkstim = clk;\r
+      \r
+   //Reset\r
+   initial\r
+     begin\r
+\t#0\r
+\t  reset    = 1\'b1;    // reset is active\r
+          start    = 1\'b0;\r
+\t  clk      = 1\'b0;\r
+\t#1000 \r
+\r
+`ifdef AUTO\r
+          //clock config (fast /2)\r
+          dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16\'h0113;\r
+          //tx config  (enable)\r
+   \t  dv_elink.elink.ecfg.ecfg_tx_reg[8:0]   = 9\'h001;\r
+          //rx config (enable)\r
+\t  dv_elink.elink.ecfg.ecfg_rx_reg[4:0]   = 5\'h01;\r
+`endif\r
+\t  reset    = 1\'b0;    // at time 100 release reset\r
+\t#4000\r
+\t  start       = 1\'b1;\t\r
+\t#10000\t  \r
+\t  $finish;\r
+     end\r
+\r
+\r
+`define IDLE  2\'b00\r
+`define DONE  2\'b10\r
+`define GO    2\'b01\r
+   \r
+   always @ (posedge clk or posedge reset)\r
+     if(reset)\r
+       state[1:0] <= `IDLE;//not started\r
+     else if(start & (state[1:0]==`IDLE))\r
+       state[1:0] <= `GO;//going\r
+     else if( ~(|count) & (state[1:0]==`GO))\r
+       state[1:0] <= `DONE;//gone\r
+   \r
+   //Notes:The testbench\r
+   //  connects a 64 bit master to a 32 bit slave\r
+   //To make this work, we limit the addresses to 64 bit aligned\r
+   \r
+//Stimulus Driver   \r
+always @ (posedge clkstim)\r
+  if(reset)\r
+    begin\r
+       ext_access          <= 1\'b0; //empty\r
+       ext_write           <= 1\'b0;\r
+       ext_datamode[1:0]   <= 2\'b0;\r
+       ext_ctrlmode[3:0]   <= 4\'b0;\r
+       ext_data[31:0]      <= 32\'b0;\r
+       ext_dstaddr[31:0]   <= 32\'b0;\r
+       ext_srcaddr[31:0]   <= 32\'b0;\r
+       ext_rd_wait         <= 1\'b0;\r
+       ext_wr_wait         <= 1\'b0;\r
+       stim_addr[MAW-1:0]  <= \'d0;\r
+       transaction[MW-1:0] <= \'d0;\r
+       count               <= `TRANS;\r
+    end   \r
+  else if ((state[1:0]==`GO) & ~(dut_wr_wait|dut_rd_wait))\r
+    begin\r
+       transaction[MW-1:0] <= stimarray[stim_addr];\r
+       ext_access          <= transaction[0];\r
+       ext_write           <= transaction[1];\r
+       ext_datamode[1:0]   <= transaction[3:2];\r
+       ext_ctrlmode[3:0]   <= transaction[7:4];\r
+       ext_dstaddr[31:0]   <= transaction[39:8];\r
+       ext_data[31:0]      <= transaction[71:40];\r
+       ext_srcaddr[31:0]   <= transaction[103:72];\r
+       stim_addr[MAW-1:0]  <= stim_addr[MAW-1:0] + 1\'b1; \r
+       count               <= count - 1\'b1;\r
+    end\r
+  else\r
+    ext_access <= 1\'b0;\r
+   \r
+   //Waveform dump\r
+`ifndef TARGET_VERILATOR\r
+   initial\r
+     begin\r
+\t$dumpfile(""test.vcd"");\r
+\t$dumpvars(0, dv_elink_tb);\r
+     end\r
+`endif\r
+   \r
+   /*AUTOWIRE*/\r
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)\r
+   wire\t\t\tdut_access;\t\t// From dv_elink of dv_elink.v\r
+   wire\t\t\tdut_failed;\t\t// From dv_elink of dv_elink.v\r
+   wire [PW-1:0]\tdut_packet;\t\t// From dv_elink of dv_elink.v\r
+   wire\t\t\tdut_passed;\t\t// From dv_elink of dv_elink.v\r
+   wire\t\t\tdut_rd_wait;\t\t// From dv_elink of dv_elink.v\r
+   wire\t\t\tdut_wr_wait;\t\t// From dv_elink of dv_elink.v\r
+   // End of automatics\r
+   \r
+   emesh2packet e2p (\r
+\t\t     // Outputs\r
+\t\t     .packet_out\t(ext_packet[PW-1:0]),\r
+\t\t     // Inputs\r
+\t\t     .access_in\t\t(ext_access),\r
+\t\t     .write_in\t\t(ext_write),\r
+\t\t     .datamode_in\t(ext_datamode[1:0]),\r
+\t\t     .ctrlmode_in\t(ext_ctrlmode[3:0]),\r
+\t\t     .dstaddr_in\t(ext_dstaddr[AW-1:0]),\r
+\t\t     .data_in\t\t(ext_data[DW-1:0]),\r
+\t\t     .srcaddr_in\t(ext_srcaddr[AW-1:0]));\r
+   \r
+   \r
+   //dut\r
+   dv_elink dv_elink(/*AUTOINST*/\r
+\t\t     // Outputs\r
+\t\t     .dut_passed\t(dut_passed),\r
+\t\t     .dut_failed\t(dut_failed),\r
+\t\t     .dut_rd_wait\t(dut_rd_wait),\r
+\t\t     .dut_wr_wait\t(dut_wr_wait),\r
+\t\t     .dut_access\t(dut_access),\r
+\t\t     .dut_packet\t(dut_packet[PW-1:0]),\r
+\t\t     // Inputs\r
+\t\t     .clk\t\t(clk),\r
+\t\t     .reset\t\t(reset),\r
+\t\t     .ext_access\t(ext_access),\r
+\t\t     .ext_packet\t(ext_packet[PW-1:0]),\r
+\t\t     .ext_rd_wait\t(ext_rd_wait),\r
+\t\t     .ext_wr_wait\t(ext_wr_wait));\r
+  \r
+endmodule // dv_elink_tb\r
+// Local Variables:\r
+// verilog-library-directories:(""."" ""../../emesh/hdl"")\r
+// End:\r
+\r
+\r
+/*\r
+ Copyright (C) 2014 Adapteva, Inc. \r
+ Contributed by Andreas Olofsson <andreas@adapteva.com>\r
+\r
+ This program is free software: you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation, either version 3 of the License, or\r
+ (at your option) any later version.This program is distributed in the hope \r
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied \r
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+ GNU General Public License for more details. You should have received a copy \r
+ of the GNU General Public License along with this program (see the file \r
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.\r
+ */\r
+"
+"module dv_elink(/*AUTOARG*/
+   // Outputs
+   dut_passed, dut_failed, dut_rd_wait, dut_wr_wait, dut_access,
+   dut_write, dut_datamode, dut_ctrlmode, dut_dstaddr, dut_srcaddr,
+   dut_data,
+   // Inputs
+   clk, reset, ext_access, ext_write, ext_datamode, ext_ctrlmode,
+   ext_dstaddr, ext_data, ext_srcaddr, ext_rd_wait, ext_wr_wait
+   );
+
+   parameter AW=32;
+   parameter DW=32;
+   parameter CW=2;             //number of clocks to send int
+   parameter IDW=12;
+   
+   //Basic
+   input  [CW-1:0] clk;        // Core clock
+   input           reset;      // Reset
+   output          dut_passed; // Indicates passing test
+   output          dut_failed; // Indicates failing test
+
+   //Input Transaction
+   input           ext_access;
+   input           ext_write;
+   input [1:0] \t   ext_datamode;
+   input [3:0]     ext_ctrlmode;            
+   input [31:0]    ext_dstaddr;
+   input [31:0]    ext_data;
+   input [31:0]    ext_srcaddr;      
+   output          dut_rd_wait;
+   output          dut_wr_wait;
+
+   //Output Transaction
+   output          dut_access;
+   output \t   dut_write;
+   output [1:0]    dut_datamode;
+   output [3:0]    dut_ctrlmode;            
+   output [31:0]   dut_dstaddr;
+   output [31:0]   dut_srcaddr;
+   output [31:0]   dut_data;  
+   input           ext_rd_wait;
+   input           ext_wr_wait;
+
+   
+   /*AUTOINPUT*/
+   /*AUTOOUTPUT*/
+   
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [7:0]\t\tdata_n;\t\t\t// From elink of elink.v
+   wire [7:0]\t\tdata_p;\t\t\t// From elink of elink.v
+   wire [31:0]\t\tdv_axi_araddr;\t\t// From dv_emaxi of emaxi.v
+   wire [1:0]\t\tdv_axi_arburst;\t\t// From dv_emaxi of emaxi.v
+   wire [3:0]\t\tdv_axi_arcache;\t\t// From dv_emaxi of emaxi.v
+   wire [IDW-1:0]\tdv_axi_arid;\t\t// From dv_emaxi of emaxi.v
+   wire [7:0]\t\tdv_axi_arlen;\t\t// From dv_emaxi of emaxi.v
+   wire [1:0]\t\tdv_axi_arlock;\t\t// From dv_emaxi of emaxi.v
+   wire [2:0]\t\tdv_axi_arprot;\t\t// From dv_emaxi of emaxi.v
+   wire [3:0]\t\tdv_axi_arqos;\t\t// From dv_emaxi of emaxi.v
+   wire\t\t\tdv_axi_arready;\t\t// From elink of elink.v
+   wire [2:0]\t\tdv_axi_arsize;\t\t// From dv_emaxi of emaxi.v
+   wire\t\t\tdv_axi_arvalid;\t\t// From dv_emaxi of emaxi.v
+   wire [31:0]\t\tdv_axi_awaddr;\t\t// From dv_emaxi of emaxi.v
+   wire [1:0]\t\tdv_axi_awburst;\t\t// From dv_emaxi of emaxi.v
+   wire [3:0]\t\tdv_axi_awcache;\t\t// From dv_emaxi of emaxi.v
+   wire [IDW-1:0]\tdv_axi_awid;\t\t// From dv_emaxi of emaxi.v
+   wire [7:0]\t\tdv_axi_awlen;\t\t// From dv_emaxi of emaxi.v
+   wire [1:0]\t\tdv_axi_awlock;\t\t// From dv_emaxi of emaxi.v
+   wire [2:0]\t\tdv_axi_awprot;\t\t// From dv_emaxi of emaxi.v
+   wire [3:0]\t\tdv_axi_awqos;\t\t// From dv_emaxi of emaxi.v
+   wire\t\t\tdv_axi_awready;\t\t// From elink of elink.v
+   wire [2:0]\t\tdv_axi_awsize;\t\t// From dv_emaxi of emaxi.v
+   wire\t\t\tdv_axi_awvalid;\t\t// From dv_emaxi of emaxi.v
+   wire [IDW-1:0]\tdv_axi_bid;\t\t// From elink of elink.v
+   wire\t\t\tdv_axi_bready;\t\t// From dv_emaxi of emaxi.v
+   wire [1:0]\t\tdv_axi_bresp;\t\t// From elink of elink.v
+   wire\t\t\tdv_axi_bvalid;\t\t// From elink of elink.v
+   wire [IDW-1:0]\tdv_axi_rid;\t\t// From elink of elink.v
+   wire\t\t\tdv_axi_rlast;\t\t// From elink of elink.v
+   wire\t\t\tdv_axi_rready;\t\t// From dv_emaxi of emaxi.v
+   wire [1:0]\t\tdv_axi_rresp;\t\t// From elink of elink.v
+   wire\t\t\tdv_axi_rvalid;\t\t// From elink of elink.v
+   wire [63:0]\t\tdv_axi_wdata;\t\t// From dv_emaxi of emaxi.v
+   wire [IDW-1:0]\tdv_axi_wid;\t\t// From dv_emaxi of emaxi.v
+   wire\t\t\tdv_axi_wlast;\t\t// From dv_emaxi of emaxi.v
+   wire\t\t\tdv_axi_wready;\t\t// From elink of elink.v
+   wire [7:0]\t\tdv_axi_wstrb;\t\t// From dv_emaxi of emaxi.v
+   wire\t\t\tdv_axi_wvalid;\t\t// From dv_emaxi of emaxi.v
+   wire [31:0]\t\telink_axi_araddr;\t// From elink of elink.v
+   wire [1:0]\t\telink_axi_arburst;\t// From elink of elink.v
+   wire [3:0]\t\telink_axi_arcache;\t// From elink of elink.v
+   wire [IDW-1:0]\telink_axi_arid;\t\t// From elink of elink.v
+   wire [7:0]\t\telink_axi_arlen;\t// From elink of elink.v
+   wire [1:0]\t\telink_axi_arlock;\t// From elink of elink.v
+   wire [2:0]\t\telink_axi_arprot;\t// From elink of elink.v
+   wire [3:0]\t\telink_axi_arqos;\t// From elink of elink.v
+   wire\t\t\telink_axi_arready;\t// From dv_esaxi of esaxi.v
+   wire [2:0]\t\telink_axi_arsize;\t// From elink of elink.v
+   wire\t\t\telink_axi_arvalid;\t// From elink of elink.v
+   wire [31:0]\t\telink_axi_awaddr;\t// From elink of elink.v
+   wire [1:0]\t\telink_axi_awburst;\t// From elink of elink.v
+   wire [3:0]\t\telink_axi_awcache;\t// From elink of elink.v
+   wire [IDW-1:0]\telink_axi_awid;\t\t// From elink of elink.v
+   wire [7:0]\t\telink_axi_awlen;\t// From elink of elink.v
+   wire [1:0]\t\telink_axi_awlock;\t// From elink of elink.v
+   wire [2:0]\t\telink_axi_awprot;\t// From elink of elink.v
+   wire [3:0]\t\telink_axi_awqos;\t// From elink of elink.v
+   wire\t\t\telink_axi_awready;\t// From dv_esaxi of esaxi.v
+   wire [2:0]\t\telink_axi_awsize;\t// From elink of elink.v
+   wire\t\t\telink_axi_awvalid;\t// From elink of elink.v
+   wire [IDW-1:0]\telink_axi_bid;\t\t// From dv_esaxi of esaxi.v
+   wire\t\t\telink_axi_bready;\t// From elink of elink.v
+   wire [1:0]\t\telink_axi_bresp;\t// From dv_esaxi of esaxi.v
+   wire\t\t\telink_axi_bvalid;\t// From dv_esaxi of esaxi.v
+   wire [31:0]\t\telink_axi_rdata;\t// From dv_esaxi of esaxi.v
+   wire [IDW-1:0]\telink_axi_rid;\t\t// From dv_esaxi of esaxi.v
+   wire\t\t\telink_axi_rlast;\t// From dv_esaxi of esaxi.v
+   wire\t\t\telink_axi_rready;\t// From elink of elink.v
+   wire [1:0]\t\telink_axi_rresp;\t// From dv_esaxi of esaxi.v
+   wire\t\t\telink_axi_rvalid;\t// From dv_esaxi of esaxi.v
+   wire [63:0]\t\telink_axi_wdata;\t// From elink of elink.v
+   wire [IDW-1:0]\telink_axi_wid;\t\t// From elink of elink.v
+   wire\t\t\telink_axi_wlast;\t// From elink of elink.v
+   wire\t\t\telink_axi_wready;\t// From dv_esaxi of esaxi.v
+   wire [7:0]\t\telink_axi_wstrb;\t// From elink of elink.v
+   wire\t\t\telink_axi_wvalid;\t// From elink of elink.v
+   wire\t\t\temem_emrq_wait;\t\t// From emem of ememory.v
+   wire\t\t\tesaxi_emrr_access;\t// From emem of ememory.v
+   wire [DW-1:0]\tesaxi_emrr_data;\t// From emem of ememory.v
+   wire\t\t\tframe_n;\t\t// From elink of elink.v
+   wire\t\t\tframe_p;\t\t// From elink of elink.v
+   wire\t\t\tlclk_n;\t\t\t// From elink of elink.v
+   wire\t\t\tlclk_p;\t\t\t// From elink of elink.v
+   wire\t\t\trd_wait_n;\t\t// From elink of elink.v
+   wire\t\t\trd_wait_p;\t\t// From elink of elink.v
+   wire\t\t\twr_wait_n;\t\t// From elink of elink.v
+   wire\t\t\twr_wait_p;\t\t// From elink of elink.v
+   // End of automatics
+
+   wire [31:0] \t\tdv_axi_rdata; //restricted to 32 bits here
+   wire \t\temaxi_emrq_rd_en;\t// From emaxi of emaxi.v
+   wire \t\temaxi_emwr_rd_en;\t// From emaxi of emaxi.v
+   wire \t\temaxi_emrq_access;\t// To emaxi of emaxi.v
+   wire [3:0]\t\temaxi_emrq_ctrlmode;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emrq_data;\t// To emaxi of emaxi.v
+   wire [1:0]\t\temaxi_emrq_datamode;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emrq_dstaddr;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emrq_srcaddr;\t// To emaxi of emaxi.v
+   wire \t\temaxi_emrq_write;\t// To emaxi of emaxi.v
+   wire \t\temaxi_emwr_access;\t// To emaxi of emaxi.v
+   wire [3:0]\t\temaxi_emwr_ctrlmode;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emwr_data;\t// To emaxi of emaxi.v
+   wire [1:0]\t\temaxi_emwr_datamode;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emwr_dstaddr;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emwr_srcaddr;\t// To emaxi of emaxi.v
+   wire \t\temaxi_emwr_write;\t// To emaxi of emaxi.v
+   wire \t\temaxi_emrr_access;\t// To emaxi of emaxi.v
+   wire [3:0]\t\temaxi_emrr_ctrlmode;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emrr_data;\t// To emaxi of emaxi.v
+   wire [1:0]\t\temaxi_emrr_datamode;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emrr_dstaddr;\t// To emaxi of emaxi.v
+   wire [31:0]\t\temaxi_emrr_srcaddr;\t// To emaxi of emaxi.v
+   wire \t\temaxi_emrr_write;\t// To emaxi of emaxi.v
+   
+   wire \t\tesaxi_emrq_access;\t// From esaxi of esaxi.v
+   wire [3:0]\t\tesaxi_emrq_ctrlmode;\t// From esaxi of esaxi.v
+   wire [31:0] \t\tesaxi_emrq_data;\t// From esaxi of esaxi.v
+   wire [1:0] \t\tesaxi_emrq_datamode;\t// From esaxi of esaxi.v
+   wire [31:0] \t\tesaxi_emrq_dstaddr;\t// From esaxi of esaxi.v
+   wire [31:0] \t\tesaxi_emrq_srcaddr;\t// From esaxi of esaxi.v
+   wire \t\tesaxi_emrq_write;\t// From esaxi of esaxi.v
+   wire \t\tesaxi_emrr_rd_en;\t// From esaxi of esaxi.v
+   wire \t\tesaxi_emwr_access;\t// From esaxi of esaxi.v
+   wire [3:0] \t\tesaxi_emwr_ctrlmode;\t// From esaxi of esaxi.v
+   wire [31:0] \t\tesaxi_emwr_data;\t// From esaxi of esaxi.v
+   wire [1:0] \t\tesaxi_emwr_datamode;\t// From esaxi of esaxi.v
+   wire [31:0] \t\tesaxi_emwr_dstaddr;\t// From esaxi of esaxi.v
+   wire [31:0] \t\tesaxi_emwr_srcaddr;\t// From esaxi of esaxi.v
+   wire \t\tesaxi_emwr_write;\t// From esaxi of esaxi.v
+   wire [3:0] \t\tcolid;
+   wire [3:0] \t\trowid;
+   wire \t\tembox_full;
+   wire \t\tembox_not_empty;
+   wire \t\tcclk_p, cclk_n;
+   wire \t\tchip_resetb;
+   wire \t\tdut_access;\t\t// To dut_monitor of emesh_monitor.v
+   wire [3:0]\t\tdut_ctrlmode;\t\t// To dut_monitor of emesh_monitor.v
+   wire [DW-1:0]\tdut_data;\t\t// To dut_monitor of emesh_monitor.v
+   wire [1:0]\t\tdut_datamode;\t\t// To dut_monitor of emesh_monitor.v
+   wire [AW-1:0]\tdut_dstaddr;\t\t// To dut_monitor of emesh_monitor.v
+   wire [AW-1:0]\tdut_srcaddr;\t\t// To dut_monitor of emesh_monitor.v
+   wire\t\t        dut_write;\t\t// To dut_monitor of emesh_monitor.v
+  
+   
+   //Clocks
+   wire clkin         = clk[0]; //for pll-->cclk, rxclk, txclk
+   wire m_axi_aclk    = clk[1]; 
+   wire s_axi_aclk    = clk[1];
+   
+   //Splitting transaction into read/write path
+
+   //Read path
+   assign emaxi_emrq_access        = ext_access & ~ext_write;
+   assign emaxi_emrq_write         = 1\'b0;
+   assign emaxi_emrq_datamode[1:0] = ext_datamode[1:0];
+   assign emaxi_emrq_ctrlmode[3:0] = ext_ctrlmode[3:0];
+   assign emaxi_emrq_dstaddr[31:0] = ext_dstaddr[31:0];
+   assign emaxi_emrq_data[31:0]    = ext_data[31:0];
+   assign emaxi_emrq_srcaddr[31:0] = ext_srcaddr[31:0];
+   
+   //Write path
+   assign emaxi_emwr_access        = ext_access & ext_write;
+   assign emaxi_emwr_write         = 1\'b1;
+   assign emaxi_emwr_datamode[1:0] = ext_datamode[1:0];
+   assign emaxi_emwr_ctrlmode[3:0] = ext_ctrlmode[3:0];
+   assign emaxi_emwr_dstaddr[31:0] = ext_dstaddr[31:0];
+   assign emaxi_emwr_data[31:0]    = ext_data[31:0];
+   assign emaxi_emwr_srcaddr[31:0] = ext_srcaddr[31:0];
+
+   //Master pushback
+   assign dut_rd_wait           = ~emaxi_emrq_rd_en & emaxi_emrq_access;
+   assign dut_wr_wait           = ~emaxi_emwr_rd_en & emaxi_emwr_access;
+   
+   //Getting results back
+
+   assign dut_access        = emaxi_emrr_access;
+   assign dut_write         = emaxi_emrr_write;
+   assign dut_datamode[1:0] = emaxi_emrr_datamode[1:0];
+   assign dut_ctrlmode[3:0] = emaxi_emrr_ctrlmode[3:0];
+   assign dut_dstaddr[31:0] = emaxi_emrr_dstaddr[31:0];
+   assign dut_data[31:0]    = emaxi_emrr_data[31:0];
+   assign dut_srcaddr[31:0] = emaxi_emrr_srcaddr[31:0];
+  
+   /*emaxi AUTO_TEMPLATE ( 
+                        // Outputs
+                        .m_\\(.*\\)    (dv_\\1[]),
+                        .em\\(.*\\)    (emaxi_em\\1[]),
+                        .m_axi_rdata ({dv_axi_rdata[31:0],dv_axi_rdata[31:0]}),
+    );
+   */
+   
+   //Drive the elink slave AXI interface
+   emaxi dv_emaxi(.emrr_progfull\t\t(1\'b0),
+\t       .m_axi_aresetn\t\t(~reset),
+\t       .m_axi_aclk\t\t(m_axi_aclk),
+\t       .emwr_rd_en\t\t(emaxi_emwr_rd_en),
+\t       .emrq_rd_en\t\t(emaxi_emrq_rd_en),
+\t       .emrr_access\t\t(emaxi_emrr_access),
+\t       .emrr_write\t\t(emaxi_emrr_write),
+\t       .emrr_datamode\t\t(emaxi_emrr_datamode[1:0]),
+\t       .emrr_ctrlmode\t\t(emaxi_emrr_ctrlmode[3:0]),
+\t       .emrr_dstaddr\t\t(emaxi_emrr_dstaddr[31:0]),
+\t       .emrr_data\t\t(emaxi_emrr_data[31:0]),
+\t       .emrr_srcaddr\t\t(emaxi_emrr_srcaddr[31:0]),
+\t       /*AUTOINST*/
+\t\t  // Outputs
+\t\t  .m_axi_awid\t\t(dv_axi_awid[IDW-1:0]),\t // Templated
+\t\t  .m_axi_awaddr\t\t(dv_axi_awaddr[31:0]),\t // Templated
+\t\t  .m_axi_awlen\t\t(dv_axi_awlen[7:0]),\t // Templated
+\t\t  .m_axi_awsize\t\t(dv_axi_awsize[2:0]),\t // Templated
+\t\t  .m_axi_awburst\t(dv_axi_awburst[1:0]),\t // Templated
+\t\t  .m_axi_awlock\t\t(dv_axi_awlock[1:0]),\t // Templated
+\t\t  .m_axi_awcache\t(dv_axi_awcache[3:0]),\t // Templated
+\t\t  .m_axi_awprot\t\t(dv_axi_awprot[2:0]),\t // Templated
+\t\t  .m_axi_awqos\t\t(dv_axi_awqos[3:0]),\t // Templated
+\t\t  .m_axi_awvalid\t(dv_axi_awvalid),\t // Templated
+\t\t  .m_axi_wid\t\t(dv_axi_wid[IDW-1:0]),\t // Templated
+\t\t  .m_axi_wdata\t\t(dv_axi_wdata[63:0]),\t // Templated
+\t\t  .m_axi_wstrb\t\t(dv_axi_wstrb[7:0]),\t // Templated
+\t\t  .m_axi_wlast\t\t(dv_axi_wlast),\t\t // Templated
+\t\t  .m_axi_wvalid\t\t(dv_axi_wvalid),\t // Templated
+\t\t  .m_axi_bready\t\t(dv_axi_bready),\t // Templated
+\t\t  .m_axi_arid\t\t(dv_axi_arid[IDW-1:0]),\t // Templated
+\t\t  .m_axi_araddr\t\t(dv_axi_araddr[31:0]),\t // Templated
+\t\t  .m_axi_arlen\t\t(dv_axi_arlen[7:0]),\t // Templated
+\t\t  .m_axi_arsize\t\t(dv_axi_arsize[2:0]),\t // Templated
+\t\t  .m_axi_arburst\t(dv_axi_arburst[1:0]),\t // Templated
+\t\t  .m_axi_arlock\t\t(dv_axi_arlock[1:0]),\t // Templated
+\t\t  .m_axi_arcache\t(dv_axi_arcache[3:0]),\t // Templated
+\t\t  .m_axi_arprot\t\t(dv_axi_arprot[2:0]),\t // Templated
+\t\t  .m_axi_arqos\t\t(dv_axi_arqos[3:0]),\t // Templated
+\t\t  .m_axi_arvalid\t(dv_axi_arvalid),\t // Templated
+\t\t  .m_axi_rready\t\t(dv_axi_rready),\t // Templated
+\t\t  // Inputs
+\t\t  .emwr_access\t\t(emaxi_emwr_access),\t // Templated
+\t\t  .emwr_write\t\t(emaxi_emwr_write),\t // Templated
+\t\t  .emwr_datamode\t(emaxi_emwr_datamode[1:0]), // Templated
+\t\t  .emwr_ctrlmode\t(emaxi_emwr_ctrlmode[3:0]), // Templated
+\t\t  .emwr_dstaddr\t\t(emaxi_emwr_dstaddr[31:0]), // Templated
+\t\t  .emwr_data\t\t(emaxi_emwr_data[31:0]), // Templated
+\t\t  .emwr_srcaddr\t\t(emaxi_emwr_srcaddr[31:0]), // Templated
+\t\t  .emrq_access\t\t(emaxi_emrq_access),\t // Templated
+\t\t  .emrq_write\t\t(emaxi_emrq_write),\t // Templated
+\t\t  .emrq_datamode\t(emaxi_emrq_datamode[1:0]), // Templated
+\t\t  .emrq_ctrlmode\t(emaxi_emrq_ctrlmode[3:0]), // Templated
+\t\t  .emrq_dstaddr\t\t(emaxi_emrq_dstaddr[31:0]), // Templated
+\t\t  .emrq_data\t\t(emaxi_emrq_data[31:0]), // Templated
+\t\t  .emrq_srcaddr\t\t(emaxi_emrq_srcaddr[31:0]), // Templated
+\t\t  .m_axi_awready\t(dv_axi_awready),\t // Templated
+\t\t  .m_axi_wready\t\t(dv_axi_wready),\t // Templated
+\t\t  .m_axi_bid\t\t(dv_axi_bid[IDW-1:0]),\t // Templated
+\t\t  .m_axi_bresp\t\t(dv_axi_bresp[1:0]),\t // Templated
+\t\t  .m_axi_bvalid\t\t(dv_axi_bvalid),\t // Templated
+\t\t  .m_axi_arready\t(dv_axi_arready),\t // Templated
+\t\t  .m_axi_rid\t\t(dv_axi_rid[IDW-1:0]),\t // Templated
+\t\t  .m_axi_rdata\t\t({dv_axi_rdata[31:0],dv_axi_rdata[31:0]}), // Templated
+\t\t  .m_axi_rresp\t\t(dv_axi_rresp[1:0]),\t // Templated
+\t\t  .m_axi_rlast\t\t(dv_axi_rlast),\t\t // Templated
+\t\t  .m_axi_rvalid\t\t(dv_axi_rvalid));\t // Templated
+
+
+   /*esaxi AUTO_TEMPLATE ( 
+                        // Outputs
+                        .s_\\(.*\\)         (elink_\\1[]),
+                        .mi_\\(.*\\)        (),
+                        .em\\(.*\\)         (esaxi_em\\1[]),
+                        .emrq_progfull\t  (emem_emrq_wait),
+                        );
+   */
+
+
+   esaxi dv_esaxi (.emwr_progfull\t\t(1\'b0),
+\t\t
+\t\t.mi_ecfg_dout\t\t(32\'b0),
+\t\t.mi_tx_emmu_dout\t(32\'b0),
+\t\t.mi_rx_emmu_dout\t(32\'b0),
+\t\t.mi_embox_dout\t\t(32\'b0),
+\t\t.ecfg_tx_ctrlmode\t(4\'b0),
+\t\t.ecfg_coreid\t\t(12\'h808),
+\t\t.ecfg_timeout_enable\t(1\'b0),
+\t\t.s_axi_aresetn\t\t(~reset),
+\t\t.s_axi_aclk\t\t(s_axi_aclk),
+\t\t.emwr_access\t\t(esaxi_emwr_access),
+\t\t.emwr_write\t\t(esaxi_emwr_write),
+\t\t.emwr_datamode\t\t(esaxi_emwr_datamode[1:0]),
+\t\t.emwr_ctrlmode\t\t(esaxi_emwr_ctrlmode[3:0]),
+\t\t.emwr_dstaddr\t\t(esaxi_emwr_dstaddr[31:0]),
+\t\t.emwr_data\t\t(esaxi_emwr_data[31:0]),
+\t\t.emwr_srcaddr\t\t(esaxi_emwr_srcaddr[31:0]),
+\t\t.emrq_access\t\t(esaxi_emrq_access),
+\t\t.emrq_write\t\t(esaxi_emrq_write),
+\t\t.emrq_datamode\t\t(esaxi_emrq_datamode[1:0]),
+\t\t.emrq_ctrlmode\t\t(esaxi_emrq_ctrlmode[3:0]),
+\t\t.emrq_dstaddr\t\t(esaxi_emrq_dstaddr[31:0]),
+\t\t.emrq_data\t\t(esaxi_emrq_data[31:0]),
+\t\t.emrq_srcaddr\t\t(esaxi_emrq_srcaddr[31:0]),
+\t\t.emrr_rd_en\t\t(esaxi_emrr_rd_en),
+\t\t/*AUTOINST*/
+\t\t   // Outputs
+\t\t   .mi_clk\t\t(),\t\t\t // Templated
+\t\t   .mi_rx_emmu_sel\t(),\t\t\t // Templated
+\t\t   .mi_tx_emmu_sel\t(),\t\t\t // Templated
+\t\t   .mi_ecfg_sel\t\t(),\t\t\t // Templated
+\t\t   .mi_embox_sel\t(),\t\t\t // Templated
+\t\t   .mi_we\t\t(),\t\t\t // Templated
+\t\t   .mi_addr\t\t(),\t\t\t // Templated
+\t\t   .mi_din\t\t(),\t\t\t // Templated
+\t\t   .s_axi_arready\t(elink_axi_arready),\t // Templated
+\t\t   .s_axi_awready\t(elink_axi_awready),\t // Templated
+\t\t   .s_axi_bid\t\t(elink_axi_bid[IDW-1:0]), // Templated
+\t\t   .s_axi_bresp\t\t(elink_axi_bresp[1:0]),\t // Templated
+\t\t   .s_axi_bvalid\t(elink_axi_bvalid),\t // Templated
+\t\t   .s_axi_rid\t\t(elink_axi_rid[IDW-1:0]), // Templated
+\t\t   .s_axi_rdata\t\t(elink_axi_rdata[31:0]), // Templated
+\t\t   .s_axi_rlast\t\t(elink_axi_rlast),\t // Templated
+\t\t   .s_axi_rresp\t\t(elink_axi_rresp[1:0]),\t // Templated
+\t\t   .s_axi_rvalid\t(elink_axi_rvalid),\t // Templated
+\t\t   .s_axi_wready\t(elink_axi_wready),\t // Templated
+\t\t   // Inputs
+\t\t   .emrq_progfull\t(emem_emrq_wait),\t // Templated
+\t\t   .emrr_data\t\t(esaxi_emrr_data[31:0]), // Templated
+\t\t   .emrr_access\t\t(esaxi_emrr_access),\t // Templated
+\t\t   .s_axi_arid\t\t(elink_axi_arid[IDW-1:0]), // Templated
+\t\t   .s_axi_araddr\t(elink_axi_araddr[31:0]), // Templated
+\t\t   .s_axi_arburst\t(elink_axi_arburst[1:0]), // Templated
+\t\t   .s_axi_arcache\t(elink_axi_arcache[3:0]), // Templated
+\t\t   .s_axi_arlock\t(elink_axi_arlock[1:0]), // Templated
+\t\t   .s_axi_arlen\t\t(elink_axi_arlen[7:0]),\t // Templated
+\t\t   .s_axi_arprot\t(elink_axi_arprot[2:0]), // Templated
+\t\t   .s_axi_arqos\t\t(elink_axi_arqos[3:0]),\t // Templated
+\t\t   .s_axi_arsize\t(elink_axi_arsize[2:0]), // Templated
+\t\t   .s_axi_arvalid\t(elink_axi_arvalid),\t // Templated
+\t\t   .s_axi_awid\t\t(elink_axi_awid[IDW-1:0]), // Templated
+\t\t   .s_axi_awaddr\t(elink_axi_awaddr[31:0]), // Templated
+\t\t   .s_axi_awburst\t(elink_axi_awburst[1:0]), // Templated
+\t\t   .s_axi_awcache\t(elink_axi_awcache[3:0]), // Templated
+\t\t   .s_axi_awlock\t(elink_axi_awlock[1:0]), // Templated
+\t\t   .s_axi_awlen\t\t(elink_axi_awlen[7:0]),\t // Templated
+\t\t   .s_axi_awprot\t(elink_axi_awprot[2:0]), // Templated
+\t\t   .s_axi_awqos\t\t(elink_axi_awqos[3:0]),\t // Templated
+\t\t   .s_axi_awsize\t(elink_axi_awsize[2:0]), // Templated
+\t\t   .s_axi_awvalid\t(elink_axi_awvalid),\t // Templated
+\t\t   .s_axi_bready\t(elink_axi_bready),\t // Templated
+\t\t   .s_axi_rready\t(elink_axi_rready),\t // Templated
+\t\t   .s_axi_wid\t\t(elink_axi_wid[IDW-1:0]), // Templated
+\t\t   .s_axi_wdata\t\t(elink_axi_wdata[31:0]), // Templated
+\t\t   .s_axi_wlast\t\t(elink_axi_wlast),\t // Templated
+\t\t   .s_axi_wstrb\t\t(elink_axi_wstrb[3:0]),\t // Templated
+\t\t   .s_axi_wvalid\t(elink_axi_wvalid));\t // Templated
+   
+   
+   /*elink AUTO_TEMPLATE ( 
+                        // Outputs
+                        .txo_\\(.*\\)       (\\1[]),
+                        .rxi_\\(.*\\)       (\\1[]),  
+                        .rxo_\\(.*\\)       (\\1[]),
+                        .txi_\\(.*\\)       (\\1[]),  
+                        .s_\\(.*\\)         (dv_\\1[]),
+                        .m_\\(.*\\)         (elink_\\1[]),
+                        .m_axi_rdata\t  ({elink_axi_rdata[31:0],elink_axi_rdata[31:0]}), //restricted to slave width
+                        );
+   */
+
+   defparam elink.ELINKID = 12\'h800;
+
+   elink elink (.hard_reset\t\t(reset),
+\t\t.embox_not_empty\t(embox_not_empty),
+\t\t.embox_full\t\t(embox_full),
+\t\t.chip_resetb\t\t(chip_resetb),
+\t\t.colid\t\t\t(colid[3:0]),
+\t\t.rowid\t\t\t(rowid[3:0]),
+\t\t.s_axi_aresetn\t\t(~reset),
+\t\t.m_axi_aresetn\t\t(~reset),
+\t\t.s_axi_aclk\t\t(s_axi_aclk),
+\t\t.m_axi_aclk\t\t(m_axi_aclk),
+\t\t.cclk_p\t\t\t(cclk_p),
+\t\t.cclk_n\t\t\t(cclk_n),
+\t\t.clkin\t\t\t(clkin),
+\t\t.clkbypass              ({clkin,clkin,clkin}),
+\t\t/*AUTOINST*/
+\t\t// Outputs
+\t\t.rxo_wr_wait_p\t\t(wr_wait_p),\t\t // Templated
+\t\t.rxo_wr_wait_n\t\t(wr_wait_n),\t\t // Templated
+\t\t.rxo_rd_wait_p\t\t(rd_wait_p),\t\t // Templated
+\t\t.rxo_rd_wait_n\t\t(rd_wait_n),\t\t // Templated
+\t\t.txo_lclk_p\t\t(lclk_p),\t\t // Templated
+\t\t.txo_lclk_n\t\t(lclk_n),\t\t // Templated
+\t\t.txo_frame_p\t\t(frame_p),\t\t // Templated
+\t\t.txo_frame_n\t\t(frame_n),\t\t // Templated
+\t\t.txo_data_p\t\t(data_p[7:0]),\t\t // Templated
+\t\t.txo_data_n\t\t(data_n[7:0]),\t\t // Templated
+\t\t.m_axi_awid\t\t(elink_axi_awid[IDW-1:0]), // Templated
+\t\t.m_axi_awaddr\t\t(elink_axi_awaddr[31:0]), // Templated
+\t\t.m_axi_awlen\t\t(elink_axi_awlen[7:0]),\t // Templated
+\t\t.m_axi_awsize\t\t(elink_axi_awsize[2:0]), // Templated
+\t\t.m_axi_awburst\t\t(elink_axi_awburst[1:0]), // Templated
+\t\t.m_axi_awlock\t\t(elink_axi_awlock[1:0]), // Templated
+\t\t.m_axi_awcache\t\t(elink_axi_awcache[3:0]), // Templated
+\t\t.m_axi_awprot\t\t(elink_axi_awprot[2:0]), // Templated
+\t\t.m_axi_awqos\t\t(elink_axi_awqos[3:0]),\t // Templated
+\t\t.m_axi_awvalid\t\t(elink_axi_awvalid),\t // Templated
+\t\t.m_axi_wid\t\t(elink_axi_wid[IDW-1:0]), // Templated
+\t\t.m_axi_wdata\t\t(elink_axi_wdata[63:0]), // Templated
+\t\t.m_axi_wstrb\t\t(elink_axi_wstrb[7:0]),\t // Templated
+\t\t.m_axi_wlast\t\t(elink_axi_wlast),\t // Templated
+\t\t.m_axi_wvalid\t\t(elink_axi_wvalid),\t // Templated
+\t\t.m_axi_bready\t\t(elink_axi_bready),\t // Templated
+\t\t.m_axi_arid\t\t(elink_axi_arid[IDW-1:0]), // Templated
+\t\t.m_axi_araddr\t\t(elink_axi_araddr[31:0]), // Templated
+\t\t.m_axi_arlen\t\t(elink_axi_arlen[7:0]),\t // Templated
+\t\t.m_axi_arsize\t\t(elink_axi_arsize[2:0]), // Templated
+\t\t.m_axi_arburst\t\t(elink_axi_arburst[1:0]), // Templated
+\t\t.m_axi_arlock\t\t(elink_axi_arlock[1:0]), // Templated
+\t\t.m_axi_arcache\t\t(elink_axi_arcache[3:0]), // Templated
+\t\t.m_axi_arprot\t\t(elink_axi_arprot[2:0]), // Templated
+\t\t.m_axi_arqos\t\t(elink_axi_arqos[3:0]),\t // Templated
+\t\t.m_axi_arvalid\t\t(elink_axi_arvalid),\t // Templated
+\t\t.m_axi_rready\t\t(elink_axi_rready),\t // Templated
+\t\t.s_axi_arready\t\t(dv_axi_arready),\t // Templated
+\t\t.s_axi_awready\t\t(dv_axi_awready),\t // Templated
+\t\t.s_axi_bid\t\t(dv_axi_bid[IDW-1:0]),\t // Templated
+\t\t.s_axi_bresp\t\t(dv_axi_bresp[1:0]),\t // Templated
+\t\t.s_axi_bvalid\t\t(dv_axi_bvalid),\t // Templated
+\t\t.s_axi_rid\t\t(dv_axi_rid[IDW-1:0]),\t // Templated
+\t\t.s_axi_rdata\t\t(dv_axi_rdata[31:0]),\t // Templated
+\t\t.s_axi_rlast\t\t(dv_axi_rlast),\t\t // Templated
+\t\t.s_axi_rresp\t\t(dv_axi_rresp[1:0]),\t // Templated
+\t\t.s_axi_rvalid\t\t(dv_axi_rvalid),\t // Templated
+\t\t.s_axi_wready\t\t(dv_axi_wready),\t // Templated
+\t\t// Inputs
+\t\t.rxi_lclk_p\t\t(lclk_p),\t\t // Templated
+\t\t.rxi_lclk_n\t\t(lclk_n),\t\t // Templated
+\t\t.rxi_frame_p\t\t(frame_p),\t\t // Templated
+\t\t.rxi_frame_n\t\t(frame_n),\t\t // Templated
+\t\t.rxi_data_p\t\t(data_p[7:0]),\t\t // Templated
+\t\t.rxi_data_n\t\t(data_n[7:0]),\t\t // Templated
+\t\t.txi_wr_wait_p\t\t(wr_wait_p),\t\t // Templated
+\t\t.txi_wr_wait_n\t\t(wr_wait_n),\t\t // Templated
+\t\t.txi_rd_wait_p\t\t(rd_wait_p),\t\t // Templated
+\t\t.txi_rd_wait_n\t\t(rd_wait_n),\t\t // Templated
+\t\t.m_axi_awready\t\t(elink_axi_awready),\t // Templated
+\t\t.m_axi_wready\t\t(elink_axi_wready),\t // Templated
+\t\t.m_axi_bid\t\t(elink_axi_bid[IDW-1:0]), // Templated
+\t\t.m_axi_bresp\t\t(elink_axi_bresp[1:0]),\t // Templated
+\t\t.m_axi_bvalid\t\t(elink_axi_bvalid),\t // Templated
+\t\t.m_axi_arready\t\t(elink_axi_arready),\t // Templated
+\t\t.m_axi_rid\t\t(elink_axi_rid[IDW-1:0]), // Templated
+\t\t.m_axi_rdata\t\t({elink_axi_rdata[31:0],elink_axi_rdata[31:0]}), // Templated
+\t\t.m_axi_rresp\t\t(elink_axi_rresp[1:0]),\t // Templated
+\t\t.m_axi_rlast\t\t(elink_axi_rlast),\t // Templated
+\t\t.m_axi_rvalid\t\t(elink_axi_rvalid),\t // Templated
+\t\t.s_axi_arid\t\t(dv_axi_arid[IDW-1:0]),\t // Templated
+\t\t.s_axi_araddr\t\t(dv_axi_araddr[31:0]),\t // Templated
+\t\t.s_axi_arburst\t\t(dv_axi_arburst[1:0]),\t // Templated
+\t\t.s_axi_arcache\t\t(dv_axi_arcache[3:0]),\t // Templated
+\t\t.s_axi_arlock\t\t(dv_axi_arlock[1:0]),\t // Templated
+\t\t.s_axi_arlen\t\t(dv_axi_arlen[7:0]),\t // Templated
+\t\t.s_axi_arprot\t\t(dv_axi_arprot[2:0]),\t // Templated
+\t\t.s_axi_arqos\t\t(dv_axi_arqos[3:0]),\t // Templated
+\t\t.s_axi_arsize\t\t(dv_axi_arsize[2:0]),\t // Templated
+\t\t.s_axi_arvalid\t\t(dv_axi_arvalid),\t // Templated
+\t\t.s_axi_awid\t\t(dv_axi_awid[IDW-1:0]),\t // Templated
+\t\t.s_axi_awaddr\t\t(dv_axi_awaddr[31:0]),\t // Templated
+\t\t.s_axi_awburst\t\t(dv_axi_awburst[1:0]),\t // Templated
+\t\t.s_axi_awcache\t\t(dv_axi_awcache[3:0]),\t // Templated
+\t\t.s_axi_awlock\t\t(dv_axi_awlock[1:0]),\t // Templated
+\t\t.s_axi_awlen\t\t(dv_axi_awlen[7:0]),\t // Templated
+\t\t.s_axi_awprot\t\t(dv_axi_awprot[2:0]),\t // Templated
+\t\t.s_axi_awqos\t\t(dv_axi_awqos[3:0]),\t // Templated
+\t\t.s_axi_awsize\t\t(dv_axi_awsize[2:0]),\t // Templated
+\t\t.s_axi_awvalid\t\t(dv_axi_awvalid),\t // Templated
+\t\t.s_axi_bready\t\t(dv_axi_bready),\t // Templated
+\t\t.s_axi_rready\t\t(dv_axi_rready),\t // Templated
+\t\t.s_axi_wid\t\t(dv_axi_wid[IDW-1:0]),\t // Templated
+\t\t.s_axi_wdata\t\t(dv_axi_wdata[31:0]),\t // Templated
+\t\t.s_axi_wlast\t\t(dv_axi_wlast),\t\t // Templated
+\t\t.s_axi_wstrb\t\t(dv_axi_wstrb[3:0]),\t // Templated
+\t\t.s_axi_wvalid\t\t(dv_axi_wvalid));\t // Templated
+
+
+   wire emem_access;
+   wire emem_write;
+   wire [1:0] emem_datamode;
+   wire [3:0] emem_ctrlmode;
+   wire [AW-1:0] emem_dstaddr;
+   wire [DW-1:0] emem_data;
+   wire [AW-1:0] emem_srcaddr;
+
+   assign  emem_access           = esaxi_emwr_access | esaxi_emrq_access;
+    
+   assign  emem_write            = esaxi_emwr_access;
+
+   assign  emem_datamode[1:0] = esaxi_emwr_access ? esaxi_emwr_datamode[1:0] :
+\t  \t\t\t                       esaxi_emrq_datamode[1:0];
+
+   assign  emem_ctrlmode[3:0] = esaxi_emwr_access ? esaxi_emwr_ctrlmode[3:0] :
+\t  \t\t\t                       esaxi_emrq_ctrlmode[3:0];
+
+
+   assign  emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
+\t  \t\t\t                       esaxi_emrq_dstaddr[AW-1:0];
+
+   assign  emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
+\t  \t\t\t                       esaxi_emrq_dstaddr[AW-1:0];
+   
+   assign  emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
+\t  \t\t\t                       esaxi_emrq_dstaddr[AW-1:0];
+   
+   assign  emem_data[DW-1:0]    = esaxi_emwr_access ? esaxi_emwr_data[DW-1:0] :
+\t  \t\t\t                        esaxi_emrq_data[DW-1:0];
+
+   assign  emem_srcaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_srcaddr[AW-1:0] :
+\t  \t\t\t                       esaxi_emrq_srcaddr[AW-1:0];
+   
+   
+   
+   
+   
+   
+   /*ememory AUTO_TEMPLATE ( 
+                        // Outputs
+                        .\\(.*\\)_out       (esaxi_emrr_\\1[]),
+                        .\\(.*\\)_in        (emem_\\1[]),
+                        .wait_out\t  (emem_emrq_wait),
+                         );
+   */
+
+   ememory emem (.wait_in\t(1\'b0),       //only one read at a time, set to zero for no1
+\t\t .clk\t\t(s_axi_aclk),
+\t\t .datamode_out\t(),
+\t\t .ctrlmode_out\t(),
+\t\t .dstaddr_out\t(),
+                 .srcaddr_out\t(),
+\t\t .write_out\t(),
+\t\t // Inputs
+\t\t /*AUTOINST*/
+\t\t // Outputs
+\t\t .wait_out\t\t(emem_emrq_wait),\t // Templated
+\t\t .access_out\t\t(esaxi_emrr_access),\t // Templated
+\t\t .data_out\t\t(esaxi_emrr_data[DW-1:0]), // Templated
+\t\t // Inputs
+\t\t .reset\t\t\t(reset),
+\t\t .access_in\t\t(emem_access),\t\t // Templated
+\t\t .write_in\t\t(emem_write),\t\t // Templated
+\t\t .datamode_in\t\t(emem_datamode[1:0]),\t // Templated
+\t\t .ctrlmode_in\t\t(emem_ctrlmode[3:0]),\t // Templated
+\t\t .dstaddr_in\t\t(emem_dstaddr[AW-1:0]),\t // Templated
+\t\t .data_in\t\t(emem_data[DW-1:0]),\t // Templated
+\t\t .srcaddr_in\t\t(emem_srcaddr[AW-1:0]));\t // Templated
+   
+   //Transaction Monitor
+   reg [31:0] \t\tetime;  
+   always @ (posedge clkin or posedge reset)
+     if(reset)
+       etime[31:0] <= 32\'b0;
+     else
+       etime[31:0] <= etime[31:0]+1\'b1;
+
+   wire \t\titrace = 1\'b1;
+
+  /*emesh_monitor AUTO_TEMPLATE ( 
+                        // Outputs
+                        .txo_\\(.*\\)       (\\1[]),
+                        .rxi_\\(.*\\)       (\\1[]),  
+                        .rxo_\\(.*\\)       (\\1[]),
+                        .txi_\\(.*\\)       (\\1[]),  
+                        .s_\\(.*\\)         (dv_\\1[]),
+                        .emesh_\\(.*\\)     (@""(substring vl-cell-name  0 3)""_\\1[]),
+                        .m_axi_rdata\t  ({32\'b0,elink_axi_rdata[31:0]}), //restricted to slave width
+                        );
+   */
+
+
+   emesh_monitor #(.NAME(""stimulus"")) ext_monitor (.emesh_wait\t\t((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
+\t\t\t\t\t\t   .clk\t\t\t(m_axi_aclk),
+\t\t\t\t\t\t   /*AUTOINST*/
+\t\t\t\t\t\t   // Inputs
+\t\t\t\t\t\t   .reset\t\t(reset),
+\t\t\t\t\t\t   .itrace\t\t(itrace),
+\t\t\t\t\t\t   .etime\t\t(etime[31:0]),
+\t\t\t\t\t\t   .emesh_access\t(ext_access),\t // Templated
+\t\t\t\t\t\t   .emesh_write\t\t(ext_write),\t // Templated
+\t\t\t\t\t\t   .emesh_datamode\t(ext_datamode[1:0]), // Templated
+\t\t\t\t\t\t   .emesh_ctrlmode\t(ext_ctrlmode[3:0]), // Templated
+\t\t\t\t\t\t   .emesh_dstaddr\t(ext_dstaddr[AW-1:0]), // Templated
+\t\t\t\t\t\t   .emesh_data\t\t(ext_data[DW-1:0]), // Templated
+\t\t\t\t\t\t   .emesh_srcaddr\t(ext_srcaddr[AW-1:0])); // Templated
+   
+   emesh_monitor #(.NAME(""dut"")) dut_monitor (.emesh_wait\t(1\'b0),
+\t\t\t\t\t      .clk\t\t(s_axi_aclk),
+\t\t\t\t\t      /*AUTOINST*/
+\t\t\t\t\t      // Inputs
+\t\t\t\t\t      .reset\t\t(reset),
+\t\t\t\t\t      .itrace\t\t(itrace),
+\t\t\t\t\t      .etime\t\t(etime[31:0]),
+\t\t\t\t\t      .emesh_access\t(dut_access),\t // Templated
+\t\t\t\t\t      .emesh_write\t(dut_write),\t // Templated
+\t\t\t\t\t      .emesh_datamode\t(dut_datamode[1:0]), // Templated
+\t\t\t\t\t      .emesh_ctrlmode\t(dut_ctrlmode[3:0]), // Templated
+\t\t\t\t\t      .emesh_dstaddr\t(dut_dstaddr[AW-1:0]), // Templated
+\t\t\t\t\t      .emesh_data\t(dut_data[DW-1:0]), // Templated
+\t\t\t\t\t      .emesh_srcaddr\t(dut_srcaddr[AW-1:0])); // Templated
+
+endmodule // dv_elink
+// Local Variables:
+// verilog-library-directories:(""."" ""../hdl"" ""../../memory/hdl"")
+// End:
+
+/*
+ Copyright (C) 2014 Adapteva, Inc. 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+"
+"module memory_writemask(/*AUTOARG*/
+   // Outputs
+   we,
+   // Inputs
+   write, datamode, addr
+   );
+
+   input         write;   
+   input [1:0]   datamode;   
+   input [2:0]   addr;
+   output [7:0]  we;
+
+   reg [7:0] \t we;
+
+   //Write mask
+   always@*
+     casez({write, datamode[1:0],addr[2:0]})
+       //Byte
+       6'b100000 : we[7:0] = 8'b00000001;
+       6'b100001 : we[7:0] = 8'b00000010;
+       6'b100010 : we[7:0] = 8'b00000100;
+       6'b100011 : we[7:0] = 8'b00001000;
+       6'b100100 : we[7:0] = 8'b00010000;
+       6'b100101 : we[7:0] = 8'b00100000;
+       6'b100110 : we[7:0] = 8'b01000000;
+       6'b100111 : we[7:0] = 8'b10000000;
+       //Short
+       6'b10100? : we[7:0] = 8'b00000011;
+       6'b10101? : we[7:0] = 8'b00001100;
+       6'b10110? : we[7:0] = 8'b00110000;
+       6'b10111? : we[7:0] = 8'b11000000;
+       //Word
+       6'b1100?? : we[7:0] = 8'b00001111;
+       6'b1101?? : we[7:0] = 8'b11110000;       
+       //Double
+       6'b111??? : we[7:0] = 8'b11111111;
+       default   : we[7:0] = 8'b00000000;
+     endcase // casez ({write, datamode[1:0],addr[2:0]})
+   
+
+endmodule // memory_writemask
+
+/*
+ Copyright (C) 2014 Adapteva, Inc.
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+ 
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+ 
+ You should have received a copy of the GNU General Public License
+ along with this program (see the file COPYING).  If not, see
+ <http://www.gnu.org/licenses/>.
+ */
+
+
+"
+"module dv_emmu_tb;
+
+   reg clk;
+   
+   reg reset;
+   
+   reg \t      go;
+
+   //Clock
+   always
+     #10 clk = ~clk;
+   
+   initial
+     begin
+\t$display($time, "" << Starting the Simulation >>"");
+\t#0
+        clk                    = 1\'b0;    // at time 0
+\treset                  = 1\'b1;    // reset is active
+\t#100 
+\t  reset    = 1\'b0;    // at time 100 release reset
+\t#100
+\t  go       = 1\'b1;\t
+\t#10000\t  
+\t  $finish;
+     end\t
+
+   //Waveform dump
+   initial
+     begin
+\t$dumpfile(""test.vcd"");
+\t$dumpvars(0, dv_emmu);
+     end
+
+
+dv_emmu dv_emmu
+  (.clk (clk),
+   .reset (reset),
+   .go (go));
+endmodule
+"
+"/*############################################################################
+ * PROGRAMMABLE DELAY ELEMENT
+ *
+ * NOTE: NOT AVAILABLE IN HR BANKS!
+ * 
+ *############################################################################
+ */
+
+module ODELAYE2 (/*AUTOARG*/
+   // Outputs
+   CNTVALUEOUT, DATAOUT,
+   // Inputs
+   C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN,
+   REGRST
+   );
+
+    parameter CINVCTRL_SEL              = ""FALSE"";
+    parameter DELAY_SRC                 = ""ODATAIN"";
+    parameter HIGH_PERFORMANCE_MODE     = ""FALSE"";
+    parameter [0:0] IS_C_INVERTED       = 1\'b0;
+    parameter [0:0] IS_ODATAIN_INVERTED = 1\'b0;
+    parameter ODELAY_TYPE               = ""FIXED"";
+    parameter integer ODELAY_VALUE      = 0;
+    parameter PIPE_SEL                  = ""FALSE"";
+    parameter real REFCLK_FREQUENCY     = 200.0;
+    parameter SIGNAL_PATTERN            = ""DATA"";
+
+   input \t C;           //clock for VARIABLE, VAR_LOAD,VAR_LOAD_PIPE mode
+   input \t REGRST;      //reset pipeline reg to all zeroes
+   input \t LD;          //loads programmed values depending on ""mode""     
+   input \t CE;          //enable encrement/decrement function
+   input \t INC;         //increment/decrement tap delays
+   input \t CINVCTRL;    //dynamically inverts clock polarity
+   input [4:0] \t CNTVALUEIN;  //input value from FPGA logic
+   input \t CLKIN;       //clk from I/O clock mux??
+   input \t ODATAIN;     //data from OSERDESE2 output
+   output \t DATAOUT;     //delayed data to pin
+   input \t LDPIPEEN;    //enables pipeline reg??
+   output [4:0]  CNTVALUEOUT; //current value for FPGA logic
+
+   
+   assign DATAOUT=ODATAIN;
+      
+endmodule // ODELAYE2
+"
+"/*
+ ########################################################################
+ 
+ ########################################################################
+ */
+
+module ecfg_if (/*AUTOARG*/
+   // Outputs
+   mi_mmu_en, mi_dma_en, mi_cfg_en, mi_we, mi_addr, mi_din,
+   access_out, packet_out,
+   // Inputs
+   clk, reset, access_in, packet_in, mi_dout0, mi_dout1, mi_dout2,
+   mi_dout3, wait_in
+   );
+
+   parameter RX     = 0;     //0,1
+   parameter PW     = 104;
+   parameter AW     = 32;
+   parameter DW     = 32;
+   parameter ID     = 12'h810;
+   
+   /********************************/
+   /*Clocks/reset                  */
+   /********************************/  
+   input             clk;  
+   input             reset;
+
+   /********************************/
+   /*Incoming Packet               */
+   /********************************/  
+   input \t     access_in;
+   input [PW-1:0]    packet_in;
+   
+   /********************************/
+   /* Register Interface           */
+   /********************************/
+   output \t mi_mmu_en;     
+   output \t mi_dma_en;
+   output \t mi_cfg_en;      
+   output        mi_we;  
+   output [14:0] mi_addr;
+   output [63:0] mi_din;   
+   input [63:0]  mi_dout0;
+   input [63:0]  mi_dout1;
+   input [63:0]  mi_dout2;
+   input [63:0]  mi_dout3;
+
+   /********************************/
+   /* Outgoing Packet              */
+   /********************************/
+   output \t     access_out;
+   output [PW-1:0]   packet_out;
+   input \t     wait_in;       //incoming wait 
+   
+   //wires
+   wire [31:0] \t dstaddr;
+   wire [31:0] \t data;   
+   wire [31:0]   srcaddr;
+   wire [1:0] \t datamode;
+   wire [3:0] \t ctrlmode;
+   wire [63:0] \t mi_dout_mux;
+   wire \t mi_rd;
+   wire \t access_forward;
+   wire \t rxsel;
+   wire \t mi_en;
+   
+   //regs;
+   reg \t\t access_out;   
+   reg [31:0] \t dstaddr_reg;
+   reg [31:0] \t srcaddr_reg;
+   reg [1:0] \t datamode_reg;
+   reg [3:0] \t ctrlmode_reg;
+   reg \t\t write_reg;
+   reg \t\t readback_reg;   
+   reg [31:0] \t data_reg;
+   wire [31:0] \t data_out;
+   
+   //parameter didn't seem to work
+   assign \t rxsel = RX;   
+
+   //splicing packet
+   packet2emesh p2e (.access_out   (),
+\t\t     .write_out\t   (write),
+\t\t     .datamode_out (datamode[1:0] ),
+\t\t     .ctrlmode_out (ctrlmode[3:0]),
+\t\t     .dstaddr_out  (dstaddr[31:0]),
+\t\t     .data_out\t   (data[31:0]),
+\t\t     .srcaddr_out  (srcaddr[31:0]),
+\t\t     .packet_in\t   (packet_in[PW-1:0])
+\t\t    );
+
+   //ENABLE SIGNALS
+   assign mi_match   = access_in & (dstaddr[31:20]==ID);
+    
+   //config select (group 2 and 3)
+   assign mi_cfg_en = mi_match & 
+\t\t      (dstaddr[19:16]==4'hF) &
+\t\t      (dstaddr[10:8]=={2'b01,rxsel});
+   
+
+   //dma select (group 5)
+   assign mi_dma_en = mi_match &
+\t\t      (dstaddr[19:16]==4'hF) & 
+\t\t      (dstaddr[10:8]==3'h5)  & 
+\t\t      (dstaddr[5]==rxsel);
+   
+
+   //mmu select
+   assign mi_mmu_en = mi_match & 
+\t\t      (dstaddr[19:16]==4'hE) &
+\t\t      (dstaddr[15]==rxsel);
+
+
+   //read/write indicator
+   assign mi_en = (mi_mmu_en | mi_cfg_en | mi_dma_en);   
+   assign mi_rd = ~write & mi_en;   
+   assign mi_we = write  & mi_en;
+   
+   //signal to carry transaction from ETX to ERX block through fifo_cdc
+   assign mi_rx_en = mi_match & 
+\t\t     ((dstaddr[19:16]==4'hE) | (dstaddr[19:16]==4'hF)) &  
+\t\t     ~mi_en;
+      
+   //ADDR
+   assign mi_addr[14:0] = dstaddr[14:0];
+   
+   //DIN
+   assign mi_din[63:0]  = {srcaddr[31:0], data[31:0]};
+   
+   //READBACK MUX (inputs should be zero if not used)
+   assign mi_dout_mux[63:0] = mi_dout0[63:0] |
+\t\t\t      mi_dout1[63:0] |
+\t\t\t      mi_dout2[63:0] |
+\t\t\t      mi_dout3[63:0];
+     
+
+   //Access out packet  
+   assign access_forward = (mi_rx_en | mi_rd);
+
+   always @ (posedge  clk)
+     if(reset)
+       access_out   <= 1'b0;
+     else if(~wait_in)
+       access_out   <= access_forward;
+   
+   always @ (posedge clk)
+     if(~wait_in)
+       begin
+\t  readback_reg      <= mi_rd;
+\t  write_reg         <= (mi_rx_en & write) | mi_rd;\t  
+\t  datamode_reg[1:0] <= datamode[1:0];
+\t  ctrlmode_reg[3:0] <= ctrlmode[3:0];
+\t  dstaddr_reg[31:0] <= mi_rx_en ? dstaddr[31:0] : srcaddr[31:0];
+\t  data_reg[31:0]    <= data[31:0];\t  
+\t  srcaddr_reg[31:0] <= mi_rx_en ? srcaddr[31:0] : mi_dout_mux[63:32];
+       end
+   
+   assign data_out[31:0] = readback_reg ? mi_dout_mux[31:0] : data_reg[31:0];
+   
+   //Create packet
+   emesh2packet e2p (.packet_out\t(packet_out[PW-1:0]),
+\t\t     .access_in\t\t(1'b1),
+\t\t     .write_in\t\t(write_reg),
+\t\t     .datamode_in        (datamode_reg[1:0]),
+\t\t     .ctrlmode_in   \t(ctrlmode_reg[3:0]),
+\t\t     .dstaddr_in   \t(dstaddr_reg[AW-1:0]),
+\t\t     .data_in\t\t(data_out[31:0]),
+\t\t     .srcaddr_in        (srcaddr_reg[AW-1:0])
+\t\t     );
+   
+   
+endmodule // ecfg_if
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"/*###########################################################################
+ *#Clock buffer with built in divider
+ *########################################################################### 
+ *
+ * Division ratios: 1,2,3,4,5,6,7,8, and bypass division ratings
+ * 
+ * BUFRs can drive:
+ * -I/O logic
+ * -logic resources
+ * 
+ * BUFRs can be driven by:
+ * -SRCCs and MRCCs in the same clock region
+ * -MRCCs in an adjacent clock region using BUFMRs
+ * -MMCMs clock outputs 0-3 driving the HPC in the same clock region
+ * -MMCMs clock outputs 0-3
+ * -General interconnect 
+ * 
+ * Input to Output Delay (Zynq7010/7020): 1.04/0.80/0.64 (-1/-2/-3 grade) 
+ * 
+ */ 
+
+module BUFR (/*AUTOARG*/
+   // Outputs
+   O,
+   // Inputs
+   I, CE, CLR
+   );
+
+   parameter BUFR_DIVIDE=4;
+   parameter SIM_DEVICE=0;
+
+   input I;   //clock input
+   input CE;  //async output clock enable
+   input CLR; //async clear for divider logic
+   output O;  //clock output
+
+   //assign O=I & CE & ~CLR;
+
+   //TODO: need to paraemtrize this!!!   
+   clock_divider clock_divider (
+\t\t\t\t// Outputs
+\t\t\t\t.clkout\t\t(O),
+\t\t\t\t// Inputs
+\t\t\t\t.clkin\t\t(I),
+\t\t\t\t.divcfg\t\t(4\'b0010),//div4
+\t\t\t\t.reset\t\t(CLR)
+\t\t\t\t);
+   
+   
+endmodule // IBUFDS
+// Local Variables:
+// verilog-library-directories:(""../../common/hdl"")
+// End:
+"
+"`include ""elink_constants.v""
+
+module etx_io (/*AUTOARG*/
+   // Outputs
+   txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
+   txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
+   // Inputs
+   reset, etx90_reset, tx_lclk, tx_lclk90, txi_wr_wait_p, txi_wr_wait_n,
+   txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access, tx_burst
+   );
+
+   parameter IOSTD_ELINK = ""LVDS_25"";
+   parameter PW          = 104;
+   parameter ETYPE       = 1;//0=parallella
+                             //1=ephycard     
+   //###########
+   //# reset, clocks
+   //##########
+   input        reset;               //reset for io  
+   input \ttx_lclk;\t     // fast clock for io
+   input \ttx_lclk90;           // fast 90deg shifted lclk   
+   input \tetx90_reset;
+   
+   //###########
+   //# eLink pins
+   //###########
+   output \ttxo_lclk_p,   txo_lclk_n;     // tx clock output
+   output \ttxo_frame_p, txo_frame_n;     // tx frame signal
+   output [7:0] txo_data_p, txo_data_n;       // tx data (dual data rate)
+   input \ttxi_wr_wait_p,txi_wr_wait_n;  // tx write pushback
+   input \ttxi_rd_wait_p, txi_rd_wait_n; // tx read pushback
+
+   //#############
+   //# Fabric interface
+   //#############
+   input [PW-1:0] tx_packet;
+   input          tx_access;
+   input          tx_burst;
+   output \t  tx_io_wait;   
+   output \t  tx_wr_wait;
+   output \t  tx_rd_wait;
+   
+   
+   //############
+   //# REGS
+   //############
+   reg [7:0] \t  tx_pointer;   
+   reg [15:0] \t  tx_data16;
+   reg \t\t  tx_access_reg;
+   reg \t\t  tx_frame;
+   reg \t\t  tx_io_wait_reg;
+   reg \t\t  io_reset;
+   reg \t\t  io_reset_in;
+   reg [PW-1:0]   tx_packet_reg;
+   reg [63:0] \t  tx_double;
+   reg [2:0] \t  tx_state_reg;
+   reg [2:0] \t  tx_state;
+   //############
+   //# WIRES
+   //############
+   wire \t  new_tran;
+   wire \t  access;
+   wire \t  write;
+   wire [1:0] \t  datamode;   
+   wire [3:0]\t  ctrlmode;
+   wire [31:0] \t  dstaddr;
+   wire [31:0] \t  data;
+   wire [31:0] \t  srcaddr;
+   wire [7:0] \t  txo_data;
+   wire \t  txo_frame;   
+   wire \t  txo_lclk90;
+   reg \t\t  tx_io_wait;
+
+   //#############################
+   //# Transmit state machine
+   //#############################  
+  
+`define IDLE    3\'b000
+`define CYCLE1  3\'b001
+`define CYCLE2  3\'b010
+`define CYCLE3  3\'b011
+`define CYCLE4  3\'b100
+`define CYCLE5  3\'b101
+`define CYCLE6  3\'b110
+`define CYCLE7  3\'b111
+     
+always @ (posedge tx_lclk)
+  if(reset)
+    tx_state[2:0] <= `IDLE;
+  else
+    case (tx_state[2:0])
+      `IDLE   : tx_state[2:0] <= tx_access ? `CYCLE1 : `IDLE;
+      `CYCLE1 : tx_state[2:0] <= `CYCLE2;
+      `CYCLE2 : tx_state[2:0] <= `CYCLE3;
+      `CYCLE3 : tx_state[2:0] <= `CYCLE4;
+      `CYCLE4 : tx_state[2:0] <= `CYCLE5;
+      `CYCLE5 : tx_state[2:0] <= `CYCLE6;
+      `CYCLE6 : tx_state[2:0] <= `CYCLE7;
+      `CYCLE7 : tx_state[2:0] <= tx_burst ? `CYCLE4 : `IDLE;\t
+    endcase // case (tx_state)   
+   
+   assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
+
+ 
+   //Creating wait pulse for slow clock domain
+   always @ (posedge tx_lclk)
+     if(reset | ~tx_access)
+       tx_io_wait <= 1\'b0;
+     else if ((tx_state[2:0] ==`CYCLE4) & ~tx_burst)
+       tx_io_wait <= 1\'b1;
+     else if (tx_state[2:0]==`CYCLE7)
+       tx_io_wait <= 1\'b0;
+  
+   //Create frame signal for output
+   always @ (posedge tx_lclk)
+     begin
+\ttx_state_reg[2:0]     <= tx_state[2:0];
+\ttx_frame              <= |(tx_state_reg[2:0]);
+     end
+
+   //#############################
+   //# 2 CYCLE PACKET PIPELINE
+   //#############################  
+   always @ (posedge tx_lclk)
+     if (tx_access)
+       tx_packet_reg[PW-1:0] <= tx_packet[PW-1:0];
+
+    packet2emesh p2e (.access_out\t(access),
+\t\t      .write_out\t(write),
+\t\t      .datamode_out\t(datamode[1:0]),
+\t\t      .ctrlmode_out\t(ctrlmode[3:0]),
+\t\t      .dstaddr_out\t(dstaddr[31:0]),
+\t\t      .data_out\t\t(data[31:0]),
+\t\t      .srcaddr_out\t(srcaddr[31:0]),
+\t\t      .packet_in\t(tx_packet_reg[PW-1:0]));
+ 
+   always @ (posedge tx_lclk)
+     if (tx_new_frame)
+       tx_double[63:0] <= {16\'b0,//16
+\t\t\t   ~write,7\'b0,ctrlmode[3:0],//12
+\t\t\t   dstaddr[31:0],datamode[1:0],write,access};//36
+     else if(tx_state[2:0]==`CYCLE4)
+       tx_double[63:0] <= {data[31:0],srcaddr[31:0]};
+  
+   //#############################
+   //# SELECTING DATA FOR TRANSMIT
+   //#############################  
+   
+   always @ (posedge tx_lclk)
+     case(tx_state_reg[2:0])
+       //Cycle1
+       3\'b001: tx_data16[15:0]  <= tx_double[47:32];       
+       //Cycle2
+       3\'b010: tx_data16[15:0]  <= tx_double[31:16];       
+       //Cycle3
+       3\'b011: tx_data16[15:0]  <= tx_double[15:0];       
+       //Cycle4\t\t\t\t      
+       3\'b100: tx_data16[15:0]  <= tx_double[63:48];       
+       //Cycle5
+       3\'b101: tx_data16[15:0]  <= tx_double[47:32];       
+       //Cycle6
+       3\'b110: tx_data16[15:0]  <= tx_double[31:16];       
+       //Cycle7
+       3\'b111: tx_data16[15:0]  <= tx_double[15:0];       
+       default  tx_data16[15:0] <= 16\'b0;
+     endcase // case (tx_state[2:0])
+                
+   //#############################
+   //# RESET SYNCHRONIZER
+   //#############################       
+   always @ (posedge tx_lclk)// or posedge reset)
+     if(reset)
+       begin
+\t  io_reset_in   <= 1\'b1;
+\t  io_reset      <= 1\'b1;
+       end
+     else
+       begin
+\t  io_reset_in  <= 1\'b0;
+\t  io_reset     <= io_reset_in; 
+       end
+
+     
+   //#############################
+   //# ODDR DRIVERS
+   //#############################  
+
+   //DATA
+   genvar        i;
+   generate for(i=0; i<8; i=i+1)
+     begin : gen_oddr
+\tODDR #(.DDR_CLK_EDGE  (""SAME_EDGE""))
+\toddr_data (
+\t\t   .Q  (txo_data[i]),
+\t\t   .C  (tx_lclk),
+\t\t   .CE (1\'b1),
+\t\t   .D1 (tx_data16[i+8]),
+\t\t   .D2 (tx_data16[i]),
+\t\t   .R  (1\'b0),
+\t\t   .S  (1\'b0)
+\t\t   );
+     end
+     endgenerate
+
+   //FRAME
+   ODDR #(.DDR_CLK_EDGE  (""SAME_EDGE""))
+   oddr_frame (
+\t      .Q  (txo_frame),
+\t      .C  (tx_lclk),
+\t      .CE (1\'b1),
+\t      .D1 (tx_frame),
+\t      .D2 (tx_frame),
+\t      .R  (io_reset), 
+\t      .S  (1\'b0)
+\t      );
+   
+   //LCLK
+   ODDR #(.DDR_CLK_EDGE  (""SAME_EDGE""),.SRTYPE(""SYNC""))
+   oddr_lclk (
+\t      .Q  (txo_lclk90),
+\t      .C  (tx_lclk90),
+\t      .CE (1\'b1),
+\t      .D1 (1\'b1),
+\t      .D2 (1\'b0),
+\t      .R  (etx90_reset),
+\t      .S  (1\'b0)
+\t      );
+\t\t  
+   //##############################
+   //# OUTPUT BUFFERS
+   //##############################
+
+   OBUFDS obufds_data[7:0] (
+\t\t\t     .O   (txo_data_p[7:0]),
+\t\t\t     .OB  (txo_data_n[7:0]),
+\t\t\t     .I   (txo_data[7:0])
+\t\t\t     );
+   
+   OBUFDS obufds_frame ( .O   (txo_frame_p),
+\t\t\t .OB  (txo_frame_n),
+\t\t\t .I   (txo_frame)
+\t\t\t );
+
+   OBUFDS obufds_lclk ( .O   (txo_lclk_p),
+\t\t\t.OB  (txo_lclk_n),
+\t\t\t.I   (txo_lclk90)
+\t\t\t);
+   
+   //################################
+   //# Wait Input Buffers
+   //################################
+
+   generate
+      if(ETYPE==1)
+\tbegin
+\t   assign tx_wr_wait = txi_wr_wait_p;
+\tend
+      else if (ETYPE==0)
+\tbegin
+\t   IBUFDS
+\t     #(.DIFF_TERM  (""TRUE""),     // Differential termination
+\t       .IOSTANDARD (IOSTD_ELINK))
+\t   ibufds_wrwait
+\t     (.I     (txi_wr_wait_p),
+\t      .IB    (txi_wr_wait_n),
+\t      .O     (tx_wr_wait));\t 
+\tend
+   endgenerate
+   
+   
+//TODO: Come up with cleaner defines for this
+//Parallella and other platforms...   
+`ifdef TODO
+  IBUFDS
+     #(.DIFF_TERM  (""TRUE""),     // Differential termination
+       .IOSTANDARD (IOSTD_ELINK))
+      ibufds_rdwait
+     (.I     (txi_rd_wait_p),
+      .IB    (txi_rd_wait_n),
+      .O     (tx_rd_wait));
+`else
+   //On Parallella this signal comes in single-ended
+   assign tx_rd_wait = txi_rd_wait_p;
+`endif
+   
+endmodule // etx_io
+// Local Variables:
+// verilog-library-directories:(""."" ""../../emesh/hdl"")
+// End:
+
+
+/*
+  Copyright (C) 2014 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+  Contributed by Gunnar Hillerstrom
+ 
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"/*
+ ########################################################################
+ MASTER ENABLE, CLOCKS, CHIP-ID
+ ######################################################################## 
+ */
+
+`include ""elink_regmap.v""
+
+module ecfg_elink (/*AUTOARG*/
+   // Outputs
+   txwr_gated_access, elink_en, clk_config, e_chipid,
+   // Inputs
+   txwr_access, txwr_packet, clk, reset
+   );
+
+   parameter RFAW             = 6;     // 32 registers for now
+   parameter PW               = 104;   // 32 registers for now
+   parameter ID               = 12\'h000;
+   parameter DEFAULT_CHIPID   = 12\'h808;
+   
+   /******************************/
+   /*REGISTER ACCESS             */
+   /******************************/
+   input \t  txwr_access;
+   input [PW-1:0] txwr_packet;
+
+   /******************************/
+   /*FILTERED WRITE FOR TX FIFO  */
+   /******************************/
+   output \t  txwr_gated_access;
+
+   /******************************/
+   /*Clock/reset                 */
+   /******************************/
+   input \t  clk;   
+   input \t  reset;         // POR ""hard reset""
+
+   /******************************/
+   /*Outputs                     */
+   /******************************/
+   output \t elink_en;         // elink master enable
+   output [15:0] clk_config;       // clock settings (for pll)
+   output [11:0] e_chipid;         // chip-id for Epiphany   
+   
+   /*------------------------CODE BODY---------------------------------------*/
+   
+   //registers
+   reg          ecfg_reset_reg;
+   reg [15:0] \tecfg_clk_reg;
+   reg [11:0] \tecfg_chipid_reg;
+   reg [31:0] \tmi_dout;
+   
+   //wires
+   wire \tecfg_read;
+   wire \tecfg_write;
+   wire \tecfg_clk_write;
+   wire \tecfg_chipid_write;
+   wire \tecfg_reset_write;
+   wire \tmi_en;
+   wire [31:0] \tmi_addr;
+   wire [31:0] \tmi_din;
+
+   packet2emesh pe2 (
+\t\t     // Outputs
+\t\t     .access_out\t(),
+\t\t     .write_out\t\t(mi_we),
+\t\t     .datamode_out\t(),
+\t\t     .ctrlmode_out\t(),
+\t\t     .dstaddr_out\t(mi_addr[31:0]),
+\t\t     .data_out\t\t(mi_din[31:0]),
+\t\t     .srcaddr_out\t(),
+\t\t     // Inputs
+\t\t     .packet_in\t\t(txwr_packet[PW-1:0])
+\t\t     );   
+         
+   /*****************************/
+   /*ADDRESS DECODE LOGIC       */
+   /*****************************/
+   assign mi_en = txwr_access & 
+\t\t  (mi_addr[31:20]==ID) &
+\t\t  (mi_addr[10:8]==3\'h2);
+   
+
+   //read/write decode
+   assign ecfg_write  = mi_en &  mi_we;
+   assign ecfg_read   = mi_en & ~mi_we;   
+
+   //Config write enables
+   assign ecfg_reset_write    = ecfg_write & (mi_addr[RFAW+1:2]==`E_RESET);
+   assign ecfg_clk_write      = ecfg_write & (mi_addr[RFAW+1:2]==`E_CLK);
+   assign ecfg_chipid_write   = ecfg_write & (mi_addr[RFAW+1:2]==`E_CHIPID);
+   
+   /*****************************/
+   /*FILTER ACCESS              */
+   /*****************************/
+   assign \ttxwr_gated_access =  txwr_access & ~(ecfg_reset_write | 
+\t\t\t\t\t\t   ecfg_clk_write   |
+                                                   ecfg_chipid_write);
+   
+   //###########################
+   //# RESET REG
+   //###########################
+    always @ (posedge clk)
+      if(reset)
+\tecfg_reset_reg <= 1\'b0;         
+      else if (ecfg_reset_write)
+\tecfg_reset_reg <= mi_din[0];  
+
+   assign elink_en    = ~ecfg_reset_reg;
+     
+   //###########################
+   //# CCLK/LCLK (PLL)
+   //###########################
+    always @ (posedge clk)
+     if(reset)
+       ecfg_clk_reg[15:0] <= 16\'h573;//all clocks on at lowest speed   
+     else if (ecfg_clk_write)
+       ecfg_clk_reg[15:0] <= mi_din[15:0];
+
+   assign clk_config[15:0] = ecfg_clk_reg[15:0];
+
+   //###########################
+   //# CHIPID
+   //###########################
+   always @ (posedge clk)
+     if(reset)
+       ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
+     else if (ecfg_chipid_write)
+       ecfg_chipid_reg[11:0] <= mi_din[11:0];   
+   
+   assign e_chipid[11:0]=ecfg_chipid_reg[5:2];   
+    
+endmodule // ecfg_elink
+
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+"
+"/*64 bit wide byte addressable memory*/
+module ememory(/*AUTOARG*/
+   // Outputs
+   wait_out, access_out, packet_out,
+   // Inputs
+   clk, reset, access_in, packet_in, wait_in
+   );
+
+   parameter DW  = 32;   
+   parameter AW  = 32;   
+   parameter MAW = 10;
+   parameter PW  = 104;
+   
+   //Basic Interface
+   input            clk;
+   input \t    reset;  
+
+   //incoming read/write
+   input \t    access_in;
+   input [PW-1:0]   packet_in;      
+   output \t    wait_out;   //pushback
+     
+   //back to mesh (readback data)
+   output \t    access_out;
+   output [PW-1:0]  packet_out;        
+   input \t    wait_in;   //pushback
+
+   wire [MAW-1:0]   addr;
+   wire [63:0]      din;
+   wire [63:0] \t    dout;
+   wire \t    en; 
+   wire \t    mem_rd;
+   wire \t    mem_wr;
+   reg [7:0] \t    wen;
+
+   //State
+   reg \t\t    access_out;   
+   reg \t\t    write_out;   
+   reg [1:0] \t    datamode_out;
+   reg [3:0] \t    ctrlmode_out;   
+   reg [AW-1:0]     dstaddr_out;   
+
+   wire [AW-1:0]    srcaddr_out;
+   wire [AW-1:0]    data_out;   
+   reg \t\t    hilo_sel;
+
+   wire \t    write_in;   
+   wire [1:0] \t    datamode_in;
+   wire [3:0] \t    ctrlmode_in;   
+   wire [AW-1:0]    dstaddr_in;
+   wire [DW-1:0]    data_in;   
+   wire [AW-1:0]    srcaddr_in;   
+
+   packet2emesh p2e (
+\t\t     .access_out\t(),
+\t\t     .write_out\t\t(write_in),
+\t\t     .datamode_out\t(datamode_in[1:0]),
+\t\t     .ctrlmode_out\t(ctrlmode_in[3:0]),
+\t\t     .dstaddr_out\t(dstaddr_in[AW-1:0]),
+\t\t     .data_out\t\t(data_in[DW-1:0]),
+\t\t     .srcaddr_out\t(srcaddr_in[AW-1:0]),
+\t\t     .packet_in\t\t(packet_in[PW-1:0])
+\t\t     );
+   
+   
+   //Access-in
+   assign mem_rd = (access_in & ~write_in & ~wait_in);
+   assign mem_wr = (access_in & write_in );
+   
+   assign en =  mem_rd | mem_wr;
+
+   //Pushback Circuit (pass through problems?)
+   assign wait_out = access_in & wait_in;
+   
+   //Address-in (shifted by three bits, 64 bit wide memory)
+   assign addr[MAW-1:0] = dstaddr_in[MAW+2:3];     
+
+   //Data-in (hardoded width)
+   assign din[63:0] =(datamode_in[1:0]==2\'b11) ? {srcaddr_in[31:0],data_in[31:0]}:
+\t\t                                 {data_in[31:0],data_in[31:0]};
+   //Write mask
+   always@*
+     casez({write_in, datamode_in[1:0],dstaddr_in[2:0]})
+       //Byte
+       6\'b100000 : wen[7:0] = 8\'b00000001;
+       6\'b100001 : wen[7:0] = 8\'b00000010;
+       6\'b100010 : wen[7:0] = 8\'b00000100;
+       6\'b100011 : wen[7:0] = 8\'b00001000;
+       6\'b100100 : wen[7:0] = 8\'b00010000;
+       6\'b100101 : wen[7:0] = 8\'b00100000;
+       6\'b100110 : wen[7:0] = 8\'b01000000;
+       6\'b100111 : wen[7:0] = 8\'b10000000;
+       //Short
+       6\'b10100? : wen[7:0] = 8\'b00000011;
+       6\'b10101? : wen[7:0] = 8\'b00001100;
+       6\'b10110? : wen[7:0] = 8\'b00110000;
+       6\'b10111? : wen[7:0] = 8\'b11000000;
+       //Word
+       6\'b1100?? : wen[7:0] = 8\'b00001111;
+       6\'b1101?? : wen[7:0] = 8\'b11110000;       
+       //Double
+       6\'b111??? : wen[7:0] = 8\'b11111111;
+       default   : wen[7:0] = 8\'b00000000;
+     endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
+
+   //Single ported memory
+   defparam mem.DW=2*DW;//TODO: really fixed to 64 bits
+   defparam mem.AW=MAW;\t\t   
+   memory_sp mem(
+\t\t // Inputs
+\t\t .clk\t(clk),
+\t\t .en\t(en),
+\t\t .wen\t(wen[7:0]),
+\t\t .addr\t(addr[MAW-1:0]),
+\t\t .din\t(din[63:0]),
+\t\t .dout\t(dout[63:0])
+\t\t );
+
+   //Outgoing transaction     
+   always @ (posedge  clk)
+     access_out                    <= mem_rd;
+                 
+   //Other emesh signals ""dataload""
+   always @ (posedge clk)
+     if(mem_rd)   
+       begin
+\t  write_out           <= 1\'b1;
+          hilo_sel            <= dstaddr_in[2];
+\t  datamode_out[1:0]   <= datamode_in[1:0];
+\t  ctrlmode_out[3:0]   <= ctrlmode_in[3:0];                  
+          dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
+       end
+
+
+   assign srcaddr_out[AW-1:0] = (datamode_out[1:0]==2\'b11) ? dout[63:32] :
+\t\t\t\t                             32\'b0;
+   assign data_out[DW-1:0]     = hilo_sel ? dout[63:32] :
+\t\t\t\t            dout[31:0]; 
+   
+   //Concatenate
+   emesh2packet e2p (.packet_out\t(packet_out[PW-1:0]),
+\t\t     .access_in\t\t(access_out),
+\t\t     .write_in\t\t(write_out),
+\t\t     .datamode_in\t(datamode_out[1:0]),
+\t\t     .ctrlmode_in\t(ctrlmode_out[3:0]),
+\t\t     .dstaddr_in\t(dstaddr_out[AW-1:0]),
+\t\t     .data_in\t\t(data_out[DW-1:0]),
+\t\t     .srcaddr_in\t(srcaddr_out[AW-1:0])
+\t\t     );
+   
+\t\t    
+endmodule // emesh_memory
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+
+/*
+ Copyright (C) 2014 Adapteva, Inc.
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+ 
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+ 
+ You should have received a copy of the GNU General Public License
+ along with this program (see the file COPYING).  If not, see
+ <http://www.gnu.org/licenses/>.
+ */
+
+
+"
+"`include ""elink_regmap.v""
+
+module etx_protocol (/*AUTOARG*/
+   // Outputs
+   etx_rd_wait, etx_wr_wait, tx_packet, tx_access, tx_burst,
+   // Inputs
+   reset, clk, etx_access, etx_packet, tx_enable, gpio_data,
+   gpio_enable, tx_io_wait, tx_rd_wait, tx_wr_wait
+   );
+
+   parameter PW = 104;
+   parameter AW = 32;   
+   parameter DW = 32;
+   parameter ID = 12\'h000;
+   
+   //Clock/reset
+   input \t  reset;
+   input          clk;
+
+   //System side
+   input          etx_access;
+   input [PW-1:0] etx_packet;  
+
+   //Pushback signals
+   output         etx_rd_wait;
+   output         etx_wr_wait;
+
+   //Enble transmit
+   input \t  tx_enable;   //transmit enable
+   input [8:0]    gpio_data;   //TODO
+   input    \t  gpio_enable; //TODO
+   
+   //Interface to IO
+   output [PW-1:0] tx_packet;
+   output          tx_access;
+   output          tx_burst;
+   input           tx_io_wait;  
+   input           tx_rd_wait;  // The wait signals are passed through
+   input           tx_wr_wait;  // to the emesh interfaces
+
+   //###################################################################
+   //# Local regs & wires
+   //###################################################################
+   reg \t\t   tx_burst;
+   
+   reg           tx_access;
+   reg [PW-1:0]  tx_packet; 
+   reg\t\t tx_rd_wait_sync;
+   reg \t\t tx_wr_wait_sync;
+   wire \t etx_write;
+   wire [1:0] \t etx_datamode;
+   wire [3:0]\t etx_ctrlmode;
+   wire [AW-1:0] etx_dstaddr;
+   wire [DW-1:0] etx_data;
+   wire \t last_write;
+   wire [1:0] \t last_datamode;
+   wire [3:0]\t last_ctrlmode;
+   wire [AW-1:0] last_dstaddr;   
+   wire \t etx_valid;
+   reg           etx_io_wait;
+   wire \t burst_match;
+   wire \t burst_type_match;
+   wire [31:0] \t burst_addr;
+   wire \t burst_addr_match;
+   
+   reg \t\t etx_rd_wait_reg;
+   reg \t\t etx_wr_wait_reg;
+
+   //packet to emesh bundle
+   packet2emesh p2m0 (.access_out\t(),
+\t\t      .write_out\t(etx_write),
+\t\t      .datamode_out\t(etx_datamode[1:0]),
+\t\t      .ctrlmode_out\t(etx_ctrlmode[3:0]),
+\t\t      .dstaddr_out\t(etx_dstaddr[31:0]),
+\t\t      .data_out\t\t(),
+\t\t      .srcaddr_out\t(),
+\t\t      .packet_in\t(etx_packet[PW-1:0]));//input
+
+   //Only set valid if not wait and 
+   assign etx_valid = (tx_enable & 
+\t\t       etx_access & 
+\t\t       ~((etx_dstaddr[31:20]==ID) & (etx_dstaddr[19:16]!=`EGROUP_RR)) &
+\t\t      ((etx_write & ~tx_wr_wait_sync) | (~etx_write & ~tx_rd_wait_sync))
+\t\t       );
+   
+   //Prepare transaction / with burst
+   always @ (posedge clk)
+     if(reset)
+       begin
+\t  tx_packet[PW-1:0] <= \'b0;
+\t  tx_access         <= 1\'b0;
+       end
+   else if(~tx_io_wait)
+     begin
+\ttx_packet[PW-1:0] <= etx_packet[PW-1:0];
+\ttx_access         <= etx_valid;
+       end
+
+   
+   always @ (posedge clk)
+     if(reset)
+       tx_burst <= 1\'b0;   
+     else       
+       tx_burst          <= (etx_write                  & //write 
+\t       \t            (etx_datamode[1:0]==2\'b11) & //double only
+\t\t\t    burst_type_match           & //same types
+\t\t\t    burst_addr_match);           //inc by 8
+   
+   //#############################
+   //# Burst Detection
+   //#############################
+
+   packet2emesh p2m1 (.access_out\t(last_access),
+\t\t     .write_out\t\t(last_write),
+\t\t      .datamode_out\t(last_datamode[1:0]),
+\t\t     .ctrlmode_out\t(last_ctrlmode[3:0]),
+\t\t     .dstaddr_out\t(last_dstaddr[31:0]),
+\t\t     .data_out\t\t(),
+\t\t     .srcaddr_out\t(),
+\t\t     .packet_in\t\t(tx_packet[PW-1:0]));//input
+
+   assign burst_addr[31:0]  = (last_dstaddr[31:0] + 4\'d8);
+   
+   assign burst_addr_match  = (burst_addr[31:0] == etx_dstaddr[31:0]);
+
+   assign burst_type_match  = {last_ctrlmode[3:0],last_datamode[1:0],last_write}
+\t\t\t       ==
+\t\t   \t      {etx_ctrlmode[3:0],etx_datamode[1:0], etx_write};
+   \t\t\t      
+
+   //#############################
+   //# Wait signals (async)
+   //#############################
+
+/*   synchronizer #(.DW(1)) rd_sync (// Outputs
+\t\t\t\t   .out\t\t(tx_rd_wait_sync),
+\t\t\t\t   // Inputs
+\t\t\t\t   .in\t\t(tx_rd_wait),
+\t\t\t\t   .clk\t\t(clk),
+\t\t\t\t   .reset\t(reset)
+\t\t\t\t   );
+   
+   synchronizer #(.DW(1)) wr_sync (// Outputs
+\t\t\t\t   .out\t\t(tx_wr_wait_sync),
+\t\t\t\t   // Inputs
+\t\t\t\t   .in\t\t(tx_wr_wait),
+\t\t\t\t   .clk\t\t(clk),
+\t\t\t\t   .reset\t(reset)
+\t\t\t\t   );
+*/
+
+   always @ (posedge clk)
+      if(reset) begin
+      tx_wr_wait_sync <= 1\'b0;
+      tx_rd_wait_sync <= 1\'b0;
+      end
+      else begin
+         tx_wr_wait_sync <= tx_wr_wait;
+\t tx_rd_wait_sync <= tx_rd_wait;
+      end
+   
+   //Stall for all etx pipeline
+   //assign etx_wr_wait = tx_wr_wait_sync | tx_io_wait;
+   //assign etx_rd_wait = tx_rd_wait_sync | tx_io_wait;
+
+   always @ (posedge clk) begin
+      etx_wr_wait_reg <= tx_wr_wait | tx_io_wait;
+      etx_rd_wait_reg <= tx_rd_wait | tx_io_wait;
+   end
+   
+   assign etx_wr_wait = etx_wr_wait_reg;
+   assign etx_rd_wait = etx_rd_wait_reg;       
+
+
+endmodule // etx_protocol
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"
+module fifo_empty_block (/*AUTOARG*/
+   // Outputs
+   rd_fifo_empty, rd_addr, rd_gray_pointer,
+   // Inputs
+   reset, rd_clk, rd_wr_gray_pointer, rd_read
+   );
+
+   parameter AW   = 2; // Number of bits to access all the entries 
+
+   //##########
+   //# INPUTS
+   //##########
+   input           reset;
+   input           rd_clk;
+   
+   input [AW:0]    rd_wr_gray_pointer;//from other clock domain
+   input           rd_read;
+   
+   //###########
+   //# OUTPUTS
+   //###########
+   output          rd_fifo_empty;
+   output [AW-1:0] rd_addr;
+   output [AW:0]   rd_gray_pointer;
+   
+   //#########
+   //# REGS
+   //#########
+   reg [AW:0]      rd_gray_pointer;
+   reg [AW:0]      rd_binary_pointer;
+   reg             rd_fifo_empty;
+
+   //##########
+   //# WIRES
+   //##########
+   wire \t   rd_fifo_empty_next;
+   wire [AW:0]     rd_binary_next;
+   wire [AW:0]     rd_gray_next;
+   
+   
+   //Counter States
+   always @(posedge rd_clk or posedge reset)
+     if(reset)
+       begin
+\t  rd_binary_pointer[AW:0]     <= {(AW+1){1'b0}};
+\t  rd_gray_pointer[AW:0]       <= {(AW+1){1'b0}};
+       end
+     else if(rd_read)
+       begin
+\t  rd_binary_pointer[AW:0]     <= rd_binary_next[AW:0];\t  
+\t  rd_gray_pointer[AW:0]       <= rd_gray_next[AW:0];\t  
+       end
+
+   //Read Address
+   assign rd_addr[AW-1:0]        = rd_binary_pointer[AW-1:0];
+
+   //Updating binary pointer
+   assign rd_binary_next[AW:0]  = rd_binary_pointer[AW:0] + 
+\t\t\t\t  {{(AW){1'b0}},rd_read};
+
+   //Gray Pointer Conversion (for more reliable synchronization)!
+   assign rd_gray_next[AW:0] = {1'b0,rd_binary_next[AW:1]} ^ 
+\t\t\t       rd_binary_next[AW:0];
+
+
+   //# FIFO empty indication
+   assign rd_fifo_empty_next = (rd_gray_next[AW:0]==rd_wr_gray_pointer[AW:0]);
+
+   always @ (posedge rd_clk or posedge reset)
+     if(reset)
+       rd_fifo_empty <= 1'b1;
+     else 
+       rd_fifo_empty <= rd_fifo_empty_next;
+ 
+endmodule // fifo_empty_block
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"module etx_core(/*AUTOARG*/
+   // Outputs
+   tx_access, tx_burst, tx_packet, txrd_wait, txrr_wait, txwr_wait,
+   etx_cfg_access, etx_cfg_packet,
+   // Inputs
+   reset, clk, tx_io_wait, tx_rd_wait, tx_wr_wait, txrd_access,
+   txrd_packet, txrr_access, txrr_packet, txwr_access, txwr_packet,
+   etx_cfg_wait
+   );
+   parameter AW      = 32;
+   parameter DW      = 32;
+   parameter PW      = 104;
+   parameter RFAW    = 6;
+   parameter ID      = 12\'h000;
+   
+   //Clocks,reset,config
+   input           reset;
+   input \t   clk;   
+  
+   //IO interface
+   output \t   tx_access;
+   output \t   tx_burst;
+   output [PW-1:0] tx_packet; 
+   input \t   tx_io_wait;  
+   input \t   tx_rd_wait;
+   input \t   tx_wr_wait;
+   
+   //TXRD
+   input \t   txrd_access;
+   input [PW-1:0]  txrd_packet;
+   output \t   txrd_wait;
+   
+   //TXRR
+   input \t   txrr_access;
+   input [PW-1:0]  txrr_packet;
+   output \t   txrr_wait;
+   
+   //TXWR
+   input \t   txwr_access;
+   input [PW-1:0]  txwr_packet;
+   output \t   txwr_wait;
+
+   //Configuration Interface (for ERX)
+   output \t   etx_cfg_access;
+   output [PW-1:0] etx_cfg_packet;
+   input \t   etx_cfg_wait;
+
+   //for status?
+   wire[15:0] \t   tx_status; 
+   
+   /*AUTOOUTPUT*/
+   /*AUTOINPUT*/
+     
+   
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [3:0]\t\tctrlmode;\t\t// From etx_cfg of etx_cfg.v
+   wire\t\t\tctrlmode_bypass;\t// From etx_cfg of etx_cfg.v
+   wire\t\t\temmu_access;\t\t// From etx_mmu of emmu.v
+   wire [PW-1:0]\temmu_packet;\t\t// From etx_mmu of emmu.v
+   wire\t\t\tetx_access;\t\t// From etx_arbiter of etx_arbiter.v
+   wire [PW-1:0]\tetx_packet;\t\t// From etx_arbiter of etx_arbiter.v
+   wire\t\t\tetx_rd_wait;\t\t// From etx_protocol of etx_protocol.v
+   wire\t\t\tetx_remap_access;\t// From etx_remap of etx_remap.v
+   wire [PW-1:0]\tetx_remap_packet;\t// From etx_remap of etx_remap.v
+   wire\t\t\tetx_rr;\t\t\t// From etx_arbiter of etx_arbiter.v
+   wire\t\t\tetx_wr_wait;\t\t// From etx_protocol of etx_protocol.v
+   wire [8:0]\t\tgpio_data;\t\t// From etx_cfg of etx_cfg.v
+   wire\t\t\tgpio_enable;\t\t// From etx_cfg of etx_cfg.v
+   wire [14:0]\t\tmi_addr;\t\t// From etx_cfgif of ecfg_if.v
+   wire [DW-1:0]\tmi_cfg_dout;\t\t// From etx_cfg of etx_cfg.v
+   wire\t\t\tmi_cfg_en;\t\t// From etx_cfgif of ecfg_if.v
+   wire [63:0]\t\tmi_din;\t\t\t// From etx_cfgif of ecfg_if.v
+   wire [DW-1:0]\tmi_mmu_dout;\t\t// From etx_mmu of emmu.v
+   wire\t\t\tmi_mmu_en;\t\t// From etx_cfgif of ecfg_if.v
+   wire\t\t\tmi_we;\t\t\t// From etx_cfgif of ecfg_if.v
+   wire\t\t\tmmu_enable;\t\t// From etx_cfg of etx_cfg.v
+   wire\t\t\tremap_enable;\t\t// From etx_cfg of etx_cfg.v
+   wire\t\t\ttx_enable;\t\t// From etx_cfg of etx_cfg.v
+   // End of automatics
+
+     
+   /************************************************************/
+   /*ELINK TRANSMIT ARBITER                                    */
+   /************************************************************/
+   defparam etx_arbiter.ID=ID;   
+   etx_arbiter etx_arbiter (
+\t\t\t      /*AUTOINST*/
+\t\t\t    // Outputs
+\t\t\t    .txwr_wait\t\t(txwr_wait),
+\t\t\t    .txrd_wait\t\t(txrd_wait),
+\t\t\t    .txrr_wait\t\t(txrr_wait),
+\t\t\t    .etx_access\t\t(etx_access),
+\t\t\t    .etx_packet\t\t(etx_packet[PW-1:0]),
+\t\t\t    .etx_rr\t\t(etx_rr),
+\t\t\t    // Inputs
+\t\t\t    .clk\t\t(clk),
+\t\t\t    .reset\t\t(reset),
+\t\t\t    .txwr_access\t(txwr_access),
+\t\t\t    .txwr_packet\t(txwr_packet[PW-1:0]),
+\t\t\t    .txrd_access\t(txrd_access),
+\t\t\t    .txrd_packet\t(txrd_packet[PW-1:0]),
+\t\t\t    .txrr_access\t(txrr_access),
+\t\t\t    .txrr_packet\t(txrr_packet[PW-1:0]),
+\t\t\t    .etx_rd_wait\t(etx_rd_wait),
+\t\t\t    .etx_wr_wait\t(etx_wr_wait),
+\t\t\t    .etx_cfg_wait\t(etx_cfg_wait),
+\t\t\t    .ctrlmode_bypass\t(ctrlmode_bypass),
+\t\t\t    .ctrlmode\t\t(ctrlmode[3:0]));
+      
+
+   /************************************************************/
+   /* CONFIGURATOIN PACKET                                     */
+   /************************************************************/
+   /*ecfg_if AUTO_TEMPLATE ( 
+    .\\(.*\\)_in          (etx_\\1[]),
+    .\\(.*\\)_out         (etx_cfg_\\1[]),
+    .mi_dout0\t\t({32\'b0,mi_cfg_dout[31:0]}),
+    .mi_dout2\t\t({32\'b0,mi_mmu_dout[31:0]}),
+    .wait_in\t\t(etx_cfg_wait),
+    );
+        */
+   
+   defparam etx_cfgif.RX =0;   
+   ecfg_if etx_cfgif (.mi_dout3\t\t(64\'b0),
+\t\t      .mi_dout1\t\t(64\'b0), 
+\t\t      .mi_dma_en\t(),
+\t\t      /*AUTOINST*/
+\t\t      // Outputs
+\t\t      .mi_mmu_en\t(mi_mmu_en),
+\t\t      .mi_cfg_en\t(mi_cfg_en),
+\t\t      .mi_we\t\t(mi_we),
+\t\t      .mi_addr\t\t(mi_addr[14:0]),
+\t\t      .mi_din\t\t(mi_din[63:0]),
+\t\t      .access_out\t(etx_cfg_access),\t // Templated
+\t\t      .packet_out\t(etx_cfg_packet[PW-1:0]), // Templated
+\t\t      // Inputs
+\t\t      .clk\t\t(clk),
+\t\t      .reset\t\t(reset),
+\t\t      .access_in\t(etx_access),\t\t // Templated
+\t\t      .packet_in\t(etx_packet[PW-1:0]),\t // Templated
+\t\t      .mi_dout0\t\t({32\'b0,mi_cfg_dout[31:0]}), // Templated
+\t\t      .mi_dout2\t\t({32\'b0,mi_mmu_dout[31:0]}), // Templated
+\t\t      .wait_in\t\t(etx_cfg_wait));\t\t // Templated
+   
+   /************************************************************/
+   /* ETX CONFIGURATION REGISTERS                              */
+   /************************************************************/
+    /*etx_cfg AUTO_TEMPLATE (.mi_dout       (mi_cfg_dout[DW-1:0]), 
+                             .mi_en\t    (mi_cfg_en),
+    );
+        */
+
+   //todo: make more useufl
+   assign tx_status[15:0]  = 16\'b0;
+/*   
+
+{2\'b0,                //15:14
+\t\t\t      etx_rd_wait,         //13
+\t\t\t      etx_wr_wait,         //12
+\t\t\t      txrr_fifo_read,      //11\t\t\t
+\t\t\t      txrr_wait,           //10
+\t\t\t      txrr_access,         //9\t \t\t
+\t\t\t      txrd_fifo_read,      //8\t\t\t
+\t\t\t      txrd_wait,           //7
+\t\t\t      txrd_access,         //6
+\t\t\t      txwr_fifo_read,      //5
+\t\t\t      txwr_wait,           //4
+\t\t\t      txwr_access,         //3
+\t\t\t      1\'b0,                //2
+\t\t\t      1\'b0,                //1
+\t\t\t      1\'b0\t           //0
+\t\t\t      };
+*/
+ 
+   etx_cfg etx_cfg (
+\t\t    /*AUTOINST*/
+\t\t    // Outputs
+\t\t    .mi_dout\t\t(mi_cfg_dout[DW-1:0]),\t // Templated
+\t\t    .tx_enable\t\t(tx_enable),
+\t\t    .mmu_enable\t\t(mmu_enable),
+\t\t    .gpio_enable\t(gpio_enable),
+\t\t    .remap_enable\t(remap_enable),
+\t\t    .gpio_data\t\t(gpio_data[8:0]),
+\t\t    .ctrlmode\t\t(ctrlmode[3:0]),
+\t\t    .ctrlmode_bypass\t(ctrlmode_bypass),
+\t\t    // Inputs
+\t\t    .reset\t\t(reset),
+\t\t    .clk\t\t(clk),
+\t\t    .mi_en\t\t(mi_cfg_en),\t\t // Templated
+\t\t    .mi_we\t\t(mi_we),
+\t\t    .mi_addr\t\t(mi_addr[RFAW+1:0]),
+\t\t    .mi_din\t\t(mi_din[31:0]),
+\t\t    .tx_status\t\t(tx_status[15:0]));
+      
+   /************************************************************/
+   /* REMAPPING (SHIFT) DESTINATION ADDRESS                    */
+   /************************************************************/
+    /*etx_remap  AUTO_TEMPLATE (\t
+                          .emesh_\\(.*\\)_in  (etx_\\1[]),
+                          .emesh_\\(.*\\)_out (etx_remap_\\1[]),
+                          .remap_en\t    (remap_enable),
+                          .remap_bypass\t    (etx_rr),
+                          .emesh_wait       (etx_wait),
+                          );
+   */
+
+   etx_remap etx_remap (/*AUTOINST*/
+\t\t\t// Outputs
+\t\t\t.emesh_access_out(etx_remap_access),\t // Templated
+\t\t\t.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
+\t\t\t// Inputs
+\t\t\t.clk\t\t(clk),
+\t\t\t.reset\t\t(reset),
+\t\t\t.emesh_access_in(etx_access),\t\t // Templated
+\t\t\t.emesh_packet_in(etx_packet[PW-1:0]),\t // Templated
+\t\t\t.remap_en\t(remap_enable),\t\t // Templated
+\t\t\t.remap_bypass\t(etx_rr),\t\t // Templated
+\t\t\t.etx_rd_wait\t(etx_rd_wait),
+\t\t\t.etx_wr_wait\t(etx_wr_wait));
+   
+ 
+   /************************************************************/
+   /* EMMU                                                     */
+   /************************************************************/
+   /*emmu  AUTO_TEMPLATE (\t
+                          .emesh_\\(.*\\)_in  (etx_remap_\\1[]),
+                          .emesh_\\(.*\\)_out (emmu_\\1[]),
+                          .mmu_en\t    (mmu_enable),
+                          .mmu_bp\t    (etx_rr),
+                          .rd_clk           (clk),
+                          .wr_clk           (clk),
+                          .emmu_access_out  (emmu_access),
+                          .emmu_packet_out  (emmu_packet[PW-1:0]),
+                          .mi_dout\t    (mi_mmu_dout[DW-1:0]),
+                          .emesh_rd_wait    (etx_rd_wait),
+                          .emesh_wr_wait    (etx_wr_wait),
+                          .emesh_packet_hi_out\t(),
+                          .mi_en\t    (mi_mmu_en),
+                         );
+   */
+
+   emmu etx_mmu (
+\t      /*AUTOINST*/
+\t\t // Outputs
+\t\t .mi_dout\t\t(mi_mmu_dout[DW-1:0]),\t // Templated
+\t\t .emesh_access_out\t(emmu_access),\t\t // Templated
+\t\t .emesh_packet_out\t(emmu_packet[PW-1:0]),\t // Templated
+\t\t .emesh_packet_hi_out\t(),\t\t\t // Templated
+\t\t // Inputs
+\t\t .reset\t\t\t(reset),
+\t\t .rd_clk\t\t(clk),\t\t\t // Templated
+\t\t .wr_clk\t\t(clk),\t\t\t // Templated
+\t\t .mmu_en\t\t(mmu_enable),\t\t // Templated
+\t\t .mmu_bp\t\t(etx_rr),\t\t // Templated
+\t\t .mi_en\t\t\t(mi_mmu_en),\t\t // Templated
+\t\t .mi_we\t\t\t(mi_we),
+\t\t .mi_addr\t\t(mi_addr[14:0]),
+\t\t .mi_din\t\t(mi_din[DW-1:0]),
+\t\t .emesh_access_in\t(etx_remap_access),\t // Templated
+\t\t .emesh_packet_in\t(etx_remap_packet[PW-1:0]), // Templated
+\t\t .emesh_rd_wait\t\t(etx_rd_wait),\t\t // Templated
+\t\t .emesh_wr_wait\t\t(etx_wr_wait));\t\t // Templated
+   
+
+   /************************************************************/
+   /*ELINK PROTOCOL LOGIC                                      */
+   /************************************************************/
+   /*etx_protocol  AUTO_TEMPLATE (\t\t\t       
+                                  .etx_rd_wait     (etx_rd_wait),
+                                  .etx_wr_wait     (etx_wr_wait),
+                                  .etx_\\(.*\\)      (emmu_\\1[]),
+                                  .etx_wait\t   (etx_wait),    
+                             );
+   */
+
+   defparam etx_protocol.ID=ID;   
+   etx_protocol etx_protocol (
+\t\t\t      /*AUTOINST*/
+\t\t\t      // Outputs
+\t\t\t      .etx_rd_wait\t(etx_rd_wait),\t // Templated
+\t\t\t      .etx_wr_wait\t(etx_wr_wait),\t // Templated
+\t\t\t      .tx_packet\t(tx_packet[PW-1:0]),
+\t\t\t      .tx_access\t(tx_access),
+\t\t\t      .tx_burst\t\t(tx_burst),
+\t\t\t      // Inputs
+\t\t\t      .reset\t\t(reset),
+\t\t\t      .clk\t\t(clk),
+\t\t\t      .etx_access\t(emmu_access),\t // Templated
+\t\t\t      .etx_packet\t(emmu_packet[PW-1:0]), // Templated
+\t\t\t      .tx_enable\t(tx_enable),
+\t\t\t      .gpio_data\t(gpio_data[8:0]),
+\t\t\t      .gpio_enable\t(gpio_enable),
+\t\t\t      .tx_io_wait\t(tx_io_wait),
+\t\t\t      .tx_rd_wait\t(tx_rd_wait),
+\t\t\t      .tx_wr_wait\t(tx_wr_wait));
+   
+endmodule // elink
+// Local Variables:
+// verilog-library-directories:(""."" ""../../emmu/hdl"" ""../../memory/hdl"")
+// End:
+
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+ 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"/* Parametrized model for xilinx async fifo*/
+module fifo_async_model
+   (/*AUTOARG*/
+   // Outputs
+   full, prog_full, almost_full, dout, empty, valid,
+   // Inputs
+   wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
+   );
+   
+   parameter DW    = 104;            //Fifo width 
+   parameter DEPTH = 1;              //Fifo depth (entries)         
+   parameter AW    = $clog2(DEPTH);  //FIFO address width (for model)
+
+   //##########
+   //# RESET/CLOCK
+   //##########
+   input           wr_rst;     //asynchronous reset
+   input           rd_rst;     //asynchronous reset
+   input           wr_clk;    //write clock   
+   input           rd_clk;    //read clock   
+
+   //##########
+   //# FIFO WRITE
+   //##########
+   input           wr_en;   
+   input  [DW-1:0] din;
+   output          full;
+   output \t   prog_full;
+   output \t   almost_full;
+   
+   //###########
+   //# FIFO READ
+   //###########
+   input \t   rd_en;
+   output [DW-1:0] dout;
+   output          empty;
+   output          valid;
+    
+   //Wires
+   wire [DW/8-1:0] wr_vec;
+   wire [AW:0]\t   wr_rd_gray_pointer;
+   wire [AW:0] \t   rd_wr_gray_pointer;
+   wire [AW:0] \t   wr_gray_pointer;
+   wire [AW:0] \t   rd_gray_pointer;
+   wire [AW-1:0]   rd_addr;
+   wire [AW-1:0]   wr_addr;
+
+   reg \t\t   valid;
+   
+   
+   assign wr_vec[DW/8-1:0] = {(DW/8){wr_en}};
+
+
+   //Valid data at output
+   always @ (posedge rd_clk or posedge rd_rst)
+     if(rd_rst)
+       valid <=1\'b0;
+     else
+       valid <= rd_en;
+   
+   memory_dp #(.DW(DW),.AW(AW)) memory_dp (
+\t\t\t\t\t   // Outputs
+\t\t\t\t\t   .rd_data\t(dout[DW-1:0]),
+\t\t\t\t\t   // Inputs
+\t\t\t\t\t   .wr_clk\t(wr_clk),
+\t\t\t\t\t   .wr_en\t(wr_vec[DW/8-1:0]),
+\t\t\t\t\t   .wr_addr\t(wr_addr[AW-1:0]),
+\t\t\t\t\t   .wr_data\t(din[DW-1:0]),
+\t\t\t\t\t   .rd_clk\t(rd_clk),
+\t\t\t\t\t   .rd_en\t(rd_en),
+\t\t\t\t\t   .rd_addr\t(rd_addr[AW-1:0]));
+
+   //Read State Machine
+   fifo_empty_block #(.AW(AW)) fifo_empty_block(
+\t\t\t\t\t\t// Outputs
+\t\t\t\t\t\t.rd_fifo_empty\t(empty),
+\t\t\t\t\t\t.rd_addr\t(rd_addr[AW-1:0]),
+\t\t\t\t\t\t.rd_gray_pointer(rd_gray_pointer[AW:0]),
+\t\t\t\t\t\t// Inputs
+\t\t\t\t\t\t.reset\t\t(rd_rst),
+\t\t\t\t\t\t.rd_clk\t\t(rd_clk),
+\t\t\t\t\t\t.rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]),
+\t\t\t\t\t\t.rd_read\t(rd_en));
+   
+   //Write circuit (and full indicator)
+   fifo_full_block #(.AW(AW)) full_block (
+\t\t\t\t\t      // Outputs
+\t\t\t\t\t      .wr_fifo_almost_full(almost_full),
+\t\t\t\t\t      .wr_fifo_full\t(full),\t\t\t\t      
+\t\t\t\t\t      .wr_addr\t\t(wr_addr[AW-1:0]),
+\t\t\t\t\t      .wr_gray_pointer\t(wr_gray_pointer[AW:0]),
+\t\t\t\t\t      // Inputs
+\t\t\t\t\t      .reset\t\t(wr_rst),
+\t\t\t\t\t      .wr_clk\t\t(wr_clk),
+\t\t\t\t\t      .wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]),
+\t\t\t\t\t      .wr_write\t\t(wr_en));
+   
+
+   //Half Full Indicator
+   fifo_full_block #(.AW(AW-1)) half_full_block (
+\t\t\t\t\t      // Outputs
+\t\t\t\t\t      .wr_fifo_almost_full(),
+\t\t\t\t\t      .wr_fifo_full\t(prog_full),\t\t\t      
+\t\t\t\t\t      .wr_addr\t\t(wr_addr[AW-2:0]),
+\t\t\t\t\t      .wr_gray_pointer\t(),
+\t\t\t\t\t      // Inputs
+\t\t\t\t\t      .reset\t\t(wr_rst),
+\t\t\t\t\t      .wr_clk\t\t(wr_clk),
+\t\t\t\t\t      .wr_rd_gray_pointer(wr_rd_gray_pointer[AW-1:0]),
+\t\t\t\t\t      .wr_write\t\t(wr_en));
+
+
+   
+   //Read pointer sync
+   synchronizer #(.DW(AW+1)) rd2wr_sync (.out\t\t(wr_rd_gray_pointer[AW:0]),
+\t\t\t\t\t .in\t\t(rd_gray_pointer[AW:0]),
+                                         .reset\t\t(wr_rst),
+\t\t\t\t\t .clk\t\t(wr_clk));
+   
+   //Write pointer sync
+   synchronizer #(.DW(AW+1)) wr2rd_sync (.out\t\t(rd_wr_gray_pointer[AW:0]),
+\t\t\t\t\t .in\t\t(wr_gray_pointer[AW:0]),
+                                         .reset\t\t(rd_rst),
+\t\t\t\t\t .clk\t\t(rd_clk));
+   
+      
+endmodule // fifo_async
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"module ereset (/*AUTOARG*/
+   // Outputs
+   etx_reset, erx_reset, sys_reset,etx90_reset,erx_ioreset,
+   // Inputs
+   reset, sys_clk, tx_lclk_div4, rx_lclk_div4,tx_lclk90,rx_lclk
+   );
+
+   // reset inputs
+   input   reset;           // POR | ~elink_en (with appropriate delays..)
+   
+   //synchronization clocks
+   input   sys_clk;        // system clock
+   input   tx_lclk_div4;   // slow clock for TX
+   input   rx_lclk_div4;   // slow clock for RX
+   input   tx_lclk90;
+   input   rx_lclk;
+      
+
+   //synchronous reset outputs
+   output  etx_reset;      // reset for TX slow logic
+   output  erx_reset;      // reset for RX slow logic
+   output  sys_reset;     // reset for system FIFOs
+   output  etx90_reset;
+   output  erx_ioreset;
+   
+   
+   reg \t   erx_ioresetb;
+   reg \t   erx_resetb;
+   reg \t   etx_resetb;
+   reg \t   sys_resetb;
+   reg \t   etx90_resetb;
+   
+   
+  /* 
+   //erx reset synchronizer
+   synchronizer sync_erx (.out\t (erx_resetb),
+\t\t\t  .in\t (1\'b1),
+\t\t\t  .clk\t (rx_lclk_div4),
+\t\t\t  .reset (reset)
+\t\t\t  );
+
+   //etx reset synchronizer
+   synchronizer sync_etx (.out\t (etx_resetb),
+\t\t\t  .in\t (1\'b1),
+\t\t\t  .clk\t (tx_lclk_div4),
+\t\t\t  .reset (reset)
+\t\t\t  );
+
+   //system reset synchronizer
+    synchronizer sync_sys (.out\t (sys_resetb),
+\t\t\t  .in\t (1\'b1),
+\t\t\t  .clk\t (sys_clk),
+\t\t\t  .reset (reset)
+\t\t\t   );
+*/
+
+   always @ (posedge rx_lclk_div4)
+     erx_resetb <= reset;
+
+   always @ (posedge tx_lclk_div4)
+     etx_resetb <= reset;
+   
+   always @ (posedge sys_clk)
+     sys_resetb <= reset;
+
+   always @ (posedge tx_lclk90)
+     etx90_resetb <= reset;
+   
+   always @ (posedge rx_lclk)
+     erx_ioresetb <= reset;
+
+   assign erx_ioreset =erx_ioresetb;
+   assign etx_reset =etx_resetb;
+   assign erx_reset =erx_resetb;
+   assign sys_reset =sys_resetb;
+   assign etx90_reset =etx90_resetb;
+   
+   
+endmodule // ereset
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl/"")
+// End:
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+ 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+"
+"/*
+ * This module stretches a pulse by DW+1 clock cycles
+ * Can be useful for synchronous clock transfers from fast to slow.
+ * 
+ */
+
+module pulse_stretcher (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, reset, in
+   );
+
+   parameter DW = 1;
+   
+   input clk;
+   input reset;   
+   input in;
+   output out;
+
+   reg [DW-1:0] wide_pulse;
+   
+   
+   always @ (posedge clk )//or posedge reset)
+     if(reset)
+       wide_pulse[DW-1:0] <= 'b0;
+     else
+       wide_pulse[DW-1:0] <= {wide_pulse[DW-2:0],in};
+
+   assign out = (|{wide_pulse[DW-1:0],in});
+   
+endmodule // pulse_stretcher
+"
+"//`timescale 1 ns / 100 ps
+module dv_embox();
+
+   parameter DW = 32;
+   
+   
+   //Stimulus to drive
+   reg        clk;
+   reg        reset;
+   reg        mi_access;
+   reg [19:0]  mi_addr;
+   reg [31:0] mi_data_in;
+   reg \t      mi_write;
+   reg [1:0]  test_state;
+   reg \t      go;
+   
+   //Reset
+   initial
+     begin
+\t$display($time, "" << Starting the Simulation >>"");\t
+\t#0
+        clk              = 1\'b0;    // at time 0
+\treset            = 1\'b1;    // reset is active
+\tmi_write         = 1\'b0;
+\tmi_access        = 1\'b0;
+\tmi_addr[19:0]    = 20\'hf0368;
+\tmi_data_in[31:0] = 32\'h0;
+\ttest_state[1:0]  = 2\'b00;
+\tgo               = 1\'b0;\t
+\t#100 
+\t  reset    = 1\'b0;    // at time 100 release reset
+\t#100
+\t  go       = 1\'b1;\t
+\t#10000\t  
+\t  $finish;
+     end
+
+   //Clock
+   always
+     #10 clk = ~clk;
+
+   //Pattern generator
+   //1.) Write in 8 transactions (split into low and high)
+   //2.) Read back 8 transactions (split into low and high)
+      
+   always @ (negedge clk)
+     if(go)
+       begin
+\t  case(test_state[1:0])
+\t    2\'b00://write
+\t      if(~done)
+\t\tbegin
+\t\t   mi_access        <= 1\'b1;
+\t\t   mi_write         <= 1\'b1;
+\t\t   mi_addr[19:0]    <= mi_addr[19:0] ^ 20\'hc;\t  
+\t\t   mi_data_in[31:0] <= mi_data_in[31:0]+1\'b1;
+\t\tend
+\t      else
+\t\tbegin
+\t\t   test_state       <= 2\'b01;\t    
+\t\t   mi_addr[19:0]    <= 20\'hf0368;
+\t\t   mi_data_in[31:0] <= 32\'h0;\t\t   
+\t\tend
+\t    2\'b01://read
+\t      if(~done)
+\t\tbegin\t    
+\t\t   mi_write         <= 1\'b0;
+\t\t   mi_access        <= 1\'b1;
+\t\t   mi_addr[19:0]    <= mi_addr[19:0] ^ 20\'hc;
+\t\t   mi_data_in[31:0] <= mi_data_in[31:0]+1\'b1;
+\t\tend
+\t      else
+\t\tbegin
+\t\t   test_state       <= 2\'b10;
+\t\t   mi_write         <= 1\'b0;
+\t\t   mi_access        <= 1\'b0;
+\t\tend
+\t  endcase // case (test_state[1:0])
+       end
+
+   wire done =  (mi_data_in[19:0]==20\'h8);
+   
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\tembox_empty;\t\t// From embox of embox.v
+   wire\t\t\tembox_full;\t\t// From embox of embox.v
+   wire [DW-1:0]\tmi_data_out;\t\t// From embox of embox.v
+   // End of automatics
+   
+   //DUT
+   embox embox(
+\t     /*AUTOINST*/
+\t       // Outputs
+\t       .mi_data_out\t\t(mi_data_out[DW-1:0]),
+\t       .embox_full\t\t(embox_full),
+\t       .embox_empty\t\t(embox_empty),
+\t       // Inputs
+\t       .reset\t\t\t(reset),
+\t       .clk\t\t\t(clk),
+\t       .mi_access\t\t(mi_access),
+\t       .mi_write\t\t(mi_write),
+\t       .mi_addr\t\t\t(mi_addr[19:0]),
+\t       .mi_data_in\t\t(mi_data_in[DW-1:0]));
+
+
+   //Waveform dump
+   initial
+     begin
+\t$dumpfile(""test.vcd"");
+\t$dumpvars(0, dv_embox);
+     end
+
+   
+endmodule // dv_embox
+// Local Variables:
+// verilog-library-directories:(""."" ""../hdl"" ""../../memory/hdl "")
+// End:
+
+
+"
+"module edma (/*AUTOARG*/
+   // Outputs
+   mi_dout, edma_access, edma_packet,
+   // Inputs
+   reset, clk, mi_en, mi_we, mi_addr, mi_din, edma_wait
+   );
+
+   /******************************/
+   /*Compile Time Parameters     */
+   /******************************/
+   parameter RFAW            = 6;
+   parameter AW              = 32;
+   parameter DW              = 32;
+   parameter PW              = 104;
+
+   /******************************/
+   /*HARDWARE RESET (EXTERNAL)   */
+   /******************************/
+   input \t     reset; 
+   input \t     clk;
+
+   /*****************************/
+   /*REGISTER INTERFACE         */
+   /*****************************/      
+   input \t     mi_en;         
+   input \t     mi_we; 
+   input [RFAW+1:0]  mi_addr;
+   input [63:0]      mi_din;
+   output [31:0]     mi_dout;   
+  
+   /*****************************/
+   /*DMA TRANSACTION            */
+   /*****************************/
+   output \t     edma_access;
+   output [PW-1:0]   edma_packet;
+   input \t     edma_wait;
+
+
+
+   
+
+
+   
+   assign edma_access=1\'b0;
+   assign edma_packet=\'d0;
+   assign  mi_dout=\'d0;
+
+   /*   
+
+    //registers
+   reg [AW-1:0]  edma_srcaddr_reg;
+   reg [AW-1:0]  edma_dstaddr_reg;
+   reg [AW-1:0]  edma_count_reg;
+   reg [AW-1:0]  edma_stride_reg;
+   reg [8:0]     edma_cfg_reg;
+   reg [1:0]     edma_status_reg;
+   reg [31:0] \t mi_dout;
+   
+   //wires
+   wire \t edma_write;
+   wire \t edma_read;
+   wire \t edma_cfg_write ;
+   wire \t edma_srcaddr_write;
+   wire \t edma_dstaddr_write;
+   wire \t edma_stride_write;
+   wire \t edma_count_write;
+   wire \t edma_message;
+   wire \t edma_expired;
+   wire          edma_last_tran;
+   wire \t edma_error;
+   wire          edma_enable;
+    
+    
+   //read/write decode
+   assign edma_write  = mi_en &  mi_we;
+   assign edma_read   = mi_en & ~mi_we;   
+
+   //DMA configuration
+   assign edma_cfg_write      = edma_write & (mi_addr[RFAW+1:2]==`EDMACFG);
+   assign edma_srcaddr_write  = edma_write & (mi_addr[RFAW+1:2]==`EDMASRCADDR);
+   assign edma_dstaddr_write  = edma_write & (mi_addr[RFAW+1:2]==`EDMADSTADDR);
+   assign edma_count_write    = edma_write & (mi_addr[RFAW+1:2]==`EDMACOUNT);
+   assign edma_stride_write   = edma_write & (mi_addr[RFAW+1:2]==`EDMASTRIDE);
+   
+   //###########################
+   //# DMACFG
+   //###########################
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       edma_cfg_reg[8:0] <= \'d0;   
+     else if (edma_cfg_write)
+       edma_cfg_reg[8:0] <= mi_din[8:0];
+
+   assign edma_enable         = edma_cfg_reg[0];  //should be zero     
+   assign edma_message        = edma_cfg_reg[8];
+
+   assign edma_access         = edma_enable & ~edma_expired;   
+   assign edma_write          = edma_cfg_reg[1];  //only 1 for test pattern   
+   assign edma_datamode[1:0]  = edma_cfg_reg[3:2];
+   assign edma_ctrlmode[3:0]  = (edma_message & edma_last_tran) ? 4\'b1100 : edma_cfg_reg[7:4];
+
+   //###########################
+   //# DMASTATUS
+   //###########################
+   //Misalignment
+   assign edma_error = ((edma_srcaddr_reg[0] | edma_dstaddr_reg[0]) & (edma_datamode[1:0]!=2\'b00)) | //16/32/64
+                       ((edma_srcaddr_reg[1] | edma_dstaddr_reg[1]) & (edma_datamode[1]))          | //32/64
+                       ((edma_srcaddr_reg[2] | edma_dstaddr_reg[2]) & (edma_datamode[1:0]==2\'b11));  //64
+
+
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       edma_status_reg[1:0] <= \'d0;   
+     else if (edma_cfg_write)
+       edma_status_reg[1:0] <= mi_din[1:0];
+     else if (edma_enable)
+       begin
+\t  edma_status_reg[0] <= edma_enable & ~edma_expired;//dma busy
+\t  edma_status_reg[1] <= edma_status_reg[1]  | (edma_enable & edma_error);
+       end
+        
+   //###########################
+   //# EDMASRCADDR
+   //###########################
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       edma_srcaddr_reg[AW-1:0] <= \'d0;   
+     else if (edma_srcaddr_write)
+       edma_srcaddr_reg[AW-1:0] <= mi_din[AW-1:0];
+     else if (edma_enable & ~edma_wait)
+       edma_srcaddr_reg[AW-1:0] <= edma_srcaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
+
+   assign edma_srcaddr[31:0]  = edma_srcaddr_reg[31:0];
+   //###########################
+   //# EDMADSTADR
+   //###########################
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       edma_dstaddr_reg[AW-1:0] <= \'d0;   
+     else if (edma_dstaddr_write)
+       edma_dstaddr_reg[AW-1:0] <= mi_din[AW-1:0];
+     else if (edma_enable & ~edma_wait)
+       edma_dstaddr_reg[AW-1:0] <= edma_dstaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
+   
+   assign edma_dstaddr[31:0]  = edma_dstaddr_reg[31:0];
+
+   //###########################
+   //# EDMACOUNT
+   //###########################
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       edma_count_reg[AW-1:0] <= \'d0;   
+     else if (edma_count_write)
+       edma_count_reg[AW-1:0] <= mi_din[AW-1:0];
+     else if (edma_enable & ~edma_wait)
+       edma_count_reg[AW-1:0] <= edma_count_reg[AW-1:0] - 1\'b1;
+   
+   assign edma_last_tran = (edma_count_reg[AW-1:0]==32\'b1);   
+   assign edma_expired   = (edma_count_reg[AW-1:0]==32\'b0);   
+
+   //###########################
+   //# EDMASTRIDE
+   //###########################
+   //NOTE: not supported yet, need to think about feature...
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       edma_stride_reg[AW-1:0] <= \'d0;   
+     else if (edma_stride_write)
+       edma_stride_reg[AW-1:0] <= mi_din[AW-1:0];
+        
+   //###########################
+   //# DUMMY DATA
+   //###########################
+   assign edma_data[31:0]     = TEST_PATTERN;   
+     
+   
+   //###########################
+   //# PACKET CREATION
+   //###########################
+   emesh2packet e2p (
+\t\t     // Outputs
+\t\t     .packet_out\t(edma_packet[PW-1:0]),
+\t\t     // Inputs
+\t\t     .access_in\t\t(edma_access),
+\t\t     .write_in\t\t(edma_write),
+\t\t     .datamode_in\t(edma_datamode[1:0]),
+\t\t     .ctrlmode_in\t(edma_ctrlmode[3:0]),
+\t\t     .dstaddr_in\t(edma_dstaddr[AW-1:0]),
+\t\t     .data_in\t\t(edma_data[DW-1:0]),
+\t\t     .srcaddr_in\t(edma_srcaddr_in[AW-1:0]));
+   
+   
+   //###############################
+   //# DATA READBACK MUX
+   //###############################
+
+   //Pipelineing readback
+   always @ (posedge clk)
+     if(edma_read)
+       case(mi_addr[RFAW+1:2])
+         `EDMACFG:    mi_dout[31:0] <= {23\'b0, edma_cfg_reg[8:0]};
+\t `EDMASTATUS: mi_dout[31:0] <= {30\'b0, edma_status_reg[1:0]};
+\t `EDMASRCADDR:mi_dout[31:0] <= {edma_srcaddr_reg[31:0]};
+\t `EDMADSTADDR:mi_dout[31:0] <= {edma_dstaddr_reg[31:0]};
+\t `EDMACOUNT:  mi_dout[31:0] <= {edma_count_reg[31:0]};\t         
+         default:    mi_dout[31:0] <= 32\'d0;
+       endcase // case (mi_addr[RFAW+1:2])
+     else
+       begin
+\t  default:    mi_dout[31:0] <= 32\'d0;
+       end
+*/
+endmodule // edma
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+
+/*
+  Copyright (C) 2013 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+"
+"module erx_core (/*AUTOARG*/
+   // Outputs
+   rx_rd_wait, rx_wr_wait, rxrd_access, rxrd_packet, rxrr_access,
+   rxrr_packet, rxwr_access, rxwr_packet, erx_cfg_wait, mailbox_full,
+   mailbox_not_empty,
+   // Inputs
+   reset, clk, rx_packet, rx_access, rx_burst, rxrd_wait, rxrr_wait,
+   rxwr_wait, erx_cfg_access, erx_cfg_packet
+   );
+
+   parameter AW      = 32;
+   parameter DW      = 32;
+   parameter PW      = 104;
+   parameter RFAW    = 6;
+   parameter ID      = 12\'h800;
+
+
+   //clock and reset
+   input\t\treset;
+   input\t\tclk;
+
+   //IO Interface
+   input [PW-1:0] \trx_packet;
+   input \t\trx_access;
+   input \t\trx_burst;
+   output \t\trx_rd_wait;
+   output \t\trx_wr_wait;
+   
+   //FIFO Access
+   output\t\trxrd_access;
+   output [PW-1:0]\trxrd_packet;
+   input\t\trxrd_wait;
+   
+   output\t\trxrr_access;
+   output [PW-1:0]\trxrr_packet;
+   input\t\trxrr_wait;
+   
+   output\t\trxwr_access;
+   output [PW-1:0]\trxwr_packet;
+   input\t\trxwr_wait;
+
+   //register interface
+   input\t\terx_cfg_access;
+   input [PW-1:0]\terx_cfg_packet;
+   output \t\terx_cfg_wait;
+
+   //mailbox outputs
+   output\t\tmailbox_full;           //need to sync to sys_clk
+   output\t\tmailbox_not_empty;      //need to sync to sys_clk
+
+   
+   /*AUTOINPUT*/
+   /*AUTOOUTPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire\t\t\tecfg_access;\t\t// From erx_cfgif of ecfg_if.v
+   wire [PW-1:0]\tecfg_packet;\t\t// From erx_cfgif of ecfg_if.v
+   wire\t\t\tedma_access;\t\t// From erx_dma of edma.v
+   wire\t\t\tedma_wait;\t\t// From erx_arbiter of erx_arbiter.v
+   wire\t\t\temesh_remap_access;\t// From erx_remap of erx_remap.v
+   wire [PW-1:0]\temesh_remap_packet;\t// From erx_remap of erx_remap.v
+   wire\t\t\temmu_access;\t\t// From erx_mmu of emmu.v
+   wire [PW-1:0]\temmu_packet;\t\t// From erx_mmu of emmu.v
+   wire [PW-1:0]\terx_packet;\t\t// From erx_protocol of erx_protocol.v
+   wire\t\t\terx_rdwr_access;\t// From erx_protocol of erx_protocol.v
+   wire\t\t\terx_rr_access;\t\t// From erx_protocol of erx_protocol.v
+   wire [14:0]\t\tmi_addr;\t\t// From erx_cfgif of ecfg_if.v
+   wire [DW-1:0]\tmi_cfg_dout;\t\t// From erx_cfg of erx_cfg.v
+   wire\t\t\tmi_cfg_en;\t\t// From erx_cfgif of ecfg_if.v
+   wire [63:0]\t\tmi_din;\t\t\t// From erx_cfgif of ecfg_if.v
+   wire [DW-1:0]\tmi_dma_dout;\t\t// From erx_dma of edma.v
+   wire\t\t\tmi_dma_en;\t\t// From erx_cfgif of ecfg_if.v
+   wire [63:0]\t\tmi_mailbox_dout;\t// From erx_mailbox of emailbox.v
+   wire [DW-1:0]\tmi_mmu_dout;\t\t// From erx_mmu of emmu.v
+   wire\t\t\tmi_mmu_en;\t\t// From erx_cfgif of ecfg_if.v
+   wire\t\t\tmi_we;\t\t\t// From erx_cfgif of ecfg_if.v
+   wire\t\t\tmmu_enable;\t\t// From erx_cfg of erx_cfg.v
+   wire [31:0]\t\tremap_base;\t\t// From erx_cfg of erx_cfg.v
+   wire [1:0]\t\tremap_mode;\t\t// From erx_cfg of erx_cfg.v
+   wire [11:0]\t\tremap_pattern;\t\t// From erx_cfg of erx_cfg.v
+   wire [11:0]\t\tremap_sel;\t\t// From erx_cfg of erx_cfg.v
+   wire\t\t\trx_enable;\t\t// From erx_cfg of erx_cfg.v
+   // End of automatics
+
+     
+   //regs
+    wire [8:0] \tgpio_datain;\t\t// To erx_cfg of erx_cfg.v
+   wire [15:0] \trx_status;
+   wire \trxwr_full;
+   wire \trxrr_full;
+   wire \trxrd_full;
+   wire \trxrd_empty;
+   wire \trxwr_empty;
+   wire \trxrr_empty;
+   wire [103:0] edma_packet;\t\t// From edma of edma.v, ...
+   
+
+   /**************************************************************/
+   /*ELINK PROTOCOL LOGIC                                        */
+   /**************************************************************/
+
+   defparam erx_protocol.ID=ID;     
+   erx_protocol erx_protocol (/*AUTOINST*/
+\t\t\t      // Outputs
+\t\t\t      .erx_rdwr_access\t(erx_rdwr_access),
+\t\t\t      .erx_rr_access\t(erx_rr_access),
+\t\t\t      .erx_packet\t(erx_packet[PW-1:0]),
+\t\t\t      // Inputs
+\t\t\t      .reset\t\t(reset),
+\t\t\t      .rx_enable\t(rx_enable),
+\t\t\t      .clk\t\t(clk),
+\t\t\t      .rx_packet\t(rx_packet[PW-1:0]),
+\t\t\t      .rx_burst\t\t(rx_burst),
+\t\t\t      .rx_access\t(rx_access));
+
+
+
+   /**************************************************************/
+   /*ADDRESS REMPAPPING                                          */
+   /**************************************************************/
+
+   /*erx_remap AUTO_TEMPLATE ( 
+                        .emesh_\\(.*\\)_out\t(emesh_remap_\\1[]),   
+                         //Inputs
+                        .emesh_access_in        (erx_rdwr_access),
+                        .emesh_\\(.*\\)_in\t(erx_\\1[]),   
+                        .mmu_en\t\t\t(ecfg_rx_mmu_enable),
+                        .emesh_packet_hi_out\t(),
+                           );
+   */
+
+   defparam erx_remap.ID = ID;
+   erx_remap erx_remap (/*AUTOINST*/
+\t\t\t// Outputs
+\t\t\t.emesh_access_out(emesh_remap_access),\t // Templated
+\t\t\t.emesh_packet_out(emesh_remap_packet[PW-1:0]), // Templated
+\t\t\t// Inputs
+\t\t\t.clk\t\t(clk),
+\t\t\t.reset\t\t(reset),
+\t\t\t.emesh_access_in(erx_rdwr_access),\t // Templated
+\t\t\t.emesh_packet_in(erx_packet[PW-1:0]),\t // Templated
+\t\t\t.remap_mode\t(remap_mode[1:0]),
+\t\t\t.remap_sel\t(remap_sel[11:0]),
+\t\t\t.remap_pattern\t(remap_pattern[11:0]),
+\t\t\t.remap_base\t(remap_base[31:0]));
+   
+ 
+   
+   /************************************************************/
+   /*ELINK MEMORY MANAGEMENT UNIT                              */
+   /************************************************************/
+   /*emmu AUTO_TEMPLATE ( 
+                        .emesh_\\(.*\\)_out\t(emmu_\\1[]),   
+                         //Inputs
+                        .emesh_\\(.*\\)_in\t(emesh_remap_\\1[]),   
+                        .mmu_en\t\t\t(mmu_enable),
+                        .rd_clk\t        \t(clk),
+                        .wr_clk\t        \t(clk),
+                        .mi_dout   \t        (mi_mmu_dout[DW-1:0]),
+                        .emesh_packet_hi_out\t(),
+                        .mi_en\t                (mi_mmu_en),
+                        
+                           );
+   */
+
+   emmu erx_mmu (.mmu_bp\t\t(1\'b0),\t
+\t\t .emesh_rd_wait\t\t(1\'b0), //absorbed by fifo
+\t\t .emesh_wr_wait\t\t(1\'b0),
+\t\t /*AUTOINST*/
+\t\t // Outputs
+\t\t .mi_dout\t\t(mi_mmu_dout[DW-1:0]),\t // Templated
+\t\t .emesh_access_out\t(emmu_access),\t\t // Templated
+\t\t .emesh_packet_out\t(emmu_packet[PW-1:0]),\t // Templated
+\t\t .emesh_packet_hi_out\t(),\t\t\t // Templated
+\t\t // Inputs
+\t\t .reset\t\t\t(reset),
+\t\t .rd_clk\t\t(clk),\t\t\t // Templated
+\t\t .wr_clk\t\t(clk),\t\t\t // Templated
+\t\t .mmu_en\t\t(mmu_enable),\t\t // Templated
+\t\t .mi_en\t\t\t(mi_mmu_en),\t\t // Templated
+\t\t .mi_we\t\t\t(mi_we),
+\t\t .mi_addr\t\t(mi_addr[14:0]),
+\t\t .mi_din\t\t(mi_din[DW-1:0]),
+\t\t .emesh_access_in\t(emesh_remap_access),\t // Templated
+\t\t .emesh_packet_in\t(emesh_remap_packet[PW-1:0])); // Templated
+   
+
+   /************************************************************/
+   /*EMAILBOX                                                  */
+   /************************************************************/
+   /*emailbox AUTO_TEMPLATE ( 
+    .mi_en              (mi_cfg_en),
+    .mi_dout            (mi_mailbox_dout[]),
+    .wr_clk\t\t(clk),
+    .rd_clk\t\t(clk),
+    .emesh_access\t(emmu_access),
+    .emesh_packet\t(emmu_packet[PW-1:0]),
+    );
+        */
+
+   defparam  erx_mailbox.ID=ID;   
+   emailbox erx_mailbox(
+\t\t\t/*AUTOINST*/
+\t\t\t// Outputs
+\t\t\t.mi_dout\t(mi_mailbox_dout[63:0]), // Templated
+\t\t\t.mailbox_full\t(mailbox_full),
+\t\t\t.mailbox_not_empty(mailbox_not_empty),
+\t\t\t// Inputs
+\t\t\t.reset\t\t(reset),
+\t\t\t.wr_clk\t\t(clk),\t\t\t // Templated
+\t\t\t.rd_clk\t\t(clk),\t\t\t // Templated
+\t\t\t.emesh_access\t(emmu_access),\t\t // Templated
+\t\t\t.emesh_packet\t(emmu_packet[PW-1:0]),\t // Templated
+\t\t\t.mi_en\t\t(mi_cfg_en),\t\t // Templated
+\t\t\t.mi_we\t\t(mi_we),
+\t\t\t.mi_addr\t(mi_addr[RFAW+1:0]),
+\t\t\t.mi_din\t\t(mi_din[63:0]));
+   
+   
+   /************************************************************/
+   /* CONFIGURATION INTERFACE                                  */
+   /************************************************************/
+   /*ecfg_if AUTO_TEMPLATE ( 
+    .wait_in\t\t(erx_cfg_wait),
+    .\\(.*\\)_in          (erx_cfg_\\1[]),
+    .\\(.*\\)_out         (ecfg_\\1[]),
+    .mi_dout0\t\t({32\'b0,mi_cfg_dout[31:0]}),
+    .mi_dout1\t\t({32\'b0,mi_dma_dout[31:0]}),
+    .mi_dout2\t\t({32\'b0,mi_mmu_dout[31:0]}),
+    .mi_dout3\t\t(mi_mailbox_dout[63:0]),
+    );
+    */
+   
+   defparam erx_cfgif.RX=1;
+   ecfg_if erx_cfgif (/*AUTOINST*/
+\t\t      // Outputs
+\t\t      .mi_mmu_en\t(mi_mmu_en),
+\t\t      .mi_dma_en\t(mi_dma_en),
+\t\t      .mi_cfg_en\t(mi_cfg_en),
+\t\t      .mi_we\t\t(mi_we),
+\t\t      .mi_addr\t\t(mi_addr[14:0]),
+\t\t      .mi_din\t\t(mi_din[63:0]),
+\t\t      .access_out\t(ecfg_access),\t\t // Templated
+\t\t      .packet_out\t(ecfg_packet[PW-1:0]),\t // Templated
+\t\t      // Inputs
+\t\t      .clk\t\t(clk),
+\t\t      .reset\t\t(reset),
+\t\t      .access_in\t(erx_cfg_access),\t // Templated
+\t\t      .packet_in\t(erx_cfg_packet[PW-1:0]), // Templated
+\t\t      .mi_dout0\t\t({32\'b0,mi_cfg_dout[31:0]}), // Templated
+\t\t      .mi_dout1\t\t({32\'b0,mi_dma_dout[31:0]}), // Templated
+\t\t      .mi_dout2\t\t({32\'b0,mi_mmu_dout[31:0]}), // Templated
+\t\t      .mi_dout3\t\t(mi_mailbox_dout[63:0]), // Templated
+\t\t      .wait_in\t\t(erx_cfg_wait));\t\t // Templated
+   
+   
+   /************************************************************/
+   /* ERX CONFIGURATION                                        */
+   /************************************************************/
+   /*erx_cfg AUTO_TEMPLATE (.mi_dout       (mi_cfg_dout[DW-1:0]),
+                            .mi_en\t   (mi_cfg_en),
+    );
+        */   
+   
+   assign rx_status[15:0] = {16\'b0};
+   assign gpio_datain[8:0]=9\'b0;
+   
+  /*
+   assign gpio_datain[8:0]= {rx_frame_par[0],
+\t\t\t     rx_data_par[7],
+\t\t\t     rx_data_par[6],
+\t\t\t     rx_data_par[5],
+\t\t\t     rx_data_par[4],
+\t\t\t     rx_data_par[3],
+\t\t\t     rx_data_par[2],
+\t\t\t     rx_data_par[1],
+\t\t\t     rx_data_par[0]
+\t\t\t     };
+   */
+   
+   erx_cfg erx_cfg (.rx_status    \t(rx_status[15:0]),
+\t\t    .timer_cfg\t\t(),
+\t\t     /*AUTOINST*/
+\t\t    // Outputs
+\t\t    .mi_dout\t\t(mi_cfg_dout[DW-1:0]),\t // Templated
+\t\t    .rx_enable\t\t(rx_enable),
+\t\t    .mmu_enable\t\t(mmu_enable),
+\t\t    .remap_mode\t\t(remap_mode[1:0]),
+\t\t    .remap_base\t\t(remap_base[31:0]),
+\t\t    .remap_pattern\t(remap_pattern[11:0]),
+\t\t    .remap_sel\t\t(remap_sel[11:0]),
+\t\t    // Inputs
+\t\t    .reset\t\t(reset),
+\t\t    .clk\t\t(clk),
+\t\t    .mi_en\t\t(mi_cfg_en),\t\t // Templated
+\t\t    .mi_we\t\t(mi_we),
+\t\t    .mi_addr\t\t(mi_addr[14:0]),
+\t\t    .mi_din\t\t(mi_din[31:0]),
+\t\t    .gpio_datain\t(gpio_datain[8:0]));
+    
+   
+   
+  
+   
+ 
+   
+   
+   /************************************************************/
+   /*ELINK DMA                                                 */
+   /************************************************************/
+   
+   /*edma AUTO_TEMPLATE (
+                         .mi_en\t\t(mi_dma_en),
+                         .edma_access\t(edma_access),   
+                         .mi_dout       (mi_dma_dout[DW-1:0]),
+                             
+                               );
+   */   
+   edma erx_dma(/*AUTOINST*/
+\t\t// Outputs
+\t\t.mi_dout\t\t(mi_dma_dout[DW-1:0]),\t // Templated
+\t\t.edma_access\t\t(edma_access),\t\t // Templated
+\t\t.edma_packet\t\t(edma_packet[PW-1:0]),
+\t\t// Inputs
+\t\t.reset\t\t\t(reset),
+\t\t.clk\t\t\t(clk),
+\t\t.mi_en\t\t\t(mi_dma_en),\t\t // Templated
+\t\t.mi_we\t\t\t(mi_we),
+\t\t.mi_addr\t\t(mi_addr[RFAW+1:0]),
+\t\t.mi_din\t\t\t(mi_din[63:0]),
+\t\t.edma_wait\t\t(edma_wait));
+   
+           
+
+\t\t\t\t 
+   /************************************************************/
+   /*ELINK RECEIVE DISTRIBUTOR (""DEMUX"")                       */
+   /*(figures out who RX transaction belongs to)               */
+   /********************1***************************************/
+   /*erx_arbiter AUTO_TEMPLATE ( 
+                        //Inputs
+                        .mmu_en\t\t(ecfg_rx_mmu_enable),
+                        .ecfg_wait\t(erx_cfg_wait),
+    )
+    */
+
+   defparam erx_arbiter.ID    = ID;
+   erx_arbiter erx_arbiter (.timeout\t(1\'b0),//TODO
+\t\t\t/*AUTOINST*/
+\t\t\t    // Outputs
+\t\t\t    .rx_rd_wait\t\t(rx_rd_wait),
+\t\t\t    .rx_wr_wait\t\t(rx_wr_wait),
+\t\t\t    .edma_wait\t\t(edma_wait),
+\t\t\t    .ecfg_wait\t\t(erx_cfg_wait),\t // Templated
+\t\t\t    .rxwr_access\t(rxwr_access),
+\t\t\t    .rxwr_packet\t(rxwr_packet[PW-1:0]),
+\t\t\t    .rxrd_access\t(rxrd_access),
+\t\t\t    .rxrd_packet\t(rxrd_packet[PW-1:0]),
+\t\t\t    .rxrr_access\t(rxrr_access),
+\t\t\t    .rxrr_packet\t(rxrr_packet[PW-1:0]),
+\t\t\t    // Inputs
+\t\t\t    .erx_rr_access\t(erx_rr_access),
+\t\t\t    .erx_packet\t\t(erx_packet[PW-1:0]),
+\t\t\t    .emmu_access\t(emmu_access),
+\t\t\t    .emmu_packet\t(emmu_packet[PW-1:0]),
+\t\t\t    .edma_access\t(edma_access),
+\t\t\t    .edma_packet\t(edma_packet[PW-1:0]),
+\t\t\t    .ecfg_access\t(ecfg_access),
+\t\t\t    .ecfg_packet\t(ecfg_packet[PW-1:0]),
+\t\t\t    .rxwr_wait\t\t(rxwr_wait),
+\t\t\t    .rxrd_wait\t\t(rxrd_wait),
+\t\t\t    .rxrr_wait\t\t(rxrr_wait));
+
+   
+endmodule // erx
+// Local Variables:
+// verilog-library-directories:(""."" ""../../emmu/hdl"" ""../../edma/hdl"" ""../../memory/hdl"" ""../../emailbox/hdl"")
+// End:
+
+/*
+ Copyright (C) 2014 Adapteva, Inc.
+  
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+"
+"module egen(/*AUTOARG*/
+   // Outputs
+   done, access_out, packet_out,
+   // Inputs
+   clk, reset, start, wait_in
+   );
+
+   parameter PW      = 104;
+   parameter AW      = 32;
+   parameter DW      = 32;
+   parameter MODE    = 0;    //read=0,write=1;
+   parameter SRC_ID  = 12\'h0;
+   parameter DST_ID  = 12\'h0;
+   parameter COUNT   = 16;
+   
+   //Clock and reset
+   input           clk;
+   input           reset;         
+
+   //Generator Control
+   input           start;        //start generator (edge)
+   output \t   done;
+   
+   //Transaction Output
+   output          access_out;
+   output [PW-1:0] packet_out;
+   input           wait_in;
+
+   //local
+   reg \t           access_reg;
+   reg \t           write_reg;
+   reg [1:0] \t   datamode_reg;
+   reg [3:0] \t   ctrlmode_reg;
+   reg [AW-1:0]    dstaddr_reg;
+   reg [DW-1:0]    data_reg;
+   reg [AW-1:0]    srcaddr_reg;
+   reg [31:0] \t   count;   
+   reg [1:0] \t   state;
+   wire \t   go;
+   wire \t   idle;
+   
+
+`define IDLE  2\'b00
+`define DONE  2\'b10
+`define GO    2\'b01
+   
+
+   assign done = (state[1:0]==`DONE);
+   assign go   = (state[1:0]==`GO);
+   assign idle = (state[1:0]==`IDLE);
+   
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       state[1:0] <= 2\'b00;//not started
+     else if(start & idle)
+       state[1:0] <= 2\'b01;//going
+     else if( ~(|count) & go)
+       state[1:0] <= 2\'b10;//done
+
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       count <= COUNT;
+     else if(state[1:0]==`GO)
+       count <= count - 1\'b1;
+      
+   always @ (posedge clk or posedge reset)
+     if(reset)
+       begin
+\t  srcaddr_reg[31:0]  <= SRC_ID<<20;
+\t  data_reg[31:0]     <= 0;
+\t  dstaddr_reg[31:0]  <= DST_ID<<20;\t  
+\t  ctrlmode_reg[3:0]  <= 4\'b0;
+\t  datamode_reg[1:0]  <= 2\'b10;
+\t  write_reg          <= MODE;
+\t  access_reg         <= 1\'b0;
+       end
+     else if (~wait_in & go)\t  
+       begin
+\t  access_reg         <= 1\'b1;
+
+\t  dstaddr_reg[31:0]  <= (dstaddr_reg[31:0]+ (1<<datamode_reg[1:0])) &
+\t                        32\'hFFF07FFF;
+
+\t  srcaddr_reg[31:0]  <= (srcaddr_reg[31:0]+ (1<<datamode_reg[1:0])) & 
+\t\t\t\t 32\'hFFF07FFF;
+
+\t  data_reg[31:0]     <= (data_reg[31:0]+1\'b1) & 
+\t\t\t\t32\'hFFF07FFF;
+       end // if (~wait_in & go)
+     else
+       begin
+\t  access_reg         <= 1\'b0;
+       end
+
+   assign access_out = access_reg;
+   
+   emesh2packet e2p (
+\t\t     // Outputs
+\t\t     .packet_out\t(packet_out[PW-1:0]),
+\t\t     // Inputs
+\t\t     .access_in\t\t(access_reg),
+\t\t     .write_in\t\t(write_reg),
+\t\t     .datamode_in\t(datamode_reg[1:0]),
+\t\t     .ctrlmode_in\t(ctrlmode_reg[3:0]),
+\t\t     .dstaddr_in\t(dstaddr_reg[AW-1:0]),
+\t\t     .data_in\t\t(data_reg[DW-1:0]),
+\t\t     .srcaddr_in\t(srcaddr_reg[AW-1:0]));
+   
+endmodule // egen
+// Local Variables:
+// verilog-library-directories:(""."" ""../../edma/hdl"" ""../../emesh/hdl"" )
+// End:
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+ 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+  
+
+   
+"
+"/* verilator lint_off WIDTH */
+module emesh_monitor(/*AUTOARG*/
+   // Inputs
+   clk, reset, itrace, etime, emesh_access, emesh_packet, emesh_wait
+   );
+   parameter AW     =  32;
+   parameter DW     =  32;
+   parameter NAME   =  ""cpu"";
+   parameter PW     = 104;
+   
+   
+   //BASIC INTERFACE
+   input            clk;
+   input            reset;
+   input            itrace;
+   input [31:0]     etime;
+   
+   //MESH TRANSCTION
+   input            emesh_access;
+   input [PW-1:0]   emesh_packet;   
+   input            emesh_wait;
+
+   //core name for trace
+   reg [63:0]      name=NAME;
+   reg [31:0] \t   ftrace;
+
+   initial
+     begin
+        ftrace  = $fopen({NAME,"".trace""}, ""w"");
+     end
+
+   always @ (posedge clk)
+     if(itrace & ~reset & emesh_access & ~emesh_wait)
+       begin\t     \t 
+\t  //$fwrite(ftrace, ""TIME=%h\
+"",etime[31:0]);
+\t  $fwrite(ftrace, ""%h_%h_%h_%h\
+"",emesh_packet[103:72], emesh_packet[71:40],emesh_packet[39:8],
+\t\t                          {emesh_packet[7:4],emesh_packet[3:2],emesh_packet[1],emesh_access});
+       end   
+endmodule // emesh_monitor
+
+
+/*
+ Copyright (C) 2014 Adapteva, Inc. 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+   
+"
+"/*
+ ########################################################################
+ Epiphany eLink AXI Master Module
+ ######################################################################## 
+
+  NOTES:
+ --write channels: write address, write data, write response
+ --read channels: read address, read data channel
+ --\'valid\' source signal used to show valid address,data,control is available
+ --\'ready\' destination  ready signal indicates readyness to accept information
+ --\'last\' signal indicates the transfer of final data item
+ --read and write have separate address channels
+ --read data channel carries read data from slave to master
+ --write channel includes a byte lane strobe signal for every eight data bits
+ --there is no acknowledge on write, treated as buffered 
+ --channels are unidirectional
+ --valid is asserted uncondotionally
+ --ready occurs cycle after valid
+ --there can be no combinatorial path between input and output of interface
+ --destination is permitted to wait for valud before asserting READY
+ --source is not allowed to wait for READY to assert VALID
+ --AWVALID must remain asserted until the rising clock edge after slave asserts AWREADY??
+ --The default state of AWREADY can be either HIGH or LOW. This specification recommends a default state of HIGH.
+ --During a write burst, the master can assert the WVALID signal only when it drives valid write data.
+ --The default state of WREADY can be HIGH, but only if the slave can always accept write data in a single cycle.
+ --The master must assert the WLAST signal while it is driving the final write transfer in the burst.
+
+ --_aw=write address channel
+ --_ar=read address channel
+ --_r=read data channel
+ --_w=write data channel
+ --_b=write response channel
+
+  */
+
+module emaxi(/*autoarg*/
+   // Outputs
+   rxwr_wait, rxrd_wait, txrr_access, txrr_packet, m_axi_awid,
+   m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
+   m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
+   m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
+   m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
+   m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
+   m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
+   // Inputs
+   rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, txrr_wait,
+   m_axi_aclk, m_axi_aresetn, m_axi_awready, m_axi_wready, m_axi_bid,
+   m_axi_bresp, m_axi_bvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
+   m_axi_rresp, m_axi_rlast, m_axi_rvalid
+   );
+
+   parameter IDW    = 12;
+   parameter PW     = 104;
+   parameter AW     = 32;
+   parameter DW     = 32;
+
+   //########################
+   //ELINK INTERFACE
+   //########################
+
+   
+   //Write request from erx
+   input \t       rxwr_access;
+   input [PW-1:0]      rxwr_packet;   
+   output \t       rxwr_wait;
+   
+   //Read request from erx
+   input \t       rxrd_access;
+   input [PW-1:0]      rxrd_packet;
+   output \t       rxrd_wait;
+   
+   //Read respoonse for etx
+   output \t       txrr_access;
+   output [PW-1:0]     txrr_packet;
+   input \t       txrr_wait;
+
+   //########################
+   //AXI MASTER INTERFACE
+   //########################
+
+   input  \t       m_axi_aclk;    // global clock signal.
+   input  \t       m_axi_aresetn; // global reset singal.
+
+   //Write address channel
+   output [IDW-1:0]    m_axi_awid;    // write address ID
+   output [31 : 0]     m_axi_awaddr;  // master interface write address   
+   output [7 : 0]      m_axi_awlen;   // burst length.
+   output [2 : 0]      m_axi_awsize;  // burst size.
+   output [1 : 0]      m_axi_awburst; // burst type.
+   output [1 : 0]      m_axi_awlock;  // lock type   
+   output [3 : 0]      m_axi_awcache; // memory type.
+   output [2 : 0]      m_axi_awprot;  // protection type.
+   output [3 : 0]      m_axi_awqos;   // quality of service
+   output \t       m_axi_awvalid; // write address valid
+   input \t       m_axi_awready; // write address ready
+
+   //Write data channel
+   output [IDW-1:0]    m_axi_wid;     
+   output [63 : 0]     m_axi_wdata;   // master interface write data.
+   output [7 : 0]      m_axi_wstrb;   // byte write strobes
+   output \t       m_axi_wlast;   // indicates last transfer in a write burst.
+   output \t       m_axi_wvalid;  // indicates data is ready to go
+   input \t       m_axi_wready;  // indicates that the slave is ready for data
+
+   //Write response channel
+   input [IDW-1:0]     m_axi_bid;
+   input [1 : 0]       m_axi_bresp;   // status of the write transaction.
+   input \t       m_axi_bvalid;  // channel is signaling a valid write response
+   output \t       m_axi_bready;  // master can accept write response.
+
+   //Read address channel
+   output [IDW-1:0]    m_axi_arid;    // read address ID
+   output [31 : 0]     m_axi_araddr;  // initial address of a read burst
+   output [7 : 0]      m_axi_arlen;   // burst length
+   output [2 : 0]      m_axi_arsize;  // burst size
+   output [1 : 0]      m_axi_arburst; // burst type
+   output [1 : 0]      m_axi_arlock;  //lock type   
+   output [3 : 0]      m_axi_arcache; // memory type
+   output [2 : 0]      m_axi_arprot;  // protection type
+   output [3 : 0]      m_axi_arqos;   // 
+   output \t       m_axi_arvalid; // valid read address and control information
+   input \t       m_axi_arready; // slave is ready to accept an address
+
+   //Read data channel   
+   input [IDW-1:0]     m_axi_rid; 
+   input [63 : 0]      m_axi_rdata;   // master read data
+   input [1 : 0]       m_axi_rresp;   // status of the read transfer
+   input \t       m_axi_rlast;   // signals last transfer in a read burst
+   input \t       m_axi_rvalid;  // signaling the required read data
+   output \t       m_axi_rready;  // master can accept the readback data
+  
+
+   //#########################################################################
+   //REGISTER/WIRE DECLARATIONS
+   //#########################################################################
+   reg [31 : 0]        m_axi_awaddr;
+   reg [7:0] \t       m_axi_awlen;
+   reg [2:0] \t       m_axi_awsize;
+   reg \t\t       m_axi_awvalid;
+   reg [63 : 0]        m_axi_wdata;
+   reg [63 : 0]     m_axi_rdata_reg;
+   reg [7 : 0] \t       m_axi_wstrb;
+   reg \t\t       m_axi_wlast;
+   reg \t\t       m_axi_wvalid;
+   reg \t\t       awvalid_b;
+   reg [31:0] \t       awaddr_b;
+   reg [2:0] \t       awsize_b;
+   reg [7:0] \t       awlen_b;
+   reg \t\t       wvalid_b;
+   reg [63:0] \t       wdata_b;
+   reg [7:0] \t       wstrb_b;
+   reg [63 : 0]        wdata_aligned;
+   reg [7 : 0] \t       wstrb_aligned;
+   
+   reg \t\t       txrr_access;
+   reg \t\t       txrr_access_reg;
+   reg [31:0] \t       txrr_data;
+   reg [31:0] \t       txrr_srcaddr;
+   
+   //wires
+   wire \t       aw_go;
+   wire \t       w_go;
+   wire \t       readinfo_wren;
+   wire \t       readinfo_full;
+   wire [47:0] \t       readinfo_out;
+   wire [47:0] \t       readinfo_in;
+
+   wire \t       awvalid_in;
+   
+   wire [1:0] \t       rxwr_datamode;
+   wire [AW-1:0]       rxwr_dstaddr;
+   wire [DW-1:0]       rxwr_data;
+   wire [AW-1:0]       rxwr_srcaddr;
+
+   wire [1:0] \t       rxrd_datamode;
+   wire [3:0] \t       rxrd_ctrlmode;
+   wire [AW-1:0]       rxrd_dstaddr;
+   wire [AW-1:0]       rxrd_srcaddr;
+
+   wire [1:0] \t       txrr_datamode;
+   wire [3:0] \t       txrr_ctrlmode;
+   wire [31:0] \t       txrr_dstaddr;
+   
+   //#########################################################################
+   //EMESH 2 PACKET CONVERSION
+   //#########################################################################
+
+   //RXWR
+   packet2emesh p2e_rxwr (
+\t\t\t  // Outputs
+\t\t\t  .access_out\t\t(),
+\t\t\t  .write_out\t\t(),
+\t\t\t  .datamode_out\t\t(rxwr_datamode[1:0]),
+\t\t\t  .ctrlmode_out\t\t(),
+\t\t\t  .dstaddr_out\t\t(rxwr_dstaddr[AW-1:0]),
+\t\t\t  .data_out\t\t(rxwr_data[DW-1:0]),
+\t\t\t  .srcaddr_out\t\t(rxwr_srcaddr[AW-1:0]),
+\t\t\t  // Inputs
+\t\t\t  .packet_in\t\t(rxwr_packet[PW-1:0])
+\t\t\t  );
+   
+   //RXRD
+   packet2emesh p2e_rxrd (
+\t\t\t  // Outputs
+\t\t\t  .access_out\t\t(),
+\t\t\t  .write_out\t\t(),
+\t\t\t  .datamode_out\t\t(rxrd_datamode[1:0]),
+\t\t\t  .ctrlmode_out\t\t(rxrd_ctrlmode[3:0]),
+\t\t\t  .dstaddr_out\t\t(rxrd_dstaddr[AW-1:0]),
+\t\t\t  .data_out\t\t(),
+\t\t\t  .srcaddr_out\t\t(rxrd_srcaddr[AW-1:0]),
+\t\t\t  // Inputs
+\t\t\t  .packet_in\t\t(rxrd_packet[PW-1:0])
+\t\t\t  );
+
+   //TXRR
+   emesh2packet e2p (
+\t\t     // Outputs
+\t\t     .packet_out\t(txrr_packet[PW-1:0]),
+\t\t     // Inputs
+\t\t     .access_in\t\t(txrr_access),
+\t\t     .write_in\t\t(1\'b1),
+\t\t     .datamode_in\t(txrr_datamode[1:0]),
+\t\t     .ctrlmode_in\t(txrr_ctrlmode[3:0]),
+\t\t     .dstaddr_in\t(txrr_dstaddr[AW-1:0]),
+\t\t     .data_in\t\t(txrr_data[DW-1:0]),
+\t\t     .srcaddr_in\t(txrr_srcaddr[AW-1:0])
+\t\t     );
+   \t\t\t    
+   //#########################################################################
+   //AXI unimplemented constants
+   //#########################################################################
+
+   assign m_axi_awburst[1:0]\t= 2\'b01; //only increment burst supported
+   assign m_axi_awcache[3:0]\t= 4\'b0000;//TODO: correct value??
+   assign m_axi_awprot[2:0]\t= 3\'b000;
+   assign m_axi_awqos[3:0]\t= 4\'b0000;
+   assign m_axi_awlock          = 2\'b00;
+
+   assign m_axi_arburst[1:0]\t= 2\'b01; //only increment burst supported
+   assign m_axi_arcache[3:0]\t= 4\'b0000;
+   assign m_axi_arprot[2:0]\t= 3\'h0;
+   assign m_axi_arqos[3:0]\t= 4\'h0;
+
+   assign m_axi_bready    \t= 1\'b1;//tie to wait signal????   
+   
+   //#########################################################################
+   //Write address channel
+   //#########################################################################
+
+   assign aw_go       = m_axi_awvalid & m_axi_awready;
+   assign w_go        = m_axi_wvalid  & m_axi_wready;
+   assign rxwr_wait   = awvalid_b   | wvalid_b;
+   assign awvalid_in  = rxwr_access & ~awvalid_b & ~wvalid_b;
+   
+   // generate write-address signals
+   always @( posedge m_axi_aclk )     
+     if(~m_axi_aresetn) 
+       begin
+          m_axi_awvalid      <= 1\'b0;
+          m_axi_awaddr[31:0] <= 32\'d0;
+          m_axi_awlen[7:0]   <= 8\'d0;
+          m_axi_awsize[2:0]  <= 3\'d0;\t  
+          awvalid_b          <= 1\'b0;
+          awaddr_b           <= \'d0;
+          awlen_b[7:0]       <= \'d0;
+          awsize_b[2:0]      <= \'d0;
+       end 
+     else 
+       begin
+          if( ~m_axi_awvalid | aw_go ) 
+\t    begin
+               if( awvalid_b ) 
+\t\t begin
+\t\t    m_axi_awvalid       <= 1\'b1;
+\t\t    m_axi_awaddr[31:0]  <= awaddr_b[31:0];
+\t\t    m_axi_awlen[7:0]    <= awlen_b[7:0];
+\t\t    m_axi_awsize[2:0]   <= awsize_b[2:0];
+\t\t end 
+\t      else 
+\t\tbegin
+\t\t   m_axi_awvalid       <= awvalid_in;
+\t\t   m_axi_awaddr[31:0]  <= rxwr_dstaddr[31:0];
+\t\t   m_axi_awlen[7:0]    <= 8\'b0;
+\t\t   m_axi_awsize[2:0]   <= { 1\'b0, rxwr_datamode[1:0]};
+\t\tend
+\t    end
+          if( awvalid_in & m_axi_awvalid & ~aw_go )
+            awvalid_b <= 1\'b1;
+          else if( aw_go )
+            awvalid_b <= 1\'b0;
+          
+\t //Pipeline stage
+         if( awvalid_in )
+\t   begin
+              awaddr_b[31:0]  <= rxwr_dstaddr[31:0];
+              awlen_b[7:0]    <= 8\'b0;
+              awsize_b[2:0]   <= { 1\'b0, rxwr_datamode[1:0] };
+         end        
+       end // else: !if(~m_axi_aresetn)
+   
+   //#########################################################################
+   //Write data alignment circuit
+   //#########################################################################
+
+   always @*
+     case( rxwr_datamode[1:0] )        
+       2\'d0:    wdata_aligned[63:0] = { 8{rxwr_data[7:0]}};
+       2\'d1:    wdata_aligned[63:0] = { 4{rxwr_data[15:0]}};
+       2\'d2:    wdata_aligned[63:0] = { 2{rxwr_data[31:0]}};
+       default: wdata_aligned[63:0] = { rxwr_srcaddr[31:0], rxwr_data[31:0]};
+     endcase
+
+   always @*
+     begin
+\tcase(rxwr_datamode[1:0])
+          2\'d0: // byte
+            case(rxwr_dstaddr[2:0])
+              3\'d0:    wstrb_aligned[7:0] = 8\'h01;
+              3\'d1:    wstrb_aligned[7:0] = 8\'h02;
+              3\'d2:    wstrb_aligned[7:0] = 8\'h04;
+              3\'d3:    wstrb_aligned[7:0] = 8\'h08;
+              3\'d4:    wstrb_aligned[7:0] = 8\'h10;
+              3\'d5:    wstrb_aligned[7:0] = 8\'h20;
+              3\'d6:    wstrb_aligned[7:0] = 8\'h40;
+              default: wstrb_aligned[7:0] = 8\'h80;
+            endcase
+          2\'d1: // 16b hword
+            case(rxwr_dstaddr[2:1])
+              2\'d0:    wstrb_aligned[7:0] = 8\'h03;
+              2\'d1:    wstrb_aligned[7:0] = 8\'h0c;
+              2\'d2:    wstrb_aligned[7:0] = 8\'h30;
+              default: wstrb_aligned[7:0] = 8\'hc0;
+            endcase
+          2\'d2: // 32b word
+            if(rxwr_dstaddr[2])
+\t      wstrb_aligned[7:0] = 8\'hf0;
+            else
+\t      wstrb_aligned[7:0] = 8\'h0f;
+\t  2\'d3: 
+\t    wstrb_aligned[7:0] = 8\'hff;
+\tendcase // case (emwr_datamode[1:0])
+     end // always @ *
+
+   //#########################################################################
+   //Write data channel
+   //#########################################################################
+
+   always @ (posedge m_axi_aclk )
+     if(~m_axi_aresetn) 
+       begin\t  
+\t  m_axi_wvalid      <= 1\'b0;
+          m_axi_wdata[63:0] <= 64\'b0;
+          m_axi_wstrb[7:0]  <= 8\'b0;
+          m_axi_wlast       <= 1\'b1; // TODO:bursts!!\t  
+          wvalid_b          <= 1\'b0;
+          wdata_b[63:0]     <= 64\'b0;
+          wstrb_b[7:0]      <= 8\'b0;         
+       end 
+     else 
+       begin
+          if( ~m_axi_wvalid | w_go ) 
+\t    begin
+            if( wvalid_b ) 
+\t      begin
+\t\t m_axi_wvalid       <= 1\'b1;
+\t\t m_axi_wdata[63:0]  <= wdata_b[63:0];
+\t\t m_axi_wstrb[7:0]   <= wstrb_b[7:0];
+              end 
+\t    else 
+\t      begin
+\t\t m_axi_wvalid       <= awvalid_in;
+\t\t m_axi_wdata[63:0]  <= wdata_aligned[63:0];
+\t\t m_axi_wstrb[7:0]   <= wstrb_aligned[7:0];
+              end
+            end // if ( ~axi_wvalid | w_go )
+
+         if( rxwr_access & m_axi_wvalid & ~w_go )
+           wvalid_b <= 1\'b1;
+         else if( w_go )
+           wvalid_b <= 1\'b0;
+\t  
+          if( awvalid_in ) 
+\t    begin
+               wdata_b[63:0] <= wdata_aligned[63:0];
+               wstrb_b[7:0]  <= wstrb_aligned[7:0];
+            end
+       end // else: !if(~m_axi_aresetn)
+   
+   //#########################################################################
+   //Read request channel
+   //#########################################################################
+   //1. read request comes in on ar channel
+   //2. use src address to match with writes coming back
+   //3. Assumes in order returns
+   
+   assign  readinfo_in[47:0] = 
+               {
+\t\t7\'b0,
+                rxrd_srcaddr[31:0],//40:9
+                rxrd_dstaddr[2:0], //8:6
+                rxrd_ctrlmode[3:0], //5:2
+                rxrd_datamode[1:0]
+                };
+   
+   fifo_sync 
+     #(
+       // parameters
+       .AW                              (5),
+       .DW                              (48)) 
+   fifo_readinfo_i
+     (
+      // outputs
+      .rd_data                          (readinfo_out[47:0]),
+      .rd_empty                         (),
+      .wr_full                          (readinfo_full),
+      // inputs
+      .clk                              (m_axi_aclk),
+      .reset                            (~m_axi_aresetn),
+      .wr_data                          (readinfo_in[47:0]),
+      .wr_en                            (m_axi_arvalid & m_axi_arready),
+      .rd_en                            (m_axi_rready & m_axi_rvalid)
+      );
+
+   assign txrr_datamode[1:0]  = readinfo_out[1:0];
+   assign txrr_ctrlmode[3:0]  = readinfo_out[5:2];
+   assign txrr_dstaddr[31:0]  = readinfo_out[40:9];
+
+   //#########################################################################
+   //Read address channel
+   //#########################################################################
+   
+   assign    m_axi_araddr[31:0]   = rxrd_dstaddr[31:0];
+   assign    m_axi_arsize[2:0]    = {1\'b0, rxrd_datamode[1:0]};
+   assign    m_axi_arlen[7:0]     = 8\'d0;
+   assign    m_axi_arvalid        = rxrd_access & ~readinfo_full;
+   assign    rxrd_wait            = m_axi_arvalid & ~m_axi_arready;
+   
+   //#########################################################################
+   //Read response channel
+   //#########################################################################
+
+   assign m_axi_rready  = ~txrr_wait; //pass through
+
+   always @( posedge m_axi_aclk )
+       if ( ~m_axi_aresetn )
+           m_axi_rdata_reg <= \'b0;
+       else
+           m_axi_rdata_reg <= m_axi_rdata;
+
+   
+   always @( posedge m_axi_aclk )
+     if( ~m_axi_aresetn ) 
+       begin      
+\t  txrr_data[31:0]     <= 32\'b0;
+\t  txrr_srcaddr[31:0]  <= 32\'b0;
+\t  txrr_access_reg     <= 1\'b0;
+\t  txrr_access         <= 1\'b0;         
+      end 
+     else 
+       begin
+          txrr_access_reg     <= m_axi_rready & m_axi_rvalid;
+\t  txrr_access         <= txrr_access_reg;//added pipeline stage for data 
+\t  // steer read data according to size & host address lsbs
+\t  //all data needs to be right aligned
+\t  //(this is due to the Epiphany right aligning all words)
+\t  case(readinfo_out[1:0])//datamode
+            2\'d0:  // byte read
+              case(readinfo_out[8:6])
+\t\t3\'d0:     txrr_data[7:0] <= m_axi_rdata_reg[7:0];
+\t\t3\'d1:     txrr_data[7:0] <= m_axi_rdata_reg[15:8];
+\t\t3\'d2:     txrr_data[7:0] <= m_axi_rdata_reg[23:16];
+\t\t3\'d3:     txrr_data[7:0] <= m_axi_rdata_reg[31:24];
+\t\t3\'d4:     txrr_data[7:0] <= m_axi_rdata_reg[39:32];
+\t\t3\'d5:     txrr_data[7:0] <= m_axi_rdata_reg[47:40];
+\t\t3\'d6:     txrr_data[7:0] <= m_axi_rdata_reg[55:48];
+\t\tdefault:  txrr_data[7:0] <= m_axi_rdata_reg[63:56];
+              endcase\t    
+            2\'d1:  // 16b hword
+              case( readinfo_out[8:7] )
+\t\t2\'d0:    txrr_data[15:0] <= m_axi_rdata_reg[15:0];
+\t\t2\'d1:    txrr_data[15:0] <= m_axi_rdata_reg[31:16];
+\t\t2\'d2:    txrr_data[15:0] <= m_axi_rdata_reg[47:32];
+\t\tdefault: txrr_data[15:0] <= m_axi_rdata_reg[63:48];
+              endcase
+            2\'d2:  // 32b word
+              if( readinfo_out[8] )
+               txrr_data[31:0] <= m_axi_rdata_reg[63:32];
+             else
+               txrr_data[31:0] <= m_axi_rdata_reg[31:0];
+           // 64b word already defined by defaults above
+           2\'d3: 
+\t     begin // 64b dword
+\t\ttxrr_data[31:0]  <= m_axi_rdata_reg[31:0];
+\t\ttxrr_srcaddr[31:0]  <= m_axi_rdata_reg[63:32];
+             end
+         endcase         
+       end // else: !if( ~m_axi_aresetn )
+   
+endmodule // emaxi
+// Local Variables:
+// verilog-library-directories:(""."" ""../../emesh/hdl"" ""../../memory/hdl"")
+// End:
+
+/*
+ copyright (c) 2014 adapteva, inc.
+ contributed by fred huettig <fred@adapteva.com>
+ contributed by andreas olofsson <andreas@adapteva.com>
+ 
+ this program is free software: you can redistribute it and/or modify
+ it under the terms of the gnu general public license as published by
+ the free software foundation, either version 3 of the license, or
+ (at your option) any later version.
+ 
+ this program is distributed in the hope that it will be useful,
+ but without any warranty; without even the implied warranty of
+ merchantability or fitness for a particular purpose.  see the
+ gnu general public license for more details.
+ 
+ you should have received a copy of the gnu general public license
+ along with this program (see the file copying).  if not, see
+ <http://www.gnu.org/licenses/>.
+ */
+"
+"/*
+ ########################################################################
+ ELINK TX CONFIGURATION REGISTER FILE
+ ######################################################################## 
+ */
+`include ""elink_regmap.v""
+module etx_cfg (/*AUTOARG*/
+   // Outputs
+   mi_dout, tx_enable, mmu_enable, gpio_enable, remap_enable,
+   gpio_data, ctrlmode, ctrlmode_bypass,
+   // Inputs
+   reset, clk, mi_en, mi_we, mi_addr, mi_din, tx_status
+   );
+
+   /******************************/
+   /*Compile Time Parameters     */
+   /******************************/
+   parameter PW               = 104;   
+   parameter RFAW             = 6;
+   parameter DEFAULT_VERSION  = 16\'h0000;
+
+   /******************************/
+   /*HARDWARE RESET (EXTERNAL)   */
+   /******************************/
+   input \t reset;             
+   input \t clk;
+
+   /*****************************/
+   /*SIMPLE MEMORY INTERFACE    */
+   /*****************************/    
+   input \t     mi_en;         
+   input \t     mi_we;            
+   input [RFAW+1:0]  mi_addr;       // complete address (no shifting!)
+   input [31:0]      mi_din;        // (lower 2 bits not used)
+   output [31:0]     mi_dout;   
+   
+   /*****************************/
+   /*ELINK CONTROL SIGNALS      */
+   /*****************************/
+   //tx (static configs)
+   output \t   tx_enable;      // enable signal for TX  
+   output \t   mmu_enable;     // enables MMU on transmit path  
+   output \t   gpio_enable;    // forces TX output pins to constants
+   output \t   remap_enable;   // enable address remapping
+   input [15:0]    tx_status;      // etx status signals
+   
+   //sampled by tx_lclk (test)
+   output [8:0]    gpio_data;      // data for elink outputs (static)   
+
+   //dynamic (control timing by use mode)
+   output [3:0]    ctrlmode;        // value for emesh ctrlmode tag
+   output          ctrlmode_bypass; // selects ctrlmode
+
+   //registers
+   reg [15:0] \t   ecfg_version_reg;
+   reg [10:0] \t   ecfg_tx_config_reg;
+   reg [8:0] \t   ecfg_tx_gpio_reg;
+   reg [2:0] \t   ecfg_tx_status_reg;
+   reg [31:0] \t   mi_dout;
+   reg \t\t   ecfg_access;
+   
+   //wires
+   wire \t   ecfg_read;
+   wire \t   ecfg_write;
+   wire \t   ecfg_tx_config_write;
+   wire \t   ecfg_tx_gpio_write;
+   wire \t   ecfg_tx_test_write;
+   wire \t   ecfg_tx_addr_write;
+   wire \t   ecfg_tx_data_write;
+   wire \t   loop_mode;
+   
+   /*****************************/
+   /*ADDRESS DECODE LOGIC       */
+   /*****************************/
+
+   //read/write decode
+   assign ecfg_write  = mi_en &  mi_we;
+   assign ecfg_read   = mi_en & ~mi_we;   
+
+   //Config write enables 
+   assign ecfg_version_write   = ecfg_write & (mi_addr[RFAW+1:2]==`E_VERSION);
+   assign ecfg_tx_config_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_CFG);
+   assign ecfg_tx_status_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_STATUS);
+   assign ecfg_tx_gpio_write   = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_GPIO);
+  
+   //###########################
+   //# TX CONFIG
+   //###########################
+   always @ (posedge clk)
+     if(reset)
+       ecfg_tx_config_reg[10:0] <= 11\'b0;
+     else if (ecfg_tx_config_write)
+       ecfg_tx_config_reg[10:0] <= mi_din[10:0];
+
+   assign tx_enable       = 1\'b1;//TODO: fix! ecfg_tx_config_reg[0];
+   assign mmu_enable      = ecfg_tx_config_reg[1];   
+   assign remap_enable    = ecfg_tx_config_reg[3:2]==2\'b01;
+   assign ctrlmode[3:0]   = ecfg_tx_config_reg[7:4];
+   assign ctrlmode_bypass = ecfg_tx_config_reg[8];
+   assign gpio_enable     = (ecfg_tx_config_reg[10:9]==2\'b01);
+
+   //###########################
+   //# STATUS REGISTER
+   //###########################   
+   always @ (posedge clk)
+     if(reset)
+       ecfg_tx_status_reg[2:0] <= \'d0;
+     else
+       ecfg_tx_status_reg[2:0]<= ecfg_tx_status_reg[2:0] | tx_status[2:0];
+
+   //###########################
+   //# GPIO DATA
+   //###########################
+   always @ (posedge clk)
+     if(reset)
+       ecfg_tx_gpio_reg[8:0] <= \'d0;   
+     else if (ecfg_tx_gpio_write)
+       ecfg_tx_gpio_reg[8:0] <= mi_din[8:0];
+
+   assign gpio_data[8:0] = ecfg_tx_gpio_reg[8:0];
+
+   
+   
+   //###########################
+   //# VERSION
+   //###########################
+   always @ (posedge clk)
+     if(reset)
+       ecfg_version_reg[15:0] <= DEFAULT_VERSION;
+     else if (ecfg_version_write)
+       ecfg_version_reg[15:0] <= mi_din[15:0];       
+
+   //###############################
+   //# DATA READBACK MUX
+   //###############################
+   //Pipelineing readback
+   always @ (posedge clk)
+     if(ecfg_read)
+       case(mi_addr[RFAW+1:2])
+         `ETX_CFG:    mi_dout[31:0] <= {21\'b0, ecfg_tx_config_reg[10:0]};
+         `ETX_GPIO:   mi_dout[31:0] <= {23\'b0, ecfg_tx_gpio_reg[8:0]};
+\t `ETX_STATUS: mi_dout[31:0] <= {16\'b0, tx_status[15:3],ecfg_tx_status_reg[2:0]};
+         `E_VERSION:  mi_dout[31:0] <= {16\'b0, ecfg_version_reg[15:0]};
+         default:     mi_dout[31:0] <= 32\'d0;
+       endcase // case (mi_addr[RFAW+1:2])
+     else
+       mi_dout[31:0] <= 32\'d0;
+
+endmodule // ecfg_tx
+
+
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+ 
+   This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.This program is distributed in the hope 
+  that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details. You should have received a copy 
+  of the GNU General Public License along with this program (see the file 
+  COPYING).  If not, see <http://www.gnu.org/licenses/>.
+*/
+"
+"/*
+ ########################################################################
+ EPIPHANY eMesh Arbiter
+ ########################################################################
+ 
+ This block takes three FIFO inputs (write, read request, read response)
+ and the DMA channel, arbitrates between the active channels, and forwards 
+ the result to the transmit output pins.
+ 
+ Arbitration Priority:
+ 1) host writes (highest)
+ 2) read requests from host
+ 3) read responses
+
+ */
+
+module etx_arbiter (/*AUTOARG*/
+   // Outputs
+   txwr_wait, txrd_wait, txrr_wait, etx_access, etx_packet, etx_rr,
+   // Inputs
+   clk, reset, txwr_access, txwr_packet, txrd_access, txrd_packet,
+   txrr_access, txrr_packet, etx_rd_wait, etx_wr_wait, etx_cfg_wait,
+   ctrlmode_bypass, ctrlmode
+   );
+
+   parameter PW = 104;
+   parameter ID = 0;
+   
+   //tx clock and reset
+   input          clk;
+   input          reset;
+
+   //Write Request (from slave)
+   input \t   txwr_access;
+   input [PW-1:0]  txwr_packet;
+   output          txwr_wait;
+   
+   //Read Request (from slave)
+   input \t   txrd_access;
+   input [PW-1:0]  txrd_packet;
+   output          txrd_wait;
+   
+   //Read Response (from master)
+   input \t   txrr_access;
+   input [PW-1:0]  txrr_packet;
+   output          txrr_wait;
+
+   //Wait signal inputs
+   input           etx_rd_wait;
+   input           etx_wr_wait;
+   input \t   etx_cfg_wait;
+   
+   //ctrlmode for rd/wr transactions
+   input \t   ctrlmode_bypass;
+   input [3:0] \t   ctrlmode;
+   
+   //Transaction for IO protocol
+   output          etx_access;
+   output [PW-1:0] etx_packet;
+   output \t   etx_rr;      //bypass translation on read response
+    
+   //regs
+   reg \t\t   etx_access;
+   reg [PW-1:0]    etx_packet;
+   reg \t\t   etx_rr;     //bypass translation on read response
+   
+   //wires  
+   wire [3:0] \t   txrd_ctrlmode;
+   wire [3:0] \t   txwr_ctrlmode;
+   wire \t   access_in;   
+   wire [PW-1:0]   etx_packet_mux;
+   wire \t   txrr_grant;
+   wire \t   txrd_grant;
+   wire \t   txwr_grant;
+   wire \t   txrr_arb_wait;
+   wire \t   txrd_arb_wait;
+   wire \t   txwr_arb_wait;
+   wire [PW-1:0]   txrd_data;
+   wire [PW-1:0]   txwr_data;
+   wire [PW-1:0]   etx_mux;
+   wire            write_in;
+
+   //##########################################################################
+   //# Insert special control mode
+   //##########################################################################
+   assign txrd_ctrlmode[3:0] =  ctrlmode_bypass ?  ctrlmode[3:0] : 
+\t\t\t\t                   txrd_packet[7:4];
+
+   assign txrd_data[PW-1:0] = {txrd_packet[PW-1:8],   
+                               txrd_ctrlmode[3:0], 
+\t\t\t       txrd_packet[3:0]};
+ 
+   
+   assign txwr_ctrlmode[3:0] =  ctrlmode_bypass ?  ctrlmode[3:0] : 
+\t\t\t\t                   txwr_packet[7:4];
+
+   assign txwr_data[PW-1:0] = {txwr_packet[PW-1:8],   
+                               txwr_ctrlmode[3:0], 
+\t\t\t       txwr_packet[3:0]};
+ 
+   //##########################################################################
+   //# Arbiter
+   //##########################################################################
+  
+   
+   arbiter_priority #(.ARW(3)) arbiter (.grant({txrr_grant,\t
+\t\t\t\t\t\ttxrd_grant,
+\t\t\t\t\t\ttxwr_grant //highest priority
+\t\t\t\t\t\t}),
+\t\t\t\t        .await({txrr_arb_wait,\t
+\t\t\t\t\t\ttxrd_arb_wait,
+\t\t\t\t\t\ttxwr_arb_wait
+\t\t\t\t\t\t}),\t
+\t\t\t\t\t.request({txrr_access,\t
+\t\t\t\t\t\t  txrd_access,
+\t\t\t\t\t\t  txwr_access
+\t\t\t\t\t\t  })\t
+\t\t\t\t  );
+   //Priority Mux
+   assign etx_mux[PW-1:0] =({(PW){txwr_grant}} & txwr_data[PW-1:0]) |
+\t\t\t   ({(PW){txrd_grant}} & txrd_data[PW-1:0]) |
+\t\t\t   ({(PW){txrr_grant}} & txrr_packet[PW-1:0]);
+ 
+   //######################################################################
+   //Pushback (stall) Signals
+   //######################################################################
+   
+   //Write waits on pin wr wait or cfg_wait
+   assign txwr_wait = etx_wr_wait | 
+\t\t      etx_cfg_wait;
+   
+   //Host read request (self throttling, one read at a time)
+   assign txrd_wait = etx_rd_wait | 
+\t\t      etx_cfg_wait | 
+\t\t      txrd_arb_wait;
+   //Read response
+   assign txrr_wait = etx_wr_wait | 
+\t\t      etx_cfg_wait | 
+\t\t      txrr_arb_wait;
+
+ 
+   //#####################################################################
+   //# Pipeline stage (arbiter+mux takes time..)
+   //#####################################################################
+   assign access_in = (txwr_grant & ~txwr_wait) |
+\t\t      (txrd_grant & ~txrd_wait) |
+\t\t      (txrr_grant & ~txrr_wait);
+
+   //Pipeline + stall
+   assign write_in = etx_mux[1];
+
+   //access
+    always @ (posedge clk)
+      if (reset)
+\tbegin
+\t   etx_access         <= 1\'b0;   
+\t   etx_rr            <= 1\'b0;\t   
+\tend
+      else if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
+\tbegin
+\t   etx_access         <= access_in;
+\t   etx_rr             <= txrr_grant;
+\tend\t   
+
+   //packet
+   always @ (posedge clk)
+     if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
+\t  etx_packet[PW-1:0] <= etx_mux[PW-1:0];\t 
+   
+endmodule // etx_arbiter
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+
+
+/*
+  Copyright (C) 2015 Adapteva, Inc.
+  Contributed by Andreas Olofsson <andreas@adapteva.com>
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program (see the file COPYING).  If not, see
+  <http://www.gnu.org/licenses/>.
+*/
+"
+"module MMCME2_ADV # (
+\t\t     parameter BANDWIDTH = ""OPTIMIZED"",
+\t\t     parameter real CLKFBOUT_MULT_F = 5.000,
+\t\t     parameter real CLKFBOUT_PHASE = 0.000,
+\t\t     parameter CLKFBOUT_USE_FINE_PS = ""FALSE"",
+\t\t     parameter real CLKIN1_PERIOD = 10.000,
+\t\t     parameter real CLKIN2_PERIOD = 0.000,
+\t\t     parameter real CLKOUT0_DIVIDE_F = 1.000,
+\t\t     parameter real CLKOUT0_DUTY_CYCLE = 0.500,
+\t\t     parameter real CLKOUT0_PHASE = 0.000,
+\t\t     parameter CLKOUT0_USE_FINE_PS = ""FALSE"",
+\t\t     parameter integer CLKOUT1_DIVIDE = 1,
+\t\t     parameter real CLKOUT1_DUTY_CYCLE = 0.500,
+\t\t     parameter real CLKOUT1_PHASE = 0.000,
+\t\t     parameter CLKOUT1_USE_FINE_PS = ""FALSE"",
+\t\t     parameter integer CLKOUT2_DIVIDE = 1,
+\t\t     parameter real CLKOUT2_DUTY_CYCLE = 0.500,
+\t\t     parameter real CLKOUT2_PHASE = 0.000,
+\t\t     parameter CLKOUT2_USE_FINE_PS = ""FALSE"",
+\t\t     parameter integer CLKOUT3_DIVIDE = 1,
+\t\t     parameter real CLKOUT3_DUTY_CYCLE = 0.500,
+\t\t     parameter real CLKOUT3_PHASE = 0.000,
+\t\t     parameter CLKOUT3_USE_FINE_PS = ""FALSE"",
+\t\t     parameter CLKOUT4_CASCADE = ""FALSE"",
+\t\t     parameter integer CLKOUT4_DIVIDE = 1,
+\t\t     parameter real CLKOUT4_DUTY_CYCLE = 0.500,
+\t\t     parameter real CLKOUT4_PHASE = 0.000,
+\t\t     parameter CLKOUT4_USE_FINE_PS = ""FALSE"",
+\t\t     parameter integer CLKOUT5_DIVIDE = 1,
+\t\t     parameter real CLKOUT5_DUTY_CYCLE = 0.500,
+\t\t     parameter real CLKOUT5_PHASE = 0.000,
+\t\t     parameter CLKOUT5_USE_FINE_PS = ""FALSE"",
+\t\t     parameter integer CLKOUT6_DIVIDE = 1,
+\t\t     parameter real CLKOUT6_DUTY_CYCLE = 0.500,
+\t\t     parameter real CLKOUT6_PHASE = 0.000,
+\t\t     parameter CLKOUT6_USE_FINE_PS = ""FALSE"",
+\t\t     parameter COMPENSATION = ""ZHOLD"",
+\t\t     parameter integer DIVCLK_DIVIDE = 1,
+\t\t     parameter [0:0] IS_CLKINSEL_INVERTED = 1\'b0,
+\t\t     parameter [0:0] IS_PSEN_INVERTED = 1\'b0,
+\t\t     parameter [0:0] IS_PSINCDEC_INVERTED = 1\'b0,
+\t\t     parameter [0:0] IS_PWRDWN_INVERTED = 1\'b0,
+\t\t     parameter [0:0] IS_RST_INVERTED = 1\'b0,
+\t\t     parameter real REF_JITTER1 = 0.010,
+\t\t     parameter real REF_JITTER2 = 0.010,
+\t\t     parameter SS_EN = ""FALSE"",
+\t\t     parameter SS_MODE = ""CENTER_HIGH"",
+\t\t     parameter integer SS_MOD_PERIOD = 10000,
+\t\t     parameter STARTUP_WAIT = ""FALSE""
+\t\t     )(
+
+  output \tCLKFBOUT,     //feedback clock to connect to CLKFBIN
+  output \tCLKFBOUTB,    //inverted feedback clock output
+  output \tCLKFBSTOPPED, //indicates that FB clock as stoppped
+  output \tCLKINSTOPPED, //indicates that input clock has stopped
+  output \tCLKOUT0,      //clock output
+  output \tCLKOUT0B,     //inverted clock output
+  output \tCLKOUT1,
+  output \tCLKOUT1B,
+  output \tCLKOUT2,
+  output \tCLKOUT2B,
+  output \tCLKOUT3,
+  output \tCLKOUT3B,
+  output \tCLKOUT4,
+  output \tCLKOUT5,
+  output \tCLKOUT6,
+  output \tLOCKED,       //indicates PLL is locked
+  output \tPSDONE,       //phase shift done
+  input \tCLKFBIN,
+  input \tCLKIN1,
+  input \tCLKIN2,
+  input \tCLKINSEL,    //selects between two input clocks,1=primary
+  output \tDRDY,        //dynamic reconfig ready
+  input [6:0] \tDADDR,       //Address port for dynamic reconfig
+  input \tDCLK,        //clock port for dynamic reconfig
+  input \tDEN,         //enable for dynamic reconfig
+  input [15:0] \tDI,          //data for dynamic reconfig
+  input \tDWE,         //dynamic reconfig write enable
+  output [15:0] DO,          //readback data for dyanmic reconfig
+  input \tPSCLK,       //phase shift clock
+  input \tPSEN,        //phase shift enable
+  input \tPSINCDEC,    //phase shift decrement/increment  
+  input \tPWRDWN,      //global power down pin
+  input \tRST          //async global reset   
+);
+
+  //#LOCAL DERIVED PARAMETERS
+   localparam VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT_F;
+   localparam CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE_F * (CLKOUT0_PHASE/360);
+   localparam CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
+   localparam CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
+   localparam CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
+   localparam CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
+   localparam CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
+   localparam CLK6_DELAY = VCO_PERIOD * CLKOUT6_DIVIDE * (CLKOUT6_PHASE/360);
+
+   localparam phases = CLKFBOUT_MULT_F / DIVCLK_DIVIDE;
+   //########################################################################
+   //# CLOCK MULTIPLIER
+   //########################################################################
+
+   //   
+   integer \tj;   
+   reg [2*phases-1:0] \tdelay;
+   always @ (CLKIN1)
+     begin\t
+\tfor(j=0; j<(2*phases); j=j+1)
+\t  delay[j] <= #(CLKIN1_PERIOD*j/(2*phases)) CLKIN1;
+     end
+   
+   reg [(phases)-1:0] \tclk_comb;
+    always @ (delay)
+      begin
+\t for(j=0; j<(phases); j=j+1)
+\t   clk_comb[j] <= delay[2*j] & ~delay[2*j+1];\t 
+      end
+   
+   reg vco_clk;   
+   integer k;   
+   always @*
+     begin
+\tvco_clk = 1\'b0;
+\tfor(k=0; k<(phases); k=k+1)
+\t  vco_clk = vco_clk | clk_comb[k];
+     end
+    
+   //##############
+   //#DIVIDERS
+   //##############
+   wire [3:0] DIVCFG[6:0]; 
+   wire [6:0] CLKOUT_DIV;
+      
+   assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE_F);
+   assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
+   assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
+   assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
+   assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
+   assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
+   assign DIVCFG[6] = $clog2(CLKOUT6_DIVIDE);
+
+   //ugly POR reset
+   reg \t      POR;
+   initial
+     begin
+\tPOR=1\'b1;
+\t#1
+\tPOR=1\'b0;\t
+     end
+
+   //BUG! This only supports divide by 2,4,8, etc for now
+   //TODO: This clearly won\'t work, need general purpose clock divider
+   //divide by 2-N (3,5,6,7 and all the other ugly numbers)
+   genvar i;
+   generate for(i=0; i<7; i=i+1)
+     begin : gen_clkdiv
+\tclock_divider clkdiv (/*AUTOINST*/
+\t\t\t      // Outputs
+\t\t\t      .clkout\t\t(CLKOUT_DIV[i]),
+\t\t\t      // Inputs
+\t\t\t      .clkin\t\t(vco_clk),
+\t\t\t      .divcfg\t\t(DIVCFG[i]),
+\t\t\t      .reset\t\t(RST | POR));\t\t
+     end      
+   endgenerate
+
+   //##############
+   //#PHASE DELAY
+   //##############
+   reg CLKOUT0;
+   reg CLKOUT1;
+   reg CLKOUT2;
+   reg CLKOUT3;
+   reg CLKOUT4;
+   reg CLKOUT5;
+   reg CLKOUT6;
+   
+   always @ (CLKOUT_DIV)
+     begin\t
+\tCLKOUT0 <= #(CLK0_DELAY) CLKOUT_DIV[0];
+\tCLKOUT1 <= #(CLK1_DELAY) CLKOUT_DIV[1];
+\tCLKOUT2 <= #(CLK2_DELAY) CLKOUT_DIV[2];
+\tCLKOUT3 <= #(CLK3_DELAY) CLKOUT_DIV[3];
+\tCLKOUT4 <= #(CLK4_DELAY) CLKOUT_DIV[4];
+\tCLKOUT5 <= #(CLK5_DELAY) CLKOUT_DIV[5];
+\tCLKOUT6 <= #(CLK6_DELAY) CLKOUT_DIV[6];
+     end
+
+   //##############
+   //#DUMMY DRIVES
+   //##############
+   assign CLKFBOUT=CLKIN1;
+   
+   //###########################
+   //#SANITY CHECK LOCK COUNTER
+   //############################
+   parameter LCW=4;   
+   reg [LCW-1:0] lock_counter;
+   wire \t reset = POR | RST;   
+   
+   always @ (posedge CLKIN1 or posedge reset)
+     if(reset)
+       lock_counter[LCW-1:0]  <= {(LCW){1\'b1}};
+     else if(~LOCKED)
+       lock_counter[LCW-1:0] <= lock_counter[LCW-1:0] - 1\'b1;
+
+   assign LOCKED = ~(|lock_counter[LCW-1:0]);
+   
+endmodule // MMCME2_ADV
+// Local Variables:
+// verilog-library-directories:(""."" ""../../common/hdl"")
+// End:
+"
+"/*Differential output buffer primitive
+ *
+ * 
+ */
+
+module OBUFDS (/*AUTOARG*/
+   // Outputs
+   O, OB,
+   // Inputs
+   I
+   );
+
+    parameter CAPACITANCE = ""DONT_CARE"";
+    parameter IOSTANDARD = ""DEFAULT"";
+    parameter SLEW = ""SLOW"";
+    
+   input  I;    
+   output O, OB;
+
+
+   assign O  = I;
+   assign OB = ~I;
+
+endmodule // OBUFDS
+
+"
+"`include ""elink_regmap.v""
+module esaxi (/*autoarg*/
+   // Outputs
+   txwr_access, txwr_packet, txrd_access, txrd_packet, rxrr_wait,
+   s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
+   s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
+   s_axi_wready,
+   // Inputs
+   txwr_wait, txrd_wait, rxrr_access, rxrr_packet, s_axi_aclk,
+   s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
+   s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
+   s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
+   s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
+   s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
+   s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
+   s_axi_wstrb, s_axi_wvalid
+   );
+   
+   parameter [11:0]  ID                  = 12\'h810;
+   parameter         IDW                 = 12;
+   parameter         PW                  = 104;
+   parameter [15:0]  RETURN_ADDR         = {ID,`EGROUP_RR};
+   parameter         AW                  = 32;
+   parameter         DW                  = 32;
+   
+   /*****************************/
+   /*Write request for TX fifo  */
+   /*****************************/  
+   output \t   txwr_access;   
+   output [PW-1:0] txwr_packet;
+   input \t   txwr_wait;
+   
+   /*****************************/
+   /*Read request for TX fifo   */
+   /*****************************/  
+   output \t   txrd_access;   
+   output [PW-1:0] txrd_packet;
+   input \t   txrd_wait;
+   
+   /*****************************/
+   /*Read response from RX fifo */
+   /*****************************/  
+   input \t   rxrr_access;         
+   input [PW-1:0]  rxrr_packet;
+   output \t   rxrr_wait;
+
+   /*****************************/
+   /*AXI slave interface        */
+   /*****************************/  
+   //Clock and reset
+   input \t  s_axi_aclk;
+   input \t  s_axi_aresetn;
+   
+   //Read address channel
+   input [IDW-1:0] s_axi_arid;    //write address ID
+   input [31:0]    s_axi_araddr;
+   input [1:0] \t   s_axi_arburst;
+   input [3:0] \t   s_axi_arcache;
+   input [1:0] \t   s_axi_arlock;
+   input [7:0] \t   s_axi_arlen;
+   input [2:0] \t   s_axi_arprot;
+   input [3:0] \t   s_axi_arqos;
+   output \t   s_axi_arready;
+   input [2:0] \t   s_axi_arsize;
+   input \t   s_axi_arvalid;
+   
+   //Write address channel
+   input [IDW-1:0] s_axi_awid;    //write address ID
+   input [31:0]    s_axi_awaddr;
+   input [1:0] \t   s_axi_awburst;
+   input [3:0] \t   s_axi_awcache;
+   input [1:0] \t   s_axi_awlock;
+   input [7:0] \t   s_axi_awlen;
+   input [2:0] \t   s_axi_awprot;
+   input [3:0] \t   s_axi_awqos;   
+   input [2:0] \t   s_axi_awsize;
+   input \t   s_axi_awvalid;
+   output \t   s_axi_awready;
+   
+   //Buffered write response channel
+   output [IDW-1:0] s_axi_bid;    //write address ID
+   output [1:0]     s_axi_bresp;
+   output \t    s_axi_bvalid;
+   input \t    s_axi_bready;
+   
+   //Read channel
+   output [IDW-1:0] s_axi_rid;    //write address ID
+   output [31:0]    s_axi_rdata;
+   output \t    s_axi_rlast;   
+   output [1:0]     s_axi_rresp;
+   output \t    s_axi_rvalid;
+   input \t    s_axi_rready;
+
+   //Write channel
+   input [IDW-1:0]  s_axi_wid;    //write address ID
+   input [31:0]     s_axi_wdata;
+   input \t    s_axi_wlast;   
+   input [3:0] \t    s_axi_wstrb;
+   input \t    s_axi_wvalid;
+   output \t    s_axi_wready;
+
+   //###################################################
+   //#WIRE/REG DECLARATIONS
+   //###################################################
+
+   reg \t\t      s_axi_awready;
+   reg \t\t      s_axi_wready;
+   reg \t\t      s_axi_bvalid;
+   reg [1:0] \t      s_axi_bresp;
+   reg \t\t      s_axi_arready;
+   
+   reg [31:0] \t      axi_awaddr;  // 32b for epiphany addr
+   reg [1:0] \t      axi_awburst;
+   reg [2:0] \t      axi_awsize;
+   reg [IDW-1:0]      axi_bid;     //what to do with this?
+ 
+   reg [31:0] \t      axi_araddr;
+   reg [7:0] \t      axi_arlen;
+   reg [1:0] \t      axi_arburst;
+   reg [2:0] \t      axi_arsize;
+   
+   reg [31:0] \t      s_axi_rdata;
+   reg [1:0] \t      s_axi_rresp;
+   reg \t\t      s_axi_rlast;
+   reg \t\t      s_axi_rvalid;
+   reg [IDW-1:0]      s_axi_rid;
+   
+   reg \t\t      read_active;
+   reg [31:0] \t      read_addr;
+   reg \t\t      write_active;
+   reg \t\t      b_wait;      // waiting to issue write response (unlikely?)
+   
+   reg \t\t      txwr_access;
+   reg [1:0] \t      txwr_datamode;
+   reg [31:0] \t      txwr_dstaddr;
+   reg [31:0] \t      txwr_data;
+
+   reg [31:0] \t      txwr_data_reg;
+   reg [31:0] \t      txwr_dstaddr_reg;
+   reg [1:0] \t      txwr_datamode_reg;
+   
+   reg \t\t      txrd_access;
+   reg [1:0] \t      txrd_datamode;
+   reg [31:0] \t      txrd_dstaddr;
+   reg [31:0] \t      txrd_srcaddr;  //read reaspne address
+   
+   reg \t\t      pre_wr_en;    // delay for data alignment
+   
+   reg \t\t      ractive_reg;  // need leading edge of active for 1st req
+   reg \t\t      rnext;
+        
+   wire \t      last_wr_beat;
+   wire \t      last_rd_beat;
+  
+   wire [31:0] \t      rxrr_mux_data;
+   wire [DW-1:0]      rxrr_data;
+   
+   //###################################################
+   //#PACKET TO MESH
+   //###################################################
+
+   //TXWR
+   emesh2packet e2p_txwr (
+\t\t     // Outputs
+\t\t     .packet_out\t(txwr_packet[PW-1:0]),
+\t\t     // Inputs
+\t\t     .access_in\t\t(txwr_access),
+\t\t     .write_in\t\t(1\'b1),
+\t\t     .datamode_in\t(txwr_datamode[1:0]),
+\t\t     .ctrlmode_in\t(4\'b0),
+\t\t     .dstaddr_in\t(txwr_dstaddr[AW-1:0]),
+\t\t     .data_in\t\t(txwr_data[DW-1:0]),
+\t\t     .srcaddr_in\t(32\'b0)//only 32b slave write supported
+\t\t     );
+
+   //TXRD
+   emesh2packet e2p_txrd (
+\t\t     // Outputs
+\t\t     .packet_out\t(txrd_packet[PW-1:0]),
+\t\t     // Inputs
+\t\t     .access_in\t\t(txrd_access),
+\t\t     .write_in\t\t(txrd_write),
+\t\t     .datamode_in\t(txrd_datamode[1:0]),
+\t\t     .ctrlmode_in\t(4\'b0),
+\t\t     .dstaddr_in\t(txrd_dstaddr[AW-1:0]),
+\t\t     .data_in\t\t(32\'b0),
+\t\t     .srcaddr_in\t(txrd_srcaddr[AW-1:0])
+\t\t     );   
+   //RXRR
+   packet2emesh p2e_rxrr (
+\t\t\t  // Outputs
+\t\t\t  .access_out\t\t(),
+\t\t\t  .write_out\t\t(),
+\t\t\t  .datamode_out\t\t(),
+\t\t\t  .ctrlmode_out\t\t(),
+\t\t\t  .dstaddr_out\t\t(),
+\t\t\t  .data_out\t\t(rxrr_data[DW-1:0]),
+\t\t\t  .srcaddr_out\t\t(),
+\t\t\t  // Inputs
+\t\t\t  .packet_in\t\t(rxrr_packet[PW-1:0])
+\t\t\t  );
+
+   //###################################################
+   //#WRITE ADDRESS CHANNEL
+   //###################################################
+
+   assign  last_wr_beat = s_axi_wready & s_axi_wvalid & s_axi_wlast;
+   
+   // axi_awready is asserted when there is no write transfer in progress
+
+   always @(posedge s_axi_aclk ) 
+     begin
+      if(~s_axi_aresetn)  
+\tbegin
+           s_axi_awready <= 1\'b1; //TODO: why not set default as 1?
+           write_active  <= 1\'b0;           
+\tend 
+      else 
+\tbegin
+           // we\'re always ready for an address cycle if we\'re not doing something else
+           //  note: might make this faster by going ready on last beat instead of after,
+           //  but if we want the very best each channel should be fifo\'d.
+           if( ~s_axi_awready & ~write_active & ~b_wait )
+             s_axi_awready <= 1\'b1;
+           else if( s_axi_awvalid )
+             s_axi_awready <= 1\'b0;
+\t   
+           // the write cycle is ""active"" as soon as we capture an address, it
+           // ends on the last beat.
+           if( s_axi_awready & s_axi_awvalid )
+             write_active <= 1\'b1;
+           else if( last_wr_beat )
+             write_active <= 1\'b0;         
+\tend // else: !if(~s_axi_aresetn)
+     end // always @ (posedge s_axi_aclk )
+   
+   // capture address & other aw info, update address during cycle
+   
+   always @( posedge s_axi_aclk ) 
+     if (~s_axi_aresetn)  
+       begin
+          axi_bid[IDW-1:0]   <= \'d0;  // capture for write response
+          axi_awaddr[31:0]   <= 32\'d0;
+          axi_awsize[2:0]    <= 3\'d0;
+          axi_awburst[1:0]   <= 2\'d0;         
+       end 
+     else 
+       begin\t  
+          if( s_axi_awready & s_axi_awvalid ) 
+\t    begin\t     
+\t       axi_bid[IDW-1:0] <= s_axi_awid[IDW-1:0];
+               axi_awaddr[31:0] <= s_axi_awaddr[31:0];
+               axi_awsize[2:0]  <= s_axi_awsize[2:0];  // 0=byte, 1=16b, 2=32b
+               axi_awburst[1:0] <= s_axi_awburst[1:0]; // type, 0=fixed, 1=incr, 2=wrap
+            end 
+\t  else if( s_axi_wvalid & s_axi_wready ) 
+            if( axi_awburst == 2\'b01 ) 
+\t      begin //incremental burst
+\t\t // the write address for all the beats in the transaction are increments by the data width.
+\t\t // note: this should be based on awsize instead to support narrow bursts, i think.
+\t\t axi_awaddr[31:2] <= axi_awaddr[31:2] + 30\'d1;
+\t\t //awaddr alignedto data width
+\t\t axi_awaddr[1:0]  <= 2\'b0;   \t\t  
+\t      end  // both fixed & wrapping types are treated as fixed, no update.
+       end // else: !if(~s_axi_aresetn)
+   
+   //###################################################
+   //#WRITE RESPONSE CHANNEL
+   //###################################################
+    assign s_axi_bid = axi_bid;
+   
+   always @ (posedge s_axi_aclk)
+     if(~s_axi_aresetn) 
+       s_axi_wready <= 1\'b0;      
+     else
+       begin
+\t  if( last_wr_beat )
+\t    s_axi_wready <= 1\'b0;
+\t  else if( write_active )
+\t    s_axi_wready <= ~txwr_wait;
+       end
+   
+   always @( posedge s_axi_aclk )
+     if (~s_axi_aresetn) 
+       begin
+          s_axi_bvalid      <= 1\'b0;
+          s_axi_bresp[1:0]  <= 2\'b0;
+          b_wait            <= 1\'b0;         
+       end 
+     else 
+       begin         
+         if( last_wr_beat ) 
+\t   begin
+              s_axi_bvalid      <= 1\'b1;
+              s_axi_bresp[1:0]  <= 2\'b0;           // \'okay\' response
+              b_wait            <= ~s_axi_bready;  // note: assumes bready will not drop without valid?            
+         end 
+\t else if (s_axi_bready & s_axi_bvalid) 
+\t   begin\t    
+              s_axi_bvalid <= 1\'b0;
+              b_wait       <= 1\'b0;            
+           end
+       end // else: !if( s_axi_aresetn == 1\'b0 )
+
+   //###################################################
+   //#READ REQUEST CHANNEL
+   //###################################################  
+
+   assign  last_rd_beat = s_axi_rvalid & s_axi_rlast & s_axi_rready;
+
+   always @( posedge s_axi_aclk ) 
+     if (~s_axi_aresetn) 
+       begin\t  
+         s_axi_arready <= 1\'b0;
+         read_active   <= 1\'b0;         
+       end 
+     else 
+       begin    
+\t  //arready
+          if( ~s_axi_arready & ~read_active )
+            s_axi_arready <= 1\'b1;
+          else if( s_axi_arvalid )
+            s_axi_arready <= 1\'b0;
+
+\t  //read_active
+          if( s_axi_arready & s_axi_arvalid )
+            read_active <= 1\'b1;
+          else if( last_rd_beat )
+            read_active <= 1\'b0;         
+       end // else: !if( s_axi_aresetn == 1\'b0 )
+   
+   //Read address channel state machine
+   always @( posedge s_axi_aclk ) 
+      if (~s_axi_aresetn) 
+\tbegin
+           axi_araddr[31:0]   <= 0;
+           axi_arlen          <= 8\'d0;
+           axi_arburst        <= 2\'d0;
+           axi_arsize[2:0]    <= 3\'b0;
+           s_axi_rlast        <= 1\'b0;
+           s_axi_rid[IDW-1:0] <= \'d0;         
+\tend
+      else 
+\tbegin         
+         if( s_axi_arready & s_axi_arvalid ) 
+\t   begin\t      
+              axi_araddr[31:0]   <= s_axi_araddr[31:0]; //NOTE: upper 2 bits get chopped by Zynq
+              axi_arlen[7:0]     <= s_axi_arlen[7:0];
+              axi_arburst        <= s_axi_arburst;
+              axi_arsize         <= s_axi_arsize;
+              s_axi_rlast        <= ~(|s_axi_arlen[7:0]);
+              s_axi_rid[IDW-1:0] <= s_axi_arid[IDW-1:0];              
+         end 
+\t else if( s_axi_rvalid & s_axi_rready) 
+\t   begin\t      
+              axi_arlen[7:0] <= axi_arlen[7:0] - 1;
+              if(axi_arlen[7:0] == 8\'d1)
+\t\ts_axi_rlast <= 1\'b1;              
+              if( s_axi_arburst == 2\'b01) 
+\t\tbegin //incremental burst
+\t\t   // the read address for all the beats in the transaction are increments by awsize
+\t\t   // note: this should be based on awsize instead to support narrow bursts, i think?
+\t\t   axi_araddr[31:2] <= axi_araddr[31:2] + 1;//TODO: doesn;t seem right...
+\t\t   //araddr aligned to 4 byte boundary
+\t\t   axi_araddr[1:0]  <= 2\'b0;   
+\t\t   //for awsize = 4 bytes (010)
+\t\tend
+           end // if ( s_axi_rvalid & s_axi_rready)
+\tend // else: !if( s_axi_aresetn == 1\'b0 )
+   
+
+   //###################################################
+   //#WRITE REQUEST
+   //###################################################  
+   assign txwr_write         = 1\'b1;
+   
+   always @( posedge s_axi_aclk ) 
+     if (~s_axi_aresetn) 
+       begin
+          txwr_data_reg[31:0]     <= 32\'d0;\t  
+          txwr_dstaddr_reg[31:0]  <= 32\'d0;\t 
+          txwr_datamode_reg[1:0]  <= 2\'d0;
+          txwr_access             <= 1\'b0;
+          pre_wr_en               <= 1\'b0;
+       end 
+     else 
+       begin
+\t  pre_wr_en                 <= s_axi_wready & s_axi_wvalid;
+          txwr_access               <= pre_wr_en;
+\t  txwr_datamode_reg[1:0]    <= axi_awsize[1:0];\t
+          txwr_dstaddr_reg[31:2]    <= axi_awaddr[31:2]; //set lsbs of address based on write strobes\t 
+\t  if(s_axi_wstrb[0] | (axi_awsize[1:0]==2\'b10))
+\t    begin
+\t       txwr_data_reg[31:0]   <= s_axi_wdata[31:0];
+\t       txwr_dstaddr_reg[1:0] <= 2\'d0;
+\t    end
+\t  else if(s_axi_wstrb[1])
+\t    begin
+\t       txwr_data_reg[31:0]   <= {8\'d0, s_axi_wdata[31:8]};
+\t       txwr_dstaddr_reg[1:0] <= 2\'d1;
+\t    end
+\t  else if(s_axi_wstrb[2])
+\t    begin
+\t       txwr_data_reg[31:0]   <= {16\'d0, s_axi_wdata[31:16]};
+\t       txwr_dstaddr_reg[1:0] <= 2\'d2;
+\t    end
+\t  else
+\t    begin
+\t       txwr_data_reg[31:0]   <= {24\'d0, s_axi_wdata[31:24]};
+\t       txwr_dstaddr_reg[1:0] <= 2\'d3;
+\t    end
+       end // else: !if(~s_axi_aresetn)
+
+   //Pipeline stage!
+   always @( posedge s_axi_aclk )     
+     begin
+        txwr_data[31:0]     <= txwr_data_reg[31:0];\t  
+        txwr_dstaddr[31:0]  <= txwr_dstaddr_reg[31:0];\t  
+        txwr_datamode[1:0]  <= txwr_datamode_reg[1:0];\t  
+     end
+   
+   
+   //###################################################
+   //#READ REQUEST (DATA CHANNEL)
+   //###################################################  
+   // -- reads are performed by sending a read
+   // -- request out the tx port and waiting for
+   // -- data to come back through the rx read response port.
+   // --
+   // -- because elink reads are not generally 
+   // -- returned in order, we will only allow
+   // -- one at a time.
+
+   //TODO: Fix this nonsense, need to improve performance
+   //Allow up to N outstanding transactions, use ID to match them up
+   //Need to look at txrd_wait signal
+   assign txrd_write         = 1\'b0;
+   always @( posedge s_axi_aclk )
+     if (~s_axi_aresetn) 
+       begin
+\t  txrd_access         <= 1\'b0;      
+\t  txrd_datamode[1:0]  <= 2\'d0;
+\t  txrd_dstaddr[31:0]  <= 32\'d0;
+\t  txrd_srcaddr[31:0]  <= 32\'d0;\t 
+          ractive_reg         <= 1\'b0;
+          rnext               <= 1\'b0;          
+      end 
+     else
+       begin
+          ractive_reg         <= read_active;
+          rnext               <= s_axi_rvalid & s_axi_rready & ~s_axi_rlast;        
+          txrd_access         <= ( ~ractive_reg & read_active ) | rnext;         
+\t  txrd_datamode[1:0]  <= axi_arsize[1:0];
+\t  txrd_dstaddr[31:0]  <= axi_araddr[31:0];
+\t  txrd_srcaddr[31:0]  <= {RETURN_ADDR, 16\'d0};
+\t  //TODO: use arid+srcaddr for out of order ?
+       end
+   //###################################################
+   //#READ RESPONSE (DATA CHANNEL)
+   //###################################################  
+   //Read response AXI state machine
+   //Only one outstanding read
+
+   assign rxrr_wait = 1\'b0;
+   
+   always @( posedge s_axi_aclk ) 
+      if (~s_axi_aresetn) 
+\tbegin
+           s_axi_rvalid       <= 1\'b0;
+           s_axi_rdata[31:0]  <= 32\'d0;
+           s_axi_rresp        <= 2\'d0;\t   
+\tend 
+      else 
+\tbegin
+         if( rxrr_access ) 
+\t   begin
+              s_axi_rvalid <= 1\'b1;
+              s_axi_rresp  <= 2\'d0;
+            case( axi_arsize[1:0] )
+              2\'b00:   s_axi_rdata[31:0] <= {4{rxrr_data[7:0]}};  //8-bit
+              2\'b01:   s_axi_rdata[31:0] <= {2{rxrr_data[15:0]}}; //16-bit
+              default: s_axi_rdata[31:0] <= rxrr_data[31:0];      //32-bit
+            endcase // case ( axi_arsize[1:0] )
+           end 
+\t else if( s_axi_rready ) 
+           s_axi_rvalid <= 1\'b0;
+\tend // else: !if( s_axi_aresetn == 1\'b0 )
+
+endmodule // esaxi
+
+/*
+ Copyright (C) 2015 Adapteva, Inc.
+ 
+ Contributed by Andreas Olofsson <andreas@adapteva.com>
+ Contributed by Fred Huettig <fred@adapteva.com>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.This program is distributed in the hope 
+ that it will be useful,but WITHOUT ANY WARRANTY; without even the implied 
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details. You should have received a copy 
+ of the GNU General Public License along with this program (see the file 
+ COPYING).  If not, see <http://www.gnu.org/licenses/>.
+ */
+"
+"/*An empty IDELAYCTRL model*/
+module IDELAYCTRL (/*AUTOARG*/
+   // Outputs
+   RDY,
+   // Inputs
+   REFCLK, RST
+   );
+
+    output  RDY;    //goes high when delay has been calibrated
+    input   REFCLK; //reference clock for setting tap delay
+    input   RST;    //reset pulse for setting 
+
+endmodule // IDELAYCTRL
+
+
+   
+
+
+"
+"
+module IBUFDS (/*AUTOARG*/
+   // Outputs
+   O,
+   // Inputs
+   I, IB
+   );
+
+   parameter DIFF_TERM=0;
+   parameter IOSTANDARD=0;
+
+   input I;
+   input IB;
+   output O;
+
+   assign O = I & ~IB;
+   
+endmodule // IBUFDS
+"